diff --git a/.gitignore b/.gitignore index 235ace8..b8528e2 100644 --- a/.gitignore +++ b/.gitignore @@ -1,9 +1,45 @@ -/.vscode/ -/build/ -/Debug -/.cache/ -.clangd -compile_commands.json -STM32Make.make -/.metadata/ -openocd.cfg \ No newline at end of file +# ---> KiCad +# For PCBs designed using KiCad: https://www.kicad.org/ +# Format documentation: https://kicad.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*.kicad_sch-bak +*-backups +*.kicad_prl +*.sch-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv + +# ---> VisualStudioCode +.vscode/* +!.vscode/settings.json +!.vscode/tasks.json +!.vscode/launch.json +!.vscode/extensions.json +!.vscode/*.code-snippets + +# Local History for Visual Studio Code +.history/ + +# Built Visual Studio Code Extensions +*.vsix + diff --git a/.gitmodules b/.gitmodules index 7473532..92937ba 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,3 +1,3 @@ -[submodule "Core/Lib/can-halal"] - path = Core/Lib/can-halal +[submodule "Software/Core/Lib/can-halal"] + path = Software/Core/Lib/can-halal url = ssh://git@git.fasttube.de:313/FaSTTUBe/can-halal.git diff --git a/Core/Lib/can-halal b/Core/Lib/can-halal deleted file mode 160000 index 8cca72d..0000000 --- a/Core/Lib/can-halal +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 8cca72d90d38ff48924c6a0d0e265bf9a9644457 diff --git a/Hardware/CHANGELOG.txt b/Hardware/CHANGELOG.txt new file mode 100644 index 0000000..140734f --- /dev/null +++ b/Hardware/CHANGELOG.txt @@ -0,0 +1,149 @@ +V0.7.1 +MVBMS: +- new outline +- removed UART +- added resistance to DNP resistors for V_{ref} +- LEDs are controlled by PWM +- added PWM for inverters with PWM_INV_COOLING +- added many testpoints + +V0.7.2 +MV_Abnehmerplatine: +- new outline +- added a second GND and 3V3 pin to the connector +- made sure the pin layout of the connector is equivalent to the one on the MVBMS +- kept the 14 tmp1075 sensors +- finished the layout of the MV-Abnehmerplatine + +V0.7.3 +MV_Abnehmerplatine: +- rechecked the distance between the traces leading to the battery cells and moved them around accordingly + +MVBMS: +- moved RGB LED pins to TIM4 from TIM3 +- moved PWM_BAT_COOLING to TIM3CH3 +- moved PWM_INV_COOLING to TIM15CH1 +- moved 60V_ENABLE to TIM2CH1 +- PMEG3015EJ for the CURRENT_MEASUREMENT to prevent reverse voltage +- add an extra connector for the cooling fans that cool the ESCs/inverters +- fixed some traces and some zones + +V0.7.4 +- added more documentation + +MV_Abnehmerplatine: +- aligned the connectors to the MVBMS connector +- slight changes to the outline for the connector +- fixed some zones + +MVBMS +- new outline + +V0.8.1 +new outlines for the MVBMS and Abnehmerplatine +added more photos under documentation + + +MV_Abnehmerplatine: +- the right side of the PCB is now smaller + +MVBMS: +- added a 1MBit I2C EEPROM to save data of the battery# +- combined everything that goes to the ESC into one connector +- both battery cooling fans are now on one connector +- ESC cooling and battery cooling fans can be controlled pwm or voltage controlled +- PRECHARGE and RELAY connectors are now one connector + +- renamed PWM_BAT_COOLING to BAT_COOING_PWM +- renamed 60V_ENABLE to BAT_COOING_ENABLE +- renamed PWM_PG_Fan_1/2 to ESC1/2_PWM +- renamed PWM_INV_COOLING to ESC_COOLING_PWM +- added ESC_COOLING_ENABLE for voltage contol of the ESC cooling fans +- connected V_{ref} to GPIO 2 of the ADBMS. With this, it can be detected if the current sensor is recieving enough voltage +- layout: + - Container layout is now better, the connectors have meaningful positions + - moved all connectors to the front including the debug header + +V0.9-cable +MV_Abnehmerplatine: +- switch from pads to through holes +- extended the layout to the middle of the busbars for the through holes + +V0.9-pogo +MV_Abnehmerplatine: +- first sketch is done + +V0.9.1-pogo +- deleted V0.9-cable because the PCB for pogo could also be used with a cable +- fixed up the zones +- 2->4 layers with 2.4mm core and 0.188mm prepreg (increasing the thickness of the copper layers is taken from thickness of the core) +- created a proper symbol and footrint for the 0921-1-15-20-75-14-11-0 which is the one I have decided on + +V0.9.2 +- added dip switch for open wire detection +- added PMEG3015EJ Diodes to RELAY_ESC/BAT_SIDE to pretect against funny business + +V0.9.3 +MV_Abnehmerplatine +- new layout: recentered the temperature sensors and pogo pins. + +V0.9.4 +MVBMS: +- removed screw holes next to the MV_Abnehmerplatine connector + +V0.9.5 +PCB_review +Schematic: +-MVBMS +- Thermische Berechnung ist worst case scenario, habe da das max von alles genommen für eine Schätzung was da passieren könnte. Die Zahl ist für die PDU. +- WC kann man auf jeden Fall sparen, da werden nur Temperaturen und Spannungen geloggt. keine wichtige Daten +- 1uF auf 100nF für NRST +- für das BMS auf jeden Fall. Für LED vllt schon aber wir haben auch ganz viele bestellt. +- Die Platine sollte da eigentlich da terminieren. DNP ist falsch für alles da +- Kapatizitätberechnung ist auch alt. Bei Balancingwiderstand kann jetzt nichts machen, im Notfall mit Software was machen. +- C19 60V tag ist eher zur orientierun, ich bezweifle das wir überhaupt <100V 10n haben +- R46 sollte entweder 0 ohm oder 1M sein. DNP macht das nicht klar eigentlich +- Serienwiderstand und Pulldown an die Gates eingefügt. +-- Meine Gedanke war schon das etwas Rückwärts fließt bei D20/21. PMEG -> RB751S40T5G Schottky diode +- Strom Sensor kann falcsh gemountet werden und dann geht V_{out} in minus, hier auch schottky +- CURRENT_SENSOR_ON is V_{ref}, geplant war ein offset aber da wirds nix. man könnte es weglassen +- der Precharge Widerstand wird das auf keinem Fall überleben. Das ist nicht so durchgedacht. + +Layout: +-MVBMS: +- 3V3 jetzt auf die innere Seite. Nach kurze Überlegung macht es schon Sinn. +- Der Deckel ist viel zu tief hinten bei dem MCU, man kann keine Stecker da packen. +- RGB LED werde ich näher zum MCU bringen man herumschieben. +- Es gibt kein Grund für den L, sieht halt gut aus ig +- Der NRST Kondensator ist jetzt neben dem Quartz +- Die Traces unten werden um 1mm nach oben geschoben +- Lage wechsel wird da gemacht um zu vermeiden, dass die Frontlage zu oft zu trennen. aber jetzt könnt man das machen wenn nur 3V3 auf front und back sind +- Die Traces für Balancingwiderstand auf die Rückseite zu bringen wird jetzt sehr lang dauern. Das hätte ich jetzt ungern gemacht wenn der Unterschied nicht groß ist. +- mit dem LDO und EEPROM auf die linke Seite hat man mehr Platz auf die rechte Seite. + +-MV_Abnehmer: +- Beschriftung der Pogopins vergößert +- 2 Lagen habe ich schon hinbekommen, aber um mehr Steifigkeit zu erzielen habe ich 4 Lagen mit fetten Prepregs gemacht. +- Wir werden den PCB mit einem 3D-Teil, was den PCB runten druckt, befestigen. Schrauben sind nicht möglich. +- Die Pogopins sollen mit ~100g runter drucken, man hofft, dass das genug Kraft ist. Filtern werde ich noch in software mal angucken +- Wegen DIP switch: Johnny meinte das Regel macht das explizit, dass wir ein Sensor und ein Spannungabnehmer trennen werden können. Der DIP-Switch sollte zu diesem Zweck passen. +- DIP switch footprint habe ich in mit dem Datenblatt verglichen, das passt. ein richtiges 3D-Model sollte man noch einfügen aber das reicht für die stp export +- Abstand zwischen SDA/SCL und 60V vergrößert +- Planeabstand von Pogopins ist jetzt 1mm +- noch 3V3 vias gestreut. Die muss man aber coaten dann oder? + +V0.9.6 +MVBMS: +- removed diode from CURRENT_MEASUREMENT +- removed diodes to RELAY_ESC/BAT_SIDE +- 3V3 on Back side, all other layers are GND + +MV_Abnehmerplatine: +- Teardrops to the Pogopins +- 2 Layers instead of 4 + +V1.0.0 +MVBMS: +- final touches to the MVBMS +MV_Abnehmerplatine: +- final touches to the MV_Abnehmerplatine \ No newline at end of file diff --git a/Hardware/Documentation/Datasheets/4000er daten.pdf b/Hardware/Documentation/Datasheets/4000er daten.pdf new file mode 100644 index 0000000..8e179bd Binary files /dev/null and b/Hardware/Documentation/Datasheets/4000er daten.pdf differ diff --git a/Hardware/Documentation/Datasheets/FaSTTUBe Bond-IQ 2023-2024.pdf b/Hardware/Documentation/Datasheets/FaSTTUBe Bond-IQ 2023-2024.pdf new file mode 100644 index 0000000..6640b98 Binary files /dev/null and b/Hardware/Documentation/Datasheets/FaSTTUBe Bond-IQ 2023-2024.pdf differ diff --git a/Hardware/Documentation/Datasheets/slpa015.pdf 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nom 3.7V/16 Ohm = 231.25 mA\n max 4.2V/16 Ohm = 262.5 mA" + (exclude_from_sim no) + (at 12.954 58.039 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left bottom) + ) + (uuid "2c0cd14d-c662-4167-9039-69a7ff6ed958") + ) + (text "V_{REG} current draw: max. 30 mA | sleep: 4 μA" + (exclude_from_sim no) + (at 224.79 35.56 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left bottom) + ) + (uuid "a6ecc33b-b9ac-4d6c-94b2-8210cb2f2c9c") + ) + (text "cell depopulation S.79 of the ADBMS6803B\n" + (exclude_from_sim no) + (at 155.067 96.012 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left bottom) + ) + (uuid "f5178808-13c2-4372-a58c-7aa792a4d09e") + ) + (hierarchical_label "CURRENT_MEASUREMENT" + (shape input) + (at 266.7 104.14 0) + (fields_autoplaced yes) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "09ea0959-60f6-4ba6-9448-b7d914cc54ae") + ) + (hierarchical_label "RELAY_BAT_SIDE_VOLTAGE" + (shape input) + (at 266.7 123.19 0) + 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a/Hardware/MVBMS/FT24_MVBMS_V1/MVBMS-F_Cu.gbr b/Hardware/MVBMS/FT24_MVBMS_V1/MVBMS-F_Cu.gbr new file mode 100644 index 0000000..a413b37 --- /dev/null +++ b/Hardware/MVBMS/FT24_MVBMS_V1/MVBMS-F_Cu.gbr @@ -0,0 +1,20093 @@ +%TF.GenerationSoftware,KiCad,Pcbnew,8.0.2*% +%TF.CreationDate,2024-06-27T20:48:59+03:00*% +%TF.ProjectId,MVBMS,4d56424d-532e-46b6-9963-61645f706362,rev?*% +%TF.SameCoordinates,Original*% +%TF.FileFunction,Copper,L1,Top*% +%TF.FilePolarity,Positive*% +%FSLAX46Y46*% +G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* +G04 Created by KiCad (PCBNEW 8.0.2) date 2024-06-27 20:48:59* +%MOMM*% +%LPD*% +G01* +G04 APERTURE LIST* +G04 Aperture macros list* +%AMRoundRect* +0 Rectangle with rounded corners* +0 $1 Rounding radius* +0 $2 $3 $4 $5 $6 $7 $8 $9 X,Y pos of 4 corners* +0 Add a 4 corners polygon primitive as box body* +4,1,4,$2,$3,$4,$5,$6,$7,$8,$9,$2,$3,0* +0 Add four circle primitives for the rounded corners* +1,1,$1+$1,$2,$3* +1,1,$1+$1,$4,$5* +1,1,$1+$1,$6,$7* +1,1,$1+$1,$8,$9* +0 Add four rect primitives between the rounded corners* +20,1,$1+$1,$2,$3,$4,$5,0* +20,1,$1+$1,$4,$5,$6,$7,0* +20,1,$1+$1,$6,$7,$8,$9,0* +20,1,$1+$1,$8,$9,$2,$3,0*% +%AMFreePoly0* +4,1,19,0.550000,-0.750000,0.000000,-0.750000,0.000000,-0.744911,-0.071157,-0.744911,-0.207708,-0.704816,-0.327430,-0.627875,-0.420627,-0.520320,-0.479746,-0.390866,-0.500000,-0.250000,-0.500000,0.250000,-0.479746,0.390866,-0.420627,0.520320,-0.327430,0.627875,-0.207708,0.704816,-0.071157,0.744911,0.000000,0.744911,0.000000,0.750000,0.550000,0.750000,0.550000,-0.750000,0.550000,-0.750000, +$1*% +%AMFreePoly1* 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+X187510000Y-107700000D03* +%TD*% +M02* diff --git a/Hardware/MVBMS/FT24_MVBMS_V1/MVBMS-F_Paste.gbr b/Hardware/MVBMS/FT24_MVBMS_V1/MVBMS-F_Paste.gbr new file mode 100644 index 0000000..f39114d --- /dev/null +++ b/Hardware/MVBMS/FT24_MVBMS_V1/MVBMS-F_Paste.gbr @@ -0,0 +1,1623 @@ +%TF.GenerationSoftware,KiCad,Pcbnew,8.0.2*% +%TF.CreationDate,2024-06-27T20:48:59+03:00*% +%TF.ProjectId,MVBMS,4d56424d-532e-46b6-9963-61645f706362,rev?*% +%TF.SameCoordinates,Original*% +%TF.FileFunction,Paste,Top*% +%TF.FilePolarity,Positive*% +%FSLAX46Y46*% +G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* +G04 Created by KiCad (PCBNEW 8.0.2) date 2024-06-27 20:48:59* +%MOMM*% +%LPD*% +G01* +G04 APERTURE LIST* +G04 Aperture macros list* +%AMRoundRect* +0 Rectangle with rounded corners* +0 $1 Rounding radius* +0 $2 $3 $4 $5 $6 $7 $8 $9 X,Y pos of 4 corners* +0 Add a 4 corners polygon primitive as box body* +4,1,4,$2,$3,$4,$5,$6,$7,$8,$9,$2,$3,0* +0 Add four circle primitives for the rounded corners* +1,1,$1+$1,$2,$3* +1,1,$1+$1,$4,$5* +1,1,$1+$1,$6,$7* +1,1,$1+$1,$8,$9* +0 Add four rect primitives between the rounded corners* +20,1,$1+$1,$2,$3,$4,$5,0* +20,1,$1+$1,$4,$5,$6,$7,0* +20,1,$1+$1,$6,$7,$8,$9,0* +20,1,$1+$1,$8,$9,$2,$3,0*% +G04 Aperture macros list end* +%ADD10C,0.200000*% +%ADD11RoundRect,0.225000X0.250000X-0.225000X0.250000X0.225000X-0.250000X0.225000X-0.250000X-0.225000X0*% +%ADD12RoundRect,0.200000X0.200000X0.275000X-0.200000X0.275000X-0.200000X-0.275000X0.200000X-0.275000X0*% +%ADD13RoundRect,0.200000X-0.200000X-0.275000X0.200000X-0.275000X0.200000X0.275000X-0.200000X0.275000X0*% +%ADD14RoundRect,0.200000X-0.275000X0.200000X-0.275000X-0.200000X0.275000X-0.200000X0.275000X0.200000X0*% +%ADD15RoundRect,0.218750X0.218750X0.256250X-0.218750X0.256250X-0.218750X-0.256250X0.218750X-0.256250X0*% +%ADD16R,1.780000X2.000000*% +%ADD17RoundRect,0.225000X-0.250000X0.225000X-0.250000X-0.225000X0.250000X-0.225000X0.250000X0.225000X0*% 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(at 131.064 15.113 0) + (effects + (font + (size 1.27 1.27) + ) + ) + (uuid "d648afb6-3143-4c59-9e0f-345f1af31207") + ) + (text "V_{out} = (V_{source} * R_{2})/(R_{1} + R_{2})\nmax. 4,964 V = (54,6V × 100k)/(1M + 100k)\nmin. 3,545 V = (39V × 100k)/(1M + 100k)\n\nV_{out}*((R_{1} + R_{2})) = (V_{source} * R_{2})\nV_{source} = V_{out} * (R_{1} + R_{2}))/(R_{2})\nV_{source} = V_{out} * 11\n\n" + (exclude_from_sim no) + (at 13.589 79.121 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "d8a2ce39-78bc-4f99-b0ec-db633808f19d") + ) + (text "https://www.digikey.de/en/resources/conversion-calculators/conversion-calculator-time-constant\n54 V, 2,2 mF pro ESC, 600 ohm\nE = 6,4152 J = ((54 V)^2 * 4,4 mF)/2\nT = 2,64 s = 600 ohm * 4,4 mF \n95% of max voltage after 3*T = 7.92 s of precharge" + (exclude_from_sim no) + (at 12.7 18.542 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + (uuid "ee6261d2-6f65-45b4-8d50-ffca1621c928") + ) + (label "RELAY_ESC_SIDE" + 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(symbol + (lib_id "MVBMS:PVG612AS") + (at 149.86 109.22 0) + (mirror y) + (unit 1) + (exclude_from_sim no) + (in_bom yes) + (on_board yes) + (dnp no) + (fields_autoplaced yes) + (uuid "f87cc886-d2db-4888-ba27-27edc3cec2f0") + (property "Reference" "U5" + (at 149.86 100.965 0) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Value" "PVG612AS" + (at 149.86 103.505 0) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Footprint" "Package_DIP:SMDIP-6_W9.53mm" + (at 149.86 116.84 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Datasheet" "https://www.infineon.com/dgdl/Infineon-PVG612A-DataSheet-v01_00-EN.pdf?fileId=5546d462533600a401535683ca14293a" + (at 149.86 119.38 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Description" "" + (at 149.86 109.22 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Siklscreen" "" + (at 149.86 109.22 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Silkscreen " "" + (at 149.86 109.22 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (pin "3" + (uuid "12b0f5c0-a03b-490a-bf2c-ee5cf6b943da") + ) + (pin "6" + (uuid "8fb63dfa-8aaa-47bc-ae2a-64736e427479") + ) + (pin "5" + (uuid "781eb4a5-fa5f-41bb-af71-5136659058fe") + ) + (pin "4" + (uuid "773358f1-5b95-4dfc-be39-3b9ba37bfc77") + ) + (pin "1" + (uuid "8e9a18ad-2c9c-4718-be25-506d6a5573cd") + ) + (pin "2" + (uuid "b9c80582-a50d-4ed7-93ab-e3985bd4619e") + ) + (instances + (project "MVBMS" + (path "/7e6153c6-9bda-478e-a814-ab2130d6c479/230d2be7-f68c-4d0a-bb36-39424b7f609b" + (reference "U5") + (unit 1) + ) + ) + ) + ) + (symbol + (lib_id "Device:R") + (at 234.95 146.05 90) + (unit 1) + (exclude_from_sim no) + (in_bom yes) + (on_board yes) + (dnp no) + (fields_autoplaced yes) + (uuid "fb2e7aa9-743c-4548-b033-2213532264d7") + (property "Reference" "R81" + (at 234.95 139.7 90) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Value" "120" + (at 234.95 142.24 90) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Footprint" "Resistor_SMD:R_0603_1608Metric" + (at 234.95 147.828 90) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Datasheet" "~" + (at 234.95 146.05 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Description" "Resistor" + (at 234.95 146.05 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Siklscreen" "" + (at 234.95 146.05 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Silkscreen " "" + (at 234.95 146.05 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (pin "1" + (uuid "a822b3cd-cc4b-4e0d-8879-ddd318f47c97") + ) + (pin "2" + (uuid "bb652cf3-4c0d-4185-8be5-daae2a159343") + ) + (instances + (project "MVBMS" + (path "/7e6153c6-9bda-478e-a814-ab2130d6c479/230d2be7-f68c-4d0a-bb36-39424b7f609b" + (reference "R81") + (unit 1) + ) + ) + ) + ) + (symbol + (lib_id "MVBMS:BZX84-A3V3") + (at 76.2 63.5 90) + (mirror x) + (unit 1) + (exclude_from_sim no) + (in_bom yes) + (on_board yes) + (dnp no) + (fields_autoplaced yes) + (uuid "fb4c7d89-0165-4960-a726-b7e45a411a0e") + (property "Reference" "D12" + (at 73.66 62.2299 90) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + ) + (property "Value" "BZX84-A5V1" + (at 73.66 64.7699 90) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + ) + (property "Footprint" "Package_TO_SOT_SMD:SOT-23-3" + (at 71.12 63.5 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Datasheet" "~" + (at 76.2 63.5 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Description" "" + (at 76.2 63.5 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Siklscreen" "" + (at 76.2 63.5 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Silkscreen " "" + (at 76.2 63.5 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (pin "1" + (uuid "c2dcf6e7-b520-4da5-a812-51c3bd3e6320") + ) + (pin "3" + (uuid "29b66464-e15d-47f7-af76-1c7ddeca8a02") + ) + (instances + (project "MVBMS" + (path "/7e6153c6-9bda-478e-a814-ab2130d6c479/230d2be7-f68c-4d0a-bb36-39424b7f609b" + (reference "D12") + (unit 1) + ) + ) + ) + ) +) diff --git a/Hardware/MVBMS/MVBMS.kicad_pcb b/Hardware/MVBMS/MVBMS.kicad_pcb new file mode 100644 index 0000000..a241966 --- /dev/null +++ b/Hardware/MVBMS/MVBMS.kicad_pcb @@ -0,0 +1,82584 @@ +(kicad_pcb + (version 20240108) + (generator "pcbnew") + (generator_version "8.0") + (general + (thickness 1.6) + (legacy_teardrops no) + ) + (paper "A3") + (layers + (0 "F.Cu" signal) + (1 "In1.Cu" signal) + (2 "In2.Cu" signal) + (31 "B.Cu" signal) + (32 "B.Adhes" user "B.Adhesive") + (33 "F.Adhes" user "F.Adhesive") + (34 "B.Paste" user) + (35 "F.Paste" user) + (36 "B.SilkS" user "B.Silkscreen") + (37 "F.SilkS" user "F.Silkscreen") + (38 "B.Mask" user) + (39 "F.Mask" user) + (40 "Dwgs.User" user "User.Drawings") + (41 "Cmts.User" user "User.Comments") + (42 "Eco1.User" user "User.Eco1") + (43 "Eco2.User" user "User.Eco2") + (44 "Edge.Cuts" user) + (45 "Margin" user) + (46 "B.CrtYd" user "B.Courtyard") + (47 "F.CrtYd" user "F.Courtyard") + (48 "B.Fab" user) + (49 "F.Fab" user) + (50 "User.1" user) + (51 "User.2" user) + (52 "User.3" user) + (53 "User.4" user) + (54 "User.5" user) + (55 "User.6" user) + (56 "User.7" user) + (57 "User.8" user) + (58 "User.9" user) + ) + (setup + (stackup + (layer "F.SilkS" + (type "Top Silk Screen") + ) + (layer "F.Paste" + (type "Top Solder Paste") + ) + (layer "F.Mask" + (type "Top Solder Mask") + (thickness 0.01) + ) + (layer "F.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "dielectric 1" + (type "prepreg") + (thickness 0.1) + (material "FR4") + (epsilon_r 4.5) + (loss_tangent 0.02) + ) + (layer "In1.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "dielectric 2" + (type "core") + (thickness 1.24) + (material "FR4") + (epsilon_r 4.5) + (loss_tangent 0.02) + ) + (layer "In2.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "dielectric 3" + (type "prepreg") + (thickness 0.1) + (material "FR4") + (epsilon_r 4.5) + (loss_tangent 0.02) + ) + (layer "B.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "B.Mask" + (type "Bottom Solder Mask") + (thickness 0.01) + ) + (layer "B.Paste" + (type "Bottom Solder Paste") + ) + (layer "B.SilkS" + (type "Bottom Silk Screen") + ) + (copper_finish "None") + (dielectric_constraints no) + ) + (pad_to_mask_clearance 0) + (allow_soldermask_bridges_in_footprints no) + (pcbplotparams + (layerselection 0x00010fc_ffffffff) + (plot_on_all_layers_selection 0x0000000_00000000) + (disableapertmacros no) + (usegerberextensions no) + (usegerberattributes yes) + (usegerberadvancedattributes yes) + (creategerberjobfile no) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) + (svgprecision 4) + (plotframeref no) + (viasonmask no) + (mode 1) + (useauxorigin yes) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (pdf_front_fp_property_popups yes) + (pdf_back_fp_property_popups yes) + (dxfpolygonmode yes) + (dxfimperialunits yes) + (dxfusepcbnewfont yes) + (psnegative no) + (psa4output no) + (plotreference yes) + (plotvalue no) + (plotfptext yes) + (plotinvisibletext no) + (sketchpadsonfab no) + (subtractmaskfromsilk yes) + (outputformat 1) + (mirror no) + (drillshape 0) + (scaleselection 1) + (outputdirectory "./FT24_MVBMS_V1") + ) + ) + (net 0 "") + (net 1 "GND") + (net 2 "/Microcontroller/XTAL_2") + (net 3 "+3V3") + (net 4 "/CAN_Transciever/V_{ref}") + (net 5 "/CAN_Transciever/CAN_HIGH") + (net 6 "/CAN_Transciever/CAN_LOW") + (net 7 "+12V") + (net 8 "/Microcontroller/XTAL_1") + (net 9 "/CAN_Transciever/CAN_TX") + (net 10 "/CAN_Transciever/CAN_RX") + (net 11 "/Microcontroller/Status_LED_R") + (net 12 "/Microcontroller/Status_LED_G") + (net 13 "/Microcontroller/Status_LED_B") + (net 14 "Net-(D19-A)") + (net 15 "/Input_Output/RELAY_DRAIN") + (net 16 "/Battery_Management_System_Right/TMP_SCL") + (net 17 "/Battery_Management_System_Right/TMP_SDA") + (net 18 "/Battery_Management_System_Right/MISO") + (net 19 "/Battery_Management_System_Right/SCK(IPA)") + (net 20 "/Battery_Management_System_Right/MOSI") + (net 21 "/Microcontroller/NRST") + (net 22 "/Microcontroller/TRACESWO") + (net 23 "/Microcontroller/SWDIO") + (net 24 "/Microcontroller/SWCLK") + (net 25 "/Battery_Management_System_Right/Filter_Balancing_Block_0/C(n)_in") + (net 26 "/Input_Output/RELAY_ENABLE") + (net 27 "/Input_Output/PRECHARGE_ENABLE") + (net 28 "/Battery_Management_System_Right/Filter_Balancing_Block_0/C(n+1)") + (net 29 "/Battery_Management_System_Right/Filter_Balancing_Block_0/C(n+1:n)") + (net 30 "/Battery_Management_System_Right/Filter_Balancing_Block_0/S(n+1)P") + (net 31 "/Battery_Management_System_Right/Filter_Balancing_Block_0/C(n+1:n)_in") + (net 32 "/Battery_Management_System_Right/Filter_Balancing_Block_0/C(n)") + (net 33 "/Battery_Management_System_Right/Filter_Balancing_Block_0/S(n)P") + (net 34 "/Battery_Management_System_Right/Filter_Balancing_Block_1/C(n+1:n)") + (net 35 "/Battery_Management_System_Right/Filter_Balancing_Block_1/C(n+1)") + (net 36 "/Battery_Management_System_Right/Filter_Balancing_Block_1/C(n+1:n)_in") + (net 37 "/Battery_Management_System_Right/Filter_Balancing_Block_1/S(n+1)P") + (net 38 "/Battery_Management_System_Right/Filter_Balancing_Block_1/C(n)") + (net 39 "/Battery_Management_System_Right/Filter_Balancing_Block_1/S(n)P") + (net 40 "/Battery_Management_System_Right/Filter_Balancing_Block_0/C(n+1)_in") + (net 41 "/Battery_Management_System_Right/Filter_Balancing_Block_2/C(n+1)") + (net 42 "/Battery_Management_System_Right/Filter_Balancing_Block_2/C(n+1:n)") + (net 43 "/Battery_Management_System_Right/Filter_Balancing_Block_2/C(n+1:n)_in") + (net 44 "/Battery_Management_System_Right/Filter_Balancing_Block_2/S(n+1)P") + (net 45 "/Battery_Management_System_Right/Filter_Balancing_Block_2/C(n)") + (net 46 "/Battery_Management_System_Right/Filter_Balancing_Block_2/S(n)P") + (net 47 "/Battery_Management_System_Right/Filter_Balancing_Block_1/C(n+1)_in") + (net 48 "/Battery_Management_System_Right/Filter_Balancing_Block_3/C(n+1:n)") + (net 49 "/Battery_Management_System_Right/Filter_Balancing_Block_3/C(n+1)") + (net 50 "/Battery_Management_System_Right/Filter_Balancing_Block_3/C(n+1:n)_in") + (net 51 "/Battery_Management_System_Right/Filter_Balancing_Block_3/S(n+1)P") + (net 52 "/Battery_Management_System_Right/Filter_Balancing_Block_3/C(n)") + (net 53 "/Battery_Management_System_Right/Filter_Balancing_Block_3/S(n)P") + (net 54 "/Battery_Management_System_Right/Filter_Balancing_Block_2/C(n+1)_in") + (net 55 "/Battery_Management_System_Right/Filter_Balancing_Block_4/C(n+1)") + (net 56 "/Battery_Management_System_Right/Filter_Balancing_Block_4/C(n+1:n)") + (net 57 "/Battery_Management_System_Right/Filter_Balancing_Block_4/C(n+1:n)_in") + (net 58 "/Battery_Management_System_Right/Filter_Balancing_Block_4/S(n+1)P") + (net 59 "/Battery_Management_System_Right/Filter_Balancing_Block_4/C(n)") + (net 60 "/Battery_Management_System_Right/Filter_Balancing_Block_4/S(n)P") + (net 61 "/Battery_Management_System_Right/Filter_Balancing_Block_3/C(n+1)_in") + (net 62 "/Battery_Management_System_Right/Filter_Balancing_Block_5/C(n+1)") + (net 63 "/Battery_Management_System_Right/Filter_Balancing_Block_5/C(n+1:n)") + (net 64 "/Battery_Management_System_Right/Filter_Balancing_Block_5/S(n+1)P") + (net 65 "/Battery_Management_System_Right/Filter_Balancing_Block_5/C(n+1:n)_in") + (net 66 "/Battery_Management_System_Right/Filter_Balancing_Block_5/C(n)") + (net 67 "/Battery_Management_System_Right/Filter_Balancing_Block_5/S(n)P") + (net 68 "/Battery_Management_System_Right/Filter_Balancing_Block_4/C(n+1)_in") + (net 69 "/Battery_Management_System_Right/Filter_Balancing_Block_5/C(n+1)_in") + (net 70 "/Input_Output/~{BAT_COOLING_PWM}") + (net 71 "/Battery_Management_System_Right/~{CS}") + (net 72 "+5V") + (net 73 "Net-(D1-K)") + (net 74 "Net-(J1-Pin_20)") + (net 75 "Net-(U3-S13P)") + (net 76 "Net-(Q0-C)") + (net 77 "Net-(U3-VREF2)") + (net 78 "Net-(U3-DRIVE)") + (net 79 "Net-(U3-VREG)") + (net 80 "Net-(U3-VREF1)") + (net 81 "Net-(D0-GK)") + (net 82 "Net-(D0-RK)") + (net 83 "Net-(D0-BK)") + (net 84 "Net-(D4-A)") + (net 85 "Net-(D1-A)") + (net 86 "Net-(D7-A)") + (net 87 "Net-(D3-A)") + (net 88 "Net-(D6-A)") + (net 89 "Net-(D11-K)") + (net 90 "Net-(JP0-C)") + (net 91 "Net-(Q0-B)") + (net 92 "/Input_Output/RELAY_BAT_SIDE") + (net 93 "Net-(Q1-D)") + (net 94 "/Microcontroller/EEPROM_SCL") + (net 95 "Net-(U0-BOOT0)") + (net 96 "Net-(U2-Rs)") + (net 97 "Net-(U3-C14:13)") + (net 98 "Net-(U3-C13)") + (net 99 "Net-(U3-V+)") + (net 100 "Net-(U3-C15)") + (net 101 "Net-(U3-C14)") + (net 102 "unconnected-(U5-Pad3)") + (net 103 "Net-(U3-IMB)") + (net 104 "Net-(D10-K)") + (net 105 "Net-(U3-IPB)") + (net 106 "unconnected-(U0-PC15-Pad4)") + (net 107 "Net-(D14-A)") + (net 108 "/Input_Output/BAT_COOLING_ENABLE") + (net 109 "/Battery_Management_System_Right/CURRENT_MEASUREMENT") + (net 110 "/Input_Output/RELAY_ESC_SIDE") + (net 111 "/Microcontroller/EEPROM_~{WC}") + (net 112 "/Battery_Management_System_Right/RELAY_ESC_SIDE_VOLTAGE") + (net 113 "unconnected-(U0-PB2-Pad20)") + (net 114 "unconnected-(U0-PC14-Pad3)") + (net 115 "/Input_Output/BAT_COOLING_PWM") + (net 116 "unconnected-(U0-PC13-Pad2)") + (net 117 "/Microcontroller/EEPROM_SDA") + (net 118 "unconnected-(U0-PB12-Pad25)") + (net 119 "unconnected-(U0-PA3-Pad13)") + (net 120 "/Input_Output/INV_PWR") + (net 121 "/Battery_Management_System_Right/RELAY_BAT_SIDE_VOLTAGE") + (net 122 "unconnected-(U3-GPIO5-Pad76)") + (net 123 "/Input_Output/BAT_PWR") + (net 124 "unconnected-(U3-GPIO6-Pad75)") + (net 125 "unconnected-(U3-NC-Pad66)") + (net 126 "unconnected-(U3-GPIO9-Pad72)") + (net 127 "unconnected-(U3-GPIO8-Pad73)") + (net 128 "unconnected-(U3-GPIO7-Pad74)") + (net 129 "unconnected-(U3-GPIO10-Pad71)") + (net 130 "unconnected-(U4-Pad3)") + (net 131 "unconnected-(U0-PA2-Pad12)") + (net 132 "/Input_Output/ESC_COOLING_PWM") + (net 133 "unconnected-(U0-PB13-Pad26)") + (net 134 "unconnected-(U6-Pad3)") + (net 135 "Net-(C1-Pad2)") + (net 136 "Net-(D8-K)") + (net 137 "Net-(D16-A)") + (net 138 "Net-(D17-A)") + (net 139 "Net-(D18-A)") + (net 140 "unconnected-(IC0-NC_2-Pad2)") + (net 141 "unconnected-(IC0-NC_3-Pad3)") + (net 142 "unconnected-(IC0-NC_1-Pad1)") + (net 143 "Net-(Q2-G)") + (net 144 "Net-(Q2-D)") + (net 145 "Net-(Q3-G)") + (net 146 "Net-(Q4-D)") + (net 147 "Net-(Q5-S)") + (net 148 "Net-(R28-Pad1)") + (net 149 "Net-(R30-Pad2)") + (net 150 "Net-(R40-Pad2)") + (net 151 "Net-(R44-Pad2)") + (net 152 "/Input_Output/ESC_COOLING_ENABLE") + (net 153 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+ (size 0.25 1.5) + (layers "F.Cu" "F.Paste" "F.Mask") + (net 61 "/Battery_Management_System_Right/Filter_Balancing_Block_3/C(n+1)_in") + (pinfunction "S9N") + (pintype "input") + (thermal_bridge_angle 45) + (uuid "70d8f557-8e3f-4f80-ab41-44c8772757ea") + ) + (pad "28" smd oval + (at -1.25 6.6875 180) + (size 0.25 1.5) + (layers "F.Cu" "F.Paste" "F.Mask") + (net 60 "/Battery_Management_System_Right/Filter_Balancing_Block_4/S(n)P") + (pinfunction "S9P") + (pintype "input") + (thermal_bridge_angle 45) + (uuid "37a4237b-9f03-422a-88e7-0671e7a98418") + ) + (pad "29" smd oval + (at -0.75 6.6875 180) + (size 0.25 1.5) + (layers "F.Cu" "F.Paste" "F.Mask") + (net 59 "/Battery_Management_System_Right/Filter_Balancing_Block_4/C(n)") + (pinfunction "C9") + (pintype "input") + (thermal_bridge_angle 45) + (uuid "9caafaf6-aaf9-4c02-9bc4-4816856a0dd7") + ) + (pad "30" smd oval + (at -0.25 6.6875 180) + (size 0.25 1.5) + (layers "F.Cu" "F.Paste" "F.Mask") + (net 49 "/Battery_Management_System_Right/Filter_Balancing_Block_3/C(n+1)") + (pinfunction "C8") + (pintype "input") + (thermal_bridge_angle 45) + (uuid "3d69f6f8-19c7-4751-95bc-2df135bc3cae") + ) + (pad "31" smd oval + (at 0.25 6.6875 180) + (size 0.25 1.5) + (layers "F.Cu" "F.Paste" "F.Mask") + (net 50 "/Battery_Management_System_Right/Filter_Balancing_Block_3/C(n+1:n)_in") + (pinfunction "S8N") + (pintype "input") + (thermal_bridge_angle 45) + (uuid "2c362e5e-3046-4a63-85b2-5c3d81b56a51") + ) + (pad "32" smd oval + (at 0.75 6.6875 180) + (size 0.25 1.5) + (layers "F.Cu" "F.Paste" "F.Mask") + (net 51 "/Battery_Management_System_Right/Filter_Balancing_Block_3/S(n+1)P") + (pinfunction "S8P") + (pintype "input") + (thermal_bridge_angle 45) + (uuid "262c7c8e-cab6-4d6a-8f75-9e9f56b26bcc") + ) + (pad "33" smd oval + (at 1.25 6.6875 180) + (size 0.25 1.5) + (layers "F.Cu" "F.Paste" "F.Mask") + (net 48 "/Battery_Management_System_Right/Filter_Balancing_Block_3/C(n+1:n)") + (pinfunction "C8:7") + (pintype "input") + (thermal_bridge_angle 45) + (uuid "ebe5a25a-3b43-439f-bcf1-2237d3a78acd") + ) + (pad "34" smd oval + (at 1.75 6.6875 180) + (size 0.25 1.5) + (layers "F.Cu" "F.Paste" "F.Mask") + (net 54 "/Battery_Management_System_Right/Filter_Balancing_Block_2/C(n+1)_in") + (pinfunction "S7N") + (pintype "input") + (thermal_bridge_angle 45) + (uuid "db29c50b-5738-4e5d-a0ba-9d41a47b9227") + ) + (pad "35" smd oval + (at 2.25 6.6875 180) + (size 0.25 1.5) + (layers "F.Cu" "F.Paste" "F.Mask") + (net 53 "/Battery_Management_System_Right/Filter_Balancing_Block_3/S(n)P") + (pinfunction "S7P") + (pintype "input") + (thermal_bridge_angle 45) + (uuid "3ce30b5e-9f31-47c7-9e12-ae56b36d0109") + ) + (pad "36" smd oval + (at 2.75 6.6875 180) + (size 0.25 1.5) + (layers "F.Cu" "F.Paste" "F.Mask") + (net 52 "/Battery_Management_System_Right/Filter_Balancing_Block_3/C(n)") + (pinfunction "C7") + (pintype "input") + (thermal_bridge_angle 45) + (uuid "30a0200b-efb9-4d62-a9f3-1e3d7b7f1a06") + ) + (pad "37" smd oval + (at 3.25 6.6875 180) + (size 0.25 1.5) + (layers "F.Cu" "F.Paste" "F.Mask") + (net 41 "/Battery_Management_System_Right/Filter_Balancing_Block_2/C(n+1)") + (pinfunction "C6") + (pintype "input") + (thermal_bridge_angle 45) + (uuid "2ba8fab8-49e3-44dc-a60e-80214776ed61") + ) + (pad "38" smd oval + (at 3.75 6.6875 180) + (size 0.25 1.5) + (layers "F.Cu" "F.Paste" "F.Mask") + (net 43 "/Battery_Management_System_Right/Filter_Balancing_Block_2/C(n+1:n)_in") + (pinfunction "S6N") + (pintype "input") + (thermal_bridge_angle 45) + (uuid "358a4c1e-ece5-4fb3-aedf-07b16652f6f7") + ) + (pad "39" smd oval + (at 4.25 6.6875 180) + (size 0.25 1.5) + (layers "F.Cu" "F.Paste" "F.Mask") + (net 44 "/Battery_Management_System_Right/Filter_Balancing_Block_2/S(n+1)P") + (pinfunction "S6P") + (pintype "input") + (thermal_bridge_angle 45) + (uuid "0168574a-58a2-4e20-97ec-a25bc39d9368") + ) + (pad "40" smd oval + (at 4.75 6.6875 180) + (size 0.25 1.5) + (layers "F.Cu" "F.Paste" "F.Mask") + (net 42 "/Battery_Management_System_Right/Filter_Balancing_Block_2/C(n+1:n)") + (pinfunction "C6:5") + (pintype "input") + (thermal_bridge_angle 45) + (uuid "e9852cea-1dce-4cf5-bf6a-611f460d09b0") + ) + (pad "41" smd oval + (at 6.6875 4.75 270) + (size 0.25 1.5) + (layers "F.Cu" "F.Paste" "F.Mask") + (net 47 "/Battery_Management_System_Right/Filter_Balancing_Block_1/C(n+1)_in") + (pinfunction "S5N") + (pintype "input") + (thermal_bridge_angle 45) + (uuid "830e54c0-ac85-4652-80b8-7183e69aff28") + ) + (pad "42" smd oval + (at 6.6875 4.25 270) + (size 0.25 1.5) + (layers "F.Cu" "F.Paste" "F.Mask") + (net 46 "/Battery_Management_System_Right/Filter_Balancing_Block_2/S(n)P") + (pinfunction "S5P") + (pintype "input") + (thermal_bridge_angle 45) + (uuid "0520e854-b47f-4124-9e1c-1cd37b7476d6") + ) + (pad "43" smd oval + (at 6.6875 3.75 270) + (size 0.25 1.5) + (layers "F.Cu" "F.Paste" "F.Mask") + (net 45 "/Battery_Management_System_Right/Filter_Balancing_Block_2/C(n)") + (pinfunction "C5") + (pintype "input") + (thermal_bridge_angle 45) + (uuid "08f2f3ea-18b6-488c-9023-6264057398b4") + ) + (pad "44" smd oval + (at 6.6875 3.25 270) + (size 0.25 1.5) + (layers "F.Cu" "F.Paste" "F.Mask") + (net 35 "/Battery_Management_System_Right/Filter_Balancing_Block_1/C(n+1)") + (pinfunction "C4") + (pintype "input") + (thermal_bridge_angle 45) + (uuid "90c69b4e-8a7c-42b3-83d2-d9731d5c9044") + ) + (pad "45" smd oval + (at 6.6875 2.75 270) + (size 0.25 1.5) + (layers "F.Cu" "F.Paste" "F.Mask") + (net 36 "/Battery_Management_System_Right/Filter_Balancing_Block_1/C(n+1:n)_in") + (pinfunction "S4N") + (pintype "input") + (thermal_bridge_angle 45) + (uuid "262a5dcd-1884-4b00-9126-99daef0cb889") + ) + (pad "46" smd oval + (at 6.6875 2.25 270) + (size 0.25 1.5) + (layers "F.Cu" "F.Paste" "F.Mask") + (net 37 "/Battery_Management_System_Right/Filter_Balancing_Block_1/S(n+1)P") + (pinfunction "S4P") + (pintype "input") + (thermal_bridge_angle 45) + (uuid "5757a571-c963-446a-bb09-3192dcfa427d") + ) + (pad "47" smd oval + (at 6.6875 1.75 270) + (size 0.25 1.5) + (layers "F.Cu" "F.Paste" "F.Mask") + (net 34 "/Battery_Management_System_Right/Filter_Balancing_Block_1/C(n+1:n)") + (pinfunction "C4:3") + (pintype "input") + (thermal_bridge_angle 45) + (uuid "7470ff4a-21ac-432a-bf92-a23e967e5226") + ) + (pad "48" smd oval + (at 6.6875 1.25 270) + (size 0.25 1.5) + (layers "F.Cu" "F.Paste" "F.Mask") + (net 40 "/Battery_Management_System_Right/Filter_Balancing_Block_0/C(n+1)_in") + (pinfunction "S3N") + (pintype "input") + (thermal_bridge_angle 45) + (uuid "835b71d7-e39c-4c82-8865-3978893b8fdc") + ) + (pad "49" smd oval + (at 6.6875 0.75 270) + (size 0.25 1.5) + (layers "F.Cu" "F.Paste" "F.Mask") + (net 39 "/Battery_Management_System_Right/Filter_Balancing_Block_1/S(n)P") + (pinfunction "S3P") + (pintype "input") + (thermal_bridge_angle 45) + (uuid "9c137e4d-da98-481b-828b-ff857fd27a1c") + ) + (pad "50" smd oval + (at 6.6875 0.25 270) + (size 0.25 1.5) + (layers "F.Cu" "F.Paste" "F.Mask") + (net 38 "/Battery_Management_System_Right/Filter_Balancing_Block_1/C(n)") + (pinfunction "C3") + (pintype "input") + (thermal_bridge_angle 45) + (uuid "f4995ac8-9624-41f6-af14-452dd044a9c8") + ) + (pad "51" smd oval + (at 6.6875 -0.25 270) + (size 0.25 1.5) + (layers "F.Cu" "F.Paste" "F.Mask") + (net 28 "/Battery_Management_System_Right/Filter_Balancing_Block_0/C(n+1)") + (pinfunction "C2") + (pintype "input") + (thermal_bridge_angle 45) + (uuid "1c767faa-3662-4526-9015-d1f31a94eb90") + ) + (pad "52" smd oval + (at 6.6875 -0.75 270) + (size 0.25 1.5) + (layers "F.Cu" "F.Paste" "F.Mask") + (net 31 "/Battery_Management_System_Right/Filter_Balancing_Block_0/C(n+1:n)_in") + (pinfunction "S2N") + (pintype "input") + (thermal_bridge_angle 45) + (uuid "eeef3013-fe70-4a79-a9ed-7f13c0f78597") + ) + (pad "53" smd oval + (at 6.6875 -1.25 270) + (size 0.25 1.5) + (layers "F.Cu" "F.Paste" "F.Mask") + (net 30 "/Battery_Management_System_Right/Filter_Balancing_Block_0/S(n+1)P") + (pinfunction "S2P") + (pintype "input") + (thermal_bridge_angle 45) + (uuid "247c9d9e-922c-49dc-900e-1d71d4b166b7") + ) + (pad "54" smd oval + (at 6.6875 -1.75 270) + (size 0.25 1.5) + (layers "F.Cu" "F.Paste" "F.Mask") + (net 29 "/Battery_Management_System_Right/Filter_Balancing_Block_0/C(n+1:n)") + (pinfunction "C2:1") + (pintype "input") + (thermal_bridge_angle 45) + (uuid "bc8b9ad9-760b-4811-9ef7-606cde7fee1b") + ) + (pad "55" smd oval + (at 6.6875 -2.25 270) + (size 0.25 1.5) + (layers "F.Cu" "F.Paste" "F.Mask") + (net 25 "/Battery_Management_System_Right/Filter_Balancing_Block_0/C(n)_in") + (pinfunction "S1N") + (pintype "input") + (thermal_bridge_angle 45) + (uuid "30c67254-879f-439b-83f3-e95b8fa03111") + ) + (pad "56" smd oval + (at 6.6875 -2.75 270) + (size 0.25 1.5) + (layers "F.Cu" "F.Paste" "F.Mask") + (net 33 "/Battery_Management_System_Right/Filter_Balancing_Block_0/S(n)P") + (pinfunction "S1P") + (pintype "input") + (thermal_bridge_angle 45) + (uuid "f28025a4-3489-4f85-aa44-5aa3c10551f1") + ) + (pad "57" smd oval + (at 6.6875 -3.25 270) + (size 0.25 1.5) + (layers "F.Cu" "F.Paste" "F.Mask") + (net 32 "/Battery_Management_System_Right/Filter_Balancing_Block_0/C(n)") + (pinfunction "C1") + (pintype "input") + (thermal_bridge_angle 45) + (uuid "b3d4c35b-3f7d-4566-9528-97ceeb953fcf") + ) + (pad "58" smd oval + (at 6.6875 -3.75 270) + (size 0.25 1.5) + (layers "F.Cu" "F.Paste" "F.Mask") + (net 71 "/Battery_Management_System_Right/~{CS}") + (pinfunction "CSB(IMA)") + (pintype "bidirectional") + (thermal_bridge_angle 45) + (uuid "3f0cb7be-eb9f-410b-806d-64b1fdb0fc0c") + ) + (pad "59" smd oval + (at 6.6875 -4.25 270) + (size 0.25 1.5) + (layers "F.Cu" "F.Paste" "F.Mask") + (net 19 "/Battery_Management_System_Right/SCK(IPA)") + (pinfunction "SCK(IPA)") + (pintype "bidirectional") + (thermal_bridge_angle 45) + (uuid "067ad982-2932-4b60-93d2-c5448c099262") + ) + (pad "60" smd oval + (at 6.6875 -4.75 270) + (size 0.25 1.5) + (layers "F.Cu" "F.Paste" "F.Mask") + (net 1 "GND") + (pinfunction "ISOMD") + (pintype "bidirectional") + (thermal_bridge_angle 45) + (uuid "898a4540-2714-4d7b-8187-aba476fb507d") + ) + (pad "61" smd oval + (at 4.75 -6.6875 180) + (size 0.25 1.5) + (layers "F.Cu" "F.Paste" "F.Mask") + (net 20 "/Battery_Management_System_Right/MOSI") + (pinfunction "SDI") + (pintype "bidirectional") + (thermal_bridge_angle 45) + (uuid "5da75f50-2e13-44bd-8ce5-bf933289b157") + ) + (pad "62" smd oval + (at 4.25 -6.6875 180) + (size 0.25 1.5) + (layers "F.Cu" "F.Paste" "F.Mask") + (net 103 "Net-(U3-IMB)") + (pinfunction "IMB") + (pintype "bidirectional") + (thermal_bridge_angle 45) + (uuid "591cb55c-e70c-42c1-81e3-289a0d5192aa") + ) + (pad "63" smd oval + (at 3.75 -6.6875 180) + (size 0.25 1.5) + (layers "F.Cu" "F.Paste" "F.Mask") + (net 105 "Net-(U3-IPB)") + (pinfunction "IPB") + (pintype "bidirectional") + (thermal_bridge_angle 45) + (uuid "38b93f92-a836-433c-af19-f4a73707d092") + ) + (pad "64" smd oval + (at 3.25 -6.6875 180) + (size 0.25 1.5) + (layers "F.Cu" "F.Paste" "F.Mask") + (net 18 "/Battery_Management_System_Right/MISO") + (pinfunction "SDO") + (pintype "bidirectional") + (thermal_bridge_angle 45) + (uuid "64ef508c-55ab-4235-9d70-8427b93e8738") + ) + (pad "65" smd oval + (at 2.75 -6.6875 180) + (size 0.25 1.5) + (layers "F.Cu" "F.Paste" "F.Mask") + (net 78 "Net-(U3-DRIVE)") + (pinfunction "DRIVE") + (pintype "bidirectional") + (thermal_bridge_angle 45) + (uuid "81ff1103-a225-49bf-9911-8d3298c05d8b") + ) + (pad "66" smd oval + (at 2.25 -6.6875 180) + (size 0.25 1.5) + (layers "F.Cu" "F.Paste" "F.Mask") + (net 125 "unconnected-(U3-NC-Pad66)") + (pinfunction "NC") + (pintype "no_connect") + (thermal_bridge_angle 45) + (uuid "1bba27e2-fc0c-407f-a75f-2905a27fca3d") + ) + (pad "67" thru_hole circle + (at -2.4 -2.4 180) + (size 0.8 0.8) + (drill 0.4) + (layers "*.Cu" "F.Mask") + (remove_unused_layers no) + (net 1 "GND") + (pinfunction "V-") + (pintype "power_in") + (uuid "635af167-7bf7-405f-9c90-2697504f9ab8") + ) + (pad "67" thru_hole circle + (at -2.4 -1.2 180) + (size 0.8 0.8) + (drill 0.4) + (layers "*.Cu" "F.Mask") + (remove_unused_layers no) + (net 1 "GND") + (pinfunction "V-") + (pintype "power_in") + (uuid "b065ade6-1e86-470a-82ec-c7cfb78b3d78") + ) + (pad "67" thru_hole circle + (at -2.4 0 180) + (size 0.8 0.8) + (drill 0.4) + (layers "*.Cu" "F.Mask") + (remove_unused_layers no) + (net 1 "GND") + (pinfunction "V-") + (pintype "power_in") + (uuid "f192a07e-533b-4096-a15a-37e1b1f3591b") + ) + (pad "67" thru_hole circle + (at -2.4 1.2 180) + (size 0.8 0.8) + (drill 0.4) + (layers "*.Cu" "F.Mask") + (remove_unused_layers no) + (net 1 "GND") + (pinfunction "V-") + (pintype "power_in") + (uuid "457942fb-f9f9-4eac-8e36-6d77c8c87a27") + ) + (pad "67" thru_hole circle + (at -2.4 2.4 180) + (size 0.8 0.8) + (drill 0.4) + (layers "*.Cu" "F.Mask") + (remove_unused_layers no) + (net 1 "GND") + (pinfunction "V-") + (pintype "power_in") + (uuid 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"https://electronics.stackexchange.com/questions/17891/stray-capacitance-for-crystals") + ) + (uuid "5fa4bb21-cbcf-4037-9235-6e818ecee0d6") + ) + (text "max. 160mA" + (exclude_from_sim no) + (at 154.432 44.704 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left bottom) + ) + (uuid "86c54088-c3bc-4783-8ddb-348cfdf5b937") + ) + (text "Crystal: WE 830030819\n\nFrom crystal datasheet:\nC_{L} = 18pF\n\nFrom AN2867:\nC_{L} = C_{L1} * C_{L2} / (C_{L1} + C_{L2}) + C_{S}\n\nWith C_{L1} = C_{L2} and C_{S} = 5pF (see link below),\nwe get C_{L1} = C_{L2} = 26pF." + (exclude_from_sim no) + (at 15.24 193.04 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left bottom) + ) + (uuid "91513385-184c-4c67-aca6-059d9d68e7e0") + ) + (text "EEPROM zur Speicherung von Daten" + (exclude_from_sim no) + (at 30.226 84.074 0) + (effects + (font + (size 1.27 1.27) + ) + ) + (uuid "e409210f-6257-473c-a35d-3c344f0efce3") + ) + (text "max. 50mA" + (exclude_from_sim no) + (at 48.26 16.764 0) + (effects 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) + ) + ) + (number "9" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + ) + ) + ) +) \ No newline at end of file diff --git a/Hardware/MVBMS/Symbol_Library/FaSTTUBe_connectors.kicad_sym b/Hardware/MVBMS/Symbol_Library/FaSTTUBe_connectors.kicad_sym new file mode 100644 index 0000000..6093356 --- /dev/null +++ b/Hardware/MVBMS/Symbol_Library/FaSTTUBe_connectors.kicad_sym @@ -0,0 +1,1060 @@ +(kicad_symbol_lib + (version 20231120) + (generator "kicad_symbol_editor") + (generator_version "8.0") + (symbol "M8_4pin_horizontal" + (pin_names + (offset 1.016) + ) + (exclude_from_sim no) + (in_bom yes) + (on_board yes) + (property "Reference" "J" + (at 5.334 5.08 0) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Value" "M8_4pin_horizontal" + (at 0 -6.35 0) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Footprint" "FaSTTUBe_connectors:M8_718_4pin_horizontal" + (at 0 -8.89 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Datasheet" 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b/Hardware/MVBMS/Symbol_Library/FaSTTUBe_connectors.pretty/M8_718_4pin_horizontal.kicad_mod new file mode 100644 index 0000000..5fa6998 --- /dev/null +++ b/Hardware/MVBMS/Symbol_Library/FaSTTUBe_connectors.pretty/M8_718_4pin_horizontal.kicad_mod @@ -0,0 +1,124 @@ +(footprint "M8_718_4pin_horizontal" + (version 20240108) + (generator "pcbnew") + (generator_version "8.0") + (layer "F.Cu") + (property "Reference" "REF**" + (at 0 3.81 0) + (layer "F.SilkS") + (uuid "b680b4a7-6cb0-40b5-a7ec-a02910a0daa4") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Value" "M8_718_4pin" + (at 0 -7.62 0) + (layer "F.Fab") + (uuid "c5a1761e-3391-4e74-90c9-947fd66e1fc6") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Footprint" "" + (at 0 0 0) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid "b99bb331-fb03-45a0-930b-51b6a76e7ba2") + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 0) + (unlocked yes) + (layer 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(remove_unused_layers no) + (uuid "a3668681-09b1-48f0-a7b1-f6b24183a469") + ) + (pad "5" thru_hole circle + (at -6.25 -0.5) + (size 4 4) + (drill 3) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (uuid "563c12e4-8f8c-446c-a11f-94f5aa93b994") + ) + (pad "5" thru_hole circle + (at 6.25 -0.5) + (size 4 4) + (drill 3) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (uuid "3451168c-3c76-4628-aee4-7c231bd100c3") + ) + (model "${KIPRJMOD}/Symbol_Libraries/FaSTTUBe_connectors_3dmodels/M8_718_4pin_horizontal.stp" + (offset + (xyz 0 -2.65 6.3) + ) + (scale + (xyz 1 1 1) + ) + (rotate + (xyz 90 0 90) + ) + ) +) \ No newline at end of file diff --git a/Hardware/MVBMS/Symbol_Library/FaSTTUBe_connectors.pretty/M8_718_4pin_vertical.kicad_mod b/Hardware/MVBMS/Symbol_Library/FaSTTUBe_connectors.pretty/M8_718_4pin_vertical.kicad_mod new file mode 100644 index 0000000..752f6b0 --- /dev/null +++ b/Hardware/MVBMS/Symbol_Library/FaSTTUBe_connectors.pretty/M8_718_4pin_vertical.kicad_mod @@ -0,0 +1,157 @@ +(footprint "M8_718_4pin_vertical" + (version 20240108) + (generator "pcbnew") + (generator_version "8.0") + (layer "F.Cu") + (property "Reference" "REF**" + (at 0 8 0) + (layer "F.SilkS") + (uuid "b680b4a7-6cb0-40b5-a7ec-a02910a0daa4") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Value" "M8_718_4pin" + (at 0 -7.62 0) + (layer "F.Fab") + (uuid "c5a1761e-3391-4e74-90c9-947fd66e1fc6") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Footprint" "" + (at 0 0 0) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid "dcaf2f58-7535-4c16-a965-c0b08929320b") + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 0) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid "23c79916-6723-4a1f-a564-a37aa3cd420c") + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Description" "" + (at 0 0 0) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid "967d72d7-8798-4823-a439-fc04a483d4ab") + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (attr through_hole) + (fp_arc + (start -6 -2.5) + (mid 0 -6.5) + (end 6 -2.5) + (stroke + (width 0.12) + (type solid) + ) + (layer "F.SilkS") + (uuid "b287f145-851e-45cc-b200-e62677b551d5") + ) + (fp_arc + (start 6 2.5) + (mid 0 6.5) + (end -6 2.5) + (stroke + (width 0.12) + (type solid) + ) + (layer "F.SilkS") + (uuid "a7f25f41-0b4c-4430-b6cd-b2160b2db099") + ) + (fp_circle + (center 0 0) + (end 8.5 0) + (stroke + (width 0.05) + (type solid) + ) + (fill none) + (layer "F.CrtYd") + (uuid "422b10b9-e829-44a2-8808-05edd8cb3050") + ) + (pad "1" thru_hole circle + (at 1.7 0.5) + (size 1.8 1.8) + (drill 1.3) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (uuid "a1c7b1f5-f895-4192-9484-2357882c73e0") + ) + (pad "2" thru_hole circle + (at 1.075 -1.45) + (size 1.8 1.8) + (drill 1.3) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (uuid "681bd495-c396-44ce-92bd-4b397cd48c04") + ) + (pad "3" thru_hole circle + (at -1.7 0.5) + (size 1.8 1.8) + (drill 1.3) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (uuid "be0953c0-632d-4dd2-85e9-4d41239f22d2") + ) + (pad "4" thru_hole circle + (at -1.075 -1.45) + (size 1.8 1.8) + (drill 1.3) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (uuid "a3668681-09b1-48f0-a7b1-f6b24183a469") + ) + (pad "5" thru_hole circle + (at -6.25 0) + (size 4 4) + (drill 3) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (uuid "563c12e4-8f8c-446c-a11f-94f5aa93b994") + ) + (pad "5" thru_hole circle + (at 6.25 0) + (size 4 4) + (drill 3) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (uuid "3451168c-3c76-4628-aee4-7c231bd100c3") + ) + (model "${KIPRJMOD}/Symbol_Libraries/FaSTTUBe_connectors_3dmodels/M8_718_4pin_vertical.stp" + (offset + (xyz 0 0 0.6) + ) + (scale + (xyz 1 1 1) + ) + (rotate + (xyz 90 90 90) + ) + ) +) \ No newline at end of file diff --git a/Hardware/MVBMS/Symbol_Library/FaSTTUBe_connectors.pretty/Micro Mate-N-Lok 6-Pol.kicad_mod b/Hardware/MVBMS/Symbol_Library/FaSTTUBe_connectors.pretty/Micro Mate-N-Lok 6-Pol.kicad_mod new file mode 100644 index 0000000..17697bd --- /dev/null +++ b/Hardware/MVBMS/Symbol_Library/FaSTTUBe_connectors.pretty/Micro Mate-N-Lok 6-Pol.kicad_mod @@ -0,0 +1,48 @@ +(module "214450876" (layer F.Cu) + (descr "2-1445087-6-1") + (tags "Connector") + (attr smd) + (fp_text reference J** (at 0.000 -1.27) (layer F.SilkS) + (effects (font (size 1.27 1.27) (thickness 0.254))) + ) + (fp_text user %R (at 0.000 -1.27) (layer F.Fab) + (effects (font (size 1.27 1.27) (thickness 0.254))) + ) + (fp_text value "214450876" (at 0.000 -1.27) (layer F.SilkS) hide + (effects (font (size 1.27 1.27) (thickness 0.254))) + ) + (fp_line (start -11 1.93) (end 11 1.93) (layer F.Fab) (width 0.1)) + (fp_line (start 11 1.93) (end 11 -1.93) (layer F.Fab) (width 0.1)) + (fp_line (start 11 -1.93) (end -11 -1.93) (layer F.Fab) (width 0.1)) + (fp_line (start -11 -1.93) (end -11 1.93) (layer F.Fab) (width 0.1)) + (fp_line (start -13.92 -5.47) (end 13.92 -5.47) (layer F.CrtYd) (width 0.1)) + (fp_line (start 13.92 -5.47) (end 13.92 2.93) (layer F.CrtYd) (width 0.1)) + (fp_line (start 13.92 2.93) (end -13.92 2.93) (layer F.CrtYd) (width 0.1)) + (fp_line (start -13.92 2.93) (end -13.92 -5.47) (layer F.CrtYd) (width 0.1)) + (fp_line (start 11 1.3) (end 11 1.93) (layer F.SilkS) (width 0.2)) + (fp_line (start 11 1.93) (end -11 1.93) (layer F.SilkS) (width 0.2)) + (fp_line (start -11 1.93) (end -11 1.3) (layer F.SilkS) (width 0.2)) + (fp_line (start -11 -1.4) (end -11 -1.93) (layer F.SilkS) (width 0.2)) + (fp_line (start -11 -1.93) (end -8.77 -1.93) (layer F.SilkS) (width 0.2)) + (fp_line (start 8.63 -1.93) (end 11 -1.93) (layer F.SilkS) (width 0.2)) + (fp_line (start 11 -1.93) (end 11 -1.1) (layer F.SilkS) (width 0.2)) + (fp_line (start 7.43 -5.1) (end 7.43 -5.1) (layer F.SilkS) (width 0.2)) + (fp_line (start 7.43 -5) (end 7.43 -5) (layer F.SilkS) (width 0.2)) + (fp_line (start 7.43 -5.1) (end 7.43 -5.1) (layer F.SilkS) (width 0.2)) + (fp_arc (start 7.43 -5.05) (end 7.430 -5.1) (angle -180) (layer F.SilkS) (width 0.2)) + (fp_arc (start 7.43 -5.05) (end 7.430 -5) (angle -180) (layer F.SilkS) (width 0.2)) + (fp_arc (start 7.43 -5.05) (end 7.430 -5.1) (angle -180) (layer F.SilkS) (width 0.2)) + (pad 1 smd rect (at 7.430 -3.2 0) (size 1.270 2.540) (layers F.Cu F.Paste F.Mask)) + (pad 2 smd rect (at 4.430 -3.2 0) (size 1.270 2.540) (layers F.Cu F.Paste F.Mask)) + (pad 3 smd rect (at 1.430 -3.2 0) (size 1.270 2.540) (layers F.Cu F.Paste F.Mask)) + (pad 4 smd rect (at -1.570 -3.2 0) (size 1.270 2.540) (layers F.Cu F.Paste F.Mask)) + (pad 5 smd rect (at -4.570 -3.2 0) (size 1.270 2.540) (layers F.Cu F.Paste F.Mask)) + (pad 6 smd rect (at -7.570 -3.2 0) (size 1.270 2.540) (layers F.Cu F.Paste F.Mask)) + (pad MP1 smd rect (at 11.205 -0 90) (size 1.650 3.430) (layers F.Cu F.Paste F.Mask)) + (pad MP2 smd rect (at -11.205 -0 90) (size 1.650 3.430) (layers F.Cu F.Paste F.Mask)) + (model 2-1445087-6.stp + (at (xyz -0.0023622046716101 0 0.36732283164197)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 -180)) + ) +) diff --git a/Hardware/MVBMS/Symbol_Library/FaSTTUBe_connectors.pretty/Micro_Mate-N-Lok_2p_horizontal.kicad_mod b/Hardware/MVBMS/Symbol_Library/FaSTTUBe_connectors.pretty/Micro_Mate-N-Lok_2p_horizontal.kicad_mod new file mode 100644 index 0000000..873a76f --- /dev/null +++ b/Hardware/MVBMS/Symbol_Library/FaSTTUBe_connectors.pretty/Micro_Mate-N-Lok_2p_horizontal.kicad_mod @@ -0,0 +1,150 @@ +(footprint "Micro_Mate-N-Lok_2p_horizontal" + (version 20240108) + (generator "pcbnew") + (generator_version "8.0") + (layer "F.Cu") + (property "Reference" "REF**" + (at 0 7.6 0) + (layer "F.SilkS") + (uuid "b3717aae-6e72-4c5e-8a33-b309bc4120fe") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Value" "Micro Mate-N-Lok 2-Pol" + (at 0 -6.22 0) + (layer "F.Fab") + (uuid "36e4278e-3a17-4a30-b25f-b47e619d8e54") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Footprint" "" + (at 0 0 0) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid "4afde509-61aa-4495-bea4-931c6d300cdc") + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 0) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid "e13156ef-c15d-4d24-b178-c187d3564ad3") + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Description" "" + (at 0 0 0) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid "d7224dbc-1065-41b6-82a1-ff9de5b98743") + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (attr through_hole) + (fp_line + (start -5 -5.4) + (end 0 -5.4) + (stroke + (width 0.15) + (type solid) + ) + (layer "F.CrtYd") + (uuid "1c02454f-e74b-4db5-89ce-8549d76c156b") + ) + (fp_line + (start -5 6.2) + (end -5 -5.4) + (stroke + (width 0.15) + (type solid) + ) + (layer "F.CrtYd") + (uuid "79b7e7a7-54a5-4f04-ada0-5a78f329fb69") + ) + (fp_line + (start 0 -5.4) + (end 5 -5.4) + (stroke + (width 0.15) + (type solid) + ) + (layer "F.CrtYd") + (uuid "a3f5f53b-a0a9-4632-9850-54b7a6125d67") + ) + (fp_line + (start 5 -5.4) + (end 5 6.2) + (stroke + (width 0.15) + (type solid) + ) + (layer "F.CrtYd") + (uuid "52aa1cc1-965b-412c-a19e-6434cee1a6e3") + ) + (fp_line + (start 5 6.2) + (end -5 6.2) + (stroke + (width 0.15) + (type solid) + ) + (layer "F.CrtYd") + (uuid "e50755df-05fe-403a-adf5-a2d6e7cc5677") + ) + (pad "" smd rect + (at -5.2 1.6) + (size 3.43 1.65) + (layers "F.Cu" "F.Paste" "F.Mask") + (uuid "c98ad03f-45fb-4c08-925c-a798f952439a") + ) + (pad "" smd rect + (at 5.21 1.6) + (size 3.43 1.65) + (layers "F.Cu" "F.Paste" "F.Mask") + (uuid "1d1a1370-ddd7-4bd7-8fbf-a91b362cb160") + ) + (pad "1" smd rect + (at -1.5 -3.88) + (size 1.27 3) + (layers "F.Cu" "F.Paste" "F.Mask") + (uuid "2291a95f-cda2-4dc8-88fc-a9b0f19ba741") + ) + (pad "2" smd rect + (at 1.5 -3.88) + (size 1.27 3) + (layers "F.Cu" "F.Paste" "F.Mask") + (uuid "6df97d6c-664b-46c7-9be8-e97b286ece26") + ) + (model "${KIPRJMOD}/Symbol_Library/FaSTTUBe_connectors_3dmodels/Micro_Mate-N-Lok_2p_horizontal.stp" + (offset + (xyz 0 -6.2 2.5) + ) + (scale + (xyz 1 1 1) + ) + (rotate + (xyz -90 0 0) + ) + ) +) \ No newline at end of file diff --git a/Hardware/MVBMS/Symbol_Library/FaSTTUBe_connectors.pretty/Micro_Mate-N-Lok_2p_vertical.kicad_mod b/Hardware/MVBMS/Symbol_Library/FaSTTUBe_connectors.pretty/Micro_Mate-N-Lok_2p_vertical.kicad_mod new file mode 100644 index 0000000..bac98af --- /dev/null +++ b/Hardware/MVBMS/Symbol_Library/FaSTTUBe_connectors.pretty/Micro_Mate-N-Lok_2p_vertical.kicad_mod @@ -0,0 +1,240 @@ +(footprint "Micro_Mate-N-Lok_2p_vertical" + (version 20240108) + (generator "pcbnew") + (generator_version "8.0") + (layer "F.Cu") + (property "Reference" "REF**" + (at 0 3.81 0) + (unlocked yes) + (layer "F.SilkS") + (uuid "42713045-fffd-4b2d-ae1e-7232d705fb12") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Value" "Micro_Mate-N-Lok_2p_vertical" + (at 0 1 0) + (unlocked yes) + (layer "F.Fab") + (uuid "c0515cd2-cdaa-467e-8354-0f6eadfa35c9") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Footprint" "" + (at 0 0 0) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid "b898cf0a-05f1-4c3b-be4e-d91efa4940f9") + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 0) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid "a88b67c9-ac78-4a8c-859a-d3187554084d") + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Description" "" + (at 0 0 0) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid "5a17c508-2162-46c6-99ef-5ad462d1b667") + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (attr smd) + (fp_line + (start -3.81 -2.54) + (end -2.54 -2.54) + (stroke + (width 0.12) + (type solid) + ) + (layer "F.SilkS") + (uuid "3742a313-c63e-4807-a7bf-be5a0ae2c781") + ) + (fp_line + (start -3.81 -1.27) + (end -3.81 -2.54) + (stroke + (width 0.12) + (type solid) + ) + (layer "F.SilkS") + (uuid "5e27f565-c85a-4f3b-9862-58c0accdd5e3") + ) + (fp_line + (start -3.81 2.54) + (end -3.81 1.27) + (stroke + (width 0.12) + (type solid) + ) + (layer "F.SilkS") + (uuid "d35d7027-ac1b-44b2-9664-3d8a37ee0f4e") + ) + (fp_line + (start -3.81 2.54) + (end 3.81 2.54) + (stroke + (width 0.12) + (type solid) + ) + (layer "F.SilkS") + (uuid "1c052668-6749-425a-9a77-35f046c8aa39") + ) + (fp_line + (start -0.508 -3.302) + (end 0.508 -3.302) + (stroke + (width 0.12) + (type solid) + ) + (layer "F.SilkS") + (uuid "4ba06b66-7669-4c70-b585-f5d4c9c33527") + ) + (fp_line + (start 2.54 -2.54) + (end 3.81 -2.54) + (stroke + (width 0.12) + (type solid) + ) + (layer "F.SilkS") + (uuid "e8558fbd-ea42-43a6-966a-7bd304bdfaad") + ) + (fp_line + (start 3.81 -2.54) + (end 3.81 -1.27) + (stroke + (width 0.12) + (type solid) + ) + (layer "F.SilkS") + (uuid "2b894b8a-c098-4d9d-be0f-2ef41dea274e") + ) + (fp_line + (start 3.81 2.54) + (end 3.81 1.27) + (stroke + (width 0.12) + (type solid) + ) + (layer "F.SilkS") + (uuid "25ca9482-069d-43de-b77e-6f2ad77fa017") + ) + (fp_circle + (center -5.08 -3.81) + (end -4.58 -3.81) + (stroke + (width 0.12) + (type solid) + ) + (fill solid) + (layer "F.SilkS") + (uuid "63489ebf-0f52-43a6-a0ab-158b1a7d4988") + ) + (fp_rect + (start -7.62 -5.08) + (end 7.62 2.54) + (stroke + (width 0.05) + (type solid) + ) + (fill none) + (layer "F.CrtYd") + (uuid "312474c5-a081-4cd1-b2e6-730f0718514a") + ) + (fp_line + (start 4.318 1.27) + (end 5.08 1.27) + (stroke + (width 0.1) + (type solid) + ) + (layer "F.Fab") + (uuid "c6462399-f2e4-4f1a-b34a-b49a04c8bdb9") + ) + (fp_line + (start 4.318 1.778) + (end 4.318 1.27) + (stroke + (width 0.1) + (type solid) + ) + (layer "F.Fab") + (uuid "f284b1e2-75a4-4a3f-a5f4-6f05f15fb4f5") + ) + (fp_text user "${REFERENCE}" + (at 0 0 0) + (unlocked yes) + (layer "F.Fab") + (uuid "1bf544e3-5940-4576-9291-2464e95c0ee2") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (pad "" smd roundrect + (at -5.2 0) + (size 3.43 1.65) + (layers "F.Cu" "F.Paste" "F.Mask") + (roundrect_rratio 0.25) + (uuid "1f3003e6-dce5-420f-906b-3f1e92b67249") + ) + (pad "" smd roundrect + (at 5.2 0) + (size 3.43 1.65) + (layers "F.Cu" "F.Paste" "F.Mask") + (roundrect_rratio 0.25) + (uuid "378af8b4-af3d-46e7-89ae-deff12ca9067") + ) + (pad "1" smd roundrect + (at -1.5 -3.2) + (size 1.27 2.54) + (layers "F.Cu" "F.Paste" "F.Mask") + (roundrect_rratio 0.25) + (uuid "ebd06df3-d52b-4cff-99a2-a771df6d3733") + ) + (pad "2" smd roundrect + (at 1.5 -3.2) + (size 1.27 2.54) + (layers "F.Cu" "F.Paste" "F.Mask") + (roundrect_rratio 0.25) + (uuid "8c0807a7-765b-4fa5-baaa-e09a2b610e6b") + ) + (model "${KIPRJMOD}/Symbol_Library/FaSTTUBe_connectors_3dmodels/Micro_Mate-N-Lok_2p_vertical.stp" + (offset + (xyz 0 0 9.24) + ) + (scale + (xyz 1 1 1) + ) + (rotate + (xyz 0 0 180) + ) + ) +) \ No newline at end of file diff --git a/Hardware/MVBMS/Symbol_Library/FaSTTUBe_connectors.pretty/Micro_Mate-N-Lok_2x2p_vertical.kicad_mod b/Hardware/MVBMS/Symbol_Library/FaSTTUBe_connectors.pretty/Micro_Mate-N-Lok_2x2p_vertical.kicad_mod new file mode 100644 index 0000000..d700bc9 --- /dev/null +++ b/Hardware/MVBMS/Symbol_Library/FaSTTUBe_connectors.pretty/Micro_Mate-N-Lok_2x2p_vertical.kicad_mod @@ -0,0 +1,303 @@ +(footprint "Micro_Mate-N-Lok_2x2p_vertical" + (version 20240108) + (generator "pcbnew") + (generator_version "8.0") + (layer "F.Cu") + (descr "3-794636-4-1") + (tags "Connector") + (property "Reference" "J**" + (at 0 0 0) + (layer "F.SilkS") + (uuid "de6dbf15-ae79-4d66-abac-08480863616c") + (effects + (font + (size 1.27 1.27) + (thickness 0.254) + ) + ) + ) + (property "Value" "37946364" + (at 0 0 0) + (layer "F.SilkS") + (hide yes) + (uuid "73454dd1-5b2b-42e4-bdce-e925fb2d75ff") + (effects + (font + (size 1.27 1.27) + (thickness 0.254) + ) + ) + ) + (property "Footprint" "" + (at 0 0 0) + (unlocked yes) + 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+END-ISO-10303-21; diff --git a/Hardware/MVBMS/Symbol_Library/FaSTTUBe_connectors_3dmodels/Micro_Mate-N-Lok_2p_horizontal.kicad_mod b/Hardware/MVBMS/Symbol_Library/FaSTTUBe_connectors_3dmodels/Micro_Mate-N-Lok_2p_horizontal.kicad_mod new file mode 100644 index 0000000..8e17e1d --- /dev/null +++ b/Hardware/MVBMS/Symbol_Library/FaSTTUBe_connectors_3dmodels/Micro_Mate-N-Lok_2p_horizontal.kicad_mod @@ -0,0 +1,17 @@ +(module "Micro Mate-N-Lok 2-Pol" (layer F.Cu) (tedit 5CE9F075) + (fp_text reference REF** (at 0 7.6) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value "Micro Mate-N-Lok 2-Pol" (at 0 -6.22) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 0 -5.4) (end 5 -5.4) (layer F.CrtYd) (width 0.15)) + (fp_line (start 5 -5.4) (end 5 6.2) (layer F.CrtYd) (width 0.15)) + (fp_line (start 5 6.2) (end -5 6.2) (layer F.CrtYd) (width 0.15)) + (fp_line (start -5 6.2) (end -5 -5.4) (layer F.CrtYd) (width 0.15)) + (fp_line (start -5 -5.4) (end 0 -5.4) (layer F.CrtYd) (width 0.15)) + (pad 1 smd rect (at -1.5 -3.88) (size 1.27 3) (layers F.Cu F.Paste F.Mask)) + (pad 2 smd rect (at 1.5 -3.88) (size 1.27 3) (layers F.Cu F.Paste F.Mask)) + (pad "" smd rect (at -5.2 1.6) (size 3.43 1.65) (layers F.Cu F.Paste F.Mask)) + (pad "" smd rect (at 5.21 1.6) (size 3.43 1.65) (layers F.Cu F.Paste F.Mask)) +) diff --git a/Hardware/MVBMS/Symbol_Library/FaSTTUBe_connectors_3dmodels/Micro_Mate-N-Lok_2p_horizontal.stp b/Hardware/MVBMS/Symbol_Library/FaSTTUBe_connectors_3dmodels/Micro_Mate-N-Lok_2p_horizontal.stp new file mode 100755 index 0000000..fd8e7d0 --- /dev/null +++ b/Hardware/MVBMS/Symbol_Library/FaSTTUBe_connectors_3dmodels/Micro_Mate-N-Lok_2p_horizontal.stp @@ -0,0 +1,7031 @@ +ISO-10303-21; +HEADER; +FILE_DESCRIPTION((''),'2;1'); +FILE_NAME('C-2-1445091-2','2010-05-29T',('workeradm'),('Tyco Electronics Ltd.'), +'PRO/ENGINEER BY PARAMETRIC TECHNOLOGY CORPORATION, 2009300', +'PRO/ENGINEER BY PARAMETRIC TECHNOLOGY CORPORATION, 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(at -5.08 0 0) + (length 5.334) + (name "G" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (number "1" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + ) + (pin passive line + (at 2.54 -5.08 90) + (length 2.54) + (name "S" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (number "2" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + ) + (pin passive line + (at 2.54 5.08 270) + (length 2.54) + (name "D" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (number "3" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + ) + ) + ) + (symbol "M24M01E-FMN6TP" + (exclude_from_sim no) + (in_bom yes) + (on_board yes) + (property "Reference" "IC0" + (at 13.97 6.985 0) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Value" "M24M01E-FMN6TP" + (at 13.97 4.445 0) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Footprint" "Package_SO:SO-8_3.9x4.9mm_P1.27mm" + (at 24.13 -94.92 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + (hide yes) + ) + ) + (property "Datasheet" "https://www.st.com/resource/en/datasheet/m24m01e-f.pdf" + (at 24.13 -194.92 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + (hide yes) + ) + ) + (property "Description" "" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Height" "1.75" + (at 24.13 -394.92 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + (hide yes) + ) + ) + (property "Mouser Part Number" "" + (at 24.13 -494.92 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + (hide yes) + ) + ) + (property "Mouser Price/Stock" "" + (at 24.13 -594.92 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + (hide yes) + ) + ) + (property "Manufacturer_Name" "STMicroelectronics" + (at 24.13 -694.92 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + (hide yes) + ) + ) + (property "Manufacturer_Part_Number" "M24M01E-FMN6TP" + (at 24.13 -794.92 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + (hide yes) + ) + ) + (symbol "M24M01E-FMN6TP_1_1" + (rectangle + (start 5.08 2.54) + (end 22.86 -10.16) + (stroke + (width 0.254) + (type default) + ) + (fill + (type background) + ) + ) + (pin passive line + (at 0 0 0) + (length 5.08) + (name "NC_1" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (number "1" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + ) + (pin passive line + (at 0 -2.54 0) + (length 5.08) + (name "NC_2" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (number "2" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + ) + (pin passive line + (at 0 -5.08 0) + (length 5.08) + (name "NC_3" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (number "3" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + ) + (pin passive line + (at 0 -7.62 0) + (length 5.08) + (name "VSS" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (number "4" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + ) + (pin passive line + (at 27.94 -7.62 180) + (length 5.08) + (name "SDA" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (number "5" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + ) + (pin passive line + (at 27.94 -5.08 180) + (length 5.08) + (name "SCL" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (number "6" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + ) + (pin passive line + (at 27.94 -2.54 180) + (length 5.08) + (name "~{WC}" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (number "7" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + ) + (pin passive line + (at 27.94 0 180) + (length 5.08) + (name "VCC" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (number "8" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + ) + ) + ) + (symbol "PVG612AS" + (exclude_from_sim no) + (in_bom yes) + (on_board yes) + (property "Reference" "U1" + (at 0 8.255 0) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Value" "PVG612AS" + (at 0 5.715 0) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Footprint" "Package_DIP:SMDIP-6_W9.53mm" + (at 0 -7.62 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Datasheet" "https://www.infineon.com/dgdl/Infineon-PVG612A-DataSheet-v01_00-EN.pdf?fileId=5546d462533600a401535683ca14293a" + (at 0 -10.16 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Description" "" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "ki_keywords" "photocouplers photorelay solidstate relay normally opened" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "ki_fp_filters" "DIP*W7.62mm*" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (symbol "PVG612AS_0_1" + (rectangle + (start -5.08 3.81) + (end 5.08 -3.81) + (stroke + (width 0.254) + (type default) + ) + (fill + (type background) + ) + ) + (polyline + (pts + (xy -3.81 -0.635) (xy -2.54 -0.635) + ) + (stroke + (width 0) + (type default) + ) + (fill + (type none) + ) + ) + (polyline + (pts + (xy 1.016 -0.635) (xy 1.016 -2.159) + ) + (stroke + (width 0.2032) + (type default) + ) + (fill + (type none) + ) + ) + (polyline + (pts + (xy 1.016 2.159) (xy 1.016 0.635) + ) + (stroke + (width 0.2032) + (type default) + ) + (fill + (type none) + ) + ) + (polyline + (pts + (xy 1.524 -0.508) (xy 1.524 -0.762) + ) + (stroke + (width 0.3556) + (type default) + ) + (fill + (type none) + ) + ) + (polyline + (pts + (xy 2.794 0) (xy 5.08 0) + ) + (stroke + (width 0) + (type default) + ) + (fill + (type none) + ) + ) + (polyline + (pts + (xy 3.429 -1.651) (xy 4.191 -1.651) + ) + (stroke + (width 0) + (type default) + ) + (fill + (type none) + ) + ) + (polyline + (pts + (xy 3.429 1.651) (xy 4.191 1.651) + ) + (stroke + (width 0) + (type default) + ) + (fill + (type none) + ) + ) + (polyline + (pts + (xy 3.81 -2.54) (xy 3.81 2.54) + ) + (stroke + (width 0) + (type default) + ) + (fill + (type none) + ) + ) + (polyline + (pts + (xy 1.524 -2.032) (xy 1.524 -2.286) (xy 1.524 -2.286) + ) + (stroke + (width 0.3556) + (type default) + ) + (fill + (type none) + ) + ) + (polyline + (pts + (xy 1.524 -1.27) (xy 1.524 -1.524) (xy 1.524 -1.524) + ) + (stroke + (width 0.3556) + (type default) + ) + (fill + (type none) + ) + ) + (polyline + (pts + (xy 1.524 0.762) (xy 1.524 0.508) (xy 1.524 0.508) + ) + (stroke + (width 0.3556) + (type default) + ) + (fill + (type none) + ) + ) + (polyline + (pts + (xy 1.524 1.524) (xy 1.524 1.27) (xy 1.524 1.27) + ) + (stroke + (width 0.3556) + (type default) + ) + (fill + (type none) + ) + ) + (polyline + (pts + (xy 1.524 2.286) (xy 1.524 2.032) (xy 1.524 2.032) + ) + (stroke + (width 0.3556) + (type default) + ) + (fill + (type none) + ) + ) + (polyline + (pts + (xy 1.651 -1.397) (xy 2.794 -1.397) (xy 2.794 -0.635) + ) + (stroke + (width 0) + (type default) + ) + (fill + (type none) + ) + ) + (polyline + (pts + (xy 1.651 1.397) (xy 2.794 1.397) (xy 2.794 0.635) + ) + (stroke + (width 0) + (type default) + ) + (fill + (type none) + ) + ) + (polyline + (pts + (xy -5.08 2.54) (xy -3.175 2.54) (xy -3.175 -2.54) (xy -5.08 -2.54) + ) + (stroke + (width 0) + (type default) + ) + (fill + (type none) + ) + ) + (polyline + (pts + (xy -3.175 -0.635) (xy -3.81 0.635) (xy -2.54 0.635) (xy -3.175 -0.635) + ) + (stroke + (width 0) + (type default) + ) + (fill + (type none) + ) + ) + (polyline + (pts + (xy 1.651 -2.159) (xy 2.794 -2.159) (xy 2.794 -2.54) (xy 5.08 -2.54) + ) + (stroke + (width 0) + (type default) + ) + (fill + (type none) + ) + ) + (polyline + (pts + (xy 1.651 -0.635) (xy 2.794 -0.635) (xy 2.794 0.635) (xy 1.651 0.635) + ) + (stroke + (width 0) + (type default) + ) + (fill + (type none) + ) + ) + (polyline + (pts + (xy 1.651 2.159) (xy 2.794 2.159) (xy 2.794 2.54) (xy 5.08 2.54) + ) + (stroke + (width 0) + (type default) + ) + (fill + (type none) + ) + ) + (polyline + (pts + (xy 1.778 -1.397) (xy 2.286 -1.27) (xy 2.286 -1.524) (xy 1.778 -1.397) + ) + (stroke + (width 0) + (type default) + ) + (fill + (type none) + ) + ) + (polyline + (pts + (xy 1.778 1.397) (xy 2.286 1.524) (xy 2.286 1.27) (xy 1.778 1.397) + ) + (stroke + (width 0) + (type default) + ) + (fill + (type none) + ) + ) + (polyline + (pts + (xy 3.81 -1.651) (xy 3.429 -0.889) (xy 4.191 -0.889) (xy 3.81 -1.651) + ) + (stroke + (width 0) + (type default) + ) + (fill + (type none) + ) + ) + (polyline + (pts + (xy 3.81 1.651) (xy 3.429 0.889) (xy 4.191 0.889) (xy 3.81 1.651) + ) + (stroke + (width 0) + (type default) + ) + (fill + (type none) + ) + ) + (polyline + (pts + (xy -1.905 -0.508) (xy -0.635 -0.508) (xy -1.016 -0.635) (xy -1.016 -0.381) (xy -0.635 -0.508) + ) + (stroke + (width 0) + (type default) + ) + (fill + (type none) + ) + ) + (polyline + (pts + (xy -1.905 0.508) (xy -0.635 0.508) (xy -1.016 0.381) (xy -1.016 0.635) (xy -0.635 0.508) + ) + (stroke + (width 0) + (type default) + ) + (fill + (type none) + ) + ) + (circle + (center 2.794 -0.635) + (radius 0.127) + (stroke + (width 0) + (type default) + ) + (fill + (type none) + ) + ) + (circle + (center 2.794 0) + (radius 0.127) + (stroke + (width 0) + (type default) + ) + (fill + (type none) + ) + ) + (circle + (center 2.794 0.635) + (radius 0.127) + (stroke + (width 0) + (type default) + ) + (fill + (type none) + ) + ) + (circle + (center 3.81 -2.54) + (radius 0.127) + (stroke + (width 0) + (type default) + ) + (fill + (type none) + ) + ) + (circle + (center 3.81 0) + (radius 0.127) + (stroke + (width 0) + (type default) + ) + (fill + (type none) + ) + ) + (circle + (center 3.81 2.54) + (radius 0.127) + (stroke + (width 0) + (type default) + ) + (fill + (type none) + ) + ) + ) + (symbol "PVG612AS_1_1" + (pin passive line + (at -7.62 2.54 0) + (length 2.54) + (name "~" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (number "1" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + ) + (pin passive line + (at -7.62 -2.54 0) + (length 2.54) + (name "~" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (number "2" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + ) + (pin no_connect line + (at -5.08 0 0) + (length 2.54) hide + (name "~" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (number "3" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + ) + (pin passive line + (at 7.62 -2.54 180) + (length 2.54) + (name "~" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (number "4" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + ) + (pin passive line + (at 7.62 0 180) + (length 2.54) + (name "~" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (number "5" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + ) + (pin passive line + (at 7.62 2.54 180) + (length 2.54) + (name "~" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (number "6" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + ) + ) + ) +) diff --git a/Hardware/MVBMS/Symbol_Library/MVBMS.kicad_sym.kicad_sym b/Hardware/MVBMS/Symbol_Library/MVBMS.kicad_sym.kicad_sym new file mode 100644 index 0000000..a42b500 --- /dev/null +++ b/Hardware/MVBMS/Symbol_Library/MVBMS.kicad_sym.kicad_sym @@ -0,0 +1,5 @@ +(kicad_symbol_lib + (version 20231120) + (generator "kicad_symbol_editor") + (generator_version "8.0") +) \ No newline at end of file diff --git a/Hardware/MVBMS/Symbol_Library/MVBMS.pretty/2024-06-20_18-19-51.kicad_sym b/Hardware/MVBMS/Symbol_Library/MVBMS.pretty/2024-06-20_18-19-51.kicad_sym new file mode 100644 index 0000000..5949e2d --- /dev/null +++ b/Hardware/MVBMS/Symbol_Library/MVBMS.pretty/2024-06-20_18-19-51.kicad_sym @@ -0,0 +1,430 @@ +(kicad_symbol_lib (version 20211014) (generator kicad_symbol_editor) + (symbol "2-1445057-6" (pin_names (offset 0.254)) (in_bom yes) (on_board yes) + (property "Reference" "J" (id 0) (at 8.89 6.35 0) + (effects (font (size 1.524 1.524))) + ) + (property "Value" "2-1445057-6" (id 1) (at 0 0 0) + (effects (font (size 1.524 1.524))) + ) + (property "Footprint" "CONN_2-1445057-6_TYCO" (id 2) (at 0 0 0) + (effects (font (size 1.27 1.27) italic) hide) + ) + (property "Datasheet" "2-1445057-6" (id 3) (at 0 0 0) + (effects (font (size 1.27 1.27) italic) hide) + ) + (property "ki_keywords" "2-1445057-6" (id 4) (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "ki_locked" "" (id 5) (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "ki_fp_filters" "CONN_2-1445057-6_TYCO" (id 6) (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (symbol "2-1445057-6_1_1" + (polyline + (pts + (xy 10.16 0) + (xy 5.08 0) + ) + (stroke (width 0.127) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (polyline + (pts + (xy 10.16 -2.54) + (xy 5.08 -2.54) + ) + (stroke (width 0.127) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (polyline + (pts + (xy 10.16 -5.08) + (xy 5.08 -5.08) + ) + (stroke (width 0.127) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (polyline + (pts + (xy 10.16 -7.62) + (xy 5.08 -7.62) + ) + (stroke (width 0.127) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (polyline + (pts + (xy 10.16 -10.16) + (xy 5.08 -10.16) + ) + (stroke (width 0.127) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (polyline + (pts + (xy 10.16 -12.7) + (xy 5.08 -12.7) + ) + (stroke (width 0.127) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (polyline + (pts + (xy 10.16 0) + (xy 8.89 0.846666) + ) + (stroke (width 0.127) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (polyline + (pts + (xy 10.16 -2.54) + (xy 8.89 -1.693334) + ) + (stroke (width 0.127) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (polyline + (pts + (xy 10.16 -5.08) + (xy 8.89 -4.233334) + ) + (stroke (width 0.127) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (polyline + (pts + (xy 10.16 -7.62) + (xy 8.89 -6.773334) + ) + (stroke (width 0.127) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (polyline + (pts + (xy 10.16 -10.16) + (xy 8.89 -9.313334) + ) + (stroke (width 0.127) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (polyline + (pts + (xy 10.16 -12.7) + (xy 8.89 -11.853334) + ) + (stroke (width 0.127) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (polyline + (pts + (xy 10.16 0) + (xy 8.89 -0.846666) + ) + (stroke (width 0.127) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (polyline + (pts + (xy 10.16 -2.54) + (xy 8.89 -3.386666) + ) + (stroke (width 0.127) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (polyline + (pts + (xy 10.16 -5.08) + (xy 8.89 -5.926666) + ) + (stroke (width 0.127) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (polyline + (pts + (xy 10.16 -7.62) + (xy 8.89 -8.466666) + ) + (stroke (width 0.127) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (polyline + (pts + (xy 10.16 -10.16) + (xy 8.89 -11.006666) + ) + (stroke (width 0.127) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (polyline + (pts + (xy 10.16 -12.7) + (xy 8.89 -13.546666) + ) + (stroke (width 0.127) (type default) (color 0 0 0 0)) + (fill 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"${KIPRJMOD}/Symbol_Library/3DModells/524652070.stp" + (offset + (xyz 0 0 2.180000034) + ) + (scale + (xyz 1 1 1) + ) + (rotate + (xyz -90 0 0) + ) + ) +) diff --git a/Hardware/MVBMS/Symbol_Library/MVBMS.pretty/m24m01e-fmn6tp.kicad_sym b/Hardware/MVBMS/Symbol_Library/MVBMS.pretty/m24m01e-fmn6tp.kicad_sym new file mode 100644 index 0000000..f92bd97 --- /dev/null +++ b/Hardware/MVBMS/Symbol_Library/MVBMS.pretty/m24m01e-fmn6tp.kicad_sym @@ -0,0 +1,262 @@ +(kicad_symbol_lib + (version 20231120) + (generator "kicad_symbol_editor") + (generator_version "8.0") + (symbol "M24M01E-FMN6TP" + (exclude_from_sim no) + (in_bom yes) + (on_board yes) + (property "Reference" "IC0" + (at 13.97 6.985 0) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Value" "M24M01E-FMN6TP" + (at 13.97 4.445 0) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Footprint" "Package_SO:SO-8_3.9x4.9mm_P1.27mm" + (at 24.13 -94.92 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + (hide yes) + ) + ) + (property "Datasheet" "https://www.st.com/resource/en/datasheet/m24m01e-f.pdf" + (at 24.13 -194.92 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + (hide yes) + ) + ) + (property "Description" "" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Height" "1.75" + (at 24.13 -394.92 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + (hide yes) + ) + ) + (property "Mouser Part Number" "" + (at 24.13 -494.92 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + (hide yes) + ) + ) + (property "Mouser Price/Stock" "" + (at 24.13 -594.92 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + (hide yes) + ) + ) + (property "Manufacturer_Name" "STMicroelectronics" + (at 24.13 -694.92 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + (hide yes) + ) + ) + (property "Manufacturer_Part_Number" "M24M01E-FMN6TP" + (at 24.13 -794.92 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + (hide yes) + ) + ) + (symbol "M24M01E-FMN6TP_1_1" + (rectangle + (start 5.08 2.54) + (end 22.86 -10.16) + (stroke + (width 0.254) + (type default) + ) + (fill + (type background) + ) + ) + (pin passive line + (at 0 0 0) + (length 5.08) + (name "NC_1" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (number "1" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + ) + (pin passive line + (at 0 -2.54 0) + (length 5.08) + (name "NC_2" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (number "2" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + ) + (pin passive line + (at 0 -5.08 0) + (length 5.08) + (name "NC_3" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (number "3" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + ) + (pin passive line + (at 0 -7.62 0) + (length 5.08) + (name "VSS" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (number "4" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + ) + (pin passive line + (at 27.94 -7.62 180) + (length 5.08) + (name "SDA" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (number "5" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + ) + (pin passive line + (at 27.94 -5.08 180) + (length 5.08) + (name "SCL" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (number "6" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + ) + (pin passive line + (at 27.94 -2.54 180) + (length 5.08) + (name "~{WC}" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (number "7" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + ) + (pin passive line + (at 27.94 0 180) + (length 5.08) + (name "VCC" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (number "8" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + ) + ) + ) +) diff --git a/Hardware/MVBMS/Symbol_Library/MVBMS.pretty/mvbms.kicad_mod b/Hardware/MVBMS/Symbol_Library/MVBMS.pretty/mvbms.kicad_mod new file mode 100644 index 0000000..d4937c9 --- /dev/null +++ b/Hardware/MVBMS/Symbol_Library/MVBMS.pretty/mvbms.kicad_mod @@ -0,0 +1,259 @@ +(footprint "mvbms" + (version 20240108) + (generator "pcbnew") + (generator_version "8.0") + (layer "F.Cu") + (descr "Through hole straight pin header, 1x01, 2.54mm pitch, single row") + (tags "Through hole pin header THT 1x01 2.54mm single row") + (property "Reference" "REF**" + (at 0 -2.33 0) + (layer "F.SilkS") + (uuid "6c50d304-4606-47dc-966e-5ce9cce54912") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Value" "mvbms" + (at 0 2.33 0) + (layer "F.Fab") + (uuid "86a9f2cd-c84c-4f67-881e-c331171fcf5a") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Footprint" "" + (at 0 0 0) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid "f533db6b-d87a-483d-8669-171e932359e2") + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 0) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid "79edd7bb-ff18-468b-a74c-de472aa41331") + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Description" "" + (at 0 0 0) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid "a34fbf3c-c5d6-441f-ab34-787ec4073ba2") + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Silkscreen" "" + (at 0 -2.54 0) + (unlocked yes) + (layer "F.SilkS") + (uuid "0bcc6461-dd1e-47f1-b5e8-46e281bb0b51") + (effects + (font + (size 1 1) + (thickness 0.1) + ) + ) + ) + (attr through_hole) + (fp_line + (start -1.33 -1.33) + (end 0 -1.33) + (stroke + (width 0.12) + (type solid) + ) + (layer "F.SilkS") + (uuid "0d1844d8-3968-40e8-a883-14d5e2cea336") + ) + (fp_line + (start -1.33 0) + (end -1.33 -1.33) + (stroke + (width 0.12) + (type solid) + ) + (layer "F.SilkS") + (uuid "f0354a49-62ac-41dc-8301-329bb549fb27") + ) + (fp_line + (start -1.33 1.27) + (end -1.33 1.33) + (stroke + (width 0.12) + (type solid) + ) + (layer "F.SilkS") + (uuid "9785722f-c04d-4c74-9491-126777973d65") + ) + (fp_line + (start -1.33 1.27) + (end 1.33 1.27) + (stroke + (width 0.12) + (type solid) + ) + (layer "F.SilkS") + (uuid "11d7a6c3-221d-4331-b595-0d9130e005e7") + ) + (fp_line + (start -1.33 1.33) + (end 1.33 1.33) + (stroke + (width 0.12) + (type solid) + ) + (layer "F.SilkS") + (uuid "79e2f484-8526-4235-8ecf-1b6fc52267cb") + ) + (fp_line + (start 1.33 1.27) + (end 1.33 1.33) + (stroke + (width 0.12) + (type solid) + ) + (layer "F.SilkS") + (uuid "8acdf3e9-f57b-4971-921b-addfdd7d3c94") + ) + (fp_line + (start -1.8 -1.8) + (end -1.8 1.8) + (stroke + (width 0.05) + (type solid) + ) + (layer "F.CrtYd") + (uuid "8f0947d6-3894-4eae-bf45-a32c3dc2459d") + ) + (fp_line + (start -1.8 1.8) + (end 1.8 1.8) + (stroke + (width 0.05) + (type solid) + ) + (layer "F.CrtYd") + (uuid "5044617d-a06e-4e10-8542-74d0bf808891") + ) + (fp_line + (start 1.8 -1.8) + (end -1.8 -1.8) + (stroke + (width 0.05) + (type solid) + ) + (layer "F.CrtYd") + (uuid "f85def44-6cb2-4b98-be73-bc1b5313c4b5") + ) + (fp_line + (start 1.8 1.8) + (end 1.8 -1.8) + (stroke + (width 0.05) + (type solid) + ) + (layer "F.CrtYd") + (uuid "5949315c-51f8-4819-b018-03e8f8c7909c") + ) + (fp_line + (start -1.27 -0.635) + (end -0.635 -1.27) + (stroke + (width 0.1) + (type solid) + ) + (layer "F.Fab") + (uuid "adc10770-1723-488c-8232-7f0ad2c7cace") + ) + (fp_line + (start -1.27 1.27) + (end -1.27 -0.635) + (stroke + (width 0.1) + (type solid) + ) + (layer "F.Fab") + (uuid "1e1e093d-57ed-4801-8603-c7acae013741") + ) + (fp_line + (start -0.635 -1.27) + (end 1.27 -1.27) + (stroke + (width 0.1) + (type solid) + ) + (layer "F.Fab") + (uuid "e7d64334-39df-49f8-834e-0ac93da15a5b") + ) + (fp_line + (start 1.27 -1.27) + (end 1.27 1.27) + (stroke + (width 0.1) + (type solid) + ) + (layer "F.Fab") + (uuid "1033fa55-0d33-4394-8b55-78af68f26749") + ) + (fp_line + (start 1.27 1.27) + (end -1.27 1.27) + (stroke + (width 0.1) + (type solid) + ) + (layer "F.Fab") + (uuid "f25c5088-ca29-4940-8a9f-a773d953f951") + ) + (fp_text user "${REFERENCE}" + (at 0 0 90) + (layer "F.Fab") + (uuid "6976de06-a21f-4558-b5c2-96b2fac0f546") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (pad "1" thru_hole rect + (at 0 0) + (size 1.7 1.7) + (drill 1) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (uuid "bf29d5b2-1ed9-48cf-a932-2258e5e431d0") + ) + (model "${KICAD8_3DMODEL_DIR}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x01_P2.54mm_Vertical.wrl" + (offset + (xyz 0 0 0) + ) + (scale + (xyz 1 1 1) + ) + (rotate + (xyz 0 0 0) + ) + ) +) \ No newline at end of file diff --git a/Hardware/MVBMS/Symbol_Library/Micro-Mate-N-Lok.kicad_sym b/Hardware/MVBMS/Symbol_Library/Micro-Mate-N-Lok.kicad_sym new file mode 100644 index 0000000..a42b500 --- /dev/null +++ b/Hardware/MVBMS/Symbol_Library/Micro-Mate-N-Lok.kicad_sym @@ -0,0 +1,5 @@ +(kicad_symbol_lib + (version 20231120) + (generator "kicad_symbol_editor") + (generator_version "8.0") +) \ No newline at end of file diff --git a/Hardware/MVBMS/Symbol_Library/Micro-Mate-N-Lok.pretty/Micro Mate-N-Lok 12-Pol.kicad_mod b/Hardware/MVBMS/Symbol_Library/Micro-Mate-N-Lok.pretty/Micro Mate-N-Lok 12-Pol.kicad_mod new file mode 100644 index 0000000..06740b2 --- /dev/null +++ b/Hardware/MVBMS/Symbol_Library/Micro-Mate-N-Lok.pretty/Micro Mate-N-Lok 12-Pol.kicad_mod @@ -0,0 +1,27 @@ +(module "Micro Mate-N-Lok 12-Pol" (layer F.Cu) (tedit 5CEB259A) + (fp_text reference REF** (at 0 10.96) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value "Micro Mate-N-Lok 12-Pol" (at 0 -10.96) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -0.0013 -6.5659) (end 20.0012 -6.5786) (layer F.CrtYd) (width 0.15)) + (fp_line (start 20.0012 -6.5786) (end 20.0012 4.5339) (layer F.CrtYd) (width 0.15)) + (fp_line (start 20.0012 4.5339) (end -20.0038 4.5212) (layer F.CrtYd) (width 0.15)) + (fp_line (start -20.0038 4.5212) (end -20.0038 -6.6548) (layer F.CrtYd) (width 0.15)) + (fp_line (start -20.0038 -6.6548) (end -0.0013 -6.5659) (layer F.CrtYd) (width 0.15)) + (pad 1 smd rect (at -16.5089 -5.0101) (size 1.27 3) (layers F.Cu F.Paste F.Mask)) + (pad 2 smd rect (at -13.5089 -5.0101) (size 1.27 3) (layers F.Cu F.Paste F.Mask)) + (pad 3 smd rect (at -10.5089 -5.0101) (size 1.27 3) (layers F.Cu F.Paste F.Mask)) + (pad 4 smd rect (at -7.5089 -5.0101) (size 1.27 3) (layers F.Cu F.Paste F.Mask)) + (pad 5 smd rect (at -4.5089 -5.0101) (size 1.27 3) (layers F.Cu F.Paste F.Mask)) + (pad 6 smd rect (at -1.5089 -5.0101) (size 1.27 3) (layers F.Cu F.Paste F.Mask)) + (pad 7 smd rect (at 1.4911 -5.0101) (size 1.27 3) (layers F.Cu F.Paste F.Mask)) + (pad 8 smd rect (at 4.4911 -5.0101) (size 1.27 3) (layers F.Cu F.Paste F.Mask)) + (pad 9 smd rect (at 7.4911 -5.0101) (size 1.27 3) (layers F.Cu F.Paste F.Mask)) + (pad 10 smd rect (at 10.4911 -5.0101) (size 1.27 3) (layers F.Cu F.Paste F.Mask)) + (pad 11 smd rect (at 13.4911 -5.0101) (size 1.27 3) (layers F.Cu F.Paste F.Mask)) + (pad 12 smd rect (at 16.4911 -5.0101) (size 1.27 3) (layers F.Cu F.Paste F.Mask)) + (pad "" smd rect (at -20.1439 0.4699) (size 3.5 1.65) (layers F.Cu F.Paste F.Mask)) + (pad "" smd rect (at 20.2661 0.4699) (size 3.5 1.65) (layers F.Cu F.Paste F.Mask)) +) diff --git a/Hardware/MVBMS/Symbol_Library/Micro-Mate-N-Lok.pretty/Micro Mate-N-Lok 16-Pol.kicad_mod b/Hardware/MVBMS/Symbol_Library/Micro-Mate-N-Lok.pretty/Micro Mate-N-Lok 16-Pol.kicad_mod new file mode 100644 index 0000000..037fc30 --- /dev/null +++ b/Hardware/MVBMS/Symbol_Library/Micro-Mate-N-Lok.pretty/Micro Mate-N-Lok 16-Pol.kicad_mod @@ -0,0 +1,35 @@ +(footprint "Micro Mate-N-Lok 16-Pol" (version 20211014) (generator pcbnew) + (layer "F.Cu") + (tedit 63F4F5FB) + (attr through_hole) + (fp_text reference "REF**" (at 4.5 11.16) (layer "F.SilkS") + (effects (font (size 1 1) (thickness 0.15))) + (tstamp e47744b9-0e80-4f40-97a2-e6c666060a7e) + ) + (fp_text value "Micro Mate-N-Lok 16-Pol" (at 4.6189 -10.6499) (layer "F.Fab") + (effects (font (size 1 1) (thickness 0.15))) + (tstamp e918b919-3275-46f5-9abf-7feb327608c4) + ) + (fp_line (start -14 6.3) (end -14 -6.3) (layer "F.CrtYd") (width 0.15) (tstamp 5af55f91-716b-4e7d-8c75-1fd345b7c35e)) + (fp_line (start -14 -6.3) (end 14.275 -6.3) (layer "F.CrtYd") (width 0.15) (tstamp 771a40f7-19a7-4bfc-b88f-460c1a7e5602)) + (fp_line (start 14.275 6.3) (end -14 6.3) (layer "F.CrtYd") (width 0.15) (tstamp 950756d1-03fe-43a0-95e7-909930c47f2a)) + (fp_line (start 14.275 -6.3) (end 14.275 6.3) (layer "F.CrtYd") (width 0.15) (tstamp ed5e43c2-1b85-442b-b823-35bf1b456dbf)) + (pad "" smd rect (at -14.135 0) (size 3.5 1.65) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 2c1b1998-f439-4485-b7ce-0b13438f40bf)) + (pad "" smd rect (at 14.275 0) (size 3.5 1.65) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 2e00a52e-9c16-45d3-84a5-a06979b617b4)) + (pad "1" smd rect (at -10.5 -4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 77f36f29-ab03-4c19-9c6a-a2d42f26a525)) + (pad "2" smd rect (at -7.5 -4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 2d1dad02-6a1d-46d3-b854-5aa81ab4f8f5)) + (pad "3" smd rect (at -4.5 -4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 01cf62da-95ed-4a12-955e-985e346f552c)) + (pad "4" smd rect (at -1.5 -4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 41c9c3b8-2883-4fdc-b499-17634b4fcf10)) + (pad "5" smd rect (at 1.5 -4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp bc3b55ee-da4a-47e7-827f-dc787b3d7436)) + (pad "6" smd rect (at 4.5 -4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 210b4586-7fb1-453c-a012-150951ba2378)) + (pad "7" smd rect (at 7.5 -4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 07c4c238-6403-4327-b6d6-e3cef522d132)) + (pad "8" smd rect (at 10.5 -4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 516d561c-e210-47a1-b528-cf70e07f88f1)) + (pad "9" smd rect (at 10.5 4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 3064363d-f6c5-452f-a8e1-931c68c1d1c5)) + (pad "10" smd rect (at 7.5 4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp d6a08934-0f05-4531-86f0-e5931f2293f7)) + (pad "11" smd rect (at 4.5 4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp ba884cb2-63bf-4c50-8b66-c3860de5c02e)) + (pad "12" smd rect (at 1.5 4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp fd758cad-e0d7-4141-bc52-0b1a72d4a012)) + (pad "13" smd rect (at -1.5 4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 3d65096b-2ccd-4f03-afa3-bd1be62a8c57)) + (pad "14" smd rect (at -4.5 4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 9ef1878b-d9e0-40a1-8a39-790b6c7302c6)) + (pad "15" smd rect (at -7.5 4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 3c048d02-8b0a-4f38-b4ad-44dab638b480)) + (pad "16" smd rect (at -10.5 4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 63ec8a7f-f3b0-4fe7-af1e-8a11758001d1)) +) diff --git a/Hardware/MVBMS/Symbol_Library/Micro-Mate-N-Lok.pretty/Micro Mate-N-Lok 2-Pol.kicad_mod b/Hardware/MVBMS/Symbol_Library/Micro-Mate-N-Lok.pretty/Micro Mate-N-Lok 2-Pol.kicad_mod new file mode 100644 index 0000000..8e17e1d --- /dev/null +++ b/Hardware/MVBMS/Symbol_Library/Micro-Mate-N-Lok.pretty/Micro Mate-N-Lok 2-Pol.kicad_mod @@ -0,0 +1,17 @@ +(module "Micro Mate-N-Lok 2-Pol" (layer F.Cu) (tedit 5CE9F075) + (fp_text reference REF** (at 0 7.6) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value "Micro Mate-N-Lok 2-Pol" (at 0 -6.22) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 0 -5.4) (end 5 -5.4) (layer F.CrtYd) (width 0.15)) + (fp_line (start 5 -5.4) (end 5 6.2) (layer F.CrtYd) (width 0.15)) + (fp_line (start 5 6.2) (end -5 6.2) (layer F.CrtYd) (width 0.15)) + (fp_line (start -5 6.2) (end -5 -5.4) (layer F.CrtYd) (width 0.15)) + (fp_line (start -5 -5.4) (end 0 -5.4) (layer F.CrtYd) (width 0.15)) + (pad 1 smd rect (at -1.5 -3.88) (size 1.27 3) (layers F.Cu F.Paste F.Mask)) + (pad 2 smd rect (at 1.5 -3.88) (size 1.27 3) (layers F.Cu F.Paste F.Mask)) + (pad "" smd rect (at -5.2 1.6) (size 3.43 1.65) (layers F.Cu F.Paste F.Mask)) + (pad "" smd rect (at 5.21 1.6) (size 3.43 1.65) (layers F.Cu F.Paste F.Mask)) +) diff --git a/Hardware/MVBMS/Symbol_Library/Micro-Mate-N-Lok.pretty/Micro Mate-N-Lok 22-Pol.kicad_mod b/Hardware/MVBMS/Symbol_Library/Micro-Mate-N-Lok.pretty/Micro Mate-N-Lok 22-Pol.kicad_mod new file mode 100644 index 0000000..fdb7142 --- /dev/null +++ b/Hardware/MVBMS/Symbol_Library/Micro-Mate-N-Lok.pretty/Micro Mate-N-Lok 22-Pol.kicad_mod @@ -0,0 +1,41 @@ +(footprint "Micro Mate-N-Lok 22-Pol" (version 20211014) (generator pcbnew) + (layer "F.Cu") + (tedit 627FA53E) + (attr through_hole) + (fp_text reference "REF**" (at 0 11.16) (layer "F.SilkS") + (effects (font (size 1 1) (thickness 0.15))) + (tstamp e47744b9-0e80-4f40-97a2-e6c666060a7e) + ) + (fp_text value "Micro Mate-N-Lok 22-Pol" (at 0.1189 -10.6499) (layer "F.Fab") + (effects (font (size 1 1) (thickness 0.15))) + (tstamp e918b919-3275-46f5-9abf-7feb327608c4) + ) + (fp_line (start -18.5 6.3) (end -18.5 -6.3) (layer "F.CrtYd") (width 0.15) (tstamp 5af55f91-716b-4e7d-8c75-1fd345b7c35e)) + (fp_line (start -18.5 -6.3) (end 18.5 -6.3) (layer "F.CrtYd") (width 0.15) (tstamp 771a40f7-19a7-4bfc-b88f-460c1a7e5602)) + (fp_line (start 18.5 6.3) (end -18.5 6.3) (layer "F.CrtYd") (width 0.15) (tstamp 950756d1-03fe-43a0-95e7-909930c47f2a)) + (fp_line (start 18.5 -6.3) (end 18.5 6.3) (layer "F.CrtYd") (width 0.15) (tstamp ed5e43c2-1b85-442b-b823-35bf1b456dbf)) + (pad "" smd rect (at -18.635 0) (size 3.5 1.65) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 2c1b1998-f439-4485-b7ce-0b13438f40bf)) + (pad "" smd rect (at 18.775 0) (size 3.5 1.65) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 2e00a52e-9c16-45d3-84a5-a06979b617b4)) + (pad "1" smd rect (at -15 -4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 77f36f29-ab03-4c19-9c6a-a2d42f26a525)) + (pad "2" smd rect (at -12 -4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 2d1dad02-6a1d-46d3-b854-5aa81ab4f8f5)) + (pad "3" smd rect (at -9 -4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 01cf62da-95ed-4a12-955e-985e346f552c)) + (pad "4" smd rect (at -6 -4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 41c9c3b8-2883-4fdc-b499-17634b4fcf10)) + (pad "5" smd rect (at -3 -4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp bc3b55ee-da4a-47e7-827f-dc787b3d7436)) + (pad "6" smd rect (at 0 -4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 210b4586-7fb1-453c-a012-150951ba2378)) + (pad "7" smd rect (at 3 -4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 07c4c238-6403-4327-b6d6-e3cef522d132)) + (pad "8" smd rect (at 6 -4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 516d561c-e210-47a1-b528-cf70e07f88f1)) + (pad "9" smd rect (at 9 -4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 0dac2fad-51ba-45c3-9ce2-db75253acc13)) + (pad "10" smd rect (at 12 -4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 95513a05-1ba8-4d8a-991b-c2b0dc386b34)) + (pad "11" smd rect (at 15 -4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 5cf2293a-aff5-41a8-84ef-ba37fb1d0a5f)) + (pad "12" smd rect (at 15 4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp e044fd7a-13ed-4916-9f2e-12e374f299f7)) + (pad "13" smd rect (at 12 4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp e0ce8632-f9df-46d0-a7b2-e7c8b1d6e07e)) + (pad "14" smd rect (at 9 4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp b0ad5a41-9a6a-4aba-a998-46cfb89c30f2)) + (pad "15" smd rect (at 6 4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 3064363d-f6c5-452f-a8e1-931c68c1d1c5)) + (pad "16" smd rect (at 3 4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp d6a08934-0f05-4531-86f0-e5931f2293f7)) + (pad "17" smd rect (at 0 4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp ba884cb2-63bf-4c50-8b66-c3860de5c02e)) + (pad "18" smd rect (at -3 4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp fd758cad-e0d7-4141-bc52-0b1a72d4a012)) + (pad "19" smd rect (at -6 4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 3d65096b-2ccd-4f03-afa3-bd1be62a8c57)) + (pad "20" smd rect (at -9 4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 9ef1878b-d9e0-40a1-8a39-790b6c7302c6)) + (pad "21" smd rect (at -12 4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 3c048d02-8b0a-4f38-b4ad-44dab638b480)) + (pad "22" smd rect (at -15 4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 63ec8a7f-f3b0-4fe7-af1e-8a11758001d1)) +) diff --git a/Hardware/MVBMS/Symbol_Library/Micro-Mate-N-Lok.pretty/Micro Mate-N-Lok 4-Pol.kicad_mod b/Hardware/MVBMS/Symbol_Library/Micro-Mate-N-Lok.pretty/Micro Mate-N-Lok 4-Pol.kicad_mod new file mode 100644 index 0000000..600e2d2 --- /dev/null +++ b/Hardware/MVBMS/Symbol_Library/Micro-Mate-N-Lok.pretty/Micro Mate-N-Lok 4-Pol.kicad_mod @@ -0,0 +1,19 @@ +(module "Micro Mate-N-Lok 4-Pol" (layer F.Cu) (tedit 5CE9F407) + (fp_text reference REF** (at 0 6) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value "Micro Mate-N-Lok 4-Pol" (at 0 -8) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 0 -6.6) (end 8 -6.6) (layer F.CrtYd) (width 0.15)) + (fp_line (start 8 -6.6) (end 8 4.6) (layer F.CrtYd) (width 0.15)) + (fp_line (start 8 4.6) (end -8 4.6) (layer F.CrtYd) (width 0.15)) + (fp_line (start -8 4.6) (end -8 -6.6) (layer F.CrtYd) (width 0.15)) + (fp_line (start -8 -6.6) (end 0 -6.6) (layer F.CrtYd) (width 0.15)) + (pad "" smd rect (at -8.2 0.4) (size 3.43 1.65) (layers F.Cu F.Paste F.Mask)) + (pad 4 smd rect (at 4.5 -5.08) (size 1.27 3) (layers F.Cu F.Paste F.Mask)) + (pad 3 smd rect (at 1.5 -5.08) (size 1.27 3) (layers F.Cu F.Paste F.Mask)) + (pad 2 smd rect (at -1.5 -5.08) (size 1.27 3) (layers F.Cu F.Paste F.Mask)) + (pad 1 smd rect (at -4.5 -5.08) (size 1.27 3) (layers F.Cu F.Paste F.Mask)) + (pad "" smd rect (at 8.21 0.4) (size 3.43 1.65) (layers F.Cu F.Paste F.Mask)) +) diff --git a/Hardware/MVBMS/Symbol_Library/Micro-Mate-N-Lok.pretty/Micro Mate-N-Lok 6-Pol.kicad_mod b/Hardware/MVBMS/Symbol_Library/Micro-Mate-N-Lok.pretty/Micro Mate-N-Lok 6-Pol.kicad_mod new file mode 100644 index 0000000..9cf90d3 --- /dev/null +++ b/Hardware/MVBMS/Symbol_Library/Micro-Mate-N-Lok.pretty/Micro Mate-N-Lok 6-Pol.kicad_mod @@ -0,0 +1,21 @@ +(module "Micro Mate-N-Lok 6-Pol" (layer F.Cu) (tedit 5CEB202F) + (fp_text reference REF** (at -0.005 8.09) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value "Micro Mate-N-Lok 6-Pol" (at 0.005 -6.04) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 0.005 -4.51) (end 11.005 -4.51) (layer F.CrtYd) (width 0.15)) + (fp_line (start 11.005 -4.51) (end 11.005 6.61) (layer F.CrtYd) (width 0.15)) + (fp_line (start 11.005 6.61) (end -11.005 6.6) (layer F.CrtYd) (width 0.15)) + (fp_line (start -11.005 6.6) (end -11.005 -4.51) (layer F.CrtYd) (width 0.15)) + (fp_line (start -11.005 -4.51) (end 0.045 -4.51) (layer F.CrtYd) (width 0.15)) + (pad 1 smd rect (at -7.5 -2.98) (size 1.27 3) (layers F.Cu F.Paste F.Mask)) + (pad 2 smd rect (at -4.5 -2.98) (size 1.27 3) (layers F.Cu F.Paste F.Mask)) + (pad 3 smd rect (at -1.5 -2.98) (size 1.27 3) (layers F.Cu F.Paste F.Mask)) + (pad 4 smd rect (at 1.5 -2.98) (size 1.27 3) (layers F.Cu F.Paste F.Mask)) + (pad 5 smd rect (at 4.5 -2.98) (size 1.27 3) (layers F.Cu F.Paste F.Mask)) + (pad 6 smd rect (at 7.5 -2.98) (size 1.27 3) (layers F.Cu F.Paste F.Mask)) + (pad "" smd rect (at -11.135 2.5) (size 3.5 1.65) (layers F.Cu F.Paste F.Mask)) + (pad "" smd rect (at 11.275 2.5) (size 3.5 1.65) (layers F.Cu F.Paste F.Mask)) +) diff --git a/Hardware/MVBMS/Symbol_Library/Micro-Mate-N-Lok.pretty/Micro Mate-N-Lok-12pin-2row.kicad_mod b/Hardware/MVBMS/Symbol_Library/Micro-Mate-N-Lok.pretty/Micro Mate-N-Lok-12pin-2row.kicad_mod new file mode 100644 index 0000000..22fb7bc --- /dev/null +++ b/Hardware/MVBMS/Symbol_Library/Micro-Mate-N-Lok.pretty/Micro Mate-N-Lok-12pin-2row.kicad_mod @@ -0,0 +1,31 @@ +(footprint "Micro Mate-N-Lok-12pin-2row" (version 20211014) (generator pcbnew) + (layer "F.Cu") + (tedit 628F8DAD) + (attr through_hole) + (fp_text reference "REF**" (at 0 11.16) (layer "F.SilkS") + (effects (font (size 1 1) (thickness 0.15))) + (tstamp e47744b9-0e80-4f40-97a2-e6c666060a7e) + ) + (fp_text value "Micro Mate-N-Lok-12pin-2row" (at 1.6189 -10.6499) (layer "F.Fab") + (effects (font (size 1 1) (thickness 0.15))) + (tstamp e918b919-3275-46f5-9abf-7feb327608c4) + ) + (fp_line (start -11 6.3) (end -11 -6.3) (layer "F.CrtYd") (width 0.15) (tstamp 5af55f91-716b-4e7d-8c75-1fd345b7c35e)) + (fp_line (start -11 -6.3) (end 11 -6.3) (layer "F.CrtYd") (width 0.15) (tstamp 771a40f7-19a7-4bfc-b88f-460c1a7e5602)) + (fp_line (start 11 6.3) (end -11 6.3) (layer "F.CrtYd") (width 0.15) (tstamp 950756d1-03fe-43a0-95e7-909930c47f2a)) + (fp_line (start 11 -6.3) (end 11 6.3) (layer "F.CrtYd") (width 0.15) (tstamp ed5e43c2-1b85-442b-b823-35bf1b456dbf)) + (pad "" smd rect (at -11.135 0) (size 3.5 1.65) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 2c1b1998-f439-4485-b7ce-0b13438f40bf)) + (pad "" smd rect (at 11.275 0) (size 3.5 1.65) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 2e00a52e-9c16-45d3-84a5-a06979b617b4)) + (pad "1" smd rect (at -7.5 -4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 77f36f29-ab03-4c19-9c6a-a2d42f26a525)) + (pad "2" smd rect (at -4.5 -4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 2d1dad02-6a1d-46d3-b854-5aa81ab4f8f5)) + (pad "3" smd rect (at -1.5 -4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 01cf62da-95ed-4a12-955e-985e346f552c)) + (pad "4" smd rect (at 1.5 -4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 41c9c3b8-2883-4fdc-b499-17634b4fcf10)) + (pad "5" smd rect (at 4.5 -4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp bc3b55ee-da4a-47e7-827f-dc787b3d7436)) + (pad "6" smd rect (at 7.5 -4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 210b4586-7fb1-453c-a012-150951ba2378)) + (pad "7" smd rect (at 7.5 4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp ba884cb2-63bf-4c50-8b66-c3860de5c02e)) + (pad "8" smd rect (at 4.5 4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp fd758cad-e0d7-4141-bc52-0b1a72d4a012)) + (pad "9" smd rect (at 1.5 4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 3d65096b-2ccd-4f03-afa3-bd1be62a8c57)) + (pad "10" smd rect (at -1.5 4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 9ef1878b-d9e0-40a1-8a39-790b6c7302c6)) + (pad "11" smd rect (at -4.5 4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 3c048d02-8b0a-4f38-b4ad-44dab638b480)) + (pad "12" smd rect (at -7.5 4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 63ec8a7f-f3b0-4fe7-af1e-8a11758001d1)) +) diff --git a/Hardware/MVBMS/Symbol_Library/Micro-Mate-N-Lok.pretty/Micro-Mate-N-Lok-16pin-2row.kicad_mod b/Hardware/MVBMS/Symbol_Library/Micro-Mate-N-Lok.pretty/Micro-Mate-N-Lok-16pin-2row.kicad_mod new file mode 100644 index 0000000..0034cd5 --- /dev/null +++ b/Hardware/MVBMS/Symbol_Library/Micro-Mate-N-Lok.pretty/Micro-Mate-N-Lok-16pin-2row.kicad_mod @@ -0,0 +1,35 @@ +(module Micro-Mate-N-Lok-16pin-2row (layer F.Cu) (tedit 5D12244A) + (fp_text reference REF** (at 0 -5.6) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value Micro-Mate-N-Lok-16pin-2row (at 0 10.3) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 13.5 0) (end 13.5 9) (layer F.CrtYd) (width 0.15)) + (fp_line (start -13.5 0) (end -13.5 9) (layer F.CrtYd) (width 0.15)) + (fp_line (start -13.5 9) (end 13.5 9) (layer F.CrtYd) (width 0.15)) + (fp_line (start -13.5 0) (end -13.5 -4) (layer F.CrtYd) (width 0.15)) + (fp_line (start -13.5 -4) (end 13.5 -4) (layer F.CrtYd) (width 0.15)) + (fp_line (start 13.5 -4) (end 13.5 0.2) (layer F.CrtYd) (width 0.15)) + (fp_line (start -13.7 0.4) (end -13.7 -4.2) (layer F.SilkS) (width 0.15)) + (fp_line (start -13.7 -4.2) (end 13.7 -4.2) (layer F.SilkS) (width 0.15)) + (fp_line (start 13.7 -4.2) (end 13.7 0.4) (layer F.SilkS) (width 0.15)) + (pad 1 thru_hole circle (at -10.5 0) (size 1.8 1.8) (drill 1.02) (layers *.Cu *.Mask)) + (pad 2 thru_hole circle (at -7.5 0) (size 1.8 1.8) (drill 1.02) (layers *.Cu *.Mask)) + (pad 3 thru_hole circle (at -4.5 0) (size 1.8 1.8) (drill 1.02) (layers *.Cu *.Mask)) + (pad 4 thru_hole circle (at -1.5 0) (size 1.8 1.8) (drill 1.02) (layers *.Cu *.Mask)) + (pad 5 thru_hole circle (at 1.5 0) (size 1.8 1.8) (drill 1.02) (layers *.Cu *.Mask)) + (pad 6 thru_hole circle (at 4.5 0) (size 1.8 1.8) (drill 1.02) (layers *.Cu *.Mask)) + (pad 7 thru_hole circle (at 7.5 0) (size 1.8 1.8) (drill 1.02) (layers *.Cu *.Mask)) + (pad 8 thru_hole circle (at 10.5 0) (size 1.8 1.8) (drill 1.02) (layers *.Cu *.Mask)) + (pad 9 thru_hole circle (at 10.5 -3) (size 1.8 1.8) (drill 1.02) (layers *.Cu *.Mask)) + (pad 10 thru_hole circle (at 7.5 -3) (size 1.8 1.8) (drill 1.02) (layers *.Cu *.Mask)) + (pad 11 thru_hole circle (at 4.5 -3) (size 1.8 1.8) (drill 1.02) (layers *.Cu *.Mask)) + (pad 12 thru_hole circle (at 1.5 -3) (size 1.8 1.8) (drill 1.02) (layers *.Cu *.Mask)) + (pad 13 thru_hole circle (at -1.5 -3) (size 1.8 1.8) (drill 1.02) (layers *.Cu *.Mask)) + (pad 14 thru_hole circle (at -4.5 -3) (size 1.8 1.8) (drill 1.02) (layers *.Cu *.Mask)) + (pad 15 thru_hole circle (at -7.5 -3) (size 1.8 1.8) (drill 1.02) (layers *.Cu *.Mask)) + (pad 16 thru_hole circle (at -10.5 -3) (size 1.8 1.8) (drill 1.02) (layers *.Cu *.Mask)) + (pad "" np_thru_hole circle (at -8.34 4.32) (size 3 3) (drill 3) (layers *.Cu *.Mask)) + (pad "" np_thru_hole circle (at 8.34 4.32) (size 3 3) (drill 3) (layers *.Cu *.Mask)) +) diff --git a/Hardware/MVBMS/bom/ibom.html b/Hardware/MVBMS/bom/ibom.html new file mode 100644 index 0000000..1248e7f --- /dev/null +++ b/Hardware/MVBMS/bom/ibom.html @@ -0,0 +1,4669 @@ + + + + + + + Interactive BOM for KiCAD + + + + + + +
+
+
+ + + + + + + + + + + +
+ Title + + Revision +
+ Company + + Date +
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Board statsFrontBackTotal
Components~~~
Groups~~~
SMD pads~~~
TH pads~
+ + + + + + + +
Checkboxes
+
+
+
+ +
+
+
Save board image
+
+ + X + +
+ +
+ + +
+
+
+ Config and checkbox state +
+ + + +
+
+
+ Save bom table as +
+ + +
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︽
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+
+ + + + diff --git a/Hardware/MVBMS/fp-lib-table b/Hardware/MVBMS/fp-lib-table new file mode 100644 index 0000000..f81d111 --- /dev/null +++ b/Hardware/MVBMS/fp-lib-table @@ -0,0 +1,10 @@ +(fp_lib_table + (version 7) + (lib (name "FaSTTUBe_logos")(type "KiCad")(uri "${KIPRJMOD}/Symbol_Library/FaSTTUBe_logos.pretty")(options "")(descr "")) + (lib (name "FaSTTUBe_connectors_3dmodels")(type "KiCad")(uri "${KIPRJMOD}/Symbol_Library/FaSTTUBe_connectors_3dmodels")(options "")(descr "")) + (lib (name "FaSTTUBe_connectors")(type "KiCad")(uri "${KIPRJMOD}/Symbol_Library/FaSTTUBe_connectors.pretty")(options "")(descr "")) + (lib (name "LED_150080M153000")(type "KiCad")(uri "${KIPRJMOD}/Symbol_Library/LED_150080M153000")(options "")(descr "")) + (lib (name "Micro-Mate-N-Lok")(type "KiCad")(uri "${KIPRJMOD}/Symbol_Library/Micro-Mate-N-Lok.pretty")(options "")(descr "")) + (lib (name "ADBMS6830")(type "KiCad")(uri "${KIPRJMOD}/Symbol_Library/ADBMS6830.pretty")(options "")(descr "")) + (lib (name "MVBMS")(type "KiCad")(uri "${KIPRJMOD}/Symbol_Library/MVBMS.pretty")(options "")(descr "")) +) diff --git a/Hardware/MVBMS/sym-lib-table b/Hardware/MVBMS/sym-lib-table new file mode 100644 index 0000000..5779bae --- /dev/null +++ b/Hardware/MVBMS/sym-lib-table @@ -0,0 +1,9 @@ +(sym_lib_table + (version 7) + (lib (name "ADBMS6830B")(type "KiCad")(uri "${KIPRJMOD}/Symbol_Library/ADBMS6830B.kicad_sym")(options "")(descr "")) + (lib (name "FaSTTUBe_connectors")(type "KiCad")(uri "${KIPRJMOD}/Symbol_Library/FaSTTUBe_connectors.kicad_sym")(options "")(descr "")) + (lib (name "MVBMS")(type "KiCad")(uri "${KIPRJMOD}/Symbol_Library/MVBMS.kicad_sym")(options "")(descr "")) + (lib (name "Miro-Mate-N-Lok ")(type "KiCad")(uri "${KIPRJMOD}/Symbol_Library/Miro-Mate-N-Lok .kicad_sym")(options "")(descr "")) + (lib (name "MVBMS.kicad_sym")(type "KiCad")(uri "${KIPRJMOD}/Symbol_Library/MVBMS.kicad_sym.kicad_sym")(options "")(descr "")) + (lib (name "m24m01e-fmn6tp")(type "KiCad")(uri "${KIPRJMOD}/Symbol_Library/MVBMS.pretty/m24m01e-fmn6tp.kicad_sym")(options "")(descr "")) +) diff --git a/Hardware/MV_Abnehmerplatine/FT24_MV_Abnehmer_V1.zip b/Hardware/MV_Abnehmerplatine/FT24_MV_Abnehmer_V1.zip new file mode 100644 index 0000000..d6e000f Binary files /dev/null and b/Hardware/MV_Abnehmerplatine/FT24_MV_Abnehmer_V1.zip differ diff --git a/Hardware/MV_Abnehmerplatine/FT24_MV_Abnehmer_V1/MV_Abnehmerplatine-B_Cu.gbr b/Hardware/MV_Abnehmerplatine/FT24_MV_Abnehmer_V1/MV_Abnehmerplatine-B_Cu.gbr new file mode 100644 index 0000000..2b5b419 --- /dev/null +++ b/Hardware/MV_Abnehmerplatine/FT24_MV_Abnehmer_V1/MV_Abnehmerplatine-B_Cu.gbr @@ -0,0 +1,6965 @@ +%TF.GenerationSoftware,KiCad,Pcbnew,8.0.2*% +%TF.CreationDate,2024-06-27T20:36:25+03:00*% +%TF.ProjectId,MV_Abnehmerplatine,4d565f41-626e-4656-986d-6572706c6174,rev?*% +%TF.SameCoordinates,Original*% +%TF.FileFunction,Copper,L2,Bot*% +%TF.FilePolarity,Positive*% +%FSLAX46Y46*% +G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* +G04 Created by KiCad (PCBNEW 8.0.2) date 2024-06-27 20:36:25* +%MOMM*% +%LPD*% +G01* +G04 APERTURE LIST* +G04 Aperture macros list* +%AMRoundRect* +0 Rectangle with rounded corners* +0 $1 Rounding radius* +0 $2 $3 $4 $5 $6 $7 $8 $9 X,Y pos of 4 corners* +0 Add a 4 corners polygon primitive as box body* +4,1,4,$2,$3,$4,$5,$6,$7,$8,$9,$2,$3,0* +0 Add four circle primitives for the rounded corners* +1,1,$1+$1,$2,$3* +1,1,$1+$1,$4,$5* +1,1,$1+$1,$6,$7* +1,1,$1+$1,$8,$9* +0 Add four rect primitives between the rounded corners* +20,1,$1+$1,$2,$3,$4,$5,0* +20,1,$1+$1,$4,$5,$6,$7,0* +20,1,$1+$1,$6,$7,$8,$9,0* +20,1,$1+$1,$8,$9,$2,$3,0*% +G04 Aperture macros list end* +%TA.AperFunction,SMDPad,CuDef*% +%ADD10RoundRect,0.062500X0.187500X0.062500X-0.187500X0.062500X-0.187500X-0.062500X0.187500X-0.062500X0*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD11C,0.600000*% +%TD*% +%TA.AperFunction,SMDPad,CuDef*% +%ADD12R,0.900000X1.600000*% +%TD*% +%TA.AperFunction,ComponentPad*% +%ADD13C,3.000000*% +%TD*% +%TA.AperFunction,SMDPad,CuDef*% +%ADD14R,0.550000X1.300000*% +%TD*% +%TA.AperFunction,SMDPad,CuDef*% +%ADD15R,0.550000X1.400000*% +%TD*% +%TA.AperFunction,ViaPad*% +%ADD16C,0.800000*% +%TD*% +%TA.AperFunction,Conductor*% +%ADD17C,0.250000*% +%TD*% +%TA.AperFunction,Conductor*% +%ADD18C,1.000000*% +%TD*% +G04 APERTURE END LIST* +D10* +%TO.P,U7,1,SDA*% +%TO.N,/SDA*% +X159440000Y-90610000D03* +%TO.P,U7,2,SCL*% +%TO.N,/SCL*% +X159440000Y-91110000D03* +%TO.P,U7,3,ALERT*% +%TO.N,unconnected-(U7-ALERT-Pad3)*% +X159440000Y-91610000D03* +%TO.P,U7,4,GND*% +%TO.N,GND*% +X159440000Y-92110000D03* +%TO.P,U7,5,A2*% +%TO.N,+3V3*% +X157540000Y-92110000D03* +%TO.P,U7,6,A1*% +X157540000Y-91610000D03* +%TO.P,U7,7,A0*% +%TO.N,/SCL*% +X157540000Y-91110000D03* +%TO.P,U7,8,V+*% +%TO.N,+3V3*% +X157540000Y-90610000D03* +D11* +%TO.P,U7,9,EP*% +%TO.N,GND*% +X158490000Y-91860000D03* +D12* +X158490000Y-91360000D03* +D11* +X158490000Y-90860000D03* +%TD*% +D13* +%TO.P,H8,1,1*% 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+%TO.P,J0,14,Pin_14*% +%TO.N,Net-(J0-Pin_14)*% +X147410000Y-73995000D03* +D14* +%TO.P,J0,15,Pin_15*% +%TO.N,Net-(J0-Pin_15)*% +X146610000Y-78545000D03* +D15* +%TO.P,J0,16,Pin_16*% +%TO.N,Net-(J0-Pin_16)*% +X146610000Y-73995000D03* +D14* +%TO.P,J0,17,Pin_17*% +%TO.N,Net-(J0-Pin_17)*% +X145810000Y-78545000D03* +D15* +%TO.P,J0,18,Pin_18*% +%TO.N,Net-(J0-Pin_18)*% +X145810000Y-73995000D03* +D14* +%TO.P,J0,19,Pin_19*% +%TO.N,Net-(J0-Pin_19)*% +X145010000Y-78545000D03* +D15* +%TO.P,J0,20,Pin_20*% +%TO.N,Net-(J0-Pin_20)*% +X145010000Y-73995000D03* +%TD*% +D10* +%TO.P,U4,1,SDA*% +%TO.N,/SDA*% +X119840000Y-90610000D03* +%TO.P,U4,2,SCL*% +%TO.N,/SCL*% +X119840000Y-91110000D03* +%TO.P,U4,3,ALERT*% +%TO.N,unconnected-(U4-ALERT-Pad3)*% +X119840000Y-91610000D03* +%TO.P,U4,4,GND*% +%TO.N,GND*% +X119840000Y-92110000D03* +%TO.P,U4,5,A2*% +%TO.N,+3V3*% +X117940000Y-92110000D03* +%TO.P,U4,6,A1*% +%TO.N,GND*% +X117940000Y-91610000D03* +%TO.P,U4,7,A0*% +%TO.N,/SDA*% +X117940000Y-91110000D03* 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b/Hardware/MV_Abnehmerplatine/FT24_MV_Abnehmer_V1/MV_Abnehmerplatine-B_Mask.gbr new file mode 100644 index 0000000..7a9520f --- /dev/null +++ b/Hardware/MV_Abnehmerplatine/FT24_MV_Abnehmer_V1/MV_Abnehmerplatine-B_Mask.gbr @@ -0,0 +1,299 @@ +%TF.GenerationSoftware,KiCad,Pcbnew,8.0.2*% +%TF.CreationDate,2024-06-27T20:36:25+03:00*% +%TF.ProjectId,MV_Abnehmerplatine,4d565f41-626e-4656-986d-6572706c6174,rev?*% +%TF.SameCoordinates,Original*% +%TF.FileFunction,Soldermask,Bot*% +%TF.FilePolarity,Negative*% +%FSLAX46Y46*% +G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* +G04 Created by KiCad (PCBNEW 8.0.2) date 2024-06-27 20:36:25* +%MOMM*% +%LPD*% +G01* +G04 APERTURE LIST* +G04 Aperture macros list* +%AMRoundRect* +0 Rectangle with rounded corners* +0 $1 Rounding radius* +0 $2 $3 $4 $5 $6 $7 $8 $9 X,Y pos of 4 corners* +0 Add a 4 corners polygon primitive as box body* +4,1,4,$2,$3,$4,$5,$6,$7,$8,$9,$2,$3,0* +0 Add four circle primitives for the rounded corners* +1,1,$1+$1,$2,$3* +1,1,$1+$1,$4,$5* +1,1,$1+$1,$6,$7* +1,1,$1+$1,$8,$9* +0 Add four rect primitives between the rounded corners* +20,1,$1+$1,$2,$3,$4,$5,0* +20,1,$1+$1,$4,$5,$6,$7,0* +20,1,$1+$1,$6,$7,$8,$9,0* +20,1,$1+$1,$8,$9,$2,$3,0*% +G04 Aperture macros list end* +%ADD10RoundRect,0.062500X0.187500X0.062500X-0.187500X0.062500X-0.187500X-0.062500X0.187500X-0.062500X0*% +%ADD11R,0.900000X1.600000*% +%ADD12C,3.000000*% +%ADD13R,0.550000X1.300000*% +%ADD14R,0.550000X1.400000*% +G04 APERTURE END LIST* +D10* +%TO.C,U7*% +X159440000Y-90610000D03* +X159440000Y-91110000D03* +X159440000Y-91610000D03* +X159440000Y-92110000D03* +X157540000Y-92110000D03* +X157540000Y-91610000D03* +X157540000Y-91110000D03* +X157540000Y-90610000D03* +D11* +X158490000Y-91360000D03* +%TD*% +D12* +%TO.C,H8*% +X170690002Y-104015000D03* +%TD*% +D10* +%TO.C,U3*% +X106640000Y-90610000D03* +X106640000Y-91110000D03* +X106640000Y-91610000D03* +X106640000Y-92110000D03* +X104740000Y-92110000D03* +X104740000Y-91610000D03* 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+X67040000Y-91610000D03* +X67040000Y-92110000D03* +X65140000Y-92110000D03* +X65140000Y-91610000D03* +X65140000Y-91110000D03* +X65140000Y-90610000D03* +D11* +X66090000Y-91360000D03* +%TD*% +D12* +%TO.C,H7*% +X157490002Y-104015000D03* +%TD*% +%TO.C,H5*% +X131090002Y-104021000D03* +%TD*% +%TO.C,H6*% +X144290002Y-104015000D03* +%TD*% +M02* diff --git a/Hardware/MV_Abnehmerplatine/FT24_MV_Abnehmer_V1/MV_Abnehmerplatine-B_Paste.gbr b/Hardware/MV_Abnehmerplatine/FT24_MV_Abnehmer_V1/MV_Abnehmerplatine-B_Paste.gbr new file mode 100644 index 0000000..53a8315 --- /dev/null +++ b/Hardware/MV_Abnehmerplatine/FT24_MV_Abnehmer_V1/MV_Abnehmerplatine-B_Paste.gbr @@ -0,0 +1,261 @@ +%TF.GenerationSoftware,KiCad,Pcbnew,8.0.2*% +%TF.CreationDate,2024-06-27T20:36:25+03:00*% +%TF.ProjectId,MV_Abnehmerplatine,4d565f41-626e-4656-986d-6572706c6174,rev?*% +%TF.SameCoordinates,Original*% +%TF.FileFunction,Paste,Bot*% +%TF.FilePolarity,Positive*% +%FSLAX46Y46*% +G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* +G04 Created by KiCad (PCBNEW 8.0.2) date 2024-06-27 20:36:25* +%MOMM*% +%LPD*% +G01* +G04 APERTURE LIST* +G04 Aperture macros list* +%AMRoundRect* +0 Rectangle with rounded corners* +0 $1 Rounding radius* +0 $2 $3 $4 $5 $6 $7 $8 $9 X,Y pos of 4 corners* +0 Add a 4 corners polygon primitive as box body* +4,1,4,$2,$3,$4,$5,$6,$7,$8,$9,$2,$3,0* +0 Add four circle primitives for the rounded corners* +1,1,$1+$1,$2,$3* +1,1,$1+$1,$4,$5* +1,1,$1+$1,$6,$7* +1,1,$1+$1,$8,$9* +0 Add four rect primitives between the rounded corners* +20,1,$1+$1,$2,$3,$4,$5,0* +20,1,$1+$1,$4,$5,$6,$7,0* +20,1,$1+$1,$6,$7,$8,$9,0* +20,1,$1+$1,$8,$9,$2,$3,0*% +G04 Aperture macros list end* +%ADD10R,0.750000X0.650000*% +%ADD11RoundRect,0.062500X0.187500X0.062500X-0.187500X0.062500X-0.187500X-0.062500X0.187500X-0.062500X0*% +%ADD12R,0.550000X1.300000*% +%ADD13R,0.550000X1.400000*% +G04 APERTURE END LIST* +D10* +%TO.C,U7*% +X158490000Y-91760000D03* +X158490000Y-90960000D03* +D11* +X159440000Y-90610000D03* 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+X78779079Y-100665000D01* +X78787352Y-100668427D01* +G37* +%TD.AperFunction*% +%TD*% +%TA.AperFunction,Conductor*% +%TO.N,Net-(J0-Pin_12)*% +G36* +X131586967Y-99524427D02* +G01* +X131590387Y-99532302D01* +X131624936Y-100546882D01* +X131624937Y-100546892D01* +X131731872Y-101269218D01* +X131913988Y-101882208D01* +X131914005Y-101882258D01* +X132174451Y-102580088D01* +X132174533Y-102580313D01* +X132512635Y-103546186D01* +X132512134Y-103555127D01* +X132505458Y-103561095D01* +X132505215Y-103561177D01* +X131093625Y-104020820D01* +X131086379Y-104020820D01* +X129674788Y-103561177D01* +X129667983Y-103555357D01* +X129667286Y-103546429D01* +X129667349Y-103546239D01* +X130005475Y-102580295D01* +X130005551Y-102580088D01* +X130265996Y-101882258D01* +X130266006Y-101882232D01* +X130448132Y-101269212D01* +X130555066Y-100546892D01* +X130589617Y-99532301D01* +X130593323Y-99524150D01* +X130601310Y-99521000D01* +X131578694Y-99521000D01* +X131586967Y-99524427D01* +G37* +%TD.AperFunction*% +%TD*% +M02* diff --git a/Hardware/MV_Abnehmerplatine/FT24_MV_Abnehmer_V1/MV_Abnehmerplatine-F_Mask.gbr b/Hardware/MV_Abnehmerplatine/FT24_MV_Abnehmer_V1/MV_Abnehmerplatine-F_Mask.gbr new file mode 100644 index 0000000..ee2a11e --- /dev/null +++ b/Hardware/MV_Abnehmerplatine/FT24_MV_Abnehmer_V1/MV_Abnehmerplatine-F_Mask.gbr @@ -0,0 +1,140 @@ +%TF.GenerationSoftware,KiCad,Pcbnew,8.0.2*% +%TF.CreationDate,2024-06-27T20:36:25+03:00*% +%TF.ProjectId,MV_Abnehmerplatine,4d565f41-626e-4656-986d-6572706c6174,rev?*% +%TF.SameCoordinates,Original*% +%TF.FileFunction,Soldermask,Top*% +%TF.FilePolarity,Negative*% +%FSLAX46Y46*% +G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* +G04 Created by KiCad (PCBNEW 8.0.2) date 2024-06-27 20:36:25* +%MOMM*% +%LPD*% +G01* +G04 APERTURE LIST* +G04 Aperture macros list* +%AMRoundRect* +0 Rectangle with rounded corners* +0 $1 Rounding radius* +0 $2 $3 $4 $5 $6 $7 $8 $9 X,Y pos of 4 corners* +0 Add a 4 corners polygon primitive as box body* +4,1,4,$2,$3,$4,$5,$6,$7,$8,$9,$2,$3,0* +0 Add four circle primitives for the rounded corners* +1,1,$1+$1,$2,$3* +1,1,$1+$1,$4,$5* +1,1,$1+$1,$6,$7* +1,1,$1+$1,$8,$9* +0 Add four rect primitives between the rounded corners* +20,1,$1+$1,$2,$3,$4,$5,0* +20,1,$1+$1,$4,$5,$6,$7,0* +20,1,$1+$1,$6,$7,$8,$9,0* +20,1,$1+$1,$8,$9,$2,$3,0*% +G04 Aperture macros list end* +%ADD10RoundRect,0.225000X-0.250000X0.225000X-0.250000X-0.225000X0.250000X-0.225000X0.250000X0.225000X0*% +%ADD11R,1.600000X1.600000*% +%ADD12C,3.000000*% +G04 APERTURE END LIST* +D10* +%TO.C,C1*% +X76090000Y-90585000D03* +X76090000Y-92135000D03* +%TD*% +%TO.C,C3*% +X102060000Y-90615000D03* +X102060000Y-92165000D03* +%TD*% +%TO.C,C4*% +X115680000Y-90625000D03* +X115680000Y-92175000D03* +%TD*% +%TO.C,C2*% +X89290000Y-90585000D03* +X89290000Y-92135000D03* +%TD*% +%TO.C,C7*% +X155290000Y-90585000D03* +X155290000Y-92135000D03* +%TD*% +%TO.C,C5*% +X128880000Y-90600000D03* +X128880000Y-92150000D03* +%TD*% +%TO.C,C10*% +X194890000Y-90585000D03* +X194890000Y-92135000D03* +%TD*% +D11* +%TO.C,SW0*% +X66140000Y-94190000D03* +X66140000Y-96730000D03* +X73760000Y-96730000D03* +X73760000Y-94190000D03* +%TD*% +D10* +%TO.C,C6*% +X142080000Y-90625000D03* +X142080000Y-92175000D03* +%TD*% +%TO.C,C11*% +X208090000Y-90585000D03* +X208090000Y-92135000D03* +%TD*% +%TO.C,C0*% +X62890000Y-90585000D03* +X62890000Y-92135000D03* +%TD*% +%TO.C,C12*% +X221290000Y-90585000D03* +X221290000Y-92135000D03* +%TD*% +%TO.C,C9*% +X181690000Y-90585000D03* +X181690000Y-92135000D03* +%TD*% +%TO.C,C8*% +X168490000Y-90585000D03* +X168490000Y-92135000D03* +%TD*% +D12* +%TO.C,H8*% +X170690002Y-104015000D03* +%TD*% +%TO.C,H4*% +X117890000Y-104015001D03* +%TD*% +%TO.C,H1*% +X78290000Y-104020000D03* +%TD*% +%TO.C,H0*% +X65090000Y-104020000D03* +%TD*% +%TO.C,H10*% +X197090002Y-104015000D03* +%TD*% +%TO.C,H3*% +X104700000Y-104015000D03* +%TD*% +%TO.C,H11*% +X210290000Y-104015000D03* +%TD*% +%TO.C,H9*% +X183890002Y-104015000D03* +%TD*% +%TO.C,H2*% +X91500002Y-104021000D03* +%TD*% +%TO.C,H13*% +X236690002Y-104015000D03* +%TD*% +%TO.C,H12*% +X223490000Y-104015000D03* +%TD*% +%TO.C,H7*% +X157490002Y-104015000D03* +%TD*% +%TO.C,H5*% +X131090002Y-104021000D03* +%TD*% +%TO.C,H6*% +X144290002Y-104015000D03* +%TD*% +M02* diff --git a/Hardware/MV_Abnehmerplatine/FT24_MV_Abnehmer_V1/MV_Abnehmerplatine-F_Paste.gbr b/Hardware/MV_Abnehmerplatine/FT24_MV_Abnehmer_V1/MV_Abnehmerplatine-F_Paste.gbr new file mode 100644 index 0000000..8c46a59 --- /dev/null +++ b/Hardware/MV_Abnehmerplatine/FT24_MV_Abnehmer_V1/MV_Abnehmerplatine-F_Paste.gbr @@ -0,0 +1,96 @@ +%TF.GenerationSoftware,KiCad,Pcbnew,8.0.2*% +%TF.CreationDate,2024-06-27T20:36:25+03:00*% +%TF.ProjectId,MV_Abnehmerplatine,4d565f41-626e-4656-986d-6572706c6174,rev?*% +%TF.SameCoordinates,Original*% +%TF.FileFunction,Paste,Top*% +%TF.FilePolarity,Positive*% +%FSLAX46Y46*% +G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* +G04 Created by KiCad (PCBNEW 8.0.2) date 2024-06-27 20:36:25* +%MOMM*% +%LPD*% +G01* +G04 APERTURE LIST* +G04 Aperture macros list* +%AMRoundRect* +0 Rectangle with rounded corners* +0 $1 Rounding radius* +0 $2 $3 $4 $5 $6 $7 $8 $9 X,Y pos of 4 corners* +0 Add a 4 corners polygon primitive as box body* +4,1,4,$2,$3,$4,$5,$6,$7,$8,$9,$2,$3,0* +0 Add four circle primitives for the rounded corners* +1,1,$1+$1,$2,$3* +1,1,$1+$1,$4,$5* +1,1,$1+$1,$6,$7* +1,1,$1+$1,$8,$9* +0 Add four rect primitives between the rounded corners* +20,1,$1+$1,$2,$3,$4,$5,0* +20,1,$1+$1,$4,$5,$6,$7,0* +20,1,$1+$1,$6,$7,$8,$9,0* +20,1,$1+$1,$8,$9,$2,$3,0*% +G04 Aperture macros list end* +%ADD10RoundRect,0.225000X-0.250000X0.225000X-0.250000X-0.225000X0.250000X-0.225000X0.250000X0.225000X0*% +%ADD11R,1.600000X1.600000*% +G04 APERTURE END LIST* +D10* +%TO.C,C1*% +X76090000Y-90585000D03* +X76090000Y-92135000D03* +%TD*% +%TO.C,C3*% +X102060000Y-90615000D03* +X102060000Y-92165000D03* +%TD*% +%TO.C,C4*% +X115680000Y-90625000D03* +X115680000Y-92175000D03* +%TD*% +%TO.C,C2*% +X89290000Y-90585000D03* +X89290000Y-92135000D03* +%TD*% +%TO.C,C7*% +X155290000Y-90585000D03* +X155290000Y-92135000D03* +%TD*% +%TO.C,C5*% +X128880000Y-90600000D03* +X128880000Y-92150000D03* +%TD*% +%TO.C,C10*% +X194890000Y-90585000D03* +X194890000Y-92135000D03* +%TD*% +D11* +%TO.C,SW0*% +X66140000Y-94190000D03* +X66140000Y-96730000D03* +X73760000Y-96730000D03* +X73760000Y-94190000D03* +%TD*% +D10* +%TO.C,C6*% +X142080000Y-90625000D03* +X142080000Y-92175000D03* +%TD*% +%TO.C,C11*% +X208090000Y-90585000D03* +X208090000Y-92135000D03* +%TD*% +%TO.C,C0*% +X62890000Y-90585000D03* +X62890000Y-92135000D03* +%TD*% +%TO.C,C12*% +X221290000Y-90585000D03* +X221290000Y-92135000D03* +%TD*% +%TO.C,C9*% +X181690000Y-90585000D03* +X181690000Y-92135000D03* +%TD*% +%TO.C,C8*% +X168490000Y-90585000D03* +X168490000Y-92135000D03* +%TD*% +M02* diff --git a/Hardware/MV_Abnehmerplatine/FT24_MV_Abnehmer_V1/MV_Abnehmerplatine-F_Silkscreen.gbr b/Hardware/MV_Abnehmerplatine/FT24_MV_Abnehmer_V1/MV_Abnehmerplatine-F_Silkscreen.gbr new file mode 100644 index 0000000..cd641d7 --- /dev/null +++ b/Hardware/MV_Abnehmerplatine/FT24_MV_Abnehmer_V1/MV_Abnehmerplatine-F_Silkscreen.gbr @@ -0,0 +1,11047 @@ +%TF.GenerationSoftware,KiCad,Pcbnew,8.0.2*% +%TF.CreationDate,2024-06-27T20:36:25+03:00*% +%TF.ProjectId,MV_Abnehmerplatine,4d565f41-626e-4656-986d-6572706c6174,rev?*% +%TF.SameCoordinates,Original*% +%TF.FileFunction,Legend,Top*% +%TF.FilePolarity,Positive*% +%FSLAX46Y46*% +G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)* +G04 Created by KiCad (PCBNEW 8.0.2) date 2024-06-27 20:36:25* +%MOMM*% +%LPD*% +G01* +G04 APERTURE LIST* +G04 Aperture macros list* +%AMRoundRect* +0 Rectangle with rounded corners* +0 $1 Rounding radius* +0 $2 $3 $4 $5 $6 $7 $8 $9 X,Y pos of 4 corners* +0 Add a 4 corners polygon primitive as box body* +4,1,4,$2,$3,$4,$5,$6,$7,$8,$9,$2,$3,0* +0 Add four circle primitives for the rounded corners* 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\n0921-5-15-20-75-14-11-0 3,05-0,75=2.3mm 2,3-0,45=1,9mm=0.0748in 98g\n\nI picked the 0921-1-15-20-75-14-11-0 because it doesnt poke out too much and doesn't apply\ntoo much force at that compression distance" + (exclude_from_sim no) + (at 12.954 13.081 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left top) + ) + (uuid "831fdf95-51c8-4fef-a984-0d8a8312e45a") + ) + (text "The connections to A0, A1, A2 are according to p. 15 in the datasheet of the TMP1075. \nThis gives the the temperature sensor its ID. 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+ (pin passive line (at -5.08 0 0) (length 3.81) + (name "Pin_1" (effects (font (size 1.27 1.27)))) + (number "1" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at -5.08 -2.54 0) (length 3.81) + (name "Pin_2" (effects (font (size 1.27 1.27)))) + (number "2" (effects (font (size 1.27 1.27)))) + ) + ) + ) + (symbol "MMNL_4p_horizontal" (pin_names (offset 1.016) hide) (in_bom yes) (on_board yes) + (property "Reference" "J" (id 0) (at 0 5.08 0) + (effects (font (size 1.27 1.27))) + ) + (property "Value" "MMNL_4p_horizontal" (id 1) (at 0 -7.62 0) + (effects (font (size 1.27 1.27))) + ) + (property "Footprint" "FaSTTUBe_connectors:Micro_Mate-N-Lok_4p_horizontal" (id 2) (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "Datasheet" "~" (id 3) (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "ki_keywords" "connector" (id 4) (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "ki_description" "Micro Mate-N-Lok, single row, 4 position, SMD, horizontal" (id 5) (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "ki_fp_filters" "Connector*:*_1x??_*" (id 6) (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (symbol "MMNL_4p_horizontal_1_1" + (arc (start 0 -4.572) (mid -0.508 -5.08) (end 0 -5.588) + (stroke (width 0.1524) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (arc (start 0 -2.032) (mid -0.508 -2.54) (end 0 -3.048) + (stroke (width 0.1524) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (polyline + (pts + (xy -1.27 -5.08) + (xy -0.508 -5.08) + ) + (stroke (width 0.1524) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (polyline + (pts + (xy -1.27 -2.54) + (xy -0.508 -2.54) + ) + (stroke (width 0.1524) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (polyline + (pts + (xy -1.27 0) + (xy -0.508 0) + ) + (stroke (width 0.1524) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (polyline + (pts + (xy -1.27 2.54) + (xy -0.508 2.54) + ) + (stroke (width 0.1524) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (arc (start 0 0.508) (mid -0.508 0) (end 0 -0.508) + (stroke (width 0.1524) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (arc (start 0 3.048) (mid -0.508 2.54) (end 0 2.032) + (stroke (width 0.1524) (type default) (color 0 0 0 0)) + (fill (type none)) + ) + (pin passive line (at -5.08 2.54 0) (length 3.81) + (name "Pin_1" (effects (font (size 1.27 1.27)))) + (number "1" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at -5.08 0 0) (length 3.81) + (name "Pin_2" (effects (font (size 1.27 1.27)))) + (number "2" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at -5.08 -2.54 0) (length 3.81) + (name "Pin_3" (effects (font (size 1.27 1.27)))) + (number "3" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at -5.08 -5.08 0) (length 3.81) + (name "Pin_4" (effects (font (size 1.27 1.27)))) + (number "4" (effects (font (size 1.27 1.27)))) + ) + ) + ) +) diff --git a/Hardware/MV_Abnehmerplatine/Symbol_Library/FaSTTUBe_logos.kicad_sym b/Hardware/MV_Abnehmerplatine/Symbol_Library/FaSTTUBe_logos.kicad_sym new file mode 100644 index 0000000..9b072fe --- /dev/null +++ b/Hardware/MV_Abnehmerplatine/Symbol_Library/FaSTTUBe_logos.kicad_sym @@ -0,0 +1,97 @@ +(kicad_symbol_lib (version 20211014) (generator kicad_symbol_editor) + (symbol "FTLogo_big" (in_bom yes) (on_board yes) + (property "Reference" "#Logo" (id 0) (at 0 3.81 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "Value" "FTLogo_big" (id 1) (at 0 -3.81 0) + (effects (font (size 1.27 1.27))) + ) + (property "Footprint" "FaSTTUBe_logos:FTLogo_big" (id 2) (at 0 -6.35 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "Datasheet" "" (id 3) (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + (symbol "FTLogo_big_0_0" + (text "Logo" (at 0 0 0) + (effects (font (size 1.27 1.27))) + ) + ) + (symbol "FTLogo_big_0_1" + (rectangle (start -6.35 2.54) (end 6.35 -2.54) + (stroke (width 0.254) (type default) (color 0 0 0 0)) + (fill (type background)) + ) + ) + ) + (symbol "FTLogo_med" (extends "FTLogo_big") + (property "Reference" "#Logo" (id 0) (at 0 3.81 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "Value" "FTLogo_med" (id 1) (at 0 -3.81 0) + (effects (font (size 1.27 1.27))) + ) + (property "Footprint" "FaSTTUBe_logos:FTLogo_medium" (id 2) (at 0 -3.81 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "Datasheet" "" (id 3) (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + ) + (symbol "FTLogo_small" (extends "FTLogo_big") + (property "Reference" "#Logo" (id 0) (at 0 3.81 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "Value" "FTLogo_small" (id 1) (at 0 -3.81 0) + (effects (font (size 1.27 1.27))) + ) + (property "Footprint" "FaSTTUBe_logos:FTLogo_small" (id 2) (at 0 -3.81 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "Datasheet" "" (id 3) (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + ) + 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3.81 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "Value" "LeitOn_small" (id 1) (at 0 -3.81 0) + (effects (font (size 1.27 1.27))) + ) + (property "Footprint" "FaSTTUBe_logos:LeitOn_small" (id 2) (at 0 -3.81 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "Datasheet" "" (id 3) (at 0 0 0) + (effects (font (size 1.27 1.27)) hide) + ) + ) +) diff --git a/Hardware/MV_Abnehmerplatine/Symbol_Library/FaSTTUBe_logos.pretty/FTLogo_big.kicad_mod b/Hardware/MV_Abnehmerplatine/Symbol_Library/FaSTTUBe_logos.pretty/FTLogo_big.kicad_mod new file mode 100755 index 0000000..27974a4 --- /dev/null +++ b/Hardware/MV_Abnehmerplatine/Symbol_Library/FaSTTUBe_logos.pretty/FTLogo_big.kicad_mod @@ -0,0 +1,1797 @@ +(footprint "FTLogo_big" (version 20211014) (generator pcbnew) + (layer "F.Cu") + (tedit 0) + (attr through_hole) + (fp_text reference "G***" (at 0 0) (layer "F.SilkS") hide + (effects (font (size 1.524 1.524) (thickness 0.3))) + (tstamp 481137d1-6c19-437a-81ce-986e57a0635f) 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100644 index 0000000..6012692 --- /dev/null +++ b/Hardware/MV_Abnehmerplatine/Symbol_Library/LIB_53309-2070/53309-2070.kicad_sym @@ -0,0 +1,120 @@ +(kicad_symbol_lib (version 20211014) (generator SamacSys_ECAD_Model) + (symbol "53309-2070" (in_bom yes) (on_board yes) + (property "Reference" "J" (at 19.05 7.62 0) + (effects (font (size 1.27 1.27)) (justify left top)) + ) + (property "Value" "53309-2070" (at 19.05 5.08 0) + (effects (font (size 1.27 1.27)) (justify left top)) + ) + (property "Footprint" "533092070" (at 19.05 -94.92 0) + (effects (font (size 1.27 1.27)) (justify left top) hide) + ) + (property "Datasheet" "https://componentsearchengine.com/Datasheets/1/53309-2070.pdf" (at 19.05 -194.92 0) + (effects (font (size 1.27 1.27)) (justify left top) hide) + ) + (property "ki_description" "Board to Board & Mezzanine Connectors 0.8 BtB Wafer Assy R RA 20Ckt EmbsTp Pkg" (at 19.05 -294.92 0) + (effects (font (size 1.27 1.27)) (justify left top) hide) + ) + (property "Height" "4.9" (at 19.05 -394.92 0) + (effects (font (size 1.27 1.27)) (justify left top) hide) + ) + (property "Mouser Part Number" "538-53309-2070" (at 19.05 -494.92 0) + (effects (font (size 1.27 1.27)) (justify left top) hide) + ) + (property "Mouser Price/Stock" "https://www.mouser.co.uk/ProductDetail/Molex/53309-2070?qs=9BfFgGvh7CfO11BRQ4L7fQ%3D%3D" (at 19.05 -594.92 0) + (effects (font (size 1.27 1.27)) (justify left top) hide) + ) + (property "Manufacturer_Name" "Molex" (at 19.05 -694.92 0) + (effects (font (size 1.27 1.27)) (justify left top) hide) + ) + (property "Manufacturer_Part_Number" "53309-2070" (at 19.05 -794.92 0) + (effects (font (size 1.27 1.27)) (justify left top) hide) + ) + (rectangle + (start 5.08 2.54) + (end 17.78 -25.4) + (stroke (width 0.254) (type default)) + (fill (type background)) + ) + (pin passive line (at 22.86 -22.86 180) (length 5.08) + (name "1" (effects (font (size 1.27 1.27)))) + (number "1" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at 0 -22.86 0) (length 5.08) + (name "2" (effects (font (size 1.27 1.27)))) + (number "2" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at 22.86 -20.32 180) (length 5.08) + (name "3" (effects (font (size 1.27 1.27)))) + (number "3" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at 0 -20.32 0) (length 5.08) + (name "4" (effects (font (size 1.27 1.27)))) + (number "4" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at 22.86 -17.78 180) (length 5.08) + (name "5" (effects (font (size 1.27 1.27)))) + (number "5" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at 0 -17.78 0) (length 5.08) + (name "6" (effects (font (size 1.27 1.27)))) + (number "6" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at 22.86 -15.24 180) (length 5.08) + (name "7" (effects (font (size 1.27 1.27)))) + (number "7" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at 0 -15.24 0) (length 5.08) + (name "8" (effects (font (size 1.27 1.27)))) + (number "8" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at 22.86 -12.7 180) (length 5.08) + (name "9" (effects (font (size 1.27 1.27)))) + (number "9" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at 0 -12.7 0) (length 5.08) + (name "10" (effects (font (size 1.27 1.27)))) + (number "10" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at 22.86 -10.16 180) (length 5.08) + (name "11" (effects (font (size 1.27 1.27)))) + (number "11" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at 0 -10.16 0) (length 5.08) + (name "12" (effects (font (size 1.27 1.27)))) + (number "12" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at 22.86 -7.62 180) (length 5.08) + (name "13" (effects (font (size 1.27 1.27)))) + (number "13" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at 0 -7.62 0) (length 5.08) + (name "14" (effects (font (size 1.27 1.27)))) + (number "14" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at 22.86 -5.08 180) (length 5.08) + (name "15" (effects (font (size 1.27 1.27)))) + (number "15" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at 0 -5.08 0) (length 5.08) + (name "16" (effects (font (size 1.27 1.27)))) + (number "16" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at 22.86 -2.54 180) (length 5.08) + (name "17" (effects (font (size 1.27 1.27)))) + (number "17" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at 0 -2.54 0) (length 5.08) + (name "18" (effects (font (size 1.27 1.27)))) + (number "18" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at 22.86 0 180) (length 5.08) + (name "19" (effects (font (size 1.27 1.27)))) + (number "19" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at 0 0 0) (length 5.08) + (name "20" (effects (font (size 1.27 1.27)))) + (number "20" (effects (font (size 1.27 1.27)))) + ) + ) +) diff --git a/Hardware/MV_Abnehmerplatine/Symbol_Library/LIB_TMP1075DSGR/KiCad/TMP1075DSGR.kicad_sym b/Hardware/MV_Abnehmerplatine/Symbol_Library/LIB_TMP1075DSGR/KiCad/TMP1075DSGR.kicad_sym new file mode 100644 index 0000000..127d0fe --- /dev/null +++ b/Hardware/MV_Abnehmerplatine/Symbol_Library/LIB_TMP1075DSGR/KiCad/TMP1075DSGR.kicad_sym @@ -0,0 +1,76 @@ +(kicad_symbol_lib (version 20211014) (generator SamacSys_ECAD_Model) + (symbol "TMP1075DSGR" (in_bom yes) (on_board yes) + (property "Reference" "IC" (at 26.67 7.62 0) + (effects (font (size 1.27 1.27)) (justify left top)) + ) + (property "Value" "TMP1075DSGR" (at 26.67 5.08 0) + (effects (font (size 1.27 1.27)) (justify left top)) + ) + (property "Footprint" "SON50P200X200X80-9N" (at 26.67 -94.92 0) + (effects (font (size 1.27 1.27)) (justify left top) hide) + ) + (property "Datasheet" "http://www.ti.com/lit/ds/symlink/tmp1075.pdf" (at 26.67 -194.92 0) + (effects (font (size 1.27 1.27)) (justify left top) hide) + ) + (property "ki_description" "High-accuracy upgrade to industry standard LM75 / TMP75 I2C temperature sensor" (at 26.67 -294.92 0) + (effects (font (size 1.27 1.27)) (justify left top) hide) + ) + (property "Height" "0.8" (at 26.67 -394.92 0) + (effects (font (size 1.27 1.27)) (justify left top) hide) + ) + (property "Mouser Part Number" "595-TMP1075DSGR" (at 26.67 -494.92 0) + (effects (font (size 1.27 1.27)) (justify left top) hide) + ) + (property "Mouser Price/Stock" "https://www.mouser.co.uk/ProductDetail/Texas-Instruments/TMP1075DSGR?qs=gZXFycFWdAOidBdJW42bRw%3D%3D" (at 26.67 -594.92 0) + (effects (font (size 1.27 1.27)) (justify left top) hide) + ) + (property "Manufacturer_Name" "Texas Instruments" (at 26.67 -694.92 0) + (effects (font (size 1.27 1.27)) (justify left top) hide) + ) + (property "Manufacturer_Part_Number" "TMP1075DSGR" (at 26.67 -794.92 0) + (effects (font (size 1.27 1.27)) (justify left top) hide) + ) + (rectangle + (start 5.08 2.54) + (end 25.4 -15.24) + (stroke (width 0.254) (type default)) + (fill (type background)) + ) + (pin passive line (at 0 0 0) (length 5.08) + (name "SDA" (effects (font (size 1.27 1.27)))) + (number "1" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at 0 -2.54 0) (length 5.08) + (name "SCL" (effects (font (size 1.27 1.27)))) + (number "2" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at 0 -5.08 0) (length 5.08) + (name "ALERT" (effects (font (size 1.27 1.27)))) + (number "3" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at 0 -7.62 0) (length 5.08) + (name "GND" (effects (font (size 1.27 1.27)))) + (number "4" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at 15.24 -20.32 90) (length 5.08) + (name "EP" (effects (font (size 1.27 1.27)))) + (number "9" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at 30.48 0 180) (length 5.08) + (name "V+" (effects (font (size 1.27 1.27)))) + (number "8" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at 30.48 -2.54 180) (length 5.08) + (name "A0" (effects (font (size 1.27 1.27)))) + (number "7" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at 30.48 -5.08 180) (length 5.08) + (name "A1" (effects (font (size 1.27 1.27)))) + (number "6" (effects (font (size 1.27 1.27)))) + ) + (pin passive line (at 30.48 -7.62 180) (length 5.08) + (name "A2" (effects (font (size 1.27 1.27)))) + (number "5" (effects (font (size 1.27 1.27)))) + ) + ) +) diff --git a/Hardware/MV_Abnehmerplatine/Symbol_Library/MV_Abnehmerplatine.kicad_sym b/Hardware/MV_Abnehmerplatine/Symbol_Library/MV_Abnehmerplatine.kicad_sym new file mode 100644 index 0000000..7ce3c50 --- /dev/null +++ b/Hardware/MV_Abnehmerplatine/Symbol_Library/MV_Abnehmerplatine.kicad_sym @@ -0,0 +1,105 @@ +(kicad_symbol_lib + (version 20231120) + (generator "kicad_symbol_editor") + (generator_version "8.0") + (symbol "0921-X-XX-20-7X-14-11-0" + (pin_numbers hide) + (pin_names + (offset 1.016) hide) + (exclude_from_sim yes) + (in_bom no) + (on_board yes) + (property "Reference" "H" + (at 0 6.35 0) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Value" "0921-X-15-20-7X-14-11-0" + (at 0 4.445 0) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Footprint" "MV_Abnehmerplatine:0921-0-15-20-76-14-11-0" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Datasheet" "https://www.mill-max.com/products/datasheet/pinsrecs/0921-1-15-20-75-14-11-0" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Description" "Mounting Hole for Pogo-pins" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "ki_keywords" "mounting hole" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "ki_fp_filters" "MountingHole*Pad*" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (symbol "0921-X-XX-20-7X-14-11-0_1_1" + (circle + (center 0 1.27) + (radius 1.27) + (stroke + (width 0.5) + (type default) + ) + (fill + (type none) + ) + ) + (pin input line + (at 0 -2.54 90) + (length 2.54) + (name "1" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (number "1" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + ) + ) + ) +) diff --git a/Hardware/MV_Abnehmerplatine/Symbol_Library/MV_Abnehmerplatine.pretty/0921-0-15-20-76-14-11-0.kicad_mod b/Hardware/MV_Abnehmerplatine/Symbol_Library/MV_Abnehmerplatine.pretty/0921-0-15-20-76-14-11-0.kicad_mod new file mode 100644 index 0000000..ac28dd8 --- /dev/null +++ b/Hardware/MV_Abnehmerplatine/Symbol_Library/MV_Abnehmerplatine.pretty/0921-0-15-20-76-14-11-0.kicad_mod @@ -0,0 +1,104 @@ +(footprint "0921-0-15-20-76-14-11-0" + (version 20240108) + (generator "pcbnew") + (generator_version "8.0") + (layer "F.Cu") + (descr "0921 Through Hole Mount Spring-Loaded Pin") + (tags "Spring-Loaded Pin, Pogo Pin") + (property "Reference" "P**" + (at 0 -2.9464 0) + (unlocked yes) + (layer "B.SilkS") + (uuid "abfc94ae-4df0-4c94-9aac-7491b696f7c6") + (effects + (font + (size 1 1) + (thickness 0.1) + ) + (justify mirror) + ) + ) + (property "Value" "0921-0-15-20-76-14-11-0" + (at 0 1 0) + (unlocked yes) + (layer "F.Fab") + (uuid "2dae4001-357d-4099-9fb5-0e83c2f7c83a") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Footprint" "0921-0-15-20-76-14-11-0" + (at 0 0 0) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid "b55526be-b407-407e-a846-dc5784395056") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "https://www.mill-max.com/products/datasheet/pinsrecs/0921-0-15-20-76-14-11-0" + (at 0 0 0) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid "e2d26811-8829-4583-b069-2724bcbb29c5") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Description" "0921 Through Hole Mount Spring-Loaded Pin" + (at 0 0 0) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid "ee2819b6-f3f6-4ea1-88d6-ac2609acb450") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (attr through_hole) + (fp_text user "${REFERENCE}" + (at 0 2.5 0) + (unlocked yes) + (layer "F.Fab") + (uuid "98b879d5-e0bb-4595-be75-b56f6cb22693") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (pad "1" thru_hole circle + (at 0 0) + (size 3 3) + (drill 1.7) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (uuid "0312a44d-5ec2-4192-96cd-61540771d78f") + ) + (model "${KIPRJMOD}/Symbol_Library/3DModells/mill-max-0921-0-15-20-76-14-11-0.step" + (offset + (xyz 0 0 -2.6) + ) + (scale + (xyz 1 1 1) + ) + (rotate + (xyz 0 90 0) + ) + ) +) diff --git a/Hardware/MV_Abnehmerplatine/Symbol_Library/MV_Abnehmerplatine.pretty/0921-1-15-20-75-14-11-0.kicad_mod b/Hardware/MV_Abnehmerplatine/Symbol_Library/MV_Abnehmerplatine.pretty/0921-1-15-20-75-14-11-0.kicad_mod new file mode 100644 index 0000000..391971c --- /dev/null +++ b/Hardware/MV_Abnehmerplatine/Symbol_Library/MV_Abnehmerplatine.pretty/0921-1-15-20-75-14-11-0.kicad_mod @@ -0,0 +1,116 @@ +(footprint "0921-1-15-20-75-14-11-0" + (version 20240108) + (generator "pcbnew") + (generator_version "8.0") + (layer "F.Cu") + (descr "0921 Through Hole Mount Spring-Loaded Pin") + (tags "Spring-Loaded Pin, Pogo Pin") + (property "Reference" "P**" + (at 0 -2.9464 0) + (unlocked yes) + (layer "B.SilkS") + (uuid "abfc94ae-4df0-4c94-9aac-7491b696f7c6") + (effects + (font + (size 2 2) + (thickness 0.3) + ) + (justify mirror) + ) + ) + (property "Value" "0921-1-15-20-75-14-11-0" + (at 0 1 0) + (unlocked yes) + (layer "F.Fab") + (uuid "2dae4001-357d-4099-9fb5-0e83c2f7c83a") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Footprint" "0921-1-15-20-75-14-11-0" + (at 0 0 0) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid "b55526be-b407-407e-a846-dc5784395056") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "https://www.mill-max.com/products/datasheet/pinsrecs/0921-1-15-20-75-14-11-0" + (at 0 0 0) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid "e2d26811-8829-4583-b069-2724bcbb29c5") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Description" "0921 Through Hole Mount Spring-Loaded Pin" + (at 0 0 0) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid "ee2819b6-f3f6-4ea1-88d6-ac2609acb450") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (attr through_hole) + (fp_text user "${REFERENCE}" + (at 0 2.5 0) + (unlocked yes) + (layer "F.Fab") + (uuid "98b879d5-e0bb-4595-be75-b56f6cb22693") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (pad "1" thru_hole circle + (at 0 0) + (size 3 3) + (drill 1.75) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (clearance 1) + (teardrops + (best_length_ratio 1) + (max_length 9) + (best_width_ratio 1) + (max_width 9) + (curve_points 5) + (filter_ratio 1) + (enabled yes) + (allow_two_segments yes) + (prefer_zone_connections yes) + ) + (uuid "0312a44d-5ec2-4192-96cd-61540771d78f") + ) + (model "${KIPRJMOD}/Symbol_Library/3DModells/mill-max-0921-1-15-20-75-14-11-0.step" + (offset + (xyz 0 0 -3.05) + ) + (scale + (xyz 1 1 1) + ) + (rotate + (xyz 0 90 0) + ) + ) +) diff --git a/Hardware/MV_Abnehmerplatine/Symbol_Library/MV_Abnehmerplatine.pretty/0921-5-15-20-77-14-11-0.kicad_mod b/Hardware/MV_Abnehmerplatine/Symbol_Library/MV_Abnehmerplatine.pretty/0921-5-15-20-77-14-11-0.kicad_mod new file mode 100644 index 0000000..2c6a29f --- /dev/null +++ b/Hardware/MV_Abnehmerplatine/Symbol_Library/MV_Abnehmerplatine.pretty/0921-5-15-20-77-14-11-0.kicad_mod @@ -0,0 +1,104 @@ +(footprint "0921-5-15-20-77-14-11-0" + (version 20240108) + (generator "pcbnew") + (generator_version "8.0") + (layer "F.Cu") + (descr "0921 Through Hole Mount Spring-Loaded Pin") + (tags "Spring-Loaded Pin, Pogo Pin") + (property "Reference" "P**" + (at 0 -2.9464 0) + (unlocked yes) + (layer "B.SilkS") + (uuid "abfc94ae-4df0-4c94-9aac-7491b696f7c6") + (effects + (font + (size 1 1) + (thickness 0.1) + ) + (justify mirror) + ) + ) + (property "Value" "0921-5-15-20-77-14-11-0" + (at 0 1 0) + (unlocked yes) + (layer "F.Fab") + (uuid "2dae4001-357d-4099-9fb5-0e83c2f7c83a") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Footprint" "0921-5-15-20-77-14-11-0" + (at 0 0 0) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid "b55526be-b407-407e-a846-dc5784395056") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "https://www.mill-max.com/products/datasheet/pinsrecs/0921-5-15-20-77-14-11-0" + (at 0 0 0) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid "e2d26811-8829-4583-b069-2724bcbb29c5") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Description" "0921 Through Hole Mount Spring-Loaded Pin" + (at 0 0 0) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid "ee2819b6-f3f6-4ea1-88d6-ac2609acb450") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (attr through_hole) + (fp_text user "${REFERENCE}" + (at 0 2.5 0) + (unlocked yes) + (layer "F.Fab") + (uuid "98b879d5-e0bb-4595-be75-b56f6cb22693") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (pad "1" thru_hole circle + (at 0 0) + (size 3 3) + (drill 1.7) + (layers "*.Cu" "*.Mask") + (remove_unused_layers no) + (uuid "0312a44d-5ec2-4192-96cd-61540771d78f") + ) + (model "${KIPRJMOD}/Symbol_Library/3DModells/mill-max-0921-5-15-20-77-14-11-0.step" + (offset + (xyz 0 0 -3.45) + ) + (scale + (xyz 1 1 1) + ) + (rotate + (xyz 0 90 0) + ) + ) +) diff --git a/Hardware/MV_Abnehmerplatine/Symbol_Library/MV_Abnehmerplatine.pretty/533092070.kicad_mod b/Hardware/MV_Abnehmerplatine/Symbol_Library/MV_Abnehmerplatine.pretty/533092070.kicad_mod new file mode 100644 index 0000000..ae36b36 --- /dev/null +++ b/Hardware/MV_Abnehmerplatine/Symbol_Library/MV_Abnehmerplatine.pretty/533092070.kicad_mod @@ -0,0 +1,412 @@ +(footprint "533092070" + (version 20240108) + (generator "pcbnew") + (generator_version "8.0") + (layer "F.Cu") + (descr "53309-2070-1") + (tags "Connector") + (property "Reference" "J**" + (at 0 0.025 0) + (layer "F.SilkS") + (uuid "919e8663-a84f-4dd2-bc46-093a7f53954d") + (effects + (font + (size 1.27 1.27) + (thickness 0.254) + ) + ) + ) + (property "Value" "533092070" + (at 0 0.025 0) + (layer "F.SilkS") + (hide yes) + (uuid "89d92af0-5e8b-47ea-8e11-d3f414fd9aee") + (effects + (font + (size 1.27 1.27) + (thickness 0.254) + ) + ) + ) + (property "Footprint" "MV_Abnehmerplatine:533092070" + (at 0 0 0) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid "21abe5fe-7e82-41ac-9c23-1af2385d6488") + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 0) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid "6bfd2cf0-3736-431e-ac24-542c7905e960") + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Description" "" + (at 0 0 0) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid "937b04dd-b71a-4c5c-b358-d923be9ef91a") + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (attr smd) + (fp_line + (start -4.9 -2.1) + (end -4.9 2.1) + (stroke + (width 0.1) + (type solid) + ) + (layer "F.SilkS") + (uuid "87f8644e-08b7-4422-8150-56eff8b3334c") + ) + (fp_line + (start -4.9 2.1) + (end -4.2 2.1) + (stroke + (width 0.1) + (type solid) + ) + (layer "F.SilkS") + (uuid "d2c6e0da-670d-4cda-a762-39bad74e7746") + ) + (fp_line + (start -4.8 -2.1) + (end -4.9 -2.1) + (stroke + (width 0.1) + (type solid) + ) + (layer "F.SilkS") + (uuid "0921438d-a04a-4ff3-9db0-ceda801c9a94") + ) + (fp_line + (start -4.2 -2.1) + (end -4.8 -2.1) + (stroke + (width 0.1) + (type solid) + ) + (layer "F.SilkS") + (uuid "b7794960-39e8-4745-bde8-fc0775d76e77") + ) + (fp_line + (start 3.6 -3.4) + (end 3.6 -3.4) + (stroke + (width 0.2) + (type solid) + ) + (layer "F.SilkS") + (uuid "c4775727-718c-47db-83a2-56194b392939") + ) + (fp_line + (start 3.8 -3.4) + (end 3.8 -3.4) + (stroke + (width 0.2) + (type solid) + ) + (layer "F.SilkS") + (uuid "5405f6f6-a5f4-479c-aa5b-83ab42915348") + ) + (fp_line + (start 4.2 -2.1) + (end 4.8 -2.1) + (stroke + (width 0.1) + (type solid) + ) + (layer "F.SilkS") + (uuid "6d3e72d6-3888-402b-ac42-540e6e36485e") + ) + (fp_line + (start 4.8 -2.1) + (end 4.9 -2.1) + (stroke + (width 0.1) + (type solid) + ) + (layer "F.SilkS") + (uuid "2456b1c6-8703-4bde-a38e-4451d64975a6") + ) + (fp_line + (start 4.9 -2.1) + (end 4.9 2.1) + (stroke + (width 0.1) + (type solid) + ) + (layer "F.SilkS") + (uuid "973914bf-a555-45fb-95b7-e9dc78761de1") + ) + (fp_line + (start 4.9 2.1) + (end 4.2 2.1) + (stroke + (width 0.1) + (type solid) + ) + (layer "F.SilkS") + (uuid "17be2e0e-ce95-463f-9a72-dd269aa247e3") + ) + (fp_arc + (start 3.6 -3.4) + (mid 3.7 -3.5) + (end 3.8 -3.4) + (stroke + (width 0.2) + (type solid) + ) + (layer "F.SilkS") + (uuid "2e113605-2100-4a62-b48a-e4dbb7dbbbac") + ) + (fp_arc + (start 3.8 -3.4) + (mid 3.7 -3.3) + (end 3.6 -3.4) + (stroke + (width 0.2) + (type solid) + ) + (layer "F.SilkS") + (uuid "d9410a35-0e48-40b4-9cd4-2cdfd5836e43") + ) + (fp_line + (start -5.9 -3.925) + (end 5.9 -3.925) + (stroke + (width 0.1) + (type solid) + ) + (layer "F.CrtYd") + (uuid "9d976b57-a5dc-4882-845f-3ed7ce8bb684") + ) + (fp_line + (start -5.9 3.975) + (end -5.9 -3.925) + (stroke + (width 0.1) + (type solid) + ) + (layer "F.CrtYd") + (uuid "dc104690-c5ee-42e4-ae24-039ad67c2f09") + ) + (fp_line + (start 5.9 -3.925) + (end 5.9 3.975) + (stroke + (width 0.1) + (type solid) + ) + (layer "F.CrtYd") + (uuid "f3cd68bc-7a6c-474a-b06c-c0ca54722af2") + ) + (fp_line + (start 5.9 3.975) + (end -5.9 3.975) + (stroke + (width 0.1) + (type solid) + ) + (layer "F.CrtYd") + (uuid "649705e8-f005-4c04-aa08-e3918a66bdeb") + ) + (fp_line + (start -4.9 -2.1) + (end 4.9 -2.1) + (stroke + (width 0.2) + (type solid) + ) + (layer "F.Fab") + (uuid "fa2149c4-b0ed-4f02-ab7f-0c2251e5bd7f") + ) + (fp_line + (start -4.9 2.1) + (end -4.9 -2.1) + (stroke + (width 0.2) + (type solid) + ) + (layer "F.Fab") + (uuid "16f9745c-2044-46cd-be00-85007c5fd17f") + ) + (fp_line + (start 4.9 -2.1) + (end 4.9 2.1) + (stroke + (width 0.2) + (type solid) + ) + (layer "F.Fab") + (uuid "d4981bd2-ae2f-4a32-bc51-a657b518ce27") + ) + (fp_line + (start 4.9 2.1) + (end -4.9 2.1) + (stroke + (width 0.2) + (type solid) + ) + (layer "F.Fab") + (uuid "2da1429d-2f7b-4817-a0fc-4ce94507c3dd") + ) + (fp_text user "${REFERENCE}" + (at 0 0.025 0) + (layer "F.Fab") + (uuid "e9f31486-8258-431c-9ede-83c128628222") + (effects + (font + (size 1.27 1.27) + (thickness 0.254) + ) + ) + ) + (pad "1" smd rect + (at 3.6 -2.275) + (size 0.55 1.3) + (layers "F.Cu" "F.Paste" "F.Mask") + (uuid "b3dfed12-0b00-45b4-a8d0-359b93d36f17") + ) + (pad "2" smd rect + (at 3.6 2.275) + (size 0.55 1.4) + (layers "F.Cu" "F.Paste" "F.Mask") + (uuid "107150e8-7028-45be-880d-598077f8cdaf") + ) + (pad "3" smd rect + (at 2.8 -2.275) + (size 0.55 1.3) + (layers "F.Cu" "F.Paste" "F.Mask") + (uuid "801a151c-41c0-4f5b-a02a-d1c6c048941b") + ) + (pad "4" smd rect + (at 2.8 2.275) + (size 0.55 1.4) + (layers "F.Cu" "F.Paste" "F.Mask") + (uuid "f814d745-1dc0-4994-a057-cc6258806258") + ) + (pad "5" smd rect + (at 2 -2.275) + (size 0.55 1.3) + (layers "F.Cu" "F.Paste" "F.Mask") + (uuid "f51afedf-d6b3-4108-9fb9-67b836abf9d7") + ) + (pad "6" smd rect + (at 2 2.275) + (size 0.55 1.4) + (layers "F.Cu" "F.Paste" "F.Mask") + (uuid "09731082-8668-4410-be2e-341b1b88517f") + ) + (pad "7" smd rect + (at 1.2 -2.275) + (size 0.55 1.3) + (layers "F.Cu" "F.Paste" "F.Mask") + (uuid "f917e655-8e99-40c4-91ff-02f1862213f4") + ) + (pad "8" smd rect + (at 1.2 2.275) + (size 0.55 1.4) + (layers "F.Cu" "F.Paste" "F.Mask") + (uuid "c2fc5068-2a79-4bcd-bf2b-d1aa5b1756eb") + ) + (pad "9" smd rect + (at 0.4 -2.275) + (size 0.55 1.3) + (layers "F.Cu" "F.Paste" "F.Mask") + (uuid "cc1d186a-0b3a-4355-a5e2-137aea955bfd") + ) + (pad "10" smd rect + (at 0.4 2.275) + (size 0.55 1.4) + (layers "F.Cu" "F.Paste" "F.Mask") + (uuid "da7fa238-bc3b-4251-abe3-56f8ff83ea8c") + ) + (pad "11" smd rect + (at -0.4 -2.275) + (size 0.55 1.3) + (layers "F.Cu" "F.Paste" "F.Mask") + (uuid "7813e24a-ce46-4517-843b-490b8d1cb4a0") + ) + (pad "12" smd rect + (at -0.4 2.275) + (size 0.55 1.4) + (layers "F.Cu" "F.Paste" "F.Mask") + (uuid "a8b9b32e-d287-4d5e-83ef-bc4580cfcf81") + ) + (pad "13" smd rect + (at -1.2 -2.275) + (size 0.55 1.3) + (layers "F.Cu" "F.Paste" "F.Mask") + (uuid "78052cef-1549-4b37-9d67-af81c09dc4b3") + ) + (pad "14" smd rect + (at -1.2 2.275) + (size 0.55 1.4) + (layers "F.Cu" "F.Paste" "F.Mask") + (uuid "d4e58b30-1cd0-4c8e-936f-b61aede51072") + ) + (pad "15" smd rect + (at -2 -2.275) + (size 0.55 1.3) + (layers "F.Cu" "F.Paste" "F.Mask") + (uuid "4251a472-4120-47d4-bbe1-5e74b2bf5b0e") + ) + (pad "16" smd rect + (at -2 2.275) + (size 0.55 1.4) + (layers "F.Cu" "F.Paste" "F.Mask") + (uuid "1d40d3c9-1d2f-434a-96e7-5720cdbe4815") + ) + (pad "17" smd rect + (at -2.8 -2.275) + (size 0.55 1.3) + (layers "F.Cu" "F.Paste" "F.Mask") + (uuid "d024091e-2037-4689-b0fc-aef501aa67d3") + ) + (pad "18" smd rect + (at -2.8 2.275) + (size 0.55 1.4) + (layers "F.Cu" "F.Paste" "F.Mask") + (uuid "17b8e640-24b9-441e-bb52-35b9635a9786") + ) + (pad "19" smd rect + (at -3.6 -2.275) + (size 0.55 1.3) + (layers "F.Cu" "F.Paste" "F.Mask") + (uuid "d4636d80-d5b5-440e-904a-4bc604c44e75") + ) + (pad "20" smd rect + (at -3.6 2.275) + (size 0.55 1.4) + (layers "F.Cu" "F.Paste" "F.Mask") + (uuid "365cefc4-b27a-4c91-bfed-a0048d7a0856") + ) + (model "${KIPRJMOD}/Symbol_Library/3DModells/53309-2070.stp" + (offset + (xyz 0 0 2.380000079) + ) + (scale + (xyz 1 1 1) + ) + (rotate + (xyz -90 0 0) + ) + ) +) \ No newline at end of file diff --git a/Hardware/MV_Abnehmerplatine/Symbol_Library/Micro-Mate-N-Lok.pretty/Micro Mate-N-Lok 12-Pol.kicad_mod b/Hardware/MV_Abnehmerplatine/Symbol_Library/Micro-Mate-N-Lok.pretty/Micro Mate-N-Lok 12-Pol.kicad_mod new file mode 100644 index 0000000..06740b2 --- /dev/null +++ b/Hardware/MV_Abnehmerplatine/Symbol_Library/Micro-Mate-N-Lok.pretty/Micro Mate-N-Lok 12-Pol.kicad_mod @@ -0,0 +1,27 @@ +(module "Micro Mate-N-Lok 12-Pol" (layer F.Cu) (tedit 5CEB259A) + (fp_text reference REF** (at 0 10.96) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value "Micro Mate-N-Lok 12-Pol" (at 0 -10.96) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -0.0013 -6.5659) (end 20.0012 -6.5786) (layer F.CrtYd) (width 0.15)) + (fp_line (start 20.0012 -6.5786) (end 20.0012 4.5339) (layer F.CrtYd) (width 0.15)) + (fp_line (start 20.0012 4.5339) (end -20.0038 4.5212) (layer F.CrtYd) (width 0.15)) + (fp_line (start -20.0038 4.5212) (end -20.0038 -6.6548) (layer F.CrtYd) (width 0.15)) + (fp_line (start -20.0038 -6.6548) (end -0.0013 -6.5659) (layer F.CrtYd) (width 0.15)) + (pad 1 smd rect (at -16.5089 -5.0101) (size 1.27 3) (layers F.Cu F.Paste F.Mask)) + (pad 2 smd rect (at -13.5089 -5.0101) (size 1.27 3) (layers F.Cu F.Paste F.Mask)) + (pad 3 smd rect (at -10.5089 -5.0101) (size 1.27 3) (layers F.Cu F.Paste F.Mask)) + (pad 4 smd rect (at -7.5089 -5.0101) (size 1.27 3) (layers F.Cu F.Paste F.Mask)) + (pad 5 smd rect (at -4.5089 -5.0101) (size 1.27 3) (layers F.Cu F.Paste F.Mask)) + (pad 6 smd rect (at -1.5089 -5.0101) (size 1.27 3) (layers F.Cu F.Paste F.Mask)) + (pad 7 smd rect (at 1.4911 -5.0101) (size 1.27 3) (layers F.Cu F.Paste F.Mask)) + (pad 8 smd rect (at 4.4911 -5.0101) (size 1.27 3) (layers F.Cu F.Paste F.Mask)) + (pad 9 smd rect (at 7.4911 -5.0101) (size 1.27 3) (layers F.Cu F.Paste F.Mask)) + (pad 10 smd rect (at 10.4911 -5.0101) (size 1.27 3) (layers F.Cu F.Paste F.Mask)) + (pad 11 smd rect (at 13.4911 -5.0101) (size 1.27 3) (layers F.Cu F.Paste F.Mask)) + (pad 12 smd rect (at 16.4911 -5.0101) (size 1.27 3) (layers F.Cu F.Paste F.Mask)) + (pad "" smd rect (at -20.1439 0.4699) (size 3.5 1.65) (layers F.Cu F.Paste F.Mask)) + (pad "" smd rect (at 20.2661 0.4699) (size 3.5 1.65) (layers F.Cu F.Paste F.Mask)) +) diff --git a/Hardware/MV_Abnehmerplatine/Symbol_Library/Micro-Mate-N-Lok.pretty/Micro Mate-N-Lok 16-Pol.kicad_mod b/Hardware/MV_Abnehmerplatine/Symbol_Library/Micro-Mate-N-Lok.pretty/Micro Mate-N-Lok 16-Pol.kicad_mod new file mode 100644 index 0000000..037fc30 --- /dev/null +++ b/Hardware/MV_Abnehmerplatine/Symbol_Library/Micro-Mate-N-Lok.pretty/Micro Mate-N-Lok 16-Pol.kicad_mod @@ -0,0 +1,35 @@ +(footprint "Micro Mate-N-Lok 16-Pol" (version 20211014) (generator pcbnew) + (layer "F.Cu") + (tedit 63F4F5FB) + (attr through_hole) + (fp_text reference "REF**" (at 4.5 11.16) (layer "F.SilkS") + (effects (font (size 1 1) (thickness 0.15))) + (tstamp e47744b9-0e80-4f40-97a2-e6c666060a7e) + ) + (fp_text value "Micro Mate-N-Lok 16-Pol" (at 4.6189 -10.6499) (layer "F.Fab") + (effects (font (size 1 1) (thickness 0.15))) + (tstamp e918b919-3275-46f5-9abf-7feb327608c4) + ) + (fp_line (start -14 6.3) (end -14 -6.3) (layer "F.CrtYd") (width 0.15) (tstamp 5af55f91-716b-4e7d-8c75-1fd345b7c35e)) + (fp_line (start -14 -6.3) (end 14.275 -6.3) (layer "F.CrtYd") (width 0.15) (tstamp 771a40f7-19a7-4bfc-b88f-460c1a7e5602)) + (fp_line (start 14.275 6.3) (end -14 6.3) (layer "F.CrtYd") (width 0.15) (tstamp 950756d1-03fe-43a0-95e7-909930c47f2a)) + (fp_line (start 14.275 -6.3) (end 14.275 6.3) (layer "F.CrtYd") (width 0.15) (tstamp ed5e43c2-1b85-442b-b823-35bf1b456dbf)) + (pad "" smd rect (at -14.135 0) (size 3.5 1.65) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 2c1b1998-f439-4485-b7ce-0b13438f40bf)) + (pad "" smd rect (at 14.275 0) (size 3.5 1.65) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 2e00a52e-9c16-45d3-84a5-a06979b617b4)) + (pad "1" smd rect (at -10.5 -4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 77f36f29-ab03-4c19-9c6a-a2d42f26a525)) + (pad "2" smd rect (at -7.5 -4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 2d1dad02-6a1d-46d3-b854-5aa81ab4f8f5)) + (pad "3" smd rect (at -4.5 -4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 01cf62da-95ed-4a12-955e-985e346f552c)) + (pad "4" smd rect (at -1.5 -4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 41c9c3b8-2883-4fdc-b499-17634b4fcf10)) + (pad "5" smd rect (at 1.5 -4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp bc3b55ee-da4a-47e7-827f-dc787b3d7436)) + (pad "6" smd rect (at 4.5 -4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 210b4586-7fb1-453c-a012-150951ba2378)) + (pad "7" smd rect (at 7.5 -4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 07c4c238-6403-4327-b6d6-e3cef522d132)) + (pad "8" smd rect (at 10.5 -4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 516d561c-e210-47a1-b528-cf70e07f88f1)) + (pad "9" smd rect (at 10.5 4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 3064363d-f6c5-452f-a8e1-931c68c1d1c5)) + (pad "10" smd rect (at 7.5 4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp d6a08934-0f05-4531-86f0-e5931f2293f7)) + (pad "11" smd rect (at 4.5 4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp ba884cb2-63bf-4c50-8b66-c3860de5c02e)) + (pad "12" smd rect (at 1.5 4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp fd758cad-e0d7-4141-bc52-0b1a72d4a012)) + (pad "13" smd rect (at -1.5 4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 3d65096b-2ccd-4f03-afa3-bd1be62a8c57)) + (pad "14" smd rect (at -4.5 4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 9ef1878b-d9e0-40a1-8a39-790b6c7302c6)) + (pad "15" smd rect (at -7.5 4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 3c048d02-8b0a-4f38-b4ad-44dab638b480)) + (pad "16" smd rect (at -10.5 4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 63ec8a7f-f3b0-4fe7-af1e-8a11758001d1)) +) diff --git a/Hardware/MV_Abnehmerplatine/Symbol_Library/Micro-Mate-N-Lok.pretty/Micro Mate-N-Lok 2-Pol.kicad_mod b/Hardware/MV_Abnehmerplatine/Symbol_Library/Micro-Mate-N-Lok.pretty/Micro Mate-N-Lok 2-Pol.kicad_mod new file mode 100644 index 0000000..8e17e1d --- /dev/null +++ b/Hardware/MV_Abnehmerplatine/Symbol_Library/Micro-Mate-N-Lok.pretty/Micro Mate-N-Lok 2-Pol.kicad_mod @@ -0,0 +1,17 @@ +(module "Micro Mate-N-Lok 2-Pol" (layer F.Cu) (tedit 5CE9F075) + (fp_text reference REF** (at 0 7.6) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value "Micro Mate-N-Lok 2-Pol" (at 0 -6.22) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 0 -5.4) (end 5 -5.4) (layer F.CrtYd) (width 0.15)) + (fp_line (start 5 -5.4) (end 5 6.2) (layer F.CrtYd) (width 0.15)) + (fp_line (start 5 6.2) (end -5 6.2) (layer F.CrtYd) (width 0.15)) + (fp_line (start -5 6.2) (end -5 -5.4) (layer F.CrtYd) (width 0.15)) + (fp_line (start -5 -5.4) (end 0 -5.4) (layer F.CrtYd) (width 0.15)) + (pad 1 smd rect (at -1.5 -3.88) (size 1.27 3) (layers F.Cu F.Paste F.Mask)) + (pad 2 smd rect (at 1.5 -3.88) (size 1.27 3) (layers F.Cu F.Paste F.Mask)) + (pad "" smd rect (at -5.2 1.6) (size 3.43 1.65) (layers F.Cu F.Paste F.Mask)) + (pad "" smd rect (at 5.21 1.6) (size 3.43 1.65) (layers F.Cu F.Paste F.Mask)) +) diff --git a/Hardware/MV_Abnehmerplatine/Symbol_Library/Micro-Mate-N-Lok.pretty/Micro Mate-N-Lok 22-Pol.kicad_mod b/Hardware/MV_Abnehmerplatine/Symbol_Library/Micro-Mate-N-Lok.pretty/Micro Mate-N-Lok 22-Pol.kicad_mod new file mode 100644 index 0000000..fdb7142 --- /dev/null +++ b/Hardware/MV_Abnehmerplatine/Symbol_Library/Micro-Mate-N-Lok.pretty/Micro Mate-N-Lok 22-Pol.kicad_mod @@ -0,0 +1,41 @@ +(footprint "Micro Mate-N-Lok 22-Pol" (version 20211014) (generator pcbnew) + (layer "F.Cu") + (tedit 627FA53E) + (attr through_hole) + (fp_text reference "REF**" (at 0 11.16) (layer "F.SilkS") + (effects (font (size 1 1) (thickness 0.15))) + (tstamp e47744b9-0e80-4f40-97a2-e6c666060a7e) + ) + (fp_text value "Micro Mate-N-Lok 22-Pol" (at 0.1189 -10.6499) (layer "F.Fab") + (effects (font (size 1 1) (thickness 0.15))) + (tstamp e918b919-3275-46f5-9abf-7feb327608c4) + ) + (fp_line (start -18.5 6.3) (end -18.5 -6.3) (layer "F.CrtYd") (width 0.15) (tstamp 5af55f91-716b-4e7d-8c75-1fd345b7c35e)) + (fp_line (start -18.5 -6.3) (end 18.5 -6.3) (layer "F.CrtYd") (width 0.15) (tstamp 771a40f7-19a7-4bfc-b88f-460c1a7e5602)) + (fp_line (start 18.5 6.3) (end -18.5 6.3) (layer "F.CrtYd") (width 0.15) (tstamp 950756d1-03fe-43a0-95e7-909930c47f2a)) + (fp_line (start 18.5 -6.3) (end 18.5 6.3) (layer "F.CrtYd") (width 0.15) (tstamp ed5e43c2-1b85-442b-b823-35bf1b456dbf)) + (pad "" smd rect (at -18.635 0) (size 3.5 1.65) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 2c1b1998-f439-4485-b7ce-0b13438f40bf)) + (pad "" smd rect (at 18.775 0) (size 3.5 1.65) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 2e00a52e-9c16-45d3-84a5-a06979b617b4)) + (pad "1" smd rect (at -15 -4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 77f36f29-ab03-4c19-9c6a-a2d42f26a525)) + (pad "2" smd rect (at -12 -4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 2d1dad02-6a1d-46d3-b854-5aa81ab4f8f5)) + (pad "3" smd rect (at -9 -4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 01cf62da-95ed-4a12-955e-985e346f552c)) + (pad "4" smd rect (at -6 -4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 41c9c3b8-2883-4fdc-b499-17634b4fcf10)) + (pad "5" smd rect (at -3 -4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp bc3b55ee-da4a-47e7-827f-dc787b3d7436)) + (pad "6" smd rect (at 0 -4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 210b4586-7fb1-453c-a012-150951ba2378)) + (pad "7" smd rect (at 3 -4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 07c4c238-6403-4327-b6d6-e3cef522d132)) + (pad "8" smd rect (at 6 -4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 516d561c-e210-47a1-b528-cf70e07f88f1)) + (pad "9" smd rect (at 9 -4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 0dac2fad-51ba-45c3-9ce2-db75253acc13)) + (pad "10" smd rect (at 12 -4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 95513a05-1ba8-4d8a-991b-c2b0dc386b34)) + (pad "11" smd rect (at 15 -4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 5cf2293a-aff5-41a8-84ef-ba37fb1d0a5f)) + (pad "12" smd rect (at 15 4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp e044fd7a-13ed-4916-9f2e-12e374f299f7)) + (pad "13" smd rect (at 12 4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp e0ce8632-f9df-46d0-a7b2-e7c8b1d6e07e)) + (pad "14" smd rect (at 9 4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp b0ad5a41-9a6a-4aba-a998-46cfb89c30f2)) + (pad "15" smd rect (at 6 4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 3064363d-f6c5-452f-a8e1-931c68c1d1c5)) + (pad "16" smd rect (at 3 4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp d6a08934-0f05-4531-86f0-e5931f2293f7)) + (pad "17" smd rect (at 0 4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp ba884cb2-63bf-4c50-8b66-c3860de5c02e)) + (pad "18" smd rect (at -3 4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp fd758cad-e0d7-4141-bc52-0b1a72d4a012)) + (pad "19" smd rect (at -6 4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 3d65096b-2ccd-4f03-afa3-bd1be62a8c57)) + (pad "20" smd rect (at -9 4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 9ef1878b-d9e0-40a1-8a39-790b6c7302c6)) + (pad "21" smd rect (at -12 4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 3c048d02-8b0a-4f38-b4ad-44dab638b480)) + (pad "22" smd rect (at -15 4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 63ec8a7f-f3b0-4fe7-af1e-8a11758001d1)) +) diff --git a/Hardware/MV_Abnehmerplatine/Symbol_Library/Micro-Mate-N-Lok.pretty/Micro Mate-N-Lok 4-Pol.kicad_mod b/Hardware/MV_Abnehmerplatine/Symbol_Library/Micro-Mate-N-Lok.pretty/Micro Mate-N-Lok 4-Pol.kicad_mod new file mode 100644 index 0000000..600e2d2 --- /dev/null +++ b/Hardware/MV_Abnehmerplatine/Symbol_Library/Micro-Mate-N-Lok.pretty/Micro Mate-N-Lok 4-Pol.kicad_mod @@ -0,0 +1,19 @@ +(module "Micro Mate-N-Lok 4-Pol" (layer F.Cu) (tedit 5CE9F407) + (fp_text reference REF** (at 0 6) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value "Micro Mate-N-Lok 4-Pol" (at 0 -8) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 0 -6.6) (end 8 -6.6) (layer F.CrtYd) (width 0.15)) + (fp_line (start 8 -6.6) (end 8 4.6) (layer F.CrtYd) (width 0.15)) + (fp_line (start 8 4.6) (end -8 4.6) (layer F.CrtYd) (width 0.15)) + (fp_line (start -8 4.6) (end -8 -6.6) (layer F.CrtYd) (width 0.15)) + (fp_line (start -8 -6.6) (end 0 -6.6) (layer F.CrtYd) (width 0.15)) + (pad "" smd rect (at -8.2 0.4) (size 3.43 1.65) (layers F.Cu F.Paste F.Mask)) + (pad 4 smd rect (at 4.5 -5.08) (size 1.27 3) (layers F.Cu F.Paste F.Mask)) + (pad 3 smd rect (at 1.5 -5.08) (size 1.27 3) (layers F.Cu F.Paste F.Mask)) + (pad 2 smd rect (at -1.5 -5.08) (size 1.27 3) (layers F.Cu F.Paste F.Mask)) + (pad 1 smd rect (at -4.5 -5.08) (size 1.27 3) (layers F.Cu F.Paste F.Mask)) + (pad "" smd rect (at 8.21 0.4) (size 3.43 1.65) (layers F.Cu F.Paste F.Mask)) +) diff --git a/Hardware/MV_Abnehmerplatine/Symbol_Library/Micro-Mate-N-Lok.pretty/Micro Mate-N-Lok 6-Pol.kicad_mod b/Hardware/MV_Abnehmerplatine/Symbol_Library/Micro-Mate-N-Lok.pretty/Micro Mate-N-Lok 6-Pol.kicad_mod new file mode 100644 index 0000000..9cf90d3 --- /dev/null +++ b/Hardware/MV_Abnehmerplatine/Symbol_Library/Micro-Mate-N-Lok.pretty/Micro Mate-N-Lok 6-Pol.kicad_mod @@ -0,0 +1,21 @@ +(module "Micro Mate-N-Lok 6-Pol" (layer F.Cu) (tedit 5CEB202F) + (fp_text reference REF** (at -0.005 8.09) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value "Micro Mate-N-Lok 6-Pol" (at 0.005 -6.04) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 0.005 -4.51) (end 11.005 -4.51) (layer F.CrtYd) (width 0.15)) + (fp_line (start 11.005 -4.51) (end 11.005 6.61) (layer F.CrtYd) (width 0.15)) + (fp_line (start 11.005 6.61) (end -11.005 6.6) (layer F.CrtYd) (width 0.15)) + (fp_line (start -11.005 6.6) (end -11.005 -4.51) (layer F.CrtYd) (width 0.15)) + (fp_line (start -11.005 -4.51) (end 0.045 -4.51) (layer F.CrtYd) (width 0.15)) + (pad 1 smd rect (at -7.5 -2.98) (size 1.27 3) (layers F.Cu F.Paste F.Mask)) + (pad 2 smd rect (at -4.5 -2.98) (size 1.27 3) (layers F.Cu F.Paste F.Mask)) + (pad 3 smd rect (at -1.5 -2.98) (size 1.27 3) (layers F.Cu F.Paste F.Mask)) + (pad 4 smd rect (at 1.5 -2.98) (size 1.27 3) (layers F.Cu F.Paste F.Mask)) + (pad 5 smd rect (at 4.5 -2.98) (size 1.27 3) (layers F.Cu F.Paste F.Mask)) + (pad 6 smd rect (at 7.5 -2.98) (size 1.27 3) (layers F.Cu F.Paste F.Mask)) + (pad "" smd rect (at -11.135 2.5) (size 3.5 1.65) (layers F.Cu F.Paste F.Mask)) + (pad "" smd rect (at 11.275 2.5) (size 3.5 1.65) (layers F.Cu F.Paste F.Mask)) +) diff --git a/Hardware/MV_Abnehmerplatine/Symbol_Library/Micro-Mate-N-Lok.pretty/Micro Mate-N-Lok-12pin-2row.kicad_mod b/Hardware/MV_Abnehmerplatine/Symbol_Library/Micro-Mate-N-Lok.pretty/Micro Mate-N-Lok-12pin-2row.kicad_mod new file mode 100644 index 0000000..22fb7bc --- /dev/null +++ b/Hardware/MV_Abnehmerplatine/Symbol_Library/Micro-Mate-N-Lok.pretty/Micro Mate-N-Lok-12pin-2row.kicad_mod @@ -0,0 +1,31 @@ +(footprint "Micro Mate-N-Lok-12pin-2row" (version 20211014) (generator pcbnew) + (layer "F.Cu") + (tedit 628F8DAD) + (attr through_hole) + (fp_text reference "REF**" (at 0 11.16) (layer "F.SilkS") + (effects (font (size 1 1) (thickness 0.15))) + (tstamp e47744b9-0e80-4f40-97a2-e6c666060a7e) + ) + (fp_text value "Micro Mate-N-Lok-12pin-2row" (at 1.6189 -10.6499) (layer "F.Fab") + (effects (font (size 1 1) (thickness 0.15))) + (tstamp e918b919-3275-46f5-9abf-7feb327608c4) + ) + (fp_line (start -11 6.3) (end -11 -6.3) (layer "F.CrtYd") (width 0.15) (tstamp 5af55f91-716b-4e7d-8c75-1fd345b7c35e)) + (fp_line (start -11 -6.3) (end 11 -6.3) (layer "F.CrtYd") (width 0.15) (tstamp 771a40f7-19a7-4bfc-b88f-460c1a7e5602)) + (fp_line (start 11 6.3) (end -11 6.3) (layer "F.CrtYd") (width 0.15) (tstamp 950756d1-03fe-43a0-95e7-909930c47f2a)) + (fp_line (start 11 -6.3) (end 11 6.3) (layer "F.CrtYd") (width 0.15) (tstamp ed5e43c2-1b85-442b-b823-35bf1b456dbf)) + (pad "" smd rect (at -11.135 0) (size 3.5 1.65) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 2c1b1998-f439-4485-b7ce-0b13438f40bf)) + (pad "" smd rect (at 11.275 0) (size 3.5 1.65) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 2e00a52e-9c16-45d3-84a5-a06979b617b4)) + (pad "1" smd rect (at -7.5 -4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 77f36f29-ab03-4c19-9c6a-a2d42f26a525)) + (pad "2" smd rect (at -4.5 -4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 2d1dad02-6a1d-46d3-b854-5aa81ab4f8f5)) + (pad "3" smd rect (at -1.5 -4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 01cf62da-95ed-4a12-955e-985e346f552c)) + (pad "4" smd rect (at 1.5 -4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 41c9c3b8-2883-4fdc-b499-17634b4fcf10)) + (pad "5" smd rect (at 4.5 -4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp bc3b55ee-da4a-47e7-827f-dc787b3d7436)) + (pad "6" smd rect (at 7.5 -4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 210b4586-7fb1-453c-a012-150951ba2378)) + (pad "7" smd rect (at 7.5 4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp ba884cb2-63bf-4c50-8b66-c3860de5c02e)) + (pad "8" smd rect (at 4.5 4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp fd758cad-e0d7-4141-bc52-0b1a72d4a012)) + (pad "9" smd rect (at 1.5 4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 3d65096b-2ccd-4f03-afa3-bd1be62a8c57)) + (pad "10" smd rect (at -1.5 4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 9ef1878b-d9e0-40a1-8a39-790b6c7302c6)) + (pad "11" smd rect (at -4.5 4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 3c048d02-8b0a-4f38-b4ad-44dab638b480)) + (pad "12" smd rect (at -7.5 4.7) (size 1.27 3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 63ec8a7f-f3b0-4fe7-af1e-8a11758001d1)) +) diff --git a/Hardware/MV_Abnehmerplatine/Symbol_Library/Micro-Mate-N-Lok.pretty/Micro-Mate-N-Lok-16pin-2row.kicad_mod b/Hardware/MV_Abnehmerplatine/Symbol_Library/Micro-Mate-N-Lok.pretty/Micro-Mate-N-Lok-16pin-2row.kicad_mod new file mode 100644 index 0000000..0034cd5 --- /dev/null +++ b/Hardware/MV_Abnehmerplatine/Symbol_Library/Micro-Mate-N-Lok.pretty/Micro-Mate-N-Lok-16pin-2row.kicad_mod @@ -0,0 +1,35 @@ +(module Micro-Mate-N-Lok-16pin-2row (layer F.Cu) (tedit 5D12244A) + (fp_text reference REF** (at 0 -5.6) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value Micro-Mate-N-Lok-16pin-2row (at 0 10.3) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 13.5 0) (end 13.5 9) (layer F.CrtYd) (width 0.15)) + (fp_line (start -13.5 0) (end -13.5 9) (layer F.CrtYd) (width 0.15)) + (fp_line (start -13.5 9) (end 13.5 9) (layer F.CrtYd) (width 0.15)) + (fp_line (start -13.5 0) (end -13.5 -4) (layer F.CrtYd) (width 0.15)) + (fp_line (start -13.5 -4) (end 13.5 -4) (layer F.CrtYd) (width 0.15)) + (fp_line (start 13.5 -4) (end 13.5 0.2) (layer F.CrtYd) (width 0.15)) + (fp_line (start -13.7 0.4) (end -13.7 -4.2) (layer F.SilkS) (width 0.15)) + (fp_line (start -13.7 -4.2) (end 13.7 -4.2) (layer F.SilkS) (width 0.15)) + (fp_line (start 13.7 -4.2) (end 13.7 0.4) (layer F.SilkS) (width 0.15)) + (pad 1 thru_hole circle (at -10.5 0) (size 1.8 1.8) (drill 1.02) (layers *.Cu *.Mask)) + (pad 2 thru_hole circle (at -7.5 0) (size 1.8 1.8) (drill 1.02) (layers *.Cu *.Mask)) + (pad 3 thru_hole circle (at -4.5 0) (size 1.8 1.8) (drill 1.02) (layers *.Cu *.Mask)) + (pad 4 thru_hole circle (at -1.5 0) (size 1.8 1.8) (drill 1.02) (layers *.Cu *.Mask)) + (pad 5 thru_hole circle (at 1.5 0) (size 1.8 1.8) (drill 1.02) (layers *.Cu *.Mask)) + (pad 6 thru_hole circle (at 4.5 0) (size 1.8 1.8) (drill 1.02) (layers *.Cu *.Mask)) + (pad 7 thru_hole circle (at 7.5 0) (size 1.8 1.8) (drill 1.02) (layers *.Cu *.Mask)) + (pad 8 thru_hole circle (at 10.5 0) (size 1.8 1.8) (drill 1.02) (layers *.Cu *.Mask)) + (pad 9 thru_hole circle (at 10.5 -3) (size 1.8 1.8) (drill 1.02) (layers *.Cu *.Mask)) + (pad 10 thru_hole circle (at 7.5 -3) (size 1.8 1.8) (drill 1.02) (layers *.Cu *.Mask)) + (pad 11 thru_hole circle (at 4.5 -3) (size 1.8 1.8) (drill 1.02) (layers *.Cu *.Mask)) + (pad 12 thru_hole circle (at 1.5 -3) (size 1.8 1.8) (drill 1.02) (layers *.Cu *.Mask)) + (pad 13 thru_hole circle (at -1.5 -3) (size 1.8 1.8) (drill 1.02) (layers *.Cu *.Mask)) + (pad 14 thru_hole circle (at -4.5 -3) (size 1.8 1.8) (drill 1.02) (layers *.Cu *.Mask)) + (pad 15 thru_hole circle (at -7.5 -3) (size 1.8 1.8) (drill 1.02) (layers *.Cu *.Mask)) + (pad 16 thru_hole circle (at -10.5 -3) (size 1.8 1.8) (drill 1.02) (layers *.Cu *.Mask)) + (pad "" np_thru_hole circle (at -8.34 4.32) (size 3 3) (drill 3) (layers *.Cu *.Mask)) + (pad "" np_thru_hole circle (at 8.34 4.32) (size 3 3) (drill 3) (layers *.Cu *.Mask)) +) diff --git a/Hardware/MV_Abnehmerplatine/Symbol_Library/VTSENS.pretty/533092070.kicad_mod b/Hardware/MV_Abnehmerplatine/Symbol_Library/VTSENS.pretty/533092070.kicad_mod new file mode 100644 index 0000000..32b9aab --- /dev/null +++ b/Hardware/MV_Abnehmerplatine/Symbol_Library/VTSENS.pretty/533092070.kicad_mod @@ -0,0 +1,83 @@ +(footprint "533092070" (version 20221018) (generator pcbnew) + (layer "F.Cu") + (descr "53309-2070-1") + (tags "Connector") + (attr smd) + (fp_text reference "J**" (at 0 0.025) (layer "F.SilkS") + (effects (font (size 1.27 1.27) (thickness 0.254))) + (tstamp 919e8663-a84f-4dd2-bc46-093a7f53954d) + ) + (fp_text value "533092070" (at 0 0.025) (layer "F.SilkS") hide + (effects (font (size 1.27 1.27) (thickness 0.254))) + (tstamp 89d92af0-5e8b-47ea-8e11-d3f414fd9aee) + ) + (fp_text user "${REFERENCE}" (at 0 0.025) (layer "F.Fab") + (effects (font (size 1.27 1.27) (thickness 0.254))) + (tstamp e9f31486-8258-431c-9ede-83c128628222) + ) + (fp_line (start -4.9 -2.1) (end -4.9 2.1) + (stroke (width 0.1) (type solid)) (layer "F.SilkS") (tstamp 87f8644e-08b7-4422-8150-56eff8b3334c)) + (fp_line (start -4.9 2.1) (end -4.2 2.1) + (stroke (width 0.1) (type solid)) (layer "F.SilkS") (tstamp d2c6e0da-670d-4cda-a762-39bad74e7746)) + (fp_line (start -4.8 -2.1) (end -4.9 -2.1) + (stroke (width 0.1) (type solid)) (layer "F.SilkS") (tstamp 0921438d-a04a-4ff3-9db0-ceda801c9a94)) + (fp_line (start -4.2 -2.1) (end -4.8 -2.1) + (stroke (width 0.1) (type solid)) (layer "F.SilkS") (tstamp b7794960-39e8-4745-bde8-fc0775d76e77)) + (fp_line (start 3.6 -3.4) (end 3.6 -3.4) + (stroke (width 0.2) (type solid)) (layer "F.SilkS") (tstamp c4775727-718c-47db-83a2-56194b392939)) + (fp_line (start 3.8 -3.4) (end 3.8 -3.4) + (stroke (width 0.2) (type solid)) (layer "F.SilkS") (tstamp 5405f6f6-a5f4-479c-aa5b-83ab42915348)) + (fp_line (start 4.2 -2.1) (end 4.8 -2.1) + (stroke (width 0.1) (type solid)) (layer "F.SilkS") (tstamp 6d3e72d6-3888-402b-ac42-540e6e36485e)) + (fp_line (start 4.8 -2.1) (end 4.9 -2.1) + (stroke (width 0.1) (type solid)) (layer "F.SilkS") (tstamp 2456b1c6-8703-4bde-a38e-4451d64975a6)) + (fp_line (start 4.9 -2.1) (end 4.9 2.1) + (stroke (width 0.1) (type solid)) (layer "F.SilkS") (tstamp 973914bf-a555-45fb-95b7-e9dc78761de1)) + (fp_line (start 4.9 2.1) (end 4.2 2.1) + (stroke (width 0.1) (type solid)) (layer "F.SilkS") (tstamp 17be2e0e-ce95-463f-9a72-dd269aa247e3)) + (fp_arc (start 3.6 -3.4) (mid 3.7 -3.5) (end 3.8 -3.4) + (stroke (width 0.2) (type solid)) (layer "F.SilkS") (tstamp 2e113605-2100-4a62-b48a-e4dbb7dbbbac)) + (fp_arc (start 3.8 -3.4) (mid 3.7 -3.3) (end 3.6 -3.4) + (stroke (width 0.2) (type solid)) (layer "F.SilkS") (tstamp d9410a35-0e48-40b4-9cd4-2cdfd5836e43)) + (fp_line (start -5.9 -3.925) (end 5.9 -3.925) + (stroke (width 0.1) (type solid)) (layer "F.CrtYd") (tstamp 9d976b57-a5dc-4882-845f-3ed7ce8bb684)) + (fp_line (start -5.9 3.975) (end -5.9 -3.925) + (stroke (width 0.1) (type solid)) (layer "F.CrtYd") (tstamp dc104690-c5ee-42e4-ae24-039ad67c2f09)) + (fp_line (start 5.9 -3.925) (end 5.9 3.975) + (stroke (width 0.1) (type solid)) (layer "F.CrtYd") (tstamp f3cd68bc-7a6c-474a-b06c-c0ca54722af2)) + (fp_line (start 5.9 3.975) (end -5.9 3.975) + (stroke (width 0.1) (type solid)) (layer "F.CrtYd") (tstamp 649705e8-f005-4c04-aa08-e3918a66bdeb)) + (fp_line (start -4.9 -2.1) (end 4.9 -2.1) + (stroke (width 0.2) (type solid)) (layer "F.Fab") (tstamp fa2149c4-b0ed-4f02-ab7f-0c2251e5bd7f)) + (fp_line (start -4.9 2.1) (end -4.9 -2.1) + (stroke (width 0.2) (type solid)) (layer "F.Fab") (tstamp 16f9745c-2044-46cd-be00-85007c5fd17f)) + (fp_line (start 4.9 -2.1) (end 4.9 2.1) + (stroke (width 0.2) (type solid)) (layer "F.Fab") (tstamp d4981bd2-ae2f-4a32-bc51-a657b518ce27)) + (fp_line (start 4.9 2.1) (end -4.9 2.1) + (stroke (width 0.2) (type solid)) (layer "F.Fab") (tstamp 2da1429d-2f7b-4817-a0fc-4ce94507c3dd)) + (pad "1" smd rect (at 3.6 -2.275) (size 0.55 1.3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp b3dfed12-0b00-45b4-a8d0-359b93d36f17)) + (pad "2" smd rect (at 3.6 2.275) (size 0.55 1.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 107150e8-7028-45be-880d-598077f8cdaf)) + (pad "3" smd rect (at 2.8 -2.275) (size 0.55 1.3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 801a151c-41c0-4f5b-a02a-d1c6c048941b)) + (pad "4" smd rect (at 2.8 2.275) (size 0.55 1.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp f814d745-1dc0-4994-a057-cc6258806258)) + (pad "5" smd rect (at 2 -2.275) (size 0.55 1.3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp f51afedf-d6b3-4108-9fb9-67b836abf9d7)) + (pad "6" smd rect (at 2 2.275) (size 0.55 1.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 09731082-8668-4410-be2e-341b1b88517f)) + (pad "7" smd rect (at 1.2 -2.275) (size 0.55 1.3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp f917e655-8e99-40c4-91ff-02f1862213f4)) + (pad "8" smd rect (at 1.2 2.275) (size 0.55 1.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 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rect (at -2 2.275) (size 0.55 1.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 1d40d3c9-1d2f-434a-96e7-5720cdbe4815)) + (pad "17" smd rect (at -2.8 -2.275) (size 0.55 1.3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp d024091e-2037-4689-b0fc-aef501aa67d3)) + (pad "18" smd rect (at -2.8 2.275) (size 0.55 1.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 17b8e640-24b9-441e-bb52-35b9635a9786)) + (pad "19" smd rect (at -3.6 -2.275) (size 0.55 1.3) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp d4636d80-d5b5-440e-904a-4bc604c44e75)) + (pad "20" smd rect (at -3.6 2.275) (size 0.55 1.4) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 365cefc4-b27a-4c91-bfed-a0048d7a0856)) + (model "${KIPRJMOD}/KiCAD_Lib/stp/53309-2070.stp" + (offset (xyz 0 0 2.380000079)) + (scale (xyz 1 1 1)) + (rotate (xyz -90 0 0)) + ) +) diff --git a/Hardware/MV_Abnehmerplatine/Symbol_Library/VTSENS.pretty/Baby_ST_Bond_Pad.kicad_mod b/Hardware/MV_Abnehmerplatine/Symbol_Library/VTSENS.pretty/Baby_ST_Bond_Pad.kicad_mod new file mode 100644 index 0000000..a799444 --- /dev/null +++ b/Hardware/MV_Abnehmerplatine/Symbol_Library/VTSENS.pretty/Baby_ST_Bond_Pad.kicad_mod @@ -0,0 +1,14 @@ +(footprint "Baby_ST_Bond_Pad" (version 20221018) (generator pcbnew) + (layer "F.Cu") + (attr smd) + (fp_text reference "REF**" (at 0 -0.5 unlocked) (layer "F.SilkS") hide + (effects (font (size 1 1) (thickness 0.15))) + (tstamp ca5f4cce-4a31-41de-a930-a7493dd9558b) + ) + (fp_text value "Baby_ST_Bond_Pad" (at 0 1 unlocked) (layer "F.Fab") hide + (effects (font (size 1 1) (thickness 0.15))) + (tstamp 4083a118-43dc-426a-8ba0-30edb80bd58c) + ) + (pad "1" smd roundrect (at 0 0) (size 2.286 1.524) (layers "F.Cu" "F.Mask") (roundrect_rratio 0.25) + (thermal_bridge_angle 45) (tstamp 489159e8-228a-49ef-b8c9-9cc144e3f6f6)) +) diff --git a/Hardware/MV_Abnehmerplatine/Symbol_Library/VTSENS.pretty/SON50P200X200X80-9N.kicad_mod b/Hardware/MV_Abnehmerplatine/Symbol_Library/VTSENS.pretty/SON50P200X200X80-9N.kicad_mod new file mode 100644 index 0000000..e723614 --- /dev/null +++ b/Hardware/MV_Abnehmerplatine/Symbol_Library/VTSENS.pretty/SON50P200X200X80-9N.kicad_mod @@ -0,0 +1,52 @@ +(footprint "SON50P200X200X80-9N" (version 20221018) (generator pcbnew) + (layer "F.Cu") + (descr "WSON-8-") + (tags "Integrated Circuit") + (attr smd) + (fp_text reference "IC**" (at 0 -2.4384) (layer "F.SilkS") + (effects (font (size 1.27 1.27) (thickness 0.254))) + (tstamp 5ca1bf46-849c-4a3c-80f9-4e5a5f421b34) + ) + (fp_text value "SON50P200X200X80-9N" (at 0 0) (layer "F.SilkS") hide + (effects (font (size 1.27 1.27) (thickness 0.254))) + (tstamp 0faa16bf-72b3-4f24-8a0a-35bf9fb32e7c) + ) + (fp_text user "${REFERENCE}" (at 0 2.4892) (layer "F.Fab") + (effects (font (size 1.27 1.27) (thickness 0.254))) + (tstamp b7c74a59-def6-4b91-a5be-2cc426d25188) + ) + (fp_circle (center -1.4 -1.4) (end -1.4 -1.275) + (stroke (width 0.25) (type solid)) (fill none) (layer "F.SilkS") (tstamp 1811ee21-048b-4984-b7c4-82f32f0e1731)) + (fp_line (start -1.625 -1.3) (end 1.625 -1.3) + (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp e32d1711-2847-4e37-a365-d9d63c41e24b)) + (fp_line (start -1.625 1.3) (end -1.625 -1.3) + (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 2c165beb-1302-4433-9492-d7fd87167e0b)) + (fp_line (start 1.625 -1.3) (end 1.625 1.3) + (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 960ff1bc-51df-436f-b509-607fa8d93cb5)) + (fp_line (start 1.625 1.3) (end -1.625 1.3) + (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp f19a16dd-1595-4610-956f-0622c93aa46e)) + (fp_line (start -1 -1) (end 1 -1) + (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp e12c6330-e385-46b2-9440-a61e0f646017)) + (fp_line (start -1 -0.5) (end -0.5 -1) + (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp cd875602-faad-4c47-9291-85c252e6e53b)) + (fp_line (start -1 1) (end -1 -1) + (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 526baa73-29e3-44d8-908d-6ecef880548a)) + (fp_line (start 1 -1) (end 1 1) + (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 21347ff4-fc7d-4db3-a1c7-7f097c1cce20)) + (fp_line (start 1 1) (end -1 1) + (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp a767b35a-b0ec-427b-8022-fd978047235c)) + (pad "1" smd rect (at -1.05 -0.75 90) (size 0.3 0.7) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 9be8c794-303e-4d94-bd05-1e81ae92857e)) + (pad "2" smd rect (at -1.05 -0.25 90) (size 0.3 0.7) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 3d4e05d3-645a-448c-9645-66cc2440c13d)) + (pad "3" smd rect (at -1.05 0.25 90) (size 0.3 0.7) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp ab95ad87-9713-4f47-b057-0446fe683edc)) + (pad "4" smd rect (at -1.05 0.75 90) (size 0.3 0.7) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 3342043c-85c5-46dc-bdd5-90273a3ae4a0)) + (pad "5" smd rect (at 1.05 0.75 90) (size 0.3 0.7) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 1d468ce5-7347-4d10-8b25-6be8259fd785)) + (pad "6" smd rect (at 1.05 0.25 90) (size 0.3 0.7) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp c81a3c5c-499b-4387-bd7c-e19b738d3bd1)) + (pad "7" smd rect (at 1.05 -0.25 90) (size 0.3 0.7) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp bdc42e13-0846-4c5f-bafe-9b6fbe8dd23e)) + (pad "8" smd rect (at 1.05 -0.75 90) (size 0.3 0.7) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp df8de995-e395-418f-9866-cd47bc9a12cd)) + (pad "9" smd rect (at 0 0) (size 1 1.7) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 6e040b39-bbe1-4e73-be7b-fce7c32f071c)) + (model "${KIPRJMOD}/KiCAD_Lib/stp/TMP1075DSGR.stp" + (offset (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) +) diff --git a/Hardware/MV_Abnehmerplatine/fp-lib-table b/Hardware/MV_Abnehmerplatine/fp-lib-table new file mode 100644 index 0000000..26510ef --- /dev/null +++ b/Hardware/MV_Abnehmerplatine/fp-lib-table @@ -0,0 +1,6 @@ +(fp_lib_table + (version 7) + (lib (name "Symbol_Library")(type "KiCad")(uri "${KIPRJMOD}/Symbol_Library")(options "")(descr "")) + (lib (name "MV_Abnehmerplatine")(type "KiCad")(uri "${KIPRJMOD}/Symbol_Library/MV_Abnehmerplatine.pretty")(options "")(descr "")) + (lib (name "FaSTTUBe_logos")(type "KiCad")(uri "${KIPRJMOD}/Symbol_Library/FaSTTUBe_logos.pretty")(options "")(descr "")) +) diff --git a/Hardware/MV_Abnehmerplatine/sym-lib-table b/Hardware/MV_Abnehmerplatine/sym-lib-table new file mode 100644 index 0000000..f26c126 --- /dev/null +++ b/Hardware/MV_Abnehmerplatine/sym-lib-table @@ -0,0 +1,6 @@ +(sym_lib_table + (version 7) + (lib (name "FaSTTUBe_connectors")(type "KiCad")(uri "${KIPRJMOD}/Symbol_Library/FaSTTUBe_connectors.kicad_sym")(options "")(descr "")) + (lib (name "FaSTTUBe_logos")(type "KiCad")(uri "${KIPRJMOD}/Symbol_Library/FaSTTUBe_logos.kicad_sym")(options "")(descr "")) + (lib (name "MV_Abnehmerplatine")(type "KiCad")(uri "${KIPRJMOD}/Symbol_Library/MV_Abnehmerplatine.kicad_sym")(options "")(descr "")) +) diff --git a/Hardware/Other/output-onlinejpgtools1.png b/Hardware/Other/output-onlinejpgtools1.png new file mode 100644 index 0000000..8fe467d Binary files /dev/null and b/Hardware/Other/output-onlinejpgtools1.png differ diff --git a/Hardware/Other/output-onlinejpgtools1.svg b/Hardware/Other/output-onlinejpgtools1.svg new file mode 100644 index 0000000..65168f7 --- /dev/null +++ b/Hardware/Other/output-onlinejpgtools1.svg @@ -0,0 +1,412 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Hardware/Other/output-onlinejpgtools2.svg b/Hardware/Other/output-onlinejpgtools2.svg new file mode 100644 index 0000000..78c99fc --- /dev/null +++ b/Hardware/Other/output-onlinejpgtools2.svg @@ -0,0 +1,395 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Hardware/dxf/FT24-PG-ME-Master-V2.dxf b/Hardware/dxf/FT24-PG-ME-Master-V2.dxf new file mode 100644 index 0000000..6877030 --- /dev/null +++ b/Hardware/dxf/FT24-PG-ME-Master-V2.dxf @@ -0,0 +1,3332 @@ + 0 +SECTION + 2 +HEADER + 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Components~~~
Groups~~~
SMD pads~~~
TH pads~
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diff --git a/LICENSE b/LICENSE new file mode 100644 index 0000000..0f4824f --- /dev/null +++ b/LICENSE @@ -0,0 +1,232 @@ +GNU GENERAL PUBLIC LICENSE +Version 3, 29 June 2007 + +Copyright © 2007 Free Software Foundation, Inc. + +Everyone is permitted to copy and distribute verbatim copies of this license document, but changing it is not allowed. + +Preamble + +The GNU General Public License is a free, copyleft license for software and other kinds of works. + +The licenses for most software and other practical works are designed to take away your freedom to share and change the works. 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Additional Terms. +“Additional permissions” are terms that supplement the terms of this License by making exceptions from one or more of its conditions. Additional permissions that are applicable to the entire Program shall be treated as though they were included in this License, to the extent that they are valid under applicable law. If additional permissions apply only to part of the Program, that part may be used separately under those permissions, but the entire Program remains governed by this License without regard to the additional permissions. + +When you convey a copy of a covered work, you may at your option remove any additional permissions from that copy, or from any part of it. (Additional permissions may be written to require their own removal in certain cases when you modify the work.) You may place additional permissions on material, added by you to a covered work, for which you have or can give appropriate copyright permission. + +Notwithstanding any other provision of this License, for material you add to a covered work, you may (if authorized by the copyright holders of that material) supplement the terms of this License with terms: + + a) Disclaiming warranty or limiting liability differently from the terms of sections 15 and 16 of this License; or + + b) Requiring preservation of specified reasonable legal notices or author attributions in that material or in the Appropriate Legal Notices displayed by works containing it; or + + c) Prohibiting misrepresentation of the origin of that material, or requiring that modified versions of such material be marked in reasonable ways as different from the original version; or + + d) Limiting the use for publicity purposes of names of licensors or authors of the material; or + + e) Declining to grant rights under trademark law for use of some trade names, trademarks, or service marks; or + + f) Requiring indemnification of licensors and authors of that material by anyone who conveys the material (or modified versions of it) with contractual assumptions of liability to the recipient, for any liability that these contractual assumptions directly impose on those licensors and authors. + +All other non-permissive additional terms are considered “further restrictions” within the meaning of section 10. If the Program as you received it, or any part of it, contains a notice stating that it is governed by this License along with a term that is a further restriction, you may remove that term. If a license document contains a further restriction but permits relicensing or conveying under this License, you may add to a covered work material governed by the terms of that license document, provided that the further restriction does not survive such relicensing or conveying. + +If you add terms to a covered work in accord with this section, you must place, in the relevant source files, a statement of the additional terms that apply to those files, or a notice indicating where to find the applicable terms. + +Additional terms, permissive or non-permissive, may be stated in the form of a separately written license, or stated as exceptions; the above requirements apply either way. + +8. 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If your rights have been terminated and not permanently reinstated, you do not qualify to receive new licenses for the same material under section 10. + +9. Acceptance Not Required for Having Copies. +You are not required to accept this License in order to receive or run a copy of the Program. Ancillary propagation of a covered work occurring solely as a consequence of using peer-to-peer transmission to receive a copy likewise does not require acceptance. However, nothing other than this License grants you permission to propagate or modify any covered work. These actions infringe copyright if you do not accept this License. Therefore, by modifying or propagating a covered work, you indicate your acceptance of this License to do so. + +10. Automatic Licensing of Downstream Recipients. +Each time you convey a covered work, the recipient automatically receives a license from the original licensors, to run, modify and propagate that work, subject to this License. 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To “grant” such a patent license to a party means to make such an agreement or commitment not to enforce a patent against the party. + +If you convey a covered work, knowingly relying on a patent license, and the Corresponding Source of the work is not available for anyone to copy, free of charge and under the terms of this License, through a publicly available network server or other readily accessible means, then you must either (1) cause the Corresponding Source to be so available, or (2) arrange to deprive yourself of the benefit of the patent license for this particular work, or (3) arrange, in a manner consistent with the requirements of this License, to extend the patent license to downstream recipients. “Knowingly relying” means you have actual knowledge that, but for the patent license, your conveying the covered work in a country, or your recipient's use of the covered work in a country, would infringe one or more identifiable patents in that country that you have reason to believe are valid. + +If, pursuant to or in connection with a single transaction or arrangement, you convey, or propagate by procuring conveyance of, a covered work, and grant a patent license to some of the parties receiving the covered work authorizing them to use, propagate, modify or convey a specific copy of the covered work, then the patent license you grant is automatically extended to all recipients of the covered work and works based on it. + +A patent license is “discriminatory” if it does not include within the scope of its coverage, prohibits the exercise of, or is conditioned on the non-exercise of one or more of the rights that are specifically granted under this License. You may not convey a covered work if you are a party to an arrangement with a third party that is in the business of distributing software, under which you make payment to the third party based on the extent of your activity of conveying the work, and under which the third party grants, to any of the parties who would receive the covered work from you, a discriminatory patent license (a) in connection with copies of the covered work conveyed by you (or copies made from those copies), or (b) primarily for and in connection with specific products or compilations that contain the covered work, unless you entered into that arrangement, or that patent license was granted, prior to 28 March 2007. + +Nothing in this License shall be construed as excluding or limiting any implied license or other defenses to infringement that may otherwise be available to you under applicable patent law. + +12. No Surrender of Others' Freedom. +If conditions are imposed on you (whether by court order, agreement or otherwise) that contradict the conditions of this License, they do not excuse you from the conditions of this License. If you cannot convey a covered work so as to satisfy simultaneously your obligations under this License and any other pertinent obligations, then as a consequence you may not convey it at all. For example, if you agree to terms that obligate you to collect a royalty for further conveying from those to whom you convey the Program, the only way you could satisfy both those terms and this License would be to refrain entirely from conveying the Program. + +13. Use with the GNU Affero General Public License. +Notwithstanding any other provision of this License, you have permission to link or combine any covered work with a work licensed under version 3 of the GNU Affero General Public License into a single combined work, and to convey the resulting work. The terms of this License will continue to apply to the part which is the covered work, but the special requirements of the GNU Affero General Public License, section 13, concerning interaction through a network will apply to the combination as such. + +14. Revised Versions of this License. +The Free Software Foundation may publish revised and/or new versions of the GNU General Public License from time to time. Such new versions will be similar in spirit to the present version, but may differ in detail to address new problems or concerns. + +Each version is given a distinguishing version number. If the Program specifies that a certain numbered version of the GNU General Public License “or any later version” applies to it, you have the option of following the terms and conditions either of that numbered version or of any later version published by the Free Software Foundation. If the Program does not specify a version number of the GNU General Public License, you may choose any version ever published by the Free Software Foundation. + +If the Program specifies that a proxy can decide which future versions of the GNU General Public License can be used, that proxy's public statement of acceptance of a version permanently authorizes you to choose that version for the Program. + +Later license versions may give you additional or different permissions. However, no additional obligations are imposed on any author or copyright holder as a result of your choosing to follow a later version. + +15. Disclaimer of Warranty. +THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM “AS IS” WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION. + +16. Limitation of Liability. +IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + +17. Interpretation of Sections 15 and 16. +If the disclaimer of warranty and limitation of liability provided above cannot be given local legal effect according to their terms, reviewing courts shall apply local law that most closely approximates an absolute waiver of all civil liability in connection with the Program, unless a warranty or assumption of liability accompanies a copy of the Program in return for a fee. + +END OF TERMS AND CONDITIONS + +How to Apply These Terms to Your New Programs + +If you develop a new program, and you want it to be of the greatest possible use to the public, the best way to achieve this is to make it free software which everyone can redistribute and change under these terms. + +To do so, attach the following notices to the program. It is safest to attach them to the start of each source file to most effectively state the exclusion of warranty; and each file should have at least the “copyright” line and a pointer to where the full notice is found. + + bg-bezeichnung + Copyright (C) 2024 FaSTTUBe + + This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along with this program. If not, see . + +Also add information on how to contact you by electronic and paper mail. + +If the program does terminal interaction, make it output a short notice like this when it starts in an interactive mode: + + bg-bezeichnung Copyright (C) 2024 FaSTTUBe + This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate parts of the General Public License. Of course, your program's commands might be different; for a GUI interface, you would use an “about box”. + +You should also get your employer (if you work as a programmer) or school, if any, to sign a “copyright disclaimer” for the program, if necessary. For more information on this, and how to apply and follow the GNU GPL, see . + +The GNU General Public License does not permit incorporating your program into proprietary programs. If your program is a subroutine library, you may consider it more useful to permit linking proprietary applications with the library. If this is what you want to do, use the GNU Lesser General Public License instead of this License. But first, please read . diff --git a/README.md b/README.md index 0d56359..7c7eb4b 100644 --- a/README.md +++ b/README.md @@ -1,3 +1,3 @@ -# mvbms-test-24 +# MVBMS_FT24 -This is the code for the the MVBMS_TEST_FT24-V1.0 \ No newline at end of file +The PCB responsible for monitoring the 60V battery which powers the powerground fans. \ No newline at end of file diff --git a/Software/.cache/clangd/index/ADBMS_Abstraction.h.44647A90EB5B18C4.idx b/Software/.cache/clangd/index/ADBMS_Abstraction.h.44647A90EB5B18C4.idx new file mode 100644 index 0000000..42e0e70 Binary files /dev/null and b/Software/.cache/clangd/index/ADBMS_Abstraction.h.44647A90EB5B18C4.idx differ diff --git a/Software/.cache/clangd/index/ADBMS_CMD_MAKROS.h.7CB8FC0B9417BC25.idx b/Software/.cache/clangd/index/ADBMS_CMD_MAKROS.h.7CB8FC0B9417BC25.idx new file mode 100644 index 0000000..3b1694f Binary files /dev/null and b/Software/.cache/clangd/index/ADBMS_CMD_MAKROS.h.7CB8FC0B9417BC25.idx differ diff --git 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a/Software/.vscode/c_cpp_properties.json b/Software/.vscode/c_cpp_properties.json new file mode 100644 index 0000000..3119810 --- /dev/null +++ b/Software/.vscode/c_cpp_properties.json @@ -0,0 +1,22 @@ +{ + "configurations": [ + { + "name": "STM32", + "includePath": [ + "Core/Inc", + "Core/Lib/can-halal", + "Drivers/CMSIS/Device/ST/STM32F3xx/Include", + "Drivers/CMSIS/Include", + "Drivers/STM32F3xx_HAL_Driver/Inc", + "Drivers/STM32F3xx_HAL_Driver/Inc/Legacy" + ], + "defines": [ + "STM32F302xC", + "STM32F3xx", + "USE_HAL_DRIVER" + ], + "compilerPath": "/run/current-system/sw/bin/arm-none-eabi-gcc" + } + ], + "version": 4 +} \ No newline at end of file diff --git a/Software/.vscode/launch.json b/Software/.vscode/launch.json new file mode 100644 index 0000000..1598d15 --- /dev/null +++ b/Software/.vscode/launch.json @@ -0,0 +1,32 @@ +{ + "configurations": [ + { + "showDevDebugOutput": "parsed", + "cwd": "${workspaceRoot}", + "executable": "./build/mvbms-test-24.elf", + "name": "Debug STM32", + "request": "launch", + "type": "cortex-debug", + "servertype": "openocd", + "preLaunchTask": "Build STM", + "device": "stm32f302xc.s", + "configFiles": [ + "openocd.cfg" + ] + }, + { + "showDevDebugOutput": "parsed", + "cwd": "${workspaceRoot}", + "executable": "./build/mvbms-test-24.elf", + "name": "Attach STM32", + "request": "attach", + "type": "cortex-debug", + "servertype": "openocd", + "preLaunchTask": "Build STM", + "device": "stm32f302xc.s", + "configFiles": [ + "openocd.cfg" + ] + } + ] +} \ No newline at end of file diff --git a/Software/.vscode/settings.json b/Software/.vscode/settings.json new file mode 100644 index 0000000..67665d6 --- /dev/null +++ b/Software/.vscode/settings.json @@ -0,0 +1,5 @@ +{ + "cortex-debug.armToolchainPath": "/run/current-system/sw/bin", + "cortex-debug.openocdPath": "/run/current-system/sw/bin/openocd", + "makefile.makefilePath": "STM32Make.make" +} \ No newline at end of file diff --git a/Software/.vscode/tasks.json b/Software/.vscode/tasks.json new file mode 100644 index 0000000..39d8d34 --- /dev/null +++ b/Software/.vscode/tasks.json @@ -0,0 +1,50 @@ +{ + "version": "2.0.0", + "tasks": [ + { + "label": "Build STM", + "type": "process", + "command": "${command:stm32-for-vscode.build}", + "options": { + "cwd": "${workspaceRoot}" + }, + "group": { + "kind": "build", + "isDefault": true + }, + "problemMatcher": [ + "$gcc" + ] + }, + { + "label": "Build Clean STM", + "type": "process", + "command": "${command:stm32-for-vscode.cleanBuild}", + "options": { + "cwd": "${workspaceRoot}" + }, + "group": { + "kind": "build", + "isDefault": true + }, + "problemMatcher": [ + "$gcc" + ] + }, + { + "label": "Flash STM", + "type": "process", + "command": "${command:stm32-for-vscode.flash}", + "options": { + "cwd": "${workspaceRoot}" + }, + "group": { + "kind": "build", + "isDefault": true + }, + "problemMatcher": [ + "$gcc" + ] + } + ] +} \ No newline at end of file diff --git a/CHANGELOG.txt b/Software/CHANGELOG.txt similarity index 100% rename from CHANGELOG.txt rename to Software/CHANGELOG.txt diff --git a/Core/Inc/ADBMS_Abstraction.h b/Software/Core/Inc/ADBMS_Abstraction.h similarity index 100% rename from Core/Inc/ADBMS_Abstraction.h rename to Software/Core/Inc/ADBMS_Abstraction.h diff --git a/Core/Inc/ADBMS_CMD_MAKROS.h b/Software/Core/Inc/ADBMS_CMD_MAKROS.h similarity index 100% rename from Core/Inc/ADBMS_CMD_MAKROS.h rename to Software/Core/Inc/ADBMS_CMD_MAKROS.h diff --git a/Core/Inc/ADBMS_LL_Driver.h b/Software/Core/Inc/ADBMS_LL_Driver.h similarity index 100% rename from Core/Inc/ADBMS_LL_Driver.h rename to Software/Core/Inc/ADBMS_LL_Driver.h diff --git a/Core/Inc/AMS_HighLevel.h b/Software/Core/Inc/AMS_HighLevel.h similarity index 100% rename from Core/Inc/AMS_HighLevel.h rename to Software/Core/Inc/AMS_HighLevel.h diff --git a/Core/Inc/PWM_control.h b/Software/Core/Inc/PWM_control.h similarity index 100% rename from Core/Inc/PWM_control.h rename to Software/Core/Inc/PWM_control.h diff --git a/Core/Inc/TMP1075.h b/Software/Core/Inc/TMP1075.h similarity index 100% rename from Core/Inc/TMP1075.h rename to Software/Core/Inc/TMP1075.h diff --git a/Core/Inc/can.h b/Software/Core/Inc/can.h similarity index 100% rename from Core/Inc/can.h rename to Software/Core/Inc/can.h diff --git a/Core/Inc/eeprom.h b/Software/Core/Inc/eeprom.h similarity index 100% rename from Core/Inc/eeprom.h rename to Software/Core/Inc/eeprom.h diff --git a/Core/Inc/errors.h b/Software/Core/Inc/errors.h similarity index 100% rename from Core/Inc/errors.h rename to Software/Core/Inc/errors.h diff --git a/Core/Inc/main.h b/Software/Core/Inc/main.h similarity index 100% rename from Core/Inc/main.h rename to Software/Core/Inc/main.h diff --git a/Core/Inc/soc_estimation.h b/Software/Core/Inc/soc_estimation.h similarity index 100% rename from Core/Inc/soc_estimation.h rename to Software/Core/Inc/soc_estimation.h diff --git a/Core/Inc/state_machine.h b/Software/Core/Inc/state_machine.h similarity index 100% rename from Core/Inc/state_machine.h rename to Software/Core/Inc/state_machine.h diff --git a/Core/Inc/status_LED.h b/Software/Core/Inc/status_LED.h similarity index 100% rename from Core/Inc/status_LED.h rename to Software/Core/Inc/status_LED.h diff --git a/Core/Inc/stm32f3xx_hal_conf.h b/Software/Core/Inc/stm32f3xx_hal_conf.h similarity index 100% rename from Core/Inc/stm32f3xx_hal_conf.h rename to Software/Core/Inc/stm32f3xx_hal_conf.h diff --git a/Core/Inc/stm32f3xx_it.h b/Software/Core/Inc/stm32f3xx_it.h similarity index 100% rename from Core/Inc/stm32f3xx_it.h rename to Software/Core/Inc/stm32f3xx_it.h diff --git a/Software/Core/Lib/can-halal/README.md b/Software/Core/Lib/can-halal/README.md new file mode 100644 index 0000000..1deade1 --- /dev/null +++ b/Software/Core/Lib/can-halal/README.md @@ -0,0 +1,33 @@ +# FaSTTUBe CAN HAL Abstraction Layer + +This repository contains an abstraction layer to provide a simplified & unified +interface to the STM32 bxCAN and FDCAN peripherals. + +## Installation + +Simply add the repository to your `Core/Lib` directory. You can also add it as a +git submodule: + + mkdir -p Core/Lib + cd Core/Lib + git submodule add ssh://git@git.fasttube.de:313/FaSTTUBe/can-halal.git + +The library needs to be told what STM family you're using, so make sure one of +the following symbols is defined when `can-halal.c` is compiled or `can-halal.h` +is included: + +- `STM32F3` +- `STM32H7` + +When using the FDCAN peripheral (H7 series), you also need to define +`FTCAN_NUM_FILTERS` (and set it to the value of "Std Filters Nbr" you configured +in your `.ioc`). + +## Usage + +1. Include `can-halal.h` +2. Call `ftcan_init()` with the appropriate handle +3. Call `ftcan_add_filter()` with all your filters +4. To transmit messages, call `ftcan_transmit()` +5. When a message is received, `ftcan_msg_received_cb()` is called. It has a + default empty implementation, which you can simply override. diff --git a/Software/Core/Lib/can-halal/can-halal.c b/Software/Core/Lib/can-halal/can-halal.c new file mode 100644 index 0000000..a99303a --- /dev/null +++ b/Software/Core/Lib/can-halal/can-halal.c @@ -0,0 +1,273 @@ +#include "can-halal.h" + +#include + +#if defined(FTCAN_IS_BXCAN) +static CAN_HandleTypeDef *hcan; + +HAL_StatusTypeDef ftcan_init(CAN_HandleTypeDef *handle) { + hcan = handle; + + HAL_StatusTypeDef status = + HAL_CAN_ActivateNotification(hcan, CAN_IT_RX_FIFO0_MSG_PENDING); + if (status != HAL_OK) { + return status; + } + + return HAL_CAN_Start(hcan); +} + +HAL_StatusTypeDef ftcan_transmit(uint16_t id, const uint8_t *data, + size_t datalen) { + static CAN_TxHeaderTypeDef header; + header.StdId = id; + header.IDE = CAN_ID_STD; + header.RTR = CAN_RTR_DATA; + header.DLC = datalen; + uint32_t mailbox; + return HAL_CAN_AddTxMessage(hcan, &header, data, &mailbox); +} + +HAL_StatusTypeDef ftcan_add_filter(uint16_t id, uint16_t mask) { + static uint32_t next_filter_no = 0; + static CAN_FilterTypeDef filter; + if (next_filter_no % 2 == 0) { + filter.FilterIdHigh = id << 5; + filter.FilterMaskIdHigh = mask << 5; + filter.FilterIdLow = id << 5; + filter.FilterMaskIdLow = mask << 5; + } else { + // Leave high filter untouched from the last configuration + filter.FilterIdLow = id << 5; + filter.FilterMaskIdLow = mask << 5; + } + filter.FilterFIFOAssignment = CAN_FILTER_FIFO0; + filter.FilterBank = next_filter_no / 2; + if (filter.FilterBank > FTCAN_NUM_FILTERS + 1) { + return HAL_ERROR; + } + filter.FilterMode = CAN_FILTERMODE_IDMASK; + filter.FilterScale = CAN_FILTERSCALE_16BIT; + filter.FilterActivation = CAN_FILTER_ENABLE; + + // Disable slave filters + // TODO: Some STM32 have multiple CAN peripherals, and one uses the slave + // filter bank + filter.SlaveStartFilterBank = FTCAN_NUM_FILTERS; + + HAL_StatusTypeDef status = HAL_CAN_ConfigFilter(hcan, &filter); + if (status == HAL_OK) { + next_filter_no++; + } + return status; +} + +void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *handle) { + if (handle != hcan) { + return; + } + CAN_RxHeaderTypeDef header; + uint8_t data[8]; + if (HAL_CAN_GetRxMessage(hcan, CAN_RX_FIFO0, &header, data) != HAL_OK) { + return; + } + + if (header.IDE != CAN_ID_STD) { + return; + } + + ftcan_msg_received_cb(header.StdId, header.DLC, data); +} +#elif defined(FTCAN_IS_FDCAN) +static FDCAN_HandleTypeDef *hcan; + +HAL_StatusTypeDef ftcan_init(FDCAN_HandleTypeDef *handle) { + hcan = handle; + + HAL_StatusTypeDef status = + HAL_FDCAN_ActivateNotification(hcan, FDCAN_IT_RX_FIFO0_NEW_MESSAGE, 0); + if (status != HAL_OK) { + return status; + } + // Reject non-matching messages + status = + HAL_FDCAN_ConfigGlobalFilter(hcan, FDCAN_REJECT, FDCAN_REJECT, + FDCAN_REJECT_REMOTE, FDCAN_REJECT_REMOTE); + if (status != HAL_OK) { + return status; + } + + return HAL_FDCAN_Start(hcan); +} + +HAL_StatusTypeDef ftcan_transmit(uint16_t id, const uint8_t *data, + size_t datalen) { + static FDCAN_TxHeaderTypeDef header; + header.Identifier = id; + header.IdType = FDCAN_STANDARD_ID; + header.TxFrameType = FDCAN_DATA_FRAME; + switch (datalen) { + case 0: + header.DataLength = FDCAN_DLC_BYTES_0; + break; + case 1: + header.DataLength = FDCAN_DLC_BYTES_1; + break; + case 2: + header.DataLength = FDCAN_DLC_BYTES_2; + break; + case 3: + header.DataLength = FDCAN_DLC_BYTES_3; + break; + case 4: + header.DataLength = FDCAN_DLC_BYTES_4; + break; + case 5: + header.DataLength = FDCAN_DLC_BYTES_5; + break; + case 6: + header.DataLength = FDCAN_DLC_BYTES_6; + break; + case 7: + header.DataLength = FDCAN_DLC_BYTES_7; + break; + case 8: + default: + header.DataLength = FDCAN_DLC_BYTES_8; + break; + } + header.ErrorStateIndicator = FDCAN_ESI_PASSIVE; + header.BitRateSwitch = FDCAN_BRS_OFF; + header.FDFormat = FDCAN_CLASSIC_CAN; + header.TxEventFifoControl = FDCAN_NO_TX_EVENTS; + + // HAL_FDCAN_AddMessageToTxFifoQ doesn't modify the data, but it's not marked + // as const for some reason. + uint8_t *data_nonconst = (uint8_t *)data; + return HAL_FDCAN_AddMessageToTxFifoQ(hcan, &header, data_nonconst); +} + +HAL_StatusTypeDef ftcan_add_filter(uint16_t id, uint16_t mask) { + static uint32_t next_filter_no = 0; + static FDCAN_FilterTypeDef filter; + filter.IdType = FDCAN_STANDARD_ID; + filter.FilterIndex = next_filter_no; + if (filter.FilterIndex > FTCAN_NUM_FILTERS + 1) { + return HAL_ERROR; + } + filter.FilterType = FDCAN_FILTER_MASK; + filter.FilterConfig = FDCAN_FILTER_TO_RXFIFO0; + filter.FilterID1 = id; + filter.FilterID2 = mask; + + HAL_StatusTypeDef status = HAL_FDCAN_ConfigFilter(hcan, &filter); + if (status == HAL_OK) { + next_filter_no++; + } + return status; +} + +void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *handle, + uint32_t RxFifo0ITs) { + if (handle != hcan || (RxFifo0ITs & FDCAN_IT_RX_FIFO0_NEW_MESSAGE) == RESET) { + return; + } + + static FDCAN_RxHeaderTypeDef header; + static uint8_t data[8]; + if (HAL_FDCAN_GetRxMessage(hcan, FDCAN_RX_FIFO0, &header, data) != HAL_OK) { + return; + } + + if (header.FDFormat != FDCAN_CLASSIC_CAN || + header.RxFrameType != FDCAN_DATA_FRAME || + header.IdType != FDCAN_STANDARD_ID) { + return; + } + + size_t datalen; + switch (header.DataLength) { + case FDCAN_DLC_BYTES_0: + datalen = 0; + break; + case FDCAN_DLC_BYTES_1: + datalen = 1; + break; + case FDCAN_DLC_BYTES_2: + datalen = 2; + break; + case FDCAN_DLC_BYTES_3: + datalen = 3; + break; + case FDCAN_DLC_BYTES_4: + datalen = 4; + break; + case FDCAN_DLC_BYTES_5: + datalen = 5; + break; + case FDCAN_DLC_BYTES_6: + datalen = 6; + break; + case FDCAN_DLC_BYTES_7: + datalen = 7; + break; + case FDCAN_DLC_BYTES_8: + datalen = 8; + break; + default: + return; + } + + ftcan_msg_received_cb(header.Identifier, datalen, data); +} +#endif + +__weak void ftcan_msg_received_cb(uint16_t id, size_t datalen, + const uint8_t *data) {} + +uint64_t ftcan_unmarshal_unsigned(const uint8_t **data_ptr, size_t num_bytes) { + if (num_bytes > 8) { + num_bytes = 8; + } + + const uint8_t *data = *data_ptr; + uint64_t result = 0; + for (size_t i = 0; i < num_bytes; i++) { + result <<= 8; + result |= data[i]; + } + *data_ptr += num_bytes; + return result; +} + +int64_t ftcan_unmarshal_signed(const uint8_t **data_ptr, size_t num_bytes) { + if (num_bytes > 8) { + num_bytes = 8; + } + + uint64_t result_unsigned = ftcan_unmarshal_unsigned(data_ptr, num_bytes); + // Sign extend by shifting left, then copying to a signed int and shifting + // back to the right + size_t diff_to_64 = 64 - num_bytes * 8; + result_unsigned <<= diff_to_64; + int64_t result; + memcpy(&result, &result_unsigned, 8); + return result >> diff_to_64; +} + +uint8_t *ftcan_marshal_unsigned(uint8_t *data, uint64_t val, size_t num_bytes) { + if (num_bytes > 8) { + num_bytes = 8; + } + + for (int i = num_bytes - 1; i >= 0; i--) { + data[i] = val & 0xFF; + val >>= 8; + } + + return data + num_bytes; +} + +uint8_t *ftcan_marshal_signed(uint8_t *data, int64_t val, size_t num_bytes) { + return ftcan_marshal_unsigned(data, val, num_bytes); +} diff --git a/Software/Core/Lib/can-halal/can-halal.h b/Software/Core/Lib/can-halal/can-halal.h new file mode 100644 index 0000000..8351424 --- /dev/null +++ b/Software/Core/Lib/can-halal/can-halal.h @@ -0,0 +1,64 @@ +#ifndef CAN_HALAL_H +#define CAN_HALAL_H + +// Define family macros if none are defined and we recognize a chip macro +#if !defined(STM32F3) && !defined(STM32H7) +#if defined(STM32F302x6) || defined(STM32F302x8) || defined(STM32F302xB) || \ + defined(STM32F302xC) +#define STM32F3 +#endif +#if defined(STM32H7A3xx) +#define STM32H7 +#endif +#endif + +#if defined(STM32F3) +#include "stm32f3xx_hal.h" +#define FTCAN_IS_BXCAN +#define FTCAN_NUM_FILTERS 13 +#elif defined(STM32H7) +#include "stm32h7xx_hal.h" +#define FTCAN_IS_FDCAN +#ifndef FTCAN_NUM_FILTERS + #error "Please configure the number of filters in CubeMX, and then add a compiler define for FTCAN_NUM_FILTERS" +#endif +#else +#error "Couldn't detect STM family" +#endif + +#if defined(FTCAN_IS_BXCAN) +HAL_StatusTypeDef ftcan_init(CAN_HandleTypeDef *handle); +#elif defined(FTCAN_IS_FDCAN) +HAL_StatusTypeDef ftcan_init(FDCAN_HandleTypeDef *handle); +#else +#error "Unknown CAN peripheral" +#endif + +HAL_StatusTypeDef ftcan_transmit(uint16_t id, const uint8_t *data, + size_t datalen); + +HAL_StatusTypeDef ftcan_add_filter(uint16_t id, uint16_t mask); + +/** + * Define this function to be notified of incoming CAN messages + */ +void ftcan_msg_received_cb(uint16_t id, size_t datalen, const uint8_t *data); + +/** + * Read num_bytes bytes from a message (unmarshalled network byte order). The + * msg pointer is advanced by the corresponding number of bytes. + * + * Both methods return a 64-bit integer, but you can safely cast it to a smaller + * integer type. + */ +uint64_t ftcan_unmarshal_unsigned(const uint8_t **data, size_t num_bytes); +int64_t ftcan_unmarshal_signed(const uint8_t **data, size_t num_bytes); + +/** + * Write num_bytes to a message (marshalled in network byte order). The pointer + * is advanced by the corresponding number of bytes and returned. + */ +uint8_t *ftcan_marshal_unsigned(uint8_t *data, uint64_t val, size_t num_bytes); +uint8_t *ftcan_marshal_signed(uint8_t *data, int64_t val, size_t num_bytes); + +#endif // CAN_HALAL_H diff --git a/Core/Src/ADBMS_Abstraction.c b/Software/Core/Src/ADBMS_Abstraction.c similarity index 100% rename from Core/Src/ADBMS_Abstraction.c rename to Software/Core/Src/ADBMS_Abstraction.c diff --git a/Core/Src/ADBMS_LL_Driver.c b/Software/Core/Src/ADBMS_LL_Driver.c similarity index 100% rename from Core/Src/ADBMS_LL_Driver.c rename to Software/Core/Src/ADBMS_LL_Driver.c diff --git a/Core/Src/AMS_HighLevel.c b/Software/Core/Src/AMS_HighLevel.c similarity index 100% rename from Core/Src/AMS_HighLevel.c rename to Software/Core/Src/AMS_HighLevel.c diff --git a/Core/Src/PWM_control.c b/Software/Core/Src/PWM_control.c similarity index 100% rename from Core/Src/PWM_control.c rename to Software/Core/Src/PWM_control.c diff --git a/Core/Src/TMP1075.c b/Software/Core/Src/TMP1075.c similarity index 100% rename from Core/Src/TMP1075.c rename to Software/Core/Src/TMP1075.c diff --git a/Core/Src/can.c b/Software/Core/Src/can.c similarity index 93% rename from Core/Src/can.c rename to Software/Core/Src/can.c index 32e8d29..66eb31d 100644 --- a/Core/Src/can.c +++ b/Software/Core/Src/can.c @@ -25,13 +25,14 @@ #define CAN_STATUS_FREQ 1000 #define CAN_LOGGING_FREQ 200 #define CAN_DUMP_FREQ 10 - +// Delay between the resets of last_message +#define CAN_RESET_DELAY 5000 // Max time to wait for CAN messages. If we reach it then we target state is set to STATE_ERROR. -#define CAN_TIMEOUT 5000 +#define CAN_TIMEOUT 10000 uint8_t id_to_log; uint8_t last_message[8]; -uint32_t can_status_timer, can_log_timer, can_timeout_timer; +uint32_t can_status_timer, can_log_timer, can_timeout_timer, can_reset_timer; void can_init(CAN_HandleTypeDef* hcan) { ftcan_init(hcan); @@ -41,7 +42,8 @@ void can_init(CAN_HandleTypeDef* hcan) { can_status_timer = HAL_GetTick() + CAN_STATUS_FREQ; can_log_timer = HAL_GetTick() + CAN_LOGGING_FREQ; can_timeout_timer = HAL_GetTick() + CAN_TIMEOUT; - id_to_log =0; + can_reset_timer = HAL_GetTick() + CAN_RESET_DELAY; + id_to_log = 0; } /* @@ -158,9 +160,9 @@ void can_handle_recieve_command(const uint8_t *data){ } else if (data[0] == 0xF0 && data[1] == 0x00) { sm_handle_ams_in(data); } else if (data[0] == 0xF1 && data[1] == 0x00) { - sm_handle_ams_in(data); + //sm_handle_ams_in(data); } else if (data[0] == 0xFF && data[1] == 0x00) { - sm_handle_ams_in(data); + //sm_handle_ams_in(data); } } @@ -192,6 +194,10 @@ void ftcan_msg_received_cb(uint16_t id, size_t datalen, const uint8_t *data){ if (id == 0x501 && datalen == 2){ can_timeout_timer = HAL_GetTick() + CAN_TIMEOUT; + if (state.current_state == STATE_ERROR){ + last_message[0] = 0; + last_message[1] = 0; + } if (last_message[0] != data[0] || last_message[1] != data[1]){ last_message[0] = data[0]; last_message[1] = data[1]; diff --git a/Core/Src/eeprom.c b/Software/Core/Src/eeprom.c similarity index 100% rename from Core/Src/eeprom.c rename to Software/Core/Src/eeprom.c diff --git a/Core/Src/errors.c b/Software/Core/Src/errors.c similarity index 100% rename from Core/Src/errors.c rename to Software/Core/Src/errors.c diff --git a/Core/Src/main.c b/Software/Core/Src/main.c similarity index 100% rename from Core/Src/main.c rename to Software/Core/Src/main.c diff --git a/Core/Src/soc_estimation.c b/Software/Core/Src/soc_estimation.c similarity index 100% rename from Core/Src/soc_estimation.c rename to Software/Core/Src/soc_estimation.c diff --git a/Core/Src/state_machine.c b/Software/Core/Src/state_machine.c similarity index 98% rename from Core/Src/state_machine.c rename to Software/Core/Src/state_machine.c index 902f9d4..446232e 100644 --- a/Core/Src/state_machine.c +++ b/Software/Core/Src/state_machine.c @@ -19,8 +19,6 @@ #define PRECHARGE_DURATION 8000 // ms // Time to wait for discharge #define DISCHARGE_DURATION 8000 // ms -// Time to wait between closing relays -#define RELAY_CLOSE_WAIT 10 // ms // waiting time between to eeprom writes #define EEPROM_WRITE_FREQ 1000 // how delay between steps of 5 -> 15ms * (100/5) = 300ms @@ -85,7 +83,7 @@ void sm_update(){ RELAY_BAT_SIDE_VOLTAGE = module.auxVoltages[3] * 15.19; // the calculation says the factor is 11. 11.711 yields the better result if (can_timeout_timer < HAL_GetTick()) - state.current_state = state.target_state = STATE_ERROR; + state.current_state = state.target_state = STATE_INACTIVE; /* if (eeprom_timer < HAL_GetTick()){ eeprom_write_status(); @@ -165,9 +163,8 @@ void sm_handle_ams_in(const uint8_t *data){ } break; case 0xF1: // EEPROM - break; if (state.current_state == STATE_INACTIVE) - // can_handle_dump(); + can_handle_dump(); break; case 0xFF: // EMERGENCY SHUTDOWN state.current_state = STATE_DISCHARGE; @@ -254,21 +251,22 @@ void sm_calibrate_powerground(){ } void sm_balancing(){ + uint32_t channels = 0b11111111111111111111111111111100; if (balancing_timer < HAL_GetTick()){ if (balancing_state){ - balancing_timer = HAL_GetTick() + 10000; + balancing_timer = HAL_GetTick() + 30000; uint8_t id_cell_lowest_voltage = 0; uint8_t num_of_cells_to_balance = 0; uint32_t channels = 0; - + for (int i = 0; i < 13; i++) { if (module.cellVoltages[i] < module.cellVoltages[id_cell_lowest_voltage]) id_cell_lowest_voltage = i; } for (int i = 0; i < 13; i++) { - if (module.cellVoltages[i] - 20 < module.cellVoltages[id_cell_lowest_voltage]){ + if (module.cellVoltages[i] - 20 > module.cellVoltages[id_cell_lowest_voltage]){ channels |= 1 << i; num_of_cells_to_balance++; } diff --git a/Core/Src/status_LED.c b/Software/Core/Src/status_LED.c similarity index 100% rename from Core/Src/status_LED.c rename to Software/Core/Src/status_LED.c diff --git a/Core/Src/stm32f3xx_hal_msp.c b/Software/Core/Src/stm32f3xx_hal_msp.c similarity index 100% rename from Core/Src/stm32f3xx_hal_msp.c rename to Software/Core/Src/stm32f3xx_hal_msp.c diff --git a/Core/Src/stm32f3xx_it.c b/Software/Core/Src/stm32f3xx_it.c similarity index 100% rename from Core/Src/stm32f3xx_it.c rename to Software/Core/Src/stm32f3xx_it.c diff --git a/Core/Src/syscalls.c b/Software/Core/Src/syscalls.c similarity index 100% rename from Core/Src/syscalls.c rename to Software/Core/Src/syscalls.c diff --git a/Core/Src/sysmem.c b/Software/Core/Src/sysmem.c similarity index 100% rename from Core/Src/sysmem.c rename to Software/Core/Src/sysmem.c diff --git a/Core/Src/system_stm32f3xx.c b/Software/Core/Src/system_stm32f3xx.c similarity index 100% rename from Core/Src/system_stm32f3xx.c rename to Software/Core/Src/system_stm32f3xx.c diff --git a/Documentation/AT 115A 14S.jpg b/Software/Documentation/AT 115A 14S.jpg similarity index 100% rename from Documentation/AT 115A 14S.jpg rename to Software/Documentation/AT 115A 14S.jpg diff --git a/Documentation/AT 195A 14S.pdf b/Software/Documentation/AT 195A 14S.pdf similarity index 100% rename from Documentation/AT 195A 14S.pdf rename to Software/Documentation/AT 195A 14S.pdf diff --git a/Documentation/State machine diagram.drawio b/Software/Documentation/State machine diagram.drawio similarity index 100% rename from Documentation/State machine diagram.drawio rename to Software/Documentation/State machine diagram.drawio diff --git a/Documentation/State machine diagram.svg b/Software/Documentation/State machine diagram.svg similarity index 100% rename from Documentation/State machine diagram.svg rename to Software/Documentation/State machine diagram.svg diff --git a/Drivers/CMSIS/Core/Include/cmsis_armcc.h b/Software/Drivers/CMSIS/Core/Include/cmsis_armcc.h similarity index 100% rename from Drivers/CMSIS/Core/Include/cmsis_armcc.h rename to Software/Drivers/CMSIS/Core/Include/cmsis_armcc.h diff --git a/Drivers/CMSIS/Core/Include/cmsis_armclang.h b/Software/Drivers/CMSIS/Core/Include/cmsis_armclang.h similarity index 100% rename from Drivers/CMSIS/Core/Include/cmsis_armclang.h rename to Software/Drivers/CMSIS/Core/Include/cmsis_armclang.h diff --git a/Drivers/CMSIS/Core/Include/cmsis_compiler.h b/Software/Drivers/CMSIS/Core/Include/cmsis_compiler.h similarity index 100% rename from Drivers/CMSIS/Core/Include/cmsis_compiler.h rename to Software/Drivers/CMSIS/Core/Include/cmsis_compiler.h diff --git a/Drivers/CMSIS/Core/Include/cmsis_gcc.h b/Software/Drivers/CMSIS/Core/Include/cmsis_gcc.h similarity index 100% rename from Drivers/CMSIS/Core/Include/cmsis_gcc.h rename to Software/Drivers/CMSIS/Core/Include/cmsis_gcc.h diff --git a/Drivers/CMSIS/Core/Include/cmsis_iccarm.h b/Software/Drivers/CMSIS/Core/Include/cmsis_iccarm.h similarity index 100% rename from Drivers/CMSIS/Core/Include/cmsis_iccarm.h rename to Software/Drivers/CMSIS/Core/Include/cmsis_iccarm.h diff --git a/Drivers/CMSIS/Core/Include/cmsis_version.h b/Software/Drivers/CMSIS/Core/Include/cmsis_version.h similarity index 100% rename from Drivers/CMSIS/Core/Include/cmsis_version.h rename to Software/Drivers/CMSIS/Core/Include/cmsis_version.h diff --git a/Drivers/CMSIS/Core/Include/core_armv8mbl.h b/Software/Drivers/CMSIS/Core/Include/core_armv8mbl.h similarity index 100% rename from Drivers/CMSIS/Core/Include/core_armv8mbl.h rename to Software/Drivers/CMSIS/Core/Include/core_armv8mbl.h diff --git a/Drivers/CMSIS/Core/Include/core_armv8mml.h b/Software/Drivers/CMSIS/Core/Include/core_armv8mml.h similarity index 100% rename from Drivers/CMSIS/Core/Include/core_armv8mml.h rename to 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a/Drivers/CMSIS/Core/Include/core_cm3.h b/Software/Drivers/CMSIS/Core/Include/core_cm3.h similarity index 100% rename from Drivers/CMSIS/Core/Include/core_cm3.h rename to Software/Drivers/CMSIS/Core/Include/core_cm3.h diff --git a/Drivers/CMSIS/Core/Include/core_cm33.h b/Software/Drivers/CMSIS/Core/Include/core_cm33.h similarity index 100% rename from Drivers/CMSIS/Core/Include/core_cm33.h rename to Software/Drivers/CMSIS/Core/Include/core_cm33.h diff --git a/Drivers/CMSIS/Core/Include/core_cm4.h b/Software/Drivers/CMSIS/Core/Include/core_cm4.h similarity index 100% rename from Drivers/CMSIS/Core/Include/core_cm4.h rename to Software/Drivers/CMSIS/Core/Include/core_cm4.h diff --git a/Drivers/CMSIS/Core/Include/core_cm7.h b/Software/Drivers/CMSIS/Core/Include/core_cm7.h similarity index 100% rename from Drivers/CMSIS/Core/Include/core_cm7.h rename to Software/Drivers/CMSIS/Core/Include/core_cm7.h diff --git a/Drivers/CMSIS/Core/Include/core_sc000.h b/Software/Drivers/CMSIS/Core/Include/core_sc000.h similarity index 100% rename from Drivers/CMSIS/Core/Include/core_sc000.h rename to Software/Drivers/CMSIS/Core/Include/core_sc000.h diff --git a/Drivers/CMSIS/Core/Include/core_sc300.h b/Software/Drivers/CMSIS/Core/Include/core_sc300.h similarity index 100% rename from Drivers/CMSIS/Core/Include/core_sc300.h rename to Software/Drivers/CMSIS/Core/Include/core_sc300.h diff --git a/Drivers/CMSIS/Core/Include/mpu_armv7.h b/Software/Drivers/CMSIS/Core/Include/mpu_armv7.h similarity index 100% rename from Drivers/CMSIS/Core/Include/mpu_armv7.h rename to Software/Drivers/CMSIS/Core/Include/mpu_armv7.h diff --git a/Drivers/CMSIS/Core/Include/mpu_armv8.h b/Software/Drivers/CMSIS/Core/Include/mpu_armv8.h similarity index 100% rename from Drivers/CMSIS/Core/Include/mpu_armv8.h rename to Software/Drivers/CMSIS/Core/Include/mpu_armv8.h diff --git a/Drivers/CMSIS/Core/Include/tz_context.h b/Software/Drivers/CMSIS/Core/Include/tz_context.h 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b/Software/Drivers/CMSIS/Core_A/Include/cmsis_armclang.h similarity index 100% rename from Drivers/CMSIS/Core_A/Include/cmsis_armclang.h rename to Software/Drivers/CMSIS/Core_A/Include/cmsis_armclang.h diff --git a/Drivers/CMSIS/Core_A/Include/cmsis_compiler.h b/Software/Drivers/CMSIS/Core_A/Include/cmsis_compiler.h similarity index 100% rename from Drivers/CMSIS/Core_A/Include/cmsis_compiler.h rename to Software/Drivers/CMSIS/Core_A/Include/cmsis_compiler.h diff --git a/Drivers/CMSIS/Core_A/Include/cmsis_cp15.h b/Software/Drivers/CMSIS/Core_A/Include/cmsis_cp15.h similarity index 100% rename from Drivers/CMSIS/Core_A/Include/cmsis_cp15.h rename to Software/Drivers/CMSIS/Core_A/Include/cmsis_cp15.h diff --git a/Drivers/CMSIS/Core_A/Include/cmsis_gcc.h b/Software/Drivers/CMSIS/Core_A/Include/cmsis_gcc.h similarity index 100% rename from Drivers/CMSIS/Core_A/Include/cmsis_gcc.h rename to Software/Drivers/CMSIS/Core_A/Include/cmsis_gcc.h diff --git a/Drivers/CMSIS/Core_A/Include/cmsis_iccarm.h b/Software/Drivers/CMSIS/Core_A/Include/cmsis_iccarm.h similarity index 100% rename from Drivers/CMSIS/Core_A/Include/cmsis_iccarm.h rename to Software/Drivers/CMSIS/Core_A/Include/cmsis_iccarm.h diff --git a/Drivers/CMSIS/Core_A/Include/core_ca.h b/Software/Drivers/CMSIS/Core_A/Include/core_ca.h similarity index 100% rename from Drivers/CMSIS/Core_A/Include/core_ca.h rename to Software/Drivers/CMSIS/Core_A/Include/core_ca.h diff --git a/Drivers/CMSIS/Core_A/Include/irq_ctrl.h b/Software/Drivers/CMSIS/Core_A/Include/irq_ctrl.h similarity index 100% rename from Drivers/CMSIS/Core_A/Include/irq_ctrl.h rename to Software/Drivers/CMSIS/Core_A/Include/irq_ctrl.h diff --git a/Drivers/CMSIS/Core_A/Source/irq_ctrl_gic.c b/Software/Drivers/CMSIS/Core_A/Source/irq_ctrl_gic.c similarity index 100% rename from Drivers/CMSIS/Core_A/Source/irq_ctrl_gic.c rename to Software/Drivers/CMSIS/Core_A/Source/irq_ctrl_gic.c diff --git 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to Software/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/matrix_tests/matrix_test_group.h diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/matrix_tests/matrix_tests.h b/Software/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/matrix_tests/matrix_tests.h similarity index 100% rename from Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/matrix_tests/matrix_tests.h rename to Software/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/matrix_tests/matrix_tests.h diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/statistics_tests/statistics_templates.h b/Software/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/statistics_tests/statistics_templates.h similarity index 100% rename from Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/statistics_tests/statistics_templates.h rename to Software/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/statistics_tests/statistics_templates.h diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/inc/statistics_tests/statistics_test_data.h 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b/Software/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/fixed_to_fixed.c similarity index 100% rename from Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/fixed_to_fixed.c rename to Software/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/fixed_to_fixed.c diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/fixed_to_float.c b/Software/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/fixed_to_float.c similarity index 100% rename from Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/fixed_to_float.c rename to Software/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/fixed_to_float.c diff --git a/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/float_to_fixed.c b/Software/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/float_to_fixed.c similarity index 100% rename from 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rename to Software/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/Abstract.txt diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/arm_class_marks_example_f32.c b/Software/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/arm_class_marks_example_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/arm_class_marks_example_f32.c rename to Software/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/arm_class_marks_example_f32.c diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/Abstract.txt b/Software/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/Abstract.txt similarity index 100% rename from Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/Abstract.txt rename to Software/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/Abstract.txt diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/arm_convolution_example_f32.c b/Software/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/arm_convolution_example_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/arm_convolution_example_f32.c rename to Software/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/arm_convolution_example_f32.c diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/math_helper.c b/Software/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/math_helper.c similarity index 100% rename from Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/math_helper.c rename to Software/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/math_helper.c diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/math_helper.h b/Software/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/math_helper.h similarity index 100% rename from Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/math_helper.h rename to Software/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/math_helper.h diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/Abstract.txt b/Software/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/Abstract.txt similarity index 100% rename from Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/Abstract.txt rename to Software/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/Abstract.txt diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/arm_dotproduct_example_f32.c b/Software/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/arm_dotproduct_example_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/arm_dotproduct_example_f32.c rename to Software/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/arm_dotproduct_example_f32.c diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/Abstract.txt b/Software/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/Abstract.txt similarity index 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b/Software/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/Abstract.txt similarity index 100% rename from Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/Abstract.txt rename to Software/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/Abstract.txt diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_data.c b/Software/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_data.c similarity index 100% rename from Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_data.c rename to Software/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_data.c diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_example_f32.c b/Software/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_example_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_example_f32.c rename to Software/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_example_f32.c diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/math_helper.c b/Software/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/math_helper.c similarity index 100% rename from Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/math_helper.c rename to Software/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/math_helper.c diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/math_helper.h b/Software/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/math_helper.h similarity index 100% rename from Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/math_helper.h rename to Software/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/math_helper.h diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/Abstract.txt b/Software/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/Abstract.txt similarity index 100% rename from Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/Abstract.txt rename to Software/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/Abstract.txt diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_data.c b/Software/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_data.c similarity index 100% rename from Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_data.c rename to Software/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_data.c diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_example_q31.c b/Software/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_example_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_example_q31.c rename to Software/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_example_q31.c diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/math_helper.c b/Software/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/math_helper.c similarity index 100% rename from Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/math_helper.c rename to Software/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/math_helper.c diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/math_helper.h b/Software/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/math_helper.h similarity index 100% rename from Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/math_helper.h rename to Software/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/math_helper.h diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/Abstract.txt b/Software/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/Abstract.txt similarity index 100% rename from Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/Abstract.txt rename to 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b/Software/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/math_helper.c similarity index 100% rename from Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/math_helper.c rename to Software/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/math_helper.c diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/math_helper.h b/Software/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/math_helper.h similarity index 100% rename from Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/math_helper.h rename to Software/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/math_helper.h diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/Abstract.txt b/Software/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/Abstract.txt similarity index 100% rename from Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/Abstract.txt rename to Software/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/Abstract.txt diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/arm_matrix_example_f32.c b/Software/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/arm_matrix_example_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/arm_matrix_example_f32.c rename to Software/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/arm_matrix_example_f32.c diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.c b/Software/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.c similarity index 100% rename from Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.c rename to Software/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.c diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.h b/Software/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.h similarity index 100% rename from Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.h rename to Software/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.h diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/Abstract.txt b/Software/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/Abstract.txt similarity index 100% rename from Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/Abstract.txt rename to Software/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/Abstract.txt diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_data.c b/Software/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_data.c similarity index 100% rename from Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_data.c rename to Software/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_data.c diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_example_f32.c b/Software/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_example_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_example_f32.c rename to Software/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_example_f32.c diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/math_helper.c b/Software/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/math_helper.c similarity index 100% rename from Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/math_helper.c rename to Software/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/math_helper.c diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/math_helper.h b/Software/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/math_helper.h similarity index 100% rename from Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/math_helper.h rename to Software/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/math_helper.h diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/Abstract.txt b/Software/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/Abstract.txt similarity index 100% rename from Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/Abstract.txt rename to Software/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/Abstract.txt diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/arm_sin_cos_example_f32.c b/Software/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/arm_sin_cos_example_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/arm_sin_cos_example_f32.c rename to Software/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/arm_sin_cos_example_f32.c diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/Abstract.txt b/Software/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/Abstract.txt similarity index 100% rename from Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/Abstract.txt rename to Software/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/Abstract.txt diff --git a/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/arm_variance_example_f32.c b/Software/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/arm_variance_example_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/arm_variance_example_f32.c rename to Software/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/arm_variance_example_f32.c diff --git a/Drivers/CMSIS/DSP/Include/arm_common_tables.h b/Software/Drivers/CMSIS/DSP/Include/arm_common_tables.h similarity index 100% rename from Drivers/CMSIS/DSP/Include/arm_common_tables.h rename to Software/Drivers/CMSIS/DSP/Include/arm_common_tables.h diff --git a/Drivers/CMSIS/DSP/Include/arm_const_structs.h b/Software/Drivers/CMSIS/DSP/Include/arm_const_structs.h similarity index 100% rename from Drivers/CMSIS/DSP/Include/arm_const_structs.h rename to Software/Drivers/CMSIS/DSP/Include/arm_const_structs.h diff --git a/Drivers/CMSIS/DSP/Include/arm_math.h b/Software/Drivers/CMSIS/DSP/Include/arm_math.h similarity index 100% rename from Drivers/CMSIS/DSP/Include/arm_math.h rename to Software/Drivers/CMSIS/DSP/Include/arm_math.h diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_f32.c b/Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_f32.c rename to Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_f32.c diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q15.c b/Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q15.c rename to Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q15.c diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q31.c b/Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q31.c rename to Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q31.c diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q7.c b/Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q7.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q7.c rename to Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q7.c diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f32.c b/Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f32.c rename to Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f32.c diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q15.c b/Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q15.c rename to Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q15.c diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q31.c b/Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q31.c rename to Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q31.c diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q7.c b/Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q7.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q7.c rename to Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q7.c diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f32.c b/Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f32.c rename to Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f32.c diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q15.c b/Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q15.c rename to Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q15.c diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q31.c b/Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q31.c rename to Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q31.c diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q7.c b/Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q7.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q7.c rename to Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q7.c diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f32.c b/Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f32.c rename to Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f32.c diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q15.c b/Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q15.c rename to Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q15.c diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q31.c b/Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q31.c rename to Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q31.c diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q7.c b/Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q7.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q7.c rename to Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q7.c diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f32.c b/Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f32.c rename to Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f32.c diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q15.c b/Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q15.c rename to Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q15.c diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q31.c b/Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q31.c rename to Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q31.c diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q7.c b/Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q7.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q7.c rename to Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q7.c diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f32.c b/Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f32.c rename to Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f32.c diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q15.c b/Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q15.c rename to Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q15.c diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q31.c b/Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q31.c rename to Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q31.c diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q7.c b/Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q7.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q7.c rename to Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q7.c diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f32.c b/Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f32.c rename to Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f32.c diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q15.c b/Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q15.c rename to Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q15.c diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q31.c b/Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q31.c rename to Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q31.c diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q7.c b/Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q7.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q7.c rename to Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q7.c diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q15.c b/Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q15.c rename to Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q15.c diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q31.c b/Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q31.c rename to Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q31.c diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q7.c b/Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q7.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q7.c rename to Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q7.c diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f32.c b/Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f32.c rename to Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f32.c diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q15.c b/Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q15.c rename to Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q15.c diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q31.c b/Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q31.c rename to Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q31.c diff --git a/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q7.c b/Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q7.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q7.c rename to Software/Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q7.c diff --git a/Drivers/CMSIS/DSP/Source/CommonTables/arm_common_tables.c b/Software/Drivers/CMSIS/DSP/Source/CommonTables/arm_common_tables.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/CommonTables/arm_common_tables.c rename to Software/Drivers/CMSIS/DSP/Source/CommonTables/arm_common_tables.c diff --git a/Drivers/CMSIS/DSP/Source/CommonTables/arm_const_structs.c b/Software/Drivers/CMSIS/DSP/Source/CommonTables/arm_const_structs.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/CommonTables/arm_const_structs.c rename to Software/Drivers/CMSIS/DSP/Source/CommonTables/arm_const_structs.c diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c b/Software/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c rename to Software/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c b/Software/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c rename to Software/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c b/Software/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c rename to Software/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c b/Software/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c rename to Software/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c b/Software/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c rename to Software/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c b/Software/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c rename to Software/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c b/Software/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c rename to Software/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c b/Software/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c rename to Software/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c b/Software/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c rename to Software/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c b/Software/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c rename to Software/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c b/Software/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c rename to Software/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c b/Software/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c rename to Software/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c b/Software/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c rename to Software/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c b/Software/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c rename to Software/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c b/Software/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c rename to Software/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c b/Software/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c rename to Software/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c b/Software/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c rename to Software/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c diff --git a/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c b/Software/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c rename to Software/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c diff --git a/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_f32.c b/Software/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_f32.c rename to Software/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_f32.c diff --git a/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q15.c b/Software/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q15.c rename to Software/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q15.c diff --git a/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q31.c b/Software/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q31.c rename to Software/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q31.c diff --git a/Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_f32.c 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b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q15.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q15.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q31.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q31.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q31.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q7.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q7.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q7.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q7.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q15.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q15.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q15.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q31.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q31.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q31.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q7.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q7.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q7.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q7.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_f32.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_f32.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_f32.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_opt_q15.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_opt_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_opt_q15.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_opt_q15.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q15.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q15.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q15.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q31.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q31.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q31.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q15.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q15.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q15.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q7.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q7.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q7.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q7.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q15.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q15.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q15.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q31.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q31.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q31.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q7.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q7.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q7.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q7.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_f32.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_f32.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_f32.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_f32.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_f32.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_f32.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q15.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q15.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q15.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q31.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q31.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q31.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q15.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q15.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q15.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q31.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q31.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q31.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_f32.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_f32.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_f32.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q15.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q15.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q15.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q31.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q31.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q31.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_f32.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_f32.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_f32.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q15.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q15.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q15.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q31.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q31.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q31.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q7.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q7.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q7.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q7.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_f32.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_f32.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_f32.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q15.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q15.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q15.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q31.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q31.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q31.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_f32.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_f32.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_f32.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_f32.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_f32.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_f32.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q15.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q15.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q15.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q31.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q31.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q31.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q15.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q15.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q15.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q31.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q31.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q31.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q15.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q15.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q15.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q31.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q31.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q31.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q7.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q7.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q7.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q7.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_f32.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_f32.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_f32.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_f32.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_f32.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_f32.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q15.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q15.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q15.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q31.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q31.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q31.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q7.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q7.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q7.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q7.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q15.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q15.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q15.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q31.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q31.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q31.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q7.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q7.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q7.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q7.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_f32.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_f32.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_f32.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_f32.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_f32.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_f32.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q15.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q15.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q15.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q31.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q31.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q31.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q15.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q15.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q15.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q31.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q31.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q31.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_f32.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_f32.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_f32.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_f32.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_f32.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_f32.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q15.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q15.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q15.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q31.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q31.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q31.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_f32.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_f32.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_f32.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_f32.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_f32.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_f32.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q15.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q15.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q15.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q31.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q31.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q31.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q15.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q15.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q15.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q31.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q31.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q31.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q15.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q15.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q15.c diff --git a/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q31.c b/Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q31.c rename to Software/Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q31.c diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_f32.c b/Software/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_f32.c rename to Software/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_f32.c diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q15.c b/Software/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q15.c rename to Software/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q15.c diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q31.c b/Software/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q31.c rename to Software/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q31.c diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_f32.c b/Software/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_f32.c rename to Software/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_f32.c diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q15.c b/Software/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q15.c rename to Software/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q15.c diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q31.c b/Software/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q31.c rename to Software/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q31.c diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_f32.c b/Software/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_f32.c rename to Software/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_f32.c diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q15.c b/Software/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q15.c rename to Software/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q15.c diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q31.c b/Software/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q31.c rename to Software/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q31.c diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f32.c b/Software/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f32.c rename to Software/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f32.c diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f64.c b/Software/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f64.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f64.c rename to Software/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f64.c diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_f32.c b/Software/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_f32.c rename to Software/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_f32.c diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q15.c b/Software/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q15.c rename to Software/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q15.c diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q31.c b/Software/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q31.c rename to Software/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q31.c diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q15.c b/Software/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q15.c rename to Software/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q15.c diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q31.c b/Software/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q31.c rename to Software/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q31.c diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_f32.c b/Software/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_f32.c rename to Software/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_f32.c diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q15.c b/Software/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q15.c rename to Software/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q15.c diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q31.c b/Software/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q31.c rename to Software/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q31.c diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_f32.c b/Software/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_f32.c rename to Software/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_f32.c diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q15.c b/Software/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q15.c rename to Software/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q15.c diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q31.c b/Software/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q31.c rename to Software/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q31.c diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_f32.c b/Software/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_f32.c rename to Software/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_f32.c diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q15.c b/Software/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q15.c rename to Software/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q15.c diff --git a/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q31.c b/Software/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q31.c rename to Software/Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q31.c diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_f32.c b/Software/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_f32.c rename to Software/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_f32.c diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q15.c b/Software/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q15.c rename to Software/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q15.c diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q31.c b/Software/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q31.c rename to Software/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q31.c diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q7.c b/Software/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q7.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q7.c rename to Software/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q7.c diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_f32.c b/Software/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_f32.c rename to Software/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_f32.c diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q15.c b/Software/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q15.c rename to Software/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q15.c diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q31.c b/Software/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q31.c rename to Software/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q31.c diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q7.c b/Software/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q7.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q7.c rename to Software/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q7.c diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_f32.c b/Software/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_f32.c rename to Software/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_f32.c diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q15.c b/Software/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q15.c rename to Software/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q15.c diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q31.c b/Software/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q31.c rename to Software/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q31.c diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q7.c b/Software/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q7.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q7.c rename to Software/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q7.c diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_f32.c b/Software/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_f32.c rename to Software/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_f32.c diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q15.c b/Software/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q15.c rename to Software/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q15.c diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q31.c b/Software/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q31.c rename to Software/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q31.c diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q7.c b/Software/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q7.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q7.c rename to Software/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q7.c diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_f32.c b/Software/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_f32.c rename to Software/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_f32.c diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q15.c b/Software/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q15.c rename to Software/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q15.c diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q31.c b/Software/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q31.c rename to Software/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q31.c diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_f32.c b/Software/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_f32.c rename to Software/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_f32.c diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q15.c b/Software/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q15.c rename to Software/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q15.c diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q31.c b/Software/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q31.c rename to Software/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q31.c diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_f32.c b/Software/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_f32.c rename to Software/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_f32.c diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q15.c b/Software/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q15.c rename to Software/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q15.c diff --git a/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q31.c b/Software/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q31.c rename to Software/Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q31.c diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c b/Software/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c rename to Software/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c b/Software/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c rename to Software/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c b/Software/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c rename to Software/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c b/Software/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c rename to Software/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c b/Software/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c rename to Software/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c b/Software/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c rename to Software/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c b/Software/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c rename to Software/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c b/Software/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c rename to Software/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c b/Software/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c rename to Software/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c b/Software/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c rename to Software/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c b/Software/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c rename to Software/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c b/Software/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c rename to Software/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c b/Software/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c rename to Software/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c b/Software/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c rename to Software/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c b/Software/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c rename to Software/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c b/Software/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c rename to Software/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c b/Software/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c rename to Software/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c b/Software/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c rename to Software/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c b/Software/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c rename to Software/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c diff --git a/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c b/Software/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c rename to Software/Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal.c b/Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal.c rename to Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal.c diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal2.S b/Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal2.S similarity index 100% rename from Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal2.S rename to Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal2.S diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_f32.c b/Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_f32.c rename to Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_f32.c diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q15.c b/Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q15.c rename to Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q15.c diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q31.c b/Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q31.c rename to Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q31.c diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_f32.c b/Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_f32.c rename to Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_f32.c diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_f32.c b/Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_f32.c rename to Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_f32.c diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q15.c b/Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q15.c rename to Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q15.c diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q31.c b/Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q31.c rename to Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q31.c diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q15.c b/Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q15.c rename to Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q15.c diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q31.c b/Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q31.c rename to Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q31.c diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_f32.c b/Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_f32.c rename to Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_f32.c diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_f32.c b/Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_f32.c rename to Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_f32.c diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q15.c b/Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q15.c rename to Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q15.c diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q31.c b/Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q31.c rename to Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q31.c diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q15.c b/Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q15.c rename to Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q15.c diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q31.c b/Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q31.c rename to Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q31.c diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix8_f32.c b/Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix8_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix8_f32.c rename to Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix8_f32.c diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_f32.c b/Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_f32.c rename to Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_f32.c diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_f32.c b/Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_f32.c rename to Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_f32.c diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q15.c b/Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q15.c rename to Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q15.c diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q31.c b/Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q31.c rename to Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q31.c diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q15.c b/Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q15.c rename to Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q15.c diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q31.c b/Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q31.c rename to Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q31.c diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_f32.c b/Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_f32.c rename to Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_f32.c diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_f32.c b/Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_f32.c rename to Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_f32.c diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_init_f32.c b/Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_init_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_init_f32.c rename to Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_init_f32.c diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_f32.c b/Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_f32.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_f32.c rename to Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_f32.c diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q15.c b/Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q15.c rename to Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q15.c diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q31.c b/Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q31.c rename to Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q31.c diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q15.c b/Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q15.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q15.c rename to Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q15.c diff --git a/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q31.c b/Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q31.c similarity index 100% rename from Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q31.c rename to Software/Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q31.c diff --git a/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h b/Software/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h similarity index 100% rename from Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h rename to Software/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h diff --git a/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h b/Software/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h similarity index 100% rename from Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h rename to Software/Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h diff --git a/Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h b/Software/Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h similarity index 100% rename from Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h rename to Software/Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h diff --git a/Drivers/CMSIS/Device/ST/STM32F3xx/LICENSE.txt b/Software/Drivers/CMSIS/Device/ST/STM32F3xx/LICENSE.txt similarity index 100% rename from Drivers/CMSIS/Device/ST/STM32F3xx/LICENSE.txt rename to Software/Drivers/CMSIS/Device/ST/STM32F3xx/LICENSE.txt diff --git a/Drivers/CMSIS/Include/cmsis_armcc.h b/Software/Drivers/CMSIS/Include/cmsis_armcc.h similarity index 100% rename from Drivers/CMSIS/Include/cmsis_armcc.h rename to Software/Drivers/CMSIS/Include/cmsis_armcc.h diff --git a/Drivers/CMSIS/Include/cmsis_armclang.h b/Software/Drivers/CMSIS/Include/cmsis_armclang.h similarity index 100% rename from Drivers/CMSIS/Include/cmsis_armclang.h rename to Software/Drivers/CMSIS/Include/cmsis_armclang.h diff --git a/Drivers/CMSIS/Include/cmsis_compiler.h b/Software/Drivers/CMSIS/Include/cmsis_compiler.h similarity index 100% rename from Drivers/CMSIS/Include/cmsis_compiler.h rename to Software/Drivers/CMSIS/Include/cmsis_compiler.h diff --git a/Drivers/CMSIS/Include/cmsis_gcc.h b/Software/Drivers/CMSIS/Include/cmsis_gcc.h similarity index 100% rename from Drivers/CMSIS/Include/cmsis_gcc.h rename to Software/Drivers/CMSIS/Include/cmsis_gcc.h diff --git a/Drivers/CMSIS/Include/cmsis_iccarm.h b/Software/Drivers/CMSIS/Include/cmsis_iccarm.h similarity index 100% rename from Drivers/CMSIS/Include/cmsis_iccarm.h rename to Software/Drivers/CMSIS/Include/cmsis_iccarm.h diff --git a/Drivers/CMSIS/Include/cmsis_version.h b/Software/Drivers/CMSIS/Include/cmsis_version.h similarity index 100% rename from Drivers/CMSIS/Include/cmsis_version.h rename to Software/Drivers/CMSIS/Include/cmsis_version.h diff --git a/Drivers/CMSIS/Include/core_armv8mbl.h b/Software/Drivers/CMSIS/Include/core_armv8mbl.h similarity index 100% rename from Drivers/CMSIS/Include/core_armv8mbl.h rename to Software/Drivers/CMSIS/Include/core_armv8mbl.h diff --git a/Drivers/CMSIS/Include/core_armv8mml.h b/Software/Drivers/CMSIS/Include/core_armv8mml.h similarity index 100% rename from Drivers/CMSIS/Include/core_armv8mml.h rename to Software/Drivers/CMSIS/Include/core_armv8mml.h diff --git a/Drivers/CMSIS/Include/core_cm0.h b/Software/Drivers/CMSIS/Include/core_cm0.h similarity index 100% rename from Drivers/CMSIS/Include/core_cm0.h rename to Software/Drivers/CMSIS/Include/core_cm0.h diff --git a/Drivers/CMSIS/Include/core_cm0plus.h b/Software/Drivers/CMSIS/Include/core_cm0plus.h similarity index 100% rename from Drivers/CMSIS/Include/core_cm0plus.h rename to Software/Drivers/CMSIS/Include/core_cm0plus.h diff --git a/Drivers/CMSIS/Include/core_cm1.h b/Software/Drivers/CMSIS/Include/core_cm1.h similarity index 100% rename from Drivers/CMSIS/Include/core_cm1.h rename to Software/Drivers/CMSIS/Include/core_cm1.h diff --git a/Drivers/CMSIS/Include/core_cm23.h b/Software/Drivers/CMSIS/Include/core_cm23.h similarity index 100% rename from Drivers/CMSIS/Include/core_cm23.h rename to Software/Drivers/CMSIS/Include/core_cm23.h diff --git a/Drivers/CMSIS/Include/core_cm3.h b/Software/Drivers/CMSIS/Include/core_cm3.h similarity index 100% rename from Drivers/CMSIS/Include/core_cm3.h rename to Software/Drivers/CMSIS/Include/core_cm3.h diff --git a/Drivers/CMSIS/Include/core_cm33.h b/Software/Drivers/CMSIS/Include/core_cm33.h similarity index 100% rename from Drivers/CMSIS/Include/core_cm33.h rename to Software/Drivers/CMSIS/Include/core_cm33.h diff --git a/Drivers/CMSIS/Include/core_cm4.h b/Software/Drivers/CMSIS/Include/core_cm4.h similarity index 100% rename from Drivers/CMSIS/Include/core_cm4.h rename to Software/Drivers/CMSIS/Include/core_cm4.h diff --git a/Drivers/CMSIS/Include/core_cm7.h b/Software/Drivers/CMSIS/Include/core_cm7.h similarity index 100% rename from Drivers/CMSIS/Include/core_cm7.h rename to Software/Drivers/CMSIS/Include/core_cm7.h diff --git a/Drivers/CMSIS/Include/core_sc000.h b/Software/Drivers/CMSIS/Include/core_sc000.h similarity index 100% rename from Drivers/CMSIS/Include/core_sc000.h rename to Software/Drivers/CMSIS/Include/core_sc000.h diff --git a/Drivers/CMSIS/Include/core_sc300.h b/Software/Drivers/CMSIS/Include/core_sc300.h similarity index 100% rename from Drivers/CMSIS/Include/core_sc300.h rename to Software/Drivers/CMSIS/Include/core_sc300.h diff --git a/Drivers/CMSIS/Include/mpu_armv7.h b/Software/Drivers/CMSIS/Include/mpu_armv7.h similarity index 100% rename from Drivers/CMSIS/Include/mpu_armv7.h rename to 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b/Software/Drivers/CMSIS/Lib/ARM/arm_cortexM4bf_math.lib similarity index 100% rename from Drivers/CMSIS/Lib/ARM/arm_cortexM4bf_math.lib rename to Software/Drivers/CMSIS/Lib/ARM/arm_cortexM4bf_math.lib diff --git a/Drivers/CMSIS/Lib/ARM/arm_cortexM4l_math.lib b/Software/Drivers/CMSIS/Lib/ARM/arm_cortexM4l_math.lib similarity index 100% rename from Drivers/CMSIS/Lib/ARM/arm_cortexM4l_math.lib rename to Software/Drivers/CMSIS/Lib/ARM/arm_cortexM4l_math.lib diff --git a/Drivers/CMSIS/Lib/ARM/arm_cortexM4lf_math.lib b/Software/Drivers/CMSIS/Lib/ARM/arm_cortexM4lf_math.lib similarity index 100% rename from Drivers/CMSIS/Lib/ARM/arm_cortexM4lf_math.lib rename to Software/Drivers/CMSIS/Lib/ARM/arm_cortexM4lf_math.lib diff --git a/Drivers/CMSIS/Lib/GCC/libarm_cortexM4l_math.a b/Software/Drivers/CMSIS/Lib/GCC/libarm_cortexM4l_math.a similarity index 100% rename from Drivers/CMSIS/Lib/GCC/libarm_cortexM4l_math.a rename to Software/Drivers/CMSIS/Lib/GCC/libarm_cortexM4l_math.a diff --git a/Drivers/CMSIS/Lib/GCC/libarm_cortexM4lf_math.a b/Software/Drivers/CMSIS/Lib/GCC/libarm_cortexM4lf_math.a similarity index 100% rename from Drivers/CMSIS/Lib/GCC/libarm_cortexM4lf_math.a rename to Software/Drivers/CMSIS/Lib/GCC/libarm_cortexM4lf_math.a diff --git a/Drivers/CMSIS/Lib/IAR/iar_cortexM4b_math.a b/Software/Drivers/CMSIS/Lib/IAR/iar_cortexM4b_math.a similarity index 100% rename from Drivers/CMSIS/Lib/IAR/iar_cortexM4b_math.a rename to Software/Drivers/CMSIS/Lib/IAR/iar_cortexM4b_math.a diff --git a/Drivers/CMSIS/Lib/IAR/iar_cortexM4bf_math.a b/Software/Drivers/CMSIS/Lib/IAR/iar_cortexM4bf_math.a similarity index 100% rename from Drivers/CMSIS/Lib/IAR/iar_cortexM4bf_math.a rename to Software/Drivers/CMSIS/Lib/IAR/iar_cortexM4bf_math.a diff --git a/Drivers/CMSIS/Lib/IAR/iar_cortexM4l_math.a b/Software/Drivers/CMSIS/Lib/IAR/iar_cortexM4l_math.a similarity index 100% rename from Drivers/CMSIS/Lib/IAR/iar_cortexM4l_math.a rename to Software/Drivers/CMSIS/Lib/IAR/iar_cortexM4l_math.a diff --git a/Drivers/CMSIS/Lib/IAR/iar_cortexM4lf_math.a b/Software/Drivers/CMSIS/Lib/IAR/iar_cortexM4lf_math.a similarity index 100% rename from Drivers/CMSIS/Lib/IAR/iar_cortexM4lf_math.a rename to Software/Drivers/CMSIS/Lib/IAR/iar_cortexM4lf_math.a diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Compiler/EventRecorderConf.h b/Software/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Compiler/EventRecorderConf.h similarity index 100% rename from Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Compiler/EventRecorderConf.h rename to Software/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Compiler/EventRecorderConf.h diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM0/RTE_Components.h b/Software/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM0/RTE_Components.h similarity index 100% rename from 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Software/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM4_FP/RTE_Components.h diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM7_SP/RTE_Components.h b/Software/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM7_SP/RTE_Components.h similarity index 100% rename from Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM7_SP/RTE_Components.h rename to Software/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/_ARMCM7_SP/RTE_Components.h diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10.cpp b/Software/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10.cpp similarity index 100% rename from Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10.cpp rename to Software/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10.cpp diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10_inputs.h b/Software/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10_inputs.h similarity index 100% rename from Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10_inputs.h rename to Software/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10_inputs.h diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10_parameter.h b/Software/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10_parameter.h similarity index 100% rename from Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10_parameter.h rename to Software/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10_parameter.h diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10_weights.h b/Software/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10_weights.h similarity index 100% rename from Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10_weights.h rename to Software/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/arm_nnexamples_cifar10_weights.h diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/readme.txt b/Software/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/readme.txt similarity index 100% rename from Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/readme.txt rename to Software/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/readme.txt diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Compiler/EventRecorderConf.h b/Software/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Compiler/EventRecorderConf.h similarity index 100% rename from Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Compiler/EventRecorderConf.h rename to Software/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Compiler/EventRecorderConf.h diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM0/RTE_Components.h b/Software/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM0/RTE_Components.h similarity index 100% rename from Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM0/RTE_Components.h rename to Software/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM0/RTE_Components.h diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM3/RTE_Components.h b/Software/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM3/RTE_Components.h similarity index 100% rename from Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM3/RTE_Components.h rename to Software/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM3/RTE_Components.h diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM4_FP/RTE_Components.h b/Software/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM4_FP/RTE_Components.h similarity index 100% rename from Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM4_FP/RTE_Components.h rename to Software/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM4_FP/RTE_Components.h diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM7_SP/RTE_Components.h b/Software/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM7_SP/RTE_Components.h similarity index 100% rename from Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM7_SP/RTE_Components.h rename to Software/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/_ARMCM7_SP/RTE_Components.h diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/arm_nnexamples_gru.cpp b/Software/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/arm_nnexamples_gru.cpp similarity index 100% rename from Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/arm_nnexamples_gru.cpp rename to Software/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/arm_nnexamples_gru.cpp diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/arm_nnexamples_gru_test_data.h b/Software/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/arm_nnexamples_gru_test_data.h similarity index 100% rename from Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/arm_nnexamples_gru_test_data.h rename to Software/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/arm_nnexamples_gru_test_data.h diff --git a/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/readme.txt b/Software/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/readme.txt similarity index 100% rename from Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/readme.txt rename to Software/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/readme.txt diff --git a/Drivers/CMSIS/NN/Include/arm_nn_tables.h b/Software/Drivers/CMSIS/NN/Include/arm_nn_tables.h similarity index 100% rename from Drivers/CMSIS/NN/Include/arm_nn_tables.h rename to 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b/Software/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM3/RTE_Components.h similarity index 100% rename from Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM3/RTE_Components.h rename to Software/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM3/RTE_Components.h diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM4_FP/RTE_Components.h b/Software/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM4_FP/RTE_Components.h similarity index 100% rename from Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM4_FP/RTE_Components.h rename to Software/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM4_FP/RTE_Components.h diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM7_SP/RTE_Components.h b/Software/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM7_SP/RTE_Components.h similarity index 100% rename from Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM7_SP/RTE_Components.h rename to Software/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/_ARMCM7_SP/RTE_Components.h diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q15_ref.c b/Software/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q15_ref.c similarity index 100% rename from Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q15_ref.c rename to Software/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q15_ref.c diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q15_ref_nonsquare.c b/Software/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q15_ref_nonsquare.c similarity index 100% rename from Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q15_ref_nonsquare.c rename to Software/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q15_ref_nonsquare.c diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q7_ref.c b/Software/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q7_ref.c similarity index 100% rename from Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q7_ref.c rename to Software/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q7_ref.c diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q7_ref_nonsquare.c b/Software/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q7_ref_nonsquare.c similarity index 100% rename from Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q7_ref_nonsquare.c rename to Software/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q7_ref_nonsquare.c diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_depthwise_separable_conv_HWC_q7_ref.c b/Software/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_depthwise_separable_conv_HWC_q7_ref.c similarity index 100% rename from Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_depthwise_separable_conv_HWC_q7_ref.c rename to Software/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_depthwise_separable_conv_HWC_q7_ref.c diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_depthwise_separable_conv_HWC_q7_ref_nonsquare.c b/Software/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_depthwise_separable_conv_HWC_q7_ref_nonsquare.c similarity index 100% rename from Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_depthwise_separable_conv_HWC_q7_ref_nonsquare.c rename to Software/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_depthwise_separable_conv_HWC_q7_ref_nonsquare.c diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_mat_q7_vec_q15_opt_ref.c b/Software/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_mat_q7_vec_q15_opt_ref.c similarity index 100% rename from Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_mat_q7_vec_q15_opt_ref.c rename to Software/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_mat_q7_vec_q15_opt_ref.c diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_mat_q7_vec_q15_ref.c b/Software/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_mat_q7_vec_q15_ref.c similarity index 100% rename from Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_mat_q7_vec_q15_ref.c rename to Software/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_mat_q7_vec_q15_ref.c diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q15_opt_ref.c b/Software/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q15_opt_ref.c similarity index 100% rename from Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q15_opt_ref.c rename to Software/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q15_opt_ref.c diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q15_ref.c b/Software/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q15_ref.c similarity index 100% rename from Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q15_ref.c rename to Software/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q15_ref.c diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q7_opt_ref.c b/Software/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q7_opt_ref.c similarity index 100% rename from Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q7_opt_ref.c rename to Software/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q7_opt_ref.c diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q7_ref.c b/Software/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q7_ref.c similarity index 100% rename from Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q7_ref.c rename to Software/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q7_ref.c diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_nn_mult_ref.c b/Software/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_nn_mult_ref.c similarity index 100% rename from Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_nn_mult_ref.c rename to Software/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_nn_mult_ref.c diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_pool_ref.c b/Software/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_pool_ref.c similarity index 100% rename from Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_pool_ref.c rename to Software/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_pool_ref.c diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_relu_ref.c b/Software/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_relu_ref.c similarity index 100% rename from Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_relu_ref.c rename to Software/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_relu_ref.c diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/fully_connected_testing_weights.h b/Software/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/fully_connected_testing_weights.h similarity index 100% rename from Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/fully_connected_testing_weights.h rename to Software/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/fully_connected_testing_weights.h diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ref_functions.h b/Software/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ref_functions.h similarity index 100% rename from Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ref_functions.h rename to Software/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/ref_functions.h diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/arm_nnexamples_nn_test.cpp b/Software/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/arm_nnexamples_nn_test.cpp similarity index 100% rename from Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/arm_nnexamples_nn_test.cpp rename to Software/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/arm_nnexamples_nn_test.cpp diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/arm_nnexamples_nn_test.h b/Software/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/arm_nnexamples_nn_test.h similarity index 100% rename from Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/arm_nnexamples_nn_test.h rename to Software/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/arm_nnexamples_nn_test.h diff --git a/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/readme.txt b/Software/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/readme.txt similarity index 100% rename from Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/readme.txt rename to Software/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/readme.txt diff --git a/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q15.c b/Software/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q15.c similarity index 100% rename from Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q15.c rename to Software/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q15.c diff --git a/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q7.c b/Software/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q7.c similarity index 100% rename from Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q7.c rename to Software/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q7.c diff --git a/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q15.c b/Software/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q15.c similarity index 100% rename from Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q15.c rename to Software/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q15.c diff --git a/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q7.c b/Software/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q7.c similarity index 100% rename from Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q7.c rename to Software/Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q7.c diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1x1_HWC_q7_fast_nonsquare.c b/Software/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1x1_HWC_q7_fast_nonsquare.c similarity index 100% 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Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic.c rename to Software/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic.c diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic_nonsquare.c b/Software/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic_nonsquare.c similarity index 100% rename from Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic_nonsquare.c rename to Software/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic_nonsquare.c diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast.c b/Software/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast.c similarity index 100% rename from Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast.c rename to Software/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast.c diff --git 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b/Software/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7_nonsquare.c similarity index 100% rename from Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7_nonsquare.c rename to Software/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7_nonsquare.c diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15.c b/Software/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15.c similarity index 100% rename from Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15.c rename to Software/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15.c diff --git a/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15_reordered.c b/Software/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15_reordered.c similarity index 100% rename from Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15_reordered.c rename to Software/Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15_reordered.c diff --git a/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15.c b/Software/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15.c similarity index 100% rename from Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15.c rename to Software/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15.c diff --git a/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15_opt.c b/Software/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15_opt.c similarity index 100% rename from Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15_opt.c rename to Software/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15_opt.c diff --git a/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15.c b/Software/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15.c similarity index 100% rename from Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15.c rename to Software/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15.c diff --git a/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15_opt.c b/Software/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15_opt.c similarity index 100% rename from Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15_opt.c rename to Software/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15_opt.c diff --git a/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7.c b/Software/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7.c similarity index 100% rename from Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7.c rename to Software/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7.c diff --git a/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7_opt.c b/Software/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7_opt.c similarity index 100% rename from Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7_opt.c rename to Software/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7_opt.c diff --git a/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q15.c b/Software/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q15.c similarity index 100% rename from Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q15.c rename to Software/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q15.c diff --git a/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q7.c b/Software/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q7.c similarity index 100% rename from Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q7.c rename to Software/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q7.c diff --git a/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nntables.c b/Software/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nntables.c similarity index 100% rename from Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nntables.c rename to Software/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nntables.c diff --git a/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_no_shift.c b/Software/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_no_shift.c similarity index 100% rename from Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_no_shift.c rename to Software/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_no_shift.c diff --git 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Drivers/CMSIS/RTOS2/Include/os_tick.h rename to Software/Drivers/CMSIS/RTOS2/Include/os_tick.h diff --git a/Drivers/CMSIS/RTOS2/Source/os_systick.c b/Software/Drivers/CMSIS/RTOS2/Source/os_systick.c similarity index 100% rename from Drivers/CMSIS/RTOS2/Source/os_systick.c rename to Software/Drivers/CMSIS/RTOS2/Source/os_systick.c diff --git a/Drivers/CMSIS/RTOS2/Source/os_tick_gtim.c b/Software/Drivers/CMSIS/RTOS2/Source/os_tick_gtim.c similarity index 100% rename from Drivers/CMSIS/RTOS2/Source/os_tick_gtim.c rename to Software/Drivers/CMSIS/RTOS2/Source/os_tick_gtim.c diff --git a/Drivers/CMSIS/RTOS2/Source/os_tick_ptim.c b/Software/Drivers/CMSIS/RTOS2/Source/os_tick_ptim.c similarity index 100% rename from Drivers/CMSIS/RTOS2/Source/os_tick_ptim.c rename to Software/Drivers/CMSIS/RTOS2/Source/os_tick_ptim.c diff --git a/Drivers/CMSIS/RTOS2/Template/cmsis_os.h b/Software/Drivers/CMSIS/RTOS2/Template/cmsis_os.h similarity index 100% rename from Drivers/CMSIS/RTOS2/Template/cmsis_os.h rename to Software/Drivers/CMSIS/RTOS2/Template/cmsis_os.h diff --git a/Drivers/CMSIS/RTOS2/Template/cmsis_os1.c b/Software/Drivers/CMSIS/RTOS2/Template/cmsis_os1.c similarity index 100% rename from Drivers/CMSIS/RTOS2/Template/cmsis_os1.c rename to Software/Drivers/CMSIS/RTOS2/Template/cmsis_os1.c diff --git a/Drivers/CMSIS/docs/General/html/LICENSE.txt b/Software/Drivers/CMSIS/docs/General/html/LICENSE.txt similarity index 100% rename from Drivers/CMSIS/docs/General/html/LICENSE.txt rename to Software/Drivers/CMSIS/docs/General/html/LICENSE.txt diff --git a/Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/Software/Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h rename to Software/Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h diff --git a/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h b/Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h rename to Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h diff --git a/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h b/Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h rename to Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h diff --git a/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h b/Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h rename to Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h diff --git a/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h b/Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h rename to Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h diff --git a/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h b/Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h rename to Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h diff --git a/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h b/Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h rename to Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h diff --git a/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h b/Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h rename to Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h diff --git a/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h b/Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h rename to Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h diff --git a/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h b/Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h rename to Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h diff --git a/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h b/Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h rename to Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h diff --git a/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h b/Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h rename to Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h diff --git a/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h b/Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h rename to Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h diff --git a/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h b/Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h rename to Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h diff --git a/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h b/Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h rename to Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h diff --git a/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h b/Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h rename to Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h diff --git a/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h b/Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h rename to Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h diff --git a/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h b/Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h rename to Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h diff --git a/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h b/Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h rename to Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h diff --git a/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h b/Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h rename to Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h diff --git a/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h b/Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h rename to Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h diff --git a/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h b/Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h rename to Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h diff --git a/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_bus.h b/Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_bus.h similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_bus.h rename to Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_bus.h diff --git a/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_cortex.h b/Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_cortex.h similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_cortex.h rename to Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_cortex.h diff --git a/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dma.h b/Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dma.h similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dma.h rename to Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_dma.h diff --git a/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_exti.h b/Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_exti.h similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_exti.h rename to Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_exti.h diff --git a/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_gpio.h b/Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_gpio.h similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_gpio.h rename to Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_gpio.h diff --git a/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_i2c.h b/Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_i2c.h similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_i2c.h rename to Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_i2c.h diff --git a/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_pwr.h b/Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_pwr.h similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_pwr.h rename to Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_pwr.h diff --git a/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rcc.h b/Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rcc.h similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rcc.h rename to Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_rcc.h diff --git a/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_spi.h b/Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_spi.h similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_spi.h rename to Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_spi.h diff --git a/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_system.h b/Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_system.h similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_system.h rename to Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_system.h diff --git a/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_tim.h b/Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_tim.h similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_tim.h rename to Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_tim.h diff --git a/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_utils.h b/Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_utils.h similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_utils.h rename to Software/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_utils.h diff --git a/Drivers/STM32F3xx_HAL_Driver/LICENSE.txt b/Software/Drivers/STM32F3xx_HAL_Driver/LICENSE.txt similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/LICENSE.txt rename to Software/Drivers/STM32F3xx_HAL_Driver/LICENSE.txt diff --git a/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c b/Software/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c rename to Software/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c diff --git a/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c b/Software/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c rename to Software/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c diff --git a/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c b/Software/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c rename to Software/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c diff --git a/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c b/Software/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c rename to Software/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c diff --git a/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c b/Software/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c rename to Software/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c diff --git a/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c b/Software/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c rename to Software/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c diff --git a/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c b/Software/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c rename to Software/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c diff --git a/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c b/Software/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c rename to Software/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c diff --git a/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c b/Software/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c rename to Software/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c diff --git a/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c b/Software/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c rename to Software/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c diff --git a/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c b/Software/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c rename to Software/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c diff --git a/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c b/Software/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c rename to Software/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c diff --git a/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c b/Software/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c rename to Software/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c diff --git a/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c b/Software/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c rename to Software/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c diff --git a/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c b/Software/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c rename to Software/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c diff --git a/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c b/Software/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c rename to Software/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c diff --git a/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c b/Software/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c rename to Software/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c diff --git a/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c b/Software/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c similarity index 100% rename from Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c rename to Software/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c diff --git a/Makefile b/Software/Makefile similarity index 100% rename from Makefile rename to Software/Makefile diff --git a/STM32-for-VSCode.config.yaml b/Software/STM32-for-VSCode.config.yaml similarity index 100% rename from STM32-for-VSCode.config.yaml rename to Software/STM32-for-VSCode.config.yaml diff --git a/STM32F302CBTx_FLASH.ld b/Software/STM32F302CBTx_FLASH.ld similarity index 100% rename from STM32F302CBTx_FLASH.ld rename to Software/STM32F302CBTx_FLASH.ld diff --git a/Software/STM32Make.make b/Software/STM32Make.make new file mode 100644 index 0000000..5a6b1cd --- /dev/null +++ b/Software/STM32Make.make @@ -0,0 +1,273 @@ +########################################################################################################################## +# File automatically-generated by STM32forVSCode +########################################################################################################################## + +# ------------------------------------------------ +# Generic Makefile (based on gcc) +# +# ChangeLog : +# 2017-02-10 - Several enhancements + project update mode +# 2015-07-22 - first version +# ------------------------------------------------ + +###################################### +# target +###################################### +TARGET = mvbms-test-24 + + +###################################### +# building variables +###################################### +# debug build? +DEBUG = 1 +# optimization +OPT = -O0 + + +####################################### +# paths +####################################### +# Build path +BUILD_DIR = build + +###################################### +# source +###################################### +# C sources +C_SOURCES = \ +Core/Lib/can-halal/can-halal.c \ +Core/Src/ADBMS_Abstraction.c \ +Core/Src/ADBMS_LL_Driver.c \ +Core/Src/AMS_HighLevel.c \ +Core/Src/PWM_control.c \ +Core/Src/TMP1075.c \ +Core/Src/can.c \ +Core/Src/eeprom.c \ +Core/Src/errors.c \ +Core/Src/main.c \ +Core/Src/soc_estimation.c \ +Core/Src/state_machine.c \ +Core/Src/status_LED.c \ +Core/Src/stm32f3xx_hal_msp.c \ +Core/Src/stm32f3xx_it.c \ +Core/Src/syscalls.c \ +Core/Src/sysmem.c \ +Core/Src/system_stm32f3xx.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c + + +CPP_SOURCES = \ + + +# ASM sources +ASM_SOURCES = \ +startup_stm32f302xc.s + + + +####################################### +# binaries +####################################### +PREFIX = arm-none-eabi- +POSTFIX = " +# The gcc compiler bin path can be either defined in make command via GCC_PATH variable (> make GCC_PATH=xxx) +# either it can be added to the PATH environment variable. +GCC_PATH="/run/current-system/sw/bin +ifdef GCC_PATH +CXX = $(GCC_PATH)/$(PREFIX)g++$(POSTFIX) +CC = $(GCC_PATH)/$(PREFIX)gcc$(POSTFIX) +AS = $(GCC_PATH)/$(PREFIX)gcc$(POSTFIX) -x assembler-with-cpp +CP = $(GCC_PATH)/$(PREFIX)objcopy$(POSTFIX) +SZ = $(GCC_PATH)/$(PREFIX)size$(POSTFIX) +else +CXX = $(PREFIX)g++ +CC = $(PREFIX)gcc +AS = $(PREFIX)gcc -x assembler-with-cpp +CP = $(PREFIX)objcopy +SZ = $(PREFIX)size +endif +HEX = $(CP) -O ihex +BIN = $(CP) -O binary -S + +####################################### +# CFLAGS +####################################### +# cpu +CPU = -mcpu=cortex-m4 + +# fpu +FPU = -mfpu=fpv4-sp-d16 + +# float-abi +FLOAT-ABI = -mfloat-abi=hard + +# mcu +MCU = $(CPU) -mthumb $(FPU) $(FLOAT-ABI) + +# macros for gcc +# AS defines +AS_DEFS = + +# C defines +C_DEFS = \ +-DSTM32F302xC \ +-DSTM32F3xx \ +-DUSE_HAL_DRIVER + + +# CXX defines +CXX_DEFS = \ +-DSTM32F302xC \ +-DUSE_HAL_DRIVER + + +# AS includes +AS_INCLUDES = \ + +# C includes +C_INCLUDES = \ +-ICore/Inc \ +-ICore/Lib/can-halal \ +-IDrivers/CMSIS/Device/ST/STM32F3xx/Include \ +-IDrivers/CMSIS/Include \ +-IDrivers/STM32F3xx_HAL_Driver/Inc \ +-IDrivers/STM32F3xx_HAL_Driver/Inc/Legacy + + + +# compile gcc flags +ASFLAGS = $(MCU) $(AS_DEFS) $(AS_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections + +CFLAGS = $(MCU) $(C_DEFS) $(C_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections + +CXXFLAGS = $(MCU) $(CXX_DEFS) $(C_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections -feliminate-unused-debug-types + +ifeq ($(DEBUG), 1) +CFLAGS += -g -gdwarf -ggdb +CXXFLAGS += -g -gdwarf -ggdb +endif + +# Add additional flags +CFLAGS += --std=gnu2x -Wall -Wextra -Wno-unused-parameter -fanalyzer -fdata-sections -ffunction-sections +ASFLAGS += -Wall -fdata-sections -ffunction-sections +CXXFLAGS += + +# Generate dependency information +CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)" +CXXFLAGS += -MMD -MP -MF"$(@:%.o=%.d)" + +####################################### +# LDFLAGS +####################################### +# link script +LDSCRIPT = STM32F302CBTx_FLASH.ld + +# libraries +LIBS = -lc -lm -lnosys +LIBDIR = \ + + +# Additional LD Flags from config file +ADDITIONALLDFLAGS = -Wl,--print-memory-usage -specs=nano.specs + +LDFLAGS = $(MCU) $(ADDITIONALLDFLAGS) -T$(LDSCRIPT) $(LIBDIR) $(LIBS) -Wl,-Map=$(BUILD_DIR)/$(TARGET).map,--cref -Wl,--gc-sections + +# default action: build all +all: $(BUILD_DIR)/$(TARGET).elf $(BUILD_DIR)/$(TARGET).hex $(BUILD_DIR)/$(TARGET).bin + + +####################################### +# build the application +####################################### +# list of cpp program objects +OBJECTS = $(addprefix $(BUILD_DIR)/,$(notdir $(CPP_SOURCES:.cpp=.o))) +vpath %.cpp $(sort $(dir $(CPP_SOURCES))) + +# list of C objects +OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(C_SOURCES:.c=.o))) +vpath %.c $(sort $(dir $(C_SOURCES))) + +# list of ASM program objects +UPPER_CASE_ASM_SOURCES = $(filter %.S,$(ASM_SOURCES)) +LOWER_CASE_ASM_SOURCES = $(filter %.s,$(ASM_SOURCES)) + +OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(UPPER_CASE_ASM_SOURCES:.S=.o))) +OBJECTS += $(addprefix $(BUILD_DIR)/,$(notdir $(LOWER_CASE_ASM_SOURCES:.s=.o))) +vpath %.s $(sort $(dir $(ASM_SOURCES))) + +$(BUILD_DIR)/%.o: %.cpp STM32Make.make | $(BUILD_DIR) + $(CXX) -c $(CXXFLAGS) -Wa,-a,-ad,-alms=$(BUILD_DIR)/$(notdir $(<:.cpp=.lst)) $< -o $@ + +$(BUILD_DIR)/%.o: %.cxx STM32Make.make | $(BUILD_DIR) + $(CXX) -c $(CXXFLAGS) -Wa,-a,-ad,-alms=$(BUILD_DIR)/$(notdir $(<:.cxx=.lst)) $< -o $@ + +$(BUILD_DIR)/%.o: %.c STM32Make.make | $(BUILD_DIR) + $(CC) -c $(CFLAGS) -Wa,-a,-ad,-alms=$(BUILD_DIR)/$(notdir $(<:.c=.lst)) $< -o $@ + +$(BUILD_DIR)/%.o: %.s STM32Make.make | $(BUILD_DIR) + $(AS) -c $(CFLAGS) $< -o $@ + +$(BUILD_DIR)/%.o: %.S STM32Make.make | $(BUILD_DIR) + $(AS) -c $(CFLAGS) $< -o $@ + +$(BUILD_DIR)/$(TARGET).elf: $(OBJECTS) STM32Make.make + $(CC) $(OBJECTS) $(LDFLAGS) -o $@ + $(SZ) $@ + +$(BUILD_DIR)/%.hex: $(BUILD_DIR)/%.elf | $(BUILD_DIR) + $(HEX) $< $@ + +$(BUILD_DIR)/%.bin: $(BUILD_DIR)/%.elf | $(BUILD_DIR) + $(BIN) $< $@ + +$(BUILD_DIR): + mkdir $@ + +####################################### +# flash +####################################### +flash: $(BUILD_DIR)/$(TARGET).elf + "/run/current-system/sw/bin/openocd" -f ./openocd.cfg -c "program $(BUILD_DIR)/$(TARGET).elf verify reset exit" + +####################################### +# erase +####################################### +erase: $(BUILD_DIR)/$(TARGET).elf + "/run/current-system/sw/bin/openocd" -f ./openocd.cfg -c "init; reset halt; stm32f3x mass_erase 0; exit" + +####################################### +# clean up +####################################### +clean: + -rm -fR $(BUILD_DIR) + +####################################### +# custom makefile rules +####################################### + + + +####################################### +# dependencies +####################################### +-include $(wildcard $(BUILD_DIR)/*.d) + +# *** EOF *** \ No newline at end of file diff --git a/Software/build/ADBMS_Abstraction.d b/Software/build/ADBMS_Abstraction.d new file mode 100644 index 0000000..f3bb33f --- /dev/null +++ b/Software/build/ADBMS_Abstraction.d @@ -0,0 +1,70 @@ +build/ADBMS_Abstraction.o: Core/Src/ADBMS_Abstraction.c \ + Core/Inc/ADBMS_Abstraction.h Core/Inc/ADBMS_CMD_MAKROS.h \ + Core/Inc/ADBMS_LL_Driver.h Core/Inc/main.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + Core/Inc/stm32f3xx_hal_conf.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h \ + Core/Inc/ADBMS_CMD_MAKROS.h Core/Inc/ADBMS_LL_Driver.h +Core/Inc/ADBMS_Abstraction.h: +Core/Inc/ADBMS_CMD_MAKROS.h: +Core/Inc/ADBMS_LL_Driver.h: +Core/Inc/main.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h: +Core/Inc/ADBMS_CMD_MAKROS.h: +Core/Inc/ADBMS_LL_Driver.h: diff --git a/Software/build/ADBMS_Abstraction.lst b/Software/build/ADBMS_Abstraction.lst new file mode 100644 index 0000000..d38c449 --- /dev/null +++ b/Software/build/ADBMS_Abstraction.lst @@ -0,0 +1,3129 @@ +ARM GAS /tmp/cclV24WD.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 6 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "ADBMS_Abstraction.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Core/Src/ADBMS_Abstraction.c" + 20 .global numberofcells + 21 .section .bss.numberofcells,"aw",%nobits + 24 numberofcells: + 25 0000 00 .space 1 + 26 .global numberofauxchannels + 27 .section .bss.numberofauxchannels,"aw",%nobits + 30 numberofauxchannels: + 31 0000 00 .space 1 + 32 .section .rodata + 33 .align 2 + 34 .LC0: + 35 0000 FFFFFFFF .ascii "\377\377\377\377\377\377" + 35 FFFF + 36 .section .text.amsReset,"ax",%progbits + 37 .align 1 + 38 .global amsReset + 39 .syntax unified + 40 .thumb + 41 .thumb_func + 43 amsReset: + 44 .LFB130: + 1:Core/Src/ADBMS_Abstraction.c **** /* + 2:Core/Src/ADBMS_Abstraction.c **** * ADBMS_Abstraction.c + 3:Core/Src/ADBMS_Abstraction.c **** * + 4:Core/Src/ADBMS_Abstraction.c **** * Created on: 14.07.2022 + 5:Core/Src/ADBMS_Abstraction.c **** * Author: max + 6:Core/Src/ADBMS_Abstraction.c **** */ + 7:Core/Src/ADBMS_Abstraction.c **** + 8:Core/Src/ADBMS_Abstraction.c **** #include "ADBMS_Abstraction.h" + 9:Core/Src/ADBMS_Abstraction.c **** #include "ADBMS_CMD_MAKROS.h" + 10:Core/Src/ADBMS_Abstraction.c **** #include "ADBMS_LL_Driver.h" + 11:Core/Src/ADBMS_Abstraction.c **** #include + 12:Core/Src/ADBMS_Abstraction.c **** + 13:Core/Src/ADBMS_Abstraction.c **** uint8 numberofcells; + 14:Core/Src/ADBMS_Abstraction.c **** uint8 numberofauxchannels; + 15:Core/Src/ADBMS_Abstraction.c **** + 16:Core/Src/ADBMS_Abstraction.c **** #define CHECK_RETURN(x) \ + 17:Core/Src/ADBMS_Abstraction.c **** { \ + ARM GAS /tmp/cclV24WD.s page 2 + + + 18:Core/Src/ADBMS_Abstraction.c **** uint8 status = x; \ + 19:Core/Src/ADBMS_Abstraction.c **** if (status != 0) \ + 20:Core/Src/ADBMS_Abstraction.c **** return status; \ + 21:Core/Src/ADBMS_Abstraction.c **** } + 22:Core/Src/ADBMS_Abstraction.c **** + 23:Core/Src/ADBMS_Abstraction.c **** uint8 amsReset() { + 45 .loc 1 23 18 + 46 .cfi_startproc + 47 @ args = 0, pretend = 0, frame = 16 + 48 @ frame_needed = 1, uses_anonymous_args = 0 + 49 0000 80B5 push {r7, lr} + 50 .cfi_def_cfa_offset 8 + 51 .cfi_offset 7, -8 + 52 .cfi_offset 14, -4 + 53 0002 84B0 sub sp, sp, #16 + 54 .cfi_def_cfa_offset 24 + 55 0004 00AF add r7, sp, #0 + 56 .cfi_def_cfa_register 7 + 24:Core/Src/ADBMS_Abstraction.c **** amsWakeUp(); + 57 .loc 1 24 3 + 58 0006 FFF7FEFF bl amsWakeUp + 25:Core/Src/ADBMS_Abstraction.c **** readCMD(SRST, NULL, 0); + 59 .loc 1 25 3 + 60 000a 0022 movs r2, #0 + 61 000c 0021 movs r1, #0 + 62 000e 2720 movs r0, #39 + 63 0010 FFF7FEFF bl readCMD + 26:Core/Src/ADBMS_Abstraction.c **** mcuDelay(10); + 64 .loc 1 26 3 + 65 0014 0A20 movs r0, #10 + 66 0016 FFF7FEFF bl mcuDelay + 27:Core/Src/ADBMS_Abstraction.c **** amsWakeUp(); + 67 .loc 1 27 3 + 68 001a FFF7FEFF bl amsWakeUp + 28:Core/Src/ADBMS_Abstraction.c **** amsStopBalancing(); + 69 .loc 1 28 3 + 70 001e FFF7FEFF bl amsStopBalancing + 29:Core/Src/ADBMS_Abstraction.c **** amsConfigOverUnderVoltage(DEFAULT_OV, DEFAULT_UV); + 71 .loc 1 29 3 + 72 0022 40F2A111 movw r1, #417 + 73 0026 40F26540 movw r0, #1125 + 74 002a FFF7FEFF bl amsConfigOverUnderVoltage + 30:Core/Src/ADBMS_Abstraction.c **** + 31:Core/Src/ADBMS_Abstraction.c **** const uint8 buffer[6] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}; + 75 .loc 1 31 15 + 76 002e 214A ldr r2, .L8 + 77 0030 3B1D adds r3, r7, #4 + 78 0032 92E80300 ldm r2, {r0, r1} + 79 0036 1860 str r0, [r3] + 80 0038 0433 adds r3, r3, #4 + 81 003a 1980 strh r1, [r3] @ movhi + 82 .LBB2: + 32:Core/Src/ADBMS_Abstraction.c **** + 33:Core/Src/ADBMS_Abstraction.c **** CHECK_RETURN(writeCMD(CLRFLAG, buffer, 6)); //clear flags, + 83 .loc 1 33 3 + 84 003c 3B1D adds r3, r7, #4 + 85 003e 0622 movs r2, #6 + ARM GAS /tmp/cclV24WD.s page 3 + + + 86 0040 1946 mov r1, r3 + 87 0042 40F21770 movw r0, #1815 + 88 0046 FFF7FEFF bl writeCMD + 89 004a 0346 mov r3, r0 + 90 004c FB73 strb r3, [r7, #15] + 91 .loc 1 33 3 is_stmt 0 discriminator 1 + 92 004e FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 93 0050 002B cmp r3, #0 + 94 0052 01D0 beq .L2 + 95 0054 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 96 .loc 1 33 3 + 97 0056 28E0 b .L7 + 98 .L2: + 99 .LBE2: + 100 .LBB3: + 34:Core/Src/ADBMS_Abstraction.c **** CHECK_RETURN(writeCMD(CLOVUV, buffer, 6)); //OVUV flags + 101 .loc 1 34 3 is_stmt 1 + 102 0058 3B1D adds r3, r7, #4 + 103 005a 0622 movs r2, #6 + 104 005c 1946 mov r1, r3 + 105 005e 40F21570 movw r0, #1813 + 106 0062 FFF7FEFF bl writeCMD + 107 0066 0346 mov r3, r0 + 108 0068 BB73 strb r3, [r7, #14] + 109 .loc 1 34 3 is_stmt 0 discriminator 1 + 110 006a BB7B ldrb r3, [r7, #14] @ zero_extendqisi2 + 111 006c 002B cmp r3, #0 + 112 006e 01D0 beq .L4 + 113 0070 BB7B ldrb r3, [r7, #14] @ zero_extendqisi2 + 114 .loc 1 34 3 + 115 0072 1AE0 b .L7 + 116 .L4: + 117 .LBE3: + 118 .LBB4: + 35:Core/Src/ADBMS_Abstraction.c **** CHECK_RETURN(writeCMD(ADCV | ADCV_CONT | ADCV_RD, NULL, 0)); //start continuous cell voltage meas + 119 .loc 1 35 3 is_stmt 1 + 120 0074 0022 movs r2, #0 + 121 0076 0021 movs r1, #0 + 122 0078 4FF47870 mov r0, #992 + 123 007c FFF7FEFF bl writeCMD + 124 0080 0346 mov r3, r0 + 125 0082 7B73 strb r3, [r7, #13] + 126 .loc 1 35 3 is_stmt 0 discriminator 1 + 127 0084 7B7B ldrb r3, [r7, #13] @ zero_extendqisi2 + 128 0086 002B cmp r3, #0 + 129 0088 01D0 beq .L5 + 130 008a 7B7B ldrb r3, [r7, #13] @ zero_extendqisi2 + 131 .loc 1 35 3 + 132 008c 0DE0 b .L7 + 133 .L5: + 134 .LBE4: + 135 .LBB5: + 36:Core/Src/ADBMS_Abstraction.c **** CHECK_RETURN(writeCMD(ADAX | ADAX_CONV_ALL, NULL, 0)); //start aux measurement + 136 .loc 1 36 3 is_stmt 1 + 137 008e 0022 movs r2, #0 + 138 0090 0021 movs r1, #0 + 139 0092 4FF48260 mov r0, #1040 + ARM GAS /tmp/cclV24WD.s page 4 + + + 140 0096 FFF7FEFF bl writeCMD + 141 009a 0346 mov r3, r0 + 142 009c 3B73 strb r3, [r7, #12] + 143 .loc 1 36 3 is_stmt 0 discriminator 1 + 144 009e 3B7B ldrb r3, [r7, #12] @ zero_extendqisi2 + 145 00a0 002B cmp r3, #0 + 146 00a2 01D0 beq .L6 + 147 00a4 3B7B ldrb r3, [r7, #12] @ zero_extendqisi2 + 148 .loc 1 36 3 + 149 00a6 00E0 b .L7 + 150 .L6: + 151 .LBE5: + 37:Core/Src/ADBMS_Abstraction.c **** + 38:Core/Src/ADBMS_Abstraction.c **** return 0; + 152 .loc 1 38 10 is_stmt 1 + 153 00a8 0023 movs r3, #0 + 154 .L7: + 39:Core/Src/ADBMS_Abstraction.c **** } + 155 .loc 1 39 1 + 156 00aa 1846 mov r0, r3 + 157 00ac 1037 adds r7, r7, #16 + 158 .cfi_def_cfa_offset 8 + 159 00ae BD46 mov sp, r7 + 160 .cfi_def_cfa_register 13 + 161 @ sp needed + 162 00b0 80BD pop {r7, pc} + 163 .L9: + 164 00b2 00BF .align 2 + 165 .L8: + 166 00b4 00000000 .word .LC0 + 167 .cfi_endproc + 168 .LFE130: + 170 .section .text.initAMS,"ax",%progbits + 171 .align 1 + 172 .global initAMS + 173 .syntax unified + 174 .thumb + 175 .thumb_func + 177 initAMS: + 178 .LFB131: + 40:Core/Src/ADBMS_Abstraction.c **** + 41:Core/Src/ADBMS_Abstraction.c **** uint8 initAMS(SPI_HandleTypeDef* hspi, uint8 numofcells, uint8 numofaux) { + 179 .loc 1 41 74 + 180 .cfi_startproc + 181 @ args = 0, pretend = 0, frame = 8 + 182 @ frame_needed = 1, uses_anonymous_args = 0 + 183 0000 80B5 push {r7, lr} + 184 .cfi_def_cfa_offset 8 + 185 .cfi_offset 7, -8 + 186 .cfi_offset 14, -4 + 187 0002 82B0 sub sp, sp, #8 + 188 .cfi_def_cfa_offset 16 + 189 0004 00AF add r7, sp, #0 + 190 .cfi_def_cfa_register 7 + 191 0006 7860 str r0, [r7, #4] + 192 0008 0B46 mov r3, r1 + 193 000a FB70 strb r3, [r7, #3] + ARM GAS /tmp/cclV24WD.s page 5 + + + 194 000c 1346 mov r3, r2 + 195 000e BB70 strb r3, [r7, #2] + 42:Core/Src/ADBMS_Abstraction.c **** adbmsDriverInit(hspi); + 196 .loc 1 42 3 + 197 0010 7868 ldr r0, [r7, #4] + 198 0012 FFF7FEFF bl adbmsDriverInit + 43:Core/Src/ADBMS_Abstraction.c **** numberofcells = numofcells; + 199 .loc 1 43 17 + 200 0016 064A ldr r2, .L12 + 201 0018 FB78 ldrb r3, [r7, #3] + 202 001a 1370 strb r3, [r2] + 44:Core/Src/ADBMS_Abstraction.c **** numberofauxchannels = numofaux; + 203 .loc 1 44 23 + 204 001c 054A ldr r2, .L12+4 + 205 001e BB78 ldrb r3, [r7, #2] + 206 0020 1370 strb r3, [r2] + 45:Core/Src/ADBMS_Abstraction.c **** + 46:Core/Src/ADBMS_Abstraction.c **** return amsReset(); + 207 .loc 1 46 10 + 208 0022 FFF7FEFF bl amsReset + 209 0026 0346 mov r3, r0 + 47:Core/Src/ADBMS_Abstraction.c **** } + 210 .loc 1 47 1 + 211 0028 1846 mov r0, r3 + 212 002a 0837 adds r7, r7, #8 + 213 .cfi_def_cfa_offset 8 + 214 002c BD46 mov sp, r7 + 215 .cfi_def_cfa_register 13 + 216 @ sp needed + 217 002e 80BD pop {r7, pc} + 218 .L13: + 219 .align 2 + 220 .L12: + 221 0030 00000000 .word numberofcells + 222 0034 00000000 .word numberofauxchannels + 223 .cfi_endproc + 224 .LFE131: + 226 .section .text.amsWakeUp,"ax",%progbits + 227 .align 1 + 228 .global amsWakeUp + 229 .syntax unified + 230 .thumb + 231 .thumb_func + 233 amsWakeUp: + 234 .LFB132: + 48:Core/Src/ADBMS_Abstraction.c **** + 49:Core/Src/ADBMS_Abstraction.c **** uint8 amsWakeUp() { + 235 .loc 1 49 19 + 236 .cfi_startproc + 237 @ args = 0, pretend = 0, frame = 8 + 238 @ frame_needed = 1, uses_anonymous_args = 0 + 239 0000 80B5 push {r7, lr} + 240 .cfi_def_cfa_offset 8 + 241 .cfi_offset 7, -8 + 242 .cfi_offset 14, -4 + 243 0002 82B0 sub sp, sp, #8 + 244 .cfi_def_cfa_offset 16 + ARM GAS /tmp/cclV24WD.s page 6 + + + 245 0004 00AF add r7, sp, #0 + 246 .cfi_def_cfa_register 7 + 50:Core/Src/ADBMS_Abstraction.c **** uint8 buf[6]; + 51:Core/Src/ADBMS_Abstraction.c **** return readCMD(RDCFGA, buf, 6); + 247 .loc 1 51 10 + 248 0006 3B46 mov r3, r7 + 249 0008 0622 movs r2, #6 + 250 000a 1946 mov r1, r3 + 251 000c 0220 movs r0, #2 + 252 000e FFF7FEFF bl readCMD + 253 0012 0346 mov r3, r0 + 52:Core/Src/ADBMS_Abstraction.c **** } + 254 .loc 1 52 1 + 255 0014 1846 mov r0, r3 + 256 0016 0837 adds r7, r7, #8 + 257 .cfi_def_cfa_offset 8 + 258 0018 BD46 mov sp, r7 + 259 .cfi_def_cfa_register 13 + 260 @ sp needed + 261 001a 80BD pop {r7, pc} + 262 .cfi_endproc + 263 .LFE132: + 265 .section .text.amsCellMeasurement,"ax",%progbits + 266 .align 1 + 267 .global amsCellMeasurement + 268 .syntax unified + 269 .thumb + 270 .thumb_func + 272 amsCellMeasurement: + 273 .LFB133: + 53:Core/Src/ADBMS_Abstraction.c **** + 54:Core/Src/ADBMS_Abstraction.c **** uint8 amsCellMeasurement(Cell_Module* module) { + 274 .loc 1 54 47 + 275 .cfi_startproc + 276 @ args = 0, pretend = 0, frame = 8 + 277 @ frame_needed = 1, uses_anonymous_args = 0 + 278 0000 80B5 push {r7, lr} + 279 .cfi_def_cfa_offset 8 + 280 .cfi_offset 7, -8 + 281 .cfi_offset 14, -4 + 282 0002 82B0 sub sp, sp, #8 + 283 .cfi_def_cfa_offset 16 + 284 0004 00AF add r7, sp, #0 + 285 .cfi_def_cfa_register 7 + 286 0006 7860 str r0, [r7, #4] + 55:Core/Src/ADBMS_Abstraction.c **** #warning check conversion counter to ensure that continous conversion has not been stopped + 56:Core/Src/ADBMS_Abstraction.c **** #warning check for OW conditions: ADSV | ADSV_OW_0 / ADSV_OW_1 + 57:Core/Src/ADBMS_Abstraction.c **** return amsReadCellVoltages(module); + 287 .loc 1 57 10 + 288 0008 7868 ldr r0, [r7, #4] + 289 000a FFF7FEFF bl amsReadCellVoltages + 290 000e 0346 mov r3, r0 + 58:Core/Src/ADBMS_Abstraction.c **** } + 291 .loc 1 58 1 + 292 0010 1846 mov r0, r3 + 293 0012 0837 adds r7, r7, #8 + 294 .cfi_def_cfa_offset 8 + ARM GAS /tmp/cclV24WD.s page 7 + + + 295 0014 BD46 mov sp, r7 + 296 .cfi_def_cfa_register 13 + 297 @ sp needed + 298 0016 80BD pop {r7, pc} + 299 .cfi_endproc + 300 .LFE133: + 302 .section .text.amsConfigCellMeasurement,"ax",%progbits + 303 .align 1 + 304 .global amsConfigCellMeasurement + 305 .syntax unified + 306 .thumb + 307 .thumb_func + 309 amsConfigCellMeasurement: + 310 .LFB134: + 59:Core/Src/ADBMS_Abstraction.c **** + 60:Core/Src/ADBMS_Abstraction.c **** uint8 amsConfigCellMeasurement(uint8 numberofChannels) { + 311 .loc 1 60 56 + 312 .cfi_startproc + 313 @ args = 0, pretend = 0, frame = 8 + 314 @ frame_needed = 1, uses_anonymous_args = 0 + 315 @ link register save eliminated. + 316 0000 80B4 push {r7} + 317 .cfi_def_cfa_offset 4 + 318 .cfi_offset 7, -4 + 319 0002 83B0 sub sp, sp, #12 + 320 .cfi_def_cfa_offset 16 + 321 0004 00AF add r7, sp, #0 + 322 .cfi_def_cfa_register 7 + 323 0006 0346 mov r3, r0 + 324 0008 FB71 strb r3, [r7, #7] + 61:Core/Src/ADBMS_Abstraction.c **** numberofcells = numberofChannels; + 325 .loc 1 61 17 + 326 000a 054A ldr r2, .L20 + 327 000c FB79 ldrb r3, [r7, #7] + 328 000e 1370 strb r3, [r2] + 62:Core/Src/ADBMS_Abstraction.c **** return 0; + 329 .loc 1 62 10 + 330 0010 0023 movs r3, #0 + 63:Core/Src/ADBMS_Abstraction.c **** } + 331 .loc 1 63 1 + 332 0012 1846 mov r0, r3 + 333 0014 0C37 adds r7, r7, #12 + 334 .cfi_def_cfa_offset 4 + 335 0016 BD46 mov sp, r7 + 336 .cfi_def_cfa_register 13 + 337 @ sp needed + 338 0018 5DF8047B ldr r7, [sp], #4 + 339 .cfi_restore 7 + 340 .cfi_def_cfa_offset 0 + 341 001c 7047 bx lr + 342 .L21: + 343 001e 00BF .align 2 + 344 .L20: + 345 0020 00000000 .word numberofcells + 346 .cfi_endproc + 347 .LFE134: + 349 .global __aeabi_i2d + ARM GAS /tmp/cclV24WD.s page 8 + + + 350 .global __aeabi_dmul + 351 .global __aeabi_dadd + 352 .global __aeabi_d2f + 353 .global __aeabi_d2uiz + 354 .section .text.amsAuxAndStatusMeasurement,"ax",%progbits + 355 .align 1 + 356 .global amsAuxAndStatusMeasurement + 357 .syntax unified + 358 .thumb + 359 .thumb_func + 361 amsAuxAndStatusMeasurement: + 362 .LFB135: + 64:Core/Src/ADBMS_Abstraction.c **** + 65:Core/Src/ADBMS_Abstraction.c **** uint8 amsAuxAndStatusMeasurement(Cell_Module* module) { + 363 .loc 1 65 55 + 364 .cfi_startproc + 365 @ args = 0, pretend = 0, frame = 32 + 366 @ frame_needed = 1, uses_anonymous_args = 0 + 367 0000 80B5 push {r7, lr} + 368 .cfi_def_cfa_offset 8 + 369 .cfi_offset 7, -8 + 370 .cfi_offset 14, -4 + 371 0002 88B0 sub sp, sp, #32 + 372 .cfi_def_cfa_offset 40 + 373 0004 00AF add r7, sp, #0 + 374 .cfi_def_cfa_register 7 + 375 0006 7860 str r0, [r7, #4] + 66:Core/Src/ADBMS_Abstraction.c **** uint8 rxbuf[AUX_GROUP_A_SIZE] = {}; + 376 .loc 1 66 9 + 377 0008 07F11003 add r3, r7, #16 + 378 000c 0022 movs r2, #0 + 379 000e 1A60 str r2, [r3] + 380 0010 9A80 strh r2, [r3, #4] @ movhi + 381 .LBB6: + 67:Core/Src/ADBMS_Abstraction.c **** + 68:Core/Src/ADBMS_Abstraction.c **** CHECK_RETURN(readCMD(RDSTATC, rxbuf, STATUS_GROUP_C_SIZE)); + 382 .loc 1 68 3 + 383 0012 07F11003 add r3, r7, #16 + 384 0016 0622 movs r2, #6 + 385 0018 1946 mov r1, r3 + 386 001a 3220 movs r0, #50 + 387 001c FFF7FEFF bl readCMD + 388 0020 0346 mov r3, r0 + 389 0022 FB77 strb r3, [r7, #31] + 390 .loc 1 68 3 is_stmt 0 discriminator 1 + 391 0024 FB7F ldrb r3, [r7, #31] @ zero_extendqisi2 + 392 0026 002B cmp r3, #0 + 393 0028 01D0 beq .L23 + 394 002a FB7F ldrb r3, [r7, #31] @ zero_extendqisi2 + 395 .loc 1 68 3 + 396 002c 22E3 b .L33 + 397 .L23: + 398 .LBE6: + 69:Core/Src/ADBMS_Abstraction.c **** + 70:Core/Src/ADBMS_Abstraction.c **** module->status.CS_FLT = rxbuf[0] | (rxbuf[1] << 8); + 399 .loc 1 70 32 is_stmt 1 + 400 002e 3B7C ldrb r3, [r7, #16] @ zero_extendqisi2 + ARM GAS /tmp/cclV24WD.s page 9 + + + 401 0030 1AB2 sxth r2, r3 + 402 .loc 1 70 44 + 403 0032 7B7C ldrb r3, [r7, #17] @ zero_extendqisi2 + 404 .loc 1 70 36 + 405 0034 1BB2 sxth r3, r3 + 406 0036 1B02 lsls r3, r3, #8 + 407 0038 1BB2 sxth r3, r3 + 408 003a 1343 orrs r3, r3, r2 + 409 003c 1BB2 sxth r3, r3 + 410 003e 9AB2 uxth r2, r3 + 411 .loc 1 70 25 + 412 0040 7B68 ldr r3, [r7, #4] + 413 0042 A3F84820 strh r2, [r3, #72] @ movhi + 71:Core/Src/ADBMS_Abstraction.c **** module->status.CCTS = rxbuf[2] | (rxbuf[3] << 8); + 414 .loc 1 71 32 + 415 0046 BB7C ldrb r3, [r7, #18] @ zero_extendqisi2 + 416 0048 1AB2 sxth r2, r3 + 417 .loc 1 71 44 + 418 004a FB7C ldrb r3, [r7, #19] @ zero_extendqisi2 + 419 .loc 1 71 36 + 420 004c 1BB2 sxth r3, r3 + 421 004e 1B02 lsls r3, r3, #8 + 422 0050 1BB2 sxth r3, r3 + 423 0052 1343 orrs r3, r3, r2 + 424 0054 1BB2 sxth r3, r3 + 425 0056 C3F30C03 ubfx r3, r3, #0, #13 + 426 005a 99B2 uxth r1, r3 + 427 .loc 1 71 25 + 428 005c 7A68 ldr r2, [r7, #4] + 429 005e B2F84A30 ldrh r3, [r2, #74] @ movhi + 430 0062 61F3CF03 bfi r3, r1, #3, #13 + 431 0066 A2F84A30 strh r3, [r2, #74] @ movhi + 72:Core/Src/ADBMS_Abstraction.c **** module->status.VA_OV = (rxbuf[4] >> 7) & 0x01; + 432 .loc 1 72 33 + 433 006a 3B7D ldrb r3, [r7, #20] @ zero_extendqisi2 + 434 .loc 1 72 43 + 435 006c DB09 lsrs r3, r3, #7 + 436 006e DBB2 uxtb r3, r3 + 437 0070 03F00103 and r3, r3, #1 + 438 0074 D9B2 uxtb r1, r3 + 439 .loc 1 72 25 + 440 0076 7A68 ldr r2, [r7, #4] + 441 0078 92F84C30 ldrb r3, [r2, #76] + 442 007c 61F30003 bfi r3, r1, #0, #1 + 443 0080 82F84C30 strb r3, [r2, #76] + 73:Core/Src/ADBMS_Abstraction.c **** module->status.VA_UV = (rxbuf[4] >> 6) & 0x01; + 444 .loc 1 73 33 + 445 0084 3B7D ldrb r3, [r7, #20] @ zero_extendqisi2 + 446 .loc 1 73 43 + 447 0086 9B09 lsrs r3, r3, #6 + 448 0088 DBB2 uxtb r3, r3 + 449 008a 03F00103 and r3, r3, #1 + 450 008e D9B2 uxtb r1, r3 + 451 .loc 1 73 25 + 452 0090 7A68 ldr r2, [r7, #4] + 453 0092 92F84C30 ldrb r3, [r2, #76] + 454 0096 61F34103 bfi r3, r1, #1, #1 + ARM GAS /tmp/cclV24WD.s page 10 + + + 455 009a 82F84C30 strb r3, [r2, #76] + 74:Core/Src/ADBMS_Abstraction.c **** module->status.VD_OV = (rxbuf[4] >> 5) & 0x01; + 456 .loc 1 74 33 + 457 009e 3B7D ldrb r3, [r7, #20] @ zero_extendqisi2 + 458 .loc 1 74 43 + 459 00a0 5B09 lsrs r3, r3, #5 + 460 00a2 DBB2 uxtb r3, r3 + 461 00a4 03F00103 and r3, r3, #1 + 462 00a8 D9B2 uxtb r1, r3 + 463 .loc 1 74 25 + 464 00aa 7A68 ldr r2, [r7, #4] + 465 00ac 92F84C30 ldrb r3, [r2, #76] + 466 00b0 61F38203 bfi r3, r1, #2, #1 + 467 00b4 82F84C30 strb r3, [r2, #76] + 75:Core/Src/ADBMS_Abstraction.c **** module->status.VD_UV = (rxbuf[4] >> 4) & 0x01; + 468 .loc 1 75 33 + 469 00b8 3B7D ldrb r3, [r7, #20] @ zero_extendqisi2 + 470 .loc 1 75 43 + 471 00ba 1B09 lsrs r3, r3, #4 + 472 00bc DBB2 uxtb r3, r3 + 473 00be 03F00103 and r3, r3, #1 + 474 00c2 D9B2 uxtb r1, r3 + 475 .loc 1 75 25 + 476 00c4 7A68 ldr r2, [r7, #4] + 477 00c6 92F84C30 ldrb r3, [r2, #76] + 478 00ca 61F3C303 bfi r3, r1, #3, #1 + 479 00ce 82F84C30 strb r3, [r2, #76] + 76:Core/Src/ADBMS_Abstraction.c **** module->status.CED = (rxbuf[4] >> 3) & 0x01; + 480 .loc 1 76 33 + 481 00d2 3B7D ldrb r3, [r7, #20] @ zero_extendqisi2 + 482 .loc 1 76 43 + 483 00d4 DB08 lsrs r3, r3, #3 + 484 00d6 DBB2 uxtb r3, r3 + 485 00d8 03F00103 and r3, r3, #1 + 486 00dc D9B2 uxtb r1, r3 + 487 .loc 1 76 25 + 488 00de 7A68 ldr r2, [r7, #4] + 489 00e0 92F84C30 ldrb r3, [r2, #76] + 490 00e4 61F30413 bfi r3, r1, #4, #1 + 491 00e8 82F84C30 strb r3, [r2, #76] + 77:Core/Src/ADBMS_Abstraction.c **** module->status.CMED = (rxbuf[4] >> 2) & 0x01; + 492 .loc 1 77 33 + 493 00ec 3B7D ldrb r3, [r7, #20] @ zero_extendqisi2 + 494 .loc 1 77 43 + 495 00ee 9B08 lsrs r3, r3, #2 + 496 00f0 DBB2 uxtb r3, r3 + 497 00f2 03F00103 and r3, r3, #1 + 498 00f6 D9B2 uxtb r1, r3 + 499 .loc 1 77 25 + 500 00f8 7A68 ldr r2, [r7, #4] + 501 00fa 92F84C30 ldrb r3, [r2, #76] + 502 00fe 61F34513 bfi r3, r1, #5, #1 + 503 0102 82F84C30 strb r3, [r2, #76] + 78:Core/Src/ADBMS_Abstraction.c **** module->status.SED = (rxbuf[4] >> 1) & 0x01; + 504 .loc 1 78 33 + 505 0106 3B7D ldrb r3, [r7, #20] @ zero_extendqisi2 + 506 .loc 1 78 43 + ARM GAS /tmp/cclV24WD.s page 11 + + + 507 0108 5B08 lsrs r3, r3, #1 + 508 010a DBB2 uxtb r3, r3 + 509 010c 03F00103 and r3, r3, #1 + 510 0110 D9B2 uxtb r1, r3 + 511 .loc 1 78 25 + 512 0112 7A68 ldr r2, [r7, #4] + 513 0114 92F84C30 ldrb r3, [r2, #76] + 514 0118 61F38613 bfi r3, r1, #6, #1 + 515 011c 82F84C30 strb r3, [r2, #76] + 79:Core/Src/ADBMS_Abstraction.c **** module->status.SMED = (rxbuf[4] >> 0) & 0x01; + 516 .loc 1 79 33 + 517 0120 3B7D ldrb r3, [r7, #20] @ zero_extendqisi2 + 518 .loc 1 79 43 + 519 0122 03F00103 and r3, r3, #1 + 520 0126 D9B2 uxtb r1, r3 + 521 .loc 1 79 25 + 522 0128 7A68 ldr r2, [r7, #4] + 523 012a 92F84C30 ldrb r3, [r2, #76] + 524 012e 61F3C713 bfi r3, r1, #7, #1 + 525 0132 82F84C30 strb r3, [r2, #76] + 80:Core/Src/ADBMS_Abstraction.c **** module->status.VDEL = (rxbuf[5] >> 7) & 0x01; + 526 .loc 1 80 33 + 527 0136 7B7D ldrb r3, [r7, #21] @ zero_extendqisi2 + 528 .loc 1 80 43 + 529 0138 DB09 lsrs r3, r3, #7 + 530 013a DBB2 uxtb r3, r3 + 531 013c 03F00103 and r3, r3, #1 + 532 0140 D9B2 uxtb r1, r3 + 533 .loc 1 80 25 + 534 0142 7A68 ldr r2, [r7, #4] + 535 0144 92F84D30 ldrb r3, [r2, #77] + 536 0148 61F30003 bfi r3, r1, #0, #1 + 537 014c 82F84D30 strb r3, [r2, #77] + 81:Core/Src/ADBMS_Abstraction.c **** module->status.VDE = (rxbuf[5] >> 6) & 0x01; + 538 .loc 1 81 33 + 539 0150 7B7D ldrb r3, [r7, #21] @ zero_extendqisi2 + 540 .loc 1 81 43 + 541 0152 9B09 lsrs r3, r3, #6 + 542 0154 DBB2 uxtb r3, r3 + 543 0156 03F00103 and r3, r3, #1 + 544 015a D9B2 uxtb r1, r3 + 545 .loc 1 81 25 + 546 015c 7A68 ldr r2, [r7, #4] + 547 015e 92F84D30 ldrb r3, [r2, #77] + 548 0162 61F34103 bfi r3, r1, #1, #1 + 549 0166 82F84D30 strb r3, [r2, #77] + 82:Core/Src/ADBMS_Abstraction.c **** module->status.COMPARE= (rxbuf[5] >> 5) & 0x01; + 550 .loc 1 82 33 + 551 016a 7B7D ldrb r3, [r7, #21] @ zero_extendqisi2 + 552 .loc 1 82 43 + 553 016c 5B09 lsrs r3, r3, #5 + 554 016e DBB2 uxtb r3, r3 + 555 0170 03F00103 and r3, r3, #1 + 556 0174 D9B2 uxtb r1, r3 + 557 .loc 1 82 25 + 558 0176 7A68 ldr r2, [r7, #4] + 559 0178 92F84D30 ldrb r3, [r2, #77] + ARM GAS /tmp/cclV24WD.s page 12 + + + 560 017c 61F38203 bfi r3, r1, #2, #1 + 561 0180 82F84D30 strb r3, [r2, #77] + 83:Core/Src/ADBMS_Abstraction.c **** module->status.SPIFLT = (rxbuf[5] >> 4) & 0x01; + 562 .loc 1 83 33 + 563 0184 7B7D ldrb r3, [r7, #21] @ zero_extendqisi2 + 564 .loc 1 83 43 + 565 0186 1B09 lsrs r3, r3, #4 + 566 0188 DBB2 uxtb r3, r3 + 567 018a 03F00103 and r3, r3, #1 + 568 018e D9B2 uxtb r1, r3 + 569 .loc 1 83 25 + 570 0190 7A68 ldr r2, [r7, #4] + 571 0192 92F84D30 ldrb r3, [r2, #77] + 572 0196 61F3C303 bfi r3, r1, #3, #1 + 573 019a 82F84D30 strb r3, [r2, #77] + 84:Core/Src/ADBMS_Abstraction.c **** module->status.SLEEP = (rxbuf[5] >> 3) & 0x01; + 574 .loc 1 84 33 + 575 019e 7B7D ldrb r3, [r7, #21] @ zero_extendqisi2 + 576 .loc 1 84 43 + 577 01a0 DB08 lsrs r3, r3, #3 + 578 01a2 DBB2 uxtb r3, r3 + 579 01a4 03F00103 and r3, r3, #1 + 580 01a8 D9B2 uxtb r1, r3 + 581 .loc 1 84 25 + 582 01aa 7A68 ldr r2, [r7, #4] + 583 01ac 92F84D30 ldrb r3, [r2, #77] + 584 01b0 61F30413 bfi r3, r1, #4, #1 + 585 01b4 82F84D30 strb r3, [r2, #77] + 85:Core/Src/ADBMS_Abstraction.c **** module->status.THSD = (rxbuf[5] >> 2) & 0x01; + 586 .loc 1 85 33 + 587 01b8 7B7D ldrb r3, [r7, #21] @ zero_extendqisi2 + 588 .loc 1 85 43 + 589 01ba 9B08 lsrs r3, r3, #2 + 590 01bc DBB2 uxtb r3, r3 + 591 01be 03F00103 and r3, r3, #1 + 592 01c2 D9B2 uxtb r1, r3 + 593 .loc 1 85 25 + 594 01c4 7A68 ldr r2, [r7, #4] + 595 01c6 92F84D30 ldrb r3, [r2, #77] + 596 01ca 61F34513 bfi r3, r1, #5, #1 + 597 01ce 82F84D30 strb r3, [r2, #77] + 86:Core/Src/ADBMS_Abstraction.c **** module->status.TMODCHK= (rxbuf[5] >> 1) & 0x01; + 598 .loc 1 86 33 + 599 01d2 7B7D ldrb r3, [r7, #21] @ zero_extendqisi2 + 600 .loc 1 86 43 + 601 01d4 5B08 lsrs r3, r3, #1 + 602 01d6 DBB2 uxtb r3, r3 + 603 01d8 03F00103 and r3, r3, #1 + 604 01dc D9B2 uxtb r1, r3 + 605 .loc 1 86 25 + 606 01de 7A68 ldr r2, [r7, #4] + 607 01e0 92F84D30 ldrb r3, [r2, #77] + 608 01e4 61F38613 bfi r3, r1, #6, #1 + 609 01e8 82F84D30 strb r3, [r2, #77] + 87:Core/Src/ADBMS_Abstraction.c **** module->status.OSCCHK = (rxbuf[5] >> 0) & 0x01; + 610 .loc 1 87 33 + 611 01ec 7B7D ldrb r3, [r7, #21] @ zero_extendqisi2 + ARM GAS /tmp/cclV24WD.s page 13 + + + 612 .loc 1 87 43 + 613 01ee 03F00103 and r3, r3, #1 + 614 01f2 D9B2 uxtb r1, r3 + 615 .loc 1 87 25 + 616 01f4 7A68 ldr r2, [r7, #4] + 617 01f6 92F84D30 ldrb r3, [r2, #77] + 618 01fa 61F3C713 bfi r3, r1, #7, #1 + 619 01fe 82F84D30 strb r3, [r2, #77] + 88:Core/Src/ADBMS_Abstraction.c **** + 89:Core/Src/ADBMS_Abstraction.c **** if (pollCMD(PLAUX) == 0x0) { //TODO: check for SPI fault + 620 .loc 1 89 7 + 621 0202 40F21E70 movw r0, #1822 + 622 0206 FFF7FEFF bl pollCMD + 623 020a 0346 mov r3, r0 + 624 .loc 1 89 6 discriminator 1 + 625 020c 002B cmp r3, #0 + 626 020e 01D1 bne .L25 + 90:Core/Src/ADBMS_Abstraction.c **** return 0; // aux ADC data not ready + 627 .loc 1 90 12 + 628 0210 0023 movs r3, #0 + 629 0212 2FE2 b .L33 + 630 .L25: + 631 .LBB7: + 91:Core/Src/ADBMS_Abstraction.c **** } + 92:Core/Src/ADBMS_Abstraction.c **** + 93:Core/Src/ADBMS_Abstraction.c **** CHECK_RETURN(readCMD(RDAUXA, rxbuf, AUX_GROUP_A_SIZE)); + 632 .loc 1 93 3 + 633 0214 07F11003 add r3, r7, #16 + 634 0218 0622 movs r2, #6 + 635 021a 1946 mov r1, r3 + 636 021c 1920 movs r0, #25 + 637 021e FFF7FEFF bl readCMD + 638 0222 0346 mov r3, r0 + 639 0224 BB77 strb r3, [r7, #30] + 640 .loc 1 93 3 is_stmt 0 discriminator 1 + 641 0226 BB7F ldrb r3, [r7, #30] @ zero_extendqisi2 + 642 0228 002B cmp r3, #0 + 643 022a 01D0 beq .L26 + 644 022c BB7F ldrb r3, [r7, #30] @ zero_extendqisi2 + 645 .loc 1 93 3 + 646 022e 21E2 b .L33 + 647 .L26: + 648 .LBE7: + 94:Core/Src/ADBMS_Abstraction.c **** + 95:Core/Src/ADBMS_Abstraction.c **** module->auxVoltages[0] = mV_from_ADBMS6830(rxbuf[0] | (rxbuf[1] << 8)); + 649 .loc 1 95 28 is_stmt 1 + 650 0230 3B7C ldrb r3, [r7, #16] @ zero_extendqisi2 + 651 0232 1AB2 sxth r2, r3 + 652 0234 7B7C ldrb r3, [r7, #17] @ zero_extendqisi2 + 653 0236 1BB2 sxth r3, r3 + 654 0238 1B02 lsls r3, r3, #8 + 655 023a 1BB2 sxth r3, r3 + 656 023c 1343 orrs r3, r3, r2 + 657 023e 1BB2 sxth r3, r3 + 658 0240 1846 mov r0, r3 + 659 0242 FFF7FEFF bl __aeabi_i2d + 660 0246 0FF23843 adr r3, .L34 + ARM GAS /tmp/cclV24WD.s page 14 + + + 661 024a D3E90023 ldrd r2, [r3] + 662 024e FFF7FEFF bl __aeabi_dmul + 663 0252 0246 mov r2, r0 + 664 0254 0B46 mov r3, r1 + 665 0256 1046 mov r0, r2 + 666 0258 1946 mov r1, r3 + 667 025a 0FF22C43 adr r3, .L34+8 + 668 025e D3E90023 ldrd r2, [r3] + 669 0262 FFF7FEFF bl __aeabi_dadd + 670 0266 0246 mov r2, r0 + 671 0268 0B46 mov r3, r1 + 672 026a 1046 mov r0, r2 + 673 026c 1946 mov r1, r3 + 674 026e FFF7FEFF bl __aeabi_d2f + 675 0272 0246 mov r2, r0 @ float + 676 .loc 1 95 26 + 677 0274 7B68 ldr r3, [r7, #4] + 678 0276 1A62 str r2, [r3, #32] @ float + 96:Core/Src/ADBMS_Abstraction.c **** module->auxVoltages[1] = mV_from_ADBMS6830(rxbuf[2] | (rxbuf[3] << 8)); + 679 .loc 1 96 28 + 680 0278 BB7C ldrb r3, [r7, #18] @ zero_extendqisi2 + 681 027a 1AB2 sxth r2, r3 + 682 027c FB7C ldrb r3, [r7, #19] @ zero_extendqisi2 + 683 027e 1BB2 sxth r3, r3 + 684 0280 1B02 lsls r3, r3, #8 + 685 0282 1BB2 sxth r3, r3 + 686 0284 1343 orrs r3, r3, r2 + 687 0286 1BB2 sxth r3, r3 + 688 0288 1846 mov r0, r3 + 689 028a FFF7FEFF bl __aeabi_i2d + 690 028e FCA3 adr r3, .L34 + 691 0290 D3E90023 ldrd r2, [r3] + 692 0294 FFF7FEFF bl __aeabi_dmul + 693 0298 0246 mov r2, r0 + 694 029a 0B46 mov r3, r1 + 695 029c 1046 mov r0, r2 + 696 029e 1946 mov r1, r3 + 697 02a0 F9A3 adr r3, .L34+8 + 698 02a2 D3E90023 ldrd r2, [r3] + 699 02a6 FFF7FEFF bl __aeabi_dadd + 700 02aa 0246 mov r2, r0 + 701 02ac 0B46 mov r3, r1 + 702 02ae 1046 mov r0, r2 + 703 02b0 1946 mov r1, r3 + 704 02b2 FFF7FEFF bl __aeabi_d2f + 705 02b6 0246 mov r2, r0 @ float + 706 .loc 1 96 26 + 707 02b8 7B68 ldr r3, [r7, #4] + 708 02ba 5A62 str r2, [r3, #36] @ float + 97:Core/Src/ADBMS_Abstraction.c **** module->auxVoltages[2] = mV_from_ADBMS6830(rxbuf[4] | (rxbuf[5] << 8)); + 709 .loc 1 97 28 + 710 02bc 3B7D ldrb r3, [r7, #20] @ zero_extendqisi2 + 711 02be 1AB2 sxth r2, r3 + 712 02c0 7B7D ldrb r3, [r7, #21] @ zero_extendqisi2 + 713 02c2 1BB2 sxth r3, r3 + 714 02c4 1B02 lsls r3, r3, #8 + 715 02c6 1BB2 sxth r3, r3 + ARM GAS /tmp/cclV24WD.s page 15 + + + 716 02c8 1343 orrs r3, r3, r2 + 717 02ca 1BB2 sxth r3, r3 + 718 02cc 1846 mov r0, r3 + 719 02ce FFF7FEFF bl __aeabi_i2d + 720 02d2 EBA3 adr r3, .L34 + 721 02d4 D3E90023 ldrd r2, [r3] + 722 02d8 FFF7FEFF bl __aeabi_dmul + 723 02dc 0246 mov r2, r0 + 724 02de 0B46 mov r3, r1 + 725 02e0 1046 mov r0, r2 + 726 02e2 1946 mov r1, r3 + 727 02e4 E8A3 adr r3, .L34+8 + 728 02e6 D3E90023 ldrd r2, [r3] + 729 02ea FFF7FEFF bl __aeabi_dadd + 730 02ee 0246 mov r2, r0 + 731 02f0 0B46 mov r3, r1 + 732 02f2 1046 mov r0, r2 + 733 02f4 1946 mov r1, r3 + 734 02f6 FFF7FEFF bl __aeabi_d2f + 735 02fa 0246 mov r2, r0 @ float + 736 .loc 1 97 26 + 737 02fc 7B68 ldr r3, [r7, #4] + 738 02fe 9A62 str r2, [r3, #40] @ float + 739 .LBB8: + 98:Core/Src/ADBMS_Abstraction.c **** + 99:Core/Src/ADBMS_Abstraction.c **** CHECK_RETURN(readCMD(RDAUXB, rxbuf, AUX_GROUP_A_SIZE)); + 740 .loc 1 99 3 + 741 0300 07F11003 add r3, r7, #16 + 742 0304 0622 movs r2, #6 + 743 0306 1946 mov r1, r3 + 744 0308 1A20 movs r0, #26 + 745 030a FFF7FEFF bl readCMD + 746 030e 0346 mov r3, r0 + 747 0310 7B77 strb r3, [r7, #29] + 748 .loc 1 99 3 is_stmt 0 discriminator 1 + 749 0312 7B7F ldrb r3, [r7, #29] @ zero_extendqisi2 + 750 0314 002B cmp r3, #0 + 751 0316 01D0 beq .L27 + 752 0318 7B7F ldrb r3, [r7, #29] @ zero_extendqisi2 + 753 .loc 1 99 3 + 754 031a ABE1 b .L33 + 755 .L27: + 756 .LBE8: + 100:Core/Src/ADBMS_Abstraction.c **** + 101:Core/Src/ADBMS_Abstraction.c **** module->auxVoltages[3] = mV_from_ADBMS6830(rxbuf[0] | (rxbuf[1] << 8)); + 757 .loc 1 101 28 is_stmt 1 + 758 031c 3B7C ldrb r3, [r7, #16] @ zero_extendqisi2 + 759 031e 1AB2 sxth r2, r3 + 760 0320 7B7C ldrb r3, [r7, #17] @ zero_extendqisi2 + 761 0322 1BB2 sxth r3, r3 + 762 0324 1B02 lsls r3, r3, #8 + 763 0326 1BB2 sxth r3, r3 + 764 0328 1343 orrs r3, r3, r2 + 765 032a 1BB2 sxth r3, r3 + 766 032c 1846 mov r0, r3 + 767 032e FFF7FEFF bl __aeabi_i2d + 768 0332 D3A3 adr r3, .L34 + ARM GAS /tmp/cclV24WD.s page 16 + + + 769 0334 D3E90023 ldrd r2, [r3] + 770 0338 FFF7FEFF bl __aeabi_dmul + 771 033c 0246 mov r2, r0 + 772 033e 0B46 mov r3, r1 + 773 0340 1046 mov r0, r2 + 774 0342 1946 mov r1, r3 + 775 0344 D0A3 adr r3, .L34+8 + 776 0346 D3E90023 ldrd r2, [r3] + 777 034a FFF7FEFF bl __aeabi_dadd + 778 034e 0246 mov r2, r0 + 779 0350 0B46 mov r3, r1 + 780 0352 1046 mov r0, r2 + 781 0354 1946 mov r1, r3 + 782 0356 FFF7FEFF bl __aeabi_d2f + 783 035a 0246 mov r2, r0 @ float + 784 .loc 1 101 26 + 785 035c 7B68 ldr r3, [r7, #4] + 786 035e DA62 str r2, [r3, #44] @ float + 102:Core/Src/ADBMS_Abstraction.c **** module->auxVoltages[4] = mV_from_ADBMS6830(rxbuf[2] | (rxbuf[3] << 8)); + 787 .loc 1 102 28 + 788 0360 BB7C ldrb r3, [r7, #18] @ zero_extendqisi2 + 789 0362 1AB2 sxth r2, r3 + 790 0364 FB7C ldrb r3, [r7, #19] @ zero_extendqisi2 + 791 0366 1BB2 sxth r3, r3 + 792 0368 1B02 lsls r3, r3, #8 + 793 036a 1BB2 sxth r3, r3 + 794 036c 1343 orrs r3, r3, r2 + 795 036e 1BB2 sxth r3, r3 + 796 0370 1846 mov r0, r3 + 797 0372 FFF7FEFF bl __aeabi_i2d + 798 0376 C2A3 adr r3, .L34 + 799 0378 D3E90023 ldrd r2, [r3] + 800 037c FFF7FEFF bl __aeabi_dmul + 801 0380 0246 mov r2, r0 + 802 0382 0B46 mov r3, r1 + 803 0384 1046 mov r0, r2 + 804 0386 1946 mov r1, r3 + 805 0388 BFA3 adr r3, .L34+8 + 806 038a D3E90023 ldrd r2, [r3] + 807 038e FFF7FEFF bl __aeabi_dadd + 808 0392 0246 mov r2, r0 + 809 0394 0B46 mov r3, r1 + 810 0396 1046 mov r0, r2 + 811 0398 1946 mov r1, r3 + 812 039a FFF7FEFF bl __aeabi_d2f + 813 039e 0246 mov r2, r0 @ float + 814 .loc 1 102 26 + 815 03a0 7B68 ldr r3, [r7, #4] + 816 03a2 1A63 str r2, [r3, #48] @ float + 103:Core/Src/ADBMS_Abstraction.c **** module->auxVoltages[5] = mV_from_ADBMS6830(rxbuf[4] | (rxbuf[5] << 8)); + 817 .loc 1 103 28 + 818 03a4 3B7D ldrb r3, [r7, #20] @ zero_extendqisi2 + 819 03a6 1AB2 sxth r2, r3 + 820 03a8 7B7D ldrb r3, [r7, #21] @ zero_extendqisi2 + 821 03aa 1BB2 sxth r3, r3 + 822 03ac 1B02 lsls r3, r3, #8 + 823 03ae 1BB2 sxth r3, r3 + ARM GAS /tmp/cclV24WD.s page 17 + + + 824 03b0 1343 orrs r3, r3, r2 + 825 03b2 1BB2 sxth r3, r3 + 826 03b4 1846 mov r0, r3 + 827 03b6 FFF7FEFF bl __aeabi_i2d + 828 03ba B1A3 adr r3, .L34 + 829 03bc D3E90023 ldrd r2, [r3] + 830 03c0 FFF7FEFF bl __aeabi_dmul + 831 03c4 0246 mov r2, r0 + 832 03c6 0B46 mov r3, r1 + 833 03c8 1046 mov r0, r2 + 834 03ca 1946 mov r1, r3 + 835 03cc AEA3 adr r3, .L34+8 + 836 03ce D3E90023 ldrd r2, [r3] + 837 03d2 FFF7FEFF bl __aeabi_dadd + 838 03d6 0246 mov r2, r0 + 839 03d8 0B46 mov r3, r1 + 840 03da 1046 mov r0, r2 + 841 03dc 1946 mov r1, r3 + 842 03de FFF7FEFF bl __aeabi_d2f + 843 03e2 0246 mov r2, r0 @ float + 844 .loc 1 103 26 + 845 03e4 7B68 ldr r3, [r7, #4] + 846 03e6 5A63 str r2, [r3, #52] @ float + 847 .LBB9: + 104:Core/Src/ADBMS_Abstraction.c **** + 105:Core/Src/ADBMS_Abstraction.c **** CHECK_RETURN(readCMD(RDAUXC, rxbuf, AUX_GROUP_A_SIZE)); + 848 .loc 1 105 3 + 849 03e8 07F11003 add r3, r7, #16 + 850 03ec 0622 movs r2, #6 + 851 03ee 1946 mov r1, r3 + 852 03f0 1B20 movs r0, #27 + 853 03f2 FFF7FEFF bl readCMD + 854 03f6 0346 mov r3, r0 + 855 03f8 3B77 strb r3, [r7, #28] + 856 .loc 1 105 3 is_stmt 0 discriminator 1 + 857 03fa 3B7F ldrb r3, [r7, #28] @ zero_extendqisi2 + 858 03fc 002B cmp r3, #0 + 859 03fe 01D0 beq .L28 + 860 0400 3B7F ldrb r3, [r7, #28] @ zero_extendqisi2 + 861 .loc 1 105 3 + 862 0402 37E1 b .L33 + 863 .L28: + 864 .LBE9: + 106:Core/Src/ADBMS_Abstraction.c **** + 107:Core/Src/ADBMS_Abstraction.c **** module->auxVoltages[6] = mV_from_ADBMS6830(rxbuf[0] | (rxbuf[1] << 8)); + 865 .loc 1 107 28 is_stmt 1 + 866 0404 3B7C ldrb r3, [r7, #16] @ zero_extendqisi2 + 867 0406 1AB2 sxth r2, r3 + 868 0408 7B7C ldrb r3, [r7, #17] @ zero_extendqisi2 + 869 040a 1BB2 sxth r3, r3 + 870 040c 1B02 lsls r3, r3, #8 + 871 040e 1BB2 sxth r3, r3 + 872 0410 1343 orrs r3, r3, r2 + 873 0412 1BB2 sxth r3, r3 + 874 0414 1846 mov r0, r3 + 875 0416 FFF7FEFF bl __aeabi_i2d + 876 041a 99A3 adr r3, .L34 + ARM GAS /tmp/cclV24WD.s page 18 + + + 877 041c D3E90023 ldrd r2, [r3] + 878 0420 FFF7FEFF bl __aeabi_dmul + 879 0424 0246 mov r2, r0 + 880 0426 0B46 mov r3, r1 + 881 0428 1046 mov r0, r2 + 882 042a 1946 mov r1, r3 + 883 042c 96A3 adr r3, .L34+8 + 884 042e D3E90023 ldrd r2, [r3] + 885 0432 FFF7FEFF bl __aeabi_dadd + 886 0436 0246 mov r2, r0 + 887 0438 0B46 mov r3, r1 + 888 043a 1046 mov r0, r2 + 889 043c 1946 mov r1, r3 + 890 043e FFF7FEFF bl __aeabi_d2f + 891 0442 0246 mov r2, r0 @ float + 892 .loc 1 107 26 + 893 0444 7B68 ldr r3, [r7, #4] + 894 0446 9A63 str r2, [r3, #56] @ float + 108:Core/Src/ADBMS_Abstraction.c **** module->auxVoltages[7] = mV_from_ADBMS6830(rxbuf[2] | (rxbuf[3] << 8)); + 895 .loc 1 108 28 + 896 0448 BB7C ldrb r3, [r7, #18] @ zero_extendqisi2 + 897 044a 1AB2 sxth r2, r3 + 898 044c FB7C ldrb r3, [r7, #19] @ zero_extendqisi2 + 899 044e 1BB2 sxth r3, r3 + 900 0450 1B02 lsls r3, r3, #8 + 901 0452 1BB2 sxth r3, r3 + 902 0454 1343 orrs r3, r3, r2 + 903 0456 1BB2 sxth r3, r3 + 904 0458 1846 mov r0, r3 + 905 045a FFF7FEFF bl __aeabi_i2d + 906 045e 88A3 adr r3, .L34 + 907 0460 D3E90023 ldrd r2, [r3] + 908 0464 FFF7FEFF bl __aeabi_dmul + 909 0468 0246 mov r2, r0 + 910 046a 0B46 mov r3, r1 + 911 046c 1046 mov r0, r2 + 912 046e 1946 mov r1, r3 + 913 0470 85A3 adr r3, .L34+8 + 914 0472 D3E90023 ldrd r2, [r3] + 915 0476 FFF7FEFF bl __aeabi_dadd + 916 047a 0246 mov r2, r0 + 917 047c 0B46 mov r3, r1 + 918 047e 1046 mov r0, r2 + 919 0480 1946 mov r1, r3 + 920 0482 FFF7FEFF bl __aeabi_d2f + 921 0486 0246 mov r2, r0 @ float + 922 .loc 1 108 26 + 923 0488 7B68 ldr r3, [r7, #4] + 924 048a DA63 str r2, [r3, #60] @ float + 109:Core/Src/ADBMS_Abstraction.c **** module->auxVoltages[8] = mV_from_ADBMS6830(rxbuf[4] | (rxbuf[5] << 8)); + 925 .loc 1 109 28 + 926 048c 3B7D ldrb r3, [r7, #20] @ zero_extendqisi2 + 927 048e 1AB2 sxth r2, r3 + 928 0490 7B7D ldrb r3, [r7, #21] @ zero_extendqisi2 + 929 0492 1BB2 sxth r3, r3 + 930 0494 1B02 lsls r3, r3, #8 + 931 0496 1BB2 sxth r3, r3 + ARM GAS /tmp/cclV24WD.s page 19 + + + 932 0498 1343 orrs r3, r3, r2 + 933 049a 1BB2 sxth r3, r3 + 934 049c 1846 mov r0, r3 + 935 049e FFF7FEFF bl __aeabi_i2d + 936 04a2 77A3 adr r3, .L34 + 937 04a4 D3E90023 ldrd r2, [r3] + 938 04a8 FFF7FEFF bl __aeabi_dmul + 939 04ac 0246 mov r2, r0 + 940 04ae 0B46 mov r3, r1 + 941 04b0 1046 mov r0, r2 + 942 04b2 1946 mov r1, r3 + 943 04b4 74A3 adr r3, .L34+8 + 944 04b6 D3E90023 ldrd r2, [r3] + 945 04ba FFF7FEFF bl __aeabi_dadd + 946 04be 0246 mov r2, r0 + 947 04c0 0B46 mov r3, r1 + 948 04c2 1046 mov r0, r2 + 949 04c4 1946 mov r1, r3 + 950 04c6 FFF7FEFF bl __aeabi_d2f + 951 04ca 0246 mov r2, r0 @ float + 952 .loc 1 109 26 + 953 04cc 7B68 ldr r3, [r7, #4] + 954 04ce 1A64 str r2, [r3, #64] @ float + 955 .LBB10: + 110:Core/Src/ADBMS_Abstraction.c **** + 111:Core/Src/ADBMS_Abstraction.c **** CHECK_RETURN(readCMD(RDAUXD, rxbuf, AUX_GROUP_A_SIZE)); + 956 .loc 1 111 3 + 957 04d0 07F11003 add r3, r7, #16 + 958 04d4 0622 movs r2, #6 + 959 04d6 1946 mov r1, r3 + 960 04d8 1F20 movs r0, #31 + 961 04da FFF7FEFF bl readCMD + 962 04de 0346 mov r3, r0 + 963 04e0 FB76 strb r3, [r7, #27] + 964 .loc 1 111 3 is_stmt 0 discriminator 1 + 965 04e2 FB7E ldrb r3, [r7, #27] @ zero_extendqisi2 + 966 04e4 002B cmp r3, #0 + 967 04e6 01D0 beq .L29 + 968 04e8 FB7E ldrb r3, [r7, #27] @ zero_extendqisi2 + 969 .loc 1 111 3 + 970 04ea C3E0 b .L33 + 971 .L29: + 972 .LBE10: + 112:Core/Src/ADBMS_Abstraction.c **** + 113:Core/Src/ADBMS_Abstraction.c **** module->auxVoltages[9] = mV_from_ADBMS6830(rxbuf[0] | (rxbuf[1] << 8)); + 973 .loc 1 113 28 is_stmt 1 + 974 04ec 3B7C ldrb r3, [r7, #16] @ zero_extendqisi2 + 975 04ee 1AB2 sxth r2, r3 + 976 04f0 7B7C ldrb r3, [r7, #17] @ zero_extendqisi2 + 977 04f2 1BB2 sxth r3, r3 + 978 04f4 1B02 lsls r3, r3, #8 + 979 04f6 1BB2 sxth r3, r3 + 980 04f8 1343 orrs r3, r3, r2 + 981 04fa 1BB2 sxth r3, r3 + 982 04fc 1846 mov r0, r3 + 983 04fe FFF7FEFF bl __aeabi_i2d + 984 0502 5FA3 adr r3, .L34 + ARM GAS /tmp/cclV24WD.s page 20 + + + 985 0504 D3E90023 ldrd r2, [r3] + 986 0508 FFF7FEFF bl __aeabi_dmul + 987 050c 0246 mov r2, r0 + 988 050e 0B46 mov r3, r1 + 989 0510 1046 mov r0, r2 + 990 0512 1946 mov r1, r3 + 991 0514 5CA3 adr r3, .L34+8 + 992 0516 D3E90023 ldrd r2, [r3] + 993 051a FFF7FEFF bl __aeabi_dadd + 994 051e 0246 mov r2, r0 + 995 0520 0B46 mov r3, r1 + 996 0522 1046 mov r0, r2 + 997 0524 1946 mov r1, r3 + 998 0526 FFF7FEFF bl __aeabi_d2f + 999 052a 0246 mov r2, r0 @ float + 1000 .loc 1 113 26 + 1001 052c 7B68 ldr r3, [r7, #4] + 1002 052e 5A64 str r2, [r3, #68] @ float + 1003 .LBB11: + 114:Core/Src/ADBMS_Abstraction.c **** + 115:Core/Src/ADBMS_Abstraction.c **** uint8 rxbuffer[STATUS_GROUP_A_SIZE]; + 116:Core/Src/ADBMS_Abstraction.c **** + 117:Core/Src/ADBMS_Abstraction.c **** CHECK_RETURN(readCMD(RDSTATA, rxbuffer, STATUS_GROUP_A_SIZE)); + 1004 .loc 1 117 3 + 1005 0530 07F10803 add r3, r7, #8 + 1006 0534 0622 movs r2, #6 + 1007 0536 1946 mov r1, r3 + 1008 0538 3020 movs r0, #48 + 1009 053a FFF7FEFF bl readCMD + 1010 053e 0346 mov r3, r0 + 1011 0540 BB76 strb r3, [r7, #26] + 1012 .loc 1 117 3 is_stmt 0 discriminator 1 + 1013 0542 BB7E ldrb r3, [r7, #26] @ zero_extendqisi2 + 1014 0544 002B cmp r3, #0 + 1015 0546 01D0 beq .L30 + 1016 0548 BB7E ldrb r3, [r7, #26] @ zero_extendqisi2 + 1017 .loc 1 117 3 + 1018 054a 93E0 b .L33 + 1019 .L30: + 1020 .LBE11: + 118:Core/Src/ADBMS_Abstraction.c **** + 119:Core/Src/ADBMS_Abstraction.c **** module->internalDieTemp = rxbuffer[2] | (rxbuffer[3] << 8); + 1021 .loc 1 119 37 is_stmt 1 + 1022 054c BB7A ldrb r3, [r7, #10] @ zero_extendqisi2 + 1023 054e 1AB2 sxth r2, r3 + 1024 .loc 1 119 52 + 1025 0550 FB7A ldrb r3, [r7, #11] @ zero_extendqisi2 + 1026 .loc 1 119 41 + 1027 0552 1BB2 sxth r3, r3 + 1028 0554 1B02 lsls r3, r3, #8 + 1029 0556 1BB2 sxth r3, r3 + 1030 0558 1343 orrs r3, r3, r2 + 1031 055a 1BB2 sxth r3, r3 + 1032 055c 9AB2 uxth r2, r3 + 1033 .loc 1 119 27 + 1034 055e 7B68 ldr r3, [r7, #4] + 1035 0560 A3F84E20 strh r2, [r3, #78] @ movhi + ARM GAS /tmp/cclV24WD.s page 21 + + + 1036 .LBB12: + 120:Core/Src/ADBMS_Abstraction.c **** + 121:Core/Src/ADBMS_Abstraction.c **** CHECK_RETURN(readCMD(RDSTATB, rxbuffer, STATUS_GROUP_B_SIZE)); + 1037 .loc 1 121 3 + 1038 0564 07F10803 add r3, r7, #8 + 1039 0568 0622 movs r2, #6 + 1040 056a 1946 mov r1, r3 + 1041 056c 3120 movs r0, #49 + 1042 056e FFF7FEFF bl readCMD + 1043 0572 0346 mov r3, r0 + 1044 0574 7B76 strb r3, [r7, #25] + 1045 .loc 1 121 3 is_stmt 0 discriminator 1 + 1046 0576 7B7E ldrb r3, [r7, #25] @ zero_extendqisi2 + 1047 0578 002B cmp r3, #0 + 1048 057a 01D0 beq .L31 + 1049 057c 7B7E ldrb r3, [r7, #25] @ zero_extendqisi2 + 1050 .loc 1 121 3 + 1051 057e 79E0 b .L33 + 1052 .L31: + 1053 .LBE12: + 122:Core/Src/ADBMS_Abstraction.c **** module->digitalSupplyVoltage = mV_from_ADBMS6830(rxbuffer[0] | (rxbuffer[1] << 8)); + 1054 .loc 1 122 34 is_stmt 1 + 1055 0580 3B7A ldrb r3, [r7, #8] @ zero_extendqisi2 + 1056 0582 1AB2 sxth r2, r3 + 1057 0584 7B7A ldrb r3, [r7, #9] @ zero_extendqisi2 + 1058 0586 1BB2 sxth r3, r3 + 1059 0588 1B02 lsls r3, r3, #8 + 1060 058a 1BB2 sxth r3, r3 + 1061 058c 1343 orrs r3, r3, r2 + 1062 058e 1BB2 sxth r3, r3 + 1063 0590 1846 mov r0, r3 + 1064 0592 FFF7FEFF bl __aeabi_i2d + 1065 0596 3AA3 adr r3, .L34 + 1066 0598 D3E90023 ldrd r2, [r3] + 1067 059c FFF7FEFF bl __aeabi_dmul + 1068 05a0 0246 mov r2, r0 + 1069 05a2 0B46 mov r3, r1 + 1070 05a4 1046 mov r0, r2 + 1071 05a6 1946 mov r1, r3 + 1072 05a8 37A3 adr r3, .L34+8 + 1073 05aa D3E90023 ldrd r2, [r3] + 1074 05ae FFF7FEFF bl __aeabi_dadd + 1075 05b2 0246 mov r2, r0 + 1076 05b4 0B46 mov r3, r1 + 1077 .loc 1 122 32 + 1078 05b6 1046 mov r0, r2 + 1079 05b8 1946 mov r1, r3 + 1080 05ba FFF7FEFF bl __aeabi_d2uiz + 1081 05be 0346 mov r3, r0 + 1082 05c0 9AB2 uxth r2, r3 + 1083 05c2 7B68 ldr r3, [r7, #4] + 1084 05c4 A3F85220 strh r2, [r3, #82] @ movhi + 123:Core/Src/ADBMS_Abstraction.c **** module->analogSupplyVoltage = mV_from_ADBMS6830(rxbuffer[2] | (rxbuffer[3] << 8)); + 1085 .loc 1 123 34 + 1086 05c8 BB7A ldrb r3, [r7, #10] @ zero_extendqisi2 + 1087 05ca 1AB2 sxth r2, r3 + 1088 05cc FB7A ldrb r3, [r7, #11] @ zero_extendqisi2 + ARM GAS /tmp/cclV24WD.s page 22 + + + 1089 05ce 1BB2 sxth r3, r3 + 1090 05d0 1B02 lsls r3, r3, #8 + 1091 05d2 1BB2 sxth r3, r3 + 1092 05d4 1343 orrs r3, r3, r2 + 1093 05d6 1BB2 sxth r3, r3 + 1094 05d8 1846 mov r0, r3 + 1095 05da FFF7FEFF bl __aeabi_i2d + 1096 05de 28A3 adr r3, .L34 + 1097 05e0 D3E90023 ldrd r2, [r3] + 1098 05e4 FFF7FEFF bl __aeabi_dmul + 1099 05e8 0246 mov r2, r0 + 1100 05ea 0B46 mov r3, r1 + 1101 05ec 1046 mov r0, r2 + 1102 05ee 1946 mov r1, r3 + 1103 05f0 25A3 adr r3, .L34+8 + 1104 05f2 D3E90023 ldrd r2, [r3] + 1105 05f6 FFF7FEFF bl __aeabi_dadd + 1106 05fa 0246 mov r2, r0 + 1107 05fc 0B46 mov r3, r1 + 1108 .loc 1 123 32 + 1109 05fe 1046 mov r0, r2 + 1110 0600 1946 mov r1, r3 + 1111 0602 FFF7FEFF bl __aeabi_d2uiz + 1112 0606 0346 mov r3, r0 + 1113 0608 9AB2 uxth r2, r3 + 1114 060a 7B68 ldr r3, [r7, #4] + 1115 060c A3F85020 strh r2, [r3, #80] @ movhi + 124:Core/Src/ADBMS_Abstraction.c **** module->refVoltage = mV_from_ADBMS6830(rxbuffer[4] | (rxbuffer[5] << 8)); + 1116 .loc 1 124 34 + 1117 0610 3B7B ldrb r3, [r7, #12] @ zero_extendqisi2 + 1118 0612 1AB2 sxth r2, r3 + 1119 0614 7B7B ldrb r3, [r7, #13] @ zero_extendqisi2 + 1120 0616 1BB2 sxth r3, r3 + 1121 0618 1B02 lsls r3, r3, #8 + 1122 061a 1BB2 sxth r3, r3 + 1123 061c 1343 orrs r3, r3, r2 + 1124 061e 1BB2 sxth r3, r3 + 1125 0620 1846 mov r0, r3 + 1126 0622 FFF7FEFF bl __aeabi_i2d + 1127 0626 16A3 adr r3, .L34 + 1128 0628 D3E90023 ldrd r2, [r3] + 1129 062c FFF7FEFF bl __aeabi_dmul + 1130 0630 0246 mov r2, r0 + 1131 0632 0B46 mov r3, r1 + 1132 0634 1046 mov r0, r2 + 1133 0636 1946 mov r1, r3 + 1134 0638 13A3 adr r3, .L34+8 + 1135 063a D3E90023 ldrd r2, [r3] + 1136 063e FFF7FEFF bl __aeabi_dadd + 1137 0642 0246 mov r2, r0 + 1138 0644 0B46 mov r3, r1 + 1139 .loc 1 124 32 + 1140 0646 1046 mov r0, r2 + 1141 0648 1946 mov r1, r3 + 1142 064a FFF7FEFF bl __aeabi_d2uiz + 1143 064e 0346 mov r3, r0 + 1144 0650 9AB2 uxth r2, r3 + ARM GAS /tmp/cclV24WD.s page 23 + + + 1145 0652 7B68 ldr r3, [r7, #4] + 1146 0654 A3F85620 strh r2, [r3, #86] @ movhi + 1147 .LBB13: + 125:Core/Src/ADBMS_Abstraction.c **** + 126:Core/Src/ADBMS_Abstraction.c **** CHECK_RETURN(writeCMD(ADAX | ADAX_CONV_ALL, NULL, 0)); //start aux measurement for next cycle + 1148 .loc 1 126 3 + 1149 0658 0022 movs r2, #0 + 1150 065a 0021 movs r1, #0 + 1151 065c 4FF48260 mov r0, #1040 + 1152 0660 FFF7FEFF bl writeCMD + 1153 0664 0346 mov r3, r0 + 1154 0666 3B76 strb r3, [r7, #24] + 1155 .loc 1 126 3 is_stmt 0 discriminator 1 + 1156 0668 3B7E ldrb r3, [r7, #24] @ zero_extendqisi2 + 1157 066a 002B cmp r3, #0 + 1158 066c 01D0 beq .L32 + 1159 066e 3B7E ldrb r3, [r7, #24] @ zero_extendqisi2 + 1160 .loc 1 126 3 + 1161 0670 00E0 b .L33 + 1162 .L32: + 1163 .LBE13: + 127:Core/Src/ADBMS_Abstraction.c **** + 128:Core/Src/ADBMS_Abstraction.c **** return 0; + 1164 .loc 1 128 10 is_stmt 1 + 1165 0672 0023 movs r3, #0 + 1166 .L33: + 129:Core/Src/ADBMS_Abstraction.c **** } + 1167 .loc 1 129 1 + 1168 0674 1846 mov r0, r3 + 1169 0676 2037 adds r7, r7, #32 + 1170 .cfi_def_cfa_offset 8 + 1171 0678 BD46 mov sp, r7 + 1172 .cfi_def_cfa_register 13 + 1173 @ sp needed + 1174 067a 80BD pop {r7, pc} + 1175 .L35: + 1176 067c AFF30080 .align 3 + 1177 .L34: + 1178 0680 33333333 .word 858993459 + 1179 0684 3333C33F .word 1069757235 + 1180 0688 00000000 .word 0 + 1181 068c 00709740 .word 1083666432 + 1182 .cfi_endproc + 1183 .LFE135: + 1185 .section .text.amsConfigBalancing,"ax",%progbits + 1186 .align 1 + 1187 .global amsConfigBalancing + 1188 .syntax unified + 1189 .thumb + 1190 .thumb_func + 1192 amsConfigBalancing: + 1193 .LFB136: + 130:Core/Src/ADBMS_Abstraction.c **** + 131:Core/Src/ADBMS_Abstraction.c **** uint8 amsConfigBalancing(uint32 channels, uint8 dutyCycle) { + 1194 .loc 1 131 60 + 1195 .cfi_startproc + 1196 @ args = 0, pretend = 0, frame = 24 + ARM GAS /tmp/cclV24WD.s page 24 + + + 1197 @ frame_needed = 1, uses_anonymous_args = 0 + 1198 0000 80B5 push {r7, lr} + 1199 .cfi_def_cfa_offset 8 + 1200 .cfi_offset 7, -8 + 1201 .cfi_offset 14, -4 + 1202 0002 86B0 sub sp, sp, #24 + 1203 .cfi_def_cfa_offset 32 + 1204 0004 00AF add r7, sp, #0 + 1205 .cfi_def_cfa_register 7 + 1206 0006 7860 str r0, [r7, #4] + 1207 0008 0B46 mov r3, r1 + 1208 000a FB70 strb r3, [r7, #3] + 132:Core/Src/ADBMS_Abstraction.c **** uint8 buffer_a[PWM_GROUP_A_SIZE] = {}; + 1209 .loc 1 132 9 + 1210 000c 07F10C03 add r3, r7, #12 + 1211 0010 0022 movs r2, #0 + 1212 0012 1A60 str r2, [r3] + 1213 0014 9A80 strh r2, [r3, #4] @ movhi + 133:Core/Src/ADBMS_Abstraction.c **** uint8 buffer_b[PWM_GROUP_B_SIZE] = {}; + 1214 .loc 1 133 9 + 1215 0016 0023 movs r3, #0 + 1216 0018 3B81 strh r3, [r7, #8] @ movhi + 1217 .LBB14: + 134:Core/Src/ADBMS_Abstraction.c **** CHECK_RETURN(writeCMD(ADCV | ADCV_CONT, NULL, 0)); //start continuous cell voltage measurement wi + 1218 .loc 1 134 3 + 1219 001a 0022 movs r2, #0 + 1220 001c 0021 movs r1, #0 + 1221 001e 4FF43870 mov r0, #736 + 1222 0022 FFF7FEFF bl writeCMD + 1223 0026 0346 mov r3, r0 + 1224 0028 FB75 strb r3, [r7, #23] + 1225 .loc 1 134 3 is_stmt 0 discriminator 1 + 1226 002a FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 1227 002c 002B cmp r3, #0 + 1228 002e 01D0 beq .L37 + 1229 0030 FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 1230 .loc 1 134 3 + 1231 0032 FDE0 b .L76 + 1232 .L37: + 1233 .LBE14: + 1234 .LBB15: + 135:Core/Src/ADBMS_Abstraction.c **** CHECK_RETURN(readCMD(RDPWMA, buffer_a, PWM_GROUP_A_SIZE)); + 1235 .loc 1 135 3 is_stmt 1 + 1236 0034 07F10C03 add r3, r7, #12 + 1237 0038 0622 movs r2, #6 + 1238 003a 1946 mov r1, r3 + 1239 003c 2220 movs r0, #34 + 1240 003e FFF7FEFF bl readCMD + 1241 0042 0346 mov r3, r0 + 1242 0044 BB75 strb r3, [r7, #22] + 1243 .loc 1 135 3 is_stmt 0 discriminator 1 + 1244 0046 BB7D ldrb r3, [r7, #22] @ zero_extendqisi2 + 1245 0048 002B cmp r3, #0 + 1246 004a 01D0 beq .L39 + 1247 004c BB7D ldrb r3, [r7, #22] @ zero_extendqisi2 + 1248 .loc 1 135 3 + 1249 004e EFE0 b .L76 + ARM GAS /tmp/cclV24WD.s page 25 + + + 1250 .L39: + 1251 .LBE15: + 1252 .LBB16: + 136:Core/Src/ADBMS_Abstraction.c **** CHECK_RETURN(readCMD(RDPWMB, buffer_b, PWM_GROUP_B_SIZE)); + 1253 .loc 1 136 3 is_stmt 1 + 1254 0050 07F10803 add r3, r7, #8 + 1255 0054 0222 movs r2, #2 + 1256 0056 1946 mov r1, r3 + 1257 0058 2320 movs r0, #35 + 1258 005a FFF7FEFF bl readCMD + 1259 005e 0346 mov r3, r0 + 1260 0060 7B75 strb r3, [r7, #21] + 1261 .loc 1 136 3 is_stmt 0 discriminator 1 + 1262 0062 7B7D ldrb r3, [r7, #21] @ zero_extendqisi2 + 1263 0064 002B cmp r3, #0 + 1264 0066 01D0 beq .L40 + 1265 0068 7B7D ldrb r3, [r7, #21] @ zero_extendqisi2 + 1266 .loc 1 136 3 + 1267 006a E1E0 b .L76 + 1268 .L40: + 1269 .LBE16: + 137:Core/Src/ADBMS_Abstraction.c **** + 138:Core/Src/ADBMS_Abstraction.c **** if (dutyCycle > 0x0F) { // there are only 4 bits for duty cycle + 1270 .loc 1 138 6 is_stmt 1 + 1271 006c FB78 ldrb r3, [r7, #3] @ zero_extendqisi2 + 1272 006e 0F2B cmp r3, #15 + 1273 0070 01D9 bls .L41 + 139:Core/Src/ADBMS_Abstraction.c **** return 1; + 1274 .loc 1 139 12 + 1275 0072 0123 movs r3, #1 + 1276 0074 DCE0 b .L76 + 1277 .L41: + 140:Core/Src/ADBMS_Abstraction.c **** } + 141:Core/Src/ADBMS_Abstraction.c **** + 142:Core/Src/ADBMS_Abstraction.c **** buffer_a[0] = ((channels & (1 << 0)) ? dutyCycle : 0) | ((channels & (1 << 1)) ? (dutyCycle << 4) + 1278 .loc 1 142 28 + 1279 0076 7B68 ldr r3, [r7, #4] + 1280 0078 03F00103 and r3, r3, #1 + 1281 .loc 1 142 57 + 1282 007c 002B cmp r3, #0 + 1283 007e 02D0 beq .L42 + 1284 .loc 1 142 57 is_stmt 0 discriminator 1 + 1285 0080 97F90320 ldrsb r2, [r7, #3] + 1286 0084 00E0 b .L43 + 1287 .L42: + 1288 .loc 1 142 57 discriminator 2 + 1289 0086 0022 movs r2, #0 + 1290 .L43: + 1291 .loc 1 142 70 is_stmt 1 discriminator 4 + 1292 0088 7B68 ldr r3, [r7, #4] + 1293 008a 03F00203 and r3, r3, #2 + 1294 .loc 1 142 57 discriminator 4 + 1295 008e 002B cmp r3, #0 + 1296 0090 04D0 beq .L44 + 1297 .loc 1 142 57 is_stmt 0 discriminator 5 + 1298 0092 97F90330 ldrsb r3, [r7, #3] + 1299 0096 1B01 lsls r3, r3, #4 + ARM GAS /tmp/cclV24WD.s page 26 + + + 1300 0098 5BB2 sxtb r3, r3 + 1301 009a 00E0 b .L45 + 1302 .L44: + 1303 .loc 1 142 57 discriminator 6 + 1304 009c 0023 movs r3, #0 + 1305 .L45: + 1306 .loc 1 142 57 discriminator 8 + 1307 009e 1343 orrs r3, r3, r2 + 1308 00a0 5BB2 sxtb r3, r3 + 1309 00a2 DBB2 uxtb r3, r3 + 1310 .loc 1 142 15 is_stmt 1 discriminator 8 + 1311 00a4 3B73 strb r3, [r7, #12] + 143:Core/Src/ADBMS_Abstraction.c **** buffer_a[1] = ((channels & (1 << 2)) ? dutyCycle : 0) | ((channels & (1 << 3)) ? (dutyCycle << 4) + 1312 .loc 1 143 28 + 1313 00a6 7B68 ldr r3, [r7, #4] + 1314 00a8 03F00403 and r3, r3, #4 + 1315 .loc 1 143 57 + 1316 00ac 002B cmp r3, #0 + 1317 00ae 02D0 beq .L46 + 1318 .loc 1 143 57 is_stmt 0 discriminator 1 + 1319 00b0 97F90320 ldrsb r2, [r7, #3] + 1320 00b4 00E0 b .L47 + 1321 .L46: + 1322 .loc 1 143 57 discriminator 2 + 1323 00b6 0022 movs r2, #0 + 1324 .L47: + 1325 .loc 1 143 70 is_stmt 1 discriminator 4 + 1326 00b8 7B68 ldr r3, [r7, #4] + 1327 00ba 03F00803 and r3, r3, #8 + 1328 .loc 1 143 57 discriminator 4 + 1329 00be 002B cmp r3, #0 + 1330 00c0 04D0 beq .L48 + 1331 .loc 1 143 57 is_stmt 0 discriminator 5 + 1332 00c2 97F90330 ldrsb r3, [r7, #3] + 1333 00c6 1B01 lsls r3, r3, #4 + 1334 00c8 5BB2 sxtb r3, r3 + 1335 00ca 00E0 b .L49 + 1336 .L48: + 1337 .loc 1 143 57 discriminator 6 + 1338 00cc 0023 movs r3, #0 + 1339 .L49: + 1340 .loc 1 143 57 discriminator 8 + 1341 00ce 1343 orrs r3, r3, r2 + 1342 00d0 5BB2 sxtb r3, r3 + 1343 00d2 DBB2 uxtb r3, r3 + 1344 .loc 1 143 15 is_stmt 1 discriminator 8 + 1345 00d4 7B73 strb r3, [r7, #13] + 144:Core/Src/ADBMS_Abstraction.c **** buffer_a[2] = ((channels & (1 << 4)) ? dutyCycle : 0) | ((channels & (1 << 5)) ? (dutyCycle << 4) + 1346 .loc 1 144 28 + 1347 00d6 7B68 ldr r3, [r7, #4] + 1348 00d8 03F01003 and r3, r3, #16 + 1349 .loc 1 144 57 + 1350 00dc 002B cmp r3, #0 + 1351 00de 02D0 beq .L50 + 1352 .loc 1 144 57 is_stmt 0 discriminator 1 + 1353 00e0 97F90320 ldrsb r2, [r7, #3] + 1354 00e4 00E0 b .L51 + ARM GAS /tmp/cclV24WD.s page 27 + + + 1355 .L50: + 1356 .loc 1 144 57 discriminator 2 + 1357 00e6 0022 movs r2, #0 + 1358 .L51: + 1359 .loc 1 144 70 is_stmt 1 discriminator 4 + 1360 00e8 7B68 ldr r3, [r7, #4] + 1361 00ea 03F02003 and r3, r3, #32 + 1362 .loc 1 144 57 discriminator 4 + 1363 00ee 002B cmp r3, #0 + 1364 00f0 04D0 beq .L52 + 1365 .loc 1 144 57 is_stmt 0 discriminator 5 + 1366 00f2 97F90330 ldrsb r3, [r7, #3] + 1367 00f6 1B01 lsls r3, r3, #4 + 1368 00f8 5BB2 sxtb r3, r3 + 1369 00fa 00E0 b .L53 + 1370 .L52: + 1371 .loc 1 144 57 discriminator 6 + 1372 00fc 0023 movs r3, #0 + 1373 .L53: + 1374 .loc 1 144 57 discriminator 8 + 1375 00fe 1343 orrs r3, r3, r2 + 1376 0100 5BB2 sxtb r3, r3 + 1377 0102 DBB2 uxtb r3, r3 + 1378 .loc 1 144 15 is_stmt 1 discriminator 8 + 1379 0104 BB73 strb r3, [r7, #14] + 145:Core/Src/ADBMS_Abstraction.c **** buffer_a[3] = ((channels & (1 << 6)) ? dutyCycle : 0) | ((channels & (1 << 7)) ? (dutyCycle << 4) + 1380 .loc 1 145 28 + 1381 0106 7B68 ldr r3, [r7, #4] + 1382 0108 03F04003 and r3, r3, #64 + 1383 .loc 1 145 57 + 1384 010c 002B cmp r3, #0 + 1385 010e 02D0 beq .L54 + 1386 .loc 1 145 57 is_stmt 0 discriminator 1 + 1387 0110 97F90320 ldrsb r2, [r7, #3] + 1388 0114 00E0 b .L55 + 1389 .L54: + 1390 .loc 1 145 57 discriminator 2 + 1391 0116 0022 movs r2, #0 + 1392 .L55: + 1393 .loc 1 145 70 is_stmt 1 discriminator 4 + 1394 0118 7B68 ldr r3, [r7, #4] + 1395 011a 03F08003 and r3, r3, #128 + 1396 .loc 1 145 57 discriminator 4 + 1397 011e 002B cmp r3, #0 + 1398 0120 04D0 beq .L56 + 1399 .loc 1 145 57 is_stmt 0 discriminator 5 + 1400 0122 97F90330 ldrsb r3, [r7, #3] + 1401 0126 1B01 lsls r3, r3, #4 + 1402 0128 5BB2 sxtb r3, r3 + 1403 012a 00E0 b .L57 + 1404 .L56: + 1405 .loc 1 145 57 discriminator 6 + 1406 012c 0023 movs r3, #0 + 1407 .L57: + 1408 .loc 1 145 57 discriminator 8 + 1409 012e 1343 orrs r3, r3, r2 + 1410 0130 5BB2 sxtb r3, r3 + ARM GAS /tmp/cclV24WD.s page 28 + + + 1411 0132 DBB2 uxtb r3, r3 + 1412 .loc 1 145 15 is_stmt 1 discriminator 8 + 1413 0134 FB73 strb r3, [r7, #15] + 146:Core/Src/ADBMS_Abstraction.c **** buffer_a[4] = ((channels & (1 << 8)) ? dutyCycle : 0) | ((channels & (1 << 9)) ? (dutyCycle << 4) + 1414 .loc 1 146 28 + 1415 0136 7B68 ldr r3, [r7, #4] + 1416 0138 03F48073 and r3, r3, #256 + 1417 .loc 1 146 57 + 1418 013c 002B cmp r3, #0 + 1419 013e 02D0 beq .L58 + 1420 .loc 1 146 57 is_stmt 0 discriminator 1 + 1421 0140 97F90320 ldrsb r2, [r7, #3] + 1422 0144 00E0 b .L59 + 1423 .L58: + 1424 .loc 1 146 57 discriminator 2 + 1425 0146 0022 movs r2, #0 + 1426 .L59: + 1427 .loc 1 146 70 is_stmt 1 discriminator 4 + 1428 0148 7B68 ldr r3, [r7, #4] + 1429 014a 03F40073 and r3, r3, #512 + 1430 .loc 1 146 57 discriminator 4 + 1431 014e 002B cmp r3, #0 + 1432 0150 04D0 beq .L60 + 1433 .loc 1 146 57 is_stmt 0 discriminator 5 + 1434 0152 97F90330 ldrsb r3, [r7, #3] + 1435 0156 1B01 lsls r3, r3, #4 + 1436 0158 5BB2 sxtb r3, r3 + 1437 015a 00E0 b .L61 + 1438 .L60: + 1439 .loc 1 146 57 discriminator 6 + 1440 015c 0023 movs r3, #0 + 1441 .L61: + 1442 .loc 1 146 57 discriminator 8 + 1443 015e 1343 orrs r3, r3, r2 + 1444 0160 5BB2 sxtb r3, r3 + 1445 0162 DBB2 uxtb r3, r3 + 1446 .loc 1 146 15 is_stmt 1 discriminator 8 + 1447 0164 3B74 strb r3, [r7, #16] + 147:Core/Src/ADBMS_Abstraction.c **** buffer_a[5] = ((channels & (1 << 10)) ? dutyCycle : 0) | ((channels & (1 << 11)) ? (dutyCycle << + 1448 .loc 1 147 28 + 1449 0166 7B68 ldr r3, [r7, #4] + 1450 0168 03F48063 and r3, r3, #1024 + 1451 .loc 1 147 58 + 1452 016c 002B cmp r3, #0 + 1453 016e 02D0 beq .L62 + 1454 .loc 1 147 58 is_stmt 0 discriminator 1 + 1455 0170 97F90320 ldrsb r2, [r7, #3] + 1456 0174 00E0 b .L63 + 1457 .L62: + 1458 .loc 1 147 58 discriminator 2 + 1459 0176 0022 movs r2, #0 + 1460 .L63: + 1461 .loc 1 147 71 is_stmt 1 discriminator 4 + 1462 0178 7B68 ldr r3, [r7, #4] + 1463 017a 03F40063 and r3, r3, #2048 + 1464 .loc 1 147 58 discriminator 4 + 1465 017e 002B cmp r3, #0 + ARM GAS /tmp/cclV24WD.s page 29 + + + 1466 0180 04D0 beq .L64 + 1467 .loc 1 147 58 is_stmt 0 discriminator 5 + 1468 0182 97F90330 ldrsb r3, [r7, #3] + 1469 0186 1B01 lsls r3, r3, #4 + 1470 0188 5BB2 sxtb r3, r3 + 1471 018a 00E0 b .L65 + 1472 .L64: + 1473 .loc 1 147 58 discriminator 6 + 1474 018c 0023 movs r3, #0 + 1475 .L65: + 1476 .loc 1 147 58 discriminator 8 + 1477 018e 1343 orrs r3, r3, r2 + 1478 0190 5BB2 sxtb r3, r3 + 1479 0192 DBB2 uxtb r3, r3 + 1480 .loc 1 147 15 is_stmt 1 discriminator 8 + 1481 0194 7B74 strb r3, [r7, #17] + 148:Core/Src/ADBMS_Abstraction.c **** + 149:Core/Src/ADBMS_Abstraction.c **** buffer_b[0] = ((channels & (1 << 12)) ? dutyCycle : 0) | ((channels & (1 << 13)) ? (dutyCycle << + 1482 .loc 1 149 28 + 1483 0196 7B68 ldr r3, [r7, #4] + 1484 0198 03F48053 and r3, r3, #4096 + 1485 .loc 1 149 58 + 1486 019c 002B cmp r3, #0 + 1487 019e 02D0 beq .L66 + 1488 .loc 1 149 58 is_stmt 0 discriminator 1 + 1489 01a0 97F90320 ldrsb r2, [r7, #3] + 1490 01a4 00E0 b .L67 + 1491 .L66: + 1492 .loc 1 149 58 discriminator 2 + 1493 01a6 0022 movs r2, #0 + 1494 .L67: + 1495 .loc 1 149 71 is_stmt 1 discriminator 4 + 1496 01a8 7B68 ldr r3, [r7, #4] + 1497 01aa 03F40053 and r3, r3, #8192 + 1498 .loc 1 149 58 discriminator 4 + 1499 01ae 002B cmp r3, #0 + 1500 01b0 04D0 beq .L68 + 1501 .loc 1 149 58 is_stmt 0 discriminator 5 + 1502 01b2 97F90330 ldrsb r3, [r7, #3] + 1503 01b6 1B01 lsls r3, r3, #4 + 1504 01b8 5BB2 sxtb r3, r3 + 1505 01ba 00E0 b .L69 + 1506 .L68: + 1507 .loc 1 149 58 discriminator 6 + 1508 01bc 0023 movs r3, #0 + 1509 .L69: + 1510 .loc 1 149 58 discriminator 8 + 1511 01be 1343 orrs r3, r3, r2 + 1512 01c0 5BB2 sxtb r3, r3 + 1513 01c2 DBB2 uxtb r3, r3 + 1514 .loc 1 149 15 is_stmt 1 discriminator 8 + 1515 01c4 3B72 strb r3, [r7, #8] + 150:Core/Src/ADBMS_Abstraction.c **** buffer_b[1] = ((channels & (1 << 14)) ? dutyCycle : 0) | ((channels & (1 << 15)) ? (dutyCycle << + 1516 .loc 1 150 28 + 1517 01c6 7B68 ldr r3, [r7, #4] + 1518 01c8 03F48043 and r3, r3, #16384 + 1519 .loc 1 150 58 + ARM GAS /tmp/cclV24WD.s page 30 + + + 1520 01cc 002B cmp r3, #0 + 1521 01ce 02D0 beq .L70 + 1522 .loc 1 150 58 is_stmt 0 discriminator 1 + 1523 01d0 97F90320 ldrsb r2, [r7, #3] + 1524 01d4 00E0 b .L71 + 1525 .L70: + 1526 .loc 1 150 58 discriminator 2 + 1527 01d6 0022 movs r2, #0 + 1528 .L71: + 1529 .loc 1 150 71 is_stmt 1 discriminator 4 + 1530 01d8 7B68 ldr r3, [r7, #4] + 1531 01da 03F40043 and r3, r3, #32768 + 1532 .loc 1 150 58 discriminator 4 + 1533 01de 002B cmp r3, #0 + 1534 01e0 04D0 beq .L72 + 1535 .loc 1 150 58 is_stmt 0 discriminator 5 + 1536 01e2 97F90330 ldrsb r3, [r7, #3] + 1537 01e6 1B01 lsls r3, r3, #4 + 1538 01e8 5BB2 sxtb r3, r3 + 1539 01ea 00E0 b .L73 + 1540 .L72: + 1541 .loc 1 150 58 discriminator 6 + 1542 01ec 0023 movs r3, #0 + 1543 .L73: + 1544 .loc 1 150 58 discriminator 8 + 1545 01ee 1343 orrs r3, r3, r2 + 1546 01f0 5BB2 sxtb r3, r3 + 1547 01f2 DBB2 uxtb r3, r3 + 1548 .loc 1 150 15 is_stmt 1 discriminator 8 + 1549 01f4 7B72 strb r3, [r7, #9] + 1550 .LBB17: + 151:Core/Src/ADBMS_Abstraction.c **** + 152:Core/Src/ADBMS_Abstraction.c **** CHECK_RETURN(writeCMD(WRPWMA, buffer_a, PWM_GROUP_A_SIZE)); + 1551 .loc 1 152 3 + 1552 01f6 07F10C03 add r3, r7, #12 + 1553 01fa 0622 movs r2, #6 + 1554 01fc 1946 mov r1, r3 + 1555 01fe 2020 movs r0, #32 + 1556 0200 FFF7FEFF bl writeCMD + 1557 0204 0346 mov r3, r0 + 1558 0206 3B75 strb r3, [r7, #20] + 1559 .loc 1 152 3 is_stmt 0 discriminator 1 + 1560 0208 3B7D ldrb r3, [r7, #20] @ zero_extendqisi2 + 1561 020a 002B cmp r3, #0 + 1562 020c 01D0 beq .L74 + 1563 020e 3B7D ldrb r3, [r7, #20] @ zero_extendqisi2 + 1564 .loc 1 152 3 + 1565 0210 0EE0 b .L76 + 1566 .L74: + 1567 .LBE17: + 1568 .LBB18: + 153:Core/Src/ADBMS_Abstraction.c **** CHECK_RETURN(writeCMD(WRPWMB, buffer_b, PWM_GROUP_B_SIZE)); + 1569 .loc 1 153 3 is_stmt 1 + 1570 0212 07F10803 add r3, r7, #8 + 1571 0216 0222 movs r2, #2 + 1572 0218 1946 mov r1, r3 + 1573 021a 2120 movs r0, #33 + ARM GAS /tmp/cclV24WD.s page 31 + + + 1574 021c FFF7FEFF bl writeCMD + 1575 0220 0346 mov r3, r0 + 1576 0222 FB74 strb r3, [r7, #19] + 1577 .loc 1 153 3 is_stmt 0 discriminator 1 + 1578 0224 FB7C ldrb r3, [r7, #19] @ zero_extendqisi2 + 1579 0226 002B cmp r3, #0 + 1580 0228 01D0 beq .L75 + 1581 022a FB7C ldrb r3, [r7, #19] @ zero_extendqisi2 + 1582 .loc 1 153 3 + 1583 022c 00E0 b .L76 + 1584 .L75: + 1585 .LBE18: + 154:Core/Src/ADBMS_Abstraction.c **** + 155:Core/Src/ADBMS_Abstraction.c **** return 0; + 1586 .loc 1 155 10 is_stmt 1 + 1587 022e 0023 movs r3, #0 + 1588 .L76: + 156:Core/Src/ADBMS_Abstraction.c **** } + 1589 .loc 1 156 1 + 1590 0230 1846 mov r0, r3 + 1591 0232 1837 adds r7, r7, #24 + 1592 .cfi_def_cfa_offset 8 + 1593 0234 BD46 mov sp, r7 + 1594 .cfi_def_cfa_register 13 + 1595 @ sp needed + 1596 0236 80BD pop {r7, pc} + 1597 .cfi_endproc + 1598 .LFE136: + 1600 .section .text.amsStartBalancing,"ax",%progbits + 1601 .align 1 + 1602 .global amsStartBalancing + 1603 .syntax unified + 1604 .thumb + 1605 .thumb_func + 1607 amsStartBalancing: + 1608 .LFB137: + 157:Core/Src/ADBMS_Abstraction.c **** + 158:Core/Src/ADBMS_Abstraction.c **** uint8 amsStartBalancing(uint8 dutyCycle) { return writeCMD(UNMUTE, NULL, 0); } + 1609 .loc 1 158 42 + 1610 .cfi_startproc + 1611 @ args = 0, pretend = 0, frame = 8 + 1612 @ frame_needed = 1, uses_anonymous_args = 0 + 1613 0000 80B5 push {r7, lr} + 1614 .cfi_def_cfa_offset 8 + 1615 .cfi_offset 7, -8 + 1616 .cfi_offset 14, -4 + 1617 0002 82B0 sub sp, sp, #8 + 1618 .cfi_def_cfa_offset 16 + 1619 0004 00AF add r7, sp, #0 + 1620 .cfi_def_cfa_register 7 + 1621 0006 0346 mov r3, r0 + 1622 0008 FB71 strb r3, [r7, #7] + 1623 .loc 1 158 51 + 1624 000a 0022 movs r2, #0 + 1625 000c 0021 movs r1, #0 + 1626 000e 2920 movs r0, #41 + 1627 0010 FFF7FEFF bl writeCMD + ARM GAS /tmp/cclV24WD.s page 32 + + + 1628 0014 0346 mov r3, r0 + 1629 .loc 1 158 78 + 1630 0016 1846 mov r0, r3 + 1631 0018 0837 adds r7, r7, #8 + 1632 .cfi_def_cfa_offset 8 + 1633 001a BD46 mov sp, r7 + 1634 .cfi_def_cfa_register 13 + 1635 @ sp needed + 1636 001c 80BD pop {r7, pc} + 1637 .cfi_endproc + 1638 .LFE137: + 1640 .section .text.amsStopBalancing,"ax",%progbits + 1641 .align 1 + 1642 .global amsStopBalancing + 1643 .syntax unified + 1644 .thumb + 1645 .thumb_func + 1647 amsStopBalancing: + 1648 .LFB138: + 159:Core/Src/ADBMS_Abstraction.c **** + 160:Core/Src/ADBMS_Abstraction.c **** uint8 amsStopBalancing() { return writeCMD(MUTE, NULL, 0); } + 1649 .loc 1 160 26 + 1650 .cfi_startproc + 1651 @ args = 0, pretend = 0, frame = 0 + 1652 @ frame_needed = 1, uses_anonymous_args = 0 + 1653 0000 80B5 push {r7, lr} + 1654 .cfi_def_cfa_offset 8 + 1655 .cfi_offset 7, -8 + 1656 .cfi_offset 14, -4 + 1657 0002 00AF add r7, sp, #0 + 1658 .cfi_def_cfa_register 7 + 1659 .loc 1 160 35 + 1660 0004 0022 movs r2, #0 + 1661 0006 0021 movs r1, #0 + 1662 0008 2820 movs r0, #40 + 1663 000a FFF7FEFF bl writeCMD + 1664 000e 0346 mov r3, r0 + 1665 .loc 1 160 60 + 1666 0010 1846 mov r0, r3 + 1667 0012 80BD pop {r7, pc} + 1668 .cfi_endproc + 1669 .LFE138: + 1671 .section .text.amsSelfTest,"ax",%progbits + 1672 .align 1 + 1673 .global amsSelfTest + 1674 .syntax unified + 1675 .thumb + 1676 .thumb_func + 1678 amsSelfTest: + 1679 .LFB139: + 161:Core/Src/ADBMS_Abstraction.c **** + 162:Core/Src/ADBMS_Abstraction.c **** uint8 amsSelfTest() { return 0; } + 1680 .loc 1 162 21 + 1681 .cfi_startproc + 1682 @ args = 0, pretend = 0, frame = 0 + 1683 @ frame_needed = 1, uses_anonymous_args = 0 + 1684 @ link register save eliminated. + ARM GAS /tmp/cclV24WD.s page 33 + + + 1685 0000 80B4 push {r7} + 1686 .cfi_def_cfa_offset 4 + 1687 .cfi_offset 7, -4 + 1688 0002 00AF add r7, sp, #0 + 1689 .cfi_def_cfa_register 7 + 1690 .loc 1 162 30 + 1691 0004 0023 movs r3, #0 + 1692 .loc 1 162 33 + 1693 0006 1846 mov r0, r3 + 1694 0008 BD46 mov sp, r7 + 1695 .cfi_def_cfa_register 13 + 1696 @ sp needed + 1697 000a 5DF8047B ldr r7, [sp], #4 + 1698 .cfi_restore 7 + 1699 .cfi_def_cfa_offset 0 + 1700 000e 7047 bx lr + 1701 .cfi_endproc + 1702 .LFE139: + 1704 .section .text.amsConfigOverUnderVoltage,"ax",%progbits + 1705 .align 1 + 1706 .global amsConfigOverUnderVoltage + 1707 .syntax unified + 1708 .thumb + 1709 .thumb_func + 1711 amsConfigOverUnderVoltage: + 1712 .LFB140: + 163:Core/Src/ADBMS_Abstraction.c **** + 164:Core/Src/ADBMS_Abstraction.c **** uint8 amsConfigOverUnderVoltage(uint16 overVoltage, uint16 underVoltage) { + 1713 .loc 1 164 74 + 1714 .cfi_startproc + 1715 @ args = 0, pretend = 0, frame = 16 + 1716 @ frame_needed = 1, uses_anonymous_args = 0 + 1717 0000 80B5 push {r7, lr} + 1718 .cfi_def_cfa_offset 8 + 1719 .cfi_offset 7, -8 + 1720 .cfi_offset 14, -4 + 1721 0002 84B0 sub sp, sp, #16 + 1722 .cfi_def_cfa_offset 24 + 1723 0004 00AF add r7, sp, #0 + 1724 .cfi_def_cfa_register 7 + 1725 0006 0346 mov r3, r0 + 1726 0008 0A46 mov r2, r1 + 1727 000a FB80 strh r3, [r7, #6] @ movhi + 1728 000c 1346 mov r3, r2 @ movhi + 1729 000e BB80 strh r3, [r7, #4] @ movhi + 165:Core/Src/ADBMS_Abstraction.c **** uint8 buffer[CFG_GROUP_A_SIZE]; + 166:Core/Src/ADBMS_Abstraction.c **** + 167:Core/Src/ADBMS_Abstraction.c **** if (underVoltage & 0xF000 || overVoltage & 0xF000) { // only 12 bits allowed + 1730 .loc 1 167 20 + 1731 0010 BB88 ldrh r3, [r7, #4] + 1732 0012 03F47043 and r3, r3, #61440 + 1733 .loc 1 167 6 + 1734 0016 002B cmp r3, #0 + 1735 0018 04D1 bne .L84 + 1736 .loc 1 167 44 discriminator 1 + 1737 001a FB88 ldrh r3, [r7, #6] + 1738 001c 03F47043 and r3, r3, #61440 + ARM GAS /tmp/cclV24WD.s page 34 + + + 1739 .loc 1 167 29 discriminator 1 + 1740 0020 002B cmp r3, #0 + 1741 0022 01D0 beq .L85 + 1742 .L84: + 168:Core/Src/ADBMS_Abstraction.c **** return 1; + 1743 .loc 1 168 12 + 1744 0024 0123 movs r3, #1 + 1745 0026 3CE0 b .L88 + 1746 .L85: + 1747 .LBB19: + 169:Core/Src/ADBMS_Abstraction.c **** } + 170:Core/Src/ADBMS_Abstraction.c **** + 171:Core/Src/ADBMS_Abstraction.c **** CHECK_RETURN(readCMD(RDCFGB, buffer, CFG_GROUP_A_SIZE)); + 1748 .loc 1 171 3 + 1749 0028 07F10803 add r3, r7, #8 + 1750 002c 0622 movs r2, #6 + 1751 002e 1946 mov r1, r3 + 1752 0030 2620 movs r0, #38 + 1753 0032 FFF7FEFF bl readCMD + 1754 0036 0346 mov r3, r0 + 1755 0038 FB73 strb r3, [r7, #15] + 1756 .loc 1 171 3 is_stmt 0 discriminator 1 + 1757 003a FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 1758 003c 002B cmp r3, #0 + 1759 003e 01D0 beq .L87 + 1760 0040 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 1761 .loc 1 171 3 + 1762 0042 2EE0 b .L88 + 1763 .L87: + 1764 .LBE19: + 172:Core/Src/ADBMS_Abstraction.c **** + 173:Core/Src/ADBMS_Abstraction.c **** //UV + 174:Core/Src/ADBMS_Abstraction.c **** buffer[0] = (uint8) (underVoltage & 0xFF); + 1765 .loc 1 174 15 is_stmt 1 + 1766 0044 BB88 ldrh r3, [r7, #4] @ movhi + 1767 0046 DBB2 uxtb r3, r3 + 1768 .loc 1 174 13 + 1769 0048 3B72 strb r3, [r7, #8] + 175:Core/Src/ADBMS_Abstraction.c **** buffer[1] &= 0xF0; + 1770 .loc 1 175 9 + 1771 004a 7B7A ldrb r3, [r7, #9] @ zero_extendqisi2 + 1772 .loc 1 175 13 + 1773 004c 23F00F03 bic r3, r3, #15 + 1774 0050 DBB2 uxtb r3, r3 + 1775 0052 7B72 strb r3, [r7, #9] + 176:Core/Src/ADBMS_Abstraction.c **** buffer[1] |= (uint8) ((underVoltage >> 8) & 0x0F); + 1776 .loc 1 176 9 + 1777 0054 7B7A ldrb r3, [r7, #9] @ zero_extendqisi2 + 1778 0056 5AB2 sxtb r2, r3 + 1779 .loc 1 176 45 + 1780 0058 BB88 ldrh r3, [r7, #4] + 1781 005a 1B0A lsrs r3, r3, #8 + 1782 005c 9BB2 uxth r3, r3 + 1783 005e 5BB2 sxtb r3, r3 + 1784 .loc 1 176 16 + 1785 0060 03F00F03 and r3, r3, #15 + 1786 0064 5BB2 sxtb r3, r3 + ARM GAS /tmp/cclV24WD.s page 35 + + + 1787 .loc 1 176 13 + 1788 0066 1343 orrs r3, r3, r2 + 1789 0068 5BB2 sxtb r3, r3 + 1790 006a DBB2 uxtb r3, r3 + 1791 006c 7B72 strb r3, [r7, #9] + 177:Core/Src/ADBMS_Abstraction.c **** + 178:Core/Src/ADBMS_Abstraction.c **** //OV + 179:Core/Src/ADBMS_Abstraction.c **** buffer[1] &= 0x0F; + 1792 .loc 1 179 9 + 1793 006e 7B7A ldrb r3, [r7, #9] @ zero_extendqisi2 + 1794 .loc 1 179 13 + 1795 0070 03F00F03 and r3, r3, #15 + 1796 0074 DBB2 uxtb r3, r3 + 1797 0076 7B72 strb r3, [r7, #9] + 180:Core/Src/ADBMS_Abstraction.c **** buffer[1] |= (uint8) (overVoltage << 4); + 1798 .loc 1 180 9 + 1799 0078 7A7A ldrb r2, [r7, #9] @ zero_extendqisi2 + 1800 .loc 1 180 16 + 1801 007a FB88 ldrh r3, [r7, #6] @ movhi + 1802 007c DBB2 uxtb r3, r3 + 1803 007e 1B01 lsls r3, r3, #4 + 1804 0080 DBB2 uxtb r3, r3 + 1805 .loc 1 180 13 + 1806 0082 1343 orrs r3, r3, r2 + 1807 0084 DBB2 uxtb r3, r3 + 1808 0086 7B72 strb r3, [r7, #9] + 181:Core/Src/ADBMS_Abstraction.c **** buffer[2] = (uint8) (overVoltage >> 4); + 1809 .loc 1 181 15 + 1810 0088 FB88 ldrh r3, [r7, #6] + 1811 008a 1B09 lsrs r3, r3, #4 + 1812 008c 9BB2 uxth r3, r3 + 1813 008e DBB2 uxtb r3, r3 + 1814 .loc 1 181 13 + 1815 0090 BB72 strb r3, [r7, #10] + 182:Core/Src/ADBMS_Abstraction.c **** + 183:Core/Src/ADBMS_Abstraction.c **** return writeCMD(WRCFGB, buffer, CFG_GROUP_A_SIZE); + 1816 .loc 1 183 10 + 1817 0092 07F10803 add r3, r7, #8 + 1818 0096 0622 movs r2, #6 + 1819 0098 1946 mov r1, r3 + 1820 009a 2420 movs r0, #36 + 1821 009c FFF7FEFF bl writeCMD + 1822 00a0 0346 mov r3, r0 + 1823 .L88: + 184:Core/Src/ADBMS_Abstraction.c **** } + 1824 .loc 1 184 1 + 1825 00a2 1846 mov r0, r3 + 1826 00a4 1037 adds r7, r7, #16 + 1827 .cfi_def_cfa_offset 8 + 1828 00a6 BD46 mov sp, r7 + 1829 .cfi_def_cfa_register 13 + 1830 @ sp needed + 1831 00a8 80BD pop {r7, pc} + 1832 .cfi_endproc + 1833 .LFE140: + 1835 .section .text.amsCheckUnderOverVoltage,"ax",%progbits + 1836 .align 1 + ARM GAS /tmp/cclV24WD.s page 36 + + + 1837 .global amsCheckUnderOverVoltage + 1838 .syntax unified + 1839 .thumb + 1840 .thumb_func + 1842 amsCheckUnderOverVoltage: + 1843 .LFB141: + 185:Core/Src/ADBMS_Abstraction.c **** + 186:Core/Src/ADBMS_Abstraction.c **** uint8 amsCheckUnderOverVoltage(Cell_Module* module) { + 1844 .loc 1 186 53 + 1845 .cfi_startproc + 1846 @ args = 0, pretend = 0, frame = 24 + 1847 @ frame_needed = 1, uses_anonymous_args = 0 + 1848 0000 80B5 push {r7, lr} + 1849 .cfi_def_cfa_offset 8 + 1850 .cfi_offset 7, -8 + 1851 .cfi_offset 14, -4 + 1852 0002 86B0 sub sp, sp, #24 + 1853 .cfi_def_cfa_offset 32 + 1854 0004 00AF add r7, sp, #0 + 1855 .cfi_def_cfa_register 7 + 1856 0006 7860 str r0, [r7, #4] + 187:Core/Src/ADBMS_Abstraction.c **** uint8 regbuffer[STATUS_GROUP_D_SIZE]; + 188:Core/Src/ADBMS_Abstraction.c **** uint32 ov_uv_data = 0; + 1857 .loc 1 188 10 + 1858 0008 0023 movs r3, #0 + 1859 000a 3B61 str r3, [r7, #16] + 1860 .LBB20: + 189:Core/Src/ADBMS_Abstraction.c **** CHECK_RETURN(readCMD(RDSTATD, regbuffer, STATUS_GROUP_D_SIZE)); + 1861 .loc 1 189 3 + 1862 000c 07F10803 add r3, r7, #8 + 1863 0010 0622 movs r2, #6 + 1864 0012 1946 mov r1, r3 + 1865 0014 3320 movs r0, #51 + 1866 0016 FFF7FEFF bl readCMD + 1867 001a 0346 mov r3, r0 + 1868 001c FB73 strb r3, [r7, #15] + 1869 .loc 1 189 3 is_stmt 0 discriminator 1 + 1870 001e FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 1871 0020 002B cmp r3, #0 + 1872 0022 01D0 beq .L90 + 1873 0024 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 1874 .loc 1 189 3 + 1875 0026 37E0 b .L94 + 1876 .L90: + 1877 .LBE20: + 190:Core/Src/ADBMS_Abstraction.c **** ov_uv_data = (regbuffer[0] << 0) | (regbuffer[1] << 8) | + 1878 .loc 1 190 26 is_stmt 1 + 1879 0028 3B7A ldrb r3, [r7, #8] @ zero_extendqisi2 + 1880 .loc 1 190 30 + 1881 002a 1A46 mov r2, r3 + 1882 .loc 1 190 49 + 1883 002c 7B7A ldrb r3, [r7, #9] @ zero_extendqisi2 + 1884 .loc 1 190 53 + 1885 002e 1B02 lsls r3, r3, #8 + 1886 .loc 1 190 37 + 1887 0030 1A43 orrs r2, r2, r3 + 191:Core/Src/ADBMS_Abstraction.c **** (regbuffer[2] << 16) | (regbuffer[3] << 24); + ARM GAS /tmp/cclV24WD.s page 37 + + + 1888 .loc 1 191 26 + 1889 0032 BB7A ldrb r3, [r7, #10] @ zero_extendqisi2 + 1890 .loc 1 191 30 + 1891 0034 1B04 lsls r3, r3, #16 + 190:Core/Src/ADBMS_Abstraction.c **** ov_uv_data = (regbuffer[0] << 0) | (regbuffer[1] << 8) | + 1892 .loc 1 190 60 + 1893 0036 1A43 orrs r2, r2, r3 + 1894 .loc 1 191 49 + 1895 0038 FB7A ldrb r3, [r7, #11] @ zero_extendqisi2 + 1896 .loc 1 191 53 + 1897 003a 1B06 lsls r3, r3, #24 + 1898 .loc 1 191 37 + 1899 003c 1343 orrs r3, r3, r2 + 190:Core/Src/ADBMS_Abstraction.c **** ov_uv_data = (regbuffer[0] << 0) | (regbuffer[1] << 8) | + 1900 .loc 1 190 14 + 1901 003e 3B61 str r3, [r7, #16] + 192:Core/Src/ADBMS_Abstraction.c **** + 193:Core/Src/ADBMS_Abstraction.c **** module->overVoltage = 0; + 1902 .loc 1 193 23 + 1903 0040 7B68 ldr r3, [r7, #4] + 1904 0042 0022 movs r2, #0 + 1905 0044 DA66 str r2, [r3, #108] + 194:Core/Src/ADBMS_Abstraction.c **** module->underVoltage = 0; + 1906 .loc 1 194 24 + 1907 0046 7B68 ldr r3, [r7, #4] + 1908 0048 0022 movs r2, #0 + 1909 004a 1A67 str r2, [r3, #112] + 1910 .LBB21: + 195:Core/Src/ADBMS_Abstraction.c **** + 196:Core/Src/ADBMS_Abstraction.c **** for (size_t i = 0; i < numberofcells; i++) { // ov/uv flags are 1-bit flags for each cell C0UV, C + 1911 .loc 1 196 15 + 1912 004c 0023 movs r3, #0 + 1913 004e 7B61 str r3, [r7, #20] + 1914 .loc 1 196 3 + 1915 0050 1BE0 b .L92 + 1916 .L93: + 197:Core/Src/ADBMS_Abstraction.c **** module->underVoltage |= (ov_uv_data >> (i * 2)) & 0x01; + 1917 .loc 1 197 11 + 1918 0052 7B68 ldr r3, [r7, #4] + 1919 0054 1A6F ldr r2, [r3, #112] + 1920 .loc 1 197 47 + 1921 0056 7B69 ldr r3, [r7, #20] + 1922 0058 5B00 lsls r3, r3, #1 + 1923 .loc 1 197 41 + 1924 005a 3969 ldr r1, [r7, #16] + 1925 005c 21FA03F3 lsr r3, r1, r3 + 1926 .loc 1 197 53 + 1927 0060 03F00103 and r3, r3, #1 + 1928 .loc 1 197 26 + 1929 0064 1A43 orrs r2, r2, r3 + 1930 0066 7B68 ldr r3, [r7, #4] + 1931 0068 1A67 str r2, [r3, #112] + 198:Core/Src/ADBMS_Abstraction.c **** module->overVoltage |= (ov_uv_data >> (i * 2 + 1)) & 0x01; + 1932 .loc 1 198 11 + 1933 006a 7B68 ldr r3, [r7, #4] + 1934 006c DA6E ldr r2, [r3, #108] + 1935 .loc 1 198 47 + ARM GAS /tmp/cclV24WD.s page 38 + + + 1936 006e 7B69 ldr r3, [r7, #20] + 1937 0070 5B00 lsls r3, r3, #1 + 1938 .loc 1 198 51 + 1939 0072 0133 adds r3, r3, #1 + 1940 .loc 1 198 41 + 1941 0074 3969 ldr r1, [r7, #16] + 1942 0076 21FA03F3 lsr r3, r1, r3 + 1943 .loc 1 198 57 + 1944 007a 03F00103 and r3, r3, #1 + 1945 .loc 1 198 26 + 1946 007e 1A43 orrs r2, r2, r3 + 1947 0080 7B68 ldr r3, [r7, #4] + 1948 0082 DA66 str r2, [r3, #108] + 196:Core/Src/ADBMS_Abstraction.c **** module->underVoltage |= (ov_uv_data >> (i * 2)) & 0x01; + 1949 .loc 1 196 42 discriminator 3 + 1950 0084 7B69 ldr r3, [r7, #20] + 1951 0086 0133 adds r3, r3, #1 + 1952 0088 7B61 str r3, [r7, #20] + 1953 .L92: + 196:Core/Src/ADBMS_Abstraction.c **** module->underVoltage |= (ov_uv_data >> (i * 2)) & 0x01; + 1954 .loc 1 196 24 discriminator 1 + 1955 008a 054B ldr r3, .L95 + 1956 008c 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 1957 008e 1A46 mov r2, r3 + 1958 0090 7B69 ldr r3, [r7, #20] + 1959 0092 9342 cmp r3, r2 + 1960 0094 DDD3 bcc .L93 + 1961 .LBE21: + 199:Core/Src/ADBMS_Abstraction.c **** } + 200:Core/Src/ADBMS_Abstraction.c **** + 201:Core/Src/ADBMS_Abstraction.c **** return 0; + 1962 .loc 1 201 10 + 1963 0096 0023 movs r3, #0 + 1964 .L94: + 202:Core/Src/ADBMS_Abstraction.c **** } + 1965 .loc 1 202 1 + 1966 0098 1846 mov r0, r3 + 1967 009a 1837 adds r7, r7, #24 + 1968 .cfi_def_cfa_offset 8 + 1969 009c BD46 mov sp, r7 + 1970 .cfi_def_cfa_register 13 + 1971 @ sp needed + 1972 009e 80BD pop {r7, pc} + 1973 .L96: + 1974 .align 2 + 1975 .L95: + 1976 00a0 00000000 .word numberofcells + 1977 .cfi_endproc + 1978 .LFE141: + 1980 .section .text.amsClearAux,"ax",%progbits + 1981 .align 1 + 1982 .global amsClearAux + 1983 .syntax unified + 1984 .thumb + 1985 .thumb_func + 1987 amsClearAux: + 1988 .LFB142: + ARM GAS /tmp/cclV24WD.s page 39 + + + 203:Core/Src/ADBMS_Abstraction.c **** + 204:Core/Src/ADBMS_Abstraction.c **** uint8 amsClearAux() { + 1989 .loc 1 204 21 + 1990 .cfi_startproc + 1991 @ args = 0, pretend = 0, frame = 0 + 1992 @ frame_needed = 1, uses_anonymous_args = 0 + 1993 0000 80B5 push {r7, lr} + 1994 .cfi_def_cfa_offset 8 + 1995 .cfi_offset 7, -8 + 1996 .cfi_offset 14, -4 + 1997 0002 00AF add r7, sp, #0 + 1998 .cfi_def_cfa_register 7 + 205:Core/Src/ADBMS_Abstraction.c **** return writeCMD(CLRAUX, NULL, 0); + 1999 .loc 1 205 10 + 2000 0004 0022 movs r2, #0 + 2001 0006 0021 movs r1, #0 + 2002 0008 40F21270 movw r0, #1810 + 2003 000c FFF7FEFF bl writeCMD + 2004 0010 0346 mov r3, r0 + 206:Core/Src/ADBMS_Abstraction.c **** } + 2005 .loc 1 206 1 + 2006 0012 1846 mov r0, r3 + 2007 0014 80BD pop {r7, pc} + 2008 .cfi_endproc + 2009 .LFE142: + 2011 .section .text.amsClearCells,"ax",%progbits + 2012 .align 1 + 2013 .global amsClearCells + 2014 .syntax unified + 2015 .thumb + 2016 .thumb_func + 2018 amsClearCells: + 2019 .LFB143: + 207:Core/Src/ADBMS_Abstraction.c **** + 208:Core/Src/ADBMS_Abstraction.c **** uint8 amsClearCells() { + 2020 .loc 1 208 23 + 2021 .cfi_startproc + 2022 @ args = 0, pretend = 0, frame = 0 + 2023 @ frame_needed = 1, uses_anonymous_args = 0 + 2024 0000 80B5 push {r7, lr} + 2025 .cfi_def_cfa_offset 8 + 2026 .cfi_offset 7, -8 + 2027 .cfi_offset 14, -4 + 2028 0002 00AF add r7, sp, #0 + 2029 .cfi_def_cfa_register 7 + 209:Core/Src/ADBMS_Abstraction.c **** return writeCMD(CLRCELL, NULL, 0); + 2030 .loc 1 209 10 + 2031 0004 0022 movs r2, #0 + 2032 0006 0021 movs r1, #0 + 2033 0008 40F21170 movw r0, #1809 + 2034 000c FFF7FEFF bl writeCMD + 2035 0010 0346 mov r3, r0 + 210:Core/Src/ADBMS_Abstraction.c **** } + 2036 .loc 1 210 1 + 2037 0012 1846 mov r0, r3 + 2038 0014 80BD pop {r7, pc} + 2039 .cfi_endproc + ARM GAS /tmp/cclV24WD.s page 40 + + + 2040 .LFE143: + 2042 .global __aeabi_d2iz + 2043 .section .text.amsReadCellVoltages,"ax",%progbits + 2044 .align 1 + 2045 .global amsReadCellVoltages + 2046 .syntax unified + 2047 .thumb + 2048 .thumb_func + 2050 amsReadCellVoltages: + 2051 .LFB144: + 211:Core/Src/ADBMS_Abstraction.c **** + 212:Core/Src/ADBMS_Abstraction.c **** uint8 amsReadCellVoltages(Cell_Module* module) { + 2052 .loc 1 212 48 + 2053 .cfi_startproc + 2054 @ args = 0, pretend = 0, frame = 24 + 2055 @ frame_needed = 1, uses_anonymous_args = 0 + 2056 0000 80B5 push {r7, lr} + 2057 .cfi_def_cfa_offset 8 + 2058 .cfi_offset 7, -8 + 2059 .cfi_offset 14, -4 + 2060 0002 86B0 sub sp, sp, #24 + 2061 .cfi_def_cfa_offset 32 + 2062 0004 00AF add r7, sp, #0 + 2063 .cfi_def_cfa_register 7 + 2064 0006 7860 str r0, [r7, #4] + 2065 .LBB22: + 213:Core/Src/ADBMS_Abstraction.c **** uint8 rxbuffer[CV_GROUP_A_SIZE]; + 214:Core/Src/ADBMS_Abstraction.c **** CHECK_RETURN(readCMD(RDCVA, rxbuffer, CV_GROUP_A_SIZE)); + 2066 .loc 1 214 3 + 2067 0008 07F10C03 add r3, r7, #12 + 2068 000c 0622 movs r2, #6 + 2069 000e 1946 mov r1, r3 + 2070 0010 0420 movs r0, #4 + 2071 0012 FFF7FEFF bl readCMD + 2072 0016 0346 mov r3, r0 + 2073 0018 FB75 strb r3, [r7, #23] + 2074 .loc 1 214 3 is_stmt 0 discriminator 1 + 2075 001a FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 2076 001c 002B cmp r3, #0 + 2077 001e 01D0 beq .L102 + 2078 0020 FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 2079 .loc 1 214 3 + 2080 0022 7CE2 b .L109 + 2081 .L102: + 2082 .LBE22: + 215:Core/Src/ADBMS_Abstraction.c **** module->cellVoltages[0] = mV_from_ADBMS6830(rxbuffer[0] | (rxbuffer[1] << 8)); + 2083 .loc 1 215 29 is_stmt 1 + 2084 0024 3B7B ldrb r3, [r7, #12] @ zero_extendqisi2 + 2085 0026 1AB2 sxth r2, r3 + 2086 0028 7B7B ldrb r3, [r7, #13] @ zero_extendqisi2 + 2087 002a 1BB2 sxth r3, r3 + 2088 002c 1B02 lsls r3, r3, #8 + 2089 002e 1BB2 sxth r3, r3 + 2090 0030 1343 orrs r3, r3, r2 + 2091 0032 1BB2 sxth r3, r3 + 2092 0034 1846 mov r0, r3 + 2093 0036 FFF7FEFF bl __aeabi_i2d + ARM GAS /tmp/cclV24WD.s page 41 + + + 2094 003a 0FF2EC43 adr r3, .L110 + 2095 003e D3E90023 ldrd r2, [r3] + 2096 0042 FFF7FEFF bl __aeabi_dmul + 2097 0046 0246 mov r2, r0 + 2098 0048 0B46 mov r3, r1 + 2099 004a 1046 mov r0, r2 + 2100 004c 1946 mov r1, r3 + 2101 004e 0FF2E043 adr r3, .L110+8 + 2102 0052 D3E90023 ldrd r2, [r3] + 2103 0056 FFF7FEFF bl __aeabi_dadd + 2104 005a 0246 mov r2, r0 + 2105 005c 0B46 mov r3, r1 + 2106 .loc 1 215 27 + 2107 005e 1046 mov r0, r2 + 2108 0060 1946 mov r1, r3 + 2109 0062 FFF7FEFF bl __aeabi_d2iz + 2110 0066 0346 mov r3, r0 + 2111 0068 1AB2 sxth r2, r3 + 2112 006a 7B68 ldr r3, [r7, #4] + 2113 006c 1A80 strh r2, [r3] @ movhi + 216:Core/Src/ADBMS_Abstraction.c **** module->cellVoltages[1] = mV_from_ADBMS6830(rxbuffer[2] | (rxbuffer[3] << 8)); + 2114 .loc 1 216 29 + 2115 006e BB7B ldrb r3, [r7, #14] @ zero_extendqisi2 + 2116 0070 1AB2 sxth r2, r3 + 2117 0072 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 2118 0074 1BB2 sxth r3, r3 + 2119 0076 1B02 lsls r3, r3, #8 + 2120 0078 1BB2 sxth r3, r3 + 2121 007a 1343 orrs r3, r3, r2 + 2122 007c 1BB2 sxth r3, r3 + 2123 007e 1846 mov r0, r3 + 2124 0080 FFF7FEFF bl __aeabi_i2d + 2125 0084 0FF2A043 adr r3, .L110 + 2126 0088 D3E90023 ldrd r2, [r3] + 2127 008c FFF7FEFF bl __aeabi_dmul + 2128 0090 0246 mov r2, r0 + 2129 0092 0B46 mov r3, r1 + 2130 0094 1046 mov r0, r2 + 2131 0096 1946 mov r1, r3 + 2132 0098 0FF29443 adr r3, .L110+8 + 2133 009c D3E90023 ldrd r2, [r3] + 2134 00a0 FFF7FEFF bl __aeabi_dadd + 2135 00a4 0246 mov r2, r0 + 2136 00a6 0B46 mov r3, r1 + 2137 .loc 1 216 27 + 2138 00a8 1046 mov r0, r2 + 2139 00aa 1946 mov r1, r3 + 2140 00ac FFF7FEFF bl __aeabi_d2iz + 2141 00b0 0346 mov r3, r0 + 2142 00b2 1AB2 sxth r2, r3 + 2143 00b4 7B68 ldr r3, [r7, #4] + 2144 00b6 5A80 strh r2, [r3, #2] @ movhi + 217:Core/Src/ADBMS_Abstraction.c **** module->cellVoltages[2] = mV_from_ADBMS6830(rxbuffer[4] | (rxbuffer[5] << 8)); + 2145 .loc 1 217 29 + 2146 00b8 3B7C ldrb r3, [r7, #16] @ zero_extendqisi2 + 2147 00ba 1AB2 sxth r2, r3 + 2148 00bc 7B7C ldrb r3, [r7, #17] @ zero_extendqisi2 + ARM GAS /tmp/cclV24WD.s page 42 + + + 2149 00be 1BB2 sxth r3, r3 + 2150 00c0 1B02 lsls r3, r3, #8 + 2151 00c2 1BB2 sxth r3, r3 + 2152 00c4 1343 orrs r3, r3, r2 + 2153 00c6 1BB2 sxth r3, r3 + 2154 00c8 1846 mov r0, r3 + 2155 00ca FFF7FEFF bl __aeabi_i2d + 2156 00ce 0FF25843 adr r3, .L110 + 2157 00d2 D3E90023 ldrd r2, [r3] + 2158 00d6 FFF7FEFF bl __aeabi_dmul + 2159 00da 0246 mov r2, r0 + 2160 00dc 0B46 mov r3, r1 + 2161 00de 1046 mov r0, r2 + 2162 00e0 1946 mov r1, r3 + 2163 00e2 0FF24C43 adr r3, .L110+8 + 2164 00e6 D3E90023 ldrd r2, [r3] + 2165 00ea FFF7FEFF bl __aeabi_dadd + 2166 00ee 0246 mov r2, r0 + 2167 00f0 0B46 mov r3, r1 + 2168 .loc 1 217 27 + 2169 00f2 1046 mov r0, r2 + 2170 00f4 1946 mov r1, r3 + 2171 00f6 FFF7FEFF bl __aeabi_d2iz + 2172 00fa 0346 mov r3, r0 + 2173 00fc 1AB2 sxth r2, r3 + 2174 00fe 7B68 ldr r3, [r7, #4] + 2175 0100 9A80 strh r2, [r3, #4] @ movhi + 2176 .LBB23: + 218:Core/Src/ADBMS_Abstraction.c **** + 219:Core/Src/ADBMS_Abstraction.c **** CHECK_RETURN(readCMD(RDCVB, rxbuffer, CV_GROUP_A_SIZE)); + 2177 .loc 1 219 3 + 2178 0102 07F10C03 add r3, r7, #12 + 2179 0106 0622 movs r2, #6 + 2180 0108 1946 mov r1, r3 + 2181 010a 0620 movs r0, #6 + 2182 010c FFF7FEFF bl readCMD + 2183 0110 0346 mov r3, r0 + 2184 0112 BB75 strb r3, [r7, #22] + 2185 .loc 1 219 3 is_stmt 0 discriminator 1 + 2186 0114 BB7D ldrb r3, [r7, #22] @ zero_extendqisi2 + 2187 0116 002B cmp r3, #0 + 2188 0118 01D0 beq .L104 + 2189 011a BB7D ldrb r3, [r7, #22] @ zero_extendqisi2 + 2190 .loc 1 219 3 + 2191 011c FFE1 b .L109 + 2192 .L104: + 2193 .LBE23: + 220:Core/Src/ADBMS_Abstraction.c **** module->cellVoltages[3] = mV_from_ADBMS6830(rxbuffer[0] | (rxbuffer[1] << 8)); + 2194 .loc 1 220 29 is_stmt 1 + 2195 011e 3B7B ldrb r3, [r7, #12] @ zero_extendqisi2 + 2196 0120 1AB2 sxth r2, r3 + 2197 0122 7B7B ldrb r3, [r7, #13] @ zero_extendqisi2 + 2198 0124 1BB2 sxth r3, r3 + 2199 0126 1B02 lsls r3, r3, #8 + 2200 0128 1BB2 sxth r3, r3 + 2201 012a 1343 orrs r3, r3, r2 + 2202 012c 1BB2 sxth r3, r3 + ARM GAS /tmp/cclV24WD.s page 43 + + + 2203 012e 1846 mov r0, r3 + 2204 0130 FFF7FEFF bl __aeabi_i2d + 2205 0134 FCA3 adr r3, .L110 + 2206 0136 D3E90023 ldrd r2, [r3] + 2207 013a FFF7FEFF bl __aeabi_dmul + 2208 013e 0246 mov r2, r0 + 2209 0140 0B46 mov r3, r1 + 2210 0142 1046 mov r0, r2 + 2211 0144 1946 mov r1, r3 + 2212 0146 FAA3 adr r3, .L110+8 + 2213 0148 D3E90023 ldrd r2, [r3] + 2214 014c FFF7FEFF bl __aeabi_dadd + 2215 0150 0246 mov r2, r0 + 2216 0152 0B46 mov r3, r1 + 2217 .loc 1 220 27 + 2218 0154 1046 mov r0, r2 + 2219 0156 1946 mov r1, r3 + 2220 0158 FFF7FEFF bl __aeabi_d2iz + 2221 015c 0346 mov r3, r0 + 2222 015e 1AB2 sxth r2, r3 + 2223 0160 7B68 ldr r3, [r7, #4] + 2224 0162 DA80 strh r2, [r3, #6] @ movhi + 221:Core/Src/ADBMS_Abstraction.c **** module->cellVoltages[4] = mV_from_ADBMS6830(rxbuffer[2] | (rxbuffer[3] << 8)); + 2225 .loc 1 221 29 + 2226 0164 BB7B ldrb r3, [r7, #14] @ zero_extendqisi2 + 2227 0166 1AB2 sxth r2, r3 + 2228 0168 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 2229 016a 1BB2 sxth r3, r3 + 2230 016c 1B02 lsls r3, r3, #8 + 2231 016e 1BB2 sxth r3, r3 + 2232 0170 1343 orrs r3, r3, r2 + 2233 0172 1BB2 sxth r3, r3 + 2234 0174 1846 mov r0, r3 + 2235 0176 FFF7FEFF bl __aeabi_i2d + 2236 017a EBA3 adr r3, .L110 + 2237 017c D3E90023 ldrd r2, [r3] + 2238 0180 FFF7FEFF bl __aeabi_dmul + 2239 0184 0246 mov r2, r0 + 2240 0186 0B46 mov r3, r1 + 2241 0188 1046 mov r0, r2 + 2242 018a 1946 mov r1, r3 + 2243 018c E8A3 adr r3, .L110+8 + 2244 018e D3E90023 ldrd r2, [r3] + 2245 0192 FFF7FEFF bl __aeabi_dadd + 2246 0196 0246 mov r2, r0 + 2247 0198 0B46 mov r3, r1 + 2248 .loc 1 221 27 + 2249 019a 1046 mov r0, r2 + 2250 019c 1946 mov r1, r3 + 2251 019e FFF7FEFF bl __aeabi_d2iz + 2252 01a2 0346 mov r3, r0 + 2253 01a4 1AB2 sxth r2, r3 + 2254 01a6 7B68 ldr r3, [r7, #4] + 2255 01a8 1A81 strh r2, [r3, #8] @ movhi + 222:Core/Src/ADBMS_Abstraction.c **** module->cellVoltages[5] = mV_from_ADBMS6830(rxbuffer[4] | (rxbuffer[5] << 8)); + 2256 .loc 1 222 29 + 2257 01aa 3B7C ldrb r3, [r7, #16] @ zero_extendqisi2 + ARM GAS /tmp/cclV24WD.s page 44 + + + 2258 01ac 1AB2 sxth r2, r3 + 2259 01ae 7B7C ldrb r3, [r7, #17] @ zero_extendqisi2 + 2260 01b0 1BB2 sxth r3, r3 + 2261 01b2 1B02 lsls r3, r3, #8 + 2262 01b4 1BB2 sxth r3, r3 + 2263 01b6 1343 orrs r3, r3, r2 + 2264 01b8 1BB2 sxth r3, r3 + 2265 01ba 1846 mov r0, r3 + 2266 01bc FFF7FEFF bl __aeabi_i2d + 2267 01c0 D9A3 adr r3, .L110 + 2268 01c2 D3E90023 ldrd r2, [r3] + 2269 01c6 FFF7FEFF bl __aeabi_dmul + 2270 01ca 0246 mov r2, r0 + 2271 01cc 0B46 mov r3, r1 + 2272 01ce 1046 mov r0, r2 + 2273 01d0 1946 mov r1, r3 + 2274 01d2 D7A3 adr r3, .L110+8 + 2275 01d4 D3E90023 ldrd r2, [r3] + 2276 01d8 FFF7FEFF bl __aeabi_dadd + 2277 01dc 0246 mov r2, r0 + 2278 01de 0B46 mov r3, r1 + 2279 .loc 1 222 27 + 2280 01e0 1046 mov r0, r2 + 2281 01e2 1946 mov r1, r3 + 2282 01e4 FFF7FEFF bl __aeabi_d2iz + 2283 01e8 0346 mov r3, r0 + 2284 01ea 1AB2 sxth r2, r3 + 2285 01ec 7B68 ldr r3, [r7, #4] + 2286 01ee 5A81 strh r2, [r3, #10] @ movhi + 2287 .LBB24: + 223:Core/Src/ADBMS_Abstraction.c **** + 224:Core/Src/ADBMS_Abstraction.c **** CHECK_RETURN(readCMD(RDCVC, rxbuffer, CV_GROUP_A_SIZE)); + 2288 .loc 1 224 3 + 2289 01f0 07F10C03 add r3, r7, #12 + 2290 01f4 0622 movs r2, #6 + 2291 01f6 1946 mov r1, r3 + 2292 01f8 0820 movs r0, #8 + 2293 01fa FFF7FEFF bl readCMD + 2294 01fe 0346 mov r3, r0 + 2295 0200 7B75 strb r3, [r7, #21] + 2296 .loc 1 224 3 is_stmt 0 discriminator 1 + 2297 0202 7B7D ldrb r3, [r7, #21] @ zero_extendqisi2 + 2298 0204 002B cmp r3, #0 + 2299 0206 01D0 beq .L105 + 2300 0208 7B7D ldrb r3, [r7, #21] @ zero_extendqisi2 + 2301 .loc 1 224 3 + 2302 020a 88E1 b .L109 + 2303 .L105: + 2304 .LBE24: + 225:Core/Src/ADBMS_Abstraction.c **** module->cellVoltages[6] = mV_from_ADBMS6830(rxbuffer[0] | (rxbuffer[1] << 8)); + 2305 .loc 1 225 29 is_stmt 1 + 2306 020c 3B7B ldrb r3, [r7, #12] @ zero_extendqisi2 + 2307 020e 1AB2 sxth r2, r3 + 2308 0210 7B7B ldrb r3, [r7, #13] @ zero_extendqisi2 + 2309 0212 1BB2 sxth r3, r3 + 2310 0214 1B02 lsls r3, r3, #8 + 2311 0216 1BB2 sxth r3, r3 + ARM GAS /tmp/cclV24WD.s page 45 + + + 2312 0218 1343 orrs r3, r3, r2 + 2313 021a 1BB2 sxth r3, r3 + 2314 021c 1846 mov r0, r3 + 2315 021e FFF7FEFF bl __aeabi_i2d + 2316 0222 C1A3 adr r3, .L110 + 2317 0224 D3E90023 ldrd r2, [r3] + 2318 0228 FFF7FEFF bl __aeabi_dmul + 2319 022c 0246 mov r2, r0 + 2320 022e 0B46 mov r3, r1 + 2321 0230 1046 mov r0, r2 + 2322 0232 1946 mov r1, r3 + 2323 0234 BEA3 adr r3, .L110+8 + 2324 0236 D3E90023 ldrd r2, [r3] + 2325 023a FFF7FEFF bl __aeabi_dadd + 2326 023e 0246 mov r2, r0 + 2327 0240 0B46 mov r3, r1 + 2328 .loc 1 225 27 + 2329 0242 1046 mov r0, r2 + 2330 0244 1946 mov r1, r3 + 2331 0246 FFF7FEFF bl __aeabi_d2iz + 2332 024a 0346 mov r3, r0 + 2333 024c 1AB2 sxth r2, r3 + 2334 024e 7B68 ldr r3, [r7, #4] + 2335 0250 9A81 strh r2, [r3, #12] @ movhi + 226:Core/Src/ADBMS_Abstraction.c **** module->cellVoltages[7] = mV_from_ADBMS6830(rxbuffer[2] | (rxbuffer[3] << 8)); + 2336 .loc 1 226 29 + 2337 0252 BB7B ldrb r3, [r7, #14] @ zero_extendqisi2 + 2338 0254 1AB2 sxth r2, r3 + 2339 0256 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 2340 0258 1BB2 sxth r3, r3 + 2341 025a 1B02 lsls r3, r3, #8 + 2342 025c 1BB2 sxth r3, r3 + 2343 025e 1343 orrs r3, r3, r2 + 2344 0260 1BB2 sxth r3, r3 + 2345 0262 1846 mov r0, r3 + 2346 0264 FFF7FEFF bl __aeabi_i2d + 2347 0268 AFA3 adr r3, .L110 + 2348 026a D3E90023 ldrd r2, [r3] + 2349 026e FFF7FEFF bl __aeabi_dmul + 2350 0272 0246 mov r2, r0 + 2351 0274 0B46 mov r3, r1 + 2352 0276 1046 mov r0, r2 + 2353 0278 1946 mov r1, r3 + 2354 027a ADA3 adr r3, .L110+8 + 2355 027c D3E90023 ldrd r2, [r3] + 2356 0280 FFF7FEFF bl __aeabi_dadd + 2357 0284 0246 mov r2, r0 + 2358 0286 0B46 mov r3, r1 + 2359 .loc 1 226 27 + 2360 0288 1046 mov r0, r2 + 2361 028a 1946 mov r1, r3 + 2362 028c FFF7FEFF bl __aeabi_d2iz + 2363 0290 0346 mov r3, r0 + 2364 0292 1AB2 sxth r2, r3 + 2365 0294 7B68 ldr r3, [r7, #4] + 2366 0296 DA81 strh r2, [r3, #14] @ movhi + 227:Core/Src/ADBMS_Abstraction.c **** module->cellVoltages[8] = mV_from_ADBMS6830(rxbuffer[4] | (rxbuffer[5] << 8)); + ARM GAS /tmp/cclV24WD.s page 46 + + + 2367 .loc 1 227 29 + 2368 0298 3B7C ldrb r3, [r7, #16] @ zero_extendqisi2 + 2369 029a 1AB2 sxth r2, r3 + 2370 029c 7B7C ldrb r3, [r7, #17] @ zero_extendqisi2 + 2371 029e 1BB2 sxth r3, r3 + 2372 02a0 1B02 lsls r3, r3, #8 + 2373 02a2 1BB2 sxth r3, r3 + 2374 02a4 1343 orrs r3, r3, r2 + 2375 02a6 1BB2 sxth r3, r3 + 2376 02a8 1846 mov r0, r3 + 2377 02aa FFF7FEFF bl __aeabi_i2d + 2378 02ae 9EA3 adr r3, .L110 + 2379 02b0 D3E90023 ldrd r2, [r3] + 2380 02b4 FFF7FEFF bl __aeabi_dmul + 2381 02b8 0246 mov r2, r0 + 2382 02ba 0B46 mov r3, r1 + 2383 02bc 1046 mov r0, r2 + 2384 02be 1946 mov r1, r3 + 2385 02c0 9BA3 adr r3, .L110+8 + 2386 02c2 D3E90023 ldrd r2, [r3] + 2387 02c6 FFF7FEFF bl __aeabi_dadd + 2388 02ca 0246 mov r2, r0 + 2389 02cc 0B46 mov r3, r1 + 2390 .loc 1 227 27 + 2391 02ce 1046 mov r0, r2 + 2392 02d0 1946 mov r1, r3 + 2393 02d2 FFF7FEFF bl __aeabi_d2iz + 2394 02d6 0346 mov r3, r0 + 2395 02d8 1AB2 sxth r2, r3 + 2396 02da 7B68 ldr r3, [r7, #4] + 2397 02dc 1A82 strh r2, [r3, #16] @ movhi + 2398 .LBB25: + 228:Core/Src/ADBMS_Abstraction.c **** + 229:Core/Src/ADBMS_Abstraction.c **** CHECK_RETURN(readCMD(RDCVD, rxbuffer, CV_GROUP_A_SIZE)); + 2399 .loc 1 229 3 + 2400 02de 07F10C03 add r3, r7, #12 + 2401 02e2 0622 movs r2, #6 + 2402 02e4 1946 mov r1, r3 + 2403 02e6 0A20 movs r0, #10 + 2404 02e8 FFF7FEFF bl readCMD + 2405 02ec 0346 mov r3, r0 + 2406 02ee 3B75 strb r3, [r7, #20] + 2407 .loc 1 229 3 is_stmt 0 discriminator 1 + 2408 02f0 3B7D ldrb r3, [r7, #20] @ zero_extendqisi2 + 2409 02f2 002B cmp r3, #0 + 2410 02f4 01D0 beq .L106 + 2411 02f6 3B7D ldrb r3, [r7, #20] @ zero_extendqisi2 + 2412 .loc 1 229 3 + 2413 02f8 11E1 b .L109 + 2414 .L106: + 2415 .LBE25: + 230:Core/Src/ADBMS_Abstraction.c **** module->cellVoltages[9] = mV_from_ADBMS6830(rxbuffer[0] | (rxbuffer[1] << 8)); + 2416 .loc 1 230 30 is_stmt 1 + 2417 02fa 3B7B ldrb r3, [r7, #12] @ zero_extendqisi2 + 2418 02fc 1AB2 sxth r2, r3 + 2419 02fe 7B7B ldrb r3, [r7, #13] @ zero_extendqisi2 + 2420 0300 1BB2 sxth r3, r3 + ARM GAS /tmp/cclV24WD.s page 47 + + + 2421 0302 1B02 lsls r3, r3, #8 + 2422 0304 1BB2 sxth r3, r3 + 2423 0306 1343 orrs r3, r3, r2 + 2424 0308 1BB2 sxth r3, r3 + 2425 030a 1846 mov r0, r3 + 2426 030c FFF7FEFF bl __aeabi_i2d + 2427 0310 85A3 adr r3, .L110 + 2428 0312 D3E90023 ldrd r2, [r3] + 2429 0316 FFF7FEFF bl __aeabi_dmul + 2430 031a 0246 mov r2, r0 + 2431 031c 0B46 mov r3, r1 + 2432 031e 1046 mov r0, r2 + 2433 0320 1946 mov r1, r3 + 2434 0322 83A3 adr r3, .L110+8 + 2435 0324 D3E90023 ldrd r2, [r3] + 2436 0328 FFF7FEFF bl __aeabi_dadd + 2437 032c 0246 mov r2, r0 + 2438 032e 0B46 mov r3, r1 + 2439 .loc 1 230 28 + 2440 0330 1046 mov r0, r2 + 2441 0332 1946 mov r1, r3 + 2442 0334 FFF7FEFF bl __aeabi_d2iz + 2443 0338 0346 mov r3, r0 + 2444 033a 1AB2 sxth r2, r3 + 2445 033c 7B68 ldr r3, [r7, #4] + 2446 033e 5A82 strh r2, [r3, #18] @ movhi + 231:Core/Src/ADBMS_Abstraction.c **** module->cellVoltages[10] = mV_from_ADBMS6830(rxbuffer[2] | (rxbuffer[3] << 8)); + 2447 .loc 1 231 30 + 2448 0340 BB7B ldrb r3, [r7, #14] @ zero_extendqisi2 + 2449 0342 1AB2 sxth r2, r3 + 2450 0344 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 2451 0346 1BB2 sxth r3, r3 + 2452 0348 1B02 lsls r3, r3, #8 + 2453 034a 1BB2 sxth r3, r3 + 2454 034c 1343 orrs r3, r3, r2 + 2455 034e 1BB2 sxth r3, r3 + 2456 0350 1846 mov r0, r3 + 2457 0352 FFF7FEFF bl __aeabi_i2d + 2458 0356 74A3 adr r3, .L110 + 2459 0358 D3E90023 ldrd r2, [r3] + 2460 035c FFF7FEFF bl __aeabi_dmul + 2461 0360 0246 mov r2, r0 + 2462 0362 0B46 mov r3, r1 + 2463 0364 1046 mov r0, r2 + 2464 0366 1946 mov r1, r3 + 2465 0368 71A3 adr r3, .L110+8 + 2466 036a D3E90023 ldrd r2, [r3] + 2467 036e FFF7FEFF bl __aeabi_dadd + 2468 0372 0246 mov r2, r0 + 2469 0374 0B46 mov r3, r1 + 2470 .loc 1 231 28 + 2471 0376 1046 mov r0, r2 + 2472 0378 1946 mov r1, r3 + 2473 037a FFF7FEFF bl __aeabi_d2iz + 2474 037e 0346 mov r3, r0 + 2475 0380 1AB2 sxth r2, r3 + 2476 0382 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/cclV24WD.s page 48 + + + 2477 0384 9A82 strh r2, [r3, #20] @ movhi + 232:Core/Src/ADBMS_Abstraction.c **** module->cellVoltages[11] = mV_from_ADBMS6830(rxbuffer[4] | (rxbuffer[5] << 8)); + 2478 .loc 1 232 30 + 2479 0386 3B7C ldrb r3, [r7, #16] @ zero_extendqisi2 + 2480 0388 1AB2 sxth r2, r3 + 2481 038a 7B7C ldrb r3, [r7, #17] @ zero_extendqisi2 + 2482 038c 1BB2 sxth r3, r3 + 2483 038e 1B02 lsls r3, r3, #8 + 2484 0390 1BB2 sxth r3, r3 + 2485 0392 1343 orrs r3, r3, r2 + 2486 0394 1BB2 sxth r3, r3 + 2487 0396 1846 mov r0, r3 + 2488 0398 FFF7FEFF bl __aeabi_i2d + 2489 039c 62A3 adr r3, .L110 + 2490 039e D3E90023 ldrd r2, [r3] + 2491 03a2 FFF7FEFF bl __aeabi_dmul + 2492 03a6 0246 mov r2, r0 + 2493 03a8 0B46 mov r3, r1 + 2494 03aa 1046 mov r0, r2 + 2495 03ac 1946 mov r1, r3 + 2496 03ae 60A3 adr r3, .L110+8 + 2497 03b0 D3E90023 ldrd r2, [r3] + 2498 03b4 FFF7FEFF bl __aeabi_dadd + 2499 03b8 0246 mov r2, r0 + 2500 03ba 0B46 mov r3, r1 + 2501 .loc 1 232 28 + 2502 03bc 1046 mov r0, r2 + 2503 03be 1946 mov r1, r3 + 2504 03c0 FFF7FEFF bl __aeabi_d2iz + 2505 03c4 0346 mov r3, r0 + 2506 03c6 1AB2 sxth r2, r3 + 2507 03c8 7B68 ldr r3, [r7, #4] + 2508 03ca DA82 strh r2, [r3, #22] @ movhi + 2509 .LBB26: + 233:Core/Src/ADBMS_Abstraction.c **** + 234:Core/Src/ADBMS_Abstraction.c **** CHECK_RETURN(readCMD(RDCVE, rxbuffer, CV_GROUP_A_SIZE)); + 2510 .loc 1 234 3 + 2511 03cc 07F10C03 add r3, r7, #12 + 2512 03d0 0622 movs r2, #6 + 2513 03d2 1946 mov r1, r3 + 2514 03d4 0920 movs r0, #9 + 2515 03d6 FFF7FEFF bl readCMD + 2516 03da 0346 mov r3, r0 + 2517 03dc FB74 strb r3, [r7, #19] + 2518 .loc 1 234 3 is_stmt 0 discriminator 1 + 2519 03de FB7C ldrb r3, [r7, #19] @ zero_extendqisi2 + 2520 03e0 002B cmp r3, #0 + 2521 03e2 01D0 beq .L107 + 2522 03e4 FB7C ldrb r3, [r7, #19] @ zero_extendqisi2 + 2523 .loc 1 234 3 + 2524 03e6 9AE0 b .L109 + 2525 .L107: + 2526 .LBE26: + 235:Core/Src/ADBMS_Abstraction.c **** module->cellVoltages[12] = mV_from_ADBMS6830(rxbuffer[0] | (rxbuffer[1] << 8)); + 2527 .loc 1 235 30 is_stmt 1 + 2528 03e8 3B7B ldrb r3, [r7, #12] @ zero_extendqisi2 + 2529 03ea 1AB2 sxth r2, r3 + ARM GAS /tmp/cclV24WD.s page 49 + + + 2530 03ec 7B7B ldrb r3, [r7, #13] @ zero_extendqisi2 + 2531 03ee 1BB2 sxth r3, r3 + 2532 03f0 1B02 lsls r3, r3, #8 + 2533 03f2 1BB2 sxth r3, r3 + 2534 03f4 1343 orrs r3, r3, r2 + 2535 03f6 1BB2 sxth r3, r3 + 2536 03f8 1846 mov r0, r3 + 2537 03fa FFF7FEFF bl __aeabi_i2d + 2538 03fe 4AA3 adr r3, .L110 + 2539 0400 D3E90023 ldrd r2, [r3] + 2540 0404 FFF7FEFF bl __aeabi_dmul + 2541 0408 0246 mov r2, r0 + 2542 040a 0B46 mov r3, r1 + 2543 040c 1046 mov r0, r2 + 2544 040e 1946 mov r1, r3 + 2545 0410 47A3 adr r3, .L110+8 + 2546 0412 D3E90023 ldrd r2, [r3] + 2547 0416 FFF7FEFF bl __aeabi_dadd + 2548 041a 0246 mov r2, r0 + 2549 041c 0B46 mov r3, r1 + 2550 .loc 1 235 28 + 2551 041e 1046 mov r0, r2 + 2552 0420 1946 mov r1, r3 + 2553 0422 FFF7FEFF bl __aeabi_d2iz + 2554 0426 0346 mov r3, r0 + 2555 0428 1AB2 sxth r2, r3 + 2556 042a 7B68 ldr r3, [r7, #4] + 2557 042c 1A83 strh r2, [r3, #24] @ movhi + 236:Core/Src/ADBMS_Abstraction.c **** module->cellVoltages[13] = mV_from_ADBMS6830(rxbuffer[2] | (rxbuffer[3] << 8)); + 2558 .loc 1 236 30 + 2559 042e BB7B ldrb r3, [r7, #14] @ zero_extendqisi2 + 2560 0430 1AB2 sxth r2, r3 + 2561 0432 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 2562 0434 1BB2 sxth r3, r3 + 2563 0436 1B02 lsls r3, r3, #8 + 2564 0438 1BB2 sxth r3, r3 + 2565 043a 1343 orrs r3, r3, r2 + 2566 043c 1BB2 sxth r3, r3 + 2567 043e 1846 mov r0, r3 + 2568 0440 FFF7FEFF bl __aeabi_i2d + 2569 0444 38A3 adr r3, .L110 + 2570 0446 D3E90023 ldrd r2, [r3] + 2571 044a FFF7FEFF bl __aeabi_dmul + 2572 044e 0246 mov r2, r0 + 2573 0450 0B46 mov r3, r1 + 2574 0452 1046 mov r0, r2 + 2575 0454 1946 mov r1, r3 + 2576 0456 36A3 adr r3, .L110+8 + 2577 0458 D3E90023 ldrd r2, [r3] + 2578 045c FFF7FEFF bl __aeabi_dadd + 2579 0460 0246 mov r2, r0 + 2580 0462 0B46 mov r3, r1 + 2581 .loc 1 236 28 + 2582 0464 1046 mov r0, r2 + 2583 0466 1946 mov r1, r3 + 2584 0468 FFF7FEFF bl __aeabi_d2iz + 2585 046c 0346 mov r3, r0 + ARM GAS /tmp/cclV24WD.s page 50 + + + 2586 046e 1AB2 sxth r2, r3 + 2587 0470 7B68 ldr r3, [r7, #4] + 2588 0472 5A83 strh r2, [r3, #26] @ movhi + 237:Core/Src/ADBMS_Abstraction.c **** module->cellVoltages[14] = mV_from_ADBMS6830(rxbuffer[4] | (rxbuffer[5] << 8)); + 2589 .loc 1 237 30 + 2590 0474 3B7C ldrb r3, [r7, #16] @ zero_extendqisi2 + 2591 0476 1AB2 sxth r2, r3 + 2592 0478 7B7C ldrb r3, [r7, #17] @ zero_extendqisi2 + 2593 047a 1BB2 sxth r3, r3 + 2594 047c 1B02 lsls r3, r3, #8 + 2595 047e 1BB2 sxth r3, r3 + 2596 0480 1343 orrs r3, r3, r2 + 2597 0482 1BB2 sxth r3, r3 + 2598 0484 1846 mov r0, r3 + 2599 0486 FFF7FEFF bl __aeabi_i2d + 2600 048a 27A3 adr r3, .L110 + 2601 048c D3E90023 ldrd r2, [r3] + 2602 0490 FFF7FEFF bl __aeabi_dmul + 2603 0494 0246 mov r2, r0 + 2604 0496 0B46 mov r3, r1 + 2605 0498 1046 mov r0, r2 + 2606 049a 1946 mov r1, r3 + 2607 049c 24A3 adr r3, .L110+8 + 2608 049e D3E90023 ldrd r2, [r3] + 2609 04a2 FFF7FEFF bl __aeabi_dadd + 2610 04a6 0246 mov r2, r0 + 2611 04a8 0B46 mov r3, r1 + 2612 .loc 1 237 28 + 2613 04aa 1046 mov r0, r2 + 2614 04ac 1946 mov r1, r3 + 2615 04ae FFF7FEFF bl __aeabi_d2iz + 2616 04b2 0346 mov r3, r0 + 2617 04b4 1AB2 sxth r2, r3 + 2618 04b6 7B68 ldr r3, [r7, #4] + 2619 04b8 9A83 strh r2, [r3, #28] @ movhi + 2620 .LBB27: + 238:Core/Src/ADBMS_Abstraction.c **** + 239:Core/Src/ADBMS_Abstraction.c **** CHECK_RETURN(readCMD(RDCVF, rxbuffer, CV_GROUP_A_SIZE)); + 2621 .loc 1 239 3 + 2622 04ba 07F10C03 add r3, r7, #12 + 2623 04be 0622 movs r2, #6 + 2624 04c0 1946 mov r1, r3 + 2625 04c2 0B20 movs r0, #11 + 2626 04c4 FFF7FEFF bl readCMD + 2627 04c8 0346 mov r3, r0 + 2628 04ca BB74 strb r3, [r7, #18] + 2629 .loc 1 239 3 is_stmt 0 discriminator 1 + 2630 04cc BB7C ldrb r3, [r7, #18] @ zero_extendqisi2 + 2631 04ce 002B cmp r3, #0 + 2632 04d0 01D0 beq .L108 + 2633 04d2 BB7C ldrb r3, [r7, #18] @ zero_extendqisi2 + 2634 .loc 1 239 3 + 2635 04d4 23E0 b .L109 + 2636 .L108: + 2637 .LBE27: + 240:Core/Src/ADBMS_Abstraction.c **** module->cellVoltages[15] = mV_from_ADBMS6830(rxbuffer[0] | (rxbuffer[1] << 8)); + 2638 .loc 1 240 30 is_stmt 1 + ARM GAS /tmp/cclV24WD.s page 51 + + + 2639 04d6 3B7B ldrb r3, [r7, #12] @ zero_extendqisi2 + 2640 04d8 1AB2 sxth r2, r3 + 2641 04da 7B7B ldrb r3, [r7, #13] @ zero_extendqisi2 + 2642 04dc 1BB2 sxth r3, r3 + 2643 04de 1B02 lsls r3, r3, #8 + 2644 04e0 1BB2 sxth r3, r3 + 2645 04e2 1343 orrs r3, r3, r2 + 2646 04e4 1BB2 sxth r3, r3 + 2647 04e6 1846 mov r0, r3 + 2648 04e8 FFF7FEFF bl __aeabi_i2d + 2649 04ec 0EA3 adr r3, .L110 + 2650 04ee D3E90023 ldrd r2, [r3] + 2651 04f2 FFF7FEFF bl __aeabi_dmul + 2652 04f6 0246 mov r2, r0 + 2653 04f8 0B46 mov r3, r1 + 2654 04fa 1046 mov r0, r2 + 2655 04fc 1946 mov r1, r3 + 2656 04fe 0CA3 adr r3, .L110+8 + 2657 0500 D3E90023 ldrd r2, [r3] + 2658 0504 FFF7FEFF bl __aeabi_dadd + 2659 0508 0246 mov r2, r0 + 2660 050a 0B46 mov r3, r1 + 2661 .loc 1 240 28 + 2662 050c 1046 mov r0, r2 + 2663 050e 1946 mov r1, r3 + 2664 0510 FFF7FEFF bl __aeabi_d2iz + 2665 0514 0346 mov r3, r0 + 2666 0516 1AB2 sxth r2, r3 + 2667 0518 7B68 ldr r3, [r7, #4] + 2668 051a DA83 strh r2, [r3, #30] @ movhi + 241:Core/Src/ADBMS_Abstraction.c **** + 242:Core/Src/ADBMS_Abstraction.c **** return 0; + 2669 .loc 1 242 10 + 2670 051c 0023 movs r3, #0 + 2671 .L109: + 243:Core/Src/ADBMS_Abstraction.c **** } + 2672 .loc 1 243 1 + 2673 051e 1846 mov r0, r3 + 2674 0520 1837 adds r7, r7, #24 + 2675 .cfi_def_cfa_offset 8 + 2676 0522 BD46 mov sp, r7 + 2677 .cfi_def_cfa_register 13 + 2678 @ sp needed + 2679 0524 80BD pop {r7, pc} + 2680 .L111: + 2681 0526 00BF .align 3 + 2682 .L110: + 2683 0528 33333333 .word 858993459 + 2684 052c 3333C33F .word 1069757235 + 2685 0530 00000000 .word 0 + 2686 0534 00709740 .word 1083666432 + 2687 .cfi_endproc + 2688 .LFE144: + 2690 .text + 2691 .Letext0: + 2692 .file 2 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 2693 .file 3 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + ARM GAS /tmp/cclV24WD.s page 52 + + + 2694 .file 4 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + 2695 .file 5 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/lib/gcc/arm-none-e + 2696 .file 6 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h" + 2697 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h" + 2698 .file 8 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h" + 2699 .file 9 "Core/Inc/ADBMS_LL_Driver.h" + 2700 .file 10 "Core/Inc/ADBMS_Abstraction.h" + ARM GAS /tmp/cclV24WD.s page 53 + + +DEFINED SYMBOLS + *ABS*:00000000 ADBMS_Abstraction.c + /tmp/cclV24WD.s:24 .bss.numberofcells:00000000 numberofcells + /tmp/cclV24WD.s:25 .bss.numberofcells:00000000 $d + /tmp/cclV24WD.s:30 .bss.numberofauxchannels:00000000 numberofauxchannels + /tmp/cclV24WD.s:31 .bss.numberofauxchannels:00000000 $d + /tmp/cclV24WD.s:33 .rodata:00000000 $d + /tmp/cclV24WD.s:37 .text.amsReset:00000000 $t + /tmp/cclV24WD.s:43 .text.amsReset:00000000 amsReset + /tmp/cclV24WD.s:233 .text.amsWakeUp:00000000 amsWakeUp + /tmp/cclV24WD.s:1647 .text.amsStopBalancing:00000000 amsStopBalancing + /tmp/cclV24WD.s:1711 .text.amsConfigOverUnderVoltage:00000000 amsConfigOverUnderVoltage + /tmp/cclV24WD.s:166 .text.amsReset:000000b4 $d + /tmp/cclV24WD.s:171 .text.initAMS:00000000 $t + /tmp/cclV24WD.s:177 .text.initAMS:00000000 initAMS + /tmp/cclV24WD.s:221 .text.initAMS:00000030 $d + /tmp/cclV24WD.s:227 .text.amsWakeUp:00000000 $t + /tmp/cclV24WD.s:266 .text.amsCellMeasurement:00000000 $t + /tmp/cclV24WD.s:272 .text.amsCellMeasurement:00000000 amsCellMeasurement + /tmp/cclV24WD.s:2050 .text.amsReadCellVoltages:00000000 amsReadCellVoltages + /tmp/cclV24WD.s:303 .text.amsConfigCellMeasurement:00000000 $t + /tmp/cclV24WD.s:309 .text.amsConfigCellMeasurement:00000000 amsConfigCellMeasurement + /tmp/cclV24WD.s:345 .text.amsConfigCellMeasurement:00000020 $d + /tmp/cclV24WD.s:355 .text.amsAuxAndStatusMeasurement:00000000 $t + /tmp/cclV24WD.s:361 .text.amsAuxAndStatusMeasurement:00000000 amsAuxAndStatusMeasurement + /tmp/cclV24WD.s:1178 .text.amsAuxAndStatusMeasurement:00000680 $d + /tmp/cclV24WD.s:1186 .text.amsConfigBalancing:00000000 $t + /tmp/cclV24WD.s:1192 .text.amsConfigBalancing:00000000 amsConfigBalancing + /tmp/cclV24WD.s:1601 .text.amsStartBalancing:00000000 $t + /tmp/cclV24WD.s:1607 .text.amsStartBalancing:00000000 amsStartBalancing + /tmp/cclV24WD.s:1641 .text.amsStopBalancing:00000000 $t + /tmp/cclV24WD.s:1672 .text.amsSelfTest:00000000 $t + /tmp/cclV24WD.s:1678 .text.amsSelfTest:00000000 amsSelfTest + /tmp/cclV24WD.s:1705 .text.amsConfigOverUnderVoltage:00000000 $t + /tmp/cclV24WD.s:1836 .text.amsCheckUnderOverVoltage:00000000 $t + /tmp/cclV24WD.s:1842 .text.amsCheckUnderOverVoltage:00000000 amsCheckUnderOverVoltage + /tmp/cclV24WD.s:1976 .text.amsCheckUnderOverVoltage:000000a0 $d + /tmp/cclV24WD.s:1981 .text.amsClearAux:00000000 $t + /tmp/cclV24WD.s:1987 .text.amsClearAux:00000000 amsClearAux + /tmp/cclV24WD.s:2012 .text.amsClearCells:00000000 $t + /tmp/cclV24WD.s:2018 .text.amsClearCells:00000000 amsClearCells + /tmp/cclV24WD.s:2044 .text.amsReadCellVoltages:00000000 $t + /tmp/cclV24WD.s:2683 .text.amsReadCellVoltages:00000528 $d + +UNDEFINED SYMBOLS +readCMD +mcuDelay +writeCMD +adbmsDriverInit +__aeabi_i2d +__aeabi_dmul +__aeabi_dadd +__aeabi_d2f +__aeabi_d2uiz +pollCMD +__aeabi_d2iz diff --git a/Software/build/ADBMS_Abstraction.o b/Software/build/ADBMS_Abstraction.o new file mode 100644 index 0000000..c45ea40 Binary files /dev/null and b/Software/build/ADBMS_Abstraction.o differ diff --git a/Software/build/ADBMS_LL_Driver.d b/Software/build/ADBMS_LL_Driver.d new file mode 100644 index 0000000..47aa474 --- /dev/null +++ b/Software/build/ADBMS_LL_Driver.d @@ -0,0 +1,64 @@ +build/ADBMS_LL_Driver.o: Core/Src/ADBMS_LL_Driver.c \ + Core/Inc/ADBMS_LL_Driver.h Core/Inc/main.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + Core/Inc/stm32f3xx_hal_conf.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h +Core/Inc/ADBMS_LL_Driver.h: +Core/Inc/main.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h: diff --git a/Software/build/ADBMS_LL_Driver.lst b/Software/build/ADBMS_LL_Driver.lst new file mode 100644 index 0000000..d3c381d --- /dev/null +++ b/Software/build/ADBMS_LL_Driver.lst @@ -0,0 +1,2629 @@ +ARM GAS /tmp/cczsHaNw.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 6 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "ADBMS_LL_Driver.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Core/Src/ADBMS_LL_Driver.c" + 20 .global adbmsspi + 21 .section .bss.adbmsspi,"aw",%nobits + 22 .align 2 + 25 adbmsspi: + 26 0000 00000000 .space 4 + 27 .section .text.adbmsDriverInit,"ax",%progbits + 28 .align 1 + 29 .global adbmsDriverInit + 30 .syntax unified + 31 .thumb + 32 .thumb_func + 34 adbmsDriverInit: + 35 .LFB130: + 1:Core/Src/ADBMS_LL_Driver.c **** /* + 2:Core/Src/ADBMS_LL_Driver.c **** * ADBMS_LL_Driver.c + 3:Core/Src/ADBMS_LL_Driver.c **** * + 4:Core/Src/ADBMS_LL_Driver.c **** * Created on: 05.06.2022 + 5:Core/Src/ADBMS_LL_Driver.c **** * Author: max + 6:Core/Src/ADBMS_LL_Driver.c **** */ + 7:Core/Src/ADBMS_LL_Driver.c **** + 8:Core/Src/ADBMS_LL_Driver.c **** #include "ADBMS_LL_Driver.h" + 9:Core/Src/ADBMS_LL_Driver.c **** + 10:Core/Src/ADBMS_LL_Driver.c **** #define INITIAL_COMMAND_PEC 0x0010 + 11:Core/Src/ADBMS_LL_Driver.c **** #define INITIAL_DATA_PEC 0x0010 + 12:Core/Src/ADBMS_LL_Driver.c **** #define ADBMS_SPI_TIMEOUT 100 // Timeout in ms + 13:Core/Src/ADBMS_LL_Driver.c **** #warning ask about the timeout value + 14:Core/Src/ADBMS_LL_Driver.c **** + 15:Core/Src/ADBMS_LL_Driver.c **** SPI_HandleTypeDef* adbmsspi; + 16:Core/Src/ADBMS_LL_Driver.c **** + 17:Core/Src/ADBMS_LL_Driver.c **** uint8 adbmsDriverInit(SPI_HandleTypeDef* hspi) { + 36 .loc 1 17 48 + 37 .cfi_startproc + 38 @ args = 0, pretend = 0, frame = 8 + 39 @ frame_needed = 1, uses_anonymous_args = 0 + 40 0000 80B5 push {r7, lr} + 41 .cfi_def_cfa_offset 8 + 42 .cfi_offset 7, -8 + 43 .cfi_offset 14, -4 + ARM GAS /tmp/cczsHaNw.s page 2 + + + 44 0002 82B0 sub sp, sp, #8 + 45 .cfi_def_cfa_offset 16 + 46 0004 00AF add r7, sp, #0 + 47 .cfi_def_cfa_register 7 + 48 0006 7860 str r0, [r7, #4] + 18:Core/Src/ADBMS_LL_Driver.c **** mcuAdbmsCSLow(); + 49 .loc 1 18 3 + 50 0008 FFF7FEFF bl mcuAdbmsCSLow + 19:Core/Src/ADBMS_LL_Driver.c **** HAL_Delay(1); + 51 .loc 1 19 3 + 52 000c 0120 movs r0, #1 + 53 000e FFF7FEFF bl HAL_Delay + 20:Core/Src/ADBMS_LL_Driver.c **** mcuAdbmsCSHigh(); + 54 .loc 1 20 3 + 55 0012 FFF7FEFF bl mcuAdbmsCSHigh + 21:Core/Src/ADBMS_LL_Driver.c **** adbmsspi = hspi; + 56 .loc 1 21 12 + 57 0016 044A ldr r2, .L3 + 58 0018 7B68 ldr r3, [r7, #4] + 59 001a 1360 str r3, [r2] + 22:Core/Src/ADBMS_LL_Driver.c **** return 0; + 60 .loc 1 22 10 + 61 001c 0023 movs r3, #0 + 23:Core/Src/ADBMS_LL_Driver.c **** } + 62 .loc 1 23 1 + 63 001e 1846 mov r0, r3 + 64 0020 0837 adds r7, r7, #8 + 65 .cfi_def_cfa_offset 8 + 66 0022 BD46 mov sp, r7 + 67 .cfi_def_cfa_register 13 + 68 @ sp needed + 69 0024 80BD pop {r7, pc} + 70 .L4: + 71 0026 00BF .align 2 + 72 .L3: + 73 0028 00000000 .word adbmsspi + 74 .cfi_endproc + 75 .LFE130: + 77 .section .text.calculateCommandPEC,"ax",%progbits + 78 .align 1 + 79 .global calculateCommandPEC + 80 .syntax unified + 81 .thumb + 82 .thumb_func + 84 calculateCommandPEC: + 85 .LFB131: + 24:Core/Src/ADBMS_LL_Driver.c **** + 25:Core/Src/ADBMS_LL_Driver.c **** //command PEC calculation + 26:Core/Src/ADBMS_LL_Driver.c **** //CRC-15 + 27:Core/Src/ADBMS_LL_Driver.c **** //x^15 + x^14 + x^10 + x^8 + x^7 + x^4 + x^3 + 1 + 28:Core/Src/ADBMS_LL_Driver.c **** + 29:Core/Src/ADBMS_LL_Driver.c **** uint8 calculateCommandPEC(uint8_t* data, uint8_t datalen) { + 86 .loc 1 29 59 + 87 .cfi_startproc + 88 @ args = 0, pretend = 0, frame = 24 + 89 @ frame_needed = 1, uses_anonymous_args = 0 + 90 0000 80B5 push {r7, lr} + ARM GAS /tmp/cczsHaNw.s page 3 + + + 91 .cfi_def_cfa_offset 8 + 92 .cfi_offset 7, -8 + 93 .cfi_offset 14, -4 + 94 0002 86B0 sub sp, sp, #24 + 95 .cfi_def_cfa_offset 32 + 96 0004 00AF add r7, sp, #0 + 97 .cfi_def_cfa_register 7 + 98 0006 7860 str r0, [r7, #4] + 99 0008 0B46 mov r3, r1 + 100 000a FB70 strb r3, [r7, #3] + 30:Core/Src/ADBMS_LL_Driver.c **** uint16 currentpec = INITIAL_COMMAND_PEC; + 101 .loc 1 30 10 + 102 000c 1023 movs r3, #16 + 103 000e FB82 strh r3, [r7, #22] @ movhi + 31:Core/Src/ADBMS_LL_Driver.c **** if (datalen >= 3) { + 104 .loc 1 31 6 + 105 0010 FB78 ldrb r3, [r7, #3] @ zero_extendqisi2 + 106 0012 022B cmp r3, #2 + 107 0014 38D9 bls .L6 + 108 .LBB2: + 32:Core/Src/ADBMS_LL_Driver.c **** for (int i = 0; i < (datalen - 2); i++) { + 109 .loc 1 32 14 + 110 0016 0023 movs r3, #0 + 111 0018 3B61 str r3, [r7, #16] + 112 .loc 1 32 5 + 113 001a 1CE0 b .L7 + 114 .L10: + 115 .LBB3: + 33:Core/Src/ADBMS_LL_Driver.c **** for (int n = 0; n < 8; n++) { + 116 .loc 1 33 16 + 117 001c 0023 movs r3, #0 + 118 001e FB60 str r3, [r7, #12] + 119 .loc 1 33 7 + 120 0020 13E0 b .L8 + 121 .L9: + 122 .LBB4: + 34:Core/Src/ADBMS_LL_Driver.c **** const uint8 din = data[i] << (n); + 123 .loc 1 34 33 + 124 0022 3B69 ldr r3, [r7, #16] + 125 0024 7A68 ldr r2, [r7, #4] + 126 0026 1344 add r3, r3, r2 + 127 0028 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 128 002a 1A46 mov r2, r3 + 129 .loc 1 34 37 + 130 002c FB68 ldr r3, [r7, #12] + 131 002e 02FA03F3 lsl r3, r2, r3 + 132 .loc 1 34 23 + 133 0032 FB72 strb r3, [r7, #11] + 35:Core/Src/ADBMS_LL_Driver.c **** currentpec = updateCommandPEC(currentpec, din); + 134 .loc 1 35 22 + 135 0034 FA7A ldrb r2, [r7, #11] @ zero_extendqisi2 + 136 0036 FB8A ldrh r3, [r7, #22] + 137 0038 1146 mov r1, r2 + 138 003a 1846 mov r0, r3 + 139 003c FFF7FEFF bl updateCommandPEC + 140 0040 0346 mov r3, r0 + 141 0042 FB82 strh r3, [r7, #22] @ movhi + ARM GAS /tmp/cczsHaNw.s page 4 + + + 142 .LBE4: + 33:Core/Src/ADBMS_LL_Driver.c **** for (int n = 0; n < 8; n++) { + 143 .loc 1 33 31 discriminator 3 + 144 0044 FB68 ldr r3, [r7, #12] + 145 0046 0133 adds r3, r3, #1 + 146 0048 FB60 str r3, [r7, #12] + 147 .L8: + 33:Core/Src/ADBMS_LL_Driver.c **** for (int n = 0; n < 8; n++) { + 148 .loc 1 33 25 discriminator 1 + 149 004a FB68 ldr r3, [r7, #12] + 150 004c 072B cmp r3, #7 + 151 004e E8DD ble .L9 + 152 .LBE3: + 32:Core/Src/ADBMS_LL_Driver.c **** for (int n = 0; n < 8; n++) { + 153 .loc 1 32 41 discriminator 2 + 154 0050 3B69 ldr r3, [r7, #16] + 155 0052 0133 adds r3, r3, #1 + 156 0054 3B61 str r3, [r7, #16] + 157 .L7: + 32:Core/Src/ADBMS_LL_Driver.c **** for (int n = 0; n < 8; n++) { + 158 .loc 1 32 34 discriminator 1 + 159 0056 FB78 ldrb r3, [r7, #3] @ zero_extendqisi2 + 160 0058 023B subs r3, r3, #2 + 32:Core/Src/ADBMS_LL_Driver.c **** for (int n = 0; n < 8; n++) { + 161 .loc 1 32 23 discriminator 1 + 162 005a 3A69 ldr r2, [r7, #16] + 163 005c 9A42 cmp r2, r3 + 164 005e DDDB blt .L10 + 165 .LBE2: + 36:Core/Src/ADBMS_LL_Driver.c **** } + 37:Core/Src/ADBMS_LL_Driver.c **** } + 38:Core/Src/ADBMS_LL_Driver.c **** + 39:Core/Src/ADBMS_LL_Driver.c **** data[datalen - 2] = (currentpec >> 7) & 0xFF; + 166 .loc 1 39 23 + 167 0060 FB8A ldrh r3, [r7, #22] + 168 0062 DB09 lsrs r3, r3, #7 + 169 0064 99B2 uxth r1, r3 + 170 .loc 1 39 9 + 171 0066 FB78 ldrb r3, [r7, #3] @ zero_extendqisi2 + 172 0068 023B subs r3, r3, #2 + 173 006a 7A68 ldr r2, [r7, #4] + 174 006c 1344 add r3, r3, r2 + 175 .loc 1 39 23 + 176 006e CAB2 uxtb r2, r1 + 177 0070 1A70 strb r2, [r3] + 40:Core/Src/ADBMS_LL_Driver.c **** data[datalen - 1] = (currentpec << 1) & 0xFF; + 178 .loc 1 40 23 + 179 0072 FB8A ldrh r3, [r7, #22] @ movhi + 180 0074 DAB2 uxtb r2, r3 + 181 .loc 1 40 9 + 182 0076 FB78 ldrb r3, [r7, #3] @ zero_extendqisi2 + 183 0078 013B subs r3, r3, #1 + 184 007a 7968 ldr r1, [r7, #4] + 185 007c 0B44 add r3, r3, r1 + 186 .loc 1 40 23 + 187 007e 5200 lsls r2, r2, #1 + 188 0080 D2B2 uxtb r2, r2 + ARM GAS /tmp/cczsHaNw.s page 5 + + + 189 0082 1A70 strb r2, [r3] + 41:Core/Src/ADBMS_LL_Driver.c **** return 0; + 190 .loc 1 41 12 + 191 0084 0023 movs r3, #0 + 192 0086 00E0 b .L11 + 193 .L6: + 42:Core/Src/ADBMS_LL_Driver.c **** } else { + 43:Core/Src/ADBMS_LL_Driver.c **** return 1; + 194 .loc 1 43 12 + 195 0088 0123 movs r3, #1 + 196 .L11: + 44:Core/Src/ADBMS_LL_Driver.c **** } + 45:Core/Src/ADBMS_LL_Driver.c **** } + 197 .loc 1 45 1 + 198 008a 1846 mov r0, r3 + 199 008c 1837 adds r7, r7, #24 + 200 .cfi_def_cfa_offset 8 + 201 008e BD46 mov sp, r7 + 202 .cfi_def_cfa_register 13 + 203 @ sp needed + 204 0090 80BD pop {r7, pc} + 205 .cfi_endproc + 206 .LFE131: + 208 .section .text.checkCommandPEC,"ax",%progbits + 209 .align 1 + 210 .global checkCommandPEC + 211 .syntax unified + 212 .thumb + 213 .thumb_func + 215 checkCommandPEC: + 216 .LFB132: + 46:Core/Src/ADBMS_LL_Driver.c **** + 47:Core/Src/ADBMS_LL_Driver.c **** uint8 checkCommandPEC(uint8* data, uint8 datalen) { + 217 .loc 1 47 51 + 218 .cfi_startproc + 219 @ args = 0, pretend = 0, frame = 24 + 220 @ frame_needed = 1, uses_anonymous_args = 0 + 221 0000 80B5 push {r7, lr} + 222 .cfi_def_cfa_offset 8 + 223 .cfi_offset 7, -8 + 224 .cfi_offset 14, -4 + 225 0002 86B0 sub sp, sp, #24 + 226 .cfi_def_cfa_offset 32 + 227 0004 00AF add r7, sp, #0 + 228 .cfi_def_cfa_register 7 + 229 0006 7860 str r0, [r7, #4] + 230 0008 0B46 mov r3, r1 + 231 000a FB70 strb r3, [r7, #3] + 48:Core/Src/ADBMS_LL_Driver.c **** if (datalen <= 3) { + 232 .loc 1 48 6 + 233 000c FB78 ldrb r3, [r7, #3] @ zero_extendqisi2 + 234 000e 032B cmp r3, #3 + 235 0010 01D8 bhi .L13 + 49:Core/Src/ADBMS_LL_Driver.c **** return 255; + 236 .loc 1 49 12 + 237 0012 FF23 movs r3, #255 + 238 0014 41E0 b .L14 + ARM GAS /tmp/cczsHaNw.s page 6 + + + 239 .L13: + 50:Core/Src/ADBMS_LL_Driver.c **** } + 51:Core/Src/ADBMS_LL_Driver.c **** + 52:Core/Src/ADBMS_LL_Driver.c **** uint16 currentpec = INITIAL_COMMAND_PEC; + 240 .loc 1 52 10 + 241 0016 1023 movs r3, #16 + 242 0018 FB82 strh r3, [r7, #22] @ movhi + 243 .LBB5: + 53:Core/Src/ADBMS_LL_Driver.c **** + 54:Core/Src/ADBMS_LL_Driver.c **** for (int i = 0; i < (datalen - 2); i++) { + 244 .loc 1 54 12 + 245 001a 0023 movs r3, #0 + 246 001c 3B61 str r3, [r7, #16] + 247 .loc 1 54 3 + 248 001e 1CE0 b .L15 + 249 .L18: + 250 .LBB6: + 55:Core/Src/ADBMS_LL_Driver.c **** for (int n = 0; n < 8; n++) { + 251 .loc 1 55 14 + 252 0020 0023 movs r3, #0 + 253 0022 FB60 str r3, [r7, #12] + 254 .loc 1 55 5 + 255 0024 13E0 b .L16 + 256 .L17: + 257 .LBB7: + 56:Core/Src/ADBMS_LL_Driver.c **** const uint8 din = data[i] << (n); + 258 .loc 1 56 31 + 259 0026 3B69 ldr r3, [r7, #16] + 260 0028 7A68 ldr r2, [r7, #4] + 261 002a 1344 add r3, r3, r2 + 262 002c 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 263 002e 1A46 mov r2, r3 + 264 .loc 1 56 35 + 265 0030 FB68 ldr r3, [r7, #12] + 266 0032 02FA03F3 lsl r3, r2, r3 + 267 .loc 1 56 21 + 268 0036 7B72 strb r3, [r7, #9] + 57:Core/Src/ADBMS_LL_Driver.c **** currentpec = updateCommandPEC(currentpec, din); + 269 .loc 1 57 20 + 270 0038 7A7A ldrb r2, [r7, #9] @ zero_extendqisi2 + 271 003a FB8A ldrh r3, [r7, #22] + 272 003c 1146 mov r1, r2 + 273 003e 1846 mov r0, r3 + 274 0040 FFF7FEFF bl updateCommandPEC + 275 0044 0346 mov r3, r0 + 276 0046 FB82 strh r3, [r7, #22] @ movhi + 277 .LBE7: + 55:Core/Src/ADBMS_LL_Driver.c **** for (int n = 0; n < 8; n++) { + 278 .loc 1 55 29 discriminator 3 + 279 0048 FB68 ldr r3, [r7, #12] + 280 004a 0133 adds r3, r3, #1 + 281 004c FB60 str r3, [r7, #12] + 282 .L16: + 55:Core/Src/ADBMS_LL_Driver.c **** for (int n = 0; n < 8; n++) { + 283 .loc 1 55 23 discriminator 1 + 284 004e FB68 ldr r3, [r7, #12] + 285 0050 072B cmp r3, #7 + ARM GAS /tmp/cczsHaNw.s page 7 + + + 286 0052 E8DD ble .L17 + 287 .LBE6: + 54:Core/Src/ADBMS_LL_Driver.c **** for (int n = 0; n < 8; n++) { + 288 .loc 1 54 39 discriminator 2 + 289 0054 3B69 ldr r3, [r7, #16] + 290 0056 0133 adds r3, r3, #1 + 291 0058 3B61 str r3, [r7, #16] + 292 .L15: + 54:Core/Src/ADBMS_LL_Driver.c **** for (int n = 0; n < 8; n++) { + 293 .loc 1 54 32 discriminator 1 + 294 005a FB78 ldrb r3, [r7, #3] @ zero_extendqisi2 + 295 005c 023B subs r3, r3, #2 + 54:Core/Src/ADBMS_LL_Driver.c **** for (int n = 0; n < 8; n++) { + 296 .loc 1 54 21 discriminator 1 + 297 005e 3A69 ldr r2, [r7, #16] + 298 0060 9A42 cmp r2, r3 + 299 0062 DDDB blt .L18 + 300 .LBE5: + 58:Core/Src/ADBMS_LL_Driver.c **** } + 59:Core/Src/ADBMS_LL_Driver.c **** } + 60:Core/Src/ADBMS_LL_Driver.c **** + 61:Core/Src/ADBMS_LL_Driver.c **** const uint8 pechigh = (currentpec >> 7) & 0xFF; + 301 .loc 1 61 15 + 302 0064 FB8A ldrh r3, [r7, #22] + 303 0066 DB09 lsrs r3, r3, #7 + 304 0068 9BB2 uxth r3, r3 + 305 006a FB72 strb r3, [r7, #11] + 62:Core/Src/ADBMS_LL_Driver.c **** const uint8 peclow = (currentpec << 1) & 0xFF; + 306 .loc 1 62 15 + 307 006c FB8A ldrh r3, [r7, #22] @ movhi + 308 006e DBB2 uxtb r3, r3 + 309 0070 5B00 lsls r3, r3, #1 + 310 0072 BB72 strb r3, [r7, #10] + 63:Core/Src/ADBMS_LL_Driver.c **** + 64:Core/Src/ADBMS_LL_Driver.c **** if ((pechigh == data[datalen - 2]) && (peclow == data[datalen - 1])) { + 311 .loc 1 64 23 + 312 0074 FB78 ldrb r3, [r7, #3] @ zero_extendqisi2 + 313 0076 023B subs r3, r3, #2 + 314 0078 7A68 ldr r2, [r7, #4] + 315 007a 1344 add r3, r3, r2 + 316 007c 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 317 .loc 1 64 6 + 318 007e FA7A ldrb r2, [r7, #11] @ zero_extendqisi2 + 319 0080 9A42 cmp r2, r3 + 320 0082 09D1 bne .L19 + 321 .loc 1 64 56 discriminator 1 + 322 0084 FB78 ldrb r3, [r7, #3] @ zero_extendqisi2 + 323 0086 013B subs r3, r3, #1 + 324 0088 7A68 ldr r2, [r7, #4] + 325 008a 1344 add r3, r3, r2 + 326 008c 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 327 .loc 1 64 38 discriminator 1 + 328 008e BA7A ldrb r2, [r7, #10] @ zero_extendqisi2 + 329 0090 9A42 cmp r2, r3 + 330 0092 01D1 bne .L19 + 65:Core/Src/ADBMS_LL_Driver.c **** return 0; + 331 .loc 1 65 12 + ARM GAS /tmp/cczsHaNw.s page 8 + + + 332 0094 0023 movs r3, #0 + 333 0096 00E0 b .L14 + 334 .L19: + 66:Core/Src/ADBMS_LL_Driver.c **** } + 67:Core/Src/ADBMS_LL_Driver.c **** + 68:Core/Src/ADBMS_LL_Driver.c **** return 1; + 335 .loc 1 68 10 + 336 0098 0123 movs r3, #1 + 337 .L14: + 69:Core/Src/ADBMS_LL_Driver.c **** } + 338 .loc 1 69 1 + 339 009a 1846 mov r0, r3 + 340 009c 1837 adds r7, r7, #24 + 341 .cfi_def_cfa_offset 8 + 342 009e BD46 mov sp, r7 + 343 .cfi_def_cfa_register 13 + 344 @ sp needed + 345 00a0 80BD pop {r7, pc} + 346 .cfi_endproc + 347 .LFE132: + 349 .section .text.updateCommandPEC,"ax",%progbits + 350 .align 1 + 351 .global updateCommandPEC + 352 .syntax unified + 353 .thumb + 354 .thumb_func + 356 updateCommandPEC: + 357 .LFB133: + 70:Core/Src/ADBMS_LL_Driver.c **** + 71:Core/Src/ADBMS_LL_Driver.c **** uint16 updateCommandPEC(uint16 currentPEC, uint8 din) { + 358 .loc 1 71 55 + 359 .cfi_startproc + 360 @ args = 0, pretend = 0, frame = 24 + 361 @ frame_needed = 1, uses_anonymous_args = 0 + 362 @ link register save eliminated. + 363 0000 80B4 push {r7} + 364 .cfi_def_cfa_offset 4 + 365 .cfi_offset 7, -4 + 366 0002 87B0 sub sp, sp, #28 + 367 .cfi_def_cfa_offset 32 + 368 0004 00AF add r7, sp, #0 + 369 .cfi_def_cfa_register 7 + 370 0006 0346 mov r3, r0 + 371 0008 0A46 mov r2, r1 + 372 000a FB80 strh r3, [r7, #6] @ movhi + 373 000c 1346 mov r3, r2 + 374 000e 7B71 strb r3, [r7, #5] + 72:Core/Src/ADBMS_LL_Driver.c **** din = (din >> 7) & 0x01; + 375 .loc 1 72 7 + 376 0010 7B79 ldrb r3, [r7, #5] @ zero_extendqisi2 + 377 0012 DB09 lsrs r3, r3, #7 + 378 0014 7B71 strb r3, [r7, #5] + 73:Core/Src/ADBMS_LL_Driver.c **** const uint8 in0 = din ^ ((currentPEC >> 14) & 0x01); + 379 .loc 1 73 47 + 380 0016 FB88 ldrh r3, [r7, #6] + 381 0018 9B0B lsrs r3, r3, #14 + 382 001a 9BB2 uxth r3, r3 + ARM GAS /tmp/cczsHaNw.s page 9 + + + 383 001c 5BB2 sxtb r3, r3 + 384 001e 03F00103 and r3, r3, #1 + 385 0022 5AB2 sxtb r2, r3 + 386 .loc 1 73 25 + 387 0024 97F90530 ldrsb r3, [r7, #5] + 388 0028 5340 eors r3, r3, r2 + 389 002a 5BB2 sxtb r3, r3 + 390 .loc 1 73 15 + 391 002c FB75 strb r3, [r7, #23] + 74:Core/Src/ADBMS_LL_Driver.c **** const uint8 in3 = in0 ^ ((currentPEC >> 2) & 0x01); + 392 .loc 1 74 46 + 393 002e FB88 ldrh r3, [r7, #6] + 394 0030 9B08 lsrs r3, r3, #2 + 395 0032 9BB2 uxth r3, r3 + 396 0034 5BB2 sxtb r3, r3 + 397 0036 03F00103 and r3, r3, #1 + 398 003a 5AB2 sxtb r2, r3 + 399 .loc 1 74 25 + 400 003c 97F91730 ldrsb r3, [r7, #23] + 401 0040 5340 eors r3, r3, r2 + 402 0042 5BB2 sxtb r3, r3 + 403 .loc 1 74 15 + 404 0044 BB75 strb r3, [r7, #22] + 75:Core/Src/ADBMS_LL_Driver.c **** const uint8 in4 = in0 ^ ((currentPEC >> 3) & 0x01); + 405 .loc 1 75 46 + 406 0046 FB88 ldrh r3, [r7, #6] + 407 0048 DB08 lsrs r3, r3, #3 + 408 004a 9BB2 uxth r3, r3 + 409 004c 5BB2 sxtb r3, r3 + 410 004e 03F00103 and r3, r3, #1 + 411 0052 5AB2 sxtb r2, r3 + 412 .loc 1 75 25 + 413 0054 97F91730 ldrsb r3, [r7, #23] + 414 0058 5340 eors r3, r3, r2 + 415 005a 5BB2 sxtb r3, r3 + 416 .loc 1 75 15 + 417 005c 7B75 strb r3, [r7, #21] + 76:Core/Src/ADBMS_LL_Driver.c **** const uint8 in7 = in0 ^ ((currentPEC >> 6) & 0x01); + 418 .loc 1 76 46 + 419 005e FB88 ldrh r3, [r7, #6] + 420 0060 9B09 lsrs r3, r3, #6 + 421 0062 9BB2 uxth r3, r3 + 422 0064 5BB2 sxtb r3, r3 + 423 0066 03F00103 and r3, r3, #1 + 424 006a 5AB2 sxtb r2, r3 + 425 .loc 1 76 25 + 426 006c 97F91730 ldrsb r3, [r7, #23] + 427 0070 5340 eors r3, r3, r2 + 428 0072 5BB2 sxtb r3, r3 + 429 .loc 1 76 15 + 430 0074 3B75 strb r3, [r7, #20] + 77:Core/Src/ADBMS_LL_Driver.c **** const uint8 in8 = in0 ^ ((currentPEC >> 7) & 0x01); + 431 .loc 1 77 46 + 432 0076 FB88 ldrh r3, [r7, #6] + 433 0078 DB09 lsrs r3, r3, #7 + 434 007a 9BB2 uxth r3, r3 + 435 007c 5BB2 sxtb r3, r3 + ARM GAS /tmp/cczsHaNw.s page 10 + + + 436 007e 03F00103 and r3, r3, #1 + 437 0082 5AB2 sxtb r2, r3 + 438 .loc 1 77 25 + 439 0084 97F91730 ldrsb r3, [r7, #23] + 440 0088 5340 eors r3, r3, r2 + 441 008a 5BB2 sxtb r3, r3 + 442 .loc 1 77 15 + 443 008c FB74 strb r3, [r7, #19] + 78:Core/Src/ADBMS_LL_Driver.c **** const uint8 in10 = in0 ^ ((currentPEC >> 9) & 0x01); + 444 .loc 1 78 47 + 445 008e FB88 ldrh r3, [r7, #6] + 446 0090 5B0A lsrs r3, r3, #9 + 447 0092 9BB2 uxth r3, r3 + 448 0094 5BB2 sxtb r3, r3 + 449 0096 03F00103 and r3, r3, #1 + 450 009a 5AB2 sxtb r2, r3 + 451 .loc 1 78 26 + 452 009c 97F91730 ldrsb r3, [r7, #23] + 453 00a0 5340 eors r3, r3, r2 + 454 00a2 5BB2 sxtb r3, r3 + 455 .loc 1 78 15 + 456 00a4 BB74 strb r3, [r7, #18] + 79:Core/Src/ADBMS_LL_Driver.c **** const uint8 in14 = in0 ^ ((currentPEC >> 13) & 0x01); + 457 .loc 1 79 48 + 458 00a6 FB88 ldrh r3, [r7, #6] + 459 00a8 5B0B lsrs r3, r3, #13 + 460 00aa 9BB2 uxth r3, r3 + 461 00ac 5BB2 sxtb r3, r3 + 462 00ae 03F00103 and r3, r3, #1 + 463 00b2 5AB2 sxtb r2, r3 + 464 .loc 1 79 26 + 465 00b4 97F91730 ldrsb r3, [r7, #23] + 466 00b8 5340 eors r3, r3, r2 + 467 00ba 5BB2 sxtb r3, r3 + 468 .loc 1 79 15 + 469 00bc 7B74 strb r3, [r7, #17] + 80:Core/Src/ADBMS_LL_Driver.c **** + 81:Core/Src/ADBMS_LL_Driver.c **** uint16 newPEC = 0; + 470 .loc 1 81 10 + 471 00be 0023 movs r3, #0 + 472 00c0 FB81 strh r3, [r7, #14] @ movhi + 82:Core/Src/ADBMS_LL_Driver.c **** + 83:Core/Src/ADBMS_LL_Driver.c **** newPEC |= in14 << 14; + 473 .loc 1 83 10 + 474 00c2 7B7C ldrb r3, [r7, #17] @ zero_extendqisi2 + 475 00c4 1BB2 sxth r3, r3 + 476 00c6 9B03 lsls r3, r3, #14 + 477 00c8 1AB2 sxth r2, r3 + 478 00ca B7F90E30 ldrsh r3, [r7, #14] + 479 00ce 1343 orrs r3, r3, r2 + 480 00d0 1BB2 sxth r3, r3 + 481 00d2 FB81 strh r3, [r7, #14] @ movhi + 84:Core/Src/ADBMS_LL_Driver.c **** newPEC |= (currentPEC & (0x01 << 12)) << 1; + 482 .loc 1 84 41 + 483 00d4 B7F90630 ldrsh r3, [r7, #6] + 484 00d8 5B00 lsls r3, r3, #1 + 485 00da 1BB2 sxth r3, r3 + ARM GAS /tmp/cczsHaNw.s page 11 + + + 486 00dc 03F40053 and r3, r3, #8192 + 487 00e0 1AB2 sxth r2, r3 + 488 .loc 1 84 10 + 489 00e2 B7F90E30 ldrsh r3, [r7, #14] + 490 00e6 1343 orrs r3, r3, r2 + 491 00e8 1BB2 sxth r3, r3 + 492 00ea FB81 strh r3, [r7, #14] @ movhi + 85:Core/Src/ADBMS_LL_Driver.c **** newPEC |= (currentPEC & (0x01 << 11)) << 1; + 493 .loc 1 85 41 + 494 00ec B7F90630 ldrsh r3, [r7, #6] + 495 00f0 5B00 lsls r3, r3, #1 + 496 00f2 1BB2 sxth r3, r3 + 497 00f4 03F48053 and r3, r3, #4096 + 498 00f8 1AB2 sxth r2, r3 + 499 .loc 1 85 10 + 500 00fa B7F90E30 ldrsh r3, [r7, #14] + 501 00fe 1343 orrs r3, r3, r2 + 502 0100 1BB2 sxth r3, r3 + 503 0102 FB81 strh r3, [r7, #14] @ movhi + 86:Core/Src/ADBMS_LL_Driver.c **** newPEC |= (currentPEC & (0x01 << 10)) << 1; + 504 .loc 1 86 41 + 505 0104 B7F90630 ldrsh r3, [r7, #6] + 506 0108 5B00 lsls r3, r3, #1 + 507 010a 1BB2 sxth r3, r3 + 508 010c 03F40063 and r3, r3, #2048 + 509 0110 1AB2 sxth r2, r3 + 510 .loc 1 86 10 + 511 0112 B7F90E30 ldrsh r3, [r7, #14] + 512 0116 1343 orrs r3, r3, r2 + 513 0118 1BB2 sxth r3, r3 + 514 011a FB81 strh r3, [r7, #14] @ movhi + 87:Core/Src/ADBMS_LL_Driver.c **** newPEC |= in10 << 10; + 515 .loc 1 87 10 + 516 011c BB7C ldrb r3, [r7, #18] @ zero_extendqisi2 + 517 011e 1BB2 sxth r3, r3 + 518 0120 9B02 lsls r3, r3, #10 + 519 0122 1AB2 sxth r2, r3 + 520 0124 B7F90E30 ldrsh r3, [r7, #14] + 521 0128 1343 orrs r3, r3, r2 + 522 012a 1BB2 sxth r3, r3 + 523 012c FB81 strh r3, [r7, #14] @ movhi + 88:Core/Src/ADBMS_LL_Driver.c **** newPEC |= (currentPEC & (0x01 << 8)) << 1; + 524 .loc 1 88 40 + 525 012e B7F90630 ldrsh r3, [r7, #6] + 526 0132 5B00 lsls r3, r3, #1 + 527 0134 1BB2 sxth r3, r3 + 528 0136 03F40073 and r3, r3, #512 + 529 013a 1AB2 sxth r2, r3 + 530 .loc 1 88 10 + 531 013c B7F90E30 ldrsh r3, [r7, #14] + 532 0140 1343 orrs r3, r3, r2 + 533 0142 1BB2 sxth r3, r3 + 534 0144 FB81 strh r3, [r7, #14] @ movhi + 89:Core/Src/ADBMS_LL_Driver.c **** newPEC |= in8 << 8; + 535 .loc 1 89 10 + 536 0146 FB7C ldrb r3, [r7, #19] @ zero_extendqisi2 + 537 0148 1BB2 sxth r3, r3 + ARM GAS /tmp/cczsHaNw.s page 12 + + + 538 014a 1B02 lsls r3, r3, #8 + 539 014c 1AB2 sxth r2, r3 + 540 014e B7F90E30 ldrsh r3, [r7, #14] + 541 0152 1343 orrs r3, r3, r2 + 542 0154 1BB2 sxth r3, r3 + 543 0156 FB81 strh r3, [r7, #14] @ movhi + 90:Core/Src/ADBMS_LL_Driver.c **** newPEC |= in7 << 7; + 544 .loc 1 90 10 + 545 0158 3B7D ldrb r3, [r7, #20] @ zero_extendqisi2 + 546 015a 1BB2 sxth r3, r3 + 547 015c DB01 lsls r3, r3, #7 + 548 015e 1AB2 sxth r2, r3 + 549 0160 B7F90E30 ldrsh r3, [r7, #14] + 550 0164 1343 orrs r3, r3, r2 + 551 0166 1BB2 sxth r3, r3 + 552 0168 FB81 strh r3, [r7, #14] @ movhi + 91:Core/Src/ADBMS_LL_Driver.c **** newPEC |= (currentPEC & (0x01 << 5)) << 1; + 553 .loc 1 91 40 + 554 016a B7F90630 ldrsh r3, [r7, #6] + 555 016e 5B00 lsls r3, r3, #1 + 556 0170 1BB2 sxth r3, r3 + 557 0172 03F04003 and r3, r3, #64 + 558 0176 1AB2 sxth r2, r3 + 559 .loc 1 91 10 + 560 0178 B7F90E30 ldrsh r3, [r7, #14] + 561 017c 1343 orrs r3, r3, r2 + 562 017e 1BB2 sxth r3, r3 + 563 0180 FB81 strh r3, [r7, #14] @ movhi + 92:Core/Src/ADBMS_LL_Driver.c **** newPEC |= (currentPEC & (0x01 << 4)) << 1; + 564 .loc 1 92 40 + 565 0182 B7F90630 ldrsh r3, [r7, #6] + 566 0186 5B00 lsls r3, r3, #1 + 567 0188 1BB2 sxth r3, r3 + 568 018a 03F02003 and r3, r3, #32 + 569 018e 1AB2 sxth r2, r3 + 570 .loc 1 92 10 + 571 0190 B7F90E30 ldrsh r3, [r7, #14] + 572 0194 1343 orrs r3, r3, r2 + 573 0196 1BB2 sxth r3, r3 + 574 0198 FB81 strh r3, [r7, #14] @ movhi + 93:Core/Src/ADBMS_LL_Driver.c **** newPEC |= in4 << 4; + 575 .loc 1 93 10 + 576 019a 7B7D ldrb r3, [r7, #21] @ zero_extendqisi2 + 577 019c 1BB2 sxth r3, r3 + 578 019e 1B01 lsls r3, r3, #4 + 579 01a0 1AB2 sxth r2, r3 + 580 01a2 B7F90E30 ldrsh r3, [r7, #14] + 581 01a6 1343 orrs r3, r3, r2 + 582 01a8 1BB2 sxth r3, r3 + 583 01aa FB81 strh r3, [r7, #14] @ movhi + 94:Core/Src/ADBMS_LL_Driver.c **** newPEC |= in3 << 3; + 584 .loc 1 94 10 + 585 01ac BB7D ldrb r3, [r7, #22] @ zero_extendqisi2 + 586 01ae 1BB2 sxth r3, r3 + 587 01b0 DB00 lsls r3, r3, #3 + 588 01b2 1AB2 sxth r2, r3 + 589 01b4 B7F90E30 ldrsh r3, [r7, #14] + ARM GAS /tmp/cczsHaNw.s page 13 + + + 590 01b8 1343 orrs r3, r3, r2 + 591 01ba 1BB2 sxth r3, r3 + 592 01bc FB81 strh r3, [r7, #14] @ movhi + 95:Core/Src/ADBMS_LL_Driver.c **** newPEC |= (currentPEC & (0x01 << 1)) << 1; + 593 .loc 1 95 40 + 594 01be B7F90630 ldrsh r3, [r7, #6] + 595 01c2 5B00 lsls r3, r3, #1 + 596 01c4 1BB2 sxth r3, r3 + 597 01c6 03F00403 and r3, r3, #4 + 598 01ca 1AB2 sxth r2, r3 + 599 .loc 1 95 10 + 600 01cc B7F90E30 ldrsh r3, [r7, #14] + 601 01d0 1343 orrs r3, r3, r2 + 602 01d2 1BB2 sxth r3, r3 + 603 01d4 FB81 strh r3, [r7, #14] @ movhi + 96:Core/Src/ADBMS_LL_Driver.c **** newPEC |= (currentPEC & (0x01)) << 1; + 604 .loc 1 96 35 + 605 01d6 B7F90630 ldrsh r3, [r7, #6] + 606 01da 5B00 lsls r3, r3, #1 + 607 01dc 1BB2 sxth r3, r3 + 608 01de 03F00203 and r3, r3, #2 + 609 01e2 1AB2 sxth r2, r3 + 610 .loc 1 96 10 + 611 01e4 B7F90E30 ldrsh r3, [r7, #14] + 612 01e8 1343 orrs r3, r3, r2 + 613 01ea 1BB2 sxth r3, r3 + 614 01ec FB81 strh r3, [r7, #14] @ movhi + 97:Core/Src/ADBMS_LL_Driver.c **** newPEC |= in0; + 615 .loc 1 97 10 + 616 01ee FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 617 01f0 9AB2 uxth r2, r3 + 618 01f2 FB89 ldrh r3, [r7, #14] @ movhi + 619 01f4 1343 orrs r3, r3, r2 + 620 01f6 FB81 strh r3, [r7, #14] @ movhi + 98:Core/Src/ADBMS_LL_Driver.c **** + 99:Core/Src/ADBMS_LL_Driver.c **** return newPEC; + 621 .loc 1 99 10 + 622 01f8 FB89 ldrh r3, [r7, #14] + 100:Core/Src/ADBMS_LL_Driver.c **** } + 623 .loc 1 100 1 + 624 01fa 1846 mov r0, r3 + 625 01fc 1C37 adds r7, r7, #28 + 626 .cfi_def_cfa_offset 4 + 627 01fe BD46 mov sp, r7 + 628 .cfi_def_cfa_register 13 + 629 @ sp needed + 630 0200 5DF8047B ldr r7, [sp], #4 + 631 .cfi_restore 7 + 632 .cfi_def_cfa_offset 0 + 633 0204 7047 bx lr + 634 .cfi_endproc + 635 .LFE133: + 637 .section .text.pec10_calc,"ax",%progbits + 638 .align 1 + 639 .global pec10_calc + 640 .syntax unified + 641 .thumb + ARM GAS /tmp/cczsHaNw.s page 14 + + + 642 .thumb_func + 644 pec10_calc: + 645 .LFB134: + 101:Core/Src/ADBMS_LL_Driver.c **** + 102:Core/Src/ADBMS_LL_Driver.c **** //data PEC calculation + 103:Core/Src/ADBMS_LL_Driver.c **** //CRC-10 + 104:Core/Src/ADBMS_LL_Driver.c **** //x^10 + x^7 + x^3 + x^2 + x + 1 + 105:Core/Src/ADBMS_LL_Driver.c **** + 106:Core/Src/ADBMS_LL_Driver.c **** uint16_t pec10_calc(bool rx_cmd, int len, const uint8_t* data) { + 646 .loc 1 106 64 + 647 .cfi_startproc + 648 @ args = 0, pretend = 0, frame = 24 + 649 @ frame_needed = 1, uses_anonymous_args = 0 + 650 @ link register save eliminated. + 651 0000 80B4 push {r7} + 652 .cfi_def_cfa_offset 4 + 653 .cfi_offset 7, -4 + 654 0002 87B0 sub sp, sp, #28 + 655 .cfi_def_cfa_offset 32 + 656 0004 00AF add r7, sp, #0 + 657 .cfi_def_cfa_register 7 + 658 0006 0346 mov r3, r0 + 659 0008 B960 str r1, [r7, #8] + 660 000a 7A60 str r2, [r7, #4] + 661 000c FB73 strb r3, [r7, #15] + 107:Core/Src/ADBMS_LL_Driver.c **** uint16_t remainder = 16; /* PEC_SEED; 0000010000 */ + 662 .loc 1 107 12 + 663 000e 1023 movs r3, #16 + 664 0010 FB82 strh r3, [r7, #22] @ movhi + 108:Core/Src/ADBMS_LL_Driver.c **** const uint16_t polynom = 0x8F; /* x10 + x7 + x3 + x2 + x + 1 <- the CRC15 polynomial + 665 .loc 1 108 18 + 666 0012 8F23 movs r3, #143 + 667 0014 3B82 strh r3, [r7, #16] @ movhi + 668 .LBB8: + 109:Core/Src/ADBMS_LL_Driver.c **** 100 1000 1111 48F */ + 110:Core/Src/ADBMS_LL_Driver.c **** + 111:Core/Src/ADBMS_LL_Driver.c **** /* Perform modulo-2 division, a byte at a time. */ + 112:Core/Src/ADBMS_LL_Driver.c **** for (uint8_t pbyte = 0; pbyte < len; ++pbyte) { + 669 .loc 1 112 16 + 670 0016 0023 movs r3, #0 + 671 0018 7B75 strb r3, [r7, #21] + 672 .loc 1 112 3 + 673 001a 24E0 b .L23 + 674 .L28: + 113:Core/Src/ADBMS_LL_Driver.c **** /* Bring the next byte into the remainder. */ + 114:Core/Src/ADBMS_LL_Driver.c **** remainder ^= (uint16_t)(data[pbyte] << 2); + 675 .loc 1 114 33 + 676 001c 7B7D ldrb r3, [r7, #21] @ zero_extendqisi2 + 677 001e 7A68 ldr r2, [r7, #4] + 678 0020 1344 add r3, r3, r2 + 679 0022 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 680 .loc 1 114 18 + 681 0024 9B00 lsls r3, r3, #2 + 682 0026 9AB2 uxth r2, r3 + 683 .loc 1 114 15 + 684 0028 FB8A ldrh r3, [r7, #22] @ movhi + 685 002a 5340 eors r3, r3, r2 + ARM GAS /tmp/cczsHaNw.s page 15 + + + 686 002c FB82 strh r3, [r7, #22] @ movhi + 687 .LBB9: + 115:Core/Src/ADBMS_LL_Driver.c **** /* Perform modulo-2 division, a bit at a time.*/ + 116:Core/Src/ADBMS_LL_Driver.c **** for (uint8_t bit_ = 8; bit_ > 0; --bit_) { + 688 .loc 1 116 18 + 689 002e 0823 movs r3, #8 + 690 0030 3B75 strb r3, [r7, #20] + 691 .loc 1 116 5 + 692 0032 12E0 b .L24 + 693 .L27: + 117:Core/Src/ADBMS_LL_Driver.c **** /* Try to divide the current data bit. */ + 118:Core/Src/ADBMS_LL_Driver.c **** if ((remainder & 0x200) > + 694 .loc 1 118 22 + 695 0034 FB8A ldrh r3, [r7, #22] + 696 0036 03F40073 and r3, r3, #512 + 697 .loc 1 118 10 + 698 003a 002B cmp r3, #0 + 699 003c 07DD ble .L25 + 119:Core/Src/ADBMS_LL_Driver.c **** 0) // equivalent to remainder & 2^14 simply check for MSB + 120:Core/Src/ADBMS_LL_Driver.c **** { + 121:Core/Src/ADBMS_LL_Driver.c **** remainder = (uint16_t)((remainder << 1)); + 700 .loc 1 121 19 + 701 003e FB8A ldrh r3, [r7, #22] @ movhi + 702 0040 5B00 lsls r3, r3, #1 + 703 0042 FB82 strh r3, [r7, #22] @ movhi + 122:Core/Src/ADBMS_LL_Driver.c **** remainder = (uint16_t)(remainder ^ polynom); + 704 .loc 1 122 19 + 705 0044 FA8A ldrh r2, [r7, #22] @ movhi + 706 0046 3B8A ldrh r3, [r7, #16] @ movhi + 707 0048 5340 eors r3, r3, r2 + 708 004a FB82 strh r3, [r7, #22] @ movhi + 709 004c 02E0 b .L26 + 710 .L25: + 123:Core/Src/ADBMS_LL_Driver.c **** } else { + 124:Core/Src/ADBMS_LL_Driver.c **** remainder = (uint16_t)(remainder << 1); + 711 .loc 1 124 19 + 712 004e FB8A ldrh r3, [r7, #22] @ movhi + 713 0050 5B00 lsls r3, r3, #1 + 714 0052 FB82 strh r3, [r7, #22] @ movhi + 715 .L26: + 116:Core/Src/ADBMS_LL_Driver.c **** /* Try to divide the current data bit. */ + 716 .loc 1 116 38 discriminator 2 + 717 0054 3B7D ldrb r3, [r7, #20] + 718 0056 013B subs r3, r3, #1 + 719 0058 3B75 strb r3, [r7, #20] + 720 .L24: + 116:Core/Src/ADBMS_LL_Driver.c **** /* Try to divide the current data bit. */ + 721 .loc 1 116 33 discriminator 1 + 722 005a 3B7D ldrb r3, [r7, #20] @ zero_extendqisi2 + 723 005c 002B cmp r3, #0 + 724 005e E9D1 bne .L27 + 725 .LBE9: + 112:Core/Src/ADBMS_LL_Driver.c **** /* Bring the next byte into the remainder. */ + 726 .loc 1 112 40 discriminator 2 + 727 0060 7B7D ldrb r3, [r7, #21] + 728 0062 0133 adds r3, r3, #1 + 729 0064 7B75 strb r3, [r7, #21] + ARM GAS /tmp/cczsHaNw.s page 16 + + + 730 .L23: + 112:Core/Src/ADBMS_LL_Driver.c **** /* Bring the next byte into the remainder. */ + 731 .loc 1 112 33 discriminator 1 + 732 0066 7B7D ldrb r3, [r7, #21] @ zero_extendqisi2 + 733 0068 BA68 ldr r2, [r7, #8] + 734 006a 9A42 cmp r2, r3 + 735 006c D6DC bgt .L28 + 736 .LBE8: + 125:Core/Src/ADBMS_LL_Driver.c **** } + 126:Core/Src/ADBMS_LL_Driver.c **** } + 127:Core/Src/ADBMS_LL_Driver.c **** } + 128:Core/Src/ADBMS_LL_Driver.c **** if (rx_cmd == true) { + 737 .loc 1 128 6 + 738 006e FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 739 0070 002B cmp r3, #0 + 740 0072 27D0 beq .L29 + 129:Core/Src/ADBMS_LL_Driver.c **** remainder ^= (uint16_t)((data[len] & 0xFC) << 2); + 741 .loc 1 129 34 + 742 0074 BB68 ldr r3, [r7, #8] + 743 0076 7A68 ldr r2, [r7, #4] + 744 0078 1344 add r3, r3, r2 + 745 007a 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 746 .loc 1 129 48 + 747 007c 1BB2 sxth r3, r3 + 748 007e 9B00 lsls r3, r3, #2 + 749 0080 1BB2 sxth r3, r3 + 750 .loc 1 129 18 + 751 0082 03F47C73 and r3, r3, #1008 + 752 0086 1AB2 sxth r2, r3 + 753 .loc 1 129 15 + 754 0088 B7F91630 ldrsh r3, [r7, #22] + 755 008c 5340 eors r3, r3, r2 + 756 008e 1BB2 sxth r3, r3 + 757 0090 FB82 strh r3, [r7, #22] @ movhi + 758 .LBB10: + 130:Core/Src/ADBMS_LL_Driver.c **** /* Perform modulo-2 division, a bit at a time */ + 131:Core/Src/ADBMS_LL_Driver.c **** for (uint8_t bit_ = 6; bit_ > 0; --bit_) { + 759 .loc 1 131 18 + 760 0092 0623 movs r3, #6 + 761 0094 FB74 strb r3, [r7, #19] + 762 .loc 1 131 5 + 763 0096 12E0 b .L30 + 764 .L33: + 132:Core/Src/ADBMS_LL_Driver.c **** /* Try to divide the current data bit */ + 133:Core/Src/ADBMS_LL_Driver.c **** if ((remainder & 0x200) > + 765 .loc 1 133 22 + 766 0098 FB8A ldrh r3, [r7, #22] + 767 009a 03F40073 and r3, r3, #512 + 768 .loc 1 133 10 + 769 009e 002B cmp r3, #0 + 770 00a0 07DD ble .L31 + 134:Core/Src/ADBMS_LL_Driver.c **** 0) // equivalent to remainder & 2^14 simply check for MSB + 135:Core/Src/ADBMS_LL_Driver.c **** { + 136:Core/Src/ADBMS_LL_Driver.c **** remainder = (uint16_t)((remainder << 1)); + 771 .loc 1 136 19 + 772 00a2 FB8A ldrh r3, [r7, #22] @ movhi + 773 00a4 5B00 lsls r3, r3, #1 + ARM GAS /tmp/cczsHaNw.s page 17 + + + 774 00a6 FB82 strh r3, [r7, #22] @ movhi + 137:Core/Src/ADBMS_LL_Driver.c **** remainder = (uint16_t)(remainder ^ polynom); + 775 .loc 1 137 19 + 776 00a8 FA8A ldrh r2, [r7, #22] @ movhi + 777 00aa 3B8A ldrh r3, [r7, #16] @ movhi + 778 00ac 5340 eors r3, r3, r2 + 779 00ae FB82 strh r3, [r7, #22] @ movhi + 780 00b0 02E0 b .L32 + 781 .L31: + 138:Core/Src/ADBMS_LL_Driver.c **** } else { + 139:Core/Src/ADBMS_LL_Driver.c **** remainder = (uint16_t)((remainder << 1)); + 782 .loc 1 139 19 + 783 00b2 FB8A ldrh r3, [r7, #22] @ movhi + 784 00b4 5B00 lsls r3, r3, #1 + 785 00b6 FB82 strh r3, [r7, #22] @ movhi + 786 .L32: + 131:Core/Src/ADBMS_LL_Driver.c **** /* Try to divide the current data bit */ + 787 .loc 1 131 38 discriminator 2 + 788 00b8 FB7C ldrb r3, [r7, #19] + 789 00ba 013B subs r3, r3, #1 + 790 00bc FB74 strb r3, [r7, #19] + 791 .L30: + 131:Core/Src/ADBMS_LL_Driver.c **** /* Try to divide the current data bit */ + 792 .loc 1 131 33 discriminator 1 + 793 00be FB7C ldrb r3, [r7, #19] @ zero_extendqisi2 + 794 00c0 002B cmp r3, #0 + 795 00c2 E9D1 bne .L33 + 796 .L29: + 797 .LBE10: + 140:Core/Src/ADBMS_LL_Driver.c **** } + 141:Core/Src/ADBMS_LL_Driver.c **** } + 142:Core/Src/ADBMS_LL_Driver.c **** } + 143:Core/Src/ADBMS_LL_Driver.c **** return ((uint16_t)(remainder & 0x3FF)); + 798 .loc 1 143 11 + 799 00c4 FB8A ldrh r3, [r7, #22] @ movhi + 800 00c6 C3F30903 ubfx r3, r3, #0, #10 + 801 00ca 9BB2 uxth r3, r3 + 144:Core/Src/ADBMS_LL_Driver.c **** } + 802 .loc 1 144 1 + 803 00cc 1846 mov r0, r3 + 804 00ce 1C37 adds r7, r7, #28 + 805 .cfi_def_cfa_offset 4 + 806 00d0 BD46 mov sp, r7 + 807 .cfi_def_cfa_register 13 + 808 @ sp needed + 809 00d2 5DF8047B ldr r7, [sp], #4 + 810 .cfi_restore 7 + 811 .cfi_def_cfa_offset 0 + 812 00d6 7047 bx lr + 813 .cfi_endproc + 814 .LFE134: + 816 .section .text.calculateDataPEC,"ax",%progbits + 817 .align 1 + 818 .global calculateDataPEC + 819 .syntax unified + 820 .thumb + 821 .thumb_func + ARM GAS /tmp/cczsHaNw.s page 18 + + + 823 calculateDataPEC: + 824 .LFB135: + 145:Core/Src/ADBMS_LL_Driver.c **** + 146:Core/Src/ADBMS_LL_Driver.c **** typedef uint16_t crc; + 147:Core/Src/ADBMS_LL_Driver.c **** crc F_CRC_CalculaCheckSum(uint8_t const AF_Datos[], uint16_t VF_nBytes); + 148:Core/Src/ADBMS_LL_Driver.c **** + 149:Core/Src/ADBMS_LL_Driver.c **** uint8 calculateDataPEC(uint8_t* data, uint8_t datalen) { + 825 .loc 1 149 56 + 826 .cfi_startproc + 827 @ args = 0, pretend = 0, frame = 16 + 828 @ frame_needed = 1, uses_anonymous_args = 0 + 829 0000 80B5 push {r7, lr} + 830 .cfi_def_cfa_offset 8 + 831 .cfi_offset 7, -8 + 832 .cfi_offset 14, -4 + 833 0002 84B0 sub sp, sp, #16 + 834 .cfi_def_cfa_offset 24 + 835 0004 00AF add r7, sp, #0 + 836 .cfi_def_cfa_register 7 + 837 0006 7860 str r0, [r7, #4] + 838 0008 0B46 mov r3, r1 + 839 000a FB70 strb r3, [r7, #3] + 150:Core/Src/ADBMS_LL_Driver.c **** + 151:Core/Src/ADBMS_LL_Driver.c **** if (datalen >= 3) { + 840 .loc 1 151 6 + 841 000c FB78 ldrb r3, [r7, #3] @ zero_extendqisi2 + 842 000e 022B cmp r3, #2 + 843 0010 1CD9 bls .L36 + 844 .LBB11: + 152:Core/Src/ADBMS_LL_Driver.c **** + 153:Core/Src/ADBMS_LL_Driver.c **** const crc currentpec = pec10_calc(true, datalen - 2, data) & 0x3FF; // mask to 10 bits + 845 .loc 1 153 30 + 846 0012 FB78 ldrb r3, [r7, #3] @ zero_extendqisi2 + 847 0014 023B subs r3, r3, #2 + 848 0016 7A68 ldr r2, [r7, #4] + 849 0018 1946 mov r1, r3 + 850 001a 0120 movs r0, #1 + 851 001c FFF7FEFF bl pec10_calc + 852 0020 0346 mov r3, r0 + 853 .loc 1 153 17 discriminator 1 + 854 0022 C3F30903 ubfx r3, r3, #0, #10 + 855 0026 FB81 strh r3, [r7, #14] @ movhi + 154:Core/Src/ADBMS_LL_Driver.c **** + 155:Core/Src/ADBMS_LL_Driver.c **** // memory layout is [[zeroes], PEC[9:8]], [PEC[7:0]] + 156:Core/Src/ADBMS_LL_Driver.c **** data[datalen - 2] = (currentpec >> 8) & 0xFF; + 856 .loc 1 156 23 + 857 0028 FB89 ldrh r3, [r7, #14] + 858 002a 1B0A lsrs r3, r3, #8 + 859 002c 99B2 uxth r1, r3 + 860 .loc 1 156 9 + 861 002e FB78 ldrb r3, [r7, #3] @ zero_extendqisi2 + 862 0030 023B subs r3, r3, #2 + 863 0032 7A68 ldr r2, [r7, #4] + 864 0034 1344 add r3, r3, r2 + 865 .loc 1 156 23 + 866 0036 CAB2 uxtb r2, r1 + 867 0038 1A70 strb r2, [r3] + ARM GAS /tmp/cczsHaNw.s page 19 + + + 157:Core/Src/ADBMS_LL_Driver.c **** data[datalen - 1] = currentpec & 0xFF; + 868 .loc 1 157 9 + 869 003a FB78 ldrb r3, [r7, #3] @ zero_extendqisi2 + 870 003c 013B subs r3, r3, #1 + 871 003e 7A68 ldr r2, [r7, #4] + 872 0040 1344 add r3, r3, r2 + 873 .loc 1 157 23 + 874 0042 FA89 ldrh r2, [r7, #14] @ movhi + 875 0044 D2B2 uxtb r2, r2 + 876 0046 1A70 strb r2, [r3] + 158:Core/Src/ADBMS_LL_Driver.c **** + 159:Core/Src/ADBMS_LL_Driver.c **** return 0; + 877 .loc 1 159 12 + 878 0048 0023 movs r3, #0 + 879 004a 00E0 b .L37 + 880 .L36: + 881 .LBE11: + 160:Core/Src/ADBMS_LL_Driver.c **** } else { + 161:Core/Src/ADBMS_LL_Driver.c **** return 1; + 882 .loc 1 161 12 + 883 004c 0123 movs r3, #1 + 884 .L37: + 162:Core/Src/ADBMS_LL_Driver.c **** } + 163:Core/Src/ADBMS_LL_Driver.c **** } + 885 .loc 1 163 1 + 886 004e 1846 mov r0, r3 + 887 0050 1037 adds r7, r7, #16 + 888 .cfi_def_cfa_offset 8 + 889 0052 BD46 mov sp, r7 + 890 .cfi_def_cfa_register 13 + 891 @ sp needed + 892 0054 80BD pop {r7, pc} + 893 .cfi_endproc + 894 .LFE135: + 896 .section .text.checkDataPEC,"ax",%progbits + 897 .align 1 + 898 .global checkDataPEC + 899 .syntax unified + 900 .thumb + 901 .thumb_func + 903 checkDataPEC: + 904 .LFB136: + 164:Core/Src/ADBMS_LL_Driver.c **** + 165:Core/Src/ADBMS_LL_Driver.c **** uint8 checkDataPEC(uint8* data, uint8 len) { + 905 .loc 1 165 44 + 906 .cfi_startproc + 907 @ args = 0, pretend = 0, frame = 16 + 908 @ frame_needed = 1, uses_anonymous_args = 0 + 909 0000 80B5 push {r7, lr} + 910 .cfi_def_cfa_offset 8 + 911 .cfi_offset 7, -8 + 912 .cfi_offset 14, -4 + 913 0002 84B0 sub sp, sp, #16 + 914 .cfi_def_cfa_offset 24 + 915 0004 00AF add r7, sp, #0 + 916 .cfi_def_cfa_register 7 + 917 0006 7860 str r0, [r7, #4] + ARM GAS /tmp/cczsHaNw.s page 20 + + + 918 0008 0B46 mov r3, r1 + 919 000a FB70 strb r3, [r7, #3] + 166:Core/Src/ADBMS_LL_Driver.c **** if (len <= 2) { + 920 .loc 1 166 6 + 921 000c FB78 ldrb r3, [r7, #3] @ zero_extendqisi2 + 922 000e 022B cmp r3, #2 + 923 0010 01D8 bhi .L39 + 167:Core/Src/ADBMS_LL_Driver.c **** return 255; + 924 .loc 1 167 12 + 925 0012 FF23 movs r3, #255 + 926 0014 0DE0 b .L40 + 927 .L39: + 168:Core/Src/ADBMS_LL_Driver.c **** } + 169:Core/Src/ADBMS_LL_Driver.c **** + 170:Core/Src/ADBMS_LL_Driver.c **** const crc currentpec = F_CRC_CalculaCheckSum(data, len); + 928 .loc 1 170 26 + 929 0016 FB78 ldrb r3, [r7, #3] @ zero_extendqisi2 + 930 0018 9BB2 uxth r3, r3 + 931 001a 1946 mov r1, r3 + 932 001c 7868 ldr r0, [r7, #4] + 933 001e FFF7FEFF bl F_CRC_CalculaCheckSum + 934 0022 0346 mov r3, r0 + 935 0024 FB81 strh r3, [r7, #14] @ movhi + 171:Core/Src/ADBMS_LL_Driver.c **** + 172:Core/Src/ADBMS_LL_Driver.c **** return (currentpec == 0) ? 0 : 1; + 936 .loc 1 172 32 + 937 0026 FB89 ldrh r3, [r7, #14] + 938 0028 002B cmp r3, #0 + 939 002a 14BF ite ne + 940 002c 0123 movne r3, #1 + 941 002e 0023 moveq r3, #0 + 942 0030 DBB2 uxtb r3, r3 + 943 .L40: + 173:Core/Src/ADBMS_LL_Driver.c **** } + 944 .loc 1 173 1 + 945 0032 1846 mov r0, r3 + 946 0034 1037 adds r7, r7, #16 + 947 .cfi_def_cfa_offset 8 + 948 0036 BD46 mov sp, r7 + 949 .cfi_def_cfa_register 13 + 950 @ sp needed + 951 0038 80BD pop {r7, pc} + 952 .cfi_endproc + 953 .LFE136: + 955 .section .text.F_CRC_ObtenValorDeTabla,"ax",%progbits + 956 .align 1 + 957 .syntax unified + 958 .thumb + 959 .thumb_func + 961 F_CRC_ObtenValorDeTabla: + 962 .LFB137: + 174:Core/Src/ADBMS_LL_Driver.c **** + 175:Core/Src/ADBMS_LL_Driver.c **** + 176:Core/Src/ADBMS_LL_Driver.c **** static crc F_CRC_ObtenValorDeTabla(uint8_t VP_Pos_Tabla) { + 963 .loc 1 176 58 + 964 .cfi_startproc + 965 @ args = 0, pretend = 0, frame = 16 + ARM GAS /tmp/cczsHaNw.s page 21 + + + 966 @ frame_needed = 1, uses_anonymous_args = 0 + 967 @ link register save eliminated. + 968 0000 80B4 push {r7} + 969 .cfi_def_cfa_offset 4 + 970 .cfi_offset 7, -4 + 971 0002 85B0 sub sp, sp, #20 + 972 .cfi_def_cfa_offset 24 + 973 0004 00AF add r7, sp, #0 + 974 .cfi_def_cfa_register 7 + 975 0006 0346 mov r3, r0 + 976 0008 FB71 strb r3, [r7, #7] + 177:Core/Src/ADBMS_LL_Driver.c **** crc VP_CRCTableValue = 0; + 977 .loc 1 177 7 + 978 000a 0023 movs r3, #0 + 979 000c FB81 strh r3, [r7, #14] @ movhi + 178:Core/Src/ADBMS_LL_Driver.c **** uint8_t VP_Pos_bit = 0; + 980 .loc 1 178 11 + 981 000e 0023 movs r3, #0 + 982 0010 7B73 strb r3, [r7, #13] + 179:Core/Src/ADBMS_LL_Driver.c **** + 180:Core/Src/ADBMS_LL_Driver.c **** VP_CRCTableValue = ((crc)(VP_Pos_Tabla)) << (10 - 8); + 983 .loc 1 180 44 + 984 0012 FB79 ldrb r3, [r7, #7] @ zero_extendqisi2 + 985 0014 9BB2 uxth r3, r3 + 986 .loc 1 180 20 + 987 0016 9B00 lsls r3, r3, #2 + 988 0018 FB81 strh r3, [r7, #14] @ movhi + 181:Core/Src/ADBMS_LL_Driver.c **** + 182:Core/Src/ADBMS_LL_Driver.c **** for (VP_Pos_bit = 0; VP_Pos_bit < 8; VP_Pos_bit++) { + 989 .loc 1 182 19 + 990 001a 0023 movs r3, #0 + 991 001c 7B73 strb r3, [r7, #13] + 992 .loc 1 182 3 + 993 001e 13E0 b .L42 + 994 .L45: + 183:Core/Src/ADBMS_LL_Driver.c **** if (VP_CRCTableValue & (((crc)1) << (10 - 1))) { + 995 .loc 1 183 26 + 996 0020 FB89 ldrh r3, [r7, #14] + 997 0022 03F40073 and r3, r3, #512 + 998 .loc 1 183 8 + 999 0026 002B cmp r3, #0 + 1000 0028 08D0 beq .L43 + 184:Core/Src/ADBMS_LL_Driver.c **** VP_CRCTableValue = (VP_CRCTableValue << 1) ^ 0x8F; + 1001 .loc 1 184 50 + 1002 002a B7F90E30 ldrsh r3, [r7, #14] + 1003 002e 5B00 lsls r3, r3, #1 + 1004 0030 1BB2 sxth r3, r3 + 1005 0032 83F08F03 eor r3, r3, #143 + 1006 0036 1BB2 sxth r3, r3 + 1007 .loc 1 184 24 + 1008 0038 FB81 strh r3, [r7, #14] @ movhi + 1009 003a 02E0 b .L44 + 1010 .L43: + 185:Core/Src/ADBMS_LL_Driver.c **** } else { + 186:Core/Src/ADBMS_LL_Driver.c **** VP_CRCTableValue = (VP_CRCTableValue << 1); + 1011 .loc 1 186 24 + 1012 003c FB89 ldrh r3, [r7, #14] @ movhi + ARM GAS /tmp/cczsHaNw.s page 22 + + + 1013 003e 5B00 lsls r3, r3, #1 + 1014 0040 FB81 strh r3, [r7, #14] @ movhi + 1015 .L44: + 182:Core/Src/ADBMS_LL_Driver.c **** if (VP_CRCTableValue & (((crc)1) << (10 - 1))) { + 1016 .loc 1 182 50 discriminator 2 + 1017 0042 7B7B ldrb r3, [r7, #13] @ zero_extendqisi2 + 1018 0044 0133 adds r3, r3, #1 + 1019 0046 7B73 strb r3, [r7, #13] + 1020 .L42: + 182:Core/Src/ADBMS_LL_Driver.c **** if (VP_CRCTableValue & (((crc)1) << (10 - 1))) { + 1021 .loc 1 182 35 discriminator 1 + 1022 0048 7B7B ldrb r3, [r7, #13] @ zero_extendqisi2 + 1023 004a 072B cmp r3, #7 + 1024 004c E8D9 bls .L45 + 187:Core/Src/ADBMS_LL_Driver.c **** } + 188:Core/Src/ADBMS_LL_Driver.c **** } + 189:Core/Src/ADBMS_LL_Driver.c **** return ((VP_CRCTableValue)); + 1025 .loc 1 189 10 + 1026 004e FB89 ldrh r3, [r7, #14] + 190:Core/Src/ADBMS_LL_Driver.c **** } + 1027 .loc 1 190 1 + 1028 0050 1846 mov r0, r3 + 1029 0052 1437 adds r7, r7, #20 + 1030 .cfi_def_cfa_offset 4 + 1031 0054 BD46 mov sp, r7 + 1032 .cfi_def_cfa_register 13 + 1033 @ sp needed + 1034 0056 5DF8047B ldr r7, [sp], #4 + 1035 .cfi_restore 7 + 1036 .cfi_def_cfa_offset 0 + 1037 005a 7047 bx lr + 1038 .cfi_endproc + 1039 .LFE137: + 1041 .section .text.F_CRC_CalculaCheckSum,"ax",%progbits + 1042 .align 1 + 1043 .global F_CRC_CalculaCheckSum + 1044 .syntax unified + 1045 .thumb + 1046 .thumb_func + 1048 F_CRC_CalculaCheckSum: + 1049 .LFB138: + 191:Core/Src/ADBMS_LL_Driver.c **** crc F_CRC_CalculaCheckSum(uint8_t const AF_Datos[], uint16_t VF_nBytes) { + 1050 .loc 1 191 73 + 1051 .cfi_startproc + 1052 @ args = 0, pretend = 0, frame = 16 + 1053 @ frame_needed = 1, uses_anonymous_args = 0 + 1054 0000 90B5 push {r4, r7, lr} + 1055 .cfi_def_cfa_offset 12 + 1056 .cfi_offset 4, -12 + 1057 .cfi_offset 7, -8 + 1058 .cfi_offset 14, -4 + 1059 0002 85B0 sub sp, sp, #20 + 1060 .cfi_def_cfa_offset 32 + 1061 0004 00AF add r7, sp, #0 + 1062 .cfi_def_cfa_register 7 + 1063 0006 7860 str r0, [r7, #4] + 1064 0008 0B46 mov r3, r1 + ARM GAS /tmp/cczsHaNw.s page 23 + + + 1065 000a 7B80 strh r3, [r7, #2] @ movhi + 192:Core/Src/ADBMS_LL_Driver.c **** crc VP_CRCTableValue = 16; + 1066 .loc 1 192 7 + 1067 000c 1023 movs r3, #16 + 1068 000e FB81 strh r3, [r7, #14] @ movhi + 193:Core/Src/ADBMS_LL_Driver.c **** int16_t VP_bytes = 0; + 1069 .loc 1 193 11 + 1070 0010 0023 movs r3, #0 + 1071 0012 BB81 strh r3, [r7, #12] @ movhi + 194:Core/Src/ADBMS_LL_Driver.c **** + 195:Core/Src/ADBMS_LL_Driver.c **** for (VP_bytes = 0; VP_bytes < VF_nBytes; VP_bytes++) { + 1072 .loc 1 195 17 + 1073 0014 0023 movs r3, #0 + 1074 0016 BB81 strh r3, [r7, #12] @ movhi + 1075 .loc 1 195 3 + 1076 0018 1CE0 b .L48 + 1077 .L49: + 196:Core/Src/ADBMS_LL_Driver.c **** + 197:Core/Src/ADBMS_LL_Driver.c **** VP_CRCTableValue = (VP_CRCTableValue << 8) ^ + 1078 .loc 1 197 48 + 1079 001a B7F90E30 ldrsh r3, [r7, #14] + 1080 001e 1B02 lsls r3, r3, #8 + 1081 0020 1CB2 sxth r4, r3 + 198:Core/Src/ADBMS_LL_Driver.c **** F_CRC_ObtenValorDeTabla( + 199:Core/Src/ADBMS_LL_Driver.c **** ((uint8_t)((VP_CRCTableValue >> (10 - 8)) & 0xFF)) ^ + 1082 .loc 1 199 29 + 1083 0022 FB89 ldrh r3, [r7, #14] + 1084 0024 9B08 lsrs r3, r3, #2 + 1085 0026 9BB2 uxth r3, r3 + 1086 0028 DAB2 uxtb r2, r3 + 200:Core/Src/ADBMS_LL_Driver.c **** AF_Datos[VP_bytes]); + 1087 .loc 1 200 36 + 1088 002a B7F90C30 ldrsh r3, [r7, #12] + 1089 002e 7968 ldr r1, [r7, #4] + 1090 0030 0B44 add r3, r3, r1 + 1091 0032 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 198:Core/Src/ADBMS_LL_Driver.c **** F_CRC_ObtenValorDeTabla( + 1092 .loc 1 198 24 + 1093 0034 5340 eors r3, r3, r2 + 1094 0036 DBB2 uxtb r3, r3 + 1095 0038 1846 mov r0, r3 + 1096 003a FFF7FEFF bl F_CRC_ObtenValorDeTabla + 1097 003e 0346 mov r3, r0 + 198:Core/Src/ADBMS_LL_Driver.c **** F_CRC_ObtenValorDeTabla( + 1098 .loc 1 198 24 is_stmt 0 discriminator 1 + 1099 0040 1BB2 sxth r3, r3 + 197:Core/Src/ADBMS_LL_Driver.c **** F_CRC_ObtenValorDeTabla( + 1100 .loc 1 197 48 is_stmt 1 + 1101 0042 6340 eors r3, r3, r4 + 1102 0044 1BB2 sxth r3, r3 + 197:Core/Src/ADBMS_LL_Driver.c **** F_CRC_ObtenValorDeTabla( + 1103 .loc 1 197 22 + 1104 0046 FB81 strh r3, [r7, #14] @ movhi + 195:Core/Src/ADBMS_LL_Driver.c **** + 1105 .loc 1 195 52 discriminator 3 + 1106 0048 B7F90C30 ldrsh r3, [r7, #12] + 1107 004c 9BB2 uxth r3, r3 + ARM GAS /tmp/cczsHaNw.s page 24 + + + 1108 004e 0133 adds r3, r3, #1 + 1109 0050 9BB2 uxth r3, r3 + 1110 0052 BB81 strh r3, [r7, #12] @ movhi + 1111 .L48: + 195:Core/Src/ADBMS_LL_Driver.c **** + 1112 .loc 1 195 31 discriminator 1 + 1113 0054 B7F90C20 ldrsh r2, [r7, #12] + 1114 0058 7B88 ldrh r3, [r7, #2] + 1115 005a 9A42 cmp r2, r3 + 1116 005c DDDB blt .L49 + 201:Core/Src/ADBMS_LL_Driver.c **** } + 202:Core/Src/ADBMS_LL_Driver.c **** + 203:Core/Src/ADBMS_LL_Driver.c **** if ((8 * sizeof(crc)) > 10) { + 204:Core/Src/ADBMS_LL_Driver.c **** VP_CRCTableValue = VP_CRCTableValue & ((((crc)(1)) << 10) - 1); + 1117 .loc 1 204 22 + 1118 005e FB89 ldrh r3, [r7, #14] @ movhi + 1119 0060 C3F30903 ubfx r3, r3, #0, #10 + 1120 0064 FB81 strh r3, [r7, #14] @ movhi + 205:Core/Src/ADBMS_LL_Driver.c **** } + 206:Core/Src/ADBMS_LL_Driver.c **** + 207:Core/Src/ADBMS_LL_Driver.c **** return (VP_CRCTableValue ^ 0x0000); + 1121 .loc 1 207 28 + 1122 0066 FB89 ldrh r3, [r7, #14] + 208:Core/Src/ADBMS_LL_Driver.c **** } + 1123 .loc 1 208 1 + 1124 0068 1846 mov r0, r3 + 1125 006a 1437 adds r7, r7, #20 + 1126 .cfi_def_cfa_offset 12 + 1127 006c BD46 mov sp, r7 + 1128 .cfi_def_cfa_register 13 + 1129 @ sp needed + 1130 006e 90BD pop {r4, r7, pc} + 1131 .cfi_endproc + 1132 .LFE138: + 1134 .section .text.updateDataPEC,"ax",%progbits + 1135 .align 1 + 1136 .global updateDataPEC + 1137 .syntax unified + 1138 .thumb + 1139 .thumb_func + 1141 updateDataPEC: + 1142 .LFB139: + 209:Core/Src/ADBMS_LL_Driver.c **** + 210:Core/Src/ADBMS_LL_Driver.c **** uint16 updateDataPEC(uint16 currentPEC, uint8 din) { + 1143 .loc 1 210 52 + 1144 .cfi_startproc + 1145 @ args = 0, pretend = 0, frame = 16 + 1146 @ frame_needed = 1, uses_anonymous_args = 0 + 1147 @ link register save eliminated. + 1148 0000 80B4 push {r7} + 1149 .cfi_def_cfa_offset 4 + 1150 .cfi_offset 7, -4 + 1151 0002 85B0 sub sp, sp, #20 + 1152 .cfi_def_cfa_offset 24 + 1153 0004 00AF add r7, sp, #0 + 1154 .cfi_def_cfa_register 7 + 1155 0006 0346 mov r3, r0 + ARM GAS /tmp/cczsHaNw.s page 25 + + + 1156 0008 0A46 mov r2, r1 + 1157 000a FB80 strh r3, [r7, #6] @ movhi + 1158 000c 1346 mov r3, r2 + 1159 000e 7B71 strb r3, [r7, #5] + 211:Core/Src/ADBMS_LL_Driver.c **** din = (din >> 7) & 0x01; + 1160 .loc 1 211 7 + 1161 0010 7B79 ldrb r3, [r7, #5] @ zero_extendqisi2 + 1162 0012 DB09 lsrs r3, r3, #7 + 1163 0014 7B71 strb r3, [r7, #5] + 212:Core/Src/ADBMS_LL_Driver.c **** const uint8 in0 = din ^ ((currentPEC >> 9) & 0x01); + 1164 .loc 1 212 46 + 1165 0016 FB88 ldrh r3, [r7, #6] + 1166 0018 5B0A lsrs r3, r3, #9 + 1167 001a 9BB2 uxth r3, r3 + 1168 001c 5BB2 sxtb r3, r3 + 1169 001e 03F00103 and r3, r3, #1 + 1170 0022 5AB2 sxtb r2, r3 + 1171 .loc 1 212 25 + 1172 0024 97F90530 ldrsb r3, [r7, #5] + 1173 0028 5340 eors r3, r3, r2 + 1174 002a 5BB2 sxtb r3, r3 + 1175 .loc 1 212 15 + 1176 002c FB73 strb r3, [r7, #15] + 213:Core/Src/ADBMS_LL_Driver.c **** const uint8 in2 = in0 ^ ((currentPEC >> 1) & 0x01); + 1177 .loc 1 213 46 + 1178 002e FB88 ldrh r3, [r7, #6] + 1179 0030 5B08 lsrs r3, r3, #1 + 1180 0032 9BB2 uxth r3, r3 + 1181 0034 5BB2 sxtb r3, r3 + 1182 0036 03F00103 and r3, r3, #1 + 1183 003a 5AB2 sxtb r2, r3 + 1184 .loc 1 213 25 + 1185 003c 97F90F30 ldrsb r3, [r7, #15] + 1186 0040 5340 eors r3, r3, r2 + 1187 0042 5BB2 sxtb r3, r3 + 1188 .loc 1 213 15 + 1189 0044 BB73 strb r3, [r7, #14] + 214:Core/Src/ADBMS_LL_Driver.c **** const uint8 in3 = in0 ^ ((currentPEC >> 2) & 0x01); + 1190 .loc 1 214 46 + 1191 0046 FB88 ldrh r3, [r7, #6] + 1192 0048 9B08 lsrs r3, r3, #2 + 1193 004a 9BB2 uxth r3, r3 + 1194 004c 5BB2 sxtb r3, r3 + 1195 004e 03F00103 and r3, r3, #1 + 1196 0052 5AB2 sxtb r2, r3 + 1197 .loc 1 214 25 + 1198 0054 97F90F30 ldrsb r3, [r7, #15] + 1199 0058 5340 eors r3, r3, r2 + 1200 005a 5BB2 sxtb r3, r3 + 1201 .loc 1 214 15 + 1202 005c 7B73 strb r3, [r7, #13] + 215:Core/Src/ADBMS_LL_Driver.c **** const uint8 in7 = in0 ^ ((currentPEC >> 6) & 0x01); + 1203 .loc 1 215 46 + 1204 005e FB88 ldrh r3, [r7, #6] + 1205 0060 9B09 lsrs r3, r3, #6 + 1206 0062 9BB2 uxth r3, r3 + 1207 0064 5BB2 sxtb r3, r3 + ARM GAS /tmp/cczsHaNw.s page 26 + + + 1208 0066 03F00103 and r3, r3, #1 + 1209 006a 5AB2 sxtb r2, r3 + 1210 .loc 1 215 25 + 1211 006c 97F90F30 ldrsb r3, [r7, #15] + 1212 0070 5340 eors r3, r3, r2 + 1213 0072 5BB2 sxtb r3, r3 + 1214 .loc 1 215 15 + 1215 0074 3B73 strb r3, [r7, #12] + 216:Core/Src/ADBMS_LL_Driver.c **** + 217:Core/Src/ADBMS_LL_Driver.c **** uint16 newPEC = 0; + 1216 .loc 1 217 10 + 1217 0076 0023 movs r3, #0 + 1218 0078 7B81 strh r3, [r7, #10] @ movhi + 218:Core/Src/ADBMS_LL_Driver.c **** + 219:Core/Src/ADBMS_LL_Driver.c **** newPEC |= (currentPEC & (0x01 << 8)) << 1; + 1219 .loc 1 219 40 + 1220 007a B7F90630 ldrsh r3, [r7, #6] + 1221 007e 5B00 lsls r3, r3, #1 + 1222 0080 1BB2 sxth r3, r3 + 1223 0082 03F40073 and r3, r3, #512 + 1224 0086 1AB2 sxth r2, r3 + 1225 .loc 1 219 10 + 1226 0088 B7F90A30 ldrsh r3, [r7, #10] + 1227 008c 1343 orrs r3, r3, r2 + 1228 008e 1BB2 sxth r3, r3 + 1229 0090 7B81 strh r3, [r7, #10] @ movhi + 220:Core/Src/ADBMS_LL_Driver.c **** newPEC |= (currentPEC & (0x01 << 7)) << 1; + 1230 .loc 1 220 40 + 1231 0092 B7F90630 ldrsh r3, [r7, #6] + 1232 0096 5B00 lsls r3, r3, #1 + 1233 0098 1BB2 sxth r3, r3 + 1234 009a 03F48073 and r3, r3, #256 + 1235 009e 1AB2 sxth r2, r3 + 1236 .loc 1 220 10 + 1237 00a0 B7F90A30 ldrsh r3, [r7, #10] + 1238 00a4 1343 orrs r3, r3, r2 + 1239 00a6 1BB2 sxth r3, r3 + 1240 00a8 7B81 strh r3, [r7, #10] @ movhi + 221:Core/Src/ADBMS_LL_Driver.c **** newPEC |= in7 << 7; + 1241 .loc 1 221 10 + 1242 00aa 3B7B ldrb r3, [r7, #12] @ zero_extendqisi2 + 1243 00ac 1BB2 sxth r3, r3 + 1244 00ae DB01 lsls r3, r3, #7 + 1245 00b0 1AB2 sxth r2, r3 + 1246 00b2 B7F90A30 ldrsh r3, [r7, #10] + 1247 00b6 1343 orrs r3, r3, r2 + 1248 00b8 1BB2 sxth r3, r3 + 1249 00ba 7B81 strh r3, [r7, #10] @ movhi + 222:Core/Src/ADBMS_LL_Driver.c **** newPEC |= (currentPEC & (0x01 << 5)) << 1; + 1250 .loc 1 222 40 + 1251 00bc B7F90630 ldrsh r3, [r7, #6] + 1252 00c0 5B00 lsls r3, r3, #1 + 1253 00c2 1BB2 sxth r3, r3 + 1254 00c4 03F04003 and r3, r3, #64 + 1255 00c8 1AB2 sxth r2, r3 + 1256 .loc 1 222 10 + 1257 00ca B7F90A30 ldrsh r3, [r7, #10] + ARM GAS /tmp/cczsHaNw.s page 27 + + + 1258 00ce 1343 orrs r3, r3, r2 + 1259 00d0 1BB2 sxth r3, r3 + 1260 00d2 7B81 strh r3, [r7, #10] @ movhi + 223:Core/Src/ADBMS_LL_Driver.c **** newPEC |= (currentPEC & (0x01 << 4)) << 1; + 1261 .loc 1 223 40 + 1262 00d4 B7F90630 ldrsh r3, [r7, #6] + 1263 00d8 5B00 lsls r3, r3, #1 + 1264 00da 1BB2 sxth r3, r3 + 1265 00dc 03F02003 and r3, r3, #32 + 1266 00e0 1AB2 sxth r2, r3 + 1267 .loc 1 223 10 + 1268 00e2 B7F90A30 ldrsh r3, [r7, #10] + 1269 00e6 1343 orrs r3, r3, r2 + 1270 00e8 1BB2 sxth r3, r3 + 1271 00ea 7B81 strh r3, [r7, #10] @ movhi + 224:Core/Src/ADBMS_LL_Driver.c **** newPEC |= in3 << 3; + 1272 .loc 1 224 10 + 1273 00ec 7B7B ldrb r3, [r7, #13] @ zero_extendqisi2 + 1274 00ee 1BB2 sxth r3, r3 + 1275 00f0 DB00 lsls r3, r3, #3 + 1276 00f2 1AB2 sxth r2, r3 + 1277 00f4 B7F90A30 ldrsh r3, [r7, #10] + 1278 00f8 1343 orrs r3, r3, r2 + 1279 00fa 1BB2 sxth r3, r3 + 1280 00fc 7B81 strh r3, [r7, #10] @ movhi + 225:Core/Src/ADBMS_LL_Driver.c **** newPEC |= in2 << 2; + 1281 .loc 1 225 10 + 1282 00fe BB7B ldrb r3, [r7, #14] @ zero_extendqisi2 + 1283 0100 1BB2 sxth r3, r3 + 1284 0102 9B00 lsls r3, r3, #2 + 1285 0104 1AB2 sxth r2, r3 + 1286 0106 B7F90A30 ldrsh r3, [r7, #10] + 1287 010a 1343 orrs r3, r3, r2 + 1288 010c 1BB2 sxth r3, r3 + 1289 010e 7B81 strh r3, [r7, #10] @ movhi + 226:Core/Src/ADBMS_LL_Driver.c **** newPEC |= (currentPEC & (0x01)) << 1; + 1290 .loc 1 226 35 + 1291 0110 B7F90630 ldrsh r3, [r7, #6] + 1292 0114 5B00 lsls r3, r3, #1 + 1293 0116 1BB2 sxth r3, r3 + 1294 0118 03F00203 and r3, r3, #2 + 1295 011c 1AB2 sxth r2, r3 + 1296 .loc 1 226 10 + 1297 011e B7F90A30 ldrsh r3, [r7, #10] + 1298 0122 1343 orrs r3, r3, r2 + 1299 0124 1BB2 sxth r3, r3 + 1300 0126 7B81 strh r3, [r7, #10] @ movhi + 227:Core/Src/ADBMS_LL_Driver.c **** newPEC |= in0; + 1301 .loc 1 227 10 + 1302 0128 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 1303 012a 9AB2 uxth r2, r3 + 1304 012c 7B89 ldrh r3, [r7, #10] @ movhi + 1305 012e 1343 orrs r3, r3, r2 + 1306 0130 7B81 strh r3, [r7, #10] @ movhi + 228:Core/Src/ADBMS_LL_Driver.c **** + 229:Core/Src/ADBMS_LL_Driver.c **** return newPEC; + 1307 .loc 1 229 10 + ARM GAS /tmp/cczsHaNw.s page 28 + + + 1308 0132 7B89 ldrh r3, [r7, #10] + 230:Core/Src/ADBMS_LL_Driver.c **** } + 1309 .loc 1 230 1 + 1310 0134 1846 mov r0, r3 + 1311 0136 1437 adds r7, r7, #20 + 1312 .cfi_def_cfa_offset 4 + 1313 0138 BD46 mov sp, r7 + 1314 .cfi_def_cfa_register 13 + 1315 @ sp needed + 1316 013a 5DF8047B ldr r7, [sp], #4 + 1317 .cfi_restore 7 + 1318 .cfi_def_cfa_offset 0 + 1319 013e 7047 bx lr + 1320 .cfi_endproc + 1321 .LFE139: + 1323 .section .text.writeCMD,"ax",%progbits + 1324 .align 1 + 1325 .global writeCMD + 1326 .syntax unified + 1327 .thumb + 1328 .thumb_func + 1330 writeCMD: + 1331 .LFB140: + 231:Core/Src/ADBMS_LL_Driver.c **** + 232:Core/Src/ADBMS_LL_Driver.c **** uint8 writeCMD(uint16 command, const uint8 * args, uint8 arglen) { + 1332 .loc 1 232 66 + 1333 .cfi_startproc + 1334 @ args = 0, pretend = 0, frame = 24 + 1335 @ frame_needed = 1, uses_anonymous_args = 0 + 1336 0000 2DE9F043 push {r4, r5, r6, r7, r8, r9, lr} + 1337 .cfi_def_cfa_offset 28 + 1338 .cfi_offset 4, -28 + 1339 .cfi_offset 5, -24 + 1340 .cfi_offset 6, -20 + 1341 .cfi_offset 7, -16 + 1342 .cfi_offset 8, -12 + 1343 .cfi_offset 9, -8 + 1344 .cfi_offset 14, -4 + 1345 0004 87B0 sub sp, sp, #28 + 1346 .cfi_def_cfa_offset 56 + 1347 0006 00AF add r7, sp, #0 + 1348 .cfi_def_cfa_register 7 + 1349 0008 0346 mov r3, r0 + 1350 000a 3960 str r1, [r7] + 1351 000c FB80 strh r3, [r7, #6] @ movhi + 1352 000e 1346 mov r3, r2 + 1353 0010 7B71 strb r3, [r7, #5] + 233:Core/Src/ADBMS_LL_Driver.c **** uint8 ret; + 234:Core/Src/ADBMS_LL_Driver.c **** if (arglen > 0) { + 1354 .loc 1 234 6 + 1355 0012 7B79 ldrb r3, [r7, #5] @ zero_extendqisi2 + 1356 0014 002B cmp r3, #0 + 1357 0016 60D0 beq .L54 + 1358 .LBB12: + 1359 .loc 1 234 19 discriminator 1 + 1360 0018 6B46 mov r3, sp + 1361 001a 1E46 mov r6, r3 + ARM GAS /tmp/cczsHaNw.s page 29 + + + 235:Core/Src/ADBMS_LL_Driver.c **** uint8 buffer[6 + arglen]; //command + PEC (2 bytes) + data + DPEC (2 bytes) + 1362 .loc 1 235 20 + 1363 001c 7B79 ldrb r3, [r7, #5] @ zero_extendqisi2 + 1364 001e 991D adds r1, r3, #6 + 1365 .loc 1 235 11 + 1366 0020 4B1E subs r3, r1, #1 + 1367 0022 3B61 str r3, [r7, #16] + 1368 0024 0A46 mov r2, r1 + 1369 0026 0023 movs r3, #0 + 1370 0028 9046 mov r8, r2 + 1371 002a 9946 mov r9, r3 + 1372 002c 4FF00002 mov r2, #0 + 1373 0030 4FF00003 mov r3, #0 + 1374 0034 4FEAC903 lsl r3, r9, #3 + 1375 0038 43EA5873 orr r3, r3, r8, lsr #29 + 1376 003c 4FEAC802 lsl r2, r8, #3 + 1377 0040 0A46 mov r2, r1 + 1378 0042 0023 movs r3, #0 + 1379 0044 1446 mov r4, r2 + 1380 0046 1D46 mov r5, r3 + 1381 0048 4FF00002 mov r2, #0 + 1382 004c 4FF00003 mov r3, #0 + 1383 0050 EB00 lsls r3, r5, #3 + 1384 0052 43EA5473 orr r3, r3, r4, lsr #29 + 1385 0056 E200 lsls r2, r4, #3 + 1386 0058 0B46 mov r3, r1 + 1387 005a 0733 adds r3, r3, #7 + 1388 005c DB08 lsrs r3, r3, #3 + 1389 005e DB00 lsls r3, r3, #3 + 1390 0060 ADEB030D sub sp, sp, r3 + 1391 0064 6B46 mov r3, sp + 1392 0066 0033 adds r3, r3, #0 + 1393 0068 FB60 str r3, [r7, #12] + 236:Core/Src/ADBMS_LL_Driver.c **** buffer[0] = (command >> 8) & 0xFF; + 1394 .loc 1 236 15 + 1395 006a FB88 ldrh r3, [r7, #6] + 1396 006c 1B0A lsrs r3, r3, #8 + 1397 006e 9BB2 uxth r3, r3 + 1398 0070 DAB2 uxtb r2, r3 + 1399 0072 FB68 ldr r3, [r7, #12] + 1400 0074 1A70 strb r2, [r3] + 237:Core/Src/ADBMS_LL_Driver.c **** buffer[1] = (command) & 0xFF; + 1401 .loc 1 237 15 + 1402 0076 FB88 ldrh r3, [r7, #6] @ movhi + 1403 0078 DAB2 uxtb r2, r3 + 1404 007a FB68 ldr r3, [r7, #12] + 1405 007c 5A70 strb r2, [r3, #1] + 238:Core/Src/ADBMS_LL_Driver.c **** + 239:Core/Src/ADBMS_LL_Driver.c **** calculateCommandPEC(buffer, 4); + 1406 .loc 1 239 5 + 1407 007e 0421 movs r1, #4 + 1408 0080 F868 ldr r0, [r7, #12] + 1409 0082 FFF7FEFF bl calculateCommandPEC + 1410 .LBB13: + 240:Core/Src/ADBMS_LL_Driver.c **** + 241:Core/Src/ADBMS_LL_Driver.c **** for (uint8 i = 0; i < arglen; i++) { + 1411 .loc 1 241 16 + ARM GAS /tmp/cczsHaNw.s page 30 + + + 1412 0086 0023 movs r3, #0 + 1413 0088 BB75 strb r3, [r7, #22] + 1414 .loc 1 241 5 + 1415 008a 0AE0 b .L55 + 1416 .L56: + 242:Core/Src/ADBMS_LL_Driver.c **** buffer[4 + i] = args[i]; + 1417 .loc 1 242 27 + 1418 008c BB7D ldrb r3, [r7, #22] @ zero_extendqisi2 + 1419 008e 3A68 ldr r2, [r7] + 1420 0090 1A44 add r2, r2, r3 + 1421 .loc 1 242 16 + 1422 0092 BB7D ldrb r3, [r7, #22] @ zero_extendqisi2 + 1423 0094 0433 adds r3, r3, #4 + 1424 .loc 1 242 27 + 1425 0096 1178 ldrb r1, [r2] @ zero_extendqisi2 + 1426 .loc 1 242 21 + 1427 0098 FA68 ldr r2, [r7, #12] + 1428 009a D154 strb r1, [r2, r3] + 241:Core/Src/ADBMS_LL_Driver.c **** buffer[4 + i] = args[i]; + 1429 .loc 1 241 36 discriminator 3 + 1430 009c BB7D ldrb r3, [r7, #22] @ zero_extendqisi2 + 1431 009e 0133 adds r3, r3, #1 + 1432 00a0 BB75 strb r3, [r7, #22] + 1433 .L55: + 241:Core/Src/ADBMS_LL_Driver.c **** buffer[4 + i] = args[i]; + 1434 .loc 1 241 25 discriminator 1 + 1435 00a2 BA7D ldrb r2, [r7, #22] @ zero_extendqisi2 + 1436 00a4 7B79 ldrb r3, [r7, #5] @ zero_extendqisi2 + 1437 00a6 9A42 cmp r2, r3 + 1438 00a8 F0D3 bcc .L56 + 1439 .LBE13: + 243:Core/Src/ADBMS_LL_Driver.c **** } + 244:Core/Src/ADBMS_LL_Driver.c **** + 245:Core/Src/ADBMS_LL_Driver.c **** calculateDataPEC(&buffer[4], arglen + 2); //DPEC is calculated over the data, not the command, + 1440 .loc 1 245 5 + 1441 00aa FB68 ldr r3, [r7, #12] + 1442 00ac 1A1D adds r2, r3, #4 + 1443 00ae 7B79 ldrb r3, [r7, #5] + 1444 00b0 0233 adds r3, r3, #2 + 1445 00b2 DBB2 uxtb r3, r3 + 1446 00b4 1946 mov r1, r3 + 1447 00b6 1046 mov r0, r2 + 1448 00b8 FFF7FEFF bl calculateDataPEC + 246:Core/Src/ADBMS_LL_Driver.c **** + 247:Core/Src/ADBMS_LL_Driver.c **** mcuAdbmsCSLow(); + 1449 .loc 1 247 5 + 1450 00bc FFF7FEFF bl mcuAdbmsCSLow + 248:Core/Src/ADBMS_LL_Driver.c **** ret = mcuSPITransmit(buffer, 6 + arglen); + 1451 .loc 1 248 11 + 1452 00c0 7B79 ldrb r3, [r7, #5] + 1453 00c2 0633 adds r3, r3, #6 + 1454 00c4 DBB2 uxtb r3, r3 + 1455 00c6 1946 mov r1, r3 + 1456 00c8 F868 ldr r0, [r7, #12] + 1457 00ca FFF7FEFF bl mcuSPITransmit + 1458 00ce 0346 mov r3, r0 + 1459 00d0 FB75 strb r3, [r7, #23] + ARM GAS /tmp/cczsHaNw.s page 31 + + + 249:Core/Src/ADBMS_LL_Driver.c **** mcuAdbmsCSHigh(); + 1460 .loc 1 249 5 + 1461 00d2 FFF7FEFF bl mcuAdbmsCSHigh + 1462 00d6 B546 mov sp, r6 + 1463 .LBE12: + 1464 00d8 19E0 b .L57 + 1465 .L54: + 1466 .LBB14: + 250:Core/Src/ADBMS_LL_Driver.c **** } else { + 251:Core/Src/ADBMS_LL_Driver.c **** uint8 buffer[4]; + 252:Core/Src/ADBMS_LL_Driver.c **** buffer[0] = (command >> 8) & 0xFF; + 1467 .loc 1 252 15 + 1468 00da FB88 ldrh r3, [r7, #6] + 1469 00dc 1B0A lsrs r3, r3, #8 + 1470 00de 9BB2 uxth r3, r3 + 1471 00e0 DBB2 uxtb r3, r3 + 1472 00e2 3B72 strb r3, [r7, #8] + 253:Core/Src/ADBMS_LL_Driver.c **** buffer[1] = (command) & 0xFF; + 1473 .loc 1 253 15 + 1474 00e4 FB88 ldrh r3, [r7, #6] @ movhi + 1475 00e6 DBB2 uxtb r3, r3 + 1476 00e8 7B72 strb r3, [r7, #9] + 254:Core/Src/ADBMS_LL_Driver.c **** calculateCommandPEC(buffer, 4); + 1477 .loc 1 254 5 + 1478 00ea 07F10803 add r3, r7, #8 + 1479 00ee 0421 movs r1, #4 + 1480 00f0 1846 mov r0, r3 + 1481 00f2 FFF7FEFF bl calculateCommandPEC + 255:Core/Src/ADBMS_LL_Driver.c **** + 256:Core/Src/ADBMS_LL_Driver.c **** mcuAdbmsCSLow(); + 1482 .loc 1 256 5 + 1483 00f6 FFF7FEFF bl mcuAdbmsCSLow + 257:Core/Src/ADBMS_LL_Driver.c **** + 258:Core/Src/ADBMS_LL_Driver.c **** ret = mcuSPITransmit(buffer, 4); + 1484 .loc 1 258 11 + 1485 00fa 07F10803 add r3, r7, #8 + 1486 00fe 0421 movs r1, #4 + 1487 0100 1846 mov r0, r3 + 1488 0102 FFF7FEFF bl mcuSPITransmit + 1489 0106 0346 mov r3, r0 + 1490 0108 FB75 strb r3, [r7, #23] + 259:Core/Src/ADBMS_LL_Driver.c **** + 260:Core/Src/ADBMS_LL_Driver.c **** mcuAdbmsCSHigh(); + 1491 .loc 1 260 5 + 1492 010a FFF7FEFF bl mcuAdbmsCSHigh + 1493 .L57: + 1494 .LBE14: + 261:Core/Src/ADBMS_LL_Driver.c **** } + 262:Core/Src/ADBMS_LL_Driver.c **** + 263:Core/Src/ADBMS_LL_Driver.c **** return ret; + 1495 .loc 1 263 10 + 1496 010e FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 264:Core/Src/ADBMS_LL_Driver.c **** } + 1497 .loc 1 264 1 + 1498 0110 1846 mov r0, r3 + 1499 0112 1C37 adds r7, r7, #28 + 1500 .cfi_def_cfa_offset 28 + ARM GAS /tmp/cczsHaNw.s page 32 + + + 1501 0114 BD46 mov sp, r7 + 1502 .cfi_def_cfa_register 13 + 1503 @ sp needed + 1504 0116 BDE8F083 pop {r4, r5, r6, r7, r8, r9, pc} + 1505 .cfi_endproc + 1506 .LFE140: + 1508 .section .text.readCMD,"ax",%progbits + 1509 .align 1 + 1510 .global readCMD + 1511 .syntax unified + 1512 .thumb + 1513 .thumb_func + 1515 readCMD: + 1516 .LFB141: + 265:Core/Src/ADBMS_LL_Driver.c **** + 266:Core/Src/ADBMS_LL_Driver.c **** uint8 readCMD(uint16 command, uint8 * buffer, uint8 buflen) { + 1517 .loc 1 266 61 + 1518 .cfi_startproc + 1519 @ args = 0, pretend = 0, frame = 48 + 1520 @ frame_needed = 1, uses_anonymous_args = 0 + 1521 0000 2DE9F04F push {r4, r5, r6, r7, r8, r9, r10, fp, lr} + 1522 .cfi_def_cfa_offset 36 + 1523 .cfi_offset 4, -36 + 1524 .cfi_offset 5, -32 + 1525 .cfi_offset 6, -28 + 1526 .cfi_offset 7, -24 + 1527 .cfi_offset 8, -20 + 1528 .cfi_offset 9, -16 + 1529 .cfi_offset 10, -12 + 1530 .cfi_offset 11, -8 + 1531 .cfi_offset 14, -4 + 1532 0004 8DB0 sub sp, sp, #52 + 1533 .cfi_def_cfa_offset 88 + 1534 0006 00AF add r7, sp, #0 + 1535 .cfi_def_cfa_register 7 + 1536 0008 0346 mov r3, r0 + 1537 000a 3961 str r1, [r7, #16] + 1538 000c FB82 strh r3, [r7, #22] @ movhi + 1539 000e 1346 mov r3, r2 + 1540 0010 7B75 strb r3, [r7, #21] + 1541 .loc 1 266 61 + 1542 0012 6B46 mov r3, sp + 1543 0014 7B60 str r3, [r7, #4] + 267:Core/Src/ADBMS_LL_Driver.c **** uint8 txbuffer[6 + buflen]; + 1544 .loc 1 267 20 + 1545 0016 7B7D ldrb r3, [r7, #21] @ zero_extendqisi2 + 1546 0018 991D adds r1, r3, #6 + 1547 .loc 1 267 9 + 1548 001a 4B1E subs r3, r1, #1 + 1549 001c BB62 str r3, [r7, #40] + 1550 001e 0A46 mov r2, r1 + 1551 0020 0023 movs r3, #0 + 1552 0022 BA60 str r2, [r7, #8] + 1553 0024 FB60 str r3, [r7, #12] + 1554 0026 4FF00002 mov r2, #0 + 1555 002a 4FF00003 mov r3, #0 + 1556 002e F868 ldr r0, [r7, #12] + ARM GAS /tmp/cczsHaNw.s page 33 + + + 1557 0030 C300 lsls r3, r0, #3 + 1558 0032 B868 ldr r0, [r7, #8] + 1559 0034 43EA5073 orr r3, r3, r0, lsr #29 + 1560 0038 B868 ldr r0, [r7, #8] + 1561 003a C200 lsls r2, r0, #3 + 1562 003c 0A46 mov r2, r1 + 1563 003e 0023 movs r3, #0 + 1564 0040 9246 mov r10, r2 + 1565 0042 9B46 mov fp, r3 + 1566 0044 4FF00002 mov r2, #0 + 1567 0048 4FF00003 mov r3, #0 + 1568 004c 4FEACB03 lsl r3, fp, #3 + 1569 0050 43EA5A73 orr r3, r3, r10, lsr #29 + 1570 0054 4FEACA02 lsl r2, r10, #3 + 1571 0058 0B46 mov r3, r1 + 1572 005a 0733 adds r3, r3, #7 + 1573 005c DB08 lsrs r3, r3, #3 + 1574 005e DB00 lsls r3, r3, #3 + 1575 0060 ADEB030D sub sp, sp, r3 + 1576 0064 6B46 mov r3, sp + 1577 0066 0033 adds r3, r3, #0 + 1578 0068 7B62 str r3, [r7, #36] + 268:Core/Src/ADBMS_LL_Driver.c **** uint8 rxbuffer[6 + buflen]; + 1579 .loc 1 268 20 + 1580 006a 7B7D ldrb r3, [r7, #21] @ zero_extendqisi2 + 1581 006c 9E1D adds r6, r3, #6 + 1582 .loc 1 268 9 + 1583 006e 731E subs r3, r6, #1 + 1584 0070 3B62 str r3, [r7, #32] + 1585 0072 3246 mov r2, r6 + 1586 0074 0023 movs r3, #0 + 1587 0076 9046 mov r8, r2 + 1588 0078 9946 mov r9, r3 + 1589 007a 4FF00002 mov r2, #0 + 1590 007e 4FF00003 mov r3, #0 + 1591 0082 4FEAC903 lsl r3, r9, #3 + 1592 0086 43EA5873 orr r3, r3, r8, lsr #29 + 1593 008a 4FEAC802 lsl r2, r8, #3 + 1594 008e 3246 mov r2, r6 + 1595 0090 0023 movs r3, #0 + 1596 0092 1446 mov r4, r2 + 1597 0094 1D46 mov r5, r3 + 1598 0096 4FF00002 mov r2, #0 + 1599 009a 4FF00003 mov r3, #0 + 1600 009e EB00 lsls r3, r5, #3 + 1601 00a0 43EA5473 orr r3, r3, r4, lsr #29 + 1602 00a4 E200 lsls r2, r4, #3 + 1603 00a6 3346 mov r3, r6 + 1604 00a8 0733 adds r3, r3, #7 + 1605 00aa DB08 lsrs r3, r3, #3 + 1606 00ac DB00 lsls r3, r3, #3 + 1607 00ae ADEB030D sub sp, sp, r3 + 1608 00b2 6B46 mov r3, sp + 1609 00b4 0033 adds r3, r3, #0 + 1610 00b6 FB61 str r3, [r7, #28] + 269:Core/Src/ADBMS_LL_Driver.c **** + 270:Core/Src/ADBMS_LL_Driver.c **** txbuffer[0] = (command >> 8) & 0xFF; + ARM GAS /tmp/cczsHaNw.s page 34 + + + 1611 .loc 1 270 15 + 1612 00b8 FB8A ldrh r3, [r7, #22] + 1613 00ba 1B0A lsrs r3, r3, #8 + 1614 00bc 9BB2 uxth r3, r3 + 1615 00be DAB2 uxtb r2, r3 + 1616 00c0 7B6A ldr r3, [r7, #36] + 1617 00c2 1A70 strb r2, [r3] + 271:Core/Src/ADBMS_LL_Driver.c **** txbuffer[1] = (command)&0xFF; + 1618 .loc 1 271 15 + 1619 00c4 FB8A ldrh r3, [r7, #22] @ movhi + 1620 00c6 DAB2 uxtb r2, r3 + 1621 00c8 7B6A ldr r3, [r7, #36] + 1622 00ca 5A70 strb r2, [r3, #1] + 272:Core/Src/ADBMS_LL_Driver.c **** calculateCommandPEC(txbuffer, 4); + 1623 .loc 1 272 3 + 1624 00cc 0421 movs r1, #4 + 1625 00ce 786A ldr r0, [r7, #36] + 1626 00d0 FFF7FEFF bl calculateCommandPEC + 273:Core/Src/ADBMS_LL_Driver.c **** + 274:Core/Src/ADBMS_LL_Driver.c **** mcuAdbmsCSLow(); + 1627 .loc 1 274 3 + 1628 00d4 FFF7FEFF bl mcuAdbmsCSLow + 275:Core/Src/ADBMS_LL_Driver.c **** uint8 status = mcuSPITransmitReceive(rxbuffer, txbuffer, 6 + buflen); + 1629 .loc 1 275 18 + 1630 00d8 7B7D ldrb r3, [r7, #21] + 1631 00da 0633 adds r3, r3, #6 + 1632 00dc DBB2 uxtb r3, r3 + 1633 00de 1A46 mov r2, r3 + 1634 00e0 796A ldr r1, [r7, #36] + 1635 00e2 F869 ldr r0, [r7, #28] + 1636 00e4 FFF7FEFF bl mcuSPITransmitReceive + 1637 00e8 0346 mov r3, r0 + 1638 00ea FB76 strb r3, [r7, #27] + 276:Core/Src/ADBMS_LL_Driver.c **** mcuAdbmsCSHigh(); + 1639 .loc 1 276 3 + 1640 00ec FFF7FEFF bl mcuAdbmsCSHigh + 277:Core/Src/ADBMS_LL_Driver.c **** + 278:Core/Src/ADBMS_LL_Driver.c **** if (status != 0) { + 1641 .loc 1 278 6 + 1642 00f0 FB7E ldrb r3, [r7, #27] @ zero_extendqisi2 + 1643 00f2 002B cmp r3, #0 + 1644 00f4 01D0 beq .L60 + 279:Core/Src/ADBMS_LL_Driver.c **** return status; + 1645 .loc 1 279 12 + 1646 00f6 FB7E ldrb r3, [r7, #27] @ zero_extendqisi2 + 1647 00f8 28E0 b .L61 + 1648 .L60: + 1649 .LBB15: + 280:Core/Src/ADBMS_LL_Driver.c **** } + 281:Core/Src/ADBMS_LL_Driver.c **** + 282:Core/Src/ADBMS_LL_Driver.c **** for (uint8 i = 0; i < buflen; i++) { + 1650 .loc 1 282 14 + 1651 00fa 0023 movs r3, #0 + 1652 00fc 87F82F30 strb r3, [r7, #47] + 1653 .loc 1 282 3 + 1654 0100 0EE0 b .L62 + 1655 .L63: + ARM GAS /tmp/cczsHaNw.s page 35 + + + 283:Core/Src/ADBMS_LL_Driver.c **** buffer[i] = rxbuffer[i + 4]; + 1656 .loc 1 283 28 + 1657 0102 97F82F30 ldrb r3, [r7, #47] @ zero_extendqisi2 + 1658 0106 1A1D adds r2, r3, #4 + 1659 .loc 1 283 11 + 1660 0108 97F82F30 ldrb r3, [r7, #47] @ zero_extendqisi2 + 1661 010c 3969 ldr r1, [r7, #16] + 1662 010e 0B44 add r3, r3, r1 + 1663 .loc 1 283 25 + 1664 0110 F969 ldr r1, [r7, #28] + 1665 0112 8A5C ldrb r2, [r1, r2] @ zero_extendqisi2 + 1666 .loc 1 283 15 + 1667 0114 1A70 strb r2, [r3] + 282:Core/Src/ADBMS_LL_Driver.c **** buffer[i] = rxbuffer[i + 4]; + 1668 .loc 1 282 34 discriminator 3 + 1669 0116 97F82F30 ldrb r3, [r7, #47] @ zero_extendqisi2 + 1670 011a 0133 adds r3, r3, #1 + 1671 011c 87F82F30 strb r3, [r7, #47] + 1672 .L62: + 282:Core/Src/ADBMS_LL_Driver.c **** buffer[i] = rxbuffer[i + 4]; + 1673 .loc 1 282 23 discriminator 1 + 1674 0120 97F82F20 ldrb r2, [r7, #47] @ zero_extendqisi2 + 1675 0124 7B7D ldrb r3, [r7, #21] @ zero_extendqisi2 + 1676 0126 9A42 cmp r2, r3 + 1677 0128 EBD3 bcc .L63 + 1678 .LBE15: + 284:Core/Src/ADBMS_LL_Driver.c **** } + 285:Core/Src/ADBMS_LL_Driver.c **** + 286:Core/Src/ADBMS_LL_Driver.c **** [[maybe_unused]] uint8 commandCounter = rxbuffer[sizeof(rxbuffer) - 2] & 0xFC; //command counter + 1679 .loc 1 286 58 + 1680 012a 3346 mov r3, r6 + 1681 .loc 1 286 69 + 1682 012c 023B subs r3, r3, #2 + 1683 .loc 1 286 51 + 1684 012e FA69 ldr r2, [r7, #28] + 1685 0130 D35C ldrb r3, [r2, r3] @ zero_extendqisi2 + 1686 .loc 1 286 26 + 1687 0132 23F00303 bic r3, r3, #3 + 1688 0136 BB76 strb r3, [r7, #26] + 287:Core/Src/ADBMS_LL_Driver.c **** //TODO: check comm + 288:Core/Src/ADBMS_LL_Driver.c **** + 289:Core/Src/ADBMS_LL_Driver.c **** return checkDataPEC(&rxbuffer[4], buflen + 2); + 1689 .loc 1 289 10 + 1690 0138 FB69 ldr r3, [r7, #28] + 1691 013a 1A1D adds r2, r3, #4 + 1692 013c 7B7D ldrb r3, [r7, #21] + 1693 013e 0233 adds r3, r3, #2 + 1694 0140 DBB2 uxtb r3, r3 + 1695 0142 1946 mov r1, r3 + 1696 0144 1046 mov r0, r2 + 1697 0146 FFF7FEFF bl checkDataPEC + 1698 014a 0346 mov r3, r0 + 1699 .L61: + 1700 014c D7F804D0 ldr sp, [r7, #4] + 290:Core/Src/ADBMS_LL_Driver.c **** } + 1701 .loc 1 290 1 + 1702 0150 1846 mov r0, r3 + ARM GAS /tmp/cczsHaNw.s page 36 + + + 1703 0152 3437 adds r7, r7, #52 + 1704 .cfi_def_cfa_offset 36 + 1705 0154 BD46 mov sp, r7 + 1706 .cfi_def_cfa_register 13 + 1707 @ sp needed + 1708 0156 BDE8F08F pop {r4, r5, r6, r7, r8, r9, r10, fp, pc} + 1709 .cfi_endproc + 1710 .LFE141: + 1712 .section .text.pollCMD,"ax",%progbits + 1713 .align 1 + 1714 .global pollCMD + 1715 .syntax unified + 1716 .thumb + 1717 .thumb_func + 1719 pollCMD: + 1720 .LFB142: + 291:Core/Src/ADBMS_LL_Driver.c **** + 292:Core/Src/ADBMS_LL_Driver.c **** //check poll command - no data PEC sent back + 293:Core/Src/ADBMS_LL_Driver.c **** uint8 pollCMD(uint16 command) { + 1721 .loc 1 293 31 + 1722 .cfi_startproc + 1723 @ args = 0, pretend = 0, frame = 24 + 1724 @ frame_needed = 1, uses_anonymous_args = 0 + 1725 0000 80B5 push {r7, lr} + 1726 .cfi_def_cfa_offset 8 + 1727 .cfi_offset 7, -8 + 1728 .cfi_offset 14, -4 + 1729 0002 86B0 sub sp, sp, #24 + 1730 .cfi_def_cfa_offset 32 + 1731 0004 00AF add r7, sp, #0 + 1732 .cfi_def_cfa_register 7 + 1733 0006 0346 mov r3, r0 + 1734 0008 FB80 strh r3, [r7, #6] @ movhi + 294:Core/Src/ADBMS_LL_Driver.c **** uint8 txbuffer[5] = {}; + 1735 .loc 1 294 9 + 1736 000a 07F11003 add r3, r7, #16 + 1737 000e 0022 movs r2, #0 + 1738 0010 1A60 str r2, [r3] + 1739 0012 1A71 strb r2, [r3, #4] + 295:Core/Src/ADBMS_LL_Driver.c **** uint8 rxbuffer[5] = {}; + 1740 .loc 1 295 9 + 1741 0014 07F10803 add r3, r7, #8 + 1742 0018 0022 movs r2, #0 + 1743 001a 1A60 str r2, [r3] + 1744 001c 1A71 strb r2, [r3, #4] + 296:Core/Src/ADBMS_LL_Driver.c **** + 297:Core/Src/ADBMS_LL_Driver.c **** txbuffer[0] = (command >> 8) & 0xFF; + 1745 .loc 1 297 15 + 1746 001e FB88 ldrh r3, [r7, #6] + 1747 0020 1B0A lsrs r3, r3, #8 + 1748 0022 9BB2 uxth r3, r3 + 1749 0024 DBB2 uxtb r3, r3 + 1750 0026 3B74 strb r3, [r7, #16] + 298:Core/Src/ADBMS_LL_Driver.c **** txbuffer[1] = (command)&0xFF; + 1751 .loc 1 298 15 + 1752 0028 FB88 ldrh r3, [r7, #6] @ movhi + 1753 002a DBB2 uxtb r3, r3 + ARM GAS /tmp/cczsHaNw.s page 37 + + + 1754 002c 7B74 strb r3, [r7, #17] + 299:Core/Src/ADBMS_LL_Driver.c **** calculateCommandPEC(txbuffer, 4); + 1755 .loc 1 299 3 + 1756 002e 07F11003 add r3, r7, #16 + 1757 0032 0421 movs r1, #4 + 1758 0034 1846 mov r0, r3 + 1759 0036 FFF7FEFF bl calculateCommandPEC + 300:Core/Src/ADBMS_LL_Driver.c **** + 301:Core/Src/ADBMS_LL_Driver.c **** mcuAdbmsCSLow(); + 1760 .loc 1 301 3 + 1761 003a FFF7FEFF bl mcuAdbmsCSLow + 302:Core/Src/ADBMS_LL_Driver.c **** uint8 status = mcuSPITransmitReceive(rxbuffer, txbuffer, 5); + 1762 .loc 1 302 18 + 1763 003e 07F11001 add r1, r7, #16 + 1764 0042 07F10803 add r3, r7, #8 + 1765 0046 0522 movs r2, #5 + 1766 0048 1846 mov r0, r3 + 1767 004a FFF7FEFF bl mcuSPITransmitReceive + 1768 004e 0346 mov r3, r0 + 1769 0050 FB75 strb r3, [r7, #23] + 303:Core/Src/ADBMS_LL_Driver.c **** mcuAdbmsCSHigh(); + 1770 .loc 1 303 3 + 1771 0052 FFF7FEFF bl mcuAdbmsCSHigh + 304:Core/Src/ADBMS_LL_Driver.c **** + 305:Core/Src/ADBMS_LL_Driver.c **** if (status != 0) { + 1772 .loc 1 305 6 + 1773 0056 FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 1774 0058 002B cmp r3, #0 + 1775 005a 01D0 beq .L66 + 306:Core/Src/ADBMS_LL_Driver.c **** return status; + 1776 .loc 1 306 12 + 1777 005c FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 1778 005e 00E0 b .L68 + 1779 .L66: + 307:Core/Src/ADBMS_LL_Driver.c **** } + 308:Core/Src/ADBMS_LL_Driver.c **** + 309:Core/Src/ADBMS_LL_Driver.c **** return rxbuffer[4]; //last byte will be poll response + 1780 .loc 1 309 18 + 1781 0060 3B7B ldrb r3, [r7, #12] @ zero_extendqisi2 + 1782 .L68: + 310:Core/Src/ADBMS_LL_Driver.c **** } + 1783 .loc 1 310 1 + 1784 0062 1846 mov r0, r3 + 1785 0064 1837 adds r7, r7, #24 + 1786 .cfi_def_cfa_offset 8 + 1787 0066 BD46 mov sp, r7 + 1788 .cfi_def_cfa_register 13 + 1789 @ sp needed + 1790 0068 80BD pop {r7, pc} + 1791 .cfi_endproc + 1792 .LFE142: + 1794 .section .text.mcuAdbmsCSLow,"ax",%progbits + 1795 .align 1 + 1796 .global mcuAdbmsCSLow + 1797 .syntax unified + 1798 .thumb + 1799 .thumb_func + ARM GAS /tmp/cczsHaNw.s page 38 + + + 1801 mcuAdbmsCSLow: + 1802 .LFB143: + 311:Core/Src/ADBMS_LL_Driver.c **** + 312:Core/Src/ADBMS_LL_Driver.c **** void mcuAdbmsCSLow() { + 1803 .loc 1 312 22 + 1804 .cfi_startproc + 1805 @ args = 0, pretend = 0, frame = 0 + 1806 @ frame_needed = 1, uses_anonymous_args = 0 + 1807 0000 80B5 push {r7, lr} + 1808 .cfi_def_cfa_offset 8 + 1809 .cfi_offset 7, -8 + 1810 .cfi_offset 14, -4 + 1811 0002 00AF add r7, sp, #0 + 1812 .cfi_def_cfa_register 7 + 313:Core/Src/ADBMS_LL_Driver.c **** HAL_GPIO_WritePin(CSB_GPIO_Port, CSB_Pin, GPIO_PIN_RESET); + 1813 .loc 1 313 3 + 1814 0004 0022 movs r2, #0 + 1815 0006 1021 movs r1, #16 + 1816 0008 4FF09040 mov r0, #1207959552 + 1817 000c FFF7FEFF bl HAL_GPIO_WritePin + 314:Core/Src/ADBMS_LL_Driver.c **** } + 1818 .loc 1 314 1 + 1819 0010 00BF nop + 1820 0012 80BD pop {r7, pc} + 1821 .cfi_endproc + 1822 .LFE143: + 1824 .section .text.mcuAdbmsCSHigh,"ax",%progbits + 1825 .align 1 + 1826 .global mcuAdbmsCSHigh + 1827 .syntax unified + 1828 .thumb + 1829 .thumb_func + 1831 mcuAdbmsCSHigh: + 1832 .LFB144: + 315:Core/Src/ADBMS_LL_Driver.c **** + 316:Core/Src/ADBMS_LL_Driver.c **** void mcuAdbmsCSHigh() { + 1833 .loc 1 316 23 + 1834 .cfi_startproc + 1835 @ args = 0, pretend = 0, frame = 0 + 1836 @ frame_needed = 1, uses_anonymous_args = 0 + 1837 0000 80B5 push {r7, lr} + 1838 .cfi_def_cfa_offset 8 + 1839 .cfi_offset 7, -8 + 1840 .cfi_offset 14, -4 + 1841 0002 00AF add r7, sp, #0 + 1842 .cfi_def_cfa_register 7 + 317:Core/Src/ADBMS_LL_Driver.c **** HAL_GPIO_WritePin(CSB_GPIO_Port, CSB_Pin, GPIO_PIN_SET); + 1843 .loc 1 317 3 + 1844 0004 0122 movs r2, #1 + 1845 0006 1021 movs r1, #16 + 1846 0008 4FF09040 mov r0, #1207959552 + 1847 000c FFF7FEFF bl HAL_GPIO_WritePin + 318:Core/Src/ADBMS_LL_Driver.c **** } + 1848 .loc 1 318 1 + 1849 0010 00BF nop + 1850 0012 80BD pop {r7, pc} + 1851 .cfi_endproc + ARM GAS /tmp/cczsHaNw.s page 39 + + + 1852 .LFE144: + 1854 .section .text.mcuSPITransmit,"ax",%progbits + 1855 .align 1 + 1856 .global mcuSPITransmit + 1857 .syntax unified + 1858 .thumb + 1859 .thumb_func + 1861 mcuSPITransmit: + 1862 .LFB145: + 319:Core/Src/ADBMS_LL_Driver.c **** + 320:Core/Src/ADBMS_LL_Driver.c **** uint8 mcuSPITransmit(uint8* buffer, uint8 buffersize) { + 1863 .loc 1 320 55 + 1864 .cfi_startproc + 1865 @ args = 0, pretend = 0, frame = 24 + 1866 @ frame_needed = 1, uses_anonymous_args = 0 + 1867 0000 2DE9F043 push {r4, r5, r6, r7, r8, r9, lr} + 1868 .cfi_def_cfa_offset 28 + 1869 .cfi_offset 4, -28 + 1870 .cfi_offset 5, -24 + 1871 .cfi_offset 6, -20 + 1872 .cfi_offset 7, -16 + 1873 .cfi_offset 8, -12 + 1874 .cfi_offset 9, -8 + 1875 .cfi_offset 14, -4 + 1876 0004 89B0 sub sp, sp, #36 + 1877 .cfi_def_cfa_offset 64 + 1878 0006 02AF add r7, sp, #8 + 1879 .cfi_def_cfa 7, 56 + 1880 0008 7860 str r0, [r7, #4] + 1881 000a 0B46 mov r3, r1 + 1882 000c FB70 strb r3, [r7, #3] + 1883 .loc 1 320 55 + 1884 000e 6B46 mov r3, sp + 1885 0010 1E46 mov r6, r3 + 321:Core/Src/ADBMS_LL_Driver.c **** uint8 rxbuf[buffersize]; + 1886 .loc 1 321 5 + 1887 0012 F978 ldrb r1, [r7, #3] @ zero_extendqisi2 + 1888 .loc 1 321 11 + 1889 0014 0B46 mov r3, r1 + 1890 0016 013B subs r3, r3, #1 + 1891 0018 7B61 str r3, [r7, #20] + 1892 001a CBB2 uxtb r3, r1 + 1893 001c 0022 movs r2, #0 + 1894 001e 9846 mov r8, r3 + 1895 0020 9146 mov r9, r2 + 1896 0022 4FF00002 mov r2, #0 + 1897 0026 4FF00003 mov r3, #0 + 1898 002a 4FEAC903 lsl r3, r9, #3 + 1899 002e 43EA5873 orr r3, r3, r8, lsr #29 + 1900 0032 4FEAC802 lsl r2, r8, #3 + 1901 0036 CBB2 uxtb r3, r1 + 1902 0038 0022 movs r2, #0 + 1903 003a 1C46 mov r4, r3 + 1904 003c 1546 mov r5, r2 + 1905 003e 4FF00002 mov r2, #0 + 1906 0042 4FF00003 mov r3, #0 + 1907 0046 EB00 lsls r3, r5, #3 + ARM GAS /tmp/cczsHaNw.s page 40 + + + 1908 0048 43EA5473 orr r3, r3, r4, lsr #29 + 1909 004c E200 lsls r2, r4, #3 + 1910 004e 0B46 mov r3, r1 + 1911 0050 0733 adds r3, r3, #7 + 1912 0052 DB08 lsrs r3, r3, #3 + 1913 0054 DB00 lsls r3, r3, #3 + 1914 0056 ADEB030D sub sp, sp, r3 + 1915 005a 02AB add r3, sp, #8 + 1916 005c 0033 adds r3, r3, #0 + 1917 005e 3B61 str r3, [r7, #16] + 322:Core/Src/ADBMS_LL_Driver.c **** const HAL_StatusTypeDef status = HAL_SPI_TransmitReceive(adbmsspi, buffer, rxbuf, buffersize, + 1918 .loc 1 322 38 + 1919 0060 0F4B ldr r3, .L73 + 1920 0062 1868 ldr r0, [r3] + 1921 0064 FB78 ldrb r3, [r7, #3] @ zero_extendqisi2 + 1922 0066 9BB2 uxth r3, r3 + 1923 0068 6422 movs r2, #100 + 1924 006a 0092 str r2, [sp] + 1925 006c 3A69 ldr r2, [r7, #16] + 1926 006e 7968 ldr r1, [r7, #4] + 1927 0070 FFF7FEFF bl HAL_SPI_TransmitReceive + 1928 0074 0346 mov r3, r0 + 1929 0076 FB73 strb r3, [r7, #15] + 1930 .LBB16: + 323:Core/Src/ADBMS_LL_Driver.c **** ADBMS_SPI_TIMEOUT); + 324:Core/Src/ADBMS_LL_Driver.c **** __HAL_SPI_CLEAR_OVRFLAG(adbmsspi); + 1931 .loc 1 324 3 + 1932 0078 0023 movs r3, #0 + 1933 007a BB60 str r3, [r7, #8] + 1934 007c 084B ldr r3, .L73 + 1935 007e 1B68 ldr r3, [r3] + 1936 0080 1B68 ldr r3, [r3] + 1937 0082 DB68 ldr r3, [r3, #12] + 1938 0084 BB60 str r3, [r7, #8] + 1939 0086 064B ldr r3, .L73 + 1940 0088 1B68 ldr r3, [r3] + 1941 008a 1B68 ldr r3, [r3] + 1942 008c 9B68 ldr r3, [r3, #8] + 1943 008e BB60 str r3, [r7, #8] + 1944 0090 BB68 ldr r3, [r7, #8] + 1945 .LBE16: + 325:Core/Src/ADBMS_LL_Driver.c **** return status; + 1946 .loc 1 325 10 + 1947 0092 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 1948 0094 B546 mov sp, r6 + 326:Core/Src/ADBMS_LL_Driver.c **** } + 1949 .loc 1 326 1 + 1950 0096 1846 mov r0, r3 + 1951 0098 1C37 adds r7, r7, #28 + 1952 .cfi_def_cfa_offset 28 + 1953 009a BD46 mov sp, r7 + 1954 .cfi_def_cfa_register 13 + 1955 @ sp needed + 1956 009c BDE8F083 pop {r4, r5, r6, r7, r8, r9, pc} + 1957 .L74: + 1958 .align 2 + 1959 .L73: + ARM GAS /tmp/cczsHaNw.s page 41 + + + 1960 00a0 00000000 .word adbmsspi + 1961 .cfi_endproc + 1962 .LFE145: + 1964 .section .text.mcuSPIReceive,"ax",%progbits + 1965 .align 1 + 1966 .global mcuSPIReceive + 1967 .syntax unified + 1968 .thumb + 1969 .thumb_func + 1971 mcuSPIReceive: + 1972 .LFB146: + 327:Core/Src/ADBMS_LL_Driver.c **** + 328:Core/Src/ADBMS_LL_Driver.c **** uint8 mcuSPIReceive(uint8* buffer, uint8 buffersize) { + 1973 .loc 1 328 54 + 1974 .cfi_startproc + 1975 @ args = 0, pretend = 0, frame = 16 + 1976 @ frame_needed = 1, uses_anonymous_args = 0 + 1977 0000 80B5 push {r7, lr} + 1978 .cfi_def_cfa_offset 8 + 1979 .cfi_offset 7, -8 + 1980 .cfi_offset 14, -4 + 1981 0002 84B0 sub sp, sp, #16 + 1982 .cfi_def_cfa_offset 24 + 1983 0004 00AF add r7, sp, #0 + 1984 .cfi_def_cfa_register 7 + 1985 0006 7860 str r0, [r7, #4] + 1986 0008 0B46 mov r3, r1 + 1987 000a FB70 strb r3, [r7, #3] + 329:Core/Src/ADBMS_LL_Driver.c **** const HAL_StatusTypeDef status = HAL_SPI_Receive(adbmsspi, buffer, buffersize, ADBMS_SPI_TIMEOU + 1988 .loc 1 329 38 + 1989 000c 074B ldr r3, .L77 + 1990 000e 1868 ldr r0, [r3] + 1991 0010 FB78 ldrb r3, [r7, #3] @ zero_extendqisi2 + 1992 0012 9AB2 uxth r2, r3 + 1993 0014 6423 movs r3, #100 + 1994 0016 7968 ldr r1, [r7, #4] + 1995 0018 FFF7FEFF bl HAL_SPI_Receive + 1996 001c 0346 mov r3, r0 + 1997 001e FB73 strb r3, [r7, #15] + 330:Core/Src/ADBMS_LL_Driver.c **** return status; + 1998 .loc 1 330 10 + 1999 0020 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 331:Core/Src/ADBMS_LL_Driver.c **** } + 2000 .loc 1 331 1 + 2001 0022 1846 mov r0, r3 + 2002 0024 1037 adds r7, r7, #16 + 2003 .cfi_def_cfa_offset 8 + 2004 0026 BD46 mov sp, r7 + 2005 .cfi_def_cfa_register 13 + 2006 @ sp needed + 2007 0028 80BD pop {r7, pc} + 2008 .L78: + 2009 002a 00BF .align 2 + 2010 .L77: + 2011 002c 00000000 .word adbmsspi + 2012 .cfi_endproc + 2013 .LFE146: + ARM GAS /tmp/cczsHaNw.s page 42 + + + 2015 .section .text.mcuSPITransmitReceive,"ax",%progbits + 2016 .align 1 + 2017 .global mcuSPITransmitReceive + 2018 .syntax unified + 2019 .thumb + 2020 .thumb_func + 2022 mcuSPITransmitReceive: + 2023 .LFB147: + 332:Core/Src/ADBMS_LL_Driver.c **** + 333:Core/Src/ADBMS_LL_Driver.c **** uint8 mcuSPITransmitReceive(uint8* rxbuffer, uint8* txbuffer, + 334:Core/Src/ADBMS_LL_Driver.c **** uint8 buffersize) { + 2024 .loc 1 334 47 + 2025 .cfi_startproc + 2026 @ args = 0, pretend = 0, frame = 24 + 2027 @ frame_needed = 1, uses_anonymous_args = 0 + 2028 0000 80B5 push {r7, lr} + 2029 .cfi_def_cfa_offset 8 + 2030 .cfi_offset 7, -8 + 2031 .cfi_offset 14, -4 + 2032 0002 88B0 sub sp, sp, #32 + 2033 .cfi_def_cfa_offset 40 + 2034 0004 02AF add r7, sp, #8 + 2035 .cfi_def_cfa 7, 32 + 2036 0006 F860 str r0, [r7, #12] + 2037 0008 B960 str r1, [r7, #8] + 2038 000a 1346 mov r3, r2 + 2039 000c FB71 strb r3, [r7, #7] + 335:Core/Src/ADBMS_LL_Driver.c **** const HAL_StatusTypeDef status = HAL_SPI_TransmitReceive(adbmsspi, txbuffer, rxbuffer, buffersi + 2040 .loc 1 335 38 + 2041 000e 084B ldr r3, .L81 + 2042 0010 1868 ldr r0, [r3] + 2043 0012 FB79 ldrb r3, [r7, #7] @ zero_extendqisi2 + 2044 0014 9BB2 uxth r3, r3 + 2045 0016 6422 movs r2, #100 + 2046 0018 0092 str r2, [sp] + 2047 001a FA68 ldr r2, [r7, #12] + 2048 001c B968 ldr r1, [r7, #8] + 2049 001e FFF7FEFF bl HAL_SPI_TransmitReceive + 2050 0022 0346 mov r3, r0 + 2051 0024 FB75 strb r3, [r7, #23] + 336:Core/Src/ADBMS_LL_Driver.c **** ADBMS_SPI_TIMEOUT); + 337:Core/Src/ADBMS_LL_Driver.c **** return status; + 2052 .loc 1 337 10 + 2053 0026 FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 338:Core/Src/ADBMS_LL_Driver.c **** } + 2054 .loc 1 338 1 + 2055 0028 1846 mov r0, r3 + 2056 002a 1837 adds r7, r7, #24 + 2057 .cfi_def_cfa_offset 8 + 2058 002c BD46 mov sp, r7 + 2059 .cfi_def_cfa_register 13 + 2060 @ sp needed + 2061 002e 80BD pop {r7, pc} + 2062 .L82: + 2063 .align 2 + 2064 .L81: + 2065 0030 00000000 .word adbmsspi + ARM GAS /tmp/cczsHaNw.s page 43 + + + 2066 .cfi_endproc + 2067 .LFE147: + 2069 .section .text.mcuDelay,"ax",%progbits + 2070 .align 1 + 2071 .global mcuDelay + 2072 .syntax unified + 2073 .thumb + 2074 .thumb_func + 2076 mcuDelay: + 2077 .LFB148: + 339:Core/Src/ADBMS_LL_Driver.c **** + 340:Core/Src/ADBMS_LL_Driver.c **** inline void mcuDelay(uint16 delay) { HAL_Delay(delay); } + 2078 .loc 1 340 36 + 2079 .cfi_startproc + 2080 @ args = 0, pretend = 0, frame = 8 + 2081 @ frame_needed = 1, uses_anonymous_args = 0 + 2082 0000 80B5 push {r7, lr} + 2083 .cfi_def_cfa_offset 8 + 2084 .cfi_offset 7, -8 + 2085 .cfi_offset 14, -4 + 2086 0002 82B0 sub sp, sp, #8 + 2087 .cfi_def_cfa_offset 16 + 2088 0004 00AF add r7, sp, #0 + 2089 .cfi_def_cfa_register 7 + 2090 0006 0346 mov r3, r0 + 2091 0008 FB80 strh r3, [r7, #6] @ movhi + 2092 .loc 1 340 38 + 2093 000a FB88 ldrh r3, [r7, #6] + 2094 000c 1846 mov r0, r3 + 2095 000e FFF7FEFF bl HAL_Delay + 2096 .loc 1 340 56 + 2097 0012 00BF nop + 2098 0014 0837 adds r7, r7, #8 + 2099 .cfi_def_cfa_offset 8 + 2100 0016 BD46 mov sp, r7 + 2101 .cfi_def_cfa_register 13 + 2102 @ sp needed + 2103 0018 80BD pop {r7, pc} + 2104 .cfi_endproc + 2105 .LFE148: + 2107 .text + 2108 .Letext0: + 2109 .file 2 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 2110 .file 3 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 2111 .file 4 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + 2112 .file 5 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h" + 2113 .file 6 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h" + 2114 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h" + 2115 .file 8 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h" + 2116 .file 9 "Core/Inc/ADBMS_LL_Driver.h" + 2117 .file 10 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h" + ARM GAS /tmp/cczsHaNw.s page 44 + + +DEFINED SYMBOLS + *ABS*:00000000 ADBMS_LL_Driver.c + /tmp/cczsHaNw.s:25 .bss.adbmsspi:00000000 adbmsspi + /tmp/cczsHaNw.s:22 .bss.adbmsspi:00000000 $d + /tmp/cczsHaNw.s:28 .text.adbmsDriverInit:00000000 $t + /tmp/cczsHaNw.s:34 .text.adbmsDriverInit:00000000 adbmsDriverInit + /tmp/cczsHaNw.s:1801 .text.mcuAdbmsCSLow:00000000 mcuAdbmsCSLow + /tmp/cczsHaNw.s:1831 .text.mcuAdbmsCSHigh:00000000 mcuAdbmsCSHigh + /tmp/cczsHaNw.s:73 .text.adbmsDriverInit:00000028 $d + /tmp/cczsHaNw.s:78 .text.calculateCommandPEC:00000000 $t + /tmp/cczsHaNw.s:84 .text.calculateCommandPEC:00000000 calculateCommandPEC + /tmp/cczsHaNw.s:356 .text.updateCommandPEC:00000000 updateCommandPEC + /tmp/cczsHaNw.s:209 .text.checkCommandPEC:00000000 $t + /tmp/cczsHaNw.s:215 .text.checkCommandPEC:00000000 checkCommandPEC + /tmp/cczsHaNw.s:350 .text.updateCommandPEC:00000000 $t + /tmp/cczsHaNw.s:638 .text.pec10_calc:00000000 $t + /tmp/cczsHaNw.s:644 .text.pec10_calc:00000000 pec10_calc + /tmp/cczsHaNw.s:817 .text.calculateDataPEC:00000000 $t + /tmp/cczsHaNw.s:823 .text.calculateDataPEC:00000000 calculateDataPEC + /tmp/cczsHaNw.s:897 .text.checkDataPEC:00000000 $t + /tmp/cczsHaNw.s:903 .text.checkDataPEC:00000000 checkDataPEC + /tmp/cczsHaNw.s:1048 .text.F_CRC_CalculaCheckSum:00000000 F_CRC_CalculaCheckSum + /tmp/cczsHaNw.s:956 .text.F_CRC_ObtenValorDeTabla:00000000 $t + /tmp/cczsHaNw.s:961 .text.F_CRC_ObtenValorDeTabla:00000000 F_CRC_ObtenValorDeTabla + /tmp/cczsHaNw.s:1042 .text.F_CRC_CalculaCheckSum:00000000 $t + /tmp/cczsHaNw.s:1135 .text.updateDataPEC:00000000 $t + /tmp/cczsHaNw.s:1141 .text.updateDataPEC:00000000 updateDataPEC + /tmp/cczsHaNw.s:1324 .text.writeCMD:00000000 $t + /tmp/cczsHaNw.s:1330 .text.writeCMD:00000000 writeCMD + /tmp/cczsHaNw.s:1861 .text.mcuSPITransmit:00000000 mcuSPITransmit + /tmp/cczsHaNw.s:1509 .text.readCMD:00000000 $t + /tmp/cczsHaNw.s:1515 .text.readCMD:00000000 readCMD + /tmp/cczsHaNw.s:2022 .text.mcuSPITransmitReceive:00000000 mcuSPITransmitReceive + /tmp/cczsHaNw.s:1713 .text.pollCMD:00000000 $t + /tmp/cczsHaNw.s:1719 .text.pollCMD:00000000 pollCMD + /tmp/cczsHaNw.s:1795 .text.mcuAdbmsCSLow:00000000 $t + /tmp/cczsHaNw.s:1825 .text.mcuAdbmsCSHigh:00000000 $t + /tmp/cczsHaNw.s:1855 .text.mcuSPITransmit:00000000 $t + /tmp/cczsHaNw.s:1960 .text.mcuSPITransmit:000000a0 $d + /tmp/cczsHaNw.s:1965 .text.mcuSPIReceive:00000000 $t + /tmp/cczsHaNw.s:1971 .text.mcuSPIReceive:00000000 mcuSPIReceive + /tmp/cczsHaNw.s:2011 .text.mcuSPIReceive:0000002c $d + /tmp/cczsHaNw.s:2016 .text.mcuSPITransmitReceive:00000000 $t + /tmp/cczsHaNw.s:2065 .text.mcuSPITransmitReceive:00000030 $d + /tmp/cczsHaNw.s:2070 .text.mcuDelay:00000000 $t + /tmp/cczsHaNw.s:2076 .text.mcuDelay:00000000 mcuDelay + +UNDEFINED SYMBOLS +HAL_Delay +HAL_GPIO_WritePin +HAL_SPI_TransmitReceive +HAL_SPI_Receive diff --git a/Software/build/ADBMS_LL_Driver.o b/Software/build/ADBMS_LL_Driver.o new file mode 100644 index 0000000..165c27b Binary files /dev/null and b/Software/build/ADBMS_LL_Driver.o differ diff --git a/Software/build/AMS_HighLevel.d b/Software/build/AMS_HighLevel.d new file mode 100644 index 0000000..efbaec9 --- /dev/null +++ b/Software/build/AMS_HighLevel.d @@ -0,0 +1,74 @@ +build/AMS_HighLevel.o: Core/Src/AMS_HighLevel.c Core/Inc/AMS_HighLevel.h \ + Core/Inc/ADBMS_Abstraction.h Core/Inc/ADBMS_CMD_MAKROS.h \ + Core/Inc/ADBMS_LL_Driver.h Core/Inc/main.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + Core/Inc/stm32f3xx_hal_conf.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h \ + Core/Lib/can-halal/can-halal.h Core/Inc/errors.h \ + Core/Inc/ADBMS_Abstraction.h Core/Inc/ADBMS_LL_Driver.h +Core/Inc/AMS_HighLevel.h: +Core/Inc/ADBMS_Abstraction.h: +Core/Inc/ADBMS_CMD_MAKROS.h: +Core/Inc/ADBMS_LL_Driver.h: +Core/Inc/main.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h: +Core/Lib/can-halal/can-halal.h: +Core/Inc/errors.h: +Core/Inc/ADBMS_Abstraction.h: +Core/Inc/ADBMS_LL_Driver.h: diff --git a/Software/build/AMS_HighLevel.lst b/Software/build/AMS_HighLevel.lst new file mode 100644 index 0000000..dd4507c --- /dev/null +++ b/Software/build/AMS_HighLevel.lst @@ -0,0 +1,1269 @@ +ARM GAS /tmp/cccWxVkc.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 6 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "AMS_HighLevel.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Core/Src/AMS_HighLevel.c" + 20 .global module + 21 .section .bss.module,"aw",%nobits + 22 .align 2 + 25 module: + 26 0000 00000000 .space 116 + 26 00000000 + 26 00000000 + 26 00000000 + 26 00000000 + 27 .global balancedCells + 28 .section .bss.balancedCells,"aw",%nobits + 29 .align 2 + 32 balancedCells: + 33 0000 00000000 .space 4 + 34 .global balancingActive + 35 .section .bss.balancingActive,"aw",%nobits + 38 balancingActive: + 39 0000 00 .space 1 + 40 .global amsuv + 41 .section .bss.amsuv,"aw",%nobits + 42 .align 1 + 45 amsuv: + 46 0000 0000 .space 2 + 47 .global amsov + 48 .section .bss.amsov,"aw",%nobits + 49 .align 1 + 52 amsov: + 53 0000 0000 .space 2 + 54 .global numberofCells + 55 .section .data.numberofCells,"aw" + 58 numberofCells: + 59 0000 0D .byte 13 + 60 .global numberofAux + 61 .section .bss.numberofAux,"aw",%nobits + 64 numberofAux: + 65 0000 00 .space 1 + 66 .global packetChecksumFails + 67 .section .bss.packetChecksumFails,"aw",%nobits + ARM GAS /tmp/cccWxVkc.s page 2 + + + 70 packetChecksumFails: + 71 0000 00 .space 1 + 72 .global deviceSleeps + 73 .section .bss.deviceSleeps,"aw",%nobits + 76 deviceSleeps: + 77 0000 00 .space 1 + 78 .global currentAMSState + 79 .section .bss.currentAMSState,"aw",%nobits + 82 currentAMSState: + 83 0000 00 .space 1 + 84 .global lastAMSState + 85 .section .bss.lastAMSState,"aw",%nobits + 88 lastAMSState: + 89 0000 00 .space 1 + 90 .global pollingTimes + 91 .section .bss.pollingTimes,"aw",%nobits + 92 .align 2 + 95 pollingTimes: + 96 0000 00000000 .space 8 + 96 00000000 + 97 .section .text.AMS_Init,"ax",%progbits + 98 .align 1 + 99 .global AMS_Init + 100 .syntax unified + 101 .thumb + 102 .thumb_func + 104 AMS_Init: + 105 .LFB130: + 1:Core/Src/AMS_HighLevel.c **** /* + 2:Core/Src/AMS_HighLevel.c **** * AMS_HighLevel.c + 3:Core/Src/AMS_HighLevel.c **** * + 4:Core/Src/AMS_HighLevel.c **** * Created on: 20.07.2022 + 5:Core/Src/AMS_HighLevel.c **** * Author: max + 6:Core/Src/AMS_HighLevel.c **** */ + 7:Core/Src/AMS_HighLevel.c **** + 8:Core/Src/AMS_HighLevel.c **** #include "AMS_HighLevel.h" + 9:Core/Src/AMS_HighLevel.c **** #include "ADBMS_Abstraction.h" + 10:Core/Src/AMS_HighLevel.c **** #include "ADBMS_LL_Driver.h" + 11:Core/Src/AMS_HighLevel.c **** #include + 12:Core/Src/AMS_HighLevel.c **** + 13:Core/Src/AMS_HighLevel.c **** Cell_Module module = {}; + 14:Core/Src/AMS_HighLevel.c **** uint32_t balancedCells = 0; + 15:Core/Src/AMS_HighLevel.c **** bool balancingActive = false; + 16:Core/Src/AMS_HighLevel.c **** + 17:Core/Src/AMS_HighLevel.c **** uint16_t amsuv = 0; + 18:Core/Src/AMS_HighLevel.c **** uint16_t amsov = 0; + 19:Core/Src/AMS_HighLevel.c **** + 20:Core/Src/AMS_HighLevel.c **** uint8_t numberofCells = 13; + 21:Core/Src/AMS_HighLevel.c **** uint8_t numberofAux = 0; + 22:Core/Src/AMS_HighLevel.c **** + 23:Core/Src/AMS_HighLevel.c **** uint8_t packetChecksumFails = 0; + 24:Core/Src/AMS_HighLevel.c **** #define MAX_PACKET_CHECKSUM_FAILS 5 + 25:Core/Src/AMS_HighLevel.c **** + 26:Core/Src/AMS_HighLevel.c **** uint8_t deviceSleeps = 0; + 27:Core/Src/AMS_HighLevel.c **** #define MAX_DEVICE_SLEEP 3 //TODO: change to correct value + 28:Core/Src/AMS_HighLevel.c **** #define MAX_CELL_VOLTAGE 4200 //change to 4200 + 29:Core/Src/AMS_HighLevel.c **** #define MIN_CELL_VOLTAGE 3200 //change to 3000 + ARM GAS /tmp/cccWxVkc.s page 3 + + + 30:Core/Src/AMS_HighLevel.c **** #define CELL_VOLTAGE_DIFF_BALANCING 20 //max difference between lowest cell and any other cell + 31:Core/Src/AMS_HighLevel.c **** + 32:Core/Src/AMS_HighLevel.c **** amsState currentAMSState = AMSDEACTIVE; + 33:Core/Src/AMS_HighLevel.c **** amsState lastAMSState = AMSDEACTIVE; + 34:Core/Src/AMS_HighLevel.c **** + 35:Core/Src/AMS_HighLevel.c **** struct pollingTimes { + 36:Core/Src/AMS_HighLevel.c **** uint32_t S_ADC_OW_CHECK; + 37:Core/Src/AMS_HighLevel.c **** uint32_t TMP1075; + 38:Core/Src/AMS_HighLevel.c **** }; + 39:Core/Src/AMS_HighLevel.c **** + 40:Core/Src/AMS_HighLevel.c **** struct pollingTimes pollingTimes = {0, 0}; + 41:Core/Src/AMS_HighLevel.c **** + 42:Core/Src/AMS_HighLevel.c **** void AMS_Init(SPI_HandleTypeDef* hspi) { + 106 .loc 1 42 40 + 107 .cfi_startproc + 108 @ args = 0, pretend = 0, frame = 16 + 109 @ frame_needed = 1, uses_anonymous_args = 0 + 110 0000 90B5 push {r4, r7, lr} + 111 .cfi_def_cfa_offset 12 + 112 .cfi_offset 4, -12 + 113 .cfi_offset 7, -8 + 114 .cfi_offset 14, -4 + 115 0002 85B0 sub sp, sp, #20 + 116 .cfi_def_cfa_offset 32 + 117 0004 00AF add r7, sp, #0 + 118 .cfi_def_cfa_register 7 + 119 0006 7860 str r0, [r7, #4] + 43:Core/Src/AMS_HighLevel.c **** initAMS(hspi, numberofCells, numberofAux); + 120 .loc 1 43 3 + 121 0008 104B ldr r3, .L2 + 122 000a 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 123 000c 104A ldr r2, .L2+4 + 124 000e 1278 ldrb r2, [r2] @ zero_extendqisi2 + 125 0010 1946 mov r1, r3 + 126 0012 7868 ldr r0, [r7, #4] + 127 0014 FFF7FEFF bl initAMS + 44:Core/Src/AMS_HighLevel.c **** amsov = DEFAULT_OV; + 128 .loc 1 44 9 + 129 0018 0E4B ldr r3, .L2+8 + 130 001a 40F26542 movw r2, #1125 + 131 001e 1A80 strh r2, [r3] @ movhi + 45:Core/Src/AMS_HighLevel.c **** amsuv = DEFAULT_UV; + 132 .loc 1 45 9 + 133 0020 0D4B ldr r3, .L2+12 + 134 0022 40F2A112 movw r2, #417 + 135 0026 1A80 strh r2, [r3] @ movhi + 46:Core/Src/AMS_HighLevel.c **** + 47:Core/Src/AMS_HighLevel.c **** pollingTimes = (struct pollingTimes) {HAL_GetTick(), HAL_GetTick()}; + 136 .loc 1 47 41 + 137 0028 FFF7FEFF bl HAL_GetTick + 138 002c 0446 mov r4, r0 + 139 .loc 1 47 56 discriminator 1 + 140 002e FFF7FEFF bl HAL_GetTick + 141 0032 0346 mov r3, r0 + 142 .loc 1 47 16 discriminator 2 + 143 0034 094A ldr r2, .L2+16 + 144 0036 1460 str r4, [r2] + ARM GAS /tmp/cccWxVkc.s page 4 + + + 145 0038 084A ldr r2, .L2+16 + 146 003a 5360 str r3, [r2, #4] + 48:Core/Src/AMS_HighLevel.c **** + 49:Core/Src/AMS_HighLevel.c **** currentAMSState = AMSIDLE; + 147 .loc 1 49 19 + 148 003c 084B ldr r3, .L2+20 + 149 003e 0122 movs r2, #1 + 150 0040 1A70 strb r2, [r3] + 50:Core/Src/AMS_HighLevel.c **** } + 151 .loc 1 50 1 + 152 0042 00BF nop + 153 0044 1437 adds r7, r7, #20 + 154 .cfi_def_cfa_offset 12 + 155 0046 BD46 mov sp, r7 + 156 .cfi_def_cfa_register 13 + 157 @ sp needed + 158 0048 90BD pop {r4, r7, pc} + 159 .L3: + 160 004a 00BF .align 2 + 161 .L2: + 162 004c 00000000 .word numberofCells + 163 0050 00000000 .word numberofAux + 164 0054 00000000 .word amsov + 165 0058 00000000 .word amsuv + 166 005c 00000000 .word pollingTimes + 167 0060 00000000 .word currentAMSState + 168 .cfi_endproc + 169 .LFE130: + 171 .section .text.AMS_Loop,"ax",%progbits + 172 .align 1 + 173 .global AMS_Loop + 174 .syntax unified + 175 .thumb + 176 .thumb_func + 178 AMS_Loop: + 179 .LFB131: + 51:Core/Src/AMS_HighLevel.c **** + 52:Core/Src/AMS_HighLevel.c **** void AMS_Loop() { + 180 .loc 1 52 17 + 181 .cfi_startproc + 182 @ args = 0, pretend = 0, frame = 0 + 183 @ frame_needed = 1, uses_anonymous_args = 0 + 184 0000 80B5 push {r7, lr} + 185 .cfi_def_cfa_offset 8 + 186 .cfi_offset 7, -8 + 187 .cfi_offset 14, -4 + 188 0002 00AF add r7, sp, #0 + 189 .cfi_def_cfa_register 7 + 53:Core/Src/AMS_HighLevel.c **** + 54:Core/Src/AMS_HighLevel.c **** // On Transition Functions called ones if the State Changed + 55:Core/Src/AMS_HighLevel.c **** + 56:Core/Src/AMS_HighLevel.c **** if (currentAMSState != lastAMSState) { + 190 .loc 1 56 23 + 191 0004 224B ldr r3, .L27 + 192 0006 1A78 ldrb r2, [r3] @ zero_extendqisi2 + 193 0008 224B ldr r3, .L27+4 + 194 000a 1B78 ldrb r3, [r3] @ zero_extendqisi2 + ARM GAS /tmp/cccWxVkc.s page 5 + + + 195 .loc 1 56 6 + 196 000c 9A42 cmp r2, r3 + 197 000e 19D0 beq .L5 + 57:Core/Src/AMS_HighLevel.c **** switch (currentAMSState) { + 198 .loc 1 57 5 + 199 0010 1F4B ldr r3, .L27 + 200 0012 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 201 0014 062B cmp r3, #6 + 202 0016 11D8 bhi .L6 + 203 0018 01A2 adr r2, .L8 + 204 001a 52F823F0 ldr pc, [r2, r3, lsl #2] + 205 001e 00BF .p2align 2 + 206 .L8: + 207 0020 3D000000 .word .L6+1 + 208 0024 3D000000 .word .L6+1 + 209 0028 3D000000 .word .L6+1 + 210 002c 3D000000 .word .L6+1 + 211 0030 3D000000 .word .L6+1 + 212 0034 3D000000 .word .L6+1 + 213 0038 3D000000 .word .L6+1 + 214 .p2align 1 + 215 .L6: + 58:Core/Src/AMS_HighLevel.c **** case AMSIDLE: + 59:Core/Src/AMS_HighLevel.c **** break; + 60:Core/Src/AMS_HighLevel.c **** case AMSDEACTIVE: + 61:Core/Src/AMS_HighLevel.c **** break; + 62:Core/Src/AMS_HighLevel.c **** case AMSCHARGING: + 63:Core/Src/AMS_HighLevel.c **** break; + 64:Core/Src/AMS_HighLevel.c **** case AMSIDLEBALANCING: + 65:Core/Src/AMS_HighLevel.c **** break; + 66:Core/Src/AMS_HighLevel.c **** case AMSDISCHARGING: + 67:Core/Src/AMS_HighLevel.c **** break; + 68:Core/Src/AMS_HighLevel.c **** case AMSWARNING: + 69:Core/Src/AMS_HighLevel.c **** break; + 70:Core/Src/AMS_HighLevel.c **** case AMSERROR: + 71:Core/Src/AMS_HighLevel.c **** break; + 72:Core/Src/AMS_HighLevel.c **** } + 73:Core/Src/AMS_HighLevel.c **** lastAMSState = currentAMSState; + 216 .loc 1 73 18 + 217 003c 144B ldr r3, .L27 + 218 003e 1A78 ldrb r2, [r3] @ zero_extendqisi2 + 219 0040 144B ldr r3, .L27+4 + 220 0042 1A70 strb r2, [r3] + 221 .L5: + 74:Core/Src/AMS_HighLevel.c **** } + 75:Core/Src/AMS_HighLevel.c **** + 76:Core/Src/AMS_HighLevel.c **** // Main Loops for different AMS States + 77:Core/Src/AMS_HighLevel.c **** + 78:Core/Src/AMS_HighLevel.c **** switch (currentAMSState) { + 222 .loc 1 78 3 + 223 0044 124B ldr r3, .L27 + 224 0046 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 225 0048 062B cmp r3, #6 + 226 004a 1ED8 bhi .L24 + 227 004c 01A2 adr r2, .L17 + 228 004e 52F823F0 ldr pc, [r2, r3, lsl #2] + 229 0052 00BF .p2align 2 + ARM GAS /tmp/cccWxVkc.s page 6 + + + 230 .L17: + 231 0054 89000000 .word .L25+1 + 232 0058 71000000 .word .L22+1 + 233 005c 77000000 .word .L21+1 + 234 0060 7D000000 .word .L20+1 + 235 0064 89000000 .word .L25+1 + 236 0068 83000000 .word .L18+1 + 237 006c 89000000 .word .L25+1 + 238 .p2align 1 + 239 .L22: + 79:Core/Src/AMS_HighLevel.c **** case AMSIDLE: + 80:Core/Src/AMS_HighLevel.c **** AMS_Idle_Loop(); + 240 .loc 1 80 5 + 241 0070 FFF7FEFF bl AMS_Idle_Loop + 81:Core/Src/AMS_HighLevel.c **** break; + 242 .loc 1 81 5 + 243 0074 09E0 b .L15 + 244 .L21: + 82:Core/Src/AMS_HighLevel.c **** case AMSDEACTIVE: + 83:Core/Src/AMS_HighLevel.c **** break; + 84:Core/Src/AMS_HighLevel.c **** case AMSCHARGING: + 85:Core/Src/AMS_HighLevel.c **** AMS_Idle_Loop(); + 245 .loc 1 85 5 + 246 0076 FFF7FEFF bl AMS_Idle_Loop + 86:Core/Src/AMS_HighLevel.c **** break; + 247 .loc 1 86 5 + 248 007a 06E0 b .L15 + 249 .L20: + 87:Core/Src/AMS_HighLevel.c **** case AMSIDLEBALANCING: + 88:Core/Src/AMS_HighLevel.c **** AMS_Idle_Loop(); + 250 .loc 1 88 5 + 251 007c FFF7FEFF bl AMS_Idle_Loop + 89:Core/Src/AMS_HighLevel.c **** break; + 252 .loc 1 89 5 + 253 0080 03E0 b .L15 + 254 .L18: + 90:Core/Src/AMS_HighLevel.c **** case AMSDISCHARGING: + 91:Core/Src/AMS_HighLevel.c **** break; + 92:Core/Src/AMS_HighLevel.c **** case AMSWARNING: + 93:Core/Src/AMS_HighLevel.c **** AMS_Warning_Loop(); + 255 .loc 1 93 5 + 256 0082 FFF7FEFF bl AMS_Warning_Loop + 94:Core/Src/AMS_HighLevel.c **** break; + 257 .loc 1 94 5 + 258 0086 00E0 b .L15 + 259 .L25: + 83:Core/Src/AMS_HighLevel.c **** case AMSCHARGING: + 260 .loc 1 83 5 + 261 0088 00BF nop + 262 .L15: + 263 .L24: + 95:Core/Src/AMS_HighLevel.c **** case AMSERROR: + 96:Core/Src/AMS_HighLevel.c **** break; + 97:Core/Src/AMS_HighLevel.c **** } + 98:Core/Src/AMS_HighLevel.c **** } + 264 .loc 1 98 1 + 265 008a 00BF nop + ARM GAS /tmp/cccWxVkc.s page 7 + + + 266 008c 80BD pop {r7, pc} + 267 .L28: + 268 008e 00BF .align 2 + 269 .L27: + 270 0090 00000000 .word currentAMSState + 271 0094 00000000 .word lastAMSState + 272 .cfi_endproc + 273 .LFE131: + 275 .section .text.AMS_Idle_Loop,"ax",%progbits + 276 .align 1 + 277 .global AMS_Idle_Loop + 278 .syntax unified + 279 .thumb + 280 .thumb_func + 282 AMS_Idle_Loop: + 283 .LFB132: + 99:Core/Src/AMS_HighLevel.c **** + 100:Core/Src/AMS_HighLevel.c **** uint8_t AMS_Idle_Loop() { + 284 .loc 1 100 25 + 285 .cfi_startproc + 286 @ args = 0, pretend = 0, frame = 24 + 287 @ frame_needed = 1, uses_anonymous_args = 0 + 288 0000 2DE9B04F push {r4, r5, r7, r8, r9, r10, fp, lr} + 289 .cfi_def_cfa_offset 32 + 290 .cfi_offset 4, -32 + 291 .cfi_offset 5, -28 + 292 .cfi_offset 7, -24 + 293 .cfi_offset 8, -20 + 294 .cfi_offset 9, -16 + 295 .cfi_offset 10, -12 + 296 .cfi_offset 11, -8 + 297 .cfi_offset 14, -4 + 298 0004 88B0 sub sp, sp, #32 + 299 .cfi_def_cfa_offset 64 + 300 0006 02AF add r7, sp, #8 + 301 .cfi_def_cfa 7, 56 + 101:Core/Src/AMS_HighLevel.c **** if (!amsWakeUp()) { + 302 .loc 1 101 8 + 303 0008 FFF7FEFF bl amsWakeUp + 304 000c 0346 mov r3, r0 + 305 .loc 1 101 6 discriminator 1 + 306 000e 002B cmp r3, #0 + 307 0010 05D1 bne .L30 + 102:Core/Src/AMS_HighLevel.c **** error_data.data_kind = SEK_INTERNAL_BMS_TIMEOUT; //we don't receive data for the wakeup command + 308 .loc 1 102 26 + 309 0012 944B ldr r3, .L46 + 310 0014 0722 movs r2, #7 + 311 0016 5A80 strh r2, [r3, #2] @ movhi + 103:Core/Src/AMS_HighLevel.c **** set_error_source(ERROR_SOURCE_INTERNAL); //so we can't tell if we timed out + 312 .loc 1 103 5 + 313 0018 2020 movs r0, #32 + 314 001a FFF7FEFF bl set_error_source + 315 .L30: + 104:Core/Src/AMS_HighLevel.c **** } + 105:Core/Src/AMS_HighLevel.c **** + 106:Core/Src/AMS_HighLevel.c **** packetChecksumFails += amsAuxAndStatusMeasurement(&module); + 316 .loc 1 106 26 + ARM GAS /tmp/cccWxVkc.s page 8 + + + 317 001e 9248 ldr r0, .L46+4 + 318 0020 FFF7FEFF bl amsAuxAndStatusMeasurement + 319 0024 0346 mov r3, r0 + 320 0026 1A46 mov r2, r3 + 321 .loc 1 106 23 discriminator 1 + 322 0028 904B ldr r3, .L46+8 + 323 002a 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 324 002c 1344 add r3, r3, r2 + 325 002e DAB2 uxtb r2, r3 + 326 0030 8E4B ldr r3, .L46+8 + 327 0032 1A70 strb r2, [r3] + 107:Core/Src/AMS_HighLevel.c **** + 108:Core/Src/AMS_HighLevel.c **** if (module.status.SLEEP) { + 328 .loc 1 108 7 + 329 0034 8C4B ldr r3, .L46+4 + 330 0036 93F84D30 ldrb r3, [r3, #77] @ zero_extendqisi2 + 331 003a 03F01003 and r3, r3, #16 + 332 003e DBB2 uxtb r3, r3 + 333 .loc 1 108 6 + 334 0040 002B cmp r3, #0 + 335 0042 12D0 beq .L31 + 109:Core/Src/AMS_HighLevel.c **** deviceSleeps++; + 336 .loc 1 109 17 + 337 0044 8A4B ldr r3, .L46+12 + 338 0046 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 339 0048 0133 adds r3, r3, #1 + 340 004a DAB2 uxtb r2, r3 + 341 004c 884B ldr r3, .L46+12 + 342 004e 1A70 strb r2, [r3] + 110:Core/Src/AMS_HighLevel.c **** if (deviceSleeps > MAX_DEVICE_SLEEP) { + 343 .loc 1 110 22 + 344 0050 874B ldr r3, .L46+12 + 345 0052 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 346 .loc 1 110 8 + 347 0054 032B cmp r3, #3 + 348 0056 06D9 bls .L32 + 111:Core/Src/AMS_HighLevel.c **** error_data.data_kind = SEK_INTERNAL_BMS_TIMEOUT; + 349 .loc 1 111 28 + 350 0058 824B ldr r3, .L46 + 351 005a 0722 movs r2, #7 + 352 005c 5A80 strh r2, [r3, #2] @ movhi + 112:Core/Src/AMS_HighLevel.c **** set_error_source(ERROR_SOURCE_INTERNAL); + 353 .loc 1 112 7 + 354 005e 2020 movs r0, #32 + 355 0060 FFF7FEFF bl set_error_source + 356 0064 01E0 b .L31 + 357 .L32: + 113:Core/Src/AMS_HighLevel.c **** } else { + 114:Core/Src/AMS_HighLevel.c **** amsReset(); + 358 .loc 1 114 7 + 359 0066 FFF7FEFF bl amsReset + 360 .L31: + 115:Core/Src/AMS_HighLevel.c **** } + 116:Core/Src/AMS_HighLevel.c **** } + 117:Core/Src/AMS_HighLevel.c **** + 118:Core/Src/AMS_HighLevel.c **** if (module.status.CS_FLT || module.status.SPIFLT || module.status.CMED || + 361 .loc 1 118 20 + ARM GAS /tmp/cccWxVkc.s page 9 + + + 362 006a 7F4B ldr r3, .L46+4 + 363 006c B3F84830 ldrh r3, [r3, #72] + 364 .loc 1 118 6 + 365 0070 002B cmp r3, #0 + 366 0072 37D1 bne .L33 + 367 .loc 1 118 28 discriminator 1 + 368 0074 7C4B ldr r3, .L46+4 + 369 0076 93F84D30 ldrb r3, [r3, #77] @ zero_extendqisi2 + 370 007a 03F00803 and r3, r3, #8 + 371 007e DBB2 uxtb r3, r3 + 372 0080 002B cmp r3, #0 + 373 0082 2FD1 bne .L33 + 374 .loc 1 118 52 discriminator 2 + 375 0084 784B ldr r3, .L46+4 + 376 0086 93F84C30 ldrb r3, [r3, #76] @ zero_extendqisi2 + 377 008a 03F02003 and r3, r3, #32 + 378 008e DBB2 uxtb r3, r3 + 379 0090 002B cmp r3, #0 + 380 0092 27D1 bne .L33 + 381 .loc 1 118 74 discriminator 3 + 382 0094 744B ldr r3, .L46+4 + 383 0096 93F84C30 ldrb r3, [r3, #76] @ zero_extendqisi2 + 384 009a 23F07F03 bic r3, r3, #127 + 385 009e DBB2 uxtb r3, r3 + 386 00a0 002B cmp r3, #0 + 387 00a2 1FD1 bne .L33 + 119:Core/Src/AMS_HighLevel.c **** module.status.SMED || module.status.VDE || module.status.VDEL || + 388 .loc 1 119 26 + 389 00a4 704B ldr r3, .L46+4 + 390 00a6 93F84D30 ldrb r3, [r3, #77] @ zero_extendqisi2 + 391 00aa 03F00203 and r3, r3, #2 + 392 00ae DBB2 uxtb r3, r3 + 393 00b0 002B cmp r3, #0 + 394 00b2 17D1 bne .L33 + 395 .loc 1 119 47 discriminator 1 + 396 00b4 6C4B ldr r3, .L46+4 + 397 00b6 93F84D30 ldrb r3, [r3, #77] @ zero_extendqisi2 + 398 00ba 03F00103 and r3, r3, #1 + 399 00be DBB2 uxtb r3, r3 + 400 00c0 002B cmp r3, #0 + 401 00c2 0FD1 bne .L33 + 402 .loc 1 119 69 discriminator 2 + 403 00c4 684B ldr r3, .L46+4 + 404 00c6 93F84D30 ldrb r3, [r3, #77] @ zero_extendqisi2 + 405 00ca 23F07F03 bic r3, r3, #127 + 406 00ce DBB2 uxtb r3, r3 + 407 00d0 002B cmp r3, #0 + 408 00d2 07D1 bne .L33 + 120:Core/Src/AMS_HighLevel.c **** module.status.OSCCHK || module.status.TMODCHK) { + 409 .loc 1 120 27 + 410 00d4 644B ldr r3, .L46+4 + 411 00d6 93F84D30 ldrb r3, [r3, #77] @ zero_extendqisi2 + 412 00da 03F04003 and r3, r3, #64 + 413 00de DBB2 uxtb r3, r3 + 414 00e0 002B cmp r3, #0 + 415 00e2 05D0 beq .L34 + 416 .L33: + ARM GAS /tmp/cccWxVkc.s page 10 + + + 121:Core/Src/AMS_HighLevel.c **** error_data.data_kind = SEK_INTERNAL_BMS_FAULT; + 417 .loc 1 121 26 + 418 00e4 5F4B ldr r3, .L46 + 419 00e6 0A22 movs r2, #10 + 420 00e8 5A80 strh r2, [r3, #2] @ movhi + 122:Core/Src/AMS_HighLevel.c **** set_error_source(ERROR_SOURCE_INTERNAL); + 421 .loc 1 122 5 + 422 00ea 2020 movs r0, #32 + 423 00ec FFF7FEFF bl set_error_source + 424 .L34: + 123:Core/Src/AMS_HighLevel.c **** } + 124:Core/Src/AMS_HighLevel.c **** + 125:Core/Src/AMS_HighLevel.c **** if (module.status.THSD) { + 425 .loc 1 125 7 + 426 00f0 5D4B ldr r3, .L46+4 + 427 00f2 93F84D30 ldrb r3, [r3, #77] @ zero_extendqisi2 + 428 00f6 03F02003 and r3, r3, #32 + 429 00fa DBB2 uxtb r3, r3 + 430 .loc 1 125 6 + 431 00fc 002B cmp r3, #0 + 432 00fe 05D0 beq .L35 + 126:Core/Src/AMS_HighLevel.c **** error_data.data_kind = SEK_INTERNAL_BMS_OVERTEMP; + 433 .loc 1 126 26 + 434 0100 584B ldr r3, .L46 + 435 0102 0922 movs r2, #9 + 436 0104 5A80 strh r2, [r3, #2] @ movhi + 127:Core/Src/AMS_HighLevel.c **** set_error_source(ERROR_SOURCE_INTERNAL); + 437 .loc 1 127 5 + 438 0106 2020 movs r0, #32 + 439 0108 FFF7FEFF bl set_error_source + 440 .L35: + 128:Core/Src/AMS_HighLevel.c **** } + 129:Core/Src/AMS_HighLevel.c **** + 130:Core/Src/AMS_HighLevel.c **** packetChecksumFails += amsCellMeasurement(&module); + 441 .loc 1 130 26 + 442 010c 5648 ldr r0, .L46+4 + 443 010e FFF7FEFF bl amsCellMeasurement + 444 0112 0346 mov r3, r0 + 445 0114 1A46 mov r2, r3 + 446 .loc 1 130 23 discriminator 1 + 447 0116 554B ldr r3, .L46+8 + 448 0118 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 449 011a 1344 add r3, r3, r2 + 450 011c DAB2 uxtb r2, r3 + 451 011e 534B ldr r3, .L46+8 + 452 0120 1A70 strb r2, [r3] + 131:Core/Src/AMS_HighLevel.c **** packetChecksumFails += amsCheckUnderOverVoltage(&module); + 453 .loc 1 131 26 + 454 0122 5148 ldr r0, .L46+4 + 455 0124 FFF7FEFF bl amsCheckUnderOverVoltage + 456 0128 0346 mov r3, r0 + 457 012a 1A46 mov r2, r3 + 458 .loc 1 131 23 discriminator 1 + 459 012c 4F4B ldr r3, .L46+8 + 460 012e 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 461 0130 1344 add r3, r3, r2 + 462 0132 DAB2 uxtb r2, r3 + ARM GAS /tmp/cccWxVkc.s page 11 + + + 463 0134 4D4B ldr r3, .L46+8 + 464 0136 1A70 strb r2, [r3] + 132:Core/Src/AMS_HighLevel.c **** + 133:Core/Src/AMS_HighLevel.c **** if (packetChecksumFails > MAX_PACKET_CHECKSUM_FAILS) { + 465 .loc 1 133 27 + 466 0138 4C4B ldr r3, .L46+8 + 467 013a 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 468 .loc 1 133 6 + 469 013c 052B cmp r3, #5 + 470 013e 05D9 bls .L36 + 134:Core/Src/AMS_HighLevel.c **** error_data.data_kind = SEK_INTERNAL_BMS_CHECKSUM_FAIL; + 471 .loc 1 134 26 + 472 0140 484B ldr r3, .L46 + 473 0142 0822 movs r2, #8 + 474 0144 5A80 strh r2, [r3, #2] @ movhi + 135:Core/Src/AMS_HighLevel.c **** set_error_source(ERROR_SOURCE_INTERNAL); + 475 .loc 1 135 5 + 476 0146 2020 movs r0, #32 + 477 0148 FFF7FEFF bl set_error_source + 478 .L36: + 136:Core/Src/AMS_HighLevel.c **** } + 137:Core/Src/AMS_HighLevel.c **** + 138:Core/Src/AMS_HighLevel.c **** int any_voltage_error = 0; + 479 .loc 1 138 7 + 480 014c 0023 movs r3, #0 + 481 014e 7B61 str r3, [r7, #20] + 482 .LBB2: + 139:Core/Src/AMS_HighLevel.c **** for (size_t i = 0; i < numberofCells; i++) { + 483 .loc 1 139 15 + 484 0150 0023 movs r3, #0 + 485 0152 3B61 str r3, [r7, #16] + 486 .loc 1 139 3 + 487 0154 48E0 b .L37 + 488 .L40: + 140:Core/Src/AMS_HighLevel.c **** if (module.cellVoltages[i] < MIN_CELL_VOLTAGE) { + 489 .loc 1 140 28 + 490 0156 444A ldr r2, .L46+4 + 491 0158 3B69 ldr r3, [r7, #16] + 492 015a 32F91330 ldrsh r3, [r2, r3, lsl #1] + 493 .loc 1 140 8 + 494 015e B3F5486F cmp r3, #3200 + 495 0162 1BDA bge .L38 + 496 .LBB3: + 141:Core/Src/AMS_HighLevel.c **** any_voltage_error = 1; + 497 .loc 1 141 25 + 498 0164 0123 movs r3, #1 + 499 0166 7B61 str r3, [r7, #20] + 142:Core/Src/AMS_HighLevel.c **** error_data.data_kind = SEK_UNDERVOLT; + 500 .loc 1 142 28 + 501 0168 3E4B ldr r3, .L46 + 502 016a 0322 movs r2, #3 + 503 016c 5A80 strh r2, [r3, #2] @ movhi + 143:Core/Src/AMS_HighLevel.c **** error_data.data[0] = i; + 504 .loc 1 143 26 + 505 016e 3B69 ldr r3, [r7, #16] + 506 0170 DAB2 uxtb r2, r3 + 507 0172 3C4B ldr r3, .L46 + ARM GAS /tmp/cccWxVkc.s page 12 + + + 508 0174 1A71 strb r2, [r3, #4] + 144:Core/Src/AMS_HighLevel.c **** uint8_t* ptr = &error_data.data[1]; + 509 .loc 1 144 16 + 510 0176 3F4B ldr r3, .L46+16 + 511 0178 7B60 str r3, [r7, #4] + 145:Core/Src/AMS_HighLevel.c **** ptr = ftcan_marshal_unsigned(ptr, module.cellVoltages[i], 2); + 512 .loc 1 145 60 + 513 017a 3B4A ldr r2, .L46+4 + 514 017c 3B69 ldr r3, [r7, #16] + 515 017e 32F91330 ldrsh r3, [r2, r3, lsl #1] + 516 .loc 1 145 13 + 517 0182 1BB2 sxth r3, r3 + 518 0184 DA17 asrs r2, r3, #31 + 519 0186 9846 mov r8, r3 + 520 0188 9146 mov r9, r2 + 521 018a 0223 movs r3, #2 + 522 018c 0093 str r3, [sp] + 523 018e 4246 mov r2, r8 + 524 0190 4B46 mov r3, r9 + 525 0192 7868 ldr r0, [r7, #4] + 526 0194 FFF7FEFF bl ftcan_marshal_unsigned + 527 0198 7860 str r0, [r7, #4] + 528 .LBE3: + 529 019a 22E0 b .L39 + 530 .L38: + 146:Core/Src/AMS_HighLevel.c **** } else if (module.cellVoltages[i] > MAX_CELL_VOLTAGE) { + 531 .loc 1 146 35 + 532 019c 324A ldr r2, .L46+4 + 533 019e 3B69 ldr r3, [r7, #16] + 534 01a0 32F91330 ldrsh r3, [r2, r3, lsl #1] + 535 .loc 1 146 15 + 536 01a4 41F26802 movw r2, #4200 + 537 01a8 9342 cmp r3, r2 + 538 01aa 1ADD ble .L39 + 539 .LBB4: + 147:Core/Src/AMS_HighLevel.c **** any_voltage_error = 1; + 540 .loc 1 147 25 + 541 01ac 0123 movs r3, #1 + 542 01ae 7B61 str r3, [r7, #20] + 148:Core/Src/AMS_HighLevel.c **** error_data.data_kind = SEK_OVERVOLT; + 543 .loc 1 148 28 + 544 01b0 2C4B ldr r3, .L46 + 545 01b2 0222 movs r2, #2 + 546 01b4 5A80 strh r2, [r3, #2] @ movhi + 149:Core/Src/AMS_HighLevel.c **** error_data.data[0] = i; + 547 .loc 1 149 26 + 548 01b6 3B69 ldr r3, [r7, #16] + 549 01b8 DAB2 uxtb r2, r3 + 550 01ba 2A4B ldr r3, .L46 + 551 01bc 1A71 strb r2, [r3, #4] + 150:Core/Src/AMS_HighLevel.c **** uint8_t* ptr = &error_data.data[1]; + 552 .loc 1 150 16 + 553 01be 2D4B ldr r3, .L46+16 + 554 01c0 BB60 str r3, [r7, #8] + 151:Core/Src/AMS_HighLevel.c **** ptr = ftcan_marshal_unsigned(ptr, module.cellVoltages[i], 2); + 555 .loc 1 151 60 + 556 01c2 294A ldr r2, .L46+4 + ARM GAS /tmp/cccWxVkc.s page 13 + + + 557 01c4 3B69 ldr r3, [r7, #16] + 558 01c6 32F91330 ldrsh r3, [r2, r3, lsl #1] + 559 .loc 1 151 13 + 560 01ca 1BB2 sxth r3, r3 + 561 01cc DA17 asrs r2, r3, #31 + 562 01ce 9A46 mov r10, r3 + 563 01d0 9346 mov fp, r2 + 564 01d2 0223 movs r3, #2 + 565 01d4 0093 str r3, [sp] + 566 01d6 5246 mov r2, r10 + 567 01d8 5B46 mov r3, fp + 568 01da B868 ldr r0, [r7, #8] + 569 01dc FFF7FEFF bl ftcan_marshal_unsigned + 570 01e0 B860 str r0, [r7, #8] + 571 .L39: + 572 .LBE4: + 139:Core/Src/AMS_HighLevel.c **** if (module.cellVoltages[i] < MIN_CELL_VOLTAGE) { + 573 .loc 1 139 42 discriminator 2 + 574 01e2 3B69 ldr r3, [r7, #16] + 575 01e4 0133 adds r3, r3, #1 + 576 01e6 3B61 str r3, [r7, #16] + 577 .L37: + 139:Core/Src/AMS_HighLevel.c **** if (module.cellVoltages[i] < MIN_CELL_VOLTAGE) { + 578 .loc 1 139 24 discriminator 1 + 579 01e8 234B ldr r3, .L46+20 + 580 01ea 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 581 01ec 1A46 mov r2, r3 + 582 01ee 3B69 ldr r3, [r7, #16] + 583 01f0 9342 cmp r3, r2 + 584 01f2 B0D3 bcc .L40 + 585 .LBE2: + 152:Core/Src/AMS_HighLevel.c **** } + 153:Core/Src/AMS_HighLevel.c **** } + 154:Core/Src/AMS_HighLevel.c **** + 155:Core/Src/AMS_HighLevel.c **** if (module.internalDieTemp > 28000) { //TODO: change to correct value + 586 .loc 1 155 13 + 587 01f4 1C4B ldr r3, .L46+4 + 588 01f6 B3F84E30 ldrh r3, [r3, #78] + 589 .loc 1 155 6 + 590 01fa 46F66052 movw r2, #28000 + 591 01fe 9342 cmp r3, r2 + 592 0200 17D9 bls .L41 + 593 .LBB5: + 156:Core/Src/AMS_HighLevel.c **** error_data.data_kind = SEK_INTERNAL_BMS_OVERTEMP; + 594 .loc 1 156 26 + 595 0202 184B ldr r3, .L46 + 596 0204 0922 movs r2, #9 + 597 0206 5A80 strh r2, [r3, #2] @ movhi + 157:Core/Src/AMS_HighLevel.c **** uint8_t* ptr = &error_data.data[0]; + 598 .loc 1 157 14 + 599 0208 1C4B ldr r3, .L46+24 + 600 020a FB60 str r3, [r7, #12] + 158:Core/Src/AMS_HighLevel.c **** ptr = ftcan_marshal_unsigned(ptr, module.internalDieTemp, 2); + 601 .loc 1 158 45 + 602 020c 164B ldr r3, .L46+4 + 603 020e B3F84E30 ldrh r3, [r3, #78] + 604 .loc 1 158 11 + ARM GAS /tmp/cccWxVkc.s page 14 + + + 605 0212 9BB2 uxth r3, r3 + 606 0214 0022 movs r2, #0 + 607 0216 1C46 mov r4, r3 + 608 0218 1546 mov r5, r2 + 609 021a 0223 movs r3, #2 + 610 021c 0093 str r3, [sp] + 611 021e 2246 mov r2, r4 + 612 0220 2B46 mov r3, r5 + 613 0222 F868 ldr r0, [r7, #12] + 614 0224 FFF7FEFF bl ftcan_marshal_unsigned + 615 0228 F860 str r0, [r7, #12] + 159:Core/Src/AMS_HighLevel.c **** + 160:Core/Src/AMS_HighLevel.c **** set_error_source(ERROR_SOURCE_INTERNAL); + 616 .loc 1 160 5 + 617 022a 2020 movs r0, #32 + 618 022c FFF7FEFF bl set_error_source + 619 .LBE5: + 620 0230 02E0 b .L42 + 621 .L41: + 161:Core/Src/AMS_HighLevel.c **** } else { + 162:Core/Src/AMS_HighLevel.c **** clear_error_source(ERROR_SOURCE_INTERNAL); + 622 .loc 1 162 5 + 623 0232 2020 movs r0, #32 + 624 0234 FFF7FEFF bl clear_error_source + 625 .L42: + 163:Core/Src/AMS_HighLevel.c **** } + 164:Core/Src/AMS_HighLevel.c **** + 165:Core/Src/AMS_HighLevel.c **** if (any_voltage_error) { + 626 .loc 1 165 6 + 627 0238 7B69 ldr r3, [r7, #20] + 628 023a 002B cmp r3, #0 + 629 023c 03D0 beq .L43 + 166:Core/Src/AMS_HighLevel.c **** set_error_source(ERROR_SOURCE_VOLTAGES); + 630 .loc 1 166 5 + 631 023e 0120 movs r0, #1 + 632 0240 FFF7FEFF bl set_error_source + 633 0244 02E0 b .L44 + 634 .L43: + 167:Core/Src/AMS_HighLevel.c **** } else { + 168:Core/Src/AMS_HighLevel.c **** clear_error_source(ERROR_SOURCE_VOLTAGES); + 635 .loc 1 168 5 + 636 0246 0120 movs r0, #1 + 637 0248 FFF7FEFF bl clear_error_source + 638 .L44: + 169:Core/Src/AMS_HighLevel.c **** } + 170:Core/Src/AMS_HighLevel.c **** + 171:Core/Src/AMS_HighLevel.c **** mcuDelay(10); + 639 .loc 1 171 3 + 640 024c 0A20 movs r0, #10 + 641 024e FFF7FEFF bl mcuDelay + 172:Core/Src/AMS_HighLevel.c **** + 173:Core/Src/AMS_HighLevel.c **** AMS_Balancing_Loop(); + 642 .loc 1 173 3 + 643 0252 FFF7FEFF bl AMS_Balancing_Loop + 174:Core/Src/AMS_HighLevel.c **** return 0; + 644 .loc 1 174 10 + 645 0256 0023 movs r3, #0 + ARM GAS /tmp/cccWxVkc.s page 15 + + + 175:Core/Src/AMS_HighLevel.c **** } + 646 .loc 1 175 1 + 647 0258 1846 mov r0, r3 + 648 025a 1837 adds r7, r7, #24 + 649 .cfi_def_cfa_offset 32 + 650 025c BD46 mov sp, r7 + 651 .cfi_def_cfa_register 13 + 652 @ sp needed + 653 025e BDE8B08F pop {r4, r5, r7, r8, r9, r10, fp, pc} + 654 .L47: + 655 0262 00BF .align 2 + 656 .L46: + 657 0264 00000000 .word error_data + 658 0268 00000000 .word module + 659 026c 00000000 .word packetChecksumFails + 660 0270 00000000 .word deviceSleeps + 661 0274 05000000 .word error_data+5 + 662 0278 00000000 .word numberofCells + 663 027c 04000000 .word error_data+4 + 664 .cfi_endproc + 665 .LFE132: + 667 .section .text.AMS_Warning_Loop,"ax",%progbits + 668 .align 1 + 669 .global AMS_Warning_Loop + 670 .syntax unified + 671 .thumb + 672 .thumb_func + 674 AMS_Warning_Loop: + 675 .LFB133: + 176:Core/Src/AMS_HighLevel.c **** + 177:Core/Src/AMS_HighLevel.c **** uint8_t AMS_Warning_Loop() { return 0; } + 676 .loc 1 177 28 + 677 .cfi_startproc + 678 @ args = 0, pretend = 0, frame = 0 + 679 @ frame_needed = 1, uses_anonymous_args = 0 + 680 @ link register save eliminated. + 681 0000 80B4 push {r7} + 682 .cfi_def_cfa_offset 4 + 683 .cfi_offset 7, -4 + 684 0002 00AF add r7, sp, #0 + 685 .cfi_def_cfa_register 7 + 686 .loc 1 177 37 + 687 0004 0023 movs r3, #0 + 688 .loc 1 177 40 + 689 0006 1846 mov r0, r3 + 690 0008 BD46 mov sp, r7 + 691 .cfi_def_cfa_register 13 + 692 @ sp needed + 693 000a 5DF8047B ldr r7, [sp], #4 + 694 .cfi_restore 7 + 695 .cfi_def_cfa_offset 0 + 696 000e 7047 bx lr + 697 .cfi_endproc + 698 .LFE133: + 700 .section .text.AMS_Error_Loop,"ax",%progbits + 701 .align 1 + 702 .global AMS_Error_Loop + ARM GAS /tmp/cccWxVkc.s page 16 + + + 703 .syntax unified + 704 .thumb + 705 .thumb_func + 707 AMS_Error_Loop: + 708 .LFB134: + 178:Core/Src/AMS_HighLevel.c **** + 179:Core/Src/AMS_HighLevel.c **** uint8_t AMS_Error_Loop() { return 0; } + 709 .loc 1 179 26 + 710 .cfi_startproc + 711 @ args = 0, pretend = 0, frame = 0 + 712 @ frame_needed = 1, uses_anonymous_args = 0 + 713 @ link register save eliminated. + 714 0000 80B4 push {r7} + 715 .cfi_def_cfa_offset 4 + 716 .cfi_offset 7, -4 + 717 0002 00AF add r7, sp, #0 + 718 .cfi_def_cfa_register 7 + 719 .loc 1 179 35 + 720 0004 0023 movs r3, #0 + 721 .loc 1 179 38 + 722 0006 1846 mov r0, r3 + 723 0008 BD46 mov sp, r7 + 724 .cfi_def_cfa_register 13 + 725 @ sp needed + 726 000a 5DF8047B ldr r7, [sp], #4 + 727 .cfi_restore 7 + 728 .cfi_def_cfa_offset 0 + 729 000e 7047 bx lr + 730 .cfi_endproc + 731 .LFE134: + 733 .section .text.AMS_Charging_Loop,"ax",%progbits + 734 .align 1 + 735 .global AMS_Charging_Loop + 736 .syntax unified + 737 .thumb + 738 .thumb_func + 740 AMS_Charging_Loop: + 741 .LFB135: + 180:Core/Src/AMS_HighLevel.c **** + 181:Core/Src/AMS_HighLevel.c **** uint8_t AMS_Charging_Loop() { return 0; } + 742 .loc 1 181 29 + 743 .cfi_startproc + 744 @ args = 0, pretend = 0, frame = 0 + 745 @ frame_needed = 1, uses_anonymous_args = 0 + 746 @ link register save eliminated. + 747 0000 80B4 push {r7} + 748 .cfi_def_cfa_offset 4 + 749 .cfi_offset 7, -4 + 750 0002 00AF add r7, sp, #0 + 751 .cfi_def_cfa_register 7 + 752 .loc 1 181 38 + 753 0004 0023 movs r3, #0 + 754 .loc 1 181 41 + 755 0006 1846 mov r0, r3 + 756 0008 BD46 mov sp, r7 + 757 .cfi_def_cfa_register 13 + 758 @ sp needed + ARM GAS /tmp/cccWxVkc.s page 17 + + + 759 000a 5DF8047B ldr r7, [sp], #4 + 760 .cfi_restore 7 + 761 .cfi_def_cfa_offset 0 + 762 000e 7047 bx lr + 763 .cfi_endproc + 764 .LFE135: + 766 .section .text.AMS_Discharging_Loop,"ax",%progbits + 767 .align 1 + 768 .global AMS_Discharging_Loop + 769 .syntax unified + 770 .thumb + 771 .thumb_func + 773 AMS_Discharging_Loop: + 774 .LFB136: + 182:Core/Src/AMS_HighLevel.c **** + 183:Core/Src/AMS_HighLevel.c **** uint8_t AMS_Discharging_Loop() { return 0; } + 775 .loc 1 183 32 + 776 .cfi_startproc + 777 @ args = 0, pretend = 0, frame = 0 + 778 @ frame_needed = 1, uses_anonymous_args = 0 + 779 @ link register save eliminated. + 780 0000 80B4 push {r7} + 781 .cfi_def_cfa_offset 4 + 782 .cfi_offset 7, -4 + 783 0002 00AF add r7, sp, #0 + 784 .cfi_def_cfa_register 7 + 785 .loc 1 183 41 + 786 0004 0023 movs r3, #0 + 787 .loc 1 183 44 + 788 0006 1846 mov r0, r3 + 789 0008 BD46 mov sp, r7 + 790 .cfi_def_cfa_register 13 + 791 @ sp needed + 792 000a 5DF8047B ldr r7, [sp], #4 + 793 .cfi_restore 7 + 794 .cfi_def_cfa_offset 0 + 795 000e 7047 bx lr + 796 .cfi_endproc + 797 .LFE136: + 799 .section .text.AMS_Balancing_Loop,"ax",%progbits + 800 .align 1 + 801 .global AMS_Balancing_Loop + 802 .syntax unified + 803 .thumb + 804 .thumb_func + 806 AMS_Balancing_Loop: + 807 .LFB137: + 184:Core/Src/AMS_HighLevel.c **** + 185:Core/Src/AMS_HighLevel.c **** uint8_t AMS_Balancing_Loop() { + 808 .loc 1 185 30 + 809 .cfi_startproc + 810 @ args = 0, pretend = 0, frame = 16 + 811 @ frame_needed = 1, uses_anonymous_args = 0 + 812 0000 80B5 push {r7, lr} + 813 .cfi_def_cfa_offset 8 + 814 .cfi_offset 7, -8 + 815 .cfi_offset 14, -4 + ARM GAS /tmp/cccWxVkc.s page 18 + + + 816 0002 84B0 sub sp, sp, #16 + 817 .cfi_def_cfa_offset 24 + 818 0004 00AF add r7, sp, #0 + 819 .cfi_def_cfa_register 7 + 186:Core/Src/AMS_HighLevel.c **** uint8_t id_cell_lowest_voltage = 0; + 820 .loc 1 186 11 + 821 0006 0023 movs r3, #0 + 822 0008 FB73 strb r3, [r7, #15] + 187:Core/Src/AMS_HighLevel.c **** uint8_t num_of_cells_to_balance = 0; + 823 .loc 1 187 11 + 824 000a 0023 movs r3, #0 + 825 000c BB73 strb r3, [r7, #14] + 188:Core/Src/AMS_HighLevel.c **** uint32_t channels = 0; + 826 .loc 1 188 12 + 827 000e 0023 movs r3, #0 + 828 0010 BB60 str r3, [r7, #8] + 829 .LBB6: + 189:Core/Src/AMS_HighLevel.c **** for (int i = 0; i < 13; i++) { + 830 .loc 1 189 12 + 831 0012 0023 movs r3, #0 + 832 0014 7B60 str r3, [r7, #4] + 833 .loc 1 189 3 + 834 0016 0EE0 b .L57 + 835 .L59: + 190:Core/Src/AMS_HighLevel.c **** if (module.cellVoltages[i] < module.cellVoltages[id_cell_lowest_voltage]) + 836 .loc 1 190 28 + 837 0018 224A ldr r2, .L65 + 838 001a 7B68 ldr r3, [r7, #4] + 839 001c 32F91320 ldrsh r2, [r2, r3, lsl #1] + 840 .loc 1 190 53 + 841 0020 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 842 0022 2049 ldr r1, .L65 + 843 0024 31F91330 ldrsh r3, [r1, r3, lsl #1] + 844 .loc 1 190 8 + 845 0028 9A42 cmp r2, r3 + 846 002a 01DA bge .L58 + 191:Core/Src/AMS_HighLevel.c **** id_cell_lowest_voltage = i; + 847 .loc 1 191 30 + 848 002c 7B68 ldr r3, [r7, #4] + 849 002e FB73 strb r3, [r7, #15] + 850 .L58: + 189:Core/Src/AMS_HighLevel.c **** for (int i = 0; i < 13; i++) { + 851 .loc 1 189 28 discriminator 2 + 852 0030 7B68 ldr r3, [r7, #4] + 853 0032 0133 adds r3, r3, #1 + 854 0034 7B60 str r3, [r7, #4] + 855 .L57: + 189:Core/Src/AMS_HighLevel.c **** for (int i = 0; i < 13; i++) { + 856 .loc 1 189 21 discriminator 1 + 857 0036 7B68 ldr r3, [r7, #4] + 858 0038 0C2B cmp r3, #12 + 859 003a EDDD ble .L59 + 860 .LBE6: + 861 .LBB7: + 192:Core/Src/AMS_HighLevel.c **** } + 193:Core/Src/AMS_HighLevel.c **** + 194:Core/Src/AMS_HighLevel.c **** for (int i = 0; i < 13; i++) { + ARM GAS /tmp/cccWxVkc.s page 19 + + + 862 .loc 1 194 12 + 863 003c 0023 movs r3, #0 + 864 003e 3B60 str r3, [r7] + 865 .loc 1 194 3 + 866 0040 18E0 b .L60 + 867 .L62: + 195:Core/Src/AMS_HighLevel.c **** if (module.cellVoltages[i] - CELL_VOLTAGE_DIFF_BALANCING < module.cellVoltages[id_cell_lowest_v + 868 .loc 1 195 28 + 869 0042 184A ldr r2, .L65 + 870 0044 3B68 ldr r3, [r7] + 871 0046 32F91330 ldrsh r3, [r2, r3, lsl #1] + 872 .loc 1 195 62 + 873 004a 133B subs r3, r3, #19 + 874 .loc 1 195 83 + 875 004c FA7B ldrb r2, [r7, #15] @ zero_extendqisi2 + 876 004e 1549 ldr r1, .L65 + 877 0050 31F91220 ldrsh r2, [r1, r2, lsl #1] + 878 .loc 1 195 8 + 879 0054 9342 cmp r3, r2 + 880 0056 0ADC bgt .L61 + 196:Core/Src/AMS_HighLevel.c **** channels |= 1 << i; + 881 .loc 1 196 21 + 882 0058 0122 movs r2, #1 + 883 005a 3B68 ldr r3, [r7] + 884 005c 02FA03F3 lsl r3, r2, r3 + 885 0060 1A46 mov r2, r3 + 886 .loc 1 196 16 + 887 0062 BB68 ldr r3, [r7, #8] + 888 0064 1343 orrs r3, r3, r2 + 889 0066 BB60 str r3, [r7, #8] + 197:Core/Src/AMS_HighLevel.c **** num_of_cells_to_balance++; + 890 .loc 1 197 30 + 891 0068 BB7B ldrb r3, [r7, #14] @ zero_extendqisi2 + 892 006a 0133 adds r3, r3, #1 + 893 006c BB73 strb r3, [r7, #14] + 894 .L61: + 194:Core/Src/AMS_HighLevel.c **** if (module.cellVoltages[i] - CELL_VOLTAGE_DIFF_BALANCING < module.cellVoltages[id_cell_lowest_v + 895 .loc 1 194 28 discriminator 2 + 896 006e 3B68 ldr r3, [r7] + 897 0070 0133 adds r3, r3, #1 + 898 0072 3B60 str r3, [r7] + 899 .L60: + 194:Core/Src/AMS_HighLevel.c **** if (module.cellVoltages[i] - CELL_VOLTAGE_DIFF_BALANCING < module.cellVoltages[id_cell_lowest_v + 900 .loc 1 194 21 discriminator 1 + 901 0074 3B68 ldr r3, [r7] + 902 0076 0C2B cmp r3, #12 + 903 0078 E3DD ble .L62 + 904 .LBE7: + 198:Core/Src/AMS_HighLevel.c **** } + 199:Core/Src/AMS_HighLevel.c **** } + 200:Core/Src/AMS_HighLevel.c **** + 201:Core/Src/AMS_HighLevel.c **** if (num_of_cells_to_balance == 0){ + 905 .loc 1 201 6 + 906 007a BB7B ldrb r3, [r7, #14] @ zero_extendqisi2 + 907 007c 002B cmp r3, #0 + 908 007e 04D1 bne .L63 + 202:Core/Src/AMS_HighLevel.c **** balancingActive = 0; + ARM GAS /tmp/cccWxVkc.s page 20 + + + 909 .loc 1 202 21 + 910 0080 094B ldr r3, .L65+4 + 911 0082 0022 movs r2, #0 + 912 0084 1A70 strb r2, [r3] + 203:Core/Src/AMS_HighLevel.c **** return 0; + 913 .loc 1 203 12 + 914 0086 0023 movs r3, #0 + 915 0088 07E0 b .L64 + 916 .L63: + 204:Core/Src/AMS_HighLevel.c **** } + 205:Core/Src/AMS_HighLevel.c **** + 206:Core/Src/AMS_HighLevel.c **** amsConfigBalancing(channels, 0xF); + 917 .loc 1 206 3 + 918 008a 0F21 movs r1, #15 + 919 008c B868 ldr r0, [r7, #8] + 920 008e FFF7FEFF bl amsConfigBalancing + 207:Core/Src/AMS_HighLevel.c **** balancingActive = 1; + 921 .loc 1 207 19 + 922 0092 054B ldr r3, .L65+4 + 923 0094 0122 movs r2, #1 + 924 0096 1A70 strb r2, [r3] + 208:Core/Src/AMS_HighLevel.c **** return 0; + 925 .loc 1 208 10 + 926 0098 0023 movs r3, #0 + 927 .L64: + 209:Core/Src/AMS_HighLevel.c **** } + 928 .loc 1 209 1 + 929 009a 1846 mov r0, r3 + 930 009c 1037 adds r7, r7, #16 + 931 .cfi_def_cfa_offset 8 + 932 009e BD46 mov sp, r7 + 933 .cfi_def_cfa_register 13 + 934 @ sp needed + 935 00a0 80BD pop {r7, pc} + 936 .L66: + 937 00a2 00BF .align 2 + 938 .L65: + 939 00a4 00000000 .word module + 940 00a8 00000000 .word balancingActive + 941 .cfi_endproc + 942 .LFE137: + 944 .text + 945 .Letext0: + 946 .file 2 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 947 .file 3 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 948 .file 4 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + 949 .file 5 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/lib/gcc/arm-none-e + 950 .file 6 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h" + 951 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h" + 952 .file 8 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h" + 953 .file 9 "Core/Inc/ADBMS_LL_Driver.h" + 954 .file 10 "Core/Inc/ADBMS_Abstraction.h" + 955 .file 11 "Core/Inc/errors.h" + 956 .file 12 "Core/Inc/AMS_HighLevel.h" + 957 .file 13 "Core/Lib/can-halal/can-halal.h" + 958 .file 14 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h" + ARM GAS /tmp/cccWxVkc.s page 21 + + +DEFINED SYMBOLS + *ABS*:00000000 AMS_HighLevel.c + /tmp/cccWxVkc.s:25 .bss.module:00000000 module + /tmp/cccWxVkc.s:22 .bss.module:00000000 $d + /tmp/cccWxVkc.s:32 .bss.balancedCells:00000000 balancedCells + /tmp/cccWxVkc.s:29 .bss.balancedCells:00000000 $d + /tmp/cccWxVkc.s:38 .bss.balancingActive:00000000 balancingActive + /tmp/cccWxVkc.s:39 .bss.balancingActive:00000000 $d + /tmp/cccWxVkc.s:45 .bss.amsuv:00000000 amsuv + /tmp/cccWxVkc.s:42 .bss.amsuv:00000000 $d + /tmp/cccWxVkc.s:52 .bss.amsov:00000000 amsov + /tmp/cccWxVkc.s:49 .bss.amsov:00000000 $d + /tmp/cccWxVkc.s:58 .data.numberofCells:00000000 numberofCells + /tmp/cccWxVkc.s:64 .bss.numberofAux:00000000 numberofAux + /tmp/cccWxVkc.s:65 .bss.numberofAux:00000000 $d + /tmp/cccWxVkc.s:70 .bss.packetChecksumFails:00000000 packetChecksumFails + /tmp/cccWxVkc.s:71 .bss.packetChecksumFails:00000000 $d + /tmp/cccWxVkc.s:76 .bss.deviceSleeps:00000000 deviceSleeps + /tmp/cccWxVkc.s:77 .bss.deviceSleeps:00000000 $d + /tmp/cccWxVkc.s:82 .bss.currentAMSState:00000000 currentAMSState + /tmp/cccWxVkc.s:83 .bss.currentAMSState:00000000 $d + /tmp/cccWxVkc.s:88 .bss.lastAMSState:00000000 lastAMSState + /tmp/cccWxVkc.s:89 .bss.lastAMSState:00000000 $d + /tmp/cccWxVkc.s:95 .bss.pollingTimes:00000000 pollingTimes + /tmp/cccWxVkc.s:92 .bss.pollingTimes:00000000 $d + /tmp/cccWxVkc.s:98 .text.AMS_Init:00000000 $t + /tmp/cccWxVkc.s:104 .text.AMS_Init:00000000 AMS_Init + /tmp/cccWxVkc.s:162 .text.AMS_Init:0000004c $d + /tmp/cccWxVkc.s:172 .text.AMS_Loop:00000000 $t + /tmp/cccWxVkc.s:178 .text.AMS_Loop:00000000 AMS_Loop + /tmp/cccWxVkc.s:207 .text.AMS_Loop:00000020 $d + /tmp/cccWxVkc.s:214 .text.AMS_Loop:0000003c $t + /tmp/cccWxVkc.s:231 .text.AMS_Loop:00000054 $d + /tmp/cccWxVkc.s:238 .text.AMS_Loop:00000070 $t + /tmp/cccWxVkc.s:282 .text.AMS_Idle_Loop:00000000 AMS_Idle_Loop + /tmp/cccWxVkc.s:674 .text.AMS_Warning_Loop:00000000 AMS_Warning_Loop + /tmp/cccWxVkc.s:270 .text.AMS_Loop:00000090 $d + /tmp/cccWxVkc.s:276 .text.AMS_Idle_Loop:00000000 $t + /tmp/cccWxVkc.s:806 .text.AMS_Balancing_Loop:00000000 AMS_Balancing_Loop + /tmp/cccWxVkc.s:657 .text.AMS_Idle_Loop:00000264 $d + /tmp/cccWxVkc.s:668 .text.AMS_Warning_Loop:00000000 $t + /tmp/cccWxVkc.s:701 .text.AMS_Error_Loop:00000000 $t + /tmp/cccWxVkc.s:707 .text.AMS_Error_Loop:00000000 AMS_Error_Loop + /tmp/cccWxVkc.s:734 .text.AMS_Charging_Loop:00000000 $t + /tmp/cccWxVkc.s:740 .text.AMS_Charging_Loop:00000000 AMS_Charging_Loop + /tmp/cccWxVkc.s:767 .text.AMS_Discharging_Loop:00000000 $t + /tmp/cccWxVkc.s:773 .text.AMS_Discharging_Loop:00000000 AMS_Discharging_Loop + /tmp/cccWxVkc.s:800 .text.AMS_Balancing_Loop:00000000 $t + /tmp/cccWxVkc.s:939 .text.AMS_Balancing_Loop:000000a4 $d + +UNDEFINED SYMBOLS +initAMS +HAL_GetTick +amsWakeUp +set_error_source +amsAuxAndStatusMeasurement +amsReset + ARM GAS /tmp/cccWxVkc.s page 22 + + +amsCellMeasurement +amsCheckUnderOverVoltage +ftcan_marshal_unsigned +clear_error_source +mcuDelay +error_data +amsConfigBalancing diff --git a/Software/build/AMS_HighLevel.o b/Software/build/AMS_HighLevel.o new file mode 100644 index 0000000..fef697e Binary files /dev/null and b/Software/build/AMS_HighLevel.o differ diff --git a/Software/build/PWM_control.d b/Software/build/PWM_control.d new file mode 100644 index 0000000..6f9fc27 --- /dev/null +++ b/Software/build/PWM_control.d @@ -0,0 +1,86 @@ +build/PWM_control.o: Core/Src/PWM_control.c Core/Inc/PWM_control.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + Core/Inc/stm32f3xx_hal_conf.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h \ + Core/Inc/state_machine.h Core/Inc/ADBMS_LL_Driver.h Core/Inc/main.h \ + Core/Inc/AMS_HighLevel.h Core/Inc/ADBMS_Abstraction.h \ + Core/Inc/ADBMS_CMD_MAKROS.h Core/Lib/can-halal/can-halal.h \ + Core/Inc/errors.h Core/Inc/can.h Core/Inc/eeprom.h \ + Core/Inc/soc_estimation.h Core/Inc/state_machine.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h Core/Inc/TMP1075.h \ + Core/Inc/errors.h Core/Inc/status_LED.h Core/Inc/TMP1075.h +Core/Inc/PWM_control.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h: +Core/Inc/state_machine.h: +Core/Inc/ADBMS_LL_Driver.h: +Core/Inc/main.h: +Core/Inc/AMS_HighLevel.h: +Core/Inc/ADBMS_Abstraction.h: +Core/Inc/ADBMS_CMD_MAKROS.h: +Core/Lib/can-halal/can-halal.h: +Core/Inc/errors.h: +Core/Inc/can.h: +Core/Inc/eeprom.h: +Core/Inc/soc_estimation.h: +Core/Inc/state_machine.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Core/Inc/TMP1075.h: +Core/Inc/errors.h: +Core/Inc/status_LED.h: +Core/Inc/TMP1075.h: diff --git a/Software/build/PWM_control.lst b/Software/build/PWM_control.lst new file mode 100644 index 0000000..04490d0 --- /dev/null +++ b/Software/build/PWM_control.lst @@ -0,0 +1,482 @@ +ARM GAS /tmp/cctnTl5L.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 6 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "PWM_control.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Core/Src/PWM_control.c" + 20 .global powerground + 21 .section .bss.powerground,"aw",%nobits + 22 .align 2 + 25 powerground: + 26 0000 00000000 .space 4 + 27 .global battery_cooling + 28 .section .bss.battery_cooling,"aw",%nobits + 29 .align 2 + 32 battery_cooling: + 33 0000 00000000 .space 4 + 34 .global esc_cooling + 35 .section .bss.esc_cooling,"aw",%nobits + 36 .align 2 + 39 esc_cooling: + 40 0000 00000000 .space 4 + 41 .section .text.PWM_control_init,"ax",%progbits + 42 .align 1 + 43 .global PWM_control_init + 44 .syntax unified + 45 .thumb + 46 .thumb_func + 48 PWM_control_init: + 49 .LFB130: + 1:Core/Src/PWM_control.c **** /* + 2:Core/Src/PWM_control.c **** * PWM_control.h + 3:Core/Src/PWM_control.c **** * + 4:Core/Src/PWM_control.c **** * Created on: 07.07.2024 + 5:Core/Src/PWM_control.c **** * Author: Hamza + 6:Core/Src/PWM_control.c **** */ + 7:Core/Src/PWM_control.c **** + 8:Core/Src/PWM_control.c **** #include "PWM_control.h" + 9:Core/Src/PWM_control.c **** + 10:Core/Src/PWM_control.c **** //uint32_t powerground1_CCR, powerground2_CCR, battery_cooling_CCR; + 11:Core/Src/PWM_control.c **** + 12:Core/Src/PWM_control.c **** TIM_HandleTypeDef *powerground, *battery_cooling, *esc_cooling; + 13:Core/Src/PWM_control.c **** + 14:Core/Src/PWM_control.c **** /* + 15:Core/Src/PWM_control.c **** Pulse width modulation mode allows for generating a signal with a frequency determined by + ARM GAS /tmp/cctnTl5L.s page 2 + + + 16:Core/Src/PWM_control.c **** the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx regi + 17:Core/Src/PWM_control.c **** */ + 18:Core/Src/PWM_control.c **** + 19:Core/Src/PWM_control.c **** void PWM_control_init(TIM_HandleTypeDef* pg, TIM_HandleTypeDef* bat_cool, TIM_HandleTypeDef* esc_co + 50 .loc 1 19 103 + 51 .cfi_startproc + 52 @ args = 0, pretend = 0, frame = 16 + 53 @ frame_needed = 1, uses_anonymous_args = 0 + 54 0000 80B5 push {r7, lr} + 55 .cfi_def_cfa_offset 8 + 56 .cfi_offset 7, -8 + 57 .cfi_offset 14, -4 + 58 0002 84B0 sub sp, sp, #16 + 59 .cfi_def_cfa_offset 24 + 60 0004 00AF add r7, sp, #0 + 61 .cfi_def_cfa_register 7 + 62 0006 F860 str r0, [r7, #12] + 63 0008 B960 str r1, [r7, #8] + 64 000a 7A60 str r2, [r7, #4] + 20:Core/Src/PWM_control.c **** current_powerground_status = 0; + 65 .loc 1 20 30 + 66 000c 144B ldr r3, .L2 + 67 000e 0022 movs r2, #0 + 68 0010 1A70 strb r2, [r3] + 21:Core/Src/PWM_control.c **** target_powerground_status = 0; + 69 .loc 1 21 29 + 70 0012 144B ldr r3, .L2+4 + 71 0014 0022 movs r2, #0 + 72 0016 1A70 strb r2, [r3] + 22:Core/Src/PWM_control.c **** + 23:Core/Src/PWM_control.c **** //battery_cooling_status = 0; + 24:Core/Src/PWM_control.c **** + 25:Core/Src/PWM_control.c **** powerground = pg; + 73 .loc 1 25 15 + 74 0018 134A ldr r2, .L2+8 + 75 001a FB68 ldr r3, [r7, #12] + 76 001c 1360 str r3, [r2] + 26:Core/Src/PWM_control.c **** battery_cooling = bat_cool; + 77 .loc 1 26 19 + 78 001e 134A ldr r2, .L2+12 + 79 0020 BB68 ldr r3, [r7, #8] + 80 0022 1360 str r3, [r2] + 27:Core/Src/PWM_control.c **** esc_cooling = esc_cool; + 81 .loc 1 27 15 + 82 0024 124A ldr r2, .L2+16 + 83 0026 7B68 ldr r3, [r7, #4] + 84 0028 1360 str r3, [r2] + 28:Core/Src/PWM_control.c **** + 29:Core/Src/PWM_control.c **** // htim2 CH3,4 BAT_COOLING_PWM,ENABLE + 30:Core/Src/PWM_control.c **** // htim3 CH3,4 ESC_L_PWM,R_PWM + 31:Core/Src/PWM_control.c **** // htim4 CH1,2,3 LED R,G,B + 32:Core/Src/PWM_control.c **** // htim15 CH1,2 ESC_COOLING_ENABLE,PWM + 33:Core/Src/PWM_control.c **** + 34:Core/Src/PWM_control.c **** HAL_TIM_PWM_Start(powerground, TIM_CHANNEL_3); //TIM3CH3 + 85 .loc 1 34 3 + 86 002a 0F4B ldr r3, .L2+8 + 87 002c 1B68 ldr r3, [r3] + ARM GAS /tmp/cctnTl5L.s page 3 + + + 88 002e 0821 movs r1, #8 + 89 0030 1846 mov r0, r3 + 90 0032 FFF7FEFF bl HAL_TIM_PWM_Start + 35:Core/Src/PWM_control.c **** HAL_TIM_PWM_Start(powerground, TIM_CHANNEL_4); //TIM3CH4 + 91 .loc 1 35 3 + 92 0036 0C4B ldr r3, .L2+8 + 93 0038 1B68 ldr r3, [r3] + 94 003a 0C21 movs r1, #12 + 95 003c 1846 mov r0, r3 + 96 003e FFF7FEFF bl HAL_TIM_PWM_Start + 36:Core/Src/PWM_control.c **** //HAL_TIM_PWM_Start(bat_cool, TIM_CHANNEL_3); //TIM1CH3 + 37:Core/Src/PWM_control.c **** + 38:Core/Src/PWM_control.c **** __HAL_TIM_SET_COMPARE(powerground, TIM_CHANNEL_1, 0); + 97 .loc 1 38 3 + 98 0042 094B ldr r3, .L2+8 + 99 0044 1B68 ldr r3, [r3] + 100 0046 1B68 ldr r3, [r3] + 101 0048 0022 movs r2, #0 + 102 004a 5A63 str r2, [r3, #52] + 39:Core/Src/PWM_control.c **** __HAL_TIM_SET_COMPARE(powerground, TIM_CHANNEL_2, 0); + 103 .loc 1 39 3 + 104 004c 064B ldr r3, .L2+8 + 105 004e 1B68 ldr r3, [r3] + 106 0050 1B68 ldr r3, [r3] + 107 0052 0022 movs r2, #0 + 108 0054 9A63 str r2, [r3, #56] + 40:Core/Src/PWM_control.c **** + 41:Core/Src/PWM_control.c **** //PWM_powerground_control(0); + 42:Core/Src/PWM_control.c **** //__HAL_TIM_SET_COMPARE(battery_cooling, TIM_CHANNEL_3, 2000); + 43:Core/Src/PWM_control.c **** } + 109 .loc 1 43 1 + 110 0056 00BF nop + 111 0058 1037 adds r7, r7, #16 + 112 .cfi_def_cfa_offset 8 + 113 005a BD46 mov sp, r7 + 114 .cfi_def_cfa_register 13 + 115 @ sp needed + 116 005c 80BD pop {r7, pc} + 117 .L3: + 118 005e 00BF .align 2 + 119 .L2: + 120 0060 00000000 .word current_powerground_status + 121 0064 00000000 .word target_powerground_status + 122 0068 00000000 .word powerground + 123 006c 00000000 .word battery_cooling + 124 0070 00000000 .word esc_cooling + 125 .cfi_endproc + 126 .LFE130: + 128 .section .text.PWM_powerground_control,"ax",%progbits + 129 .align 1 + 130 .global PWM_powerground_control + 131 .syntax unified + 132 .thumb + 133 .thumb_func + 135 PWM_powerground_control: + 136 .LFB131: + 44:Core/Src/PWM_control.c **** + ARM GAS /tmp/cctnTl5L.s page 4 + + + 45:Core/Src/PWM_control.c **** /* + 46:Core/Src/PWM_control.c **** controls the duty cycle of the fans by setting the CCR of the channel + 47:Core/Src/PWM_control.c **** 6+percent/100 = x/ARR + 48:Core/Src/PWM_control.c **** DUTYCYCLE = 40000 * X/100 + 49:Core/Src/PWM_control.c **** */ + 50:Core/Src/PWM_control.c **** void PWM_powerground_control(uint8_t percent){ + 137 .loc 1 50 46 + 138 .cfi_startproc + 139 @ args = 0, pretend = 0, frame = 16 + 140 @ frame_needed = 1, uses_anonymous_args = 0 + 141 @ link register save eliminated. + 142 0000 80B4 push {r7} + 143 .cfi_def_cfa_offset 4 + 144 .cfi_offset 7, -4 + 145 0002 85B0 sub sp, sp, #20 + 146 .cfi_def_cfa_offset 24 + 147 0004 00AF add r7, sp, #0 + 148 .cfi_def_cfa_register 7 + 149 0006 0346 mov r3, r0 + 150 0008 FB71 strb r3, [r7, #7] + 51:Core/Src/PWM_control.c **** if (percent > 100){ //something went wrong + 151 .loc 1 51 6 + 152 000a FB79 ldrb r3, [r7, #7] @ zero_extendqisi2 + 153 000c 642B cmp r3, #100 + 154 000e 11D9 bls .L5 + 52:Core/Src/PWM_control.c **** __HAL_TIM_SET_COMPARE(powerground, TIM_CHANNEL_3, 0); + 155 .loc 1 52 5 + 156 0010 174B ldr r3, .L7 + 157 0012 1B68 ldr r3, [r3] + 158 0014 1B68 ldr r3, [r3] + 159 0016 0022 movs r2, #0 + 160 0018 DA63 str r2, [r3, #60] + 53:Core/Src/PWM_control.c **** __HAL_TIM_SET_COMPARE(powerground, TIM_CHANNEL_4, 0); + 161 .loc 1 53 5 + 162 001a 154B ldr r3, .L7 + 163 001c 1B68 ldr r3, [r3] + 164 001e 1B68 ldr r3, [r3] + 165 0020 0022 movs r2, #0 + 166 0022 1A64 str r2, [r3, #64] + 54:Core/Src/PWM_control.c **** current_powerground_status = target_powerground_status = 0; + 167 .loc 1 54 62 + 168 0024 134B ldr r3, .L7+4 + 169 0026 0022 movs r2, #0 + 170 0028 1A70 strb r2, [r3] + 171 .loc 1 54 34 + 172 002a 124B ldr r3, .L7+4 + 173 002c 1A78 ldrb r2, [r3] @ zero_extendqisi2 + 174 002e 124B ldr r3, .L7+8 + 175 0030 1A70 strb r2, [r3] + 55:Core/Src/PWM_control.c **** return; + 176 .loc 1 55 5 + 177 0032 18E0 b .L4 + 178 .L5: + 56:Core/Src/PWM_control.c **** } + 57:Core/Src/PWM_control.c **** current_powerground_status = target_powerground_status = percent; + 179 .loc 1 57 58 + 180 0034 0F4A ldr r2, .L7+4 + ARM GAS /tmp/cctnTl5L.s page 5 + + + 181 0036 FB79 ldrb r3, [r7, #7] + 182 0038 1370 strb r3, [r2] + 183 .loc 1 57 30 + 184 003a 0E4B ldr r3, .L7+4 + 185 003c 1A78 ldrb r2, [r3] @ zero_extendqisi2 + 186 003e 0E4B ldr r3, .L7+8 + 187 0040 1A70 strb r2, [r3] + 58:Core/Src/PWM_control.c **** + 59:Core/Src/PWM_control.c **** int ccr = 2000 + (20 * percent); + 188 .loc 1 59 24 + 189 0042 FA79 ldrb r2, [r7, #7] @ zero_extendqisi2 + 190 0044 1346 mov r3, r2 + 191 0046 9B00 lsls r3, r3, #2 + 192 0048 1344 add r3, r3, r2 + 193 004a 9B00 lsls r3, r3, #2 + 194 .loc 1 59 7 + 195 004c 03F5FA63 add r3, r3, #2000 + 196 0050 FB60 str r3, [r7, #12] + 60:Core/Src/PWM_control.c **** __HAL_TIM_SET_COMPARE(powerground, TIM_CHANNEL_3, ccr); + 197 .loc 1 60 3 + 198 0052 074B ldr r3, .L7 + 199 0054 1B68 ldr r3, [r3] + 200 0056 1B68 ldr r3, [r3] + 201 0058 FA68 ldr r2, [r7, #12] + 202 005a DA63 str r2, [r3, #60] + 61:Core/Src/PWM_control.c **** __HAL_TIM_SET_COMPARE(powerground, TIM_CHANNEL_4, ccr); + 203 .loc 1 61 3 + 204 005c 044B ldr r3, .L7 + 205 005e 1B68 ldr r3, [r3] + 206 0060 1B68 ldr r3, [r3] + 207 0062 FA68 ldr r2, [r7, #12] + 208 0064 1A64 str r2, [r3, #64] + 209 .L4: + 62:Core/Src/PWM_control.c **** } + 210 .loc 1 62 1 + 211 0066 1437 adds r7, r7, #20 + 212 .cfi_def_cfa_offset 4 + 213 0068 BD46 mov sp, r7 + 214 .cfi_def_cfa_register 13 + 215 @ sp needed + 216 006a 5DF8047B ldr r7, [sp], #4 + 217 .cfi_restore 7 + 218 .cfi_def_cfa_offset 0 + 219 006e 7047 bx lr + 220 .L8: + 221 .align 2 + 222 .L7: + 223 0070 00000000 .word powerground + 224 0074 00000000 .word target_powerground_status + 225 0078 00000000 .word current_powerground_status + 226 .cfi_endproc + 227 .LFE131: + 229 .section .text.PWM_powerground_softcontrol,"ax",%progbits + 230 .align 1 + 231 .global PWM_powerground_softcontrol + 232 .syntax unified + 233 .thumb + ARM GAS /tmp/cctnTl5L.s page 6 + + + 234 .thumb_func + 236 PWM_powerground_softcontrol: + 237 .LFB132: + 63:Core/Src/PWM_control.c **** + 64:Core/Src/PWM_control.c **** void PWM_powerground_softcontrol(){ + 238 .loc 1 64 35 + 239 .cfi_startproc + 240 @ args = 0, pretend = 0, frame = 8 + 241 @ frame_needed = 1, uses_anonymous_args = 0 + 242 @ link register save eliminated. + 243 0000 80B4 push {r7} + 244 .cfi_def_cfa_offset 4 + 245 .cfi_offset 7, -4 + 246 0002 83B0 sub sp, sp, #12 + 247 .cfi_def_cfa_offset 16 + 248 0004 00AF add r7, sp, #0 + 249 .cfi_def_cfa_register 7 + 65:Core/Src/PWM_control.c **** int ccr = 2000 + (20 * current_powerground_status); + 250 .loc 1 65 24 + 251 0006 0D4B ldr r3, .L10 + 252 0008 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 253 000a 1A46 mov r2, r3 + 254 000c 1346 mov r3, r2 + 255 000e 9B00 lsls r3, r3, #2 + 256 0010 1344 add r3, r3, r2 + 257 0012 9B00 lsls r3, r3, #2 + 258 .loc 1 65 7 + 259 0014 03F5FA63 add r3, r3, #2000 + 260 0018 7B60 str r3, [r7, #4] + 66:Core/Src/PWM_control.c **** __HAL_TIM_SET_COMPARE(powerground, TIM_CHANNEL_3, ccr); + 261 .loc 1 66 3 + 262 001a 094B ldr r3, .L10+4 + 263 001c 1B68 ldr r3, [r3] + 264 001e 1B68 ldr r3, [r3] + 265 0020 7A68 ldr r2, [r7, #4] + 266 0022 DA63 str r2, [r3, #60] + 67:Core/Src/PWM_control.c **** __HAL_TIM_SET_COMPARE(powerground, TIM_CHANNEL_4, ccr); + 267 .loc 1 67 3 + 268 0024 064B ldr r3, .L10+4 + 269 0026 1B68 ldr r3, [r3] + 270 0028 1B68 ldr r3, [r3] + 271 002a 7A68 ldr r2, [r7, #4] + 272 002c 1A64 str r2, [r3, #64] + 68:Core/Src/PWM_control.c **** } + 273 .loc 1 68 1 + 274 002e 00BF nop + 275 0030 0C37 adds r7, r7, #12 + 276 .cfi_def_cfa_offset 4 + 277 0032 BD46 mov sp, r7 + 278 .cfi_def_cfa_register 13 + 279 @ sp needed + 280 0034 5DF8047B ldr r7, [sp], #4 + 281 .cfi_restore 7 + 282 .cfi_def_cfa_offset 0 + 283 0038 7047 bx lr + 284 .L11: + 285 003a 00BF .align 2 + ARM GAS /tmp/cctnTl5L.s page 7 + + + 286 .L10: + 287 003c 00000000 .word current_powerground_status + 288 0040 00000000 .word powerground + 289 .cfi_endproc + 290 .LFE132: + 292 .section .text.PWM_battery_cooling_control,"ax",%progbits + 293 .align 1 + 294 .global PWM_battery_cooling_control + 295 .syntax unified + 296 .thumb + 297 .thumb_func + 299 PWM_battery_cooling_control: + 300 .LFB133: + 69:Core/Src/PWM_control.c **** + 70:Core/Src/PWM_control.c **** void PWM_battery_cooling_control(uint8_t percent){} + 301 .loc 1 70 50 + 302 .cfi_startproc + 303 @ args = 0, pretend = 0, frame = 8 + 304 @ frame_needed = 1, uses_anonymous_args = 0 + 305 @ link register save eliminated. + 306 0000 80B4 push {r7} + 307 .cfi_def_cfa_offset 4 + 308 .cfi_offset 7, -4 + 309 0002 83B0 sub sp, sp, #12 + 310 .cfi_def_cfa_offset 16 + 311 0004 00AF add r7, sp, #0 + 312 .cfi_def_cfa_register 7 + 313 0006 0346 mov r3, r0 + 314 0008 FB71 strb r3, [r7, #7] + 315 .loc 1 70 51 + 316 000a 00BF nop + 317 000c 0C37 adds r7, r7, #12 + 318 .cfi_def_cfa_offset 4 + 319 000e BD46 mov sp, r7 + 320 .cfi_def_cfa_register 13 + 321 @ sp needed + 322 0010 5DF8047B ldr r7, [sp], #4 + 323 .cfi_restore 7 + 324 .cfi_def_cfa_offset 0 + 325 0014 7047 bx lr + 326 .cfi_endproc + 327 .LFE133: + 329 .section .text.PWM_esc_cooling,"ax",%progbits + 330 .align 1 + 331 .global PWM_esc_cooling + 332 .syntax unified + 333 .thumb + 334 .thumb_func + 336 PWM_esc_cooling: + 337 .LFB134: + 71:Core/Src/PWM_control.c **** void PWM_esc_cooling(uint8_t percent){} + 338 .loc 1 71 38 + 339 .cfi_startproc + 340 @ args = 0, pretend = 0, frame = 8 + 341 @ frame_needed = 1, uses_anonymous_args = 0 + 342 @ link register save eliminated. + 343 0000 80B4 push {r7} + ARM GAS /tmp/cctnTl5L.s page 8 + + + 344 .cfi_def_cfa_offset 4 + 345 .cfi_offset 7, -4 + 346 0002 83B0 sub sp, sp, #12 + 347 .cfi_def_cfa_offset 16 + 348 0004 00AF add r7, sp, #0 + 349 .cfi_def_cfa_register 7 + 350 0006 0346 mov r3, r0 + 351 0008 FB71 strb r3, [r7, #7] + 352 .loc 1 71 39 + 353 000a 00BF nop + 354 000c 0C37 adds r7, r7, #12 + 355 .cfi_def_cfa_offset 4 + 356 000e BD46 mov sp, r7 + 357 .cfi_def_cfa_register 13 + 358 @ sp needed + 359 0010 5DF8047B ldr r7, [sp], #4 + 360 .cfi_restore 7 + 361 .cfi_def_cfa_offset 0 + 362 0014 7047 bx lr + 363 .cfi_endproc + 364 .LFE134: + 366 .text + 367 .Letext0: + 368 .file 2 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 369 .file 3 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 370 .file 4 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + 371 .file 5 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h" + 372 .file 6 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h" + 373 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h" + 374 .file 8 "Core/Inc/PWM_control.h" + ARM GAS /tmp/cctnTl5L.s page 9 + + +DEFINED SYMBOLS + *ABS*:00000000 PWM_control.c + /tmp/cctnTl5L.s:25 .bss.powerground:00000000 powerground + /tmp/cctnTl5L.s:22 .bss.powerground:00000000 $d + /tmp/cctnTl5L.s:32 .bss.battery_cooling:00000000 battery_cooling + /tmp/cctnTl5L.s:29 .bss.battery_cooling:00000000 $d + /tmp/cctnTl5L.s:39 .bss.esc_cooling:00000000 esc_cooling + /tmp/cctnTl5L.s:36 .bss.esc_cooling:00000000 $d + /tmp/cctnTl5L.s:42 .text.PWM_control_init:00000000 $t + /tmp/cctnTl5L.s:48 .text.PWM_control_init:00000000 PWM_control_init + /tmp/cctnTl5L.s:120 .text.PWM_control_init:00000060 $d + /tmp/cctnTl5L.s:129 .text.PWM_powerground_control:00000000 $t + /tmp/cctnTl5L.s:135 .text.PWM_powerground_control:00000000 PWM_powerground_control + /tmp/cctnTl5L.s:223 .text.PWM_powerground_control:00000070 $d + /tmp/cctnTl5L.s:230 .text.PWM_powerground_softcontrol:00000000 $t + /tmp/cctnTl5L.s:236 .text.PWM_powerground_softcontrol:00000000 PWM_powerground_softcontrol + /tmp/cctnTl5L.s:287 .text.PWM_powerground_softcontrol:0000003c $d + /tmp/cctnTl5L.s:293 .text.PWM_battery_cooling_control:00000000 $t + /tmp/cctnTl5L.s:299 .text.PWM_battery_cooling_control:00000000 PWM_battery_cooling_control + /tmp/cctnTl5L.s:330 .text.PWM_esc_cooling:00000000 $t + /tmp/cctnTl5L.s:336 .text.PWM_esc_cooling:00000000 PWM_esc_cooling + +UNDEFINED SYMBOLS +HAL_TIM_PWM_Start +current_powerground_status +target_powerground_status diff --git a/Software/build/PWM_control.o b/Software/build/PWM_control.o new file mode 100644 index 0000000..daac45b Binary files /dev/null and b/Software/build/PWM_control.o differ diff --git a/Software/build/TMP1075.d b/Software/build/TMP1075.d new file mode 100644 index 0000000..eaac475 --- /dev/null +++ b/Software/build/TMP1075.d @@ -0,0 +1,86 @@ +build/TMP1075.o: Core/Src/TMP1075.c Core/Inc/TMP1075.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + Core/Inc/stm32f3xx_hal_conf.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h \ + Core/Lib/can-halal/can-halal.h Core/Inc/errors.h \ + Core/Inc/state_machine.h Core/Inc/ADBMS_LL_Driver.h Core/Inc/main.h \ + Core/Inc/AMS_HighLevel.h Core/Inc/ADBMS_Abstraction.h \ + Core/Inc/ADBMS_CMD_MAKROS.h Core/Inc/can.h Core/Inc/state_machine.h \ + Core/Inc/eeprom.h Core/Inc/soc_estimation.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h Core/Inc/TMP1075.h \ + Core/Inc/errors.h Core/Inc/PWM_control.h Core/Inc/status_LED.h +Core/Inc/TMP1075.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h: +Core/Lib/can-halal/can-halal.h: +Core/Inc/errors.h: +Core/Inc/state_machine.h: +Core/Inc/ADBMS_LL_Driver.h: +Core/Inc/main.h: +Core/Inc/AMS_HighLevel.h: +Core/Inc/ADBMS_Abstraction.h: +Core/Inc/ADBMS_CMD_MAKROS.h: +Core/Inc/can.h: +Core/Inc/state_machine.h: +Core/Inc/eeprom.h: +Core/Inc/soc_estimation.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Core/Inc/TMP1075.h: +Core/Inc/errors.h: +Core/Inc/PWM_control.h: +Core/Inc/status_LED.h: diff --git a/Software/build/TMP1075.lst b/Software/build/TMP1075.lst new file mode 100644 index 0000000..b7b1078 --- /dev/null +++ b/Software/build/TMP1075.lst @@ -0,0 +1,803 @@ +ARM GAS /tmp/cc1QLhHg.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 6 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "TMP1075.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Core/Src/TMP1075.c" + 20 .global tmp1075_temps + 21 .section .bss.tmp1075_temps,"aw",%nobits + 22 .align 2 + 25 tmp1075_temps: + 26 0000 00000000 .space 26 + 26 00000000 + 26 00000000 + 26 00000000 + 26 00000000 + 27 .global tmp1075_failed_sensors + 28 .section .bss.tmp1075_failed_sensors,"aw",%nobits + 29 .align 2 + 32 tmp1075_failed_sensors: + 33 0000 00000000 .space 4 + 34 .global nfailed_temp_sensors + 35 .section .bss.nfailed_temp_sensors,"aw",%nobits + 38 nfailed_temp_sensors: + 39 0000 00 .space 1 + 40 .global hi2c + 41 .section .bss.hi2c,"aw",%nobits + 42 .align 2 + 45 hi2c: + 46 0000 00000000 .space 4 + 47 .section .text.tmp1075_init,"ax",%progbits + 48 .align 1 + 49 .global tmp1075_init + 50 .syntax unified + 51 .thumb + 52 .thumb_func + 54 tmp1075_init: + 55 .LFB130: + 1:Core/Src/TMP1075.c **** #include "TMP1075.h" + 2:Core/Src/TMP1075.c **** #include "state_machine.h" + 3:Core/Src/TMP1075.c **** + 4:Core/Src/TMP1075.c **** #define MAX_TEMP_DISCHARGING ((int16_t)(59 / 0.0625f)) + 5:Core/Src/TMP1075.c **** #define MIN_TEMP_DISCHARGING ((int16_t)(-20 / 0.0625f)) + 6:Core/Src/TMP1075.c **** #define MAX_TEMP_CHARGING ((int16_t)(45 / 0.0625f)) + 7:Core/Src/TMP1075.c **** #define MIN_TEMP_CHARGING ((int16_t)(0 / 0.0625f)) + ARM GAS /tmp/cc1QLhHg.s page 2 + + + 8:Core/Src/TMP1075.c **** + 9:Core/Src/TMP1075.c **** #define MAX_FAILED_TEMP 2 //TODO: change value for compliance with the actual number of sensors + 10:Core/Src/TMP1075.c **** // TODO: "change value for compliance with the actual number of sensors", change temps to float + 11:Core/Src/TMP1075.c **** + 12:Core/Src/TMP1075.c **** int16_t tmp1075_temps[N_TEMP_SENSORS] = {0}; + 13:Core/Src/TMP1075.c **** uint32_t tmp1075_failed_sensors = 0; + 14:Core/Src/TMP1075.c **** uint8_t nfailed_temp_sensors = 0; + 15:Core/Src/TMP1075.c **** + 16:Core/Src/TMP1075.c **** I2C_HandleTypeDef* hi2c; + 17:Core/Src/TMP1075.c **** + 18:Core/Src/TMP1075.c **** HAL_StatusTypeDef tmp1075_init(I2C_HandleTypeDef* handle) { + 56 .loc 1 18 59 + 57 .cfi_startproc + 58 @ args = 0, pretend = 0, frame = 16 + 59 @ frame_needed = 1, uses_anonymous_args = 0 + 60 0000 80B5 push {r7, lr} + 61 .cfi_def_cfa_offset 8 + 62 .cfi_offset 7, -8 + 63 .cfi_offset 14, -4 + 64 0002 84B0 sub sp, sp, #16 + 65 .cfi_def_cfa_offset 24 + 66 0004 00AF add r7, sp, #0 + 67 .cfi_def_cfa_register 7 + 68 0006 7860 str r0, [r7, #4] + 19:Core/Src/TMP1075.c **** hi2c = handle; + 69 .loc 1 19 8 + 70 0008 0D4A ldr r2, .L6 + 71 000a 7B68 ldr r3, [r7, #4] + 72 000c 1360 str r3, [r2] + 73 .LBB2: + 20:Core/Src/TMP1075.c **** for (int i = 0; i < N_TEMP_SENSORS; i++) { + 74 .loc 1 20 12 + 75 000e 0023 movs r3, #0 + 76 0010 FB60 str r3, [r7, #12] + 77 .loc 1 20 3 + 78 0012 0CE0 b .L2 + 79 .L5: + 80 .LBB3: + 21:Core/Src/TMP1075.c **** HAL_StatusTypeDef status = tmp1075_sensor_init(i); + 81 .loc 1 21 32 + 82 0014 F868 ldr r0, [r7, #12] + 83 0016 FFF7FEFF bl tmp1075_sensor_init + 84 001a 0346 mov r3, r0 + 85 001c FB72 strb r3, [r7, #11] + 22:Core/Src/TMP1075.c **** if (status != HAL_OK) { + 86 .loc 1 22 8 + 87 001e FB7A ldrb r3, [r7, #11] @ zero_extendqisi2 + 88 0020 002B cmp r3, #0 + 89 0022 01D0 beq .L3 + 23:Core/Src/TMP1075.c **** return status; + 90 .loc 1 23 14 + 91 0024 FB7A ldrb r3, [r7, #11] @ zero_extendqisi2 + 92 0026 06E0 b .L4 + 93 .L3: + 94 .LBE3: + 20:Core/Src/TMP1075.c **** HAL_StatusTypeDef status = tmp1075_sensor_init(i); + 95 .loc 1 20 40 discriminator 2 + ARM GAS /tmp/cc1QLhHg.s page 3 + + + 96 0028 FB68 ldr r3, [r7, #12] + 97 002a 0133 adds r3, r3, #1 + 98 002c FB60 str r3, [r7, #12] + 99 .L2: + 20:Core/Src/TMP1075.c **** HAL_StatusTypeDef status = tmp1075_sensor_init(i); + 100 .loc 1 20 21 discriminator 1 + 101 002e FB68 ldr r3, [r7, #12] + 102 0030 0C2B cmp r3, #12 + 103 0032 EFDD ble .L5 + 104 .LBE2: + 24:Core/Src/TMP1075.c **** } + 25:Core/Src/TMP1075.c **** } + 26:Core/Src/TMP1075.c **** return HAL_OK; + 105 .loc 1 26 10 + 106 0034 0023 movs r3, #0 + 107 .L4: + 27:Core/Src/TMP1075.c **** } + 108 .loc 1 27 1 + 109 0036 1846 mov r0, r3 + 110 0038 1037 adds r7, r7, #16 + 111 .cfi_def_cfa_offset 8 + 112 003a BD46 mov sp, r7 + 113 .cfi_def_cfa_register 13 + 114 @ sp needed + 115 003c 80BD pop {r7, pc} + 116 .L7: + 117 003e 00BF .align 2 + 118 .L6: + 119 0040 00000000 .word hi2c + 120 .cfi_endproc + 121 .LFE130: + 123 .section .text.handle_over_maxtemp,"ax",%progbits + 124 .align 1 + 125 .global handle_over_maxtemp + 126 .syntax unified + 127 .thumb + 128 .thumb_func + 130 handle_over_maxtemp: + 131 .LFB131: + 28:Core/Src/TMP1075.c **** + 29:Core/Src/TMP1075.c **** void handle_over_maxtemp(uint8_t index, uint16_t value) { + 132 .loc 1 29 57 + 133 .cfi_startproc + 134 @ args = 0, pretend = 0, frame = 16 + 135 @ frame_needed = 1, uses_anonymous_args = 0 + 136 0000 B0B5 push {r4, r5, r7, lr} + 137 .cfi_def_cfa_offset 16 + 138 .cfi_offset 4, -16 + 139 .cfi_offset 5, -12 + 140 .cfi_offset 7, -8 + 141 .cfi_offset 14, -4 + 142 0002 86B0 sub sp, sp, #24 + 143 .cfi_def_cfa_offset 40 + 144 0004 02AF add r7, sp, #8 + 145 .cfi_def_cfa 7, 32 + 146 0006 0346 mov r3, r0 + 147 0008 0A46 mov r2, r1 + ARM GAS /tmp/cc1QLhHg.s page 4 + + + 148 000a FB71 strb r3, [r7, #7] + 149 000c 1346 mov r3, r2 @ movhi + 150 000e BB80 strh r3, [r7, #4] @ movhi + 30:Core/Src/TMP1075.c **** set_error_source(ERROR_SOURCE_TEMPERATURES); + 151 .loc 1 30 3 + 152 0010 0220 movs r0, #2 + 153 0012 FFF7FEFF bl set_error_source + 31:Core/Src/TMP1075.c **** error_data.data_kind = SEK_OVERTEMP; + 154 .loc 1 31 24 + 155 0016 0C4B ldr r3, .L9 + 156 0018 0022 movs r2, #0 + 157 001a 5A80 strh r2, [r3, #2] @ movhi + 32:Core/Src/TMP1075.c **** error_data.data[0] = index; + 158 .loc 1 32 22 + 159 001c 0A4A ldr r2, .L9 + 160 001e FB79 ldrb r3, [r7, #7] + 161 0020 1371 strb r3, [r2, #4] + 33:Core/Src/TMP1075.c **** uint8_t* ptr = &error_data.data[1]; + 162 .loc 1 33 12 + 163 0022 0A4B ldr r3, .L9+4 + 164 0024 FB60 str r3, [r7, #12] + 34:Core/Src/TMP1075.c **** ptr = ftcan_marshal_unsigned(ptr, value, 2); + 165 .loc 1 34 9 + 166 0026 BB88 ldrh r3, [r7, #4] + 167 0028 0022 movs r2, #0 + 168 002a 1C46 mov r4, r3 + 169 002c 1546 mov r5, r2 + 170 002e 0223 movs r3, #2 + 171 0030 0093 str r3, [sp] + 172 0032 2246 mov r2, r4 + 173 0034 2B46 mov r3, r5 + 174 0036 F868 ldr r0, [r7, #12] + 175 0038 FFF7FEFF bl ftcan_marshal_unsigned + 176 003c F860 str r0, [r7, #12] + 35:Core/Src/TMP1075.c **** } + 177 .loc 1 35 1 + 178 003e 00BF nop + 179 0040 1037 adds r7, r7, #16 + 180 .cfi_def_cfa_offset 16 + 181 0042 BD46 mov sp, r7 + 182 .cfi_def_cfa_register 13 + 183 @ sp needed + 184 0044 B0BD pop {r4, r5, r7, pc} + 185 .L10: + 186 0046 00BF .align 2 + 187 .L9: + 188 0048 00000000 .word error_data + 189 004c 05000000 .word error_data+5 + 190 .cfi_endproc + 191 .LFE131: + 193 .section .text.tmp1075_measure,"ax",%progbits + 194 .align 1 + 195 .global tmp1075_measure + 196 .syntax unified + 197 .thumb + 198 .thumb_func + 200 tmp1075_measure: + ARM GAS /tmp/cc1QLhHg.s page 5 + + + 201 .LFB132: + 36:Core/Src/TMP1075.c **** + 37:Core/Src/TMP1075.c **** HAL_StatusTypeDef tmp1075_measure() { + 202 .loc 1 37 37 + 203 .cfi_startproc + 204 @ args = 0, pretend = 0, frame = 16 + 205 @ frame_needed = 1, uses_anonymous_args = 0 + 206 0000 80B5 push {r7, lr} + 207 .cfi_def_cfa_offset 8 + 208 .cfi_offset 7, -8 + 209 .cfi_offset 14, -4 + 210 0002 84B0 sub sp, sp, #16 + 211 .cfi_def_cfa_offset 24 + 212 0004 00AF add r7, sp, #0 + 213 .cfi_def_cfa_register 7 + 38:Core/Src/TMP1075.c **** int err = 0; + 214 .loc 1 38 7 + 215 0006 0023 movs r3, #0 + 216 0008 FB60 str r3, [r7, #12] + 39:Core/Src/TMP1075.c **** int temp_error = 0; + 217 .loc 1 39 7 + 218 000a 0023 movs r3, #0 + 219 000c BB60 str r3, [r7, #8] + 220 .LBB4: + 40:Core/Src/TMP1075.c **** for (int i = 0; i < N_TEMP_SENSORS; i++) { + 221 .loc 1 40 12 + 222 000e 0023 movs r3, #0 + 223 0010 7B60 str r3, [r7, #4] + 224 .loc 1 40 3 + 225 0012 9FE0 b .L12 + 226 .L23: + 41:Core/Src/TMP1075.c **** if (tmp1075_sensor_read(i, &tmp1075_temps[i]) != HAL_OK || (tmp1075_temps[i] & 0x000F) != 0) { + 227 .loc 1 41 9 + 228 0014 7B68 ldr r3, [r7, #4] + 229 0016 5B00 lsls r3, r3, #1 + 230 0018 5F4A ldr r2, .L27 + 231 001a 1344 add r3, r3, r2 + 232 001c 1946 mov r1, r3 + 233 001e 7868 ldr r0, [r7, #4] + 234 0020 FFF7FEFF bl tmp1075_sensor_read + 235 0024 0346 mov r3, r0 + 236 .loc 1 41 8 discriminator 1 + 237 0026 002B cmp r3, #0 + 238 0028 08D1 bne .L13 + 239 .loc 1 41 78 discriminator 1 + 240 002a 5B4A ldr r2, .L27 + 241 002c 7B68 ldr r3, [r7, #4] + 242 002e 32F91330 ldrsh r3, [r2, r3, lsl #1] + 243 .loc 1 41 82 discriminator 1 + 244 0032 9BB2 uxth r3, r3 + 245 0034 03F00F03 and r3, r3, #15 + 246 .loc 1 41 61 discriminator 1 + 247 0038 002B cmp r3, #0 + 248 003a 12D0 beq .L14 + 249 .L13: + 42:Core/Src/TMP1075.c **** tmp1075_failed_sensors |= 1 << i; + 250 .loc 1 42 35 + ARM GAS /tmp/cc1QLhHg.s page 6 + + + 251 003c 0122 movs r2, #1 + 252 003e 7B68 ldr r3, [r7, #4] + 253 0040 02FA03F3 lsl r3, r2, r3 + 254 0044 1A46 mov r2, r3 + 255 .loc 1 42 30 + 256 0046 554B ldr r3, .L27+4 + 257 0048 1B68 ldr r3, [r3] + 258 004a 1343 orrs r3, r3, r2 + 259 004c 534A ldr r2, .L27+4 + 260 004e 1360 str r3, [r2] + 43:Core/Src/TMP1075.c **** nfailed_temp_sensors++; + 261 .loc 1 43 27 + 262 0050 534B ldr r3, .L27+8 + 263 0052 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 264 0054 0133 adds r3, r3, #1 + 265 0056 DAB2 uxtb r2, r3 + 266 0058 514B ldr r3, .L27+8 + 267 005a 1A70 strb r2, [r3] + 44:Core/Src/TMP1075.c **** err = 1; + 268 .loc 1 44 11 + 269 005c 0123 movs r3, #1 + 270 005e FB60 str r3, [r7, #12] + 271 0060 75E0 b .L15 + 272 .L14: + 45:Core/Src/TMP1075.c **** } else { + 46:Core/Src/TMP1075.c **** tmp1075_temps[i] >>= 4; + 273 .loc 1 46 20 + 274 0062 4D4A ldr r2, .L27 + 275 0064 7B68 ldr r3, [r7, #4] + 276 0066 32F91330 ldrsh r3, [r2, r3, lsl #1] + 277 .loc 1 46 24 + 278 006a 1B11 asrs r3, r3, #4 + 279 006c 19B2 sxth r1, r3 + 280 006e 4A4A ldr r2, .L27 + 281 0070 7B68 ldr r3, [r7, #4] + 282 0072 22F81310 strh r1, [r2, r3, lsl #1] @ movhi + 47:Core/Src/TMP1075.c **** tmp1075_failed_sensors &= ~(1 << i); + 283 .loc 1 47 37 + 284 0076 0122 movs r2, #1 + 285 0078 7B68 ldr r3, [r7, #4] + 286 007a 02FA03F3 lsl r3, r2, r3 + 287 .loc 1 47 33 + 288 007e DB43 mvns r3, r3 + 289 0080 1A46 mov r2, r3 + 290 .loc 1 47 30 + 291 0082 464B ldr r3, .L27+4 + 292 0084 1B68 ldr r3, [r3] + 293 0086 1340 ands r3, r3, r2 + 294 0088 444A ldr r2, .L27+4 + 295 008a 1360 str r3, [r2] + 48:Core/Src/TMP1075.c **** if (state.current_state == STATE_CHARGING || state.current_state == STATE_CHARGING_PRECHARGE) + 296 .loc 1 48 16 + 297 008c 454B ldr r3, .L27+12 + 298 008e 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 299 .loc 1 48 10 + 300 0090 062B cmp r3, #6 + 301 0092 03D0 beq .L16 + ARM GAS /tmp/cc1QLhHg.s page 7 + + + 302 .loc 1 48 57 discriminator 1 + 303 0094 434B ldr r3, .L27+12 + 304 0096 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 305 .loc 1 48 49 discriminator 1 + 306 0098 052B cmp r3, #5 + 307 009a 14D1 bne .L17 + 308 .L16: + 49:Core/Src/TMP1075.c **** if (tmp1075_temps[i] >= MAX_TEMP_CHARGING) { + 309 .loc 1 49 26 + 310 009c 3E4A ldr r2, .L27 + 311 009e 7B68 ldr r3, [r7, #4] + 312 00a0 32F91330 ldrsh r3, [r2, r3, lsl #1] + 313 .loc 1 49 12 + 314 00a4 B3F5347F cmp r3, #720 + 315 00a8 21DB blt .L19 + 50:Core/Src/TMP1075.c **** temp_error = 1; + 316 .loc 1 50 22 + 317 00aa 0123 movs r3, #1 + 318 00ac BB60 str r3, [r7, #8] + 51:Core/Src/TMP1075.c **** handle_over_maxtemp(i, tmp1075_temps[i]); + 319 .loc 1 51 11 + 320 00ae 7B68 ldr r3, [r7, #4] + 321 00b0 DAB2 uxtb r2, r3 + 322 .loc 1 51 47 + 323 00b2 3949 ldr r1, .L27 + 324 00b4 7B68 ldr r3, [r7, #4] + 325 00b6 31F91330 ldrsh r3, [r1, r3, lsl #1] + 326 .loc 1 51 11 + 327 00ba 9BB2 uxth r3, r3 + 328 00bc 1946 mov r1, r3 + 329 00be 1046 mov r0, r2 + 330 00c0 FFF7FEFF bl handle_over_maxtemp + 49:Core/Src/TMP1075.c **** if (tmp1075_temps[i] >= MAX_TEMP_CHARGING) { + 331 .loc 1 49 12 + 332 00c4 13E0 b .L19 + 333 .L17: + 52:Core/Src/TMP1075.c **** } + 53:Core/Src/TMP1075.c **** } else { + 54:Core/Src/TMP1075.c **** if (tmp1075_temps[i] >= MAX_TEMP_DISCHARGING) { + 334 .loc 1 54 26 + 335 00c6 344A ldr r2, .L27 + 336 00c8 7B68 ldr r3, [r7, #4] + 337 00ca 32F91330 ldrsh r3, [r2, r3, lsl #1] + 338 .loc 1 54 12 + 339 00ce B3F56C7F cmp r3, #944 + 340 00d2 0CDB blt .L19 + 55:Core/Src/TMP1075.c **** temp_error = 1; + 341 .loc 1 55 22 + 342 00d4 0123 movs r3, #1 + 343 00d6 BB60 str r3, [r7, #8] + 56:Core/Src/TMP1075.c **** handle_over_maxtemp(i, tmp1075_temps[i]); + 344 .loc 1 56 11 + 345 00d8 7B68 ldr r3, [r7, #4] + 346 00da DAB2 uxtb r2, r3 + 347 .loc 1 56 47 + 348 00dc 2E49 ldr r1, .L27 + 349 00de 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/cc1QLhHg.s page 8 + + + 350 00e0 31F91330 ldrsh r3, [r1, r3, lsl #1] + 351 .loc 1 56 11 + 352 00e4 9BB2 uxth r3, r3 + 353 00e6 1946 mov r1, r3 + 354 00e8 1046 mov r0, r2 + 355 00ea FFF7FEFF bl handle_over_maxtemp + 356 .L19: + 57:Core/Src/TMP1075.c **** } + 58:Core/Src/TMP1075.c **** } + 59:Core/Src/TMP1075.c **** + 60:Core/Src/TMP1075.c **** if (state.current_state == STATE_CHARGING || state.current_state == STATE_CHARGING_PRECHARGE) + 357 .loc 1 60 16 + 358 00ee 2D4B ldr r3, .L27+12 + 359 00f0 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 360 .loc 1 60 10 + 361 00f2 062B cmp r3, #6 + 362 00f4 03D0 beq .L20 + 363 .loc 1 60 57 discriminator 1 + 364 00f6 2B4B ldr r3, .L27+12 + 365 00f8 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 366 .loc 1 60 49 discriminator 1 + 367 00fa 052B cmp r3, #5 + 368 00fc 13D1 bne .L21 + 369 .L20: + 61:Core/Src/TMP1075.c **** if (tmp1075_temps[i] <= MIN_TEMP_CHARGING) { + 370 .loc 1 61 26 + 371 00fe 264A ldr r2, .L27 + 372 0100 7B68 ldr r3, [r7, #4] + 373 0102 32F91330 ldrsh r3, [r2, r3, lsl #1] + 374 .loc 1 61 12 + 375 0106 002B cmp r3, #0 + 376 0108 21DC bgt .L15 + 62:Core/Src/TMP1075.c **** temp_error = 1; + 377 .loc 1 62 22 + 378 010a 0123 movs r3, #1 + 379 010c BB60 str r3, [r7, #8] + 63:Core/Src/TMP1075.c **** handle_over_maxtemp(i, tmp1075_temps[i]); + 380 .loc 1 63 11 + 381 010e 7B68 ldr r3, [r7, #4] + 382 0110 DAB2 uxtb r2, r3 + 383 .loc 1 63 47 + 384 0112 2149 ldr r1, .L27 + 385 0114 7B68 ldr r3, [r7, #4] + 386 0116 31F91330 ldrsh r3, [r1, r3, lsl #1] + 387 .loc 1 63 11 + 388 011a 9BB2 uxth r3, r3 + 389 011c 1946 mov r1, r3 + 390 011e 1046 mov r0, r2 + 391 0120 FFF7FEFF bl handle_over_maxtemp + 61:Core/Src/TMP1075.c **** if (tmp1075_temps[i] <= MIN_TEMP_CHARGING) { + 392 .loc 1 61 12 + 393 0124 13E0 b .L15 + 394 .L21: + 64:Core/Src/TMP1075.c **** } + 65:Core/Src/TMP1075.c **** } else { + 66:Core/Src/TMP1075.c **** if (tmp1075_temps[i] <= MIN_TEMP_DISCHARGING) { + 395 .loc 1 66 26 + ARM GAS /tmp/cc1QLhHg.s page 9 + + + 396 0126 1C4A ldr r2, .L27 + 397 0128 7B68 ldr r3, [r7, #4] + 398 012a 32F91330 ldrsh r3, [r2, r3, lsl #1] + 399 .loc 1 66 12 + 400 012e 13F5A07F cmn r3, #320 + 401 0132 0CDC bgt .L15 + 67:Core/Src/TMP1075.c **** temp_error = 1; + 402 .loc 1 67 22 + 403 0134 0123 movs r3, #1 + 404 0136 BB60 str r3, [r7, #8] + 68:Core/Src/TMP1075.c **** handle_over_maxtemp(i, tmp1075_temps[i]); + 405 .loc 1 68 11 + 406 0138 7B68 ldr r3, [r7, #4] + 407 013a DAB2 uxtb r2, r3 + 408 .loc 1 68 47 + 409 013c 1649 ldr r1, .L27 + 410 013e 7B68 ldr r3, [r7, #4] + 411 0140 31F91330 ldrsh r3, [r1, r3, lsl #1] + 412 .loc 1 68 11 + 413 0144 9BB2 uxth r3, r3 + 414 0146 1946 mov r1, r3 + 415 0148 1046 mov r0, r2 + 416 014a FFF7FEFF bl handle_over_maxtemp + 417 .L15: + 40:Core/Src/TMP1075.c **** if (tmp1075_sensor_read(i, &tmp1075_temps[i]) != HAL_OK || (tmp1075_temps[i] & 0x000F) != 0) { + 418 .loc 1 40 40 discriminator 2 + 419 014e 7B68 ldr r3, [r7, #4] + 420 0150 0133 adds r3, r3, #1 + 421 0152 7B60 str r3, [r7, #4] + 422 .L12: + 40:Core/Src/TMP1075.c **** if (tmp1075_sensor_read(i, &tmp1075_temps[i]) != HAL_OK || (tmp1075_temps[i] & 0x000F) != 0) { + 423 .loc 1 40 21 discriminator 1 + 424 0154 7B68 ldr r3, [r7, #4] + 425 0156 0C2B cmp r3, #12 + 426 0158 7FF75CAF ble .L23 + 427 .LBE4: + 69:Core/Src/TMP1075.c **** } + 70:Core/Src/TMP1075.c **** } + 71:Core/Src/TMP1075.c **** } + 72:Core/Src/TMP1075.c **** } + 73:Core/Src/TMP1075.c **** if (nfailed_temp_sensors > MAX_FAILED_TEMP) { + 428 .loc 1 73 28 + 429 015c 104B ldr r3, .L27+8 + 430 015e 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 431 .loc 1 73 6 + 432 0160 022B cmp r3, #2 + 433 0162 06D9 bls .L24 + 74:Core/Src/TMP1075.c **** error_data.data_kind = SEK_TOO_FEW_TEMPS; + 434 .loc 1 74 26 + 435 0164 104B ldr r3, .L27+16 + 436 0166 0422 movs r2, #4 + 437 0168 5A80 strh r2, [r3, #2] @ movhi + 75:Core/Src/TMP1075.c **** set_error_source(ERROR_SOURCE_TEMPERATURES); + 438 .loc 1 75 5 + 439 016a 0220 movs r0, #2 + 440 016c FFF7FEFF bl set_error_source + 441 0170 05E0 b .L25 + ARM GAS /tmp/cc1QLhHg.s page 10 + + + 442 .L24: + 76:Core/Src/TMP1075.c **** } else if (!temp_error) { + 443 .loc 1 76 13 + 444 0172 BB68 ldr r3, [r7, #8] + 445 0174 002B cmp r3, #0 + 446 0176 02D1 bne .L25 + 77:Core/Src/TMP1075.c **** clear_error_source(ERROR_SOURCE_TEMPERATURES); + 447 .loc 1 77 5 + 448 0178 0220 movs r0, #2 + 449 017a FFF7FEFF bl clear_error_source + 450 .L25: + 78:Core/Src/TMP1075.c **** } + 79:Core/Src/TMP1075.c **** nfailed_temp_sensors = 0; + 451 .loc 1 79 24 + 452 017e 084B ldr r3, .L27+8 + 453 0180 0022 movs r2, #0 + 454 0182 1A70 strb r2, [r3] + 80:Core/Src/TMP1075.c **** return err ? HAL_ERROR : HAL_OK; + 455 .loc 1 80 26 + 456 0184 FB68 ldr r3, [r7, #12] + 457 0186 002B cmp r3, #0 + 458 0188 14BF ite ne + 459 018a 0123 movne r3, #1 + 460 018c 0023 moveq r3, #0 + 461 018e DBB2 uxtb r3, r3 + 81:Core/Src/TMP1075.c **** } + 462 .loc 1 81 1 + 463 0190 1846 mov r0, r3 + 464 0192 1037 adds r7, r7, #16 + 465 .cfi_def_cfa_offset 8 + 466 0194 BD46 mov sp, r7 + 467 .cfi_def_cfa_register 13 + 468 @ sp needed + 469 0196 80BD pop {r7, pc} + 470 .L28: + 471 .align 2 + 472 .L27: + 473 0198 00000000 .word tmp1075_temps + 474 019c 00000000 .word tmp1075_failed_sensors + 475 01a0 00000000 .word nfailed_temp_sensors + 476 01a4 00000000 .word state + 477 01a8 00000000 .word error_data + 478 .cfi_endproc + 479 .LFE132: + 481 .section .text.tmp1075_sensor_init,"ax",%progbits + 482 .align 1 + 483 .global tmp1075_sensor_init + 484 .syntax unified + 485 .thumb + 486 .thumb_func + 488 tmp1075_sensor_init: + 489 .LFB133: + 82:Core/Src/TMP1075.c **** + 83:Core/Src/TMP1075.c **** HAL_StatusTypeDef tmp1075_sensor_init(int n) { + 490 .loc 1 83 46 + 491 .cfi_startproc + 492 @ args = 0, pretend = 0, frame = 16 + ARM GAS /tmp/cc1QLhHg.s page 11 + + + 493 @ frame_needed = 1, uses_anonymous_args = 0 + 494 0000 80B5 push {r7, lr} + 495 .cfi_def_cfa_offset 8 + 496 .cfi_offset 7, -8 + 497 .cfi_offset 14, -4 + 498 0002 86B0 sub sp, sp, #24 + 499 .cfi_def_cfa_offset 32 + 500 0004 02AF add r7, sp, #8 + 501 .cfi_def_cfa 7, 24 + 502 0006 7860 str r0, [r7, #4] + 84:Core/Src/TMP1075.c **** uint16_t addr = (0b1000000 | n) << 1; + 503 .loc 1 84 35 + 504 0008 7B68 ldr r3, [r7, #4] + 505 000a 1BB2 sxth r3, r3 + 506 000c 5B00 lsls r3, r3, #1 + 507 000e 1BB2 sxth r3, r3 + 508 0010 43F08003 orr r3, r3, #128 + 509 0014 1BB2 sxth r3, r3 + 510 .loc 1 84 12 + 511 0016 FB81 strh r3, [r7, #14] @ movhi + 85:Core/Src/TMP1075.c **** uint8_t data[] = {0}; + 512 .loc 1 85 11 + 513 0018 0023 movs r3, #0 + 514 001a 3B73 strb r3, [r7, #12] + 86:Core/Src/TMP1075.c **** return HAL_I2C_Master_Transmit(hi2c, addr, data, sizeof(data), 100); + 515 .loc 1 86 10 + 516 001c 074B ldr r3, .L31 + 517 001e 1868 ldr r0, [r3] + 518 0020 07F10C02 add r2, r7, #12 + 519 0024 F989 ldrh r1, [r7, #14] + 520 0026 6423 movs r3, #100 + 521 0028 0093 str r3, [sp] + 522 002a 0123 movs r3, #1 + 523 002c FFF7FEFF bl HAL_I2C_Master_Transmit + 524 0030 0346 mov r3, r0 + 87:Core/Src/TMP1075.c **** } + 525 .loc 1 87 1 + 526 0032 1846 mov r0, r3 + 527 0034 1037 adds r7, r7, #16 + 528 .cfi_def_cfa_offset 8 + 529 0036 BD46 mov sp, r7 + 530 .cfi_def_cfa_register 13 + 531 @ sp needed + 532 0038 80BD pop {r7, pc} + 533 .L32: + 534 003a 00BF .align 2 + 535 .L31: + 536 003c 00000000 .word hi2c + 537 .cfi_endproc + 538 .LFE133: + 540 .section .text.tmp1075_sensor_read,"ax",%progbits + 541 .align 1 + 542 .global tmp1075_sensor_read + 543 .syntax unified + 544 .thumb + 545 .thumb_func + 547 tmp1075_sensor_read: + ARM GAS /tmp/cc1QLhHg.s page 12 + + + 548 .LFB134: + 88:Core/Src/TMP1075.c **** + 89:Core/Src/TMP1075.c **** HAL_StatusTypeDef tmp1075_sensor_read(int n, int16_t* res) { + 549 .loc 1 89 60 + 550 .cfi_startproc + 551 @ args = 0, pretend = 0, frame = 16 + 552 @ frame_needed = 1, uses_anonymous_args = 0 + 553 0000 80B5 push {r7, lr} + 554 .cfi_def_cfa_offset 8 + 555 .cfi_offset 7, -8 + 556 .cfi_offset 14, -4 + 557 0002 86B0 sub sp, sp, #24 + 558 .cfi_def_cfa_offset 32 + 559 0004 02AF add r7, sp, #8 + 560 .cfi_def_cfa 7, 24 + 561 0006 7860 str r0, [r7, #4] + 562 0008 3960 str r1, [r7] + 90:Core/Src/TMP1075.c **** uint16_t addr = (0b1000000 | n) << 1; + 563 .loc 1 90 35 + 564 000a 7B68 ldr r3, [r7, #4] + 565 000c 1BB2 sxth r3, r3 + 566 000e 5B00 lsls r3, r3, #1 + 567 0010 1BB2 sxth r3, r3 + 568 0012 43F08003 orr r3, r3, #128 + 569 0016 1BB2 sxth r3, r3 + 570 .loc 1 90 12 + 571 0018 FB81 strh r3, [r7, #14] @ movhi + 91:Core/Src/TMP1075.c **** addr |= 1; // Read + 572 .loc 1 91 8 + 573 001a FB89 ldrh r3, [r7, #14] @ movhi + 574 001c 43F00103 orr r3, r3, #1 + 575 0020 FB81 strh r3, [r7, #14] @ movhi + 92:Core/Src/TMP1075.c **** uint8_t result[2]; + 93:Core/Src/TMP1075.c **** HAL_StatusTypeDef status = + 94:Core/Src/TMP1075.c **** HAL_I2C_Master_Receive(hi2c, addr, result, sizeof(result), 5); //5ms timeout for failure (cas + 576 .loc 1 94 7 + 577 0022 0F4B ldr r3, .L36 + 578 0024 1868 ldr r0, [r3] + 579 0026 07F10802 add r2, r7, #8 + 580 002a F989 ldrh r1, [r7, #14] + 581 002c 0523 movs r3, #5 + 582 002e 0093 str r3, [sp] + 583 0030 0223 movs r3, #2 + 584 0032 FFF7FEFF bl HAL_I2C_Master_Receive + 585 0036 0346 mov r3, r0 + 586 0038 7B73 strb r3, [r7, #13] + 95:Core/Src/TMP1075.c **** if (status == HAL_OK) { + 587 .loc 1 95 6 + 588 003a 7B7B ldrb r3, [r7, #13] @ zero_extendqisi2 + 589 003c 002B cmp r3, #0 + 590 003e 09D1 bne .L34 + 96:Core/Src/TMP1075.c **** *res = (result[0] << 8) | result[1]; + 591 .loc 1 96 19 + 592 0040 3B7A ldrb r3, [r7, #8] @ zero_extendqisi2 + 593 .loc 1 96 29 + 594 0042 1BB2 sxth r3, r3 + 595 0044 1B02 lsls r3, r3, #8 + ARM GAS /tmp/cc1QLhHg.s page 13 + + + 596 0046 1AB2 sxth r2, r3 + 597 .loc 1 96 37 + 598 0048 7B7A ldrb r3, [r7, #9] @ zero_extendqisi2 + 599 004a 1BB2 sxth r3, r3 + 600 .loc 1 96 29 + 601 004c 1343 orrs r3, r3, r2 + 602 004e 1AB2 sxth r2, r3 + 603 .loc 1 96 10 + 604 0050 3B68 ldr r3, [r7] + 605 0052 1A80 strh r2, [r3] @ movhi + 606 .L34: + 97:Core/Src/TMP1075.c **** } + 98:Core/Src/TMP1075.c **** return status; + 607 .loc 1 98 10 + 608 0054 7B7B ldrb r3, [r7, #13] @ zero_extendqisi2 + 99:Core/Src/TMP1075.c **** } + 609 .loc 1 99 1 + 610 0056 1846 mov r0, r3 + 611 0058 1037 adds r7, r7, #16 + 612 .cfi_def_cfa_offset 8 + 613 005a BD46 mov sp, r7 + 614 .cfi_def_cfa_register 13 + 615 @ sp needed + 616 005c 80BD pop {r7, pc} + 617 .L37: + 618 005e 00BF .align 2 + 619 .L36: + 620 0060 00000000 .word hi2c + 621 .cfi_endproc + 622 .LFE134: + 624 .text + 625 .Letext0: + 626 .file 2 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 627 .file 3 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 628 .file 4 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + 629 .file 5 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/lib/gcc/arm-none-e + 630 .file 6 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h" + 631 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h" + 632 .file 8 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h" + 633 .file 9 "Core/Inc/errors.h" + 634 .file 10 "Core/Inc/TMP1075.h" + 635 .file 11 "Core/Inc/state_machine.h" + 636 .file 12 "Core/Lib/can-halal/can-halal.h" + ARM GAS /tmp/cc1QLhHg.s page 14 + + +DEFINED SYMBOLS + *ABS*:00000000 TMP1075.c + /tmp/cc1QLhHg.s:25 .bss.tmp1075_temps:00000000 tmp1075_temps + /tmp/cc1QLhHg.s:22 .bss.tmp1075_temps:00000000 $d + /tmp/cc1QLhHg.s:32 .bss.tmp1075_failed_sensors:00000000 tmp1075_failed_sensors + /tmp/cc1QLhHg.s:29 .bss.tmp1075_failed_sensors:00000000 $d + /tmp/cc1QLhHg.s:38 .bss.nfailed_temp_sensors:00000000 nfailed_temp_sensors + /tmp/cc1QLhHg.s:39 .bss.nfailed_temp_sensors:00000000 $d + /tmp/cc1QLhHg.s:45 .bss.hi2c:00000000 hi2c + /tmp/cc1QLhHg.s:42 .bss.hi2c:00000000 $d + /tmp/cc1QLhHg.s:48 .text.tmp1075_init:00000000 $t + /tmp/cc1QLhHg.s:54 .text.tmp1075_init:00000000 tmp1075_init + /tmp/cc1QLhHg.s:488 .text.tmp1075_sensor_init:00000000 tmp1075_sensor_init + /tmp/cc1QLhHg.s:119 .text.tmp1075_init:00000040 $d + /tmp/cc1QLhHg.s:124 .text.handle_over_maxtemp:00000000 $t + /tmp/cc1QLhHg.s:130 .text.handle_over_maxtemp:00000000 handle_over_maxtemp + /tmp/cc1QLhHg.s:188 .text.handle_over_maxtemp:00000048 $d + /tmp/cc1QLhHg.s:194 .text.tmp1075_measure:00000000 $t + /tmp/cc1QLhHg.s:200 .text.tmp1075_measure:00000000 tmp1075_measure + /tmp/cc1QLhHg.s:547 .text.tmp1075_sensor_read:00000000 tmp1075_sensor_read + /tmp/cc1QLhHg.s:473 .text.tmp1075_measure:00000198 $d + /tmp/cc1QLhHg.s:482 .text.tmp1075_sensor_init:00000000 $t + /tmp/cc1QLhHg.s:536 .text.tmp1075_sensor_init:0000003c $d + /tmp/cc1QLhHg.s:541 .text.tmp1075_sensor_read:00000000 $t + /tmp/cc1QLhHg.s:620 .text.tmp1075_sensor_read:00000060 $d + +UNDEFINED SYMBOLS +set_error_source +ftcan_marshal_unsigned +error_data +clear_error_source +state +HAL_I2C_Master_Transmit +HAL_I2C_Master_Receive diff --git a/Software/build/TMP1075.o b/Software/build/TMP1075.o new file mode 100644 index 0000000..e3f2bcb Binary files /dev/null and b/Software/build/TMP1075.o differ diff --git a/Software/build/can-halal.d b/Software/build/can-halal.d new file mode 100644 index 0000000..c682ad1 --- /dev/null +++ b/Software/build/can-halal.d @@ -0,0 +1,63 @@ +build/can-halal.o: Core/Lib/can-halal/can-halal.c \ + Core/Lib/can-halal/can-halal.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + Core/Inc/stm32f3xx_hal_conf.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h +Core/Lib/can-halal/can-halal.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h: diff --git a/Software/build/can-halal.lst b/Software/build/can-halal.lst new file mode 100644 index 0000000..4e3ac71 --- /dev/null +++ b/Software/build/can-halal.lst @@ -0,0 +1,1139 @@ +ARM GAS /tmp/ccI3jx5x.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 6 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "can-halal.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Core/Lib/can-halal/can-halal.c" + 20 .section .bss.hcan,"aw",%nobits + 21 .align 2 + 24 hcan: + 25 0000 00000000 .space 4 + 26 .section .text.ftcan_init,"ax",%progbits + 27 .align 1 + 28 .global ftcan_init + 29 .syntax unified + 30 .thumb + 31 .thumb_func + 33 ftcan_init: + 34 .LFB130: + 1:Core/Lib/can-halal/can-halal.c **** #include "can-halal.h" + 2:Core/Lib/can-halal/can-halal.c **** + 3:Core/Lib/can-halal/can-halal.c **** #include + 4:Core/Lib/can-halal/can-halal.c **** + 5:Core/Lib/can-halal/can-halal.c **** #if defined(FTCAN_IS_BXCAN) + 6:Core/Lib/can-halal/can-halal.c **** static CAN_HandleTypeDef *hcan; + 7:Core/Lib/can-halal/can-halal.c **** + 8:Core/Lib/can-halal/can-halal.c **** HAL_StatusTypeDef ftcan_init(CAN_HandleTypeDef *handle) { + 35 .loc 1 8 57 + 36 .cfi_startproc + 37 @ args = 0, pretend = 0, frame = 16 + 38 @ frame_needed = 1, uses_anonymous_args = 0 + 39 0000 80B5 push {r7, lr} + 40 .cfi_def_cfa_offset 8 + 41 .cfi_offset 7, -8 + 42 .cfi_offset 14, -4 + 43 0002 84B0 sub sp, sp, #16 + 44 .cfi_def_cfa_offset 24 + 45 0004 00AF add r7, sp, #0 + 46 .cfi_def_cfa_register 7 + 47 0006 7860 str r0, [r7, #4] + 9:Core/Lib/can-halal/can-halal.c **** hcan = handle; + 48 .loc 1 9 8 + 49 0008 0C4A ldr r2, .L4 + 50 000a 7B68 ldr r3, [r7, #4] + 51 000c 1360 str r3, [r2] + ARM GAS /tmp/ccI3jx5x.s page 2 + + + 10:Core/Lib/can-halal/can-halal.c **** + 11:Core/Lib/can-halal/can-halal.c **** HAL_StatusTypeDef status = + 12:Core/Lib/can-halal/can-halal.c **** HAL_CAN_ActivateNotification(hcan, CAN_IT_RX_FIFO0_MSG_PENDING); + 52 .loc 1 12 7 + 53 000e 0B4B ldr r3, .L4 + 54 0010 1B68 ldr r3, [r3] + 55 0012 0221 movs r1, #2 + 56 0014 1846 mov r0, r3 + 57 0016 FFF7FEFF bl HAL_CAN_ActivateNotification + 58 001a 0346 mov r3, r0 + 59 001c FB73 strb r3, [r7, #15] + 13:Core/Lib/can-halal/can-halal.c **** if (status != HAL_OK) { + 60 .loc 1 13 6 + 61 001e FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 62 0020 002B cmp r3, #0 + 63 0022 01D0 beq .L2 + 14:Core/Lib/can-halal/can-halal.c **** return status; + 64 .loc 1 14 12 + 65 0024 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 66 0026 05E0 b .L3 + 67 .L2: + 15:Core/Lib/can-halal/can-halal.c **** } + 16:Core/Lib/can-halal/can-halal.c **** + 17:Core/Lib/can-halal/can-halal.c **** return HAL_CAN_Start(hcan); + 68 .loc 1 17 10 + 69 0028 044B ldr r3, .L4 + 70 002a 1B68 ldr r3, [r3] + 71 002c 1846 mov r0, r3 + 72 002e FFF7FEFF bl HAL_CAN_Start + 73 0032 0346 mov r3, r0 + 74 .L3: + 18:Core/Lib/can-halal/can-halal.c **** } + 75 .loc 1 18 1 + 76 0034 1846 mov r0, r3 + 77 0036 1037 adds r7, r7, #16 + 78 .cfi_def_cfa_offset 8 + 79 0038 BD46 mov sp, r7 + 80 .cfi_def_cfa_register 13 + 81 @ sp needed + 82 003a 80BD pop {r7, pc} + 83 .L5: + 84 .align 2 + 85 .L4: + 86 003c 00000000 .word hcan + 87 .cfi_endproc + 88 .LFE130: + 90 .section .text.ftcan_transmit,"ax",%progbits + 91 .align 1 + 92 .global ftcan_transmit + 93 .syntax unified + 94 .thumb + 95 .thumb_func + 97 ftcan_transmit: + 98 .LFB131: + 19:Core/Lib/can-halal/can-halal.c **** + 20:Core/Lib/can-halal/can-halal.c **** HAL_StatusTypeDef ftcan_transmit(uint16_t id, const uint8_t *data, + 21:Core/Lib/can-halal/can-halal.c **** size_t datalen) { + ARM GAS /tmp/ccI3jx5x.s page 3 + + + 99 .loc 1 21 50 + 100 .cfi_startproc + 101 @ args = 0, pretend = 0, frame = 24 + 102 @ frame_needed = 1, uses_anonymous_args = 0 + 103 0000 80B5 push {r7, lr} + 104 .cfi_def_cfa_offset 8 + 105 .cfi_offset 7, -8 + 106 .cfi_offset 14, -4 + 107 0002 86B0 sub sp, sp, #24 + 108 .cfi_def_cfa_offset 32 + 109 0004 00AF add r7, sp, #0 + 110 .cfi_def_cfa_register 7 + 111 0006 0346 mov r3, r0 + 112 0008 B960 str r1, [r7, #8] + 113 000a 7A60 str r2, [r7, #4] + 114 000c FB81 strh r3, [r7, #14] @ movhi + 22:Core/Lib/can-halal/can-halal.c **** static CAN_TxHeaderTypeDef header; + 23:Core/Lib/can-halal/can-halal.c **** header.StdId = id; + 115 .loc 1 23 16 + 116 000e FB89 ldrh r3, [r7, #14] + 117 0010 0B4A ldr r2, .L8 + 118 0012 1360 str r3, [r2] + 24:Core/Lib/can-halal/can-halal.c **** header.IDE = CAN_ID_STD; + 119 .loc 1 24 14 + 120 0014 0A4B ldr r3, .L8 + 121 0016 0022 movs r2, #0 + 122 0018 9A60 str r2, [r3, #8] + 25:Core/Lib/can-halal/can-halal.c **** header.RTR = CAN_RTR_DATA; + 123 .loc 1 25 14 + 124 001a 094B ldr r3, .L8 + 125 001c 0022 movs r2, #0 + 126 001e DA60 str r2, [r3, #12] + 26:Core/Lib/can-halal/can-halal.c **** header.DLC = datalen; + 127 .loc 1 26 14 + 128 0020 074A ldr r2, .L8 + 129 0022 7B68 ldr r3, [r7, #4] + 130 0024 1361 str r3, [r2, #16] + 27:Core/Lib/can-halal/can-halal.c **** uint32_t mailbox; + 28:Core/Lib/can-halal/can-halal.c **** return HAL_CAN_AddTxMessage(hcan, &header, data, &mailbox); + 131 .loc 1 28 10 + 132 0026 074B ldr r3, .L8+4 + 133 0028 1868 ldr r0, [r3] + 134 002a 07F11403 add r3, r7, #20 + 135 002e BA68 ldr r2, [r7, #8] + 136 0030 0349 ldr r1, .L8 + 137 0032 FFF7FEFF bl HAL_CAN_AddTxMessage + 138 0036 0346 mov r3, r0 + 29:Core/Lib/can-halal/can-halal.c **** } + 139 .loc 1 29 1 + 140 0038 1846 mov r0, r3 + 141 003a 1837 adds r7, r7, #24 + 142 .cfi_def_cfa_offset 8 + 143 003c BD46 mov sp, r7 + 144 .cfi_def_cfa_register 13 + 145 @ sp needed + 146 003e 80BD pop {r7, pc} + 147 .L9: + ARM GAS /tmp/ccI3jx5x.s page 4 + + + 148 .align 2 + 149 .L8: + 150 0040 00000000 .word header.2 + 151 0044 00000000 .word hcan + 152 .cfi_endproc + 153 .LFE131: + 155 .section .text.ftcan_add_filter,"ax",%progbits + 156 .align 1 + 157 .global ftcan_add_filter + 158 .syntax unified + 159 .thumb + 160 .thumb_func + 162 ftcan_add_filter: + 163 .LFB132: + 30:Core/Lib/can-halal/can-halal.c **** + 31:Core/Lib/can-halal/can-halal.c **** HAL_StatusTypeDef ftcan_add_filter(uint16_t id, uint16_t mask) { + 164 .loc 1 31 64 + 165 .cfi_startproc + 166 @ args = 0, pretend = 0, frame = 16 + 167 @ frame_needed = 1, uses_anonymous_args = 0 + 168 0000 80B5 push {r7, lr} + 169 .cfi_def_cfa_offset 8 + 170 .cfi_offset 7, -8 + 171 .cfi_offset 14, -4 + 172 0002 84B0 sub sp, sp, #16 + 173 .cfi_def_cfa_offset 24 + 174 0004 00AF add r7, sp, #0 + 175 .cfi_def_cfa_register 7 + 176 0006 0346 mov r3, r0 + 177 0008 0A46 mov r2, r1 + 178 000a FB80 strh r3, [r7, #6] @ movhi + 179 000c 1346 mov r3, r2 @ movhi + 180 000e BB80 strh r3, [r7, #4] @ movhi + 32:Core/Lib/can-halal/can-halal.c **** static uint32_t next_filter_no = 0; + 33:Core/Lib/can-halal/can-halal.c **** static CAN_FilterTypeDef filter; + 34:Core/Lib/can-halal/can-halal.c **** if (next_filter_no % 2 == 0) { + 181 .loc 1 34 22 + 182 0010 264B ldr r3, .L16 + 183 0012 1B68 ldr r3, [r3] + 184 0014 03F00103 and r3, r3, #1 + 185 .loc 1 34 6 + 186 0018 002B cmp r3, #0 + 187 001a 10D1 bne .L11 + 35:Core/Lib/can-halal/can-halal.c **** filter.FilterIdHigh = id << 5; + 188 .loc 1 35 30 + 189 001c FB88 ldrh r3, [r7, #6] + 190 001e 5B01 lsls r3, r3, #5 + 191 .loc 1 35 25 + 192 0020 234A ldr r2, .L16+4 + 193 0022 1360 str r3, [r2] + 36:Core/Lib/can-halal/can-halal.c **** filter.FilterMaskIdHigh = mask << 5; + 194 .loc 1 36 36 + 195 0024 BB88 ldrh r3, [r7, #4] + 196 0026 5B01 lsls r3, r3, #5 + 197 .loc 1 36 29 + 198 0028 214A ldr r2, .L16+4 + 199 002a 9360 str r3, [r2, #8] + ARM GAS /tmp/ccI3jx5x.s page 5 + + + 37:Core/Lib/can-halal/can-halal.c **** filter.FilterIdLow = id << 5; + 200 .loc 1 37 29 + 201 002c FB88 ldrh r3, [r7, #6] + 202 002e 5B01 lsls r3, r3, #5 + 203 .loc 1 37 24 + 204 0030 1F4A ldr r2, .L16+4 + 205 0032 5360 str r3, [r2, #4] + 38:Core/Lib/can-halal/can-halal.c **** filter.FilterMaskIdLow = mask << 5; + 206 .loc 1 38 35 + 207 0034 BB88 ldrh r3, [r7, #4] + 208 0036 5B01 lsls r3, r3, #5 + 209 .loc 1 38 28 + 210 0038 1D4A ldr r2, .L16+4 + 211 003a D360 str r3, [r2, #12] + 212 003c 07E0 b .L12 + 213 .L11: + 39:Core/Lib/can-halal/can-halal.c **** } else { + 40:Core/Lib/can-halal/can-halal.c **** // Leave high filter untouched from the last configuration + 41:Core/Lib/can-halal/can-halal.c **** filter.FilterIdLow = id << 5; + 214 .loc 1 41 29 + 215 003e FB88 ldrh r3, [r7, #6] + 216 0040 5B01 lsls r3, r3, #5 + 217 .loc 1 41 24 + 218 0042 1B4A ldr r2, .L16+4 + 219 0044 5360 str r3, [r2, #4] + 42:Core/Lib/can-halal/can-halal.c **** filter.FilterMaskIdLow = mask << 5; + 220 .loc 1 42 35 + 221 0046 BB88 ldrh r3, [r7, #4] + 222 0048 5B01 lsls r3, r3, #5 + 223 .loc 1 42 28 + 224 004a 194A ldr r2, .L16+4 + 225 004c D360 str r3, [r2, #12] + 226 .L12: + 43:Core/Lib/can-halal/can-halal.c **** } + 44:Core/Lib/can-halal/can-halal.c **** filter.FilterFIFOAssignment = CAN_FILTER_FIFO0; + 227 .loc 1 44 31 + 228 004e 184B ldr r3, .L16+4 + 229 0050 0022 movs r2, #0 + 230 0052 1A61 str r2, [r3, #16] + 45:Core/Lib/can-halal/can-halal.c **** filter.FilterBank = next_filter_no / 2; + 231 .loc 1 45 38 + 232 0054 154B ldr r3, .L16 + 233 0056 1B68 ldr r3, [r3] + 234 0058 5B08 lsrs r3, r3, #1 + 235 .loc 1 45 21 + 236 005a 154A ldr r2, .L16+4 + 237 005c 5361 str r3, [r2, #20] + 46:Core/Lib/can-halal/can-halal.c **** if (filter.FilterBank > FTCAN_NUM_FILTERS + 1) { + 238 .loc 1 46 13 + 239 005e 144B ldr r3, .L16+4 + 240 0060 5B69 ldr r3, [r3, #20] + 241 .loc 1 46 6 + 242 0062 0E2B cmp r3, #14 + 243 0064 01D9 bls .L13 + 47:Core/Lib/can-halal/can-halal.c **** return HAL_ERROR; + 244 .loc 1 47 12 + 245 0066 0123 movs r3, #1 + ARM GAS /tmp/ccI3jx5x.s page 6 + + + 246 0068 1CE0 b .L14 + 247 .L13: + 48:Core/Lib/can-halal/can-halal.c **** } + 49:Core/Lib/can-halal/can-halal.c **** filter.FilterMode = CAN_FILTERMODE_IDMASK; + 248 .loc 1 49 21 + 249 006a 114B ldr r3, .L16+4 + 250 006c 0022 movs r2, #0 + 251 006e 9A61 str r2, [r3, #24] + 50:Core/Lib/can-halal/can-halal.c **** filter.FilterScale = CAN_FILTERSCALE_16BIT; + 252 .loc 1 50 22 + 253 0070 0F4B ldr r3, .L16+4 + 254 0072 0022 movs r2, #0 + 255 0074 DA61 str r2, [r3, #28] + 51:Core/Lib/can-halal/can-halal.c **** filter.FilterActivation = CAN_FILTER_ENABLE; + 256 .loc 1 51 27 + 257 0076 0E4B ldr r3, .L16+4 + 258 0078 0122 movs r2, #1 + 259 007a 1A62 str r2, [r3, #32] + 52:Core/Lib/can-halal/can-halal.c **** + 53:Core/Lib/can-halal/can-halal.c **** // Disable slave filters + 54:Core/Lib/can-halal/can-halal.c **** // TODO: Some STM32 have multiple CAN peripherals, and one uses the slave + 55:Core/Lib/can-halal/can-halal.c **** // filter bank + 56:Core/Lib/can-halal/can-halal.c **** filter.SlaveStartFilterBank = FTCAN_NUM_FILTERS; + 260 .loc 1 56 31 + 261 007c 0C4B ldr r3, .L16+4 + 262 007e 0D22 movs r2, #13 + 263 0080 5A62 str r2, [r3, #36] + 57:Core/Lib/can-halal/can-halal.c **** + 58:Core/Lib/can-halal/can-halal.c **** HAL_StatusTypeDef status = HAL_CAN_ConfigFilter(hcan, &filter); + 264 .loc 1 58 30 + 265 0082 0C4B ldr r3, .L16+8 + 266 0084 1B68 ldr r3, [r3] + 267 0086 0A49 ldr r1, .L16+4 + 268 0088 1846 mov r0, r3 + 269 008a FFF7FEFF bl HAL_CAN_ConfigFilter + 270 008e 0346 mov r3, r0 + 271 0090 FB73 strb r3, [r7, #15] + 59:Core/Lib/can-halal/can-halal.c **** if (status == HAL_OK) { + 272 .loc 1 59 6 + 273 0092 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 274 0094 002B cmp r3, #0 + 275 0096 04D1 bne .L15 + 60:Core/Lib/can-halal/can-halal.c **** next_filter_no++; + 276 .loc 1 60 19 + 277 0098 044B ldr r3, .L16 + 278 009a 1B68 ldr r3, [r3] + 279 009c 0133 adds r3, r3, #1 + 280 009e 034A ldr r2, .L16 + 281 00a0 1360 str r3, [r2] + 282 .L15: + 61:Core/Lib/can-halal/can-halal.c **** } + 62:Core/Lib/can-halal/can-halal.c **** return status; + 283 .loc 1 62 10 + 284 00a2 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 285 .L14: + 63:Core/Lib/can-halal/can-halal.c **** } + 286 .loc 1 63 1 + ARM GAS /tmp/ccI3jx5x.s page 7 + + + 287 00a4 1846 mov r0, r3 + 288 00a6 1037 adds r7, r7, #16 + 289 .cfi_def_cfa_offset 8 + 290 00a8 BD46 mov sp, r7 + 291 .cfi_def_cfa_register 13 + 292 @ sp needed + 293 00aa 80BD pop {r7, pc} + 294 .L17: + 295 .align 2 + 296 .L16: + 297 00ac 00000000 .word next_filter_no.1 + 298 00b0 00000000 .word filter.0 + 299 00b4 00000000 .word hcan + 300 .cfi_endproc + 301 .LFE132: + 303 .section .text.HAL_CAN_RxFifo0MsgPendingCallback,"ax",%progbits + 304 .align 1 + 305 .global HAL_CAN_RxFifo0MsgPendingCallback + 306 .syntax unified + 307 .thumb + 308 .thumb_func + 310 HAL_CAN_RxFifo0MsgPendingCallback: + 311 .LFB133: + 64:Core/Lib/can-halal/can-halal.c **** + 65:Core/Lib/can-halal/can-halal.c **** void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *handle) { + 312 .loc 1 65 67 + 313 .cfi_startproc + 314 @ args = 0, pretend = 0, frame = 48 + 315 @ frame_needed = 1, uses_anonymous_args = 0 + 316 0000 80B5 push {r7, lr} + 317 .cfi_def_cfa_offset 8 + 318 .cfi_offset 7, -8 + 319 .cfi_offset 14, -4 + 320 0002 8CB0 sub sp, sp, #48 + 321 .cfi_def_cfa_offset 56 + 322 0004 00AF add r7, sp, #0 + 323 .cfi_def_cfa_register 7 + 324 0006 7860 str r0, [r7, #4] + 66:Core/Lib/can-halal/can-halal.c **** if (handle != hcan) { + 325 .loc 1 66 14 + 326 0008 124B ldr r3, .L27 + 327 000a 1B68 ldr r3, [r3] + 328 .loc 1 66 6 + 329 000c 7A68 ldr r2, [r7, #4] + 330 000e 9A42 cmp r2, r3 + 331 0010 17D1 bne .L24 + 67:Core/Lib/can-halal/can-halal.c **** return; + 68:Core/Lib/can-halal/can-halal.c **** } + 69:Core/Lib/can-halal/can-halal.c **** CAN_RxHeaderTypeDef header; + 70:Core/Lib/can-halal/can-halal.c **** uint8_t data[8]; + 71:Core/Lib/can-halal/can-halal.c **** if (HAL_CAN_GetRxMessage(hcan, CAN_RX_FIFO0, &header, data) != HAL_OK) { + 332 .loc 1 71 7 + 333 0012 104B ldr r3, .L27 + 334 0014 1868 ldr r0, [r3] + 335 0016 07F10C03 add r3, r7, #12 + 336 001a 07F11402 add r2, r7, #20 + 337 001e 0021 movs r1, #0 + ARM GAS /tmp/ccI3jx5x.s page 8 + + + 338 0020 FFF7FEFF bl HAL_CAN_GetRxMessage + 339 0024 0346 mov r3, r0 + 340 .loc 1 71 6 discriminator 1 + 341 0026 002B cmp r3, #0 + 342 0028 0DD1 bne .L25 + 72:Core/Lib/can-halal/can-halal.c **** return; + 73:Core/Lib/can-halal/can-halal.c **** } + 74:Core/Lib/can-halal/can-halal.c **** + 75:Core/Lib/can-halal/can-halal.c **** if (header.IDE != CAN_ID_STD) { + 343 .loc 1 75 13 + 344 002a FB69 ldr r3, [r7, #28] + 345 .loc 1 75 6 + 346 002c 002B cmp r3, #0 + 347 002e 0CD1 bne .L26 + 76:Core/Lib/can-halal/can-halal.c **** return; + 77:Core/Lib/can-halal/can-halal.c **** } + 78:Core/Lib/can-halal/can-halal.c **** + 79:Core/Lib/can-halal/can-halal.c **** ftcan_msg_received_cb(header.StdId, header.DLC, data); + 348 .loc 1 79 31 + 349 0030 7B69 ldr r3, [r7, #20] + 350 .loc 1 79 3 + 351 0032 9BB2 uxth r3, r3 + 352 .loc 1 79 45 + 353 0034 796A ldr r1, [r7, #36] + 354 .loc 1 79 3 + 355 0036 07F10C02 add r2, r7, #12 + 356 003a 1846 mov r0, r3 + 357 003c FFF7FEFF bl ftcan_msg_received_cb + 358 0040 04E0 b .L18 + 359 .L24: + 67:Core/Lib/can-halal/can-halal.c **** } + 360 .loc 1 67 5 + 361 0042 00BF nop + 362 0044 02E0 b .L18 + 363 .L25: + 72:Core/Lib/can-halal/can-halal.c **** return; + 364 .loc 1 72 5 + 365 0046 00BF nop + 366 0048 00E0 b .L18 + 367 .L26: + 76:Core/Lib/can-halal/can-halal.c **** return; + 368 .loc 1 76 5 + 369 004a 00BF nop + 370 .L18: + 80:Core/Lib/can-halal/can-halal.c **** } + 371 .loc 1 80 1 + 372 004c 3037 adds r7, r7, #48 + 373 .cfi_def_cfa_offset 8 + 374 004e BD46 mov sp, r7 + 375 .cfi_def_cfa_register 13 + 376 @ sp needed + 377 0050 80BD pop {r7, pc} + 378 .L28: + 379 0052 00BF .align 2 + 380 .L27: + 381 0054 00000000 .word hcan + 382 .cfi_endproc + ARM GAS /tmp/ccI3jx5x.s page 9 + + + 383 .LFE133: + 385 .section .text.ftcan_msg_received_cb,"ax",%progbits + 386 .align 1 + 387 .weak ftcan_msg_received_cb + 388 .syntax unified + 389 .thumb + 390 .thumb_func + 392 ftcan_msg_received_cb: + 393 .LFB134: + 81:Core/Lib/can-halal/can-halal.c **** #elif defined(FTCAN_IS_FDCAN) + 82:Core/Lib/can-halal/can-halal.c **** static FDCAN_HandleTypeDef *hcan; + 83:Core/Lib/can-halal/can-halal.c **** + 84:Core/Lib/can-halal/can-halal.c **** HAL_StatusTypeDef ftcan_init(FDCAN_HandleTypeDef *handle) { + 85:Core/Lib/can-halal/can-halal.c **** hcan = handle; + 86:Core/Lib/can-halal/can-halal.c **** + 87:Core/Lib/can-halal/can-halal.c **** HAL_StatusTypeDef status = + 88:Core/Lib/can-halal/can-halal.c **** HAL_FDCAN_ActivateNotification(hcan, FDCAN_IT_RX_FIFO0_NEW_MESSAGE, 0); + 89:Core/Lib/can-halal/can-halal.c **** if (status != HAL_OK) { + 90:Core/Lib/can-halal/can-halal.c **** return status; + 91:Core/Lib/can-halal/can-halal.c **** } + 92:Core/Lib/can-halal/can-halal.c **** // Reject non-matching messages + 93:Core/Lib/can-halal/can-halal.c **** status = + 94:Core/Lib/can-halal/can-halal.c **** HAL_FDCAN_ConfigGlobalFilter(hcan, FDCAN_REJECT, FDCAN_REJECT, + 95:Core/Lib/can-halal/can-halal.c **** FDCAN_REJECT_REMOTE, FDCAN_REJECT_REMOTE); + 96:Core/Lib/can-halal/can-halal.c **** if (status != HAL_OK) { + 97:Core/Lib/can-halal/can-halal.c **** return status; + 98:Core/Lib/can-halal/can-halal.c **** } + 99:Core/Lib/can-halal/can-halal.c **** + 100:Core/Lib/can-halal/can-halal.c **** return HAL_FDCAN_Start(hcan); + 101:Core/Lib/can-halal/can-halal.c **** } + 102:Core/Lib/can-halal/can-halal.c **** + 103:Core/Lib/can-halal/can-halal.c **** HAL_StatusTypeDef ftcan_transmit(uint16_t id, const uint8_t *data, + 104:Core/Lib/can-halal/can-halal.c **** size_t datalen) { + 105:Core/Lib/can-halal/can-halal.c **** static FDCAN_TxHeaderTypeDef header; + 106:Core/Lib/can-halal/can-halal.c **** header.Identifier = id; + 107:Core/Lib/can-halal/can-halal.c **** header.IdType = FDCAN_STANDARD_ID; + 108:Core/Lib/can-halal/can-halal.c **** header.TxFrameType = FDCAN_DATA_FRAME; + 109:Core/Lib/can-halal/can-halal.c **** switch (datalen) { + 110:Core/Lib/can-halal/can-halal.c **** case 0: + 111:Core/Lib/can-halal/can-halal.c **** header.DataLength = FDCAN_DLC_BYTES_0; + 112:Core/Lib/can-halal/can-halal.c **** break; + 113:Core/Lib/can-halal/can-halal.c **** case 1: + 114:Core/Lib/can-halal/can-halal.c **** header.DataLength = FDCAN_DLC_BYTES_1; + 115:Core/Lib/can-halal/can-halal.c **** break; + 116:Core/Lib/can-halal/can-halal.c **** case 2: + 117:Core/Lib/can-halal/can-halal.c **** header.DataLength = FDCAN_DLC_BYTES_2; + 118:Core/Lib/can-halal/can-halal.c **** break; + 119:Core/Lib/can-halal/can-halal.c **** case 3: + 120:Core/Lib/can-halal/can-halal.c **** header.DataLength = FDCAN_DLC_BYTES_3; + 121:Core/Lib/can-halal/can-halal.c **** break; + 122:Core/Lib/can-halal/can-halal.c **** case 4: + 123:Core/Lib/can-halal/can-halal.c **** header.DataLength = FDCAN_DLC_BYTES_4; + 124:Core/Lib/can-halal/can-halal.c **** break; + 125:Core/Lib/can-halal/can-halal.c **** case 5: + 126:Core/Lib/can-halal/can-halal.c **** header.DataLength = FDCAN_DLC_BYTES_5; + 127:Core/Lib/can-halal/can-halal.c **** break; + 128:Core/Lib/can-halal/can-halal.c **** case 6: + ARM GAS /tmp/ccI3jx5x.s page 10 + + + 129:Core/Lib/can-halal/can-halal.c **** header.DataLength = FDCAN_DLC_BYTES_6; + 130:Core/Lib/can-halal/can-halal.c **** break; + 131:Core/Lib/can-halal/can-halal.c **** case 7: + 132:Core/Lib/can-halal/can-halal.c **** header.DataLength = FDCAN_DLC_BYTES_7; + 133:Core/Lib/can-halal/can-halal.c **** break; + 134:Core/Lib/can-halal/can-halal.c **** case 8: + 135:Core/Lib/can-halal/can-halal.c **** default: + 136:Core/Lib/can-halal/can-halal.c **** header.DataLength = FDCAN_DLC_BYTES_8; + 137:Core/Lib/can-halal/can-halal.c **** break; + 138:Core/Lib/can-halal/can-halal.c **** } + 139:Core/Lib/can-halal/can-halal.c **** header.ErrorStateIndicator = FDCAN_ESI_PASSIVE; + 140:Core/Lib/can-halal/can-halal.c **** header.BitRateSwitch = FDCAN_BRS_OFF; + 141:Core/Lib/can-halal/can-halal.c **** header.FDFormat = FDCAN_CLASSIC_CAN; + 142:Core/Lib/can-halal/can-halal.c **** header.TxEventFifoControl = FDCAN_NO_TX_EVENTS; + 143:Core/Lib/can-halal/can-halal.c **** + 144:Core/Lib/can-halal/can-halal.c **** // HAL_FDCAN_AddMessageToTxFifoQ doesn't modify the data, but it's not marked + 145:Core/Lib/can-halal/can-halal.c **** // as const for some reason. + 146:Core/Lib/can-halal/can-halal.c **** uint8_t *data_nonconst = (uint8_t *)data; + 147:Core/Lib/can-halal/can-halal.c **** return HAL_FDCAN_AddMessageToTxFifoQ(hcan, &header, data_nonconst); + 148:Core/Lib/can-halal/can-halal.c **** } + 149:Core/Lib/can-halal/can-halal.c **** + 150:Core/Lib/can-halal/can-halal.c **** HAL_StatusTypeDef ftcan_add_filter(uint16_t id, uint16_t mask) { + 151:Core/Lib/can-halal/can-halal.c **** static uint32_t next_filter_no = 0; + 152:Core/Lib/can-halal/can-halal.c **** static FDCAN_FilterTypeDef filter; + 153:Core/Lib/can-halal/can-halal.c **** filter.IdType = FDCAN_STANDARD_ID; + 154:Core/Lib/can-halal/can-halal.c **** filter.FilterIndex = next_filter_no; + 155:Core/Lib/can-halal/can-halal.c **** if (filter.FilterIndex > FTCAN_NUM_FILTERS + 1) { + 156:Core/Lib/can-halal/can-halal.c **** return HAL_ERROR; + 157:Core/Lib/can-halal/can-halal.c **** } + 158:Core/Lib/can-halal/can-halal.c **** filter.FilterType = FDCAN_FILTER_MASK; + 159:Core/Lib/can-halal/can-halal.c **** filter.FilterConfig = FDCAN_FILTER_TO_RXFIFO0; + 160:Core/Lib/can-halal/can-halal.c **** filter.FilterID1 = id; + 161:Core/Lib/can-halal/can-halal.c **** filter.FilterID2 = mask; + 162:Core/Lib/can-halal/can-halal.c **** + 163:Core/Lib/can-halal/can-halal.c **** HAL_StatusTypeDef status = HAL_FDCAN_ConfigFilter(hcan, &filter); + 164:Core/Lib/can-halal/can-halal.c **** if (status == HAL_OK) { + 165:Core/Lib/can-halal/can-halal.c **** next_filter_no++; + 166:Core/Lib/can-halal/can-halal.c **** } + 167:Core/Lib/can-halal/can-halal.c **** return status; + 168:Core/Lib/can-halal/can-halal.c **** } + 169:Core/Lib/can-halal/can-halal.c **** + 170:Core/Lib/can-halal/can-halal.c **** void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *handle, + 171:Core/Lib/can-halal/can-halal.c **** uint32_t RxFifo0ITs) { + 172:Core/Lib/can-halal/can-halal.c **** if (handle != hcan || (RxFifo0ITs & FDCAN_IT_RX_FIFO0_NEW_MESSAGE) == RESET) { + 173:Core/Lib/can-halal/can-halal.c **** return; + 174:Core/Lib/can-halal/can-halal.c **** } + 175:Core/Lib/can-halal/can-halal.c **** + 176:Core/Lib/can-halal/can-halal.c **** static FDCAN_RxHeaderTypeDef header; + 177:Core/Lib/can-halal/can-halal.c **** static uint8_t data[8]; + 178:Core/Lib/can-halal/can-halal.c **** if (HAL_FDCAN_GetRxMessage(hcan, FDCAN_RX_FIFO0, &header, data) != HAL_OK) { + 179:Core/Lib/can-halal/can-halal.c **** return; + 180:Core/Lib/can-halal/can-halal.c **** } + 181:Core/Lib/can-halal/can-halal.c **** + 182:Core/Lib/can-halal/can-halal.c **** if (header.FDFormat != FDCAN_CLASSIC_CAN || + 183:Core/Lib/can-halal/can-halal.c **** header.RxFrameType != FDCAN_DATA_FRAME || + 184:Core/Lib/can-halal/can-halal.c **** header.IdType != FDCAN_STANDARD_ID) { + 185:Core/Lib/can-halal/can-halal.c **** return; + ARM GAS /tmp/ccI3jx5x.s page 11 + + + 186:Core/Lib/can-halal/can-halal.c **** } + 187:Core/Lib/can-halal/can-halal.c **** + 188:Core/Lib/can-halal/can-halal.c **** size_t datalen; + 189:Core/Lib/can-halal/can-halal.c **** switch (header.DataLength) { + 190:Core/Lib/can-halal/can-halal.c **** case FDCAN_DLC_BYTES_0: + 191:Core/Lib/can-halal/can-halal.c **** datalen = 0; + 192:Core/Lib/can-halal/can-halal.c **** break; + 193:Core/Lib/can-halal/can-halal.c **** case FDCAN_DLC_BYTES_1: + 194:Core/Lib/can-halal/can-halal.c **** datalen = 1; + 195:Core/Lib/can-halal/can-halal.c **** break; + 196:Core/Lib/can-halal/can-halal.c **** case FDCAN_DLC_BYTES_2: + 197:Core/Lib/can-halal/can-halal.c **** datalen = 2; + 198:Core/Lib/can-halal/can-halal.c **** break; + 199:Core/Lib/can-halal/can-halal.c **** case FDCAN_DLC_BYTES_3: + 200:Core/Lib/can-halal/can-halal.c **** datalen = 3; + 201:Core/Lib/can-halal/can-halal.c **** break; + 202:Core/Lib/can-halal/can-halal.c **** case FDCAN_DLC_BYTES_4: + 203:Core/Lib/can-halal/can-halal.c **** datalen = 4; + 204:Core/Lib/can-halal/can-halal.c **** break; + 205:Core/Lib/can-halal/can-halal.c **** case FDCAN_DLC_BYTES_5: + 206:Core/Lib/can-halal/can-halal.c **** datalen = 5; + 207:Core/Lib/can-halal/can-halal.c **** break; + 208:Core/Lib/can-halal/can-halal.c **** case FDCAN_DLC_BYTES_6: + 209:Core/Lib/can-halal/can-halal.c **** datalen = 6; + 210:Core/Lib/can-halal/can-halal.c **** break; + 211:Core/Lib/can-halal/can-halal.c **** case FDCAN_DLC_BYTES_7: + 212:Core/Lib/can-halal/can-halal.c **** datalen = 7; + 213:Core/Lib/can-halal/can-halal.c **** break; + 214:Core/Lib/can-halal/can-halal.c **** case FDCAN_DLC_BYTES_8: + 215:Core/Lib/can-halal/can-halal.c **** datalen = 8; + 216:Core/Lib/can-halal/can-halal.c **** break; + 217:Core/Lib/can-halal/can-halal.c **** default: + 218:Core/Lib/can-halal/can-halal.c **** return; + 219:Core/Lib/can-halal/can-halal.c **** } + 220:Core/Lib/can-halal/can-halal.c **** + 221:Core/Lib/can-halal/can-halal.c **** ftcan_msg_received_cb(header.Identifier, datalen, data); + 222:Core/Lib/can-halal/can-halal.c **** } + 223:Core/Lib/can-halal/can-halal.c **** #endif + 224:Core/Lib/can-halal/can-halal.c **** + 225:Core/Lib/can-halal/can-halal.c **** __weak void ftcan_msg_received_cb(uint16_t id, size_t datalen, + 226:Core/Lib/can-halal/can-halal.c **** const uint8_t *data) {} + 394 .loc 1 226 56 + 395 .cfi_startproc + 396 @ args = 0, pretend = 0, frame = 16 + 397 @ frame_needed = 1, uses_anonymous_args = 0 + 398 @ link register save eliminated. + 399 0000 80B4 push {r7} + 400 .cfi_def_cfa_offset 4 + 401 .cfi_offset 7, -4 + 402 0002 85B0 sub sp, sp, #20 + 403 .cfi_def_cfa_offset 24 + 404 0004 00AF add r7, sp, #0 + 405 .cfi_def_cfa_register 7 + 406 0006 0346 mov r3, r0 + 407 0008 B960 str r1, [r7, #8] + 408 000a 7A60 str r2, [r7, #4] + 409 000c FB81 strh r3, [r7, #14] @ movhi + ARM GAS /tmp/ccI3jx5x.s page 12 + + + 410 .loc 1 226 57 + 411 000e 00BF nop + 412 0010 1437 adds r7, r7, #20 + 413 .cfi_def_cfa_offset 4 + 414 0012 BD46 mov sp, r7 + 415 .cfi_def_cfa_register 13 + 416 @ sp needed + 417 0014 5DF8047B ldr r7, [sp], #4 + 418 .cfi_restore 7 + 419 .cfi_def_cfa_offset 0 + 420 0018 7047 bx lr + 421 .cfi_endproc + 422 .LFE134: + 424 .section .text.ftcan_unmarshal_unsigned,"ax",%progbits + 425 .align 1 + 426 .global ftcan_unmarshal_unsigned + 427 .syntax unified + 428 .thumb + 429 .thumb_func + 431 ftcan_unmarshal_unsigned: + 432 .LFB135: + 227:Core/Lib/can-halal/can-halal.c **** + 228:Core/Lib/can-halal/can-halal.c **** uint64_t ftcan_unmarshal_unsigned(const uint8_t **data_ptr, size_t num_bytes) { + 433 .loc 1 228 79 + 434 .cfi_startproc + 435 @ args = 0, pretend = 0, frame = 24 + 436 @ frame_needed = 1, uses_anonymous_args = 0 + 437 @ link register save eliminated. + 438 0000 2DE9B003 push {r4, r5, r7, r8, r9} + 439 .cfi_def_cfa_offset 20 + 440 .cfi_offset 4, -20 + 441 .cfi_offset 5, -16 + 442 .cfi_offset 7, -12 + 443 .cfi_offset 8, -8 + 444 .cfi_offset 9, -4 + 445 0004 87B0 sub sp, sp, #28 + 446 .cfi_def_cfa_offset 48 + 447 0006 00AF add r7, sp, #0 + 448 .cfi_def_cfa_register 7 + 449 0008 7860 str r0, [r7, #4] + 450 000a 3960 str r1, [r7] + 229:Core/Lib/can-halal/can-halal.c **** if (num_bytes > 8) { + 451 .loc 1 229 6 + 452 000c 3B68 ldr r3, [r7] + 453 000e 082B cmp r3, #8 + 454 0010 01D9 bls .L31 + 230:Core/Lib/can-halal/can-halal.c **** num_bytes = 8; + 455 .loc 1 230 15 + 456 0012 0823 movs r3, #8 + 457 0014 3B60 str r3, [r7] + 458 .L31: + 231:Core/Lib/can-halal/can-halal.c **** } + 232:Core/Lib/can-halal/can-halal.c **** + 233:Core/Lib/can-halal/can-halal.c **** const uint8_t *data = *data_ptr; + 459 .loc 1 233 18 + 460 0016 7B68 ldr r3, [r7, #4] + 461 0018 1B68 ldr r3, [r3] + ARM GAS /tmp/ccI3jx5x.s page 13 + + + 462 001a BB60 str r3, [r7, #8] + 234:Core/Lib/can-halal/can-halal.c **** uint64_t result = 0; + 463 .loc 1 234 12 + 464 001c 4FF00002 mov r2, #0 + 465 0020 4FF00003 mov r3, #0 + 466 0024 C7E90423 strd r2, [r7, #16] + 467 .LBB2: + 235:Core/Lib/can-halal/can-halal.c **** for (size_t i = 0; i < num_bytes; i++) { + 468 .loc 1 235 15 + 469 0028 0023 movs r3, #0 + 470 002a FB60 str r3, [r7, #12] + 471 .loc 1 235 3 + 472 002c 1EE0 b .L32 + 473 .L33: + 236:Core/Lib/can-halal/can-halal.c **** result <<= 8; + 474 .loc 1 236 12 + 475 002e D7E90401 ldrd r0, [r7, #16] + 476 0032 4FF00002 mov r2, #0 + 477 0036 4FF00003 mov r3, #0 + 478 003a 0B02 lsls r3, r1, #8 + 479 003c 43EA1063 orr r3, r3, r0, lsr #24 + 480 0040 0202 lsls r2, r0, #8 + 481 0042 C7E90423 strd r2, [r7, #16] + 237:Core/Lib/can-halal/can-halal.c **** result |= data[i]; + 482 .loc 1 237 19 + 483 0046 BA68 ldr r2, [r7, #8] + 484 0048 FB68 ldr r3, [r7, #12] + 485 004a 1344 add r3, r3, r2 + 486 004c 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 487 004e DBB2 uxtb r3, r3 + 488 0050 0022 movs r2, #0 + 489 0052 1C46 mov r4, r3 + 490 0054 1546 mov r5, r2 + 491 .loc 1 237 12 + 492 0056 D7E90423 ldrd r2, [r7, #16] + 493 005a 42EA0408 orr r8, r2, r4 + 494 005e 43EA0509 orr r9, r3, r5 + 495 0062 C7E90489 strd r8, [r7, #16] + 235:Core/Lib/can-halal/can-halal.c **** for (size_t i = 0; i < num_bytes; i++) { + 496 .loc 1 235 38 discriminator 3 + 497 0066 FB68 ldr r3, [r7, #12] + 498 0068 0133 adds r3, r3, #1 + 499 006a FB60 str r3, [r7, #12] + 500 .L32: + 235:Core/Lib/can-halal/can-halal.c **** for (size_t i = 0; i < num_bytes; i++) { + 501 .loc 1 235 24 discriminator 1 + 502 006c FA68 ldr r2, [r7, #12] + 503 006e 3B68 ldr r3, [r7] + 504 0070 9A42 cmp r2, r3 + 505 0072 DCD3 bcc .L33 + 506 .LBE2: + 238:Core/Lib/can-halal/can-halal.c **** } + 239:Core/Lib/can-halal/can-halal.c **** *data_ptr += num_bytes; + 507 .loc 1 239 3 + 508 0074 7B68 ldr r3, [r7, #4] + 509 0076 1A68 ldr r2, [r3] + 510 .loc 1 239 13 + ARM GAS /tmp/ccI3jx5x.s page 14 + + + 511 0078 3B68 ldr r3, [r7] + 512 007a 1A44 add r2, r2, r3 + 513 007c 7B68 ldr r3, [r7, #4] + 514 007e 1A60 str r2, [r3] + 240:Core/Lib/can-halal/can-halal.c **** return result; + 515 .loc 1 240 10 + 516 0080 D7E90423 ldrd r2, [r7, #16] + 241:Core/Lib/can-halal/can-halal.c **** } + 517 .loc 1 241 1 + 518 0084 1046 mov r0, r2 + 519 0086 1946 mov r1, r3 + 520 0088 1C37 adds r7, r7, #28 + 521 .cfi_def_cfa_offset 20 + 522 008a BD46 mov sp, r7 + 523 .cfi_def_cfa_register 13 + 524 @ sp needed + 525 008c BDE8B003 pop {r4, r5, r7, r8, r9} + 526 .cfi_restore 9 + 527 .cfi_restore 8 + 528 .cfi_restore 7 + 529 .cfi_restore 5 + 530 .cfi_restore 4 + 531 .cfi_def_cfa_offset 0 + 532 0090 7047 bx lr + 533 .cfi_endproc + 534 .LFE135: + 536 .section .text.ftcan_unmarshal_signed,"ax",%progbits + 537 .align 1 + 538 .global ftcan_unmarshal_signed + 539 .syntax unified + 540 .thumb + 541 .thumb_func + 543 ftcan_unmarshal_signed: + 544 .LFB136: + 242:Core/Lib/can-halal/can-halal.c **** + 243:Core/Lib/can-halal/can-halal.c **** int64_t ftcan_unmarshal_signed(const uint8_t **data_ptr, size_t num_bytes) { + 545 .loc 1 243 76 + 546 .cfi_startproc + 547 @ args = 0, pretend = 0, frame = 32 + 548 @ frame_needed = 1, uses_anonymous_args = 0 + 549 0000 2DE9F043 push {r4, r5, r6, r7, r8, r9, lr} + 550 .cfi_def_cfa_offset 28 + 551 .cfi_offset 4, -28 + 552 .cfi_offset 5, -24 + 553 .cfi_offset 6, -20 + 554 .cfi_offset 7, -16 + 555 .cfi_offset 8, -12 + 556 .cfi_offset 9, -8 + 557 .cfi_offset 14, -4 + 558 0004 89B0 sub sp, sp, #36 + 559 .cfi_def_cfa_offset 64 + 560 0006 00AF add r7, sp, #0 + 561 .cfi_def_cfa_register 7 + 562 0008 7860 str r0, [r7, #4] + 563 000a 3960 str r1, [r7] + 244:Core/Lib/can-halal/can-halal.c **** if (num_bytes > 8) { + 564 .loc 1 244 6 + ARM GAS /tmp/ccI3jx5x.s page 15 + + + 565 000c 3B68 ldr r3, [r7] + 566 000e 082B cmp r3, #8 + 567 0010 01D9 bls .L36 + 245:Core/Lib/can-halal/can-halal.c **** num_bytes = 8; + 568 .loc 1 245 15 + 569 0012 0823 movs r3, #8 + 570 0014 3B60 str r3, [r7] + 571 .L36: + 246:Core/Lib/can-halal/can-halal.c **** } + 247:Core/Lib/can-halal/can-halal.c **** + 248:Core/Lib/can-halal/can-halal.c **** uint64_t result_unsigned = ftcan_unmarshal_unsigned(data_ptr, num_bytes); + 572 .loc 1 248 30 + 573 0016 3968 ldr r1, [r7] + 574 0018 7868 ldr r0, [r7, #4] + 575 001a FFF7FEFF bl ftcan_unmarshal_unsigned + 576 001e 0246 mov r2, r0 + 577 0020 0B46 mov r3, r1 + 578 .loc 1 248 12 discriminator 1 + 579 0022 C7E90423 strd r2, [r7, #16] + 249:Core/Lib/can-halal/can-halal.c **** // Sign extend by shifting left, then copying to a signed int and shifting + 250:Core/Lib/can-halal/can-halal.c **** // back to the right + 251:Core/Lib/can-halal/can-halal.c **** size_t diff_to_64 = 64 - num_bytes * 8; + 580 .loc 1 251 26 + 581 0026 3B68 ldr r3, [r7] + 582 0028 C3F10803 rsb r3, r3, #8 + 583 .loc 1 251 10 + 584 002c DB00 lsls r3, r3, #3 + 585 002e FB61 str r3, [r7, #28] + 252:Core/Lib/can-halal/can-halal.c **** result_unsigned <<= diff_to_64; + 586 .loc 1 252 19 + 587 0030 D7E90423 ldrd r2, [r7, #16] + 588 0034 F969 ldr r1, [r7, #28] + 589 0036 A1F12006 sub r6, r1, #32 + 590 003a C1F12000 rsb r0, r1, #32 + 591 003e 03FA01F5 lsl r5, r3, r1 + 592 0042 02FA06F6 lsl r6, r2, r6 + 593 0046 3543 orrs r5, r5, r6 + 594 0048 22FA00F0 lsr r0, r2, r0 + 595 004c 0543 orrs r5, r5, r0 + 596 004e 02FA01F4 lsl r4, r2, r1 + 597 0052 C7E90445 strd r4, [r7, #16] + 253:Core/Lib/can-halal/can-halal.c **** int64_t result; + 254:Core/Lib/can-halal/can-halal.c **** memcpy(&result, &result_unsigned, 8); + 598 .loc 1 254 3 + 599 0056 D7E90423 ldrd r2, [r7, #16] + 600 005a C7E90223 strd r2, [r7, #8] + 255:Core/Lib/can-halal/can-halal.c **** return result >> diff_to_64; + 601 .loc 1 255 17 + 602 005e D7E90223 ldrd r2, [r7, #8] + 603 0062 F969 ldr r1, [r7, #28] + 604 0064 C1F12004 rsb r4, r1, #32 + 605 0068 B1F12000 subs r0, r1, #32 + 606 006c 22FA01F8 lsr r8, r2, r1 + 607 0070 03FA04F4 lsl r4, r3, r4 + 608 0074 48EA0408 orr r8, r8, r4 + 609 0078 03D4 bmi .L37 + 610 007a 43FA00F0 asr r0, r3, r0 + ARM GAS /tmp/ccI3jx5x.s page 16 + + + 611 007e 48EA0008 orr r8, r8, r0 + 612 .L37: + 613 0082 43FA01F9 asr r9, r3, r1 + 614 0086 4246 mov r2, r8 + 615 0088 4B46 mov r3, r9 + 256:Core/Lib/can-halal/can-halal.c **** } + 616 .loc 1 256 1 + 617 008a 1046 mov r0, r2 + 618 008c 1946 mov r1, r3 + 619 008e 2437 adds r7, r7, #36 + 620 .cfi_def_cfa_offset 28 + 621 0090 BD46 mov sp, r7 + 622 .cfi_def_cfa_register 13 + 623 @ sp needed + 624 0092 BDE8F083 pop {r4, r5, r6, r7, r8, r9, pc} + 625 .cfi_endproc + 626 .LFE136: + 628 .section .text.ftcan_marshal_unsigned,"ax",%progbits + 629 .align 1 + 630 .global ftcan_marshal_unsigned + 631 .syntax unified + 632 .thumb + 633 .thumb_func + 635 ftcan_marshal_unsigned: + 636 .LFB137: + 257:Core/Lib/can-halal/can-halal.c **** + 258:Core/Lib/can-halal/can-halal.c **** uint8_t *ftcan_marshal_unsigned(uint8_t *data, uint64_t val, size_t num_bytes) { + 637 .loc 1 258 80 + 638 .cfi_startproc + 639 @ args = 4, pretend = 0, frame = 24 + 640 @ frame_needed = 1, uses_anonymous_args = 0 + 641 @ link register save eliminated. + 642 0000 80B4 push {r7} + 643 .cfi_def_cfa_offset 4 + 644 .cfi_offset 7, -4 + 645 0002 87B0 sub sp, sp, #28 + 646 .cfi_def_cfa_offset 32 + 647 0004 00AF add r7, sp, #0 + 648 .cfi_def_cfa_register 7 + 649 0006 F860 str r0, [r7, #12] + 650 0008 C7E90023 strd r2, [r7] + 259:Core/Lib/can-halal/can-halal.c **** if (num_bytes > 8) { + 651 .loc 1 259 6 + 652 000c 3B6A ldr r3, [r7, #32] + 653 000e 082B cmp r3, #8 + 654 0010 01D9 bls .L40 + 260:Core/Lib/can-halal/can-halal.c **** num_bytes = 8; + 655 .loc 1 260 15 + 656 0012 0823 movs r3, #8 + 657 0014 3B62 str r3, [r7, #32] + 658 .L40: + 659 .LBB3: + 261:Core/Lib/can-halal/can-halal.c **** } + 262:Core/Lib/can-halal/can-halal.c **** + 263:Core/Lib/can-halal/can-halal.c **** for (int i = num_bytes - 1; i >= 0; i--) { + 660 .loc 1 263 26 + 661 0016 3B6A ldr r3, [r7, #32] + ARM GAS /tmp/ccI3jx5x.s page 17 + + + 662 0018 013B subs r3, r3, #1 + 663 .loc 1 263 12 + 664 001a 7B61 str r3, [r7, #20] + 665 .loc 1 263 3 + 666 001c 13E0 b .L41 + 667 .L42: + 264:Core/Lib/can-halal/can-halal.c **** data[i] = val & 0xFF; + 668 .loc 1 264 9 + 669 001e 7B69 ldr r3, [r7, #20] + 670 0020 FA68 ldr r2, [r7, #12] + 671 0022 1344 add r3, r3, r2 + 672 .loc 1 264 13 + 673 0024 3A78 ldrb r2, [r7] @ zero_extendqisi2 + 674 0026 1A70 strb r2, [r3] + 265:Core/Lib/can-halal/can-halal.c **** val >>= 8; + 675 .loc 1 265 9 + 676 0028 D7E90001 ldrd r0, [r7] + 677 002c 4FF00002 mov r2, #0 + 678 0030 4FF00003 mov r3, #0 + 679 0034 020A lsrs r2, r0, #8 + 680 0036 42EA0162 orr r2, r2, r1, lsl #24 + 681 003a 0B0A lsrs r3, r1, #8 + 682 003c C7E90023 strd r2, [r7] + 263:Core/Lib/can-halal/can-halal.c **** data[i] = val & 0xFF; + 683 .loc 1 263 40 discriminator 3 + 684 0040 7B69 ldr r3, [r7, #20] + 685 0042 013B subs r3, r3, #1 + 686 0044 7B61 str r3, [r7, #20] + 687 .L41: + 263:Core/Lib/can-halal/can-halal.c **** data[i] = val & 0xFF; + 688 .loc 1 263 33 discriminator 1 + 689 0046 7B69 ldr r3, [r7, #20] + 690 0048 002B cmp r3, #0 + 691 004a E8DA bge .L42 + 692 .LBE3: + 266:Core/Lib/can-halal/can-halal.c **** } + 267:Core/Lib/can-halal/can-halal.c **** + 268:Core/Lib/can-halal/can-halal.c **** return data + num_bytes; + 693 .loc 1 268 15 + 694 004c FA68 ldr r2, [r7, #12] + 695 004e 3B6A ldr r3, [r7, #32] + 696 0050 1344 add r3, r3, r2 + 269:Core/Lib/can-halal/can-halal.c **** } + 697 .loc 1 269 1 + 698 0052 1846 mov r0, r3 + 699 0054 1C37 adds r7, r7, #28 + 700 .cfi_def_cfa_offset 4 + 701 0056 BD46 mov sp, r7 + 702 .cfi_def_cfa_register 13 + 703 @ sp needed + 704 0058 5DF8047B ldr r7, [sp], #4 + 705 .cfi_restore 7 + 706 .cfi_def_cfa_offset 0 + 707 005c 7047 bx lr + 708 .cfi_endproc + 709 .LFE137: + 711 .section .text.ftcan_marshal_signed,"ax",%progbits + ARM GAS /tmp/ccI3jx5x.s page 18 + + + 712 .align 1 + 713 .global ftcan_marshal_signed + 714 .syntax unified + 715 .thumb + 716 .thumb_func + 718 ftcan_marshal_signed: + 719 .LFB138: + 270:Core/Lib/can-halal/can-halal.c **** + 271:Core/Lib/can-halal/can-halal.c **** uint8_t *ftcan_marshal_signed(uint8_t *data, int64_t val, size_t num_bytes) { + 720 .loc 1 271 77 + 721 .cfi_startproc + 722 @ args = 4, pretend = 0, frame = 16 + 723 @ frame_needed = 1, uses_anonymous_args = 0 + 724 0000 80B5 push {r7, lr} + 725 .cfi_def_cfa_offset 8 + 726 .cfi_offset 7, -8 + 727 .cfi_offset 14, -4 + 728 0002 86B0 sub sp, sp, #24 + 729 .cfi_def_cfa_offset 32 + 730 0004 02AF add r7, sp, #8 + 731 .cfi_def_cfa 7, 24 + 732 0006 F860 str r0, [r7, #12] + 733 0008 C7E90023 strd r2, [r7] + 272:Core/Lib/can-halal/can-halal.c **** return ftcan_marshal_unsigned(data, val, num_bytes); + 734 .loc 1 272 10 + 735 000c D7E90023 ldrd r2, [r7] + 736 0010 B969 ldr r1, [r7, #24] + 737 0012 0091 str r1, [sp] + 738 0014 F868 ldr r0, [r7, #12] + 739 0016 FFF7FEFF bl ftcan_marshal_unsigned + 740 001a 0346 mov r3, r0 + 273:Core/Lib/can-halal/can-halal.c **** } + 741 .loc 1 273 1 + 742 001c 1846 mov r0, r3 + 743 001e 1037 adds r7, r7, #16 + 744 .cfi_def_cfa_offset 8 + 745 0020 BD46 mov sp, r7 + 746 .cfi_def_cfa_register 13 + 747 @ sp needed + 748 0022 80BD pop {r7, pc} + 749 .cfi_endproc + 750 .LFE138: + 752 .section .bss.header.2,"aw",%nobits + 753 .align 2 + 756 header.2: + 757 0000 00000000 .space 24 + 757 00000000 + 757 00000000 + 757 00000000 + 757 00000000 + 758 .section .bss.next_filter_no.1,"aw",%nobits + 759 .align 2 + 762 next_filter_no.1: + 763 0000 00000000 .space 4 + 764 .section .bss.filter.0,"aw",%nobits + 765 .align 2 + 768 filter.0: + ARM GAS /tmp/ccI3jx5x.s page 19 + + + 769 0000 00000000 .space 40 + 769 00000000 + 769 00000000 + 769 00000000 + 769 00000000 + 770 .text + 771 .Letext0: + 772 .file 2 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 773 .file 3 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 774 .file 4 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + 775 .file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h" + 776 .file 6 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/lib/gcc/arm-none-e + 777 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h" + 778 .file 8 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h" + ARM GAS /tmp/ccI3jx5x.s page 20 + + +DEFINED SYMBOLS + *ABS*:00000000 can-halal.c + /tmp/ccI3jx5x.s:21 .bss.hcan:00000000 $d + /tmp/ccI3jx5x.s:24 .bss.hcan:00000000 hcan + /tmp/ccI3jx5x.s:27 .text.ftcan_init:00000000 $t + /tmp/ccI3jx5x.s:33 .text.ftcan_init:00000000 ftcan_init + /tmp/ccI3jx5x.s:86 .text.ftcan_init:0000003c $d + /tmp/ccI3jx5x.s:91 .text.ftcan_transmit:00000000 $t + /tmp/ccI3jx5x.s:97 .text.ftcan_transmit:00000000 ftcan_transmit + /tmp/ccI3jx5x.s:150 .text.ftcan_transmit:00000040 $d + /tmp/ccI3jx5x.s:756 .bss.header.2:00000000 header.2 + /tmp/ccI3jx5x.s:156 .text.ftcan_add_filter:00000000 $t + /tmp/ccI3jx5x.s:162 .text.ftcan_add_filter:00000000 ftcan_add_filter + /tmp/ccI3jx5x.s:297 .text.ftcan_add_filter:000000ac $d + /tmp/ccI3jx5x.s:762 .bss.next_filter_no.1:00000000 next_filter_no.1 + /tmp/ccI3jx5x.s:768 .bss.filter.0:00000000 filter.0 + /tmp/ccI3jx5x.s:304 .text.HAL_CAN_RxFifo0MsgPendingCallback:00000000 $t + /tmp/ccI3jx5x.s:310 .text.HAL_CAN_RxFifo0MsgPendingCallback:00000000 HAL_CAN_RxFifo0MsgPendingCallback + /tmp/ccI3jx5x.s:392 .text.ftcan_msg_received_cb:00000000 ftcan_msg_received_cb + /tmp/ccI3jx5x.s:381 .text.HAL_CAN_RxFifo0MsgPendingCallback:00000054 $d + /tmp/ccI3jx5x.s:386 .text.ftcan_msg_received_cb:00000000 $t + /tmp/ccI3jx5x.s:425 .text.ftcan_unmarshal_unsigned:00000000 $t + /tmp/ccI3jx5x.s:431 .text.ftcan_unmarshal_unsigned:00000000 ftcan_unmarshal_unsigned + /tmp/ccI3jx5x.s:537 .text.ftcan_unmarshal_signed:00000000 $t + /tmp/ccI3jx5x.s:543 .text.ftcan_unmarshal_signed:00000000 ftcan_unmarshal_signed + /tmp/ccI3jx5x.s:629 .text.ftcan_marshal_unsigned:00000000 $t + /tmp/ccI3jx5x.s:635 .text.ftcan_marshal_unsigned:00000000 ftcan_marshal_unsigned + /tmp/ccI3jx5x.s:712 .text.ftcan_marshal_signed:00000000 $t + /tmp/ccI3jx5x.s:718 .text.ftcan_marshal_signed:00000000 ftcan_marshal_signed + /tmp/ccI3jx5x.s:753 .bss.header.2:00000000 $d + /tmp/ccI3jx5x.s:759 .bss.next_filter_no.1:00000000 $d + /tmp/ccI3jx5x.s:765 .bss.filter.0:00000000 $d + +UNDEFINED SYMBOLS +HAL_CAN_ActivateNotification +HAL_CAN_Start +HAL_CAN_AddTxMessage +HAL_CAN_ConfigFilter +HAL_CAN_GetRxMessage diff --git a/Software/build/can-halal.o b/Software/build/can-halal.o new file mode 100644 index 0000000..81314c5 Binary files /dev/null and b/Software/build/can-halal.o differ diff --git a/Software/build/can.d b/Software/build/can.d new file mode 100644 index 0000000..2c55082 --- /dev/null +++ b/Software/build/can.d @@ -0,0 +1,88 @@ +build/can.o: Core/Src/can.c Core/Inc/can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + Core/Inc/stm32f3xx_hal_conf.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h Core/Inc/main.h \ + Core/Lib/can-halal/can-halal.h Core/Inc/state_machine.h \ + Core/Inc/ADBMS_LL_Driver.h Core/Inc/AMS_HighLevel.h \ + Core/Inc/ADBMS_Abstraction.h Core/Inc/ADBMS_CMD_MAKROS.h \ + Core/Inc/errors.h Core/Inc/eeprom.h Core/Inc/soc_estimation.h \ + Core/Inc/state_machine.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h Core/Inc/TMP1075.h \ + Core/Inc/errors.h Core/Inc/PWM_control.h Core/Inc/status_LED.h \ + Core/Inc/TMP1075.h Core/Inc/soc_estimation.h +Core/Inc/can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h: +Core/Inc/main.h: +Core/Lib/can-halal/can-halal.h: +Core/Inc/state_machine.h: +Core/Inc/ADBMS_LL_Driver.h: +Core/Inc/AMS_HighLevel.h: +Core/Inc/ADBMS_Abstraction.h: +Core/Inc/ADBMS_CMD_MAKROS.h: +Core/Inc/errors.h: +Core/Inc/eeprom.h: +Core/Inc/soc_estimation.h: +Core/Inc/state_machine.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Core/Inc/TMP1075.h: +Core/Inc/errors.h: +Core/Inc/PWM_control.h: +Core/Inc/status_LED.h: +Core/Inc/TMP1075.h: +Core/Inc/soc_estimation.h: diff --git a/Software/build/can.lst b/Software/build/can.lst new file mode 100644 index 0000000..4cbc3f1 --- /dev/null +++ b/Software/build/can.lst @@ -0,0 +1,1160 @@ +ARM GAS /tmp/ccrYTcjJ.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 6 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "can.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Core/Src/can.c" + 20 .global id_to_log + 21 .section .bss.id_to_log,"aw",%nobits + 24 id_to_log: + 25 0000 00 .space 1 + 26 .global last_message + 27 .section .bss.last_message,"aw",%nobits + 28 .align 2 + 31 last_message: + 32 0000 00000000 .space 8 + 32 00000000 + 33 .global can_status_timer + 34 .section .bss.can_status_timer,"aw",%nobits + 35 .align 2 + 38 can_status_timer: + 39 0000 00000000 .space 4 + 40 .global can_log_timer + 41 .section .bss.can_log_timer,"aw",%nobits + 42 .align 2 + 45 can_log_timer: + 46 0000 00000000 .space 4 + 47 .global can_timeout_timer + 48 .section .bss.can_timeout_timer,"aw",%nobits + 49 .align 2 + 52 can_timeout_timer: + 53 0000 00000000 .space 4 + 54 .section .text.can_init,"ax",%progbits + 55 .align 1 + 56 .global can_init + 57 .syntax unified + 58 .thumb + 59 .thumb_func + 61 can_init: + 62 .LFB130: + 1:Core/Src/can.c **** /* + 2:Core/Src/can.c **** * can.h + 3:Core/Src/can.c **** * + 4:Core/Src/can.c **** * Created on: 07.07.2024 + 5:Core/Src/can.c **** * Author: Hamza + ARM GAS /tmp/ccrYTcjJ.s page 2 + + + 6:Core/Src/can.c **** */ + 7:Core/Src/can.c **** + 8:Core/Src/can.c **** #include "can.h" + 9:Core/Src/can.c **** #include "AMS_HighLevel.h" + 10:Core/Src/can.c **** #include "PWM_control.h" + 11:Core/Src/can.c **** #include "TMP1075.h" + 12:Core/Src/can.c **** #include "can-halal.h" + 13:Core/Src/can.c **** #include "eeprom.h" + 14:Core/Src/can.c **** #include "soc_estimation.h" + 15:Core/Src/can.c **** #include "state_machine.h" + 16:Core/Src/can.c **** #include "stm32f3xx_hal.h" + 17:Core/Src/can.c **** #include "stm32f3xx_hal_def.h" + 18:Core/Src/can.c **** #include + 19:Core/Src/can.c **** + 20:Core/Src/can.c **** #define CAN_ID_IN 0x501 + 21:Core/Src/can.c **** #define CAN_ID_OUT 0x502 + 22:Core/Src/can.c **** #define CAN_ID_LOG 0x503 + 23:Core/Src/can.c **** + 24:Core/Src/can.c **** // Every X ms, send message + 25:Core/Src/can.c **** #define CAN_STATUS_FREQ 1000 + 26:Core/Src/can.c **** #define CAN_LOGGING_FREQ 200 + 27:Core/Src/can.c **** #define CAN_DUMP_FREQ 10 + 28:Core/Src/can.c **** + 29:Core/Src/can.c **** // Max time to wait for CAN messages. If we reach it then we target state is set to STATE_ERROR. + 30:Core/Src/can.c **** #define CAN_TIMEOUT 5000 + 31:Core/Src/can.c **** + 32:Core/Src/can.c **** uint8_t id_to_log; + 33:Core/Src/can.c **** uint8_t last_message[8]; + 34:Core/Src/can.c **** uint32_t can_status_timer, can_log_timer, can_timeout_timer; + 35:Core/Src/can.c **** + 36:Core/Src/can.c **** void can_init(CAN_HandleTypeDef* hcan) { + 63 .loc 1 36 40 + 64 .cfi_startproc + 65 @ args = 0, pretend = 0, frame = 8 + 66 @ frame_needed = 1, uses_anonymous_args = 0 + 67 0000 80B5 push {r7, lr} + 68 .cfi_def_cfa_offset 8 + 69 .cfi_offset 7, -8 + 70 .cfi_offset 14, -4 + 71 0002 82B0 sub sp, sp, #8 + 72 .cfi_def_cfa_offset 16 + 73 0004 00AF add r7, sp, #0 + 74 .cfi_def_cfa_register 7 + 75 0006 7860 str r0, [r7, #4] + 37:Core/Src/can.c **** ftcan_init(hcan); + 76 .loc 1 37 3 + 77 0008 7868 ldr r0, [r7, #4] + 78 000a FFF7FEFF bl ftcan_init + 38:Core/Src/can.c **** ftcan_add_filter(CAN_ID_IN, 0xFFF); + 79 .loc 1 38 3 + 80 000e 40F6FF71 movw r1, #4095 + 81 0012 40F20150 movw r0, #1281 + 82 0016 FFF7FEFF bl ftcan_add_filter + 39:Core/Src/can.c **** last_message[0] = -1; + 83 .loc 1 39 19 + 84 001a 114B ldr r3, .L2 + 85 001c FF22 movs r2, #255 + ARM GAS /tmp/ccrYTcjJ.s page 3 + + + 86 001e 1A70 strb r2, [r3] + 40:Core/Src/can.c **** last_message[1] = -1; + 87 .loc 1 40 19 + 88 0020 0F4B ldr r3, .L2 + 89 0022 FF22 movs r2, #255 + 90 0024 5A70 strb r2, [r3, #1] + 41:Core/Src/can.c **** can_status_timer = HAL_GetTick() + CAN_STATUS_FREQ; + 91 .loc 1 41 22 + 92 0026 FFF7FEFF bl HAL_GetTick + 93 002a 0346 mov r3, r0 + 94 .loc 1 41 36 discriminator 1 + 95 002c 03F57A73 add r3, r3, #1000 + 96 .loc 1 41 20 discriminator 1 + 97 0030 0C4A ldr r2, .L2+4 + 98 0032 1360 str r3, [r2] + 42:Core/Src/can.c **** can_log_timer = HAL_GetTick() + CAN_LOGGING_FREQ; + 99 .loc 1 42 19 + 100 0034 FFF7FEFF bl HAL_GetTick + 101 0038 0346 mov r3, r0 + 102 .loc 1 42 33 discriminator 1 + 103 003a C833 adds r3, r3, #200 + 104 .loc 1 42 17 discriminator 1 + 105 003c 0A4A ldr r2, .L2+8 + 106 003e 1360 str r3, [r2] + 43:Core/Src/can.c **** can_timeout_timer = HAL_GetTick() + CAN_TIMEOUT; + 107 .loc 1 43 23 + 108 0040 FFF7FEFF bl HAL_GetTick + 109 0044 0346 mov r3, r0 + 110 .loc 1 43 37 discriminator 1 + 111 0046 03F59C53 add r3, r3, #4992 + 112 004a 0833 adds r3, r3, #8 + 113 .loc 1 43 21 discriminator 1 + 114 004c 074A ldr r2, .L2+12 + 115 004e 1360 str r3, [r2] + 44:Core/Src/can.c **** id_to_log =0; + 116 .loc 1 44 13 + 117 0050 074B ldr r3, .L2+16 + 118 0052 0022 movs r2, #0 + 119 0054 1A70 strb r2, [r3] + 45:Core/Src/can.c **** } + 120 .loc 1 45 1 + 121 0056 00BF nop + 122 0058 0837 adds r7, r7, #8 + 123 .cfi_def_cfa_offset 8 + 124 005a BD46 mov sp, r7 + 125 .cfi_def_cfa_register 13 + 126 @ sp needed + 127 005c 80BD pop {r7, pc} + 128 .L3: + 129 005e 00BF .align 2 + 130 .L2: + 131 0060 00000000 .word last_message + 132 0064 00000000 .word can_status_timer + 133 0068 00000000 .word can_log_timer + 134 006c 00000000 .word can_timeout_timer + 135 0070 00000000 .word id_to_log + 136 .cfi_endproc + ARM GAS /tmp/ccrYTcjJ.s page 4 + + + 137 .LFE130: + 139 .global __aeabi_i2d + 140 .global __aeabi_ddiv + 141 .global __aeabi_d2f + 142 .section .text.can_handle_send_status,"ax",%progbits + 143 .align 1 + 144 .global can_handle_send_status + 145 .syntax unified + 146 .thumb + 147 .thumb_func + 149 can_handle_send_status: + 150 .LFB131: + 46:Core/Src/can.c **** + 47:Core/Src/can.c **** /* + 48:Core/Src/can.c **** This function sends the status of the mvbms, the battery and of powerground. + 49:Core/Src/can.c **** once every 1s in states: INACTIVE, PRECHARGE, DISCHARGE, CHARGING, ERROR. + 50:Core/Src/can.c **** once every 0.5s in states: READY, ACTIVE. + 51:Core/Src/can.c **** with format of: + 52:Core/Src/can.c **** CAN Messages: + 53:Core/Src/can.c **** Error bit + 54:Core/Src/can.c **** MVBMS state + 55:Core/Src/can.c **** Powerground Status 0-100% + 56:Core/Src/can.c **** Errors + 57:Core/Src/can.c **** Battery state of charge + 58:Core/Src/can.c **** Pack Voltage + 59:Core/Src/can.c **** Current + 60:Core/Src/can.c **** Battery temperature (12 bit) + 61:Core/Src/can.c **** + 62:Core/Src/can.c **** Min/Max. Cell Temp (ID, Min Temp, ID, Max Temp)(3B), + 63:Core/Src/can.c **** Min/Max Cell Voltage (ID, Min Voltage, ID, Max Voltage)(3B) + 64:Core/Src/can.c **** + 65:Core/Src/can.c **** bit 0 (1b): empty + 66:Core/Src/can.c **** bit 1-3 (3b): state + 67:Core/Src/can.c **** bit 4-11 (8b): powerground status + 68:Core/Src/can.c **** bit 12-19 (8b): error + 69:Core/Src/can.c **** bit 20-27 (8b): state of charge from 0-100% + 70:Core/Src/can.c **** bit 28-39 (12b): battery voltage + 71:Core/Src/can.c **** bit 40-51 (12b): current measurement + 72:Core/Src/can.c **** bit 52-63 (12b): temperature of the cell with highest temperature + 73:Core/Src/can.c **** + 74:Core/Src/can.c **** + 75:Core/Src/can.c **** bit 0-3 (4b): ID of the sensor with highest temperature + 76:Core/Src/can.c **** bit 4-7 (4b): ID of the sensor with lowest temperataure + 77:Core/Src/can.c **** bit 8-19 (12b): temperature of the coldest cell + 78:Core/Src/can.c **** bit 20-23 (4b): ID of the cell with the lowest voltage + 79:Core/Src/can.c **** bit 24-35 (12b): lowest cell voltage + 80:Core/Src/can.c **** bit 36-39 (4b): ID of the cell the the highest voltage + 81:Core/Src/can.c **** bit 40-51 (12b): highest cell voltage + 82:Core/Src/can.c **** bit 52-63 (12b): empty + 83:Core/Src/can.c **** */ + 84:Core/Src/can.c **** + 85:Core/Src/can.c **** void can_handle_send_status() { + 151 .loc 1 85 31 + 152 .cfi_startproc + 153 @ args = 0, pretend = 0, frame = 24 + 154 @ frame_needed = 1, uses_anonymous_args = 0 + 155 0000 80B5 push {r7, lr} + ARM GAS /tmp/ccrYTcjJ.s page 5 + + + 156 .cfi_def_cfa_offset 8 + 157 .cfi_offset 7, -8 + 158 .cfi_offset 14, -4 + 159 0002 86B0 sub sp, sp, #24 + 160 .cfi_def_cfa_offset 32 + 161 0004 00AF add r7, sp, #0 + 162 .cfi_def_cfa_register 7 + 86:Core/Src/can.c **** if (can_status_timer > HAL_GetTick()) + 163 .loc 1 86 26 + 164 0006 FFF7FEFF bl HAL_GetTick + 165 000a 0246 mov r2, r0 + 166 .loc 1 86 24 discriminator 1 + 167 000c 4D4B ldr r3, .L8 + 168 000e 1B68 ldr r3, [r3] + 169 .loc 1 86 6 discriminator 1 + 170 0010 9A42 cmp r2, r3 + 171 0012 C0F09380 bcc .L7 + 172 .LBB2: + 87:Core/Src/can.c **** return; + 88:Core/Src/can.c **** else { + 89:Core/Src/can.c **** uint8_t data[8] = {}; + 173 .loc 1 89 13 + 174 0016 07F11003 add r3, r7, #16 + 175 001a 0022 movs r2, #0 + 176 001c 1A60 str r2, [r3] + 177 001e 5A60 str r2, [r3, #4] + 90:Core/Src/can.c **** can_status_timer = HAL_GetTick() + CAN_STATUS_FREQ; + 178 .loc 1 90 24 + 179 0020 FFF7FEFF bl HAL_GetTick + 180 0024 0346 mov r3, r0 + 181 .loc 1 90 38 discriminator 1 + 182 0026 03F57A73 add r3, r3, #1000 + 183 .loc 1 90 22 discriminator 1 + 184 002a 464A ldr r2, .L8 + 185 002c 1360 str r3, [r2] + 91:Core/Src/can.c **** + 92:Core/Src/can.c **** uint8_t id_highest_temp = 0; + 186 .loc 1 92 13 + 187 002e 0023 movs r3, #0 + 188 0030 FB73 strb r3, [r7, #15] + 93:Core/Src/can.c **** uint16_t highest_temp = 0; + 189 .loc 1 93 14 + 190 0032 0023 movs r3, #0 + 191 0034 BB81 strh r3, [r7, #12] @ movhi + 94:Core/Src/can.c **** sm_check_battery_temperature(&id_highest_temp, &highest_temp); + 192 .loc 1 94 5 + 193 0036 07F10C02 add r2, r7, #12 + 194 003a 07F10F03 add r3, r7, #15 + 195 003e 1146 mov r1, r2 + 196 0040 1846 mov r0, r3 + 197 0042 FFF7FEFF bl sm_check_battery_temperature + 95:Core/Src/can.c **** + 96:Core/Src/can.c **** data[0] = (state.current_state); // 8 bit state (only 3 are use) + 198 .loc 1 96 21 + 199 0046 404B ldr r3, .L8+4 + 200 0048 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 201 .loc 1 96 13 + ARM GAS /tmp/ccrYTcjJ.s page 6 + + + 202 004a 3B74 strb r3, [r7, #16] + 97:Core/Src/can.c **** data[1] = (current_powerground_status); // 8 bit powerground + 203 .loc 1 97 13 + 204 004c 3F4B ldr r3, .L8+8 + 205 004e 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 206 0050 7B74 strb r3, [r7, #17] + 98:Core/Src/can.c **** data[2] = (state.error_source); // 8 bit error + 207 .loc 1 98 21 + 208 0052 3D4B ldr r3, .L8+4 + 209 0054 5B88 ldrh r3, [r3, #2] + 210 .loc 1 98 13 + 211 0056 DBB2 uxtb r3, r3 + 212 0058 BB74 strb r3, [r7, #18] + 99:Core/Src/can.c **** data[3] = ((int) current_soc); // 8 bit state of charge + 213 .loc 1 99 16 + 214 005a 3D4B ldr r3, .L8+12 + 215 005c D3ED007A vldr.32 s15, [r3] + 216 0060 FDEEE77A vcvt.s32.f32 s15, s15 + 217 0064 C7ED017A vstr.32 s15, [r7, #4] @ int + 218 .loc 1 99 13 + 219 0068 3B79 ldrb r3, [r7, #4] @ zero_extendqisi2 + 220 006a FB74 strb r3, [r7, #19] + 100:Core/Src/can.c **** data[4] = (roundf(RELAY_BAT_SIDE_VOLTAGE / 1000.0)); // 8 bit battery voltage + 221 .loc 1 100 46 + 222 006c 394B ldr r3, .L8+16 + 223 006e 1B68 ldr r3, [r3] + 224 0070 1846 mov r0, r3 + 225 0072 FFF7FEFF bl __aeabi_i2d + 226 0076 4FF00002 mov r2, #0 + 227 007a 374B ldr r3, .L8+20 + 228 007c FFF7FEFF bl __aeabi_ddiv + 229 0080 0246 mov r2, r0 + 230 0082 0B46 mov r3, r1 + 231 .loc 1 100 16 + 232 0084 1046 mov r0, r2 + 233 0086 1946 mov r1, r3 + 234 0088 FFF7FEFF bl __aeabi_d2f + 235 008c 0346 mov r3, r0 @ float + 236 008e 00EE103A vmov s0, r3 + 237 0092 FFF7FEFF bl roundf + 238 0096 F0EE407A vmov.f32 s15, s0 + 239 .loc 1 100 13 discriminator 1 + 240 009a FCEEE77A vcvt.u32.f32 s15, s15 + 241 009e C7ED017A vstr.32 s15, [r7, #4] @ int + 242 00a2 3B79 ldrb r3, [r7, #4] + 243 00a4 DBB2 uxtb r3, r3 + 244 00a6 3B75 strb r3, [r7, #20] + 101:Core/Src/can.c **** data[5] = (roundf(RELAY_ESC_SIDE_VOLTAGE / 1000.0)); // 8 bit Inverter voltage + 245 .loc 1 101 46 + 246 00a8 2C4B ldr r3, .L8+24 + 247 00aa 1B68 ldr r3, [r3] + 248 00ac 1846 mov r0, r3 + 249 00ae FFF7FEFF bl __aeabi_i2d + 250 00b2 4FF00002 mov r2, #0 + 251 00b6 284B ldr r3, .L8+20 + 252 00b8 FFF7FEFF bl __aeabi_ddiv + 253 00bc 0246 mov r2, r0 + ARM GAS /tmp/ccrYTcjJ.s page 7 + + + 254 00be 0B46 mov r3, r1 + 255 .loc 1 101 16 + 256 00c0 1046 mov r0, r2 + 257 00c2 1946 mov r1, r3 + 258 00c4 FFF7FEFF bl __aeabi_d2f + 259 00c8 0346 mov r3, r0 @ float + 260 00ca 00EE103A vmov s0, r3 + 261 00ce FFF7FEFF bl roundf + 262 00d2 F0EE407A vmov.f32 s15, s0 + 263 .loc 1 101 13 discriminator 1 + 264 00d6 FCEEE77A vcvt.u32.f32 s15, s15 + 265 00da C7ED017A vstr.32 s15, [r7, #4] @ int + 266 00de 3B79 ldrb r3, [r7, #4] + 267 00e0 DBB2 uxtb r3, r3 + 268 00e2 7B75 strb r3, [r7, #21] + 102:Core/Src/can.c **** data[6] = (roundf(CURRENT_MEASUREMENT / 1000.0)); // 8 bit Current + 269 .loc 1 102 43 + 270 00e4 1E4B ldr r3, .L8+28 + 271 00e6 1B68 ldr r3, [r3] + 272 00e8 1846 mov r0, r3 + 273 00ea FFF7FEFF bl __aeabi_i2d + 274 00ee 4FF00002 mov r2, #0 + 275 00f2 194B ldr r3, .L8+20 + 276 00f4 FFF7FEFF bl __aeabi_ddiv + 277 00f8 0246 mov r2, r0 + 278 00fa 0B46 mov r3, r1 + 279 .loc 1 102 16 + 280 00fc 1046 mov r0, r2 + 281 00fe 1946 mov r1, r3 + 282 0100 FFF7FEFF bl __aeabi_d2f + 283 0104 0346 mov r3, r0 @ float + 284 0106 00EE103A vmov s0, r3 + 285 010a FFF7FEFF bl roundf + 286 010e F0EE407A vmov.f32 s15, s0 + 287 .loc 1 102 13 discriminator 1 + 288 0112 FCEEE77A vcvt.u32.f32 s15, s15 + 289 0116 C7ED017A vstr.32 s15, [r7, #4] @ int + 290 011a 3B79 ldrb r3, [r7, #4] + 291 011c DBB2 uxtb r3, r3 + 292 011e BB75 strb r3, [r7, #22] + 103:Core/Src/can.c **** data[7] = ((highest_temp) >> 4); // 8 bit highest cell temperature + 293 .loc 1 103 13 + 294 0120 BB89 ldrh r3, [r7, #12] + 295 0122 1B09 lsrs r3, r3, #4 + 296 0124 9BB2 uxth r3, r3 + 297 0126 DBB2 uxtb r3, r3 + 298 0128 FB75 strb r3, [r7, #23] + 104:Core/Src/can.c **** //data[7] = state.error_source; + 105:Core/Src/can.c **** ftcan_transmit(CAN_ID_OUT, data, sizeof(data)); + 299 .loc 1 105 5 + 300 012a 07F11003 add r3, r7, #16 + 301 012e 0822 movs r2, #8 + 302 0130 1946 mov r1, r3 + 303 0132 40F20250 movw r0, #1282 + 304 0136 FFF7FEFF bl ftcan_transmit + 305 013a 00E0 b .L4 + 306 .L7: + ARM GAS /tmp/ccrYTcjJ.s page 8 + + + 307 .LBE2: + 87:Core/Src/can.c **** else { + 308 .loc 1 87 5 + 309 013c 00BF nop + 310 .L4: + 106:Core/Src/can.c **** } + 107:Core/Src/can.c **** } + 311 .loc 1 107 1 + 312 013e 1837 adds r7, r7, #24 + 313 .cfi_def_cfa_offset 8 + 314 0140 BD46 mov sp, r7 + 315 .cfi_def_cfa_register 13 + 316 @ sp needed + 317 0142 80BD pop {r7, pc} + 318 .L9: + 319 .align 2 + 320 .L8: + 321 0144 00000000 .word can_status_timer + 322 0148 00000000 .word state + 323 014c 00000000 .word current_powerground_status + 324 0150 00000000 .word current_soc + 325 0154 00000000 .word RELAY_BAT_SIDE_VOLTAGE + 326 0158 00408F40 .word 1083129856 + 327 015c 00000000 .word RELAY_ESC_SIDE_VOLTAGE + 328 0160 00000000 .word CURRENT_MEASUREMENT + 329 .cfi_endproc + 330 .LFE131: + 332 .section .text.can_handle_send_log,"ax",%progbits + 333 .align 1 + 334 .global can_handle_send_log + 335 .syntax unified + 336 .thumb + 337 .thumb_func + 339 can_handle_send_log: + 340 .LFB132: + 108:Core/Src/can.c **** + 109:Core/Src/can.c **** void can_handle_send_log(){ + 341 .loc 1 109 27 + 342 .cfi_startproc + 343 @ args = 0, pretend = 0, frame = 8 + 344 @ frame_needed = 1, uses_anonymous_args = 0 + 345 0000 80B5 push {r7, lr} + 346 .cfi_def_cfa_offset 8 + 347 .cfi_offset 7, -8 + 348 .cfi_offset 14, -4 + 349 0002 82B0 sub sp, sp, #8 + 350 .cfi_def_cfa_offset 16 + 351 0004 00AF add r7, sp, #0 + 352 .cfi_def_cfa_register 7 + 110:Core/Src/can.c **** if (can_log_timer > HAL_GetTick()) + 353 .loc 1 110 23 + 354 0006 FFF7FEFF bl HAL_GetTick + 355 000a 0246 mov r2, r0 + 356 .loc 1 110 21 discriminator 1 + 357 000c 214B ldr r3, .L15 + 358 000e 1B68 ldr r3, [r3] + 359 .loc 1 110 6 discriminator 1 + ARM GAS /tmp/ccrYTcjJ.s page 9 + + + 360 0010 9A42 cmp r2, r3 + 361 0012 3BD3 bcc .L14 + 362 .LBB3: + 111:Core/Src/can.c **** return; + 112:Core/Src/can.c **** else { + 113:Core/Src/can.c **** uint8_t data[4] = {}; + 363 .loc 1 113 13 + 364 0014 0023 movs r3, #0 + 365 0016 7B60 str r3, [r7, #4] + 114:Core/Src/can.c **** can_log_timer = HAL_GetTick() + CAN_LOGGING_FREQ; + 366 .loc 1 114 21 + 367 0018 FFF7FEFF bl HAL_GetTick + 368 001c 0346 mov r3, r0 + 369 .loc 1 114 35 discriminator 1 + 370 001e C833 adds r3, r3, #200 + 371 .loc 1 114 19 discriminator 1 + 372 0020 1C4A ldr r2, .L15 + 373 0022 1360 str r3, [r2] + 115:Core/Src/can.c **** data[0] = id_to_log; + 374 .loc 1 115 13 + 375 0024 1C4B ldr r3, .L15+4 + 376 0026 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 377 0028 3B71 strb r3, [r7, #4] + 116:Core/Src/can.c **** data[1] = module.cellVoltages[id_to_log] >> 8; + 378 .loc 1 116 34 + 379 002a 1B4B ldr r3, .L15+4 + 380 002c 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 381 002e 1A46 mov r2, r3 + 382 0030 1A4B ldr r3, .L15+8 + 383 0032 33F91230 ldrsh r3, [r3, r2, lsl #1] + 384 .loc 1 116 13 + 385 0036 1B12 asrs r3, r3, #8 + 386 0038 1BB2 sxth r3, r3 + 387 003a DBB2 uxtb r3, r3 + 388 003c 7B71 strb r3, [r7, #5] + 117:Core/Src/can.c **** data[2] = module.cellVoltages[id_to_log]; + 389 .loc 1 117 34 + 390 003e 164B ldr r3, .L15+4 + 391 0040 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 392 0042 1A46 mov r2, r3 + 393 0044 154B ldr r3, .L15+8 + 394 0046 33F91230 ldrsh r3, [r3, r2, lsl #1] + 395 .loc 1 117 13 + 396 004a DBB2 uxtb r3, r3 + 397 004c BB71 strb r3, [r7, #6] + 118:Core/Src/can.c **** data[3] = tmp1075_temps[id_to_log] >> 4; + 398 .loc 1 118 28 + 399 004e 124B ldr r3, .L15+4 + 400 0050 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 401 0052 1A46 mov r2, r3 + 402 0054 124B ldr r3, .L15+12 + 403 0056 33F91230 ldrsh r3, [r3, r2, lsl #1] + 404 .loc 1 118 13 + 405 005a 1B11 asrs r3, r3, #4 + 406 005c 1BB2 sxth r3, r3 + 407 005e DBB2 uxtb r3, r3 + 408 0060 FB71 strb r3, [r7, #7] + ARM GAS /tmp/ccrYTcjJ.s page 10 + + + 119:Core/Src/can.c **** ftcan_transmit(CAN_ID_LOG, data, 4); + 409 .loc 1 119 5 + 410 0062 3B1D adds r3, r7, #4 + 411 0064 0422 movs r2, #4 + 412 0066 1946 mov r1, r3 + 413 0068 40F20350 movw r0, #1283 + 414 006c FFF7FEFF bl ftcan_transmit + 120:Core/Src/can.c **** id_to_log++; + 415 .loc 1 120 14 + 416 0070 094B ldr r3, .L15+4 + 417 0072 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 418 0074 0133 adds r3, r3, #1 + 419 0076 DAB2 uxtb r2, r3 + 420 0078 074B ldr r3, .L15+4 + 421 007a 1A70 strb r2, [r3] + 121:Core/Src/can.c **** if (id_to_log == 13) + 422 .loc 1 121 19 + 423 007c 064B ldr r3, .L15+4 + 424 007e 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 425 .loc 1 121 8 + 426 0080 0D2B cmp r3, #13 + 427 0082 04D1 bne .L10 + 122:Core/Src/can.c **** id_to_log = 0; + 428 .loc 1 122 17 + 429 0084 044B ldr r3, .L15+4 + 430 0086 0022 movs r2, #0 + 431 0088 1A70 strb r2, [r3] + 432 008a 00E0 b .L10 + 433 .L14: + 434 .LBE3: + 111:Core/Src/can.c **** else { + 435 .loc 1 111 5 + 436 008c 00BF nop + 437 .L10: + 123:Core/Src/can.c **** } + 124:Core/Src/can.c **** /* + 125:Core/Src/can.c **** 021E 30 + 126:Core/Src/can.c **** 0232 50 + 127:Core/Src/can.c **** 0238 60 + 128:Core/Src/can.c **** 0246 70 + 129:Core/Src/can.c **** 0250 80 + 130:Core/Src/can.c **** 025A 90 + 131:Core/Src/can.c **** 0264 100 + 132:Core/Src/can.c **** */ + 133:Core/Src/can.c **** } + 438 .loc 1 133 1 + 439 008e 0837 adds r7, r7, #8 + 440 .cfi_def_cfa_offset 8 + 441 0090 BD46 mov sp, r7 + 442 .cfi_def_cfa_register 13 + 443 @ sp needed + 444 0092 80BD pop {r7, pc} + 445 .L16: + 446 .align 2 + 447 .L15: + 448 0094 00000000 .word can_log_timer + 449 0098 00000000 .word id_to_log + ARM GAS /tmp/ccrYTcjJ.s page 11 + + + 450 009c 00000000 .word module + 451 00a0 00000000 .word tmp1075_temps + 452 .cfi_endproc + 453 .LFE132: + 455 .section .text.can_handle_recieve_command,"ax",%progbits + 456 .align 1 + 457 .global can_handle_recieve_command + 458 .syntax unified + 459 .thumb + 460 .thumb_func + 462 can_handle_recieve_command: + 463 .LFB133: + 134:Core/Src/can.c **** + 135:Core/Src/can.c **** /* + 136:Core/Src/can.c **** can_handle_recieve_command() should only check if the message is valid and then hand it + 137:Core/Src/can.c **** to the sm_handle_ams_in() which handles the state machine transition. + 138:Core/Src/can.c **** + 139:Core/Src/can.c **** This function recieves a command from the Autobox with the CAN ID of 0x501. + 140:Core/Src/can.c **** with format of: + 141:Core/Src/can.c **** data[0] = target state + 142:Core/Src/can.c **** 0x00 STATE_INACTIVE | disconnect power to the ESC of powerground. Send it to return the mvbms to + 143:Core/Src/can.c **** 0x01 STATE_READY | connect power to the ESC of powerground and but with no PWM signal. + 144:Core/Src/can.c **** 0x02 STATE_ACTIVE | activate powerground at (data[1]) percent. + 145:Core/Src/can.c **** + 146:Core/Src/can.c **** allowed transitions: + 147:Core/Src/can.c **** STATE_INACTIVE -> STATE_READY + 148:Core/Src/can.c **** STATE_READY -> STATE_INACTIVE, STATE_ACTIVE + 149:Core/Src/can.c **** STATE_ACTIVE -> STATE_INACTIVE, STATE_READY + 150:Core/Src/can.c **** */ + 151:Core/Src/can.c **** void can_handle_recieve_command(const uint8_t *data){ + 464 .loc 1 151 53 + 465 .cfi_startproc + 466 @ args = 0, pretend = 0, frame = 8 + 467 @ frame_needed = 1, uses_anonymous_args = 0 + 468 0000 80B5 push {r7, lr} + 469 .cfi_def_cfa_offset 8 + 470 .cfi_offset 7, -8 + 471 .cfi_offset 14, -4 + 472 0002 82B0 sub sp, sp, #8 + 473 .cfi_def_cfa_offset 16 + 474 0004 00AF add r7, sp, #0 + 475 .cfi_def_cfa_register 7 + 476 0006 7860 str r0, [r7, #4] + 152:Core/Src/can.c **** if (data[0] == 0x00){ + 477 .loc 1 152 11 + 478 0008 7B68 ldr r3, [r7, #4] + 479 000a 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 480 .loc 1 152 6 + 481 000c 002B cmp r3, #0 + 482 000e 03D1 bne .L18 + 153:Core/Src/can.c **** sm_handle_ams_in(data); + 483 .loc 1 153 5 + 484 0010 7868 ldr r0, [r7, #4] + 485 0012 FFF7FEFF bl sm_handle_ams_in + 154:Core/Src/can.c **** } else if (data[0] == 0x01 && data[1] == 0x00){ + 155:Core/Src/can.c **** sm_handle_ams_in(data); + 156:Core/Src/can.c **** } else if (data[0] == 0x02 && data[1] <= 100) { + ARM GAS /tmp/ccrYTcjJ.s page 12 + + + 157:Core/Src/can.c **** sm_handle_ams_in(data); + 158:Core/Src/can.c **** } else if (data[0] == 0xF0 && data[1] == 0x00) { + 159:Core/Src/can.c **** sm_handle_ams_in(data); + 160:Core/Src/can.c **** } else if (data[0] == 0xF1 && data[1] == 0x00) { + 161:Core/Src/can.c **** sm_handle_ams_in(data); + 162:Core/Src/can.c **** } else if (data[0] == 0xFF && data[1] == 0x00) { + 163:Core/Src/can.c **** sm_handle_ams_in(data); + 164:Core/Src/can.c **** } + 165:Core/Src/can.c **** } + 486 .loc 1 165 1 + 487 0016 40E0 b .L24 + 488 .L18: + 154:Core/Src/can.c **** } else if (data[0] == 0x01 && data[1] == 0x00){ + 489 .loc 1 154 18 + 490 0018 7B68 ldr r3, [r7, #4] + 491 001a 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 154:Core/Src/can.c **** } else if (data[0] == 0x01 && data[1] == 0x00){ + 492 .loc 1 154 13 + 493 001c 012B cmp r3, #1 + 494 001e 08D1 bne .L20 + 154:Core/Src/can.c **** } else if (data[0] == 0x01 && data[1] == 0x00){ + 495 .loc 1 154 37 discriminator 1 + 496 0020 7B68 ldr r3, [r7, #4] + 497 0022 0133 adds r3, r3, #1 + 498 0024 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 154:Core/Src/can.c **** } else if (data[0] == 0x01 && data[1] == 0x00){ + 499 .loc 1 154 30 discriminator 1 + 500 0026 002B cmp r3, #0 + 501 0028 03D1 bne .L20 + 155:Core/Src/can.c **** } else if (data[0] == 0x02 && data[1] <= 100) { + 502 .loc 1 155 5 + 503 002a 7868 ldr r0, [r7, #4] + 504 002c FFF7FEFF bl sm_handle_ams_in + 505 0030 33E0 b .L19 + 506 .L20: + 156:Core/Src/can.c **** sm_handle_ams_in(data); + 507 .loc 1 156 18 + 508 0032 7B68 ldr r3, [r7, #4] + 509 0034 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 156:Core/Src/can.c **** sm_handle_ams_in(data); + 510 .loc 1 156 13 + 511 0036 022B cmp r3, #2 + 512 0038 08D1 bne .L21 + 156:Core/Src/can.c **** sm_handle_ams_in(data); + 513 .loc 1 156 37 discriminator 1 + 514 003a 7B68 ldr r3, [r7, #4] + 515 003c 0133 adds r3, r3, #1 + 516 003e 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 156:Core/Src/can.c **** sm_handle_ams_in(data); + 517 .loc 1 156 30 discriminator 1 + 518 0040 642B cmp r3, #100 + 519 0042 03D8 bhi .L21 + 157:Core/Src/can.c **** } else if (data[0] == 0xF0 && data[1] == 0x00) { + 520 .loc 1 157 5 + 521 0044 7868 ldr r0, [r7, #4] + 522 0046 FFF7FEFF bl sm_handle_ams_in + 523 004a 26E0 b .L19 + ARM GAS /tmp/ccrYTcjJ.s page 13 + + + 524 .L21: + 158:Core/Src/can.c **** sm_handle_ams_in(data); + 525 .loc 1 158 18 + 526 004c 7B68 ldr r3, [r7, #4] + 527 004e 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 158:Core/Src/can.c **** sm_handle_ams_in(data); + 528 .loc 1 158 13 + 529 0050 F02B cmp r3, #240 + 530 0052 08D1 bne .L22 + 158:Core/Src/can.c **** sm_handle_ams_in(data); + 531 .loc 1 158 37 discriminator 1 + 532 0054 7B68 ldr r3, [r7, #4] + 533 0056 0133 adds r3, r3, #1 + 534 0058 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 158:Core/Src/can.c **** sm_handle_ams_in(data); + 535 .loc 1 158 30 discriminator 1 + 536 005a 002B cmp r3, #0 + 537 005c 03D1 bne .L22 + 159:Core/Src/can.c **** } else if (data[0] == 0xF1 && data[1] == 0x00) { + 538 .loc 1 159 5 + 539 005e 7868 ldr r0, [r7, #4] + 540 0060 FFF7FEFF bl sm_handle_ams_in + 541 0064 19E0 b .L19 + 542 .L22: + 160:Core/Src/can.c **** sm_handle_ams_in(data); + 543 .loc 1 160 18 + 544 0066 7B68 ldr r3, [r7, #4] + 545 0068 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 160:Core/Src/can.c **** sm_handle_ams_in(data); + 546 .loc 1 160 13 + 547 006a F12B cmp r3, #241 + 548 006c 08D1 bne .L23 + 160:Core/Src/can.c **** sm_handle_ams_in(data); + 549 .loc 1 160 37 discriminator 1 + 550 006e 7B68 ldr r3, [r7, #4] + 551 0070 0133 adds r3, r3, #1 + 552 0072 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 160:Core/Src/can.c **** sm_handle_ams_in(data); + 553 .loc 1 160 30 discriminator 1 + 554 0074 002B cmp r3, #0 + 555 0076 03D1 bne .L23 + 161:Core/Src/can.c **** } else if (data[0] == 0xFF && data[1] == 0x00) { + 556 .loc 1 161 5 + 557 0078 7868 ldr r0, [r7, #4] + 558 007a FFF7FEFF bl sm_handle_ams_in + 559 007e 0CE0 b .L19 + 560 .L23: + 162:Core/Src/can.c **** sm_handle_ams_in(data); + 561 .loc 1 162 18 + 562 0080 7B68 ldr r3, [r7, #4] + 563 0082 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 162:Core/Src/can.c **** sm_handle_ams_in(data); + 564 .loc 1 162 13 + 565 0084 FF2B cmp r3, #255 + 566 0086 08D1 bne .L24 + 162:Core/Src/can.c **** sm_handle_ams_in(data); + 567 .loc 1 162 37 discriminator 1 + ARM GAS /tmp/ccrYTcjJ.s page 14 + + + 568 0088 7B68 ldr r3, [r7, #4] + 569 008a 0133 adds r3, r3, #1 + 570 008c 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 162:Core/Src/can.c **** sm_handle_ams_in(data); + 571 .loc 1 162 30 discriminator 1 + 572 008e 002B cmp r3, #0 + 573 0090 03D1 bne .L24 + 163:Core/Src/can.c **** } + 574 .loc 1 163 5 + 575 0092 7868 ldr r0, [r7, #4] + 576 0094 FFF7FEFF bl sm_handle_ams_in + 577 .loc 1 165 1 + 578 0098 FFE7 b .L24 + 579 .L19: + 580 .L24: + 581 009a 00BF nop + 582 009c 0837 adds r7, r7, #8 + 583 .cfi_def_cfa_offset 8 + 584 009e BD46 mov sp, r7 + 585 .cfi_def_cfa_register 13 + 586 @ sp needed + 587 00a0 80BD pop {r7, pc} + 588 .cfi_endproc + 589 .LFE133: + 591 .section .text.can_handle_dump,"ax",%progbits + 592 .align 1 + 593 .global can_handle_dump + 594 .syntax unified + 595 .thumb + 596 .thumb_func + 598 can_handle_dump: + 599 .LFB134: + 166:Core/Src/can.c **** + 167:Core/Src/can.c **** void can_handle_dump() { + 600 .loc 1 167 24 + 601 .cfi_startproc + 602 @ args = 0, pretend = 0, frame = 16 + 603 @ frame_needed = 1, uses_anonymous_args = 0 + 604 0000 80B5 push {r7, lr} + 605 .cfi_def_cfa_offset 8 + 606 .cfi_offset 7, -8 + 607 .cfi_offset 14, -4 + 608 0002 84B0 sub sp, sp, #16 + 609 .cfi_def_cfa_offset 24 + 610 0004 00AF add r7, sp, #0 + 611 .cfi_def_cfa_register 7 + 168:Core/Src/can.c **** uint8_t* data = {}; + 612 .loc 1 168 12 + 613 0006 0023 movs r3, #0 + 614 0008 BB60 str r3, [r7, #8] + 169:Core/Src/can.c **** HAL_StatusTypeDef status = HAL_OK; + 615 .loc 1 169 21 + 616 000a 0023 movs r3, #0 + 617 000c FB71 strb r3, [r7, #7] + 170:Core/Src/can.c **** while (status == HAL_OK){ + 618 .loc 1 170 9 + 619 000e 22E0 b .L26 + ARM GAS /tmp/ccrYTcjJ.s page 15 + + + 620 .L29: + 171:Core/Src/can.c **** HAL_Delay(2); + 621 .loc 1 171 5 + 622 0010 0220 movs r0, #2 + 623 0012 FFF7FEFF bl HAL_Delay + 172:Core/Src/can.c **** eeprom_read(data, 62); + 624 .loc 1 172 5 + 625 0016 3E21 movs r1, #62 + 626 0018 B868 ldr r0, [r7, #8] + 627 001a FFF7FEFF bl eeprom_read + 628 .LBB4: + 173:Core/Src/can.c **** for (int i = 0; i < (EEPROM_MEMORY_SIZE-8)/8; i += 8) { + 629 .loc 1 173 14 + 630 001e 0023 movs r3, #0 + 631 0020 FB60 str r3, [r7, #12] + 632 .loc 1 173 5 + 633 0022 0BE0 b .L27 + 634 .L28: + 174:Core/Src/can.c **** ftcan_transmit(CAN_ID_OUT, &data[i], 8); + 635 .loc 1 174 7 + 636 0024 FB68 ldr r3, [r7, #12] + 637 .loc 1 174 34 + 638 0026 BA68 ldr r2, [r7, #8] + 639 0028 1344 add r3, r3, r2 + 640 .loc 1 174 7 + 641 002a 0822 movs r2, #8 + 642 002c 1946 mov r1, r3 + 643 002e 40F20250 movw r0, #1282 + 644 0032 FFF7FEFF bl ftcan_transmit + 173:Core/Src/can.c **** for (int i = 0; i < (EEPROM_MEMORY_SIZE-8)/8; i += 8) { + 645 .loc 1 173 53 discriminator 3 + 646 0036 FB68 ldr r3, [r7, #12] + 647 0038 0833 adds r3, r3, #8 + 648 003a FB60 str r3, [r7, #12] + 649 .L27: + 173:Core/Src/can.c **** for (int i = 0; i < (EEPROM_MEMORY_SIZE-8)/8; i += 8) { + 650 .loc 1 173 23 discriminator 1 + 651 003c FB68 ldr r3, [r7, #12] + 652 003e 43F6FE72 movw r2, #16382 + 653 0042 9342 cmp r3, r2 + 654 0044 EEDD ble .L28 + 655 .LBE4: + 175:Core/Src/can.c **** } + 176:Core/Src/can.c **** ftcan_transmit(CAN_ID_OUT, &data[56], 6); + 656 .loc 1 176 32 + 657 0046 BB68 ldr r3, [r7, #8] + 658 0048 3833 adds r3, r3, #56 + 659 .loc 1 176 5 + 660 004a 0622 movs r2, #6 + 661 004c 1946 mov r1, r3 + 662 004e 40F20250 movw r0, #1282 + 663 0052 FFF7FEFF bl ftcan_transmit + 664 .L26: + 170:Core/Src/can.c **** HAL_Delay(2); + 665 .loc 1 170 17 + 666 0056 FB79 ldrb r3, [r7, #7] @ zero_extendqisi2 + 667 0058 002B cmp r3, #0 + ARM GAS /tmp/ccrYTcjJ.s page 16 + + + 668 005a D9D0 beq .L29 + 177:Core/Src/can.c **** } + 178:Core/Src/can.c **** read_address = 0; + 669 .loc 1 178 16 + 670 005c 034B ldr r3, .L30 + 671 005e 0022 movs r2, #0 + 672 0060 1A60 str r2, [r3] + 179:Core/Src/can.c **** } + 673 .loc 1 179 1 + 674 0062 00BF nop + 675 0064 1037 adds r7, r7, #16 + 676 .cfi_def_cfa_offset 8 + 677 0066 BD46 mov sp, r7 + 678 .cfi_def_cfa_register 13 + 679 @ sp needed + 680 0068 80BD pop {r7, pc} + 681 .L31: + 682 006a 00BF .align 2 + 683 .L30: + 684 006c 00000000 .word read_address + 685 .cfi_endproc + 686 .LFE134: + 688 .section .text.ftcan_msg_received_cb,"ax",%progbits + 689 .align 1 + 690 .global ftcan_msg_received_cb + 691 .syntax unified + 692 .thumb + 693 .thumb_func + 695 ftcan_msg_received_cb: + 696 .LFB135: + 180:Core/Src/can.c **** + 181:Core/Src/can.c **** /* + 182:Core/Src/can.c **** implements the _weak method ftcan_msg_recieved_cb() which throws an interrupt when a CAN message is + 183:Core/Src/can.c **** it only checks if the id is and datalen is correct thans hands data over to can_handle_recieve_comm + 184:Core/Src/can.c **** + 185:Core/Src/can.c **** in MXCUBE under CAN NVIC settings "USB low priority or CAN_RX0 interrupts" has to be on + 186:Core/Src/can.c **** */ + 187:Core/Src/can.c **** void ftcan_msg_received_cb(uint16_t id, size_t datalen, const uint8_t *data){ + 697 .loc 1 187 77 + 698 .cfi_startproc + 699 @ args = 0, pretend = 0, frame = 16 + 700 @ frame_needed = 1, uses_anonymous_args = 0 + 701 0000 80B5 push {r7, lr} + 702 .cfi_def_cfa_offset 8 + 703 .cfi_offset 7, -8 + 704 .cfi_offset 14, -4 + 705 0002 84B0 sub sp, sp, #16 + 706 .cfi_def_cfa_offset 24 + 707 0004 00AF add r7, sp, #0 + 708 .cfi_def_cfa_register 7 + 709 0006 0346 mov r3, r0 + 710 0008 B960 str r1, [r7, #8] + 711 000a 7A60 str r2, [r7, #4] + 712 000c FB81 strh r3, [r7, #14] @ movhi + 188:Core/Src/can.c **** if (programming_mode == 1){ + 713 .loc 1 188 24 + 714 000e 1F4B ldr r3, .L37 + ARM GAS /tmp/ccrYTcjJ.s page 17 + + + 715 0010 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 716 .loc 1 188 6 + 717 0012 002B cmp r3, #0 + 718 0014 03D0 beq .L33 + 189:Core/Src/can.c **** can_handle_recieve_command(data); + 719 .loc 1 189 5 + 720 0016 7868 ldr r0, [r7, #4] + 721 0018 FFF7FEFF bl can_handle_recieve_command + 190:Core/Src/can.c **** return; + 722 .loc 1 190 5 + 723 001c 32E0 b .L32 + 724 .L33: + 191:Core/Src/can.c **** } + 192:Core/Src/can.c **** + 193:Core/Src/can.c **** if (id == 0x501 && datalen == 2){ + 725 .loc 1 193 6 + 726 001e FB89 ldrh r3, [r7, #14] + 727 0020 40F20152 movw r2, #1281 + 728 0024 9342 cmp r3, r2 + 729 0026 2DD1 bne .L32 + 730 .loc 1 193 19 discriminator 1 + 731 0028 BB68 ldr r3, [r7, #8] + 732 002a 022B cmp r3, #2 + 733 002c 2AD1 bne .L32 + 194:Core/Src/can.c **** can_timeout_timer = HAL_GetTick() + CAN_TIMEOUT; + 734 .loc 1 194 25 + 735 002e FFF7FEFF bl HAL_GetTick + 736 0032 0346 mov r3, r0 + 737 .loc 1 194 39 discriminator 1 + 738 0034 03F59C53 add r3, r3, #4992 + 739 0038 0833 adds r3, r3, #8 + 740 .loc 1 194 23 discriminator 1 + 741 003a 154A ldr r2, .L37+4 + 742 003c 1360 str r3, [r2] + 195:Core/Src/can.c **** if (state.current_state == STATE_ERROR){ + 743 .loc 1 195 14 + 744 003e 154B ldr r3, .L37+8 + 745 0040 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 746 .loc 1 195 8 + 747 0042 072B cmp r3, #7 + 748 0044 05D1 bne .L35 + 196:Core/Src/can.c **** last_message[0] = 0; + 749 .loc 1 196 23 + 750 0046 144B ldr r3, .L37+12 + 751 0048 0022 movs r2, #0 + 752 004a 1A70 strb r2, [r3] + 197:Core/Src/can.c **** last_message[1] = 0; + 753 .loc 1 197 23 + 754 004c 124B ldr r3, .L37+12 + 755 004e 0022 movs r2, #0 + 756 0050 5A70 strb r2, [r3, #1] + 757 .L35: + 198:Core/Src/can.c **** } + 199:Core/Src/can.c **** if (last_message[0] != data[0] || last_message[1] != data[1]){ + 758 .loc 1 199 21 + 759 0052 114B ldr r3, .L37+12 + 760 0054 1A78 ldrb r2, [r3] @ zero_extendqisi2 + ARM GAS /tmp/ccrYTcjJ.s page 18 + + + 761 .loc 1 199 25 + 762 0056 7B68 ldr r3, [r7, #4] + 763 0058 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 764 .loc 1 199 8 + 765 005a 9A42 cmp r2, r3 + 766 005c 06D1 bne .L36 + 767 .loc 1 199 51 discriminator 1 + 768 005e 0E4B ldr r3, .L37+12 + 769 0060 5A78 ldrb r2, [r3, #1] @ zero_extendqisi2 + 770 .loc 1 199 62 discriminator 1 + 771 0062 7B68 ldr r3, [r7, #4] + 772 0064 0133 adds r3, r3, #1 + 773 .loc 1 199 55 discriminator 1 + 774 0066 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 775 .loc 1 199 36 discriminator 1 + 776 0068 9A42 cmp r2, r3 + 777 006a 0BD0 beq .L32 + 778 .L36: + 200:Core/Src/can.c **** last_message[0] = data[0]; + 779 .loc 1 200 29 + 780 006c 7B68 ldr r3, [r7, #4] + 781 006e 1A78 ldrb r2, [r3] @ zero_extendqisi2 + 782 .loc 1 200 23 + 783 0070 094B ldr r3, .L37+12 + 784 0072 1A70 strb r2, [r3] + 201:Core/Src/can.c **** last_message[1] = data[1]; + 785 .loc 1 201 29 + 786 0074 7B68 ldr r3, [r7, #4] + 787 0076 0133 adds r3, r3, #1 + 788 0078 1A78 ldrb r2, [r3] @ zero_extendqisi2 + 789 .loc 1 201 23 + 790 007a 074B ldr r3, .L37+12 + 791 007c 5A70 strb r2, [r3, #1] + 202:Core/Src/can.c **** can_handle_recieve_command(data); + 792 .loc 1 202 7 + 793 007e 7868 ldr r0, [r7, #4] + 794 0080 FFF7FEFF bl can_handle_recieve_command + 795 .L32: + 203:Core/Src/can.c **** } + 204:Core/Src/can.c **** } + 205:Core/Src/can.c **** } + 796 .loc 1 205 1 + 797 0084 1037 adds r7, r7, #16 + 798 .cfi_def_cfa_offset 8 + 799 0086 BD46 mov sp, r7 + 800 .cfi_def_cfa_register 13 + 801 @ sp needed + 802 0088 80BD pop {r7, pc} + 803 .L38: + 804 008a 00BF .align 2 + 805 .L37: + 806 008c 00000000 .word programming_mode + 807 0090 00000000 .word can_timeout_timer + 808 0094 00000000 .word state + 809 0098 00000000 .word last_message + 810 .cfi_endproc + 811 .LFE135: + ARM GAS /tmp/ccrYTcjJ.s page 19 + + + 813 .text + 814 .Letext0: + 815 .file 2 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 816 .file 3 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 817 .file 4 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + 818 .file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h" + 819 .file 6 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/lib/gcc/arm-none-e + 820 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h" + 821 .file 8 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h" + 822 .file 9 "Core/Inc/ADBMS_LL_Driver.h" + 823 .file 10 "Core/Inc/ADBMS_Abstraction.h" + 824 .file 11 "Core/Inc/AMS_HighLevel.h" + 825 .file 12 "Core/Inc/soc_estimation.h" + 826 .file 13 "Core/Inc/TMP1075.h" + 827 .file 14 "Core/Inc/eeprom.h" + 828 .file 15 "Core/Inc/PWM_control.h" + 829 .file 16 "Core/Inc/state_machine.h" + 830 .file 17 "Core/Inc/can.h" + 831 .file 18 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h" + 832 .file 19 "Core/Lib/can-halal/can-halal.h" + 833 .file 20 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/inc + ARM GAS /tmp/ccrYTcjJ.s page 20 + + +DEFINED SYMBOLS + *ABS*:00000000 can.c + /tmp/ccrYTcjJ.s:24 .bss.id_to_log:00000000 id_to_log + /tmp/ccrYTcjJ.s:25 .bss.id_to_log:00000000 $d + /tmp/ccrYTcjJ.s:31 .bss.last_message:00000000 last_message + /tmp/ccrYTcjJ.s:28 .bss.last_message:00000000 $d + /tmp/ccrYTcjJ.s:38 .bss.can_status_timer:00000000 can_status_timer + /tmp/ccrYTcjJ.s:35 .bss.can_status_timer:00000000 $d + /tmp/ccrYTcjJ.s:45 .bss.can_log_timer:00000000 can_log_timer + /tmp/ccrYTcjJ.s:42 .bss.can_log_timer:00000000 $d + /tmp/ccrYTcjJ.s:52 .bss.can_timeout_timer:00000000 can_timeout_timer + /tmp/ccrYTcjJ.s:49 .bss.can_timeout_timer:00000000 $d + /tmp/ccrYTcjJ.s:55 .text.can_init:00000000 $t + /tmp/ccrYTcjJ.s:61 .text.can_init:00000000 can_init + /tmp/ccrYTcjJ.s:131 .text.can_init:00000060 $d + /tmp/ccrYTcjJ.s:143 .text.can_handle_send_status:00000000 $t + /tmp/ccrYTcjJ.s:149 .text.can_handle_send_status:00000000 can_handle_send_status + /tmp/ccrYTcjJ.s:321 .text.can_handle_send_status:00000144 $d + /tmp/ccrYTcjJ.s:333 .text.can_handle_send_log:00000000 $t + /tmp/ccrYTcjJ.s:339 .text.can_handle_send_log:00000000 can_handle_send_log + /tmp/ccrYTcjJ.s:448 .text.can_handle_send_log:00000094 $d + /tmp/ccrYTcjJ.s:456 .text.can_handle_recieve_command:00000000 $t + /tmp/ccrYTcjJ.s:462 .text.can_handle_recieve_command:00000000 can_handle_recieve_command + /tmp/ccrYTcjJ.s:592 .text.can_handle_dump:00000000 $t + /tmp/ccrYTcjJ.s:598 .text.can_handle_dump:00000000 can_handle_dump + /tmp/ccrYTcjJ.s:684 .text.can_handle_dump:0000006c $d + /tmp/ccrYTcjJ.s:689 .text.ftcan_msg_received_cb:00000000 $t + /tmp/ccrYTcjJ.s:695 .text.ftcan_msg_received_cb:00000000 ftcan_msg_received_cb + /tmp/ccrYTcjJ.s:806 .text.ftcan_msg_received_cb:0000008c $d + +UNDEFINED SYMBOLS +ftcan_init +ftcan_add_filter +HAL_GetTick +__aeabi_i2d +__aeabi_ddiv +__aeabi_d2f +sm_check_battery_temperature +roundf +ftcan_transmit +state +current_powerground_status +current_soc +RELAY_BAT_SIDE_VOLTAGE +RELAY_ESC_SIDE_VOLTAGE +CURRENT_MEASUREMENT +module +tmp1075_temps +sm_handle_ams_in +HAL_Delay +eeprom_read +read_address +programming_mode diff --git a/Software/build/can.o b/Software/build/can.o new file mode 100644 index 0000000..4e62e5e Binary files /dev/null and b/Software/build/can.o differ diff --git a/Software/build/eeprom.d b/Software/build/eeprom.d new file mode 100644 index 0000000..17a0366 --- /dev/null +++ b/Software/build/eeprom.d @@ -0,0 +1,86 @@ +build/eeprom.o: Core/Src/eeprom.c Core/Inc/eeprom.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + Core/Inc/stm32f3xx_hal_conf.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h \ + Core/Inc/ADBMS_LL_Driver.h Core/Inc/main.h Core/Inc/soc_estimation.h \ + Core/Inc/state_machine.h Core/Inc/AMS_HighLevel.h \ + Core/Inc/ADBMS_Abstraction.h Core/Inc/ADBMS_CMD_MAKROS.h \ + Core/Lib/can-halal/can-halal.h Core/Inc/errors.h Core/Inc/can.h \ + Core/Inc/errors.h Core/Inc/PWM_control.h Core/Inc/status_LED.h \ + Core/Inc/state_machine.h Core/Inc/TMP1075.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h Core/Inc/TMP1075.h +Core/Inc/eeprom.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h: +Core/Inc/ADBMS_LL_Driver.h: +Core/Inc/main.h: +Core/Inc/soc_estimation.h: +Core/Inc/state_machine.h: +Core/Inc/AMS_HighLevel.h: +Core/Inc/ADBMS_Abstraction.h: +Core/Inc/ADBMS_CMD_MAKROS.h: +Core/Lib/can-halal/can-halal.h: +Core/Inc/errors.h: +Core/Inc/can.h: +Core/Inc/errors.h: +Core/Inc/PWM_control.h: +Core/Inc/status_LED.h: +Core/Inc/state_machine.h: +Core/Inc/TMP1075.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Core/Inc/TMP1075.h: diff --git a/Software/build/eeprom.lst b/Software/build/eeprom.lst new file mode 100644 index 0000000..958d7a0 --- /dev/null +++ b/Software/build/eeprom.lst @@ -0,0 +1,873 @@ +ARM GAS /tmp/ccvqyNaH.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 6 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "eeprom.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Core/Src/eeprom.c" + 20 .section .bss.hi2c,"aw",%nobits + 21 .align 2 + 24 hi2c: + 25 0000 00000000 .space 4 + 26 .global write_address + 27 .section .bss.write_address,"aw",%nobits + 28 .align 2 + 31 write_address: + 32 0000 00000000 .space 4 + 33 .global read_address + 34 .section .bss.read_address,"aw",%nobits + 35 .align 2 + 38 read_address: + 39 0000 00000000 .space 4 + 40 .section .text.eeprom_init,"ax",%progbits + 41 .align 1 + 42 .global eeprom_init + 43 .syntax unified + 44 .thumb + 45 .thumb_func + 47 eeprom_init: + 48 .LFB130: + 1:Core/Src/eeprom.c **** /* + 2:Core/Src/eeprom.c **** * PWM_control.h + 3:Core/Src/eeprom.c **** * + 4:Core/Src/eeprom.c **** * Created on: 10.07.2024 + 5:Core/Src/eeprom.c **** * Author: Hamza + 6:Core/Src/eeprom.c **** */ + 7:Core/Src/eeprom.c **** + 8:Core/Src/eeprom.c **** #include + 9:Core/Src/eeprom.c **** + 10:Core/Src/eeprom.c **** // TODO: test this + 11:Core/Src/eeprom.c **** static I2C_HandleTypeDef* hi2c; + 12:Core/Src/eeprom.c **** uint32_t write_address, read_address; + 13:Core/Src/eeprom.c **** + 14:Core/Src/eeprom.c **** void eeprom_init(I2C_HandleTypeDef* handle) { + 49 .loc 1 14 45 + 50 .cfi_startproc + ARM GAS /tmp/ccvqyNaH.s page 2 + + + 51 @ args = 0, pretend = 0, frame = 8 + 52 @ frame_needed = 1, uses_anonymous_args = 0 + 53 @ link register save eliminated. + 54 0000 80B4 push {r7} + 55 .cfi_def_cfa_offset 4 + 56 .cfi_offset 7, -4 + 57 0002 83B0 sub sp, sp, #12 + 58 .cfi_def_cfa_offset 16 + 59 0004 00AF add r7, sp, #0 + 60 .cfi_def_cfa_register 7 + 61 0006 7860 str r0, [r7, #4] + 15:Core/Src/eeprom.c **** hi2c = handle; + 62 .loc 1 15 8 + 63 0008 074A ldr r2, .L2 + 64 000a 7B68 ldr r3, [r7, #4] + 65 000c 1360 str r3, [r2] + 16:Core/Src/eeprom.c **** write_address = 0; + 66 .loc 1 16 17 + 67 000e 074B ldr r3, .L2+4 + 68 0010 0022 movs r2, #0 + 69 0012 1A60 str r2, [r3] + 17:Core/Src/eeprom.c **** read_address = 0; + 70 .loc 1 17 16 + 71 0014 064B ldr r3, .L2+8 + 72 0016 0022 movs r2, #0 + 73 0018 1A60 str r2, [r3] + 18:Core/Src/eeprom.c **** } + 74 .loc 1 18 1 + 75 001a 00BF nop + 76 001c 0C37 adds r7, r7, #12 + 77 .cfi_def_cfa_offset 4 + 78 001e BD46 mov sp, r7 + 79 .cfi_def_cfa_register 13 + 80 @ sp needed + 81 0020 5DF8047B ldr r7, [sp], #4 + 82 .cfi_restore 7 + 83 .cfi_def_cfa_offset 0 + 84 0024 7047 bx lr + 85 .L3: + 86 0026 00BF .align 2 + 87 .L2: + 88 0028 00000000 .word hi2c + 89 002c 00000000 .word write_address + 90 0030 00000000 .word read_address + 91 .cfi_endproc + 92 .LFE130: + 94 .section .text.eeprom_write_status,"ax",%progbits + 95 .align 1 + 96 .global eeprom_write_status + 97 .syntax unified + 98 .thumb + 99 .thumb_func + 101 eeprom_write_status: + 102 .LFB131: + 19:Core/Src/eeprom.c **** + 20:Core/Src/eeprom.c **** void eeprom_write_status(){ + 103 .loc 1 20 27 + ARM GAS /tmp/ccvqyNaH.s page 3 + + + 104 .cfi_startproc + 105 @ args = 0, pretend = 0, frame = 32 + 106 @ frame_needed = 1, uses_anonymous_args = 0 + 107 0000 2DE9F041 push {r4, r5, r6, r7, r8, lr} + 108 .cfi_def_cfa_offset 24 + 109 .cfi_offset 4, -24 + 110 .cfi_offset 5, -20 + 111 .cfi_offset 6, -16 + 112 .cfi_offset 7, -12 + 113 .cfi_offset 8, -8 + 114 .cfi_offset 14, -4 + 115 0004 88B0 sub sp, sp, #32 + 116 .cfi_def_cfa_offset 56 + 117 0006 00AF add r7, sp, #0 + 118 .cfi_def_cfa_register 7 + 119 .loc 1 20 27 + 120 0008 6B46 mov r3, sp + 121 000a 9846 mov r8, r3 + 21:Core/Src/eeprom.c **** uint8_t data_length = 62; + 122 .loc 1 21 11 + 123 000c 3E23 movs r3, #62 + 124 000e FB75 strb r3, [r7, #23] + 22:Core/Src/eeprom.c **** uint8_t data[data_length] = {}; + 125 .loc 1 22 3 + 126 0010 FE7D ldrb r6, [r7, #23] @ zero_extendqisi2 + 127 .loc 1 22 11 + 128 0012 3346 mov r3, r6 + 129 0014 013B subs r3, r3, #1 + 130 0016 3B61 str r3, [r7, #16] + 131 0018 F3B2 uxtb r3, r6 + 132 001a 0022 movs r2, #0 + 133 001c 1C46 mov r4, r3 + 134 001e 1546 mov r5, r2 + 135 0020 4FF00002 mov r2, #0 + 136 0024 4FF00003 mov r3, #0 + 137 0028 EB00 lsls r3, r5, #3 + 138 002a 43EA5473 orr r3, r3, r4, lsr #29 + 139 002e E200 lsls r2, r4, #3 + 140 0030 3446 mov r4, r6 + 141 0032 F3B2 uxtb r3, r6 + 142 0034 0022 movs r2, #0 + 143 0036 1846 mov r0, r3 + 144 0038 1146 mov r1, r2 + 145 003a 4FF00002 mov r2, #0 + 146 003e 4FF00003 mov r3, #0 + 147 0042 CB00 lsls r3, r1, #3 + 148 0044 43EA5073 orr r3, r3, r0, lsr #29 + 149 0048 C200 lsls r2, r0, #3 + 150 004a 3346 mov r3, r6 + 151 004c 0733 adds r3, r3, #7 + 152 004e DB08 lsrs r3, r3, #3 + 153 0050 DB00 lsls r3, r3, #3 + 154 0052 ADEB030D sub sp, sp, r3 + 155 0056 6B46 mov r3, sp + 156 0058 0033 adds r3, r3, #0 + 157 005a FB60 str r3, [r7, #12] + 158 .loc 1 22 11 is_stmt 0 discriminator 1 + ARM GAS /tmp/ccvqyNaH.s page 4 + + + 159 005c FB68 ldr r3, [r7, #12] + 160 005e 2246 mov r2, r4 + 161 0060 0021 movs r1, #0 + 162 0062 1846 mov r0, r3 + 163 0064 FFF7FEFF bl memset + 23:Core/Src/eeprom.c **** + 24:Core/Src/eeprom.c **** // data 0-9 + 25:Core/Src/eeprom.c **** data[0] = ((state.current_state << 4) | (current_powerground_status >> 4)); + 164 .loc 1 25 20 is_stmt 1 + 165 0068 534B ldr r3, .L9 + 166 006a 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 167 .loc 1 25 41 + 168 006c 5BB2 sxtb r3, r3 + 169 006e 1B01 lsls r3, r3, #4 + 170 0070 5AB2 sxtb r2, r3 + 171 0072 524B ldr r3, .L9+4 + 172 0074 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 173 0076 1B09 lsrs r3, r3, #4 + 174 0078 DBB2 uxtb r3, r3 + 175 007a 5BB2 sxtb r3, r3 + 176 007c 1343 orrs r3, r3, r2 + 177 007e 5BB2 sxtb r3, r3 + 178 0080 DAB2 uxtb r2, r3 + 179 .loc 1 25 11 + 180 0082 FB68 ldr r3, [r7, #12] + 181 0084 1A70 strb r2, [r3] + 26:Core/Src/eeprom.c **** data[1] = ((current_powerground_status << 4) | (state.error_source >> 4)); // 4 bit powerg + 182 .loc 1 26 48 + 183 0086 4D4B ldr r3, .L9+4 + 184 0088 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 185 008a 5BB2 sxtb r3, r3 + 186 008c 1B01 lsls r3, r3, #4 + 187 008e 5AB2 sxtb r2, r3 + 188 .loc 1 26 56 + 189 0090 494B ldr r3, .L9 + 190 0092 5B88 ldrh r3, [r3, #2] + 191 .loc 1 26 48 + 192 0094 1B09 lsrs r3, r3, #4 + 193 0096 9BB2 uxth r3, r3 + 194 0098 5BB2 sxtb r3, r3 + 195 009a 1343 orrs r3, r3, r2 + 196 009c 5BB2 sxtb r3, r3 + 197 009e DAB2 uxtb r2, r3 + 198 .loc 1 26 11 + 199 00a0 FB68 ldr r3, [r7, #12] + 200 00a2 5A70 strb r2, [r3, #1] + 27:Core/Src/eeprom.c **** data[2] = ((state.error_source << 4) | (0)); // 4 bit error + 201 .loc 1 27 20 + 202 00a4 444B ldr r3, .L9 + 203 00a6 5B88 ldrh r3, [r3, #2] + 204 .loc 1 27 40 + 205 00a8 DBB2 uxtb r3, r3 + 206 00aa 1B01 lsls r3, r3, #4 + 207 00ac DAB2 uxtb r2, r3 + 208 .loc 1 27 11 + 209 00ae FB68 ldr r3, [r7, #12] + 210 00b0 9A70 strb r2, [r3, #2] + ARM GAS /tmp/ccvqyNaH.s page 5 + + + 28:Core/Src/eeprom.c **** data[3] = ((int) current_soc); // 8 bit state + 211 .loc 1 28 14 + 212 00b2 434B ldr r3, .L9+8 + 213 00b4 D3ED007A vldr.32 s15, [r3] + 214 00b8 FDEEE77A vcvt.s32.f32 s15, s15 + 215 00bc C7ED017A vstr.32 s15, [r7, #4] @ int + 216 .loc 1 28 11 + 217 00c0 3A79 ldrb r2, [r7, #4] @ zero_extendqisi2 + 218 00c2 FB68 ldr r3, [r7, #12] + 219 00c4 DA70 strb r2, [r3, #3] + 29:Core/Src/eeprom.c **** data[4] = (RELAY_BAT_SIDE_VOLTAGE >> 8); // 16 bit batte + 220 .loc 1 29 37 + 221 00c6 3F4B ldr r3, .L9+12 + 222 00c8 1B68 ldr r3, [r3] + 223 00ca 1B12 asrs r3, r3, #8 + 224 .loc 1 29 11 + 225 00cc DAB2 uxtb r2, r3 + 226 00ce FB68 ldr r3, [r7, #12] + 227 00d0 1A71 strb r2, [r3, #4] + 30:Core/Src/eeprom.c **** data[5] = (RELAY_BAT_SIDE_VOLTAGE); + 228 .loc 1 30 11 + 229 00d2 3C4B ldr r3, .L9+12 + 230 00d4 1B68 ldr r3, [r3] + 231 00d6 DAB2 uxtb r2, r3 + 232 00d8 FB68 ldr r3, [r7, #12] + 233 00da 5A71 strb r2, [r3, #5] + 31:Core/Src/eeprom.c **** data[6] = (RELAY_ESC_SIDE_VOLTAGE >> 8); // 16 bit Inver + 234 .loc 1 31 37 + 235 00dc 3A4B ldr r3, .L9+16 + 236 00de 1B68 ldr r3, [r3] + 237 00e0 1B12 asrs r3, r3, #8 + 238 .loc 1 31 11 + 239 00e2 DAB2 uxtb r2, r3 + 240 00e4 FB68 ldr r3, [r7, #12] + 241 00e6 9A71 strb r2, [r3, #6] + 32:Core/Src/eeprom.c **** data[7] = (RELAY_ESC_SIDE_VOLTAGE); + 242 .loc 1 32 11 + 243 00e8 374B ldr r3, .L9+16 + 244 00ea 1B68 ldr r3, [r3] + 245 00ec DAB2 uxtb r2, r3 + 246 00ee FB68 ldr r3, [r7, #12] + 247 00f0 DA71 strb r2, [r3, #7] + 33:Core/Src/eeprom.c **** data[8] = (CURRENT_MEASUREMENT >> 8); // 16 bit Inver + 248 .loc 1 33 34 + 249 00f2 364B ldr r3, .L9+20 + 250 00f4 1B68 ldr r3, [r3] + 251 00f6 1B12 asrs r3, r3, #8 + 252 .loc 1 33 11 + 253 00f8 DAB2 uxtb r2, r3 + 254 00fa FB68 ldr r3, [r7, #12] + 255 00fc 1A72 strb r2, [r3, #8] + 34:Core/Src/eeprom.c **** data[9] = (CURRENT_MEASUREMENT); + 256 .loc 1 34 11 + 257 00fe 334B ldr r3, .L9+20 + 258 0100 1B68 ldr r3, [r3] + 259 0102 DAB2 uxtb r2, r3 + 260 0104 FB68 ldr r3, [r7, #12] + ARM GAS /tmp/ccvqyNaH.s page 6 + + + 261 0106 5A72 strb r2, [r3, #9] + 262 .LBB2: + 35:Core/Src/eeprom.c **** + 36:Core/Src/eeprom.c **** // data 10-35 + 37:Core/Src/eeprom.c **** for (int i = 0; i < 13; i++) { + 263 .loc 1 37 12 + 264 0108 0023 movs r3, #0 + 265 010a FB61 str r3, [r7, #28] + 266 .loc 1 37 3 + 267 010c 24E0 b .L5 + 268 .L6: + 38:Core/Src/eeprom.c **** data[(i*2)] = ((int) module.auxVoltages[i]) >> 8; + 269 .loc 1 38 45 + 270 010e 304A ldr r2, .L9+24 + 271 0110 FB69 ldr r3, [r7, #28] + 272 0112 0833 adds r3, r3, #8 + 273 0114 9B00 lsls r3, r3, #2 + 274 0116 1344 add r3, r3, r2 + 275 0118 D3ED007A vldr.32 s15, [r3] + 276 .loc 1 38 21 + 277 011c FDEEE77A vcvt.s32.f32 s15, s15 + 278 0120 17EE903A vmov r3, s15 @ int + 279 .loc 1 38 50 + 280 0124 1A12 asrs r2, r3, #8 + 281 .loc 1 38 12 + 282 0126 FB69 ldr r3, [r7, #28] + 283 0128 5B00 lsls r3, r3, #1 + 284 .loc 1 38 18 + 285 012a D1B2 uxtb r1, r2 + 286 012c FA68 ldr r2, [r7, #12] + 287 012e D154 strb r1, [r2, r3] + 39:Core/Src/eeprom.c **** data[(i*2)+1] = ((int) module.auxVoltages[i]); + 288 .loc 1 39 47 + 289 0130 274A ldr r2, .L9+24 + 290 0132 FB69 ldr r3, [r7, #28] + 291 0134 0833 adds r3, r3, #8 + 292 0136 9B00 lsls r3, r3, #2 + 293 0138 1344 add r3, r3, r2 + 294 013a D3ED007A vldr.32 s15, [r3] + 295 .loc 1 39 23 + 296 013e FDEEE77A vcvt.s32.f32 s15, s15 + 297 0142 C7ED017A vstr.32 s15, [r7, #4] @ int + 298 .loc 1 39 12 + 299 0146 FB69 ldr r3, [r7, #28] + 300 0148 5B00 lsls r3, r3, #1 + 301 .loc 1 39 15 + 302 014a 0133 adds r3, r3, #1 + 303 .loc 1 39 20 + 304 014c 3979 ldrb r1, [r7, #4] @ zero_extendqisi2 + 305 014e FA68 ldr r2, [r7, #12] + 306 0150 D154 strb r1, [r2, r3] + 37:Core/Src/eeprom.c **** data[(i*2)] = ((int) module.auxVoltages[i]) >> 8; + 307 .loc 1 37 28 discriminator 3 + 308 0152 FB69 ldr r3, [r7, #28] + 309 0154 0133 adds r3, r3, #1 + 310 0156 FB61 str r3, [r7, #28] + 311 .L5: + ARM GAS /tmp/ccvqyNaH.s page 7 + + + 37:Core/Src/eeprom.c **** data[(i*2)] = ((int) module.auxVoltages[i]) >> 8; + 312 .loc 1 37 21 discriminator 1 + 313 0158 FB69 ldr r3, [r7, #28] + 314 015a 0C2B cmp r3, #12 + 315 015c D7DD ble .L6 + 316 .LBE2: + 317 .LBB3: + 40:Core/Src/eeprom.c **** } + 41:Core/Src/eeprom.c **** + 42:Core/Src/eeprom.c **** // data 36-61 + 43:Core/Src/eeprom.c **** for (int i = 0; i < 13; i++) { + 318 .loc 1 43 12 + 319 015e 0023 movs r3, #0 + 320 0160 BB61 str r3, [r7, #24] + 321 .loc 1 43 3 + 322 0162 17E0 b .L7 + 323 .L8: + 44:Core/Src/eeprom.c **** data[(i*2)] = (tmp1075_temps[i]) >> 8; + 324 .loc 1 44 33 + 325 0164 1B4A ldr r2, .L9+28 + 326 0166 BB69 ldr r3, [r7, #24] + 327 0168 32F91330 ldrsh r3, [r2, r3, lsl #1] + 328 .loc 1 44 17 + 329 016c 1B12 asrs r3, r3, #8 + 330 016e 1AB2 sxth r2, r3 + 331 .loc 1 44 12 + 332 0170 BB69 ldr r3, [r7, #24] + 333 0172 5B00 lsls r3, r3, #1 + 334 .loc 1 44 17 + 335 0174 D1B2 uxtb r1, r2 + 336 0176 FA68 ldr r2, [r7, #12] + 337 0178 D154 strb r1, [r2, r3] + 45:Core/Src/eeprom.c **** data[(i*2)+1] = (tmp1075_temps[i]); + 338 .loc 1 45 35 + 339 017a 164A ldr r2, .L9+28 + 340 017c BB69 ldr r3, [r7, #24] + 341 017e 32F91320 ldrsh r2, [r2, r3, lsl #1] + 342 .loc 1 45 12 + 343 0182 BB69 ldr r3, [r7, #24] + 344 0184 5B00 lsls r3, r3, #1 + 345 .loc 1 45 15 + 346 0186 0133 adds r3, r3, #1 + 347 .loc 1 45 19 + 348 0188 D1B2 uxtb r1, r2 + 349 018a FA68 ldr r2, [r7, #12] + 350 018c D154 strb r1, [r2, r3] + 43:Core/Src/eeprom.c **** data[(i*2)] = (tmp1075_temps[i]) >> 8; + 351 .loc 1 43 28 discriminator 3 + 352 018e BB69 ldr r3, [r7, #24] + 353 0190 0133 adds r3, r3, #1 + 354 0192 BB61 str r3, [r7, #24] + 355 .L7: + 43:Core/Src/eeprom.c **** data[(i*2)] = (tmp1075_temps[i]) >> 8; + 356 .loc 1 43 21 discriminator 1 + 357 0194 BB69 ldr r3, [r7, #24] + 358 0196 0C2B cmp r3, #12 + 359 0198 E4DD ble .L8 + ARM GAS /tmp/ccvqyNaH.s page 8 + + + 360 .LBE3: + 46:Core/Src/eeprom.c **** } + 47:Core/Src/eeprom.c **** eeprom_write(data, 62); + 361 .loc 1 47 3 + 362 019a 3E21 movs r1, #62 + 363 019c F868 ldr r0, [r7, #12] + 364 019e FFF7FEFF bl eeprom_write + 48:Core/Src/eeprom.c **** write_address++; + 365 .loc 1 48 16 + 366 01a2 0D4B ldr r3, .L9+32 + 367 01a4 1B68 ldr r3, [r3] + 368 01a6 0133 adds r3, r3, #1 + 369 01a8 0B4A ldr r2, .L9+32 + 370 01aa 1360 str r3, [r2] + 371 01ac C546 mov sp, r8 + 49:Core/Src/eeprom.c **** } + 372 .loc 1 49 1 + 373 01ae 00BF nop + 374 01b0 2037 adds r7, r7, #32 + 375 .cfi_def_cfa_offset 24 + 376 01b2 BD46 mov sp, r7 + 377 .cfi_def_cfa_register 13 + 378 @ sp needed + 379 01b4 BDE8F081 pop {r4, r5, r6, r7, r8, pc} + 380 .L10: + 381 .align 2 + 382 .L9: + 383 01b8 00000000 .word state + 384 01bc 00000000 .word current_powerground_status + 385 01c0 00000000 .word current_soc + 386 01c4 00000000 .word RELAY_BAT_SIDE_VOLTAGE + 387 01c8 00000000 .word RELAY_ESC_SIDE_VOLTAGE + 388 01cc 00000000 .word CURRENT_MEASUREMENT + 389 01d0 00000000 .word module + 390 01d4 00000000 .word tmp1075_temps + 391 01d8 00000000 .word write_address + 392 .cfi_endproc + 393 .LFE131: + 395 .section .text.eeprom_read,"ax",%progbits + 396 .align 1 + 397 .global eeprom_read + 398 .syntax unified + 399 .thumb + 400 .thumb_func + 402 eeprom_read: + 403 .LFB132: + 50:Core/Src/eeprom.c **** + 51:Core/Src/eeprom.c **** HAL_StatusTypeDef eeprom_read(uint8_t* data, uint16_t data_length){ + 404 .loc 1 51 67 + 405 .cfi_startproc + 406 @ args = 0, pretend = 0, frame = 16 + 407 @ frame_needed = 1, uses_anonymous_args = 0 + 408 0000 80B5 push {r7, lr} + 409 .cfi_def_cfa_offset 8 + 410 .cfi_offset 7, -8 + 411 .cfi_offset 14, -4 + 412 0002 88B0 sub sp, sp, #32 + ARM GAS /tmp/ccvqyNaH.s page 9 + + + 413 .cfi_def_cfa_offset 40 + 414 0004 04AF add r7, sp, #16 + 415 .cfi_def_cfa 7, 24 + 416 0006 7860 str r0, [r7, #4] + 417 0008 0B46 mov r3, r1 + 418 000a 7B80 strh r3, [r7, #2] @ movhi + 52:Core/Src/eeprom.c **** HAL_StatusTypeDef status = HAL_OK; + 419 .loc 1 52 21 + 420 000c 0023 movs r3, #0 + 421 000e FB73 strb r3, [r7, #15] + 422 .LBB4: + 53:Core/Src/eeprom.c **** for (size_t i = 0; i < data_length; i++) { + 423 .loc 1 53 15 + 424 0010 0023 movs r3, #0 + 425 0012 BB60 str r3, [r7, #8] + 426 .loc 1 53 3 + 427 0014 46E0 b .L12 + 428 .L17: + 54:Core/Src/eeprom.c **** if (read_address > EEPROM_MEMORY_SIZE){ + 429 .loc 1 54 22 + 430 0016 284B ldr r3, .L18 + 431 0018 1B68 ldr r3, [r3] + 432 .loc 1 54 8 + 433 001a B3F5003F cmp r3, #131072 + 434 001e 04D9 bls .L13 + 55:Core/Src/eeprom.c **** read_address = 0; + 435 .loc 1 55 20 + 436 0020 254B ldr r3, .L18 + 437 0022 0022 movs r2, #0 + 438 0024 1A60 str r2, [r3] + 56:Core/Src/eeprom.c **** return HAL_BUSY; + 439 .loc 1 56 14 + 440 0026 0223 movs r3, #2 + 441 0028 41E0 b .L14 + 442 .L13: + 57:Core/Src/eeprom.c **** } else if (read_address <= 65535){ + 443 .loc 1 57 29 + 444 002a 234B ldr r3, .L18 + 445 002c 1B68 ldr r3, [r3] + 446 .loc 1 57 15 + 447 002e B3F5803F cmp r3, #65536 + 448 0032 14D2 bcs .L15 + 58:Core/Src/eeprom.c **** status = HAL_I2C_Mem_Read( + 449 .loc 1 58 16 + 450 0034 214B ldr r3, .L18+4 + 451 0036 1868 ldr r0, [r3] + 452 0038 1F4B ldr r3, .L18 + 453 003a 1B68 ldr r3, [r3] + 454 003c 99B2 uxth r1, r3 + 455 003e 7A68 ldr r2, [r7, #4] + 456 0040 BB68 ldr r3, [r7, #8] + 457 0042 1344 add r3, r3, r2 + 458 0044 0A22 movs r2, #10 + 459 0046 0292 str r2, [sp, #8] + 460 0048 0122 movs r2, #1 + 461 004a 0192 str r2, [sp, #4] + 462 004c 0093 str r3, [sp] + ARM GAS /tmp/ccvqyNaH.s page 10 + + + 463 004e 0223 movs r3, #2 + 464 0050 0A46 mov r2, r1 + 465 0052 A421 movs r1, #164 + 466 0054 FFF7FEFF bl HAL_I2C_Mem_Read + 467 0058 0346 mov r3, r0 + 468 005a FB73 strb r3, [r7, #15] + 469 005c 1AE0 b .L16 + 470 .L15: + 59:Core/Src/eeprom.c **** hi2c, EEPROM_I2C_ADDR, + 60:Core/Src/eeprom.c **** read_address, EERROM_MEMORY_ADDR_SIZE, + 61:Core/Src/eeprom.c **** &data[i], 1, 10); + 62:Core/Src/eeprom.c **** } else if (read_address > 65535) { + 471 .loc 1 62 29 + 472 005e 164B ldr r3, .L18 + 473 0060 1B68 ldr r3, [r3] + 474 .loc 1 62 15 + 475 0062 B3F5803F cmp r3, #65536 + 476 0066 15D3 bcc .L16 + 63:Core/Src/eeprom.c **** status = HAL_I2C_Mem_Read( + 477 .loc 1 63 18 + 478 0068 144B ldr r3, .L18+4 + 479 006a 1868 ldr r0, [r3] + 480 006c 124B ldr r3, .L18 + 481 006e 1B68 ldr r3, [r3] + 482 0070 9BB2 uxth r3, r3 + 483 0072 0133 adds r3, r3, #1 + 484 0074 99B2 uxth r1, r3 + 485 0076 7A68 ldr r2, [r7, #4] + 486 0078 BB68 ldr r3, [r7, #8] + 487 007a 1344 add r3, r3, r2 + 488 007c 0A22 movs r2, #10 + 489 007e 0292 str r2, [sp, #8] + 490 0080 0122 movs r2, #1 + 491 0082 0192 str r2, [sp, #4] + 492 0084 0093 str r3, [sp] + 493 0086 0223 movs r3, #2 + 494 0088 0A46 mov r2, r1 + 495 008a A621 movs r1, #166 + 496 008c FFF7FEFF bl HAL_I2C_Mem_Read + 497 0090 0346 mov r3, r0 + 498 0092 FB73 strb r3, [r7, #15] + 499 .L16: + 64:Core/Src/eeprom.c **** hi2c, EEPROM_I2C_ADDR + 2, + 65:Core/Src/eeprom.c **** read_address - 65535, EERROM_MEMORY_ADDR_SIZE, + 66:Core/Src/eeprom.c **** &data[i], 1, 10); + 67:Core/Src/eeprom.c **** } + 68:Core/Src/eeprom.c **** read_address++; + 500 .loc 1 68 17 + 501 0094 084B ldr r3, .L18 + 502 0096 1B68 ldr r3, [r3] + 503 0098 0133 adds r3, r3, #1 + 504 009a 074A ldr r2, .L18 + 505 009c 1360 str r3, [r2] + 53:Core/Src/eeprom.c **** if (read_address > EEPROM_MEMORY_SIZE){ + 506 .loc 1 53 40 discriminator 2 + 507 009e BB68 ldr r3, [r7, #8] + 508 00a0 0133 adds r3, r3, #1 + ARM GAS /tmp/ccvqyNaH.s page 11 + + + 509 00a2 BB60 str r3, [r7, #8] + 510 .L12: + 53:Core/Src/eeprom.c **** if (read_address > EEPROM_MEMORY_SIZE){ + 511 .loc 1 53 24 discriminator 1 + 512 00a4 7B88 ldrh r3, [r7, #2] + 513 00a6 BA68 ldr r2, [r7, #8] + 514 00a8 9A42 cmp r2, r3 + 515 00aa B4D3 bcc .L17 + 516 .LBE4: + 69:Core/Src/eeprom.c **** } + 70:Core/Src/eeprom.c **** return status; + 517 .loc 1 70 10 + 518 00ac FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 519 .L14: + 71:Core/Src/eeprom.c **** } + 520 .loc 1 71 1 + 521 00ae 1846 mov r0, r3 + 522 00b0 1037 adds r7, r7, #16 + 523 .cfi_def_cfa_offset 8 + 524 00b2 BD46 mov sp, r7 + 525 .cfi_def_cfa_register 13 + 526 @ sp needed + 527 00b4 80BD pop {r7, pc} + 528 .L19: + 529 00b6 00BF .align 2 + 530 .L18: + 531 00b8 00000000 .word read_address + 532 00bc 00000000 .word hi2c + 533 .cfi_endproc + 534 .LFE132: + 536 .section .text.eeprom_write,"ax",%progbits + 537 .align 1 + 538 .global eeprom_write + 539 .syntax unified + 540 .thumb + 541 .thumb_func + 543 eeprom_write: + 544 .LFB133: + 72:Core/Src/eeprom.c **** + 73:Core/Src/eeprom.c **** HAL_StatusTypeDef eeprom_write(uint8_t* data, uint16_t data_length){ + 545 .loc 1 73 68 + 546 .cfi_startproc + 547 @ args = 0, pretend = 0, frame = 16 + 548 @ frame_needed = 1, uses_anonymous_args = 0 + 549 0000 80B5 push {r7, lr} + 550 .cfi_def_cfa_offset 8 + 551 .cfi_offset 7, -8 + 552 .cfi_offset 14, -4 + 553 0002 88B0 sub sp, sp, #32 + 554 .cfi_def_cfa_offset 40 + 555 0004 04AF add r7, sp, #16 + 556 .cfi_def_cfa 7, 24 + 557 0006 7860 str r0, [r7, #4] + 558 0008 0B46 mov r3, r1 + 559 000a 7B80 strh r3, [r7, #2] @ movhi + 74:Core/Src/eeprom.c **** HAL_StatusTypeDef status = HAL_OK; + 560 .loc 1 74 21 + ARM GAS /tmp/ccvqyNaH.s page 12 + + + 561 000c 0023 movs r3, #0 + 562 000e FB73 strb r3, [r7, #15] + 75:Core/Src/eeprom.c **** HAL_GPIO_WritePin(EEPROM___WC__GPIO_Port, EEPROM___WC__Pin, GPIO_PIN_RESET); + 563 .loc 1 75 3 + 564 0010 0022 movs r2, #0 + 565 0012 4FF48071 mov r1, #256 + 566 0016 4FF09040 mov r0, #1207959552 + 567 001a FFF7FEFF bl HAL_GPIO_WritePin + 568 .LBB5: + 76:Core/Src/eeprom.c **** for (size_t i = 0; i < data_length; i++) { + 569 .loc 1 76 15 + 570 001e 0023 movs r3, #0 + 571 0020 BB60 str r3, [r7, #8] + 572 .loc 1 76 3 + 573 0022 46E0 b .L21 + 574 .L26: + 77:Core/Src/eeprom.c **** if (write_address > EEPROM_MEMORY_SIZE){ + 575 .loc 1 77 23 + 576 0024 2B4B ldr r3, .L27 + 577 0026 1B68 ldr r3, [r3] + 578 .loc 1 77 8 + 579 0028 B3F5003F cmp r3, #131072 + 580 002c 04D9 bls .L22 + 78:Core/Src/eeprom.c **** write_address = 0; + 581 .loc 1 78 21 + 582 002e 294B ldr r3, .L27 + 583 0030 0022 movs r2, #0 + 584 0032 1A60 str r2, [r3] + 79:Core/Src/eeprom.c **** return HAL_BUSY; + 585 .loc 1 79 14 + 586 0034 0223 movs r3, #2 + 587 0036 48E0 b .L23 + 588 .L22: + 80:Core/Src/eeprom.c **** } else if (write_address <= 65535){ + 589 .loc 1 80 30 + 590 0038 264B ldr r3, .L27 + 591 003a 1B68 ldr r3, [r3] + 592 .loc 1 80 15 + 593 003c B3F5803F cmp r3, #65536 + 594 0040 14D2 bcs .L24 + 81:Core/Src/eeprom.c **** status = HAL_I2C_Mem_Write( + 595 .loc 1 81 16 + 596 0042 254B ldr r3, .L27+4 + 597 0044 1868 ldr r0, [r3] + 598 0046 234B ldr r3, .L27 + 599 0048 1B68 ldr r3, [r3] + 600 004a 99B2 uxth r1, r3 + 601 004c 7A68 ldr r2, [r7, #4] + 602 004e BB68 ldr r3, [r7, #8] + 603 0050 1344 add r3, r3, r2 + 604 0052 0A22 movs r2, #10 + 605 0054 0292 str r2, [sp, #8] + 606 0056 0122 movs r2, #1 + 607 0058 0192 str r2, [sp, #4] + 608 005a 0093 str r3, [sp] + 609 005c 0223 movs r3, #2 + 610 005e 0A46 mov r2, r1 + ARM GAS /tmp/ccvqyNaH.s page 13 + + + 611 0060 A421 movs r1, #164 + 612 0062 FFF7FEFF bl HAL_I2C_Mem_Write + 613 0066 0346 mov r3, r0 + 614 0068 FB73 strb r3, [r7, #15] + 615 006a 1AE0 b .L25 + 616 .L24: + 82:Core/Src/eeprom.c **** hi2c, EEPROM_I2C_ADDR, + 83:Core/Src/eeprom.c **** write_address, EERROM_MEMORY_ADDR_SIZE, + 84:Core/Src/eeprom.c **** &data[i], 1, 10); + 85:Core/Src/eeprom.c **** + 86:Core/Src/eeprom.c **** } else if (write_address > 65535) { + 617 .loc 1 86 30 + 618 006c 194B ldr r3, .L27 + 619 006e 1B68 ldr r3, [r3] + 620 .loc 1 86 15 + 621 0070 B3F5803F cmp r3, #65536 + 622 0074 15D3 bcc .L25 + 87:Core/Src/eeprom.c **** status = HAL_I2C_Mem_Write( + 623 .loc 1 87 18 + 624 0076 184B ldr r3, .L27+4 + 625 0078 1868 ldr r0, [r3] + 626 007a 164B ldr r3, .L27 + 627 007c 1B68 ldr r3, [r3] + 628 007e 9BB2 uxth r3, r3 + 629 0080 0133 adds r3, r3, #1 + 630 0082 99B2 uxth r1, r3 + 631 0084 7A68 ldr r2, [r7, #4] + 632 0086 BB68 ldr r3, [r7, #8] + 633 0088 1344 add r3, r3, r2 + 634 008a 0A22 movs r2, #10 + 635 008c 0292 str r2, [sp, #8] + 636 008e 0122 movs r2, #1 + 637 0090 0192 str r2, [sp, #4] + 638 0092 0093 str r3, [sp] + 639 0094 0223 movs r3, #2 + 640 0096 0A46 mov r2, r1 + 641 0098 A621 movs r1, #166 + 642 009a FFF7FEFF bl HAL_I2C_Mem_Write + 643 009e 0346 mov r3, r0 + 644 00a0 FB73 strb r3, [r7, #15] + 645 .L25: + 88:Core/Src/eeprom.c **** hi2c, EEPROM_I2C_ADDR + 2, + 89:Core/Src/eeprom.c **** write_address - 65535, EERROM_MEMORY_ADDR_SIZE, + 90:Core/Src/eeprom.c **** &data[i], 1, 10); + 91:Core/Src/eeprom.c **** } + 92:Core/Src/eeprom.c **** write_address++; + 646 .loc 1 92 18 + 647 00a2 0C4B ldr r3, .L27 + 648 00a4 1B68 ldr r3, [r3] + 649 00a6 0133 adds r3, r3, #1 + 650 00a8 0A4A ldr r2, .L27 + 651 00aa 1360 str r3, [r2] + 76:Core/Src/eeprom.c **** if (write_address > EEPROM_MEMORY_SIZE){ + 652 .loc 1 76 40 discriminator 2 + 653 00ac BB68 ldr r3, [r7, #8] + 654 00ae 0133 adds r3, r3, #1 + 655 00b0 BB60 str r3, [r7, #8] + ARM GAS /tmp/ccvqyNaH.s page 14 + + + 656 .L21: + 76:Core/Src/eeprom.c **** if (write_address > EEPROM_MEMORY_SIZE){ + 657 .loc 1 76 24 discriminator 1 + 658 00b2 7B88 ldrh r3, [r7, #2] + 659 00b4 BA68 ldr r2, [r7, #8] + 660 00b6 9A42 cmp r2, r3 + 661 00b8 B4D3 bcc .L26 + 662 .LBE5: + 93:Core/Src/eeprom.c **** } + 94:Core/Src/eeprom.c **** HAL_GPIO_WritePin(EEPROM___WC__GPIO_Port, EEPROM___WC__Pin, GPIO_PIN_SET); + 663 .loc 1 94 3 + 664 00ba 0122 movs r2, #1 + 665 00bc 4FF48071 mov r1, #256 + 666 00c0 4FF09040 mov r0, #1207959552 + 667 00c4 FFF7FEFF bl HAL_GPIO_WritePin + 95:Core/Src/eeprom.c **** return status; + 668 .loc 1 95 10 + 669 00c8 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 670 .L23: + 96:Core/Src/eeprom.c **** } + 671 .loc 1 96 1 + 672 00ca 1846 mov r0, r3 + 673 00cc 1037 adds r7, r7, #16 + 674 .cfi_def_cfa_offset 8 + 675 00ce BD46 mov sp, r7 + 676 .cfi_def_cfa_register 13 + 677 @ sp needed + 678 00d0 80BD pop {r7, pc} + 679 .L28: + 680 00d2 00BF .align 2 + 681 .L27: + 682 00d4 00000000 .word write_address + 683 00d8 00000000 .word hi2c + 684 .cfi_endproc + 685 .LFE133: + 687 .text + 688 .Letext0: + 689 .file 2 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 690 .file 3 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 691 .file 4 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + 692 .file 5 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/lib/gcc/arm-none-e + 693 .file 6 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h" + 694 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h" + 695 .file 8 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h" + 696 .file 9 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h" + 697 .file 10 "Core/Inc/ADBMS_LL_Driver.h" + 698 .file 11 "Core/Inc/ADBMS_Abstraction.h" + 699 .file 12 "Core/Inc/AMS_HighLevel.h" + 700 .file 13 "Core/Inc/PWM_control.h" + 701 .file 14 "Core/Inc/TMP1075.h" + 702 .file 15 "Core/Inc/state_machine.h" + 703 .file 16 "Core/Inc/soc_estimation.h" + 704 .file 17 "Core/Inc/eeprom.h" + ARM GAS /tmp/ccvqyNaH.s page 15 + + +DEFINED SYMBOLS + *ABS*:00000000 eeprom.c + /tmp/ccvqyNaH.s:21 .bss.hi2c:00000000 $d + /tmp/ccvqyNaH.s:24 .bss.hi2c:00000000 hi2c + /tmp/ccvqyNaH.s:31 .bss.write_address:00000000 write_address + /tmp/ccvqyNaH.s:28 .bss.write_address:00000000 $d + /tmp/ccvqyNaH.s:38 .bss.read_address:00000000 read_address + /tmp/ccvqyNaH.s:35 .bss.read_address:00000000 $d + /tmp/ccvqyNaH.s:41 .text.eeprom_init:00000000 $t + /tmp/ccvqyNaH.s:47 .text.eeprom_init:00000000 eeprom_init + /tmp/ccvqyNaH.s:88 .text.eeprom_init:00000028 $d + /tmp/ccvqyNaH.s:95 .text.eeprom_write_status:00000000 $t + /tmp/ccvqyNaH.s:101 .text.eeprom_write_status:00000000 eeprom_write_status + /tmp/ccvqyNaH.s:543 .text.eeprom_write:00000000 eeprom_write + /tmp/ccvqyNaH.s:383 .text.eeprom_write_status:000001b8 $d + /tmp/ccvqyNaH.s:396 .text.eeprom_read:00000000 $t + /tmp/ccvqyNaH.s:402 .text.eeprom_read:00000000 eeprom_read + /tmp/ccvqyNaH.s:531 .text.eeprom_read:000000b8 $d + /tmp/ccvqyNaH.s:537 .text.eeprom_write:00000000 $t + /tmp/ccvqyNaH.s:682 .text.eeprom_write:000000d4 $d + +UNDEFINED SYMBOLS +memset +state +current_powerground_status +current_soc +RELAY_BAT_SIDE_VOLTAGE +RELAY_ESC_SIDE_VOLTAGE +CURRENT_MEASUREMENT +module +tmp1075_temps +HAL_I2C_Mem_Read +HAL_GPIO_WritePin +HAL_I2C_Mem_Write diff --git a/Software/build/eeprom.o b/Software/build/eeprom.o new file mode 100644 index 0000000..16208f4 Binary files /dev/null and b/Software/build/eeprom.o differ diff --git a/Software/build/errors.d b/Software/build/errors.d new file mode 100644 index 0000000..e6f98a7 --- /dev/null +++ b/Software/build/errors.d @@ -0,0 +1,62 @@ +build/errors.o: Core/Src/errors.c Core/Inc/errors.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + Core/Inc/stm32f3xx_hal_conf.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h +Core/Inc/errors.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h: diff --git a/Software/build/errors.lst b/Software/build/errors.lst new file mode 100644 index 0000000..88ddcb2 --- /dev/null +++ b/Software/build/errors.lst @@ -0,0 +1,193 @@ +ARM GAS /tmp/ccQkv5NS.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 6 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "errors.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Core/Src/errors.c" + 20 .global error_data + 21 .section .bss.error_data,"aw",%nobits + 22 .align 2 + 25 error_data: + 26 0000 00000000 .space 12 + 26 00000000 + 26 00000000 + 27 .section .text.set_error_source,"ax",%progbits + 28 .align 1 + 29 .global set_error_source + 30 .syntax unified + 31 .thumb + 32 .thumb_func + 34 set_error_source: + 35 .LFB130: + 1:Core/Src/errors.c **** #include "errors.h" + 2:Core/Src/errors.c **** #include "stm32f3xx_hal.h" + 3:Core/Src/errors.c **** + 4:Core/Src/errors.c **** + 5:Core/Src/errors.c **** #warning move all errors here + 6:Core/Src/errors.c **** + 7:Core/Src/errors.c **** SlaveErrorData error_data; + 8:Core/Src/errors.c **** + 9:Core/Src/errors.c **** void set_error_source(SlaveErrorKind source) { + 36 .loc 1 9 46 + 37 .cfi_startproc + 38 @ args = 0, pretend = 0, frame = 8 + 39 @ frame_needed = 1, uses_anonymous_args = 0 + 40 0000 80B5 push {r7, lr} + 41 .cfi_def_cfa_offset 8 + 42 .cfi_offset 7, -8 + 43 .cfi_offset 14, -4 + 44 0002 82B0 sub sp, sp, #8 + 45 .cfi_def_cfa_offset 16 + 46 0004 00AF add r7, sp, #0 + 47 .cfi_def_cfa_register 7 + 48 0006 0346 mov r3, r0 + 49 0008 FB80 strh r3, [r7, #6] @ movhi + ARM GAS /tmp/ccQkv5NS.s page 2 + + + 10:Core/Src/errors.c **** if (!error_data.error_sources) { + 50 .loc 1 10 18 + 51 000a 0D4B ldr r3, .L3 + 52 000c 1B88 ldrh r3, [r3] + 53 .loc 1 10 6 + 54 000e 002B cmp r3, #0 + 55 0010 04D1 bne .L2 + 11:Core/Src/errors.c **** error_data.errors_since = HAL_GetTick(); + 56 .loc 1 11 31 + 57 0012 FFF7FEFF bl HAL_GetTick + 58 0016 0346 mov r3, r0 + 59 .loc 1 11 29 discriminator 1 + 60 0018 094A ldr r2, .L3 + 61 001a 9360 str r3, [r2, #8] + 62 .L2: + 12:Core/Src/errors.c **** } + 13:Core/Src/errors.c **** error_data.error_sources |= (1 << source); + 63 .loc 1 13 13 + 64 001c 084B ldr r3, .L3 + 65 001e 1B88 ldrh r3, [r3] + 66 0020 1AB2 sxth r2, r3 + 67 .loc 1 13 34 + 68 0022 FB88 ldrh r3, [r7, #6] + 69 0024 0121 movs r1, #1 + 70 0026 01FA03F3 lsl r3, r1, r3 + 71 .loc 1 13 28 + 72 002a 1BB2 sxth r3, r3 + 73 002c 1343 orrs r3, r3, r2 + 74 002e 1BB2 sxth r3, r3 + 75 0030 9AB2 uxth r2, r3 + 76 0032 034B ldr r3, .L3 + 77 0034 1A80 strh r2, [r3] @ movhi + 14:Core/Src/errors.c **** } + 78 .loc 1 14 1 + 79 0036 00BF nop + 80 0038 0837 adds r7, r7, #8 + 81 .cfi_def_cfa_offset 8 + 82 003a BD46 mov sp, r7 + 83 .cfi_def_cfa_register 13 + 84 @ sp needed + 85 003c 80BD pop {r7, pc} + 86 .L4: + 87 003e 00BF .align 2 + 88 .L3: + 89 0040 00000000 .word error_data + 90 .cfi_endproc + 91 .LFE130: + 93 .section .text.clear_error_source,"ax",%progbits + 94 .align 1 + 95 .global clear_error_source + 96 .syntax unified + 97 .thumb + 98 .thumb_func + 100 clear_error_source: + 101 .LFB131: + 15:Core/Src/errors.c **** + 16:Core/Src/errors.c **** void clear_error_source(SlaveErrorKind source) { error_data.error_sources &= ~(1 << source); } + ARM GAS /tmp/ccQkv5NS.s page 3 + + + 102 .loc 1 16 48 + 103 .cfi_startproc + 104 @ args = 0, pretend = 0, frame = 8 + 105 @ frame_needed = 1, uses_anonymous_args = 0 + 106 @ link register save eliminated. + 107 0000 80B4 push {r7} + 108 .cfi_def_cfa_offset 4 + 109 .cfi_offset 7, -4 + 110 0002 83B0 sub sp, sp, #12 + 111 .cfi_def_cfa_offset 16 + 112 0004 00AF add r7, sp, #0 + 113 .cfi_def_cfa_register 7 + 114 0006 0346 mov r3, r0 + 115 0008 FB80 strh r3, [r7, #6] @ movhi + 116 .loc 1 16 60 + 117 000a 0A4B ldr r3, .L6 + 118 000c 1B88 ldrh r3, [r3] + 119 000e 1AB2 sxth r2, r3 + 120 .loc 1 16 82 + 121 0010 FB88 ldrh r3, [r7, #6] + 122 0012 0121 movs r1, #1 + 123 0014 01FA03F3 lsl r3, r1, r3 + 124 .loc 1 16 75 + 125 0018 1BB2 sxth r3, r3 + 126 001a DB43 mvns r3, r3 + 127 001c 1BB2 sxth r3, r3 + 128 001e 1340 ands r3, r3, r2 + 129 0020 1BB2 sxth r3, r3 + 130 0022 9AB2 uxth r2, r3 + 131 0024 034B ldr r3, .L6 + 132 0026 1A80 strh r2, [r3] @ movhi + 133 .loc 1 16 94 + 134 0028 00BF nop + 135 002a 0C37 adds r7, r7, #12 + 136 .cfi_def_cfa_offset 4 + 137 002c BD46 mov sp, r7 + 138 .cfi_def_cfa_register 13 + 139 @ sp needed + 140 002e 5DF8047B ldr r7, [sp], #4 + 141 .cfi_restore 7 + 142 .cfi_def_cfa_offset 0 + 143 0032 7047 bx lr + 144 .L7: + 145 .align 2 + 146 .L6: + 147 0034 00000000 .word error_data + 148 .cfi_endproc + 149 .LFE131: + 151 .text + 152 .Letext0: + 153 .file 2 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 154 .file 3 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 155 .file 4 "Core/Inc/errors.h" + 156 .file 5 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h" + ARM GAS /tmp/ccQkv5NS.s page 4 + + +DEFINED SYMBOLS + *ABS*:00000000 errors.c + /tmp/ccQkv5NS.s:25 .bss.error_data:00000000 error_data + /tmp/ccQkv5NS.s:22 .bss.error_data:00000000 $d + /tmp/ccQkv5NS.s:28 .text.set_error_source:00000000 $t + /tmp/ccQkv5NS.s:34 .text.set_error_source:00000000 set_error_source + /tmp/ccQkv5NS.s:89 .text.set_error_source:00000040 $d + /tmp/ccQkv5NS.s:94 .text.clear_error_source:00000000 $t + /tmp/ccQkv5NS.s:100 .text.clear_error_source:00000000 clear_error_source + /tmp/ccQkv5NS.s:147 .text.clear_error_source:00000034 $d + +UNDEFINED SYMBOLS +HAL_GetTick diff --git a/Software/build/errors.o b/Software/build/errors.o new file mode 100644 index 0000000..620437f Binary files /dev/null and b/Software/build/errors.o differ diff --git a/Software/build/main.d b/Software/build/main.d new file mode 100644 index 0000000..d13ab86 --- /dev/null +++ b/Software/build/main.d @@ -0,0 +1,94 @@ +build/main.o: Core/Src/main.c Core/Inc/main.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + Core/Inc/stm32f3xx_hal_conf.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h \ + Core/Inc/ADBMS_Abstraction.h Core/Inc/ADBMS_CMD_MAKROS.h \ + Core/Inc/ADBMS_LL_Driver.h Core/Inc/main.h Core/Inc/ADBMS_CMD_MAKROS.h \ + Core/Inc/PWM_control.h Core/Inc/state_machine.h Core/Inc/AMS_HighLevel.h \ + Core/Inc/ADBMS_Abstraction.h Core/Lib/can-halal/can-halal.h \ + Core/Inc/errors.h Core/Inc/can.h Core/Inc/eeprom.h \ + Core/Inc/soc_estimation.h Core/Inc/state_machine.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h Core/Inc/TMP1075.h \ + Core/Inc/errors.h Core/Inc/status_LED.h Core/Inc/TMP1075.h \ + Core/Inc/soc_estimation.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h +Core/Inc/main.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h: +Core/Inc/ADBMS_Abstraction.h: +Core/Inc/ADBMS_CMD_MAKROS.h: +Core/Inc/ADBMS_LL_Driver.h: +Core/Inc/main.h: +Core/Inc/ADBMS_CMD_MAKROS.h: +Core/Inc/PWM_control.h: +Core/Inc/state_machine.h: +Core/Inc/AMS_HighLevel.h: +Core/Inc/ADBMS_Abstraction.h: +Core/Lib/can-halal/can-halal.h: +Core/Inc/errors.h: +Core/Inc/can.h: +Core/Inc/eeprom.h: +Core/Inc/soc_estimation.h: +Core/Inc/state_machine.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Core/Inc/TMP1075.h: +Core/Inc/errors.h: +Core/Inc/status_LED.h: +Core/Inc/TMP1075.h: +Core/Inc/soc_estimation.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: diff --git a/Software/build/main.lst b/Software/build/main.lst new file mode 100644 index 0000000..55df77a --- /dev/null +++ b/Software/build/main.lst @@ -0,0 +1,2622 @@ +ARM GAS /tmp/ccSWt3lr.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 6 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "main.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Core/Src/main.c" + 20 .global hcan + 21 .section .bss.hcan,"aw",%nobits + 22 .align 2 + 25 hcan: + 26 0000 00000000 .space 40 + 26 00000000 + 26 00000000 + 26 00000000 + 26 00000000 + 27 .global hi2c1 + 28 .section .bss.hi2c1,"aw",%nobits + 29 .align 2 + 32 hi2c1: + 33 0000 00000000 .space 84 + 33 00000000 + 33 00000000 + 33 00000000 + 33 00000000 + 34 .global hi2c2 + 35 .section .bss.hi2c2,"aw",%nobits + 36 .align 2 + 39 hi2c2: + 40 0000 00000000 .space 84 + 40 00000000 + 40 00000000 + 40 00000000 + 40 00000000 + 41 .global hspi1 + 42 .section .bss.hspi1,"aw",%nobits + 43 .align 2 + 46 hspi1: + 47 0000 00000000 .space 100 + 47 00000000 + 47 00000000 + 47 00000000 + 47 00000000 + 48 .global htim2 + 49 .section .bss.htim2,"aw",%nobits + ARM GAS /tmp/ccSWt3lr.s page 2 + + + 50 .align 2 + 53 htim2: + 54 0000 00000000 .space 76 + 54 00000000 + 54 00000000 + 54 00000000 + 54 00000000 + 55 .global htim3 + 56 .section .bss.htim3,"aw",%nobits + 57 .align 2 + 60 htim3: + 61 0000 00000000 .space 76 + 61 00000000 + 61 00000000 + 61 00000000 + 61 00000000 + 62 .global htim4 + 63 .section .bss.htim4,"aw",%nobits + 64 .align 2 + 67 htim4: + 68 0000 00000000 .space 76 + 68 00000000 + 68 00000000 + 68 00000000 + 68 00000000 + 69 .global htim15 + 70 .section .bss.htim15,"aw",%nobits + 71 .align 2 + 74 htim15: + 75 0000 00000000 .space 76 + 75 00000000 + 75 00000000 + 75 00000000 + 75 00000000 + 76 .section .text.main,"ax",%progbits + 77 .align 1 + 78 .global main + 79 .syntax unified + 80 .thumb + 81 .thumb_func + 83 main: + 84 .LFB130: + 1:Core/Src/main.c **** /* USER CODE BEGIN Header */ + 2:Core/Src/main.c **** /** + 3:Core/Src/main.c **** ****************************************************************************** + 4:Core/Src/main.c **** * @file : main.c + 5:Core/Src/main.c **** * @brief : Main program body + 6:Core/Src/main.c **** ****************************************************************************** + 7:Core/Src/main.c **** * @attention + 8:Core/Src/main.c **** * + 9:Core/Src/main.c **** * Copyright (c) 2024 STMicroelectronics. + 10:Core/Src/main.c **** * All rights reserved. + 11:Core/Src/main.c **** * + 12:Core/Src/main.c **** * This software is licensed under terms that can be found in the LICENSE file + 13:Core/Src/main.c **** * in the root directory of this software component. + 14:Core/Src/main.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 15:Core/Src/main.c **** * + ARM GAS /tmp/ccSWt3lr.s page 3 + + + 16:Core/Src/main.c **** ****************************************************************************** + 17:Core/Src/main.c **** */ + 18:Core/Src/main.c **** /* USER CODE END Header */ + 19:Core/Src/main.c **** /* Includes ------------------------------------------------------------------*/ + 20:Core/Src/main.c **** #include "main.h" + 21:Core/Src/main.c **** + 22:Core/Src/main.c **** /* Private includes ----------------------------------------------------------*/ + 23:Core/Src/main.c **** /* USER CODE BEGIN Includes */ + 24:Core/Src/main.c **** #include "ADBMS_Abstraction.h" + 25:Core/Src/main.c **** #include "ADBMS_CMD_MAKROS.h" + 26:Core/Src/main.c **** #include "PWM_control.h" + 27:Core/Src/main.c **** #include "can.h" + 28:Core/Src/main.c **** #include "AMS_HighLevel.h" + 29:Core/Src/main.c **** #include "soc_estimation.h" + 30:Core/Src/main.c **** #include "state_machine.h" + 31:Core/Src/main.c **** #include + 32:Core/Src/main.c **** #include + 33:Core/Src/main.c **** #include "TMP1075.h" + 34:Core/Src/main.c **** #include "errors.h" + 35:Core/Src/main.c **** #include "stm32f302xc.h" + 36:Core/Src/main.c **** #include "stm32f3xx_hal.h" + 37:Core/Src/main.c **** #include "stm32f3xx_hal_tim.h" + 38:Core/Src/main.c **** /* USER CODE END Includes */ + 39:Core/Src/main.c **** + 40:Core/Src/main.c **** /* Private typedef -----------------------------------------------------------*/ + 41:Core/Src/main.c **** /* USER CODE BEGIN PTD */ + 42:Core/Src/main.c **** + 43:Core/Src/main.c **** /* USER CODE END PTD */ + 44:Core/Src/main.c **** + 45:Core/Src/main.c **** /* Private define ------------------------------------------------------------*/ + 46:Core/Src/main.c **** /* USER CODE BEGIN PD */ + 47:Core/Src/main.c **** + 48:Core/Src/main.c **** /* USER CODE END PD */ + 49:Core/Src/main.c **** + 50:Core/Src/main.c **** /* Private macro -------------------------------------------------------------*/ + 51:Core/Src/main.c **** /* USER CODE BEGIN PM */ + 52:Core/Src/main.c **** + 53:Core/Src/main.c **** // htim2 CH3,4 BAT_COOLING_PWM,ENABLE + 54:Core/Src/main.c **** // htim3 CH3,4 ESC_L_PWM,R_PWM + 55:Core/Src/main.c **** // htim4 CH1,2,3 LED R,G,B + 56:Core/Src/main.c **** // htim15 CH1,2 ESC_COOLING_ENABLE,PWM + 57:Core/Src/main.c **** + 58:Core/Src/main.c **** /* USER CODE END PM */ + 59:Core/Src/main.c **** + 60:Core/Src/main.c **** /* Private variables ---------------------------------------------------------*/ + 61:Core/Src/main.c **** CAN_HandleTypeDef hcan; + 62:Core/Src/main.c **** + 63:Core/Src/main.c **** I2C_HandleTypeDef hi2c1; + 64:Core/Src/main.c **** I2C_HandleTypeDef hi2c2; + 65:Core/Src/main.c **** + 66:Core/Src/main.c **** SPI_HandleTypeDef hspi1; + 67:Core/Src/main.c **** + 68:Core/Src/main.c **** TIM_HandleTypeDef htim2; + 69:Core/Src/main.c **** TIM_HandleTypeDef htim3; + 70:Core/Src/main.c **** TIM_HandleTypeDef htim4; + 71:Core/Src/main.c **** TIM_HandleTypeDef htim15; + 72:Core/Src/main.c **** + ARM GAS /tmp/ccSWt3lr.s page 4 + + + 73:Core/Src/main.c **** /* USER CODE BEGIN PV */ + 74:Core/Src/main.c **** + 75:Core/Src/main.c **** /* USER CODE END PV */ + 76:Core/Src/main.c **** + 77:Core/Src/main.c **** /* Private function prototypes -----------------------------------------------*/ + 78:Core/Src/main.c **** void SystemClock_Config(void); + 79:Core/Src/main.c **** static void MX_GPIO_Init(void); + 80:Core/Src/main.c **** static void MX_CAN_Init(void); + 81:Core/Src/main.c **** static void MX_I2C1_Init(void); + 82:Core/Src/main.c **** static void MX_SPI1_Init(void); + 83:Core/Src/main.c **** static void MX_TIM15_Init(void); + 84:Core/Src/main.c **** static void MX_I2C2_Init(void); + 85:Core/Src/main.c **** static void MX_TIM2_Init(void); + 86:Core/Src/main.c **** static void MX_TIM3_Init(void); + 87:Core/Src/main.c **** static void MX_TIM4_Init(void); + 88:Core/Src/main.c **** /* USER CODE BEGIN PFP */ + 89:Core/Src/main.c **** + 90:Core/Src/main.c **** /* USER CODE END PFP */ + 91:Core/Src/main.c **** + 92:Core/Src/main.c **** /* Private user code ---------------------------------------------------------*/ + 93:Core/Src/main.c **** /* USER CODE BEGIN 0 */ + 94:Core/Src/main.c **** + 95:Core/Src/main.c **** /* USER CODE END 0 */ + 96:Core/Src/main.c **** + 97:Core/Src/main.c **** /** + 98:Core/Src/main.c **** * @brief The application entry point. + 99:Core/Src/main.c **** * @retval int + 100:Core/Src/main.c **** */ + 101:Core/Src/main.c **** int main(void) + 102:Core/Src/main.c **** { + 85 .loc 1 102 1 + 86 .cfi_startproc + 87 @ args = 0, pretend = 0, frame = 8 + 88 @ frame_needed = 1, uses_anonymous_args = 0 + 89 0000 80B5 push {r7, lr} + 90 .cfi_def_cfa_offset 8 + 91 .cfi_offset 7, -8 + 92 .cfi_offset 14, -4 + 93 0002 82B0 sub sp, sp, #8 + 94 .cfi_def_cfa_offset 16 + 95 0004 00AF add r7, sp, #0 + 96 .cfi_def_cfa_register 7 + 103:Core/Src/main.c **** + 104:Core/Src/main.c **** /* USER CODE BEGIN 1 */ + 105:Core/Src/main.c **** + 106:Core/Src/main.c **** /* USER CODE END 1 */ + 107:Core/Src/main.c **** + 108:Core/Src/main.c **** /* MCU Configuration--------------------------------------------------------*/ + 109:Core/Src/main.c **** + 110:Core/Src/main.c **** /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + 111:Core/Src/main.c **** HAL_Init(); + 97 .loc 1 111 3 + 98 0006 FFF7FEFF bl HAL_Init + 112:Core/Src/main.c **** + 113:Core/Src/main.c **** /* USER CODE BEGIN Init */ + 114:Core/Src/main.c **** + 115:Core/Src/main.c **** /* USER CODE END Init */ + ARM GAS /tmp/ccSWt3lr.s page 5 + + + 116:Core/Src/main.c **** + 117:Core/Src/main.c **** /* Configure the system clock */ + 118:Core/Src/main.c **** SystemClock_Config(); + 99 .loc 1 118 3 + 100 000a FFF7FEFF bl SystemClock_Config + 119:Core/Src/main.c **** + 120:Core/Src/main.c **** /* USER CODE BEGIN SysInit */ + 121:Core/Src/main.c **** + 122:Core/Src/main.c **** /* USER CODE END SysInit */ + 123:Core/Src/main.c **** + 124:Core/Src/main.c **** /* Initialize all configured peripherals */ + 125:Core/Src/main.c **** MX_GPIO_Init(); + 101 .loc 1 125 3 + 102 000e FFF7FEFF bl MX_GPIO_Init + 126:Core/Src/main.c **** MX_CAN_Init(); + 103 .loc 1 126 3 + 104 0012 FFF7FEFF bl MX_CAN_Init + 127:Core/Src/main.c **** MX_I2C1_Init(); + 105 .loc 1 127 3 + 106 0016 FFF7FEFF bl MX_I2C1_Init + 128:Core/Src/main.c **** MX_SPI1_Init(); + 107 .loc 1 128 3 + 108 001a FFF7FEFF bl MX_SPI1_Init + 129:Core/Src/main.c **** MX_TIM15_Init(); + 109 .loc 1 129 3 + 110 001e FFF7FEFF bl MX_TIM15_Init + 130:Core/Src/main.c **** MX_I2C2_Init(); + 111 .loc 1 130 3 + 112 0022 FFF7FEFF bl MX_I2C2_Init + 131:Core/Src/main.c **** MX_TIM2_Init(); + 113 .loc 1 131 3 + 114 0026 FFF7FEFF bl MX_TIM2_Init + 132:Core/Src/main.c **** MX_TIM3_Init(); + 115 .loc 1 132 3 + 116 002a FFF7FEFF bl MX_TIM3_Init + 133:Core/Src/main.c **** MX_TIM4_Init(); + 117 .loc 1 133 3 + 118 002e FFF7FEFF bl MX_TIM4_Init + 134:Core/Src/main.c **** /* USER CODE BEGIN 2 */ + 135:Core/Src/main.c **** sm_init(); + 119 .loc 1 135 3 + 120 0032 FFF7FEFF bl sm_init + 136:Core/Src/main.c **** tmp1075_init(&hi2c1); + 121 .loc 1 136 3 + 122 0036 1748 ldr r0, .L4 + 123 0038 FFF7FEFF bl tmp1075_init + 137:Core/Src/main.c **** AMS_Init(&hspi1); + 124 .loc 1 137 3 + 125 003c 1648 ldr r0, .L4+4 + 126 003e FFF7FEFF bl AMS_Init + 138:Core/Src/main.c **** can_init(&hcan); + 127 .loc 1 138 3 + 128 0042 1648 ldr r0, .L4+8 + 129 0044 FFF7FEFF bl can_init + 139:Core/Src/main.c **** PWM_control_init(&htim3, &htim2, &htim15); + 130 .loc 1 139 3 + 131 0048 154A ldr r2, .L4+12 + ARM GAS /tmp/ccSWt3lr.s page 6 + + + 132 004a 1649 ldr r1, .L4+16 + 133 004c 1648 ldr r0, .L4+20 + 134 004e FFF7FEFF bl PWM_control_init + 140:Core/Src/main.c **** soc_init(); + 135 .loc 1 140 3 + 136 0052 FFF7FEFF bl soc_init + 141:Core/Src/main.c **** status_led_init(&htim4, &htim4, &htim4); + 137 .loc 1 141 3 + 138 0056 154A ldr r2, .L4+24 + 139 0058 1449 ldr r1, .L4+24 + 140 005a 1448 ldr r0, .L4+24 + 141 005c FFF7FEFF bl status_led_init + 142:Core/Src/main.c **** sm_program_powerground(); + 142 .loc 1 142 3 + 143 0060 FFF7FEFF bl sm_program_powerground + 143:Core/Src/main.c **** eeprom_init(&hi2c2); + 144 .loc 1 143 3 + 145 0064 1248 ldr r0, .L4+28 + 146 0066 FFF7FEFF bl eeprom_init + 144:Core/Src/main.c **** AMS_Loop(); + 147 .loc 1 144 3 + 148 006a FFF7FEFF bl AMS_Loop + 145:Core/Src/main.c **** uint32_t startup_timer = 500 + HAL_GetTick(); + 149 .loc 1 145 34 + 150 006e FFF7FEFF bl HAL_GetTick + 151 0072 0346 mov r3, r0 + 152 .loc 1 145 12 discriminator 1 + 153 0074 03F5FA73 add r3, r3, #500 + 154 0078 7B60 str r3, [r7, #4] + 146:Core/Src/main.c **** while (startup_timer > HAL_GetTick()); + 155 .loc 1 146 9 + 156 007a 00BF nop + 157 .L2: + 158 .loc 1 146 26 discriminator 1 + 159 007c FFF7FEFF bl HAL_GetTick + 160 0080 0246 mov r2, r0 + 161 .loc 1 146 24 discriminator 1 + 162 0082 7B68 ldr r3, [r7, #4] + 163 0084 9342 cmp r3, r2 + 164 0086 F9D8 bhi .L2 + 165 .L3: + 147:Core/Src/main.c **** /* USER CODE END 2 */ + 148:Core/Src/main.c **** + 149:Core/Src/main.c **** /* Infinite loop */ + 150:Core/Src/main.c **** /* USER CODE BEGIN WHILE */ + 151:Core/Src/main.c **** while (1) + 152:Core/Src/main.c **** { + 153:Core/Src/main.c **** /* USER CODE END WHILE */ + 154:Core/Src/main.c **** + 155:Core/Src/main.c **** /* USER CODE BEGIN 3 */ + 156:Core/Src/main.c **** AMS_Loop(); + 166 .loc 1 156 5 + 167 0088 FFF7FEFF bl AMS_Loop + 157:Core/Src/main.c **** sm_update(); + 168 .loc 1 157 5 discriminator 1 + 169 008c FFF7FEFF bl sm_update + 156:Core/Src/main.c **** sm_update(); + ARM GAS /tmp/ccSWt3lr.s page 7 + + + 170 .loc 1 156 5 + 171 0090 00BF nop + 172 0092 F9E7 b .L3 + 173 .L5: + 174 .align 2 + 175 .L4: + 176 0094 00000000 .word hi2c1 + 177 0098 00000000 .word hspi1 + 178 009c 00000000 .word hcan + 179 00a0 00000000 .word htim15 + 180 00a4 00000000 .word htim2 + 181 00a8 00000000 .word htim3 + 182 00ac 00000000 .word htim4 + 183 00b0 00000000 .word hi2c2 + 184 .cfi_endproc + 185 .LFE130: + 187 .section .text.SystemClock_Config,"ax",%progbits + 188 .align 1 + 189 .global SystemClock_Config + 190 .syntax unified + 191 .thumb + 192 .thumb_func + 194 SystemClock_Config: + 195 .LFB131: + 158:Core/Src/main.c **** //sm_test_cycle_states(); + 159:Core/Src/main.c **** } + 160:Core/Src/main.c **** /* USER CODE END 3 */ + 161:Core/Src/main.c **** } + 162:Core/Src/main.c **** + 163:Core/Src/main.c **** /** + 164:Core/Src/main.c **** * @brief System Clock Configuration + 165:Core/Src/main.c **** * @retval None + 166:Core/Src/main.c **** */ + 167:Core/Src/main.c **** void SystemClock_Config(void) + 168:Core/Src/main.c **** { + 196 .loc 1 168 1 + 197 .cfi_startproc + 198 @ args = 0, pretend = 0, frame = 112 + 199 @ frame_needed = 1, uses_anonymous_args = 0 + 200 0000 80B5 push {r7, lr} + 201 .cfi_def_cfa_offset 8 + 202 .cfi_offset 7, -8 + 203 .cfi_offset 14, -4 + 204 0002 9CB0 sub sp, sp, #112 + 205 .cfi_def_cfa_offset 120 + 206 0004 00AF add r7, sp, #0 + 207 .cfi_def_cfa_register 7 + 169:Core/Src/main.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + 208 .loc 1 169 22 + 209 0006 07F14803 add r3, r7, #72 + 210 000a 2822 movs r2, #40 + 211 000c 0021 movs r1, #0 + 212 000e 1846 mov r0, r3 + 213 0010 FFF7FEFF bl memset + 170:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + 214 .loc 1 170 22 + 215 0014 07F13403 add r3, r7, #52 + ARM GAS /tmp/ccSWt3lr.s page 8 + + + 216 0018 0022 movs r2, #0 + 217 001a 1A60 str r2, [r3] + 218 001c 5A60 str r2, [r3, #4] + 219 001e 9A60 str r2, [r3, #8] + 220 0020 DA60 str r2, [r3, #12] + 221 0022 1A61 str r2, [r3, #16] + 171:Core/Src/main.c **** RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + 222 .loc 1 171 28 + 223 0024 3B46 mov r3, r7 + 224 0026 3422 movs r2, #52 + 225 0028 0021 movs r1, #0 + 226 002a 1846 mov r0, r3 + 227 002c FFF7FEFF bl memset + 172:Core/Src/main.c **** + 173:Core/Src/main.c **** /** Initializes the RCC Oscillators according to the specified parameters + 174:Core/Src/main.c **** * in the RCC_OscInitTypeDef structure. + 175:Core/Src/main.c **** */ + 176:Core/Src/main.c **** RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + 228 .loc 1 176 36 + 229 0030 0123 movs r3, #1 + 230 0032 BB64 str r3, [r7, #72] + 177:Core/Src/main.c **** RCC_OscInitStruct.HSEState = RCC_HSE_ON; + 231 .loc 1 177 30 + 232 0034 4FF48033 mov r3, #65536 + 233 0038 FB64 str r3, [r7, #76] + 178:Core/Src/main.c **** RCC_OscInitStruct.HSIState = RCC_HSI_ON; + 234 .loc 1 178 30 + 235 003a 0123 movs r3, #1 + 236 003c BB65 str r3, [r7, #88] + 179:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + 237 .loc 1 179 34 + 238 003e 0023 movs r3, #0 + 239 0040 7B66 str r3, [r7, #100] + 180:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + 240 .loc 1 180 7 + 241 0042 07F14803 add r3, r7, #72 + 242 0046 1846 mov r0, r3 + 243 0048 FFF7FEFF bl HAL_RCC_OscConfig + 244 004c 0346 mov r3, r0 + 245 .loc 1 180 6 discriminator 1 + 246 004e 002B cmp r3, #0 + 247 0050 01D0 beq .L7 + 181:Core/Src/main.c **** { + 182:Core/Src/main.c **** Error_Handler(); + 248 .loc 1 182 5 + 249 0052 FFF7FEFF bl Error_Handler + 250 .L7: + 183:Core/Src/main.c **** } + 184:Core/Src/main.c **** + 185:Core/Src/main.c **** /** Initializes the CPU, AHB and APB buses clocks + 186:Core/Src/main.c **** */ + 187:Core/Src/main.c **** RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + 251 .loc 1 187 31 + 252 0056 0F23 movs r3, #15 + 253 0058 7B63 str r3, [r7, #52] + 188:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + 189:Core/Src/main.c **** RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE; + ARM GAS /tmp/ccSWt3lr.s page 9 + + + 254 .loc 1 189 34 + 255 005a 0123 movs r3, #1 + 256 005c BB63 str r3, [r7, #56] + 190:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + 257 .loc 1 190 35 + 258 005e 0023 movs r3, #0 + 259 0060 FB63 str r3, [r7, #60] + 191:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + 260 .loc 1 191 36 + 261 0062 0023 movs r3, #0 + 262 0064 3B64 str r3, [r7, #64] + 192:Core/Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + 263 .loc 1 192 36 + 264 0066 0023 movs r3, #0 + 265 0068 7B64 str r3, [r7, #68] + 193:Core/Src/main.c **** + 194:Core/Src/main.c **** if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) + 266 .loc 1 194 7 + 267 006a 07F13403 add r3, r7, #52 + 268 006e 0021 movs r1, #0 + 269 0070 1846 mov r0, r3 + 270 0072 FFF7FEFF bl HAL_RCC_ClockConfig + 271 0076 0346 mov r3, r0 + 272 .loc 1 194 6 discriminator 1 + 273 0078 002B cmp r3, #0 + 274 007a 01D0 beq .L8 + 195:Core/Src/main.c **** { + 196:Core/Src/main.c **** Error_Handler(); + 275 .loc 1 196 5 + 276 007c FFF7FEFF bl Error_Handler + 277 .L8: + 197:Core/Src/main.c **** } + 198:Core/Src/main.c **** PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C1|RCC_PERIPHCLK_I2C2; + 278 .loc 1 198 38 + 279 0080 6023 movs r3, #96 + 280 0082 3B60 str r3, [r7] + 199:Core/Src/main.c **** PeriphClkInit.I2c1ClockSelection = RCC_I2C1CLKSOURCE_SYSCLK; + 281 .loc 1 199 36 + 282 0084 1023 movs r3, #16 + 283 0086 FB61 str r3, [r7, #28] + 200:Core/Src/main.c **** PeriphClkInit.I2c2ClockSelection = RCC_I2C2CLKSOURCE_SYSCLK; + 284 .loc 1 200 36 + 285 0088 2023 movs r3, #32 + 286 008a 3B62 str r3, [r7, #32] + 201:Core/Src/main.c **** if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + 287 .loc 1 201 7 + 288 008c 3B46 mov r3, r7 + 289 008e 1846 mov r0, r3 + 290 0090 FFF7FEFF bl HAL_RCCEx_PeriphCLKConfig + 291 0094 0346 mov r3, r0 + 292 .loc 1 201 6 discriminator 1 + 293 0096 002B cmp r3, #0 + 294 0098 01D0 beq .L10 + 202:Core/Src/main.c **** { + 203:Core/Src/main.c **** Error_Handler(); + 295 .loc 1 203 5 + 296 009a FFF7FEFF bl Error_Handler + ARM GAS /tmp/ccSWt3lr.s page 10 + + + 297 .L10: + 204:Core/Src/main.c **** } + 205:Core/Src/main.c **** } + 298 .loc 1 205 1 + 299 009e 00BF nop + 300 00a0 7037 adds r7, r7, #112 + 301 .cfi_def_cfa_offset 8 + 302 00a2 BD46 mov sp, r7 + 303 .cfi_def_cfa_register 13 + 304 @ sp needed + 305 00a4 80BD pop {r7, pc} + 306 .cfi_endproc + 307 .LFE131: + 309 .section .text.MX_CAN_Init,"ax",%progbits + 310 .align 1 + 311 .syntax unified + 312 .thumb + 313 .thumb_func + 315 MX_CAN_Init: + 316 .LFB132: + 206:Core/Src/main.c **** + 207:Core/Src/main.c **** /** + 208:Core/Src/main.c **** * @brief CAN Initialization Function + 209:Core/Src/main.c **** * @param None + 210:Core/Src/main.c **** * @retval None + 211:Core/Src/main.c **** */ + 212:Core/Src/main.c **** static void MX_CAN_Init(void) + 213:Core/Src/main.c **** { + 317 .loc 1 213 1 + 318 .cfi_startproc + 319 @ args = 0, pretend = 0, frame = 0 + 320 @ frame_needed = 1, uses_anonymous_args = 0 + 321 0000 80B5 push {r7, lr} + 322 .cfi_def_cfa_offset 8 + 323 .cfi_offset 7, -8 + 324 .cfi_offset 14, -4 + 325 0002 00AF add r7, sp, #0 + 326 .cfi_def_cfa_register 7 + 214:Core/Src/main.c **** + 215:Core/Src/main.c **** /* USER CODE BEGIN CAN_Init 0 */ + 216:Core/Src/main.c **** + 217:Core/Src/main.c **** /* USER CODE END CAN_Init 0 */ + 218:Core/Src/main.c **** + 219:Core/Src/main.c **** /* USER CODE BEGIN CAN_Init 1 */ + 220:Core/Src/main.c **** + 221:Core/Src/main.c **** /* USER CODE END CAN_Init 1 */ + 222:Core/Src/main.c **** hcan.Instance = CAN; + 327 .loc 1 222 17 + 328 0004 174B ldr r3, .L14 + 329 0006 184A ldr r2, .L14+4 + 330 0008 1A60 str r2, [r3] + 223:Core/Src/main.c **** hcan.Init.Prescaler = 2; + 331 .loc 1 223 23 + 332 000a 164B ldr r3, .L14 + 333 000c 0222 movs r2, #2 + 334 000e 5A60 str r2, [r3, #4] + 224:Core/Src/main.c **** hcan.Init.Mode = CAN_MODE_NORMAL; + ARM GAS /tmp/ccSWt3lr.s page 11 + + + 335 .loc 1 224 18 + 336 0010 144B ldr r3, .L14 + 337 0012 0022 movs r2, #0 + 338 0014 9A60 str r2, [r3, #8] + 225:Core/Src/main.c **** hcan.Init.SyncJumpWidth = CAN_SJW_1TQ; + 339 .loc 1 225 27 + 340 0016 134B ldr r3, .L14 + 341 0018 0022 movs r2, #0 + 342 001a DA60 str r2, [r3, #12] + 226:Core/Src/main.c **** hcan.Init.TimeSeg1 = CAN_BS1_13TQ; + 343 .loc 1 226 22 + 344 001c 114B ldr r3, .L14 + 345 001e 4FF44022 mov r2, #786432 + 346 0022 1A61 str r2, [r3, #16] + 227:Core/Src/main.c **** hcan.Init.TimeSeg2 = CAN_BS2_2TQ; + 347 .loc 1 227 22 + 348 0024 0F4B ldr r3, .L14 + 349 0026 4FF48012 mov r2, #1048576 + 350 002a 5A61 str r2, [r3, #20] + 228:Core/Src/main.c **** hcan.Init.TimeTriggeredMode = DISABLE; + 351 .loc 1 228 31 + 352 002c 0D4B ldr r3, .L14 + 353 002e 0022 movs r2, #0 + 354 0030 1A76 strb r2, [r3, #24] + 229:Core/Src/main.c **** hcan.Init.AutoBusOff = ENABLE; + 355 .loc 1 229 24 + 356 0032 0C4B ldr r3, .L14 + 357 0034 0122 movs r2, #1 + 358 0036 5A76 strb r2, [r3, #25] + 230:Core/Src/main.c **** hcan.Init.AutoWakeUp = DISABLE; + 359 .loc 1 230 24 + 360 0038 0A4B ldr r3, .L14 + 361 003a 0022 movs r2, #0 + 362 003c 9A76 strb r2, [r3, #26] + 231:Core/Src/main.c **** hcan.Init.AutoRetransmission = ENABLE; + 363 .loc 1 231 32 + 364 003e 094B ldr r3, .L14 + 365 0040 0122 movs r2, #1 + 366 0042 DA76 strb r2, [r3, #27] + 232:Core/Src/main.c **** hcan.Init.ReceiveFifoLocked = DISABLE; + 367 .loc 1 232 31 + 368 0044 074B ldr r3, .L14 + 369 0046 0022 movs r2, #0 + 370 0048 1A77 strb r2, [r3, #28] + 233:Core/Src/main.c **** hcan.Init.TransmitFifoPriority = DISABLE; + 371 .loc 1 233 34 + 372 004a 064B ldr r3, .L14 + 373 004c 0022 movs r2, #0 + 374 004e 5A77 strb r2, [r3, #29] + 234:Core/Src/main.c **** if (HAL_CAN_Init(&hcan) != HAL_OK) + 375 .loc 1 234 7 + 376 0050 0448 ldr r0, .L14 + 377 0052 FFF7FEFF bl HAL_CAN_Init + 378 0056 0346 mov r3, r0 + 379 .loc 1 234 6 discriminator 1 + 380 0058 002B cmp r3, #0 + 381 005a 01D0 beq .L13 + ARM GAS /tmp/ccSWt3lr.s page 12 + + + 235:Core/Src/main.c **** { + 236:Core/Src/main.c **** Error_Handler(); + 382 .loc 1 236 5 + 383 005c FFF7FEFF bl Error_Handler + 384 .L13: + 237:Core/Src/main.c **** } + 238:Core/Src/main.c **** /* USER CODE BEGIN CAN_Init 2 */ + 239:Core/Src/main.c **** + 240:Core/Src/main.c **** /* USER CODE END CAN_Init 2 */ + 241:Core/Src/main.c **** + 242:Core/Src/main.c **** } + 385 .loc 1 242 1 + 386 0060 00BF nop + 387 0062 80BD pop {r7, pc} + 388 .L15: + 389 .align 2 + 390 .L14: + 391 0064 00000000 .word hcan + 392 0068 00640040 .word 1073767424 + 393 .cfi_endproc + 394 .LFE132: + 396 .section .text.MX_I2C1_Init,"ax",%progbits + 397 .align 1 + 398 .syntax unified + 399 .thumb + 400 .thumb_func + 402 MX_I2C1_Init: + 403 .LFB133: + 243:Core/Src/main.c **** + 244:Core/Src/main.c **** /** + 245:Core/Src/main.c **** * @brief I2C1 Initialization Function + 246:Core/Src/main.c **** * @param None + 247:Core/Src/main.c **** * @retval None + 248:Core/Src/main.c **** */ + 249:Core/Src/main.c **** static void MX_I2C1_Init(void) + 250:Core/Src/main.c **** { + 404 .loc 1 250 1 + 405 .cfi_startproc + 406 @ args = 0, pretend = 0, frame = 0 + 407 @ frame_needed = 1, uses_anonymous_args = 0 + 408 0000 80B5 push {r7, lr} + 409 .cfi_def_cfa_offset 8 + 410 .cfi_offset 7, -8 + 411 .cfi_offset 14, -4 + 412 0002 00AF add r7, sp, #0 + 413 .cfi_def_cfa_register 7 + 251:Core/Src/main.c **** + 252:Core/Src/main.c **** /* USER CODE BEGIN I2C1_Init 0 */ + 253:Core/Src/main.c **** + 254:Core/Src/main.c **** /* USER CODE END I2C1_Init 0 */ + 255:Core/Src/main.c **** + 256:Core/Src/main.c **** /* USER CODE BEGIN I2C1_Init 1 */ + 257:Core/Src/main.c **** + 258:Core/Src/main.c **** /* USER CODE END I2C1_Init 1 */ + 259:Core/Src/main.c **** hi2c1.Instance = I2C1; + 414 .loc 1 259 18 + 415 0004 1B4B ldr r3, .L21 + ARM GAS /tmp/ccSWt3lr.s page 13 + + + 416 0006 1C4A ldr r2, .L21+4 + 417 0008 1A60 str r2, [r3] + 260:Core/Src/main.c **** hi2c1.Init.Timing = 0x00303D5B; + 418 .loc 1 260 21 + 419 000a 1A4B ldr r3, .L21 + 420 000c 1B4A ldr r2, .L21+8 + 421 000e 5A60 str r2, [r3, #4] + 261:Core/Src/main.c **** hi2c1.Init.OwnAddress1 = 0; + 422 .loc 1 261 26 + 423 0010 184B ldr r3, .L21 + 424 0012 0022 movs r2, #0 + 425 0014 9A60 str r2, [r3, #8] + 262:Core/Src/main.c **** hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + 426 .loc 1 262 29 + 427 0016 174B ldr r3, .L21 + 428 0018 0122 movs r2, #1 + 429 001a DA60 str r2, [r3, #12] + 263:Core/Src/main.c **** hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; + 430 .loc 1 263 30 + 431 001c 154B ldr r3, .L21 + 432 001e 0022 movs r2, #0 + 433 0020 1A61 str r2, [r3, #16] + 264:Core/Src/main.c **** hi2c1.Init.OwnAddress2 = 0; + 434 .loc 1 264 26 + 435 0022 144B ldr r3, .L21 + 436 0024 0022 movs r2, #0 + 437 0026 5A61 str r2, [r3, #20] + 265:Core/Src/main.c **** hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK; + 438 .loc 1 265 31 + 439 0028 124B ldr r3, .L21 + 440 002a 0022 movs r2, #0 + 441 002c 9A61 str r2, [r3, #24] + 266:Core/Src/main.c **** hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; + 442 .loc 1 266 30 + 443 002e 114B ldr r3, .L21 + 444 0030 0022 movs r2, #0 + 445 0032 DA61 str r2, [r3, #28] + 267:Core/Src/main.c **** hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; + 446 .loc 1 267 28 + 447 0034 0F4B ldr r3, .L21 + 448 0036 0022 movs r2, #0 + 449 0038 1A62 str r2, [r3, #32] + 268:Core/Src/main.c **** if (HAL_I2C_Init(&hi2c1) != HAL_OK) + 450 .loc 1 268 7 + 451 003a 0E48 ldr r0, .L21 + 452 003c FFF7FEFF bl HAL_I2C_Init + 453 0040 0346 mov r3, r0 + 454 .loc 1 268 6 discriminator 1 + 455 0042 002B cmp r3, #0 + 456 0044 01D0 beq .L17 + 269:Core/Src/main.c **** { + 270:Core/Src/main.c **** Error_Handler(); + 457 .loc 1 270 5 + 458 0046 FFF7FEFF bl Error_Handler + 459 .L17: + 271:Core/Src/main.c **** } + 272:Core/Src/main.c **** + ARM GAS /tmp/ccSWt3lr.s page 14 + + + 273:Core/Src/main.c **** /** Configure Analogue filter + 274:Core/Src/main.c **** */ + 275:Core/Src/main.c **** if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK) + 460 .loc 1 275 7 + 461 004a 0021 movs r1, #0 + 462 004c 0948 ldr r0, .L21 + 463 004e FFF7FEFF bl HAL_I2CEx_ConfigAnalogFilter + 464 0052 0346 mov r3, r0 + 465 .loc 1 275 6 discriminator 1 + 466 0054 002B cmp r3, #0 + 467 0056 01D0 beq .L18 + 276:Core/Src/main.c **** { + 277:Core/Src/main.c **** Error_Handler(); + 468 .loc 1 277 5 + 469 0058 FFF7FEFF bl Error_Handler + 470 .L18: + 278:Core/Src/main.c **** } + 279:Core/Src/main.c **** + 280:Core/Src/main.c **** /** Configure Digital filter + 281:Core/Src/main.c **** */ + 282:Core/Src/main.c **** if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK) + 471 .loc 1 282 7 + 472 005c 0021 movs r1, #0 + 473 005e 0548 ldr r0, .L21 + 474 0060 FFF7FEFF bl HAL_I2CEx_ConfigDigitalFilter + 475 0064 0346 mov r3, r0 + 476 .loc 1 282 6 discriminator 1 + 477 0066 002B cmp r3, #0 + 478 0068 01D0 beq .L20 + 283:Core/Src/main.c **** { + 284:Core/Src/main.c **** Error_Handler(); + 479 .loc 1 284 5 + 480 006a FFF7FEFF bl Error_Handler + 481 .L20: + 285:Core/Src/main.c **** } + 286:Core/Src/main.c **** /* USER CODE BEGIN I2C1_Init 2 */ + 287:Core/Src/main.c **** + 288:Core/Src/main.c **** /* USER CODE END I2C1_Init 2 */ + 289:Core/Src/main.c **** + 290:Core/Src/main.c **** } + 482 .loc 1 290 1 + 483 006e 00BF nop + 484 0070 80BD pop {r7, pc} + 485 .L22: + 486 0072 00BF .align 2 + 487 .L21: + 488 0074 00000000 .word hi2c1 + 489 0078 00540040 .word 1073763328 + 490 007c 5B3D3000 .word 3161435 + 491 .cfi_endproc + 492 .LFE133: + 494 .section .text.MX_I2C2_Init,"ax",%progbits + 495 .align 1 + 496 .syntax unified + 497 .thumb + 498 .thumb_func + 500 MX_I2C2_Init: + ARM GAS /tmp/ccSWt3lr.s page 15 + + + 501 .LFB134: + 291:Core/Src/main.c **** + 292:Core/Src/main.c **** /** + 293:Core/Src/main.c **** * @brief I2C2 Initialization Function + 294:Core/Src/main.c **** * @param None + 295:Core/Src/main.c **** * @retval None + 296:Core/Src/main.c **** */ + 297:Core/Src/main.c **** static void MX_I2C2_Init(void) + 298:Core/Src/main.c **** { + 502 .loc 1 298 1 + 503 .cfi_startproc + 504 @ args = 0, pretend = 0, frame = 0 + 505 @ frame_needed = 1, uses_anonymous_args = 0 + 506 0000 80B5 push {r7, lr} + 507 .cfi_def_cfa_offset 8 + 508 .cfi_offset 7, -8 + 509 .cfi_offset 14, -4 + 510 0002 00AF add r7, sp, #0 + 511 .cfi_def_cfa_register 7 + 299:Core/Src/main.c **** + 300:Core/Src/main.c **** /* USER CODE BEGIN I2C2_Init 0 */ + 301:Core/Src/main.c **** + 302:Core/Src/main.c **** /* USER CODE END I2C2_Init 0 */ + 303:Core/Src/main.c **** + 304:Core/Src/main.c **** /* USER CODE BEGIN I2C2_Init 1 */ + 305:Core/Src/main.c **** + 306:Core/Src/main.c **** /* USER CODE END I2C2_Init 1 */ + 307:Core/Src/main.c **** hi2c2.Instance = I2C2; + 512 .loc 1 307 18 + 513 0004 1B4B ldr r3, .L28 + 514 0006 1C4A ldr r2, .L28+4 + 515 0008 1A60 str r2, [r3] + 308:Core/Src/main.c **** hi2c2.Init.Timing = 0x00303D5B; + 516 .loc 1 308 21 + 517 000a 1A4B ldr r3, .L28 + 518 000c 1B4A ldr r2, .L28+8 + 519 000e 5A60 str r2, [r3, #4] + 309:Core/Src/main.c **** hi2c2.Init.OwnAddress1 = 0; + 520 .loc 1 309 26 + 521 0010 184B ldr r3, .L28 + 522 0012 0022 movs r2, #0 + 523 0014 9A60 str r2, [r3, #8] + 310:Core/Src/main.c **** hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + 524 .loc 1 310 29 + 525 0016 174B ldr r3, .L28 + 526 0018 0122 movs r2, #1 + 527 001a DA60 str r2, [r3, #12] + 311:Core/Src/main.c **** hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; + 528 .loc 1 311 30 + 529 001c 154B ldr r3, .L28 + 530 001e 0022 movs r2, #0 + 531 0020 1A61 str r2, [r3, #16] + 312:Core/Src/main.c **** hi2c2.Init.OwnAddress2 = 0; + 532 .loc 1 312 26 + 533 0022 144B ldr r3, .L28 + 534 0024 0022 movs r2, #0 + 535 0026 5A61 str r2, [r3, #20] + ARM GAS /tmp/ccSWt3lr.s page 16 + + + 313:Core/Src/main.c **** hi2c2.Init.OwnAddress2Masks = I2C_OA2_NOMASK; + 536 .loc 1 313 31 + 537 0028 124B ldr r3, .L28 + 538 002a 0022 movs r2, #0 + 539 002c 9A61 str r2, [r3, #24] + 314:Core/Src/main.c **** hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; + 540 .loc 1 314 30 + 541 002e 114B ldr r3, .L28 + 542 0030 0022 movs r2, #0 + 543 0032 DA61 str r2, [r3, #28] + 315:Core/Src/main.c **** hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; + 544 .loc 1 315 28 + 545 0034 0F4B ldr r3, .L28 + 546 0036 0022 movs r2, #0 + 547 0038 1A62 str r2, [r3, #32] + 316:Core/Src/main.c **** if (HAL_I2C_Init(&hi2c2) != HAL_OK) + 548 .loc 1 316 7 + 549 003a 0E48 ldr r0, .L28 + 550 003c FFF7FEFF bl HAL_I2C_Init + 551 0040 0346 mov r3, r0 + 552 .loc 1 316 6 discriminator 1 + 553 0042 002B cmp r3, #0 + 554 0044 01D0 beq .L24 + 317:Core/Src/main.c **** { + 318:Core/Src/main.c **** Error_Handler(); + 555 .loc 1 318 5 + 556 0046 FFF7FEFF bl Error_Handler + 557 .L24: + 319:Core/Src/main.c **** } + 320:Core/Src/main.c **** + 321:Core/Src/main.c **** /** Configure Analogue filter + 322:Core/Src/main.c **** */ + 323:Core/Src/main.c **** if (HAL_I2CEx_ConfigAnalogFilter(&hi2c2, I2C_ANALOGFILTER_ENABLE) != HAL_OK) + 558 .loc 1 323 7 + 559 004a 0021 movs r1, #0 + 560 004c 0948 ldr r0, .L28 + 561 004e FFF7FEFF bl HAL_I2CEx_ConfigAnalogFilter + 562 0052 0346 mov r3, r0 + 563 .loc 1 323 6 discriminator 1 + 564 0054 002B cmp r3, #0 + 565 0056 01D0 beq .L25 + 324:Core/Src/main.c **** { + 325:Core/Src/main.c **** Error_Handler(); + 566 .loc 1 325 5 + 567 0058 FFF7FEFF bl Error_Handler + 568 .L25: + 326:Core/Src/main.c **** } + 327:Core/Src/main.c **** + 328:Core/Src/main.c **** /** Configure Digital filter + 329:Core/Src/main.c **** */ + 330:Core/Src/main.c **** if (HAL_I2CEx_ConfigDigitalFilter(&hi2c2, 0) != HAL_OK) + 569 .loc 1 330 7 + 570 005c 0021 movs r1, #0 + 571 005e 0548 ldr r0, .L28 + 572 0060 FFF7FEFF bl HAL_I2CEx_ConfigDigitalFilter + 573 0064 0346 mov r3, r0 + 574 .loc 1 330 6 discriminator 1 + ARM GAS /tmp/ccSWt3lr.s page 17 + + + 575 0066 002B cmp r3, #0 + 576 0068 01D0 beq .L27 + 331:Core/Src/main.c **** { + 332:Core/Src/main.c **** Error_Handler(); + 577 .loc 1 332 5 + 578 006a FFF7FEFF bl Error_Handler + 579 .L27: + 333:Core/Src/main.c **** } + 334:Core/Src/main.c **** /* USER CODE BEGIN I2C2_Init 2 */ + 335:Core/Src/main.c **** + 336:Core/Src/main.c **** /* USER CODE END I2C2_Init 2 */ + 337:Core/Src/main.c **** + 338:Core/Src/main.c **** } + 580 .loc 1 338 1 + 581 006e 00BF nop + 582 0070 80BD pop {r7, pc} + 583 .L29: + 584 0072 00BF .align 2 + 585 .L28: + 586 0074 00000000 .word hi2c2 + 587 0078 00580040 .word 1073764352 + 588 007c 5B3D3000 .word 3161435 + 589 .cfi_endproc + 590 .LFE134: + 592 .section .text.MX_SPI1_Init,"ax",%progbits + 593 .align 1 + 594 .syntax unified + 595 .thumb + 596 .thumb_func + 598 MX_SPI1_Init: + 599 .LFB135: + 339:Core/Src/main.c **** + 340:Core/Src/main.c **** /** + 341:Core/Src/main.c **** * @brief SPI1 Initialization Function + 342:Core/Src/main.c **** * @param None + 343:Core/Src/main.c **** * @retval None + 344:Core/Src/main.c **** */ + 345:Core/Src/main.c **** static void MX_SPI1_Init(void) + 346:Core/Src/main.c **** { + 600 .loc 1 346 1 + 601 .cfi_startproc + 602 @ args = 0, pretend = 0, frame = 0 + 603 @ frame_needed = 1, uses_anonymous_args = 0 + 604 0000 80B5 push {r7, lr} + 605 .cfi_def_cfa_offset 8 + 606 .cfi_offset 7, -8 + 607 .cfi_offset 14, -4 + 608 0002 00AF add r7, sp, #0 + 609 .cfi_def_cfa_register 7 + 347:Core/Src/main.c **** + 348:Core/Src/main.c **** /* USER CODE BEGIN SPI1_Init 0 */ + 349:Core/Src/main.c **** + 350:Core/Src/main.c **** /* USER CODE END SPI1_Init 0 */ + 351:Core/Src/main.c **** + 352:Core/Src/main.c **** /* USER CODE BEGIN SPI1_Init 1 */ + 353:Core/Src/main.c **** + 354:Core/Src/main.c **** /* USER CODE END SPI1_Init 1 */ + ARM GAS /tmp/ccSWt3lr.s page 18 + + + 355:Core/Src/main.c **** /* SPI1 parameter configuration*/ + 356:Core/Src/main.c **** hspi1.Instance = SPI1; + 610 .loc 1 356 18 + 611 0004 1B4B ldr r3, .L33 + 612 0006 1C4A ldr r2, .L33+4 + 613 0008 1A60 str r2, [r3] + 357:Core/Src/main.c **** hspi1.Init.Mode = SPI_MODE_MASTER; + 614 .loc 1 357 19 + 615 000a 1A4B ldr r3, .L33 + 616 000c 4FF48272 mov r2, #260 + 617 0010 5A60 str r2, [r3, #4] + 358:Core/Src/main.c **** hspi1.Init.Direction = SPI_DIRECTION_2LINES; + 618 .loc 1 358 24 + 619 0012 184B ldr r3, .L33 + 620 0014 0022 movs r2, #0 + 621 0016 9A60 str r2, [r3, #8] + 359:Core/Src/main.c **** hspi1.Init.DataSize = SPI_DATASIZE_8BIT; + 622 .loc 1 359 23 + 623 0018 164B ldr r3, .L33 + 624 001a 4FF4E062 mov r2, #1792 + 625 001e DA60 str r2, [r3, #12] + 360:Core/Src/main.c **** hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; + 626 .loc 1 360 26 + 627 0020 144B ldr r3, .L33 + 628 0022 0022 movs r2, #0 + 629 0024 1A61 str r2, [r3, #16] + 361:Core/Src/main.c **** hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; + 630 .loc 1 361 23 + 631 0026 134B ldr r3, .L33 + 632 0028 0022 movs r2, #0 + 633 002a 5A61 str r2, [r3, #20] + 362:Core/Src/main.c **** hspi1.Init.NSS = SPI_NSS_SOFT; + 634 .loc 1 362 18 + 635 002c 114B ldr r3, .L33 + 636 002e 4FF40072 mov r2, #512 + 637 0032 9A61 str r2, [r3, #24] + 363:Core/Src/main.c **** hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_32; + 638 .loc 1 363 32 + 639 0034 0F4B ldr r3, .L33 + 640 0036 2022 movs r2, #32 + 641 0038 DA61 str r2, [r3, #28] + 364:Core/Src/main.c **** hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; + 642 .loc 1 364 23 + 643 003a 0E4B ldr r3, .L33 + 644 003c 0022 movs r2, #0 + 645 003e 1A62 str r2, [r3, #32] + 365:Core/Src/main.c **** hspi1.Init.TIMode = SPI_TIMODE_DISABLE; + 646 .loc 1 365 21 + 647 0040 0C4B ldr r3, .L33 + 648 0042 0022 movs r2, #0 + 649 0044 5A62 str r2, [r3, #36] + 366:Core/Src/main.c **** hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + 650 .loc 1 366 29 + 651 0046 0B4B ldr r3, .L33 + 652 0048 0022 movs r2, #0 + 653 004a 9A62 str r2, [r3, #40] + 367:Core/Src/main.c **** hspi1.Init.CRCPolynomial = 7; + ARM GAS /tmp/ccSWt3lr.s page 19 + + + 654 .loc 1 367 28 + 655 004c 094B ldr r3, .L33 + 656 004e 0722 movs r2, #7 + 657 0050 DA62 str r2, [r3, #44] + 368:Core/Src/main.c **** hspi1.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE; + 658 .loc 1 368 24 + 659 0052 084B ldr r3, .L33 + 660 0054 0022 movs r2, #0 + 661 0056 1A63 str r2, [r3, #48] + 369:Core/Src/main.c **** hspi1.Init.NSSPMode = SPI_NSS_PULSE_ENABLE; + 662 .loc 1 369 23 + 663 0058 064B ldr r3, .L33 + 664 005a 0822 movs r2, #8 + 665 005c 5A63 str r2, [r3, #52] + 370:Core/Src/main.c **** if (HAL_SPI_Init(&hspi1) != HAL_OK) + 666 .loc 1 370 7 + 667 005e 0548 ldr r0, .L33 + 668 0060 FFF7FEFF bl HAL_SPI_Init + 669 0064 0346 mov r3, r0 + 670 .loc 1 370 6 discriminator 1 + 671 0066 002B cmp r3, #0 + 672 0068 01D0 beq .L32 + 371:Core/Src/main.c **** { + 372:Core/Src/main.c **** Error_Handler(); + 673 .loc 1 372 5 + 674 006a FFF7FEFF bl Error_Handler + 675 .L32: + 373:Core/Src/main.c **** } + 374:Core/Src/main.c **** /* USER CODE BEGIN SPI1_Init 2 */ + 375:Core/Src/main.c **** + 376:Core/Src/main.c **** /* USER CODE END SPI1_Init 2 */ + 377:Core/Src/main.c **** + 378:Core/Src/main.c **** } + 676 .loc 1 378 1 + 677 006e 00BF nop + 678 0070 80BD pop {r7, pc} + 679 .L34: + 680 0072 00BF .align 2 + 681 .L33: + 682 0074 00000000 .word hspi1 + 683 0078 00300140 .word 1073819648 + 684 .cfi_endproc + 685 .LFE135: + 687 .section .text.MX_TIM2_Init,"ax",%progbits + 688 .align 1 + 689 .syntax unified + 690 .thumb + 691 .thumb_func + 693 MX_TIM2_Init: + 694 .LFB136: + 379:Core/Src/main.c **** + 380:Core/Src/main.c **** /** + 381:Core/Src/main.c **** * @brief TIM2 Initialization Function + 382:Core/Src/main.c **** * @param None + 383:Core/Src/main.c **** * @retval None + 384:Core/Src/main.c **** */ + 385:Core/Src/main.c **** static void MX_TIM2_Init(void) + ARM GAS /tmp/ccSWt3lr.s page 20 + + + 386:Core/Src/main.c **** { + 695 .loc 1 386 1 + 696 .cfi_startproc + 697 @ args = 0, pretend = 0, frame = 40 + 698 @ frame_needed = 1, uses_anonymous_args = 0 + 699 0000 80B5 push {r7, lr} + 700 .cfi_def_cfa_offset 8 + 701 .cfi_offset 7, -8 + 702 .cfi_offset 14, -4 + 703 0002 8AB0 sub sp, sp, #40 + 704 .cfi_def_cfa_offset 48 + 705 0004 00AF add r7, sp, #0 + 706 .cfi_def_cfa_register 7 + 387:Core/Src/main.c **** + 388:Core/Src/main.c **** /* USER CODE BEGIN TIM2_Init 0 */ + 389:Core/Src/main.c **** + 390:Core/Src/main.c **** /* USER CODE END TIM2_Init 0 */ + 391:Core/Src/main.c **** + 392:Core/Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0}; + 707 .loc 1 392 27 + 708 0006 07F11C03 add r3, r7, #28 + 709 000a 0022 movs r2, #0 + 710 000c 1A60 str r2, [r3] + 711 000e 5A60 str r2, [r3, #4] + 712 0010 9A60 str r2, [r3, #8] + 393:Core/Src/main.c **** TIM_OC_InitTypeDef sConfigOC = {0}; + 713 .loc 1 393 22 + 714 0012 3B46 mov r3, r7 + 715 0014 0022 movs r2, #0 + 716 0016 1A60 str r2, [r3] + 717 0018 5A60 str r2, [r3, #4] + 718 001a 9A60 str r2, [r3, #8] + 719 001c DA60 str r2, [r3, #12] + 720 001e 1A61 str r2, [r3, #16] + 721 0020 5A61 str r2, [r3, #20] + 722 0022 9A61 str r2, [r3, #24] + 394:Core/Src/main.c **** + 395:Core/Src/main.c **** /* USER CODE BEGIN TIM2_Init 1 */ + 396:Core/Src/main.c **** + 397:Core/Src/main.c **** /* USER CODE END TIM2_Init 1 */ + 398:Core/Src/main.c **** htim2.Instance = TIM2; + 723 .loc 1 398 18 + 724 0024 274B ldr r3, .L40 + 725 0026 4FF08042 mov r2, #1073741824 + 726 002a 1A60 str r2, [r3] + 399:Core/Src/main.c **** htim2.Init.Prescaler = 0; + 727 .loc 1 399 24 + 728 002c 254B ldr r3, .L40 + 729 002e 0022 movs r2, #0 + 730 0030 5A60 str r2, [r3, #4] + 400:Core/Src/main.c **** htim2.Init.CounterMode = TIM_COUNTERMODE_UP; + 731 .loc 1 400 26 + 732 0032 244B ldr r3, .L40 + 733 0034 0022 movs r2, #0 + 734 0036 9A60 str r2, [r3, #8] + 401:Core/Src/main.c **** htim2.Init.Period = 4294967295; + 735 .loc 1 401 21 + ARM GAS /tmp/ccSWt3lr.s page 21 + + + 736 0038 224B ldr r3, .L40 + 737 003a 4FF0FF32 mov r2, #-1 + 738 003e DA60 str r2, [r3, #12] + 402:Core/Src/main.c **** htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + 739 .loc 1 402 28 + 740 0040 204B ldr r3, .L40 + 741 0042 0022 movs r2, #0 + 742 0044 1A61 str r2, [r3, #16] + 403:Core/Src/main.c **** htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + 743 .loc 1 403 32 + 744 0046 1F4B ldr r3, .L40 + 745 0048 0022 movs r2, #0 + 746 004a 9A61 str r2, [r3, #24] + 404:Core/Src/main.c **** if (HAL_TIM_PWM_Init(&htim2) != HAL_OK) + 747 .loc 1 404 7 + 748 004c 1D48 ldr r0, .L40 + 749 004e FFF7FEFF bl HAL_TIM_PWM_Init + 750 0052 0346 mov r3, r0 + 751 .loc 1 404 6 discriminator 1 + 752 0054 002B cmp r3, #0 + 753 0056 01D0 beq .L36 + 405:Core/Src/main.c **** { + 406:Core/Src/main.c **** Error_Handler(); + 754 .loc 1 406 5 + 755 0058 FFF7FEFF bl Error_Handler + 756 .L36: + 407:Core/Src/main.c **** } + 408:Core/Src/main.c **** sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + 757 .loc 1 408 37 + 758 005c 0023 movs r3, #0 + 759 005e FB61 str r3, [r7, #28] + 409:Core/Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + 760 .loc 1 409 33 + 761 0060 0023 movs r3, #0 + 762 0062 7B62 str r3, [r7, #36] + 410:Core/Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) + 763 .loc 1 410 7 + 764 0064 07F11C03 add r3, r7, #28 + 765 0068 1946 mov r1, r3 + 766 006a 1648 ldr r0, .L40 + 767 006c FFF7FEFF bl HAL_TIMEx_MasterConfigSynchronization + 768 0070 0346 mov r3, r0 + 769 .loc 1 410 6 discriminator 1 + 770 0072 002B cmp r3, #0 + 771 0074 01D0 beq .L37 + 411:Core/Src/main.c **** { + 412:Core/Src/main.c **** Error_Handler(); + 772 .loc 1 412 5 + 773 0076 FFF7FEFF bl Error_Handler + 774 .L37: + 413:Core/Src/main.c **** } + 414:Core/Src/main.c **** sConfigOC.OCMode = TIM_OCMODE_PWM1; + 775 .loc 1 414 20 + 776 007a 6023 movs r3, #96 + 777 007c 3B60 str r3, [r7] + 415:Core/Src/main.c **** sConfigOC.Pulse = 0; + 778 .loc 1 415 19 + ARM GAS /tmp/ccSWt3lr.s page 22 + + + 779 007e 0023 movs r3, #0 + 780 0080 7B60 str r3, [r7, #4] + 416:Core/Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + 781 .loc 1 416 24 + 782 0082 0023 movs r3, #0 + 783 0084 BB60 str r3, [r7, #8] + 417:Core/Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + 784 .loc 1 417 24 + 785 0086 0023 movs r3, #0 + 786 0088 3B61 str r3, [r7, #16] + 418:Core/Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) + 787 .loc 1 418 7 + 788 008a 3B46 mov r3, r7 + 789 008c 0822 movs r2, #8 + 790 008e 1946 mov r1, r3 + 791 0090 0C48 ldr r0, .L40 + 792 0092 FFF7FEFF bl HAL_TIM_PWM_ConfigChannel + 793 0096 0346 mov r3, r0 + 794 .loc 1 418 6 discriminator 1 + 795 0098 002B cmp r3, #0 + 796 009a 01D0 beq .L38 + 419:Core/Src/main.c **** { + 420:Core/Src/main.c **** Error_Handler(); + 797 .loc 1 420 5 + 798 009c FFF7FEFF bl Error_Handler + 799 .L38: + 421:Core/Src/main.c **** } + 422:Core/Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) + 800 .loc 1 422 7 + 801 00a0 3B46 mov r3, r7 + 802 00a2 0C22 movs r2, #12 + 803 00a4 1946 mov r1, r3 + 804 00a6 0748 ldr r0, .L40 + 805 00a8 FFF7FEFF bl HAL_TIM_PWM_ConfigChannel + 806 00ac 0346 mov r3, r0 + 807 .loc 1 422 6 discriminator 1 + 808 00ae 002B cmp r3, #0 + 809 00b0 01D0 beq .L39 + 423:Core/Src/main.c **** { + 424:Core/Src/main.c **** Error_Handler(); + 810 .loc 1 424 5 + 811 00b2 FFF7FEFF bl Error_Handler + 812 .L39: + 425:Core/Src/main.c **** } + 426:Core/Src/main.c **** /* USER CODE BEGIN TIM2_Init 2 */ + 427:Core/Src/main.c **** + 428:Core/Src/main.c **** /* USER CODE END TIM2_Init 2 */ + 429:Core/Src/main.c **** HAL_TIM_MspPostInit(&htim2); + 813 .loc 1 429 3 + 814 00b6 0348 ldr r0, .L40 + 815 00b8 FFF7FEFF bl HAL_TIM_MspPostInit + 430:Core/Src/main.c **** + 431:Core/Src/main.c **** } + 816 .loc 1 431 1 + 817 00bc 00BF nop + 818 00be 2837 adds r7, r7, #40 + 819 .cfi_def_cfa_offset 8 + ARM GAS /tmp/ccSWt3lr.s page 23 + + + 820 00c0 BD46 mov sp, r7 + 821 .cfi_def_cfa_register 13 + 822 @ sp needed + 823 00c2 80BD pop {r7, pc} + 824 .L41: + 825 .align 2 + 826 .L40: + 827 00c4 00000000 .word htim2 + 828 .cfi_endproc + 829 .LFE136: + 831 .section .text.MX_TIM3_Init,"ax",%progbits + 832 .align 1 + 833 .syntax unified + 834 .thumb + 835 .thumb_func + 837 MX_TIM3_Init: + 838 .LFB137: + 432:Core/Src/main.c **** + 433:Core/Src/main.c **** /** + 434:Core/Src/main.c **** * @brief TIM3 Initialization Function + 435:Core/Src/main.c **** * @param None + 436:Core/Src/main.c **** * @retval None + 437:Core/Src/main.c **** */ + 438:Core/Src/main.c **** static void MX_TIM3_Init(void) + 439:Core/Src/main.c **** { + 839 .loc 1 439 1 + 840 .cfi_startproc + 841 @ args = 0, pretend = 0, frame = 40 + 842 @ frame_needed = 1, uses_anonymous_args = 0 + 843 0000 80B5 push {r7, lr} + 844 .cfi_def_cfa_offset 8 + 845 .cfi_offset 7, -8 + 846 .cfi_offset 14, -4 + 847 0002 8AB0 sub sp, sp, #40 + 848 .cfi_def_cfa_offset 48 + 849 0004 00AF add r7, sp, #0 + 850 .cfi_def_cfa_register 7 + 440:Core/Src/main.c **** + 441:Core/Src/main.c **** /* USER CODE BEGIN TIM3_Init 0 */ + 442:Core/Src/main.c **** + 443:Core/Src/main.c **** /* USER CODE END TIM3_Init 0 */ + 444:Core/Src/main.c **** + 445:Core/Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0}; + 851 .loc 1 445 27 + 852 0006 07F11C03 add r3, r7, #28 + 853 000a 0022 movs r2, #0 + 854 000c 1A60 str r2, [r3] + 855 000e 5A60 str r2, [r3, #4] + 856 0010 9A60 str r2, [r3, #8] + 446:Core/Src/main.c **** TIM_OC_InitTypeDef sConfigOC = {0}; + 857 .loc 1 446 22 + 858 0012 3B46 mov r3, r7 + 859 0014 0022 movs r2, #0 + 860 0016 1A60 str r2, [r3] + 861 0018 5A60 str r2, [r3, #4] + 862 001a 9A60 str r2, [r3, #8] + 863 001c DA60 str r2, [r3, #12] + ARM GAS /tmp/ccSWt3lr.s page 24 + + + 864 001e 1A61 str r2, [r3, #16] + 865 0020 5A61 str r2, [r3, #20] + 866 0022 9A61 str r2, [r3, #24] + 447:Core/Src/main.c **** + 448:Core/Src/main.c **** /* USER CODE BEGIN TIM3_Init 1 */ + 449:Core/Src/main.c **** + 450:Core/Src/main.c **** /* USER CODE END TIM3_Init 1 */ + 451:Core/Src/main.c **** htim3.Instance = TIM3; + 867 .loc 1 451 18 + 868 0024 274B ldr r3, .L47 + 869 0026 284A ldr r2, .L47+4 + 870 0028 1A60 str r2, [r3] + 452:Core/Src/main.c **** htim3.Init.Prescaler = 7; + 871 .loc 1 452 24 + 872 002a 264B ldr r3, .L47 + 873 002c 0722 movs r2, #7 + 874 002e 5A60 str r2, [r3, #4] + 453:Core/Src/main.c **** htim3.Init.CounterMode = TIM_COUNTERMODE_UP; + 875 .loc 1 453 26 + 876 0030 244B ldr r3, .L47 + 877 0032 0022 movs r2, #0 + 878 0034 9A60 str r2, [r3, #8] + 454:Core/Src/main.c **** htim3.Init.Period = 39999; + 879 .loc 1 454 21 + 880 0036 234B ldr r3, .L47 + 881 0038 49F63F42 movw r2, #39999 + 882 003c DA60 str r2, [r3, #12] + 455:Core/Src/main.c **** htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + 883 .loc 1 455 28 + 884 003e 214B ldr r3, .L47 + 885 0040 0022 movs r2, #0 + 886 0042 1A61 str r2, [r3, #16] + 456:Core/Src/main.c **** htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + 887 .loc 1 456 32 + 888 0044 1F4B ldr r3, .L47 + 889 0046 0022 movs r2, #0 + 890 0048 9A61 str r2, [r3, #24] + 457:Core/Src/main.c **** if (HAL_TIM_PWM_Init(&htim3) != HAL_OK) + 891 .loc 1 457 7 + 892 004a 1E48 ldr r0, .L47 + 893 004c FFF7FEFF bl HAL_TIM_PWM_Init + 894 0050 0346 mov r3, r0 + 895 .loc 1 457 6 discriminator 1 + 896 0052 002B cmp r3, #0 + 897 0054 01D0 beq .L43 + 458:Core/Src/main.c **** { + 459:Core/Src/main.c **** Error_Handler(); + 898 .loc 1 459 5 + 899 0056 FFF7FEFF bl Error_Handler + 900 .L43: + 460:Core/Src/main.c **** } + 461:Core/Src/main.c **** sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + 901 .loc 1 461 37 + 902 005a 0023 movs r3, #0 + 903 005c FB61 str r3, [r7, #28] + 462:Core/Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + 904 .loc 1 462 33 + ARM GAS /tmp/ccSWt3lr.s page 25 + + + 905 005e 0023 movs r3, #0 + 906 0060 7B62 str r3, [r7, #36] + 463:Core/Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) + 907 .loc 1 463 7 + 908 0062 07F11C03 add r3, r7, #28 + 909 0066 1946 mov r1, r3 + 910 0068 1648 ldr r0, .L47 + 911 006a FFF7FEFF bl HAL_TIMEx_MasterConfigSynchronization + 912 006e 0346 mov r3, r0 + 913 .loc 1 463 6 discriminator 1 + 914 0070 002B cmp r3, #0 + 915 0072 01D0 beq .L44 + 464:Core/Src/main.c **** { + 465:Core/Src/main.c **** Error_Handler(); + 916 .loc 1 465 5 + 917 0074 FFF7FEFF bl Error_Handler + 918 .L44: + 466:Core/Src/main.c **** } + 467:Core/Src/main.c **** sConfigOC.OCMode = TIM_OCMODE_PWM1; + 919 .loc 1 467 20 + 920 0078 6023 movs r3, #96 + 921 007a 3B60 str r3, [r7] + 468:Core/Src/main.c **** sConfigOC.Pulse = 0; + 922 .loc 1 468 19 + 923 007c 0023 movs r3, #0 + 924 007e 7B60 str r3, [r7, #4] + 469:Core/Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + 925 .loc 1 469 24 + 926 0080 0023 movs r3, #0 + 927 0082 BB60 str r3, [r7, #8] + 470:Core/Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + 928 .loc 1 470 24 + 929 0084 0023 movs r3, #0 + 930 0086 3B61 str r3, [r7, #16] + 471:Core/Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) + 931 .loc 1 471 7 + 932 0088 3B46 mov r3, r7 + 933 008a 0822 movs r2, #8 + 934 008c 1946 mov r1, r3 + 935 008e 0D48 ldr r0, .L47 + 936 0090 FFF7FEFF bl HAL_TIM_PWM_ConfigChannel + 937 0094 0346 mov r3, r0 + 938 .loc 1 471 6 discriminator 1 + 939 0096 002B cmp r3, #0 + 940 0098 01D0 beq .L45 + 472:Core/Src/main.c **** { + 473:Core/Src/main.c **** Error_Handler(); + 941 .loc 1 473 5 + 942 009a FFF7FEFF bl Error_Handler + 943 .L45: + 474:Core/Src/main.c **** } + 475:Core/Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) + 944 .loc 1 475 7 + 945 009e 3B46 mov r3, r7 + 946 00a0 0C22 movs r2, #12 + 947 00a2 1946 mov r1, r3 + 948 00a4 0748 ldr r0, .L47 + ARM GAS /tmp/ccSWt3lr.s page 26 + + + 949 00a6 FFF7FEFF bl HAL_TIM_PWM_ConfigChannel + 950 00aa 0346 mov r3, r0 + 951 .loc 1 475 6 discriminator 1 + 952 00ac 002B cmp r3, #0 + 953 00ae 01D0 beq .L46 + 476:Core/Src/main.c **** { + 477:Core/Src/main.c **** Error_Handler(); + 954 .loc 1 477 5 + 955 00b0 FFF7FEFF bl Error_Handler + 956 .L46: + 478:Core/Src/main.c **** } + 479:Core/Src/main.c **** /* USER CODE BEGIN TIM3_Init 2 */ + 480:Core/Src/main.c **** + 481:Core/Src/main.c **** /* USER CODE END TIM3_Init 2 */ + 482:Core/Src/main.c **** HAL_TIM_MspPostInit(&htim3); + 957 .loc 1 482 3 + 958 00b4 0348 ldr r0, .L47 + 959 00b6 FFF7FEFF bl HAL_TIM_MspPostInit + 483:Core/Src/main.c **** + 484:Core/Src/main.c **** } + 960 .loc 1 484 1 + 961 00ba 00BF nop + 962 00bc 2837 adds r7, r7, #40 + 963 .cfi_def_cfa_offset 8 + 964 00be BD46 mov sp, r7 + 965 .cfi_def_cfa_register 13 + 966 @ sp needed + 967 00c0 80BD pop {r7, pc} + 968 .L48: + 969 00c2 00BF .align 2 + 970 .L47: + 971 00c4 00000000 .word htim3 + 972 00c8 00040040 .word 1073742848 + 973 .cfi_endproc + 974 .LFE137: + 976 .section .text.MX_TIM4_Init,"ax",%progbits + 977 .align 1 + 978 .syntax unified + 979 .thumb + 980 .thumb_func + 982 MX_TIM4_Init: + 983 .LFB138: + 485:Core/Src/main.c **** + 486:Core/Src/main.c **** /** + 487:Core/Src/main.c **** * @brief TIM4 Initialization Function + 488:Core/Src/main.c **** * @param None + 489:Core/Src/main.c **** * @retval None + 490:Core/Src/main.c **** */ + 491:Core/Src/main.c **** static void MX_TIM4_Init(void) + 492:Core/Src/main.c **** { + 984 .loc 1 492 1 + 985 .cfi_startproc + 986 @ args = 0, pretend = 0, frame = 40 + 987 @ frame_needed = 1, uses_anonymous_args = 0 + 988 0000 80B5 push {r7, lr} + 989 .cfi_def_cfa_offset 8 + 990 .cfi_offset 7, -8 + ARM GAS /tmp/ccSWt3lr.s page 27 + + + 991 .cfi_offset 14, -4 + 992 0002 8AB0 sub sp, sp, #40 + 993 .cfi_def_cfa_offset 48 + 994 0004 00AF add r7, sp, #0 + 995 .cfi_def_cfa_register 7 + 493:Core/Src/main.c **** + 494:Core/Src/main.c **** /* USER CODE BEGIN TIM4_Init 0 */ + 495:Core/Src/main.c **** + 496:Core/Src/main.c **** /* USER CODE END TIM4_Init 0 */ + 497:Core/Src/main.c **** + 498:Core/Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0}; + 996 .loc 1 498 27 + 997 0006 07F11C03 add r3, r7, #28 + 998 000a 0022 movs r2, #0 + 999 000c 1A60 str r2, [r3] + 1000 000e 5A60 str r2, [r3, #4] + 1001 0010 9A60 str r2, [r3, #8] + 499:Core/Src/main.c **** TIM_OC_InitTypeDef sConfigOC = {0}; + 1002 .loc 1 499 22 + 1003 0012 3B46 mov r3, r7 + 1004 0014 0022 movs r2, #0 + 1005 0016 1A60 str r2, [r3] + 1006 0018 5A60 str r2, [r3, #4] + 1007 001a 9A60 str r2, [r3, #8] + 1008 001c DA60 str r2, [r3, #12] + 1009 001e 1A61 str r2, [r3, #16] + 1010 0020 5A61 str r2, [r3, #20] + 1011 0022 9A61 str r2, [r3, #24] + 500:Core/Src/main.c **** + 501:Core/Src/main.c **** /* USER CODE BEGIN TIM4_Init 1 */ + 502:Core/Src/main.c **** + 503:Core/Src/main.c **** /* USER CODE END TIM4_Init 1 */ + 504:Core/Src/main.c **** htim4.Instance = TIM4; + 1012 .loc 1 504 18 + 1013 0024 2C4B ldr r3, .L55 + 1014 0026 2D4A ldr r2, .L55+4 + 1015 0028 1A60 str r2, [r3] + 505:Core/Src/main.c **** htim4.Init.Prescaler = 624; + 1016 .loc 1 505 24 + 1017 002a 2B4B ldr r3, .L55 + 1018 002c 4FF41C72 mov r2, #624 + 1019 0030 5A60 str r2, [r3, #4] + 506:Core/Src/main.c **** htim4.Init.CounterMode = TIM_COUNTERMODE_UP; + 1020 .loc 1 506 26 + 1021 0032 294B ldr r3, .L55 + 1022 0034 0022 movs r2, #0 + 1023 0036 9A60 str r2, [r3, #8] + 507:Core/Src/main.c **** htim4.Init.Period = 255; + 1024 .loc 1 507 21 + 1025 0038 274B ldr r3, .L55 + 1026 003a FF22 movs r2, #255 + 1027 003c DA60 str r2, [r3, #12] + 508:Core/Src/main.c **** htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + 1028 .loc 1 508 28 + 1029 003e 264B ldr r3, .L55 + 1030 0040 0022 movs r2, #0 + 1031 0042 1A61 str r2, [r3, #16] + ARM GAS /tmp/ccSWt3lr.s page 28 + + + 509:Core/Src/main.c **** htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + 1032 .loc 1 509 32 + 1033 0044 244B ldr r3, .L55 + 1034 0046 0022 movs r2, #0 + 1035 0048 9A61 str r2, [r3, #24] + 510:Core/Src/main.c **** if (HAL_TIM_PWM_Init(&htim4) != HAL_OK) + 1036 .loc 1 510 7 + 1037 004a 2348 ldr r0, .L55 + 1038 004c FFF7FEFF bl HAL_TIM_PWM_Init + 1039 0050 0346 mov r3, r0 + 1040 .loc 1 510 6 discriminator 1 + 1041 0052 002B cmp r3, #0 + 1042 0054 01D0 beq .L50 + 511:Core/Src/main.c **** { + 512:Core/Src/main.c **** Error_Handler(); + 1043 .loc 1 512 5 + 1044 0056 FFF7FEFF bl Error_Handler + 1045 .L50: + 513:Core/Src/main.c **** } + 514:Core/Src/main.c **** sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + 1046 .loc 1 514 37 + 1047 005a 0023 movs r3, #0 + 1048 005c FB61 str r3, [r7, #28] + 515:Core/Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + 1049 .loc 1 515 33 + 1050 005e 0023 movs r3, #0 + 1051 0060 7B62 str r3, [r7, #36] + 516:Core/Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) + 1052 .loc 1 516 7 + 1053 0062 07F11C03 add r3, r7, #28 + 1054 0066 1946 mov r1, r3 + 1055 0068 1B48 ldr r0, .L55 + 1056 006a FFF7FEFF bl HAL_TIMEx_MasterConfigSynchronization + 1057 006e 0346 mov r3, r0 + 1058 .loc 1 516 6 discriminator 1 + 1059 0070 002B cmp r3, #0 + 1060 0072 01D0 beq .L51 + 517:Core/Src/main.c **** { + 518:Core/Src/main.c **** Error_Handler(); + 1061 .loc 1 518 5 + 1062 0074 FFF7FEFF bl Error_Handler + 1063 .L51: + 519:Core/Src/main.c **** } + 520:Core/Src/main.c **** sConfigOC.OCMode = TIM_OCMODE_PWM1; + 1064 .loc 1 520 20 + 1065 0078 6023 movs r3, #96 + 1066 007a 3B60 str r3, [r7] + 521:Core/Src/main.c **** sConfigOC.Pulse = 0; + 1067 .loc 1 521 19 + 1068 007c 0023 movs r3, #0 + 1069 007e 7B60 str r3, [r7, #4] + 522:Core/Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + 1070 .loc 1 522 24 + 1071 0080 0023 movs r3, #0 + 1072 0082 BB60 str r3, [r7, #8] + 523:Core/Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + 1073 .loc 1 523 24 + ARM GAS /tmp/ccSWt3lr.s page 29 + + + 1074 0084 0023 movs r3, #0 + 1075 0086 3B61 str r3, [r7, #16] + 524:Core/Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) + 1076 .loc 1 524 7 + 1077 0088 3B46 mov r3, r7 + 1078 008a 0022 movs r2, #0 + 1079 008c 1946 mov r1, r3 + 1080 008e 1248 ldr r0, .L55 + 1081 0090 FFF7FEFF bl HAL_TIM_PWM_ConfigChannel + 1082 0094 0346 mov r3, r0 + 1083 .loc 1 524 6 discriminator 1 + 1084 0096 002B cmp r3, #0 + 1085 0098 01D0 beq .L52 + 525:Core/Src/main.c **** { + 526:Core/Src/main.c **** Error_Handler(); + 1086 .loc 1 526 5 + 1087 009a FFF7FEFF bl Error_Handler + 1088 .L52: + 527:Core/Src/main.c **** } + 528:Core/Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) + 1089 .loc 1 528 7 + 1090 009e 3B46 mov r3, r7 + 1091 00a0 0422 movs r2, #4 + 1092 00a2 1946 mov r1, r3 + 1093 00a4 0C48 ldr r0, .L55 + 1094 00a6 FFF7FEFF bl HAL_TIM_PWM_ConfigChannel + 1095 00aa 0346 mov r3, r0 + 1096 .loc 1 528 6 discriminator 1 + 1097 00ac 002B cmp r3, #0 + 1098 00ae 01D0 beq .L53 + 529:Core/Src/main.c **** { + 530:Core/Src/main.c **** Error_Handler(); + 1099 .loc 1 530 5 + 1100 00b0 FFF7FEFF bl Error_Handler + 1101 .L53: + 531:Core/Src/main.c **** } + 532:Core/Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) + 1102 .loc 1 532 7 + 1103 00b4 3B46 mov r3, r7 + 1104 00b6 0822 movs r2, #8 + 1105 00b8 1946 mov r1, r3 + 1106 00ba 0748 ldr r0, .L55 + 1107 00bc FFF7FEFF bl HAL_TIM_PWM_ConfigChannel + 1108 00c0 0346 mov r3, r0 + 1109 .loc 1 532 6 discriminator 1 + 1110 00c2 002B cmp r3, #0 + 1111 00c4 01D0 beq .L54 + 533:Core/Src/main.c **** { + 534:Core/Src/main.c **** Error_Handler(); + 1112 .loc 1 534 5 + 1113 00c6 FFF7FEFF bl Error_Handler + 1114 .L54: + 535:Core/Src/main.c **** } + 536:Core/Src/main.c **** /* USER CODE BEGIN TIM4_Init 2 */ + 537:Core/Src/main.c **** + 538:Core/Src/main.c **** /* USER CODE END TIM4_Init 2 */ + 539:Core/Src/main.c **** HAL_TIM_MspPostInit(&htim4); + ARM GAS /tmp/ccSWt3lr.s page 30 + + + 1115 .loc 1 539 3 + 1116 00ca 0348 ldr r0, .L55 + 1117 00cc FFF7FEFF bl HAL_TIM_MspPostInit + 540:Core/Src/main.c **** + 541:Core/Src/main.c **** } + 1118 .loc 1 541 1 + 1119 00d0 00BF nop + 1120 00d2 2837 adds r7, r7, #40 + 1121 .cfi_def_cfa_offset 8 + 1122 00d4 BD46 mov sp, r7 + 1123 .cfi_def_cfa_register 13 + 1124 @ sp needed + 1125 00d6 80BD pop {r7, pc} + 1126 .L56: + 1127 .align 2 + 1128 .L55: + 1129 00d8 00000000 .word htim4 + 1130 00dc 00080040 .word 1073743872 + 1131 .cfi_endproc + 1132 .LFE138: + 1134 .section .text.MX_TIM15_Init,"ax",%progbits + 1135 .align 1 + 1136 .syntax unified + 1137 .thumb + 1138 .thumb_func + 1140 MX_TIM15_Init: + 1141 .LFB139: + 542:Core/Src/main.c **** + 543:Core/Src/main.c **** /** + 544:Core/Src/main.c **** * @brief TIM15 Initialization Function + 545:Core/Src/main.c **** * @param None + 546:Core/Src/main.c **** * @retval None + 547:Core/Src/main.c **** */ + 548:Core/Src/main.c **** static void MX_TIM15_Init(void) + 549:Core/Src/main.c **** { + 1142 .loc 1 549 1 + 1143 .cfi_startproc + 1144 @ args = 0, pretend = 0, frame = 88 + 1145 @ frame_needed = 1, uses_anonymous_args = 0 + 1146 0000 80B5 push {r7, lr} + 1147 .cfi_def_cfa_offset 8 + 1148 .cfi_offset 7, -8 + 1149 .cfi_offset 14, -4 + 1150 0002 96B0 sub sp, sp, #88 + 1151 .cfi_def_cfa_offset 96 + 1152 0004 00AF add r7, sp, #0 + 1153 .cfi_def_cfa_register 7 + 550:Core/Src/main.c **** + 551:Core/Src/main.c **** /* USER CODE BEGIN TIM15_Init 0 */ + 552:Core/Src/main.c **** + 553:Core/Src/main.c **** /* USER CODE END TIM15_Init 0 */ + 554:Core/Src/main.c **** + 555:Core/Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0}; + 1154 .loc 1 555 27 + 1155 0006 07F14C03 add r3, r7, #76 + 1156 000a 0022 movs r2, #0 + 1157 000c 1A60 str r2, [r3] + ARM GAS /tmp/ccSWt3lr.s page 31 + + + 1158 000e 5A60 str r2, [r3, #4] + 1159 0010 9A60 str r2, [r3, #8] + 556:Core/Src/main.c **** TIM_OC_InitTypeDef sConfigOC = {0}; + 1160 .loc 1 556 22 + 1161 0012 07F13003 add r3, r7, #48 + 1162 0016 0022 movs r2, #0 + 1163 0018 1A60 str r2, [r3] + 1164 001a 5A60 str r2, [r3, #4] + 1165 001c 9A60 str r2, [r3, #8] + 1166 001e DA60 str r2, [r3, #12] + 1167 0020 1A61 str r2, [r3, #16] + 1168 0022 5A61 str r2, [r3, #20] + 1169 0024 9A61 str r2, [r3, #24] + 557:Core/Src/main.c **** TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0}; + 1170 .loc 1 557 34 + 1171 0026 3B1D adds r3, r7, #4 + 1172 0028 2C22 movs r2, #44 + 1173 002a 0021 movs r1, #0 + 1174 002c 1846 mov r0, r3 + 1175 002e FFF7FEFF bl memset + 558:Core/Src/main.c **** + 559:Core/Src/main.c **** /* USER CODE BEGIN TIM15_Init 1 */ + 560:Core/Src/main.c **** + 561:Core/Src/main.c **** /* USER CODE END TIM15_Init 1 */ + 562:Core/Src/main.c **** htim15.Instance = TIM15; + 1176 .loc 1 562 19 + 1177 0032 3A4B ldr r3, .L63 + 1178 0034 3A4A ldr r2, .L63+4 + 1179 0036 1A60 str r2, [r3] + 563:Core/Src/main.c **** htim15.Init.Prescaler = 0; + 1180 .loc 1 563 25 + 1181 0038 384B ldr r3, .L63 + 1182 003a 0022 movs r2, #0 + 1183 003c 5A60 str r2, [r3, #4] + 564:Core/Src/main.c **** htim15.Init.CounterMode = TIM_COUNTERMODE_UP; + 1184 .loc 1 564 27 + 1185 003e 374B ldr r3, .L63 + 1186 0040 0022 movs r2, #0 + 1187 0042 9A60 str r2, [r3, #8] + 565:Core/Src/main.c **** htim15.Init.Period = 65535; + 1188 .loc 1 565 22 + 1189 0044 354B ldr r3, .L63 + 1190 0046 4FF6FF72 movw r2, #65535 + 1191 004a DA60 str r2, [r3, #12] + 566:Core/Src/main.c **** htim15.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + 1192 .loc 1 566 29 + 1193 004c 334B ldr r3, .L63 + 1194 004e 0022 movs r2, #0 + 1195 0050 1A61 str r2, [r3, #16] + 567:Core/Src/main.c **** htim15.Init.RepetitionCounter = 0; + 1196 .loc 1 567 33 + 1197 0052 324B ldr r3, .L63 + 1198 0054 0022 movs r2, #0 + 1199 0056 5A61 str r2, [r3, #20] + 568:Core/Src/main.c **** htim15.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + 1200 .loc 1 568 33 + 1201 0058 304B ldr r3, .L63 + ARM GAS /tmp/ccSWt3lr.s page 32 + + + 1202 005a 0022 movs r2, #0 + 1203 005c 9A61 str r2, [r3, #24] + 569:Core/Src/main.c **** if (HAL_TIM_PWM_Init(&htim15) != HAL_OK) + 1204 .loc 1 569 7 + 1205 005e 2F48 ldr r0, .L63 + 1206 0060 FFF7FEFF bl HAL_TIM_PWM_Init + 1207 0064 0346 mov r3, r0 + 1208 .loc 1 569 6 discriminator 1 + 1209 0066 002B cmp r3, #0 + 1210 0068 01D0 beq .L58 + 570:Core/Src/main.c **** { + 571:Core/Src/main.c **** Error_Handler(); + 1211 .loc 1 571 5 + 1212 006a FFF7FEFF bl Error_Handler + 1213 .L58: + 572:Core/Src/main.c **** } + 573:Core/Src/main.c **** sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + 1214 .loc 1 573 37 + 1215 006e 0023 movs r3, #0 + 1216 0070 FB64 str r3, [r7, #76] + 574:Core/Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + 1217 .loc 1 574 33 + 1218 0072 0023 movs r3, #0 + 1219 0074 7B65 str r3, [r7, #84] + 575:Core/Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim15, &sMasterConfig) != HAL_OK) + 1220 .loc 1 575 7 + 1221 0076 07F14C03 add r3, r7, #76 + 1222 007a 1946 mov r1, r3 + 1223 007c 2748 ldr r0, .L63 + 1224 007e FFF7FEFF bl HAL_TIMEx_MasterConfigSynchronization + 1225 0082 0346 mov r3, r0 + 1226 .loc 1 575 6 discriminator 1 + 1227 0084 002B cmp r3, #0 + 1228 0086 01D0 beq .L59 + 576:Core/Src/main.c **** { + 577:Core/Src/main.c **** Error_Handler(); + 1229 .loc 1 577 5 + 1230 0088 FFF7FEFF bl Error_Handler + 1231 .L59: + 578:Core/Src/main.c **** } + 579:Core/Src/main.c **** sConfigOC.OCMode = TIM_OCMODE_PWM1; + 1232 .loc 1 579 20 + 1233 008c 6023 movs r3, #96 + 1234 008e 3B63 str r3, [r7, #48] + 580:Core/Src/main.c **** sConfigOC.Pulse = 0; + 1235 .loc 1 580 19 + 1236 0090 0023 movs r3, #0 + 1237 0092 7B63 str r3, [r7, #52] + 581:Core/Src/main.c **** sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + 1238 .loc 1 581 24 + 1239 0094 0023 movs r3, #0 + 1240 0096 BB63 str r3, [r7, #56] + 582:Core/Src/main.c **** sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH; + 1241 .loc 1 582 25 + 1242 0098 0023 movs r3, #0 + 1243 009a FB63 str r3, [r7, #60] + 583:Core/Src/main.c **** sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + ARM GAS /tmp/ccSWt3lr.s page 33 + + + 1244 .loc 1 583 24 + 1245 009c 0023 movs r3, #0 + 1246 009e 3B64 str r3, [r7, #64] + 584:Core/Src/main.c **** sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET; + 1247 .loc 1 584 25 + 1248 00a0 0023 movs r3, #0 + 1249 00a2 7B64 str r3, [r7, #68] + 585:Core/Src/main.c **** sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET; + 1250 .loc 1 585 26 + 1251 00a4 0023 movs r3, #0 + 1252 00a6 BB64 str r3, [r7, #72] + 586:Core/Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim15, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) + 1253 .loc 1 586 7 + 1254 00a8 07F13003 add r3, r7, #48 + 1255 00ac 0022 movs r2, #0 + 1256 00ae 1946 mov r1, r3 + 1257 00b0 1A48 ldr r0, .L63 + 1258 00b2 FFF7FEFF bl HAL_TIM_PWM_ConfigChannel + 1259 00b6 0346 mov r3, r0 + 1260 .loc 1 586 6 discriminator 1 + 1261 00b8 002B cmp r3, #0 + 1262 00ba 01D0 beq .L60 + 587:Core/Src/main.c **** { + 588:Core/Src/main.c **** Error_Handler(); + 1263 .loc 1 588 5 + 1264 00bc FFF7FEFF bl Error_Handler + 1265 .L60: + 589:Core/Src/main.c **** } + 590:Core/Src/main.c **** if (HAL_TIM_PWM_ConfigChannel(&htim15, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) + 1266 .loc 1 590 7 + 1267 00c0 07F13003 add r3, r7, #48 + 1268 00c4 0422 movs r2, #4 + 1269 00c6 1946 mov r1, r3 + 1270 00c8 1448 ldr r0, .L63 + 1271 00ca FFF7FEFF bl HAL_TIM_PWM_ConfigChannel + 1272 00ce 0346 mov r3, r0 + 1273 .loc 1 590 6 discriminator 1 + 1274 00d0 002B cmp r3, #0 + 1275 00d2 01D0 beq .L61 + 591:Core/Src/main.c **** { + 592:Core/Src/main.c **** Error_Handler(); + 1276 .loc 1 592 5 + 1277 00d4 FFF7FEFF bl Error_Handler + 1278 .L61: + 593:Core/Src/main.c **** } + 594:Core/Src/main.c **** sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE; + 1279 .loc 1 594 40 + 1280 00d8 0023 movs r3, #0 + 1281 00da 7B60 str r3, [r7, #4] + 595:Core/Src/main.c **** sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE; + 1282 .loc 1 595 41 + 1283 00dc 0023 movs r3, #0 + 1284 00de BB60 str r3, [r7, #8] + 596:Core/Src/main.c **** sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF; + 1285 .loc 1 596 34 + 1286 00e0 0023 movs r3, #0 + 1287 00e2 FB60 str r3, [r7, #12] + ARM GAS /tmp/ccSWt3lr.s page 34 + + + 597:Core/Src/main.c **** sBreakDeadTimeConfig.DeadTime = 0; + 1288 .loc 1 597 33 + 1289 00e4 0023 movs r3, #0 + 1290 00e6 3B61 str r3, [r7, #16] + 598:Core/Src/main.c **** sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE; + 1291 .loc 1 598 35 + 1292 00e8 0023 movs r3, #0 + 1293 00ea 7B61 str r3, [r7, #20] + 599:Core/Src/main.c **** sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH; + 1294 .loc 1 599 38 + 1295 00ec 4FF40053 mov r3, #8192 + 1296 00f0 BB61 str r3, [r7, #24] + 600:Core/Src/main.c **** sBreakDeadTimeConfig.BreakFilter = 0; + 1297 .loc 1 600 36 + 1298 00f2 0023 movs r3, #0 + 1299 00f4 FB61 str r3, [r7, #28] + 601:Core/Src/main.c **** sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE; + 1300 .loc 1 601 40 + 1301 00f6 0023 movs r3, #0 + 1302 00f8 FB62 str r3, [r7, #44] + 602:Core/Src/main.c **** if (HAL_TIMEx_ConfigBreakDeadTime(&htim15, &sBreakDeadTimeConfig) != HAL_OK) + 1303 .loc 1 602 7 + 1304 00fa 3B1D adds r3, r7, #4 + 1305 00fc 1946 mov r1, r3 + 1306 00fe 0748 ldr r0, .L63 + 1307 0100 FFF7FEFF bl HAL_TIMEx_ConfigBreakDeadTime + 1308 0104 0346 mov r3, r0 + 1309 .loc 1 602 6 discriminator 1 + 1310 0106 002B cmp r3, #0 + 1311 0108 01D0 beq .L62 + 603:Core/Src/main.c **** { + 604:Core/Src/main.c **** Error_Handler(); + 1312 .loc 1 604 5 + 1313 010a FFF7FEFF bl Error_Handler + 1314 .L62: + 605:Core/Src/main.c **** } + 606:Core/Src/main.c **** /* USER CODE BEGIN TIM15_Init 2 */ + 607:Core/Src/main.c **** + 608:Core/Src/main.c **** /* USER CODE END TIM15_Init 2 */ + 609:Core/Src/main.c **** HAL_TIM_MspPostInit(&htim15); + 1315 .loc 1 609 3 + 1316 010e 0348 ldr r0, .L63 + 1317 0110 FFF7FEFF bl HAL_TIM_MspPostInit + 610:Core/Src/main.c **** + 611:Core/Src/main.c **** } + 1318 .loc 1 611 1 + 1319 0114 00BF nop + 1320 0116 5837 adds r7, r7, #88 + 1321 .cfi_def_cfa_offset 8 + 1322 0118 BD46 mov sp, r7 + 1323 .cfi_def_cfa_register 13 + 1324 @ sp needed + 1325 011a 80BD pop {r7, pc} + 1326 .L64: + 1327 .align 2 + 1328 .L63: + 1329 011c 00000000 .word htim15 + ARM GAS /tmp/ccSWt3lr.s page 35 + + + 1330 0120 00400140 .word 1073823744 + 1331 .cfi_endproc + 1332 .LFE139: + 1334 .section .text.MX_GPIO_Init,"ax",%progbits + 1335 .align 1 + 1336 .syntax unified + 1337 .thumb + 1338 .thumb_func + 1340 MX_GPIO_Init: + 1341 .LFB140: + 612:Core/Src/main.c **** + 613:Core/Src/main.c **** /** + 614:Core/Src/main.c **** * @brief GPIO Initialization Function + 615:Core/Src/main.c **** * @param None + 616:Core/Src/main.c **** * @retval None + 617:Core/Src/main.c **** */ + 618:Core/Src/main.c **** static void MX_GPIO_Init(void) + 619:Core/Src/main.c **** { + 1342 .loc 1 619 1 + 1343 .cfi_startproc + 1344 @ args = 0, pretend = 0, frame = 40 + 1345 @ frame_needed = 1, uses_anonymous_args = 0 + 1346 0000 80B5 push {r7, lr} + 1347 .cfi_def_cfa_offset 8 + 1348 .cfi_offset 7, -8 + 1349 .cfi_offset 14, -4 + 1350 0002 8AB0 sub sp, sp, #40 + 1351 .cfi_def_cfa_offset 48 + 1352 0004 00AF add r7, sp, #0 + 1353 .cfi_def_cfa_register 7 + 620:Core/Src/main.c **** GPIO_InitTypeDef GPIO_InitStruct = {0}; + 1354 .loc 1 620 20 + 1355 0006 07F11403 add r3, r7, #20 + 1356 000a 0022 movs r2, #0 + 1357 000c 1A60 str r2, [r3] + 1358 000e 5A60 str r2, [r3, #4] + 1359 0010 9A60 str r2, [r3, #8] + 1360 0012 DA60 str r2, [r3, #12] + 1361 0014 1A61 str r2, [r3, #16] + 1362 .LBB4: + 621:Core/Src/main.c **** /* USER CODE BEGIN MX_GPIO_Init_1 */ + 622:Core/Src/main.c **** /* USER CODE END MX_GPIO_Init_1 */ + 623:Core/Src/main.c **** + 624:Core/Src/main.c **** /* GPIO Ports Clock Enable */ + 625:Core/Src/main.c **** __HAL_RCC_GPIOC_CLK_ENABLE(); + 1363 .loc 1 625 3 + 1364 0016 424B ldr r3, .L66 + 1365 0018 5B69 ldr r3, [r3, #20] + 1366 001a 414A ldr r2, .L66 + 1367 001c 43F40023 orr r3, r3, #524288 + 1368 0020 5361 str r3, [r2, #20] + 1369 0022 3F4B ldr r3, .L66 + 1370 0024 5B69 ldr r3, [r3, #20] + 1371 0026 03F40023 and r3, r3, #524288 + 1372 002a 3B61 str r3, [r7, #16] + 1373 002c 3B69 ldr r3, [r7, #16] + 1374 .LBE4: + ARM GAS /tmp/ccSWt3lr.s page 36 + + + 1375 .LBB5: + 626:Core/Src/main.c **** __HAL_RCC_GPIOF_CLK_ENABLE(); + 1376 .loc 1 626 3 + 1377 002e 3C4B ldr r3, .L66 + 1378 0030 5B69 ldr r3, [r3, #20] + 1379 0032 3B4A ldr r2, .L66 + 1380 0034 43F48003 orr r3, r3, #4194304 + 1381 0038 5361 str r3, [r2, #20] + 1382 003a 394B ldr r3, .L66 + 1383 003c 5B69 ldr r3, [r3, #20] + 1384 003e 03F48003 and r3, r3, #4194304 + 1385 0042 FB60 str r3, [r7, #12] + 1386 0044 FB68 ldr r3, [r7, #12] + 1387 .LBE5: + 1388 .LBB6: + 627:Core/Src/main.c **** __HAL_RCC_GPIOA_CLK_ENABLE(); + 1389 .loc 1 627 3 + 1390 0046 364B ldr r3, .L66 + 1391 0048 5B69 ldr r3, [r3, #20] + 1392 004a 354A ldr r2, .L66 + 1393 004c 43F40033 orr r3, r3, #131072 + 1394 0050 5361 str r3, [r2, #20] + 1395 0052 334B ldr r3, .L66 + 1396 0054 5B69 ldr r3, [r3, #20] + 1397 0056 03F40033 and r3, r3, #131072 + 1398 005a BB60 str r3, [r7, #8] + 1399 005c BB68 ldr r3, [r7, #8] + 1400 .LBE6: + 1401 .LBB7: + 628:Core/Src/main.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); + 1402 .loc 1 628 3 + 1403 005e 304B ldr r3, .L66 + 1404 0060 5B69 ldr r3, [r3, #20] + 1405 0062 2F4A ldr r2, .L66 + 1406 0064 43F48023 orr r3, r3, #262144 + 1407 0068 5361 str r3, [r2, #20] + 1408 006a 2D4B ldr r3, .L66 + 1409 006c 5B69 ldr r3, [r3, #20] + 1410 006e 03F48023 and r3, r3, #262144 + 1411 0072 7B60 str r3, [r7, #4] + 1412 0074 7B68 ldr r3, [r7, #4] + 1413 .LBE7: + 629:Core/Src/main.c **** + 630:Core/Src/main.c **** /*Configure GPIO pin Output Level */ + 631:Core/Src/main.c **** HAL_GPIO_WritePin(GPIOA, CSB_Pin|EEPROM___WC__Pin, GPIO_PIN_RESET); + 1414 .loc 1 631 3 + 1415 0076 0022 movs r2, #0 + 1416 0078 4FF48871 mov r1, #272 + 1417 007c 4FF09040 mov r0, #1207959552 + 1418 0080 FFF7FEFF bl HAL_GPIO_WritePin + 632:Core/Src/main.c **** + 633:Core/Src/main.c **** /*Configure GPIO pin Output Level */ + 634:Core/Src/main.c **** HAL_GPIO_WritePin(GPIOB, RELAY_ENABLE_Pin|PRECHARGE_ENABLE_Pin, GPIO_PIN_RESET); + 1419 .loc 1 634 3 + 1420 0084 0022 movs r2, #0 + 1421 0086 3021 movs r1, #48 + 1422 0088 2648 ldr r0, .L66+4 + ARM GAS /tmp/ccSWt3lr.s page 37 + + + 1423 008a FFF7FEFF bl HAL_GPIO_WritePin + 635:Core/Src/main.c **** + 636:Core/Src/main.c **** /*Configure GPIO pins : PC13 PC14 PC15 */ + 637:Core/Src/main.c **** GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; + 1424 .loc 1 637 23 + 1425 008e 4FF46043 mov r3, #57344 + 1426 0092 7B61 str r3, [r7, #20] + 638:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + 1427 .loc 1 638 24 + 1428 0094 0323 movs r3, #3 + 1429 0096 BB61 str r3, [r7, #24] + 639:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 1430 .loc 1 639 24 + 1431 0098 0023 movs r3, #0 + 1432 009a FB61 str r3, [r7, #28] + 640:Core/Src/main.c **** HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + 1433 .loc 1 640 3 + 1434 009c 07F11403 add r3, r7, #20 + 1435 00a0 1946 mov r1, r3 + 1436 00a2 2148 ldr r0, .L66+8 + 1437 00a4 FFF7FEFF bl HAL_GPIO_Init + 641:Core/Src/main.c **** + 642:Core/Src/main.c **** /*Configure GPIO pins : PA0 PA1 PA2 PA3 */ + 643:Core/Src/main.c **** GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3; + 1438 .loc 1 643 23 + 1439 00a8 0F23 movs r3, #15 + 1440 00aa 7B61 str r3, [r7, #20] + 644:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + 1441 .loc 1 644 24 + 1442 00ac 0323 movs r3, #3 + 1443 00ae BB61 str r3, [r7, #24] + 645:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 1444 .loc 1 645 24 + 1445 00b0 0023 movs r3, #0 + 1446 00b2 FB61 str r3, [r7, #28] + 646:Core/Src/main.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 1447 .loc 1 646 3 + 1448 00b4 07F11403 add r3, r7, #20 + 1449 00b8 1946 mov r1, r3 + 1450 00ba 4FF09040 mov r0, #1207959552 + 1451 00be FFF7FEFF bl HAL_GPIO_Init + 647:Core/Src/main.c **** + 648:Core/Src/main.c **** /*Configure GPIO pins : CSB_Pin EEPROM___WC__Pin */ + 649:Core/Src/main.c **** GPIO_InitStruct.Pin = CSB_Pin|EEPROM___WC__Pin; + 1452 .loc 1 649 23 + 1453 00c2 4FF48873 mov r3, #272 + 1454 00c6 7B61 str r3, [r7, #20] + 650:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 1455 .loc 1 650 24 + 1456 00c8 0123 movs r3, #1 + 1457 00ca BB61 str r3, [r7, #24] + 651:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 1458 .loc 1 651 24 + 1459 00cc 0023 movs r3, #0 + 1460 00ce FB61 str r3, [r7, #28] + 652:Core/Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + 1461 .loc 1 652 25 + ARM GAS /tmp/ccSWt3lr.s page 38 + + + 1462 00d0 0323 movs r3, #3 + 1463 00d2 3B62 str r3, [r7, #32] + 653:Core/Src/main.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 1464 .loc 1 653 3 + 1465 00d4 07F11403 add r3, r7, #20 + 1466 00d8 1946 mov r1, r3 + 1467 00da 4FF09040 mov r0, #1207959552 + 1468 00de FFF7FEFF bl HAL_GPIO_Init + 654:Core/Src/main.c **** + 655:Core/Src/main.c **** /*Configure GPIO pins : PB2 PB12 PB13 */ + 656:Core/Src/main.c **** GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_12|GPIO_PIN_13; + 1469 .loc 1 656 23 + 1470 00e2 43F20403 movw r3, #12292 + 1471 00e6 7B61 str r3, [r7, #20] + 657:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + 1472 .loc 1 657 24 + 1473 00e8 0323 movs r3, #3 + 1474 00ea BB61 str r3, [r7, #24] + 658:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 1475 .loc 1 658 24 + 1476 00ec 0023 movs r3, #0 + 1477 00ee FB61 str r3, [r7, #28] + 659:Core/Src/main.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 1478 .loc 1 659 3 + 1479 00f0 07F11403 add r3, r7, #20 + 1480 00f4 1946 mov r1, r3 + 1481 00f6 0B48 ldr r0, .L66+4 + 1482 00f8 FFF7FEFF bl HAL_GPIO_Init + 660:Core/Src/main.c **** + 661:Core/Src/main.c **** /*Configure GPIO pins : RELAY_ENABLE_Pin PRECHARGE_ENABLE_Pin */ + 662:Core/Src/main.c **** GPIO_InitStruct.Pin = RELAY_ENABLE_Pin|PRECHARGE_ENABLE_Pin; + 1483 .loc 1 662 23 + 1484 00fc 3023 movs r3, #48 + 1485 00fe 7B61 str r3, [r7, #20] + 663:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 1486 .loc 1 663 24 + 1487 0100 0123 movs r3, #1 + 1488 0102 BB61 str r3, [r7, #24] + 664:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 1489 .loc 1 664 24 + 1490 0104 0023 movs r3, #0 + 1491 0106 FB61 str r3, [r7, #28] + 665:Core/Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 1492 .loc 1 665 25 + 1493 0108 0023 movs r3, #0 + 1494 010a 3B62 str r3, [r7, #32] + 666:Core/Src/main.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 1495 .loc 1 666 3 + 1496 010c 07F11403 add r3, r7, #20 + 1497 0110 1946 mov r1, r3 + 1498 0112 0448 ldr r0, .L66+4 + 1499 0114 FFF7FEFF bl HAL_GPIO_Init + 667:Core/Src/main.c **** + 668:Core/Src/main.c **** /* USER CODE BEGIN MX_GPIO_Init_2 */ + 669:Core/Src/main.c **** /* USER CODE END MX_GPIO_Init_2 */ + 670:Core/Src/main.c **** } + 1500 .loc 1 670 1 + ARM GAS /tmp/ccSWt3lr.s page 39 + + + 1501 0118 00BF nop + 1502 011a 2837 adds r7, r7, #40 + 1503 .cfi_def_cfa_offset 8 + 1504 011c BD46 mov sp, r7 + 1505 .cfi_def_cfa_register 13 + 1506 @ sp needed + 1507 011e 80BD pop {r7, pc} + 1508 .L67: + 1509 .align 2 + 1510 .L66: + 1511 0120 00100240 .word 1073876992 + 1512 0124 00040048 .word 1207960576 + 1513 0128 00080048 .word 1207961600 + 1514 .cfi_endproc + 1515 .LFE140: + 1517 .section .text.Error_Handler,"ax",%progbits + 1518 .align 1 + 1519 .global Error_Handler + 1520 .syntax unified + 1521 .thumb + 1522 .thumb_func + 1524 Error_Handler: + 1525 .LFB141: + 671:Core/Src/main.c **** + 672:Core/Src/main.c **** /* USER CODE BEGIN 4 */ + 673:Core/Src/main.c **** + 674:Core/Src/main.c **** /* USER CODE END 4 */ + 675:Core/Src/main.c **** + 676:Core/Src/main.c **** /** + 677:Core/Src/main.c **** * @brief This function is executed in case of error occurrence. + 678:Core/Src/main.c **** * @retval None + 679:Core/Src/main.c **** */ + 680:Core/Src/main.c **** void Error_Handler(void) + 681:Core/Src/main.c **** { + 1526 .loc 1 681 1 + 1527 .cfi_startproc + 1528 @ args = 0, pretend = 0, frame = 0 + 1529 @ frame_needed = 1, uses_anonymous_args = 0 + 1530 @ link register save eliminated. + 1531 0000 80B4 push {r7} + 1532 .cfi_def_cfa_offset 4 + 1533 .cfi_offset 7, -4 + 1534 0002 00AF add r7, sp, #0 + 1535 .cfi_def_cfa_register 7 + 1536 .LBB8: + 1537 .LBB9: + 1538 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h" + 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** + 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h + 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file + 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.0.4 + 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 09. April 2018 + 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ + 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* + 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 + ARM GAS /tmp/ccSWt3lr.s page 40 + + + 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may + 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. + 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at + 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 + 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software + 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT + 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and + 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. + 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 24:Drivers/CMSIS/Include/cmsis_gcc.h **** + 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H + 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H + 27:Drivers/CMSIS/Include/cmsis_gcc.h **** + 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ + 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" + 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" + 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" + 33:Drivers/CMSIS/Include/cmsis_gcc.h **** + 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ + 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin + 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) + 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 38:Drivers/CMSIS/Include/cmsis_gcc.h **** + 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ + 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM + 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm + 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE + 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline + 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE + 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline + 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE + 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline + 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN + 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) + 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED + 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) + 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK + 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) + 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED + 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) + 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT + 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION + ARM GAS /tmp/ccSWt3lr.s page 41 + + + 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) + 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ + 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE + 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- + 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ + 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add + 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE + 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- + 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ + 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add + 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED + 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) + 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT + 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict + 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 116:Drivers/CMSIS/Include/cmsis_gcc.h **** + 117:Drivers/CMSIS/Include/cmsis_gcc.h **** + 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ + 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface + 120:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + 121:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 122:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 123:Drivers/CMSIS/Include/cmsis_gcc.h **** + 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + ARM GAS /tmp/ccSWt3lr.s page 42 + + + 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts + 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + 127:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 128:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) + 130:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); + 132:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 133:Drivers/CMSIS/Include/cmsis_gcc.h **** + 134:Drivers/CMSIS/Include/cmsis_gcc.h **** + 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 136:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts + 137:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. + 138:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 139:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) + 141:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 142:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); + 1539 .loc 2 142 3 + 1540 .syntax unified + 1541 @ 142 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1542 0004 72B6 cpsid i + 1543 @ 0 "" 2 + 143:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 1544 .loc 2 143 1 + 1545 .thumb + 1546 .syntax unified + 1547 0006 00BF nop + 1548 .L69: + 1549 .LBE9: + 1550 .LBE8: + 682:Core/Src/main.c **** /* USER CODE BEGIN Error_Handler_Debug */ + 683:Core/Src/main.c **** /* User can add his own implementation to report the HAL error return state */ + 684:Core/Src/main.c **** __disable_irq(); + 685:Core/Src/main.c **** while (1) + 1551 .loc 1 685 9 + 1552 0008 00BF nop + 1553 000a FDE7 b .L69 + 1554 .cfi_endproc + 1555 .LFE141: + 1557 .text + 1558 .Letext0: + 1559 .file 3 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 1560 .file 4 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 1561 .file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + 1562 .file 6 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h" + 1563 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h" + 1564 .file 8 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h" + 1565 .file 9 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h" + 1566 .file 10 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h" + 1567 .file 11 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h" + 1568 .file 12 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h" + 1569 .file 13 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h" + 1570 .file 14 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h" + 1571 .file 15 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h" + 1572 .file 16 "Core/Inc/main.h" + 1573 .file 17 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h" + ARM GAS /tmp/ccSWt3lr.s page 43 + + + 1574 .file 18 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h" + 1575 .file 19 "Core/Inc/state_machine.h" + 1576 .file 20 "Core/Inc/AMS_HighLevel.h" + 1577 .file 21 "Core/Inc/eeprom.h" + 1578 .file 22 "Core/Inc/status_LED.h" + 1579 .file 23 "Core/Inc/soc_estimation.h" + 1580 .file 24 "Core/Inc/PWM_control.h" + 1581 .file 25 "Core/Inc/can.h" + 1582 .file 26 "Core/Inc/TMP1075.h" + 1583 .file 27 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h" + ARM GAS /tmp/ccSWt3lr.s page 44 + + +DEFINED SYMBOLS + *ABS*:00000000 main.c + /tmp/ccSWt3lr.s:25 .bss.hcan:00000000 hcan + /tmp/ccSWt3lr.s:22 .bss.hcan:00000000 $d + /tmp/ccSWt3lr.s:32 .bss.hi2c1:00000000 hi2c1 + /tmp/ccSWt3lr.s:29 .bss.hi2c1:00000000 $d + /tmp/ccSWt3lr.s:39 .bss.hi2c2:00000000 hi2c2 + /tmp/ccSWt3lr.s:36 .bss.hi2c2:00000000 $d + /tmp/ccSWt3lr.s:46 .bss.hspi1:00000000 hspi1 + /tmp/ccSWt3lr.s:43 .bss.hspi1:00000000 $d + /tmp/ccSWt3lr.s:53 .bss.htim2:00000000 htim2 + /tmp/ccSWt3lr.s:50 .bss.htim2:00000000 $d + /tmp/ccSWt3lr.s:60 .bss.htim3:00000000 htim3 + /tmp/ccSWt3lr.s:57 .bss.htim3:00000000 $d + /tmp/ccSWt3lr.s:67 .bss.htim4:00000000 htim4 + /tmp/ccSWt3lr.s:64 .bss.htim4:00000000 $d + /tmp/ccSWt3lr.s:74 .bss.htim15:00000000 htim15 + /tmp/ccSWt3lr.s:71 .bss.htim15:00000000 $d + /tmp/ccSWt3lr.s:77 .text.main:00000000 $t + /tmp/ccSWt3lr.s:83 .text.main:00000000 main + /tmp/ccSWt3lr.s:194 .text.SystemClock_Config:00000000 SystemClock_Config + /tmp/ccSWt3lr.s:1340 .text.MX_GPIO_Init:00000000 MX_GPIO_Init + /tmp/ccSWt3lr.s:315 .text.MX_CAN_Init:00000000 MX_CAN_Init + /tmp/ccSWt3lr.s:402 .text.MX_I2C1_Init:00000000 MX_I2C1_Init + /tmp/ccSWt3lr.s:598 .text.MX_SPI1_Init:00000000 MX_SPI1_Init + /tmp/ccSWt3lr.s:1140 .text.MX_TIM15_Init:00000000 MX_TIM15_Init + /tmp/ccSWt3lr.s:500 .text.MX_I2C2_Init:00000000 MX_I2C2_Init + /tmp/ccSWt3lr.s:693 .text.MX_TIM2_Init:00000000 MX_TIM2_Init + /tmp/ccSWt3lr.s:837 .text.MX_TIM3_Init:00000000 MX_TIM3_Init + /tmp/ccSWt3lr.s:982 .text.MX_TIM4_Init:00000000 MX_TIM4_Init + /tmp/ccSWt3lr.s:176 .text.main:00000094 $d + /tmp/ccSWt3lr.s:188 .text.SystemClock_Config:00000000 $t + /tmp/ccSWt3lr.s:1524 .text.Error_Handler:00000000 Error_Handler + /tmp/ccSWt3lr.s:310 .text.MX_CAN_Init:00000000 $t + /tmp/ccSWt3lr.s:391 .text.MX_CAN_Init:00000064 $d + /tmp/ccSWt3lr.s:397 .text.MX_I2C1_Init:00000000 $t + /tmp/ccSWt3lr.s:488 .text.MX_I2C1_Init:00000074 $d + /tmp/ccSWt3lr.s:495 .text.MX_I2C2_Init:00000000 $t + /tmp/ccSWt3lr.s:586 .text.MX_I2C2_Init:00000074 $d + /tmp/ccSWt3lr.s:593 .text.MX_SPI1_Init:00000000 $t + /tmp/ccSWt3lr.s:682 .text.MX_SPI1_Init:00000074 $d + /tmp/ccSWt3lr.s:688 .text.MX_TIM2_Init:00000000 $t + /tmp/ccSWt3lr.s:827 .text.MX_TIM2_Init:000000c4 $d + /tmp/ccSWt3lr.s:832 .text.MX_TIM3_Init:00000000 $t + /tmp/ccSWt3lr.s:971 .text.MX_TIM3_Init:000000c4 $d + /tmp/ccSWt3lr.s:977 .text.MX_TIM4_Init:00000000 $t + /tmp/ccSWt3lr.s:1129 .text.MX_TIM4_Init:000000d8 $d + /tmp/ccSWt3lr.s:1135 .text.MX_TIM15_Init:00000000 $t + /tmp/ccSWt3lr.s:1329 .text.MX_TIM15_Init:0000011c $d + /tmp/ccSWt3lr.s:1335 .text.MX_GPIO_Init:00000000 $t + /tmp/ccSWt3lr.s:1511 .text.MX_GPIO_Init:00000120 $d + /tmp/ccSWt3lr.s:1518 .text.Error_Handler:00000000 $t + +UNDEFINED SYMBOLS +HAL_Init +sm_init +tmp1075_init + ARM GAS /tmp/ccSWt3lr.s page 45 + + +AMS_Init +can_init +PWM_control_init +soc_init +status_led_init +sm_program_powerground +eeprom_init +AMS_Loop +HAL_GetTick +sm_update +memset +HAL_RCC_OscConfig +HAL_RCC_ClockConfig +HAL_RCCEx_PeriphCLKConfig +HAL_CAN_Init +HAL_I2C_Init +HAL_I2CEx_ConfigAnalogFilter +HAL_I2CEx_ConfigDigitalFilter +HAL_SPI_Init +HAL_TIM_PWM_Init +HAL_TIMEx_MasterConfigSynchronization +HAL_TIM_PWM_ConfigChannel +HAL_TIM_MspPostInit +HAL_TIMEx_ConfigBreakDeadTime +HAL_GPIO_WritePin +HAL_GPIO_Init diff --git a/Software/build/main.o b/Software/build/main.o new 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/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/crtn.o + +Memory Configuration + +Name Origin Length Attributes +RAM 0x20000000 0x00008000 xrw +FLASH 0x08000000 0x00020000 xr +*default* 0x00000000 0xffffffff + +Linker script and memory map + +LOAD /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/crti.o +LOAD /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/crtbegin.o +LOAD /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o +LOAD build/can-halal.o +LOAD build/ADBMS_Abstraction.o +LOAD build/ADBMS_LL_Driver.o +LOAD build/AMS_HighLevel.o +LOAD build/PWM_control.o +LOAD build/TMP1075.o +LOAD build/can.o +LOAD build/eeprom.o +LOAD build/errors.o +LOAD build/main.o +LOAD build/soc_estimation.o +LOAD build/state_machine.o +LOAD build/status_LED.o +LOAD build/stm32f3xx_hal_msp.o +LOAD build/stm32f3xx_it.o +LOAD build/syscalls.o +LOAD build/sysmem.o +LOAD build/system_stm32f3xx.o +LOAD build/stm32f3xx_hal.o +LOAD build/stm32f3xx_hal_can.o +LOAD build/stm32f3xx_hal_cortex.o +LOAD build/stm32f3xx_hal_dma.o +LOAD build/stm32f3xx_hal_exti.o +LOAD build/stm32f3xx_hal_flash.o +LOAD build/stm32f3xx_hal_flash_ex.o +LOAD build/stm32f3xx_hal_gpio.o +LOAD build/stm32f3xx_hal_i2c.o +LOAD build/stm32f3xx_hal_i2c_ex.o +LOAD build/stm32f3xx_hal_pwr.o +LOAD build/stm32f3xx_hal_pwr_ex.o +LOAD build/stm32f3xx_hal_rcc.o +LOAD build/stm32f3xx_hal_rcc_ex.o +LOAD build/stm32f3xx_hal_spi.o +LOAD build/stm32f3xx_hal_spi_ex.o +LOAD build/stm32f3xx_hal_tim.o +LOAD build/stm32f3xx_hal_tim_ex.o +LOAD build/startup_stm32f302xc.o +LOAD /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a +LOAD /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a +LOAD /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libnosys.a +START GROUP +LOAD /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/libgcc.a +LOAD /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a +END GROUP +START GROUP +LOAD /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/libgcc.a +LOAD /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a +END GROUP +LOAD /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/crtend.o +LOAD /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/crtn.o + 0x20008000 _estack = (ORIGIN (RAM) + LENGTH (RAM)) + 0x00000200 _Min_Heap_Size = 0x200 + 0x00000400 _Min_Stack_Size = 0x400 + +.isr_vector 0x08000000 0x188 + 0x08000000 . = ALIGN (0x4) + *(.isr_vector) + .isr_vector 0x08000000 0x188 build/startup_stm32f302xc.o + 0x08000000 g_pfnVectors + 0x08000188 . = ALIGN (0x4) + +.text 0x08000188 0x9b30 + 0x08000188 . = ALIGN (0x4) + *(.text) + .text 0x08000188 0x378 /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_addsubdf3.o) + 0x08000188 __aeabi_drsub + 0x08000190 __aeabi_dsub + 0x08000190 __subdf3 + 0x08000194 __adddf3 + 0x08000194 __aeabi_dadd + 0x0800040c __aeabi_ui2d + 0x0800040c __floatunsidf + 0x0800042c __floatsidf + 0x0800042c __aeabi_i2d + 0x08000450 __extendsfdf2 + 0x08000450 __aeabi_f2d + 0x08000494 __aeabi_ul2d + 0x08000494 __floatundidf + 0x080004a4 __floatdidf + 0x080004a4 __aeabi_l2d + .text 0x08000500 0x424 /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_muldivdf3.o) + 0x08000500 __aeabi_dmul + 0x08000500 __muldf3 + 0x08000754 __aeabi_ddiv + 0x08000754 __divdf3 + .text 0x08000924 0x50 /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_fixdfsi.o) + 0x08000924 __fixdfsi + 0x08000924 __aeabi_d2iz + .text 0x08000974 0x40 /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_fixunsdfsi.o) + 0x08000974 __fixunsdfsi + 0x08000974 __aeabi_d2uiz + .text 0x080009b4 0xa0 /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_truncdfsf2.o) + 0x080009b4 __aeabi_d2f + 0x080009b4 __truncdfsf2 + *(.text*) + .text.deregister_tm_clones + 0x08000a54 0x1c /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/crtbegin.o + .text.register_tm_clones + 0x08000a70 0x24 /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/crtbegin.o + .text.__do_global_dtors_aux + 0x08000a94 0x28 /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/crtbegin.o + .text.frame_dummy + 0x08000abc 0x24 /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/crtbegin.o + .text.ftcan_init + 0x08000ae0 0x40 build/can-halal.o + 0x08000ae0 ftcan_init + .text.ftcan_transmit + 0x08000b20 0x48 build/can-halal.o + 0x08000b20 ftcan_transmit + .text.ftcan_add_filter + 0x08000b68 0xb8 build/can-halal.o + 0x08000b68 ftcan_add_filter + .text.HAL_CAN_RxFifo0MsgPendingCallback + 0x08000c20 0x58 build/can-halal.o + 0x08000c20 HAL_CAN_RxFifo0MsgPendingCallback + .text.ftcan_marshal_unsigned + 0x08000c78 0x5e build/can-halal.o + 0x08000c78 ftcan_marshal_unsigned + *fill* 0x08000cd6 0x2 + .text.amsReset + 0x08000cd8 0xb8 build/ADBMS_Abstraction.o + 0x08000cd8 amsReset + .text.initAMS 0x08000d90 0x38 build/ADBMS_Abstraction.o + 0x08000d90 initAMS + .text.amsWakeUp + 0x08000dc8 0x1c build/ADBMS_Abstraction.o + 0x08000dc8 amsWakeUp + .text.amsCellMeasurement + 0x08000de4 0x18 build/ADBMS_Abstraction.o + 0x08000de4 amsCellMeasurement + *fill* 0x08000dfc 0x4 + .text.amsAuxAndStatusMeasurement + 0x08000e00 0x690 build/ADBMS_Abstraction.o + 0x08000e00 amsAuxAndStatusMeasurement + .text.amsConfigBalancing + 0x08001490 0x238 build/ADBMS_Abstraction.o + 0x08001490 amsConfigBalancing + .text.amsStartBalancing + 0x080016c8 0x1e build/ADBMS_Abstraction.o + 0x080016c8 amsStartBalancing + .text.amsStopBalancing + 0x080016e6 0x14 build/ADBMS_Abstraction.o + 0x080016e6 amsStopBalancing + .text.amsConfigOverUnderVoltage + 0x080016fa 0xaa build/ADBMS_Abstraction.o + 0x080016fa amsConfigOverUnderVoltage + .text.amsCheckUnderOverVoltage + 0x080017a4 0xa4 build/ADBMS_Abstraction.o + 0x080017a4 amsCheckUnderOverVoltage + .text.amsReadCellVoltages + 0x08001848 0x538 build/ADBMS_Abstraction.o + 0x08001848 amsReadCellVoltages + .text.adbmsDriverInit + 0x08001d80 0x2c build/ADBMS_LL_Driver.o + 0x08001d80 adbmsDriverInit + .text.calculateCommandPEC + 0x08001dac 0x92 build/ADBMS_LL_Driver.o + 0x08001dac calculateCommandPEC + .text.updateCommandPEC + 0x08001e3e 0x206 build/ADBMS_LL_Driver.o + 0x08001e3e updateCommandPEC + .text.pec10_calc + 0x08002044 0xd8 build/ADBMS_LL_Driver.o + 0x08002044 pec10_calc + .text.calculateDataPEC + 0x0800211c 0x56 build/ADBMS_LL_Driver.o + 0x0800211c calculateDataPEC + .text.checkDataPEC + 0x08002172 0x3a build/ADBMS_LL_Driver.o + 0x08002172 checkDataPEC + .text.F_CRC_ObtenValorDeTabla + 0x080021ac 0x5c build/ADBMS_LL_Driver.o + .text.F_CRC_CalculaCheckSum + 0x08002208 0x70 build/ADBMS_LL_Driver.o + 0x08002208 F_CRC_CalculaCheckSum + .text.writeCMD + 0x08002278 0x11a build/ADBMS_LL_Driver.o + 0x08002278 writeCMD + .text.readCMD 0x08002392 0x15a build/ADBMS_LL_Driver.o + 0x08002392 readCMD + .text.pollCMD 0x080024ec 0x6a build/ADBMS_LL_Driver.o + 0x080024ec pollCMD + .text.mcuAdbmsCSLow + 0x08002556 0x14 build/ADBMS_LL_Driver.o + 0x08002556 mcuAdbmsCSLow + .text.mcuAdbmsCSHigh + 0x0800256a 0x14 build/ADBMS_LL_Driver.o + 0x0800256a mcuAdbmsCSHigh + *fill* 0x0800257e 0x2 + .text.mcuSPITransmit + 0x08002580 0xa4 build/ADBMS_LL_Driver.o + 0x08002580 mcuSPITransmit + .text.mcuSPITransmitReceive + 0x08002624 0x34 build/ADBMS_LL_Driver.o + 0x08002624 mcuSPITransmitReceive + .text.mcuDelay + 0x08002658 0x1a build/ADBMS_LL_Driver.o + 0x08002658 mcuDelay + *fill* 0x08002672 0x2 + .text.AMS_Init + 0x08002674 0x64 build/AMS_HighLevel.o + 0x08002674 AMS_Init + .text.AMS_Loop + 0x080026d8 0x98 build/AMS_HighLevel.o + 0x080026d8 AMS_Loop + .text.AMS_Idle_Loop + 0x08002770 0x280 build/AMS_HighLevel.o + 0x08002770 AMS_Idle_Loop + .text.AMS_Warning_Loop + 0x080029f0 0x10 build/AMS_HighLevel.o + 0x080029f0 AMS_Warning_Loop + .text.AMS_Balancing_Loop + 0x08002a00 0xac build/AMS_HighLevel.o + 0x08002a00 AMS_Balancing_Loop + .text.PWM_control_init + 0x08002aac 0x74 build/PWM_control.o + 0x08002aac PWM_control_init + .text.PWM_powerground_control + 0x08002b20 0x7c build/PWM_control.o + 0x08002b20 PWM_powerground_control + .text.PWM_powerground_softcontrol + 0x08002b9c 0x44 build/PWM_control.o + 0x08002b9c PWM_powerground_softcontrol + .text.tmp1075_init + 0x08002be0 0x44 build/TMP1075.o + 0x08002be0 tmp1075_init + .text.handle_over_maxtemp + 0x08002c24 0x50 build/TMP1075.o + 0x08002c24 handle_over_maxtemp + .text.tmp1075_measure + 0x08002c74 0x1ac build/TMP1075.o + 0x08002c74 tmp1075_measure + .text.tmp1075_sensor_init + 0x08002e20 0x40 build/TMP1075.o + 0x08002e20 tmp1075_sensor_init + .text.tmp1075_sensor_read + 0x08002e60 0x64 build/TMP1075.o + 0x08002e60 tmp1075_sensor_read + .text.can_init + 0x08002ec4 0x74 build/can.o + 0x08002ec4 can_init + .text.can_handle_send_status + 0x08002f38 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build/main.o + .text.MX_TIM2_Init + 0x08003674 0xc8 build/main.o + .text.MX_TIM3_Init + 0x0800373c 0xcc build/main.o + .text.MX_TIM4_Init + 0x08003808 0xe0 build/main.o + .text.MX_TIM15_Init + 0x080038e8 0x124 build/main.o + .text.MX_GPIO_Init + 0x08003a0c 0x12c build/main.o + .text.Error_Handler + 0x08003b38 0xc build/main.o + 0x08003b38 Error_Handler + .text.soc_init + 0x08003b44 0x30 build/soc_estimation.o + 0x08003b44 soc_init + .text.soc_update + 0x08003b74 0x100 build/soc_estimation.o + 0x08003b74 soc_update + .text.soc_for_ocv + 0x08003c74 0xe4 build/soc_estimation.o + 0x08003c74 soc_for_ocv + .text.sm_init 0x08003d58 0x88 build/state_machine.o + 0x08003d58 sm_init + .text.sm_update + 0x08003de0 0x1d0 build/state_machine.o + 0x08003de0 sm_update + .text.sm_handle_ams_in + 0x08003fb0 0x10c build/state_machine.o + 0x08003fb0 sm_handle_ams_in + .text.sm_precharge_discharge_manager + 0x080040bc 0xdc build/state_machine.o + 0x080040bc sm_precharge_discharge_manager + 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build/stm32f3xx_it.o + 0x08005050 UsageFault_Handler + .text.SVC_Handler + 0x08005058 0xe build/stm32f3xx_it.o + 0x08005058 SVC_Handler + .text.DebugMon_Handler + 0x08005066 0xe build/stm32f3xx_it.o + 0x08005066 DebugMon_Handler + .text.PendSV_Handler + 0x08005074 0xe build/stm32f3xx_it.o + 0x08005074 PendSV_Handler + .text.SysTick_Handler + 0x08005082 0xc build/stm32f3xx_it.o + 0x08005082 SysTick_Handler + *fill* 0x0800508e 0x2 + .text.USB_LP_CAN_RX0_IRQHandler + 0x08005090 0x14 build/stm32f3xx_it.o + 0x08005090 USB_LP_CAN_RX0_IRQHandler + .text.CAN_RX1_IRQHandler + 0x080050a4 0x14 build/stm32f3xx_it.o + 0x080050a4 CAN_RX1_IRQHandler + .text.SystemInit + 0x080050b8 0x24 build/system_stm32f3xx.o + 0x080050b8 SystemInit + .text.HAL_Init + 0x080050dc 0x2c build/stm32f3xx_hal.o + 0x080050dc HAL_Init + .text.HAL_InitTick + 0x08005108 0x60 build/stm32f3xx_hal.o + 0x08005108 HAL_InitTick + .text.HAL_IncTick + 0x08005168 0x28 build/stm32f3xx_hal.o + 0x08005168 HAL_IncTick + .text.HAL_GetTick + 0x08005190 0x18 build/stm32f3xx_hal.o + 0x08005190 HAL_GetTick + .text.HAL_Delay + 0x080051a8 0x48 build/stm32f3xx_hal.o + 0x080051a8 HAL_Delay + .text.HAL_CAN_Init + 0x080051f0 0x1f6 build/stm32f3xx_hal_can.o + 0x080051f0 HAL_CAN_Init + .text.HAL_CAN_ConfigFilter + 0x080053e6 0x194 build/stm32f3xx_hal_can.o + 0x080053e6 HAL_CAN_ConfigFilter + .text.HAL_CAN_Start + 0x0800557a 0x88 build/stm32f3xx_hal_can.o + 0x0800557a HAL_CAN_Start + .text.HAL_CAN_AddTxMessage + 0x08005602 0x1a0 build/stm32f3xx_hal_can.o + 0x08005602 HAL_CAN_AddTxMessage + .text.HAL_CAN_GetRxMessage + 0x080057a2 0x244 build/stm32f3xx_hal_can.o + 0x080057a2 HAL_CAN_GetRxMessage + .text.HAL_CAN_ActivateNotification + 0x080059e6 0x4c build/stm32f3xx_hal_can.o + 0x080059e6 HAL_CAN_ActivateNotification + .text.HAL_CAN_IRQHandler + 0x08005a32 0x36e build/stm32f3xx_hal_can.o + 0x08005a32 HAL_CAN_IRQHandler + .text.HAL_CAN_TxMailbox0CompleteCallback + 0x08005da0 0x14 build/stm32f3xx_hal_can.o + 0x08005da0 HAL_CAN_TxMailbox0CompleteCallback + .text.HAL_CAN_TxMailbox1CompleteCallback + 0x08005db4 0x14 build/stm32f3xx_hal_can.o + 0x08005db4 HAL_CAN_TxMailbox1CompleteCallback + .text.HAL_CAN_TxMailbox2CompleteCallback + 0x08005dc8 0x14 build/stm32f3xx_hal_can.o + 0x08005dc8 HAL_CAN_TxMailbox2CompleteCallback + .text.HAL_CAN_TxMailbox0AbortCallback + 0x08005ddc 0x14 build/stm32f3xx_hal_can.o + 0x08005ddc HAL_CAN_TxMailbox0AbortCallback + .text.HAL_CAN_TxMailbox1AbortCallback + 0x08005df0 0x14 build/stm32f3xx_hal_can.o + 0x08005df0 HAL_CAN_TxMailbox1AbortCallback + .text.HAL_CAN_TxMailbox2AbortCallback + 0x08005e04 0x14 build/stm32f3xx_hal_can.o + 0x08005e04 HAL_CAN_TxMailbox2AbortCallback + .text.HAL_CAN_RxFifo0FullCallback + 0x08005e18 0x14 build/stm32f3xx_hal_can.o + 0x08005e18 HAL_CAN_RxFifo0FullCallback + .text.HAL_CAN_RxFifo1MsgPendingCallback + 0x08005e2c 0x14 build/stm32f3xx_hal_can.o + 0x08005e2c HAL_CAN_RxFifo1MsgPendingCallback + .text.HAL_CAN_RxFifo1FullCallback + 0x08005e40 0x14 build/stm32f3xx_hal_can.o + 0x08005e40 HAL_CAN_RxFifo1FullCallback + .text.HAL_CAN_SleepCallback + 0x08005e54 0x14 build/stm32f3xx_hal_can.o + 0x08005e54 HAL_CAN_SleepCallback + .text.HAL_CAN_WakeUpFromRxMsgCallback + 0x08005e68 0x14 build/stm32f3xx_hal_can.o + 0x08005e68 HAL_CAN_WakeUpFromRxMsgCallback + .text.HAL_CAN_ErrorCallback + 0x08005e7c 0x14 build/stm32f3xx_hal_can.o + 0x08005e7c HAL_CAN_ErrorCallback + .text.__NVIC_SetPriorityGrouping + 0x08005e90 0x48 build/stm32f3xx_hal_cortex.o + .text.__NVIC_GetPriorityGrouping + 0x08005ed8 0x1c build/stm32f3xx_hal_cortex.o + .text.__NVIC_EnableIRQ + 0x08005ef4 0x3c build/stm32f3xx_hal_cortex.o + .text.__NVIC_SetPriority + 0x08005f30 0x54 build/stm32f3xx_hal_cortex.o + .text.NVIC_EncodePriority + 0x08005f84 0x66 build/stm32f3xx_hal_cortex.o + *fill* 0x08005fea 0x2 + .text.SysTick_Config + 0x08005fec 0x44 build/stm32f3xx_hal_cortex.o + .text.HAL_NVIC_SetPriorityGrouping + 0x08006030 0x16 build/stm32f3xx_hal_cortex.o + 0x08006030 HAL_NVIC_SetPriorityGrouping + .text.HAL_NVIC_SetPriority + 0x08006046 0x38 build/stm32f3xx_hal_cortex.o + 0x08006046 HAL_NVIC_SetPriority + .text.HAL_NVIC_EnableIRQ + 0x0800607e 0x1c build/stm32f3xx_hal_cortex.o + 0x0800607e HAL_NVIC_EnableIRQ + .text.HAL_SYSTICK_Config + 0x0800609a 0x18 build/stm32f3xx_hal_cortex.o + 0x0800609a HAL_SYSTICK_Config + *fill* 0x080060b2 0x2 + .text.HAL_GPIO_Init + 0x080060b4 0x2f4 build/stm32f3xx_hal_gpio.o + 0x080060b4 HAL_GPIO_Init + .text.HAL_GPIO_WritePin + 0x080063a8 0x30 build/stm32f3xx_hal_gpio.o + 0x080063a8 HAL_GPIO_WritePin + .text.HAL_I2C_Init + 0x080063d8 0x11e build/stm32f3xx_hal_i2c.o + 0x080063d8 HAL_I2C_Init + *fill* 0x080064f6 0x2 + .text.HAL_I2C_Master_Transmit + 0x080064f8 0x1e8 build/stm32f3xx_hal_i2c.o + 0x080064f8 HAL_I2C_Master_Transmit + .text.HAL_I2C_Master_Receive + 0x080066e0 0x1ec build/stm32f3xx_hal_i2c.o + 0x080066e0 HAL_I2C_Master_Receive + .text.I2C_Flush_TXDR + 0x080068cc 0x48 build/stm32f3xx_hal_i2c.o + .text.I2C_WaitOnFlagUntilTimeout + 0x08006914 0x9e build/stm32f3xx_hal_i2c.o + .text.I2C_WaitOnTXISFlagUntilTimeout + 0x080069b2 0x8e build/stm32f3xx_hal_i2c.o + .text.I2C_WaitOnSTOPFlagUntilTimeout + 0x08006a40 0x86 build/stm32f3xx_hal_i2c.o + *fill* 0x08006ac6 0x2 + .text.I2C_WaitOnRXNEFlagUntilTimeout + 0x08006ac8 0x104 build/stm32f3xx_hal_i2c.o + .text.I2C_IsErrorOccurred + 0x08006bcc 0x1c0 build/stm32f3xx_hal_i2c.o + .text.I2C_TransferConfig + 0x08006d8c 0x64 build/stm32f3xx_hal_i2c.o + .text.HAL_I2CEx_ConfigAnalogFilter + 0x08006df0 0x96 build/stm32f3xx_hal_i2c_ex.o + 0x08006df0 HAL_I2CEx_ConfigAnalogFilter + .text.HAL_I2CEx_ConfigDigitalFilter + 0x08006e86 0x98 build/stm32f3xx_hal_i2c_ex.o + 0x08006e86 HAL_I2CEx_ConfigDigitalFilter + *fill* 0x08006f1e 0x2 + .text.HAL_RCC_OscConfig + 0x08006f20 0x101c build/stm32f3xx_hal_rcc.o + 0x08006f20 HAL_RCC_OscConfig + .text.HAL_RCC_ClockConfig + 0x08007f3c 0x2dc build/stm32f3xx_hal_rcc.o + 0x08007f3c HAL_RCC_ClockConfig + .text.HAL_RCC_GetSysClockFreq + 0x08008218 0xd8 build/stm32f3xx_hal_rcc.o + 0x08008218 HAL_RCC_GetSysClockFreq + .text.HAL_RCCEx_PeriphCLKConfig + 0x080082f0 0x320 build/stm32f3xx_hal_rcc_ex.o + 0x080082f0 HAL_RCCEx_PeriphCLKConfig + .text.HAL_SPI_Init + 0x08008610 0x156 build/stm32f3xx_hal_spi.o + 0x08008610 HAL_SPI_Init + .text.HAL_SPI_TransmitReceive + 0x08008766 0x444 build/stm32f3xx_hal_spi.o + 0x08008766 HAL_SPI_TransmitReceive + *fill* 0x08008baa 0x2 + .text.SPI_WaitFlagStateUntilTimeout + 0x08008bac 0x110 build/stm32f3xx_hal_spi.o + .text.SPI_WaitFifoStateUntilTimeout + 0x08008cbc 0x12c build/stm32f3xx_hal_spi.o + .text.SPI_EndRxTxTransaction + 0x08008de8 0x8c build/stm32f3xx_hal_spi.o + .text.HAL_TIM_PWM_Init + 0x08008e74 0xae build/stm32f3xx_hal_tim.o + 0x08008e74 HAL_TIM_PWM_Init + *fill* 0x08008f22 0x2 + .text.HAL_TIM_PWM_Start + 0x08008f24 0x1e8 build/stm32f3xx_hal_tim.o + 0x08008f24 HAL_TIM_PWM_Start + .text.HAL_TIM_PWM_ConfigChannel + 0x0800910c 0x228 build/stm32f3xx_hal_tim.o + 0x0800910c HAL_TIM_PWM_ConfigChannel + .text.TIM_Base_SetConfig + 0x08009334 0x104 build/stm32f3xx_hal_tim.o + 0x08009334 TIM_Base_SetConfig + .text.TIM_OC1_SetConfig + 0x08009438 0x10c build/stm32f3xx_hal_tim.o + .text.TIM_OC2_SetConfig + 0x08009544 0x100 build/stm32f3xx_hal_tim.o + 0x08009544 TIM_OC2_SetConfig + .text.TIM_OC3_SetConfig + 0x08009644 0xfc build/stm32f3xx_hal_tim.o + .text.TIM_OC4_SetConfig + 0x08009740 0xc8 build/stm32f3xx_hal_tim.o + .text.TIM_OC5_SetConfig + 0x08009808 0xbc build/stm32f3xx_hal_tim.o + .text.TIM_OC6_SetConfig + 0x080098c4 0xc0 build/stm32f3xx_hal_tim.o + .text.TIM_CCxChannelCmd + 0x08009984 0x4a build/stm32f3xx_hal_tim.o + 0x08009984 TIM_CCxChannelCmd + *fill* 0x080099ce 0x2 + .text.HAL_TIMEx_MasterConfigSynchronization + 0x080099d0 0xe8 build/stm32f3xx_hal_tim_ex.o + 0x080099d0 HAL_TIMEx_MasterConfigSynchronization + .text.HAL_TIMEx_ConfigBreakDeadTime + 0x08009ab8 0xf0 build/stm32f3xx_hal_tim_ex.o + 0x08009ab8 HAL_TIMEx_ConfigBreakDeadTime + .text.Reset_Handler + 0x08009ba8 0x50 build/startup_stm32f302xc.o + 0x08009ba8 Reset_Handler + .text.Default_Handler + 0x08009bf8 0x2 build/startup_stm32f302xc.o + 0x08009bf8 RTC_Alarm_IRQHandler + 0x08009bf8 TIM1_CC_IRQHandler + 0x08009bf8 USB_HP_IRQHandler + 0x08009bf8 PVD_IRQHandler + 0x08009bf8 TAMP_STAMP_IRQHandler + 0x08009bf8 EXTI3_IRQHandler + 0x08009bf8 USB_HP_CAN_TX_IRQHandler + 0x08009bf8 EXTI0_IRQHandler + 0x08009bf8 I2C2_EV_IRQHandler + 0x08009bf8 FPU_IRQHandler + 0x08009bf8 TIM1_UP_TIM16_IRQHandler + 0x08009bf8 ADC1_2_IRQHandler + 0x08009bf8 SPI1_IRQHandler + 0x08009bf8 CAN_SCE_IRQHandler + 0x08009bf8 TIM6_DAC_IRQHandler + 0x08009bf8 DMA2_Channel2_IRQHandler + 0x08009bf8 DMA1_Channel4_IRQHandler + 0x08009bf8 USART3_IRQHandler + 0x08009bf8 DMA1_Channel7_IRQHandler + 0x08009bf8 UART5_IRQHandler + 0x08009bf8 TIM4_IRQHandler + 0x08009bf8 DMA2_Channel1_IRQHandler + 0x08009bf8 I2C1_EV_IRQHandler + 0x08009bf8 DMA1_Channel6_IRQHandler + 0x08009bf8 UART4_IRQHandler + 0x08009bf8 DMA2_Channel4_IRQHandler + 0x08009bf8 TIM3_IRQHandler + 0x08009bf8 RCC_IRQHandler + 0x08009bf8 DMA1_Channel1_IRQHandler + 0x08009bf8 Default_Handler + 0x08009bf8 USBWakeUp_RMP_IRQHandler + 0x08009bf8 EXTI15_10_IRQHandler + 0x08009bf8 EXTI9_5_IRQHandler + 0x08009bf8 RTC_WKUP_IRQHandler + 0x08009bf8 SPI2_IRQHandler + 0x08009bf8 DMA2_Channel5_IRQHandler + 0x08009bf8 DMA1_Channel5_IRQHandler + 0x08009bf8 USB_LP_IRQHandler + 0x08009bf8 EXTI4_IRQHandler + 0x08009bf8 COMP1_2_IRQHandler + 0x08009bf8 TIM1_TRG_COM_TIM17_IRQHandler + 0x08009bf8 DMA1_Channel3_IRQHandler + 0x08009bf8 WWDG_IRQHandler + 0x08009bf8 TIM2_IRQHandler + 0x08009bf8 EXTI1_IRQHandler + 0x08009bf8 COMP4_6_IRQHandler + 0x08009bf8 USART2_IRQHandler + 0x08009bf8 I2C2_ER_IRQHandler + 0x08009bf8 DMA1_Channel2_IRQHandler + 0x08009bf8 FLASH_IRQHandler + 0x08009bf8 USART1_IRQHandler + 0x08009bf8 SPI3_IRQHandler + 0x08009bf8 I2C1_ER_IRQHandler + 0x08009bf8 USBWakeUp_IRQHandler + 0x08009bf8 DMA2_Channel3_IRQHandler + 0x08009bf8 EXTI2_TSC_IRQHandler + 0x08009bf8 TIM1_BRK_TIM15_IRQHandler + *fill* 0x08009bfa 0x2 + .text.__libc_init_array + 0x08009bfc 0x48 /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-init.o) + 0x08009bfc __libc_init_array + .text.memset 0x08009c44 0x10 /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-memset.o) + 0x08009c44 memset + .text.roundf 0x08009c54 0x4c /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(libm_a-sf_round.o) + 0x08009c54 roundf + *(.glue_7) + .glue_7 0x08009ca0 0x0 linker stubs + *(.glue_7t) + .glue_7t 0x08009ca0 0x0 linker stubs + *(.eh_frame) + .eh_frame 0x08009ca0 0x0 /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/crtbegin.o + *(.init) + .init 0x08009ca0 0x4 /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/crti.o + 0x08009ca0 _init + .init 0x08009ca4 0x8 /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/crtn.o + *(.fini) + .fini 0x08009cac 0x4 /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/crti.o + 0x08009cac _fini + .fini 0x08009cb0 0x8 /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/crtn.o + 0x08009cb8 . = ALIGN (0x4) + 0x08009cb8 _etext = . + +.vfp11_veneer 0x08009cb8 0x0 + .vfp11_veneer 0x08009cb8 0x0 linker stubs + +.v4_bx 0x08009cb8 0x0 + .v4_bx 0x08009cb8 0x0 linker stubs + +.iplt 0x08009cb8 0x0 + .iplt 0x08009cb8 0x0 /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/crtbegin.o + +.rodata 0x08009cb8 0x38 + 0x08009cb8 . = ALIGN (0x4) + *(.rodata) + .rodata 0x08009cb8 0x6 build/ADBMS_Abstraction.o + *(.rodata*) + *fill* 0x08009cbe 0x2 + .rodata.AHBPrescTable + 0x08009cc0 0x10 build/system_stm32f3xx.o + 0x08009cc0 AHBPrescTable + .rodata.aPLLMULFactorTable + 0x08009cd0 0x10 build/stm32f3xx_hal_rcc.o + .rodata.aPredivFactorTable + 0x08009ce0 0x10 build/stm32f3xx_hal_rcc.o + 0x08009cf0 . = ALIGN (0x4) + +.rel.dyn 0x08009cf0 0x0 + .rel.iplt 0x08009cf0 0x0 /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/crtbegin.o + +.ARM.extab + *(.ARM.extab* .gnu.linkonce.armextab.*) + +.ARM 0x08009cf0 0x0 + 0x08009cf0 __exidx_start = . + *(.ARM.exidx*) + 0x08009cf0 __exidx_end = . + +.preinit_array 0x08009cf0 0x0 + 0x08009cf0 PROVIDE (__preinit_array_start = .) + *(.preinit_array*) + 0x08009cf0 PROVIDE (__preinit_array_end = .) + +.init_array 0x08009cf0 0x4 + 0x08009cf0 PROVIDE (__init_array_start = .) + *(SORT_BY_NAME(.init_array.*)) + *(.init_array*) + .init_array 0x08009cf0 0x4 /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/crtbegin.o + 0x08009cf4 PROVIDE (__init_array_end = .) + +.fini_array 0x08009cf4 0x4 + [!provide] PROVIDE (__fini_array_start = .) + *(SORT_BY_NAME(.fini_array.*)) + *(.fini_array*) + .fini_array 0x08009cf4 0x4 /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/crtbegin.o + [!provide] PROVIDE (__fini_array_end = .) + 0x08009cf8 _sidata = LOADADDR (.data) + +.data 0x20000000 0x68 load address 0x08009cf8 + 0x20000000 . = ALIGN (0x4) + 0x20000000 _sdata = . + *(.data) + *(.data*) + .data.numberofCells + 0x20000000 0x1 build/AMS_HighLevel.o + 0x20000000 numberofCells + *fill* 0x20000001 0x3 + .data.OCV_SOC_PAIRS + 0x20000004 0x58 build/soc_estimation.o + 0x20000004 OCV_SOC_PAIRS + .data.SystemCoreClock + 0x2000005c 0x4 build/system_stm32f3xx.o + 0x2000005c SystemCoreClock + .data.uwTickPrio + 0x20000060 0x4 build/stm32f3xx_hal.o + 0x20000060 uwTickPrio + .data.uwTickFreq + 0x20000064 0x1 build/stm32f3xx_hal.o + 0x20000064 uwTickFreq + 0x20000068 . = ALIGN (0x4) + *fill* 0x20000065 0x3 + 0x20000068 _edata = . + +.tm_clone_table + 0x20000068 0x0 load address 0x08009d60 + .tm_clone_table + 0x20000068 0x0 /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/crtbegin.o + .tm_clone_table + 0x20000068 0x0 /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/crtend.o + +.igot.plt 0x20000068 0x0 load address 0x08009d60 + .igot.plt 0x20000068 0x0 /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/crtbegin.o + 0x20000068 . = ALIGN (0x4) + +.bss 0x20000068 0x424 load address 0x08009d60 + 0x20000068 _sbss = . + 0x20000068 __bss_start__ = _sbss + *(.bss) + *(.bss*) + .bss.completed.1 + 0x20000068 0x1 /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/crtbegin.o + *fill* 0x20000069 0x3 + .bss.object.0 0x2000006c 0x18 /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/crtbegin.o + .bss.hcan 0x20000084 0x4 build/can-halal.o + .bss.header.2 0x20000088 0x18 build/can-halal.o + .bss.next_filter_no.1 + 0x200000a0 0x4 build/can-halal.o + .bss.filter.0 0x200000a4 0x28 build/can-halal.o + .bss.numberofcells + 0x200000cc 0x1 build/ADBMS_Abstraction.o + 0x200000cc numberofcells + .bss.numberofauxchannels + 0x200000cd 0x1 build/ADBMS_Abstraction.o + 0x200000cd numberofauxchannels + *fill* 0x200000ce 0x2 + .bss.adbmsspi 0x200000d0 0x4 build/ADBMS_LL_Driver.o + 0x200000d0 adbmsspi + .bss.module 0x200000d4 0x74 build/AMS_HighLevel.o + 0x200000d4 module + .bss.balancingActive + 0x20000148 0x1 build/AMS_HighLevel.o + 0x20000148 balancingActive + *fill* 0x20000149 0x1 + .bss.amsuv 0x2000014a 0x2 build/AMS_HighLevel.o + 0x2000014a amsuv + .bss.amsov 0x2000014c 0x2 build/AMS_HighLevel.o + 0x2000014c amsov + .bss.numberofAux + 0x2000014e 0x1 build/AMS_HighLevel.o + 0x2000014e numberofAux + .bss.packetChecksumFails + 0x2000014f 0x1 build/AMS_HighLevel.o + 0x2000014f packetChecksumFails + .bss.deviceSleeps + 0x20000150 0x1 build/AMS_HighLevel.o + 0x20000150 deviceSleeps + .bss.currentAMSState + 0x20000151 0x1 build/AMS_HighLevel.o + 0x20000151 currentAMSState + .bss.lastAMSState + 0x20000152 0x1 build/AMS_HighLevel.o + 0x20000152 lastAMSState + *fill* 0x20000153 0x1 + .bss.pollingTimes + 0x20000154 0x8 build/AMS_HighLevel.o + 0x20000154 pollingTimes + .bss.powerground + 0x2000015c 0x4 build/PWM_control.o + 0x2000015c powerground + .bss.battery_cooling + 0x20000160 0x4 build/PWM_control.o + 0x20000160 battery_cooling + .bss.esc_cooling + 0x20000164 0x4 build/PWM_control.o + 0x20000164 esc_cooling + .bss.tmp1075_temps + 0x20000168 0x1a build/TMP1075.o + 0x20000168 tmp1075_temps + *fill* 0x20000182 0x2 + .bss.tmp1075_failed_sensors + 0x20000184 0x4 build/TMP1075.o + 0x20000184 tmp1075_failed_sensors + .bss.nfailed_temp_sensors + 0x20000188 0x1 build/TMP1075.o + 0x20000188 nfailed_temp_sensors + *fill* 0x20000189 0x3 + .bss.hi2c 0x2000018c 0x4 build/TMP1075.o + 0x2000018c hi2c + .bss.id_to_log + 0x20000190 0x1 build/can.o + 0x20000190 id_to_log + *fill* 0x20000191 0x3 + .bss.last_message + 0x20000194 0x8 build/can.o + 0x20000194 last_message + .bss.can_status_timer + 0x2000019c 0x4 build/can.o + 0x2000019c can_status_timer + .bss.can_log_timer + 0x200001a0 0x4 build/can.o + 0x200001a0 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build/soc_estimation.o + 0x20000428 current_was_flowing + .bss.last_current_time + 0x2000042c 0x4 build/soc_estimation.o + 0x2000042c last_current_time + .bss.soc_before_current + 0x20000430 0x4 build/soc_estimation.o + 0x20000430 soc_before_current + .bss.mAs_before_current + 0x20000434 0x4 build/soc_estimation.o + 0x20000434 mAs_before_current + .bss.programming_mode + 0x20000438 0x1 build/state_machine.o + 0x20000438 programming_mode + .bss.debugging_mode + 0x20000439 0x1 build/state_machine.o + 0x20000439 debugging_mode + *fill* 0x2000043a 0x2 + .bss.state 0x2000043c 0x6 build/state_machine.o + 0x2000043c state + *fill* 0x20000442 0x2 + .bss.RELAY_BAT_SIDE_VOLTAGE + 0x20000444 0x4 build/state_machine.o + 0x20000444 RELAY_BAT_SIDE_VOLTAGE + .bss.RELAY_ESC_SIDE_VOLTAGE + 0x20000448 0x4 build/state_machine.o + 0x20000448 RELAY_ESC_SIDE_VOLTAGE + .bss.CURRENT_MEASUREMENT + 0x2000044c 0x4 build/state_machine.o + 0x2000044c CURRENT_MEASUREMENT + .bss.CURRENT_MEASUREMENT_ON + 0x20000450 0x1 build/state_machine.o + 0x20000450 CURRENT_MEASUREMENT_ON + .bss.balancing_state + 0x20000451 0x1 build/state_machine.o + 0x20000451 balancing_state + *fill* 0x20000452 0x2 + .bss.error_timer + 0x20000454 0x4 build/state_machine.o + 0x20000454 error_timer + .bss.precharge_timer + 0x20000458 0x4 build/state_machine.o + 0x20000458 precharge_timer + .bss.discharge_timer + 0x2000045c 0x4 build/state_machine.o + 0x2000045c discharge_timer + .bss.balancing_timer + 0x20000460 0x4 build/state_machine.o + 0x20000460 balancing_timer + .bss.eeprom_timer + 0x20000464 0x4 build/state_machine.o + 0x20000464 eeprom_timer + .bss.powerground_softstart_timer + 0x20000468 0x4 build/state_machine.o + 0x20000468 powerground_softstart_timer + .bss.powerground_calibration_timer + 0x2000046c 0x4 build/state_machine.o + 0x2000046c powerground_calibration_timer + .bss.current_powerground_status + 0x20000470 0x1 build/state_machine.o + 0x20000470 current_powerground_status + .bss.target_powerground_status + 0x20000471 0x1 build/state_machine.o + 0x20000471 target_powerground_status + *fill* 0x20000472 0x2 + .bss.red 0x20000474 0x4 build/status_LED.o + 0x20000474 red + .bss.green 0x20000478 0x4 build/status_LED.o + 0x20000478 green + .bss.blue 0x2000047c 0x4 build/status_LED.o + 0x2000047c blue + .bss.blink_timer + 0x20000480 0x4 build/status_LED.o + 0x20000480 blink_timer + .bss.blink_state + 0x20000484 0x1 build/status_LED.o + 0x20000484 blink_state + *fill* 0x20000485 0x3 + .bss.uwTick 0x20000488 0x4 build/stm32f3xx_hal.o + 0x20000488 uwTick + *(COMMON) + 0x2000048c . = ALIGN (0x4) + 0x2000048c _ebss = . + 0x2000048c __bss_end__ = _ebss + +._user_heap_stack + 0x2000048c 0x604 load address 0x08009d60 + 0x20000490 . = ALIGN (0x8) + *fill* 0x2000048c 0x4 + [!provide] PROVIDE (end = .) + 0x20000490 PROVIDE (_end = .) + 0x20000690 . = (. + _Min_Heap_Size) + *fill* 0x20000490 0x200 + 0x20000a90 . = (. + _Min_Stack_Size) + *fill* 0x20000690 0x400 + 0x20000a90 . = ALIGN (0x8) + +/DISCARD/ + libc.a(*) + libm.a(*) + libgcc.a(*) + +.ARM.attributes + 0x00000000 0x30 + *(.ARM.attributes) + .ARM.attributes + 0x00000000 0x22 /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/crti.o + .ARM.attributes + 0x00000022 0x34 /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/crtbegin.o + .ARM.attributes + 0x00000056 0x34 build/can-halal.o + .ARM.attributes + 0x0000008a 0x34 build/ADBMS_Abstraction.o + .ARM.attributes + 0x000000be 0x34 build/ADBMS_LL_Driver.o + .ARM.attributes + 0x000000f2 0x34 build/AMS_HighLevel.o + .ARM.attributes + 0x00000126 0x34 build/PWM_control.o + .ARM.attributes + 0x0000015a 0x34 build/TMP1075.o + .ARM.attributes + 0x0000018e 0x34 build/can.o + .ARM.attributes + 0x000001c2 0x34 build/eeprom.o + .ARM.attributes + 0x000001f6 0x34 build/errors.o + .ARM.attributes + 0x0000022a 0x34 build/main.o + .ARM.attributes + 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build/main.o +FLASH_IRQHandler build/startup_stm32f302xc.o +FLASH_PageErase build/stm32f3xx_hal_flash_ex.o + build/stm32f3xx_hal_flash.o +FLASH_WaitForLastOperation build/stm32f3xx_hal_flash.o + build/stm32f3xx_hal_flash_ex.o +FPU_IRQHandler build/startup_stm32f302xc.o +F_CRC_CalculaCheckSum build/ADBMS_LL_Driver.o +HAL_CAN_AbortTxRequest build/stm32f3xx_hal_can.o +HAL_CAN_ActivateNotification build/stm32f3xx_hal_can.o + build/can-halal.o +HAL_CAN_AddTxMessage build/stm32f3xx_hal_can.o + build/can-halal.o +HAL_CAN_ConfigFilter build/stm32f3xx_hal_can.o + build/can-halal.o +HAL_CAN_DeInit build/stm32f3xx_hal_can.o +HAL_CAN_DeactivateNotification build/stm32f3xx_hal_can.o +HAL_CAN_ErrorCallback build/stm32f3xx_hal_can.o +HAL_CAN_GetError build/stm32f3xx_hal_can.o +HAL_CAN_GetRxFifoFillLevel build/stm32f3xx_hal_can.o +HAL_CAN_GetRxMessage build/stm32f3xx_hal_can.o + build/can-halal.o +HAL_CAN_GetState build/stm32f3xx_hal_can.o +HAL_CAN_GetTxMailboxesFreeLevel build/stm32f3xx_hal_can.o +HAL_CAN_GetTxTimestamp build/stm32f3xx_hal_can.o +HAL_CAN_IRQHandler build/stm32f3xx_hal_can.o + build/stm32f3xx_it.o +HAL_CAN_Init build/stm32f3xx_hal_can.o + build/main.o +HAL_CAN_IsSleepActive build/stm32f3xx_hal_can.o +HAL_CAN_IsTxMessagePending build/stm32f3xx_hal_can.o +HAL_CAN_MspDeInit build/stm32f3xx_hal_msp.o +HAL_CAN_MspInit build/stm32f3xx_hal_msp.o +HAL_CAN_RequestSleep build/stm32f3xx_hal_can.o +HAL_CAN_ResetError build/stm32f3xx_hal_can.o +HAL_CAN_RxFifo0FullCallback build/stm32f3xx_hal_can.o +HAL_CAN_RxFifo0MsgPendingCallback build/can-halal.o +HAL_CAN_RxFifo1FullCallback build/stm32f3xx_hal_can.o +HAL_CAN_RxFifo1MsgPendingCallback build/stm32f3xx_hal_can.o +HAL_CAN_SleepCallback build/stm32f3xx_hal_can.o +HAL_CAN_Start build/stm32f3xx_hal_can.o + build/can-halal.o +HAL_CAN_Stop build/stm32f3xx_hal_can.o +HAL_CAN_TxMailbox0AbortCallback build/stm32f3xx_hal_can.o +HAL_CAN_TxMailbox0CompleteCallback build/stm32f3xx_hal_can.o +HAL_CAN_TxMailbox1AbortCallback build/stm32f3xx_hal_can.o +HAL_CAN_TxMailbox1CompleteCallback build/stm32f3xx_hal_can.o +HAL_CAN_TxMailbox2AbortCallback build/stm32f3xx_hal_can.o +HAL_CAN_TxMailbox2CompleteCallback build/stm32f3xx_hal_can.o +HAL_CAN_WakeUp build/stm32f3xx_hal_can.o +HAL_CAN_WakeUpFromRxMsgCallback build/stm32f3xx_hal_can.o +HAL_DBGMCU_DisableDBGSleepMode build/stm32f3xx_hal.o +HAL_DBGMCU_DisableDBGStandbyMode build/stm32f3xx_hal.o +HAL_DBGMCU_DisableDBGStopMode build/stm32f3xx_hal.o +HAL_DBGMCU_EnableDBGSleepMode build/stm32f3xx_hal.o +HAL_DBGMCU_EnableDBGStandbyMode build/stm32f3xx_hal.o +HAL_DBGMCU_EnableDBGStopMode build/stm32f3xx_hal.o +HAL_DMA_Abort build/stm32f3xx_hal_dma.o + build/stm32f3xx_hal_spi.o +HAL_DMA_Abort_IT build/stm32f3xx_hal_dma.o + build/stm32f3xx_hal_tim_ex.o + build/stm32f3xx_hal_tim.o + build/stm32f3xx_hal_spi.o + build/stm32f3xx_hal_i2c.o +HAL_DMA_DeInit build/stm32f3xx_hal_dma.o +HAL_DMA_GetError build/stm32f3xx_hal_dma.o +HAL_DMA_GetState build/stm32f3xx_hal_dma.o + build/stm32f3xx_hal_i2c.o +HAL_DMA_IRQHandler build/stm32f3xx_hal_dma.o +HAL_DMA_Init build/stm32f3xx_hal_dma.o +HAL_DMA_PollForTransfer build/stm32f3xx_hal_dma.o +HAL_DMA_RegisterCallback build/stm32f3xx_hal_dma.o +HAL_DMA_Start build/stm32f3xx_hal_dma.o +HAL_DMA_Start_IT build/stm32f3xx_hal_dma.o + build/stm32f3xx_hal_tim_ex.o + build/stm32f3xx_hal_tim.o + build/stm32f3xx_hal_spi.o + build/stm32f3xx_hal_i2c.o +HAL_DMA_UnRegisterCallback build/stm32f3xx_hal_dma.o +HAL_DeInit build/stm32f3xx_hal.o +HAL_Delay build/stm32f3xx_hal.o + build/can.o + build/ADBMS_LL_Driver.o +HAL_EXTI_ClearConfigLine build/stm32f3xx_hal_exti.o +HAL_EXTI_ClearPending build/stm32f3xx_hal_exti.o +HAL_EXTI_GenerateSWI build/stm32f3xx_hal_exti.o +HAL_EXTI_GetConfigLine build/stm32f3xx_hal_exti.o +HAL_EXTI_GetHandle build/stm32f3xx_hal_exti.o +HAL_EXTI_GetPending build/stm32f3xx_hal_exti.o +HAL_EXTI_IRQHandler build/stm32f3xx_hal_exti.o +HAL_EXTI_RegisterCallback build/stm32f3xx_hal_exti.o +HAL_EXTI_SetConfigLine build/stm32f3xx_hal_exti.o +HAL_FLASHEx_Erase build/stm32f3xx_hal_flash_ex.o +HAL_FLASHEx_Erase_IT build/stm32f3xx_hal_flash_ex.o +HAL_FLASHEx_OBErase build/stm32f3xx_hal_flash_ex.o +HAL_FLASHEx_OBGetConfig build/stm32f3xx_hal_flash_ex.o +HAL_FLASHEx_OBGetUserData build/stm32f3xx_hal_flash_ex.o +HAL_FLASHEx_OBProgram build/stm32f3xx_hal_flash_ex.o +HAL_FLASH_EndOfOperationCallback build/stm32f3xx_hal_flash.o +HAL_FLASH_GetError build/stm32f3xx_hal_flash.o +HAL_FLASH_IRQHandler build/stm32f3xx_hal_flash.o +HAL_FLASH_Lock build/stm32f3xx_hal_flash.o +HAL_FLASH_OB_Launch build/stm32f3xx_hal_flash.o +HAL_FLASH_OB_Lock build/stm32f3xx_hal_flash.o +HAL_FLASH_OB_Unlock build/stm32f3xx_hal_flash.o +HAL_FLASH_OperationErrorCallback build/stm32f3xx_hal_flash.o +HAL_FLASH_Program build/stm32f3xx_hal_flash.o +HAL_FLASH_Program_IT build/stm32f3xx_hal_flash.o +HAL_FLASH_Unlock build/stm32f3xx_hal_flash.o +HAL_GPIO_DeInit build/stm32f3xx_hal_gpio.o + build/stm32f3xx_hal_msp.o +HAL_GPIO_EXTI_Callback build/stm32f3xx_hal_gpio.o +HAL_GPIO_EXTI_IRQHandler build/stm32f3xx_hal_gpio.o +HAL_GPIO_Init build/stm32f3xx_hal_gpio.o + build/stm32f3xx_hal_rcc.o + build/stm32f3xx_hal_msp.o + build/main.o +HAL_GPIO_LockPin build/stm32f3xx_hal_gpio.o +HAL_GPIO_ReadPin build/stm32f3xx_hal_gpio.o +HAL_GPIO_TogglePin build/stm32f3xx_hal_gpio.o +HAL_GPIO_WritePin build/stm32f3xx_hal_gpio.o + build/state_machine.o + build/main.o + build/eeprom.o + build/ADBMS_LL_Driver.o +HAL_GetDEVID build/stm32f3xx_hal.o +HAL_GetHalVersion build/stm32f3xx_hal.o +HAL_GetREVID build/stm32f3xx_hal.o +HAL_GetTick build/stm32f3xx_hal.o + build/stm32f3xx_hal_spi.o + build/stm32f3xx_hal_rcc_ex.o + build/stm32f3xx_hal_rcc.o + build/stm32f3xx_hal_i2c.o + build/stm32f3xx_hal_flash.o + build/stm32f3xx_hal_dma.o + build/stm32f3xx_hal_can.o + build/status_LED.o + build/state_machine.o + build/soc_estimation.o + build/main.o + build/errors.o + build/can.o + build/AMS_HighLevel.o +HAL_GetTickFreq build/stm32f3xx_hal.o +HAL_GetTickPrio build/stm32f3xx_hal.o +HAL_GetUIDw0 build/stm32f3xx_hal.o +HAL_GetUIDw1 build/stm32f3xx_hal.o +HAL_GetUIDw2 build/stm32f3xx_hal.o +HAL_I2CEx_ConfigAnalogFilter build/stm32f3xx_hal_i2c_ex.o + build/main.o +HAL_I2CEx_ConfigDigitalFilter build/stm32f3xx_hal_i2c_ex.o + build/main.o +HAL_I2CEx_DisableFastModePlus build/stm32f3xx_hal_i2c_ex.o +HAL_I2CEx_DisableWakeUp build/stm32f3xx_hal_i2c_ex.o +HAL_I2CEx_EnableFastModePlus build/stm32f3xx_hal_i2c_ex.o +HAL_I2CEx_EnableWakeUp build/stm32f3xx_hal_i2c_ex.o +HAL_I2C_AbortCpltCallback build/stm32f3xx_hal_i2c.o +HAL_I2C_AddrCallback build/stm32f3xx_hal_i2c.o +HAL_I2C_DeInit build/stm32f3xx_hal_i2c.o +HAL_I2C_DisableListen_IT build/stm32f3xx_hal_i2c.o +HAL_I2C_ER_IRQHandler build/stm32f3xx_hal_i2c.o +HAL_I2C_EV_IRQHandler build/stm32f3xx_hal_i2c.o +HAL_I2C_EnableListen_IT build/stm32f3xx_hal_i2c.o +HAL_I2C_ErrorCallback build/stm32f3xx_hal_i2c.o +HAL_I2C_GetError build/stm32f3xx_hal_i2c.o +HAL_I2C_GetMode build/stm32f3xx_hal_i2c.o +HAL_I2C_GetState build/stm32f3xx_hal_i2c.o +HAL_I2C_Init build/stm32f3xx_hal_i2c.o + build/main.o +HAL_I2C_IsDeviceReady build/stm32f3xx_hal_i2c.o +HAL_I2C_ListenCpltCallback build/stm32f3xx_hal_i2c.o +HAL_I2C_MasterRxCpltCallback build/stm32f3xx_hal_i2c.o +HAL_I2C_MasterTxCpltCallback build/stm32f3xx_hal_i2c.o +HAL_I2C_Master_Abort_IT build/stm32f3xx_hal_i2c.o +HAL_I2C_Master_Receive build/stm32f3xx_hal_i2c.o + build/TMP1075.o +HAL_I2C_Master_Receive_DMA build/stm32f3xx_hal_i2c.o +HAL_I2C_Master_Receive_IT build/stm32f3xx_hal_i2c.o +HAL_I2C_Master_Seq_Receive_DMA build/stm32f3xx_hal_i2c.o +HAL_I2C_Master_Seq_Receive_IT build/stm32f3xx_hal_i2c.o +HAL_I2C_Master_Seq_Transmit_DMA build/stm32f3xx_hal_i2c.o +HAL_I2C_Master_Seq_Transmit_IT build/stm32f3xx_hal_i2c.o +HAL_I2C_Master_Transmit build/stm32f3xx_hal_i2c.o + build/TMP1075.o +HAL_I2C_Master_Transmit_DMA build/stm32f3xx_hal_i2c.o +HAL_I2C_Master_Transmit_IT build/stm32f3xx_hal_i2c.o +HAL_I2C_MemRxCpltCallback build/stm32f3xx_hal_i2c.o +HAL_I2C_MemTxCpltCallback build/stm32f3xx_hal_i2c.o +HAL_I2C_Mem_Read build/stm32f3xx_hal_i2c.o + build/eeprom.o +HAL_I2C_Mem_Read_DMA build/stm32f3xx_hal_i2c.o +HAL_I2C_Mem_Read_IT build/stm32f3xx_hal_i2c.o +HAL_I2C_Mem_Write build/stm32f3xx_hal_i2c.o + build/eeprom.o +HAL_I2C_Mem_Write_DMA build/stm32f3xx_hal_i2c.o +HAL_I2C_Mem_Write_IT build/stm32f3xx_hal_i2c.o +HAL_I2C_MspDeInit build/stm32f3xx_hal_msp.o +HAL_I2C_MspInit build/stm32f3xx_hal_msp.o +HAL_I2C_SlaveRxCpltCallback build/stm32f3xx_hal_i2c.o +HAL_I2C_SlaveTxCpltCallback build/stm32f3xx_hal_i2c.o +HAL_I2C_Slave_Receive build/stm32f3xx_hal_i2c.o +HAL_I2C_Slave_Receive_DMA build/stm32f3xx_hal_i2c.o +HAL_I2C_Slave_Receive_IT build/stm32f3xx_hal_i2c.o +HAL_I2C_Slave_Seq_Receive_DMA build/stm32f3xx_hal_i2c.o +HAL_I2C_Slave_Seq_Receive_IT build/stm32f3xx_hal_i2c.o +HAL_I2C_Slave_Seq_Transmit_DMA build/stm32f3xx_hal_i2c.o +HAL_I2C_Slave_Seq_Transmit_IT build/stm32f3xx_hal_i2c.o +HAL_I2C_Slave_Transmit build/stm32f3xx_hal_i2c.o +HAL_I2C_Slave_Transmit_DMA build/stm32f3xx_hal_i2c.o +HAL_I2C_Slave_Transmit_IT build/stm32f3xx_hal_i2c.o +HAL_IncTick build/stm32f3xx_hal.o + build/stm32f3xx_it.o +HAL_Init build/stm32f3xx_hal.o + build/main.o +HAL_InitTick build/stm32f3xx_hal.o + build/stm32f3xx_hal_rcc.o +HAL_MPU_ConfigRegion build/stm32f3xx_hal_cortex.o +HAL_MPU_Disable build/stm32f3xx_hal_cortex.o +HAL_MPU_Enable build/stm32f3xx_hal_cortex.o +HAL_MspDeInit build/stm32f3xx_hal.o +HAL_MspInit build/stm32f3xx_hal_msp.o +HAL_NVIC_ClearPendingIRQ build/stm32f3xx_hal_cortex.o +HAL_NVIC_DisableIRQ build/stm32f3xx_hal_cortex.o + build/stm32f3xx_hal_msp.o +HAL_NVIC_EnableIRQ build/stm32f3xx_hal_cortex.o + build/stm32f3xx_hal_msp.o +HAL_NVIC_GetActive build/stm32f3xx_hal_cortex.o +HAL_NVIC_GetPendingIRQ build/stm32f3xx_hal_cortex.o +HAL_NVIC_GetPriority build/stm32f3xx_hal_cortex.o +HAL_NVIC_GetPriorityGrouping build/stm32f3xx_hal_cortex.o +HAL_NVIC_SetPendingIRQ build/stm32f3xx_hal_cortex.o +HAL_NVIC_SetPriority build/stm32f3xx_hal_cortex.o + build/stm32f3xx_hal.o + build/stm32f3xx_hal_msp.o +HAL_NVIC_SetPriorityGrouping build/stm32f3xx_hal_cortex.o + build/stm32f3xx_hal.o +HAL_NVIC_SystemReset build/stm32f3xx_hal_cortex.o +HAL_PWR_ConfigPVD build/stm32f3xx_hal_pwr_ex.o +HAL_PWR_DeInit build/stm32f3xx_hal_pwr.o +HAL_PWR_DisableBkUpAccess build/stm32f3xx_hal_pwr.o +HAL_PWR_DisablePVD build/stm32f3xx_hal_pwr_ex.o +HAL_PWR_DisableSEVOnPend build/stm32f3xx_hal_pwr.o +HAL_PWR_DisableSleepOnExit build/stm32f3xx_hal_pwr.o +HAL_PWR_DisableWakeUpPin build/stm32f3xx_hal_pwr.o +HAL_PWR_EnableBkUpAccess build/stm32f3xx_hal_pwr.o +HAL_PWR_EnablePVD build/stm32f3xx_hal_pwr_ex.o +HAL_PWR_EnableSEVOnPend build/stm32f3xx_hal_pwr.o +HAL_PWR_EnableSleepOnExit build/stm32f3xx_hal_pwr.o +HAL_PWR_EnableWakeUpPin build/stm32f3xx_hal_pwr.o +HAL_PWR_EnterSLEEPMode build/stm32f3xx_hal_pwr.o +HAL_PWR_EnterSTANDBYMode build/stm32f3xx_hal_pwr.o +HAL_PWR_EnterSTOPMode build/stm32f3xx_hal_pwr.o +HAL_PWR_PVDCallback build/stm32f3xx_hal_pwr_ex.o +HAL_PWR_PVD_IRQHandler build/stm32f3xx_hal_pwr_ex.o +HAL_RCCEx_GetPeriphCLKConfig build/stm32f3xx_hal_rcc_ex.o +HAL_RCCEx_GetPeriphCLKFreq build/stm32f3xx_hal_rcc_ex.o +HAL_RCCEx_PeriphCLKConfig build/stm32f3xx_hal_rcc_ex.o + build/main.o +HAL_RCC_CSSCallback build/stm32f3xx_hal_rcc.o +HAL_RCC_ClockConfig build/stm32f3xx_hal_rcc.o + build/main.o +HAL_RCC_DeInit build/stm32f3xx_hal_rcc.o +HAL_RCC_DisableCSS build/stm32f3xx_hal_rcc.o +HAL_RCC_EnableCSS build/stm32f3xx_hal_rcc.o +HAL_RCC_GetClockConfig build/stm32f3xx_hal_rcc.o +HAL_RCC_GetHCLKFreq build/stm32f3xx_hal_rcc.o +HAL_RCC_GetOscConfig build/stm32f3xx_hal_rcc.o +HAL_RCC_GetPCLK1Freq build/stm32f3xx_hal_rcc.o + build/stm32f3xx_hal_rcc_ex.o +HAL_RCC_GetPCLK2Freq build/stm32f3xx_hal_rcc.o + build/stm32f3xx_hal_rcc_ex.o +HAL_RCC_GetSysClockFreq build/stm32f3xx_hal_rcc.o + build/stm32f3xx_hal_rcc_ex.o +HAL_RCC_MCOConfig build/stm32f3xx_hal_rcc.o +HAL_RCC_NMI_IRQHandler build/stm32f3xx_hal_rcc.o +HAL_RCC_OscConfig build/stm32f3xx_hal_rcc.o + build/main.o +HAL_ResumeTick build/stm32f3xx_hal.o +HAL_SPIEx_FlushRxFifo build/stm32f3xx_hal_spi_ex.o +HAL_SPI_Abort build/stm32f3xx_hal_spi.o +HAL_SPI_AbortCpltCallback build/stm32f3xx_hal_spi.o +HAL_SPI_Abort_IT build/stm32f3xx_hal_spi.o +HAL_SPI_DMAPause build/stm32f3xx_hal_spi.o +HAL_SPI_DMAResume build/stm32f3xx_hal_spi.o +HAL_SPI_DMAStop build/stm32f3xx_hal_spi.o +HAL_SPI_DeInit build/stm32f3xx_hal_spi.o +HAL_SPI_ErrorCallback build/stm32f3xx_hal_spi.o +HAL_SPI_GetError build/stm32f3xx_hal_spi.o +HAL_SPI_GetState build/stm32f3xx_hal_spi.o +HAL_SPI_IRQHandler build/stm32f3xx_hal_spi.o +HAL_SPI_Init build/stm32f3xx_hal_spi.o + build/main.o +HAL_SPI_MspDeInit build/stm32f3xx_hal_msp.o +HAL_SPI_MspInit build/stm32f3xx_hal_msp.o +HAL_SPI_Receive build/stm32f3xx_hal_spi.o + build/ADBMS_LL_Driver.o +HAL_SPI_Receive_DMA build/stm32f3xx_hal_spi.o +HAL_SPI_Receive_IT build/stm32f3xx_hal_spi.o +HAL_SPI_RxCpltCallback build/stm32f3xx_hal_spi.o +HAL_SPI_RxHalfCpltCallback build/stm32f3xx_hal_spi.o +HAL_SPI_Transmit build/stm32f3xx_hal_spi.o +HAL_SPI_TransmitReceive build/stm32f3xx_hal_spi.o + build/ADBMS_LL_Driver.o +HAL_SPI_TransmitReceive_DMA build/stm32f3xx_hal_spi.o +HAL_SPI_TransmitReceive_IT build/stm32f3xx_hal_spi.o +HAL_SPI_Transmit_DMA build/stm32f3xx_hal_spi.o +HAL_SPI_Transmit_IT build/stm32f3xx_hal_spi.o +HAL_SPI_TxCpltCallback build/stm32f3xx_hal_spi.o +HAL_SPI_TxHalfCpltCallback build/stm32f3xx_hal_spi.o +HAL_SPI_TxRxCpltCallback build/stm32f3xx_hal_spi.o +HAL_SPI_TxRxHalfCpltCallback build/stm32f3xx_hal_spi.o +HAL_SYSTICK_CLKSourceConfig build/stm32f3xx_hal_cortex.o +HAL_SYSTICK_Callback build/stm32f3xx_hal_cortex.o +HAL_SYSTICK_Config build/stm32f3xx_hal_cortex.o + build/stm32f3xx_hal.o +HAL_SYSTICK_IRQHandler build/stm32f3xx_hal_cortex.o +HAL_SetTickFreq build/stm32f3xx_hal.o +HAL_SuspendTick build/stm32f3xx_hal.o +HAL_TIMEx_Break2Callback build/stm32f3xx_hal_tim_ex.o + build/stm32f3xx_hal_tim.o +HAL_TIMEx_BreakCallback build/stm32f3xx_hal_tim_ex.o + build/stm32f3xx_hal_tim.o +HAL_TIMEx_CommutCallback build/stm32f3xx_hal_tim_ex.o + build/stm32f3xx_hal_tim.o +HAL_TIMEx_CommutHalfCpltCallback build/stm32f3xx_hal_tim_ex.o +HAL_TIMEx_ConfigBreakDeadTime build/stm32f3xx_hal_tim_ex.o + build/main.o +HAL_TIMEx_ConfigCommutEvent build/stm32f3xx_hal_tim_ex.o +HAL_TIMEx_ConfigCommutEvent_DMA build/stm32f3xx_hal_tim_ex.o +HAL_TIMEx_ConfigCommutEvent_IT build/stm32f3xx_hal_tim_ex.o +HAL_TIMEx_GetChannelNState build/stm32f3xx_hal_tim_ex.o +HAL_TIMEx_GroupChannel5 build/stm32f3xx_hal_tim_ex.o +HAL_TIMEx_HallSensor_DeInit build/stm32f3xx_hal_tim_ex.o +HAL_TIMEx_HallSensor_GetState build/stm32f3xx_hal_tim_ex.o +HAL_TIMEx_HallSensor_Init build/stm32f3xx_hal_tim_ex.o +HAL_TIMEx_HallSensor_MspDeInit build/stm32f3xx_hal_tim_ex.o +HAL_TIMEx_HallSensor_MspInit build/stm32f3xx_hal_tim_ex.o +HAL_TIMEx_HallSensor_Start build/stm32f3xx_hal_tim_ex.o +HAL_TIMEx_HallSensor_Start_DMA build/stm32f3xx_hal_tim_ex.o +HAL_TIMEx_HallSensor_Start_IT build/stm32f3xx_hal_tim_ex.o +HAL_TIMEx_HallSensor_Stop build/stm32f3xx_hal_tim_ex.o +HAL_TIMEx_HallSensor_Stop_DMA build/stm32f3xx_hal_tim_ex.o +HAL_TIMEx_HallSensor_Stop_IT build/stm32f3xx_hal_tim_ex.o +HAL_TIMEx_MasterConfigSynchronization build/stm32f3xx_hal_tim_ex.o + build/main.o +HAL_TIMEx_OCN_Start build/stm32f3xx_hal_tim_ex.o +HAL_TIMEx_OCN_Start_DMA build/stm32f3xx_hal_tim_ex.o +HAL_TIMEx_OCN_Start_IT build/stm32f3xx_hal_tim_ex.o +HAL_TIMEx_OCN_Stop build/stm32f3xx_hal_tim_ex.o +HAL_TIMEx_OCN_Stop_DMA build/stm32f3xx_hal_tim_ex.o +HAL_TIMEx_OCN_Stop_IT build/stm32f3xx_hal_tim_ex.o +HAL_TIMEx_OnePulseN_Start build/stm32f3xx_hal_tim_ex.o +HAL_TIMEx_OnePulseN_Start_IT build/stm32f3xx_hal_tim_ex.o +HAL_TIMEx_OnePulseN_Stop build/stm32f3xx_hal_tim_ex.o +HAL_TIMEx_OnePulseN_Stop_IT build/stm32f3xx_hal_tim_ex.o +HAL_TIMEx_PWMN_Start build/stm32f3xx_hal_tim_ex.o +HAL_TIMEx_PWMN_Start_DMA build/stm32f3xx_hal_tim_ex.o +HAL_TIMEx_PWMN_Start_IT build/stm32f3xx_hal_tim_ex.o +HAL_TIMEx_PWMN_Stop build/stm32f3xx_hal_tim_ex.o +HAL_TIMEx_PWMN_Stop_DMA build/stm32f3xx_hal_tim_ex.o +HAL_TIMEx_PWMN_Stop_IT build/stm32f3xx_hal_tim_ex.o +HAL_TIMEx_RemapConfig build/stm32f3xx_hal_tim_ex.o +HAL_TIM_Base_DeInit build/stm32f3xx_hal_tim.o +HAL_TIM_Base_GetState build/stm32f3xx_hal_tim.o +HAL_TIM_Base_Init build/stm32f3xx_hal_tim.o +HAL_TIM_Base_MspDeInit build/stm32f3xx_hal_tim.o +HAL_TIM_Base_MspInit build/stm32f3xx_hal_tim.o +HAL_TIM_Base_Start build/stm32f3xx_hal_tim.o +HAL_TIM_Base_Start_DMA build/stm32f3xx_hal_tim.o +HAL_TIM_Base_Start_IT build/stm32f3xx_hal_tim.o +HAL_TIM_Base_Stop build/stm32f3xx_hal_tim.o +HAL_TIM_Base_Stop_DMA build/stm32f3xx_hal_tim.o +HAL_TIM_Base_Stop_IT build/stm32f3xx_hal_tim.o +HAL_TIM_ConfigClockSource build/stm32f3xx_hal_tim.o +HAL_TIM_ConfigOCrefClear build/stm32f3xx_hal_tim.o +HAL_TIM_ConfigTI1Input build/stm32f3xx_hal_tim.o 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build/stm32f3xx_hal_tim_ex.o +HAL_TIM_GenerateEvent build/stm32f3xx_hal_tim.o +HAL_TIM_GetActiveChannel build/stm32f3xx_hal_tim.o +HAL_TIM_GetChannelState build/stm32f3xx_hal_tim.o +HAL_TIM_IC_CaptureCallback build/stm32f3xx_hal_tim.o +HAL_TIM_IC_CaptureHalfCpltCallback build/stm32f3xx_hal_tim.o +HAL_TIM_IC_ConfigChannel build/stm32f3xx_hal_tim.o +HAL_TIM_IC_DeInit build/stm32f3xx_hal_tim.o +HAL_TIM_IC_GetState build/stm32f3xx_hal_tim.o +HAL_TIM_IC_Init build/stm32f3xx_hal_tim.o +HAL_TIM_IC_MspDeInit build/stm32f3xx_hal_tim.o +HAL_TIM_IC_MspInit build/stm32f3xx_hal_tim.o +HAL_TIM_IC_Start build/stm32f3xx_hal_tim.o +HAL_TIM_IC_Start_DMA build/stm32f3xx_hal_tim.o +HAL_TIM_IC_Start_IT build/stm32f3xx_hal_tim.o +HAL_TIM_IC_Stop build/stm32f3xx_hal_tim.o +HAL_TIM_IC_Stop_DMA build/stm32f3xx_hal_tim.o +HAL_TIM_IC_Stop_IT build/stm32f3xx_hal_tim.o +HAL_TIM_IRQHandler build/stm32f3xx_hal_tim.o +HAL_TIM_MspPostInit build/stm32f3xx_hal_msp.o + build/main.o +HAL_TIM_OC_ConfigChannel build/stm32f3xx_hal_tim.o +HAL_TIM_OC_DeInit build/stm32f3xx_hal_tim.o +HAL_TIM_OC_DelayElapsedCallback build/stm32f3xx_hal_tim.o +HAL_TIM_OC_GetState build/stm32f3xx_hal_tim.o +HAL_TIM_OC_Init build/stm32f3xx_hal_tim.o +HAL_TIM_OC_MspDeInit build/stm32f3xx_hal_tim.o +HAL_TIM_OC_MspInit build/stm32f3xx_hal_tim.o +HAL_TIM_OC_Start build/stm32f3xx_hal_tim.o +HAL_TIM_OC_Start_DMA build/stm32f3xx_hal_tim.o +HAL_TIM_OC_Start_IT build/stm32f3xx_hal_tim.o +HAL_TIM_OC_Stop build/stm32f3xx_hal_tim.o +HAL_TIM_OC_Stop_DMA build/stm32f3xx_hal_tim.o +HAL_TIM_OC_Stop_IT build/stm32f3xx_hal_tim.o +HAL_TIM_OnePulse_ConfigChannel build/stm32f3xx_hal_tim.o +HAL_TIM_OnePulse_DeInit build/stm32f3xx_hal_tim.o +HAL_TIM_OnePulse_GetState build/stm32f3xx_hal_tim.o +HAL_TIM_OnePulse_Init build/stm32f3xx_hal_tim.o +HAL_TIM_OnePulse_MspDeInit build/stm32f3xx_hal_tim.o +HAL_TIM_OnePulse_MspInit build/stm32f3xx_hal_tim.o +HAL_TIM_OnePulse_Start build/stm32f3xx_hal_tim.o +HAL_TIM_OnePulse_Start_IT build/stm32f3xx_hal_tim.o +HAL_TIM_OnePulse_Stop build/stm32f3xx_hal_tim.o +HAL_TIM_OnePulse_Stop_IT build/stm32f3xx_hal_tim.o +HAL_TIM_PWM_ConfigChannel build/stm32f3xx_hal_tim.o + build/main.o +HAL_TIM_PWM_DeInit build/stm32f3xx_hal_tim.o +HAL_TIM_PWM_GetState build/stm32f3xx_hal_tim.o +HAL_TIM_PWM_Init build/stm32f3xx_hal_tim.o + build/main.o +HAL_TIM_PWM_MspDeInit build/stm32f3xx_hal_msp.o +HAL_TIM_PWM_MspInit build/stm32f3xx_hal_msp.o +HAL_TIM_PWM_PulseFinishedCallback build/stm32f3xx_hal_tim.o + build/stm32f3xx_hal_tim_ex.o +HAL_TIM_PWM_PulseFinishedHalfCpltCallback build/stm32f3xx_hal_tim.o +HAL_TIM_PWM_Start build/stm32f3xx_hal_tim.o + build/status_LED.o + build/PWM_control.o +HAL_TIM_PWM_Start_DMA build/stm32f3xx_hal_tim.o +HAL_TIM_PWM_Start_IT build/stm32f3xx_hal_tim.o +HAL_TIM_PWM_Stop build/stm32f3xx_hal_tim.o +HAL_TIM_PWM_Stop_DMA build/stm32f3xx_hal_tim.o +HAL_TIM_PWM_Stop_IT build/stm32f3xx_hal_tim.o +HAL_TIM_PeriodElapsedCallback build/stm32f3xx_hal_tim.o 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build/state_machine.o +PendSV_Handler build/stm32f3xx_it.o +RCC_IRQHandler build/startup_stm32f302xc.o +RELAY_BAT_SIDE_VOLTAGE build/state_machine.o + build/eeprom.o + build/can.o +RELAY_ESC_SIDE_VOLTAGE build/state_machine.o + build/eeprom.o + build/can.o +RTC_Alarm_IRQHandler build/startup_stm32f302xc.o +RTC_WKUP_IRQHandler build/startup_stm32f302xc.o +Reset_Handler build/startup_stm32f302xc.o +SPI1_IRQHandler build/startup_stm32f302xc.o +SPI2_IRQHandler build/startup_stm32f302xc.o +SPI3_IRQHandler build/startup_stm32f302xc.o +SVC_Handler build/stm32f3xx_it.o +SysTick_Handler build/stm32f3xx_it.o +SystemClock_Config build/main.o +SystemCoreClock build/system_stm32f3xx.o + build/stm32f3xx_hal_spi.o + build/stm32f3xx_hal_rcc_ex.o + build/stm32f3xx_hal_rcc.o + build/stm32f3xx_hal.o +SystemCoreClockUpdate build/system_stm32f3xx.o +SystemInit build/system_stm32f3xx.o + build/startup_stm32f302xc.o +TAMP_STAMP_IRQHandler build/startup_stm32f302xc.o +TIM1_BRK_TIM15_IRQHandler build/startup_stm32f302xc.o +TIM1_CC_IRQHandler build/startup_stm32f302xc.o +TIM1_TRG_COM_TIM17_IRQHandler build/startup_stm32f302xc.o +TIM1_UP_TIM16_IRQHandler build/startup_stm32f302xc.o +TIM2_IRQHandler build/startup_stm32f302xc.o +TIM3_IRQHandler build/startup_stm32f302xc.o +TIM4_IRQHandler build/startup_stm32f302xc.o +TIM6_DAC_IRQHandler build/startup_stm32f302xc.o +TIMEx_DMACommutationCplt build/stm32f3xx_hal_tim_ex.o + build/stm32f3xx_hal_tim.o +TIMEx_DMACommutationHalfCplt build/stm32f3xx_hal_tim_ex.o + build/stm32f3xx_hal_tim.o +TIM_Base_SetConfig build/stm32f3xx_hal_tim.o + build/stm32f3xx_hal_tim_ex.o +TIM_CCxChannelCmd build/stm32f3xx_hal_tim.o + build/stm32f3xx_hal_tim_ex.o +TIM_DMACaptureCplt build/stm32f3xx_hal_tim.o + build/stm32f3xx_hal_tim_ex.o +TIM_DMACaptureHalfCplt build/stm32f3xx_hal_tim.o + build/stm32f3xx_hal_tim_ex.o +TIM_DMADelayPulseHalfCplt build/stm32f3xx_hal_tim.o + build/stm32f3xx_hal_tim_ex.o +TIM_DMAError build/stm32f3xx_hal_tim.o + build/stm32f3xx_hal_tim_ex.o +TIM_ETR_SetConfig build/stm32f3xx_hal_tim.o +TIM_OC2_SetConfig build/stm32f3xx_hal_tim.o + build/stm32f3xx_hal_tim_ex.o +TIM_TI1_SetConfig build/stm32f3xx_hal_tim.o + build/stm32f3xx_hal_tim_ex.o +UART4_IRQHandler build/startup_stm32f302xc.o +UART5_IRQHandler build/startup_stm32f302xc.o +USART1_IRQHandler build/startup_stm32f302xc.o +USART2_IRQHandler build/startup_stm32f302xc.o +USART3_IRQHandler build/startup_stm32f302xc.o +USBWakeUp_IRQHandler build/startup_stm32f302xc.o +USBWakeUp_RMP_IRQHandler build/startup_stm32f302xc.o +USB_HP_CAN_TX_IRQHandler build/startup_stm32f302xc.o +USB_HP_IRQHandler build/startup_stm32f302xc.o +USB_LP_CAN_RX0_IRQHandler build/stm32f3xx_it.o +USB_LP_IRQHandler build/startup_stm32f302xc.o +UsageFault_Handler build/stm32f3xx_it.o +WWDG_IRQHandler build/startup_stm32f302xc.o +_ITM_deregisterTMCloneTable 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/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/libgcc.a(_arm_truncdfsf2.o) +_close build/syscalls.o + /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-closer.o) +_close_r /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-closer.o) + /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-stdio.o) +_ebss build/startup_stm32f302xc.o +_edata build/startup_stm32f302xc.o +_end build/sysmem.o +_estack build/startup_stm32f302xc.o + build/sysmem.o +_execve build/syscalls.o +_exit build/syscalls.o + /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-exit.o) +_fflush_r /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-fflush.o) + /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-findfp.o) +_fini /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/crti.o +_fork build/syscalls.o +_free_r /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-freer.o) + /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-fflush.o) + /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-reent.o) +_fstat build/syscalls.o +_fwalk_sglue /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-fwalk.o) + /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-fflush.o) + /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-findfp.o) +_getpid build/syscalls.o +_impure_data /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-impure.o) + /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-fflush.o) + /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-findfp.o) +_impure_ptr /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-impure.o) + /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-fflush.o) + /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-reent.o) + /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-errno.o) +_init /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/thumb/v7e-m+fp/hard/crti.o + /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-init.o) +_isatty build/syscalls.o +_kill build/syscalls.o +_link build/syscalls.o +_lseek build/syscalls.o + /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-lseekr.o) +_lseek_r /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-lseekr.o) + /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-stdio.o) +_mainCRTStartup /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o +_malloc_r /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-mallocr.o) + /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-findfp.o) +_open build/syscalls.o +_read build/syscalls.o + /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-readr.o) +_read_r /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-readr.o) + /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-stdio.o) +_reclaim_reent /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-reent.o) +_sbrk build/sysmem.o + /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-sbrkr.o) +_sbrk_r /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-sbrkr.o) + /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-mallocr.o) +_sbss build/startup_stm32f302xc.o +_sdata build/startup_stm32f302xc.o +_sidata build/startup_stm32f302xc.o +_stack_init /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o +_start /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o +_stat build/syscalls.o +_times build/syscalls.o +_unlink build/syscalls.o +_wait build/syscalls.o +_write build/syscalls.o + /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-writer.o) +_write_r /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-writer.o) + /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-stdio.o) +adbmsDriverInit build/ADBMS_LL_Driver.o + build/ADBMS_Abstraction.o +adbmsspi build/ADBMS_LL_Driver.o +amsAuxAndStatusMeasurement build/ADBMS_Abstraction.o + build/AMS_HighLevel.o +amsCellMeasurement build/ADBMS_Abstraction.o + build/AMS_HighLevel.o +amsCheckUnderOverVoltage build/ADBMS_Abstraction.o + build/AMS_HighLevel.o +amsClearAux build/ADBMS_Abstraction.o +amsClearCells build/ADBMS_Abstraction.o +amsConfigBalancing build/ADBMS_Abstraction.o + build/state_machine.o + build/AMS_HighLevel.o +amsConfigCellMeasurement build/ADBMS_Abstraction.o +amsConfigOverUnderVoltage build/ADBMS_Abstraction.o +amsReadCellVoltages build/ADBMS_Abstraction.o +amsReset build/ADBMS_Abstraction.o + build/AMS_HighLevel.o +amsSelfTest build/ADBMS_Abstraction.o +amsStartBalancing build/ADBMS_Abstraction.o + build/state_machine.o +amsStopBalancing build/ADBMS_Abstraction.o + build/state_machine.o +amsWakeUp build/ADBMS_Abstraction.o + build/AMS_HighLevel.o +amsov build/AMS_HighLevel.o +amsuv build/AMS_HighLevel.o +atexit /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o +balancedCells build/AMS_HighLevel.o +balancingActive build/AMS_HighLevel.o +balancing_state build/state_machine.o +balancing_timer build/state_machine.o +base_offset build/state_machine.o +battery_cooling build/PWM_control.o +blink_state build/status_LED.o +blink_timer build/status_LED.o +blue build/status_LED.o +calculateCommandPEC build/ADBMS_LL_Driver.o +calculateDataPEC build/ADBMS_LL_Driver.o +can_handle_dump build/can.o +can_handle_recieve_command build/can.o +can_handle_send_log build/can.o + build/state_machine.o +can_handle_send_status build/can.o + build/state_machine.o +can_init build/can.o + build/main.o +can_log_timer build/can.o +can_status_timer build/can.o +can_timeout_timer build/can.o +checkCommandPEC build/ADBMS_LL_Driver.o +checkDataPEC build/ADBMS_LL_Driver.o +clear_error_source build/errors.o + build/TMP1075.o + build/AMS_HighLevel.o +currentAMSState build/AMS_HighLevel.o + build/state_machine.o +current_powerground_status build/state_machine.o + build/eeprom.o + build/can.o + build/PWM_control.o +current_soc build/soc_estimation.o + build/eeprom.o + build/can.o +current_was_flowing build/soc_estimation.o +debugging_mode build/state_machine.o +deviceSleeps build/AMS_HighLevel.o +discharge_timer build/state_machine.o +eeprom_init build/eeprom.o + build/main.o +eeprom_read build/eeprom.o + build/can.o +eeprom_timer build/state_machine.o +eeprom_write build/eeprom.o +eeprom_write_status build/eeprom.o + build/state_machine.o +environ build/syscalls.o +errno /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-reent.o) + /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-sbrkr.o) + /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-lseekr.o) + /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-closer.o) + /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-writer.o) + /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-readr.o) +error_data build/errors.o + build/state_machine.o + build/TMP1075.o + build/AMS_HighLevel.o +error_timer build/state_machine.o +esc_cooling build/PWM_control.o +exit /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-exit.o) + /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o +fflush /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-fflush.o) +ftcan_add_filter build/can-halal.o + build/can.o +ftcan_init build/can-halal.o + build/can.o +ftcan_marshal_signed build/can-halal.o +ftcan_marshal_unsigned build/can-halal.o + build/TMP1075.o + build/AMS_HighLevel.o +ftcan_msg_received_cb build/can.o + build/can-halal.o +ftcan_transmit build/can-halal.o + build/can.o +ftcan_unmarshal_signed build/can-halal.o +ftcan_unmarshal_unsigned build/can-halal.o +g_pfnVectors build/startup_stm32f302xc.o +green build/status_LED.o +handle_over_maxtemp build/TMP1075.o +hardware_init_hook /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o +hcan build/main.o + build/stm32f3xx_it.o +hi2c build/TMP1075.o +hi2c1 build/main.o +hi2c2 build/main.o +hspi1 build/main.o +htim15 build/main.o +htim2 build/main.o +htim3 build/main.o +htim4 build/main.o +id_to_log build/can.o +initAMS build/ADBMS_Abstraction.o + build/AMS_HighLevel.o +initialise_monitor_handles build/syscalls.o +lastAMSState build/AMS_HighLevel.o +last_current_time build/soc_estimation.o +last_message build/can.o +mAs_before_current build/soc_estimation.o +main build/main.o + build/startup_stm32f302xc.o + /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o +mcuAdbmsCSHigh build/ADBMS_LL_Driver.o +mcuAdbmsCSLow build/ADBMS_LL_Driver.o +mcuDelay build/ADBMS_LL_Driver.o + build/AMS_HighLevel.o + build/ADBMS_Abstraction.o +mcuSPIReceive build/ADBMS_LL_Driver.o +mcuSPITransmit build/ADBMS_LL_Driver.o +mcuSPITransmitReceive build/ADBMS_LL_Driver.o +memset /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-memset.o) + /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libc_nano.a(libc_a-findfp.o) + build/main.o + build/eeprom.o + /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o +module build/AMS_HighLevel.o + build/state_machine.o + build/eeprom.o + build/can.o +nfailed_temp_sensors build/TMP1075.o +numberofAux build/AMS_HighLevel.o +numberofCells build/AMS_HighLevel.o +numberofauxchannels build/ADBMS_Abstraction.o +numberofcells build/ADBMS_Abstraction.o +pFlash build/stm32f3xx_hal_flash.o + build/stm32f3xx_hal_flash_ex.o +packetChecksumFails build/AMS_HighLevel.o +pec10_calc build/ADBMS_LL_Driver.o +pollCMD build/ADBMS_LL_Driver.o + build/ADBMS_Abstraction.o +pollingTimes build/AMS_HighLevel.o +powerground build/PWM_control.o +powerground_calibration_stage build/state_machine.o +powerground_calibration_timer build/state_machine.o +powerground_softstart_timer build/state_machine.o +precharge_timer build/state_machine.o +programming_mode build/state_machine.o + build/can.o +readCMD build/ADBMS_LL_Driver.o + build/ADBMS_Abstraction.o +read_address build/eeprom.o + build/can.o +red build/status_LED.o +roundf /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/libm.a(libm_a-sf_round.o) + build/can.o +set_error_source build/errors.o + build/TMP1075.o + build/AMS_HighLevel.o +sm_balancing build/state_machine.o +sm_calibrate_powerground build/state_machine.o +sm_check_battery_temperature build/state_machine.o + build/soc_estimation.o + build/can.o +sm_check_errors build/state_machine.o +sm_eeprom_write_status build/state_machine.o +sm_handle_ams_in build/state_machine.o + build/can.o +sm_init build/state_machine.o + build/main.o +sm_powerground_manager build/state_machine.o +sm_precharge_discharge_manager build/state_machine.o +sm_program_powerground build/state_machine.o + build/main.o +sm_return_cell_temperature build/state_machine.o +sm_return_cell_voltage build/state_machine.o +sm_set_error_source build/state_machine.o +sm_set_relay build/state_machine.o +sm_set_relay_positions build/state_machine.o +sm_test_cycle_states build/state_machine.o +sm_update build/state_machine.o + build/main.o +sm_update_active build/state_machine.o +sm_update_charging build/state_machine.o +sm_update_charging_precharge build/state_machine.o +sm_update_discharge build/state_machine.o +sm_update_error build/state_machine.o +sm_update_inactive build/state_machine.o +sm_update_precharge build/state_machine.o +sm_update_ready build/state_machine.o +soc_before_current build/soc_estimation.o +soc_for_ocv build/soc_estimation.o +soc_init build/soc_estimation.o + build/main.o +soc_update build/soc_estimation.o + build/state_machine.o +software_init_hook /nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/bin/../lib/gcc/arm-none-eabi/13.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o +state build/state_machine.o + build/status_LED.o + build/eeprom.o + build/can.o + build/TMP1075.o +status_led_init build/status_LED.o + build/main.o +status_led_set build/status_LED.o +status_led_set_color build/status_LED.o +status_led_update build/status_LED.o + build/state_machine.o +target_powerground_status build/state_machine.o + build/PWM_control.o +tmp1075_failed_sensors build/TMP1075.o +tmp1075_init build/TMP1075.o + build/main.o +tmp1075_measure build/TMP1075.o + build/state_machine.o +tmp1075_sensor_init build/TMP1075.o +tmp1075_sensor_read build/TMP1075.o +tmp1075_temps build/TMP1075.o + build/state_machine.o + build/eeprom.o + build/can.o +updateCommandPEC build/ADBMS_LL_Driver.o +updateDataPEC build/ADBMS_LL_Driver.o +uwTick build/stm32f3xx_hal.o +uwTickFreq build/stm32f3xx_hal.o +uwTickPrio build/stm32f3xx_hal.o + build/stm32f3xx_hal_rcc.o +writeCMD build/ADBMS_LL_Driver.o + build/ADBMS_Abstraction.o +write_address build/eeprom.o diff --git a/Software/build/soc_estimation.d b/Software/build/soc_estimation.d new file mode 100644 index 0000000..75846cd --- /dev/null +++ b/Software/build/soc_estimation.d @@ -0,0 +1,89 @@ +build/soc_estimation.o: Core/Src/soc_estimation.c \ + Core/Inc/soc_estimation.h Core/Inc/state_machine.h \ + Core/Inc/ADBMS_LL_Driver.h Core/Inc/main.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + Core/Inc/stm32f3xx_hal_conf.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h \ + Core/Inc/AMS_HighLevel.h Core/Inc/ADBMS_Abstraction.h \ + Core/Inc/ADBMS_CMD_MAKROS.h Core/Lib/can-halal/can-halal.h \ + Core/Inc/errors.h Core/Inc/can.h Core/Inc/eeprom.h \ + Core/Inc/soc_estimation.h Core/Inc/state_machine.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h Core/Inc/TMP1075.h \ + Core/Inc/errors.h Core/Inc/PWM_control.h Core/Inc/status_LED.h \ + Core/Inc/TMP1075.h +Core/Inc/soc_estimation.h: +Core/Inc/state_machine.h: +Core/Inc/ADBMS_LL_Driver.h: +Core/Inc/main.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h: +Core/Inc/AMS_HighLevel.h: +Core/Inc/ADBMS_Abstraction.h: +Core/Inc/ADBMS_CMD_MAKROS.h: +Core/Lib/can-halal/can-halal.h: +Core/Inc/errors.h: +Core/Inc/can.h: +Core/Inc/eeprom.h: +Core/Inc/soc_estimation.h: +Core/Inc/state_machine.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Core/Inc/TMP1075.h: +Core/Inc/errors.h: +Core/Inc/PWM_control.h: +Core/Inc/status_LED.h: +Core/Inc/TMP1075.h: diff --git a/Software/build/soc_estimation.lst b/Software/build/soc_estimation.lst new file mode 100644 index 0000000..2a1af18 --- /dev/null +++ b/Software/build/soc_estimation.lst @@ -0,0 +1,603 @@ +ARM GAS /tmp/ccSOWY3y.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 6 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "soc_estimation.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Core/Src/soc_estimation.c" + 20 .global OCV_SOC_PAIRS + 21 .section .data.OCV_SOC_PAIRS,"aw" + 22 .align 2 + 25 OCV_SOC_PAIRS: + 26 0000 B80B .short 3000 + 27 0002 0000 .space 2 + 28 0004 00000000 .word 0 + 29 0008 160D .short 3350 + 30 000a 0000 .space 2 + 31 000c 00002041 .word 1092616192 + 32 0010 7A0D .short 3450 + 33 0012 0000 .space 2 + 34 0014 0000A041 .word 1101004800 + 35 0018 AC0D .short 3500 + 36 001a 0000 .space 2 + 37 001c 0000F041 .word 1106247680 + 38 0020 CA0D .short 3530 + 39 0022 0000 .space 2 + 40 0024 00002042 .word 1109393408 + 41 0028 F20D .short 3570 + 42 002a 0000 .space 2 + 43 002c 00004842 .word 1112014848 + 44 0030 100E .short 3600 + 45 0032 0000 .space 2 + 46 0034 00007042 .word 1114636288 + 47 0038 2E0E .short 3630 + 48 003a 0000 .space 2 + 49 003c 00008C42 .word 1116471296 + 50 0040 740E .short 3700 + 51 0042 0000 .space 2 + 52 0044 0000A042 .word 1117782016 + 53 0048 D80E .short 3800 + 54 004a 0000 .space 2 + 55 004c 0000B442 .word 1119092736 + 56 0050 2210 .short 4130 + 57 0052 0000 .space 2 + 58 0054 0000C842 .word 1120403456 + 59 .global current_soc + ARM GAS /tmp/ccSOWY3y.s page 2 + + + 60 .section .bss.current_soc,"aw",%nobits + 61 .align 2 + 64 current_soc: + 65 0000 00000000 .space 4 + 66 .global current_was_flowing + 67 .section .bss.current_was_flowing,"aw",%nobits + 68 .align 2 + 71 current_was_flowing: + 72 0000 00000000 .space 4 + 73 .global last_current_time + 74 .section .bss.last_current_time,"aw",%nobits + 75 .align 2 + 78 last_current_time: + 79 0000 00000000 .space 4 + 80 .global soc_before_current + 81 .section .bss.soc_before_current,"aw",%nobits + 82 .align 2 + 85 soc_before_current: + 86 0000 00000000 .space 4 + 87 .global mAs_before_current + 88 .section .bss.mAs_before_current,"aw",%nobits + 89 .align 2 + 92 mAs_before_current: + 93 0000 00000000 .space 4 + 94 .section .text.soc_init,"ax",%progbits + 95 .align 1 + 96 .global soc_init + 97 .syntax unified + 98 .thumb + 99 .thumb_func + 101 soc_init: + 102 .LFB130: + 1:Core/Src/soc_estimation.c **** #include "soc_estimation.h" + 2:Core/Src/soc_estimation.c **** #include + 3:Core/Src/soc_estimation.c **** + 4:Core/Src/soc_estimation.c **** #define SOC_ESTIMATION_NO_CURRENT_THRESH 1000 // mA + 5:Core/Src/soc_estimation.c **** #define SOC_ESTIMATION_NO_CURRENT_TIME 100000 // ms + 6:Core/Src/soc_estimation.c **** #define SOC_ESTIMATION_BATTERY_CAPACITY 28800 // mAs + 7:Core/Src/soc_estimation.c **** + 8:Core/Src/soc_estimation.c **** #define MIN_CELL_VOLTAGE 3000 + 9:Core/Src/soc_estimation.c **** #define MAX_CELL_VOLTAGE 4130 + 10:Core/Src/soc_estimation.c **** + 11:Core/Src/soc_estimation.c **** + 12:Core/Src/soc_estimation.c **** // https://www.desmos.com/calculator/mm22vmxl2x + 13:Core/Src/soc_estimation.c **** ocv_soc_pair_t OCV_SOC_PAIRS[] = { + 14:Core/Src/soc_estimation.c **** {3000, 0.00f}, {3350, 10.00f}, {3450, 20.00f}, + 15:Core/Src/soc_estimation.c **** {3500, 30.00f}, {3530, 40.00f}, {3570, 50.00f}, + 16:Core/Src/soc_estimation.c **** {3600, 60.00f}, {3630, 70.00f}, {3700, 80.00f}, + 17:Core/Src/soc_estimation.c **** {3800, 90.00f}, {4130, 100.00f} + 18:Core/Src/soc_estimation.c **** }; + 19:Core/Src/soc_estimation.c **** + 20:Core/Src/soc_estimation.c **** float current_soc; + 21:Core/Src/soc_estimation.c **** + 22:Core/Src/soc_estimation.c **** int current_was_flowing; + 23:Core/Src/soc_estimation.c **** uint32_t last_current_time; + 24:Core/Src/soc_estimation.c **** float soc_before_current; + 25:Core/Src/soc_estimation.c **** float mAs_before_current; + ARM GAS /tmp/ccSOWY3y.s page 3 + + + 26:Core/Src/soc_estimation.c **** + 27:Core/Src/soc_estimation.c **** void soc_init() { + 103 .loc 1 27 17 + 104 .cfi_startproc + 105 @ args = 0, pretend = 0, frame = 0 + 106 @ frame_needed = 1, uses_anonymous_args = 0 + 107 @ link register save eliminated. + 108 0000 80B4 push {r7} + 109 .cfi_def_cfa_offset 4 + 110 .cfi_offset 7, -4 + 111 0002 00AF add r7, sp, #0 + 112 .cfi_def_cfa_register 7 + 28:Core/Src/soc_estimation.c **** current_soc = 0; + 113 .loc 1 28 15 + 114 0004 074B ldr r3, .L2 + 115 0006 4FF00002 mov r2, #0 + 116 000a 1A60 str r2, [r3] @ float + 29:Core/Src/soc_estimation.c **** last_current_time = 0; + 117 .loc 1 29 21 + 118 000c 064B ldr r3, .L2+4 + 119 000e 0022 movs r2, #0 + 120 0010 1A60 str r2, [r3] + 30:Core/Src/soc_estimation.c **** current_was_flowing = 1; + 121 .loc 1 30 23 + 122 0012 064B ldr r3, .L2+8 + 123 0014 0122 movs r2, #1 + 124 0016 1A60 str r2, [r3] + 31:Core/Src/soc_estimation.c **** } + 125 .loc 1 31 1 + 126 0018 00BF nop + 127 001a BD46 mov sp, r7 + 128 .cfi_def_cfa_register 13 + 129 @ sp needed + 130 001c 5DF8047B ldr r7, [sp], #4 + 131 .cfi_restore 7 + 132 .cfi_def_cfa_offset 0 + 133 0020 7047 bx lr + 134 .L3: + 135 0022 00BF .align 2 + 136 .L2: + 137 0024 00000000 .word current_soc + 138 0028 00000000 .word last_current_time + 139 002c 00000000 .word current_was_flowing + 140 .cfi_endproc + 141 .LFE130: + 143 .section .text.soc_update,"ax",%progbits + 144 .align 1 + 145 .global soc_update + 146 .syntax unified + 147 .thumb + 148 .thumb_func + 150 soc_update: + 151 .LFB131: + 32:Core/Src/soc_estimation.c **** + 33:Core/Src/soc_estimation.c **** void soc_update() { + 152 .loc 1 33 19 + 153 .cfi_startproc + ARM GAS /tmp/ccSOWY3y.s page 4 + + + 154 @ args = 0, pretend = 0, frame = 16 + 155 @ frame_needed = 1, uses_anonymous_args = 0 + 156 0000 80B5 push {r7, lr} + 157 .cfi_def_cfa_offset 8 + 158 .cfi_offset 7, -8 + 159 .cfi_offset 14, -4 + 160 0002 84B0 sub sp, sp, #16 + 161 .cfi_def_cfa_offset 24 + 162 0004 00AF add r7, sp, #0 + 163 .cfi_def_cfa_register 7 + 34:Core/Src/soc_estimation.c **** uint32_t now = HAL_GetTick(); + 164 .loc 1 34 18 + 165 0006 FFF7FEFF bl HAL_GetTick + 166 000a F860 str r0, [r7, #12] + 35:Core/Src/soc_estimation.c **** if (CURRENT_MEASUREMENT >= SOC_ESTIMATION_NO_CURRENT_THRESH) { + 167 .loc 1 35 27 + 168 000c 334B ldr r3, .L11 + 169 000e 1B68 ldr r3, [r3] + 170 .loc 1 35 6 + 171 0010 B3F57A7F cmp r3, #1000 + 172 0014 17DB blt .L5 + 36:Core/Src/soc_estimation.c **** last_current_time = now; + 173 .loc 1 36 23 + 174 0016 324A ldr r2, .L11+4 + 175 0018 FB68 ldr r3, [r7, #12] + 176 001a 1360 str r3, [r2] + 37:Core/Src/soc_estimation.c **** if (!current_was_flowing) { + 177 .loc 1 37 9 + 178 001c 314B ldr r3, .L11+8 + 179 001e 1B68 ldr r3, [r3] + 180 .loc 1 37 8 + 181 0020 002B cmp r3, #0 + 182 0022 0CD1 bne .L6 + 38:Core/Src/soc_estimation.c **** soc_before_current = current_soc; + 183 .loc 1 38 26 + 184 0024 304B ldr r3, .L11+12 + 185 0026 1B68 ldr r3, [r3] @ float + 186 0028 304A ldr r2, .L11+16 + 187 002a 1360 str r3, [r2] @ float + 39:Core/Src/soc_estimation.c **** mAs_before_current = CURRENT_MEASUREMENT; + 188 .loc 1 39 26 + 189 002c 2B4B ldr r3, .L11 + 190 002e 1B68 ldr r3, [r3] + 191 0030 07EE903A vmov s15, r3 @ int + 192 0034 F8EEE77A vcvt.f32.s32 s15, s15 + 193 0038 2D4B ldr r3, .L11+20 + 194 003a C3ED007A vstr.32 s15, [r3] + 195 .L6: + 40:Core/Src/soc_estimation.c **** } + 41:Core/Src/soc_estimation.c **** current_was_flowing = 1; + 196 .loc 1 41 25 + 197 003e 294B ldr r3, .L11+8 + 198 0040 0122 movs r2, #1 + 199 0042 1A60 str r2, [r3] + 200 0044 02E0 b .L7 + 201 .L5: + 42:Core/Src/soc_estimation.c **** } else { + ARM GAS /tmp/ccSOWY3y.s page 5 + + + 43:Core/Src/soc_estimation.c **** current_was_flowing = 0; + 202 .loc 1 43 25 + 203 0046 274B ldr r3, .L11+8 + 204 0048 0022 movs r2, #0 + 205 004a 1A60 str r2, [r3] + 206 .L7: + 44:Core/Src/soc_estimation.c **** } + 45:Core/Src/soc_estimation.c **** + 46:Core/Src/soc_estimation.c **** if (now - last_current_time >= SOC_ESTIMATION_NO_CURRENT_TIME || + 207 .loc 1 46 11 + 208 004c 244B ldr r3, .L11+4 + 209 004e 1B68 ldr r3, [r3] + 210 0050 FA68 ldr r2, [r7, #12] + 211 0052 D31A subs r3, r2, r3 + 212 .loc 1 46 6 + 213 0054 274A ldr r2, .L11+24 + 214 0056 9342 cmp r3, r2 + 215 0058 03D8 bhi .L8 + 47:Core/Src/soc_estimation.c **** last_current_time == 0) { + 216 .loc 1 47 25 + 217 005a 214B ldr r3, .L11+4 + 218 005c 1B68 ldr r3, [r3] + 46:Core/Src/soc_estimation.c **** last_current_time == 0) { + 219 .loc 1 46 65 discriminator 1 + 220 005e 002B cmp r3, #0 + 221 0060 13D1 bne .L9 + 222 .L8: + 223 .LBB2: + 48:Core/Src/soc_estimation.c **** // Assume we're measuring OCV if there's been no current for a while (or + 49:Core/Src/soc_estimation.c **** // we've just turned on the battery). + 50:Core/Src/soc_estimation.c **** uint8_t id = 0; + 224 .loc 1 50 13 + 225 0062 0023 movs r3, #0 + 226 0064 FB70 strb r3, [r7, #3] + 51:Core/Src/soc_estimation.c **** uint16_t min_voltage = 0; + 227 .loc 1 51 14 + 228 0066 0023 movs r3, #0 + 229 0068 3B80 strh r3, [r7] @ movhi + 52:Core/Src/soc_estimation.c **** sm_check_battery_temperature(&id, &min_voltage); + 230 .loc 1 52 5 + 231 006a 3A46 mov r2, r7 + 232 006c FB1C adds r3, r7, #3 + 233 006e 1146 mov r1, r2 + 234 0070 1846 mov r0, r3 + 235 0072 FFF7FEFF bl sm_check_battery_temperature + 53:Core/Src/soc_estimation.c **** current_soc = soc_for_ocv(min_voltage); + 236 .loc 1 53 19 + 237 0076 3B88 ldrh r3, [r7] + 238 0078 1846 mov r0, r3 + 239 007a FFF7FEFF bl soc_for_ocv + 240 007e F0EE407A vmov.f32 s15, s0 + 241 .loc 1 53 17 discriminator 1 + 242 0082 194B ldr r3, .L11+12 + 243 0084 C3ED007A vstr.32 s15, [r3] + 244 .LBE2: + 47:Core/Src/soc_estimation.c **** // Assume we're measuring OCV if there's been no current for a while (or + 245 .loc 1 47 31 + ARM GAS /tmp/ccSOWY3y.s page 6 + + + 246 0088 23E0 b .L10 + 247 .L9: + 248 .LBB3: + 54:Core/Src/soc_estimation.c **** } else { + 55:Core/Src/soc_estimation.c **** // Otherwise, use the current counter to update SoC + 56:Core/Src/soc_estimation.c **** float as_delta = CURRENT_MEASUREMENT - mAs_before_current; + 249 .loc 1 56 43 + 250 008a 144B ldr r3, .L11 + 251 008c 1B68 ldr r3, [r3] + 252 008e 07EE903A vmov s15, r3 @ int + 253 0092 B8EEE77A vcvt.f32.s32 s14, s15 + 254 0096 164B ldr r3, .L11+20 + 255 0098 D3ED007A vldr.32 s15, [r3] + 256 .loc 1 56 11 + 257 009c 77EE677A vsub.f32 s15, s14, s15 + 258 00a0 C7ED027A vstr.32 s15, [r7, #8] + 57:Core/Src/soc_estimation.c **** float soc_delta = as_delta / SOC_ESTIMATION_BATTERY_CAPACITY * 100; + 259 .loc 1 57 32 + 260 00a4 97ED027A vldr.32 s14, [r7, #8] + 261 00a8 DFED136A vldr.32 s13, .L11+28 + 262 00ac C7EE267A vdiv.f32 s15, s14, s13 + 263 .loc 1 57 11 + 264 00b0 9FED127A vldr.32 s14, .L11+32 + 265 00b4 67EE877A vmul.f32 s15, s15, s14 + 266 00b8 C7ED017A vstr.32 s15, [r7, #4] + 58:Core/Src/soc_estimation.c **** current_soc = soc_before_current + soc_delta; + 267 .loc 1 58 38 + 268 00bc 0B4B ldr r3, .L11+16 + 269 00be 93ED007A vldr.32 s14, [r3] + 270 00c2 D7ED017A vldr.32 s15, [r7, #4] + 271 00c6 77EE277A vadd.f32 s15, s14, s15 + 272 .loc 1 58 17 + 273 00ca 074B ldr r3, .L11+12 + 274 00cc C3ED007A vstr.32 s15, [r3] + 275 .LBE3: + 59:Core/Src/soc_estimation.c **** } + 60:Core/Src/soc_estimation.c **** } + 276 .loc 1 60 1 + 277 00d0 00BF nop + 278 .L10: + 279 00d2 00BF nop + 280 00d4 1037 adds r7, r7, #16 + 281 .cfi_def_cfa_offset 8 + 282 00d6 BD46 mov sp, r7 + 283 .cfi_def_cfa_register 13 + 284 @ sp needed + 285 00d8 80BD pop {r7, pc} + 286 .L12: + 287 00da 00BF .align 2 + 288 .L11: + 289 00dc 00000000 .word CURRENT_MEASUREMENT + 290 00e0 00000000 .word last_current_time + 291 00e4 00000000 .word current_was_flowing + 292 00e8 00000000 .word current_soc + 293 00ec 00000000 .word soc_before_current + 294 00f0 00000000 .word mAs_before_current + 295 00f4 9F860100 .word 99999 + ARM GAS /tmp/ccSOWY3y.s page 7 + + + 296 00f8 0000E146 .word 1189150720 + 297 00fc 0000C842 .word 1120403456 + 298 .cfi_endproc + 299 .LFE131: + 301 .section .text.soc_for_ocv,"ax",%progbits + 302 .align 1 + 303 .global soc_for_ocv + 304 .syntax unified + 305 .thumb + 306 .thumb_func + 308 soc_for_ocv: + 309 .LFB132: + 61:Core/Src/soc_estimation.c **** + 62:Core/Src/soc_estimation.c **** float soc_for_ocv(uint16_t ocv) { + 310 .loc 1 62 33 + 311 .cfi_startproc + 312 @ args = 0, pretend = 0, frame = 40 + 313 @ frame_needed = 1, uses_anonymous_args = 0 + 314 @ link register save eliminated. + 315 0000 80B4 push {r7} + 316 .cfi_def_cfa_offset 4 + 317 .cfi_offset 7, -4 + 318 0002 8BB0 sub sp, sp, #44 + 319 .cfi_def_cfa_offset 48 + 320 0004 00AF add r7, sp, #0 + 321 .cfi_def_cfa_register 7 + 322 0006 0346 mov r3, r0 + 323 0008 FB80 strh r3, [r7, #6] @ movhi + 63:Core/Src/soc_estimation.c **** size_t i = 0; + 324 .loc 1 63 10 + 325 000a 0023 movs r3, #0 + 326 000c 7B62 str r3, [r7, #36] + 64:Core/Src/soc_estimation.c **** size_t array_length = sizeof(OCV_SOC_PAIRS) / sizeof(*OCV_SOC_PAIRS); + 327 .loc 1 64 10 + 328 000e 0B23 movs r3, #11 + 329 0010 3B62 str r3, [r7, #32] + 65:Core/Src/soc_estimation.c **** // Find the index of the first element with OCV greater than the target OCV + 66:Core/Src/soc_estimation.c **** while (i < array_length && OCV_SOC_PAIRS[i].ocv <= ocv) { + 330 .loc 1 66 9 + 331 0012 02E0 b .L14 + 332 .L16: + 67:Core/Src/soc_estimation.c **** i++; + 333 .loc 1 67 6 + 334 0014 7B6A ldr r3, [r7, #36] + 335 0016 0133 adds r3, r3, #1 + 336 0018 7B62 str r3, [r7, #36] + 337 .L14: + 66:Core/Src/soc_estimation.c **** i++; + 338 .loc 1 66 27 + 339 001a 7A6A ldr r2, [r7, #36] + 340 001c 3B6A ldr r3, [r7, #32] + 341 001e 9A42 cmp r2, r3 + 342 0020 06D2 bcs .L15 + 66:Core/Src/soc_estimation.c **** i++; + 343 .loc 1 66 46 discriminator 1 + 344 0022 2F4A ldr r2, .L20 + 345 0024 7B6A ldr r3, [r7, #36] + ARM GAS /tmp/ccSOWY3y.s page 8 + + + 346 0026 32F83330 ldrh r3, [r2, r3, lsl #3] + 66:Core/Src/soc_estimation.c **** i++; + 347 .loc 1 66 27 discriminator 1 + 348 002a FA88 ldrh r2, [r7, #6] + 349 002c 9A42 cmp r2, r3 + 350 002e F1D2 bcs .L16 + 351 .L15: + 68:Core/Src/soc_estimation.c **** } + 69:Core/Src/soc_estimation.c **** + 70:Core/Src/soc_estimation.c **** // If the target OCV is lower than the smallest OCV in the array, return the + 71:Core/Src/soc_estimation.c **** // first SOC value + 72:Core/Src/soc_estimation.c **** if (i == 0) { + 352 .loc 1 72 6 + 353 0030 7B6A ldr r3, [r7, #36] + 354 0032 002B cmp r3, #0 + 355 0034 02D1 bne .L17 + 73:Core/Src/soc_estimation.c **** return OCV_SOC_PAIRS[0].soc; + 356 .loc 1 73 28 + 357 0036 2A4B ldr r3, .L20 + 358 0038 5B68 ldr r3, [r3, #4] @ float + 359 003a 48E0 b .L18 + 360 .L17: + 74:Core/Src/soc_estimation.c **** } + 75:Core/Src/soc_estimation.c **** + 76:Core/Src/soc_estimation.c **** // If the target OCV is higher than the largest OCV in the array, return the + 77:Core/Src/soc_estimation.c **** // last SOC value + 78:Core/Src/soc_estimation.c **** if (i == array_length) { + 361 .loc 1 78 6 + 362 003c 7A6A ldr r2, [r7, #36] + 363 003e 3B6A ldr r3, [r7, #32] + 364 0040 9A42 cmp r2, r3 + 365 0042 07D1 bne .L19 + 79:Core/Src/soc_estimation.c **** return OCV_SOC_PAIRS[array_length - 1].soc; + 366 .loc 1 79 39 + 367 0044 3B6A ldr r3, [r7, #32] + 368 0046 013B subs r3, r3, #1 + 369 .loc 1 79 43 + 370 0048 254A ldr r2, .L20 + 371 004a DB00 lsls r3, r3, #3 + 372 004c 1344 add r3, r3, r2 + 373 004e 0433 adds r3, r3, #4 + 374 0050 1B68 ldr r3, [r3] @ float + 375 0052 3CE0 b .L18 + 376 .L19: + 80:Core/Src/soc_estimation.c **** } + 81:Core/Src/soc_estimation.c **** + 82:Core/Src/soc_estimation.c **** // Perform linear interpolation + 83:Core/Src/soc_estimation.c **** uint16_t ocv1 = OCV_SOC_PAIRS[i - 1].ocv; + 377 .loc 1 83 35 + 378 0054 7B6A ldr r3, [r7, #36] + 379 0056 013B subs r3, r3, #1 + 380 .loc 1 83 12 + 381 0058 214A ldr r2, .L20 + 382 005a 32F83330 ldrh r3, [r2, r3, lsl #3] @ movhi + 383 005e FB83 strh r3, [r7, #30] @ movhi + 84:Core/Src/soc_estimation.c **** uint16_t ocv2 = OCV_SOC_PAIRS[i].ocv; + 384 .loc 1 84 12 + ARM GAS /tmp/ccSOWY3y.s page 9 + + + 385 0060 1F4A ldr r2, .L20 + 386 0062 7B6A ldr r3, [r7, #36] + 387 0064 32F83330 ldrh r3, [r2, r3, lsl #3] @ movhi + 388 0068 BB83 strh r3, [r7, #28] @ movhi + 85:Core/Src/soc_estimation.c **** float soc1 = OCV_SOC_PAIRS[i - 1].soc; + 389 .loc 1 85 32 + 390 006a 7B6A ldr r3, [r7, #36] + 391 006c 013B subs r3, r3, #1 + 392 .loc 1 85 9 + 393 006e 1C4A ldr r2, .L20 + 394 0070 DB00 lsls r3, r3, #3 + 395 0072 1344 add r3, r3, r2 + 396 0074 0433 adds r3, r3, #4 + 397 0076 1B68 ldr r3, [r3] @ float + 398 0078 BB61 str r3, [r7, #24] @ float + 86:Core/Src/soc_estimation.c **** float soc2 = OCV_SOC_PAIRS[i].soc; + 399 .loc 1 86 9 + 400 007a 194A ldr r2, .L20 + 401 007c 7B6A ldr r3, [r7, #36] + 402 007e DB00 lsls r3, r3, #3 + 403 0080 1344 add r3, r3, r2 + 404 0082 0433 adds r3, r3, #4 + 405 0084 1B68 ldr r3, [r3] @ float + 406 0086 7B61 str r3, [r7, #20] @ float + 87:Core/Src/soc_estimation.c **** + 88:Core/Src/soc_estimation.c **** float slope = (soc2 - soc1) / (ocv2 - ocv1); + 407 .loc 1 88 23 + 408 0088 97ED057A vldr.32 s14, [r7, #20] + 409 008c D7ED067A vldr.32 s15, [r7, #24] + 410 0090 77EE676A vsub.f32 s13, s14, s15 + 411 .loc 1 88 39 + 412 0094 BA8B ldrh r2, [r7, #28] + 413 0096 FB8B ldrh r3, [r7, #30] + 414 0098 D31A subs r3, r2, r3 + 415 .loc 1 88 31 + 416 009a 07EE903A vmov s15, r3 @ int + 417 009e B8EEE77A vcvt.f32.s32 s14, s15 + 418 .loc 1 88 9 + 419 00a2 C6EE877A vdiv.f32 s15, s13, s14 + 420 00a6 C7ED047A vstr.32 s15, [r7, #16] + 89:Core/Src/soc_estimation.c **** float interpolated_soc = soc1 + slope * (ocv - ocv1); + 421 .loc 1 89 48 + 422 00aa FA88 ldrh r2, [r7, #6] + 423 00ac FB8B ldrh r3, [r7, #30] + 424 00ae D31A subs r3, r2, r3 + 425 .loc 1 89 41 + 426 00b0 07EE903A vmov s15, r3 @ int + 427 00b4 B8EEE77A vcvt.f32.s32 s14, s15 + 428 00b8 D7ED047A vldr.32 s15, [r7, #16] + 429 00bc 67EE277A vmul.f32 s15, s14, s15 + 430 .loc 1 89 9 + 431 00c0 97ED067A vldr.32 s14, [r7, #24] + 432 00c4 77EE277A vadd.f32 s15, s14, s15 + 433 00c8 C7ED037A vstr.32 s15, [r7, #12] + 90:Core/Src/soc_estimation.c **** + 91:Core/Src/soc_estimation.c **** return interpolated_soc; + 434 .loc 1 91 10 + ARM GAS /tmp/ccSOWY3y.s page 10 + + + 435 00cc FB68 ldr r3, [r7, #12] @ float + 436 .L18: + 92:Core/Src/soc_estimation.c **** } + 437 .loc 1 92 1 + 438 00ce 07EE903A vmov s15, r3 + 439 00d2 B0EE670A vmov.f32 s0, s15 + 440 00d6 2C37 adds r7, r7, #44 + 441 .cfi_def_cfa_offset 4 + 442 00d8 BD46 mov sp, r7 + 443 .cfi_def_cfa_register 13 + 444 @ sp needed + 445 00da 5DF8047B ldr r7, [sp], #4 + 446 .cfi_restore 7 + 447 .cfi_def_cfa_offset 0 + 448 00de 7047 bx lr + 449 .L21: + 450 .align 2 + 451 .L20: + 452 00e0 00000000 .word OCV_SOC_PAIRS + 453 .cfi_endproc + 454 .LFE132: + 456 .text + 457 .Letext0: + 458 .file 2 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 459 .file 3 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 460 .file 4 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/lib/gcc/arm-none-e + 461 .file 5 "Core/Inc/state_machine.h" + 462 .file 6 "Core/Inc/soc_estimation.h" + 463 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h" + ARM GAS /tmp/ccSOWY3y.s page 11 + + +DEFINED SYMBOLS + *ABS*:00000000 soc_estimation.c + /tmp/ccSOWY3y.s:25 .data.OCV_SOC_PAIRS:00000000 OCV_SOC_PAIRS + /tmp/ccSOWY3y.s:22 .data.OCV_SOC_PAIRS:00000000 $d + /tmp/ccSOWY3y.s:64 .bss.current_soc:00000000 current_soc + /tmp/ccSOWY3y.s:61 .bss.current_soc:00000000 $d + /tmp/ccSOWY3y.s:71 .bss.current_was_flowing:00000000 current_was_flowing + /tmp/ccSOWY3y.s:68 .bss.current_was_flowing:00000000 $d + /tmp/ccSOWY3y.s:78 .bss.last_current_time:00000000 last_current_time + /tmp/ccSOWY3y.s:75 .bss.last_current_time:00000000 $d + /tmp/ccSOWY3y.s:85 .bss.soc_before_current:00000000 soc_before_current + /tmp/ccSOWY3y.s:82 .bss.soc_before_current:00000000 $d + /tmp/ccSOWY3y.s:92 .bss.mAs_before_current:00000000 mAs_before_current + /tmp/ccSOWY3y.s:89 .bss.mAs_before_current:00000000 $d + /tmp/ccSOWY3y.s:95 .text.soc_init:00000000 $t + /tmp/ccSOWY3y.s:101 .text.soc_init:00000000 soc_init + /tmp/ccSOWY3y.s:137 .text.soc_init:00000024 $d + /tmp/ccSOWY3y.s:144 .text.soc_update:00000000 $t + /tmp/ccSOWY3y.s:150 .text.soc_update:00000000 soc_update + /tmp/ccSOWY3y.s:308 .text.soc_for_ocv:00000000 soc_for_ocv + /tmp/ccSOWY3y.s:289 .text.soc_update:000000dc $d + /tmp/ccSOWY3y.s:302 .text.soc_for_ocv:00000000 $t + /tmp/ccSOWY3y.s:452 .text.soc_for_ocv:000000e0 $d + +UNDEFINED SYMBOLS +HAL_GetTick +sm_check_battery_temperature +CURRENT_MEASUREMENT diff --git a/Software/build/soc_estimation.o b/Software/build/soc_estimation.o new file mode 100644 index 0000000..84cfe51 Binary files /dev/null and b/Software/build/soc_estimation.o differ diff --git a/Software/build/startup_stm32f302xc.d b/Software/build/startup_stm32f302xc.d new file mode 100644 index 0000000..3a580d3 --- /dev/null +++ b/Software/build/startup_stm32f302xc.d @@ -0,0 +1 @@ +build/startup_stm32f302xc.o: startup_stm32f302xc.s diff --git a/Software/build/startup_stm32f302xc.o b/Software/build/startup_stm32f302xc.o new file mode 100644 index 0000000..9fdbacb Binary files /dev/null and b/Software/build/startup_stm32f302xc.o differ diff --git a/Software/build/state_machine.d b/Software/build/state_machine.d new file mode 100644 index 0000000..3ac3b59 --- /dev/null +++ b/Software/build/state_machine.d @@ -0,0 +1,88 @@ +build/state_machine.o: Core/Src/state_machine.c Core/Inc/state_machine.h \ + Core/Inc/ADBMS_LL_Driver.h Core/Inc/main.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + Core/Inc/stm32f3xx_hal_conf.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h \ + Core/Inc/AMS_HighLevel.h Core/Inc/ADBMS_Abstraction.h \ + Core/Inc/ADBMS_CMD_MAKROS.h Core/Lib/can-halal/can-halal.h \ + Core/Inc/errors.h Core/Inc/can.h Core/Inc/state_machine.h \ + Core/Inc/eeprom.h Core/Inc/soc_estimation.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h Core/Inc/TMP1075.h \ + Core/Inc/errors.h Core/Inc/PWM_control.h Core/Inc/status_LED.h \ + Core/Inc/TMP1075.h Core/Inc/ADBMS_Abstraction.h +Core/Inc/state_machine.h: +Core/Inc/ADBMS_LL_Driver.h: +Core/Inc/main.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h: +Core/Inc/AMS_HighLevel.h: +Core/Inc/ADBMS_Abstraction.h: +Core/Inc/ADBMS_CMD_MAKROS.h: +Core/Lib/can-halal/can-halal.h: +Core/Inc/errors.h: +Core/Inc/can.h: +Core/Inc/state_machine.h: +Core/Inc/eeprom.h: +Core/Inc/soc_estimation.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Core/Inc/TMP1075.h: +Core/Inc/errors.h: +Core/Inc/PWM_control.h: +Core/Inc/status_LED.h: +Core/Inc/TMP1075.h: +Core/Inc/ADBMS_Abstraction.h: diff --git a/Software/build/state_machine.lst b/Software/build/state_machine.lst new file mode 100644 index 0000000..8f43fbe --- /dev/null +++ b/Software/build/state_machine.lst @@ -0,0 +1,3913 @@ +ARM GAS /tmp/cctkPVvk.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 6 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "state_machine.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Core/Src/state_machine.c" + 20 .global programming_mode + 21 .section .bss.programming_mode,"aw",%nobits + 24 programming_mode: + 25 0000 00 .space 1 + 26 .global debugging_mode + 27 .section .bss.debugging_mode,"aw",%nobits + 30 debugging_mode: + 31 0000 00 .space 1 + 32 .global state + 33 .section .bss.state,"aw",%nobits + 34 .align 2 + 37 state: + 38 0000 00000000 .space 6 + 38 0000 + 39 .global RELAY_BAT_SIDE_VOLTAGE + 40 .section .bss.RELAY_BAT_SIDE_VOLTAGE,"aw",%nobits + 41 .align 2 + 44 RELAY_BAT_SIDE_VOLTAGE: + 45 0000 00000000 .space 4 + 46 .global RELAY_ESC_SIDE_VOLTAGE + 47 .section .bss.RELAY_ESC_SIDE_VOLTAGE,"aw",%nobits + 48 .align 2 + 51 RELAY_ESC_SIDE_VOLTAGE: + 52 0000 00000000 .space 4 + 53 .global CURRENT_MEASUREMENT + 54 .section .bss.CURRENT_MEASUREMENT,"aw",%nobits + 55 .align 2 + 58 CURRENT_MEASUREMENT: + 59 0000 00000000 .space 4 + 60 .global CURRENT_MEASUREMENT_ON + 61 .section .bss.CURRENT_MEASUREMENT_ON,"aw",%nobits + 64 CURRENT_MEASUREMENT_ON: + 65 0000 00 .space 1 + 66 .global balancing_state + 67 .section .bss.balancing_state,"aw",%nobits + 70 balancing_state: + 71 0000 00 .space 1 + 72 .global base_offset + ARM GAS /tmp/cctkPVvk.s page 2 + + + 73 .section .bss.base_offset,"aw",%nobits + 74 .align 2 + 77 base_offset: + 78 0000 00000000 .space 4 + 79 .global error_timer + 80 .section .bss.error_timer,"aw",%nobits + 81 .align 2 + 84 error_timer: + 85 0000 00000000 .space 4 + 86 .global precharge_timer + 87 .section .bss.precharge_timer,"aw",%nobits + 88 .align 2 + 91 precharge_timer: + 92 0000 00000000 .space 4 + 93 .global discharge_timer + 94 .section .bss.discharge_timer,"aw",%nobits + 95 .align 2 + 98 discharge_timer: + 99 0000 00000000 .space 4 + 100 .global balancing_timer + 101 .section .bss.balancing_timer,"aw",%nobits + 102 .align 2 + 105 balancing_timer: + 106 0000 00000000 .space 4 + 107 .global eeprom_timer + 108 .section .bss.eeprom_timer,"aw",%nobits + 109 .align 2 + 112 eeprom_timer: + 113 0000 00000000 .space 4 + 114 .global powerground_softstart_timer + 115 .section .bss.powerground_softstart_timer,"aw",%nobits + 116 .align 2 + 119 powerground_softstart_timer: + 120 0000 00000000 .space 4 + 121 .global powerground_calibration_timer + 122 .section .bss.powerground_calibration_timer,"aw",%nobits + 123 .align 2 + 126 powerground_calibration_timer: + 127 0000 00000000 .space 4 + 128 .global powerground_calibration_stage + 129 .section .bss.powerground_calibration_stage,"aw",%nobits + 132 powerground_calibration_stage: + 133 0000 00 .space 1 + 134 .global current_powerground_status + 135 .section .bss.current_powerground_status,"aw",%nobits + 138 current_powerground_status: + 139 0000 00 .space 1 + 140 .global target_powerground_status + 141 .section .bss.target_powerground_status,"aw",%nobits + 144 target_powerground_status: + 145 0000 00 .space 1 + 146 .section .bss.timestamp,"aw",%nobits + 147 .align 2 + 150 timestamp: + 151 0000 00000000 .space 4 + 152 .section .text.sm_init,"ax",%progbits + 153 .align 1 + ARM GAS /tmp/cctkPVvk.s page 3 + + + 154 .global sm_init + 155 .syntax unified + 156 .thumb + 157 .thumb_func + 159 sm_init: + 160 .LFB130: + 1:Core/Src/state_machine.c **** /* + 2:Core/Src/state_machine.c **** * state_machine.h + 3:Core/Src/state_machine.c **** * + 4:Core/Src/state_machine.c **** * Created on: 07.07.2024 + 5:Core/Src/state_machine.c **** * Author: Hamza + 6:Core/Src/state_machine.c **** */ + 7:Core/Src/state_machine.c **** + 8:Core/Src/state_machine.c **** #include + 9:Core/Src/state_machine.c **** #include + 10:Core/Src/state_machine.c **** #include "ADBMS_Abstraction.h" + 11:Core/Src/state_machine.c **** #include "AMS_HighLevel.h" + 12:Core/Src/state_machine.c **** #include "PWM_control.h" + 13:Core/Src/state_machine.c **** #include "can.h" + 14:Core/Src/state_machine.c **** #include "eeprom.h" + 15:Core/Src/state_machine.c **** #include "stm32f3xx_hal.h" + 16:Core/Src/state_machine.c **** + 17:Core/Src/state_machine.c **** // Time to wait after reaching 95% of battery voltage before exiting precharge + 18:Core/Src/state_machine.c **** // Set this to 1000 in scruti to demonstrate the voltage on the multimeter + 19:Core/Src/state_machine.c **** #define PRECHARGE_DURATION 8000 // ms + 20:Core/Src/state_machine.c **** // Time to wait for discharge + 21:Core/Src/state_machine.c **** #define DISCHARGE_DURATION 8000 // ms + 22:Core/Src/state_machine.c **** // Time to wait between closing relays + 23:Core/Src/state_machine.c **** #define RELAY_CLOSE_WAIT 10 // ms + 24:Core/Src/state_machine.c **** // waiting time between to eeprom writes + 25:Core/Src/state_machine.c **** #define EEPROM_WRITE_FREQ 1000 + 26:Core/Src/state_machine.c **** // how delay between steps of 5 -> 15ms * (100/5) = 300ms + 27:Core/Src/state_machine.c **** #define POWERGROUND_SOFTSTART_INCREMENT_DELAY 15 + 28:Core/Src/state_machine.c **** // after errors are cleared wait for ERROR_LATCH_TIME ms before returning to inactive mode + 29:Core/Src/state_machine.c **** #define ERROR_LATCH_TIME 10000 //ms + 30:Core/Src/state_machine.c **** + 31:Core/Src/state_machine.c **** /* + 32:Core/Src/state_machine.c **** 10 + 33:Core/Src/state_machine.c **** 20 + 34:Core/Src/state_machine.c **** 30 + 35:Core/Src/state_machine.c **** 40 + 36:Core/Src/state_machine.c **** 50 + 37:Core/Src/state_machine.c **** 60 + 38:Core/Src/state_machine.c **** 70 + 39:Core/Src/state_machine.c **** 80 + 40:Core/Src/state_machine.c **** 90 + 41:Core/Src/state_machine.c **** 100 + 42:Core/Src/state_machine.c **** */ + 43:Core/Src/state_machine.c **** + 44:Core/Src/state_machine.c **** bool programming_mode; + 45:Core/Src/state_machine.c **** bool debugging_mode; + 46:Core/Src/state_machine.c **** + 47:Core/Src/state_machine.c **** StateHandle state; + 48:Core/Src/state_machine.c **** int32_t RELAY_BAT_SIDE_VOLTAGE; + 49:Core/Src/state_machine.c **** int32_t RELAY_ESC_SIDE_VOLTAGE; + 50:Core/Src/state_machine.c **** int32_t CURRENT_MEASUREMENT; + 51:Core/Src/state_machine.c **** bool CURRENT_MEASUREMENT_ON; + ARM GAS /tmp/cctkPVvk.s page 4 + + + 52:Core/Src/state_machine.c **** bool balancing_state; + 53:Core/Src/state_machine.c **** float base_offset = 0; + 54:Core/Src/state_machine.c **** + 55:Core/Src/state_machine.c **** uint32_t error_timer; + 56:Core/Src/state_machine.c **** uint32_t precharge_timer; + 57:Core/Src/state_machine.c **** uint32_t discharge_timer; + 58:Core/Src/state_machine.c **** uint32_t balancing_timer; + 59:Core/Src/state_machine.c **** uint32_t eeprom_timer; + 60:Core/Src/state_machine.c **** + 61:Core/Src/state_machine.c **** uint32_t powerground_softstart_timer; + 62:Core/Src/state_machine.c **** uint32_t powerground_calibration_timer; + 63:Core/Src/state_machine.c **** uint8_t powerground_calibration_stage; + 64:Core/Src/state_machine.c **** + 65:Core/Src/state_machine.c **** uint8_t current_powerground_status; + 66:Core/Src/state_machine.c **** uint8_t target_powerground_status; + 67:Core/Src/state_machine.c **** + 68:Core/Src/state_machine.c **** static uint32_t timestamp; + 69:Core/Src/state_machine.c **** + 70:Core/Src/state_machine.c **** void sm_init(){ + 161 .loc 1 70 15 + 162 .cfi_startproc + 163 @ args = 0, pretend = 0, frame = 0 + 164 @ frame_needed = 1, uses_anonymous_args = 0 + 165 @ link register save eliminated. + 166 0000 80B4 push {r7} + 167 .cfi_def_cfa_offset 4 + 168 .cfi_offset 7, -4 + 169 0002 00AF add r7, sp, #0 + 170 .cfi_def_cfa_register 7 + 71:Core/Src/state_machine.c **** state.current_state = STATE_INACTIVE; + 171 .loc 1 71 23 + 172 0004 164B ldr r3, .L2 + 173 0006 0022 movs r2, #0 + 174 0008 1A70 strb r2, [r3] + 72:Core/Src/state_machine.c **** state.target_state = STATE_INACTIVE; + 175 .loc 1 72 22 + 176 000a 154B ldr r3, .L2 + 177 000c 0022 movs r2, #0 + 178 000e 5A70 strb r2, [r3, #1] + 73:Core/Src/state_machine.c **** state.error_source = 0; + 179 .loc 1 73 22 + 180 0010 134B ldr r3, .L2 + 181 0012 0022 movs r2, #0 + 182 0014 5A80 strh r2, [r3, #2] @ movhi + 74:Core/Src/state_machine.c **** precharge_timer = discharge_timer = powerground_calibration_timer = error_timer = eeprom_timer = + 183 .loc 1 74 116 + 184 0016 134B ldr r3, .L2+4 + 185 0018 0022 movs r2, #0 + 186 001a 1A60 str r2, [r3] + 187 .loc 1 74 98 + 188 001c 114B ldr r3, .L2+4 + 189 001e 1B68 ldr r3, [r3] + 190 0020 114A ldr r2, .L2+8 + 191 0022 1360 str r3, [r2] + 192 .loc 1 74 83 + 193 0024 104B ldr r3, .L2+8 + 194 0026 1B68 ldr r3, [r3] + ARM GAS /tmp/cctkPVvk.s page 5 + + + 195 0028 104A ldr r2, .L2+12 + 196 002a 1360 str r3, [r2] + 197 .loc 1 74 69 + 198 002c 0F4B ldr r3, .L2+12 + 199 002e 1B68 ldr r3, [r3] + 200 0030 0F4A ldr r2, .L2+16 + 201 0032 1360 str r3, [r2] + 202 .loc 1 74 37 + 203 0034 0E4B ldr r3, .L2+16 + 204 0036 1B68 ldr r3, [r3] + 205 0038 0E4A ldr r2, .L2+20 + 206 003a 1360 str r3, [r2] + 207 .loc 1 74 19 + 208 003c 0D4B ldr r3, .L2+20 + 209 003e 1B68 ldr r3, [r3] + 210 0040 0D4A ldr r2, .L2+24 + 211 0042 1360 str r3, [r2] + 75:Core/Src/state_machine.c **** programming_mode = 0; + 212 .loc 1 75 20 + 213 0044 0D4B ldr r3, .L2+28 + 214 0046 0022 movs r2, #0 + 215 0048 1A70 strb r2, [r3] + 76:Core/Src/state_machine.c **** debugging_mode = 0; + 216 .loc 1 76 18 + 217 004a 0D4B ldr r3, .L2+32 + 218 004c 0022 movs r2, #0 + 219 004e 1A70 strb r2, [r3] + 77:Core/Src/state_machine.c **** balancing_state = 0; + 220 .loc 1 77 19 + 221 0050 0C4B ldr r3, .L2+36 + 222 0052 0022 movs r2, #0 + 223 0054 1A70 strb r2, [r3] + 78:Core/Src/state_machine.c **** } + 224 .loc 1 78 1 + 225 0056 00BF nop + 226 0058 BD46 mov sp, r7 + 227 .cfi_def_cfa_register 13 + 228 @ sp needed + 229 005a 5DF8047B ldr r7, [sp], #4 + 230 .cfi_restore 7 + 231 .cfi_def_cfa_offset 0 + 232 005e 7047 bx lr + 233 .L3: + 234 .align 2 + 235 .L2: + 236 0060 00000000 .word state + 237 0064 00000000 .word balancing_timer + 238 0068 00000000 .word eeprom_timer + 239 006c 00000000 .word error_timer + 240 0070 00000000 .word powerground_calibration_timer + 241 0074 00000000 .word discharge_timer + 242 0078 00000000 .word precharge_timer + 243 007c 00000000 .word programming_mode + 244 0080 00000000 .word debugging_mode + 245 0084 00000000 .word balancing_state + 246 .cfi_endproc + 247 .LFE130: + ARM GAS /tmp/cctkPVvk.s page 6 + + + 249 .global __aeabi_f2d + 250 .global __aeabi_dsub + 251 .global __aeabi_dmul + 252 .global __aeabi_d2iz + 253 .section .text.sm_update,"ax",%progbits + 254 .align 1 + 255 .global sm_update + 256 .syntax unified + 257 .thumb + 258 .thumb_func + 260 sm_update: + 261 .LFB131: + 79:Core/Src/state_machine.c **** + 80:Core/Src/state_machine.c **** void sm_update(){ + 262 .loc 1 80 17 + 263 .cfi_startproc + 264 @ args = 0, pretend = 0, frame = 0 + 265 @ frame_needed = 1, uses_anonymous_args = 0 + 266 0000 80B5 push {r7, lr} + 267 .cfi_def_cfa_offset 8 + 268 .cfi_offset 7, -8 + 269 .cfi_offset 14, -4 + 270 0002 00AF add r7, sp, #0 + 271 .cfi_def_cfa_register 7 + 81:Core/Src/state_machine.c **** + 82:Core/Src/state_machine.c **** CURRENT_MEASUREMENT = (module.auxVoltages[0] > 2495) ? (module.auxVoltages[0] - (2495.0)) * (300. + 272 .loc 1 82 44 + 273 0004 6A4B ldr r3, .L21+24 + 274 0006 D3ED087A vldr.32 s15, [r3, #32] + 275 .loc 1 82 23 + 276 000a 9FED6A7A vldr.32 s14, .L21+28 + 277 000e F4EEC77A vcmpe.f32 s15, s14 + 278 0012 F1EE10FA vmrs APSR_nzcv, FPSCR + 279 0016 1ADD ble .L19 + 280 .loc 1 82 77 discriminator 1 + 281 0018 654B ldr r3, .L21+24 + 282 001a 1B6A ldr r3, [r3, #32] @ float + 283 001c 1846 mov r0, r3 @ float + 284 001e FFF7FEFF bl __aeabi_f2d + 285 .loc 1 82 81 discriminator 1 + 286 0022 5DA3 adr r3, .L21 + 287 0024 D3E90023 ldrd r2, [r3] + 288 0028 FFF7FEFF bl __aeabi_dsub + 289 002c 0246 mov r2, r0 + 290 002e 0B46 mov r3, r1 + 291 0030 1046 mov r0, r2 + 292 0032 1946 mov r1, r3 + 293 .loc 1 82 93 discriminator 1 + 294 0034 5AA3 adr r3, .L21+8 + 295 0036 D3E90023 ldrd r2, [r3] + 296 003a FFF7FEFF bl __aeabi_dmul + 297 003e 0246 mov r2, r0 + 298 0040 0B46 mov r3, r1 + 299 .loc 1 82 23 discriminator 1 + 300 0042 1046 mov r0, r2 + 301 0044 1946 mov r1, r3 + 302 0046 FFF7FEFF bl __aeabi_d2iz + ARM GAS /tmp/cctkPVvk.s page 7 + + + 303 004a 0346 mov r3, r0 + 304 004c 00E0 b .L7 + 305 .L19: + 306 .loc 1 82 23 is_stmt 0 discriminator 2 + 307 004e 0023 movs r3, #0 + 308 .L7: + 309 .loc 1 82 23 discriminator 4 + 310 0050 594A ldr r2, .L21+32 + 311 0052 1360 str r3, [r2] + 83:Core/Src/state_machine.c **** CURRENT_MEASUREMENT_ON = (module.auxVoltages[1] > 2400); + 312 .loc 1 83 47 is_stmt 1 + 313 0054 564B ldr r3, .L21+24 + 314 0056 D3ED097A vldr.32 s15, [r3, #36] + 315 .loc 1 83 51 + 316 005a 9FED587A vldr.32 s14, .L21+36 + 317 005e F4EEC77A vcmpe.f32 s15, s14 + 318 0062 F1EE10FA vmrs APSR_nzcv, FPSCR + 319 0066 CCBF ite gt + 320 0068 0123 movgt r3, #1 + 321 006a 0023 movle r3, #0 + 322 006c DAB2 uxtb r2, r3 + 323 .loc 1 83 26 + 324 006e 544B ldr r3, .L21+40 + 325 0070 1A70 strb r2, [r3] + 84:Core/Src/state_machine.c **** RELAY_ESC_SIDE_VOLTAGE = module.auxVoltages[2] * 15.19; + 326 .loc 1 84 46 + 327 0072 4F4B ldr r3, .L21+24 + 328 0074 9B6A ldr r3, [r3, #40] @ float + 329 0076 1846 mov r0, r3 @ float + 330 0078 FFF7FEFF bl __aeabi_f2d + 331 .loc 1 84 50 + 332 007c 4AA3 adr r3, .L21+16 + 333 007e D3E90023 ldrd r2, [r3] + 334 0082 FFF7FEFF bl __aeabi_dmul + 335 0086 0246 mov r2, r0 + 336 0088 0B46 mov r3, r1 + 337 .loc 1 84 26 + 338 008a 1046 mov r0, r2 + 339 008c 1946 mov r1, r3 + 340 008e FFF7FEFF bl __aeabi_d2iz + 341 0092 0346 mov r3, r0 + 342 0094 4B4A ldr r2, .L21+44 + 343 0096 1360 str r3, [r2] + 85:Core/Src/state_machine.c **** RELAY_BAT_SIDE_VOLTAGE = module.auxVoltages[3] * 15.19; // the calculation says the factor is + 344 .loc 1 85 46 + 345 0098 454B ldr r3, .L21+24 + 346 009a DB6A ldr r3, [r3, #44] @ float + 347 009c 1846 mov r0, r3 @ float + 348 009e FFF7FEFF bl __aeabi_f2d + 349 .loc 1 85 50 + 350 00a2 41A3 adr r3, .L21+16 + 351 00a4 D3E90023 ldrd r2, [r3] + 352 00a8 FFF7FEFF bl __aeabi_dmul + 353 00ac 0246 mov r2, r0 + 354 00ae 0B46 mov r3, r1 + 355 .loc 1 85 26 + 356 00b0 1046 mov r0, r2 + ARM GAS /tmp/cctkPVvk.s page 8 + + + 357 00b2 1946 mov r1, r3 + 358 00b4 FFF7FEFF bl __aeabi_d2iz + 359 00b8 0346 mov r3, r0 + 360 00ba 434A ldr r2, .L21+48 + 361 00bc 1360 str r3, [r2] + 86:Core/Src/state_machine.c **** + 87:Core/Src/state_machine.c **** //if (can_timeout_timer < HAL_GetTick()) + 88:Core/Src/state_machine.c **** // state.current_state = state.target_state = STATE_INACTIVE; + 89:Core/Src/state_machine.c **** /* + 90:Core/Src/state_machine.c **** if (eeprom_timer < HAL_GetTick()){ + 91:Core/Src/state_machine.c **** eeprom_write_status(); + 92:Core/Src/state_machine.c **** eeprom_timer = HAL_GetTick() + EEPROM_WRITE_FREQ; + 93:Core/Src/state_machine.c **** } + 94:Core/Src/state_machine.c **** */ + 95:Core/Src/state_machine.c **** can_handle_send_status(); + 362 .loc 1 95 3 + 363 00be FFF7FEFF bl can_handle_send_status + 96:Core/Src/state_machine.c **** can_handle_send_log(); + 364 .loc 1 96 3 + 365 00c2 FFF7FEFF bl can_handle_send_log + 97:Core/Src/state_machine.c **** sm_check_errors(); + 366 .loc 1 97 3 + 367 00c6 FFF7FEFF bl sm_check_errors + 98:Core/Src/state_machine.c **** sm_precharge_discharge_manager(); + 368 .loc 1 98 3 + 369 00ca FFF7FEFF bl sm_precharge_discharge_manager + 99:Core/Src/state_machine.c **** //sm_calibrate_powerground(); + 100:Core/Src/state_machine.c **** sm_balancing(); + 370 .loc 1 100 3 + 371 00ce FFF7FEFF bl sm_balancing + 101:Core/Src/state_machine.c **** sm_powerground_manager(); + 372 .loc 1 101 3 + 373 00d2 FFF7FEFF bl sm_powerground_manager + 102:Core/Src/state_machine.c **** tmp1075_measure(); + 374 .loc 1 102 3 + 375 00d6 FFF7FEFF bl tmp1075_measure + 103:Core/Src/state_machine.c **** status_led_update(); + 376 .loc 1 103 3 + 377 00da FFF7FEFF bl status_led_update + 104:Core/Src/state_machine.c **** soc_update(); + 378 .loc 1 104 3 + 379 00de FFF7FEFF bl soc_update + 105:Core/Src/state_machine.c **** + 106:Core/Src/state_machine.c **** switch (state.current_state) { + 380 .loc 1 106 16 + 381 00e2 3A4B ldr r3, .L21+52 + 382 00e4 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 383 .loc 1 106 3 + 384 00e6 072B cmp r3, #7 + 385 00e8 4AD8 bhi .L8 + 386 00ea 01A2 adr r2, .L10 + 387 00ec 52F823F0 ldr pc, [r2, r3, lsl #2] + 388 .p2align 2 + 389 .L10: + 390 00f0 11010000 .word .L17+1 + 391 00f4 1F010000 .word .L16+1 + 392 00f8 2D010000 .word .L15+1 + ARM GAS /tmp/cctkPVvk.s page 9 + + + 393 00fc 3B010000 .word .L14+1 + 394 0100 49010000 .word .L13+1 + 395 0104 57010000 .word .L12+1 + 396 0108 65010000 .word .L11+1 + 397 010c 73010000 .word .L9+1 + 398 .p2align 1 + 399 .L17: + 107:Core/Src/state_machine.c **** case STATE_INACTIVE: + 108:Core/Src/state_machine.c **** state.current_state = sm_update_inactive(); // monitor only + 400 .loc 1 108 29 + 401 0110 FFF7FEFF bl sm_update_inactive + 402 0114 0346 mov r3, r0 + 403 0116 1A46 mov r2, r3 + 404 .loc 1 108 27 discriminator 1 + 405 0118 2C4B ldr r3, .L21+52 + 406 011a 1A70 strb r2, [r3] + 109:Core/Src/state_machine.c **** break; + 407 .loc 1 109 7 + 408 011c 30E0 b .L8 + 409 .L16: + 110:Core/Src/state_machine.c **** case STATE_PRECHARGE: + 111:Core/Src/state_machine.c **** state.current_state = sm_update_precharge(); // set PRECHARGE + 410 .loc 1 111 29 + 411 011e FFF7FEFF bl sm_update_precharge + 412 0122 0346 mov r3, r0 + 413 0124 1A46 mov r2, r3 + 414 .loc 1 111 27 discriminator 1 + 415 0126 294B ldr r3, .L21+52 + 416 0128 1A70 strb r2, [r3] + 112:Core/Src/state_machine.c **** break; + 417 .loc 1 112 7 + 418 012a 29E0 b .L8 + 419 .L15: + 113:Core/Src/state_machine.c **** case STATE_READY: + 114:Core/Src/state_machine.c **** state.current_state = sm_update_ready(); + 420 .loc 1 114 29 + 421 012c FFF7FEFF bl sm_update_ready + 422 0130 0346 mov r3, r0 + 423 0132 1A46 mov r2, r3 + 424 .loc 1 114 27 discriminator 1 + 425 0134 254B ldr r3, .L21+52 + 426 0136 1A70 strb r2, [r3] + 115:Core/Src/state_machine.c **** break; + 427 .loc 1 115 7 + 428 0138 22E0 b .L8 + 429 .L14: + 116:Core/Src/state_machine.c **** case STATE_ACTIVE: + 117:Core/Src/state_machine.c **** state.current_state = sm_update_active(); + 430 .loc 1 117 29 + 431 013a FFF7FEFF bl sm_update_active + 432 013e 0346 mov r3, r0 + 433 0140 1A46 mov r2, r3 + 434 .loc 1 117 27 discriminator 1 + 435 0142 224B ldr r3, .L21+52 + 436 0144 1A70 strb r2, [r3] + 118:Core/Src/state_machine.c **** break; + 437 .loc 1 118 7 + ARM GAS /tmp/cctkPVvk.s page 10 + + + 438 0146 1BE0 b .L8 + 439 .L13: + 119:Core/Src/state_machine.c **** case STATE_DISCHARGE: + 120:Core/Src/state_machine.c **** state.current_state = sm_update_discharge(); + 440 .loc 1 120 29 + 441 0148 FFF7FEFF bl sm_update_discharge + 442 014c 0346 mov r3, r0 + 443 014e 1A46 mov r2, r3 + 444 .loc 1 120 27 discriminator 1 + 445 0150 1E4B ldr r3, .L21+52 + 446 0152 1A70 strb r2, [r3] + 121:Core/Src/state_machine.c **** break; + 447 .loc 1 121 7 + 448 0154 14E0 b .L8 + 449 .L12: + 122:Core/Src/state_machine.c **** case STATE_CHARGING_PRECHARGE: + 123:Core/Src/state_machine.c **** state.current_state = sm_update_charging_precharge(); + 450 .loc 1 123 29 + 451 0156 FFF7FEFF bl sm_update_charging_precharge + 452 015a 0346 mov r3, r0 + 453 015c 1A46 mov r2, r3 + 454 .loc 1 123 27 discriminator 1 + 455 015e 1B4B ldr r3, .L21+52 + 456 0160 1A70 strb r2, [r3] + 124:Core/Src/state_machine.c **** break; + 457 .loc 1 124 7 + 458 0162 0DE0 b .L8 + 459 .L11: + 125:Core/Src/state_machine.c **** case STATE_CHARGING: + 126:Core/Src/state_machine.c **** state.current_state = sm_update_charging(); + 460 .loc 1 126 29 + 461 0164 FFF7FEFF bl sm_update_charging + 462 0168 0346 mov r3, r0 + 463 016a 1A46 mov r2, r3 + 464 .loc 1 126 27 discriminator 1 + 465 016c 174B ldr r3, .L21+52 + 466 016e 1A70 strb r2, [r3] + 127:Core/Src/state_machine.c **** break; + 467 .loc 1 127 7 + 468 0170 06E0 b .L8 + 469 .L9: + 128:Core/Src/state_machine.c **** case STATE_ERROR: + 129:Core/Src/state_machine.c **** state.current_state = sm_update_error(); // enter the correct ERROR state + 470 .loc 1 129 29 + 471 0172 FFF7FEFF bl sm_update_error + 472 0176 0346 mov r3, r0 + 473 0178 1A46 mov r2, r3 + 474 .loc 1 129 27 discriminator 1 + 475 017a 144B ldr r3, .L21+52 + 476 017c 1A70 strb r2, [r3] + 130:Core/Src/state_machine.c **** break; + 477 .loc 1 130 7 + 478 017e 00BF nop + 479 .L8: + 131:Core/Src/state_machine.c **** } + 132:Core/Src/state_machine.c **** + 133:Core/Src/state_machine.c **** sm_set_relay_positions(state.current_state); + ARM GAS /tmp/cctkPVvk.s page 11 + + + 480 .loc 1 133 3 + 481 0180 124B ldr r3, .L21+52 + 482 0182 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 483 0184 1846 mov r0, r3 + 484 0186 FFF7FEFF bl sm_set_relay_positions + 134:Core/Src/state_machine.c **** state.target_state = state.current_state; + 485 .loc 1 134 29 + 486 018a 104B ldr r3, .L21+52 + 487 018c 1A78 ldrb r2, [r3] @ zero_extendqisi2 + 488 .loc 1 134 22 + 489 018e 0F4B ldr r3, .L21+52 + 490 0190 5A70 strb r2, [r3, #1] + 135:Core/Src/state_machine.c **** } + 491 .loc 1 135 1 + 492 0192 00BF nop + 493 0194 80BD pop {r7, pc} + 494 .L22: + 495 0196 00BF .align 3 + 496 .L21: + 497 0198 00000000 .word 0 + 498 019c 007EA340 .word 1084456448 + 499 01a0 00000000 .word 0 + 500 01a4 00C07240 .word 1081262080 + 501 01a8 E17A14AE .word -1374389535 + 502 01ac 47612E40 .word 1076781383 + 503 01b0 00000000 .word module + 504 01b4 00F01B45 .word 1159458816 + 505 01b8 00000000 .word CURRENT_MEASUREMENT + 506 01bc 00001645 .word 1159069696 + 507 01c0 00000000 .word CURRENT_MEASUREMENT_ON + 508 01c4 00000000 .word RELAY_ESC_SIDE_VOLTAGE + 509 01c8 00000000 .word RELAY_BAT_SIDE_VOLTAGE + 510 01cc 00000000 .word state + 511 .cfi_endproc + 512 .LFE131: + 514 .section .text.sm_handle_ams_in,"ax",%progbits + 515 .align 1 + 516 .global sm_handle_ams_in + 517 .syntax unified + 518 .thumb + 519 .thumb_func + 521 sm_handle_ams_in: + 522 .LFB132: + 136:Core/Src/state_machine.c **** + 137:Core/Src/state_machine.c **** void sm_handle_ams_in(const uint8_t *data){ + 523 .loc 1 137 43 + 524 .cfi_startproc + 525 @ args = 0, pretend = 0, frame = 8 + 526 @ frame_needed = 1, uses_anonymous_args = 0 + 527 0000 80B5 push {r7, lr} + 528 .cfi_def_cfa_offset 8 + 529 .cfi_offset 7, -8 + 530 .cfi_offset 14, -4 + 531 0002 82B0 sub sp, sp, #8 + 532 .cfi_def_cfa_offset 16 + 533 0004 00AF add r7, sp, #0 + 534 .cfi_def_cfa_register 7 + ARM GAS /tmp/cctkPVvk.s page 12 + + + 535 0006 7860 str r0, [r7, #4] + 138:Core/Src/state_machine.c **** if (programming_mode == 1 && (state.current_state == STATE_READY || state.current_state == STATE_ + 536 .loc 1 138 24 + 537 0008 3D4B ldr r3, .L46 + 538 000a 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 539 .loc 1 138 6 + 540 000c 002B cmp r3, #0 + 541 000e 0DD0 beq .L24 + 542 .loc 1 138 38 discriminator 1 + 543 0010 3C4B ldr r3, .L46+4 + 544 0012 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 545 .loc 1 138 29 discriminator 1 + 546 0014 022B cmp r3, #2 + 547 0016 03D0 beq .L25 + 548 .loc 1 138 76 discriminator 3 + 549 0018 3A4B ldr r3, .L46+4 + 550 001a 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 551 .loc 1 138 68 discriminator 3 + 552 001c 032B cmp r3, #3 + 553 001e 05D1 bne .L24 + 554 .L25: + 555 .loc 1 138 138 discriminator 4 + 556 0020 7B68 ldr r3, [r7, #4] + 557 0022 0133 adds r3, r3, #1 + 558 .loc 1 138 110 discriminator 4 + 559 0024 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 560 0026 1846 mov r0, r3 + 561 0028 FFF7FEFF bl PWM_powerground_control + 562 .L24: + 139:Core/Src/state_machine.c **** + 140:Core/Src/state_machine.c **** switch (data[0]) { + 563 .loc 1 140 15 + 564 002c 7B68 ldr r3, [r7, #4] + 565 002e 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 566 .loc 1 140 3 + 567 0030 FF2B cmp r3, #255 + 568 0032 50D0 beq .L26 + 569 0034 FF2B cmp r3, #255 + 570 0036 5EDC bgt .L40 + 571 0038 F12B cmp r3, #241 + 572 003a 53D0 beq .L41 + 573 003c F12B cmp r3, #241 + 574 003e 5ADC bgt .L40 + 575 0040 F02B cmp r3, #240 + 576 0042 40D0 beq .L29 + 577 0044 F02B cmp r3, #240 + 578 0046 56DC bgt .L40 + 579 0048 022B cmp r3, #2 + 580 004a 2BD0 beq .L30 + 581 004c 022B cmp r3, #2 + 582 004e 52DC bgt .L40 + 583 0050 002B cmp r3, #0 + 584 0052 02D0 beq .L31 + 585 0054 012B cmp r3, #1 + 586 0056 0BD0 beq .L32 + 141:Core/Src/state_machine.c **** case 0x00: + 142:Core/Src/state_machine.c **** if (state.current_state != STATE_INACTIVE){ + ARM GAS /tmp/cctkPVvk.s page 13 + + + 143:Core/Src/state_machine.c **** state.target_state = STATE_DISCHARGE; + 144:Core/Src/state_machine.c **** PWM_powerground_control(255); + 145:Core/Src/state_machine.c **** } + 146:Core/Src/state_machine.c **** break; + 147:Core/Src/state_machine.c **** case 0x01: + 148:Core/Src/state_machine.c **** if (state.target_state == STATE_INACTIVE || state.target_state == STATE_DISCHARGE){ + 149:Core/Src/state_machine.c **** state.target_state = STATE_PRECHARGE; + 150:Core/Src/state_machine.c **** PWM_powerground_control(0); + 151:Core/Src/state_machine.c **** } else if (state.target_state == STATE_ACTIVE){ + 152:Core/Src/state_machine.c **** state.target_state = STATE_READY; + 153:Core/Src/state_machine.c **** PWM_powerground_control(0); + 154:Core/Src/state_machine.c **** } + 155:Core/Src/state_machine.c **** break; + 156:Core/Src/state_machine.c **** case 0x02: + 157:Core/Src/state_machine.c **** if (state.current_state == STATE_READY || state.current_state == STATE_ACTIVE){ + 158:Core/Src/state_machine.c **** target_powerground_status = data[1]; + 159:Core/Src/state_machine.c **** state.target_state = STATE_ACTIVE; // READY -> ACTIVE + 160:Core/Src/state_machine.c **** } + 161:Core/Src/state_machine.c **** break; + 162:Core/Src/state_machine.c **** case 0xF0: + 163:Core/Src/state_machine.c **** if (state.current_state == STATE_INACTIVE){ + 164:Core/Src/state_machine.c **** state.target_state = STATE_CHARGING_PRECHARGE; + 165:Core/Src/state_machine.c **** } + 166:Core/Src/state_machine.c **** break; + 167:Core/Src/state_machine.c **** case 0xF1: // EEPROM + 168:Core/Src/state_machine.c **** break; + 169:Core/Src/state_machine.c **** if (state.current_state == STATE_INACTIVE) + 170:Core/Src/state_machine.c **** // can_handle_dump(); + 171:Core/Src/state_machine.c **** break; + 172:Core/Src/state_machine.c **** case 0xFF: // EMERGENCY SHUTDOWN + 173:Core/Src/state_machine.c **** state.current_state = STATE_DISCHARGE; + 174:Core/Src/state_machine.c **** state.target_state = STATE_ERROR; + 175:Core/Src/state_machine.c **** break; + 176:Core/Src/state_machine.c **** } + 177:Core/Src/state_machine.c **** } + 587 .loc 1 177 1 + 588 0058 4DE0 b .L40 + 589 .L31: + 142:Core/Src/state_machine.c **** state.target_state = STATE_DISCHARGE; + 590 .loc 1 142 16 + 591 005a 2A4B ldr r3, .L46+4 + 592 005c 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 142:Core/Src/state_machine.c **** state.target_state = STATE_DISCHARGE; + 593 .loc 1 142 10 + 594 005e 002B cmp r3, #0 + 595 0060 42D0 beq .L42 + 143:Core/Src/state_machine.c **** PWM_powerground_control(255); + 596 .loc 1 143 28 + 597 0062 284B ldr r3, .L46+4 + 598 0064 0422 movs r2, #4 + 599 0066 5A70 strb r2, [r3, #1] + 144:Core/Src/state_machine.c **** } + 600 .loc 1 144 9 + 601 0068 FF20 movs r0, #255 + 602 006a FFF7FEFF bl PWM_powerground_control + 146:Core/Src/state_machine.c **** case 0x01: + 603 .loc 1 146 7 + ARM GAS /tmp/cctkPVvk.s page 14 + + + 604 006e 3BE0 b .L42 + 605 .L32: + 148:Core/Src/state_machine.c **** state.target_state = STATE_PRECHARGE; + 606 .loc 1 148 16 + 607 0070 244B ldr r3, .L46+4 + 608 0072 5B78 ldrb r3, [r3, #1] @ zero_extendqisi2 + 148:Core/Src/state_machine.c **** state.target_state = STATE_PRECHARGE; + 609 .loc 1 148 10 + 610 0074 002B cmp r3, #0 + 611 0076 03D0 beq .L34 + 148:Core/Src/state_machine.c **** state.target_state = STATE_PRECHARGE; + 612 .loc 1 148 56 discriminator 1 + 613 0078 224B ldr r3, .L46+4 + 614 007a 5B78 ldrb r3, [r3, #1] @ zero_extendqisi2 + 148:Core/Src/state_machine.c **** state.target_state = STATE_PRECHARGE; + 615 .loc 1 148 48 discriminator 1 + 616 007c 042B cmp r3, #4 + 617 007e 06D1 bne .L35 + 618 .L34: + 149:Core/Src/state_machine.c **** PWM_powerground_control(0); + 619 .loc 1 149 28 + 620 0080 204B ldr r3, .L46+4 + 621 0082 0122 movs r2, #1 + 622 0084 5A70 strb r2, [r3, #1] + 150:Core/Src/state_machine.c **** } else if (state.target_state == STATE_ACTIVE){ + 623 .loc 1 150 9 + 624 0086 0020 movs r0, #0 + 625 0088 FFF7FEFF bl PWM_powerground_control + 155:Core/Src/state_machine.c **** case 0x02: + 626 .loc 1 155 7 + 627 008c 2EE0 b .L43 + 628 .L35: + 151:Core/Src/state_machine.c **** state.target_state = STATE_READY; + 629 .loc 1 151 23 + 630 008e 1D4B ldr r3, .L46+4 + 631 0090 5B78 ldrb r3, [r3, #1] @ zero_extendqisi2 + 151:Core/Src/state_machine.c **** state.target_state = STATE_READY; + 632 .loc 1 151 17 + 633 0092 032B cmp r3, #3 + 634 0094 2AD1 bne .L43 + 152:Core/Src/state_machine.c **** PWM_powerground_control(0); + 635 .loc 1 152 28 + 636 0096 1B4B ldr r3, .L46+4 + 637 0098 0222 movs r2, #2 + 638 009a 5A70 strb r2, [r3, #1] + 153:Core/Src/state_machine.c **** } + 639 .loc 1 153 9 + 640 009c 0020 movs r0, #0 + 641 009e FFF7FEFF bl PWM_powerground_control + 155:Core/Src/state_machine.c **** case 0x02: + 642 .loc 1 155 7 + 643 00a2 23E0 b .L43 + 644 .L30: + 157:Core/Src/state_machine.c **** target_powerground_status = data[1]; + 645 .loc 1 157 16 + 646 00a4 174B ldr r3, .L46+4 + 647 00a6 1B78 ldrb r3, [r3] @ zero_extendqisi2 + ARM GAS /tmp/cctkPVvk.s page 15 + + + 157:Core/Src/state_machine.c **** target_powerground_status = data[1]; + 648 .loc 1 157 10 + 649 00a8 022B cmp r3, #2 + 650 00aa 03D0 beq .L37 + 157:Core/Src/state_machine.c **** target_powerground_status = data[1]; + 651 .loc 1 157 54 discriminator 1 + 652 00ac 154B ldr r3, .L46+4 + 653 00ae 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 157:Core/Src/state_machine.c **** target_powerground_status = data[1]; + 654 .loc 1 157 46 discriminator 1 + 655 00b0 032B cmp r3, #3 + 656 00b2 1DD1 bne .L44 + 657 .L37: + 158:Core/Src/state_machine.c **** state.target_state = STATE_ACTIVE; // READY -> ACTIVE + 658 .loc 1 158 41 + 659 00b4 7B68 ldr r3, [r7, #4] + 660 00b6 0133 adds r3, r3, #1 + 661 00b8 1A78 ldrb r2, [r3] @ zero_extendqisi2 + 158:Core/Src/state_machine.c **** state.target_state = STATE_ACTIVE; // READY -> ACTIVE + 662 .loc 1 158 35 + 663 00ba 134B ldr r3, .L46+8 + 664 00bc 1A70 strb r2, [r3] + 159:Core/Src/state_machine.c **** } + 665 .loc 1 159 28 + 666 00be 114B ldr r3, .L46+4 + 667 00c0 0322 movs r2, #3 + 668 00c2 5A70 strb r2, [r3, #1] + 161:Core/Src/state_machine.c **** case 0xF0: + 669 .loc 1 161 7 + 670 00c4 14E0 b .L44 + 671 .L29: + 163:Core/Src/state_machine.c **** state.target_state = STATE_CHARGING_PRECHARGE; + 672 .loc 1 163 16 + 673 00c6 0F4B ldr r3, .L46+4 + 674 00c8 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 163:Core/Src/state_machine.c **** state.target_state = STATE_CHARGING_PRECHARGE; + 675 .loc 1 163 10 + 676 00ca 002B cmp r3, #0 + 677 00cc 12D1 bne .L45 + 164:Core/Src/state_machine.c **** } + 678 .loc 1 164 28 + 679 00ce 0D4B ldr r3, .L46+4 + 680 00d0 0522 movs r2, #5 + 681 00d2 5A70 strb r2, [r3, #1] + 166:Core/Src/state_machine.c **** case 0xF1: // EEPROM + 682 .loc 1 166 7 + 683 00d4 0EE0 b .L45 + 684 .L26: + 173:Core/Src/state_machine.c **** state.target_state = STATE_ERROR; + 685 .loc 1 173 27 + 686 00d6 0B4B ldr r3, .L46+4 + 687 00d8 0422 movs r2, #4 + 688 00da 1A70 strb r2, [r3] + 174:Core/Src/state_machine.c **** break; + 689 .loc 1 174 26 + 690 00dc 094B ldr r3, .L46+4 + 691 00de 0722 movs r2, #7 + ARM GAS /tmp/cctkPVvk.s page 16 + + + 692 00e0 5A70 strb r2, [r3, #1] + 175:Core/Src/state_machine.c **** } + 693 .loc 1 175 7 + 694 00e2 08E0 b .L27 + 695 .L41: + 168:Core/Src/state_machine.c **** if (state.current_state == STATE_INACTIVE) + 696 .loc 1 168 7 + 697 00e4 00BF nop + 698 00e6 06E0 b .L40 + 699 .L42: + 146:Core/Src/state_machine.c **** case 0x01: + 700 .loc 1 146 7 + 701 00e8 00BF nop + 702 00ea 04E0 b .L40 + 703 .L43: + 155:Core/Src/state_machine.c **** case 0x02: + 704 .loc 1 155 7 + 705 00ec 00BF nop + 706 00ee 02E0 b .L40 + 707 .L44: + 161:Core/Src/state_machine.c **** case 0xF0: + 708 .loc 1 161 7 + 709 00f0 00BF nop + 710 00f2 00E0 b .L40 + 711 .L45: + 166:Core/Src/state_machine.c **** case 0xF1: // EEPROM + 712 .loc 1 166 7 + 713 00f4 00BF nop + 714 .L27: + 715 .L40: + 716 .loc 1 177 1 + 717 00f6 00BF nop + 718 00f8 0837 adds r7, r7, #8 + 719 .cfi_def_cfa_offset 8 + 720 00fa BD46 mov sp, r7 + 721 .cfi_def_cfa_register 13 + 722 @ sp needed + 723 00fc 80BD pop {r7, pc} + 724 .L47: + 725 00fe 00BF .align 2 + 726 .L46: + 727 0100 00000000 .word programming_mode + 728 0104 00000000 .word state + 729 0108 00000000 .word target_powerground_status + 730 .cfi_endproc + 731 .LFE132: + 733 .section .text.sm_precharge_discharge_manager,"ax",%progbits + 734 .align 1 + 735 .global sm_precharge_discharge_manager + 736 .syntax unified + 737 .thumb + 738 .thumb_func + 740 sm_precharge_discharge_manager: + 741 .LFB133: + 178:Core/Src/state_machine.c **** + 179:Core/Src/state_machine.c **** void sm_precharge_discharge_manager(){ + 742 .loc 1 179 38 + ARM GAS /tmp/cctkPVvk.s page 17 + + + 743 .cfi_startproc + 744 @ args = 0, pretend = 0, frame = 0 + 745 @ frame_needed = 1, uses_anonymous_args = 0 + 746 0000 80B5 push {r7, lr} + 747 .cfi_def_cfa_offset 8 + 748 .cfi_offset 7, -8 + 749 .cfi_offset 14, -4 + 750 0002 00AF add r7, sp, #0 + 751 .cfi_def_cfa_register 7 + 180:Core/Src/state_machine.c **** + 181:Core/Src/state_machine.c **** if (state.current_state != STATE_PRECHARGE && state.target_state == STATE_PRECHARGE){ + 752 .loc 1 181 12 + 753 0004 324B ldr r3, .L56 + 754 0006 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 755 .loc 1 181 6 + 756 0008 012B cmp r3, #1 + 757 000a 0BD0 beq .L49 + 758 .loc 1 181 54 discriminator 1 + 759 000c 304B ldr r3, .L56 + 760 000e 5B78 ldrb r3, [r3, #1] @ zero_extendqisi2 + 761 .loc 1 181 46 discriminator 1 + 762 0010 012B cmp r3, #1 + 763 0012 07D1 bne .L49 + 182:Core/Src/state_machine.c **** precharge_timer = HAL_GetTick() + PRECHARGE_DURATION; + 764 .loc 1 182 23 + 765 0014 FFF7FEFF bl HAL_GetTick + 766 0018 0346 mov r3, r0 + 767 .loc 1 182 37 discriminator 1 + 768 001a 03F5FA53 add r3, r3, #8000 + 769 .loc 1 182 21 discriminator 1 + 770 001e 2D4A ldr r2, .L56+4 + 771 0020 1360 str r3, [r2] + 772 .loc 1 182 21 is_stmt 0 + 773 0022 10E0 b .L50 + 774 .L49: + 183:Core/Src/state_machine.c **** } else if (state.current_state == STATE_PRECHARGE && precharge_timer < HAL_GetTick()) { + 775 .loc 1 183 19 is_stmt 1 + 776 0024 2A4B ldr r3, .L56 + 777 0026 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 778 .loc 1 183 13 + 779 0028 012B cmp r3, #1 + 780 002a 0CD1 bne .L50 + 781 .loc 1 183 74 discriminator 1 + 782 002c FFF7FEFF bl HAL_GetTick + 783 0030 0246 mov r2, r0 + 784 .loc 1 183 72 discriminator 1 + 785 0032 284B ldr r3, .L56+4 + 786 0034 1B68 ldr r3, [r3] + 787 .loc 1 183 53 discriminator 1 + 788 0036 9A42 cmp r2, r3 + 789 0038 05D9 bls .L50 + 184:Core/Src/state_machine.c **** state.target_state = STATE_READY; + 790 .loc 1 184 24 + 791 003a 254B ldr r3, .L56 + 792 003c 0222 movs r2, #2 + 793 003e 5A70 strb r2, [r3, #1] + 185:Core/Src/state_machine.c **** precharge_timer = 0; + ARM GAS /tmp/cctkPVvk.s page 18 + + + 794 .loc 1 185 21 + 795 0040 244B ldr r3, .L56+4 + 796 0042 0022 movs r2, #0 + 797 0044 1A60 str r2, [r3] + 798 .L50: + 186:Core/Src/state_machine.c **** } + 187:Core/Src/state_machine.c **** + 188:Core/Src/state_machine.c **** if (state.current_state != STATE_CHARGING_PRECHARGE && state.target_state == STATE_CHARGING_PRECH + 799 .loc 1 188 12 + 800 0046 224B ldr r3, .L56 + 801 0048 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 802 .loc 1 188 6 + 803 004a 052B cmp r3, #5 + 804 004c 0BD0 beq .L51 + 805 .loc 1 188 63 discriminator 1 + 806 004e 204B ldr r3, .L56 + 807 0050 5B78 ldrb r3, [r3, #1] @ zero_extendqisi2 + 808 .loc 1 188 55 discriminator 1 + 809 0052 052B cmp r3, #5 + 810 0054 07D1 bne .L51 + 189:Core/Src/state_machine.c **** precharge_timer = HAL_GetTick() + PRECHARGE_DURATION; + 811 .loc 1 189 23 + 812 0056 FFF7FEFF bl HAL_GetTick + 813 005a 0346 mov r3, r0 + 814 .loc 1 189 37 discriminator 1 + 815 005c 03F5FA53 add r3, r3, #8000 + 816 .loc 1 189 21 discriminator 1 + 817 0060 1C4A ldr r2, .L56+4 + 818 0062 1360 str r3, [r2] + 819 .loc 1 189 21 is_stmt 0 + 820 0064 10E0 b .L52 + 821 .L51: + 190:Core/Src/state_machine.c **** } else if (state.current_state == STATE_CHARGING_PRECHARGE && precharge_timer < HAL_GetTick()) { + 822 .loc 1 190 19 is_stmt 1 + 823 0066 1A4B ldr r3, .L56 + 824 0068 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 825 .loc 1 190 13 + 826 006a 052B cmp r3, #5 + 827 006c 0CD1 bne .L52 + 828 .loc 1 190 83 discriminator 1 + 829 006e FFF7FEFF bl HAL_GetTick + 830 0072 0246 mov r2, r0 + 831 .loc 1 190 81 discriminator 1 + 832 0074 174B ldr r3, .L56+4 + 833 0076 1B68 ldr r3, [r3] + 834 .loc 1 190 62 discriminator 1 + 835 0078 9A42 cmp r2, r3 + 836 007a 05D9 bls .L52 + 191:Core/Src/state_machine.c **** state.target_state = STATE_CHARGING; + 837 .loc 1 191 24 + 838 007c 144B ldr r3, .L56 + 839 007e 0622 movs r2, #6 + 840 0080 5A70 strb r2, [r3, #1] + 192:Core/Src/state_machine.c **** precharge_timer = 0; + 841 .loc 1 192 21 + 842 0082 144B ldr r3, .L56+4 + 843 0084 0022 movs r2, #0 + ARM GAS /tmp/cctkPVvk.s page 19 + + + 844 0086 1A60 str r2, [r3] + 845 .L52: + 193:Core/Src/state_machine.c **** } + 194:Core/Src/state_machine.c **** + 195:Core/Src/state_machine.c **** if (state.current_state != STATE_DISCHARGE && state.target_state == STATE_DISCHARGE){ + 846 .loc 1 195 12 + 847 0088 114B ldr r3, .L56 + 848 008a 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 849 .loc 1 195 6 + 850 008c 042B cmp r3, #4 + 851 008e 0BD0 beq .L53 + 852 .loc 1 195 54 discriminator 1 + 853 0090 0F4B ldr r3, .L56 + 854 0092 5B78 ldrb r3, [r3, #1] @ zero_extendqisi2 + 855 .loc 1 195 46 discriminator 1 + 856 0094 042B cmp r3, #4 + 857 0096 07D1 bne .L53 + 196:Core/Src/state_machine.c **** discharge_timer = HAL_GetTick() + DISCHARGE_DURATION; + 858 .loc 1 196 23 + 859 0098 FFF7FEFF bl HAL_GetTick + 860 009c 0346 mov r3, r0 + 861 .loc 1 196 37 discriminator 1 + 862 009e 03F5FA53 add r3, r3, #8000 + 863 .loc 1 196 21 discriminator 1 + 864 00a2 0D4A ldr r2, .L56+8 + 865 00a4 1360 str r3, [r2] + 197:Core/Src/state_machine.c **** } else if (state.current_state == STATE_DISCHARGE && discharge_timer < HAL_GetTick()) { + 198:Core/Src/state_machine.c **** state.target_state = STATE_INACTIVE; + 199:Core/Src/state_machine.c **** discharge_timer = 0; + 200:Core/Src/state_machine.c **** } + 201:Core/Src/state_machine.c **** + 202:Core/Src/state_machine.c **** } + 866 .loc 1 202 1 + 867 00a6 10E0 b .L55 + 868 .L53: + 197:Core/Src/state_machine.c **** } else if (state.current_state == STATE_DISCHARGE && discharge_timer < HAL_GetTick()) { + 869 .loc 1 197 19 + 870 00a8 094B ldr r3, .L56 + 871 00aa 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 197:Core/Src/state_machine.c **** } else if (state.current_state == STATE_DISCHARGE && discharge_timer < HAL_GetTick()) { + 872 .loc 1 197 13 + 873 00ac 042B cmp r3, #4 + 874 00ae 0CD1 bne .L55 + 197:Core/Src/state_machine.c **** } else if (state.current_state == STATE_DISCHARGE && discharge_timer < HAL_GetTick()) { + 875 .loc 1 197 74 discriminator 1 + 876 00b0 FFF7FEFF bl HAL_GetTick + 877 00b4 0246 mov r2, r0 + 197:Core/Src/state_machine.c **** } else if (state.current_state == STATE_DISCHARGE && discharge_timer < HAL_GetTick()) { + 878 .loc 1 197 72 discriminator 1 + 879 00b6 084B ldr r3, .L56+8 + 880 00b8 1B68 ldr r3, [r3] + 197:Core/Src/state_machine.c **** } else if (state.current_state == STATE_DISCHARGE && discharge_timer < HAL_GetTick()) { + 881 .loc 1 197 53 discriminator 1 + 882 00ba 9A42 cmp r2, r3 + 883 00bc 05D9 bls .L55 + 198:Core/Src/state_machine.c **** discharge_timer = 0; + 884 .loc 1 198 24 + ARM GAS /tmp/cctkPVvk.s page 20 + + + 885 00be 044B ldr r3, .L56 + 886 00c0 0022 movs r2, #0 + 887 00c2 5A70 strb r2, [r3, #1] + 199:Core/Src/state_machine.c **** } + 888 .loc 1 199 21 + 889 00c4 044B ldr r3, .L56+8 + 890 00c6 0022 movs r2, #0 + 891 00c8 1A60 str r2, [r3] + 892 .L55: + 893 .loc 1 202 1 + 894 00ca 00BF nop + 895 00cc 80BD pop {r7, pc} + 896 .L57: + 897 00ce 00BF .align 2 + 898 .L56: + 899 00d0 00000000 .word state + 900 00d4 00000000 .word precharge_timer + 901 00d8 00000000 .word discharge_timer + 902 .cfi_endproc + 903 .LFE133: + 905 .section .text.sm_powerground_manager,"ax",%progbits + 906 .align 1 + 907 .global sm_powerground_manager + 908 .syntax unified + 909 .thumb + 910 .thumb_func + 912 sm_powerground_manager: + 913 .LFB134: + 203:Core/Src/state_machine.c **** + 204:Core/Src/state_machine.c **** void sm_powerground_manager(){ + 914 .loc 1 204 30 + 915 .cfi_startproc + 916 @ args = 0, pretend = 0, frame = 0 + 917 @ frame_needed = 1, uses_anonymous_args = 0 + 918 0000 80B5 push {r7, lr} + 919 .cfi_def_cfa_offset 8 + 920 .cfi_offset 7, -8 + 921 .cfi_offset 14, -4 + 922 0002 00AF add r7, sp, #0 + 923 .cfi_def_cfa_register 7 + 205:Core/Src/state_machine.c **** if (current_powerground_status == target_powerground_status) + 924 .loc 1 205 34 + 925 0004 254B ldr r3, .L65 + 926 0006 1A78 ldrb r2, [r3] @ zero_extendqisi2 + 927 0008 254B ldr r3, .L65+4 + 928 000a 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 929 .loc 1 205 6 + 930 000c 9A42 cmp r2, r3 + 931 000e 43D0 beq .L64 + 206:Core/Src/state_machine.c **** return; + 207:Core/Src/state_machine.c **** if ( current_powerground_status > 100 || target_powerground_status > 100){ //something went wrong + 932 .loc 1 207 35 + 933 0010 224B ldr r3, .L65 + 934 0012 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 935 .loc 1 207 6 + 936 0014 642B cmp r3, #100 + 937 0016 03D8 bhi .L61 + ARM GAS /tmp/cctkPVvk.s page 21 + + + 938 .loc 1 207 70 discriminator 1 + 939 0018 214B ldr r3, .L65+4 + 940 001a 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 941 .loc 1 207 41 discriminator 1 + 942 001c 642B cmp r3, #100 + 943 001e 0AD9 bls .L62 + 944 .L61: + 208:Core/Src/state_machine.c **** PWM_powerground_control(255); + 945 .loc 1 208 5 + 946 0020 FF20 movs r0, #255 + 947 0022 FFF7FEFF bl PWM_powerground_control + 209:Core/Src/state_machine.c **** current_powerground_status = target_powerground_status= 0; + 948 .loc 1 209 59 + 949 0026 1E4B ldr r3, .L65+4 + 950 0028 0022 movs r2, #0 + 951 002a 1A70 strb r2, [r3] + 952 .loc 1 209 32 + 953 002c 1C4B ldr r3, .L65+4 + 954 002e 1A78 ldrb r2, [r3] @ zero_extendqisi2 + 955 0030 1A4B ldr r3, .L65 + 956 0032 1A70 strb r2, [r3] + 210:Core/Src/state_machine.c **** return; + 957 .loc 1 210 5 + 958 0034 31E0 b .L58 + 959 .L62: + 211:Core/Src/state_machine.c **** } + 212:Core/Src/state_machine.c **** + 213:Core/Src/state_machine.c **** if (powerground_softstart_timer < HAL_GetTick()){ + 960 .loc 1 213 37 + 961 0036 FFF7FEFF bl HAL_GetTick + 962 003a 0246 mov r2, r0 + 963 .loc 1 213 35 discriminator 1 + 964 003c 194B ldr r3, .L65+8 + 965 003e 1B68 ldr r3, [r3] + 966 .loc 1 213 6 discriminator 1 + 967 0040 9A42 cmp r2, r3 + 968 0042 2AD9 bls .L58 + 214:Core/Src/state_machine.c **** if (current_powerground_status < target_powerground_status){ + 969 .loc 1 214 36 + 970 0044 154B ldr r3, .L65 + 971 0046 1A78 ldrb r2, [r3] @ zero_extendqisi2 + 972 0048 154B ldr r3, .L65+4 + 973 004a 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 974 .loc 1 214 8 + 975 004c 9A42 cmp r2, r3 + 976 004e 0ED2 bcs .L63 + 215:Core/Src/state_machine.c **** current_powerground_status += 5; + 977 .loc 1 215 34 + 978 0050 124B ldr r3, .L65 + 979 0052 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 980 0054 0533 adds r3, r3, #5 + 981 0056 DAB2 uxtb r2, r3 + 982 0058 104B ldr r3, .L65 + 983 005a 1A70 strb r2, [r3] + 216:Core/Src/state_machine.c **** PWM_powerground_softcontrol(); + 984 .loc 1 216 7 + 985 005c FFF7FEFF bl PWM_powerground_softcontrol + ARM GAS /tmp/cctkPVvk.s page 22 + + + 217:Core/Src/state_machine.c **** powerground_softstart_timer = HAL_GetTick() + POWERGROUND_SOFTSTART_INCREMENT_DELAY; + 986 .loc 1 217 37 + 987 0060 FFF7FEFF bl HAL_GetTick + 988 0064 0346 mov r3, r0 + 989 .loc 1 217 51 discriminator 1 + 990 0066 0F33 adds r3, r3, #15 + 991 .loc 1 217 35 discriminator 1 + 992 0068 0E4A ldr r2, .L65+8 + 993 006a 1360 str r3, [r2] + 994 006c 15E0 b .L58 + 995 .L63: + 218:Core/Src/state_machine.c **** } else if (current_powerground_status > target_powerground_status) { + 996 .loc 1 218 43 + 997 006e 0B4B ldr r3, .L65 + 998 0070 1A78 ldrb r2, [r3] @ zero_extendqisi2 + 999 0072 0B4B ldr r3, .L65+4 + 1000 0074 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 1001 .loc 1 218 15 + 1002 0076 9A42 cmp r2, r3 + 1003 0078 0FD9 bls .L58 + 219:Core/Src/state_machine.c **** current_powerground_status -= 5; + 1004 .loc 1 219 34 + 1005 007a 084B ldr r3, .L65 + 1006 007c 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 1007 007e 053B subs r3, r3, #5 + 1008 0080 DAB2 uxtb r2, r3 + 1009 0082 064B ldr r3, .L65 + 1010 0084 1A70 strb r2, [r3] + 220:Core/Src/state_machine.c **** PWM_powerground_softcontrol(); + 1011 .loc 1 220 7 + 1012 0086 FFF7FEFF bl PWM_powerground_softcontrol + 221:Core/Src/state_machine.c **** powerground_softstart_timer = HAL_GetTick() + POWERGROUND_SOFTSTART_INCREMENT_DELAY; + 1013 .loc 1 221 37 + 1014 008a FFF7FEFF bl HAL_GetTick + 1015 008e 0346 mov r3, r0 + 1016 .loc 1 221 51 discriminator 1 + 1017 0090 0F33 adds r3, r3, #15 + 1018 .loc 1 221 35 discriminator 1 + 1019 0092 044A ldr r2, .L65+8 + 1020 0094 1360 str r3, [r2] + 1021 0096 00E0 b .L58 + 1022 .L64: + 206:Core/Src/state_machine.c **** if ( current_powerground_status > 100 || target_powerground_status > 100){ //something went wrong + 1023 .loc 1 206 5 + 1024 0098 00BF nop + 1025 .L58: + 222:Core/Src/state_machine.c **** } + 223:Core/Src/state_machine.c **** } + 224:Core/Src/state_machine.c **** } + 1026 .loc 1 224 1 + 1027 009a 80BD pop {r7, pc} + 1028 .L66: + 1029 .align 2 + 1030 .L65: + 1031 009c 00000000 .word current_powerground_status + 1032 00a0 00000000 .word target_powerground_status + 1033 00a4 00000000 .word powerground_softstart_timer + ARM GAS /tmp/cctkPVvk.s page 23 + + + 1034 .cfi_endproc + 1035 .LFE134: + 1037 .section .text.sm_calibrate_powerground,"ax",%progbits + 1038 .align 1 + 1039 .global sm_calibrate_powerground + 1040 .syntax unified + 1041 .thumb + 1042 .thumb_func + 1044 sm_calibrate_powerground: + 1045 .LFB135: + 225:Core/Src/state_machine.c **** + 226:Core/Src/state_machine.c **** void sm_calibrate_powerground(){ + 1046 .loc 1 226 32 + 1047 .cfi_startproc + 1048 @ args = 0, pretend = 0, frame = 0 + 1049 @ frame_needed = 1, uses_anonymous_args = 0 + 1050 0000 80B5 push {r7, lr} + 1051 .cfi_def_cfa_offset 8 + 1052 .cfi_offset 7, -8 + 1053 .cfi_offset 14, -4 + 1054 0002 00AF add r7, sp, #0 + 1055 .cfi_def_cfa_register 7 + 227:Core/Src/state_machine.c **** if (powerground_calibration_stage != 4 && state.current_state == STATE_PRECHARGE){ + 1056 .loc 1 227 37 + 1057 0004 2D4B ldr r3, .L81 + 1058 0006 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 1059 .loc 1 227 6 + 1060 0008 042B cmp r3, #4 + 1061 000a 56D0 beq .L67 + 1062 .loc 1 227 50 discriminator 1 + 1063 000c 2C4B ldr r3, .L81+4 + 1064 000e 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 1065 .loc 1 227 42 discriminator 1 + 1066 0010 012B cmp r3, #1 + 1067 0012 52D1 bne .L67 + 228:Core/Src/state_machine.c **** switch (powerground_calibration_stage) { + 1068 .loc 1 228 5 + 1069 0014 294B ldr r3, .L81 + 1070 0016 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 1071 0018 032B cmp r3, #3 + 1072 001a 4ED8 bhi .L67 + 1073 001c 01A2 adr r2, .L70 + 1074 001e 52F823F0 ldr pc, [r2, r3, lsl #2] + 1075 0022 00BF .p2align 2 + 1076 .L70: + 1077 0024 35000000 .word .L73+1 + 1078 0028 47000000 .word .L72+1 + 1079 002c 71000000 .word .L71+1 + 1080 0030 9B000000 .word .L69+1 + 1081 .p2align 1 + 1082 .L73: + 229:Core/Src/state_machine.c **** case 0: + 230:Core/Src/state_machine.c **** powerground_calibration_timer = HAL_GetTick() + 0; + 1083 .loc 1 230 41 + 1084 0034 FFF7FEFF bl HAL_GetTick + 1085 0038 0346 mov r3, r0 + 1086 .loc 1 230 39 discriminator 1 + ARM GAS /tmp/cctkPVvk.s page 24 + + + 1087 003a 224A ldr r2, .L81+8 + 1088 003c 1360 str r3, [r2] + 231:Core/Src/state_machine.c **** powerground_calibration_stage = 1; + 1089 .loc 1 231 39 + 1090 003e 1F4B ldr r3, .L81 + 1091 0040 0122 movs r2, #1 + 1092 0042 1A70 strb r2, [r3] + 232:Core/Src/state_machine.c **** return; + 1093 .loc 1 232 9 + 1094 0044 39E0 b .L67 + 1095 .L72: + 233:Core/Src/state_machine.c **** case 1: + 234:Core/Src/state_machine.c **** if (powerground_calibration_timer < HAL_GetTick()){ + 1096 .loc 1 234 45 + 1097 0046 FFF7FEFF bl HAL_GetTick + 1098 004a 0246 mov r2, r0 + 1099 .loc 1 234 43 discriminator 1 + 1100 004c 1D4B ldr r3, .L81+8 + 1101 004e 1B68 ldr r3, [r3] + 1102 .loc 1 234 12 discriminator 1 + 1103 0050 9A42 cmp r2, r3 + 1104 0052 2DD9 bls .L77 + 235:Core/Src/state_machine.c **** powerground_calibration_timer = HAL_GetTick() + 2000; + 1105 .loc 1 235 43 + 1106 0054 FFF7FEFF bl HAL_GetTick + 1107 0058 0346 mov r3, r0 + 1108 .loc 1 235 57 discriminator 1 + 1109 005a 03F5FA63 add r3, r3, #2000 + 1110 .loc 1 235 41 discriminator 1 + 1111 005e 194A ldr r2, .L81+8 + 1112 0060 1360 str r3, [r2] + 236:Core/Src/state_machine.c **** powerground_calibration_stage = 2; + 1113 .loc 1 236 41 + 1114 0062 164B ldr r3, .L81 + 1115 0064 0222 movs r2, #2 + 1116 0066 1A70 strb r2, [r3] + 237:Core/Src/state_machine.c **** PWM_powerground_control(100); + 1117 .loc 1 237 11 + 1118 0068 6420 movs r0, #100 + 1119 006a FFF7FEFF bl PWM_powerground_control + 238:Core/Src/state_machine.c **** } + 239:Core/Src/state_machine.c **** return; + 1120 .loc 1 239 9 + 1121 006e 1FE0 b .L77 + 1122 .L71: + 240:Core/Src/state_machine.c **** case 2: + 241:Core/Src/state_machine.c **** if (powerground_calibration_timer < HAL_GetTick()){ + 1123 .loc 1 241 45 + 1124 0070 FFF7FEFF bl HAL_GetTick + 1125 0074 0246 mov r2, r0 + 1126 .loc 1 241 43 discriminator 1 + 1127 0076 134B ldr r3, .L81+8 + 1128 0078 1B68 ldr r3, [r3] + 1129 .loc 1 241 12 discriminator 1 + 1130 007a 9A42 cmp r2, r3 + 1131 007c 1AD9 bls .L78 + 242:Core/Src/state_machine.c **** powerground_calibration_timer = HAL_GetTick() + 1000; + ARM GAS /tmp/cctkPVvk.s page 25 + + + 1132 .loc 1 242 43 + 1133 007e FFF7FEFF bl HAL_GetTick + 1134 0082 0346 mov r3, r0 + 1135 .loc 1 242 57 discriminator 1 + 1136 0084 03F57A73 add r3, r3, #1000 + 1137 .loc 1 242 41 discriminator 1 + 1138 0088 0E4A ldr r2, .L81+8 + 1139 008a 1360 str r3, [r2] + 243:Core/Src/state_machine.c **** powerground_calibration_stage = 3; + 1140 .loc 1 243 41 + 1141 008c 0B4B ldr r3, .L81 + 1142 008e 0322 movs r2, #3 + 1143 0090 1A70 strb r2, [r3] + 244:Core/Src/state_machine.c **** PWM_powerground_control(0); + 1144 .loc 1 244 11 + 1145 0092 0020 movs r0, #0 + 1146 0094 FFF7FEFF bl PWM_powerground_control + 245:Core/Src/state_machine.c **** } + 246:Core/Src/state_machine.c **** return; + 1147 .loc 1 246 9 + 1148 0098 0CE0 b .L78 + 1149 .L69: + 247:Core/Src/state_machine.c **** case 3: + 248:Core/Src/state_machine.c **** if (powerground_calibration_timer < HAL_GetTick()){ + 1150 .loc 1 248 45 + 1151 009a FFF7FEFF bl HAL_GetTick + 1152 009e 0246 mov r2, r0 + 1153 .loc 1 248 43 discriminator 1 + 1154 00a0 084B ldr r3, .L81+8 + 1155 00a2 1B68 ldr r3, [r3] + 1156 .loc 1 248 12 discriminator 1 + 1157 00a4 9A42 cmp r2, r3 + 1158 00a6 07D9 bls .L79 + 249:Core/Src/state_machine.c **** powerground_calibration_stage = 4; + 1159 .loc 1 249 41 + 1160 00a8 044B ldr r3, .L81 + 1161 00aa 0422 movs r2, #4 + 1162 00ac 1A70 strb r2, [r3] + 250:Core/Src/state_machine.c **** } + 251:Core/Src/state_machine.c **** return; + 1163 .loc 1 251 9 + 1164 00ae 03E0 b .L79 + 1165 .L77: + 239:Core/Src/state_machine.c **** case 2: + 1166 .loc 1 239 9 + 1167 00b0 00BF nop + 1168 00b2 02E0 b .L67 + 1169 .L78: + 246:Core/Src/state_machine.c **** case 3: + 1170 .loc 1 246 9 + 1171 00b4 00BF nop + 1172 00b6 00E0 b .L67 + 1173 .L79: + 1174 .loc 1 251 9 + 1175 00b8 00BF nop + 1176 .L67: + 252:Core/Src/state_machine.c **** } + ARM GAS /tmp/cctkPVvk.s page 26 + + + 253:Core/Src/state_machine.c **** } + 254:Core/Src/state_machine.c **** } + 1177 .loc 1 254 1 + 1178 00ba 80BD pop {r7, pc} + 1179 .L82: + 1180 .align 2 + 1181 .L81: + 1182 00bc 00000000 .word powerground_calibration_stage + 1183 00c0 00000000 .word state + 1184 00c4 00000000 .word powerground_calibration_timer + 1185 .cfi_endproc + 1186 .LFE135: + 1188 .section .text.sm_balancing,"ax",%progbits + 1189 .align 1 + 1190 .global sm_balancing + 1191 .syntax unified + 1192 .thumb + 1193 .thumb_func + 1195 sm_balancing: + 1196 .LFB136: + 255:Core/Src/state_machine.c **** + 256:Core/Src/state_machine.c **** void sm_balancing(){ + 1197 .loc 1 256 20 + 1198 .cfi_startproc + 1199 @ args = 0, pretend = 0, frame = 16 + 1200 @ frame_needed = 1, uses_anonymous_args = 0 + 1201 0000 80B5 push {r7, lr} + 1202 .cfi_def_cfa_offset 8 + 1203 .cfi_offset 7, -8 + 1204 .cfi_offset 14, -4 + 1205 0002 84B0 sub sp, sp, #16 + 1206 .cfi_def_cfa_offset 24 + 1207 0004 00AF add r7, sp, #0 + 1208 .cfi_def_cfa_register 7 + 257:Core/Src/state_machine.c **** if (balancing_timer < HAL_GetTick()){ + 1209 .loc 1 257 25 + 1210 0006 FFF7FEFF bl HAL_GetTick + 1211 000a 0246 mov r2, r0 + 1212 .loc 1 257 23 discriminator 1 + 1213 000c 364B ldr r3, .L93 + 1214 000e 1B68 ldr r3, [r3] + 1215 .loc 1 257 6 discriminator 1 + 1216 0010 9A42 cmp r2, r3 + 1217 0012 65D9 bls .L83 + 258:Core/Src/state_machine.c **** if (balancing_state){ + 1218 .loc 1 258 9 + 1219 0014 354B ldr r3, .L93+4 + 1220 0016 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 1221 .loc 1 258 8 + 1222 0018 002B cmp r3, #0 + 1223 001a 55D0 beq .L85 + 1224 .LBB2: + 259:Core/Src/state_machine.c **** balancing_timer = HAL_GetTick() + 30000; + 1225 .loc 1 259 25 + 1226 001c FFF7FEFF bl HAL_GetTick + 1227 0020 0346 mov r3, r0 + 1228 .loc 1 259 39 discriminator 1 + ARM GAS /tmp/cctkPVvk.s page 27 + + + 1229 0022 03F5EA43 add r3, r3, #29952 + 1230 0026 3033 adds r3, r3, #48 + 1231 .loc 1 259 23 discriminator 1 + 1232 0028 2F4A ldr r2, .L93 + 1233 002a 1360 str r3, [r2] + 260:Core/Src/state_machine.c **** + 261:Core/Src/state_machine.c **** uint8_t id_cell_lowest_voltage = 0; + 1234 .loc 1 261 15 + 1235 002c 0023 movs r3, #0 + 1236 002e FB73 strb r3, [r7, #15] + 262:Core/Src/state_machine.c **** uint8_t num_of_cells_to_balance = 0; + 1237 .loc 1 262 15 + 1238 0030 0023 movs r3, #0 + 1239 0032 BB73 strb r3, [r7, #14] + 263:Core/Src/state_machine.c **** uint32_t channels = 0; + 1240 .loc 1 263 16 + 1241 0034 0023 movs r3, #0 + 1242 0036 BB60 str r3, [r7, #8] + 1243 .LBB3: + 264:Core/Src/state_machine.c **** + 265:Core/Src/state_machine.c **** for (int i = 0; i < 13; i++) { + 1244 .loc 1 265 16 + 1245 0038 0023 movs r3, #0 + 1246 003a 7B60 str r3, [r7, #4] + 1247 .loc 1 265 7 + 1248 003c 0EE0 b .L86 + 1249 .L88: + 266:Core/Src/state_machine.c **** if (module.cellVoltages[i] < module.cellVoltages[id_cell_lowest_voltage]) + 1250 .loc 1 266 32 + 1251 003e 2C4A ldr r2, .L93+8 + 1252 0040 7B68 ldr r3, [r7, #4] + 1253 0042 32F91320 ldrsh r2, [r2, r3, lsl #1] + 1254 .loc 1 266 57 + 1255 0046 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 1256 0048 2949 ldr r1, .L93+8 + 1257 004a 31F91330 ldrsh r3, [r1, r3, lsl #1] + 1258 .loc 1 266 12 + 1259 004e 9A42 cmp r2, r3 + 1260 0050 01DA bge .L87 + 267:Core/Src/state_machine.c **** id_cell_lowest_voltage = i; + 1261 .loc 1 267 34 + 1262 0052 7B68 ldr r3, [r7, #4] + 1263 0054 FB73 strb r3, [r7, #15] + 1264 .L87: + 265:Core/Src/state_machine.c **** if (module.cellVoltages[i] < module.cellVoltages[id_cell_lowest_voltage]) + 1265 .loc 1 265 32 discriminator 2 + 1266 0056 7B68 ldr r3, [r7, #4] + 1267 0058 0133 adds r3, r3, #1 + 1268 005a 7B60 str r3, [r7, #4] + 1269 .L86: + 265:Core/Src/state_machine.c **** if (module.cellVoltages[i] < module.cellVoltages[id_cell_lowest_voltage]) + 1270 .loc 1 265 25 discriminator 1 + 1271 005c 7B68 ldr r3, [r7, #4] + 1272 005e 0C2B cmp r3, #12 + 1273 0060 EDDD ble .L88 + 1274 .LBE3: + 1275 .LBB4: + ARM GAS /tmp/cctkPVvk.s page 28 + + + 268:Core/Src/state_machine.c **** } + 269:Core/Src/state_machine.c **** + 270:Core/Src/state_machine.c **** for (int i = 0; i < 13; i++) { + 1276 .loc 1 270 16 + 1277 0062 0023 movs r3, #0 + 1278 0064 3B60 str r3, [r7] + 1279 .loc 1 270 7 + 1280 0066 18E0 b .L89 + 1281 .L91: + 271:Core/Src/state_machine.c **** if (module.cellVoltages[i] - 20 > module.cellVoltages[id_cell_lowest_voltage]){ + 1282 .loc 1 271 32 + 1283 0068 214A ldr r2, .L93+8 + 1284 006a 3B68 ldr r3, [r7] + 1285 006c 32F91330 ldrsh r3, [r2, r3, lsl #1] + 1286 .loc 1 271 36 + 1287 0070 143B subs r3, r3, #20 + 1288 .loc 1 271 62 + 1289 0072 FA7B ldrb r2, [r7, #15] @ zero_extendqisi2 + 1290 0074 1E49 ldr r1, .L93+8 + 1291 0076 31F91220 ldrsh r2, [r1, r2, lsl #1] + 1292 .loc 1 271 12 + 1293 007a 9342 cmp r3, r2 + 1294 007c 0ADD ble .L90 + 272:Core/Src/state_machine.c **** channels |= 1 << i; + 1295 .loc 1 272 25 + 1296 007e 0122 movs r2, #1 + 1297 0080 3B68 ldr r3, [r7] + 1298 0082 02FA03F3 lsl r3, r2, r3 + 1299 0086 1A46 mov r2, r3 + 1300 .loc 1 272 20 + 1301 0088 BB68 ldr r3, [r7, #8] + 1302 008a 1343 orrs r3, r3, r2 + 1303 008c BB60 str r3, [r7, #8] + 273:Core/Src/state_machine.c **** num_of_cells_to_balance++; + 1304 .loc 1 273 34 + 1305 008e BB7B ldrb r3, [r7, #14] @ zero_extendqisi2 + 1306 0090 0133 adds r3, r3, #1 + 1307 0092 BB73 strb r3, [r7, #14] + 1308 .L90: + 270:Core/Src/state_machine.c **** if (module.cellVoltages[i] - 20 > module.cellVoltages[id_cell_lowest_voltage]){ + 1309 .loc 1 270 32 discriminator 2 + 1310 0094 3B68 ldr r3, [r7] + 1311 0096 0133 adds r3, r3, #1 + 1312 0098 3B60 str r3, [r7] + 1313 .L89: + 270:Core/Src/state_machine.c **** if (module.cellVoltages[i] - 20 > module.cellVoltages[id_cell_lowest_voltage]){ + 1314 .loc 1 270 25 discriminator 1 + 1315 009a 3B68 ldr r3, [r7] + 1316 009c 0C2B cmp r3, #12 + 1317 009e E3DD ble .L91 + 1318 .LBE4: + 274:Core/Src/state_machine.c **** } + 275:Core/Src/state_machine.c **** } + 276:Core/Src/state_machine.c **** + 277:Core/Src/state_machine.c **** if (num_of_cells_to_balance == 0){ + 1319 .loc 1 277 10 + 1320 00a0 BB7B ldrb r3, [r7, #14] @ zero_extendqisi2 + ARM GAS /tmp/cctkPVvk.s page 29 + + + 1321 00a2 002B cmp r3, #0 + 1322 00a4 05D1 bne .L92 + 278:Core/Src/state_machine.c **** amsStopBalancing(); + 1323 .loc 1 278 9 + 1324 00a6 FFF7FEFF bl amsStopBalancing + 279:Core/Src/state_machine.c **** balancing_state = 0; + 1325 .loc 1 279 25 + 1326 00aa 104B ldr r3, .L93+4 + 1327 00ac 0022 movs r2, #0 + 1328 00ae 1A70 strb r2, [r3] + 280:Core/Src/state_machine.c **** return; + 1329 .loc 1 280 9 + 1330 00b0 16E0 b .L83 + 1331 .L92: + 281:Core/Src/state_machine.c **** } + 282:Core/Src/state_machine.c **** + 283:Core/Src/state_machine.c **** amsConfigBalancing(channels, 0xF); + 1332 .loc 1 283 7 + 1333 00b2 0F21 movs r1, #15 + 1334 00b4 B868 ldr r0, [r7, #8] + 1335 00b6 FFF7FEFF bl amsConfigBalancing + 284:Core/Src/state_machine.c **** amsStartBalancing(0xF); + 1336 .loc 1 284 7 + 1337 00ba 0F20 movs r0, #15 + 1338 00bc FFF7FEFF bl amsStartBalancing + 285:Core/Src/state_machine.c **** balancing_state = 1; + 1339 .loc 1 285 23 + 1340 00c0 0A4B ldr r3, .L93+4 + 1341 00c2 0122 movs r2, #1 + 1342 00c4 1A70 strb r2, [r3] + 1343 .LBE2: + 1344 00c6 0BE0 b .L83 + 1345 .L85: + 286:Core/Src/state_machine.c **** } else { + 287:Core/Src/state_machine.c **** balancing_timer = HAL_GetTick() + 1000; + 1346 .loc 1 287 25 + 1347 00c8 FFF7FEFF bl HAL_GetTick + 1348 00cc 0346 mov r3, r0 + 1349 .loc 1 287 39 discriminator 1 + 1350 00ce 03F57A73 add r3, r3, #1000 + 1351 .loc 1 287 23 discriminator 1 + 1352 00d2 054A ldr r2, .L93 + 1353 00d4 1360 str r3, [r2] + 288:Core/Src/state_machine.c **** balancing_state = 0; + 1354 .loc 1 288 23 + 1355 00d6 054B ldr r3, .L93+4 + 1356 00d8 0022 movs r2, #0 + 1357 00da 1A70 strb r2, [r3] + 289:Core/Src/state_machine.c **** amsStopBalancing(); + 1358 .loc 1 289 7 + 1359 00dc FFF7FEFF bl amsStopBalancing + 1360 .L83: + 290:Core/Src/state_machine.c **** } + 291:Core/Src/state_machine.c **** } + 292:Core/Src/state_machine.c **** } + 1361 .loc 1 292 1 + 1362 00e0 1037 adds r7, r7, #16 + ARM GAS /tmp/cctkPVvk.s page 30 + + + 1363 .cfi_def_cfa_offset 8 + 1364 00e2 BD46 mov sp, r7 + 1365 .cfi_def_cfa_register 13 + 1366 @ sp needed + 1367 00e4 80BD pop {r7, pc} + 1368 .L94: + 1369 00e6 00BF .align 2 + 1370 .L93: + 1371 00e8 00000000 .word balancing_timer + 1372 00ec 00000000 .word balancing_state + 1373 00f0 00000000 .word module + 1374 .cfi_endproc + 1375 .LFE136: + 1377 .section .text.sm_program_powerground,"ax",%progbits + 1378 .align 1 + 1379 .global sm_program_powerground + 1380 .syntax unified + 1381 .thumb + 1382 .thumb_func + 1384 sm_program_powerground: + 1385 .LFB137: + 293:Core/Src/state_machine.c **** + 294:Core/Src/state_machine.c **** void sm_program_powerground(){ + 1386 .loc 1 294 30 + 1387 .cfi_startproc + 1388 @ args = 0, pretend = 0, frame = 0 + 1389 @ frame_needed = 1, uses_anonymous_args = 0 + 1390 0000 80B5 push {r7, lr} + 1391 .cfi_def_cfa_offset 8 + 1392 .cfi_offset 7, -8 + 1393 .cfi_offset 14, -4 + 1394 0002 00AF add r7, sp, #0 + 1395 .cfi_def_cfa_register 7 + 295:Core/Src/state_machine.c **** if (programming_mode == 0) + 1396 .loc 1 295 24 + 1397 0004 0A4B ldr r3, .L101 + 1398 0006 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 1399 0008 83F00103 eor r3, r3, #1 + 1400 000c DBB2 uxtb r3, r3 + 1401 .loc 1 295 6 + 1402 000e 002B cmp r3, #0 + 1403 0010 0CD1 bne .L100 + 296:Core/Src/state_machine.c **** return; + 297:Core/Src/state_machine.c **** PWM_powerground_control(100); + 1404 .loc 1 297 3 + 1405 0012 6420 movs r0, #100 + 1406 0014 FFF7FEFF bl PWM_powerground_control + 298:Core/Src/state_machine.c **** state.current_state = state.target_state = STATE_ACTIVE; + 1407 .loc 1 298 44 + 1408 0018 064B ldr r3, .L101+4 + 1409 001a 0322 movs r2, #3 + 1410 001c 5A70 strb r2, [r3, #1] + 1411 .loc 1 298 30 + 1412 001e 054B ldr r3, .L101+4 + 1413 0020 5A78 ldrb r2, [r3, #1] @ zero_extendqisi2 + 1414 .loc 1 298 23 + 1415 0022 044B ldr r3, .L101+4 + ARM GAS /tmp/cctkPVvk.s page 31 + + + 1416 0024 1A70 strb r2, [r3] + 1417 .L98: + 299:Core/Src/state_machine.c **** while (1) { + 300:Core/Src/state_machine.c **** can_handle_send_status(); + 1418 .loc 1 300 5 discriminator 1 + 1419 0026 FFF7FEFF bl can_handle_send_status + 1420 002a FCE7 b .L98 + 1421 .L100: + 296:Core/Src/state_machine.c **** PWM_powerground_control(100); + 1422 .loc 1 296 5 + 1423 002c 00BF nop + 301:Core/Src/state_machine.c **** } + 302:Core/Src/state_machine.c **** } + 1424 .loc 1 302 1 + 1425 002e 80BD pop {r7, pc} + 1426 .L102: + 1427 .align 2 + 1428 .L101: + 1429 0030 00000000 .word programming_mode + 1430 0034 00000000 .word state + 1431 .cfi_endproc + 1432 .LFE137: + 1434 .section .text.sm_eeprom_write_status,"ax",%progbits + 1435 .align 1 + 1436 .global sm_eeprom_write_status + 1437 .syntax unified + 1438 .thumb + 1439 .thumb_func + 1441 sm_eeprom_write_status: + 1442 .LFB138: + 303:Core/Src/state_machine.c **** + 304:Core/Src/state_machine.c **** void sm_eeprom_write_status(){ + 1443 .loc 1 304 30 + 1444 .cfi_startproc + 1445 @ args = 0, pretend = 0, frame = 0 + 1446 @ frame_needed = 1, uses_anonymous_args = 0 + 1447 0000 80B5 push {r7, lr} + 1448 .cfi_def_cfa_offset 8 + 1449 .cfi_offset 7, -8 + 1450 .cfi_offset 14, -4 + 1451 0002 00AF add r7, sp, #0 + 1452 .cfi_def_cfa_register 7 + 305:Core/Src/state_machine.c **** if (eeprom_timer < HAL_GetTick()){ + 1453 .loc 1 305 22 + 1454 0004 FFF7FEFF bl HAL_GetTick + 1455 0008 0246 mov r2, r0 + 1456 .loc 1 305 20 discriminator 1 + 1457 000a 074B ldr r3, .L106 + 1458 000c 1B68 ldr r3, [r3] + 1459 .loc 1 305 6 discriminator 1 + 1460 000e 9A42 cmp r2, r3 + 1461 0010 08D9 bls .L105 + 306:Core/Src/state_machine.c **** eeprom_write_status(); + 1462 .loc 1 306 5 + 1463 0012 FFF7FEFF bl eeprom_write_status + 307:Core/Src/state_machine.c **** eeprom_timer = HAL_GetTick() + EEPROM_WRITE_FREQ; + 1464 .loc 1 307 20 + ARM GAS /tmp/cctkPVvk.s page 32 + + + 1465 0016 FFF7FEFF bl HAL_GetTick + 1466 001a 0346 mov r3, r0 + 1467 .loc 1 307 34 discriminator 1 + 1468 001c 03F57A73 add r3, r3, #1000 + 1469 .loc 1 307 18 discriminator 1 + 1470 0020 014A ldr r2, .L106 + 1471 0022 1360 str r3, [r2] + 1472 .L105: + 308:Core/Src/state_machine.c **** } + 309:Core/Src/state_machine.c **** } + 1473 .loc 1 309 1 + 1474 0024 00BF nop + 1475 0026 80BD pop {r7, pc} + 1476 .L107: + 1477 .align 2 + 1478 .L106: + 1479 0028 00000000 .word eeprom_timer + 1480 .cfi_endproc + 1481 .LFE138: + 1483 .section .text.sm_check_errors,"ax",%progbits + 1484 .align 1 + 1485 .global sm_check_errors + 1486 .syntax unified + 1487 .thumb + 1488 .thumb_func + 1490 sm_check_errors: + 1491 .LFB139: + 310:Core/Src/state_machine.c **** + 311:Core/Src/state_machine.c **** void sm_check_errors(){ + 1492 .loc 1 311 23 + 1493 .cfi_startproc + 1494 @ args = 0, pretend = 0, frame = 0 + 1495 @ frame_needed = 1, uses_anonymous_args = 0 + 1496 0000 80B5 push {r7, lr} + 1497 .cfi_def_cfa_offset 8 + 1498 .cfi_offset 7, -8 + 1499 .cfi_offset 14, -4 + 1500 0002 00AF add r7, sp, #0 + 1501 .cfi_def_cfa_register 7 + 312:Core/Src/state_machine.c **** if (programming_mode == 1 || debugging_mode == 1) {return;} // to disable error checking + 1502 .loc 1 312 24 + 1503 0004 774B ldr r3, .L126 + 1504 0006 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 1505 .loc 1 312 6 + 1506 0008 002B cmp r3, #0 + 1507 000a 40F0E880 bne .L125 + 1508 .loc 1 312 47 discriminator 2 + 1509 000e 764B ldr r3, .L126+4 + 1510 0010 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 1511 .loc 1 312 29 discriminator 2 + 1512 0012 002B cmp r3, #0 + 1513 0014 40F0E380 bne .L125 + 313:Core/Src/state_machine.c **** state.error_type.temperature_error = (error_data.error_sources & (1 << 0) || error_data.error_sou + 1514 .loc 1 313 51 + 1515 0018 744B ldr r3, .L126+8 + 1516 001a 1B88 ldrh r3, [r3] + 1517 .loc 1 313 66 + ARM GAS /tmp/cctkPVvk.s page 33 + + + 1518 001c 03F00103 and r3, r3, #1 + 1519 .loc 1 313 160 + 1520 0020 002B cmp r3, #0 + 1521 0022 0BD1 bne .L112 + 1522 .loc 1 313 90 discriminator 2 + 1523 0024 714B ldr r3, .L126+8 + 1524 0026 1B88 ldrh r3, [r3] + 1525 .loc 1 313 105 discriminator 2 + 1526 0028 03F00203 and r3, r3, #2 + 1527 .loc 1 313 77 discriminator 2 + 1528 002c 002B cmp r3, #0 + 1529 002e 05D1 bne .L112 + 1530 .loc 1 313 129 discriminator 4 + 1531 0030 6E4B ldr r3, .L126+8 + 1532 0032 1B88 ldrh r3, [r3] + 1533 .loc 1 313 144 discriminator 4 + 1534 0034 03F01003 and r3, r3, #16 + 1535 .loc 1 313 160 discriminator 4 + 1536 0038 002B cmp r3, #0 + 1537 003a 01D0 beq .L113 + 1538 .L112: + 1539 .loc 1 313 160 is_stmt 0 discriminator 5 + 1540 003c 0123 movs r3, #1 + 1541 .loc 1 313 160 + 1542 003e 00E0 b .L114 + 1543 .L113: + 1544 .loc 1 313 160 discriminator 6 + 1545 0040 0023 movs r3, #0 + 1546 .L114: + 1547 .loc 1 313 160 discriminator 8 + 1548 0042 03F00103 and r3, r3, #1 + 1549 0046 D9B2 uxtb r1, r3 + 1550 .loc 1 313 38 is_stmt 1 discriminator 8 + 1551 0048 694A ldr r2, .L126+12 + 1552 004a 1379 ldrb r3, [r2, #4] + 1553 004c 61F38203 bfi r3, r1, #2, #1 + 1554 0050 1371 strb r3, [r2, #4] + 314:Core/Src/state_machine.c **** state.error_type.voltage_error = (error_data.error_sources & (1 << 2)|| error_data.error_sources + 1555 .loc 1 314 47 + 1556 0052 664B ldr r3, .L126+8 + 1557 0054 1B88 ldrh r3, [r3] + 1558 .loc 1 314 62 + 1559 0056 03F00403 and r3, r3, #4 + 1560 .loc 1 314 188 + 1561 005a 002B cmp r3, #0 + 1562 005c 11D1 bne .L115 + 1563 .loc 1 314 85 discriminator 2 + 1564 005e 634B ldr r3, .L126+8 + 1565 0060 1B88 ldrh r3, [r3] + 1566 .loc 1 314 100 discriminator 2 + 1567 0062 03F00803 and r3, r3, #8 + 1568 .loc 1 314 72 discriminator 2 + 1569 0066 002B cmp r3, #0 + 1570 0068 0BD1 bne .L115 + 1571 .loc 1 314 123 discriminator 4 + 1572 006a 604B ldr r3, .L126+8 + 1573 006c 1B88 ldrh r3, [r3] + ARM GAS /tmp/cctkPVvk.s page 34 + + + 1574 .loc 1 314 138 discriminator 4 + 1575 006e 03F02003 and r3, r3, #32 + 1576 .loc 1 314 110 discriminator 4 + 1577 0072 002B cmp r3, #0 + 1578 0074 05D1 bne .L115 + 1579 .loc 1 314 175 discriminator 6 + 1580 0076 5F4B ldr r3, .L126+16 + 1581 0078 1B68 ldr r3, [r3] + 1582 .loc 1 314 188 discriminator 6 + 1583 007a 47F22F52 movw r2, #29999 + 1584 007e 9342 cmp r3, r2 + 1585 0080 01DC bgt .L116 + 1586 .L115: + 1587 .loc 1 314 188 is_stmt 0 discriminator 7 + 1588 0082 0123 movs r3, #1 + 1589 .loc 1 314 188 + 1590 0084 00E0 b .L117 + 1591 .L116: + 1592 .loc 1 314 188 discriminator 8 + 1593 0086 0023 movs r3, #0 + 1594 .L117: + 1595 .loc 1 314 188 discriminator 10 + 1596 0088 03F00103 and r3, r3, #1 + 1597 008c D9B2 uxtb r1, r3 + 1598 .loc 1 314 34 is_stmt 1 discriminator 10 + 1599 008e 584A ldr r2, .L126+12 + 1600 0090 1379 ldrb r3, [r2, #4] + 1601 0092 61F34513 bfi r3, r1, #5, #1 + 1602 0096 1371 strb r3, [r2, #4] + 315:Core/Src/state_machine.c **** state.error_type.bms_timeout = (error_data.error_sources & (1 << 7)) ? 1 : 0; + 1603 .loc 1 315 45 + 1604 0098 544B ldr r3, .L126+8 + 1605 009a 1B88 ldrh r3, [r3] + 1606 .loc 1 315 76 + 1607 009c DB11 asrs r3, r3, #7 + 1608 009e 03F00103 and r3, r3, #1 + 1609 00a2 D9B2 uxtb r1, r3 + 1610 .loc 1 315 32 + 1611 00a4 524A ldr r2, .L126+12 + 1612 00a6 1379 ldrb r3, [r2, #4] + 1613 00a8 61F30003 bfi r3, r1, #0, #1 + 1614 00ac 1371 strb r3, [r2, #4] + 316:Core/Src/state_machine.c **** state.error_type.bms_fault = (error_data.error_sources & (1 << 8) || error_data.error_sources & ( + 1615 .loc 1 316 43 + 1616 00ae 4F4B ldr r3, .L126+8 + 1617 00b0 1B88 ldrh r3, [r3] + 1618 .loc 1 316 58 + 1619 00b2 03F48073 and r3, r3, #256 + 1620 .loc 1 316 153 + 1621 00b6 002B cmp r3, #0 + 1622 00b8 0BD1 bne .L118 + 1623 .loc 1 316 82 discriminator 2 + 1624 00ba 4C4B ldr r3, .L126+8 + 1625 00bc 1B88 ldrh r3, [r3] + 1626 .loc 1 316 97 discriminator 2 + 1627 00be 03F48063 and r3, r3, #1024 + 1628 .loc 1 316 69 discriminator 2 + ARM GAS /tmp/cctkPVvk.s page 35 + + + 1629 00c2 002B cmp r3, #0 + 1630 00c4 05D1 bne .L118 + 1631 .loc 1 316 122 discriminator 4 + 1632 00c6 494B ldr r3, .L126+8 + 1633 00c8 1B88 ldrh r3, [r3] + 1634 .loc 1 316 137 discriminator 4 + 1635 00ca 03F40073 and r3, r3, #512 + 1636 .loc 1 316 153 discriminator 4 + 1637 00ce 002B cmp r3, #0 + 1638 00d0 01D0 beq .L119 + 1639 .L118: + 1640 .loc 1 316 153 is_stmt 0 discriminator 5 + 1641 00d2 0123 movs r3, #1 + 1642 .loc 1 316 153 + 1643 00d4 00E0 b .L120 + 1644 .L119: + 1645 .loc 1 316 153 discriminator 6 + 1646 00d6 0023 movs r3, #0 + 1647 .L120: + 1648 .loc 1 316 153 discriminator 8 + 1649 00d8 03F00103 and r3, r3, #1 + 1650 00dc D9B2 uxtb r1, r3 + 1651 .loc 1 316 30 is_stmt 1 discriminator 8 + 1652 00de 444A ldr r2, .L126+12 + 1653 00e0 1379 ldrb r3, [r2, #4] + 1654 00e2 61F34103 bfi r3, r1, #1, #1 + 1655 00e6 1371 strb r3, [r2, #4] + 317:Core/Src/state_machine.c **** //SEK_EEPROM_ERR: state.error_type.eeprom_error = 1; + 318:Core/Src/state_machine.c **** //state.error_type.current_error = (powerground_status > 10 && CURRENT_MEASUREMENT < 500) ? 1 : 0 + 319:Core/Src/state_machine.c **** state.error_type.current_sensor_missing = (!CURRENT_MEASUREMENT_ON) ? 1 : 0; + 1656 .loc 1 319 75 + 1657 00e8 434B ldr r3, .L126+20 + 1658 00ea 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 1659 00ec 83F00103 eor r3, r3, #1 + 1660 00f0 D9B2 uxtb r1, r3 + 1661 .loc 1 319 43 + 1662 00f2 3F4A ldr r2, .L126+12 + 1663 00f4 1379 ldrb r3, [r2, #4] + 1664 00f6 61F30413 bfi r3, r1, #4, #1 + 1665 00fa 1371 strb r3, [r2, #4] + 320:Core/Src/state_machine.c **** state.error_type.voltage_missing = (RELAY_BAT_SIDE_VOLTAGE < 1000) ? 1 : 0; + 1666 .loc 1 320 74 + 1667 00fc 3D4B ldr r3, .L126+16 + 1668 00fe 1B68 ldr r3, [r3] + 1669 0100 40F2E732 movw r2, #999 + 1670 0104 9342 cmp r3, r2 + 1671 0106 D4BF ite le + 1672 0108 0123 movle r3, #1 + 1673 010a 0023 movgt r3, #0 + 1674 010c D9B2 uxtb r1, r3 + 1675 .loc 1 320 36 + 1676 010e 384A ldr r2, .L126+12 + 1677 0110 1379 ldrb r3, [r2, #4] + 1678 0112 61F38613 bfi r3, r1, #6, #1 + 1679 0116 1371 strb r3, [r2, #4] + 321:Core/Src/state_machine.c **** + 322:Core/Src/state_machine.c **** + ARM GAS /tmp/cctkPVvk.s page 36 + + + 323:Core/Src/state_machine.c **** if (state.error_type.current_error == 1 || state.error_type.current_sensor_missing == 1 || //stat + 1680 .loc 1 323 38 + 1681 0118 354B ldr r3, .L126+12 + 1682 011a 1B79 ldrb r3, [r3, #4] @ zero_extendqisi2 + 1683 011c 03F00803 and r3, r3, #8 + 1684 0120 DBB2 uxtb r3, r3 + 1685 .loc 1 323 6 + 1686 0122 002B cmp r3, #0 + 1687 0124 30D1 bne .L121 + 1688 .loc 1 323 86 discriminator 1 + 1689 0126 324B ldr r3, .L126+12 + 1690 0128 1B79 ldrb r3, [r3, #4] @ zero_extendqisi2 + 1691 012a 03F01003 and r3, r3, #16 + 1692 012e DBB2 uxtb r3, r3 + 1693 .loc 1 323 43 discriminator 1 + 1694 0130 002B cmp r3, #0 + 1695 0132 29D1 bne .L121 + 324:Core/Src/state_machine.c **** state.error_type.state_transition_fail == 1 || state.error_type.temperature_error == 1 || sta + 1696 .loc 1 324 46 + 1697 0134 2E4B ldr r3, .L126+12 + 1698 0136 1B79 ldrb r3, [r3, #4] @ zero_extendqisi2 + 1699 0138 23F07F03 bic r3, r3, #127 + 1700 013c DBB2 uxtb r3, r3 + 323:Core/Src/state_machine.c **** state.error_type.state_transition_fail == 1 || state.error_type.temperature_error == 1 || sta + 1701 .loc 1 323 91 discriminator 2 + 1702 013e 002B cmp r3, #0 + 1703 0140 22D1 bne .L121 + 1704 .loc 1 324 89 + 1705 0142 2B4B ldr r3, .L126+12 + 1706 0144 1B79 ldrb r3, [r3, #4] @ zero_extendqisi2 + 1707 0146 03F00403 and r3, r3, #4 + 1708 014a DBB2 uxtb r3, r3 + 1709 .loc 1 324 51 + 1710 014c 002B cmp r3, #0 + 1711 014e 1BD1 bne .L121 + 1712 .loc 1 324 128 discriminator 1 + 1713 0150 274B ldr r3, .L126+12 + 1714 0152 1B79 ldrb r3, [r3, #4] @ zero_extendqisi2 + 1715 0154 03F02003 and r3, r3, #32 + 1716 0158 DBB2 uxtb r3, r3 + 1717 .loc 1 324 94 discriminator 1 + 1718 015a 002B cmp r3, #0 + 1719 015c 14D1 bne .L121 + 325:Core/Src/state_machine.c **** state.error_type.voltage_missing == 1 || state.error_type.bms_fault == 1 || state.error_type. + 1720 .loc 1 325 40 + 1721 015e 244B ldr r3, .L126+12 + 1722 0160 1B79 ldrb r3, [r3, #4] @ zero_extendqisi2 + 1723 0162 03F04003 and r3, r3, #64 + 1724 0166 DBB2 uxtb r3, r3 + 324:Core/Src/state_machine.c **** state.error_type.state_transition_fail == 1 || state.error_type.temperature_error == 1 || sta + 1725 .loc 1 324 133 discriminator 2 + 1726 0168 002B cmp r3, #0 + 1727 016a 0DD1 bne .L121 + 1728 .loc 1 325 75 + 1729 016c 204B ldr r3, .L126+12 + 1730 016e 1B79 ldrb r3, [r3, #4] @ zero_extendqisi2 + 1731 0170 03F00203 and r3, r3, #2 + ARM GAS /tmp/cctkPVvk.s page 37 + + + 1732 0174 DBB2 uxtb r3, r3 + 1733 .loc 1 325 45 + 1734 0176 002B cmp r3, #0 + 1735 0178 06D1 bne .L121 + 1736 .loc 1 325 112 discriminator 1 + 1737 017a 1D4B ldr r3, .L126+12 + 1738 017c 1B79 ldrb r3, [r3, #4] @ zero_extendqisi2 + 1739 017e 03F00103 and r3, r3, #1 + 1740 0182 DBB2 uxtb r3, r3 + 1741 .loc 1 325 80 discriminator 1 + 1742 0184 002B cmp r3, #0 + 1743 0186 19D0 beq .L122 + 1744 .L121: + 326:Core/Src/state_machine.c **** { + 327:Core/Src/state_machine.c **** if (state.current_state != STATE_INACTIVE && state.current_state != STATE_ERROR) + 1745 .loc 1 327 14 + 1746 0188 194B ldr r3, .L126+12 + 1747 018a 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 1748 .loc 1 327 8 + 1749 018c 002B cmp r3, #0 + 1750 018e 06D0 beq .L123 + 1751 .loc 1 327 55 discriminator 1 + 1752 0190 174B ldr r3, .L126+12 + 1753 0192 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 1754 .loc 1 327 47 discriminator 1 + 1755 0194 072B cmp r3, #7 + 1756 0196 02D0 beq .L123 + 328:Core/Src/state_machine.c **** state.current_state = STATE_DISCHARGE; + 1757 .loc 1 328 27 + 1758 0198 154B ldr r3, .L126+12 + 1759 019a 0422 movs r2, #4 + 1760 019c 1A70 strb r2, [r3] + 1761 .L123: + 329:Core/Src/state_machine.c **** state.target_state = STATE_ERROR; + 1762 .loc 1 329 24 + 1763 019e 144B ldr r3, .L126+12 + 1764 01a0 0722 movs r2, #7 + 1765 01a2 5A70 strb r2, [r3, #1] + 330:Core/Src/state_machine.c **** PWM_powerground_control(255); + 1766 .loc 1 330 5 + 1767 01a4 FF20 movs r0, #255 + 1768 01a6 FFF7FEFF bl PWM_powerground_control + 331:Core/Src/state_machine.c **** error_timer = HAL_GetTick() + ERROR_LATCH_TIME; + 1769 .loc 1 331 19 + 1770 01aa FFF7FEFF bl HAL_GetTick + 1771 01ae 0346 mov r3, r0 + 1772 .loc 1 331 33 discriminator 1 + 1773 01b0 03F51C53 add r3, r3, #9984 + 1774 01b4 1033 adds r3, r3, #16 + 1775 .loc 1 331 17 discriminator 1 + 1776 01b6 114A ldr r2, .L126+24 + 1777 01b8 1360 str r3, [r2] + 1778 .loc 1 331 17 is_stmt 0 + 1779 01ba 0DE0 b .L124 + 1780 .L122: + 332:Core/Src/state_machine.c **** } else if (state.current_state == STATE_ERROR && error_timer < HAL_GetTick()){ + 1781 .loc 1 332 19 is_stmt 1 + ARM GAS /tmp/cctkPVvk.s page 38 + + + 1782 01bc 0C4B ldr r3, .L126+12 + 1783 01be 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 1784 .loc 1 332 13 + 1785 01c0 072B cmp r3, #7 + 1786 01c2 09D1 bne .L124 + 1787 .loc 1 332 66 discriminator 1 + 1788 01c4 FFF7FEFF bl HAL_GetTick + 1789 01c8 0246 mov r2, r0 + 1790 .loc 1 332 64 discriminator 1 + 1791 01ca 0C4B ldr r3, .L126+24 + 1792 01cc 1B68 ldr r3, [r3] + 1793 .loc 1 332 49 discriminator 1 + 1794 01ce 9A42 cmp r2, r3 + 1795 01d0 02D9 bls .L124 + 333:Core/Src/state_machine.c **** state.target_state = STATE_INACTIVE; + 1796 .loc 1 333 24 + 1797 01d2 074B ldr r3, .L126+12 + 1798 01d4 0022 movs r2, #0 + 1799 01d6 5A70 strb r2, [r3, #1] + 1800 .L124: + 334:Core/Src/state_machine.c **** } + 335:Core/Src/state_machine.c **** sm_set_error_source(); + 1801 .loc 1 335 3 + 1802 01d8 FFF7FEFF bl sm_set_error_source + 1803 01dc 00E0 b .L108 + 1804 .L125: + 312:Core/Src/state_machine.c **** state.error_type.temperature_error = (error_data.error_sources & (1 << 0) || error_data.error_sou + 1805 .loc 1 312 54 + 1806 01de 00BF nop + 1807 .L108: + 336:Core/Src/state_machine.c **** } + 1808 .loc 1 336 1 + 1809 01e0 80BD pop {r7, pc} + 1810 .L127: + 1811 01e2 00BF .align 2 + 1812 .L126: + 1813 01e4 00000000 .word programming_mode + 1814 01e8 00000000 .word debugging_mode + 1815 01ec 00000000 .word error_data + 1816 01f0 00000000 .word state + 1817 01f4 00000000 .word RELAY_BAT_SIDE_VOLTAGE + 1818 01f8 00000000 .word CURRENT_MEASUREMENT_ON + 1819 01fc 00000000 .word error_timer + 1820 .cfi_endproc + 1821 .LFE139: + 1823 .section .text.sm_set_error_source,"ax",%progbits + 1824 .align 1 + 1825 .global sm_set_error_source + 1826 .syntax unified + 1827 .thumb + 1828 .thumb_func + 1830 sm_set_error_source: + 1831 .LFB140: + 337:Core/Src/state_machine.c **** + 338:Core/Src/state_machine.c **** void sm_set_error_source(){ + 1832 .loc 1 338 27 + 1833 .cfi_startproc + ARM GAS /tmp/cctkPVvk.s page 39 + + + 1834 @ args = 0, pretend = 0, frame = 0 + 1835 @ frame_needed = 1, uses_anonymous_args = 0 + 1836 @ link register save eliminated. + 1837 0000 80B4 push {r7} + 1838 .cfi_def_cfa_offset 4 + 1839 .cfi_offset 7, -4 + 1840 0002 00AF add r7, sp, #0 + 1841 .cfi_def_cfa_register 7 + 339:Core/Src/state_machine.c **** state.error_source = 0; + 1842 .loc 1 339 22 + 1843 0004 414B ldr r3, .L129 + 1844 0006 0022 movs r2, #0 + 1845 0008 5A80 strh r2, [r3, #2] @ movhi + 340:Core/Src/state_machine.c **** state.error_source |= (state.error_type.bms_timeout << 0); + 1846 .loc 1 340 8 + 1847 000a 404B ldr r3, .L129 + 1848 000c 5B88 ldrh r3, [r3, #2] + 1849 .loc 1 340 42 + 1850 000e 3F4A ldr r2, .L129 + 1851 0010 1279 ldrb r2, [r2, #4] + 1852 0012 C2F30002 ubfx r2, r2, #0, #1 + 1853 0016 D2B2 uxtb r2, r2 + 1854 .loc 1 340 22 + 1855 0018 1343 orrs r3, r3, r2 + 1856 001a 9AB2 uxth r2, r3 + 1857 001c 3B4B ldr r3, .L129 + 1858 001e 5A80 strh r2, [r3, #2] @ movhi + 341:Core/Src/state_machine.c **** state.error_source |= (state.error_type.bms_fault << 1); + 1859 .loc 1 341 8 + 1860 0020 3A4B ldr r3, .L129 + 1861 0022 5B88 ldrh r3, [r3, #2] + 1862 0024 1AB2 sxth r2, r3 + 1863 .loc 1 341 42 + 1864 0026 394B ldr r3, .L129 + 1865 0028 1B79 ldrb r3, [r3, #4] + 1866 002a C3F34003 ubfx r3, r3, #1, #1 + 1867 002e DBB2 uxtb r3, r3 + 1868 .loc 1 341 22 + 1869 0030 1BB2 sxth r3, r3 + 1870 0032 5B00 lsls r3, r3, #1 + 1871 0034 1BB2 sxth r3, r3 + 1872 0036 1343 orrs r3, r3, r2 + 1873 0038 1BB2 sxth r3, r3 + 1874 003a 9AB2 uxth r2, r3 + 1875 003c 334B ldr r3, .L129 + 1876 003e 5A80 strh r2, [r3, #2] @ movhi + 342:Core/Src/state_machine.c **** state.error_source |= (state.error_type.temperature_error << 2); + 1877 .loc 1 342 8 + 1878 0040 324B ldr r3, .L129 + 1879 0042 5B88 ldrh r3, [r3, #2] + 1880 0044 1AB2 sxth r2, r3 + 1881 .loc 1 342 42 + 1882 0046 314B ldr r3, .L129 + 1883 0048 1B79 ldrb r3, [r3, #4] + 1884 004a C3F38003 ubfx r3, r3, #2, #1 + 1885 004e DBB2 uxtb r3, r3 + 1886 .loc 1 342 22 + ARM GAS /tmp/cctkPVvk.s page 40 + + + 1887 0050 1BB2 sxth r3, r3 + 1888 0052 9B00 lsls r3, r3, #2 + 1889 0054 1BB2 sxth r3, r3 + 1890 0056 1343 orrs r3, r3, r2 + 1891 0058 1BB2 sxth r3, r3 + 1892 005a 9AB2 uxth r2, r3 + 1893 005c 2B4B ldr r3, .L129 + 1894 005e 5A80 strh r2, [r3, #2] @ movhi + 343:Core/Src/state_machine.c **** state.error_source |= (state.error_type.current_error << 3); + 1895 .loc 1 343 8 + 1896 0060 2A4B ldr r3, .L129 + 1897 0062 5B88 ldrh r3, [r3, #2] + 1898 0064 1AB2 sxth r2, r3 + 1899 .loc 1 343 42 + 1900 0066 294B ldr r3, .L129 + 1901 0068 1B79 ldrb r3, [r3, #4] + 1902 006a C3F3C003 ubfx r3, r3, #3, #1 + 1903 006e DBB2 uxtb r3, r3 + 1904 .loc 1 343 22 + 1905 0070 1BB2 sxth r3, r3 + 1906 0072 DB00 lsls r3, r3, #3 + 1907 0074 1BB2 sxth r3, r3 + 1908 0076 1343 orrs r3, r3, r2 + 1909 0078 1BB2 sxth r3, r3 + 1910 007a 9AB2 uxth r2, r3 + 1911 007c 234B ldr r3, .L129 + 1912 007e 5A80 strh r2, [r3, #2] @ movhi + 344:Core/Src/state_machine.c **** + 345:Core/Src/state_machine.c **** state.error_source |= (state.error_type.current_sensor_missing << 4); + 1913 .loc 1 345 8 + 1914 0080 224B ldr r3, .L129 + 1915 0082 5B88 ldrh r3, [r3, #2] + 1916 0084 1AB2 sxth r2, r3 + 1917 .loc 1 345 42 + 1918 0086 214B ldr r3, .L129 + 1919 0088 1B79 ldrb r3, [r3, #4] + 1920 008a C3F30013 ubfx r3, r3, #4, #1 + 1921 008e DBB2 uxtb r3, r3 + 1922 .loc 1 345 22 + 1923 0090 1BB2 sxth r3, r3 + 1924 0092 1B01 lsls r3, r3, #4 + 1925 0094 1BB2 sxth r3, r3 + 1926 0096 1343 orrs r3, r3, r2 + 1927 0098 1BB2 sxth r3, r3 + 1928 009a 9AB2 uxth r2, r3 + 1929 009c 1B4B ldr r3, .L129 + 1930 009e 5A80 strh r2, [r3, #2] @ movhi + 346:Core/Src/state_machine.c **** state.error_source |= (state.error_type.voltage_error << 5); + 1931 .loc 1 346 8 + 1932 00a0 1A4B ldr r3, .L129 + 1933 00a2 5B88 ldrh r3, [r3, #2] + 1934 00a4 1AB2 sxth r2, r3 + 1935 .loc 1 346 42 + 1936 00a6 194B ldr r3, .L129 + 1937 00a8 1B79 ldrb r3, [r3, #4] + 1938 00aa C3F34013 ubfx r3, r3, #5, #1 + 1939 00ae DBB2 uxtb r3, r3 + ARM GAS /tmp/cctkPVvk.s page 41 + + + 1940 .loc 1 346 22 + 1941 00b0 1BB2 sxth r3, r3 + 1942 00b2 5B01 lsls r3, r3, #5 + 1943 00b4 1BB2 sxth r3, r3 + 1944 00b6 1343 orrs r3, r3, r2 + 1945 00b8 1BB2 sxth r3, r3 + 1946 00ba 9AB2 uxth r2, r3 + 1947 00bc 134B ldr r3, .L129 + 1948 00be 5A80 strh r2, [r3, #2] @ movhi + 347:Core/Src/state_machine.c **** state.error_source |= (state.error_type.voltage_missing << 6); + 1949 .loc 1 347 8 + 1950 00c0 124B ldr r3, .L129 + 1951 00c2 5B88 ldrh r3, [r3, #2] + 1952 00c4 1AB2 sxth r2, r3 + 1953 .loc 1 347 42 + 1954 00c6 114B ldr r3, .L129 + 1955 00c8 1B79 ldrb r3, [r3, #4] + 1956 00ca C3F38013 ubfx r3, r3, #6, #1 + 1957 00ce DBB2 uxtb r3, r3 + 1958 .loc 1 347 22 + 1959 00d0 1BB2 sxth r3, r3 + 1960 00d2 9B01 lsls r3, r3, #6 + 1961 00d4 1BB2 sxth r3, r3 + 1962 00d6 1343 orrs r3, r3, r2 + 1963 00d8 1BB2 sxth r3, r3 + 1964 00da 9AB2 uxth r2, r3 + 1965 00dc 0B4B ldr r3, .L129 + 1966 00de 5A80 strh r2, [r3, #2] @ movhi + 348:Core/Src/state_machine.c **** state.error_source |= (state.error_type.state_transition_fail << 7); + 1967 .loc 1 348 8 + 1968 00e0 0A4B ldr r3, .L129 + 1969 00e2 5B88 ldrh r3, [r3, #2] + 1970 00e4 1AB2 sxth r2, r3 + 1971 .loc 1 348 42 + 1972 00e6 094B ldr r3, .L129 + 1973 00e8 1B79 ldrb r3, [r3, #4] + 1974 00ea C3F3C013 ubfx r3, r3, #7, #1 + 1975 00ee DBB2 uxtb r3, r3 + 1976 .loc 1 348 22 + 1977 00f0 1BB2 sxth r3, r3 + 1978 00f2 DB01 lsls r3, r3, #7 + 1979 00f4 1BB2 sxth r3, r3 + 1980 00f6 1343 orrs r3, r3, r2 + 1981 00f8 1BB2 sxth r3, r3 + 1982 00fa 9AB2 uxth r2, r3 + 1983 00fc 034B ldr r3, .L129 + 1984 00fe 5A80 strh r2, [r3, #2] @ movhi + 349:Core/Src/state_machine.c **** } + 1985 .loc 1 349 1 + 1986 0100 00BF nop + 1987 0102 BD46 mov sp, r7 + 1988 .cfi_def_cfa_register 13 + 1989 @ sp needed + 1990 0104 5DF8047B ldr r7, [sp], #4 + 1991 .cfi_restore 7 + 1992 .cfi_def_cfa_offset 0 + 1993 0108 7047 bx lr + ARM GAS /tmp/cctkPVvk.s page 42 + + + 1994 .L130: + 1995 010a 00BF .align 2 + 1996 .L129: + 1997 010c 00000000 .word state + 1998 .cfi_endproc + 1999 .LFE140: + 2001 .section .text.sm_update_inactive,"ax",%progbits + 2002 .align 1 + 2003 .global sm_update_inactive + 2004 .syntax unified + 2005 .thumb + 2006 .thumb_func + 2008 sm_update_inactive: + 2009 .LFB141: + 350:Core/Src/state_machine.c **** + 351:Core/Src/state_machine.c **** State sm_update_inactive(){ + 2010 .loc 1 351 27 + 2011 .cfi_startproc + 2012 @ args = 0, pretend = 0, frame = 0 + 2013 @ frame_needed = 1, uses_anonymous_args = 0 + 2014 @ link register save eliminated. + 2015 0000 80B4 push {r7} + 2016 .cfi_def_cfa_offset 4 + 2017 .cfi_offset 7, -4 + 2018 0002 00AF add r7, sp, #0 + 2019 .cfi_def_cfa_register 7 + 352:Core/Src/state_machine.c **** switch (state.target_state) { + 2020 .loc 1 352 16 + 2021 0004 0B4B ldr r3, .L137 + 2022 0006 5B78 ldrb r3, [r3, #1] @ zero_extendqisi2 + 2023 .loc 1 352 3 + 2024 0008 072B cmp r3, #7 + 2025 000a 0AD0 beq .L132 + 2026 000c 072B cmp r3, #7 + 2027 000e 0ADC bgt .L133 + 2028 0010 012B cmp r3, #1 + 2029 0012 02D0 beq .L134 + 2030 0014 052B cmp r3, #5 + 2031 0016 02D0 beq .L135 + 2032 0018 05E0 b .L133 + 2033 .L134: + 353:Core/Src/state_machine.c **** case STATE_PRECHARGE: + 354:Core/Src/state_machine.c **** return STATE_PRECHARGE; + 2034 .loc 1 354 14 + 2035 001a 0123 movs r3, #1 + 2036 001c 04E0 b .L136 + 2037 .L135: + 355:Core/Src/state_machine.c **** case STATE_CHARGING_PRECHARGE: + 356:Core/Src/state_machine.c **** return STATE_CHARGING_PRECHARGE; + 2038 .loc 1 356 14 + 2039 001e 0523 movs r3, #5 + 2040 0020 02E0 b .L136 + 2041 .L132: + 357:Core/Src/state_machine.c **** case STATE_ERROR: + 358:Core/Src/state_machine.c **** return STATE_ERROR; + 2042 .loc 1 358 14 + 2043 0022 0723 movs r3, #7 + ARM GAS /tmp/cctkPVvk.s page 43 + + + 2044 0024 00E0 b .L136 + 2045 .L133: + 359:Core/Src/state_machine.c **** default: + 360:Core/Src/state_machine.c **** return STATE_INACTIVE; + 2046 .loc 1 360 14 + 2047 0026 0023 movs r3, #0 + 2048 .L136: + 361:Core/Src/state_machine.c **** } + 362:Core/Src/state_machine.c **** } + 2049 .loc 1 362 1 + 2050 0028 1846 mov r0, r3 + 2051 002a BD46 mov sp, r7 + 2052 .cfi_def_cfa_register 13 + 2053 @ sp needed + 2054 002c 5DF8047B ldr r7, [sp], #4 + 2055 .cfi_restore 7 + 2056 .cfi_def_cfa_offset 0 + 2057 0030 7047 bx lr + 2058 .L138: + 2059 0032 00BF .align 2 + 2060 .L137: + 2061 0034 00000000 .word state + 2062 .cfi_endproc + 2063 .LFE141: + 2065 .section .text.sm_update_precharge,"ax",%progbits + 2066 .align 1 + 2067 .global sm_update_precharge + 2068 .syntax unified + 2069 .thumb + 2070 .thumb_func + 2072 sm_update_precharge: + 2073 .LFB142: + 363:Core/Src/state_machine.c **** + 364:Core/Src/state_machine.c **** State sm_update_precharge(){ + 2074 .loc 1 364 28 + 2075 .cfi_startproc + 2076 @ args = 0, pretend = 0, frame = 0 + 2077 @ frame_needed = 1, uses_anonymous_args = 0 + 2078 @ link register save eliminated. + 2079 0000 80B4 push {r7} + 2080 .cfi_def_cfa_offset 4 + 2081 .cfi_offset 7, -4 + 2082 0002 00AF add r7, sp, #0 + 2083 .cfi_def_cfa_register 7 + 365:Core/Src/state_machine.c **** switch (state.target_state) { + 2084 .loc 1 365 16 + 2085 0004 084B ldr r3, .L145 + 2086 0006 5B78 ldrb r3, [r3, #1] @ zero_extendqisi2 + 2087 .loc 1 365 3 + 2088 0008 002B cmp r3, #0 + 2089 000a 02D0 beq .L140 + 2090 000c 022B cmp r3, #2 + 2091 000e 02D0 beq .L141 + 2092 0010 03E0 b .L144 + 2093 .L140: + 366:Core/Src/state_machine.c **** case STATE_INACTIVE: // if CAN Signal 0000 0000 then immidiete shutdown + 367:Core/Src/state_machine.c **** return STATE_DISCHARGE; + ARM GAS /tmp/cctkPVvk.s page 44 + + + 2094 .loc 1 367 14 + 2095 0012 0423 movs r3, #4 + 2096 0014 02E0 b .L143 + 2097 .L141: + 368:Core/Src/state_machine.c **** case STATE_READY: + 369:Core/Src/state_machine.c **** return STATE_READY; + 2098 .loc 1 369 14 + 2099 0016 0223 movs r3, #2 + 2100 0018 00E0 b .L143 + 2101 .L144: + 370:Core/Src/state_machine.c **** default: + 371:Core/Src/state_machine.c **** return STATE_PRECHARGE; + 2102 .loc 1 371 14 + 2103 001a 0123 movs r3, #1 + 2104 .L143: + 372:Core/Src/state_machine.c **** } + 373:Core/Src/state_machine.c **** } + 2105 .loc 1 373 1 + 2106 001c 1846 mov r0, r3 + 2107 001e BD46 mov sp, r7 + 2108 .cfi_def_cfa_register 13 + 2109 @ sp needed + 2110 0020 5DF8047B ldr r7, [sp], #4 + 2111 .cfi_restore 7 + 2112 .cfi_def_cfa_offset 0 + 2113 0024 7047 bx lr + 2114 .L146: + 2115 0026 00BF .align 2 + 2116 .L145: + 2117 0028 00000000 .word state + 2118 .cfi_endproc + 2119 .LFE142: + 2121 .section .text.sm_update_ready,"ax",%progbits + 2122 .align 1 + 2123 .global sm_update_ready + 2124 .syntax unified + 2125 .thumb + 2126 .thumb_func + 2128 sm_update_ready: + 2129 .LFB143: + 374:Core/Src/state_machine.c **** + 375:Core/Src/state_machine.c **** State sm_update_ready(){ + 2130 .loc 1 375 24 + 2131 .cfi_startproc + 2132 @ args = 0, pretend = 0, frame = 0 + 2133 @ frame_needed = 1, uses_anonymous_args = 0 + 2134 @ link register save eliminated. + 2135 0000 80B4 push {r7} + 2136 .cfi_def_cfa_offset 4 + 2137 .cfi_offset 7, -4 + 2138 0002 00AF add r7, sp, #0 + 2139 .cfi_def_cfa_register 7 + 376:Core/Src/state_machine.c **** switch (state.target_state) { + 2140 .loc 1 376 16 + 2141 0004 084B ldr r3, .L153 + 2142 0006 5B78 ldrb r3, [r3, #1] @ zero_extendqisi2 + 2143 .loc 1 376 3 + ARM GAS /tmp/cctkPVvk.s page 45 + + + 2144 0008 032B cmp r3, #3 + 2145 000a 02D0 beq .L148 + 2146 000c 042B cmp r3, #4 + 2147 000e 02D0 beq .L149 + 2148 0010 03E0 b .L152 + 2149 .L148: + 377:Core/Src/state_machine.c **** case STATE_ACTIVE: // if CAN Signal 1100 0000 then turn on powerground + 378:Core/Src/state_machine.c **** return STATE_ACTIVE; + 2150 .loc 1 378 14 + 2151 0012 0323 movs r3, #3 + 2152 0014 02E0 b .L151 + 2153 .L149: + 379:Core/Src/state_machine.c **** case STATE_DISCHARGE: // if CAN Signal 0000 0000 then shutdown + 380:Core/Src/state_machine.c **** return STATE_DISCHARGE; + 2154 .loc 1 380 14 + 2155 0016 0423 movs r3, #4 + 2156 0018 00E0 b .L151 + 2157 .L152: + 381:Core/Src/state_machine.c **** default: + 382:Core/Src/state_machine.c **** return STATE_READY; + 2158 .loc 1 382 14 + 2159 001a 0223 movs r3, #2 + 2160 .L151: + 383:Core/Src/state_machine.c **** } + 384:Core/Src/state_machine.c **** } + 2161 .loc 1 384 1 + 2162 001c 1846 mov r0, r3 + 2163 001e BD46 mov sp, r7 + 2164 .cfi_def_cfa_register 13 + 2165 @ sp needed + 2166 0020 5DF8047B ldr r7, [sp], #4 + 2167 .cfi_restore 7 + 2168 .cfi_def_cfa_offset 0 + 2169 0024 7047 bx lr + 2170 .L154: + 2171 0026 00BF .align 2 + 2172 .L153: + 2173 0028 00000000 .word state + 2174 .cfi_endproc + 2175 .LFE143: + 2177 .section .text.sm_update_active,"ax",%progbits + 2178 .align 1 + 2179 .global sm_update_active + 2180 .syntax unified + 2181 .thumb + 2182 .thumb_func + 2184 sm_update_active: + 2185 .LFB144: + 385:Core/Src/state_machine.c **** + 386:Core/Src/state_machine.c **** State sm_update_active(){ + 2186 .loc 1 386 25 + 2187 .cfi_startproc + 2188 @ args = 0, pretend = 0, frame = 0 + 2189 @ frame_needed = 1, uses_anonymous_args = 0 + 2190 @ link register save eliminated. + 2191 0000 80B4 push {r7} + 2192 .cfi_def_cfa_offset 4 + ARM GAS /tmp/cctkPVvk.s page 46 + + + 2193 .cfi_offset 7, -4 + 2194 0002 00AF add r7, sp, #0 + 2195 .cfi_def_cfa_register 7 + 387:Core/Src/state_machine.c **** switch (state.target_state) { + 2196 .loc 1 387 16 + 2197 0004 084B ldr r3, .L161 + 2198 0006 5B78 ldrb r3, [r3, #1] @ zero_extendqisi2 + 2199 .loc 1 387 3 + 2200 0008 022B cmp r3, #2 + 2201 000a 02D0 beq .L156 + 2202 000c 042B cmp r3, #4 + 2203 000e 02D0 beq .L157 + 2204 0010 03E0 b .L160 + 2205 .L156: + 388:Core/Src/state_machine.c **** case STATE_READY: // if CAN Signal 1000 0000 then turn oof powerground but stay read + 389:Core/Src/state_machine.c **** return STATE_READY; + 2206 .loc 1 389 14 + 2207 0012 0223 movs r3, #2 + 2208 0014 02E0 b .L159 + 2209 .L157: + 390:Core/Src/state_machine.c **** case STATE_DISCHARGE: // if CAN Signal 0000 0000 then shutdown + 391:Core/Src/state_machine.c **** return STATE_DISCHARGE; + 2210 .loc 1 391 14 + 2211 0016 0423 movs r3, #4 + 2212 0018 00E0 b .L159 + 2213 .L160: + 392:Core/Src/state_machine.c **** default: + 393:Core/Src/state_machine.c **** return STATE_ACTIVE; + 2214 .loc 1 393 14 + 2215 001a 0323 movs r3, #3 + 2216 .L159: + 394:Core/Src/state_machine.c **** } + 395:Core/Src/state_machine.c **** } + 2217 .loc 1 395 1 + 2218 001c 1846 mov r0, r3 + 2219 001e BD46 mov sp, r7 + 2220 .cfi_def_cfa_register 13 + 2221 @ sp needed + 2222 0020 5DF8047B ldr r7, [sp], #4 + 2223 .cfi_restore 7 + 2224 .cfi_def_cfa_offset 0 + 2225 0024 7047 bx lr + 2226 .L162: + 2227 0026 00BF .align 2 + 2228 .L161: + 2229 0028 00000000 .word state + 2230 .cfi_endproc + 2231 .LFE144: + 2233 .section .text.sm_update_discharge,"ax",%progbits + 2234 .align 1 + 2235 .global sm_update_discharge + 2236 .syntax unified + 2237 .thumb + 2238 .thumb_func + 2240 sm_update_discharge: + 2241 .LFB145: + 396:Core/Src/state_machine.c **** + ARM GAS /tmp/cctkPVvk.s page 47 + + + 397:Core/Src/state_machine.c **** State sm_update_discharge(){ + 2242 .loc 1 397 28 + 2243 .cfi_startproc + 2244 @ args = 0, pretend = 0, frame = 0 + 2245 @ frame_needed = 1, uses_anonymous_args = 0 + 2246 @ link register save eliminated. + 2247 0000 80B4 push {r7} + 2248 .cfi_def_cfa_offset 4 + 2249 .cfi_offset 7, -4 + 2250 0002 00AF add r7, sp, #0 + 2251 .cfi_def_cfa_register 7 + 398:Core/Src/state_machine.c **** switch (state.target_state) { + 2252 .loc 1 398 16 + 2253 0004 084B ldr r3, .L169 + 2254 0006 5B78 ldrb r3, [r3, #1] @ zero_extendqisi2 + 2255 .loc 1 398 3 + 2256 0008 002B cmp r3, #0 + 2257 000a 02D0 beq .L164 + 2258 000c 072B cmp r3, #7 + 2259 000e 02D0 beq .L165 + 2260 0010 03E0 b .L168 + 2261 .L164: + 399:Core/Src/state_machine.c **** case STATE_INACTIVE: + 400:Core/Src/state_machine.c **** return STATE_INACTIVE; + 2262 .loc 1 400 14 + 2263 0012 0023 movs r3, #0 + 2264 0014 02E0 b .L167 + 2265 .L165: + 401:Core/Src/state_machine.c **** case STATE_ERROR: + 402:Core/Src/state_machine.c **** return STATE_ERROR; + 2266 .loc 1 402 14 + 2267 0016 0723 movs r3, #7 + 2268 0018 00E0 b .L167 + 2269 .L168: + 403:Core/Src/state_machine.c **** default: + 404:Core/Src/state_machine.c **** return STATE_DISCHARGE; + 2270 .loc 1 404 14 + 2271 001a 0423 movs r3, #4 + 2272 .L167: + 405:Core/Src/state_machine.c **** } + 406:Core/Src/state_machine.c **** } + 2273 .loc 1 406 1 + 2274 001c 1846 mov r0, r3 + 2275 001e BD46 mov sp, r7 + 2276 .cfi_def_cfa_register 13 + 2277 @ sp needed + 2278 0020 5DF8047B ldr r7, [sp], #4 + 2279 .cfi_restore 7 + 2280 .cfi_def_cfa_offset 0 + 2281 0024 7047 bx lr + 2282 .L170: + 2283 0026 00BF .align 2 + 2284 .L169: + 2285 0028 00000000 .word state + 2286 .cfi_endproc + 2287 .LFE145: + 2289 .section .text.sm_update_charging_precharge,"ax",%progbits + ARM GAS /tmp/cctkPVvk.s page 48 + + + 2290 .align 1 + 2291 .global sm_update_charging_precharge + 2292 .syntax unified + 2293 .thumb + 2294 .thumb_func + 2296 sm_update_charging_precharge: + 2297 .LFB146: + 407:Core/Src/state_machine.c **** + 408:Core/Src/state_machine.c **** State sm_update_charging_precharge(){ + 2298 .loc 1 408 37 + 2299 .cfi_startproc + 2300 @ args = 0, pretend = 0, frame = 0 + 2301 @ frame_needed = 1, uses_anonymous_args = 0 + 2302 @ link register save eliminated. + 2303 0000 80B4 push {r7} + 2304 .cfi_def_cfa_offset 4 + 2305 .cfi_offset 7, -4 + 2306 0002 00AF add r7, sp, #0 + 2307 .cfi_def_cfa_register 7 + 409:Core/Src/state_machine.c **** switch (state.target_state) { + 2308 .loc 1 409 16 + 2309 0004 074B ldr r3, .L175 + 2310 0006 5B78 ldrb r3, [r3, #1] @ zero_extendqisi2 + 2311 .loc 1 409 3 + 2312 0008 042B cmp r3, #4 + 2313 000a 03D0 beq .L172 + 2314 000c 062B cmp r3, #6 + 2315 000e 03D1 bne .L173 + 410:Core/Src/state_machine.c **** case STATE_CHARGING: + 411:Core/Src/state_machine.c **** return STATE_CHARGING; + 2316 .loc 1 411 14 + 2317 0010 0623 movs r3, #6 + 2318 0012 02E0 b .L174 + 2319 .L172: + 412:Core/Src/state_machine.c **** case STATE_DISCHARGE: + 413:Core/Src/state_machine.c **** return STATE_DISCHARGE; + 2320 .loc 1 413 14 + 2321 0014 0423 movs r3, #4 + 2322 0016 00E0 b .L174 + 2323 .L173: + 414:Core/Src/state_machine.c **** default: + 415:Core/Src/state_machine.c **** return STATE_CHARGING_PRECHARGE; + 2324 .loc 1 415 14 + 2325 0018 0523 movs r3, #5 + 2326 .L174: + 416:Core/Src/state_machine.c **** } + 417:Core/Src/state_machine.c **** } + 2327 .loc 1 417 1 + 2328 001a 1846 mov r0, r3 + 2329 001c BD46 mov sp, r7 + 2330 .cfi_def_cfa_register 13 + 2331 @ sp needed + 2332 001e 5DF8047B ldr r7, [sp], #4 + 2333 .cfi_restore 7 + 2334 .cfi_def_cfa_offset 0 + 2335 0022 7047 bx lr + 2336 .L176: + ARM GAS /tmp/cctkPVvk.s page 49 + + + 2337 .align 2 + 2338 .L175: + 2339 0024 00000000 .word state + 2340 .cfi_endproc + 2341 .LFE146: + 2343 .section .text.sm_update_charging,"ax",%progbits + 2344 .align 1 + 2345 .global sm_update_charging + 2346 .syntax unified + 2347 .thumb + 2348 .thumb_func + 2350 sm_update_charging: + 2351 .LFB147: + 418:Core/Src/state_machine.c **** + 419:Core/Src/state_machine.c **** State sm_update_charging(){ + 2352 .loc 1 419 27 + 2353 .cfi_startproc + 2354 @ args = 0, pretend = 0, frame = 0 + 2355 @ frame_needed = 1, uses_anonymous_args = 0 + 2356 @ link register save eliminated. + 2357 0000 80B4 push {r7} + 2358 .cfi_def_cfa_offset 4 + 2359 .cfi_offset 7, -4 + 2360 0002 00AF add r7, sp, #0 + 2361 .cfi_def_cfa_register 7 + 420:Core/Src/state_machine.c **** switch (state.target_state) { + 2362 .loc 1 420 16 + 2363 0004 084B ldr r3, .L180 + 2364 0006 5B78 ldrb r3, [r3, #1] @ zero_extendqisi2 + 2365 .loc 1 420 3 + 2366 0008 042B cmp r3, #4 + 2367 000a 04D1 bne .L178 + 421:Core/Src/state_machine.c **** case STATE_DISCHARGE: + 422:Core/Src/state_machine.c **** currentAMSState = AMSIDLE; + 2368 .loc 1 422 23 + 2369 000c 074B ldr r3, .L180+4 + 2370 000e 0122 movs r2, #1 + 2371 0010 1A70 strb r2, [r3] + 423:Core/Src/state_machine.c **** return STATE_DISCHARGE; + 2372 .loc 1 423 14 + 2373 0012 0423 movs r3, #4 + 2374 0014 03E0 b .L179 + 2375 .L178: + 424:Core/Src/state_machine.c **** default: + 425:Core/Src/state_machine.c **** currentAMSState = AMSCHARGING; + 2376 .loc 1 425 23 + 2377 0016 054B ldr r3, .L180+4 + 2378 0018 0222 movs r2, #2 + 2379 001a 1A70 strb r2, [r3] + 426:Core/Src/state_machine.c **** return STATE_CHARGING; + 2380 .loc 1 426 14 + 2381 001c 0623 movs r3, #6 + 2382 .L179: + 427:Core/Src/state_machine.c **** } + 428:Core/Src/state_machine.c **** } + 2383 .loc 1 428 1 + 2384 001e 1846 mov r0, r3 + ARM GAS /tmp/cctkPVvk.s page 50 + + + 2385 0020 BD46 mov sp, r7 + 2386 .cfi_def_cfa_register 13 + 2387 @ sp needed + 2388 0022 5DF8047B ldr r7, [sp], #4 + 2389 .cfi_restore 7 + 2390 .cfi_def_cfa_offset 0 + 2391 0026 7047 bx lr + 2392 .L181: + 2393 .align 2 + 2394 .L180: + 2395 0028 00000000 .word state + 2396 002c 00000000 .word currentAMSState + 2397 .cfi_endproc + 2398 .LFE147: + 2400 .section .text.sm_update_error,"ax",%progbits + 2401 .align 1 + 2402 .global sm_update_error + 2403 .syntax unified + 2404 .thumb + 2405 .thumb_func + 2407 sm_update_error: + 2408 .LFB148: + 429:Core/Src/state_machine.c **** + 430:Core/Src/state_machine.c **** State sm_update_error(){ + 2409 .loc 1 430 24 + 2410 .cfi_startproc + 2411 @ args = 0, pretend = 0, frame = 0 + 2412 @ frame_needed = 1, uses_anonymous_args = 0 + 2413 @ link register save eliminated. + 2414 0000 80B4 push {r7} + 2415 .cfi_def_cfa_offset 4 + 2416 .cfi_offset 7, -4 + 2417 0002 00AF add r7, sp, #0 + 2418 .cfi_def_cfa_register 7 + 431:Core/Src/state_machine.c **** switch (state.target_state) { + 2419 .loc 1 431 16 + 2420 0004 074B ldr r3, .L186 + 2421 0006 5B78 ldrb r3, [r3, #1] @ zero_extendqisi2 + 2422 .loc 1 431 3 + 2423 0008 002B cmp r3, #0 + 2424 000a 03D0 beq .L183 + 2425 000c 042B cmp r3, #4 + 2426 000e 03D1 bne .L184 + 432:Core/Src/state_machine.c **** case STATE_DISCHARGE: + 433:Core/Src/state_machine.c **** return STATE_DISCHARGE; + 2427 .loc 1 433 14 + 2428 0010 0423 movs r3, #4 + 2429 0012 02E0 b .L185 + 2430 .L183: + 434:Core/Src/state_machine.c **** case STATE_INACTIVE: + 435:Core/Src/state_machine.c **** return STATE_INACTIVE; + 2431 .loc 1 435 14 + 2432 0014 0023 movs r3, #0 + 2433 0016 00E0 b .L185 + 2434 .L184: + 436:Core/Src/state_machine.c **** default: + 437:Core/Src/state_machine.c **** return STATE_ERROR; + ARM GAS /tmp/cctkPVvk.s page 51 + + + 2435 .loc 1 437 14 + 2436 0018 0723 movs r3, #7 + 2437 .L185: + 438:Core/Src/state_machine.c **** } + 439:Core/Src/state_machine.c **** } + 2438 .loc 1 439 1 + 2439 001a 1846 mov r0, r3 + 2440 001c BD46 mov sp, r7 + 2441 .cfi_def_cfa_register 13 + 2442 @ sp needed + 2443 001e 5DF8047B ldr r7, [sp], #4 + 2444 .cfi_restore 7 + 2445 .cfi_def_cfa_offset 0 + 2446 0022 7047 bx lr + 2447 .L187: + 2448 .align 2 + 2449 .L186: + 2450 0024 00000000 .word state + 2451 .cfi_endproc + 2452 .LFE148: + 2454 .section .text.sm_set_relay_positions,"ax",%progbits + 2455 .align 1 + 2456 .global sm_set_relay_positions + 2457 .syntax unified + 2458 .thumb + 2459 .thumb_func + 2461 sm_set_relay_positions: + 2462 .LFB149: + 440:Core/Src/state_machine.c **** + 441:Core/Src/state_machine.c **** void sm_set_relay_positions(State current_state){ + 2463 .loc 1 441 49 + 2464 .cfi_startproc + 2465 @ args = 0, pretend = 0, frame = 8 + 2466 @ frame_needed = 1, uses_anonymous_args = 0 + 2467 0000 80B5 push {r7, lr} + 2468 .cfi_def_cfa_offset 8 + 2469 .cfi_offset 7, -8 + 2470 .cfi_offset 14, -4 + 2471 0002 82B0 sub sp, sp, #8 + 2472 .cfi_def_cfa_offset 16 + 2473 0004 00AF add r7, sp, #0 + 2474 .cfi_def_cfa_register 7 + 2475 0006 0346 mov r3, r0 + 2476 0008 FB71 strb r3, [r7, #7] + 442:Core/Src/state_machine.c **** switch (state.current_state) { + 2477 .loc 1 442 16 + 2478 000a 314B ldr r3, .L201 + 2479 000c 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 2480 .loc 1 442 3 + 2481 000e 072B cmp r3, #7 + 2482 0010 5AD8 bhi .L199 + 2483 0012 01A2 adr r2, .L191 + 2484 0014 52F823F0 ldr pc, [r2, r3, lsl #2] + 2485 .p2align 2 + 2486 .L191: + 2487 0018 39000000 .word .L198+1 + 2488 001c 4B000000 .word .L197+1 + ARM GAS /tmp/cctkPVvk.s page 52 + + + 2489 0020 5D000000 .word .L196+1 + 2490 0024 6F000000 .word .L195+1 + 2491 0028 81000000 .word .L194+1 + 2492 002c 93000000 .word .L193+1 + 2493 0030 A5000000 .word .L192+1 + 2494 0034 B7000000 .word .L190+1 + 2495 .p2align 1 + 2496 .L198: + 443:Core/Src/state_machine.c **** case STATE_INACTIVE: + 444:Core/Src/state_machine.c **** sm_set_relay(RELAY_MAIN, 0); + 2497 .loc 1 444 7 + 2498 0038 0021 movs r1, #0 + 2499 003a 0020 movs r0, #0 + 2500 003c FFF7FEFF bl sm_set_relay + 445:Core/Src/state_machine.c **** sm_set_relay(RELAY_PRECHARGE, 0); + 2501 .loc 1 445 7 + 2502 0040 0021 movs r1, #0 + 2503 0042 0120 movs r0, #1 + 2504 0044 FFF7FEFF bl sm_set_relay + 446:Core/Src/state_machine.c **** break; + 2505 .loc 1 446 7 + 2506 0048 3EE0 b .L189 + 2507 .L197: + 447:Core/Src/state_machine.c **** case STATE_PRECHARGE: + 448:Core/Src/state_machine.c **** sm_set_relay(RELAY_MAIN, 0); + 2508 .loc 1 448 7 + 2509 004a 0021 movs r1, #0 + 2510 004c 0020 movs r0, #0 + 2511 004e FFF7FEFF bl sm_set_relay + 449:Core/Src/state_machine.c **** sm_set_relay(RELAY_PRECHARGE, 1); + 2512 .loc 1 449 7 + 2513 0052 0121 movs r1, #1 + 2514 0054 0120 movs r0, #1 + 2515 0056 FFF7FEFF bl sm_set_relay + 450:Core/Src/state_machine.c **** break; + 2516 .loc 1 450 7 + 2517 005a 35E0 b .L189 + 2518 .L196: + 451:Core/Src/state_machine.c **** case STATE_READY: + 452:Core/Src/state_machine.c **** sm_set_relay(RELAY_MAIN, 1); + 2519 .loc 1 452 7 + 2520 005c 0121 movs r1, #1 + 2521 005e 0020 movs r0, #0 + 2522 0060 FFF7FEFF bl sm_set_relay + 453:Core/Src/state_machine.c **** sm_set_relay(RELAY_PRECHARGE, 0); + 2523 .loc 1 453 7 + 2524 0064 0021 movs r1, #0 + 2525 0066 0120 movs r0, #1 + 2526 0068 FFF7FEFF bl sm_set_relay + 454:Core/Src/state_machine.c **** break; + 2527 .loc 1 454 7 + 2528 006c 2CE0 b .L189 + 2529 .L195: + 455:Core/Src/state_machine.c **** case STATE_ACTIVE: + 456:Core/Src/state_machine.c **** sm_set_relay(RELAY_MAIN, 1); + 2530 .loc 1 456 7 + 2531 006e 0121 movs r1, #1 + ARM GAS /tmp/cctkPVvk.s page 53 + + + 2532 0070 0020 movs r0, #0 + 2533 0072 FFF7FEFF bl sm_set_relay + 457:Core/Src/state_machine.c **** sm_set_relay(RELAY_PRECHARGE, 0); + 2534 .loc 1 457 7 + 2535 0076 0021 movs r1, #0 + 2536 0078 0120 movs r0, #1 + 2537 007a FFF7FEFF bl sm_set_relay + 458:Core/Src/state_machine.c **** break; + 2538 .loc 1 458 7 + 2539 007e 23E0 b .L189 + 2540 .L194: + 459:Core/Src/state_machine.c **** case STATE_DISCHARGE: + 460:Core/Src/state_machine.c **** sm_set_relay(RELAY_MAIN, 0); + 2541 .loc 1 460 7 + 2542 0080 0021 movs r1, #0 + 2543 0082 0020 movs r0, #0 + 2544 0084 FFF7FEFF bl sm_set_relay + 461:Core/Src/state_machine.c **** sm_set_relay(RELAY_PRECHARGE, 1); + 2545 .loc 1 461 7 + 2546 0088 0121 movs r1, #1 + 2547 008a 0120 movs r0, #1 + 2548 008c FFF7FEFF bl sm_set_relay + 462:Core/Src/state_machine.c **** break; + 2549 .loc 1 462 7 + 2550 0090 1AE0 b .L189 + 2551 .L193: + 463:Core/Src/state_machine.c **** case STATE_CHARGING_PRECHARGE: + 464:Core/Src/state_machine.c **** sm_set_relay(RELAY_MAIN, 0); + 2552 .loc 1 464 7 + 2553 0092 0021 movs r1, #0 + 2554 0094 0020 movs r0, #0 + 2555 0096 FFF7FEFF bl sm_set_relay + 465:Core/Src/state_machine.c **** sm_set_relay(RELAY_PRECHARGE, 1); + 2556 .loc 1 465 7 + 2557 009a 0121 movs r1, #1 + 2558 009c 0120 movs r0, #1 + 2559 009e FFF7FEFF bl sm_set_relay + 466:Core/Src/state_machine.c **** break; + 2560 .loc 1 466 7 + 2561 00a2 11E0 b .L189 + 2562 .L192: + 467:Core/Src/state_machine.c **** case STATE_CHARGING: + 468:Core/Src/state_machine.c **** sm_set_relay(RELAY_MAIN, 1); + 2563 .loc 1 468 7 + 2564 00a4 0121 movs r1, #1 + 2565 00a6 0020 movs r0, #0 + 2566 00a8 FFF7FEFF bl sm_set_relay + 469:Core/Src/state_machine.c **** sm_set_relay(RELAY_PRECHARGE, 0); + 2567 .loc 1 469 7 + 2568 00ac 0021 movs r1, #0 + 2569 00ae 0120 movs r0, #1 + 2570 00b0 FFF7FEFF bl sm_set_relay + 470:Core/Src/state_machine.c **** break; + 2571 .loc 1 470 7 + 2572 00b4 08E0 b .L189 + 2573 .L190: + 471:Core/Src/state_machine.c **** case STATE_ERROR: + ARM GAS /tmp/cctkPVvk.s page 54 + + + 472:Core/Src/state_machine.c **** sm_set_relay(RELAY_MAIN, 0); + 2574 .loc 1 472 7 + 2575 00b6 0021 movs r1, #0 + 2576 00b8 0020 movs r0, #0 + 2577 00ba FFF7FEFF bl sm_set_relay + 473:Core/Src/state_machine.c **** sm_set_relay(RELAY_PRECHARGE, 0); + 2578 .loc 1 473 7 + 2579 00be 0021 movs r1, #0 + 2580 00c0 0120 movs r0, #1 + 2581 00c2 FFF7FEFF bl sm_set_relay + 474:Core/Src/state_machine.c **** break; + 2582 .loc 1 474 7 + 2583 00c6 00BF nop + 2584 .L189: + 2585 .L199: + 475:Core/Src/state_machine.c **** } + 476:Core/Src/state_machine.c **** } + 2586 .loc 1 476 1 + 2587 00c8 00BF nop + 2588 00ca 0837 adds r7, r7, #8 + 2589 .cfi_def_cfa_offset 8 + 2590 00cc BD46 mov sp, r7 + 2591 .cfi_def_cfa_register 13 + 2592 @ sp needed + 2593 00ce 80BD pop {r7, pc} + 2594 .L202: + 2595 .align 2 + 2596 .L201: + 2597 00d0 00000000 .word state + 2598 .cfi_endproc + 2599 .LFE149: + 2601 .section .text.sm_set_relay,"ax",%progbits + 2602 .align 1 + 2603 .global sm_set_relay + 2604 .syntax unified + 2605 .thumb + 2606 .thumb_func + 2608 sm_set_relay: + 2609 .LFB150: + 477:Core/Src/state_machine.c **** + 478:Core/Src/state_machine.c **** void sm_set_relay(Relay relay, bool closed){ + 2610 .loc 1 478 44 + 2611 .cfi_startproc + 2612 @ args = 0, pretend = 0, frame = 16 + 2613 @ frame_needed = 1, uses_anonymous_args = 0 + 2614 0000 80B5 push {r7, lr} + 2615 .cfi_def_cfa_offset 8 + 2616 .cfi_offset 7, -8 + 2617 .cfi_offset 14, -4 + 2618 0002 84B0 sub sp, sp, #16 + 2619 .cfi_def_cfa_offset 24 + 2620 0004 00AF add r7, sp, #0 + 2621 .cfi_def_cfa_register 7 + 2622 0006 0346 mov r3, r0 + 2623 0008 0A46 mov r2, r1 + 2624 000a FB71 strb r3, [r7, #7] + 2625 000c 1346 mov r3, r2 + ARM GAS /tmp/cctkPVvk.s page 55 + + + 2626 000e BB71 strb r3, [r7, #6] + 479:Core/Src/state_machine.c **** GPIO_PinState state = closed ? GPIO_PIN_SET : GPIO_PIN_RESET; + 2627 .loc 1 479 47 + 2628 0010 BB79 ldrb r3, [r7, #6] @ zero_extendqisi2 + 2629 .loc 1 479 17 + 2630 0012 FB73 strb r3, [r7, #15] + 480:Core/Src/state_machine.c **** switch (relay) { + 2631 .loc 1 480 3 + 2632 0014 FB79 ldrb r3, [r7, #7] @ zero_extendqisi2 + 2633 0016 002B cmp r3, #0 + 2634 0018 02D0 beq .L204 + 2635 001a 012B cmp r3, #1 + 2636 001c 07D0 beq .L205 + 481:Core/Src/state_machine.c **** case RELAY_MAIN: + 482:Core/Src/state_machine.c **** HAL_GPIO_WritePin(RELAY_ENABLE_GPIO_Port, RELAY_ENABLE_Pin, state); + 483:Core/Src/state_machine.c **** break; + 484:Core/Src/state_machine.c **** case RELAY_PRECHARGE: + 485:Core/Src/state_machine.c **** HAL_GPIO_WritePin(PRECHARGE_ENABLE_GPIO_Port, PRECHARGE_ENABLE_Pin, state); + 486:Core/Src/state_machine.c **** break; + 487:Core/Src/state_machine.c **** } + 488:Core/Src/state_machine.c **** } + 2637 .loc 1 488 1 + 2638 001e 0DE0 b .L207 + 2639 .L204: + 482:Core/Src/state_machine.c **** break; + 2640 .loc 1 482 7 + 2641 0020 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 2642 0022 1A46 mov r2, r3 + 2643 0024 1021 movs r1, #16 + 2644 0026 0748 ldr r0, .L208 + 2645 0028 FFF7FEFF bl HAL_GPIO_WritePin + 483:Core/Src/state_machine.c **** case RELAY_PRECHARGE: + 2646 .loc 1 483 7 + 2647 002c 06E0 b .L206 + 2648 .L205: + 485:Core/Src/state_machine.c **** break; + 2649 .loc 1 485 7 + 2650 002e FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 2651 0030 1A46 mov r2, r3 + 2652 0032 2021 movs r1, #32 + 2653 0034 0348 ldr r0, .L208 + 2654 0036 FFF7FEFF bl HAL_GPIO_WritePin + 486:Core/Src/state_machine.c **** } + 2655 .loc 1 486 7 + 2656 003a 00BF nop + 2657 .L206: + 2658 .L207: + 2659 .loc 1 488 1 + 2660 003c 00BF nop + 2661 003e 1037 adds r7, r7, #16 + 2662 .cfi_def_cfa_offset 8 + 2663 0040 BD46 mov sp, r7 + 2664 .cfi_def_cfa_register 13 + 2665 @ sp needed + 2666 0042 80BD pop {r7, pc} + 2667 .L209: + 2668 .align 2 + ARM GAS /tmp/cctkPVvk.s page 56 + + + 2669 .L208: + 2670 0044 00040048 .word 1207960576 + 2671 .cfi_endproc + 2672 .LFE150: + 2674 .section .text.sm_check_battery_temperature,"ax",%progbits + 2675 .align 1 + 2676 .global sm_check_battery_temperature + 2677 .syntax unified + 2678 .thumb + 2679 .thumb_func + 2681 sm_check_battery_temperature: + 2682 .LFB151: + 489:Core/Src/state_machine.c **** + 490:Core/Src/state_machine.c **** /* returns the ID and temperature of the hottest cell */ + 491:Core/Src/state_machine.c **** void sm_check_battery_temperature(uint8_t *id, uint16_t *temp){ + 2683 .loc 1 491 63 + 2684 .cfi_startproc + 2685 @ args = 0, pretend = 0, frame = 16 + 2686 @ frame_needed = 1, uses_anonymous_args = 0 + 2687 @ link register save eliminated. + 2688 0000 80B4 push {r7} + 2689 .cfi_def_cfa_offset 4 + 2690 .cfi_offset 7, -4 + 2691 0002 85B0 sub sp, sp, #20 + 2692 .cfi_def_cfa_offset 24 + 2693 0004 00AF add r7, sp, #0 + 2694 .cfi_def_cfa_register 7 + 2695 0006 7860 str r0, [r7, #4] + 2696 0008 3960 str r1, [r7] + 2697 .LBB5: + 492:Core/Src/state_machine.c **** for (int i = 0; i < N_TEMP_SENSORS; i++) { + 2698 .loc 1 492 12 + 2699 000a 0023 movs r3, #0 + 2700 000c FB60 str r3, [r7, #12] + 2701 .loc 1 492 3 + 2702 000e 16E0 b .L211 + 2703 .L213: + 493:Core/Src/state_machine.c **** if (tmp1075_temps[i] > *temp){ + 2704 .loc 1 493 22 + 2705 0010 104A ldr r2, .L214 + 2706 0012 FB68 ldr r3, [r7, #12] + 2707 0014 32F91330 ldrsh r3, [r2, r3, lsl #1] + 2708 0018 1A46 mov r2, r3 + 2709 .loc 1 493 28 + 2710 001a 3B68 ldr r3, [r7] + 2711 001c 1B88 ldrh r3, [r3] + 2712 .loc 1 493 8 + 2713 001e 9A42 cmp r2, r3 + 2714 0020 0ADD ble .L212 + 494:Core/Src/state_machine.c **** *id = i; + 2715 .loc 1 494 11 + 2716 0022 FB68 ldr r3, [r7, #12] + 2717 0024 DAB2 uxtb r2, r3 + 2718 0026 7B68 ldr r3, [r7, #4] + 2719 0028 1A70 strb r2, [r3] + 495:Core/Src/state_machine.c **** *temp = tmp1075_temps[i]; + 2720 .loc 1 495 28 + ARM GAS /tmp/cctkPVvk.s page 57 + + + 2721 002a 0A4A ldr r2, .L214 + 2722 002c FB68 ldr r3, [r7, #12] + 2723 002e 32F91330 ldrsh r3, [r2, r3, lsl #1] + 2724 0032 9AB2 uxth r2, r3 + 2725 .loc 1 495 13 + 2726 0034 3B68 ldr r3, [r7] + 2727 0036 1A80 strh r2, [r3] @ movhi + 2728 .L212: + 492:Core/Src/state_machine.c **** if (tmp1075_temps[i] > *temp){ + 2729 .loc 1 492 40 discriminator 2 + 2730 0038 FB68 ldr r3, [r7, #12] + 2731 003a 0133 adds r3, r3, #1 + 2732 003c FB60 str r3, [r7, #12] + 2733 .L211: + 492:Core/Src/state_machine.c **** if (tmp1075_temps[i] > *temp){ + 2734 .loc 1 492 21 discriminator 1 + 2735 003e FB68 ldr r3, [r7, #12] + 2736 0040 0C2B cmp r3, #12 + 2737 0042 E5DD ble .L213 + 2738 .LBE5: + 496:Core/Src/state_machine.c **** } + 497:Core/Src/state_machine.c **** } + 498:Core/Src/state_machine.c **** } + 2739 .loc 1 498 1 + 2740 0044 00BF nop + 2741 0046 00BF nop + 2742 0048 1437 adds r7, r7, #20 + 2743 .cfi_def_cfa_offset 4 + 2744 004a BD46 mov sp, r7 + 2745 .cfi_def_cfa_register 13 + 2746 @ sp needed + 2747 004c 5DF8047B ldr r7, [sp], #4 + 2748 .cfi_restore 7 + 2749 .cfi_def_cfa_offset 0 + 2750 0050 7047 bx lr + 2751 .L215: + 2752 0052 00BF .align 2 + 2753 .L214: + 2754 0054 00000000 .word tmp1075_temps + 2755 .cfi_endproc + 2756 .LFE151: + 2758 .section .text.sm_return_cell_temperature,"ax",%progbits + 2759 .align 1 + 2760 .global sm_return_cell_temperature + 2761 .syntax unified + 2762 .thumb + 2763 .thumb_func + 2765 sm_return_cell_temperature: + 2766 .LFB152: + 499:Core/Src/state_machine.c **** + 500:Core/Src/state_machine.c **** int16_t sm_return_cell_temperature(int id){ return tmp1075_temps[id]; } + 2767 .loc 1 500 43 + 2768 .cfi_startproc + 2769 @ args = 0, pretend = 0, frame = 8 + 2770 @ frame_needed = 1, uses_anonymous_args = 0 + 2771 @ link register save eliminated. + 2772 0000 80B4 push {r7} + ARM GAS /tmp/cctkPVvk.s page 58 + + + 2773 .cfi_def_cfa_offset 4 + 2774 .cfi_offset 7, -4 + 2775 0002 83B0 sub sp, sp, #12 + 2776 .cfi_def_cfa_offset 16 + 2777 0004 00AF add r7, sp, #0 + 2778 .cfi_def_cfa_register 7 + 2779 0006 7860 str r0, [r7, #4] + 2780 .loc 1 500 65 + 2781 0008 044A ldr r2, .L218 + 2782 000a 7B68 ldr r3, [r7, #4] + 2783 000c 32F91330 ldrsh r3, [r2, r3, lsl #1] + 2784 .loc 1 500 71 + 2785 0010 1846 mov r0, r3 + 2786 0012 0C37 adds r7, r7, #12 + 2787 .cfi_def_cfa_offset 4 + 2788 0014 BD46 mov sp, r7 + 2789 .cfi_def_cfa_register 13 + 2790 @ sp needed + 2791 0016 5DF8047B ldr r7, [sp], #4 + 2792 .cfi_restore 7 + 2793 .cfi_def_cfa_offset 0 + 2794 001a 7047 bx lr + 2795 .L219: + 2796 .align 2 + 2797 .L218: + 2798 001c 00000000 .word tmp1075_temps + 2799 .cfi_endproc + 2800 .LFE152: + 2802 .section .text.sm_return_cell_voltage,"ax",%progbits + 2803 .align 1 + 2804 .global sm_return_cell_voltage + 2805 .syntax unified + 2806 .thumb + 2807 .thumb_func + 2809 sm_return_cell_voltage: + 2810 .LFB153: + 501:Core/Src/state_machine.c **** + 502:Core/Src/state_machine.c **** int16_t sm_return_cell_voltage(int id){ return module.cellVoltages[id]; } + 2811 .loc 1 502 39 + 2812 .cfi_startproc + 2813 @ args = 0, pretend = 0, frame = 8 + 2814 @ frame_needed = 1, uses_anonymous_args = 0 + 2815 @ link register save eliminated. + 2816 0000 80B4 push {r7} + 2817 .cfi_def_cfa_offset 4 + 2818 .cfi_offset 7, -4 + 2819 0002 83B0 sub sp, sp, #12 + 2820 .cfi_def_cfa_offset 16 + 2821 0004 00AF add r7, sp, #0 + 2822 .cfi_def_cfa_register 7 + 2823 0006 7860 str r0, [r7, #4] + 2824 .loc 1 502 67 + 2825 0008 044A ldr r2, .L222 + 2826 000a 7B68 ldr r3, [r7, #4] + 2827 000c 32F91330 ldrsh r3, [r2, r3, lsl #1] + 2828 .loc 1 502 73 + 2829 0010 1846 mov r0, r3 + ARM GAS /tmp/cctkPVvk.s page 59 + + + 2830 0012 0C37 adds r7, r7, #12 + 2831 .cfi_def_cfa_offset 4 + 2832 0014 BD46 mov sp, r7 + 2833 .cfi_def_cfa_register 13 + 2834 @ sp needed + 2835 0016 5DF8047B ldr r7, [sp], #4 + 2836 .cfi_restore 7 + 2837 .cfi_def_cfa_offset 0 + 2838 001a 7047 bx lr + 2839 .L223: + 2840 .align 2 + 2841 .L222: + 2842 001c 00000000 .word module + 2843 .cfi_endproc + 2844 .LFE153: + 2846 .section .text.sm_test_cycle_states,"ax",%progbits + 2847 .align 1 + 2848 .global sm_test_cycle_states + 2849 .syntax unified + 2850 .thumb + 2851 .thumb_func + 2853 sm_test_cycle_states: + 2854 .LFB154: + 503:Core/Src/state_machine.c **** + 504:Core/Src/state_machine.c **** void sm_test_cycle_states(){ + 2855 .loc 1 504 28 + 2856 .cfi_startproc + 2857 @ args = 0, pretend = 0, frame = 0 + 2858 @ frame_needed = 1, uses_anonymous_args = 0 + 2859 0000 80B5 push {r7, lr} + 2860 .cfi_def_cfa_offset 8 + 2861 .cfi_offset 7, -8 + 2862 .cfi_offset 14, -4 + 2863 0002 00AF add r7, sp, #0 + 2864 .cfi_def_cfa_register 7 + 505:Core/Src/state_machine.c **** RELAY_BAT_SIDE_VOLTAGE = module.auxVoltages[0]; + 2865 .loc 1 505 46 + 2866 0004 434B ldr r3, .L237 + 2867 0006 D3ED087A vldr.32 s15, [r3, #32] + 2868 .loc 1 505 26 + 2869 000a FDEEE77A vcvt.s32.f32 s15, s15 + 2870 000e 17EE902A vmov r2, s15 @ int + 2871 0012 414B ldr r3, .L237+4 + 2872 0014 1A60 str r2, [r3] + 506:Core/Src/state_machine.c **** RELAY_ESC_SIDE_VOLTAGE = module.auxVoltages[1]; + 2873 .loc 1 506 46 + 2874 0016 3F4B ldr r3, .L237 + 2875 0018 D3ED097A vldr.32 s15, [r3, #36] + 2876 .loc 1 506 26 + 2877 001c FDEEE77A vcvt.s32.f32 s15, s15 + 2878 0020 17EE902A vmov r2, s15 @ int + 2879 0024 3D4B ldr r3, .L237+8 + 2880 0026 1A60 str r2, [r3] + 507:Core/Src/state_machine.c **** CURRENT_MEASUREMENT = module.auxVoltages[2]; + 2881 .loc 1 507 43 + 2882 0028 3A4B ldr r3, .L237 + 2883 002a D3ED0A7A vldr.32 s15, [r3, #40] + ARM GAS /tmp/cctkPVvk.s page 60 + + + 2884 .loc 1 507 23 + 2885 002e FDEEE77A vcvt.s32.f32 s15, s15 + 2886 0032 17EE902A vmov r2, s15 @ int + 2887 0036 3A4B ldr r3, .L237+12 + 2888 0038 1A60 str r2, [r3] + 508:Core/Src/state_machine.c **** sm_set_relay_positions(state.current_state); + 2889 .loc 1 508 3 + 2890 003a 3A4B ldr r3, .L237+16 + 2891 003c 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 2892 003e 1846 mov r0, r3 + 2893 0040 FFF7FEFF bl sm_set_relay_positions + 509:Core/Src/state_machine.c **** + 510:Core/Src/state_machine.c **** if (timestamp > HAL_GetTick()) + 2894 .loc 1 510 19 + 2895 0044 FFF7FEFF bl HAL_GetTick + 2896 0048 0246 mov r2, r0 + 2897 .loc 1 510 17 discriminator 1 + 2898 004a 374B ldr r3, .L237+20 + 2899 004c 1B68 ldr r3, [r3] + 2900 .loc 1 510 6 discriminator 1 + 2901 004e 9A42 cmp r2, r3 + 2902 0050 5DD3 bcc .L235 + 511:Core/Src/state_machine.c **** return; + 512:Core/Src/state_machine.c **** switch (state.current_state) { + 2903 .loc 1 512 16 + 2904 0052 344B ldr r3, .L237+16 + 2905 0054 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 2906 .loc 1 512 3 + 2907 0056 072B cmp r3, #7 + 2908 0058 54D8 bhi .L227 + 2909 005a 01A2 adr r2, .L229 + 2910 005c 52F823F0 ldr pc, [r2, r3, lsl #2] + 2911 .p2align 2 + 2912 .L229: + 2913 0060 81000000 .word .L234+1 + 2914 0064 9F000000 .word .L233+1 + 2915 0068 B7000000 .word .L232+1 + 2916 006c CF000000 .word .L231+1 + 2917 0070 ED000000 .word .L230+1 + 2918 0074 05010000 .word .L227+1 + 2919 0078 05010000 .word .L227+1 + 2920 007c 05010000 .word .L227+1 + 2921 .p2align 1 + 2922 .L234: + 513:Core/Src/state_machine.c **** case STATE_INACTIVE: + 514:Core/Src/state_machine.c **** state.current_state = STATE_PRECHARGE; + 2923 .loc 1 514 27 + 2924 0080 284B ldr r3, .L237+16 + 2925 0082 0122 movs r2, #1 + 2926 0084 1A70 strb r2, [r3] + 515:Core/Src/state_machine.c **** timestamp = HAL_GetTick() + 30000; + 2927 .loc 1 515 19 + 2928 0086 FFF7FEFF bl HAL_GetTick + 2929 008a 0346 mov r3, r0 + 2930 .loc 1 515 33 discriminator 1 + 2931 008c 03F5EA43 add r3, r3, #29952 + 2932 0090 3033 adds r3, r3, #48 + ARM GAS /tmp/cctkPVvk.s page 61 + + + 2933 .loc 1 515 17 discriminator 1 + 2934 0092 254A ldr r2, .L237+20 + 2935 0094 1360 str r3, [r2] + 516:Core/Src/state_machine.c **** PWM_powerground_control(0); + 2936 .loc 1 516 7 + 2937 0096 0020 movs r0, #0 + 2938 0098 FFF7FEFF bl PWM_powerground_control + 517:Core/Src/state_machine.c **** break; + 2939 .loc 1 517 7 + 2940 009c 32E0 b .L227 + 2941 .L233: + 518:Core/Src/state_machine.c **** case STATE_PRECHARGE: + 519:Core/Src/state_machine.c **** state.current_state = STATE_READY; + 2942 .loc 1 519 27 + 2943 009e 214B ldr r3, .L237+16 + 2944 00a0 0222 movs r2, #2 + 2945 00a2 1A70 strb r2, [r3] + 520:Core/Src/state_machine.c **** timestamp = HAL_GetTick() + 10000; + 2946 .loc 1 520 19 + 2947 00a4 FFF7FEFF bl HAL_GetTick + 2948 00a8 0346 mov r3, r0 + 2949 .loc 1 520 33 discriminator 1 + 2950 00aa 03F51C53 add r3, r3, #9984 + 2951 00ae 1033 adds r3, r3, #16 + 2952 .loc 1 520 17 discriminator 1 + 2953 00b0 1D4A ldr r2, .L237+20 + 2954 00b2 1360 str r3, [r2] + 521:Core/Src/state_machine.c **** break; + 2955 .loc 1 521 7 + 2956 00b4 26E0 b .L227 + 2957 .L232: + 522:Core/Src/state_machine.c **** case STATE_READY: + 523:Core/Src/state_machine.c **** state.current_state = STATE_ACTIVE; + 2958 .loc 1 523 27 + 2959 00b6 1B4B ldr r3, .L237+16 + 2960 00b8 0322 movs r2, #3 + 2961 00ba 1A70 strb r2, [r3] + 524:Core/Src/state_machine.c **** timestamp = HAL_GetTick() + 10000; + 2962 .loc 1 524 19 + 2963 00bc FFF7FEFF bl HAL_GetTick + 2964 00c0 0346 mov r3, r0 + 2965 .loc 1 524 33 discriminator 1 + 2966 00c2 03F51C53 add r3, r3, #9984 + 2967 00c6 1033 adds r3, r3, #16 + 2968 .loc 1 524 17 discriminator 1 + 2969 00c8 174A ldr r2, .L237+20 + 2970 00ca 1360 str r3, [r2] + 525:Core/Src/state_machine.c **** break; + 2971 .loc 1 525 7 + 2972 00cc 1AE0 b .L227 + 2973 .L231: + 526:Core/Src/state_machine.c **** case STATE_ACTIVE: + 527:Core/Src/state_machine.c **** state.current_state = STATE_DISCHARGE; + 2974 .loc 1 527 27 + 2975 00ce 154B ldr r3, .L237+16 + 2976 00d0 0422 movs r2, #4 + 2977 00d2 1A70 strb r2, [r3] + ARM GAS /tmp/cctkPVvk.s page 62 + + + 528:Core/Src/state_machine.c **** timestamp = HAL_GetTick() + 10000; + 2978 .loc 1 528 19 + 2979 00d4 FFF7FEFF bl HAL_GetTick + 2980 00d8 0346 mov r3, r0 + 2981 .loc 1 528 33 discriminator 1 + 2982 00da 03F51C53 add r3, r3, #9984 + 2983 00de 1033 adds r3, r3, #16 + 2984 .loc 1 528 17 discriminator 1 + 2985 00e0 114A ldr r2, .L237+20 + 2986 00e2 1360 str r3, [r2] + 529:Core/Src/state_machine.c **** PWM_powerground_control(10); + 2987 .loc 1 529 7 + 2988 00e4 0A20 movs r0, #10 + 2989 00e6 FFF7FEFF bl PWM_powerground_control + 530:Core/Src/state_machine.c **** break; + 2990 .loc 1 530 7 + 2991 00ea 0BE0 b .L227 + 2992 .L230: + 531:Core/Src/state_machine.c **** case STATE_DISCHARGE: + 532:Core/Src/state_machine.c **** state.current_state = STATE_INACTIVE; + 2993 .loc 1 532 27 + 2994 00ec 0D4B ldr r3, .L237+16 + 2995 00ee 0022 movs r2, #0 + 2996 00f0 1A70 strb r2, [r3] + 533:Core/Src/state_machine.c **** timestamp = HAL_GetTick() + 10000; + 2997 .loc 1 533 19 + 2998 00f2 FFF7FEFF bl HAL_GetTick + 2999 00f6 0346 mov r3, r0 + 3000 .loc 1 533 33 discriminator 1 + 3001 00f8 03F51C53 add r3, r3, #9984 + 3002 00fc 1033 adds r3, r3, #16 + 3003 .loc 1 533 17 discriminator 1 + 3004 00fe 0A4A ldr r2, .L237+20 + 3005 0100 1360 str r3, [r2] + 534:Core/Src/state_machine.c **** break; + 3006 .loc 1 534 7 + 3007 0102 00BF nop + 3008 .L227: + 535:Core/Src/state_machine.c **** case STATE_CHARGING_PRECHARGE: + 536:Core/Src/state_machine.c **** case STATE_CHARGING: + 537:Core/Src/state_machine.c **** case STATE_ERROR: + 538:Core/Src/state_machine.c **** break; + 539:Core/Src/state_machine.c **** } + 540:Core/Src/state_machine.c **** + 541:Core/Src/state_machine.c **** state.target_state = state.current_state; + 3009 .loc 1 541 29 + 3010 0104 074B ldr r3, .L237+16 + 3011 0106 1A78 ldrb r2, [r3] @ zero_extendqisi2 + 3012 .loc 1 541 22 + 3013 0108 064B ldr r3, .L237+16 + 3014 010a 5A70 strb r2, [r3, #1] + 3015 010c 00E0 b .L224 + 3016 .L235: + 511:Core/Src/state_machine.c **** switch (state.current_state) { + 3017 .loc 1 511 5 + 3018 010e 00BF nop + 3019 .L224: + ARM GAS /tmp/cctkPVvk.s page 63 + + + 542:Core/Src/state_machine.c **** }... + 3020 .loc 1 542 1 + 3021 0110 80BD pop {r7, pc} + 3022 .L238: + 3023 0112 00BF .align 2 + 3024 .L237: + 3025 0114 00000000 .word module + 3026 0118 00000000 .word RELAY_BAT_SIDE_VOLTAGE + 3027 011c 00000000 .word RELAY_ESC_SIDE_VOLTAGE + 3028 0120 00000000 .word CURRENT_MEASUREMENT + 3029 0124 00000000 .word state + 3030 0128 00000000 .word timestamp + 3031 .cfi_endproc + 3032 .LFE154: + 3034 .text + 3035 .Letext0: + 3036 .file 2 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 3037 .file 3 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 3038 .file 4 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + 3039 .file 5 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h" + 3040 .file 6 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h" + 3041 .file 7 "Core/Inc/ADBMS_LL_Driver.h" + 3042 .file 8 "Core/Inc/ADBMS_Abstraction.h" + 3043 .file 9 "Core/Inc/errors.h" + 3044 .file 10 "Core/Inc/AMS_HighLevel.h" + 3045 .file 11 "Core/Inc/TMP1075.h" + 3046 .file 12 "Core/Inc/PWM_control.h" + 3047 .file 13 "Core/Inc/state_machine.h" + 3048 .file 14 "Core/Inc/eeprom.h" + 3049 .file 15 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h" + 3050 .file 16 "Core/Inc/soc_estimation.h" + 3051 .file 17 "Core/Inc/status_LED.h" + 3052 .file 18 "Core/Inc/can.h" + ARM GAS /tmp/cctkPVvk.s page 64 + + +DEFINED SYMBOLS + *ABS*:00000000 state_machine.c + /tmp/cctkPVvk.s:24 .bss.programming_mode:00000000 programming_mode + /tmp/cctkPVvk.s:25 .bss.programming_mode:00000000 $d + /tmp/cctkPVvk.s:30 .bss.debugging_mode:00000000 debugging_mode + /tmp/cctkPVvk.s:31 .bss.debugging_mode:00000000 $d + /tmp/cctkPVvk.s:37 .bss.state:00000000 state + /tmp/cctkPVvk.s:34 .bss.state:00000000 $d + /tmp/cctkPVvk.s:44 .bss.RELAY_BAT_SIDE_VOLTAGE:00000000 RELAY_BAT_SIDE_VOLTAGE + /tmp/cctkPVvk.s:41 .bss.RELAY_BAT_SIDE_VOLTAGE:00000000 $d + /tmp/cctkPVvk.s:51 .bss.RELAY_ESC_SIDE_VOLTAGE:00000000 RELAY_ESC_SIDE_VOLTAGE + /tmp/cctkPVvk.s:48 .bss.RELAY_ESC_SIDE_VOLTAGE:00000000 $d + /tmp/cctkPVvk.s:58 .bss.CURRENT_MEASUREMENT:00000000 CURRENT_MEASUREMENT + /tmp/cctkPVvk.s:55 .bss.CURRENT_MEASUREMENT:00000000 $d + /tmp/cctkPVvk.s:64 .bss.CURRENT_MEASUREMENT_ON:00000000 CURRENT_MEASUREMENT_ON + /tmp/cctkPVvk.s:65 .bss.CURRENT_MEASUREMENT_ON:00000000 $d + /tmp/cctkPVvk.s:70 .bss.balancing_state:00000000 balancing_state + /tmp/cctkPVvk.s:71 .bss.balancing_state:00000000 $d + /tmp/cctkPVvk.s:77 .bss.base_offset:00000000 base_offset + /tmp/cctkPVvk.s:74 .bss.base_offset:00000000 $d + /tmp/cctkPVvk.s:84 .bss.error_timer:00000000 error_timer + /tmp/cctkPVvk.s:81 .bss.error_timer:00000000 $d + /tmp/cctkPVvk.s:91 .bss.precharge_timer:00000000 precharge_timer + /tmp/cctkPVvk.s:88 .bss.precharge_timer:00000000 $d + /tmp/cctkPVvk.s:98 .bss.discharge_timer:00000000 discharge_timer + /tmp/cctkPVvk.s:95 .bss.discharge_timer:00000000 $d + /tmp/cctkPVvk.s:105 .bss.balancing_timer:00000000 balancing_timer + /tmp/cctkPVvk.s:102 .bss.balancing_timer:00000000 $d + /tmp/cctkPVvk.s:112 .bss.eeprom_timer:00000000 eeprom_timer + /tmp/cctkPVvk.s:109 .bss.eeprom_timer:00000000 $d + /tmp/cctkPVvk.s:119 .bss.powerground_softstart_timer:00000000 powerground_softstart_timer + /tmp/cctkPVvk.s:116 .bss.powerground_softstart_timer:00000000 $d + /tmp/cctkPVvk.s:126 .bss.powerground_calibration_timer:00000000 powerground_calibration_timer + /tmp/cctkPVvk.s:123 .bss.powerground_calibration_timer:00000000 $d + /tmp/cctkPVvk.s:132 .bss.powerground_calibration_stage:00000000 powerground_calibration_stage + /tmp/cctkPVvk.s:133 .bss.powerground_calibration_stage:00000000 $d + /tmp/cctkPVvk.s:138 .bss.current_powerground_status:00000000 current_powerground_status + /tmp/cctkPVvk.s:139 .bss.current_powerground_status:00000000 $d + /tmp/cctkPVvk.s:144 .bss.target_powerground_status:00000000 target_powerground_status + /tmp/cctkPVvk.s:145 .bss.target_powerground_status:00000000 $d + /tmp/cctkPVvk.s:147 .bss.timestamp:00000000 $d + /tmp/cctkPVvk.s:150 .bss.timestamp:00000000 timestamp + /tmp/cctkPVvk.s:153 .text.sm_init:00000000 $t + /tmp/cctkPVvk.s:159 .text.sm_init:00000000 sm_init + /tmp/cctkPVvk.s:236 .text.sm_init:00000060 $d + /tmp/cctkPVvk.s:254 .text.sm_update:00000000 $t + /tmp/cctkPVvk.s:260 .text.sm_update:00000000 sm_update + /tmp/cctkPVvk.s:1490 .text.sm_check_errors:00000000 sm_check_errors + /tmp/cctkPVvk.s:740 .text.sm_precharge_discharge_manager:00000000 sm_precharge_discharge_manager + /tmp/cctkPVvk.s:1195 .text.sm_balancing:00000000 sm_balancing + /tmp/cctkPVvk.s:912 .text.sm_powerground_manager:00000000 sm_powerground_manager + /tmp/cctkPVvk.s:390 .text.sm_update:000000f0 $d + /tmp/cctkPVvk.s:398 .text.sm_update:00000110 $t + /tmp/cctkPVvk.s:2008 .text.sm_update_inactive:00000000 sm_update_inactive + /tmp/cctkPVvk.s:2072 .text.sm_update_precharge:00000000 sm_update_precharge + /tmp/cctkPVvk.s:2128 .text.sm_update_ready:00000000 sm_update_ready + /tmp/cctkPVvk.s:2184 .text.sm_update_active:00000000 sm_update_active + ARM GAS /tmp/cctkPVvk.s page 65 + + + /tmp/cctkPVvk.s:2240 .text.sm_update_discharge:00000000 sm_update_discharge + /tmp/cctkPVvk.s:2296 .text.sm_update_charging_precharge:00000000 sm_update_charging_precharge + /tmp/cctkPVvk.s:2350 .text.sm_update_charging:00000000 sm_update_charging + /tmp/cctkPVvk.s:2407 .text.sm_update_error:00000000 sm_update_error + /tmp/cctkPVvk.s:2461 .text.sm_set_relay_positions:00000000 sm_set_relay_positions + /tmp/cctkPVvk.s:497 .text.sm_update:00000198 $d + /tmp/cctkPVvk.s:515 .text.sm_handle_ams_in:00000000 $t + /tmp/cctkPVvk.s:521 .text.sm_handle_ams_in:00000000 sm_handle_ams_in + /tmp/cctkPVvk.s:727 .text.sm_handle_ams_in:00000100 $d + /tmp/cctkPVvk.s:734 .text.sm_precharge_discharge_manager:00000000 $t + /tmp/cctkPVvk.s:899 .text.sm_precharge_discharge_manager:000000d0 $d + /tmp/cctkPVvk.s:906 .text.sm_powerground_manager:00000000 $t + /tmp/cctkPVvk.s:1031 .text.sm_powerground_manager:0000009c $d + /tmp/cctkPVvk.s:1038 .text.sm_calibrate_powerground:00000000 $t + /tmp/cctkPVvk.s:1044 .text.sm_calibrate_powerground:00000000 sm_calibrate_powerground + /tmp/cctkPVvk.s:1077 .text.sm_calibrate_powerground:00000024 $d + /tmp/cctkPVvk.s:1081 .text.sm_calibrate_powerground:00000034 $t + /tmp/cctkPVvk.s:1182 .text.sm_calibrate_powerground:000000bc $d + /tmp/cctkPVvk.s:1189 .text.sm_balancing:00000000 $t + /tmp/cctkPVvk.s:1371 .text.sm_balancing:000000e8 $d + /tmp/cctkPVvk.s:1378 .text.sm_program_powerground:00000000 $t + /tmp/cctkPVvk.s:1384 .text.sm_program_powerground:00000000 sm_program_powerground + /tmp/cctkPVvk.s:1429 .text.sm_program_powerground:00000030 $d + /tmp/cctkPVvk.s:1435 .text.sm_eeprom_write_status:00000000 $t + /tmp/cctkPVvk.s:1441 .text.sm_eeprom_write_status:00000000 sm_eeprom_write_status + /tmp/cctkPVvk.s:1479 .text.sm_eeprom_write_status:00000028 $d + /tmp/cctkPVvk.s:1484 .text.sm_check_errors:00000000 $t + /tmp/cctkPVvk.s:1830 .text.sm_set_error_source:00000000 sm_set_error_source + /tmp/cctkPVvk.s:1813 .text.sm_check_errors:000001e4 $d + /tmp/cctkPVvk.s:1824 .text.sm_set_error_source:00000000 $t + /tmp/cctkPVvk.s:1997 .text.sm_set_error_source:0000010c $d + /tmp/cctkPVvk.s:2002 .text.sm_update_inactive:00000000 $t + /tmp/cctkPVvk.s:2061 .text.sm_update_inactive:00000034 $d + /tmp/cctkPVvk.s:2066 .text.sm_update_precharge:00000000 $t + /tmp/cctkPVvk.s:2117 .text.sm_update_precharge:00000028 $d + /tmp/cctkPVvk.s:2122 .text.sm_update_ready:00000000 $t + /tmp/cctkPVvk.s:2173 .text.sm_update_ready:00000028 $d + /tmp/cctkPVvk.s:2178 .text.sm_update_active:00000000 $t + /tmp/cctkPVvk.s:2229 .text.sm_update_active:00000028 $d + /tmp/cctkPVvk.s:2234 .text.sm_update_discharge:00000000 $t + /tmp/cctkPVvk.s:2285 .text.sm_update_discharge:00000028 $d + /tmp/cctkPVvk.s:2290 .text.sm_update_charging_precharge:00000000 $t + /tmp/cctkPVvk.s:2339 .text.sm_update_charging_precharge:00000024 $d + /tmp/cctkPVvk.s:2344 .text.sm_update_charging:00000000 $t + /tmp/cctkPVvk.s:2395 .text.sm_update_charging:00000028 $d + /tmp/cctkPVvk.s:2401 .text.sm_update_error:00000000 $t + /tmp/cctkPVvk.s:2450 .text.sm_update_error:00000024 $d + /tmp/cctkPVvk.s:2455 .text.sm_set_relay_positions:00000000 $t + /tmp/cctkPVvk.s:2487 .text.sm_set_relay_positions:00000018 $d + /tmp/cctkPVvk.s:2495 .text.sm_set_relay_positions:00000038 $t + /tmp/cctkPVvk.s:2608 .text.sm_set_relay:00000000 sm_set_relay + /tmp/cctkPVvk.s:2597 .text.sm_set_relay_positions:000000d0 $d + /tmp/cctkPVvk.s:2602 .text.sm_set_relay:00000000 $t + /tmp/cctkPVvk.s:2670 .text.sm_set_relay:00000044 $d + /tmp/cctkPVvk.s:2675 .text.sm_check_battery_temperature:00000000 $t + /tmp/cctkPVvk.s:2681 .text.sm_check_battery_temperature:00000000 sm_check_battery_temperature + /tmp/cctkPVvk.s:2754 .text.sm_check_battery_temperature:00000054 $d + ARM GAS /tmp/cctkPVvk.s page 66 + + + /tmp/cctkPVvk.s:2759 .text.sm_return_cell_temperature:00000000 $t + /tmp/cctkPVvk.s:2765 .text.sm_return_cell_temperature:00000000 sm_return_cell_temperature + /tmp/cctkPVvk.s:2798 .text.sm_return_cell_temperature:0000001c $d + /tmp/cctkPVvk.s:2803 .text.sm_return_cell_voltage:00000000 $t + /tmp/cctkPVvk.s:2809 .text.sm_return_cell_voltage:00000000 sm_return_cell_voltage + /tmp/cctkPVvk.s:2842 .text.sm_return_cell_voltage:0000001c $d + /tmp/cctkPVvk.s:2847 .text.sm_test_cycle_states:00000000 $t + /tmp/cctkPVvk.s:2853 .text.sm_test_cycle_states:00000000 sm_test_cycle_states + /tmp/cctkPVvk.s:2913 .text.sm_test_cycle_states:00000060 $d + /tmp/cctkPVvk.s:2921 .text.sm_test_cycle_states:00000080 $t + /tmp/cctkPVvk.s:3025 .text.sm_test_cycle_states:00000114 $d + +UNDEFINED SYMBOLS +__aeabi_f2d +__aeabi_dsub +__aeabi_dmul +__aeabi_d2iz +can_handle_send_status +can_handle_send_log +tmp1075_measure +status_led_update +soc_update +module +PWM_powerground_control +HAL_GetTick +PWM_powerground_softcontrol +amsStopBalancing +amsConfigBalancing +amsStartBalancing +eeprom_write_status +error_data +currentAMSState +HAL_GPIO_WritePin +tmp1075_temps diff --git a/Software/build/state_machine.o b/Software/build/state_machine.o new file mode 100644 index 0000000..3b7e35a Binary files /dev/null and b/Software/build/state_machine.o differ diff --git a/Software/build/status_LED.d b/Software/build/status_LED.d new file mode 100644 index 0000000..8b16560 --- /dev/null +++ b/Software/build/status_LED.d @@ -0,0 +1,88 @@ +build/status_LED.o: Core/Src/status_LED.c Core/Inc/ADBMS_LL_Driver.h \ + Core/Inc/main.h Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + Core/Inc/stm32f3xx_hal_conf.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h \ + Core/Inc/state_machine.h Core/Inc/ADBMS_LL_Driver.h \ + Core/Inc/AMS_HighLevel.h Core/Inc/ADBMS_Abstraction.h \ + Core/Inc/ADBMS_CMD_MAKROS.h Core/Lib/can-halal/can-halal.h \ + Core/Inc/errors.h Core/Inc/can.h Core/Inc/state_machine.h \ + Core/Inc/eeprom.h Core/Inc/soc_estimation.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h Core/Inc/TMP1075.h \ + Core/Inc/errors.h Core/Inc/PWM_control.h Core/Inc/status_LED.h \ + Core/Inc/TMP1075.h +Core/Inc/ADBMS_LL_Driver.h: +Core/Inc/main.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h: +Core/Inc/state_machine.h: +Core/Inc/ADBMS_LL_Driver.h: +Core/Inc/AMS_HighLevel.h: +Core/Inc/ADBMS_Abstraction.h: +Core/Inc/ADBMS_CMD_MAKROS.h: +Core/Lib/can-halal/can-halal.h: +Core/Inc/errors.h: +Core/Inc/can.h: +Core/Inc/state_machine.h: +Core/Inc/eeprom.h: +Core/Inc/soc_estimation.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Core/Inc/TMP1075.h: +Core/Inc/errors.h: +Core/Inc/PWM_control.h: +Core/Inc/status_LED.h: +Core/Inc/TMP1075.h: diff --git a/Software/build/status_LED.lst b/Software/build/status_LED.lst new file mode 100644 index 0000000..ba035da --- /dev/null +++ b/Software/build/status_LED.lst @@ -0,0 +1,683 @@ +ARM GAS /tmp/ccnT6iWU.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 6 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "status_LED.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Core/Src/status_LED.c" + 20 .global red + 21 .section .bss.red,"aw",%nobits + 22 .align 2 + 25 red: + 26 0000 00000000 .space 4 + 27 .global green + 28 .section .bss.green,"aw",%nobits + 29 .align 2 + 32 green: + 33 0000 00000000 .space 4 + 34 .global blue + 35 .section .bss.blue,"aw",%nobits + 36 .align 2 + 39 blue: + 40 0000 00000000 .space 4 + 41 .global blink_timer + 42 .section .bss.blink_timer,"aw",%nobits + 43 .align 2 + 46 blink_timer: + 47 0000 00000000 .space 4 + 48 .global blink_state + 49 .section .bss.blink_state,"aw",%nobits + 52 blink_state: + 53 0000 00 .space 1 + 54 .section .text.status_led_init,"ax",%progbits + 55 .align 1 + 56 .global status_led_init + 57 .syntax unified + 58 .thumb + 59 .thumb_func + 61 status_led_init: + 62 .LFB130: + 1:Core/Src/status_LED.c **** /* + 2:Core/Src/status_LED.c **** * status_LED.h + 3:Core/Src/status_LED.c **** * + 4:Core/Src/status_LED.c **** * Created on: 07.07.2024 + 5:Core/Src/status_LED.c **** * Author: Hamza + 6:Core/Src/status_LED.c **** */ + ARM GAS /tmp/ccnT6iWU.s page 2 + + + 7:Core/Src/status_LED.c **** + 8:Core/Src/status_LED.c **** #include "ADBMS_LL_Driver.h" + 9:Core/Src/status_LED.c **** #include "state_machine.h" + 10:Core/Src/status_LED.c **** #include "stm32f3xx_hal.h" + 11:Core/Src/status_LED.c **** #include + 12:Core/Src/status_LED.c **** #include + 13:Core/Src/status_LED.c **** + 14:Core/Src/status_LED.c **** // TODO test out pulldown and pushpull settings + 15:Core/Src/status_LED.c **** + 16:Core/Src/status_LED.c **** /* The PWM period (1/FPWM) is defined by the following parameters: + 17:Core/Src/status_LED.c **** ARR value, the Prescaler value, and the internal clock itself which drives the timer module FCLK. + 18:Core/Src/status_LED.c **** F_PWM = (F_CLK)/((ARR + 1) * (PSC + 1)) + 19:Core/Src/status_LED.c **** + 20:Core/Src/status_LED.c **** Prescaler: + 21:Core/Src/status_LED.c **** (ARR + 1) * (PSC + 1) = (F_CLK)/(F_PWM) + 22:Core/Src/status_LED.c **** (PSC + 1) = (F_CLK)/(F_PWM * (ARR + 1)) + 23:Core/Src/status_LED.c **** 625 = (16MHz)/(100Hz * (255 + 1)) + 24:Core/Src/status_LED.c **** + 25:Core/Src/status_LED.c **** F_CLK = 16 MHz + 26:Core/Src/status_LED.c **** */ + 27:Core/Src/status_LED.c **** + 28:Core/Src/status_LED.c **** #define STATUS_LED_ARR 255 + 29:Core/Src/status_LED.c **** #define TIME_BLINK_SLOW 2000 + 30:Core/Src/status_LED.c **** #define TIME_BLINK_FAST 500 + 31:Core/Src/status_LED.c **** + 32:Core/Src/status_LED.c **** TIM_HandleTypeDef* red; + 33:Core/Src/status_LED.c **** TIM_HandleTypeDef* green; + 34:Core/Src/status_LED.c **** TIM_HandleTypeDef* blue; + 35:Core/Src/status_LED.c **** + 36:Core/Src/status_LED.c **** uint32_t blink_timer; + 37:Core/Src/status_LED.c **** bool blink_state; + 38:Core/Src/status_LED.c **** + 39:Core/Src/status_LED.c **** void status_led_init(TIM_HandleTypeDef* r, TIM_HandleTypeDef* g, TIM_HandleTypeDef* b){ + 63 .loc 1 39 87 + 64 .cfi_startproc + 65 @ args = 0, pretend = 0, frame = 16 + 66 @ frame_needed = 1, uses_anonymous_args = 0 + 67 0000 80B5 push {r7, lr} + 68 .cfi_def_cfa_offset 8 + 69 .cfi_offset 7, -8 + 70 .cfi_offset 14, -4 + 71 0002 84B0 sub sp, sp, #16 + 72 .cfi_def_cfa_offset 24 + 73 0004 00AF add r7, sp, #0 + 74 .cfi_def_cfa_register 7 + 75 0006 F860 str r0, [r7, #12] + 76 0008 B960 str r1, [r7, #8] + 77 000a 7A60 str r2, [r7, #4] + 40:Core/Src/status_LED.c **** red = r; + 78 .loc 1 40 7 + 79 000c 144A ldr r2, .L2 + 80 000e FB68 ldr r3, [r7, #12] + 81 0010 1360 str r3, [r2] + 41:Core/Src/status_LED.c **** green = g; + 82 .loc 1 41 9 + 83 0012 144A ldr r2, .L2+4 + 84 0014 BB68 ldr r3, [r7, #8] + ARM GAS /tmp/ccnT6iWU.s page 3 + + + 85 0016 1360 str r3, [r2] + 42:Core/Src/status_LED.c **** blue = b; + 86 .loc 1 42 8 + 87 0018 134A ldr r2, .L2+8 + 88 001a 7B68 ldr r3, [r7, #4] + 89 001c 1360 str r3, [r2] + 43:Core/Src/status_LED.c **** + 44:Core/Src/status_LED.c **** blink_timer = 0; + 90 .loc 1 44 15 + 91 001e 134B ldr r3, .L2+12 + 92 0020 0022 movs r2, #0 + 93 0022 1A60 str r2, [r3] + 45:Core/Src/status_LED.c **** blink_state = 0; + 94 .loc 1 45 15 + 95 0024 124B ldr r3, .L2+16 + 96 0026 0022 movs r2, #0 + 97 0028 1A70 strb r2, [r3] + 46:Core/Src/status_LED.c **** + 47:Core/Src/status_LED.c **** HAL_TIM_PWM_Start(red, TIM_CHANNEL_1); //TIM4CH1 + 98 .loc 1 47 3 + 99 002a 0D4B ldr r3, .L2 + 100 002c 1B68 ldr r3, [r3] + 101 002e 0021 movs r1, #0 + 102 0030 1846 mov r0, r3 + 103 0032 FFF7FEFF bl HAL_TIM_PWM_Start + 48:Core/Src/status_LED.c **** HAL_TIM_PWM_Start(green, TIM_CHANNEL_2); //TIM4CH2 + 104 .loc 1 48 3 + 105 0036 0B4B ldr r3, .L2+4 + 106 0038 1B68 ldr r3, [r3] + 107 003a 0421 movs r1, #4 + 108 003c 1846 mov r0, r3 + 109 003e FFF7FEFF bl HAL_TIM_PWM_Start + 49:Core/Src/status_LED.c **** HAL_TIM_PWM_Start(blue, TIM_CHANNEL_3); //TIM4CH3 + 110 .loc 1 49 3 + 111 0042 094B ldr r3, .L2+8 + 112 0044 1B68 ldr r3, [r3] + 113 0046 0821 movs r1, #8 + 114 0048 1846 mov r0, r3 + 115 004a FFF7FEFF bl HAL_TIM_PWM_Start + 50:Core/Src/status_LED.c **** + 51:Core/Src/status_LED.c **** status_led_set(255, 255, 255); + 116 .loc 1 51 3 + 117 004e FF22 movs r2, #255 + 118 0050 FF21 movs r1, #255 + 119 0052 FF20 movs r0, #255 + 120 0054 FFF7FEFF bl status_led_set + 52:Core/Src/status_LED.c **** } + 121 .loc 1 52 1 + 122 0058 00BF nop + 123 005a 1037 adds r7, r7, #16 + 124 .cfi_def_cfa_offset 8 + 125 005c BD46 mov sp, r7 + 126 .cfi_def_cfa_register 13 + 127 @ sp needed + 128 005e 80BD pop {r7, pc} + 129 .L3: + 130 .align 2 + ARM GAS /tmp/ccnT6iWU.s page 4 + + + 131 .L2: + 132 0060 00000000 .word red + 133 0064 00000000 .word green + 134 0068 00000000 .word blue + 135 006c 00000000 .word blink_timer + 136 0070 00000000 .word blink_state + 137 .cfi_endproc + 138 .LFE130: + 140 .section .text.status_led_update,"ax",%progbits + 141 .align 1 + 142 .global status_led_update + 143 .syntax unified + 144 .thumb + 145 .thumb_func + 147 status_led_update: + 148 .LFB131: + 53:Core/Src/status_LED.c **** + 54:Core/Src/status_LED.c **** void status_led_update(){ + 149 .loc 1 54 25 + 150 .cfi_startproc + 151 @ args = 0, pretend = 0, frame = 0 + 152 @ frame_needed = 1, uses_anonymous_args = 0 + 153 0000 80B5 push {r7, lr} + 154 .cfi_def_cfa_offset 8 + 155 .cfi_offset 7, -8 + 156 .cfi_offset 14, -4 + 157 0002 00AF add r7, sp, #0 + 158 .cfi_def_cfa_register 7 + 55:Core/Src/status_LED.c **** if (state.current_state == STATE_ERROR){ + 159 .loc 1 55 12 + 160 0004 344B ldr r3, .L20 + 161 0006 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 162 .loc 1 55 6 + 163 0008 072B cmp r3, #7 + 164 000a 03D1 bne .L5 + 56:Core/Src/status_LED.c **** status_led_set_color(RED); + 165 .loc 1 56 5 + 166 000c 0120 movs r0, #1 + 167 000e FFF7FEFF bl status_led_set_color + 57:Core/Src/status_LED.c **** return; + 168 .loc 1 57 5 + 169 0012 60E0 b .L4 + 170 .L5: + 58:Core/Src/status_LED.c **** } + 59:Core/Src/status_LED.c **** if(blink_timer > HAL_GetTick()){ + 171 .loc 1 59 20 + 172 0014 FFF7FEFF bl HAL_GetTick + 173 0018 0246 mov r2, r0 + 174 .loc 1 59 18 discriminator 1 + 175 001a 304B ldr r3, .L20+4 + 176 001c 1B68 ldr r3, [r3] + 177 .loc 1 59 5 discriminator 1 + 178 001e 9A42 cmp r2, r3 + 179 0020 58D3 bcc .L18 + 60:Core/Src/status_LED.c **** return; + 61:Core/Src/status_LED.c **** } + 62:Core/Src/status_LED.c **** + ARM GAS /tmp/ccnT6iWU.s page 5 + + + 63:Core/Src/status_LED.c **** if (blink_state == 1){ + 180 .loc 1 63 19 + 181 0022 2F4B ldr r3, .L20+8 + 182 0024 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 183 .loc 1 63 6 + 184 0026 002B cmp r3, #0 + 185 0028 17D0 beq .L8 + 64:Core/Src/status_LED.c **** if (state.current_state == STATE_INACTIVE) + 186 .loc 1 64 14 + 187 002a 2B4B ldr r3, .L20 + 188 002c 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 189 .loc 1 64 8 + 190 002e 002B cmp r3, #0 + 191 0030 06D1 bne .L9 + 65:Core/Src/status_LED.c **** blink_timer = HAL_GetTick() + TIME_BLINK_SLOW/10; + 192 .loc 1 65 21 + 193 0032 FFF7FEFF bl HAL_GetTick + 194 0036 0346 mov r3, r0 + 195 .loc 1 65 35 discriminator 1 + 196 0038 C833 adds r3, r3, #200 + 197 .loc 1 65 19 discriminator 1 + 198 003a 284A ldr r2, .L20+4 + 199 003c 1360 str r3, [r2] + 200 003e 05E0 b .L10 + 201 .L9: + 66:Core/Src/status_LED.c **** else + 67:Core/Src/status_LED.c **** blink_timer = HAL_GetTick() + TIME_BLINK_FAST/10; + 202 .loc 1 67 21 + 203 0040 FFF7FEFF bl HAL_GetTick + 204 0044 0346 mov r3, r0 + 205 .loc 1 67 35 discriminator 1 + 206 0046 3233 adds r3, r3, #50 + 207 .loc 1 67 19 discriminator 1 + 208 0048 244A ldr r2, .L20+4 + 209 004a 1360 str r3, [r2] + 210 .L10: + 68:Core/Src/status_LED.c **** blink_state = 0; + 211 .loc 1 68 17 + 212 004c 244B ldr r3, .L20+8 + 213 004e 0022 movs r2, #0 + 214 0050 1A70 strb r2, [r3] + 69:Core/Src/status_LED.c **** status_led_set_color(OFF); + 215 .loc 1 69 5 + 216 0052 0020 movs r0, #0 + 217 0054 FFF7FEFF bl status_led_set_color + 70:Core/Src/status_LED.c **** return; + 218 .loc 1 70 5 + 219 0058 3DE0 b .L4 + 220 .L8: + 71:Core/Src/status_LED.c **** } else { + 72:Core/Src/status_LED.c **** if (state.current_state == STATE_INACTIVE) + 221 .loc 1 72 14 + 222 005a 1F4B ldr r3, .L20 + 223 005c 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 224 .loc 1 72 8 + 225 005e 002B cmp r3, #0 + 226 0060 07D1 bne .L11 + ARM GAS /tmp/ccnT6iWU.s page 6 + + + 73:Core/Src/status_LED.c **** blink_timer = HAL_GetTick() + TIME_BLINK_SLOW; + 227 .loc 1 73 21 + 228 0062 FFF7FEFF bl HAL_GetTick + 229 0066 0346 mov r3, r0 + 230 .loc 1 73 35 discriminator 1 + 231 0068 03F5FA63 add r3, r3, #2000 + 232 .loc 1 73 19 discriminator 1 + 233 006c 1B4A ldr r2, .L20+4 + 234 006e 1360 str r3, [r2] + 235 0070 06E0 b .L12 + 236 .L11: + 74:Core/Src/status_LED.c **** else + 75:Core/Src/status_LED.c **** blink_timer = HAL_GetTick() + TIME_BLINK_FAST; + 237 .loc 1 75 21 + 238 0072 FFF7FEFF bl HAL_GetTick + 239 0076 0346 mov r3, r0 + 240 .loc 1 75 35 discriminator 1 + 241 0078 03F5FA73 add r3, r3, #500 + 242 .loc 1 75 19 discriminator 1 + 243 007c 174A ldr r2, .L20+4 + 244 007e 1360 str r3, [r2] + 245 .L12: + 76:Core/Src/status_LED.c **** blink_state = 1; + 246 .loc 1 76 17 + 247 0080 174B ldr r3, .L20+8 + 248 0082 0122 movs r2, #1 + 249 0084 1A70 strb r2, [r3] + 77:Core/Src/status_LED.c **** } + 78:Core/Src/status_LED.c **** + 79:Core/Src/status_LED.c **** switch (state.current_state) { + 250 .loc 1 79 16 + 251 0086 144B ldr r3, .L20 + 252 0088 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 253 .loc 1 79 3 + 254 008a 072B cmp r3, #7 + 255 008c 23D8 bhi .L4 + 256 008e 01A2 adr r2, .L14 + 257 0090 52F823F0 ldr pc, [r2, r3, lsl #2] + 258 .p2align 2 + 259 .L14: + 260 0094 B5000000 .word .L17+1 + 261 0098 BD000000 .word .L16+1 + 262 009c C5000000 .word .L15+1 + 263 00a0 C5000000 .word .L15+1 + 264 00a4 BD000000 .word .L16+1 + 265 00a8 BD000000 .word .L16+1 + 266 00ac C5000000 .word .L15+1 + 267 00b0 CD000000 .word .L13+1 + 268 .p2align 1 + 269 .L17: + 80:Core/Src/status_LED.c **** case STATE_INACTIVE: + 81:Core/Src/status_LED.c **** status_led_set_color(GREEN); + 270 .loc 1 81 5 + 271 00b4 0220 movs r0, #2 + 272 00b6 FFF7FEFF bl status_led_set_color + 82:Core/Src/status_LED.c **** break; + 273 .loc 1 82 5 + ARM GAS /tmp/ccnT6iWU.s page 7 + + + 274 00ba 0CE0 b .L4 + 275 .L16: + 83:Core/Src/status_LED.c **** case STATE_CHARGING_PRECHARGE: + 84:Core/Src/status_LED.c **** case STATE_PRECHARGE: + 85:Core/Src/status_LED.c **** case STATE_DISCHARGE: + 86:Core/Src/status_LED.c **** status_led_set_color( YELLOW); + 276 .loc 1 86 5 + 277 00bc 0420 movs r0, #4 + 278 00be FFF7FEFF bl status_led_set_color + 87:Core/Src/status_LED.c **** break; + 279 .loc 1 87 5 + 280 00c2 08E0 b .L4 + 281 .L15: + 88:Core/Src/status_LED.c **** case STATE_CHARGING: + 89:Core/Src/status_LED.c **** case STATE_READY: + 90:Core/Src/status_LED.c **** case STATE_ACTIVE: + 91:Core/Src/status_LED.c **** status_led_set_color(PINK); + 282 .loc 1 91 5 + 283 00c4 0520 movs r0, #5 + 284 00c6 FFF7FEFF bl status_led_set_color + 92:Core/Src/status_LED.c **** break; + 285 .loc 1 92 5 + 286 00ca 04E0 b .L4 + 287 .L13: + 93:Core/Src/status_LED.c **** case STATE_ERROR: + 94:Core/Src/status_LED.c **** status_led_set_color(RED); + 288 .loc 1 94 5 + 289 00cc 0120 movs r0, #1 + 290 00ce FFF7FEFF bl status_led_set_color + 95:Core/Src/status_LED.c **** break; + 291 .loc 1 95 5 + 292 00d2 00E0 b .L4 + 293 .L18: + 60:Core/Src/status_LED.c **** } + 294 .loc 1 60 5 + 295 00d4 00BF nop + 296 .L4: + 96:Core/Src/status_LED.c **** } + 97:Core/Src/status_LED.c **** } + 297 .loc 1 97 1 + 298 00d6 80BD pop {r7, pc} + 299 .L21: + 300 .align 2 + 301 .L20: + 302 00d8 00000000 .word state + 303 00dc 00000000 .word blink_timer + 304 00e0 00000000 .word blink_state + 305 .cfi_endproc + 306 .LFE131: + 308 .section .text.status_led_set_color,"ax",%progbits + 309 .align 1 + 310 .global status_led_set_color + 311 .syntax unified + 312 .thumb + 313 .thumb_func + 315 status_led_set_color: + 316 .LFB132: + ARM GAS /tmp/ccnT6iWU.s page 8 + + + 98:Core/Src/status_LED.c **** + 99:Core/Src/status_LED.c **** void status_led_set_color(color color){ + 317 .loc 1 99 39 + 318 .cfi_startproc + 319 @ args = 0, pretend = 0, frame = 8 + 320 @ frame_needed = 1, uses_anonymous_args = 0 + 321 0000 80B5 push {r7, lr} + 322 .cfi_def_cfa_offset 8 + 323 .cfi_offset 7, -8 + 324 .cfi_offset 14, -4 + 325 0002 82B0 sub sp, sp, #8 + 326 .cfi_def_cfa_offset 16 + 327 0004 00AF add r7, sp, #0 + 328 .cfi_def_cfa_register 7 + 329 0006 0346 mov r3, r0 + 330 0008 FB71 strb r3, [r7, #7] + 100:Core/Src/status_LED.c **** switch (color) { + 331 .loc 1 100 3 + 332 000a FB79 ldrb r3, [r7, #7] @ zero_extendqisi2 + 333 000c 072B cmp r3, #7 + 334 000e 43D8 bhi .L33 + 335 0010 01A2 adr r2, .L25 + 336 0012 52F823F0 ldr pc, [r2, r3, lsl #2] + 337 0016 00BF .p2align 2 + 338 .L25: + 339 0018 8D000000 .word .L32+1 + 340 001c 39000000 .word .L31+1 + 341 0020 45000000 .word .L30+1 + 342 0024 51000000 .word .L29+1 + 343 0028 5D000000 .word .L28+1 + 344 002c 69000000 .word .L27+1 + 345 0030 75000000 .word .L26+1 + 346 0034 81000000 .word .L24+1 + 347 .p2align 1 + 348 .L31: + 101:Core/Src/status_LED.c **** case RED: + 102:Core/Src/status_LED.c **** status_led_set(0, 255, 255); + 349 .loc 1 102 5 + 350 0038 FF22 movs r2, #255 + 351 003a FF21 movs r1, #255 + 352 003c 0020 movs r0, #0 + 353 003e FFF7FEFF bl status_led_set + 103:Core/Src/status_LED.c **** break; + 354 .loc 1 103 5 + 355 0042 29E0 b .L23 + 356 .L30: + 104:Core/Src/status_LED.c **** case GREEN: + 105:Core/Src/status_LED.c **** status_led_set(255, 0, 255); + 357 .loc 1 105 5 + 358 0044 FF22 movs r2, #255 + 359 0046 0021 movs r1, #0 + 360 0048 FF20 movs r0, #255 + 361 004a FFF7FEFF bl status_led_set + 106:Core/Src/status_LED.c **** break; + 362 .loc 1 106 5 + 363 004e 23E0 b .L23 + 364 .L29: + ARM GAS /tmp/ccnT6iWU.s page 9 + + + 107:Core/Src/status_LED.c **** case BLUE: + 108:Core/Src/status_LED.c **** status_led_set(255, 255, 0); + 365 .loc 1 108 5 + 366 0050 0022 movs r2, #0 + 367 0052 FF21 movs r1, #255 + 368 0054 FF20 movs r0, #255 + 369 0056 FFF7FEFF bl status_led_set + 109:Core/Src/status_LED.c **** break; + 370 .loc 1 109 5 + 371 005a 1DE0 b .L23 + 372 .L28: + 110:Core/Src/status_LED.c **** case YELLOW: + 111:Core/Src/status_LED.c **** status_led_set(0, 0, 255); + 373 .loc 1 111 5 + 374 005c FF22 movs r2, #255 + 375 005e 0021 movs r1, #0 + 376 0060 0020 movs r0, #0 + 377 0062 FFF7FEFF bl status_led_set + 112:Core/Src/status_LED.c **** break; + 378 .loc 1 112 5 + 379 0066 17E0 b .L23 + 380 .L27: + 113:Core/Src/status_LED.c **** case PINK: + 114:Core/Src/status_LED.c **** status_led_set(0, 255, 0); + 381 .loc 1 114 5 + 382 0068 0022 movs r2, #0 + 383 006a FF21 movs r1, #255 + 384 006c 0020 movs r0, #0 + 385 006e FFF7FEFF bl status_led_set + 115:Core/Src/status_LED.c **** break; + 386 .loc 1 115 5 + 387 0072 11E0 b .L23 + 388 .L26: + 116:Core/Src/status_LED.c **** case CYAN: + 117:Core/Src/status_LED.c **** status_led_set(255, 0, 0); + 389 .loc 1 117 5 + 390 0074 0022 movs r2, #0 + 391 0076 0021 movs r1, #0 + 392 0078 FF20 movs r0, #255 + 393 007a FFF7FEFF bl status_led_set + 118:Core/Src/status_LED.c **** break; + 394 .loc 1 118 5 + 395 007e 0BE0 b .L23 + 396 .L24: + 119:Core/Src/status_LED.c **** case WHITE: + 120:Core/Src/status_LED.c **** status_led_set(0, 0, 0); + 397 .loc 1 120 5 + 398 0080 0022 movs r2, #0 + 399 0082 0021 movs r1, #0 + 400 0084 0020 movs r0, #0 + 401 0086 FFF7FEFF bl status_led_set + 121:Core/Src/status_LED.c **** break; + 402 .loc 1 121 5 + 403 008a 05E0 b .L23 + 404 .L32: + 122:Core/Src/status_LED.c **** case OFF: + 123:Core/Src/status_LED.c **** status_led_set(255,255,255); + ARM GAS /tmp/ccnT6iWU.s page 10 + + + 405 .loc 1 123 5 + 406 008c FF22 movs r2, #255 + 407 008e FF21 movs r1, #255 + 408 0090 FF20 movs r0, #255 + 409 0092 FFF7FEFF bl status_led_set + 124:Core/Src/status_LED.c **** break; + 410 .loc 1 124 5 + 411 0096 00BF nop + 412 .L23: + 413 .L33: + 125:Core/Src/status_LED.c **** } + 126:Core/Src/status_LED.c **** } + 414 .loc 1 126 1 + 415 0098 00BF nop + 416 009a 0837 adds r7, r7, #8 + 417 .cfi_def_cfa_offset 8 + 418 009c BD46 mov sp, r7 + 419 .cfi_def_cfa_register 13 + 420 @ sp needed + 421 009e 80BD pop {r7, pc} + 422 .cfi_endproc + 423 .LFE132: + 425 .section .text.status_led_set,"ax",%progbits + 426 .align 1 + 427 .global status_led_set + 428 .syntax unified + 429 .thumb + 430 .thumb_func + 432 status_led_set: + 433 .LFB133: + 127:Core/Src/status_LED.c **** + 128:Core/Src/status_LED.c **** void status_led_set(uint8_t r, uint8_t g, uint8_t b){ + 434 .loc 1 128 53 + 435 .cfi_startproc + 436 @ args = 0, pretend = 0, frame = 8 + 437 @ frame_needed = 1, uses_anonymous_args = 0 + 438 @ link register save eliminated. + 439 0000 80B4 push {r7} + 440 .cfi_def_cfa_offset 4 + 441 .cfi_offset 7, -4 + 442 0002 83B0 sub sp, sp, #12 + 443 .cfi_def_cfa_offset 16 + 444 0004 00AF add r7, sp, #0 + 445 .cfi_def_cfa_register 7 + 446 0006 0346 mov r3, r0 + 447 0008 FB71 strb r3, [r7, #7] + 448 000a 0B46 mov r3, r1 + 449 000c BB71 strb r3, [r7, #6] + 450 000e 1346 mov r3, r2 + 451 0010 7B71 strb r3, [r7, #5] + 129:Core/Src/status_LED.c **** __HAL_TIM_SET_COMPARE(red, TIM_CHANNEL_1, r); + 452 .loc 1 129 3 + 453 0012 0A4B ldr r3, .L36 + 454 0014 1B68 ldr r3, [r3] + 455 0016 1B68 ldr r3, [r3] + 456 0018 FA79 ldrb r2, [r7, #7] @ zero_extendqisi2 + 457 001a 5A63 str r2, [r3, #52] + ARM GAS /tmp/ccnT6iWU.s page 11 + + + 130:Core/Src/status_LED.c **** __HAL_TIM_SET_COMPARE(green, TIM_CHANNEL_2, g); + 458 .loc 1 130 3 + 459 001c 084B ldr r3, .L36+4 + 460 001e 1B68 ldr r3, [r3] + 461 0020 1B68 ldr r3, [r3] + 462 0022 BA79 ldrb r2, [r7, #6] @ zero_extendqisi2 + 463 0024 9A63 str r2, [r3, #56] + 131:Core/Src/status_LED.c **** __HAL_TIM_SET_COMPARE(blue, TIM_CHANNEL_3, b); + 464 .loc 1 131 3 + 465 0026 074B ldr r3, .L36+8 + 466 0028 1B68 ldr r3, [r3] + 467 002a 1B68 ldr r3, [r3] + 468 002c 7A79 ldrb r2, [r7, #5] @ zero_extendqisi2 + 469 002e DA63 str r2, [r3, #60] + 132:Core/Src/status_LED.c **** }... + 470 .loc 1 132 1 + 471 0030 00BF nop + 472 0032 0C37 adds r7, r7, #12 + 473 .cfi_def_cfa_offset 4 + 474 0034 BD46 mov sp, r7 + 475 .cfi_def_cfa_register 13 + 476 @ sp needed + 477 0036 5DF8047B ldr r7, [sp], #4 + 478 .cfi_restore 7 + 479 .cfi_def_cfa_offset 0 + 480 003a 7047 bx lr + 481 .L37: + 482 .align 2 + 483 .L36: + 484 003c 00000000 .word red + 485 0040 00000000 .word green + 486 0044 00000000 .word blue + 487 .cfi_endproc + 488 .LFE133: + 490 .text + 491 .Letext0: + 492 .file 2 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 493 .file 3 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 494 .file 4 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + 495 .file 5 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h" + 496 .file 6 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h" + 497 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h" + 498 .file 8 "Core/Inc/status_LED.h" + 499 .file 9 "Core/Inc/state_machine.h" + 500 .file 10 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h" + ARM GAS /tmp/ccnT6iWU.s page 12 + + +DEFINED SYMBOLS + *ABS*:00000000 status_LED.c + /tmp/ccnT6iWU.s:25 .bss.red:00000000 red + /tmp/ccnT6iWU.s:22 .bss.red:00000000 $d + /tmp/ccnT6iWU.s:32 .bss.green:00000000 green + /tmp/ccnT6iWU.s:29 .bss.green:00000000 $d + /tmp/ccnT6iWU.s:39 .bss.blue:00000000 blue + /tmp/ccnT6iWU.s:36 .bss.blue:00000000 $d + /tmp/ccnT6iWU.s:46 .bss.blink_timer:00000000 blink_timer + /tmp/ccnT6iWU.s:43 .bss.blink_timer:00000000 $d + /tmp/ccnT6iWU.s:52 .bss.blink_state:00000000 blink_state + /tmp/ccnT6iWU.s:53 .bss.blink_state:00000000 $d + /tmp/ccnT6iWU.s:55 .text.status_led_init:00000000 $t + /tmp/ccnT6iWU.s:61 .text.status_led_init:00000000 status_led_init + /tmp/ccnT6iWU.s:432 .text.status_led_set:00000000 status_led_set + /tmp/ccnT6iWU.s:132 .text.status_led_init:00000060 $d + /tmp/ccnT6iWU.s:141 .text.status_led_update:00000000 $t + /tmp/ccnT6iWU.s:147 .text.status_led_update:00000000 status_led_update + /tmp/ccnT6iWU.s:315 .text.status_led_set_color:00000000 status_led_set_color + /tmp/ccnT6iWU.s:260 .text.status_led_update:00000094 $d + /tmp/ccnT6iWU.s:268 .text.status_led_update:000000b4 $t + /tmp/ccnT6iWU.s:302 .text.status_led_update:000000d8 $d + /tmp/ccnT6iWU.s:309 .text.status_led_set_color:00000000 $t + /tmp/ccnT6iWU.s:339 .text.status_led_set_color:00000018 $d + /tmp/ccnT6iWU.s:347 .text.status_led_set_color:00000038 $t + /tmp/ccnT6iWU.s:426 .text.status_led_set:00000000 $t + /tmp/ccnT6iWU.s:484 .text.status_led_set:0000003c $d + +UNDEFINED SYMBOLS +HAL_TIM_PWM_Start +HAL_GetTick +state diff --git a/Software/build/status_LED.o b/Software/build/status_LED.o new file mode 100644 index 0000000..791d465 Binary files /dev/null and b/Software/build/status_LED.o differ diff --git a/Software/build/stm32f3xx_hal.d b/Software/build/stm32f3xx_hal.d new file mode 100644 index 0000000..5fcd6a9 --- /dev/null +++ b/Software/build/stm32f3xx_hal.d @@ -0,0 +1,61 @@ +build/stm32f3xx_hal.o: Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + Core/Inc/stm32f3xx_hal_conf.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h: diff --git a/Software/build/stm32f3xx_hal.lst b/Software/build/stm32f3xx_hal.lst new file mode 100644 index 0000000..2ece9d6 --- /dev/null +++ b/Software/build/stm32f3xx_hal.lst @@ -0,0 +1,1795 @@ +ARM GAS /tmp/ccHZ4rZ5.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 6 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "stm32f3xx_hal.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c" + 20 .global uwTick + 21 .section .bss.uwTick,"aw",%nobits + 22 .align 2 + 25 uwTick: + 26 0000 00000000 .space 4 + 27 .global uwTickPrio + 28 .section .data.uwTickPrio,"aw" + 29 .align 2 + 32 uwTickPrio: + 33 0000 10000000 .word 16 + 34 .global uwTickFreq + 35 .section .data.uwTickFreq,"aw" + 38 uwTickFreq: + 39 0000 01 .byte 1 + 40 .section .text.HAL_Init,"ax",%progbits + 41 .align 1 + 42 .global HAL_Init + 43 .syntax unified + 44 .thumb + 45 .thumb_func + 47 HAL_Init: + 48 .LFB130: + 1:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 2:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** ****************************************************************************** + 3:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @file stm32f3xx_hal.c + 4:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @author MCD Application Team + 5:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief HAL module driver. + 6:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * This is the common part of the HAL initialization + 7:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * + 8:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** ****************************************************************************** + 9:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @attention + 10:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * + 11:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * Copyright (c) 2016 STMicroelectronics. + 12:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * All rights reserved. + 13:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * + 14:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * This software is licensed under terms that can be found in the LICENSE file + 15:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * in the root directory of this software component. + 16:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + ARM GAS /tmp/ccHZ4rZ5.s page 2 + + + 17:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * + 18:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** ****************************************************************************** + 19:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** @verbatim + 20:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** ============================================================================== + 21:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** ##### How to use this driver ##### + 22:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** ============================================================================== + 23:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** [..] + 24:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** The common HAL driver contains a set of generic and common APIs that can be + 25:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** used by the PPP peripheral drivers and the user to start using the HAL. + 26:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** [..] + 27:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** The HAL contains two APIs categories: + 28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** (+) HAL Initialization and de-initialization functions + 29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** (+) HAL Control functions + 30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 31:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** @endverbatim + 32:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** ****************************************************************************** + 33:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 34:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 35:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* Includes ------------------------------------------------------------------*/ + 36:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** #include "stm32f3xx_hal.h" + 37:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 38:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** @addtogroup STM32F3xx_HAL_Driver + 39:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @{ + 40:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 41:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 42:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** @defgroup HAL HAL + 43:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief HAL module driver. + 44:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @{ + 45:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 46:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 47:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** #ifdef HAL_MODULE_ENABLED + 48:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 49:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* Private typedef -----------------------------------------------------------*/ + 50:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* Private define ------------------------------------------------------------*/ + 51:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** @defgroup HAL_Private Constants + 52:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @{ + 53:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 54:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 55:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief STM32F3xx HAL Driver version number V1.5.7 + 56:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 57:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** #define __STM32F3xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ + 58:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** #define __STM32F3xx_HAL_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */ + 59:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** #define __STM32F3xx_HAL_VERSION_SUB2 (0x07U) /*!< [15:8] sub2 version */ + 60:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** #define __STM32F3xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ + 61:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** #define __STM32F3xx_HAL_VERSION ((__STM32F3xx_HAL_VERSION_MAIN << 24U)\ + 62:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** |(__STM32F3xx_HAL_VERSION_SUB1 << 16U)\ + 63:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** |(__STM32F3xx_HAL_VERSION_SUB2 << 8U )\ + 64:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** |(__STM32F3xx_HAL_VERSION_RC)) + 65:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 66:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** #define IDCODE_DEVID_MASK (0x00000FFFU) + 67:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 68:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @} + 69:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 70:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 71:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* Private macro -------------------------------------------------------------*/ + 72:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* Exported variables --------------------------------------------------------*/ + 73:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** @defgroup HAL_Exported_Variables HAL Exported Variables + ARM GAS /tmp/ccHZ4rZ5.s page 3 + + + 74:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @{ + 75:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 76:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** __IO uint32_t uwTick; + 77:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ + 78:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ + 79:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 80:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @} + 81:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 82:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* Private function prototypes -----------------------------------------------*/ + 83:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* Exported functions ---------------------------------------------------------*/ + 84:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** @defgroup HAL_Exported_Functions HAL Exported Functions + 86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @{ + 87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 88:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 89:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions + 90:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief Initialization and de-initialization functions + 91:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * + 92:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** @verbatim + 93:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** =============================================================================== + 94:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** ##### Initialization and de-initialization functions ##### + 95:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** =============================================================================== + 96:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** [..] This section provides functions allowing to: + 97:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** (+) Initializes the Flash interface, the NVIC allocation and initial clock + 98:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** configuration. It initializes the systick also when timeout is needed + 99:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** and the backup domain when enabled. + 100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** (+) de-Initializes common part of the HAL. + 101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** (+) Configure The time base source to have 1ms time base with a dedicated + 102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** Tick interrupt priority. + 103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** (++) SysTick timer is used by default as source of time base, but user + 104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** can eventually implement his proper time base source (a general purpose + 105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** timer for example or other time source), keeping in mind that Time base + 106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and + 107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** handled in milliseconds basis. + 108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** (++) Time base configuration function (HAL_InitTick ()) is called automatically + 109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** at the beginning of the program after reset by HAL_Init() or at any time + 110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** when clock is configured, by HAL_RCC_ClockConfig(). + 111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** (++) Source of time base is configured to generate interrupts at regular + 112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** time intervals. Care must be taken if HAL_Delay() is called from a + 113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** peripheral ISR process, the Tick interrupt line must have higher priority + 114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** (numerically lower) than the peripheral interrupt. Otherwise the caller + 115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** ISR process will be blocked. + 116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** (++) functions affecting time base configurations are declared as __Weak + 117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** to make override possible in case of other implementations in user file. + 118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** @endverbatim + 120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @{ + 121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief This function configures the Flash prefetch, + 125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * Configures time base source, NVIC and Low level hardware + 126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @note This function is called at the beginning of program after reset and before + 127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * the clock configuration + 128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * + 129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @note The Systick configuration is based on HSI clock, as HSI is the clock + 130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * used after a system Reset and the NVIC configuration is set to Priority group 4 + ARM GAS /tmp/ccHZ4rZ5.s page 4 + + + 131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * + 132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @note The time base configuration is based on MSI clock when exiting from Reset. + 133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * Once done, time base tick start incrementing. + 134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * In the default implementation,Systick is used as source of time base. + 135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * The tick variable is incremented each 1ms in its ISR. + 136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval HAL status + 137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** HAL_StatusTypeDef HAL_Init(void) + 139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 49 .loc 1 139 1 + 50 .cfi_startproc + 51 @ args = 0, pretend = 0, frame = 0 + 52 @ frame_needed = 1, uses_anonymous_args = 0 + 53 0000 80B5 push {r7, lr} + 54 .cfi_def_cfa_offset 8 + 55 .cfi_offset 7, -8 + 56 .cfi_offset 14, -4 + 57 0002 00AF add r7, sp, #0 + 58 .cfi_def_cfa_register 7 + 140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* Configure Flash prefetch */ + 141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** #if (PREFETCH_ENABLE != 0U) + 142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); + 59 .loc 1 142 3 + 60 0004 084B ldr r3, .L3 + 61 0006 1B68 ldr r3, [r3] + 62 0008 074A ldr r2, .L3 + 63 000a 43F01003 orr r3, r3, #16 + 64 000e 1360 str r3, [r2] + 143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** #endif /* PREFETCH_ENABLE */ + 144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* Set Interrupt Group Priority */ + 146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + 65 .loc 1 146 3 + 66 0010 0320 movs r0, #3 + 67 0012 FFF7FEFF bl HAL_NVIC_SetPriorityGrouping + 147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* Enable systick and configure 1ms tick (default clock after Reset is HSI) */ + 149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** HAL_InitTick(TICK_INT_PRIORITY); + 68 .loc 1 149 3 + 69 0016 0F20 movs r0, #15 + 70 0018 FFF7FEFF bl HAL_InitTick + 150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* Init the low level hardware */ + 152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** HAL_MspInit(); + 71 .loc 1 152 3 + 72 001c FFF7FEFF bl HAL_MspInit + 153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* Return function status */ + 155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** return HAL_OK; + 73 .loc 1 155 10 + 74 0020 0023 movs r3, #0 + 156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 75 .loc 1 156 1 + 76 0022 1846 mov r0, r3 + 77 0024 80BD pop {r7, pc} + 78 .L4: + 79 0026 00BF .align 2 + ARM GAS /tmp/ccHZ4rZ5.s page 5 + + + 80 .L3: + 81 0028 00200240 .word 1073881088 + 82 .cfi_endproc + 83 .LFE130: + 85 .section .text.HAL_DeInit,"ax",%progbits + 86 .align 1 + 87 .global HAL_DeInit + 88 .syntax unified + 89 .thumb + 90 .thumb_func + 92 HAL_DeInit: + 93 .LFB131: + 157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief This function de-Initializes common part of the HAL and stops the systick. + 160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @note This function is optional. + 161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval HAL status + 162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** HAL_StatusTypeDef HAL_DeInit(void) + 164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 94 .loc 1 164 1 + 95 .cfi_startproc + 96 @ args = 0, pretend = 0, frame = 0 + 97 @ frame_needed = 1, uses_anonymous_args = 0 + 98 0000 80B5 push {r7, lr} + 99 .cfi_def_cfa_offset 8 + 100 .cfi_offset 7, -8 + 101 .cfi_offset 14, -4 + 102 0002 00AF add r7, sp, #0 + 103 .cfi_def_cfa_register 7 + 165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* Reset of all peripherals */ + 166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** __HAL_RCC_APB1_FORCE_RESET(); + 104 .loc 1 166 3 + 105 0004 0C4B ldr r3, .L7 + 106 0006 4FF0FF32 mov r2, #-1 + 107 000a 1A61 str r2, [r3, #16] + 167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** __HAL_RCC_APB1_RELEASE_RESET(); + 108 .loc 1 167 3 + 109 000c 0A4B ldr r3, .L7 + 110 000e 0022 movs r2, #0 + 111 0010 1A61 str r2, [r3, #16] + 168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** __HAL_RCC_APB2_FORCE_RESET(); + 112 .loc 1 169 3 + 113 0012 094B ldr r3, .L7 + 114 0014 4FF0FF32 mov r2, #-1 + 115 0018 DA60 str r2, [r3, #12] + 170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** __HAL_RCC_APB2_RELEASE_RESET(); + 116 .loc 1 170 3 + 117 001a 074B ldr r3, .L7 + 118 001c 0022 movs r2, #0 + 119 001e DA60 str r2, [r3, #12] + 171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** __HAL_RCC_AHB_FORCE_RESET(); + 120 .loc 1 172 3 + 121 0020 054B ldr r3, .L7 + 122 0022 4FF0FF32 mov r2, #-1 + ARM GAS /tmp/ccHZ4rZ5.s page 6 + + + 123 0026 9A62 str r2, [r3, #40] + 173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** __HAL_RCC_AHB_RELEASE_RESET(); + 124 .loc 1 173 3 + 125 0028 034B ldr r3, .L7 + 126 002a 0022 movs r2, #0 + 127 002c 9A62 str r2, [r3, #40] + 174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* De-Init the low level hardware */ + 176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** HAL_MspDeInit(); + 128 .loc 1 176 3 + 129 002e FFF7FEFF bl HAL_MspDeInit + 177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* Return function status */ + 179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** return HAL_OK; + 130 .loc 1 179 10 + 131 0032 0023 movs r3, #0 + 180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 132 .loc 1 180 1 + 133 0034 1846 mov r0, r3 + 134 0036 80BD pop {r7, pc} + 135 .L8: + 136 .align 2 + 137 .L7: + 138 0038 00100240 .word 1073876992 + 139 .cfi_endproc + 140 .LFE131: + 142 .section .text.HAL_MspInit,"ax",%progbits + 143 .align 1 + 144 .weak HAL_MspInit + 145 .syntax unified + 146 .thumb + 147 .thumb_func + 149 HAL_MspInit: + 150 .LFB132: + 181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief Initialize the MSP. + 184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval None + 185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** __weak void HAL_MspInit(void) + 187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 151 .loc 1 187 1 + 152 .cfi_startproc + 153 @ args = 0, pretend = 0, frame = 0 + 154 @ frame_needed = 1, uses_anonymous_args = 0 + 155 @ link register save eliminated. + 156 0000 80B4 push {r7} + 157 .cfi_def_cfa_offset 4 + 158 .cfi_offset 7, -4 + 159 0002 00AF add r7, sp, #0 + 160 .cfi_def_cfa_register 7 + 188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* NOTE : This function should not be modified, when the callback is needed, + 189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** the HAL_MspInit could be implemented in the user file + 190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 161 .loc 1 191 1 + 162 0004 00BF nop + ARM GAS /tmp/ccHZ4rZ5.s page 7 + + + 163 0006 BD46 mov sp, r7 + 164 .cfi_def_cfa_register 13 + 165 @ sp needed + 166 0008 5DF8047B ldr r7, [sp], #4 + 167 .cfi_restore 7 + 168 .cfi_def_cfa_offset 0 + 169 000c 7047 bx lr + 170 .cfi_endproc + 171 .LFE132: + 173 .section .text.HAL_MspDeInit,"ax",%progbits + 174 .align 1 + 175 .weak HAL_MspDeInit + 176 .syntax unified + 177 .thumb + 178 .thumb_func + 180 HAL_MspDeInit: + 181 .LFB133: + 192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief DeInitialize the MSP. + 195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval None + 196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** __weak void HAL_MspDeInit(void) + 198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 182 .loc 1 198 1 + 183 .cfi_startproc + 184 @ args = 0, pretend = 0, frame = 0 + 185 @ frame_needed = 1, uses_anonymous_args = 0 + 186 @ link register save eliminated. + 187 0000 80B4 push {r7} + 188 .cfi_def_cfa_offset 4 + 189 .cfi_offset 7, -4 + 190 0002 00AF add r7, sp, #0 + 191 .cfi_def_cfa_register 7 + 199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* NOTE : This function should not be modified, when the callback is needed, + 200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** the HAL_MspDeInit could be implemented in the user file + 201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 192 .loc 1 202 1 + 193 0004 00BF nop + 194 0006 BD46 mov sp, r7 + 195 .cfi_def_cfa_register 13 + 196 @ sp needed + 197 0008 5DF8047B ldr r7, [sp], #4 + 198 .cfi_restore 7 + 199 .cfi_def_cfa_offset 0 + 200 000c 7047 bx lr + 201 .cfi_endproc + 202 .LFE133: + 204 .section .text.HAL_InitTick,"ax",%progbits + 205 .align 1 + 206 .weak HAL_InitTick + 207 .syntax unified + 208 .thumb + 209 .thumb_func + 211 HAL_InitTick: + 212 .LFB134: + ARM GAS /tmp/ccHZ4rZ5.s page 8 + + + 203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief This function configures the source of the time base. + 206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * The time source is configured to have 1ms time base with a dedicated + 207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * Tick interrupt priority. + 208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @note This function is called automatically at the beginning of program after + 209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig() + 210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @note In the default implementation , SysTick timer is the source of time base. + 211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * It is used to generate interrupts at regular time intervals. + 212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * Care must be taken if HAL_Delay() is called from a peripheral ISR process, + 213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * The SysTick interrupt must have higher priority (numerically lower) + 214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. + 215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * The function is declared as __Weak to be overwritten in case of other + 216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * implementation in user file. + 217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @param TickPriority Tick interrupt priority. + 218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval HAL status + 219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) + 221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 213 .loc 1 221 1 + 214 .cfi_startproc + 215 @ args = 0, pretend = 0, frame = 8 + 216 @ frame_needed = 1, uses_anonymous_args = 0 + 217 0000 80B5 push {r7, lr} + 218 .cfi_def_cfa_offset 8 + 219 .cfi_offset 7, -8 + 220 .cfi_offset 14, -4 + 221 0002 82B0 sub sp, sp, #8 + 222 .cfi_def_cfa_offset 16 + 223 0004 00AF add r7, sp, #0 + 224 .cfi_def_cfa_register 7 + 225 0006 7860 str r0, [r7, #4] + 222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* Configure the SysTick to have interrupt in 1ms time basis*/ + 223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) + 226 .loc 1 223 7 + 227 0008 124B ldr r3, .L16 + 228 000a 1A68 ldr r2, [r3] + 229 .loc 1 223 51 + 230 000c 124B ldr r3, .L16+4 + 231 000e 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 232 0010 1946 mov r1, r3 + 233 0012 4FF47A73 mov r3, #1000 + 234 0016 B3FBF1F3 udiv r3, r3, r1 + 235 .loc 1 223 7 + 236 001a B2FBF3F3 udiv r3, r2, r3 + 237 001e 1846 mov r0, r3 + 238 0020 FFF7FEFF bl HAL_SYSTICK_Config + 239 0024 0346 mov r3, r0 + 240 .loc 1 223 6 discriminator 1 + 241 0026 002B cmp r3, #0 + 242 0028 01D0 beq .L12 + 224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** return HAL_ERROR; + 243 .loc 1 225 12 + 244 002a 0123 movs r3, #1 + 245 002c 0EE0 b .L13 + 246 .L12: + ARM GAS /tmp/ccHZ4rZ5.s page 9 + + + 226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* Configure the SysTick IRQ priority */ + 229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + 247 .loc 1 229 6 + 248 002e 7B68 ldr r3, [r7, #4] + 249 0030 0F2B cmp r3, #15 + 250 0032 0AD8 bhi .L14 + 230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + 251 .loc 1 231 5 + 252 0034 0022 movs r2, #0 + 253 0036 7968 ldr r1, [r7, #4] + 254 0038 4FF0FF30 mov r0, #-1 + 255 003c FFF7FEFF bl HAL_NVIC_SetPriority + 232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** uwTickPrio = TickPriority; + 256 .loc 1 232 16 + 257 0040 064A ldr r2, .L16+8 + 258 0042 7B68 ldr r3, [r7, #4] + 259 0044 1360 str r3, [r2] + 233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** else + 235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** return HAL_ERROR; + 237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* Return function status */ + 239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** return HAL_OK; + 260 .loc 1 239 10 + 261 0046 0023 movs r3, #0 + 262 0048 00E0 b .L13 + 263 .L14: + 236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 264 .loc 1 236 12 + 265 004a 0123 movs r3, #1 + 266 .L13: + 240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 267 .loc 1 240 1 + 268 004c 1846 mov r0, r3 + 269 004e 0837 adds r7, r7, #8 + 270 .cfi_def_cfa_offset 8 + 271 0050 BD46 mov sp, r7 + 272 .cfi_def_cfa_register 13 + 273 @ sp needed + 274 0052 80BD pop {r7, pc} + 275 .L17: + 276 .align 2 + 277 .L16: + 278 0054 00000000 .word SystemCoreClock + 279 0058 00000000 .word uwTickFreq + 280 005c 00000000 .word uwTickPrio + 281 .cfi_endproc + 282 .LFE134: + 284 .section .text.HAL_IncTick,"ax",%progbits + 285 .align 1 + 286 .weak HAL_IncTick + 287 .syntax unified + 288 .thumb + ARM GAS /tmp/ccHZ4rZ5.s page 10 + + + 289 .thumb_func + 291 HAL_IncTick: + 292 .LFB135: + 241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @} + 244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** @defgroup HAL_Exported_Functions_Group2 HAL Control functions + 247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief HAL Control functions + 248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * + 249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** @verbatim + 250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** =============================================================================== + 251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** ##### HAL Control functions ##### + 252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** =============================================================================== + 253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** [..] This section provides functions allowing to: + 254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** (+) Provide a tick value in millisecond + 255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** (+) Provide a blocking delay in millisecond + 256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** (+) Suspend the time base source interrupt + 257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** (+) Resume the time base source interrupt + 258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** (+) Get the HAL API driver version + 259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** (+) Get the device identifier + 260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** (+) Get the device revision identifier + 261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** (+) Enable/Disable Debug module during Sleep mode + 262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** (+) Enable/Disable Debug module during STOP mode + 263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** (+) Enable/Disable Debug module during STANDBY mode + 264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** @endverbatim + 266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @{ + 267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief This function is called to increment a global variable "uwTick" + 271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * used as application time base. + 272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @note In the default implementation, this variable is incremented each 1ms + 273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * in SysTick ISR. + 274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @note This function is declared as __weak to be overwritten in case of other + 275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * implementations in user file. + 276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval None + 277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** __weak void HAL_IncTick(void) + 279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 293 .loc 1 279 1 + 294 .cfi_startproc + 295 @ args = 0, pretend = 0, frame = 0 + 296 @ frame_needed = 1, uses_anonymous_args = 0 + 297 @ link register save eliminated. + 298 0000 80B4 push {r7} + 299 .cfi_def_cfa_offset 4 + 300 .cfi_offset 7, -4 + 301 0002 00AF add r7, sp, #0 + 302 .cfi_def_cfa_register 7 + 280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** uwTick += uwTickFreq; + 303 .loc 1 280 10 + 304 0004 064B ldr r3, .L19 + 305 0006 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 306 0008 1A46 mov r2, r3 + ARM GAS /tmp/ccHZ4rZ5.s page 11 + + + 307 000a 064B ldr r3, .L19+4 + 308 000c 1B68 ldr r3, [r3] + 309 000e 1344 add r3, r3, r2 + 310 0010 044A ldr r2, .L19+4 + 311 0012 1360 str r3, [r2] + 281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 312 .loc 1 281 1 + 313 0014 00BF nop + 314 0016 BD46 mov sp, r7 + 315 .cfi_def_cfa_register 13 + 316 @ sp needed + 317 0018 5DF8047B ldr r7, [sp], #4 + 318 .cfi_restore 7 + 319 .cfi_def_cfa_offset 0 + 320 001c 7047 bx lr + 321 .L20: + 322 001e 00BF .align 2 + 323 .L19: + 324 0020 00000000 .word uwTickFreq + 325 0024 00000000 .word uwTick + 326 .cfi_endproc + 327 .LFE135: + 329 .section .text.HAL_GetTick,"ax",%progbits + 330 .align 1 + 331 .weak HAL_GetTick + 332 .syntax unified + 333 .thumb + 334 .thumb_func + 336 HAL_GetTick: + 337 .LFB136: + 282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief Povides a tick value in millisecond. + 285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @note The function is declared as __Weak to be overwritten in case of other + 286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * implementations in user file. + 287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval tick value + 288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** __weak uint32_t HAL_GetTick(void) + 290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 338 .loc 1 290 1 + 339 .cfi_startproc + 340 @ args = 0, pretend = 0, frame = 0 + 341 @ frame_needed = 1, uses_anonymous_args = 0 + 342 @ link register save eliminated. + 343 0000 80B4 push {r7} + 344 .cfi_def_cfa_offset 4 + 345 .cfi_offset 7, -4 + 346 0002 00AF add r7, sp, #0 + 347 .cfi_def_cfa_register 7 + 291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** return uwTick; + 348 .loc 1 291 10 + 349 0004 034B ldr r3, .L23 + 350 0006 1B68 ldr r3, [r3] + 292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 351 .loc 1 292 1 + 352 0008 1846 mov r0, r3 + 353 000a BD46 mov sp, r7 + ARM GAS /tmp/ccHZ4rZ5.s page 12 + + + 354 .cfi_def_cfa_register 13 + 355 @ sp needed + 356 000c 5DF8047B ldr r7, [sp], #4 + 357 .cfi_restore 7 + 358 .cfi_def_cfa_offset 0 + 359 0010 7047 bx lr + 360 .L24: + 361 0012 00BF .align 2 + 362 .L23: + 363 0014 00000000 .word uwTick + 364 .cfi_endproc + 365 .LFE136: + 367 .section .text.HAL_GetTickPrio,"ax",%progbits + 368 .align 1 + 369 .global HAL_GetTickPrio + 370 .syntax unified + 371 .thumb + 372 .thumb_func + 374 HAL_GetTickPrio: + 375 .LFB137: + 293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief This function returns a tick priority. + 296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval tick priority + 297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** uint32_t HAL_GetTickPrio(void) + 299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 376 .loc 1 299 1 + 377 .cfi_startproc + 378 @ args = 0, pretend = 0, frame = 0 + 379 @ frame_needed = 1, uses_anonymous_args = 0 + 380 @ link register save eliminated. + 381 0000 80B4 push {r7} + 382 .cfi_def_cfa_offset 4 + 383 .cfi_offset 7, -4 + 384 0002 00AF add r7, sp, #0 + 385 .cfi_def_cfa_register 7 + 300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** return uwTickPrio; + 386 .loc 1 300 10 + 387 0004 034B ldr r3, .L27 + 388 0006 1B68 ldr r3, [r3] + 301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 389 .loc 1 301 1 + 390 0008 1846 mov r0, r3 + 391 000a BD46 mov sp, r7 + 392 .cfi_def_cfa_register 13 + 393 @ sp needed + 394 000c 5DF8047B ldr r7, [sp], #4 + 395 .cfi_restore 7 + 396 .cfi_def_cfa_offset 0 + 397 0010 7047 bx lr + 398 .L28: + 399 0012 00BF .align 2 + 400 .L27: + 401 0014 00000000 .word uwTickPrio + 402 .cfi_endproc + 403 .LFE137: + ARM GAS /tmp/ccHZ4rZ5.s page 13 + + + 405 .section .text.HAL_SetTickFreq,"ax",%progbits + 406 .align 1 + 407 .global HAL_SetTickFreq + 408 .syntax unified + 409 .thumb + 410 .thumb_func + 412 HAL_SetTickFreq: + 413 .LFB138: + 302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief Set new tick Freq. + 305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval status + 306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) + 308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 414 .loc 1 308 1 + 415 .cfi_startproc + 416 @ args = 0, pretend = 0, frame = 16 + 417 @ frame_needed = 1, uses_anonymous_args = 0 + 418 0000 80B5 push {r7, lr} + 419 .cfi_def_cfa_offset 8 + 420 .cfi_offset 7, -8 + 421 .cfi_offset 14, -4 + 422 0002 84B0 sub sp, sp, #16 + 423 .cfi_def_cfa_offset 24 + 424 0004 00AF add r7, sp, #0 + 425 .cfi_def_cfa_register 7 + 426 0006 0346 mov r3, r0 + 427 0008 FB71 strb r3, [r7, #7] + 309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** HAL_StatusTypeDef status = HAL_OK; + 428 .loc 1 309 21 + 429 000a 0023 movs r3, #0 + 430 000c FB73 strb r3, [r7, #15] + 310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** HAL_TickFreqTypeDef prevTickFreq; + 311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** assert_param(IS_TICKFREQ(Freq)); + 313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** if (uwTickFreq != Freq) + 431 .loc 1 314 18 + 432 000e 0E4B ldr r3, .L32 + 433 0010 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 434 .loc 1 314 6 + 435 0012 FA79 ldrb r2, [r7, #7] @ zero_extendqisi2 + 436 0014 9A42 cmp r2, r3 + 437 0016 12D0 beq .L30 + 315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* Back up uwTickFreq frequency */ + 317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** prevTickFreq = uwTickFreq; + 438 .loc 1 317 18 + 439 0018 0B4B ldr r3, .L32 + 440 001a 1B78 ldrb r3, [r3] + 441 001c BB73 strb r3, [r7, #14] + 318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* Update uwTickFreq global variable used by HAL_InitTick() */ + 320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** uwTickFreq = Freq; + 442 .loc 1 320 16 + 443 001e 0A4A ldr r2, .L32 + ARM GAS /tmp/ccHZ4rZ5.s page 14 + + + 444 0020 FB79 ldrb r3, [r7, #7] + 445 0022 1370 strb r3, [r2] + 321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* Apply the new tick Freq */ + 323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** status = HAL_InitTick(uwTickPrio); + 446 .loc 1 323 14 + 447 0024 094B ldr r3, .L32+4 + 448 0026 1B68 ldr r3, [r3] + 449 0028 1846 mov r0, r3 + 450 002a FFF7FEFF bl HAL_InitTick + 451 002e 0346 mov r3, r0 + 452 0030 FB73 strb r3, [r7, #15] + 324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** if (status != HAL_OK) + 453 .loc 1 325 8 + 454 0032 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 455 0034 002B cmp r3, #0 + 456 0036 02D0 beq .L30 + 326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* Restore previous tick frequency */ + 328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** uwTickFreq = prevTickFreq; + 457 .loc 1 328 18 + 458 0038 034A ldr r2, .L32 + 459 003a BB7B ldrb r3, [r7, #14] + 460 003c 1370 strb r3, [r2] + 461 .L30: + 329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** return status; + 462 .loc 1 332 10 + 463 003e FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 464 .loc 1 333 1 + 465 0040 1846 mov r0, r3 + 466 0042 1037 adds r7, r7, #16 + 467 .cfi_def_cfa_offset 8 + 468 0044 BD46 mov sp, r7 + 469 .cfi_def_cfa_register 13 + 470 @ sp needed + 471 0046 80BD pop {r7, pc} + 472 .L33: + 473 .align 2 + 474 .L32: + 475 0048 00000000 .word uwTickFreq + 476 004c 00000000 .word uwTickPrio + 477 .cfi_endproc + 478 .LFE138: + 480 .section .text.HAL_GetTickFreq,"ax",%progbits + 481 .align 1 + 482 .global HAL_GetTickFreq + 483 .syntax unified + 484 .thumb + 485 .thumb_func + 487 HAL_GetTickFreq: + 488 .LFB139: + 334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + ARM GAS /tmp/ccHZ4rZ5.s page 15 + + + 335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief Return tick frequency. + 337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval Tick frequency. + 338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * Value of @ref HAL_TickFreqTypeDef. + 339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** HAL_TickFreqTypeDef HAL_GetTickFreq(void) + 341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 489 .loc 1 341 1 + 490 .cfi_startproc + 491 @ args = 0, pretend = 0, frame = 0 + 492 @ frame_needed = 1, uses_anonymous_args = 0 + 493 @ link register save eliminated. + 494 0000 80B4 push {r7} + 495 .cfi_def_cfa_offset 4 + 496 .cfi_offset 7, -4 + 497 0002 00AF add r7, sp, #0 + 498 .cfi_def_cfa_register 7 + 342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** return uwTickFreq; + 499 .loc 1 342 10 + 500 0004 034B ldr r3, .L36 + 501 0006 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 502 .loc 1 343 1 + 503 0008 1846 mov r0, r3 + 504 000a BD46 mov sp, r7 + 505 .cfi_def_cfa_register 13 + 506 @ sp needed + 507 000c 5DF8047B ldr r7, [sp], #4 + 508 .cfi_restore 7 + 509 .cfi_def_cfa_offset 0 + 510 0010 7047 bx lr + 511 .L37: + 512 0012 00BF .align 2 + 513 .L36: + 514 0014 00000000 .word uwTickFreq + 515 .cfi_endproc + 516 .LFE139: + 518 .section .text.HAL_Delay,"ax",%progbits + 519 .align 1 + 520 .weak HAL_Delay + 521 .syntax unified + 522 .thumb + 523 .thumb_func + 525 HAL_Delay: + 526 .LFB140: + 344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief This function provides accurate delay (in milliseconds) based + 347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * on variable incremented. + 348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @note In the default implementation , SysTick timer is the source of time base. + 349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * It is used to generate interrupts at regular time intervals where uwTick + 350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * is incremented. + 351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * The function is declared as __Weak to be overwritten in case of other + 352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * implementations in user file. + 353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @param Delay specifies the delay time length, in milliseconds. + 354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval None + 355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + ARM GAS /tmp/ccHZ4rZ5.s page 16 + + + 356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** __weak void HAL_Delay(uint32_t Delay) + 357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 527 .loc 1 357 1 + 528 .cfi_startproc + 529 @ args = 0, pretend = 0, frame = 16 + 530 @ frame_needed = 1, uses_anonymous_args = 0 + 531 0000 80B5 push {r7, lr} + 532 .cfi_def_cfa_offset 8 + 533 .cfi_offset 7, -8 + 534 .cfi_offset 14, -4 + 535 0002 84B0 sub sp, sp, #16 + 536 .cfi_def_cfa_offset 24 + 537 0004 00AF add r7, sp, #0 + 538 .cfi_def_cfa_register 7 + 539 0006 7860 str r0, [r7, #4] + 358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** uint32_t tickstart = HAL_GetTick(); + 540 .loc 1 358 24 + 541 0008 FFF7FEFF bl HAL_GetTick + 542 000c B860 str r0, [r7, #8] + 359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** uint32_t wait = Delay; + 543 .loc 1 359 12 + 544 000e 7B68 ldr r3, [r7, #4] + 545 0010 FB60 str r3, [r7, #12] + 360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* Add freq to guarantee minimum wait */ + 362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** if (wait < HAL_MAX_DELAY) + 546 .loc 1 362 6 + 547 0012 FB68 ldr r3, [r7, #12] + 548 0014 B3F1FF3F cmp r3, #-1 + 549 0018 05D0 beq .L41 + 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** wait += (uint32_t)(uwTickFreq); + 550 .loc 1 364 13 + 551 001a 0A4B ldr r3, .L42 + 552 001c 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 553 001e 1A46 mov r2, r3 + 554 .loc 1 364 10 + 555 0020 FB68 ldr r3, [r7, #12] + 556 0022 1344 add r3, r3, r2 + 557 0024 FB60 str r3, [r7, #12] + 558 .L41: + 365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** while((HAL_GetTick() - tickstart) < wait) + 559 .loc 1 367 8 + 560 0026 00BF nop + 561 .L40: + 562 .loc 1 367 10 discriminator 1 + 563 0028 FFF7FEFF bl HAL_GetTick + 564 002c 0246 mov r2, r0 + 565 .loc 1 367 24 discriminator 1 + 566 002e BB68 ldr r3, [r7, #8] + 567 0030 D31A subs r3, r2, r3 + 568 .loc 1 367 37 discriminator 1 + 569 0032 FA68 ldr r2, [r7, #12] + 570 0034 9A42 cmp r2, r3 + 571 0036 F7D8 bhi .L40 + ARM GAS /tmp/ccHZ4rZ5.s page 17 + + + 368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 572 .loc 1 370 1 + 573 0038 00BF nop + 574 003a 00BF nop + 575 003c 1037 adds r7, r7, #16 + 576 .cfi_def_cfa_offset 8 + 577 003e BD46 mov sp, r7 + 578 .cfi_def_cfa_register 13 + 579 @ sp needed + 580 0040 80BD pop {r7, pc} + 581 .L43: + 582 0042 00BF .align 2 + 583 .L42: + 584 0044 00000000 .word uwTickFreq + 585 .cfi_endproc + 586 .LFE140: + 588 .section .text.HAL_SuspendTick,"ax",%progbits + 589 .align 1 + 590 .weak HAL_SuspendTick + 591 .syntax unified + 592 .thumb + 593 .thumb_func + 595 HAL_SuspendTick: + 596 .LFB141: + 371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief Suspend Tick increment. + 374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @note In the default implementation , SysTick timer is the source of time base. It is + 375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() + 376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * is called, the the SysTick interrupt will be disabled and so Tick increment + 377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * is suspended. + 378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @note This function is declared as __weak to be overwritten in case of other + 379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * implementations in user file. + 380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval None + 381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** __weak void HAL_SuspendTick(void) + 383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 597 .loc 1 384 1 + 598 .cfi_startproc + 599 @ args = 0, pretend = 0, frame = 0 + 600 @ frame_needed = 1, uses_anonymous_args = 0 + 601 @ link register save eliminated. + 602 0000 80B4 push {r7} + 603 .cfi_def_cfa_offset 4 + 604 .cfi_offset 7, -4 + 605 0002 00AF add r7, sp, #0 + 606 .cfi_def_cfa_register 7 + 385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* Disable SysTick Interrupt */ + 386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; + 607 .loc 1 386 10 + 608 0004 054B ldr r3, .L45 + 609 0006 1B68 ldr r3, [r3] + 610 0008 044A ldr r2, .L45 + 611 .loc 1 386 17 + ARM GAS /tmp/ccHZ4rZ5.s page 18 + + + 612 000a 23F00203 bic r3, r3, #2 + 613 000e 1360 str r3, [r2] + 387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 614 .loc 1 388 1 + 615 0010 00BF nop + 616 0012 BD46 mov sp, r7 + 617 .cfi_def_cfa_register 13 + 618 @ sp needed + 619 0014 5DF8047B ldr r7, [sp], #4 + 620 .cfi_restore 7 + 621 .cfi_def_cfa_offset 0 + 622 0018 7047 bx lr + 623 .L46: + 624 001a 00BF .align 2 + 625 .L45: + 626 001c 10E000E0 .word -536813552 + 627 .cfi_endproc + 628 .LFE141: + 630 .section .text.HAL_ResumeTick,"ax",%progbits + 631 .align 1 + 632 .weak HAL_ResumeTick + 633 .syntax unified + 634 .thumb + 635 .thumb_func + 637 HAL_ResumeTick: + 638 .LFB142: + 389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief Resume Tick increment. + 392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @note In the default implementation , SysTick timer is the source of time base. It is + 393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() + 394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * is called, the the SysTick interrupt will be enabled and so Tick increment + 395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * is resumed. + 396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * The function is declared as __Weak to be overwritten in case of other + 397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * implementations in user file. + 398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval None + 399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** __weak void HAL_ResumeTick(void) + 401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 639 .loc 1 401 1 + 640 .cfi_startproc + 641 @ args = 0, pretend = 0, frame = 0 + 642 @ frame_needed = 1, uses_anonymous_args = 0 + 643 @ link register save eliminated. + 644 0000 80B4 push {r7} + 645 .cfi_def_cfa_offset 4 + 646 .cfi_offset 7, -4 + 647 0002 00AF add r7, sp, #0 + 648 .cfi_def_cfa_register 7 + 402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /* Enable SysTick Interrupt */ + 403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; + 649 .loc 1 403 10 + 650 0004 054B ldr r3, .L48 + 651 0006 1B68 ldr r3, [r3] + 652 0008 044A ldr r2, .L48 + 653 .loc 1 403 18 + ARM GAS /tmp/ccHZ4rZ5.s page 19 + + + 654 000a 43F00203 orr r3, r3, #2 + 655 000e 1360 str r3, [r2] + 404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 656 .loc 1 405 1 + 657 0010 00BF nop + 658 0012 BD46 mov sp, r7 + 659 .cfi_def_cfa_register 13 + 660 @ sp needed + 661 0014 5DF8047B ldr r7, [sp], #4 + 662 .cfi_restore 7 + 663 .cfi_def_cfa_offset 0 + 664 0018 7047 bx lr + 665 .L49: + 666 001a 00BF .align 2 + 667 .L48: + 668 001c 10E000E0 .word -536813552 + 669 .cfi_endproc + 670 .LFE142: + 672 .section .text.HAL_GetHalVersion,"ax",%progbits + 673 .align 1 + 674 .global HAL_GetHalVersion + 675 .syntax unified + 676 .thumb + 677 .thumb_func + 679 HAL_GetHalVersion: + 680 .LFB143: + 406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief This function returns the HAL revision + 409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval version 0xXYZR (8bits for each decimal, R for RC) + 410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** uint32_t HAL_GetHalVersion(void) + 412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 681 .loc 1 412 1 + 682 .cfi_startproc + 683 @ args = 0, pretend = 0, frame = 0 + 684 @ frame_needed = 1, uses_anonymous_args = 0 + 685 @ link register save eliminated. + 686 0000 80B4 push {r7} + 687 .cfi_def_cfa_offset 4 + 688 .cfi_offset 7, -4 + 689 0002 00AF add r7, sp, #0 + 690 .cfi_def_cfa_register 7 + 413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** return __STM32F3xx_HAL_VERSION; + 691 .loc 1 413 9 + 692 0004 024B ldr r3, .L52 + 414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 693 .loc 1 414 1 + 694 0006 1846 mov r0, r3 + 695 0008 BD46 mov sp, r7 + 696 .cfi_def_cfa_register 13 + 697 @ sp needed + 698 000a 5DF8047B ldr r7, [sp], #4 + 699 .cfi_restore 7 + 700 .cfi_def_cfa_offset 0 + 701 000e 7047 bx lr + ARM GAS /tmp/ccHZ4rZ5.s page 20 + + + 702 .L53: + 703 .align 2 + 704 .L52: + 705 0010 00070501 .word 17106688 + 706 .cfi_endproc + 707 .LFE143: + 709 .section .text.HAL_GetREVID,"ax",%progbits + 710 .align 1 + 711 .global HAL_GetREVID + 712 .syntax unified + 713 .thumb + 714 .thumb_func + 716 HAL_GetREVID: + 717 .LFB144: + 415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief Returns the device revision identifier. + 418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval Device revision identifier + 419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** uint32_t HAL_GetREVID(void) + 421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 718 .loc 1 421 1 + 719 .cfi_startproc + 720 @ args = 0, pretend = 0, frame = 0 + 721 @ frame_needed = 1, uses_anonymous_args = 0 + 722 @ link register save eliminated. + 723 0000 80B4 push {r7} + 724 .cfi_def_cfa_offset 4 + 725 .cfi_offset 7, -4 + 726 0002 00AF add r7, sp, #0 + 727 .cfi_def_cfa_register 7 + 422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** return((DBGMCU->IDCODE) >> 16U); + 728 .loc 1 422 17 + 729 0004 034B ldr r3, .L56 + 730 0006 1B68 ldr r3, [r3] + 731 .loc 1 422 27 + 732 0008 1B0C lsrs r3, r3, #16 + 423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 733 .loc 1 423 1 + 734 000a 1846 mov r0, r3 + 735 000c BD46 mov sp, r7 + 736 .cfi_def_cfa_register 13 + 737 @ sp needed + 738 000e 5DF8047B ldr r7, [sp], #4 + 739 .cfi_restore 7 + 740 .cfi_def_cfa_offset 0 + 741 0012 7047 bx lr + 742 .L57: + 743 .align 2 + 744 .L56: + 745 0014 002004E0 .word -536600576 + 746 .cfi_endproc + 747 .LFE144: + 749 .section .text.HAL_GetDEVID,"ax",%progbits + 750 .align 1 + 751 .global HAL_GetDEVID + 752 .syntax unified + ARM GAS /tmp/ccHZ4rZ5.s page 21 + + + 753 .thumb + 754 .thumb_func + 756 HAL_GetDEVID: + 757 .LFB145: + 424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief Returns the device identifier. + 427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval Device identifier + 428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** uint32_t HAL_GetDEVID(void) + 430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 758 .loc 1 430 1 + 759 .cfi_startproc + 760 @ args = 0, pretend = 0, frame = 0 + 761 @ frame_needed = 1, uses_anonymous_args = 0 + 762 @ link register save eliminated. + 763 0000 80B4 push {r7} + 764 .cfi_def_cfa_offset 4 + 765 .cfi_offset 7, -4 + 766 0002 00AF add r7, sp, #0 + 767 .cfi_def_cfa_register 7 + 431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); + 768 .loc 1 431 17 + 769 0004 044B ldr r3, .L60 + 770 0006 1B68 ldr r3, [r3] + 771 .loc 1 431 27 + 772 0008 C3F30B03 ubfx r3, r3, #0, #12 + 432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 773 .loc 1 432 1 + 774 000c 1846 mov r0, r3 + 775 000e BD46 mov sp, r7 + 776 .cfi_def_cfa_register 13 + 777 @ sp needed + 778 0010 5DF8047B ldr r7, [sp], #4 + 779 .cfi_restore 7 + 780 .cfi_def_cfa_offset 0 + 781 0014 7047 bx lr + 782 .L61: + 783 0016 00BF .align 2 + 784 .L60: + 785 0018 002004E0 .word -536600576 + 786 .cfi_endproc + 787 .LFE145: + 789 .section .text.HAL_GetUIDw0,"ax",%progbits + 790 .align 1 + 791 .global HAL_GetUIDw0 + 792 .syntax unified + 793 .thumb + 794 .thumb_func + 796 HAL_GetUIDw0: + 797 .LFB146: + 433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief Returns first word of the unique device identifier (UID based on 96 bits) + 436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval Device identifier + 437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** uint32_t HAL_GetUIDw0(void) + ARM GAS /tmp/ccHZ4rZ5.s page 22 + + + 439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 798 .loc 1 439 1 + 799 .cfi_startproc + 800 @ args = 0, pretend = 0, frame = 0 + 801 @ frame_needed = 1, uses_anonymous_args = 0 + 802 @ link register save eliminated. + 803 0000 80B4 push {r7} + 804 .cfi_def_cfa_offset 4 + 805 .cfi_offset 7, -4 + 806 0002 00AF add r7, sp, #0 + 807 .cfi_def_cfa_register 7 + 440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** return(READ_REG(*((uint32_t *)UID_BASE))); + 808 .loc 1 440 11 + 809 0004 034B ldr r3, .L64 + 810 0006 1B68 ldr r3, [r3] + 441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 811 .loc 1 441 1 + 812 0008 1846 mov r0, r3 + 813 000a BD46 mov sp, r7 + 814 .cfi_def_cfa_register 13 + 815 @ sp needed + 816 000c 5DF8047B ldr r7, [sp], #4 + 817 .cfi_restore 7 + 818 .cfi_def_cfa_offset 0 + 819 0010 7047 bx lr + 820 .L65: + 821 0012 00BF .align 2 + 822 .L64: + 823 0014 ACF7FF1F .word 536868780 + 824 .cfi_endproc + 825 .LFE146: + 827 .section .text.HAL_GetUIDw1,"ax",%progbits + 828 .align 1 + 829 .global HAL_GetUIDw1 + 830 .syntax unified + 831 .thumb + 832 .thumb_func + 834 HAL_GetUIDw1: + 835 .LFB147: + 442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief Returns second word of the unique device identifier (UID based on 96 bits) + 445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval Device identifier + 446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** uint32_t HAL_GetUIDw1(void) + 448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 836 .loc 1 448 1 + 837 .cfi_startproc + 838 @ args = 0, pretend = 0, frame = 0 + 839 @ frame_needed = 1, uses_anonymous_args = 0 + 840 @ link register save eliminated. + 841 0000 80B4 push {r7} + 842 .cfi_def_cfa_offset 4 + 843 .cfi_offset 7, -4 + 844 0002 00AF add r7, sp, #0 + 845 .cfi_def_cfa_register 7 + 449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** return(READ_REG(*((uint32_t *)(UID_BASE + 4U)))); + ARM GAS /tmp/ccHZ4rZ5.s page 23 + + + 846 .loc 1 449 11 + 847 0004 034B ldr r3, .L68 + 848 0006 1B68 ldr r3, [r3] + 450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 849 .loc 1 450 1 + 850 0008 1846 mov r0, r3 + 851 000a BD46 mov sp, r7 + 852 .cfi_def_cfa_register 13 + 853 @ sp needed + 854 000c 5DF8047B ldr r7, [sp], #4 + 855 .cfi_restore 7 + 856 .cfi_def_cfa_offset 0 + 857 0010 7047 bx lr + 858 .L69: + 859 0012 00BF .align 2 + 860 .L68: + 861 0014 B0F7FF1F .word 536868784 + 862 .cfi_endproc + 863 .LFE147: + 865 .section .text.HAL_GetUIDw2,"ax",%progbits + 866 .align 1 + 867 .global HAL_GetUIDw2 + 868 .syntax unified + 869 .thumb + 870 .thumb_func + 872 HAL_GetUIDw2: + 873 .LFB148: + 451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief Returns third word of the unique device identifier (UID based on 96 bits) + 454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval Device identifier + 455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** uint32_t HAL_GetUIDw2(void) + 457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 874 .loc 1 457 1 + 875 .cfi_startproc + 876 @ args = 0, pretend = 0, frame = 0 + 877 @ frame_needed = 1, uses_anonymous_args = 0 + 878 @ link register save eliminated. + 879 0000 80B4 push {r7} + 880 .cfi_def_cfa_offset 4 + 881 .cfi_offset 7, -4 + 882 0002 00AF add r7, sp, #0 + 883 .cfi_def_cfa_register 7 + 458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** return(READ_REG(*((uint32_t *)(UID_BASE + 8U)))); + 884 .loc 1 458 11 + 885 0004 034B ldr r3, .L72 + 886 0006 1B68 ldr r3, [r3] + 459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 887 .loc 1 459 1 + 888 0008 1846 mov r0, r3 + 889 000a BD46 mov sp, r7 + 890 .cfi_def_cfa_register 13 + 891 @ sp needed + 892 000c 5DF8047B ldr r7, [sp], #4 + 893 .cfi_restore 7 + 894 .cfi_def_cfa_offset 0 + ARM GAS /tmp/ccHZ4rZ5.s page 24 + + + 895 0010 7047 bx lr + 896 .L73: + 897 0012 00BF .align 2 + 898 .L72: + 899 0014 B4F7FF1F .word 536868788 + 900 .cfi_endproc + 901 .LFE148: + 903 .section .text.HAL_DBGMCU_EnableDBGSleepMode,"ax",%progbits + 904 .align 1 + 905 .global HAL_DBGMCU_EnableDBGSleepMode + 906 .syntax unified + 907 .thumb + 908 .thumb_func + 910 HAL_DBGMCU_EnableDBGSleepMode: + 911 .LFB149: + 460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief Enable the Debug Module during SLEEP mode + 463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval None + 464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** void HAL_DBGMCU_EnableDBGSleepMode(void) + 466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 912 .loc 1 466 1 + 913 .cfi_startproc + 914 @ args = 0, pretend = 0, frame = 0 + 915 @ frame_needed = 1, uses_anonymous_args = 0 + 916 @ link register save eliminated. + 917 0000 80B4 push {r7} + 918 .cfi_def_cfa_offset 4 + 919 .cfi_offset 7, -4 + 920 0002 00AF add r7, sp, #0 + 921 .cfi_def_cfa_register 7 + 467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); + 922 .loc 1 467 3 + 923 0004 054B ldr r3, .L75 + 924 0006 5B68 ldr r3, [r3, #4] + 925 0008 044A ldr r2, .L75 + 926 000a 43F00103 orr r3, r3, #1 + 927 000e 5360 str r3, [r2, #4] + 468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 928 .loc 1 468 1 + 929 0010 00BF nop + 930 0012 BD46 mov sp, r7 + 931 .cfi_def_cfa_register 13 + 932 @ sp needed + 933 0014 5DF8047B ldr r7, [sp], #4 + 934 .cfi_restore 7 + 935 .cfi_def_cfa_offset 0 + 936 0018 7047 bx lr + 937 .L76: + 938 001a 00BF .align 2 + 939 .L75: + 940 001c 002004E0 .word -536600576 + 941 .cfi_endproc + 942 .LFE149: + 944 .section .text.HAL_DBGMCU_DisableDBGSleepMode,"ax",%progbits + 945 .align 1 + ARM GAS /tmp/ccHZ4rZ5.s page 25 + + + 946 .global HAL_DBGMCU_DisableDBGSleepMode + 947 .syntax unified + 948 .thumb + 949 .thumb_func + 951 HAL_DBGMCU_DisableDBGSleepMode: + 952 .LFB150: + 469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief Disable the Debug Module during SLEEP mode + 472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval None + 473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** void HAL_DBGMCU_DisableDBGSleepMode(void) + 475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 953 .loc 1 475 1 + 954 .cfi_startproc + 955 @ args = 0, pretend = 0, frame = 0 + 956 @ frame_needed = 1, uses_anonymous_args = 0 + 957 @ link register save eliminated. + 958 0000 80B4 push {r7} + 959 .cfi_def_cfa_offset 4 + 960 .cfi_offset 7, -4 + 961 0002 00AF add r7, sp, #0 + 962 .cfi_def_cfa_register 7 + 476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); + 963 .loc 1 476 3 + 964 0004 054B ldr r3, .L78 + 965 0006 5B68 ldr r3, [r3, #4] + 966 0008 044A ldr r2, .L78 + 967 000a 23F00103 bic r3, r3, #1 + 968 000e 5360 str r3, [r2, #4] + 477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 969 .loc 1 477 1 + 970 0010 00BF nop + 971 0012 BD46 mov sp, r7 + 972 .cfi_def_cfa_register 13 + 973 @ sp needed + 974 0014 5DF8047B ldr r7, [sp], #4 + 975 .cfi_restore 7 + 976 .cfi_def_cfa_offset 0 + 977 0018 7047 bx lr + 978 .L79: + 979 001a 00BF .align 2 + 980 .L78: + 981 001c 002004E0 .word -536600576 + 982 .cfi_endproc + 983 .LFE150: + 985 .section .text.HAL_DBGMCU_EnableDBGStopMode,"ax",%progbits + 986 .align 1 + 987 .global HAL_DBGMCU_EnableDBGStopMode + 988 .syntax unified + 989 .thumb + 990 .thumb_func + 992 HAL_DBGMCU_EnableDBGStopMode: + 993 .LFB151: + 478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief Enable the Debug Module during STOP mode + ARM GAS /tmp/ccHZ4rZ5.s page 26 + + + 481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval None + 482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** void HAL_DBGMCU_EnableDBGStopMode(void) + 484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 994 .loc 1 484 1 + 995 .cfi_startproc + 996 @ args = 0, pretend = 0, frame = 0 + 997 @ frame_needed = 1, uses_anonymous_args = 0 + 998 @ link register save eliminated. + 999 0000 80B4 push {r7} + 1000 .cfi_def_cfa_offset 4 + 1001 .cfi_offset 7, -4 + 1002 0002 00AF add r7, sp, #0 + 1003 .cfi_def_cfa_register 7 + 485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); + 1004 .loc 1 485 3 + 1005 0004 054B ldr r3, .L81 + 1006 0006 5B68 ldr r3, [r3, #4] + 1007 0008 044A ldr r2, .L81 + 1008 000a 43F00203 orr r3, r3, #2 + 1009 000e 5360 str r3, [r2, #4] + 486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 1010 .loc 1 486 1 + 1011 0010 00BF nop + 1012 0012 BD46 mov sp, r7 + 1013 .cfi_def_cfa_register 13 + 1014 @ sp needed + 1015 0014 5DF8047B ldr r7, [sp], #4 + 1016 .cfi_restore 7 + 1017 .cfi_def_cfa_offset 0 + 1018 0018 7047 bx lr + 1019 .L82: + 1020 001a 00BF .align 2 + 1021 .L81: + 1022 001c 002004E0 .word -536600576 + 1023 .cfi_endproc + 1024 .LFE151: + 1026 .section .text.HAL_DBGMCU_DisableDBGStopMode,"ax",%progbits + 1027 .align 1 + 1028 .global HAL_DBGMCU_DisableDBGStopMode + 1029 .syntax unified + 1030 .thumb + 1031 .thumb_func + 1033 HAL_DBGMCU_DisableDBGStopMode: + 1034 .LFB152: + 487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief Disable the Debug Module during STOP mode + 490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval None + 491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** void HAL_DBGMCU_DisableDBGStopMode(void) + 493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 1035 .loc 1 493 1 + 1036 .cfi_startproc + 1037 @ args = 0, pretend = 0, frame = 0 + 1038 @ frame_needed = 1, uses_anonymous_args = 0 + 1039 @ link register save eliminated. + ARM GAS /tmp/ccHZ4rZ5.s page 27 + + + 1040 0000 80B4 push {r7} + 1041 .cfi_def_cfa_offset 4 + 1042 .cfi_offset 7, -4 + 1043 0002 00AF add r7, sp, #0 + 1044 .cfi_def_cfa_register 7 + 494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); + 1045 .loc 1 494 3 + 1046 0004 054B ldr r3, .L84 + 1047 0006 5B68 ldr r3, [r3, #4] + 1048 0008 044A ldr r2, .L84 + 1049 000a 23F00203 bic r3, r3, #2 + 1050 000e 5360 str r3, [r2, #4] + 495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 1051 .loc 1 495 1 + 1052 0010 00BF nop + 1053 0012 BD46 mov sp, r7 + 1054 .cfi_def_cfa_register 13 + 1055 @ sp needed + 1056 0014 5DF8047B ldr r7, [sp], #4 + 1057 .cfi_restore 7 + 1058 .cfi_def_cfa_offset 0 + 1059 0018 7047 bx lr + 1060 .L85: + 1061 001a 00BF .align 2 + 1062 .L84: + 1063 001c 002004E0 .word -536600576 + 1064 .cfi_endproc + 1065 .LFE152: + 1067 .section .text.HAL_DBGMCU_EnableDBGStandbyMode,"ax",%progbits + 1068 .align 1 + 1069 .global HAL_DBGMCU_EnableDBGStandbyMode + 1070 .syntax unified + 1071 .thumb + 1072 .thumb_func + 1074 HAL_DBGMCU_EnableDBGStandbyMode: + 1075 .LFB153: + 496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief Enable the Debug Module during STANDBY mode + 499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval None + 500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** void HAL_DBGMCU_EnableDBGStandbyMode(void) + 502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 1076 .loc 1 502 1 + 1077 .cfi_startproc + 1078 @ args = 0, pretend = 0, frame = 0 + 1079 @ frame_needed = 1, uses_anonymous_args = 0 + 1080 @ link register save eliminated. + 1081 0000 80B4 push {r7} + 1082 .cfi_def_cfa_offset 4 + 1083 .cfi_offset 7, -4 + 1084 0002 00AF add r7, sp, #0 + 1085 .cfi_def_cfa_register 7 + 503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); + 1086 .loc 1 503 3 + 1087 0004 054B ldr r3, .L87 + 1088 0006 5B68 ldr r3, [r3, #4] + ARM GAS /tmp/ccHZ4rZ5.s page 28 + + + 1089 0008 044A ldr r2, .L87 + 1090 000a 43F00403 orr r3, r3, #4 + 1091 000e 5360 str r3, [r2, #4] + 504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 1092 .loc 1 504 1 + 1093 0010 00BF nop + 1094 0012 BD46 mov sp, r7 + 1095 .cfi_def_cfa_register 13 + 1096 @ sp needed + 1097 0014 5DF8047B ldr r7, [sp], #4 + 1098 .cfi_restore 7 + 1099 .cfi_def_cfa_offset 0 + 1100 0018 7047 bx lr + 1101 .L88: + 1102 001a 00BF .align 2 + 1103 .L87: + 1104 001c 002004E0 .word -536600576 + 1105 .cfi_endproc + 1106 .LFE153: + 1108 .section .text.HAL_DBGMCU_DisableDBGStandbyMode,"ax",%progbits + 1109 .align 1 + 1110 .global HAL_DBGMCU_DisableDBGStandbyMode + 1111 .syntax unified + 1112 .thumb + 1113 .thumb_func + 1115 HAL_DBGMCU_DisableDBGStandbyMode: + 1116 .LFB154: + 505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** + 506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** /** + 507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @brief Disable the Debug Module during STANDBY mode + 508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** * @retval None + 509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** */ + 510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** void HAL_DBGMCU_DisableDBGStandbyMode(void) + 511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** { + 1117 .loc 1 511 1 + 1118 .cfi_startproc + 1119 @ args = 0, pretend = 0, frame = 0 + 1120 @ frame_needed = 1, uses_anonymous_args = 0 + 1121 @ link register save eliminated. + 1122 0000 80B4 push {r7} + 1123 .cfi_def_cfa_offset 4 + 1124 .cfi_offset 7, -4 + 1125 0002 00AF add r7, sp, #0 + 1126 .cfi_def_cfa_register 7 + 512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); + 1127 .loc 1 512 3 + 1128 0004 054B ldr r3, .L90 + 1129 0006 5B68 ldr r3, [r3, #4] + 1130 0008 044A ldr r2, .L90 + 1131 000a 23F00403 bic r3, r3, #4 + 1132 000e 5360 str r3, [r2, #4] + 513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal.c **** } + 1133 .loc 1 513 1 + 1134 0010 00BF nop + 1135 0012 BD46 mov sp, r7 + 1136 .cfi_def_cfa_register 13 + 1137 @ sp needed + ARM GAS /tmp/ccHZ4rZ5.s page 29 + + + 1138 0014 5DF8047B ldr r7, [sp], #4 + 1139 .cfi_restore 7 + 1140 .cfi_def_cfa_offset 0 + 1141 0018 7047 bx lr + 1142 .L91: + 1143 001a 00BF .align 2 + 1144 .L90: + 1145 001c 002004E0 .word -536600576 + 1146 .cfi_endproc + 1147 .LFE154: + 1149 .text + 1150 .Letext0: + 1151 .file 2 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + 1152 .file 3 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 1153 .file 4 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 1154 .file 5 "Drivers/CMSIS/Include/core_cm4.h" + 1155 .file 6 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h" + 1156 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h" + 1157 .file 8 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h" + 1158 .file 9 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h" + ARM GAS /tmp/ccHZ4rZ5.s page 30 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f3xx_hal.c + /tmp/ccHZ4rZ5.s:25 .bss.uwTick:00000000 uwTick + /tmp/ccHZ4rZ5.s:22 .bss.uwTick:00000000 $d + /tmp/ccHZ4rZ5.s:32 .data.uwTickPrio:00000000 uwTickPrio + /tmp/ccHZ4rZ5.s:29 .data.uwTickPrio:00000000 $d + /tmp/ccHZ4rZ5.s:38 .data.uwTickFreq:00000000 uwTickFreq + /tmp/ccHZ4rZ5.s:41 .text.HAL_Init:00000000 $t + /tmp/ccHZ4rZ5.s:47 .text.HAL_Init:00000000 HAL_Init + /tmp/ccHZ4rZ5.s:211 .text.HAL_InitTick:00000000 HAL_InitTick + /tmp/ccHZ4rZ5.s:149 .text.HAL_MspInit:00000000 HAL_MspInit + /tmp/ccHZ4rZ5.s:81 .text.HAL_Init:00000028 $d + /tmp/ccHZ4rZ5.s:86 .text.HAL_DeInit:00000000 $t + /tmp/ccHZ4rZ5.s:92 .text.HAL_DeInit:00000000 HAL_DeInit + /tmp/ccHZ4rZ5.s:180 .text.HAL_MspDeInit:00000000 HAL_MspDeInit + /tmp/ccHZ4rZ5.s:138 .text.HAL_DeInit:00000038 $d + /tmp/ccHZ4rZ5.s:143 .text.HAL_MspInit:00000000 $t + /tmp/ccHZ4rZ5.s:174 .text.HAL_MspDeInit:00000000 $t + /tmp/ccHZ4rZ5.s:205 .text.HAL_InitTick:00000000 $t + /tmp/ccHZ4rZ5.s:278 .text.HAL_InitTick:00000054 $d + /tmp/ccHZ4rZ5.s:285 .text.HAL_IncTick:00000000 $t + /tmp/ccHZ4rZ5.s:291 .text.HAL_IncTick:00000000 HAL_IncTick + /tmp/ccHZ4rZ5.s:324 .text.HAL_IncTick:00000020 $d + /tmp/ccHZ4rZ5.s:330 .text.HAL_GetTick:00000000 $t + /tmp/ccHZ4rZ5.s:336 .text.HAL_GetTick:00000000 HAL_GetTick + /tmp/ccHZ4rZ5.s:363 .text.HAL_GetTick:00000014 $d + /tmp/ccHZ4rZ5.s:368 .text.HAL_GetTickPrio:00000000 $t + /tmp/ccHZ4rZ5.s:374 .text.HAL_GetTickPrio:00000000 HAL_GetTickPrio + /tmp/ccHZ4rZ5.s:401 .text.HAL_GetTickPrio:00000014 $d + /tmp/ccHZ4rZ5.s:406 .text.HAL_SetTickFreq:00000000 $t + /tmp/ccHZ4rZ5.s:412 .text.HAL_SetTickFreq:00000000 HAL_SetTickFreq + /tmp/ccHZ4rZ5.s:475 .text.HAL_SetTickFreq:00000048 $d + /tmp/ccHZ4rZ5.s:481 .text.HAL_GetTickFreq:00000000 $t + /tmp/ccHZ4rZ5.s:487 .text.HAL_GetTickFreq:00000000 HAL_GetTickFreq + /tmp/ccHZ4rZ5.s:514 .text.HAL_GetTickFreq:00000014 $d + /tmp/ccHZ4rZ5.s:519 .text.HAL_Delay:00000000 $t + /tmp/ccHZ4rZ5.s:525 .text.HAL_Delay:00000000 HAL_Delay + /tmp/ccHZ4rZ5.s:584 .text.HAL_Delay:00000044 $d + /tmp/ccHZ4rZ5.s:589 .text.HAL_SuspendTick:00000000 $t + /tmp/ccHZ4rZ5.s:595 .text.HAL_SuspendTick:00000000 HAL_SuspendTick + /tmp/ccHZ4rZ5.s:626 .text.HAL_SuspendTick:0000001c $d + /tmp/ccHZ4rZ5.s:631 .text.HAL_ResumeTick:00000000 $t + /tmp/ccHZ4rZ5.s:637 .text.HAL_ResumeTick:00000000 HAL_ResumeTick + /tmp/ccHZ4rZ5.s:668 .text.HAL_ResumeTick:0000001c $d + /tmp/ccHZ4rZ5.s:673 .text.HAL_GetHalVersion:00000000 $t + /tmp/ccHZ4rZ5.s:679 .text.HAL_GetHalVersion:00000000 HAL_GetHalVersion + /tmp/ccHZ4rZ5.s:705 .text.HAL_GetHalVersion:00000010 $d + /tmp/ccHZ4rZ5.s:710 .text.HAL_GetREVID:00000000 $t + /tmp/ccHZ4rZ5.s:716 .text.HAL_GetREVID:00000000 HAL_GetREVID + /tmp/ccHZ4rZ5.s:745 .text.HAL_GetREVID:00000014 $d + /tmp/ccHZ4rZ5.s:750 .text.HAL_GetDEVID:00000000 $t + /tmp/ccHZ4rZ5.s:756 .text.HAL_GetDEVID:00000000 HAL_GetDEVID + /tmp/ccHZ4rZ5.s:785 .text.HAL_GetDEVID:00000018 $d + /tmp/ccHZ4rZ5.s:790 .text.HAL_GetUIDw0:00000000 $t + /tmp/ccHZ4rZ5.s:796 .text.HAL_GetUIDw0:00000000 HAL_GetUIDw0 + /tmp/ccHZ4rZ5.s:823 .text.HAL_GetUIDw0:00000014 $d + /tmp/ccHZ4rZ5.s:828 .text.HAL_GetUIDw1:00000000 $t + ARM GAS /tmp/ccHZ4rZ5.s page 31 + + + /tmp/ccHZ4rZ5.s:834 .text.HAL_GetUIDw1:00000000 HAL_GetUIDw1 + /tmp/ccHZ4rZ5.s:861 .text.HAL_GetUIDw1:00000014 $d + /tmp/ccHZ4rZ5.s:866 .text.HAL_GetUIDw2:00000000 $t + /tmp/ccHZ4rZ5.s:872 .text.HAL_GetUIDw2:00000000 HAL_GetUIDw2 + /tmp/ccHZ4rZ5.s:899 .text.HAL_GetUIDw2:00000014 $d + /tmp/ccHZ4rZ5.s:904 .text.HAL_DBGMCU_EnableDBGSleepMode:00000000 $t + /tmp/ccHZ4rZ5.s:910 .text.HAL_DBGMCU_EnableDBGSleepMode:00000000 HAL_DBGMCU_EnableDBGSleepMode + /tmp/ccHZ4rZ5.s:940 .text.HAL_DBGMCU_EnableDBGSleepMode:0000001c $d + /tmp/ccHZ4rZ5.s:945 .text.HAL_DBGMCU_DisableDBGSleepMode:00000000 $t + /tmp/ccHZ4rZ5.s:951 .text.HAL_DBGMCU_DisableDBGSleepMode:00000000 HAL_DBGMCU_DisableDBGSleepMode + /tmp/ccHZ4rZ5.s:981 .text.HAL_DBGMCU_DisableDBGSleepMode:0000001c $d + /tmp/ccHZ4rZ5.s:986 .text.HAL_DBGMCU_EnableDBGStopMode:00000000 $t + /tmp/ccHZ4rZ5.s:992 .text.HAL_DBGMCU_EnableDBGStopMode:00000000 HAL_DBGMCU_EnableDBGStopMode + /tmp/ccHZ4rZ5.s:1022 .text.HAL_DBGMCU_EnableDBGStopMode:0000001c $d + /tmp/ccHZ4rZ5.s:1027 .text.HAL_DBGMCU_DisableDBGStopMode:00000000 $t + /tmp/ccHZ4rZ5.s:1033 .text.HAL_DBGMCU_DisableDBGStopMode:00000000 HAL_DBGMCU_DisableDBGStopMode + /tmp/ccHZ4rZ5.s:1063 .text.HAL_DBGMCU_DisableDBGStopMode:0000001c $d + /tmp/ccHZ4rZ5.s:1068 .text.HAL_DBGMCU_EnableDBGStandbyMode:00000000 $t + /tmp/ccHZ4rZ5.s:1074 .text.HAL_DBGMCU_EnableDBGStandbyMode:00000000 HAL_DBGMCU_EnableDBGStandbyMode + /tmp/ccHZ4rZ5.s:1104 .text.HAL_DBGMCU_EnableDBGStandbyMode:0000001c $d + /tmp/ccHZ4rZ5.s:1109 .text.HAL_DBGMCU_DisableDBGStandbyMode:00000000 $t + /tmp/ccHZ4rZ5.s:1115 .text.HAL_DBGMCU_DisableDBGStandbyMode:00000000 HAL_DBGMCU_DisableDBGStandbyMode + /tmp/ccHZ4rZ5.s:1145 .text.HAL_DBGMCU_DisableDBGStandbyMode:0000001c $d + +UNDEFINED SYMBOLS +HAL_NVIC_SetPriorityGrouping +HAL_SYSTICK_Config +HAL_NVIC_SetPriority +SystemCoreClock diff --git a/Software/build/stm32f3xx_hal.o b/Software/build/stm32f3xx_hal.o new file mode 100644 index 0000000..5a93f8d Binary files /dev/null and b/Software/build/stm32f3xx_hal.o differ diff --git a/Software/build/stm32f3xx_hal_can.d b/Software/build/stm32f3xx_hal_can.d new file mode 100644 index 0000000..9cb0868 --- /dev/null +++ b/Software/build/stm32f3xx_hal_can.d @@ -0,0 +1,62 @@ +build/stm32f3xx_hal_can.o: \ + Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + Core/Inc/stm32f3xx_hal_conf.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h: diff --git a/Software/build/stm32f3xx_hal_can.lst b/Software/build/stm32f3xx_hal_can.lst new file mode 100644 index 0000000..76c68d3 --- /dev/null +++ b/Software/build/stm32f3xx_hal_can.lst @@ -0,0 +1,7602 @@ +ARM GAS /tmp/ccM1MpQr.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 6 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "stm32f3xx_hal_can.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c" + 20 .section .text.HAL_CAN_Init,"ax",%progbits + 21 .align 1 + 22 .global HAL_CAN_Init + 23 .syntax unified + 24 .thumb + 25 .thumb_func + 27 HAL_CAN_Init: + 28 .LFB130: + 1:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** + 2:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ****************************************************************************** + 3:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @file stm32f3xx_hal_can.c + 4:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @author MCD Application Team + 5:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief CAN HAL module driver. + 6:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * functionalities of the Controller Area Network (CAN) peripheral: + 8:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * + Initialization and de-initialization functions + 9:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * + Configuration functions + 10:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * + Control functions + 11:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * + Interrupts management + 12:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * + Callbacks functions + 13:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * + Peripheral State and Error functions + 14:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * + 15:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ****************************************************************************** + 16:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @attention + 17:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * + 18:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * Copyright (c) 2016 STMicroelectronics. + 19:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * All rights reserved. + 20:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * + 21:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * This software is licensed under terms that can be found in the LICENSE file + 22:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * in the root directory of this software component. + 23:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 24:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * + 25:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ****************************************************************************** + 26:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** @verbatim + 27:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ============================================================================== + 28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ##### How to use this driver ##### + 29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ============================================================================== + 30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** [..] + ARM GAS /tmp/ccM1MpQr.s page 2 + + + 31:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (#) Initialize the CAN low level resources by implementing the + 32:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_MspInit(): + 33:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (++) Enable the CAN interface clock using __HAL_RCC_CANx_CLK_ENABLE() + 34:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (++) Configure CAN pins + 35:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+++) Enable the clock for the CAN GPIOs + 36:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+++) Configure CAN pins as alternate function open-drain + 37:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (++) In case of using interrupts (e.g. HAL_CAN_ActivateNotification()) + 38:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+++) Configure the CAN interrupt priority using + 39:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_NVIC_SetPriority() + 40:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+++) Enable the CAN IRQ handler using HAL_NVIC_EnableIRQ() + 41:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+++) In CAN IRQ handler, call HAL_CAN_IRQHandler() + 42:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 43:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (#) Initialize the CAN peripheral using HAL_CAN_Init() function. This + 44:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** function resorts to HAL_CAN_MspInit() for low-level initialization. + 45:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 46:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (#) Configure the reception filters using the following configuration + 47:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** functions: + 48:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (++) HAL_CAN_ConfigFilter() + 49:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 50:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (#) Start the CAN module using HAL_CAN_Start() function. At this level + 51:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** the node is active on the bus: it receive messages, and can send + 52:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** messages. + 53:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 54:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (#) To manage messages transmission, the following Tx control functions + 55:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** can be used: + 56:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (++) HAL_CAN_AddTxMessage() to request transmission of a new + 57:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** message. + 58:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (++) HAL_CAN_AbortTxRequest() to abort transmission of a pending + 59:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** message. + 60:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (++) HAL_CAN_GetTxMailboxesFreeLevel() to get the number of free Tx + 61:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** mailboxes. + 62:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (++) HAL_CAN_IsTxMessagePending() to check if a message is pending + 63:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** in a Tx mailbox. + 64:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (++) HAL_CAN_GetTxTimestamp() to get the timestamp of Tx message + 65:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** sent, if time triggered communication mode is enabled. + 66:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 67:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (#) When a message is received into the CAN Rx FIFOs, it can be retrieved + 68:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** using the HAL_CAN_GetRxMessage() function. The function + 69:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_GetRxFifoFillLevel() allows to know how many Rx message are + 70:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** stored in the Rx Fifo. + 71:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 72:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (#) Calling the HAL_CAN_Stop() function stops the CAN module. + 73:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 74:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (#) The deinitialization is achieved with HAL_CAN_DeInit() function. + 75:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 76:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 77:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** *** Polling mode operation *** + 78:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ============================== + 79:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** [..] + 80:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (#) Reception: + 81:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (++) Monitor reception of message using HAL_CAN_GetRxFifoFillLevel() + 82:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** until at least one message is received. + 83:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (++) Then get the message using HAL_CAN_GetRxMessage(). + 84:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (#) Transmission: + 86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (++) Monitor the Tx mailboxes availability until at least one Tx + 87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** mailbox is free, using HAL_CAN_GetTxMailboxesFreeLevel(). + ARM GAS /tmp/ccM1MpQr.s page 3 + + + 88:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (++) Then request transmission of a message using + 89:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_AddTxMessage(). + 90:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 91:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 92:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** *** Interrupt mode operation *** + 93:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ================================ + 94:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** [..] + 95:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (#) Notifications are activated using HAL_CAN_ActivateNotification() + 96:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** function. Then, the process can be controlled through the + 97:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** available user callbacks: HAL_CAN_xxxCallback(), using same APIs + 98:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_GetRxMessage() and HAL_CAN_AddTxMessage(). + 99:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (#) Notifications can be deactivated using + 101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_DeactivateNotification() function. + 102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (#) Special care should be taken for CAN_IT_RX_FIFO0_MSG_PENDING and + 104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** CAN_IT_RX_FIFO1_MSG_PENDING notifications. These notifications trig + 105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** the callbacks HAL_CAN_RxFIFO0MsgPendingCallback() and + 106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_RxFIFO1MsgPendingCallback(). User has two possible options + 107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** here. + 108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (++) Directly get the Rx message in the callback, using + 109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_GetRxMessage(). + 110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (++) Or deactivate the notification in the callback without + 111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** getting the Rx message. The Rx message can then be got later + 112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** using HAL_CAN_GetRxMessage(). Once the Rx message have been + 113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** read, the notification can be activated again. + 114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** *** Sleep mode *** + 117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ================== + 118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** [..] + 119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (#) The CAN peripheral can be put in sleep mode (low power), using + 120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_RequestSleep(). The sleep mode will be entered as soon as the + 121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** current CAN activity (transmission or reception of a CAN frame) will + 122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** be completed. + 123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (#) A notification can be activated to be informed when the sleep mode + 125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** will be entered. + 126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (#) It can be checked if the sleep mode is entered using + 128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_IsSleepActive(). + 129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** Note that the CAN state (accessible from the API HAL_CAN_GetState()) + 130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** is HAL_CAN_STATE_SLEEP_PENDING as soon as the sleep mode request is + 131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** submitted (the sleep mode is not yet entered), and become + 132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_STATE_SLEEP_ACTIVE when the sleep mode is effective. + 133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (#) The wake-up from sleep mode can be triggered by two ways: + 135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (++) Using HAL_CAN_WakeUp(). When returning from this function, + 136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** the sleep mode is exited (if return status is HAL_OK). + 137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (++) When a start of Rx CAN frame is detected by the CAN peripheral, + 138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if automatic wake up mode is enabled. + 139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** *** Callback registration *** + 141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ============================================= + 142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** The compilation define USE_HAL_CAN_REGISTER_CALLBACKS when set to 1 + 144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** allows the user to configure dynamically the driver callbacks. + ARM GAS /tmp/ccM1MpQr.s page 4 + + + 145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** Use Function HAL_CAN_RegisterCallback() to register an interrupt callback. + 146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** Function HAL_CAN_RegisterCallback() allows to register following callbacks: + 148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) TxMailbox0CompleteCallback : Tx Mailbox 0 Complete Callback. + 149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) TxMailbox1CompleteCallback : Tx Mailbox 1 Complete Callback. + 150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) TxMailbox2CompleteCallback : Tx Mailbox 2 Complete Callback. + 151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) TxMailbox0AbortCallback : Tx Mailbox 0 Abort Callback. + 152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) TxMailbox1AbortCallback : Tx Mailbox 1 Abort Callback. + 153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) TxMailbox2AbortCallback : Tx Mailbox 2 Abort Callback. + 154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) RxFifo0MsgPendingCallback : Rx Fifo 0 Message Pending Callback. + 155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) RxFifo0FullCallback : Rx Fifo 0 Full Callback. + 156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) RxFifo1MsgPendingCallback : Rx Fifo 1 Message Pending Callback. + 157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) RxFifo1FullCallback : Rx Fifo 1 Full Callback. + 158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) SleepCallback : Sleep Callback. + 159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) WakeUpFromRxMsgCallback : Wake Up From Rx Message Callback. + 160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) ErrorCallback : Error Callback. + 161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) MspInitCallback : CAN MspInit. + 162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) MspDeInitCallback : CAN MspDeInit. + 163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** This function takes as parameters the HAL peripheral handle, the Callback ID + 164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** and a pointer to the user callback function. + 165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** Use function HAL_CAN_UnRegisterCallback() to reset a callback to the default + 167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** weak function. + 168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_UnRegisterCallback takes as parameters the HAL peripheral handle, + 169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** and the Callback ID. + 170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** This function allows to reset following callbacks: + 171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) TxMailbox0CompleteCallback : Tx Mailbox 0 Complete Callback. + 172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) TxMailbox1CompleteCallback : Tx Mailbox 1 Complete Callback. + 173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) TxMailbox2CompleteCallback : Tx Mailbox 2 Complete Callback. + 174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) TxMailbox0AbortCallback : Tx Mailbox 0 Abort Callback. + 175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) TxMailbox1AbortCallback : Tx Mailbox 1 Abort Callback. + 176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) TxMailbox2AbortCallback : Tx Mailbox 2 Abort Callback. + 177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) RxFifo0MsgPendingCallback : Rx Fifo 0 Message Pending Callback. + 178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) RxFifo0FullCallback : Rx Fifo 0 Full Callback. + 179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) RxFifo1MsgPendingCallback : Rx Fifo 1 Message Pending Callback. + 180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) RxFifo1FullCallback : Rx Fifo 1 Full Callback. + 181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) SleepCallback : Sleep Callback. + 182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) WakeUpFromRxMsgCallback : Wake Up From Rx Message Callback. + 183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) ErrorCallback : Error Callback. + 184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) MspInitCallback : CAN MspInit. + 185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) MspDeInitCallback : CAN MspDeInit. + 186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** By default, after the HAL_CAN_Init() and when the state is HAL_CAN_STATE_RESET, + 188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** all callbacks are set to the corresponding weak functions: + 189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** example HAL_CAN_ErrorCallback(). + 190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** Exception done for MspInit and MspDeInit functions that are + 191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** reset to the legacy weak function in the HAL_CAN_Init()/ HAL_CAN_DeInit() only when + 192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** these callbacks are null (not registered beforehand). + 193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if not, MspInit or MspDeInit are not null, the HAL_CAN_Init()/ HAL_CAN_DeInit() + 194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + 195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** Callbacks can be registered/unregistered in HAL_CAN_STATE_READY state only. + 197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** Exception done MspInit/MspDeInit that can be registered/unregistered + 198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** in HAL_CAN_STATE_READY or HAL_CAN_STATE_RESET state, + 199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + 200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** In that case first register the MspInit/MspDeInit user callbacks + 201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** using HAL_CAN_RegisterCallback() before calling HAL_CAN_DeInit() + ARM GAS /tmp/ccM1MpQr.s page 5 + + + 202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** or HAL_CAN_Init() function. + 203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** When The compilation define USE_HAL_CAN_REGISTER_CALLBACKS is set to 0 or + 205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** not defined, the callback registration feature is not available and all callbacks + 206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** are set to the corresponding weak functions. + 207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** @endverbatim + 209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ****************************************************************************** + 210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ + 211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Includes ------------------------------------------------------------------*/ + 213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #include "stm32f3xx_hal.h" + 214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** @addtogroup STM32F3xx_HAL_Driver + 216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @{ + 217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ + 218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #if defined(CAN) + 220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** @defgroup CAN CAN + 222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief CAN driver modules + 223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @{ + 224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ + 225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #ifdef HAL_CAN_MODULE_ENABLED + 227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #ifdef HAL_CAN_LEGACY_MODULE_ENABLED + 229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #error "The CAN driver cannot be used with its legacy, Please enable only one CAN module at once" + 230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ + 231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Private typedef -----------------------------------------------------------*/ + 233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Private define ------------------------------------------------------------*/ + 234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** @defgroup CAN_Private_Constants CAN Private Constants + 235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @{ + 236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ + 237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #define CAN_TIMEOUT_VALUE 10U + 238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** + 239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @} + 240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ + 241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Private macro -------------------------------------------------------------*/ + 242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Private variables ---------------------------------------------------------*/ + 243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Private function prototypes -----------------------------------------------*/ + 244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Exported functions --------------------------------------------------------*/ + 245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** @defgroup CAN_Exported_Functions CAN Exported Functions + 247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @{ + 248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ + 249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions + 251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Initialization and Configuration functions + 252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * + 253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** @verbatim + 254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ============================================================================== + 255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ##### Initialization and de-initialization functions ##### + 256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ============================================================================== + 257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** [..] This section provides functions allowing to: + 258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_Init : Initialize and configure the CAN. + ARM GAS /tmp/ccM1MpQr.s page 6 + + + 259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_DeInit : De-initialize the CAN. + 260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_MspInit : Initialize the CAN MSP. + 261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_MspDeInit : DeInitialize the CAN MSP. + 262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** @endverbatim + 264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @{ + 265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ + 266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** + 268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Initializes the CAN peripheral according to the specified + 269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * parameters in the CAN_InitStruct. + 270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains + 271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. + 272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval HAL status + 273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ + 274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) + 275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 29 .loc 1 275 1 + 30 .cfi_startproc + 31 @ args = 0, pretend = 0, frame = 16 + 32 @ frame_needed = 1, uses_anonymous_args = 0 + 33 0000 80B5 push {r7, lr} + 34 .cfi_def_cfa_offset 8 + 35 .cfi_offset 7, -8 + 36 .cfi_offset 14, -4 + 37 0002 84B0 sub sp, sp, #16 + 38 .cfi_def_cfa_offset 24 + 39 0004 00AF add r7, sp, #0 + 40 .cfi_def_cfa_register 7 + 41 0006 7860 str r0, [r7, #4] + 276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t tickstart; + 277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check CAN handle */ + 279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (hcan == NULL) + 42 .loc 1 279 6 + 43 0008 7B68 ldr r3, [r7, #4] + 44 000a 002B cmp r3, #0 + 45 000c 01D1 bne .L2 + 280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_ERROR; + 46 .loc 1 281 12 + 47 000e 0123 movs r3, #1 + 48 0010 EDE0 b .L3 + 49 .L2: + 282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check the parameters */ + 285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); + 286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TimeTriggeredMode)); + 287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoBusOff)); + 288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoWakeUp)); + 289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoRetransmission)); + 290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ReceiveFifoLocked)); + 291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TransmitFifoPriority)); + 292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_MODE(hcan->Init.Mode)); + 293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_SJW(hcan->Init.SyncJumpWidth)); + 294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_BS1(hcan->Init.TimeSeg1)); + ARM GAS /tmp/ccM1MpQr.s page 7 + + + 295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_BS2(hcan->Init.TimeSeg2)); + 296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler)); + 297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + 299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (hcan->State == HAL_CAN_STATE_RESET) + 300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Reset callbacks to legacy functions */ + 302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->RxFifo0MsgPendingCallback = HAL_CAN_RxFifo0MsgPendingCallback; /* Legacy weak RxFifo0M + 303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->RxFifo0FullCallback = HAL_CAN_RxFifo0FullCallback; /* Legacy weak RxFifo0F + 304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->RxFifo1MsgPendingCallback = HAL_CAN_RxFifo1MsgPendingCallback; /* Legacy weak RxFifo1M + 305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->RxFifo1FullCallback = HAL_CAN_RxFifo1FullCallback; /* Legacy weak RxFifo1F + 306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->TxMailbox0CompleteCallback = HAL_CAN_TxMailbox0CompleteCallback; /* Legacy weak TxMailbo + 307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->TxMailbox1CompleteCallback = HAL_CAN_TxMailbox1CompleteCallback; /* Legacy weak TxMailbo + 308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->TxMailbox2CompleteCallback = HAL_CAN_TxMailbox2CompleteCallback; /* Legacy weak TxMailbo + 309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->TxMailbox0AbortCallback = HAL_CAN_TxMailbox0AbortCallback; /* Legacy weak TxMailbo + 310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->TxMailbox1AbortCallback = HAL_CAN_TxMailbox1AbortCallback; /* Legacy weak TxMailbo + 311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->TxMailbox2AbortCallback = HAL_CAN_TxMailbox2AbortCallback; /* Legacy weak TxMailbo + 312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->SleepCallback = HAL_CAN_SleepCallback; /* Legacy weak SleepCal + 313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->WakeUpFromRxMsgCallback = HAL_CAN_WakeUpFromRxMsgCallback; /* Legacy weak WakeUpFr + 314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCallback = HAL_CAN_ErrorCallback; /* Legacy weak ErrorCal + 315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (hcan->MspInitCallback == NULL) + 317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->MspInitCallback = HAL_CAN_MspInit; /* Legacy weak MspInit */ + 319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Init the low level hardware: CLOCK, NVIC */ + 322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->MspInitCallback(hcan); + 323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #else + 326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (hcan->State == HAL_CAN_STATE_RESET) + 50 .loc 1 326 11 + 51 0012 7B68 ldr r3, [r7, #4] + 52 0014 93F82030 ldrb r3, [r3, #32] + 53 0018 DBB2 uxtb r3, r3 + 54 .loc 1 326 6 + 55 001a 002B cmp r3, #0 + 56 001c 02D1 bne .L4 + 327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Init the low level hardware: CLOCK, NVIC */ + 329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_MspInit(hcan); + 57 .loc 1 329 5 + 58 001e 7868 ldr r0, [r7, #4] + 59 0020 FFF7FEFF bl HAL_CAN_MspInit + 60 .L4: + 330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ + 332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Request initialisation */ + 334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); + 61 .loc 1 334 3 + 62 0024 7B68 ldr r3, [r7, #4] + 63 0026 1B68 ldr r3, [r3] + 64 0028 1A68 ldr r2, [r3] + 65 002a 7B68 ldr r3, [r7, #4] + 66 002c 1B68 ldr r3, [r3] + ARM GAS /tmp/ccM1MpQr.s page 8 + + + 67 002e 42F00102 orr r2, r2, #1 + 68 0032 1A60 str r2, [r3] + 335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Get tick */ + 337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** tickstart = HAL_GetTick(); + 69 .loc 1 337 15 + 70 0034 FFF7FEFF bl HAL_GetTick + 71 0038 F860 str r0, [r7, #12] + 338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Wait initialisation acknowledge */ + 340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) + 72 .loc 1 340 9 + 73 003a 12E0 b .L5 + 74 .L6: + 341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + 75 .loc 1 342 10 + 76 003c FFF7FEFF bl HAL_GetTick + 77 0040 0246 mov r2, r0 + 78 .loc 1 342 24 discriminator 1 + 79 0042 FB68 ldr r3, [r7, #12] + 80 0044 D31A subs r3, r2, r3 + 81 .loc 1 342 8 discriminator 1 + 82 0046 0A2B cmp r3, #10 + 83 0048 0BD9 bls .L5 + 343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code */ + 345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + 84 .loc 1 345 11 + 85 004a 7B68 ldr r3, [r7, #4] + 86 004c 5B6A ldr r3, [r3, #36] + 87 .loc 1 345 23 + 88 004e 43F40032 orr r2, r3, #131072 + 89 0052 7B68 ldr r3, [r7, #4] + 90 0054 5A62 str r2, [r3, #36] + 346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Change CAN state */ + 348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->State = HAL_CAN_STATE_ERROR; + 91 .loc 1 348 19 + 92 0056 7B68 ldr r3, [r7, #4] + 93 0058 0522 movs r2, #5 + 94 005a 83F82020 strb r2, [r3, #32] + 349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_ERROR; + 95 .loc 1 350 14 + 96 005e 0123 movs r3, #1 + 97 0060 C5E0 b .L3 + 98 .L5: + 340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 99 .loc 1 340 15 + 100 0062 7B68 ldr r3, [r7, #4] + 101 0064 1B68 ldr r3, [r3] + 340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 102 .loc 1 340 25 + 103 0066 5B68 ldr r3, [r3, #4] + 340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 104 .loc 1 340 31 + ARM GAS /tmp/ccM1MpQr.s page 9 + + + 105 0068 03F00103 and r3, r3, #1 + 340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 106 .loc 1 340 47 + 107 006c 002B cmp r3, #0 + 108 006e E5D0 beq .L6 + 351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Exit from sleep mode */ + 355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + 109 .loc 1 355 3 + 110 0070 7B68 ldr r3, [r7, #4] + 111 0072 1B68 ldr r3, [r3] + 112 0074 1A68 ldr r2, [r3] + 113 0076 7B68 ldr r3, [r7, #4] + 114 0078 1B68 ldr r3, [r3] + 115 007a 22F00202 bic r2, r2, #2 + 116 007e 1A60 str r2, [r3] + 356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Get tick */ + 358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** tickstart = HAL_GetTick(); + 117 .loc 1 358 15 + 118 0080 FFF7FEFF bl HAL_GetTick + 119 0084 F860 str r0, [r7, #12] + 359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check Sleep mode leave acknowledge */ + 361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) + 120 .loc 1 361 9 + 121 0086 12E0 b .L7 + 122 .L8: + 362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + 123 .loc 1 363 10 + 124 0088 FFF7FEFF bl HAL_GetTick + 125 008c 0246 mov r2, r0 + 126 .loc 1 363 24 discriminator 1 + 127 008e FB68 ldr r3, [r7, #12] + 128 0090 D31A subs r3, r2, r3 + 129 .loc 1 363 8 discriminator 1 + 130 0092 0A2B cmp r3, #10 + 131 0094 0BD9 bls .L7 + 364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code */ + 366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + 132 .loc 1 366 11 + 133 0096 7B68 ldr r3, [r7, #4] + 134 0098 5B6A ldr r3, [r3, #36] + 135 .loc 1 366 23 + 136 009a 43F40032 orr r2, r3, #131072 + 137 009e 7B68 ldr r3, [r7, #4] + 138 00a0 5A62 str r2, [r3, #36] + 367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Change CAN state */ + 369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->State = HAL_CAN_STATE_ERROR; + 139 .loc 1 369 19 + 140 00a2 7B68 ldr r3, [r7, #4] + 141 00a4 0522 movs r2, #5 + ARM GAS /tmp/ccM1MpQr.s page 10 + + + 142 00a6 83F82020 strb r2, [r3, #32] + 370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_ERROR; + 143 .loc 1 371 14 + 144 00aa 0123 movs r3, #1 + 145 00ac 9FE0 b .L3 + 146 .L7: + 361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 147 .loc 1 361 15 + 148 00ae 7B68 ldr r3, [r7, #4] + 149 00b0 1B68 ldr r3, [r3] + 361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 150 .loc 1 361 25 + 151 00b2 5B68 ldr r3, [r3, #4] + 361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 152 .loc 1 361 31 + 153 00b4 03F00203 and r3, r3, #2 + 361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 154 .loc 1 361 47 + 155 00b8 002B cmp r3, #0 + 156 00ba E5D1 bne .L8 + 372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Set the time triggered communication mode */ + 376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (hcan->Init.TimeTriggeredMode == ENABLE) + 157 .loc 1 376 17 + 158 00bc 7B68 ldr r3, [r7, #4] + 159 00be 1B7E ldrb r3, [r3, #24] @ zero_extendqisi2 + 160 .loc 1 376 6 + 161 00c0 012B cmp r3, #1 + 162 00c2 08D1 bne .L9 + 377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); + 163 .loc 1 378 5 + 164 00c4 7B68 ldr r3, [r7, #4] + 165 00c6 1B68 ldr r3, [r3] + 166 00c8 1A68 ldr r2, [r3] + 167 00ca 7B68 ldr r3, [r7, #4] + 168 00cc 1B68 ldr r3, [r3] + 169 00ce 42F08002 orr r2, r2, #128 + 170 00d2 1A60 str r2, [r3] + 171 00d4 07E0 b .L10 + 172 .L9: + 379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else + 381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); + 173 .loc 1 382 5 + 174 00d6 7B68 ldr r3, [r7, #4] + 175 00d8 1B68 ldr r3, [r3] + 176 00da 1A68 ldr r2, [r3] + 177 00dc 7B68 ldr r3, [r7, #4] + 178 00de 1B68 ldr r3, [r3] + 179 00e0 22F08002 bic r2, r2, #128 + 180 00e4 1A60 str r2, [r3] + 181 .L10: + ARM GAS /tmp/ccM1MpQr.s page 11 + + + 383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Set the automatic bus-off management */ + 386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (hcan->Init.AutoBusOff == ENABLE) + 182 .loc 1 386 17 + 183 00e6 7B68 ldr r3, [r7, #4] + 184 00e8 5B7E ldrb r3, [r3, #25] @ zero_extendqisi2 + 185 .loc 1 386 6 + 186 00ea 012B cmp r3, #1 + 187 00ec 08D1 bne .L11 + 387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); + 188 .loc 1 388 5 + 189 00ee 7B68 ldr r3, [r7, #4] + 190 00f0 1B68 ldr r3, [r3] + 191 00f2 1A68 ldr r2, [r3] + 192 00f4 7B68 ldr r3, [r7, #4] + 193 00f6 1B68 ldr r3, [r3] + 194 00f8 42F04002 orr r2, r2, #64 + 195 00fc 1A60 str r2, [r3] + 196 00fe 07E0 b .L12 + 197 .L11: + 389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else + 391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); + 198 .loc 1 392 5 + 199 0100 7B68 ldr r3, [r7, #4] + 200 0102 1B68 ldr r3, [r3] + 201 0104 1A68 ldr r2, [r3] + 202 0106 7B68 ldr r3, [r7, #4] + 203 0108 1B68 ldr r3, [r3] + 204 010a 22F04002 bic r2, r2, #64 + 205 010e 1A60 str r2, [r3] + 206 .L12: + 393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Set the automatic wake-up mode */ + 396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (hcan->Init.AutoWakeUp == ENABLE) + 207 .loc 1 396 17 + 208 0110 7B68 ldr r3, [r7, #4] + 209 0112 9B7E ldrb r3, [r3, #26] @ zero_extendqisi2 + 210 .loc 1 396 6 + 211 0114 012B cmp r3, #1 + 212 0116 08D1 bne .L13 + 397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); + 213 .loc 1 398 5 + 214 0118 7B68 ldr r3, [r7, #4] + 215 011a 1B68 ldr r3, [r3] + 216 011c 1A68 ldr r2, [r3] + 217 011e 7B68 ldr r3, [r7, #4] + 218 0120 1B68 ldr r3, [r3] + 219 0122 42F02002 orr r2, r2, #32 + 220 0126 1A60 str r2, [r3] + 221 0128 07E0 b .L14 + 222 .L13: + ARM GAS /tmp/ccM1MpQr.s page 12 + + + 399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else + 401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); + 223 .loc 1 402 5 + 224 012a 7B68 ldr r3, [r7, #4] + 225 012c 1B68 ldr r3, [r3] + 226 012e 1A68 ldr r2, [r3] + 227 0130 7B68 ldr r3, [r7, #4] + 228 0132 1B68 ldr r3, [r3] + 229 0134 22F02002 bic r2, r2, #32 + 230 0138 1A60 str r2, [r3] + 231 .L14: + 403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Set the automatic retransmission */ + 406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (hcan->Init.AutoRetransmission == ENABLE) + 232 .loc 1 406 17 + 233 013a 7B68 ldr r3, [r7, #4] + 234 013c DB7E ldrb r3, [r3, #27] @ zero_extendqisi2 + 235 .loc 1 406 6 + 236 013e 012B cmp r3, #1 + 237 0140 08D1 bne .L15 + 407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART); + 238 .loc 1 408 5 + 239 0142 7B68 ldr r3, [r7, #4] + 240 0144 1B68 ldr r3, [r3] + 241 0146 1A68 ldr r2, [r3] + 242 0148 7B68 ldr r3, [r7, #4] + 243 014a 1B68 ldr r3, [r3] + 244 014c 22F01002 bic r2, r2, #16 + 245 0150 1A60 str r2, [r3] + 246 0152 07E0 b .L16 + 247 .L15: + 409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else + 411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** SET_BIT(hcan->Instance->MCR, CAN_MCR_NART); + 248 .loc 1 412 5 + 249 0154 7B68 ldr r3, [r7, #4] + 250 0156 1B68 ldr r3, [r3] + 251 0158 1A68 ldr r2, [r3] + 252 015a 7B68 ldr r3, [r7, #4] + 253 015c 1B68 ldr r3, [r3] + 254 015e 42F01002 orr r2, r2, #16 + 255 0162 1A60 str r2, [r3] + 256 .L16: + 413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Set the receive FIFO locked mode */ + 416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (hcan->Init.ReceiveFifoLocked == ENABLE) + 257 .loc 1 416 17 + 258 0164 7B68 ldr r3, [r7, #4] + 259 0166 1B7F ldrb r3, [r3, #28] @ zero_extendqisi2 + 260 .loc 1 416 6 + 261 0168 012B cmp r3, #1 + ARM GAS /tmp/ccM1MpQr.s page 13 + + + 262 016a 08D1 bne .L17 + 417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); + 263 .loc 1 418 5 + 264 016c 7B68 ldr r3, [r7, #4] + 265 016e 1B68 ldr r3, [r3] + 266 0170 1A68 ldr r2, [r3] + 267 0172 7B68 ldr r3, [r7, #4] + 268 0174 1B68 ldr r3, [r3] + 269 0176 42F00802 orr r2, r2, #8 + 270 017a 1A60 str r2, [r3] + 271 017c 07E0 b .L18 + 272 .L17: + 419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else + 421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); + 273 .loc 1 422 5 + 274 017e 7B68 ldr r3, [r7, #4] + 275 0180 1B68 ldr r3, [r3] + 276 0182 1A68 ldr r2, [r3] + 277 0184 7B68 ldr r3, [r7, #4] + 278 0186 1B68 ldr r3, [r3] + 279 0188 22F00802 bic r2, r2, #8 + 280 018c 1A60 str r2, [r3] + 281 .L18: + 423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Set the transmit FIFO priority */ + 426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (hcan->Init.TransmitFifoPriority == ENABLE) + 282 .loc 1 426 17 + 283 018e 7B68 ldr r3, [r7, #4] + 284 0190 5B7F ldrb r3, [r3, #29] @ zero_extendqisi2 + 285 .loc 1 426 6 + 286 0192 012B cmp r3, #1 + 287 0194 08D1 bne .L19 + 427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); + 288 .loc 1 428 5 + 289 0196 7B68 ldr r3, [r7, #4] + 290 0198 1B68 ldr r3, [r3] + 291 019a 1A68 ldr r2, [r3] + 292 019c 7B68 ldr r3, [r7, #4] + 293 019e 1B68 ldr r3, [r3] + 294 01a0 42F00402 orr r2, r2, #4 + 295 01a4 1A60 str r2, [r3] + 296 01a6 07E0 b .L20 + 297 .L19: + 429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else + 431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); + 298 .loc 1 432 5 + 299 01a8 7B68 ldr r3, [r7, #4] + 300 01aa 1B68 ldr r3, [r3] + 301 01ac 1A68 ldr r2, [r3] + 302 01ae 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/ccM1MpQr.s page 14 + + + 303 01b0 1B68 ldr r3, [r3] + 304 01b2 22F00402 bic r2, r2, #4 + 305 01b6 1A60 str r2, [r3] + 306 .L20: + 433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Set the bit timing register */ + 436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode | + 307 .loc 1 436 3 + 308 01b8 7B68 ldr r3, [r7, #4] + 309 01ba 9A68 ldr r2, [r3, #8] + 310 01bc 7B68 ldr r3, [r7, #4] + 311 01be DB68 ldr r3, [r3, #12] + 312 01c0 1A43 orrs r2, r2, r3 + 313 01c2 7B68 ldr r3, [r7, #4] + 314 01c4 1B69 ldr r3, [r3, #16] + 315 01c6 1A43 orrs r2, r2, r3 + 316 01c8 7B68 ldr r3, [r7, #4] + 317 01ca 5B69 ldr r3, [r3, #20] + 318 01cc 42EA0301 orr r1, r2, r3 + 319 01d0 7B68 ldr r3, [r7, #4] + 320 01d2 5B68 ldr r3, [r3, #4] + 321 01d4 5A1E subs r2, r3, #1 + 322 01d6 7B68 ldr r3, [r7, #4] + 323 01d8 1B68 ldr r3, [r3] + 324 01da 0A43 orrs r2, r2, r1 + 325 01dc DA61 str r2, [r3, #28] + 437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->Init.SyncJumpWidth | + 438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->Init.TimeSeg1 | + 439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->Init.TimeSeg2 | + 440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (hcan->Init.Prescaler - 1U))); + 441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Initialize the error code */ + 443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode = HAL_CAN_ERROR_NONE; + 326 .loc 1 443 19 + 327 01de 7B68 ldr r3, [r7, #4] + 328 01e0 0022 movs r2, #0 + 329 01e2 5A62 str r2, [r3, #36] + 444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Initialize the CAN state */ + 446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->State = HAL_CAN_STATE_READY; + 330 .loc 1 446 15 + 331 01e4 7B68 ldr r3, [r7, #4] + 332 01e6 0122 movs r2, #1 + 333 01e8 83F82020 strb r2, [r3, #32] + 447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return function status */ + 449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_OK; + 334 .loc 1 449 10 + 335 01ec 0023 movs r3, #0 + 336 .L3: + 450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 337 .loc 1 450 1 + 338 01ee 1846 mov r0, r3 + 339 01f0 1037 adds r7, r7, #16 + 340 .cfi_def_cfa_offset 8 + 341 01f2 BD46 mov sp, r7 + ARM GAS /tmp/ccM1MpQr.s page 15 + + + 342 .cfi_def_cfa_register 13 + 343 @ sp needed + 344 01f4 80BD pop {r7, pc} + 345 .cfi_endproc + 346 .LFE130: + 348 .section .text.HAL_CAN_DeInit,"ax",%progbits + 349 .align 1 + 350 .global HAL_CAN_DeInit + 351 .syntax unified + 352 .thumb + 353 .thumb_func + 355 HAL_CAN_DeInit: + 356 .LFB131: + 451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** + 453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Deinitializes the CAN peripheral registers to their default + 454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * reset values. + 455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains + 456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. + 457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval HAL status + 458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ + 459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan) + 460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 357 .loc 1 460 1 + 358 .cfi_startproc + 359 @ args = 0, pretend = 0, frame = 8 + 360 @ frame_needed = 1, uses_anonymous_args = 0 + 361 0000 80B5 push {r7, lr} + 362 .cfi_def_cfa_offset 8 + 363 .cfi_offset 7, -8 + 364 .cfi_offset 14, -4 + 365 0002 82B0 sub sp, sp, #8 + 366 .cfi_def_cfa_offset 16 + 367 0004 00AF add r7, sp, #0 + 368 .cfi_def_cfa_register 7 + 369 0006 7860 str r0, [r7, #4] + 461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check CAN handle */ + 462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (hcan == NULL) + 370 .loc 1 462 6 + 371 0008 7B68 ldr r3, [r7, #4] + 372 000a 002B cmp r3, #0 + 373 000c 01D1 bne .L22 + 463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_ERROR; + 374 .loc 1 464 12 + 375 000e 0123 movs r3, #1 + 376 0010 15E0 b .L23 + 377 .L22: + 465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check the parameters */ + 468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); + 469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Stop the CAN module */ + 471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (void)HAL_CAN_Stop(hcan); + 378 .loc 1 471 9 + 379 0012 7868 ldr r0, [r7, #4] + ARM GAS /tmp/ccM1MpQr.s page 16 + + + 380 0014 FFF7FEFF bl HAL_CAN_Stop + 472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + 474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (hcan->MspDeInitCallback == NULL) + 475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->MspDeInitCallback = HAL_CAN_MspDeInit; /* Legacy weak MspDeInit */ + 477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* DeInit the low level hardware: CLOCK, NVIC */ + 480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->MspDeInitCallback(hcan); + 481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #else + 483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* DeInit the low level hardware: CLOCK, NVIC */ + 484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_MspDeInit(hcan); + 381 .loc 1 484 3 + 382 0018 7868 ldr r0, [r7, #4] + 383 001a FFF7FEFF bl HAL_CAN_MspDeInit + 485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ + 486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Reset the CAN peripheral */ + 488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET); + 384 .loc 1 488 3 + 385 001e 7B68 ldr r3, [r7, #4] + 386 0020 1B68 ldr r3, [r3] + 387 0022 1A68 ldr r2, [r3] + 388 0024 7B68 ldr r3, [r7, #4] + 389 0026 1B68 ldr r3, [r3] + 390 0028 42F40042 orr r2, r2, #32768 + 391 002c 1A60 str r2, [r3] + 489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Reset the CAN ErrorCode */ + 491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode = HAL_CAN_ERROR_NONE; + 392 .loc 1 491 19 + 393 002e 7B68 ldr r3, [r7, #4] + 394 0030 0022 movs r2, #0 + 395 0032 5A62 str r2, [r3, #36] + 492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Change CAN state */ + 494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->State = HAL_CAN_STATE_RESET; + 396 .loc 1 494 15 + 397 0034 7B68 ldr r3, [r7, #4] + 398 0036 0022 movs r2, #0 + 399 0038 83F82020 strb r2, [r3, #32] + 495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return function status */ + 497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_OK; + 400 .loc 1 497 10 + 401 003c 0023 movs r3, #0 + 402 .L23: + 498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 403 .loc 1 498 1 + 404 003e 1846 mov r0, r3 + 405 0040 0837 adds r7, r7, #8 + 406 .cfi_def_cfa_offset 8 + 407 0042 BD46 mov sp, r7 + 408 .cfi_def_cfa_register 13 + 409 @ sp needed + ARM GAS /tmp/ccM1MpQr.s page 17 + + + 410 0044 80BD pop {r7, pc} + 411 .cfi_endproc + 412 .LFE131: + 414 .section .text.HAL_CAN_MspInit,"ax",%progbits + 415 .align 1 + 416 .weak HAL_CAN_MspInit + 417 .syntax unified + 418 .thumb + 419 .thumb_func + 421 HAL_CAN_MspInit: + 422 .LFB132: + 499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** + 501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Initializes the CAN MSP. + 502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains + 503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. + 504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval None + 505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ + 506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __weak void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan) + 507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 423 .loc 1 507 1 + 424 .cfi_startproc + 425 @ args = 0, pretend = 0, frame = 8 + 426 @ frame_needed = 1, uses_anonymous_args = 0 + 427 @ link register save eliminated. + 428 0000 80B4 push {r7} + 429 .cfi_def_cfa_offset 4 + 430 .cfi_offset 7, -4 + 431 0002 83B0 sub sp, sp, #12 + 432 .cfi_def_cfa_offset 16 + 433 0004 00AF add r7, sp, #0 + 434 .cfi_def_cfa_register 7 + 435 0006 7860 str r0, [r7, #4] + 508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Prevent unused argument(s) compilation warning */ + 509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** UNUSED(hcan); + 510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* NOTE : This function Should not be modified, when the callback is needed, + 512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** the HAL_CAN_MspInit could be implemented in the user file + 513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ + 514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 436 .loc 1 514 1 + 437 0008 00BF nop + 438 000a 0C37 adds r7, r7, #12 + 439 .cfi_def_cfa_offset 4 + 440 000c BD46 mov sp, r7 + 441 .cfi_def_cfa_register 13 + 442 @ sp needed + 443 000e 5DF8047B ldr r7, [sp], #4 + 444 .cfi_restore 7 + 445 .cfi_def_cfa_offset 0 + 446 0012 7047 bx lr + 447 .cfi_endproc + 448 .LFE132: + 450 .section .text.HAL_CAN_MspDeInit,"ax",%progbits + 451 .align 1 + 452 .weak HAL_CAN_MspDeInit + 453 .syntax unified + ARM GAS /tmp/ccM1MpQr.s page 18 + + + 454 .thumb + 455 .thumb_func + 457 HAL_CAN_MspDeInit: + 458 .LFB133: + 515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** + 517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief DeInitializes the CAN MSP. + 518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains + 519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. + 520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval None + 521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ + 522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan) + 523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 459 .loc 1 523 1 + 460 .cfi_startproc + 461 @ args = 0, pretend = 0, frame = 8 + 462 @ frame_needed = 1, uses_anonymous_args = 0 + 463 @ link register save eliminated. + 464 0000 80B4 push {r7} + 465 .cfi_def_cfa_offset 4 + 466 .cfi_offset 7, -4 + 467 0002 83B0 sub sp, sp, #12 + 468 .cfi_def_cfa_offset 16 + 469 0004 00AF add r7, sp, #0 + 470 .cfi_def_cfa_register 7 + 471 0006 7860 str r0, [r7, #4] + 524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Prevent unused argument(s) compilation warning */ + 525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** UNUSED(hcan); + 526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* NOTE : This function Should not be modified, when the callback is needed, + 528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** the HAL_CAN_MspDeInit could be implemented in the user file + 529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ + 530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 472 .loc 1 530 1 + 473 0008 00BF nop + 474 000a 0C37 adds r7, r7, #12 + 475 .cfi_def_cfa_offset 4 + 476 000c BD46 mov sp, r7 + 477 .cfi_def_cfa_register 13 + 478 @ sp needed + 479 000e 5DF8047B ldr r7, [sp], #4 + 480 .cfi_restore 7 + 481 .cfi_def_cfa_offset 0 + 482 0012 7047 bx lr + 483 .cfi_endproc + 484 .LFE133: + 486 .section .text.HAL_CAN_ConfigFilter,"ax",%progbits + 487 .align 1 + 488 .global HAL_CAN_ConfigFilter + 489 .syntax unified + 490 .thumb + 491 .thumb_func + 493 HAL_CAN_ConfigFilter: + 494 .LFB134: + 531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + 533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** + ARM GAS /tmp/ccM1MpQr.s page 19 + + + 534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Register a CAN CallBack. + 535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * To be used instead of the weak predefined callback + 536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains + 537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for CAN module + 538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param CallbackID ID of the callback to be registered + 539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * This parameter can be one of the following values: + 540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID Tx Mailbox 0 Complete callback ID + 541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID Tx Mailbox 1 Complete callback ID + 542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID Tx Mailbox 2 Complete callback ID + 543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CB_ID Tx Mailbox 0 Abort callback ID + 544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CB_ID Tx Mailbox 1 Abort callback ID + 545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CB_ID Tx Mailbox 2 Abort callback ID + 546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID Rx Fifo 0 message pending callback ID + 547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_RX_FIFO0_FULL_CB_ID Rx Fifo 0 full callback ID + 548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID Rx Fifo 1 message pending callback ID + 549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_RX_FIFO1_FULL_CB_ID Rx Fifo 1 full callback ID + 550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_SLEEP_CB_ID Sleep callback ID + 551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID Wake Up from Rx message callback ID + 552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_ERROR_CB_ID Error callback ID + 553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID + 554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID + 555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param pCallback pointer to the Callback function + 556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval HAL status + 557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ + 558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef Callb + 559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** void (* pCallback)(CAN_HandleTypeDef *_hcan)) + 560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_StatusTypeDef status = HAL_OK; + 562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (pCallback == NULL) + 564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update the error code */ + 566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + 567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_ERROR; + 569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (hcan->State == HAL_CAN_STATE_READY) + 572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** switch (CallbackID) + 574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID : + 576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->TxMailbox0CompleteCallback = pCallback; + 577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID : + 580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->TxMailbox1CompleteCallback = pCallback; + 581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID : + 584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->TxMailbox2CompleteCallback = pCallback; + 585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_TX_MAILBOX0_ABORT_CB_ID : + 588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->TxMailbox0AbortCallback = pCallback; + 589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + ARM GAS /tmp/ccM1MpQr.s page 20 + + + 591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_TX_MAILBOX1_ABORT_CB_ID : + 592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->TxMailbox1AbortCallback = pCallback; + 593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_TX_MAILBOX2_ABORT_CB_ID : + 596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->TxMailbox2AbortCallback = pCallback; + 597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID : + 600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->RxFifo0MsgPendingCallback = pCallback; + 601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 602:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_RX_FIFO0_FULL_CB_ID : + 604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->RxFifo0FullCallback = pCallback; + 605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID : + 608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->RxFifo1MsgPendingCallback = pCallback; + 609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_RX_FIFO1_FULL_CB_ID : + 612:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->RxFifo1FullCallback = pCallback; + 613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_SLEEP_CB_ID : + 616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->SleepCallback = pCallback; + 617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID : + 620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->WakeUpFromRxMsgCallback = pCallback; + 621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_ERROR_CB_ID : + 624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCallback = pCallback; + 625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_MSPINIT_CB_ID : + 628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->MspInitCallback = pCallback; + 629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_MSPDEINIT_CB_ID : + 632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->MspDeInitCallback = pCallback; + 633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** default : + 636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update the error code */ + 637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + 638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return error status */ + 640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** status = HAL_ERROR; + 641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 642:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else if (hcan->State == HAL_CAN_STATE_RESET) + 645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** switch (CallbackID) + 647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + ARM GAS /tmp/ccM1MpQr.s page 21 + + + 648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_MSPINIT_CB_ID : + 649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->MspInitCallback = pCallback; + 650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_MSPDEINIT_CB_ID : + 653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->MspDeInitCallback = pCallback; + 654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 655:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** default : + 657:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update the error code */ + 658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + 659:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return error status */ + 661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** status = HAL_ERROR; + 662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 664:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else + 666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update the error code */ + 668:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + 669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return error status */ + 671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** status = HAL_ERROR; + 672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return status; + 675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** + 678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Unregister a CAN CallBack. + 679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * CAN callback is redirected to the weak predefined callback + 680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains + 681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for CAN module + 682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param CallbackID ID of the callback to be unregistered + 683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * This parameter can be one of the following values: + 684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID Tx Mailbox 0 Complete callback ID + 685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID Tx Mailbox 1 Complete callback ID + 686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID Tx Mailbox 2 Complete callback ID + 687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CB_ID Tx Mailbox 0 Abort callback ID + 688:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CB_ID Tx Mailbox 1 Abort callback ID + 689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CB_ID Tx Mailbox 2 Abort callback ID + 690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID Rx Fifo 0 message pending callback ID + 691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_RX_FIFO0_FULL_CB_ID Rx Fifo 0 full callback ID + 692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID Rx Fifo 1 message pending callback ID + 693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_RX_FIFO1_FULL_CB_ID Rx Fifo 1 full callback ID + 694:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_SLEEP_CB_ID Sleep callback ID + 695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID Wake Up from Rx message callback ID + 696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_ERROR_CB_ID Error callback ID + 697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID + 698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID + 699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval HAL status + 700:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ + 701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef Cal + 702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_StatusTypeDef status = HAL_OK; + 704:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + ARM GAS /tmp/ccM1MpQr.s page 22 + + + 705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (hcan->State == HAL_CAN_STATE_READY) + 706:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 707:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** switch (CallbackID) + 708:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID : + 710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->TxMailbox0CompleteCallback = HAL_CAN_TxMailbox0CompleteCallback; + 711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 713:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID : + 714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->TxMailbox1CompleteCallback = HAL_CAN_TxMailbox1CompleteCallback; + 715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 716:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID : + 718:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->TxMailbox2CompleteCallback = HAL_CAN_TxMailbox2CompleteCallback; + 719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 720:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_TX_MAILBOX0_ABORT_CB_ID : + 722:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->TxMailbox0AbortCallback = HAL_CAN_TxMailbox0AbortCallback; + 723:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 724:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 725:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_TX_MAILBOX1_ABORT_CB_ID : + 726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->TxMailbox1AbortCallback = HAL_CAN_TxMailbox1AbortCallback; + 727:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_TX_MAILBOX2_ABORT_CB_ID : + 730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->TxMailbox2AbortCallback = HAL_CAN_TxMailbox2AbortCallback; + 731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID : + 734:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->RxFifo0MsgPendingCallback = HAL_CAN_RxFifo0MsgPendingCallback; + 735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 737:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_RX_FIFO0_FULL_CB_ID : + 738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->RxFifo0FullCallback = HAL_CAN_RxFifo0FullCallback; + 739:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID : + 742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->RxFifo1MsgPendingCallback = HAL_CAN_RxFifo1MsgPendingCallback; + 743:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 745:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_RX_FIFO1_FULL_CB_ID : + 746:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->RxFifo1FullCallback = HAL_CAN_RxFifo1FullCallback; + 747:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 748:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_SLEEP_CB_ID : + 750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->SleepCallback = HAL_CAN_SleepCallback; + 751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 752:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID : + 754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->WakeUpFromRxMsgCallback = HAL_CAN_WakeUpFromRxMsgCallback; + 755:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_ERROR_CB_ID : + 758:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCallback = HAL_CAN_ErrorCallback; + 759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 760:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 761:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_MSPINIT_CB_ID : + ARM GAS /tmp/ccM1MpQr.s page 23 + + + 762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->MspInitCallback = HAL_CAN_MspInit; + 763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 764:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_MSPDEINIT_CB_ID : + 766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->MspDeInitCallback = HAL_CAN_MspDeInit; + 767:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** default : + 770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update the error code */ + 771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + 772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return error status */ + 774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** status = HAL_ERROR; + 775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 777:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else if (hcan->State == HAL_CAN_STATE_RESET) + 779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 780:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** switch (CallbackID) + 781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 782:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_MSPINIT_CB_ID : + 783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->MspInitCallback = HAL_CAN_MspInit; + 784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case HAL_CAN_MSPDEINIT_CB_ID : + 787:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->MspDeInitCallback = HAL_CAN_MspDeInit; + 788:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** default : + 791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update the error code */ + 792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + 793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return error status */ + 795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** status = HAL_ERROR; + 796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 798:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 799:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else + 800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update the error code */ + 802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + 803:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 804:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return error status */ + 805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** status = HAL_ERROR; + 806:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 807:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 808:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return status; + 809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + 811:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** + 813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @} + 814:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ + 815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** @defgroup CAN_Exported_Functions_Group2 Configuration functions + 817:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Configuration functions. + 818:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * + ARM GAS /tmp/ccM1MpQr.s page 24 + + + 819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** @verbatim + 820:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ============================================================================== + 821:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ##### Configuration functions ##### + 822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ============================================================================== + 823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** [..] This section provides functions allowing to: + 824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_ConfigFilter : Configure the CAN reception filters + 825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** @endverbatim + 827:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @{ + 828:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ + 829:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 830:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** + 831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Configures the CAN reception filter according to the specified + 832:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * parameters in the CAN_FilterInitStruct. + 833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains + 834:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. + 835:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param sFilterConfig pointer to a CAN_FilterTypeDef structure that + 836:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * contains the filter configuration information. + 837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval None + 838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ + 839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_FilterTypeDef *sFilterCon + 840:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 495 .loc 1 840 1 + 496 .cfi_startproc + 497 @ args = 0, pretend = 0, frame = 24 + 498 @ frame_needed = 1, uses_anonymous_args = 0 + 499 @ link register save eliminated. + 500 0000 80B4 push {r7} + 501 .cfi_def_cfa_offset 4 + 502 .cfi_offset 7, -4 + 503 0002 87B0 sub sp, sp, #28 + 504 .cfi_def_cfa_offset 32 + 505 0004 00AF add r7, sp, #0 + 506 .cfi_def_cfa_register 7 + 507 0006 7860 str r0, [r7, #4] + 508 0008 3960 str r1, [r7] + 841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t filternbrbitpos; + 842:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** CAN_TypeDef *can_ip = hcan->Instance; + 509 .loc 1 842 16 + 510 000a 7B68 ldr r3, [r7, #4] + 511 000c 1B68 ldr r3, [r3] + 512 000e 7B61 str r3, [r7, #20] + 843:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_StateTypeDef state = hcan->State; + 513 .loc 1 843 24 + 514 0010 7B68 ldr r3, [r7, #4] + 515 0012 93F82030 ldrb r3, [r3, #32] + 516 0016 FB74 strb r3, [r7, #19] + 844:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((state == HAL_CAN_STATE_READY) || + 517 .loc 1 845 6 + 518 0018 FB7C ldrb r3, [r7, #19] @ zero_extendqisi2 + 519 001a 012B cmp r3, #1 + 520 001c 03D0 beq .L27 + 521 .loc 1 845 38 discriminator 1 + 522 001e FB7C ldrb r3, [r7, #19] @ zero_extendqisi2 + 523 0020 022B cmp r3, #2 + 524 0022 40F0AA80 bne .L28 + ARM GAS /tmp/ccM1MpQr.s page 25 + + + 525 .L27: + 846:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (state == HAL_CAN_STATE_LISTENING)) + 847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check the parameters */ + 849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdHigh)); + 850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdLow)); + 851:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdHigh)); + 852:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdLow)); + 853:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode)); + 854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale)); + 855:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment)); + 856:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_FILTER_ACTIVATION(sFilterConfig->FilterActivation)); + 857:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* CAN is single instance with 14 dedicated filters banks */ + 859:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check the parameters */ + 861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); + 862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Initialisation mode for the filter */ + 864:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** SET_BIT(can_ip->FMR, CAN_FMR_FINIT); + 526 .loc 1 864 5 + 527 0026 7B69 ldr r3, [r7, #20] + 528 0028 D3F80032 ldr r3, [r3, #512] + 529 002c 43F00102 orr r2, r3, #1 + 530 0030 7B69 ldr r3, [r7, #20] + 531 0032 C3F80022 str r2, [r3, #512] + 865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Convert filter number into bit position */ + 867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU); + 532 .loc 1 867 52 + 533 0036 3B68 ldr r3, [r7] + 534 0038 5B69 ldr r3, [r3, #20] + 535 .loc 1 867 65 + 536 003a 03F01F03 and r3, r3, #31 + 537 .loc 1 867 21 + 538 003e 0122 movs r2, #1 + 539 0040 02FA03F3 lsl r3, r2, r3 + 540 0044 FB60 str r3, [r7, #12] + 868:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Filter Deactivation */ + 870:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** CLEAR_BIT(can_ip->FA1R, filternbrbitpos); + 541 .loc 1 870 5 + 542 0046 7B69 ldr r3, [r7, #20] + 543 0048 D3F81C22 ldr r2, [r3, #540] + 544 004c FB68 ldr r3, [r7, #12] + 545 004e DB43 mvns r3, r3 + 546 0050 1A40 ands r2, r2, r3 + 547 0052 7B69 ldr r3, [r7, #20] + 548 0054 C3F81C22 str r2, [r3, #540] + 871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Filter Scale */ + 873:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) + 549 .loc 1 873 22 + 550 0058 3B68 ldr r3, [r7] + 551 005a DB69 ldr r3, [r3, #28] + 552 .loc 1 873 8 + 553 005c 002B cmp r3, #0 + ARM GAS /tmp/ccM1MpQr.s page 26 + + + 554 005e 23D1 bne .L29 + 874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 875:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* 16-bit scale for the filter */ + 876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** CLEAR_BIT(can_ip->FS1R, filternbrbitpos); + 555 .loc 1 876 7 + 556 0060 7B69 ldr r3, [r7, #20] + 557 0062 D3F80C22 ldr r2, [r3, #524] + 558 0066 FB68 ldr r3, [r7, #12] + 559 0068 DB43 mvns r3, r3 + 560 006a 1A40 ands r2, r2, r3 + 561 006c 7B69 ldr r3, [r7, #20] + 562 006e C3F80C22 str r2, [r3, #524] + 877:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 878:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* First 16-bit identifier and First 16-bit mask */ + 879:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Or First 16-bit identifier and Second 16-bit identifier */ + 880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = + 881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | + 563 .loc 1 881 48 + 564 0072 3B68 ldr r3, [r7] + 565 0074 DB68 ldr r3, [r3, #12] + 566 .loc 1 881 67 + 567 0076 1904 lsls r1, r3, #16 + 882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + 568 .loc 1 882 47 + 569 0078 3B68 ldr r3, [r7] + 570 007a 5B68 ldr r3, [r3, #4] + 571 .loc 1 882 22 + 572 007c 9BB2 uxth r3, r3 + 880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | + 573 .loc 1 880 44 + 574 007e 3A68 ldr r2, [r7] + 575 0080 5269 ldr r2, [r2, #20] + 881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + 576 .loc 1 881 75 + 577 0082 1943 orrs r1, r1, r3 + 880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | + 578 .loc 1 880 62 + 579 0084 7B69 ldr r3, [r7, #20] + 580 0086 4832 adds r2, r2, #72 + 581 0088 43F83210 str r1, [r3, r2, lsl #3] + 883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 884:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Second 16-bit identifier and Second 16-bit mask */ + 885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Or Third 16-bit identifier and Fourth 16-bit identifier */ + 886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = + 887:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + 582 .loc 1 887 48 + 583 008c 3B68 ldr r3, [r7] + 584 008e 9B68 ldr r3, [r3, #8] + 585 .loc 1 887 68 + 586 0090 1904 lsls r1, r3, #16 + 888:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); + 587 .loc 1 888 47 + 588 0092 3B68 ldr r3, [r7] + 589 0094 1B68 ldr r3, [r3] + 590 .loc 1 888 22 + 591 0096 9AB2 uxth r2, r3 + 886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + ARM GAS /tmp/ccM1MpQr.s page 27 + + + 592 .loc 1 886 44 + 593 0098 3B68 ldr r3, [r7] + 594 009a 5B69 ldr r3, [r3, #20] + 887:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); + 595 .loc 1 887 76 + 596 009c 0A43 orrs r2, r2, r1 + 886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + 597 .loc 1 886 62 + 598 009e 7969 ldr r1, [r7, #20] + 599 00a0 4833 adds r3, r3, #72 + 600 00a2 DB00 lsls r3, r3, #3 + 601 00a4 0B44 add r3, r3, r1 + 602 00a6 5A60 str r2, [r3, #4] + 603 .L29: + 889:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 890:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) + 604 .loc 1 891 22 + 605 00a8 3B68 ldr r3, [r7] + 606 00aa DB69 ldr r3, [r3, #28] + 607 .loc 1 891 8 + 608 00ac 012B cmp r3, #1 + 609 00ae 22D1 bne .L30 + 892:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* 32-bit scale for the filter */ + 894:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** SET_BIT(can_ip->FS1R, filternbrbitpos); + 610 .loc 1 894 7 + 611 00b0 7B69 ldr r3, [r7, #20] + 612 00b2 D3F80C22 ldr r2, [r3, #524] + 613 00b6 FB68 ldr r3, [r7, #12] + 614 00b8 1A43 orrs r2, r2, r3 + 615 00ba 7B69 ldr r3, [r7, #20] + 616 00bc C3F80C22 str r2, [r3, #524] + 895:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* 32-bit identifier or First 32-bit identifier */ + 897:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = + 898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | + 617 .loc 1 898 48 + 618 00c0 3B68 ldr r3, [r7] + 619 00c2 1B68 ldr r3, [r3] + 620 .loc 1 898 64 + 621 00c4 1904 lsls r1, r3, #16 + 899:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + 622 .loc 1 899 47 + 623 00c6 3B68 ldr r3, [r7] + 624 00c8 5B68 ldr r3, [r3, #4] + 625 .loc 1 899 22 + 626 00ca 9BB2 uxth r3, r3 + 897:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | + 627 .loc 1 897 44 + 628 00cc 3A68 ldr r2, [r7] + 629 00ce 5269 ldr r2, [r2, #20] + 898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + 630 .loc 1 898 72 + 631 00d0 1943 orrs r1, r1, r3 + 897:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | + 632 .loc 1 897 62 + ARM GAS /tmp/ccM1MpQr.s page 28 + + + 633 00d2 7B69 ldr r3, [r7, #20] + 634 00d4 4832 adds r2, r2, #72 + 635 00d6 43F83210 str r1, [r3, r2, lsl #3] + 900:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* 32-bit mask or Second 32-bit identifier */ + 902:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = + 903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + 636 .loc 1 903 48 + 637 00da 3B68 ldr r3, [r7] + 638 00dc 9B68 ldr r3, [r3, #8] + 639 .loc 1 903 68 + 640 00de 1904 lsls r1, r3, #16 + 904:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); + 641 .loc 1 904 47 + 642 00e0 3B68 ldr r3, [r7] + 643 00e2 DB68 ldr r3, [r3, #12] + 644 .loc 1 904 22 + 645 00e4 9AB2 uxth r2, r3 + 902:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + 646 .loc 1 902 44 + 647 00e6 3B68 ldr r3, [r7] + 648 00e8 5B69 ldr r3, [r3, #20] + 903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); + 649 .loc 1 903 76 + 650 00ea 0A43 orrs r2, r2, r1 + 902:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + 651 .loc 1 902 62 + 652 00ec 7969 ldr r1, [r7, #20] + 653 00ee 4833 adds r3, r3, #72 + 654 00f0 DB00 lsls r3, r3, #3 + 655 00f2 0B44 add r3, r3, r1 + 656 00f4 5A60 str r2, [r3, #4] + 657 .L30: + 905:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 906:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Filter Mode */ + 908:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) + 658 .loc 1 908 22 + 659 00f6 3B68 ldr r3, [r7] + 660 00f8 9B69 ldr r3, [r3, #24] + 661 .loc 1 908 8 + 662 00fa 002B cmp r3, #0 + 663 00fc 09D1 bne .L31 + 909:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Id/Mask mode for the filter*/ + 911:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** CLEAR_BIT(can_ip->FM1R, filternbrbitpos); + 664 .loc 1 911 7 + 665 00fe 7B69 ldr r3, [r7, #20] + 666 0100 D3F80422 ldr r2, [r3, #516] + 667 0104 FB68 ldr r3, [r7, #12] + 668 0106 DB43 mvns r3, r3 + 669 0108 1A40 ands r2, r2, r3 + 670 010a 7B69 ldr r3, [r7, #20] + 671 010c C3F80422 str r2, [r3, #516] + 672 0110 07E0 b .L32 + 673 .L31: + 912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + ARM GAS /tmp/ccM1MpQr.s page 29 + + + 913:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ + 914:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 915:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Identifier list mode for the filter*/ + 916:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** SET_BIT(can_ip->FM1R, filternbrbitpos); + 674 .loc 1 916 7 + 675 0112 7B69 ldr r3, [r7, #20] + 676 0114 D3F80422 ldr r2, [r3, #516] + 677 0118 FB68 ldr r3, [r7, #12] + 678 011a 1A43 orrs r2, r2, r3 + 679 011c 7B69 ldr r3, [r7, #20] + 680 011e C3F80422 str r2, [r3, #516] + 681 .L32: + 917:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 918:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 919:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Filter FIFO assignment */ + 920:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) + 682 .loc 1 920 22 + 683 0122 3B68 ldr r3, [r7] + 684 0124 1B69 ldr r3, [r3, #16] + 685 .loc 1 920 8 + 686 0126 002B cmp r3, #0 + 687 0128 09D1 bne .L33 + 921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 922:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* FIFO 0 assignation for the filter */ + 923:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** CLEAR_BIT(can_ip->FFA1R, filternbrbitpos); + 688 .loc 1 923 7 + 689 012a 7B69 ldr r3, [r7, #20] + 690 012c D3F81422 ldr r2, [r3, #532] + 691 0130 FB68 ldr r3, [r7, #12] + 692 0132 DB43 mvns r3, r3 + 693 0134 1A40 ands r2, r2, r3 + 694 0136 7B69 ldr r3, [r7, #20] + 695 0138 C3F81422 str r2, [r3, #532] + 696 013c 07E0 b .L34 + 697 .L33: + 924:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 925:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else + 926:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* FIFO 1 assignation for the filter */ + 928:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** SET_BIT(can_ip->FFA1R, filternbrbitpos); + 698 .loc 1 928 7 + 699 013e 7B69 ldr r3, [r7, #20] + 700 0140 D3F81422 ldr r2, [r3, #532] + 701 0144 FB68 ldr r3, [r7, #12] + 702 0146 1A43 orrs r2, r2, r3 + 703 0148 7B69 ldr r3, [r7, #20] + 704 014a C3F81422 str r2, [r3, #532] + 705 .L34: + 929:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 930:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 931:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Filter activation */ + 932:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE) + 706 .loc 1 932 22 + 707 014e 3B68 ldr r3, [r7] + 708 0150 1B6A ldr r3, [r3, #32] + 709 .loc 1 932 8 + 710 0152 012B cmp r3, #1 + ARM GAS /tmp/ccM1MpQr.s page 30 + + + 711 0154 07D1 bne .L35 + 933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 934:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** SET_BIT(can_ip->FA1R, filternbrbitpos); + 712 .loc 1 934 7 + 713 0156 7B69 ldr r3, [r7, #20] + 714 0158 D3F81C22 ldr r2, [r3, #540] + 715 015c FB68 ldr r3, [r7, #12] + 716 015e 1A43 orrs r2, r2, r3 + 717 0160 7B69 ldr r3, [r7, #20] + 718 0162 C3F81C22 str r2, [r3, #540] + 719 .L35: + 935:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 936:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Leave the initialisation mode for the filter */ + 938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT); + 720 .loc 1 938 5 + 721 0166 7B69 ldr r3, [r7, #20] + 722 0168 D3F80032 ldr r3, [r3, #512] + 723 016c 23F00102 bic r2, r3, #1 + 724 0170 7B69 ldr r3, [r7, #20] + 725 0172 C3F80022 str r2, [r3, #512] + 939:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return function status */ + 941:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_OK; + 726 .loc 1 941 12 + 727 0176 0023 movs r3, #0 + 728 0178 06E0 b .L36 + 729 .L28: + 942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 943:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else + 944:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code */ + 946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + 730 .loc 1 946 9 + 731 017a 7B68 ldr r3, [r7, #4] + 732 017c 5B6A ldr r3, [r3, #36] + 733 .loc 1 946 21 + 734 017e 43F48022 orr r2, r3, #262144 + 735 0182 7B68 ldr r3, [r7, #4] + 736 0184 5A62 str r2, [r3, #36] + 947:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 948:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_ERROR; + 737 .loc 1 948 12 + 738 0186 0123 movs r3, #1 + 739 .L36: + 949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 950:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 740 .loc 1 950 1 + 741 0188 1846 mov r0, r3 + 742 018a 1C37 adds r7, r7, #28 + 743 .cfi_def_cfa_offset 4 + 744 018c BD46 mov sp, r7 + 745 .cfi_def_cfa_register 13 + 746 @ sp needed + 747 018e 5DF8047B ldr r7, [sp], #4 + 748 .cfi_restore 7 + 749 .cfi_def_cfa_offset 0 + ARM GAS /tmp/ccM1MpQr.s page 31 + + + 750 0192 7047 bx lr + 751 .cfi_endproc + 752 .LFE134: + 754 .section .text.HAL_CAN_Start,"ax",%progbits + 755 .align 1 + 756 .global HAL_CAN_Start + 757 .syntax unified + 758 .thumb + 759 .thumb_func + 761 HAL_CAN_Start: + 762 .LFB135: + 951:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** + 953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @} + 954:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ + 955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 956:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** @defgroup CAN_Exported_Functions_Group3 Control functions + 957:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Control functions + 958:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * + 959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** @verbatim + 960:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ============================================================================== + 961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ##### Control functions ##### + 962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ============================================================================== + 963:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** [..] This section provides functions allowing to: + 964:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_Start : Start the CAN module + 965:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_Stop : Stop the CAN module + 966:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_RequestSleep : Request sleep mode entry. + 967:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_WakeUp : Wake up from sleep mode. + 968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_IsSleepActive : Check is sleep mode is active. + 969:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_AddTxMessage : Add a message to the Tx mailboxes + 970:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** and activate the corresponding + 971:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** transmission request + 972:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_AbortTxRequest : Abort transmission request + 973:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_GetTxMailboxesFreeLevel : Return Tx mailboxes free level + 974:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_IsTxMessagePending : Check if a transmission request is + 975:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** pending on the selected Tx mailbox + 976:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_GetRxMessage : Get a CAN frame from the Rx FIFO + 977:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_GetRxFifoFillLevel : Return Rx FIFO fill level + 978:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 979:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** @endverbatim + 980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @{ + 981:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ + 982:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 983:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** + 984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Start the CAN module. + 985:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to an CAN_HandleTypeDef structure that contains + 986:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. + 987:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval HAL status + 988:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ + 989:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan) + 990:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 763 .loc 1 990 1 + 764 .cfi_startproc + 765 @ args = 0, pretend = 0, frame = 16 + 766 @ frame_needed = 1, uses_anonymous_args = 0 + 767 0000 80B5 push {r7, lr} + 768 .cfi_def_cfa_offset 8 + ARM GAS /tmp/ccM1MpQr.s page 32 + + + 769 .cfi_offset 7, -8 + 770 .cfi_offset 14, -4 + 771 0002 84B0 sub sp, sp, #16 + 772 .cfi_def_cfa_offset 24 + 773 0004 00AF add r7, sp, #0 + 774 .cfi_def_cfa_register 7 + 775 0006 7860 str r0, [r7, #4] + 991:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t tickstart; + 992:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 993:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (hcan->State == HAL_CAN_STATE_READY) + 776 .loc 1 993 11 + 777 0008 7B68 ldr r3, [r7, #4] + 778 000a 93F82030 ldrb r3, [r3, #32] + 779 000e DBB2 uxtb r3, r3 + 780 .loc 1 993 6 + 781 0010 012B cmp r3, #1 + 782 0012 2ED1 bne .L38 + 994:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Change CAN peripheral state */ + 996:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->State = HAL_CAN_STATE_LISTENING; + 783 .loc 1 996 17 + 784 0014 7B68 ldr r3, [r7, #4] + 785 0016 0222 movs r2, #2 + 786 0018 83F82020 strb r2, [r3, #32] + 997:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + 998:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Request leave initialisation */ + 999:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); + 787 .loc 1 999 5 + 788 001c 7B68 ldr r3, [r7, #4] + 789 001e 1B68 ldr r3, [r3] + 790 0020 1A68 ldr r2, [r3] + 791 0022 7B68 ldr r3, [r7, #4] + 792 0024 1B68 ldr r3, [r3] + 793 0026 22F00102 bic r2, r2, #1 + 794 002a 1A60 str r2, [r3] +1000:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1001:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Get tick */ +1002:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** tickstart = HAL_GetTick(); + 795 .loc 1 1002 17 + 796 002c FFF7FEFF bl HAL_GetTick + 797 0030 F860 str r0, [r7, #12] +1003:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Wait the acknowledge */ +1005:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) + 798 .loc 1 1005 11 + 799 0032 12E0 b .L39 + 800 .L41: +1006:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check for the Timeout */ +1008:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + 801 .loc 1 1008 12 + 802 0034 FFF7FEFF bl HAL_GetTick + 803 0038 0246 mov r2, r0 + 804 .loc 1 1008 26 discriminator 1 + 805 003a FB68 ldr r3, [r7, #12] + 806 003c D31A subs r3, r2, r3 + 807 .loc 1 1008 10 discriminator 1 + ARM GAS /tmp/ccM1MpQr.s page 33 + + + 808 003e 0A2B cmp r3, #10 + 809 0040 0BD9 bls .L39 +1009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1010:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code */ +1011:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + 810 .loc 1 1011 13 + 811 0042 7B68 ldr r3, [r7, #4] + 812 0044 5B6A ldr r3, [r3, #36] + 813 .loc 1 1011 25 + 814 0046 43F40032 orr r2, r3, #131072 + 815 004a 7B68 ldr r3, [r7, #4] + 816 004c 5A62 str r2, [r3, #36] +1012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1013:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Change CAN state */ +1014:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->State = HAL_CAN_STATE_ERROR; + 817 .loc 1 1014 21 + 818 004e 7B68 ldr r3, [r7, #4] + 819 0050 0522 movs r2, #5 + 820 0052 83F82020 strb r2, [r3, #32] +1015:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_ERROR; + 821 .loc 1 1016 16 + 822 0056 0123 movs r3, #1 + 823 0058 12E0 b .L40 + 824 .L39: +1005:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 825 .loc 1 1005 17 + 826 005a 7B68 ldr r3, [r7, #4] + 827 005c 1B68 ldr r3, [r3] +1005:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 828 .loc 1 1005 27 + 829 005e 5B68 ldr r3, [r3, #4] +1005:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 830 .loc 1 1005 33 + 831 0060 03F00103 and r3, r3, #1 +1005:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 832 .loc 1 1005 49 + 833 0064 002B cmp r3, #0 + 834 0066 E5D1 bne .L41 +1017:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1018:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1019:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Reset the CAN ErrorCode */ +1021:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode = HAL_CAN_ERROR_NONE; + 835 .loc 1 1021 21 + 836 0068 7B68 ldr r3, [r7, #4] + 837 006a 0022 movs r2, #0 + 838 006c 5A62 str r2, [r3, #36] +1022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1023:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return function status */ +1024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_OK; + 839 .loc 1 1024 12 + 840 006e 0023 movs r3, #0 + 841 0070 06E0 b .L40 + 842 .L38: +1025:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else + ARM GAS /tmp/ccM1MpQr.s page 34 + + +1027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1028:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code */ +1029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY; + 843 .loc 1 1029 9 + 844 0072 7B68 ldr r3, [r7, #4] + 845 0074 5B6A ldr r3, [r3, #36] + 846 .loc 1 1029 21 + 847 0076 43F40022 orr r2, r3, #524288 + 848 007a 7B68 ldr r3, [r7, #4] + 849 007c 5A62 str r2, [r3, #36] +1030:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1031:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_ERROR; + 850 .loc 1 1031 12 + 851 007e 0123 movs r3, #1 + 852 .L40: +1032:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1033:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 853 .loc 1 1033 1 + 854 0080 1846 mov r0, r3 + 855 0082 1037 adds r7, r7, #16 + 856 .cfi_def_cfa_offset 8 + 857 0084 BD46 mov sp, r7 + 858 .cfi_def_cfa_register 13 + 859 @ sp needed + 860 0086 80BD pop {r7, pc} + 861 .cfi_endproc + 862 .LFE135: + 864 .section .text.HAL_CAN_Stop,"ax",%progbits + 865 .align 1 + 866 .global HAL_CAN_Stop + 867 .syntax unified + 868 .thumb + 869 .thumb_func + 871 HAL_CAN_Stop: + 872 .LFB136: +1034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1035:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +1036:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Stop the CAN module and enable access to configuration registers. +1037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to an CAN_HandleTypeDef structure that contains +1038:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +1039:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval HAL status +1040:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +1041:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan) +1042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 873 .loc 1 1042 1 + 874 .cfi_startproc + 875 @ args = 0, pretend = 0, frame = 16 + 876 @ frame_needed = 1, uses_anonymous_args = 0 + 877 0000 80B5 push {r7, lr} + 878 .cfi_def_cfa_offset 8 + 879 .cfi_offset 7, -8 + 880 .cfi_offset 14, -4 + 881 0002 84B0 sub sp, sp, #16 + 882 .cfi_def_cfa_offset 24 + 883 0004 00AF add r7, sp, #0 + 884 .cfi_def_cfa_register 7 + 885 0006 7860 str r0, [r7, #4] + ARM GAS /tmp/ccM1MpQr.s page 35 + + +1043:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t tickstart; +1044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1045:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (hcan->State == HAL_CAN_STATE_LISTENING) + 886 .loc 1 1045 11 + 887 0008 7B68 ldr r3, [r7, #4] + 888 000a 93F82030 ldrb r3, [r3, #32] + 889 000e DBB2 uxtb r3, r3 + 890 .loc 1 1045 6 + 891 0010 022B cmp r3, #2 + 892 0012 33D1 bne .L43 +1046:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Request initialisation */ +1048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); + 893 .loc 1 1048 5 + 894 0014 7B68 ldr r3, [r7, #4] + 895 0016 1B68 ldr r3, [r3] + 896 0018 1A68 ldr r2, [r3] + 897 001a 7B68 ldr r3, [r7, #4] + 898 001c 1B68 ldr r3, [r3] + 899 001e 42F00102 orr r2, r2, #1 + 900 0022 1A60 str r2, [r3] +1049:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1050:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Get tick */ +1051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** tickstart = HAL_GetTick(); + 901 .loc 1 1051 17 + 902 0024 FFF7FEFF bl HAL_GetTick + 903 0028 F860 str r0, [r7, #12] +1052:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Wait the acknowledge */ +1054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) + 904 .loc 1 1054 11 + 905 002a 12E0 b .L44 + 906 .L46: +1055:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check for the Timeout */ +1057:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + 907 .loc 1 1057 12 + 908 002c FFF7FEFF bl HAL_GetTick + 909 0030 0246 mov r2, r0 + 910 .loc 1 1057 26 discriminator 1 + 911 0032 FB68 ldr r3, [r7, #12] + 912 0034 D31A subs r3, r2, r3 + 913 .loc 1 1057 10 discriminator 1 + 914 0036 0A2B cmp r3, #10 + 915 0038 0BD9 bls .L44 +1058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code */ +1060:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + 916 .loc 1 1060 13 + 917 003a 7B68 ldr r3, [r7, #4] + 918 003c 5B6A ldr r3, [r3, #36] + 919 .loc 1 1060 25 + 920 003e 43F40032 orr r2, r3, #131072 + 921 0042 7B68 ldr r3, [r7, #4] + 922 0044 5A62 str r2, [r3, #36] +1061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1062:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Change CAN state */ + ARM GAS /tmp/ccM1MpQr.s page 36 + + +1063:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->State = HAL_CAN_STATE_ERROR; + 923 .loc 1 1063 21 + 924 0046 7B68 ldr r3, [r7, #4] + 925 0048 0522 movs r2, #5 + 926 004a 83F82020 strb r2, [r3, #32] +1064:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_ERROR; + 927 .loc 1 1065 16 + 928 004e 0123 movs r3, #1 + 929 0050 1BE0 b .L45 + 930 .L44: +1054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 931 .loc 1 1054 17 + 932 0052 7B68 ldr r3, [r7, #4] + 933 0054 1B68 ldr r3, [r3] +1054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 934 .loc 1 1054 27 + 935 0056 5B68 ldr r3, [r3, #4] +1054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 936 .loc 1 1054 33 + 937 0058 03F00103 and r3, r3, #1 +1054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 938 .loc 1 1054 49 + 939 005c 002B cmp r3, #0 + 940 005e E5D0 beq .L46 +1066:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1067:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1069:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Exit from sleep mode */ +1070:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + 941 .loc 1 1070 5 + 942 0060 7B68 ldr r3, [r7, #4] + 943 0062 1B68 ldr r3, [r3] + 944 0064 1A68 ldr r2, [r3] + 945 0066 7B68 ldr r3, [r7, #4] + 946 0068 1B68 ldr r3, [r3] + 947 006a 22F00202 bic r2, r2, #2 + 948 006e 1A60 str r2, [r3] +1071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1072:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Change CAN peripheral state */ +1073:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->State = HAL_CAN_STATE_READY; + 949 .loc 1 1073 17 + 950 0070 7B68 ldr r3, [r7, #4] + 951 0072 0122 movs r2, #1 + 952 0074 83F82020 strb r2, [r3, #32] +1074:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1075:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return function status */ +1076:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_OK; + 953 .loc 1 1076 12 + 954 0078 0023 movs r3, #0 + 955 007a 06E0 b .L45 + 956 .L43: +1077:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1078:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else +1079:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code */ +1081:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_NOT_STARTED; + ARM GAS /tmp/ccM1MpQr.s page 37 + + + 957 .loc 1 1081 9 + 958 007c 7B68 ldr r3, [r7, #4] + 959 007e 5B6A ldr r3, [r3, #36] + 960 .loc 1 1081 21 + 961 0080 43F48012 orr r2, r3, #1048576 + 962 0084 7B68 ldr r3, [r7, #4] + 963 0086 5A62 str r2, [r3, #36] +1082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_ERROR; + 964 .loc 1 1083 12 + 965 0088 0123 movs r3, #1 + 966 .L45: +1084:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 967 .loc 1 1085 1 + 968 008a 1846 mov r0, r3 + 969 008c 1037 adds r7, r7, #16 + 970 .cfi_def_cfa_offset 8 + 971 008e BD46 mov sp, r7 + 972 .cfi_def_cfa_register 13 + 973 @ sp needed + 974 0090 80BD pop {r7, pc} + 975 .cfi_endproc + 976 .LFE136: + 978 .section .text.HAL_CAN_RequestSleep,"ax",%progbits + 979 .align 1 + 980 .global HAL_CAN_RequestSleep + 981 .syntax unified + 982 .thumb + 983 .thumb_func + 985 HAL_CAN_RequestSleep: + 986 .LFB137: +1086:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1087:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +1088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Request the sleep mode (low power) entry. +1089:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * When returning from this function, Sleep mode will be entered +1090:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * as soon as the current CAN activity (transmission or reception +1091:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * of a CAN frame) has been completed. +1092:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains +1093:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +1094:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval HAL status. +1095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +1096:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan) +1097:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 987 .loc 1 1097 1 + 988 .cfi_startproc + 989 @ args = 0, pretend = 0, frame = 16 + 990 @ frame_needed = 1, uses_anonymous_args = 0 + 991 @ link register save eliminated. + 992 0000 80B4 push {r7} + 993 .cfi_def_cfa_offset 4 + 994 .cfi_offset 7, -4 + 995 0002 85B0 sub sp, sp, #20 + 996 .cfi_def_cfa_offset 24 + 997 0004 00AF add r7, sp, #0 + 998 .cfi_def_cfa_register 7 + 999 0006 7860 str r0, [r7, #4] + ARM GAS /tmp/ccM1MpQr.s page 38 + + +1098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_StateTypeDef state = hcan->State; + 1000 .loc 1 1098 24 + 1001 0008 7B68 ldr r3, [r7, #4] + 1002 000a 93F82030 ldrb r3, [r3, #32] + 1003 000e FB73 strb r3, [r7, #15] +1099:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((state == HAL_CAN_STATE_READY) || + 1004 .loc 1 1100 6 + 1005 0010 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 1006 0012 012B cmp r3, #1 + 1007 0014 02D0 beq .L48 + 1008 .loc 1 1100 38 discriminator 1 + 1009 0016 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 1010 0018 022B cmp r3, #2 + 1011 001a 09D1 bne .L49 + 1012 .L48: +1101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (state == HAL_CAN_STATE_LISTENING)) +1102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Request Sleep mode */ +1104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** SET_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + 1013 .loc 1 1104 5 + 1014 001c 7B68 ldr r3, [r7, #4] + 1015 001e 1B68 ldr r3, [r3] + 1016 0020 1A68 ldr r2, [r3] + 1017 0022 7B68 ldr r3, [r7, #4] + 1018 0024 1B68 ldr r3, [r3] + 1019 0026 42F00202 orr r2, r2, #2 + 1020 002a 1A60 str r2, [r3] +1105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return function status */ +1107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_OK; + 1021 .loc 1 1107 12 + 1022 002c 0023 movs r3, #0 + 1023 002e 06E0 b .L50 + 1024 .L49: +1108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else +1110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code */ +1112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + 1025 .loc 1 1112 9 + 1026 0030 7B68 ldr r3, [r7, #4] + 1027 0032 5B6A ldr r3, [r3, #36] + 1028 .loc 1 1112 21 + 1029 0034 43F48022 orr r2, r3, #262144 + 1030 0038 7B68 ldr r3, [r7, #4] + 1031 003a 5A62 str r2, [r3, #36] +1113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return function status */ +1115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_ERROR; + 1032 .loc 1 1115 12 + 1033 003c 0123 movs r3, #1 + 1034 .L50: +1116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1035 .loc 1 1117 1 + 1036 003e 1846 mov r0, r3 + ARM GAS /tmp/ccM1MpQr.s page 39 + + + 1037 0040 1437 adds r7, r7, #20 + 1038 .cfi_def_cfa_offset 4 + 1039 0042 BD46 mov sp, r7 + 1040 .cfi_def_cfa_register 13 + 1041 @ sp needed + 1042 0044 5DF8047B ldr r7, [sp], #4 + 1043 .cfi_restore 7 + 1044 .cfi_def_cfa_offset 0 + 1045 0048 7047 bx lr + 1046 .cfi_endproc + 1047 .LFE137: + 1049 .section .text.HAL_CAN_WakeUp,"ax",%progbits + 1050 .align 1 + 1051 .global HAL_CAN_WakeUp + 1052 .syntax unified + 1053 .thumb + 1054 .thumb_func + 1056 HAL_CAN_WakeUp: + 1057 .LFB138: +1118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +1120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Wake up from sleep mode. +1121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * When returning with HAL_OK status from this function, Sleep mode +1122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * is exited. +1123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains +1124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +1125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval HAL status. +1126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +1127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan) +1128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 1058 .loc 1 1128 1 + 1059 .cfi_startproc + 1060 @ args = 0, pretend = 0, frame = 24 + 1061 @ frame_needed = 1, uses_anonymous_args = 0 + 1062 @ link register save eliminated. + 1063 0000 80B4 push {r7} + 1064 .cfi_def_cfa_offset 4 + 1065 .cfi_offset 7, -4 + 1066 0002 87B0 sub sp, sp, #28 + 1067 .cfi_def_cfa_offset 32 + 1068 0004 00AF add r7, sp, #0 + 1069 .cfi_def_cfa_register 7 + 1070 0006 7860 str r0, [r7, #4] +1129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __IO uint32_t count = 0; + 1071 .loc 1 1129 17 + 1072 0008 0023 movs r3, #0 + 1073 000a FB60 str r3, [r7, #12] +1130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t timeout = 1000000U; + 1074 .loc 1 1130 12 + 1075 000c 1C4B ldr r3, .L57 + 1076 000e 7B61 str r3, [r7, #20] +1131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_StateTypeDef state = hcan->State; + 1077 .loc 1 1131 24 + 1078 0010 7B68 ldr r3, [r7, #4] + 1079 0012 93F82030 ldrb r3, [r3, #32] + 1080 0016 FB74 strb r3, [r7, #19] +1132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + ARM GAS /tmp/ccM1MpQr.s page 40 + + +1133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((state == HAL_CAN_STATE_READY) || + 1081 .loc 1 1133 6 + 1082 0018 FB7C ldrb r3, [r7, #19] @ zero_extendqisi2 + 1083 001a 012B cmp r3, #1 + 1084 001c 02D0 beq .L52 + 1085 .loc 1 1133 38 discriminator 1 + 1086 001e FB7C ldrb r3, [r7, #19] @ zero_extendqisi2 + 1087 0020 022B cmp r3, #2 + 1088 0022 1FD1 bne .L53 + 1089 .L52: +1134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (state == HAL_CAN_STATE_LISTENING)) +1135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Wake up request */ +1137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + 1090 .loc 1 1137 5 + 1091 0024 7B68 ldr r3, [r7, #4] + 1092 0026 1B68 ldr r3, [r3] + 1093 0028 1A68 ldr r2, [r3] + 1094 002a 7B68 ldr r3, [r7, #4] + 1095 002c 1B68 ldr r3, [r3] + 1096 002e 22F00202 bic r2, r2, #2 + 1097 0032 1A60 str r2, [r3] + 1098 .L56: +1138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Wait sleep mode is exited */ +1140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** do +1141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Increment counter */ +1143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** count++; + 1099 .loc 1 1143 12 + 1100 0034 FB68 ldr r3, [r7, #12] + 1101 0036 0133 adds r3, r3, #1 + 1102 0038 FB60 str r3, [r7, #12] +1144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check if timeout is reached */ +1146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (count > timeout) + 1103 .loc 1 1146 17 + 1104 003a FB68 ldr r3, [r7, #12] + 1105 .loc 1 1146 10 + 1106 003c 7A69 ldr r2, [r7, #20] + 1107 003e 9A42 cmp r2, r3 + 1108 0040 07D2 bcs .L54 +1147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code */ +1149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + 1109 .loc 1 1149 13 + 1110 0042 7B68 ldr r3, [r7, #4] + 1111 0044 5B6A ldr r3, [r3, #36] + 1112 .loc 1 1149 25 + 1113 0046 43F40032 orr r2, r3, #131072 + 1114 004a 7B68 ldr r3, [r7, #4] + 1115 004c 5A62 str r2, [r3, #36] +1150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_ERROR; + 1116 .loc 1 1151 16 + 1117 004e 0123 movs r3, #1 + 1118 0050 0FE0 b .L55 + ARM GAS /tmp/ccM1MpQr.s page 41 + + + 1119 .L54: +1152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U); + 1120 .loc 1 1154 17 + 1121 0052 7B68 ldr r3, [r7, #4] + 1122 0054 1B68 ldr r3, [r3] + 1123 .loc 1 1154 27 + 1124 0056 5B68 ldr r3, [r3, #4] + 1125 .loc 1 1154 33 + 1126 0058 03F00203 and r3, r3, #2 + 1127 .loc 1 1154 49 + 1128 005c 002B cmp r3, #0 + 1129 005e E9D1 bne .L56 +1155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return function status */ +1157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_OK; + 1130 .loc 1 1157 12 + 1131 0060 0023 movs r3, #0 + 1132 0062 06E0 b .L55 + 1133 .L53: +1158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else +1160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code */ +1162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + 1134 .loc 1 1162 9 + 1135 0064 7B68 ldr r3, [r7, #4] + 1136 0066 5B6A ldr r3, [r3, #36] + 1137 .loc 1 1162 21 + 1138 0068 43F48022 orr r2, r3, #262144 + 1139 006c 7B68 ldr r3, [r7, #4] + 1140 006e 5A62 str r2, [r3, #36] +1163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_ERROR; + 1141 .loc 1 1164 12 + 1142 0070 0123 movs r3, #1 + 1143 .L55: +1165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1144 .loc 1 1166 1 + 1145 0072 1846 mov r0, r3 + 1146 0074 1C37 adds r7, r7, #28 + 1147 .cfi_def_cfa_offset 4 + 1148 0076 BD46 mov sp, r7 + 1149 .cfi_def_cfa_register 13 + 1150 @ sp needed + 1151 0078 5DF8047B ldr r7, [sp], #4 + 1152 .cfi_restore 7 + 1153 .cfi_def_cfa_offset 0 + 1154 007c 7047 bx lr + 1155 .L58: + 1156 007e 00BF .align 2 + 1157 .L57: + 1158 0080 40420F00 .word 1000000 + 1159 .cfi_endproc + 1160 .LFE138: + ARM GAS /tmp/ccM1MpQr.s page 42 + + + 1162 .section .text.HAL_CAN_IsSleepActive,"ax",%progbits + 1163 .align 1 + 1164 .global HAL_CAN_IsSleepActive + 1165 .syntax unified + 1166 .thumb + 1167 .thumb_func + 1169 HAL_CAN_IsSleepActive: + 1170 .LFB139: +1167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +1169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Check is sleep mode is active. +1170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains +1171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +1172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval Status +1173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * - 0 : Sleep mode is not active. +1174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * - 1 : Sleep mode is active. +1175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +1176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t HAL_CAN_IsSleepActive(const CAN_HandleTypeDef *hcan) +1177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 1171 .loc 1 1177 1 + 1172 .cfi_startproc + 1173 @ args = 0, pretend = 0, frame = 16 + 1174 @ frame_needed = 1, uses_anonymous_args = 0 + 1175 @ link register save eliminated. + 1176 0000 80B4 push {r7} + 1177 .cfi_def_cfa_offset 4 + 1178 .cfi_offset 7, -4 + 1179 0002 85B0 sub sp, sp, #20 + 1180 .cfi_def_cfa_offset 24 + 1181 0004 00AF add r7, sp, #0 + 1182 .cfi_def_cfa_register 7 + 1183 0006 7860 str r0, [r7, #4] +1178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t status = 0U; + 1184 .loc 1 1178 12 + 1185 0008 0023 movs r3, #0 + 1186 000a FB60 str r3, [r7, #12] +1179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_StateTypeDef state = hcan->State; + 1187 .loc 1 1179 24 + 1188 000c 7B68 ldr r3, [r7, #4] + 1189 000e 93F82030 ldrb r3, [r3, #32] + 1190 0012 FB72 strb r3, [r7, #11] +1180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((state == HAL_CAN_STATE_READY) || + 1191 .loc 1 1181 6 + 1192 0014 FB7A ldrb r3, [r7, #11] @ zero_extendqisi2 + 1193 0016 012B cmp r3, #1 + 1194 0018 02D0 beq .L60 + 1195 .loc 1 1181 38 discriminator 1 + 1196 001a FB7A ldrb r3, [r7, #11] @ zero_extendqisi2 + 1197 001c 022B cmp r3, #2 + 1198 001e 08D1 bne .L61 + 1199 .L60: +1182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (state == HAL_CAN_STATE_LISTENING)) +1183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check Sleep mode */ +1185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) + 1200 .loc 1 1185 14 + ARM GAS /tmp/ccM1MpQr.s page 43 + + + 1201 0020 7B68 ldr r3, [r7, #4] + 1202 0022 1B68 ldr r3, [r3] + 1203 .loc 1 1185 24 + 1204 0024 5B68 ldr r3, [r3, #4] + 1205 .loc 1 1185 30 + 1206 0026 03F00203 and r3, r3, #2 + 1207 .loc 1 1185 8 + 1208 002a 002B cmp r3, #0 + 1209 002c 01D0 beq .L61 +1186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** status = 1U; + 1210 .loc 1 1187 14 + 1211 002e 0123 movs r3, #1 + 1212 0030 FB60 str r3, [r7, #12] + 1213 .L61: +1188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return function status */ +1192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return status; + 1214 .loc 1 1192 10 + 1215 0032 FB68 ldr r3, [r7, #12] +1193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1216 .loc 1 1193 1 + 1217 0034 1846 mov r0, r3 + 1218 0036 1437 adds r7, r7, #20 + 1219 .cfi_def_cfa_offset 4 + 1220 0038 BD46 mov sp, r7 + 1221 .cfi_def_cfa_register 13 + 1222 @ sp needed + 1223 003a 5DF8047B ldr r7, [sp], #4 + 1224 .cfi_restore 7 + 1225 .cfi_def_cfa_offset 0 + 1226 003e 7047 bx lr + 1227 .cfi_endproc + 1228 .LFE139: + 1230 .section .text.HAL_CAN_AddTxMessage,"ax",%progbits + 1231 .align 1 + 1232 .global HAL_CAN_AddTxMessage + 1233 .syntax unified + 1234 .thumb + 1235 .thumb_func + 1237 HAL_CAN_AddTxMessage: + 1238 .LFB140: +1194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +1196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Add a message to the first free Tx mailbox and activate the +1197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * corresponding transmission request. +1198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains +1199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +1200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param pHeader pointer to a CAN_TxHeaderTypeDef structure. +1201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param aData array containing the payload of the Tx frame. +1202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param pTxMailbox pointer to a variable where the function will return +1203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the TxMailbox used to store the Tx message. +1204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * This parameter can be a value of @arg CAN_Tx_Mailboxes. +1205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval HAL status +1206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ + ARM GAS /tmp/ccM1MpQr.s page 44 + + +1207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, const CAN_TxHeaderTypeDef *pHeader, +1208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** const uint8_t aData[], uint32_t *pTxMailbox) +1209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 1239 .loc 1 1209 1 + 1240 .cfi_startproc + 1241 @ args = 0, pretend = 0, frame = 32 + 1242 @ frame_needed = 1, uses_anonymous_args = 0 + 1243 @ link register save eliminated. + 1244 0000 80B4 push {r7} + 1245 .cfi_def_cfa_offset 4 + 1246 .cfi_offset 7, -4 + 1247 0002 89B0 sub sp, sp, #36 + 1248 .cfi_def_cfa_offset 40 + 1249 0004 00AF add r7, sp, #0 + 1250 .cfi_def_cfa_register 7 + 1251 0006 F860 str r0, [r7, #12] + 1252 0008 B960 str r1, [r7, #8] + 1253 000a 7A60 str r2, [r7, #4] + 1254 000c 3B60 str r3, [r7] +1210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t transmitmailbox; +1211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_StateTypeDef state = hcan->State; + 1255 .loc 1 1211 24 + 1256 000e FB68 ldr r3, [r7, #12] + 1257 0010 93F82030 ldrb r3, [r3, #32] + 1258 0014 FB77 strb r3, [r7, #31] +1212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t tsr = READ_REG(hcan->Instance->TSR); + 1259 .loc 1 1212 18 + 1260 0016 FB68 ldr r3, [r7, #12] + 1261 0018 1B68 ldr r3, [r3] + 1262 .loc 1 1212 12 + 1263 001a 9B68 ldr r3, [r3, #8] + 1264 001c BB61 str r3, [r7, #24] +1213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check the parameters */ +1215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_IDTYPE(pHeader->IDE)); +1216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_RTR(pHeader->RTR)); +1217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_DLC(pHeader->DLC)); +1218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (pHeader->IDE == CAN_ID_STD) +1219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_STDID(pHeader->StdId)); +1221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else +1223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_EXTID(pHeader->ExtId)); +1225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime)); +1227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((state == HAL_CAN_STATE_READY) || + 1265 .loc 1 1228 6 + 1266 001e FB7F ldrb r3, [r7, #31] @ zero_extendqisi2 + 1267 0020 012B cmp r3, #1 + 1268 0022 03D0 beq .L64 + 1269 .loc 1 1228 38 discriminator 1 + 1270 0024 FB7F ldrb r3, [r7, #31] @ zero_extendqisi2 + 1271 0026 022B cmp r3, #2 + 1272 0028 40F0AD80 bne .L65 + 1273 .L64: + ARM GAS /tmp/ccM1MpQr.s page 45 + + +1229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (state == HAL_CAN_STATE_LISTENING)) +1230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check that all the Tx mailboxes are not full */ +1232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (((tsr & CAN_TSR_TME0) != 0U) || + 1274 .loc 1 1232 15 + 1275 002c BB69 ldr r3, [r7, #24] + 1276 002e 03F08063 and r3, r3, #67108864 + 1277 .loc 1 1232 8 + 1278 0032 002B cmp r3, #0 + 1279 0034 0AD1 bne .L66 +1233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((tsr & CAN_TSR_TME1) != 0U) || + 1280 .loc 1 1233 15 + 1281 0036 BB69 ldr r3, [r7, #24] + 1282 0038 03F00063 and r3, r3, #134217728 +1232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((tsr & CAN_TSR_TME1) != 0U) || + 1283 .loc 1 1232 38 discriminator 1 + 1284 003c 002B cmp r3, #0 + 1285 003e 05D1 bne .L66 +1234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((tsr & CAN_TSR_TME2) != 0U)) + 1286 .loc 1 1234 15 + 1287 0040 BB69 ldr r3, [r7, #24] + 1288 0042 03F08053 and r3, r3, #268435456 +1233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((tsr & CAN_TSR_TME1) != 0U) || + 1289 .loc 1 1233 38 + 1290 0046 002B cmp r3, #0 + 1291 0048 00F09580 beq .L67 + 1292 .L66: +1235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Select an empty transmit mailbox */ +1237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos; + 1293 .loc 1 1237 46 + 1294 004c BB69 ldr r3, [r7, #24] + 1295 004e 1B0E lsrs r3, r3, #24 + 1296 .loc 1 1237 23 + 1297 0050 03F00303 and r3, r3, #3 + 1298 0054 7B61 str r3, [r7, #20] +1238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Store the Tx mailbox */ +1240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** *pTxMailbox = (uint32_t)1 << transmitmailbox; + 1299 .loc 1 1240 33 + 1300 0056 0122 movs r2, #1 + 1301 0058 7B69 ldr r3, [r7, #20] + 1302 005a 9A40 lsls r2, r2, r3 + 1303 .loc 1 1240 19 + 1304 005c 3B68 ldr r3, [r7] + 1305 005e 1A60 str r2, [r3] +1241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Set up the Id */ +1243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (pHeader->IDE == CAN_ID_STD) + 1306 .loc 1 1243 18 + 1307 0060 BB68 ldr r3, [r7, #8] + 1308 0062 9B68 ldr r3, [r3, #8] + 1309 .loc 1 1243 10 + 1310 0064 002B cmp r3, #0 + 1311 0066 0DD1 bne .L68 +1244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | + ARM GAS /tmp/ccM1MpQr.s page 46 + + + 1312 .loc 1 1245 68 + 1313 0068 BB68 ldr r3, [r7, #8] + 1314 006a 1B68 ldr r3, [r3] + 1315 .loc 1 1245 76 + 1316 006c 5A05 lsls r2, r3, #21 +1246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** pHeader->RTR); + 1317 .loc 1 1246 67 + 1318 006e BB68 ldr r3, [r7, #8] + 1319 0070 DB68 ldr r3, [r3, #12] +1245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** pHeader->RTR); + 1320 .loc 1 1245 13 + 1321 0072 F968 ldr r1, [r7, #12] + 1322 0074 0968 ldr r1, [r1] +1245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** pHeader->RTR); + 1323 .loc 1 1245 98 + 1324 0076 1A43 orrs r2, r2, r3 +1245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** pHeader->RTR); + 1325 .loc 1 1245 57 + 1326 0078 7B69 ldr r3, [r7, #20] + 1327 007a 1833 adds r3, r3, #24 + 1328 007c 1B01 lsls r3, r3, #4 + 1329 007e 0B44 add r3, r3, r1 + 1330 0080 1A60 str r2, [r3] + 1331 0082 0FE0 b .L69 + 1332 .L68: +1247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else +1249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | + 1333 .loc 1 1250 68 + 1334 0084 BB68 ldr r3, [r7, #8] + 1335 0086 5B68 ldr r3, [r3, #4] + 1336 .loc 1 1250 76 + 1337 0088 DA00 lsls r2, r3, #3 +1251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** pHeader->IDE | + 1338 .loc 1 1251 67 + 1339 008a BB68 ldr r3, [r7, #8] + 1340 008c 9B68 ldr r3, [r3, #8] +1250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** pHeader->IDE | + 1341 .loc 1 1250 98 + 1342 008e 1A43 orrs r2, r2, r3 +1252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** pHeader->RTR); + 1343 .loc 1 1252 67 + 1344 0090 BB68 ldr r3, [r7, #8] + 1345 0092 DB68 ldr r3, [r3, #12] +1250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** pHeader->IDE | + 1346 .loc 1 1250 13 + 1347 0094 F968 ldr r1, [r7, #12] + 1348 0096 0968 ldr r1, [r1] +1251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** pHeader->IDE | + 1349 .loc 1 1251 73 + 1350 0098 1A43 orrs r2, r2, r3 +1250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** pHeader->IDE | + 1351 .loc 1 1250 57 + 1352 009a 7B69 ldr r3, [r7, #20] + 1353 009c 1833 adds r3, r3, #24 + 1354 009e 1B01 lsls r3, r3, #4 + ARM GAS /tmp/ccM1MpQr.s page 47 + + + 1355 00a0 0B44 add r3, r3, r1 + 1356 00a2 1A60 str r2, [r3] + 1357 .L69: +1253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Set up the DLC */ +1256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC); + 1358 .loc 1 1256 11 + 1359 00a4 FB68 ldr r3, [r7, #12] + 1360 00a6 1968 ldr r1, [r3] + 1361 .loc 1 1256 66 + 1362 00a8 BB68 ldr r3, [r7, #8] + 1363 00aa 1A69 ldr r2, [r3, #16] + 1364 .loc 1 1256 56 + 1365 00ac 7B69 ldr r3, [r7, #20] + 1366 00ae 1833 adds r3, r3, #24 + 1367 00b0 1B01 lsls r3, r3, #4 + 1368 00b2 0B44 add r3, r3, r1 + 1369 00b4 0433 adds r3, r3, #4 + 1370 00b6 1A60 str r2, [r3] +1257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Set up the Transmit Global Time mode */ +1259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (pHeader->TransmitGlobalTime == ENABLE) + 1371 .loc 1 1259 18 + 1372 00b8 BB68 ldr r3, [r7, #8] + 1373 00ba 1B7D ldrb r3, [r3, #20] @ zero_extendqisi2 + 1374 .loc 1 1259 10 + 1375 00bc 012B cmp r3, #1 + 1376 00be 11D1 bne .L70 +1260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT); + 1377 .loc 1 1261 9 + 1378 00c0 FB68 ldr r3, [r7, #12] + 1379 00c2 1A68 ldr r2, [r3] + 1380 00c4 7B69 ldr r3, [r7, #20] + 1381 00c6 1833 adds r3, r3, #24 + 1382 00c8 1B01 lsls r3, r3, #4 + 1383 00ca 1344 add r3, r3, r2 + 1384 00cc 0433 adds r3, r3, #4 + 1385 00ce 1B68 ldr r3, [r3] + 1386 00d0 FA68 ldr r2, [r7, #12] + 1387 00d2 1168 ldr r1, [r2] + 1388 00d4 43F48072 orr r2, r3, #256 + 1389 00d8 7B69 ldr r3, [r7, #20] + 1390 00da 1833 adds r3, r3, #24 + 1391 00dc 1B01 lsls r3, r3, #4 + 1392 00de 0B44 add r3, r3, r1 + 1393 00e0 0433 adds r3, r3, #4 + 1394 00e2 1A60 str r2, [r3] + 1395 .L70: +1262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Set up the data field */ +1265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, + 1396 .loc 1 1265 7 + 1397 00e4 7B68 ldr r3, [r7, #4] + 1398 00e6 0733 adds r3, r3, #7 + ARM GAS /tmp/ccM1MpQr.s page 48 + + + 1399 00e8 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 1400 00ea 1A06 lsls r2, r3, #24 + 1401 00ec 7B68 ldr r3, [r7, #4] + 1402 00ee 0633 adds r3, r3, #6 + 1403 00f0 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 1404 00f2 1B04 lsls r3, r3, #16 + 1405 00f4 1A43 orrs r2, r2, r3 + 1406 00f6 7B68 ldr r3, [r7, #4] + 1407 00f8 0533 adds r3, r3, #5 + 1408 00fa 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 1409 00fc 1B02 lsls r3, r3, #8 + 1410 00fe 1343 orrs r3, r3, r2 + 1411 0100 7A68 ldr r2, [r7, #4] + 1412 0102 0432 adds r2, r2, #4 + 1413 0104 1278 ldrb r2, [r2] @ zero_extendqisi2 + 1414 0106 1046 mov r0, r2 + 1415 0108 FA68 ldr r2, [r7, #12] + 1416 010a 1168 ldr r1, [r2] + 1417 010c 43EA0002 orr r2, r3, r0 + 1418 0110 7B69 ldr r3, [r7, #20] + 1419 0112 1B01 lsls r3, r3, #4 + 1420 0114 0B44 add r3, r3, r1 + 1421 0116 03F5C673 add r3, r3, #396 + 1422 011a 1A60 str r2, [r3] +1266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) | +1267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) | +1268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) | +1269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos)); +1270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, + 1423 .loc 1 1270 7 + 1424 011c 7B68 ldr r3, [r7, #4] + 1425 011e 0333 adds r3, r3, #3 + 1426 0120 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 1427 0122 1A06 lsls r2, r3, #24 + 1428 0124 7B68 ldr r3, [r7, #4] + 1429 0126 0233 adds r3, r3, #2 + 1430 0128 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 1431 012a 1B04 lsls r3, r3, #16 + 1432 012c 1A43 orrs r2, r2, r3 + 1433 012e 7B68 ldr r3, [r7, #4] + 1434 0130 0133 adds r3, r3, #1 + 1435 0132 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 1436 0134 1B02 lsls r3, r3, #8 + 1437 0136 1343 orrs r3, r3, r2 + 1438 0138 7A68 ldr r2, [r7, #4] + 1439 013a 1278 ldrb r2, [r2] @ zero_extendqisi2 + 1440 013c 1046 mov r0, r2 + 1441 013e FA68 ldr r2, [r7, #12] + 1442 0140 1168 ldr r1, [r2] + 1443 0142 43EA0002 orr r2, r3, r0 + 1444 0146 7B69 ldr r3, [r7, #20] + 1445 0148 1B01 lsls r3, r3, #4 + 1446 014a 0B44 add r3, r3, r1 + 1447 014c 03F5C473 add r3, r3, #392 + 1448 0150 1A60 str r2, [r3] +1271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((uint32_t)aData[3] << CAN_TDL0R_DATA3_Pos) | +1272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) | + ARM GAS /tmp/ccM1MpQr.s page 49 + + +1273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) | +1274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos)); +1275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Request transmission */ +1277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ); + 1449 .loc 1 1277 7 + 1450 0152 FB68 ldr r3, [r7, #12] + 1451 0154 1A68 ldr r2, [r3] + 1452 0156 7B69 ldr r3, [r7, #20] + 1453 0158 1833 adds r3, r3, #24 + 1454 015a 1B01 lsls r3, r3, #4 + 1455 015c 1344 add r3, r3, r2 + 1456 015e 1B68 ldr r3, [r3] + 1457 0160 FA68 ldr r2, [r7, #12] + 1458 0162 1168 ldr r1, [r2] + 1459 0164 43F00102 orr r2, r3, #1 + 1460 0168 7B69 ldr r3, [r7, #20] + 1461 016a 1833 adds r3, r3, #24 + 1462 016c 1B01 lsls r3, r3, #4 + 1463 016e 0B44 add r3, r3, r1 + 1464 0170 1A60 str r2, [r3] +1278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return function status */ +1280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_OK; + 1465 .loc 1 1280 14 + 1466 0172 0023 movs r3, #0 + 1467 0174 0EE0 b .L71 + 1468 .L67: +1281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else +1283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code */ +1285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + 1469 .loc 1 1285 11 + 1470 0176 FB68 ldr r3, [r7, #12] + 1471 0178 5B6A ldr r3, [r3, #36] + 1472 .loc 1 1285 23 + 1473 017a 43F40012 orr r2, r3, #2097152 + 1474 017e FB68 ldr r3, [r7, #12] + 1475 0180 5A62 str r2, [r3, #36] +1286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_ERROR; + 1476 .loc 1 1287 14 + 1477 0182 0123 movs r3, #1 + 1478 0184 06E0 b .L71 + 1479 .L65: +1288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else +1291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code */ +1293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + 1480 .loc 1 1293 9 + 1481 0186 FB68 ldr r3, [r7, #12] + 1482 0188 5B6A ldr r3, [r3, #36] + 1483 .loc 1 1293 21 + 1484 018a 43F48022 orr r2, r3, #262144 + ARM GAS /tmp/ccM1MpQr.s page 50 + + + 1485 018e FB68 ldr r3, [r7, #12] + 1486 0190 5A62 str r2, [r3, #36] +1294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_ERROR; + 1487 .loc 1 1295 12 + 1488 0192 0123 movs r3, #1 + 1489 .L71: +1296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1490 .loc 1 1297 1 + 1491 0194 1846 mov r0, r3 + 1492 0196 2437 adds r7, r7, #36 + 1493 .cfi_def_cfa_offset 4 + 1494 0198 BD46 mov sp, r7 + 1495 .cfi_def_cfa_register 13 + 1496 @ sp needed + 1497 019a 5DF8047B ldr r7, [sp], #4 + 1498 .cfi_restore 7 + 1499 .cfi_def_cfa_offset 0 + 1500 019e 7047 bx lr + 1501 .cfi_endproc + 1502 .LFE140: + 1504 .section .text.HAL_CAN_AbortTxRequest,"ax",%progbits + 1505 .align 1 + 1506 .global HAL_CAN_AbortTxRequest + 1507 .syntax unified + 1508 .thumb + 1509 .thumb_func + 1511 HAL_CAN_AbortTxRequest: + 1512 .LFB141: +1298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +1300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Abort transmission requests +1301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to an CAN_HandleTypeDef structure that contains +1302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +1303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param TxMailboxes List of the Tx Mailboxes to abort. +1304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * This parameter can be any combination of @arg CAN_Tx_Mailboxes. +1305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval HAL status +1306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +1307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes) +1308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 1513 .loc 1 1308 1 + 1514 .cfi_startproc + 1515 @ args = 0, pretend = 0, frame = 16 + 1516 @ frame_needed = 1, uses_anonymous_args = 0 + 1517 @ link register save eliminated. + 1518 0000 80B4 push {r7} + 1519 .cfi_def_cfa_offset 4 + 1520 .cfi_offset 7, -4 + 1521 0002 85B0 sub sp, sp, #20 + 1522 .cfi_def_cfa_offset 24 + 1523 0004 00AF add r7, sp, #0 + 1524 .cfi_def_cfa_register 7 + 1525 0006 7860 str r0, [r7, #4] + 1526 0008 3960 str r1, [r7] +1309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_StateTypeDef state = hcan->State; + 1527 .loc 1 1309 24 + ARM GAS /tmp/ccM1MpQr.s page 51 + + + 1528 000a 7B68 ldr r3, [r7, #4] + 1529 000c 93F82030 ldrb r3, [r3, #32] + 1530 0010 FB73 strb r3, [r7, #15] +1310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check function parameters */ +1312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes)); +1313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((state == HAL_CAN_STATE_READY) || + 1531 .loc 1 1314 6 + 1532 0012 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 1533 0014 012B cmp r3, #1 + 1534 0016 02D0 beq .L73 + 1535 .loc 1 1314 38 discriminator 1 + 1536 0018 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 1537 001a 022B cmp r3, #2 + 1538 001c 28D1 bne .L74 + 1539 .L73: +1315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (state == HAL_CAN_STATE_LISTENING)) +1316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check Tx Mailbox 0 */ +1318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((TxMailboxes & CAN_TX_MAILBOX0) != 0U) + 1540 .loc 1 1318 22 + 1541 001e 3B68 ldr r3, [r7] + 1542 0020 03F00103 and r3, r3, #1 + 1543 .loc 1 1318 8 + 1544 0024 002B cmp r3, #0 + 1545 0026 07D0 beq .L75 +1319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Add cancellation request for Tx Mailbox 0 */ +1321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ0); + 1546 .loc 1 1321 7 + 1547 0028 7B68 ldr r3, [r7, #4] + 1548 002a 1B68 ldr r3, [r3] + 1549 002c 9A68 ldr r2, [r3, #8] + 1550 002e 7B68 ldr r3, [r7, #4] + 1551 0030 1B68 ldr r3, [r3] + 1552 0032 42F08002 orr r2, r2, #128 + 1553 0036 9A60 str r2, [r3, #8] + 1554 .L75: +1322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check Tx Mailbox 1 */ +1325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((TxMailboxes & CAN_TX_MAILBOX1) != 0U) + 1555 .loc 1 1325 22 + 1556 0038 3B68 ldr r3, [r7] + 1557 003a 03F00203 and r3, r3, #2 + 1558 .loc 1 1325 8 + 1559 003e 002B cmp r3, #0 + 1560 0040 07D0 beq .L76 +1326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Add cancellation request for Tx Mailbox 1 */ +1328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ1); + 1561 .loc 1 1328 7 + 1562 0042 7B68 ldr r3, [r7, #4] + 1563 0044 1B68 ldr r3, [r3] + 1564 0046 9A68 ldr r2, [r3, #8] + 1565 0048 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/ccM1MpQr.s page 52 + + + 1566 004a 1B68 ldr r3, [r3] + 1567 004c 42F40042 orr r2, r2, #32768 + 1568 0050 9A60 str r2, [r3, #8] + 1569 .L76: +1329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check Tx Mailbox 2 */ +1332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((TxMailboxes & CAN_TX_MAILBOX2) != 0U) + 1570 .loc 1 1332 22 + 1571 0052 3B68 ldr r3, [r7] + 1572 0054 03F00403 and r3, r3, #4 + 1573 .loc 1 1332 8 + 1574 0058 002B cmp r3, #0 + 1575 005a 07D0 beq .L77 +1333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Add cancellation request for Tx Mailbox 2 */ +1335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ2); + 1576 .loc 1 1335 7 + 1577 005c 7B68 ldr r3, [r7, #4] + 1578 005e 1B68 ldr r3, [r3] + 1579 0060 9A68 ldr r2, [r3, #8] + 1580 0062 7B68 ldr r3, [r7, #4] + 1581 0064 1B68 ldr r3, [r3] + 1582 0066 42F40002 orr r2, r2, #8388608 + 1583 006a 9A60 str r2, [r3, #8] + 1584 .L77: +1336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return function status */ +1339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_OK; + 1585 .loc 1 1339 12 + 1586 006c 0023 movs r3, #0 + 1587 006e 06E0 b .L78 + 1588 .L74: +1340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else +1342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code */ +1344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + 1589 .loc 1 1344 9 + 1590 0070 7B68 ldr r3, [r7, #4] + 1591 0072 5B6A ldr r3, [r3, #36] + 1592 .loc 1 1344 21 + 1593 0074 43F48022 orr r2, r3, #262144 + 1594 0078 7B68 ldr r3, [r7, #4] + 1595 007a 5A62 str r2, [r3, #36] +1345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_ERROR; + 1596 .loc 1 1346 12 + 1597 007c 0123 movs r3, #1 + 1598 .L78: +1347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1599 .loc 1 1348 1 + 1600 007e 1846 mov r0, r3 + 1601 0080 1437 adds r7, r7, #20 + 1602 .cfi_def_cfa_offset 4 + ARM GAS /tmp/ccM1MpQr.s page 53 + + + 1603 0082 BD46 mov sp, r7 + 1604 .cfi_def_cfa_register 13 + 1605 @ sp needed + 1606 0084 5DF8047B ldr r7, [sp], #4 + 1607 .cfi_restore 7 + 1608 .cfi_def_cfa_offset 0 + 1609 0088 7047 bx lr + 1610 .cfi_endproc + 1611 .LFE141: + 1613 .section .text.HAL_CAN_GetTxMailboxesFreeLevel,"ax",%progbits + 1614 .align 1 + 1615 .global HAL_CAN_GetTxMailboxesFreeLevel + 1616 .syntax unified + 1617 .thumb + 1618 .thumb_func + 1620 HAL_CAN_GetTxMailboxesFreeLevel: + 1621 .LFB142: +1349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +1351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Return Tx Mailboxes free level: number of free Tx Mailboxes. +1352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains +1353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +1354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval Number of free Tx Mailboxes. +1355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +1356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t HAL_CAN_GetTxMailboxesFreeLevel(const CAN_HandleTypeDef *hcan) +1357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 1622 .loc 1 1357 1 + 1623 .cfi_startproc + 1624 @ args = 0, pretend = 0, frame = 16 + 1625 @ frame_needed = 1, uses_anonymous_args = 0 + 1626 @ link register save eliminated. + 1627 0000 80B4 push {r7} + 1628 .cfi_def_cfa_offset 4 + 1629 .cfi_offset 7, -4 + 1630 0002 85B0 sub sp, sp, #20 + 1631 .cfi_def_cfa_offset 24 + 1632 0004 00AF add r7, sp, #0 + 1633 .cfi_def_cfa_register 7 + 1634 0006 7860 str r0, [r7, #4] +1358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t freelevel = 0U; + 1635 .loc 1 1358 12 + 1636 0008 0023 movs r3, #0 + 1637 000a FB60 str r3, [r7, #12] +1359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_StateTypeDef state = hcan->State; + 1638 .loc 1 1359 24 + 1639 000c 7B68 ldr r3, [r7, #4] + 1640 000e 93F82030 ldrb r3, [r3, #32] + 1641 0012 FB72 strb r3, [r7, #11] +1360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((state == HAL_CAN_STATE_READY) || + 1642 .loc 1 1361 6 + 1643 0014 FB7A ldrb r3, [r7, #11] @ zero_extendqisi2 + 1644 0016 012B cmp r3, #1 + 1645 0018 02D0 beq .L80 + 1646 .loc 1 1361 38 discriminator 1 + 1647 001a FB7A ldrb r3, [r7, #11] @ zero_extendqisi2 + 1648 001c 022B cmp r3, #2 + ARM GAS /tmp/ccM1MpQr.s page 54 + + + 1649 001e 1DD1 bne .L81 + 1650 .L80: +1362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (state == HAL_CAN_STATE_LISTENING)) +1363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check Tx Mailbox 0 status */ +1365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((hcan->Instance->TSR & CAN_TSR_TME0) != 0U) + 1651 .loc 1 1365 14 + 1652 0020 7B68 ldr r3, [r7, #4] + 1653 0022 1B68 ldr r3, [r3] + 1654 .loc 1 1365 24 + 1655 0024 9B68 ldr r3, [r3, #8] + 1656 .loc 1 1365 30 + 1657 0026 03F08063 and r3, r3, #67108864 + 1658 .loc 1 1365 8 + 1659 002a 002B cmp r3, #0 + 1660 002c 02D0 beq .L82 +1366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** freelevel++; + 1661 .loc 1 1367 16 + 1662 002e FB68 ldr r3, [r7, #12] + 1663 0030 0133 adds r3, r3, #1 + 1664 0032 FB60 str r3, [r7, #12] + 1665 .L82: +1368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check Tx Mailbox 1 status */ +1371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((hcan->Instance->TSR & CAN_TSR_TME1) != 0U) + 1666 .loc 1 1371 14 + 1667 0034 7B68 ldr r3, [r7, #4] + 1668 0036 1B68 ldr r3, [r3] + 1669 .loc 1 1371 24 + 1670 0038 9B68 ldr r3, [r3, #8] + 1671 .loc 1 1371 30 + 1672 003a 03F00063 and r3, r3, #134217728 + 1673 .loc 1 1371 8 + 1674 003e 002B cmp r3, #0 + 1675 0040 02D0 beq .L83 +1372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** freelevel++; + 1676 .loc 1 1373 16 + 1677 0042 FB68 ldr r3, [r7, #12] + 1678 0044 0133 adds r3, r3, #1 + 1679 0046 FB60 str r3, [r7, #12] + 1680 .L83: +1374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check Tx Mailbox 2 status */ +1377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((hcan->Instance->TSR & CAN_TSR_TME2) != 0U) + 1681 .loc 1 1377 14 + 1682 0048 7B68 ldr r3, [r7, #4] + 1683 004a 1B68 ldr r3, [r3] + 1684 .loc 1 1377 24 + 1685 004c 9B68 ldr r3, [r3, #8] + 1686 .loc 1 1377 30 + 1687 004e 03F08053 and r3, r3, #268435456 + 1688 .loc 1 1377 8 + 1689 0052 002B cmp r3, #0 + ARM GAS /tmp/ccM1MpQr.s page 55 + + + 1690 0054 02D0 beq .L81 +1378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** freelevel++; + 1691 .loc 1 1379 16 + 1692 0056 FB68 ldr r3, [r7, #12] + 1693 0058 0133 adds r3, r3, #1 + 1694 005a FB60 str r3, [r7, #12] + 1695 .L81: +1380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return Tx Mailboxes free level */ +1384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return freelevel; + 1696 .loc 1 1384 10 + 1697 005c FB68 ldr r3, [r7, #12] +1385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1698 .loc 1 1385 1 + 1699 005e 1846 mov r0, r3 + 1700 0060 1437 adds r7, r7, #20 + 1701 .cfi_def_cfa_offset 4 + 1702 0062 BD46 mov sp, r7 + 1703 .cfi_def_cfa_register 13 + 1704 @ sp needed + 1705 0064 5DF8047B ldr r7, [sp], #4 + 1706 .cfi_restore 7 + 1707 .cfi_def_cfa_offset 0 + 1708 0068 7047 bx lr + 1709 .cfi_endproc + 1710 .LFE142: + 1712 .section .text.HAL_CAN_IsTxMessagePending,"ax",%progbits + 1713 .align 1 + 1714 .global HAL_CAN_IsTxMessagePending + 1715 .syntax unified + 1716 .thumb + 1717 .thumb_func + 1719 HAL_CAN_IsTxMessagePending: + 1720 .LFB143: +1386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +1388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Check if a transmission request is pending on the selected Tx +1389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * Mailboxes. +1390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to an CAN_HandleTypeDef structure that contains +1391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +1392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param TxMailboxes List of Tx Mailboxes to check. +1393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * This parameter can be any combination of @arg CAN_Tx_Mailboxes. +1394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval Status +1395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * - 0 : No pending transmission request on any selected Tx Mailboxes. +1396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * - 1 : Pending transmission request on at least one of the selected +1397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * Tx Mailbox. +1398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +1399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t HAL_CAN_IsTxMessagePending(const CAN_HandleTypeDef *hcan, uint32_t TxMailboxes) +1400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 1721 .loc 1 1400 1 + 1722 .cfi_startproc + 1723 @ args = 0, pretend = 0, frame = 16 + 1724 @ frame_needed = 1, uses_anonymous_args = 0 + 1725 @ link register save eliminated. + ARM GAS /tmp/ccM1MpQr.s page 56 + + + 1726 0000 80B4 push {r7} + 1727 .cfi_def_cfa_offset 4 + 1728 .cfi_offset 7, -4 + 1729 0002 85B0 sub sp, sp, #20 + 1730 .cfi_def_cfa_offset 24 + 1731 0004 00AF add r7, sp, #0 + 1732 .cfi_def_cfa_register 7 + 1733 0006 7860 str r0, [r7, #4] + 1734 0008 3960 str r1, [r7] +1401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t status = 0U; + 1735 .loc 1 1401 12 + 1736 000a 0023 movs r3, #0 + 1737 000c FB60 str r3, [r7, #12] +1402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_StateTypeDef state = hcan->State; + 1738 .loc 1 1402 24 + 1739 000e 7B68 ldr r3, [r7, #4] + 1740 0010 93F82030 ldrb r3, [r3, #32] + 1741 0014 FB72 strb r3, [r7, #11] +1403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check function parameters */ +1405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes)); +1406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((state == HAL_CAN_STATE_READY) || + 1742 .loc 1 1407 6 + 1743 0016 FB7A ldrb r3, [r7, #11] @ zero_extendqisi2 + 1744 0018 012B cmp r3, #1 + 1745 001a 02D0 beq .L86 + 1746 .loc 1 1407 38 discriminator 1 + 1747 001c FB7A ldrb r3, [r7, #11] @ zero_extendqisi2 + 1748 001e 022B cmp r3, #2 + 1749 0020 0BD1 bne .L87 + 1750 .L86: +1408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (state == HAL_CAN_STATE_LISTENING)) +1409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check pending transmission request on the selected Tx Mailboxes */ +1411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((hcan->Instance->TSR & (TxMailboxes << CAN_TSR_TME0_Pos)) != (TxMailboxes << CAN_TSR_TME0_P + 1751 .loc 1 1411 14 + 1752 0022 7B68 ldr r3, [r7, #4] + 1753 0024 1B68 ldr r3, [r3] + 1754 .loc 1 1411 24 + 1755 0026 9A68 ldr r2, [r3, #8] + 1756 .loc 1 1411 45 + 1757 0028 3B68 ldr r3, [r7] + 1758 002a 9B06 lsls r3, r3, #26 + 1759 .loc 1 1411 30 + 1760 002c 1A40 ands r2, r2, r3 + 1761 .loc 1 1411 83 + 1762 002e 3B68 ldr r3, [r7] + 1763 0030 9B06 lsls r3, r3, #26 + 1764 .loc 1 1411 8 + 1765 0032 9A42 cmp r2, r3 + 1766 0034 01D0 beq .L87 +1412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** status = 1U; + 1767 .loc 1 1413 14 + 1768 0036 0123 movs r3, #1 + 1769 0038 FB60 str r3, [r7, #12] + ARM GAS /tmp/ccM1MpQr.s page 57 + + + 1770 .L87: +1414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return status */ +1418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return status; + 1771 .loc 1 1418 10 + 1772 003a FB68 ldr r3, [r7, #12] +1419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1773 .loc 1 1419 1 + 1774 003c 1846 mov r0, r3 + 1775 003e 1437 adds r7, r7, #20 + 1776 .cfi_def_cfa_offset 4 + 1777 0040 BD46 mov sp, r7 + 1778 .cfi_def_cfa_register 13 + 1779 @ sp needed + 1780 0042 5DF8047B ldr r7, [sp], #4 + 1781 .cfi_restore 7 + 1782 .cfi_def_cfa_offset 0 + 1783 0046 7047 bx lr + 1784 .cfi_endproc + 1785 .LFE143: + 1787 .section .text.HAL_CAN_GetTxTimestamp,"ax",%progbits + 1788 .align 1 + 1789 .global HAL_CAN_GetTxTimestamp + 1790 .syntax unified + 1791 .thumb + 1792 .thumb_func + 1794 HAL_CAN_GetTxTimestamp: + 1795 .LFB144: +1420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +1422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Return timestamp of Tx message sent, if time triggered communication +1423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** mode is enabled. +1424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains +1425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +1426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param TxMailbox Tx Mailbox where the timestamp of message sent will be +1427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * read. +1428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * This parameter can be one value of @arg CAN_Tx_Mailboxes. +1429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval Timestamp of message sent from Tx Mailbox. +1430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +1431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t HAL_CAN_GetTxTimestamp(const CAN_HandleTypeDef *hcan, uint32_t TxMailbox) +1432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 1796 .loc 1 1432 1 + 1797 .cfi_startproc + 1798 @ args = 0, pretend = 0, frame = 32 + 1799 @ frame_needed = 1, uses_anonymous_args = 0 + 1800 @ link register save eliminated. + 1801 0000 80B4 push {r7} + 1802 .cfi_def_cfa_offset 4 + 1803 .cfi_offset 7, -4 + 1804 0002 89B0 sub sp, sp, #36 + 1805 .cfi_def_cfa_offset 40 + 1806 0004 00AF add r7, sp, #0 + 1807 .cfi_def_cfa_register 7 + 1808 0006 7860 str r0, [r7, #4] + 1809 0008 3960 str r1, [r7] + ARM GAS /tmp/ccM1MpQr.s page 58 + + +1433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t timestamp = 0U; + 1810 .loc 1 1433 12 + 1811 000a 0023 movs r3, #0 + 1812 000c FB61 str r3, [r7, #28] +1434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t transmitmailbox; +1435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_StateTypeDef state = hcan->State; + 1813 .loc 1 1435 24 + 1814 000e 7B68 ldr r3, [r7, #4] + 1815 0010 93F82030 ldrb r3, [r3, #32] + 1816 0014 FB76 strb r3, [r7, #27] +1436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check function parameters */ +1438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_TX_MAILBOX(TxMailbox)); +1439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((state == HAL_CAN_STATE_READY) || + 1817 .loc 1 1440 6 + 1818 0016 FB7E ldrb r3, [r7, #27] @ zero_extendqisi2 + 1819 0018 012B cmp r3, #1 + 1820 001a 02D0 beq .L90 + 1821 .loc 1 1440 38 discriminator 1 + 1822 001c FB7E ldrb r3, [r7, #27] @ zero_extendqisi2 + 1823 001e 022B cmp r3, #2 + 1824 0020 15D1 bne .L91 + 1825 .L90: + 1826 0022 3B68 ldr r3, [r7] + 1827 0024 3B61 str r3, [r7, #16] + 1828 .LBB4: + 1829 .LBB5: + 1830 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h" + 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** + 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h + 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file + 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.0.4 + 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 09. April 2018 + 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ + 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* + 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 + 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may + 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. + 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at + 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 + 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software + 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT + 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and + 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. + 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 24:Drivers/CMSIS/Include/cmsis_gcc.h **** + 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H + 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H + 27:Drivers/CMSIS/Include/cmsis_gcc.h **** + 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ + ARM GAS /tmp/ccM1MpQr.s page 59 + + + 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" + 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" + 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" + 33:Drivers/CMSIS/Include/cmsis_gcc.h **** + 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ + 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin + 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) + 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 38:Drivers/CMSIS/Include/cmsis_gcc.h **** + 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ + 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM + 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm + 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE + 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline + 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE + 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline + 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE + 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline + 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN + 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) + 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED + 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) + 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK + 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) + 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED + 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) + 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT + 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION + 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) + 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ + 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE + 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- + 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + ARM GAS /tmp/ccM1MpQr.s page 60 + + + 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ + 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add + 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE + 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- + 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ + 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add + 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED + 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) + 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT + 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict + 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 116:Drivers/CMSIS/Include/cmsis_gcc.h **** + 117:Drivers/CMSIS/Include/cmsis_gcc.h **** + 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ + 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface + 120:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + 121:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 122:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 123:Drivers/CMSIS/Include/cmsis_gcc.h **** + 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts + 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + 127:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 128:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) + 130:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); + 132:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 133:Drivers/CMSIS/Include/cmsis_gcc.h **** + 134:Drivers/CMSIS/Include/cmsis_gcc.h **** + 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 136:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts + 137:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. + 138:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 139:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) + 141:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 142:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); + ARM GAS /tmp/ccM1MpQr.s page 61 + + + 143:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 144:Drivers/CMSIS/Include/cmsis_gcc.h **** + 145:Drivers/CMSIS/Include/cmsis_gcc.h **** + 146:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 147:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register + 148:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register. + 149:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value + 150:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) + 152:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 153:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 154:Drivers/CMSIS/Include/cmsis_gcc.h **** + 155:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) ); + 156:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 157:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 158:Drivers/CMSIS/Include/cmsis_gcc.h **** + 159:Drivers/CMSIS/Include/cmsis_gcc.h **** + 160:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 161:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 162:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register (non-secure) + 163:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the non-secure Control Register when in secure mode. + 164:Drivers/CMSIS/Include/cmsis_gcc.h **** \return non-secure Control Register value + 165:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 166:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) + 167:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 168:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 169:Drivers/CMSIS/Include/cmsis_gcc.h **** + 170:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + 171:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 172:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 174:Drivers/CMSIS/Include/cmsis_gcc.h **** + 175:Drivers/CMSIS/Include/cmsis_gcc.h **** + 176:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 177:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register + 178:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register. + 179:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 180:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 181:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) + 182:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 183:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + 184:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 185:Drivers/CMSIS/Include/cmsis_gcc.h **** + 186:Drivers/CMSIS/Include/cmsis_gcc.h **** + 187:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 188:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 189:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register (non-secure) + 190:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the non-secure Control Register when in secure state. + 191:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 192:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 193:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) + 194:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 195:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + 196:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 197:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 198:Drivers/CMSIS/Include/cmsis_gcc.h **** + 199:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccM1MpQr.s page 62 + + + 200:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 201:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register + 202:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register. + 203:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value + 204:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void) + 206:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 207:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 208:Drivers/CMSIS/Include/cmsis_gcc.h **** + 209:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 210:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 211:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 212:Drivers/CMSIS/Include/cmsis_gcc.h **** + 213:Drivers/CMSIS/Include/cmsis_gcc.h **** + 214:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 215:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register + 216:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register. + 217:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value + 218:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 219:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void) + 220:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 221:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 222:Drivers/CMSIS/Include/cmsis_gcc.h **** + 223:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + 224:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 225:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 226:Drivers/CMSIS/Include/cmsis_gcc.h **** + 227:Drivers/CMSIS/Include/cmsis_gcc.h **** + 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 229:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register + 230:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register. + 231:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value + 232:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void) + 234:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 235:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 236:Drivers/CMSIS/Include/cmsis_gcc.h **** + 237:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + 238:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 239:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 240:Drivers/CMSIS/Include/cmsis_gcc.h **** + 241:Drivers/CMSIS/Include/cmsis_gcc.h **** + 242:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 243:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer + 244:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP). + 245:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 246:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 247:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void) + 248:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 249:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 250:Drivers/CMSIS/Include/cmsis_gcc.h **** + 251:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp" : "=r" (result) ); + 252:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 253:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 254:Drivers/CMSIS/Include/cmsis_gcc.h **** + 255:Drivers/CMSIS/Include/cmsis_gcc.h **** + 256:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + ARM GAS /tmp/ccM1MpQr.s page 63 + + + 257:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 258:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer (non-secure) + 259:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s + 260:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 261:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) + 263:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 264:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 265:Drivers/CMSIS/Include/cmsis_gcc.h **** + 266:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + 267:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 268:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 269:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 270:Drivers/CMSIS/Include/cmsis_gcc.h **** + 271:Drivers/CMSIS/Include/cmsis_gcc.h **** + 272:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 273:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer + 274:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP). + 275:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 276:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 277:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) + 278:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 279:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); + 280:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 281:Drivers/CMSIS/Include/cmsis_gcc.h **** + 282:Drivers/CMSIS/Include/cmsis_gcc.h **** + 283:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 284:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 285:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + 286:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta + 287:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 288:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 289:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) + 290:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 291:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); + 292:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 293:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 294:Drivers/CMSIS/Include/cmsis_gcc.h **** + 295:Drivers/CMSIS/Include/cmsis_gcc.h **** + 296:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 297:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer + 298:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP). + 299:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 300:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 301:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void) + 302:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 303:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 304:Drivers/CMSIS/Include/cmsis_gcc.h **** + 305:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp" : "=r" (result) ); + 306:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 307:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 308:Drivers/CMSIS/Include/cmsis_gcc.h **** + 309:Drivers/CMSIS/Include/cmsis_gcc.h **** + 310:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 311:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 312:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer (non-secure) + 313:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat + ARM GAS /tmp/ccM1MpQr.s page 64 + + + 314:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 315:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 316:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) + 317:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 318:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 319:Drivers/CMSIS/Include/cmsis_gcc.h **** + 320:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + 321:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 322:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 324:Drivers/CMSIS/Include/cmsis_gcc.h **** + 325:Drivers/CMSIS/Include/cmsis_gcc.h **** + 326:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 327:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer + 328:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP). + 329:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 330:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 331:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) + 332:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 333:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); + 334:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 335:Drivers/CMSIS/Include/cmsis_gcc.h **** + 336:Drivers/CMSIS/Include/cmsis_gcc.h **** + 337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 338:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 339:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer (non-secure) + 340:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + 341:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 342:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 343:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) + 344:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 345:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); + 346:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 347:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 348:Drivers/CMSIS/Include/cmsis_gcc.h **** + 349:Drivers/CMSIS/Include/cmsis_gcc.h **** + 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 352:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Stack Pointer (non-secure) + 353:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + 354:Drivers/CMSIS/Include/cmsis_gcc.h **** \return SP Register value + 355:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) + 357:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 358:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 359:Drivers/CMSIS/Include/cmsis_gcc.h **** + 360:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + 361:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 362:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 363:Drivers/CMSIS/Include/cmsis_gcc.h **** + 364:Drivers/CMSIS/Include/cmsis_gcc.h **** + 365:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 366:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Stack Pointer (non-secure) + 367:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + 368:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfStack Stack Pointer value to set + 369:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 370:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) + ARM GAS /tmp/ccM1MpQr.s page 65 + + + 371:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 372:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); + 373:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 374:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 375:Drivers/CMSIS/Include/cmsis_gcc.h **** + 376:Drivers/CMSIS/Include/cmsis_gcc.h **** + 377:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 378:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask + 379:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register. + 380:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 381:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 382:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) + 383:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 384:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 385:Drivers/CMSIS/Include/cmsis_gcc.h **** + 386:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 387:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 388:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 389:Drivers/CMSIS/Include/cmsis_gcc.h **** + 390:Drivers/CMSIS/Include/cmsis_gcc.h **** + 391:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 392:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 393:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask (non-secure) + 394:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg + 395:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 396:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 397:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) + 398:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 399:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 400:Drivers/CMSIS/Include/cmsis_gcc.h **** + 401:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + 402:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 403:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 405:Drivers/CMSIS/Include/cmsis_gcc.h **** + 406:Drivers/CMSIS/Include/cmsis_gcc.h **** + 407:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 408:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask + 409:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register. + 410:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 411:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 412:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) + 413:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 414:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 415:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 416:Drivers/CMSIS/Include/cmsis_gcc.h **** + 417:Drivers/CMSIS/Include/cmsis_gcc.h **** + 418:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 419:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 420:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask (non-secure) + 421:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + 422:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 423:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 424:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) + 425:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 426:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); + 427:Drivers/CMSIS/Include/cmsis_gcc.h **** } + ARM GAS /tmp/ccM1MpQr.s page 66 + + + 428:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 429:Drivers/CMSIS/Include/cmsis_gcc.h **** + 430:Drivers/CMSIS/Include/cmsis_gcc.h **** + 431:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 432:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 433:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + 434:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 435:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ + 436:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + 437:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 438:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 439:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void) + 440:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 441:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory"); + 442:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 443:Drivers/CMSIS/Include/cmsis_gcc.h **** + 444:Drivers/CMSIS/Include/cmsis_gcc.h **** + 445:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 446:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ + 447:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR. + 448:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 449:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 450:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void) + 451:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 452:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory"); + 453:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 454:Drivers/CMSIS/Include/cmsis_gcc.h **** + 455:Drivers/CMSIS/Include/cmsis_gcc.h **** + 456:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 457:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority + 458:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register. + 459:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 460:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 461:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) + 462:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 463:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 464:Drivers/CMSIS/Include/cmsis_gcc.h **** + 465:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + 466:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 467:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 468:Drivers/CMSIS/Include/cmsis_gcc.h **** + 469:Drivers/CMSIS/Include/cmsis_gcc.h **** + 470:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 471:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 472:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority (non-secure) + 473:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Base Priority register when in secure state. + 474:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 475:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) + 477:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 478:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 479:Drivers/CMSIS/Include/cmsis_gcc.h **** + 480:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + 481:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 482:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 483:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 484:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccM1MpQr.s page 67 + + + 485:Drivers/CMSIS/Include/cmsis_gcc.h **** + 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 487:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority + 488:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register. + 489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 490:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) + 492:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 493:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); + 494:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 495:Drivers/CMSIS/Include/cmsis_gcc.h **** + 496:Drivers/CMSIS/Include/cmsis_gcc.h **** + 497:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 498:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 499:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority (non-secure) + 500:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Base Priority register when in secure state. + 501:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 502:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 503:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) + 504:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 505:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); + 506:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 507:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 508:Drivers/CMSIS/Include/cmsis_gcc.h **** + 509:Drivers/CMSIS/Include/cmsis_gcc.h **** + 510:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 511:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition + 512:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable + 513:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level. + 514:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 515:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 516:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) + 517:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 518:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); + 519:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 520:Drivers/CMSIS/Include/cmsis_gcc.h **** + 521:Drivers/CMSIS/Include/cmsis_gcc.h **** + 522:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 523:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask + 524:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register. + 525:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 526:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) + 528:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 529:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 530:Drivers/CMSIS/Include/cmsis_gcc.h **** + 531:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + 532:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 533:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 534:Drivers/CMSIS/Include/cmsis_gcc.h **** + 535:Drivers/CMSIS/Include/cmsis_gcc.h **** + 536:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 537:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 538:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask (non-secure) + 539:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Fault Mask register when in secure state. + 540:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 541:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + ARM GAS /tmp/ccM1MpQr.s page 68 + + + 542:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) + 543:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 544:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 545:Drivers/CMSIS/Include/cmsis_gcc.h **** + 546:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + 547:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 548:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 549:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 550:Drivers/CMSIS/Include/cmsis_gcc.h **** + 551:Drivers/CMSIS/Include/cmsis_gcc.h **** + 552:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 553:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask + 554:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register. + 555:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 556:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 557:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) + 558:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 559:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); + 560:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 561:Drivers/CMSIS/Include/cmsis_gcc.h **** + 562:Drivers/CMSIS/Include/cmsis_gcc.h **** + 563:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 564:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 565:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask (non-secure) + 566:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Fault Mask register when in secure state. + 567:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 568:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 569:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) + 570:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 571:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); + 572:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 573:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 574:Drivers/CMSIS/Include/cmsis_gcc.h **** + 575:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 576:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 577:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + 578:Drivers/CMSIS/Include/cmsis_gcc.h **** + 579:Drivers/CMSIS/Include/cmsis_gcc.h **** + 580:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 581:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + 582:Drivers/CMSIS/Include/cmsis_gcc.h **** + 583:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 584:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit + 585:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 586:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 587:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 588:Drivers/CMSIS/Include/cmsis_gcc.h **** + 589:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + 590:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 591:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 592:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) + 593:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 594:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 595:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 596:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 597:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 598:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + ARM GAS /tmp/ccM1MpQr.s page 69 + + + 599:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 600:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + 601:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 602:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 603:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 604:Drivers/CMSIS/Include/cmsis_gcc.h **** + 605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) + 606:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 607:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit (non-secure) + 608:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 609:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + 610:Drivers/CMSIS/Include/cmsis_gcc.h **** + 611:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in + 612:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 613:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 614:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) + 615:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 617:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 618:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 619:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 620:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 621:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + 622:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 623:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 624:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 625:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 626:Drivers/CMSIS/Include/cmsis_gcc.h **** + 627:Drivers/CMSIS/Include/cmsis_gcc.h **** + 628:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 629:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer Limit + 630:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 631:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 632:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 633:Drivers/CMSIS/Include/cmsis_gcc.h **** + 634:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + 635:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 636:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 637:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) + 638:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 639:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 640:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 641:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 642:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 643:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 644:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); + 645:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 646:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 647:Drivers/CMSIS/Include/cmsis_gcc.h **** + 648:Drivers/CMSIS/Include/cmsis_gcc.h **** + 649:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 651:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + 652:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 653:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 654:Drivers/CMSIS/Include/cmsis_gcc.h **** + 655:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s + ARM GAS /tmp/ccM1MpQr.s page 70 + + + 656:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 657:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 658:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) + 659:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 661:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 662:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 663:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 664:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); + 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 666:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 667:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 668:Drivers/CMSIS/Include/cmsis_gcc.h **** + 669:Drivers/CMSIS/Include/cmsis_gcc.h **** + 670:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 671:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit + 672:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 673:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 674:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 675:Drivers/CMSIS/Include/cmsis_gcc.h **** + 676:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + 677:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 678:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) + 680:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 681:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 682:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 683:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 684:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 685:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 686:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 687:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + 688:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 689:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 690:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 691:Drivers/CMSIS/Include/cmsis_gcc.h **** + 692:Drivers/CMSIS/Include/cmsis_gcc.h **** + 693:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 694:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 695:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit (non-secure) + 696:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 697:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + 698:Drivers/CMSIS/Include/cmsis_gcc.h **** + 699:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec + 700:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 701:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 702:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) + 703:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 704:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 705:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 706:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 707:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 708:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 709:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + 710:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 711:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 712:Drivers/CMSIS/Include/cmsis_gcc.h **** } + ARM GAS /tmp/ccM1MpQr.s page 71 + + + 713:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 714:Drivers/CMSIS/Include/cmsis_gcc.h **** + 715:Drivers/CMSIS/Include/cmsis_gcc.h **** + 716:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 717:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit + 718:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 719:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 720:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 721:Drivers/CMSIS/Include/cmsis_gcc.h **** + 722:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + 723:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + 724:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) + 726:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 728:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 729:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 730:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 731:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 732:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); + 733:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 734:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 735:Drivers/CMSIS/Include/cmsis_gcc.h **** + 736:Drivers/CMSIS/Include/cmsis_gcc.h **** + 737:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 738:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 739:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit (non-secure) + 740:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 741:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 742:Drivers/CMSIS/Include/cmsis_gcc.h **** + 743:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu + 744:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer value to set + 745:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) + 747:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 749:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 750:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 751:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 752:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); + 753:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 754:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 755:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 756:Drivers/CMSIS/Include/cmsis_gcc.h **** + 757:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 758:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + 759:Drivers/CMSIS/Include/cmsis_gcc.h **** + 760:Drivers/CMSIS/Include/cmsis_gcc.h **** + 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 762:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR + 763:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register. + 764:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value + 765:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 766:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) + 767:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 768:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 769:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + ARM GAS /tmp/ccM1MpQr.s page 72 + + + 770:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) + 771:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + 772:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 773:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 774:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_arm_get_fpscr(); + 775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 776:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 777:Drivers/CMSIS/Include/cmsis_gcc.h **** + 778:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + 779:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 781:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 782:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0U); + 783:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 784:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 785:Drivers/CMSIS/Include/cmsis_gcc.h **** + 786:Drivers/CMSIS/Include/cmsis_gcc.h **** + 787:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 788:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR + 789:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register. + 790:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set + 791:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) + 793:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 795:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 796:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr) + 797:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + 798:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 799:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 800:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_arm_set_fpscr(fpscr); + 801:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 802:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); + 803:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 805:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)fpscr; + 806:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 807:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 808:Drivers/CMSIS/Include/cmsis_gcc.h **** + 809:Drivers/CMSIS/Include/cmsis_gcc.h **** + 810:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */ + 811:Drivers/CMSIS/Include/cmsis_gcc.h **** + 812:Drivers/CMSIS/Include/cmsis_gcc.h **** + 813:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */ + 814:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + 815:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions + 816:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 817:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 818:Drivers/CMSIS/Include/cmsis_gcc.h **** + 819:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2. + 820:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l" + 821:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */ + 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__) + 823:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r) + 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r) + 825:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r) + 826:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + ARM GAS /tmp/ccM1MpQr.s page 73 + + + 827:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r) + 828:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r) + 829:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r) + 830:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 831:Drivers/CMSIS/Include/cmsis_gcc.h **** + 832:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 833:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation + 834:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes. + 835:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 836:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP() __ASM volatile ("nop") + 837:Drivers/CMSIS/Include/cmsis_gcc.h **** + 838:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 839:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt + 840:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o + 841:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI() __ASM volatile ("wfi") + 843:Drivers/CMSIS/Include/cmsis_gcc.h **** + 844:Drivers/CMSIS/Include/cmsis_gcc.h **** + 845:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 846:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event + 847:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter + 848:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs. + 849:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE() __ASM volatile ("wfe") + 851:Drivers/CMSIS/Include/cmsis_gcc.h **** + 852:Drivers/CMSIS/Include/cmsis_gcc.h **** + 853:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 854:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event + 855:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + 856:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 857:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev") + 858:Drivers/CMSIS/Include/cmsis_gcc.h **** + 859:Drivers/CMSIS/Include/cmsis_gcc.h **** + 860:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 861:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier + 862:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor, + 863:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory, + 864:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed. + 865:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 866:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void) + 867:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 868:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory"); + 869:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 870:Drivers/CMSIS/Include/cmsis_gcc.h **** + 871:Drivers/CMSIS/Include/cmsis_gcc.h **** + 872:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 873:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier + 874:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier. + 875:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete. + 876:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 877:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void) + 878:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 879:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory"); + 880:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 881:Drivers/CMSIS/Include/cmsis_gcc.h **** + 882:Drivers/CMSIS/Include/cmsis_gcc.h **** + 883:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + ARM GAS /tmp/ccM1MpQr.s page 74 + + + 884:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Memory Barrier + 885:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Ensures the apparent order of the explicit memory operations before + 886:Drivers/CMSIS/Include/cmsis_gcc.h **** and after the instruction, without ensuring their completion. + 887:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 888:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void) + 889:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 890:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dmb 0xF":::"memory"); + 891:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 892:Drivers/CMSIS/Include/cmsis_gcc.h **** + 893:Drivers/CMSIS/Include/cmsis_gcc.h **** + 894:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 895:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (32 bit) + 896:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x785 + 897:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 898:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 899:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 900:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV(uint32_t value) + 901:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 902:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + 903:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_bswap32(value); + 904:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 905:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 906:Drivers/CMSIS/Include/cmsis_gcc.h **** + 907:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + 908:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 909:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 910:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 911:Drivers/CMSIS/Include/cmsis_gcc.h **** + 912:Drivers/CMSIS/Include/cmsis_gcc.h **** + 913:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 914:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) + 915:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes + 916:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 917:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 918:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 919:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) + 920:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 921:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 922:Drivers/CMSIS/Include/cmsis_gcc.h **** + 923:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + 924:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 925:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 926:Drivers/CMSIS/Include/cmsis_gcc.h **** + 927:Drivers/CMSIS/Include/cmsis_gcc.h **** + 928:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 929:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) + 930:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For exam + 931:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 932:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 933:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 934:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE int16_t __REVSH(int16_t value) + 935:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 936:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + 937:Drivers/CMSIS/Include/cmsis_gcc.h **** return (int16_t)__builtin_bswap16(value); + 938:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 939:Drivers/CMSIS/Include/cmsis_gcc.h **** int16_t result; + 940:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccM1MpQr.s page 75 + + + 941:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + 942:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 943:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 944:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 945:Drivers/CMSIS/Include/cmsis_gcc.h **** + 946:Drivers/CMSIS/Include/cmsis_gcc.h **** + 947:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 948:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Rotate Right in unsigned value (32 bit) + 949:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v + 950:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op1 Value to rotate + 951:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op2 Number of Bits to rotate + 952:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Rotated value + 953:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 954:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) + 955:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 956:Drivers/CMSIS/Include/cmsis_gcc.h **** op2 %= 32U; + 957:Drivers/CMSIS/Include/cmsis_gcc.h **** if (op2 == 0U) + 958:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 959:Drivers/CMSIS/Include/cmsis_gcc.h **** return op1; + 960:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 961:Drivers/CMSIS/Include/cmsis_gcc.h **** return (op1 >> op2) | (op1 << (32U - op2)); + 962:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 963:Drivers/CMSIS/Include/cmsis_gcc.h **** + 964:Drivers/CMSIS/Include/cmsis_gcc.h **** + 965:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 966:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Breakpoint + 967:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Causes the processor to enter Debug state. + 968:Drivers/CMSIS/Include/cmsis_gcc.h **** Debug tools can use this to investigate system state when the instruction at a particula + 969:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value is ignored by the processor. + 970:Drivers/CMSIS/Include/cmsis_gcc.h **** If required, a debugger can use it to store additional information about the break + 971:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 972:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __BKPT(value) __ASM volatile ("bkpt "#value) + 973:Drivers/CMSIS/Include/cmsis_gcc.h **** + 974:Drivers/CMSIS/Include/cmsis_gcc.h **** + 975:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 976:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse bit order of value + 977:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the bit order of the given value. + 978:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 979:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 980:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) + 982:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 984:Drivers/CMSIS/Include/cmsis_gcc.h **** + 985:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 986:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 987:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 1831 .loc 2 988 4 + 1832 0026 3B69 ldr r3, [r7, #16] + 1833 .syntax unified + 1834 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1835 0028 93FAA3F3 rbit r3, r3 + 1836 @ 0 "" 2 + 1837 .thumb + 1838 .syntax unified + 1839 002c FB60 str r3, [r7, #12] + ARM GAS /tmp/ccM1MpQr.s page 76 + + + 989:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 990:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + 991:Drivers/CMSIS/Include/cmsis_gcc.h **** + 992:Drivers/CMSIS/Include/cmsis_gcc.h **** result = value; /* r will be reversed bits of v; first get LSB of v */ + 993:Drivers/CMSIS/Include/cmsis_gcc.h **** for (value >>= 1U; value != 0U; value >>= 1U) + 994:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 995:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= 1U; + 996:Drivers/CMSIS/Include/cmsis_gcc.h **** result |= value & 1U; + 997:Drivers/CMSIS/Include/cmsis_gcc.h **** s--; + 998:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 999:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= s; /* shift when v's highest bits are zero */ +1000:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif +1001:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 1840 .loc 2 1001 10 + 1841 002e FB68 ldr r3, [r7, #12] + 1842 .LBE5: + 1843 .LBE4: +1441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (state == HAL_CAN_STATE_LISTENING)) +1442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Select the Tx mailbox */ +1444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** transmitmailbox = POSITION_VAL(TxMailbox); + 1844 .loc 1 1444 23 discriminator 1 + 1845 0030 B3FA83F3 clz r3, r3 + 1846 .loc 1 1444 23 is_stmt 0 discriminator 2 + 1847 0034 DBB2 uxtb r3, r3 + 1848 .loc 1 1444 21 is_stmt 1 discriminator 2 + 1849 0036 7B61 str r3, [r7, #20] +1445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Get timestamp */ +1447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** timestamp = (hcan->Instance->sTxMailBox[transmitmailbox].TDTR & CAN_TDT0R_TIME) >> CAN_TDT0R_TI + 1850 .loc 1 1447 22 + 1851 0038 7B68 ldr r3, [r7, #4] + 1852 003a 1A68 ldr r2, [r3] + 1853 .loc 1 1447 61 + 1854 003c 7B69 ldr r3, [r7, #20] + 1855 003e 1833 adds r3, r3, #24 + 1856 0040 1B01 lsls r3, r3, #4 + 1857 0042 1344 add r3, r3, r2 + 1858 0044 0433 adds r3, r3, #4 + 1859 0046 1B68 ldr r3, [r3] + 1860 .loc 1 1447 85 + 1861 0048 1B0C lsrs r3, r3, #16 + 1862 .loc 1 1447 15 + 1863 004a 9BB2 uxth r3, r3 + 1864 004c FB61 str r3, [r7, #28] + 1865 .L91: +1448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return the timestamp */ +1451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return timestamp; + 1866 .loc 1 1451 10 + 1867 004e FB69 ldr r3, [r7, #28] +1452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 1868 .loc 1 1452 1 + 1869 0050 1846 mov r0, r3 + 1870 0052 2437 adds r7, r7, #36 + 1871 .cfi_def_cfa_offset 4 + ARM GAS /tmp/ccM1MpQr.s page 77 + + + 1872 0054 BD46 mov sp, r7 + 1873 .cfi_def_cfa_register 13 + 1874 @ sp needed + 1875 0056 5DF8047B ldr r7, [sp], #4 + 1876 .cfi_restore 7 + 1877 .cfi_def_cfa_offset 0 + 1878 005a 7047 bx lr + 1879 .cfi_endproc + 1880 .LFE144: + 1882 .section .text.HAL_CAN_GetRxMessage,"ax",%progbits + 1883 .align 1 + 1884 .global HAL_CAN_GetRxMessage + 1885 .syntax unified + 1886 .thumb + 1887 .thumb_func + 1889 HAL_CAN_GetRxMessage: + 1890 .LFB145: +1453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +1455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Get an CAN frame from the Rx FIFO zone into the message RAM. +1456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to an CAN_HandleTypeDef structure that contains +1457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +1458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param RxFifo Fifo number of the received message to be read. +1459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * This parameter can be a value of @arg CAN_receive_FIFO_number. +1460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param pHeader pointer to a CAN_RxHeaderTypeDef structure where the header +1461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * of the Rx frame will be stored. +1462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param aData array where the payload of the Rx frame will be stored. +1463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval HAL status +1464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +1465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, +1466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]) +1467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 1891 .loc 1 1467 1 + 1892 .cfi_startproc + 1893 @ args = 0, pretend = 0, frame = 24 + 1894 @ frame_needed = 1, uses_anonymous_args = 0 + 1895 @ link register save eliminated. + 1896 0000 80B4 push {r7} + 1897 .cfi_def_cfa_offset 4 + 1898 .cfi_offset 7, -4 + 1899 0002 87B0 sub sp, sp, #28 + 1900 .cfi_def_cfa_offset 32 + 1901 0004 00AF add r7, sp, #0 + 1902 .cfi_def_cfa_register 7 + 1903 0006 F860 str r0, [r7, #12] + 1904 0008 B960 str r1, [r7, #8] + 1905 000a 7A60 str r2, [r7, #4] + 1906 000c 3B60 str r3, [r7] +1468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_StateTypeDef state = hcan->State; + 1907 .loc 1 1468 24 + 1908 000e FB68 ldr r3, [r7, #12] + 1909 0010 93F82030 ldrb r3, [r3, #32] + 1910 0014 FB75 strb r3, [r7, #23] +1469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_RX_FIFO(RxFifo)); +1471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((state == HAL_CAN_STATE_READY) || + ARM GAS /tmp/ccM1MpQr.s page 78 + + + 1911 .loc 1 1472 6 + 1912 0016 FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 1913 0018 012B cmp r3, #1 + 1914 001a 03D0 beq .L95 + 1915 .loc 1 1472 38 discriminator 1 + 1916 001c FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 1917 001e 022B cmp r3, #2 + 1918 0020 40F00381 bne .L96 + 1919 .L95: +1473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (state == HAL_CAN_STATE_LISTENING)) +1474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check the Rx FIFO */ +1476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ + 1920 .loc 1 1476 8 + 1921 0024 BB68 ldr r3, [r7, #8] + 1922 0026 002B cmp r3, #0 + 1923 0028 0ED1 bne .L97 +1477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check that the Rx FIFO 0 is not empty */ +1479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U) + 1924 .loc 1 1479 16 + 1925 002a FB68 ldr r3, [r7, #12] + 1926 002c 1B68 ldr r3, [r3] + 1927 .loc 1 1479 26 + 1928 002e DB68 ldr r3, [r3, #12] + 1929 .loc 1 1479 33 + 1930 0030 03F00303 and r3, r3, #3 + 1931 .loc 1 1479 10 + 1932 0034 002B cmp r3, #0 + 1933 0036 16D1 bne .L98 +1480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code */ +1482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + 1934 .loc 1 1482 13 + 1935 0038 FB68 ldr r3, [r7, #12] + 1936 003a 5B6A ldr r3, [r3, #36] + 1937 .loc 1 1482 25 + 1938 003c 43F40012 orr r2, r3, #2097152 + 1939 0040 FB68 ldr r3, [r7, #12] + 1940 0042 5A62 str r2, [r3, #36] +1483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_ERROR; + 1941 .loc 1 1484 16 + 1942 0044 0123 movs r3, #1 + 1943 0046 F7E0 b .L99 + 1944 .L97: +1485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else /* Rx element is assigned to Rx FIFO 1 */ +1488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check that the Rx FIFO 1 is not empty */ +1490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U) + 1945 .loc 1 1490 16 + 1946 0048 FB68 ldr r3, [r7, #12] + 1947 004a 1B68 ldr r3, [r3] + 1948 .loc 1 1490 26 + 1949 004c 1B69 ldr r3, [r3, #16] + ARM GAS /tmp/ccM1MpQr.s page 79 + + + 1950 .loc 1 1490 33 + 1951 004e 03F00303 and r3, r3, #3 + 1952 .loc 1 1490 10 + 1953 0052 002B cmp r3, #0 + 1954 0054 07D1 bne .L98 +1491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code */ +1493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + 1955 .loc 1 1493 13 + 1956 0056 FB68 ldr r3, [r7, #12] + 1957 0058 5B6A ldr r3, [r3, #36] + 1958 .loc 1 1493 25 + 1959 005a 43F40012 orr r2, r3, #2097152 + 1960 005e FB68 ldr r3, [r7, #12] + 1961 0060 5A62 str r2, [r3, #36] +1494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_ERROR; + 1962 .loc 1 1495 16 + 1963 0062 0123 movs r3, #1 + 1964 0064 E8E0 b .L99 + 1965 .L98: +1496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Get the header */ +1500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR; + 1966 .loc 1 1500 39 + 1967 0066 FB68 ldr r3, [r7, #12] + 1968 0068 1A68 ldr r2, [r3] + 1969 .loc 1 1500 71 + 1970 006a BB68 ldr r3, [r7, #8] + 1971 006c 1B33 adds r3, r3, #27 + 1972 006e 1B01 lsls r3, r3, #4 + 1973 0070 1344 add r3, r3, r2 + 1974 0072 1B68 ldr r3, [r3] + 1975 .loc 1 1500 33 + 1976 0074 03F00402 and r2, r3, #4 + 1977 .loc 1 1500 18 + 1978 0078 7B68 ldr r3, [r7, #4] + 1979 007a 9A60 str r2, [r3, #8] +1501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (pHeader->IDE == CAN_ID_STD) + 1980 .loc 1 1501 16 + 1981 007c 7B68 ldr r3, [r7, #4] + 1982 007e 9B68 ldr r3, [r3, #8] + 1983 .loc 1 1501 8 + 1984 0080 002B cmp r3, #0 + 1985 0082 0CD1 bne .L100 +1502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_ + 1986 .loc 1 1503 45 + 1987 0084 FB68 ldr r3, [r7, #12] + 1988 0086 1A68 ldr r2, [r3] + 1989 .loc 1 1503 77 + 1990 0088 BB68 ldr r3, [r7, #8] + 1991 008a 1B33 adds r3, r3, #27 + 1992 008c 1B01 lsls r3, r3, #4 + 1993 008e 1344 add r3, r3, r2 + ARM GAS /tmp/ccM1MpQr.s page 80 + + + 1994 0090 1B68 ldr r3, [r3] + 1995 .loc 1 1503 83 + 1996 0092 5B0D lsrs r3, r3, #21 + 1997 0094 C3F30A02 ubfx r2, r3, #0, #11 + 1998 .loc 1 1503 22 + 1999 0098 7B68 ldr r3, [r7, #4] + 2000 009a 1A60 str r2, [r3] + 2001 009c 0BE0 b .L101 + 2002 .L100: +1504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else +1506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & +1508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos; + 2003 .loc 1 1508 29 + 2004 009e FB68 ldr r3, [r7, #12] + 2005 00a0 1A68 ldr r2, [r3] + 2006 .loc 1 1508 61 + 2007 00a2 BB68 ldr r3, [r7, #8] + 2008 00a4 1B33 adds r3, r3, #27 + 2009 00a6 1B01 lsls r3, r3, #4 + 2010 00a8 1344 add r3, r3, r2 + 2011 00aa 1B68 ldr r3, [r3] + 2012 .loc 1 1508 67 + 2013 00ac DB08 lsrs r3, r3, #3 + 2014 00ae 23F06042 bic r2, r3, #-536870912 +1507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos; + 2015 .loc 1 1507 22 + 2016 00b2 7B68 ldr r3, [r7, #4] + 2017 00b4 5A60 str r2, [r3, #4] + 2018 .L101: +1509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR); + 2019 .loc 1 1510 40 + 2020 00b6 FB68 ldr r3, [r7, #12] + 2021 00b8 1A68 ldr r2, [r3] + 2022 .loc 1 1510 72 + 2023 00ba BB68 ldr r3, [r7, #8] + 2024 00bc 1B33 adds r3, r3, #27 + 2025 00be 1B01 lsls r3, r3, #4 + 2026 00c0 1344 add r3, r3, r2 + 2027 00c2 1B68 ldr r3, [r3] + 2028 .loc 1 1510 34 + 2029 00c4 03F00202 and r2, r3, #2 + 2030 .loc 1 1510 18 + 2031 00c8 7B68 ldr r3, [r7, #4] + 2032 00ca DA60 str r2, [r3, #12] +1511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (((CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos) >= 8U) + 2033 .loc 1 1511 31 + 2034 00cc FB68 ldr r3, [r7, #12] + 2035 00ce 1A68 ldr r2, [r3] + 2036 .loc 1 1511 63 + 2037 00d0 BB68 ldr r3, [r7, #8] + 2038 00d2 1B33 adds r3, r3, #27 + 2039 00d4 1B01 lsls r3, r3, #4 + 2040 00d6 1344 add r3, r3, r2 + 2041 00d8 0433 adds r3, r3, #4 + ARM GAS /tmp/ccM1MpQr.s page 81 + + + 2042 00da 1B68 ldr r3, [r3] + 2043 .loc 1 1511 92 + 2044 00dc 03F00803 and r3, r3, #8 + 2045 .loc 1 1511 8 + 2046 00e0 002B cmp r3, #0 + 2047 00e2 03D0 beq .L102 +1512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Truncate DLC to 8 if received field is over range */ +1514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** pHeader->DLC = 8U; + 2048 .loc 1 1514 20 + 2049 00e4 7B68 ldr r3, [r7, #4] + 2050 00e6 0822 movs r2, #8 + 2051 00e8 1A61 str r2, [r3, #16] + 2052 00ea 0BE0 b .L103 + 2053 .L102: +1515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else +1517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_P + 2054 .loc 1 1518 43 + 2055 00ec FB68 ldr r3, [r7, #12] + 2056 00ee 1A68 ldr r2, [r3] + 2057 .loc 1 1518 75 + 2058 00f0 BB68 ldr r3, [r7, #8] + 2059 00f2 1B33 adds r3, r3, #27 + 2060 00f4 1B01 lsls r3, r3, #4 + 2061 00f6 1344 add r3, r3, r2 + 2062 00f8 0433 adds r3, r3, #4 + 2063 00fa 1B68 ldr r3, [r3] + 2064 .loc 1 1518 82 + 2065 00fc 03F00F02 and r2, r3, #15 + 2066 .loc 1 1518 20 + 2067 0100 7B68 ldr r3, [r7, #4] + 2068 0102 1A61 str r2, [r3, #16] + 2069 .L103: +1519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_ + 2070 .loc 1 1520 54 + 2071 0104 FB68 ldr r3, [r7, #12] + 2072 0106 1A68 ldr r2, [r3] + 2073 .loc 1 1520 86 + 2074 0108 BB68 ldr r3, [r7, #8] + 2075 010a 1B33 adds r3, r3, #27 + 2076 010c 1B01 lsls r3, r3, #4 + 2077 010e 1344 add r3, r3, r2 + 2078 0110 0433 adds r3, r3, #4 + 2079 0112 1B68 ldr r3, [r3] + 2080 .loc 1 1520 93 + 2081 0114 1B0A lsrs r3, r3, #8 + 2082 0116 DAB2 uxtb r2, r3 + 2083 .loc 1 1520 31 + 2084 0118 7B68 ldr r3, [r7, #4] + 2085 011a 9A61 str r2, [r3, #24] +1521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_ + 2086 .loc 1 1521 48 + 2087 011c FB68 ldr r3, [r7, #12] + 2088 011e 1A68 ldr r2, [r3] + ARM GAS /tmp/ccM1MpQr.s page 82 + + + 2089 .loc 1 1521 80 + 2090 0120 BB68 ldr r3, [r7, #8] + 2091 0122 1B33 adds r3, r3, #27 + 2092 0124 1B01 lsls r3, r3, #4 + 2093 0126 1344 add r3, r3, r2 + 2094 0128 0433 adds r3, r3, #4 + 2095 012a 1B68 ldr r3, [r3] + 2096 .loc 1 1521 87 + 2097 012c 1B0C lsrs r3, r3, #16 + 2098 012e 9AB2 uxth r2, r3 + 2099 .loc 1 1521 24 + 2100 0130 7B68 ldr r3, [r7, #4] + 2101 0132 5A61 str r2, [r3, #20] +1522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Get the data */ +1524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R + 2102 .loc 1 1524 49 + 2103 0134 FB68 ldr r3, [r7, #12] + 2104 0136 1A68 ldr r2, [r3] + 2105 .loc 1 1524 81 + 2106 0138 BB68 ldr r3, [r7, #8] + 2107 013a 1B01 lsls r3, r3, #4 + 2108 013c 1344 add r3, r3, r2 + 2109 013e 03F5DC73 add r3, r3, #440 + 2110 0142 1B68 ldr r3, [r3] + 2111 .loc 1 1524 16 + 2112 0144 DAB2 uxtb r2, r3 + 2113 .loc 1 1524 14 + 2114 0146 3B68 ldr r3, [r7] + 2115 0148 1A70 strb r2, [r3] +1525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R + 2116 .loc 1 1525 49 + 2117 014a FB68 ldr r3, [r7, #12] + 2118 014c 1A68 ldr r2, [r3] + 2119 .loc 1 1525 81 + 2120 014e BB68 ldr r3, [r7, #8] + 2121 0150 1B01 lsls r3, r3, #4 + 2122 0152 1344 add r3, r3, r2 + 2123 0154 03F5DC73 add r3, r3, #440 + 2124 0158 1B68 ldr r3, [r3] + 2125 .loc 1 1525 88 + 2126 015a 1A0A lsrs r2, r3, #8 + 2127 .loc 1 1525 10 + 2128 015c 3B68 ldr r3, [r7] + 2129 015e 0133 adds r3, r3, #1 + 2130 .loc 1 1525 16 + 2131 0160 D2B2 uxtb r2, r2 + 2132 .loc 1 1525 14 + 2133 0162 1A70 strb r2, [r3] +1526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R + 2134 .loc 1 1526 49 + 2135 0164 FB68 ldr r3, [r7, #12] + 2136 0166 1A68 ldr r2, [r3] + 2137 .loc 1 1526 81 + 2138 0168 BB68 ldr r3, [r7, #8] + 2139 016a 1B01 lsls r3, r3, #4 + 2140 016c 1344 add r3, r3, r2 + ARM GAS /tmp/ccM1MpQr.s page 83 + + + 2141 016e 03F5DC73 add r3, r3, #440 + 2142 0172 1B68 ldr r3, [r3] + 2143 .loc 1 1526 88 + 2144 0174 1A0C lsrs r2, r3, #16 + 2145 .loc 1 1526 10 + 2146 0176 3B68 ldr r3, [r7] + 2147 0178 0233 adds r3, r3, #2 + 2148 .loc 1 1526 16 + 2149 017a D2B2 uxtb r2, r2 + 2150 .loc 1 1526 14 + 2151 017c 1A70 strb r2, [r3] +1527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R + 2152 .loc 1 1527 49 + 2153 017e FB68 ldr r3, [r7, #12] + 2154 0180 1A68 ldr r2, [r3] + 2155 .loc 1 1527 81 + 2156 0182 BB68 ldr r3, [r7, #8] + 2157 0184 1B01 lsls r3, r3, #4 + 2158 0186 1344 add r3, r3, r2 + 2159 0188 03F5DC73 add r3, r3, #440 + 2160 018c 1B68 ldr r3, [r3] + 2161 .loc 1 1527 88 + 2162 018e 1A0E lsrs r2, r3, #24 + 2163 .loc 1 1527 10 + 2164 0190 3B68 ldr r3, [r7] + 2165 0192 0333 adds r3, r3, #3 + 2166 .loc 1 1527 16 + 2167 0194 D2B2 uxtb r2, r2 + 2168 .loc 1 1527 14 + 2169 0196 1A70 strb r2, [r3] +1528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R + 2170 .loc 1 1528 49 + 2171 0198 FB68 ldr r3, [r7, #12] + 2172 019a 1A68 ldr r2, [r3] + 2173 .loc 1 1528 81 + 2174 019c BB68 ldr r3, [r7, #8] + 2175 019e 1B01 lsls r3, r3, #4 + 2176 01a0 1344 add r3, r3, r2 + 2177 01a2 03F5DE73 add r3, r3, #444 + 2178 01a6 1A68 ldr r2, [r3] + 2179 .loc 1 1528 10 + 2180 01a8 3B68 ldr r3, [r7] + 2181 01aa 0433 adds r3, r3, #4 + 2182 .loc 1 1528 16 + 2183 01ac D2B2 uxtb r2, r2 + 2184 .loc 1 1528 14 + 2185 01ae 1A70 strb r2, [r3] +1529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R + 2186 .loc 1 1529 49 + 2187 01b0 FB68 ldr r3, [r7, #12] + 2188 01b2 1A68 ldr r2, [r3] + 2189 .loc 1 1529 81 + 2190 01b4 BB68 ldr r3, [r7, #8] + 2191 01b6 1B01 lsls r3, r3, #4 + 2192 01b8 1344 add r3, r3, r2 + 2193 01ba 03F5DE73 add r3, r3, #444 + 2194 01be 1B68 ldr r3, [r3] + ARM GAS /tmp/ccM1MpQr.s page 84 + + + 2195 .loc 1 1529 88 + 2196 01c0 1A0A lsrs r2, r3, #8 + 2197 .loc 1 1529 10 + 2198 01c2 3B68 ldr r3, [r7] + 2199 01c4 0533 adds r3, r3, #5 + 2200 .loc 1 1529 16 + 2201 01c6 D2B2 uxtb r2, r2 + 2202 .loc 1 1529 14 + 2203 01c8 1A70 strb r2, [r3] +1530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R + 2204 .loc 1 1530 49 + 2205 01ca FB68 ldr r3, [r7, #12] + 2206 01cc 1A68 ldr r2, [r3] + 2207 .loc 1 1530 81 + 2208 01ce BB68 ldr r3, [r7, #8] + 2209 01d0 1B01 lsls r3, r3, #4 + 2210 01d2 1344 add r3, r3, r2 + 2211 01d4 03F5DE73 add r3, r3, #444 + 2212 01d8 1B68 ldr r3, [r3] + 2213 .loc 1 1530 88 + 2214 01da 1A0C lsrs r2, r3, #16 + 2215 .loc 1 1530 10 + 2216 01dc 3B68 ldr r3, [r7] + 2217 01de 0633 adds r3, r3, #6 + 2218 .loc 1 1530 16 + 2219 01e0 D2B2 uxtb r2, r2 + 2220 .loc 1 1530 14 + 2221 01e2 1A70 strb r2, [r3] +1531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R + 2222 .loc 1 1531 49 + 2223 01e4 FB68 ldr r3, [r7, #12] + 2224 01e6 1A68 ldr r2, [r3] + 2225 .loc 1 1531 81 + 2226 01e8 BB68 ldr r3, [r7, #8] + 2227 01ea 1B01 lsls r3, r3, #4 + 2228 01ec 1344 add r3, r3, r2 + 2229 01ee 03F5DE73 add r3, r3, #444 + 2230 01f2 1B68 ldr r3, [r3] + 2231 .loc 1 1531 88 + 2232 01f4 1A0E lsrs r2, r3, #24 + 2233 .loc 1 1531 10 + 2234 01f6 3B68 ldr r3, [r7] + 2235 01f8 0733 adds r3, r3, #7 + 2236 .loc 1 1531 16 + 2237 01fa D2B2 uxtb r2, r2 + 2238 .loc 1 1531 14 + 2239 01fc 1A70 strb r2, [r3] +1532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Release the FIFO */ +1534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ + 2240 .loc 1 1534 8 + 2241 01fe BB68 ldr r3, [r7, #8] + 2242 0200 002B cmp r3, #0 + 2243 0202 08D1 bne .L104 +1535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Release RX FIFO 0 */ +1537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0); + ARM GAS /tmp/ccM1MpQr.s page 85 + + + 2244 .loc 1 1537 7 + 2245 0204 FB68 ldr r3, [r7, #12] + 2246 0206 1B68 ldr r3, [r3] + 2247 0208 DA68 ldr r2, [r3, #12] + 2248 020a FB68 ldr r3, [r7, #12] + 2249 020c 1B68 ldr r3, [r3] + 2250 020e 42F02002 orr r2, r2, #32 + 2251 0212 DA60 str r2, [r3, #12] + 2252 0214 07E0 b .L105 + 2253 .L104: +1538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else /* Rx element is assigned to Rx FIFO 1 */ +1540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Release RX FIFO 1 */ +1542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1); + 2254 .loc 1 1542 7 + 2255 0216 FB68 ldr r3, [r7, #12] + 2256 0218 1B68 ldr r3, [r3] + 2257 021a 1A69 ldr r2, [r3, #16] + 2258 021c FB68 ldr r3, [r7, #12] + 2259 021e 1B68 ldr r3, [r3] + 2260 0220 42F02002 orr r2, r2, #32 + 2261 0224 1A61 str r2, [r3, #16] + 2262 .L105: +1543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return function status */ +1546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_OK; + 2263 .loc 1 1546 12 + 2264 0226 0023 movs r3, #0 + 2265 0228 06E0 b .L99 + 2266 .L96: +1547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else +1549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code */ +1551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + 2267 .loc 1 1551 9 + 2268 022a FB68 ldr r3, [r7, #12] + 2269 022c 5B6A ldr r3, [r3, #36] + 2270 .loc 1 1551 21 + 2271 022e 43F48022 orr r2, r3, #262144 + 2272 0232 FB68 ldr r3, [r7, #12] + 2273 0234 5A62 str r2, [r3, #36] +1552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_ERROR; + 2274 .loc 1 1553 12 + 2275 0236 0123 movs r3, #1 + 2276 .L99: +1554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 2277 .loc 1 1555 1 + 2278 0238 1846 mov r0, r3 + 2279 023a 1C37 adds r7, r7, #28 + 2280 .cfi_def_cfa_offset 4 + 2281 023c BD46 mov sp, r7 + 2282 .cfi_def_cfa_register 13 + ARM GAS /tmp/ccM1MpQr.s page 86 + + + 2283 @ sp needed + 2284 023e 5DF8047B ldr r7, [sp], #4 + 2285 .cfi_restore 7 + 2286 .cfi_def_cfa_offset 0 + 2287 0242 7047 bx lr + 2288 .cfi_endproc + 2289 .LFE145: + 2291 .section .text.HAL_CAN_GetRxFifoFillLevel,"ax",%progbits + 2292 .align 1 + 2293 .global HAL_CAN_GetRxFifoFillLevel + 2294 .syntax unified + 2295 .thumb + 2296 .thumb_func + 2298 HAL_CAN_GetRxFifoFillLevel: + 2299 .LFB146: +1556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +1558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Return Rx FIFO fill level. +1559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to an CAN_HandleTypeDef structure that contains +1560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +1561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param RxFifo Rx FIFO. +1562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * This parameter can be a value of @arg CAN_receive_FIFO_number. +1563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval Number of messages available in Rx FIFO. +1564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +1565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t HAL_CAN_GetRxFifoFillLevel(const CAN_HandleTypeDef *hcan, uint32_t RxFifo) +1566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2300 .loc 1 1566 1 + 2301 .cfi_startproc + 2302 @ args = 0, pretend = 0, frame = 16 + 2303 @ frame_needed = 1, uses_anonymous_args = 0 + 2304 @ link register save eliminated. + 2305 0000 80B4 push {r7} + 2306 .cfi_def_cfa_offset 4 + 2307 .cfi_offset 7, -4 + 2308 0002 85B0 sub sp, sp, #20 + 2309 .cfi_def_cfa_offset 24 + 2310 0004 00AF add r7, sp, #0 + 2311 .cfi_def_cfa_register 7 + 2312 0006 7860 str r0, [r7, #4] + 2313 0008 3960 str r1, [r7] +1567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t filllevel = 0U; + 2314 .loc 1 1567 12 + 2315 000a 0023 movs r3, #0 + 2316 000c FB60 str r3, [r7, #12] +1568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_StateTypeDef state = hcan->State; + 2317 .loc 1 1568 24 + 2318 000e 7B68 ldr r3, [r7, #4] + 2319 0010 93F82030 ldrb r3, [r3, #32] + 2320 0014 FB72 strb r3, [r7, #11] +1569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check function parameters */ +1571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_RX_FIFO(RxFifo)); +1572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((state == HAL_CAN_STATE_READY) || + 2321 .loc 1 1573 6 + 2322 0016 FB7A ldrb r3, [r7, #11] @ zero_extendqisi2 + 2323 0018 012B cmp r3, #1 + ARM GAS /tmp/ccM1MpQr.s page 87 + + + 2324 001a 02D0 beq .L107 + 2325 .loc 1 1573 38 discriminator 1 + 2326 001c FB7A ldrb r3, [r7, #11] @ zero_extendqisi2 + 2327 001e 022B cmp r3, #2 + 2328 0020 0FD1 bne .L108 + 2329 .L107: +1574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (state == HAL_CAN_STATE_LISTENING)) +1575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (RxFifo == CAN_RX_FIFO0) + 2330 .loc 1 1576 8 + 2331 0022 3B68 ldr r3, [r7] + 2332 0024 002B cmp r3, #0 + 2333 0026 06D1 bne .L109 +1577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** filllevel = hcan->Instance->RF0R & CAN_RF0R_FMP0; + 2334 .loc 1 1578 23 + 2335 0028 7B68 ldr r3, [r7, #4] + 2336 002a 1B68 ldr r3, [r3] + 2337 .loc 1 1578 33 + 2338 002c DB68 ldr r3, [r3, #12] + 2339 .loc 1 1578 17 + 2340 002e 03F00303 and r3, r3, #3 + 2341 0032 FB60 str r3, [r7, #12] + 2342 0034 05E0 b .L108 + 2343 .L109: +1579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else /* RxFifo == CAN_RX_FIFO1 */ +1581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** filllevel = hcan->Instance->RF1R & CAN_RF1R_FMP1; + 2344 .loc 1 1582 23 + 2345 0036 7B68 ldr r3, [r7, #4] + 2346 0038 1B68 ldr r3, [r3] + 2347 .loc 1 1582 33 + 2348 003a 1B69 ldr r3, [r3, #16] + 2349 .loc 1 1582 17 + 2350 003c 03F00303 and r3, r3, #3 + 2351 0040 FB60 str r3, [r7, #12] + 2352 .L108: +1583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return Rx FIFO fill level */ +1587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return filllevel; + 2353 .loc 1 1587 10 + 2354 0042 FB68 ldr r3, [r7, #12] +1588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 2355 .loc 1 1588 1 + 2356 0044 1846 mov r0, r3 + 2357 0046 1437 adds r7, r7, #20 + 2358 .cfi_def_cfa_offset 4 + 2359 0048 BD46 mov sp, r7 + 2360 .cfi_def_cfa_register 13 + 2361 @ sp needed + 2362 004a 5DF8047B ldr r7, [sp], #4 + 2363 .cfi_restore 7 + 2364 .cfi_def_cfa_offset 0 + 2365 004e 7047 bx lr + ARM GAS /tmp/ccM1MpQr.s page 88 + + + 2366 .cfi_endproc + 2367 .LFE146: + 2369 .section .text.HAL_CAN_ActivateNotification,"ax",%progbits + 2370 .align 1 + 2371 .global HAL_CAN_ActivateNotification + 2372 .syntax unified + 2373 .thumb + 2374 .thumb_func + 2376 HAL_CAN_ActivateNotification: + 2377 .LFB147: +1589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +1591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @} +1592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +1593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** @defgroup CAN_Exported_Functions_Group4 Interrupts management +1595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Interrupts management +1596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * +1597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** @verbatim +1598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ============================================================================== +1599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ##### Interrupts management ##### +1600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ============================================================================== +1601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** [..] This section provides functions allowing to: +1602:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_ActivateNotification : Enable interrupts +1603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_DeactivateNotification : Disable interrupts +1604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_IRQHandler : Handles CAN interrupt request +1605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** @endverbatim +1607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @{ +1608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +1609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +1611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Enable interrupts. +1612:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to an CAN_HandleTypeDef structure that contains +1613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +1614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param ActiveITs indicates which interrupts will be enabled. +1615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * This parameter can be any combination of @arg CAN_Interrupts. +1616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval HAL status +1617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +1618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs) +1619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2378 .loc 1 1619 1 + 2379 .cfi_startproc + 2380 @ args = 0, pretend = 0, frame = 16 + 2381 @ frame_needed = 1, uses_anonymous_args = 0 + 2382 @ link register save eliminated. + 2383 0000 80B4 push {r7} + 2384 .cfi_def_cfa_offset 4 + 2385 .cfi_offset 7, -4 + 2386 0002 85B0 sub sp, sp, #20 + 2387 .cfi_def_cfa_offset 24 + 2388 0004 00AF add r7, sp, #0 + 2389 .cfi_def_cfa_register 7 + 2390 0006 7860 str r0, [r7, #4] + 2391 0008 3960 str r1, [r7] +1620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_StateTypeDef state = hcan->State; + 2392 .loc 1 1620 24 + ARM GAS /tmp/ccM1MpQr.s page 89 + + + 2393 000a 7B68 ldr r3, [r7, #4] + 2394 000c 93F82030 ldrb r3, [r3, #32] + 2395 0010 FB73 strb r3, [r7, #15] +1621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check function parameters */ +1623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_IT(ActiveITs)); +1624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((state == HAL_CAN_STATE_READY) || + 2396 .loc 1 1625 6 + 2397 0012 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 2398 0014 012B cmp r3, #1 + 2399 0016 02D0 beq .L112 + 2400 .loc 1 1625 38 discriminator 1 + 2401 0018 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 2402 001a 022B cmp r3, #2 + 2403 001c 09D1 bne .L113 + 2404 .L112: +1626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (state == HAL_CAN_STATE_LISTENING)) +1627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Enable the selected interrupts */ +1629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __HAL_CAN_ENABLE_IT(hcan, ActiveITs); + 2405 .loc 1 1629 5 + 2406 001e 7B68 ldr r3, [r7, #4] + 2407 0020 1B68 ldr r3, [r3] + 2408 0022 5969 ldr r1, [r3, #20] + 2409 0024 7B68 ldr r3, [r7, #4] + 2410 0026 1B68 ldr r3, [r3] + 2411 0028 3A68 ldr r2, [r7] + 2412 002a 0A43 orrs r2, r2, r1 + 2413 002c 5A61 str r2, [r3, #20] +1630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return function status */ +1632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_OK; + 2414 .loc 1 1632 12 + 2415 002e 0023 movs r3, #0 + 2416 0030 06E0 b .L114 + 2417 .L113: +1633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else +1635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code */ +1637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + 2418 .loc 1 1637 9 + 2419 0032 7B68 ldr r3, [r7, #4] + 2420 0034 5B6A ldr r3, [r3, #36] + 2421 .loc 1 1637 21 + 2422 0036 43F48022 orr r2, r3, #262144 + 2423 003a 7B68 ldr r3, [r7, #4] + 2424 003c 5A62 str r2, [r3, #36] +1638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_ERROR; + 2425 .loc 1 1639 12 + 2426 003e 0123 movs r3, #1 + 2427 .L114: +1640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 2428 .loc 1 1641 1 + ARM GAS /tmp/ccM1MpQr.s page 90 + + + 2429 0040 1846 mov r0, r3 + 2430 0042 1437 adds r7, r7, #20 + 2431 .cfi_def_cfa_offset 4 + 2432 0044 BD46 mov sp, r7 + 2433 .cfi_def_cfa_register 13 + 2434 @ sp needed + 2435 0046 5DF8047B ldr r7, [sp], #4 + 2436 .cfi_restore 7 + 2437 .cfi_def_cfa_offset 0 + 2438 004a 7047 bx lr + 2439 .cfi_endproc + 2440 .LFE147: + 2442 .section .text.HAL_CAN_DeactivateNotification,"ax",%progbits + 2443 .align 1 + 2444 .global HAL_CAN_DeactivateNotification + 2445 .syntax unified + 2446 .thumb + 2447 .thumb_func + 2449 HAL_CAN_DeactivateNotification: + 2450 .LFB148: +1642:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +1644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Disable interrupts. +1645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to an CAN_HandleTypeDef structure that contains +1646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +1647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param InactiveITs indicates which interrupts will be disabled. +1648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * This parameter can be any combination of @arg CAN_Interrupts. +1649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval HAL status +1650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +1651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs) +1652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2451 .loc 1 1652 1 + 2452 .cfi_startproc + 2453 @ args = 0, pretend = 0, frame = 16 + 2454 @ frame_needed = 1, uses_anonymous_args = 0 + 2455 @ link register save eliminated. + 2456 0000 80B4 push {r7} + 2457 .cfi_def_cfa_offset 4 + 2458 .cfi_offset 7, -4 + 2459 0002 85B0 sub sp, sp, #20 + 2460 .cfi_def_cfa_offset 24 + 2461 0004 00AF add r7, sp, #0 + 2462 .cfi_def_cfa_register 7 + 2463 0006 7860 str r0, [r7, #4] + 2464 0008 3960 str r1, [r7] +1653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_StateTypeDef state = hcan->State; + 2465 .loc 1 1653 24 + 2466 000a 7B68 ldr r3, [r7, #4] + 2467 000c 93F82030 ldrb r3, [r3, #32] + 2468 0010 FB73 strb r3, [r7, #15] +1654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1655:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check function parameters */ +1656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** assert_param(IS_CAN_IT(InactiveITs)); +1657:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((state == HAL_CAN_STATE_READY) || + 2469 .loc 1 1658 6 + 2470 0012 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + ARM GAS /tmp/ccM1MpQr.s page 91 + + + 2471 0014 012B cmp r3, #1 + 2472 0016 02D0 beq .L116 + 2473 .loc 1 1658 38 discriminator 1 + 2474 0018 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 2475 001a 022B cmp r3, #2 + 2476 001c 0AD1 bne .L117 + 2477 .L116: +1659:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (state == HAL_CAN_STATE_LISTENING)) +1660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Disable the selected interrupts */ +1662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __HAL_CAN_DISABLE_IT(hcan, InactiveITs); + 2478 .loc 1 1662 5 + 2479 001e 7B68 ldr r3, [r7, #4] + 2480 0020 1B68 ldr r3, [r3] + 2481 0022 5969 ldr r1, [r3, #20] + 2482 0024 3B68 ldr r3, [r7] + 2483 0026 DA43 mvns r2, r3 + 2484 0028 7B68 ldr r3, [r7, #4] + 2485 002a 1B68 ldr r3, [r3] + 2486 002c 0A40 ands r2, r2, r1 + 2487 002e 5A61 str r2, [r3, #20] +1663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1664:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return function status */ +1665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_OK; + 2488 .loc 1 1665 12 + 2489 0030 0023 movs r3, #0 + 2490 0032 06E0 b .L118 + 2491 .L117: +1666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else +1668:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code */ +1670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + 2492 .loc 1 1670 9 + 2493 0034 7B68 ldr r3, [r7, #4] + 2494 0036 5B6A ldr r3, [r3, #36] + 2495 .loc 1 1670 21 + 2496 0038 43F48022 orr r2, r3, #262144 + 2497 003c 7B68 ldr r3, [r7, #4] + 2498 003e 5A62 str r2, [r3, #36] +1671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return HAL_ERROR; + 2499 .loc 1 1672 12 + 2500 0040 0123 movs r3, #1 + 2501 .L118: +1673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 2502 .loc 1 1674 1 + 2503 0042 1846 mov r0, r3 + 2504 0044 1437 adds r7, r7, #20 + 2505 .cfi_def_cfa_offset 4 + 2506 0046 BD46 mov sp, r7 + 2507 .cfi_def_cfa_register 13 + 2508 @ sp needed + 2509 0048 5DF8047B ldr r7, [sp], #4 + 2510 .cfi_restore 7 + 2511 .cfi_def_cfa_offset 0 + ARM GAS /tmp/ccM1MpQr.s page 92 + + + 2512 004c 7047 bx lr + 2513 .cfi_endproc + 2514 .LFE148: + 2516 .section .text.HAL_CAN_IRQHandler,"ax",%progbits + 2517 .align 1 + 2518 .global HAL_CAN_IRQHandler + 2519 .syntax unified + 2520 .thumb + 2521 .thumb_func + 2523 HAL_CAN_IRQHandler: + 2524 .LFB149: +1675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +1677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Handles CAN interrupt request +1678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains +1679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +1680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval None +1681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +1682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) +1683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 2525 .loc 1 1683 1 + 2526 .cfi_startproc + 2527 @ args = 0, pretend = 0, frame = 40 + 2528 @ frame_needed = 1, uses_anonymous_args = 0 + 2529 0000 80B5 push {r7, lr} + 2530 .cfi_def_cfa_offset 8 + 2531 .cfi_offset 7, -8 + 2532 .cfi_offset 14, -4 + 2533 0002 8AB0 sub sp, sp, #40 + 2534 .cfi_def_cfa_offset 48 + 2535 0004 00AF add r7, sp, #0 + 2536 .cfi_def_cfa_register 7 + 2537 0006 7860 str r0, [r7, #4] +1684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t errorcode = HAL_CAN_ERROR_NONE; + 2538 .loc 1 1684 12 + 2539 0008 0023 movs r3, #0 + 2540 000a 7B62 str r3, [r7, #36] +1685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t interrupts = READ_REG(hcan->Instance->IER); + 2541 .loc 1 1685 25 + 2542 000c 7B68 ldr r3, [r7, #4] + 2543 000e 1B68 ldr r3, [r3] + 2544 .loc 1 1685 12 + 2545 0010 5B69 ldr r3, [r3, #20] + 2546 0012 3B62 str r3, [r7, #32] +1686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t msrflags = READ_REG(hcan->Instance->MSR); + 2547 .loc 1 1686 23 + 2548 0014 7B68 ldr r3, [r7, #4] + 2549 0016 1B68 ldr r3, [r3] + 2550 .loc 1 1686 12 + 2551 0018 5B68 ldr r3, [r3, #4] + 2552 001a FB61 str r3, [r7, #28] +1687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t tsrflags = READ_REG(hcan->Instance->TSR); + 2553 .loc 1 1687 23 + 2554 001c 7B68 ldr r3, [r7, #4] + 2555 001e 1B68 ldr r3, [r3] + 2556 .loc 1 1687 12 + 2557 0020 9B68 ldr r3, [r3, #8] + ARM GAS /tmp/ccM1MpQr.s page 93 + + + 2558 0022 BB61 str r3, [r7, #24] +1688:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R); + 2559 .loc 1 1688 24 + 2560 0024 7B68 ldr r3, [r7, #4] + 2561 0026 1B68 ldr r3, [r3] + 2562 .loc 1 1688 12 + 2563 0028 DB68 ldr r3, [r3, #12] + 2564 002a 7B61 str r3, [r7, #20] +1689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R); + 2565 .loc 1 1689 24 + 2566 002c 7B68 ldr r3, [r7, #4] + 2567 002e 1B68 ldr r3, [r3] + 2568 .loc 1 1689 12 + 2569 0030 1B69 ldr r3, [r3, #16] + 2570 0032 3B61 str r3, [r7, #16] +1690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t esrflags = READ_REG(hcan->Instance->ESR); + 2571 .loc 1 1690 23 + 2572 0034 7B68 ldr r3, [r7, #4] + 2573 0036 1B68 ldr r3, [r3] + 2574 .loc 1 1690 12 + 2575 0038 9B69 ldr r3, [r3, #24] + 2576 003a FB60 str r3, [r7, #12] +1691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Transmit Mailbox empty interrupt management *****************************/ +1693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U) + 2577 .loc 1 1693 19 + 2578 003c 3B6A ldr r3, [r7, #32] + 2579 003e 03F00103 and r3, r3, #1 + 2580 .loc 1 1693 6 + 2581 0042 002B cmp r3, #0 + 2582 0044 7CD0 beq .L120 +1694:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Transmit Mailbox 0 management *****************************************/ +1696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((tsrflags & CAN_TSR_RQCP0) != 0U) + 2583 .loc 1 1696 19 + 2584 0046 BB69 ldr r3, [r7, #24] + 2585 0048 03F00103 and r3, r3, #1 + 2586 .loc 1 1696 8 + 2587 004c 002B cmp r3, #0 + 2588 004e 23D0 beq .L121 +1697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */ +1699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0); + 2589 .loc 1 1699 7 + 2590 0050 7B68 ldr r3, [r7, #4] + 2591 0052 1B68 ldr r3, [r3] + 2592 0054 0122 movs r2, #1 + 2593 0056 9A60 str r2, [r3, #8] +1700:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((tsrflags & CAN_TSR_TXOK0) != 0U) + 2594 .loc 1 1701 21 + 2595 0058 BB69 ldr r3, [r7, #24] + 2596 005a 03F00203 and r3, r3, #2 + 2597 .loc 1 1701 10 + 2598 005e 002B cmp r3, #0 + 2599 0060 03D0 beq .L122 +1702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + ARM GAS /tmp/ccM1MpQr.s page 94 + + +1703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Transmission Mailbox 0 complete callback */ +1704:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +1705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call registered callback*/ +1706:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->TxMailbox0CompleteCallback(hcan); +1707:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #else +1708:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call weak (surcharged) callback */ +1709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_TxMailbox0CompleteCallback(hcan); + 2600 .loc 1 1709 9 + 2601 0062 7868 ldr r0, [r7, #4] + 2602 0064 FFF7FEFF bl HAL_CAN_TxMailbox0CompleteCallback + 2603 0068 16E0 b .L121 + 2604 .L122: +1710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ +1711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else +1713:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((tsrflags & CAN_TSR_ALST0) != 0U) + 2605 .loc 1 1714 23 + 2606 006a BB69 ldr r3, [r7, #24] + 2607 006c 03F00403 and r3, r3, #4 + 2608 .loc 1 1714 12 + 2609 0070 002B cmp r3, #0 + 2610 0072 04D0 beq .L123 +1715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1716:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code */ +1717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** errorcode |= HAL_CAN_ERROR_TX_ALST0; + 2611 .loc 1 1717 21 + 2612 0074 7B6A ldr r3, [r7, #36] + 2613 0076 43F40063 orr r3, r3, #2048 + 2614 007a 7B62 str r3, [r7, #36] + 2615 007c 0CE0 b .L121 + 2616 .L123: +1718:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else if ((tsrflags & CAN_TSR_TERR0) != 0U) + 2617 .loc 1 1719 28 + 2618 007e BB69 ldr r3, [r7, #24] + 2619 0080 03F00803 and r3, r3, #8 + 2620 .loc 1 1719 17 + 2621 0084 002B cmp r3, #0 + 2622 0086 04D0 beq .L124 +1720:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code */ +1722:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** errorcode |= HAL_CAN_ERROR_TX_TERR0; + 2623 .loc 1 1722 21 + 2624 0088 7B6A ldr r3, [r7, #36] + 2625 008a 43F48053 orr r3, r3, #4096 + 2626 008e 7B62 str r3, [r7, #36] + 2627 0090 02E0 b .L121 + 2628 .L124: +1723:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1724:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else +1725:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Transmission Mailbox 0 abort callback */ +1727:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +1728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call registered callback*/ +1729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->TxMailbox0AbortCallback(hcan); +1730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #else + ARM GAS /tmp/ccM1MpQr.s page 95 + + +1731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call weak (surcharged) callback */ +1732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_TxMailbox0AbortCallback(hcan); + 2629 .loc 1 1732 11 + 2630 0092 7868 ldr r0, [r7, #4] + 2631 0094 FFF7FEFF bl HAL_CAN_TxMailbox0AbortCallback + 2632 .L121: +1733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ +1734:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1737:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Transmit Mailbox 1 management *****************************************/ +1739:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((tsrflags & CAN_TSR_RQCP1) != 0U) + 2633 .loc 1 1739 19 + 2634 0098 BB69 ldr r3, [r7, #24] + 2635 009a 03F48073 and r3, r3, #256 + 2636 .loc 1 1739 8 + 2637 009e 002B cmp r3, #0 + 2638 00a0 24D0 beq .L125 +1740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */ +1742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1); + 2639 .loc 1 1742 7 + 2640 00a2 7B68 ldr r3, [r7, #4] + 2641 00a4 1B68 ldr r3, [r3] + 2642 00a6 4FF48072 mov r2, #256 + 2643 00aa 9A60 str r2, [r3, #8] +1743:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((tsrflags & CAN_TSR_TXOK1) != 0U) + 2644 .loc 1 1744 21 + 2645 00ac BB69 ldr r3, [r7, #24] + 2646 00ae 03F40073 and r3, r3, #512 + 2647 .loc 1 1744 10 + 2648 00b2 002B cmp r3, #0 + 2649 00b4 03D0 beq .L126 +1745:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1746:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Transmission Mailbox 1 complete callback */ +1747:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +1748:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call registered callback*/ +1749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->TxMailbox1CompleteCallback(hcan); +1750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #else +1751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call weak (surcharged) callback */ +1752:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_TxMailbox1CompleteCallback(hcan); + 2650 .loc 1 1752 9 + 2651 00b6 7868 ldr r0, [r7, #4] + 2652 00b8 FFF7FEFF bl HAL_CAN_TxMailbox1CompleteCallback + 2653 00bc 16E0 b .L125 + 2654 .L126: +1753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ +1754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1755:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else +1756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((tsrflags & CAN_TSR_ALST1) != 0U) + 2655 .loc 1 1757 23 + 2656 00be BB69 ldr r3, [r7, #24] + 2657 00c0 03F48063 and r3, r3, #1024 + 2658 .loc 1 1757 12 + ARM GAS /tmp/ccM1MpQr.s page 96 + + + 2659 00c4 002B cmp r3, #0 + 2660 00c6 04D0 beq .L127 +1758:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code */ +1760:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** errorcode |= HAL_CAN_ERROR_TX_ALST1; + 2661 .loc 1 1760 21 + 2662 00c8 7B6A ldr r3, [r7, #36] + 2663 00ca 43F40053 orr r3, r3, #8192 + 2664 00ce 7B62 str r3, [r7, #36] + 2665 00d0 0CE0 b .L125 + 2666 .L127: +1761:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else if ((tsrflags & CAN_TSR_TERR1) != 0U) + 2667 .loc 1 1762 28 + 2668 00d2 BB69 ldr r3, [r7, #24] + 2669 00d4 03F40063 and r3, r3, #2048 + 2670 .loc 1 1762 17 + 2671 00d8 002B cmp r3, #0 + 2672 00da 04D0 beq .L128 +1763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1764:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code */ +1765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** errorcode |= HAL_CAN_ERROR_TX_TERR1; + 2673 .loc 1 1765 21 + 2674 00dc 7B6A ldr r3, [r7, #36] + 2675 00de 43F48043 orr r3, r3, #16384 + 2676 00e2 7B62 str r3, [r7, #36] + 2677 00e4 02E0 b .L125 + 2678 .L128: +1766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1767:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else +1768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Transmission Mailbox 1 abort callback */ +1770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +1771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call registered callback*/ +1772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->TxMailbox1AbortCallback(hcan); +1773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #else +1774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call weak (surcharged) callback */ +1775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_TxMailbox1AbortCallback(hcan); + 2679 .loc 1 1775 11 + 2680 00e6 7868 ldr r0, [r7, #4] + 2681 00e8 FFF7FEFF bl HAL_CAN_TxMailbox1AbortCallback + 2682 .L125: +1776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ +1777:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1780:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Transmit Mailbox 2 management *****************************************/ +1782:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((tsrflags & CAN_TSR_RQCP2) != 0U) + 2683 .loc 1 1782 19 + 2684 00ec BB69 ldr r3, [r7, #24] + 2685 00ee 03F48033 and r3, r3, #65536 + 2686 .loc 1 1782 8 + 2687 00f2 002B cmp r3, #0 + 2688 00f4 24D0 beq .L120 +1783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */ + ARM GAS /tmp/ccM1MpQr.s page 97 + + +1785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2); + 2689 .loc 1 1785 7 + 2690 00f6 7B68 ldr r3, [r7, #4] + 2691 00f8 1B68 ldr r3, [r3] + 2692 00fa 4FF48032 mov r2, #65536 + 2693 00fe 9A60 str r2, [r3, #8] +1786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1787:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((tsrflags & CAN_TSR_TXOK2) != 0U) + 2694 .loc 1 1787 21 + 2695 0100 BB69 ldr r3, [r7, #24] + 2696 0102 03F40033 and r3, r3, #131072 + 2697 .loc 1 1787 10 + 2698 0106 002B cmp r3, #0 + 2699 0108 03D0 beq .L129 +1788:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Transmission Mailbox 2 complete callback */ +1790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +1791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call registered callback*/ +1792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->TxMailbox2CompleteCallback(hcan); +1793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #else +1794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call weak (surcharged) callback */ +1795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_TxMailbox2CompleteCallback(hcan); + 2700 .loc 1 1795 9 + 2701 010a 7868 ldr r0, [r7, #4] + 2702 010c FFF7FEFF bl HAL_CAN_TxMailbox2CompleteCallback + 2703 0110 16E0 b .L120 + 2704 .L129: +1796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ +1797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1798:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else +1799:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((tsrflags & CAN_TSR_ALST2) != 0U) + 2705 .loc 1 1800 23 + 2706 0112 BB69 ldr r3, [r7, #24] + 2707 0114 03F48023 and r3, r3, #262144 + 2708 .loc 1 1800 12 + 2709 0118 002B cmp r3, #0 + 2710 011a 04D0 beq .L130 +1801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code */ +1803:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** errorcode |= HAL_CAN_ERROR_TX_ALST2; + 2711 .loc 1 1803 21 + 2712 011c 7B6A ldr r3, [r7, #36] + 2713 011e 43F40043 orr r3, r3, #32768 + 2714 0122 7B62 str r3, [r7, #36] + 2715 0124 0CE0 b .L120 + 2716 .L130: +1804:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else if ((tsrflags & CAN_TSR_TERR2) != 0U) + 2717 .loc 1 1805 28 + 2718 0126 BB69 ldr r3, [r7, #24] + 2719 0128 03F40023 and r3, r3, #524288 + 2720 .loc 1 1805 17 + 2721 012c 002B cmp r3, #0 + 2722 012e 04D0 beq .L131 +1806:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1807:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code */ + ARM GAS /tmp/ccM1MpQr.s page 98 + + +1808:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** errorcode |= HAL_CAN_ERROR_TX_TERR2; + 2723 .loc 1 1808 21 + 2724 0130 7B6A ldr r3, [r7, #36] + 2725 0132 43F48033 orr r3, r3, #65536 + 2726 0136 7B62 str r3, [r7, #36] + 2727 0138 02E0 b .L120 + 2728 .L131: +1809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else +1811:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Transmission Mailbox 2 abort callback */ +1813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +1814:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call registered callback*/ +1815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->TxMailbox2AbortCallback(hcan); +1816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #else +1817:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call weak (surcharged) callback */ +1818:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_TxMailbox2AbortCallback(hcan); + 2729 .loc 1 1818 11 + 2730 013a 7868 ldr r0, [r7, #4] + 2731 013c FFF7FEFF bl HAL_CAN_TxMailbox2AbortCallback + 2732 .L120: +1819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ +1820:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1821:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Receive FIFO 0 overrun interrupt management *****************************/ +1826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U) + 2733 .loc 1 1826 19 + 2734 0140 3B6A ldr r3, [r7, #32] + 2735 0142 03F00803 and r3, r3, #8 + 2736 .loc 1 1826 6 + 2737 0146 002B cmp r3, #0 + 2738 0148 0CD0 beq .L132 +1827:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1828:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((rf0rflags & CAN_RF0R_FOVR0) != 0U) + 2739 .loc 1 1828 20 + 2740 014a 7B69 ldr r3, [r7, #20] + 2741 014c 03F01003 and r3, r3, #16 + 2742 .loc 1 1828 8 + 2743 0150 002B cmp r3, #0 + 2744 0152 07D0 beq .L132 +1829:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1830:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Set CAN error code to Rx Fifo 0 overrun error */ +1831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** errorcode |= HAL_CAN_ERROR_RX_FOV0; + 2745 .loc 1 1831 17 + 2746 0154 7B6A ldr r3, [r7, #36] + 2747 0156 43F40073 orr r3, r3, #512 + 2748 015a 7B62 str r3, [r7, #36] +1832:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Clear FIFO0 Overrun Flag */ +1834:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); + 2749 .loc 1 1834 7 + 2750 015c 7B68 ldr r3, [r7, #4] + 2751 015e 1B68 ldr r3, [r3] + 2752 0160 1022 movs r2, #16 + ARM GAS /tmp/ccM1MpQr.s page 99 + + + 2753 0162 DA60 str r2, [r3, #12] + 2754 .L132: +1835:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1836:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Receive FIFO 0 full interrupt management ********************************/ +1839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U) + 2755 .loc 1 1839 19 + 2756 0164 3B6A ldr r3, [r7, #32] + 2757 0166 03F00403 and r3, r3, #4 + 2758 .loc 1 1839 6 + 2759 016a 002B cmp r3, #0 + 2760 016c 0BD0 beq .L133 +1840:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((rf0rflags & CAN_RF0R_FULL0) != 0U) + 2761 .loc 1 1841 20 + 2762 016e 7B69 ldr r3, [r7, #20] + 2763 0170 03F00803 and r3, r3, #8 + 2764 .loc 1 1841 8 + 2765 0174 002B cmp r3, #0 + 2766 0176 06D0 beq .L133 +1842:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1843:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Clear FIFO 0 full Flag */ +1844:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0); + 2767 .loc 1 1844 7 + 2768 0178 7B68 ldr r3, [r7, #4] + 2769 017a 1B68 ldr r3, [r3] + 2770 017c 0822 movs r2, #8 + 2771 017e DA60 str r2, [r3, #12] +1845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1846:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Receive FIFO 0 full Callback */ +1847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +1848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call registered callback*/ +1849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->RxFifo0FullCallback(hcan); +1850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #else +1851:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call weak (surcharged) callback */ +1852:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_RxFifo0FullCallback(hcan); + 2772 .loc 1 1852 7 + 2773 0180 7868 ldr r0, [r7, #4] + 2774 0182 FFF7FEFF bl HAL_CAN_RxFifo0FullCallback + 2775 .L133: +1853:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ +1854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1855:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1856:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1857:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Receive FIFO 0 message pending interrupt management *********************/ +1858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U) + 2776 .loc 1 1858 19 + 2777 0186 3B6A ldr r3, [r7, #32] + 2778 0188 03F00203 and r3, r3, #2 + 2779 .loc 1 1858 6 + 2780 018c 002B cmp r3, #0 + 2781 018e 09D0 beq .L134 +1859:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check if message is still pending */ +1861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U) + 2782 .loc 1 1861 14 + ARM GAS /tmp/ccM1MpQr.s page 100 + + + 2783 0190 7B68 ldr r3, [r7, #4] + 2784 0192 1B68 ldr r3, [r3] + 2785 .loc 1 1861 24 + 2786 0194 DB68 ldr r3, [r3, #12] + 2787 .loc 1 1861 31 + 2788 0196 03F00303 and r3, r3, #3 + 2789 .loc 1 1861 8 + 2790 019a 002B cmp r3, #0 + 2791 019c 02D0 beq .L134 +1862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Receive FIFO 0 message pending Callback */ +1864:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +1865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call registered callback*/ +1866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->RxFifo0MsgPendingCallback(hcan); +1867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #else +1868:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call weak (surcharged) callback */ +1869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_RxFifo0MsgPendingCallback(hcan); + 2792 .loc 1 1869 7 + 2793 019e 7868 ldr r0, [r7, #4] + 2794 01a0 FFF7FEFF bl HAL_CAN_RxFifo0MsgPendingCallback + 2795 .L134: +1870:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ +1871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1873:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Receive FIFO 1 overrun interrupt management *****************************/ +1875:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U) + 2796 .loc 1 1875 19 + 2797 01a4 3B6A ldr r3, [r7, #32] + 2798 01a6 03F04003 and r3, r3, #64 + 2799 .loc 1 1875 6 + 2800 01aa 002B cmp r3, #0 + 2801 01ac 0CD0 beq .L135 +1876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1877:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((rf1rflags & CAN_RF1R_FOVR1) != 0U) + 2802 .loc 1 1877 20 + 2803 01ae 3B69 ldr r3, [r7, #16] + 2804 01b0 03F01003 and r3, r3, #16 + 2805 .loc 1 1877 8 + 2806 01b4 002B cmp r3, #0 + 2807 01b6 07D0 beq .L135 +1878:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1879:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Set CAN error code to Rx Fifo 1 overrun error */ +1880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** errorcode |= HAL_CAN_ERROR_RX_FOV1; + 2808 .loc 1 1880 17 + 2809 01b8 7B6A ldr r3, [r7, #36] + 2810 01ba 43F48063 orr r3, r3, #1024 + 2811 01be 7B62 str r3, [r7, #36] +1881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Clear FIFO1 Overrun Flag */ +1883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); + 2812 .loc 1 1883 7 + 2813 01c0 7B68 ldr r3, [r7, #4] + 2814 01c2 1B68 ldr r3, [r3] + 2815 01c4 1022 movs r2, #16 + 2816 01c6 1A61 str r2, [r3, #16] + 2817 .L135: + ARM GAS /tmp/ccM1MpQr.s page 101 + + +1884:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1887:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Receive FIFO 1 full interrupt management ********************************/ +1888:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U) + 2818 .loc 1 1888 19 + 2819 01c8 3B6A ldr r3, [r7, #32] + 2820 01ca 03F02003 and r3, r3, #32 + 2821 .loc 1 1888 6 + 2822 01ce 002B cmp r3, #0 + 2823 01d0 0BD0 beq .L136 +1889:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1890:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((rf1rflags & CAN_RF1R_FULL1) != 0U) + 2824 .loc 1 1890 20 + 2825 01d2 3B69 ldr r3, [r7, #16] + 2826 01d4 03F00803 and r3, r3, #8 + 2827 .loc 1 1890 8 + 2828 01d8 002B cmp r3, #0 + 2829 01da 06D0 beq .L136 +1891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1892:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Clear FIFO 1 full Flag */ +1893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1); + 2830 .loc 1 1893 7 + 2831 01dc 7B68 ldr r3, [r7, #4] + 2832 01de 1B68 ldr r3, [r3] + 2833 01e0 0822 movs r2, #8 + 2834 01e2 1A61 str r2, [r3, #16] +1894:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1895:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Receive FIFO 1 full Callback */ +1896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +1897:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call registered callback*/ +1898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->RxFifo1FullCallback(hcan); +1899:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #else +1900:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call weak (surcharged) callback */ +1901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_RxFifo1FullCallback(hcan); + 2835 .loc 1 1901 7 + 2836 01e4 7868 ldr r0, [r7, #4] + 2837 01e6 FFF7FEFF bl HAL_CAN_RxFifo1FullCallback + 2838 .L136: +1902:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ +1903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1904:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1905:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1906:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Receive FIFO 1 message pending interrupt management *********************/ +1907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U) + 2839 .loc 1 1907 19 + 2840 01ea 3B6A ldr r3, [r7, #32] + 2841 01ec 03F01003 and r3, r3, #16 + 2842 .loc 1 1907 6 + 2843 01f0 002B cmp r3, #0 + 2844 01f2 09D0 beq .L137 +1908:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1909:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check if message is still pending */ +1910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U) + 2845 .loc 1 1910 14 + 2846 01f4 7B68 ldr r3, [r7, #4] + 2847 01f6 1B68 ldr r3, [r3] + ARM GAS /tmp/ccM1MpQr.s page 102 + + + 2848 .loc 1 1910 24 + 2849 01f8 1B69 ldr r3, [r3, #16] + 2850 .loc 1 1910 31 + 2851 01fa 03F00303 and r3, r3, #3 + 2852 .loc 1 1910 8 + 2853 01fe 002B cmp r3, #0 + 2854 0200 02D0 beq .L137 +1911:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Receive FIFO 1 message pending Callback */ +1913:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +1914:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call registered callback*/ +1915:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->RxFifo1MsgPendingCallback(hcan); +1916:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #else +1917:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call weak (surcharged) callback */ +1918:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_RxFifo1MsgPendingCallback(hcan); + 2855 .loc 1 1918 7 + 2856 0202 7868 ldr r0, [r7, #4] + 2857 0204 FFF7FEFF bl HAL_CAN_RxFifo1MsgPendingCallback + 2858 .L137: +1919:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ +1920:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1922:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1923:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Sleep interrupt management *********************************************/ +1924:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((interrupts & CAN_IT_SLEEP_ACK) != 0U) + 2859 .loc 1 1924 19 + 2860 0208 3B6A ldr r3, [r7, #32] + 2861 020a 03F40033 and r3, r3, #131072 + 2862 .loc 1 1924 6 + 2863 020e 002B cmp r3, #0 + 2864 0210 0BD0 beq .L138 +1925:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1926:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((msrflags & CAN_MSR_SLAKI) != 0U) + 2865 .loc 1 1926 19 + 2866 0212 FB69 ldr r3, [r7, #28] + 2867 0214 03F01003 and r3, r3, #16 + 2868 .loc 1 1926 8 + 2869 0218 002B cmp r3, #0 + 2870 021a 06D0 beq .L138 +1927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1928:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Clear Sleep interrupt Flag */ +1929:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI); + 2871 .loc 1 1929 7 + 2872 021c 7B68 ldr r3, [r7, #4] + 2873 021e 1B68 ldr r3, [r3] + 2874 0220 1022 movs r2, #16 + 2875 0222 5A60 str r2, [r3, #4] +1930:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1931:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Sleep Callback */ +1932:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +1933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call registered callback*/ +1934:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->SleepCallback(hcan); +1935:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #else +1936:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call weak (surcharged) callback */ +1937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_SleepCallback(hcan); + 2876 .loc 1 1937 7 + 2877 0224 7868 ldr r0, [r7, #4] + ARM GAS /tmp/ccM1MpQr.s page 103 + + + 2878 0226 FFF7FEFF bl HAL_CAN_SleepCallback + 2879 .L138: +1938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ +1939:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1941:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* WakeUp interrupt management *********************************************/ +1943:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((interrupts & CAN_IT_WAKEUP) != 0U) + 2880 .loc 1 1943 19 + 2881 022a 3B6A ldr r3, [r7, #32] + 2882 022c 03F48033 and r3, r3, #65536 + 2883 .loc 1 1943 6 + 2884 0230 002B cmp r3, #0 + 2885 0232 0BD0 beq .L139 +1944:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((msrflags & CAN_MSR_WKUI) != 0U) + 2886 .loc 1 1945 19 + 2887 0234 FB69 ldr r3, [r7, #28] + 2888 0236 03F00803 and r3, r3, #8 + 2889 .loc 1 1945 8 + 2890 023a 002B cmp r3, #0 + 2891 023c 06D0 beq .L139 +1946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1947:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Clear WakeUp Flag */ +1948:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU); + 2892 .loc 1 1948 7 + 2893 023e 7B68 ldr r3, [r7, #4] + 2894 0240 1B68 ldr r3, [r3] + 2895 0242 0822 movs r2, #8 + 2896 0244 5A60 str r2, [r3, #4] +1949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1950:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* WakeUp Callback */ +1951:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +1952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call registered callback*/ +1953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->WakeUpFromRxMsgCallback(hcan); +1954:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #else +1955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call weak (surcharged) callback */ +1956:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_WakeUpFromRxMsgCallback(hcan); + 2897 .loc 1 1956 7 + 2898 0246 7868 ldr r0, [r7, #4] + 2899 0248 FFF7FEFF bl HAL_CAN_WakeUpFromRxMsgCallback + 2900 .L139: +1957:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ +1958:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1960:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Error interrupts management *********************************************/ +1962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((interrupts & CAN_IT_ERROR) != 0U) + 2901 .loc 1 1962 19 + 2902 024c 3B6A ldr r3, [r7, #32] + 2903 024e 03F40043 and r3, r3, #32768 + 2904 .loc 1 1962 6 + 2905 0252 002B cmp r3, #0 + 2906 0254 7BD0 beq .L140 +1963:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1964:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((msrflags & CAN_MSR_ERRI) != 0U) + 2907 .loc 1 1964 19 + ARM GAS /tmp/ccM1MpQr.s page 104 + + + 2908 0256 FB69 ldr r3, [r7, #28] + 2909 0258 03F00403 and r3, r3, #4 + 2910 .loc 1 1964 8 + 2911 025c 002B cmp r3, #0 + 2912 025e 72D0 beq .L141 +1965:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1966:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check Error Warning Flag */ +1967:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && + 2913 .loc 1 1967 24 + 2914 0260 3B6A ldr r3, [r7, #32] + 2915 0262 03F48073 and r3, r3, #256 + 2916 .loc 1 1967 10 + 2917 0266 002B cmp r3, #0 + 2918 0268 08D0 beq .L142 +1968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((esrflags & CAN_ESR_EWGF) != 0U)) + 2919 .loc 1 1968 22 + 2920 026a FB68 ldr r3, [r7, #12] + 2921 026c 03F00103 and r3, r3, #1 +1967:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((esrflags & CAN_ESR_EWGF) != 0U)) + 2922 .loc 1 1967 55 discriminator 1 + 2923 0270 002B cmp r3, #0 + 2924 0272 03D0 beq .L142 +1969:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1970:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Set CAN error code to Error Warning */ +1971:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** errorcode |= HAL_CAN_ERROR_EWG; + 2925 .loc 1 1971 19 + 2926 0274 7B6A ldr r3, [r7, #36] + 2927 0276 43F00103 orr r3, r3, #1 + 2928 027a 7B62 str r3, [r7, #36] + 2929 .L142: +1972:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1973:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* No need for clear of Error Warning Flag as read-only */ +1974:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1975:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1976:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check Error Passive Flag */ +1977:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && + 2930 .loc 1 1977 24 + 2931 027c 3B6A ldr r3, [r7, #32] + 2932 027e 03F40073 and r3, r3, #512 + 2933 .loc 1 1977 10 + 2934 0282 002B cmp r3, #0 + 2935 0284 08D0 beq .L143 +1978:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((esrflags & CAN_ESR_EPVF) != 0U)) + 2936 .loc 1 1978 22 + 2937 0286 FB68 ldr r3, [r7, #12] + 2938 0288 03F00203 and r3, r3, #2 +1977:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((esrflags & CAN_ESR_EPVF) != 0U)) + 2939 .loc 1 1977 55 discriminator 1 + 2940 028c 002B cmp r3, #0 + 2941 028e 03D0 beq .L143 +1979:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Set CAN error code to Error Passive */ +1981:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** errorcode |= HAL_CAN_ERROR_EPV; + 2942 .loc 1 1981 19 + 2943 0290 7B6A ldr r3, [r7, #36] + 2944 0292 43F00203 orr r3, r3, #2 + 2945 0296 7B62 str r3, [r7, #36] + ARM GAS /tmp/ccM1MpQr.s page 105 + + + 2946 .L143: +1982:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1983:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* No need for clear of Error Passive Flag as read-only */ +1984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1985:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1986:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check Bus-off Flag */ +1987:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (((interrupts & CAN_IT_BUSOFF) != 0U) && + 2947 .loc 1 1987 24 + 2948 0298 3B6A ldr r3, [r7, #32] + 2949 029a 03F48063 and r3, r3, #1024 + 2950 .loc 1 1987 10 + 2951 029e 002B cmp r3, #0 + 2952 02a0 08D0 beq .L144 +1988:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((esrflags & CAN_ESR_BOFF) != 0U)) + 2953 .loc 1 1988 22 + 2954 02a2 FB68 ldr r3, [r7, #12] + 2955 02a4 03F00403 and r3, r3, #4 +1987:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((esrflags & CAN_ESR_BOFF) != 0U)) + 2956 .loc 1 1987 48 discriminator 1 + 2957 02a8 002B cmp r3, #0 + 2958 02aa 03D0 beq .L144 +1989:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +1990:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Set CAN error code to Bus-Off */ +1991:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** errorcode |= HAL_CAN_ERROR_BOF; + 2959 .loc 1 1991 19 + 2960 02ac 7B6A ldr r3, [r7, #36] + 2961 02ae 43F00403 orr r3, r3, #4 + 2962 02b2 7B62 str r3, [r7, #36] + 2963 .L144: +1992:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1993:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* No need for clear of Error Bus-Off as read-only */ +1994:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +1995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +1996:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check Last Error Code Flag */ +1997:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && + 2964 .loc 1 1997 24 + 2965 02b4 3B6A ldr r3, [r7, #32] + 2966 02b6 03F40063 and r3, r3, #2048 + 2967 .loc 1 1997 10 + 2968 02ba 002B cmp r3, #0 + 2969 02bc 43D0 beq .L141 +1998:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((esrflags & CAN_ESR_LEC) != 0U)) + 2970 .loc 1 1998 22 + 2971 02be FB68 ldr r3, [r7, #12] + 2972 02c0 03F07003 and r3, r3, #112 +1997:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ((esrflags & CAN_ESR_LEC) != 0U)) + 2973 .loc 1 1997 57 discriminator 1 + 2974 02c4 002B cmp r3, #0 + 2975 02c6 3ED0 beq .L141 +1999:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +2000:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** switch (esrflags & CAN_ESR_LEC) + 2976 .loc 1 2000 26 + 2977 02c8 FB68 ldr r3, [r7, #12] + 2978 02ca 03F07003 and r3, r3, #112 + 2979 .loc 1 2000 9 + 2980 02ce 602B cmp r3, #96 + 2981 02d0 2BD0 beq .L145 + ARM GAS /tmp/ccM1MpQr.s page 106 + + + 2982 02d2 602B cmp r3, #96 + 2983 02d4 2ED8 bhi .L154 + 2984 02d6 502B cmp r3, #80 + 2985 02d8 22D0 beq .L147 + 2986 02da 502B cmp r3, #80 + 2987 02dc 2AD8 bhi .L154 + 2988 02de 402B cmp r3, #64 + 2989 02e0 19D0 beq .L148 + 2990 02e2 402B cmp r3, #64 + 2991 02e4 26D8 bhi .L154 + 2992 02e6 302B cmp r3, #48 + 2993 02e8 10D0 beq .L149 + 2994 02ea 302B cmp r3, #48 + 2995 02ec 22D8 bhi .L154 + 2996 02ee 102B cmp r3, #16 + 2997 02f0 02D0 beq .L150 + 2998 02f2 202B cmp r3, #32 + 2999 02f4 05D0 beq .L151 +2001:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +2002:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case (CAN_ESR_LEC_0): +2003:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Set CAN error code to Stuff error */ +2004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** errorcode |= HAL_CAN_ERROR_STF; +2005:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; +2006:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case (CAN_ESR_LEC_1): +2007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Set CAN error code to Form error */ +2008:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** errorcode |= HAL_CAN_ERROR_FOR; +2009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; +2010:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case (CAN_ESR_LEC_1 | CAN_ESR_LEC_0): +2011:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Set CAN error code to Acknowledgement error */ +2012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** errorcode |= HAL_CAN_ERROR_ACK; +2013:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; +2014:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case (CAN_ESR_LEC_2): +2015:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Set CAN error code to Bit recessive error */ +2016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** errorcode |= HAL_CAN_ERROR_BR; +2017:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; +2018:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case (CAN_ESR_LEC_2 | CAN_ESR_LEC_0): +2019:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Set CAN error code to Bit Dominant error */ +2020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** errorcode |= HAL_CAN_ERROR_BD; +2021:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; +2022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1): +2023:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Set CAN error code to CRC error */ +2024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** errorcode |= HAL_CAN_ERROR_CRC; +2025:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; +2026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** default: +2027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 3000 .loc 1 2027 13 + 3001 02f6 1DE0 b .L154 + 3002 .L150: +2004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 3003 .loc 1 2004 23 + 3004 02f8 7B6A ldr r3, [r7, #36] + 3005 02fa 43F00803 orr r3, r3, #8 + 3006 02fe 7B62 str r3, [r7, #36] +2005:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case (CAN_ESR_LEC_1): + 3007 .loc 1 2005 13 + 3008 0300 19E0 b .L152 + 3009 .L151: + ARM GAS /tmp/ccM1MpQr.s page 107 + + +2008:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 3010 .loc 1 2008 23 + 3011 0302 7B6A ldr r3, [r7, #36] + 3012 0304 43F01003 orr r3, r3, #16 + 3013 0308 7B62 str r3, [r7, #36] +2009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case (CAN_ESR_LEC_1 | CAN_ESR_LEC_0): + 3014 .loc 1 2009 13 + 3015 030a 14E0 b .L152 + 3016 .L149: +2012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 3017 .loc 1 2012 23 + 3018 030c 7B6A ldr r3, [r7, #36] + 3019 030e 43F02003 orr r3, r3, #32 + 3020 0312 7B62 str r3, [r7, #36] +2013:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case (CAN_ESR_LEC_2): + 3021 .loc 1 2013 13 + 3022 0314 0FE0 b .L152 + 3023 .L148: +2016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 3024 .loc 1 2016 23 + 3025 0316 7B6A ldr r3, [r7, #36] + 3026 0318 43F04003 orr r3, r3, #64 + 3027 031c 7B62 str r3, [r7, #36] +2017:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case (CAN_ESR_LEC_2 | CAN_ESR_LEC_0): + 3028 .loc 1 2017 13 + 3029 031e 0AE0 b .L152 + 3030 .L147: +2020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 3031 .loc 1 2020 23 + 3032 0320 7B6A ldr r3, [r7, #36] + 3033 0322 43F08003 orr r3, r3, #128 + 3034 0326 7B62 str r3, [r7, #36] +2021:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1): + 3035 .loc 1 2021 13 + 3036 0328 05E0 b .L152 + 3037 .L145: +2024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** break; + 3038 .loc 1 2024 23 + 3039 032a 7B6A ldr r3, [r7, #36] + 3040 032c 43F48073 orr r3, r3, #256 + 3041 0330 7B62 str r3, [r7, #36] +2025:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** default: + 3042 .loc 1 2025 13 + 3043 0332 00E0 b .L152 + 3044 .L154: + 3045 .loc 1 2027 13 + 3046 0334 00BF nop + 3047 .L152: +2028:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +2029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2030:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Clear Last error code Flag */ +2031:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC); + 3048 .loc 1 2031 9 + 3049 0336 7B68 ldr r3, [r7, #4] + 3050 0338 1B68 ldr r3, [r3] + 3051 033a 9A69 ldr r2, [r3, #24] + 3052 033c 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/ccM1MpQr.s page 108 + + + 3053 033e 1B68 ldr r3, [r3] + 3054 0340 22F07002 bic r2, r2, #112 + 3055 0344 9A61 str r2, [r3, #24] + 3056 .L141: +2032:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +2033:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +2034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2035:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Clear ERRI Flag */ +2036:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI); + 3057 .loc 1 2036 5 + 3058 0346 7B68 ldr r3, [r7, #4] + 3059 0348 1B68 ldr r3, [r3] + 3060 034a 0422 movs r2, #4 + 3061 034c 5A60 str r2, [r3, #4] + 3062 .L140: +2037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +2038:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2039:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call the Error call Back in case of Errors */ +2040:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if (errorcode != HAL_CAN_ERROR_NONE) + 3063 .loc 1 2040 6 + 3064 034e 7B6A ldr r3, [r7, #36] + 3065 0350 002B cmp r3, #0 + 3066 0352 08D0 beq .L155 +2041:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +2042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code in handle */ +2043:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= errorcode; + 3067 .loc 1 2043 9 + 3068 0354 7B68 ldr r3, [r7, #4] + 3069 0356 5A6A ldr r2, [r3, #36] + 3070 .loc 1 2043 21 + 3071 0358 7B6A ldr r3, [r7, #36] + 3072 035a 1A43 orrs r2, r2, r3 + 3073 035c 7B68 ldr r3, [r7, #4] + 3074 035e 5A62 str r2, [r3, #36] +2044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2045:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call Error callback function */ +2046:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +2047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call registered callback*/ +2048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCallback(hcan); +2049:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #else +2050:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Call weak (surcharged) callback */ +2051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_ErrorCallback(hcan); + 3075 .loc 1 2051 5 + 3076 0360 7868 ldr r0, [r7, #4] + 3077 0362 FFF7FEFF bl HAL_CAN_ErrorCallback + 3078 .L155: +2052:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** #endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ +2053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +2054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 3079 .loc 1 2054 1 + 3080 0366 00BF nop + 3081 0368 2837 adds r7, r7, #40 + 3082 .cfi_def_cfa_offset 8 + 3083 036a BD46 mov sp, r7 + 3084 .cfi_def_cfa_register 13 + 3085 @ sp needed + 3086 036c 80BD pop {r7, pc} + ARM GAS /tmp/ccM1MpQr.s page 109 + + + 3087 .cfi_endproc + 3088 .LFE149: + 3090 .section .text.HAL_CAN_TxMailbox0CompleteCallback,"ax",%progbits + 3091 .align 1 + 3092 .weak HAL_CAN_TxMailbox0CompleteCallback + 3093 .syntax unified + 3094 .thumb + 3095 .thumb_func + 3097 HAL_CAN_TxMailbox0CompleteCallback: + 3098 .LFB150: +2055:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +2057:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @} +2058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2060:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** @defgroup CAN_Exported_Functions_Group5 Callback functions +2061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief CAN Callback functions +2062:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * +2063:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** @verbatim +2064:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ============================================================================== +2065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ##### Callback functions ##### +2066:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ============================================================================== +2067:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** [..] +2068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** This subsection provides the following callback functions: +2069:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_TxMailbox0CompleteCallback +2070:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_TxMailbox1CompleteCallback +2071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_TxMailbox2CompleteCallback +2072:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_TxMailbox0AbortCallback +2073:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_TxMailbox1AbortCallback +2074:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_TxMailbox2AbortCallback +2075:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_RxFifo0MsgPendingCallback +2076:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_RxFifo0FullCallback +2077:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_RxFifo1MsgPendingCallback +2078:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_RxFifo1FullCallback +2079:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_SleepCallback +2080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_WakeUpFromRxMsgCallback +2081:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_ErrorCallback +2082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** @endverbatim +2084:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @{ +2085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2086:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2087:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +2088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Transmission Mailbox 0 complete callback. +2089:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains +2090:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +2091:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval None +2092:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2093:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan) +2094:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 3099 .loc 1 2094 1 + 3100 .cfi_startproc + 3101 @ args = 0, pretend = 0, frame = 8 + 3102 @ frame_needed = 1, uses_anonymous_args = 0 + 3103 @ link register save eliminated. + 3104 0000 80B4 push {r7} + 3105 .cfi_def_cfa_offset 4 + ARM GAS /tmp/ccM1MpQr.s page 110 + + + 3106 .cfi_offset 7, -4 + 3107 0002 83B0 sub sp, sp, #12 + 3108 .cfi_def_cfa_offset 16 + 3109 0004 00AF add r7, sp, #0 + 3110 .cfi_def_cfa_register 7 + 3111 0006 7860 str r0, [r7, #4] +2095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Prevent unused argument(s) compilation warning */ +2096:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** UNUSED(hcan); +2097:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* NOTE : This function Should not be modified, when the callback is needed, +2099:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the +2100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** user file +2101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 3112 .loc 1 2102 1 + 3113 0008 00BF nop + 3114 000a 0C37 adds r7, r7, #12 + 3115 .cfi_def_cfa_offset 4 + 3116 000c BD46 mov sp, r7 + 3117 .cfi_def_cfa_register 13 + 3118 @ sp needed + 3119 000e 5DF8047B ldr r7, [sp], #4 + 3120 .cfi_restore 7 + 3121 .cfi_def_cfa_offset 0 + 3122 0012 7047 bx lr + 3123 .cfi_endproc + 3124 .LFE150: + 3126 .section .text.HAL_CAN_TxMailbox1CompleteCallback,"ax",%progbits + 3127 .align 1 + 3128 .weak HAL_CAN_TxMailbox1CompleteCallback + 3129 .syntax unified + 3130 .thumb + 3131 .thumb_func + 3133 HAL_CAN_TxMailbox1CompleteCallback: + 3134 .LFB151: +2103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +2105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Transmission Mailbox 1 complete callback. +2106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains +2107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +2108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval None +2109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan) +2111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 3135 .loc 1 2111 1 + 3136 .cfi_startproc + 3137 @ args = 0, pretend = 0, frame = 8 + 3138 @ frame_needed = 1, uses_anonymous_args = 0 + 3139 @ link register save eliminated. + 3140 0000 80B4 push {r7} + 3141 .cfi_def_cfa_offset 4 + 3142 .cfi_offset 7, -4 + 3143 0002 83B0 sub sp, sp, #12 + 3144 .cfi_def_cfa_offset 16 + 3145 0004 00AF add r7, sp, #0 + 3146 .cfi_def_cfa_register 7 + 3147 0006 7860 str r0, [r7, #4] + ARM GAS /tmp/ccM1MpQr.s page 111 + + +2112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Prevent unused argument(s) compilation warning */ +2113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** UNUSED(hcan); +2114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* NOTE : This function Should not be modified, when the callback is needed, +2116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the +2117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** user file +2118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 3148 .loc 1 2119 1 + 3149 0008 00BF nop + 3150 000a 0C37 adds r7, r7, #12 + 3151 .cfi_def_cfa_offset 4 + 3152 000c BD46 mov sp, r7 + 3153 .cfi_def_cfa_register 13 + 3154 @ sp needed + 3155 000e 5DF8047B ldr r7, [sp], #4 + 3156 .cfi_restore 7 + 3157 .cfi_def_cfa_offset 0 + 3158 0012 7047 bx lr + 3159 .cfi_endproc + 3160 .LFE151: + 3162 .section .text.HAL_CAN_TxMailbox2CompleteCallback,"ax",%progbits + 3163 .align 1 + 3164 .weak HAL_CAN_TxMailbox2CompleteCallback + 3165 .syntax unified + 3166 .thumb + 3167 .thumb_func + 3169 HAL_CAN_TxMailbox2CompleteCallback: + 3170 .LFB152: +2120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +2122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Transmission Mailbox 2 complete callback. +2123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains +2124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +2125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval None +2126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan) +2128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 3171 .loc 1 2128 1 + 3172 .cfi_startproc + 3173 @ args = 0, pretend = 0, frame = 8 + 3174 @ frame_needed = 1, uses_anonymous_args = 0 + 3175 @ link register save eliminated. + 3176 0000 80B4 push {r7} + 3177 .cfi_def_cfa_offset 4 + 3178 .cfi_offset 7, -4 + 3179 0002 83B0 sub sp, sp, #12 + 3180 .cfi_def_cfa_offset 16 + 3181 0004 00AF add r7, sp, #0 + 3182 .cfi_def_cfa_register 7 + 3183 0006 7860 str r0, [r7, #4] +2129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Prevent unused argument(s) compilation warning */ +2130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** UNUSED(hcan); +2131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* NOTE : This function Should not be modified, when the callback is needed, +2133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the +2134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** user file + ARM GAS /tmp/ccM1MpQr.s page 112 + + +2135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 3184 .loc 1 2136 1 + 3185 0008 00BF nop + 3186 000a 0C37 adds r7, r7, #12 + 3187 .cfi_def_cfa_offset 4 + 3188 000c BD46 mov sp, r7 + 3189 .cfi_def_cfa_register 13 + 3190 @ sp needed + 3191 000e 5DF8047B ldr r7, [sp], #4 + 3192 .cfi_restore 7 + 3193 .cfi_def_cfa_offset 0 + 3194 0012 7047 bx lr + 3195 .cfi_endproc + 3196 .LFE152: + 3198 .section .text.HAL_CAN_TxMailbox0AbortCallback,"ax",%progbits + 3199 .align 1 + 3200 .weak HAL_CAN_TxMailbox0AbortCallback + 3201 .syntax unified + 3202 .thumb + 3203 .thumb_func + 3205 HAL_CAN_TxMailbox0AbortCallback: + 3206 .LFB153: +2137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +2139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Transmission Mailbox 0 Cancellation callback. +2140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to an CAN_HandleTypeDef structure that contains +2141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +2142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval None +2143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan) +2145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 3207 .loc 1 2145 1 + 3208 .cfi_startproc + 3209 @ args = 0, pretend = 0, frame = 8 + 3210 @ frame_needed = 1, uses_anonymous_args = 0 + 3211 @ link register save eliminated. + 3212 0000 80B4 push {r7} + 3213 .cfi_def_cfa_offset 4 + 3214 .cfi_offset 7, -4 + 3215 0002 83B0 sub sp, sp, #12 + 3216 .cfi_def_cfa_offset 16 + 3217 0004 00AF add r7, sp, #0 + 3218 .cfi_def_cfa_register 7 + 3219 0006 7860 str r0, [r7, #4] +2146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Prevent unused argument(s) compilation warning */ +2147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** UNUSED(hcan); +2148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* NOTE : This function Should not be modified, when the callback is needed, +2150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** the HAL_CAN_TxMailbox0AbortCallback could be implemented in the +2151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** user file +2152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 3220 .loc 1 2153 1 + 3221 0008 00BF nop + 3222 000a 0C37 adds r7, r7, #12 + 3223 .cfi_def_cfa_offset 4 + ARM GAS /tmp/ccM1MpQr.s page 113 + + + 3224 000c BD46 mov sp, r7 + 3225 .cfi_def_cfa_register 13 + 3226 @ sp needed + 3227 000e 5DF8047B ldr r7, [sp], #4 + 3228 .cfi_restore 7 + 3229 .cfi_def_cfa_offset 0 + 3230 0012 7047 bx lr + 3231 .cfi_endproc + 3232 .LFE153: + 3234 .section .text.HAL_CAN_TxMailbox1AbortCallback,"ax",%progbits + 3235 .align 1 + 3236 .weak HAL_CAN_TxMailbox1AbortCallback + 3237 .syntax unified + 3238 .thumb + 3239 .thumb_func + 3241 HAL_CAN_TxMailbox1AbortCallback: + 3242 .LFB154: +2154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +2156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Transmission Mailbox 1 Cancellation callback. +2157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to an CAN_HandleTypeDef structure that contains +2158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +2159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval None +2160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan) +2162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 3243 .loc 1 2162 1 + 3244 .cfi_startproc + 3245 @ args = 0, pretend = 0, frame = 8 + 3246 @ frame_needed = 1, uses_anonymous_args = 0 + 3247 @ link register save eliminated. + 3248 0000 80B4 push {r7} + 3249 .cfi_def_cfa_offset 4 + 3250 .cfi_offset 7, -4 + 3251 0002 83B0 sub sp, sp, #12 + 3252 .cfi_def_cfa_offset 16 + 3253 0004 00AF add r7, sp, #0 + 3254 .cfi_def_cfa_register 7 + 3255 0006 7860 str r0, [r7, #4] +2163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Prevent unused argument(s) compilation warning */ +2164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** UNUSED(hcan); +2165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* NOTE : This function Should not be modified, when the callback is needed, +2167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** the HAL_CAN_TxMailbox1AbortCallback could be implemented in the +2168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** user file +2169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 3256 .loc 1 2170 1 + 3257 0008 00BF nop + 3258 000a 0C37 adds r7, r7, #12 + 3259 .cfi_def_cfa_offset 4 + 3260 000c BD46 mov sp, r7 + 3261 .cfi_def_cfa_register 13 + 3262 @ sp needed + 3263 000e 5DF8047B ldr r7, [sp], #4 + 3264 .cfi_restore 7 + 3265 .cfi_def_cfa_offset 0 + ARM GAS /tmp/ccM1MpQr.s page 114 + + + 3266 0012 7047 bx lr + 3267 .cfi_endproc + 3268 .LFE154: + 3270 .section .text.HAL_CAN_TxMailbox2AbortCallback,"ax",%progbits + 3271 .align 1 + 3272 .weak HAL_CAN_TxMailbox2AbortCallback + 3273 .syntax unified + 3274 .thumb + 3275 .thumb_func + 3277 HAL_CAN_TxMailbox2AbortCallback: + 3278 .LFB155: +2171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +2173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Transmission Mailbox 2 Cancellation callback. +2174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to an CAN_HandleTypeDef structure that contains +2175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +2176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval None +2177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan) +2179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 3279 .loc 1 2179 1 + 3280 .cfi_startproc + 3281 @ args = 0, pretend = 0, frame = 8 + 3282 @ frame_needed = 1, uses_anonymous_args = 0 + 3283 @ link register save eliminated. + 3284 0000 80B4 push {r7} + 3285 .cfi_def_cfa_offset 4 + 3286 .cfi_offset 7, -4 + 3287 0002 83B0 sub sp, sp, #12 + 3288 .cfi_def_cfa_offset 16 + 3289 0004 00AF add r7, sp, #0 + 3290 .cfi_def_cfa_register 7 + 3291 0006 7860 str r0, [r7, #4] +2180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Prevent unused argument(s) compilation warning */ +2181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** UNUSED(hcan); +2182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* NOTE : This function Should not be modified, when the callback is needed, +2184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** the HAL_CAN_TxMailbox2AbortCallback could be implemented in the +2185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** user file +2186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 3292 .loc 1 2187 1 + 3293 0008 00BF nop + 3294 000a 0C37 adds r7, r7, #12 + 3295 .cfi_def_cfa_offset 4 + 3296 000c BD46 mov sp, r7 + 3297 .cfi_def_cfa_register 13 + 3298 @ sp needed + 3299 000e 5DF8047B ldr r7, [sp], #4 + 3300 .cfi_restore 7 + 3301 .cfi_def_cfa_offset 0 + 3302 0012 7047 bx lr + 3303 .cfi_endproc + 3304 .LFE155: + 3306 .section .text.HAL_CAN_RxFifo0MsgPendingCallback,"ax",%progbits + 3307 .align 1 + 3308 .weak HAL_CAN_RxFifo0MsgPendingCallback + ARM GAS /tmp/ccM1MpQr.s page 115 + + + 3309 .syntax unified + 3310 .thumb + 3311 .thumb_func + 3313 HAL_CAN_RxFifo0MsgPendingCallback: + 3314 .LFB156: +2188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +2190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Rx FIFO 0 message pending callback. +2191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains +2192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +2193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval None +2194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __weak void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan) +2196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 3315 .loc 1 2196 1 + 3316 .cfi_startproc + 3317 @ args = 0, pretend = 0, frame = 8 + 3318 @ frame_needed = 1, uses_anonymous_args = 0 + 3319 @ link register save eliminated. + 3320 0000 80B4 push {r7} + 3321 .cfi_def_cfa_offset 4 + 3322 .cfi_offset 7, -4 + 3323 0002 83B0 sub sp, sp, #12 + 3324 .cfi_def_cfa_offset 16 + 3325 0004 00AF add r7, sp, #0 + 3326 .cfi_def_cfa_register 7 + 3327 0006 7860 str r0, [r7, #4] +2197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Prevent unused argument(s) compilation warning */ +2198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** UNUSED(hcan); +2199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* NOTE : This function Should not be modified, when the callback is needed, +2201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** the HAL_CAN_RxFifo0MsgPendingCallback could be implemented in the +2202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** user file +2203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 3328 .loc 1 2204 1 + 3329 0008 00BF nop + 3330 000a 0C37 adds r7, r7, #12 + 3331 .cfi_def_cfa_offset 4 + 3332 000c BD46 mov sp, r7 + 3333 .cfi_def_cfa_register 13 + 3334 @ sp needed + 3335 000e 5DF8047B ldr r7, [sp], #4 + 3336 .cfi_restore 7 + 3337 .cfi_def_cfa_offset 0 + 3338 0012 7047 bx lr + 3339 .cfi_endproc + 3340 .LFE156: + 3342 .section .text.HAL_CAN_RxFifo0FullCallback,"ax",%progbits + 3343 .align 1 + 3344 .weak HAL_CAN_RxFifo0FullCallback + 3345 .syntax unified + 3346 .thumb + 3347 .thumb_func + 3349 HAL_CAN_RxFifo0FullCallback: + 3350 .LFB157: +2205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** + ARM GAS /tmp/ccM1MpQr.s page 116 + + +2206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +2207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Rx FIFO 0 full callback. +2208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains +2209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +2210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval None +2211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan) +2213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 3351 .loc 1 2213 1 + 3352 .cfi_startproc + 3353 @ args = 0, pretend = 0, frame = 8 + 3354 @ frame_needed = 1, uses_anonymous_args = 0 + 3355 @ link register save eliminated. + 3356 0000 80B4 push {r7} + 3357 .cfi_def_cfa_offset 4 + 3358 .cfi_offset 7, -4 + 3359 0002 83B0 sub sp, sp, #12 + 3360 .cfi_def_cfa_offset 16 + 3361 0004 00AF add r7, sp, #0 + 3362 .cfi_def_cfa_register 7 + 3363 0006 7860 str r0, [r7, #4] +2214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Prevent unused argument(s) compilation warning */ +2215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** UNUSED(hcan); +2216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* NOTE : This function Should not be modified, when the callback is needed, +2218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** the HAL_CAN_RxFifo0FullCallback could be implemented in the user +2219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** file +2220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 3364 .loc 1 2221 1 + 3365 0008 00BF nop + 3366 000a 0C37 adds r7, r7, #12 + 3367 .cfi_def_cfa_offset 4 + 3368 000c BD46 mov sp, r7 + 3369 .cfi_def_cfa_register 13 + 3370 @ sp needed + 3371 000e 5DF8047B ldr r7, [sp], #4 + 3372 .cfi_restore 7 + 3373 .cfi_def_cfa_offset 0 + 3374 0012 7047 bx lr + 3375 .cfi_endproc + 3376 .LFE157: + 3378 .section .text.HAL_CAN_RxFifo1MsgPendingCallback,"ax",%progbits + 3379 .align 1 + 3380 .weak HAL_CAN_RxFifo1MsgPendingCallback + 3381 .syntax unified + 3382 .thumb + 3383 .thumb_func + 3385 HAL_CAN_RxFifo1MsgPendingCallback: + 3386 .LFB158: +2222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +2224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Rx FIFO 1 message pending callback. +2225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains +2226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +2227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval None +2228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ + ARM GAS /tmp/ccM1MpQr.s page 117 + + +2229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __weak void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan) +2230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 3387 .loc 1 2230 1 + 3388 .cfi_startproc + 3389 @ args = 0, pretend = 0, frame = 8 + 3390 @ frame_needed = 1, uses_anonymous_args = 0 + 3391 @ link register save eliminated. + 3392 0000 80B4 push {r7} + 3393 .cfi_def_cfa_offset 4 + 3394 .cfi_offset 7, -4 + 3395 0002 83B0 sub sp, sp, #12 + 3396 .cfi_def_cfa_offset 16 + 3397 0004 00AF add r7, sp, #0 + 3398 .cfi_def_cfa_register 7 + 3399 0006 7860 str r0, [r7, #4] +2231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Prevent unused argument(s) compilation warning */ +2232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** UNUSED(hcan); +2233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* NOTE : This function Should not be modified, when the callback is needed, +2235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** the HAL_CAN_RxFifo1MsgPendingCallback could be implemented in the +2236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** user file +2237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 3400 .loc 1 2238 1 + 3401 0008 00BF nop + 3402 000a 0C37 adds r7, r7, #12 + 3403 .cfi_def_cfa_offset 4 + 3404 000c BD46 mov sp, r7 + 3405 .cfi_def_cfa_register 13 + 3406 @ sp needed + 3407 000e 5DF8047B ldr r7, [sp], #4 + 3408 .cfi_restore 7 + 3409 .cfi_def_cfa_offset 0 + 3410 0012 7047 bx lr + 3411 .cfi_endproc + 3412 .LFE158: + 3414 .section .text.HAL_CAN_RxFifo1FullCallback,"ax",%progbits + 3415 .align 1 + 3416 .weak HAL_CAN_RxFifo1FullCallback + 3417 .syntax unified + 3418 .thumb + 3419 .thumb_func + 3421 HAL_CAN_RxFifo1FullCallback: + 3422 .LFB159: +2239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +2241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Rx FIFO 1 full callback. +2242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains +2243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +2244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval None +2245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan) +2247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 3423 .loc 1 2247 1 + 3424 .cfi_startproc + 3425 @ args = 0, pretend = 0, frame = 8 + 3426 @ frame_needed = 1, uses_anonymous_args = 0 + ARM GAS /tmp/ccM1MpQr.s page 118 + + + 3427 @ link register save eliminated. + 3428 0000 80B4 push {r7} + 3429 .cfi_def_cfa_offset 4 + 3430 .cfi_offset 7, -4 + 3431 0002 83B0 sub sp, sp, #12 + 3432 .cfi_def_cfa_offset 16 + 3433 0004 00AF add r7, sp, #0 + 3434 .cfi_def_cfa_register 7 + 3435 0006 7860 str r0, [r7, #4] +2248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Prevent unused argument(s) compilation warning */ +2249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** UNUSED(hcan); +2250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* NOTE : This function Should not be modified, when the callback is needed, +2252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** the HAL_CAN_RxFifo1FullCallback could be implemented in the user +2253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** file +2254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 3436 .loc 1 2255 1 + 3437 0008 00BF nop + 3438 000a 0C37 adds r7, r7, #12 + 3439 .cfi_def_cfa_offset 4 + 3440 000c BD46 mov sp, r7 + 3441 .cfi_def_cfa_register 13 + 3442 @ sp needed + 3443 000e 5DF8047B ldr r7, [sp], #4 + 3444 .cfi_restore 7 + 3445 .cfi_def_cfa_offset 0 + 3446 0012 7047 bx lr + 3447 .cfi_endproc + 3448 .LFE159: + 3450 .section .text.HAL_CAN_SleepCallback,"ax",%progbits + 3451 .align 1 + 3452 .weak HAL_CAN_SleepCallback + 3453 .syntax unified + 3454 .thumb + 3455 .thumb_func + 3457 HAL_CAN_SleepCallback: + 3458 .LFB160: +2256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +2258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Sleep callback. +2259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains +2260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +2261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval None +2262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan) +2264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 3459 .loc 1 2264 1 + 3460 .cfi_startproc + 3461 @ args = 0, pretend = 0, frame = 8 + 3462 @ frame_needed = 1, uses_anonymous_args = 0 + 3463 @ link register save eliminated. + 3464 0000 80B4 push {r7} + 3465 .cfi_def_cfa_offset 4 + 3466 .cfi_offset 7, -4 + 3467 0002 83B0 sub sp, sp, #12 + 3468 .cfi_def_cfa_offset 16 + ARM GAS /tmp/ccM1MpQr.s page 119 + + + 3469 0004 00AF add r7, sp, #0 + 3470 .cfi_def_cfa_register 7 + 3471 0006 7860 str r0, [r7, #4] +2265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Prevent unused argument(s) compilation warning */ +2266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** UNUSED(hcan); +2267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* NOTE : This function Should not be modified, when the callback is needed, +2269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** the HAL_CAN_SleepCallback could be implemented in the user file +2270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 3472 .loc 1 2271 1 + 3473 0008 00BF nop + 3474 000a 0C37 adds r7, r7, #12 + 3475 .cfi_def_cfa_offset 4 + 3476 000c BD46 mov sp, r7 + 3477 .cfi_def_cfa_register 13 + 3478 @ sp needed + 3479 000e 5DF8047B ldr r7, [sp], #4 + 3480 .cfi_restore 7 + 3481 .cfi_def_cfa_offset 0 + 3482 0012 7047 bx lr + 3483 .cfi_endproc + 3484 .LFE160: + 3486 .section .text.HAL_CAN_WakeUpFromRxMsgCallback,"ax",%progbits + 3487 .align 1 + 3488 .weak HAL_CAN_WakeUpFromRxMsgCallback + 3489 .syntax unified + 3490 .thumb + 3491 .thumb_func + 3493 HAL_CAN_WakeUpFromRxMsgCallback: + 3494 .LFB161: +2272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +2274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief WakeUp from Rx message callback. +2275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains +2276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +2277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval None +2278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan) +2280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 3495 .loc 1 2280 1 + 3496 .cfi_startproc + 3497 @ args = 0, pretend = 0, frame = 8 + 3498 @ frame_needed = 1, uses_anonymous_args = 0 + 3499 @ link register save eliminated. + 3500 0000 80B4 push {r7} + 3501 .cfi_def_cfa_offset 4 + 3502 .cfi_offset 7, -4 + 3503 0002 83B0 sub sp, sp, #12 + 3504 .cfi_def_cfa_offset 16 + 3505 0004 00AF add r7, sp, #0 + 3506 .cfi_def_cfa_register 7 + 3507 0006 7860 str r0, [r7, #4] +2281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Prevent unused argument(s) compilation warning */ +2282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** UNUSED(hcan); +2283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* NOTE : This function Should not be modified, when the callback is needed, + ARM GAS /tmp/ccM1MpQr.s page 120 + + +2285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the +2286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** user file +2287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 3508 .loc 1 2288 1 + 3509 0008 00BF nop + 3510 000a 0C37 adds r7, r7, #12 + 3511 .cfi_def_cfa_offset 4 + 3512 000c BD46 mov sp, r7 + 3513 .cfi_def_cfa_register 13 + 3514 @ sp needed + 3515 000e 5DF8047B ldr r7, [sp], #4 + 3516 .cfi_restore 7 + 3517 .cfi_def_cfa_offset 0 + 3518 0012 7047 bx lr + 3519 .cfi_endproc + 3520 .LFE161: + 3522 .section .text.HAL_CAN_ErrorCallback,"ax",%progbits + 3523 .align 1 + 3524 .weak HAL_CAN_ErrorCallback + 3525 .syntax unified + 3526 .thumb + 3527 .thumb_func + 3529 HAL_CAN_ErrorCallback: + 3530 .LFB162: +2289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +2291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Error CAN callback. +2292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains +2293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +2294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval None +2295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) +2297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 3531 .loc 1 2297 1 + 3532 .cfi_startproc + 3533 @ args = 0, pretend = 0, frame = 8 + 3534 @ frame_needed = 1, uses_anonymous_args = 0 + 3535 @ link register save eliminated. + 3536 0000 80B4 push {r7} + 3537 .cfi_def_cfa_offset 4 + 3538 .cfi_offset 7, -4 + 3539 0002 83B0 sub sp, sp, #12 + 3540 .cfi_def_cfa_offset 16 + 3541 0004 00AF add r7, sp, #0 + 3542 .cfi_def_cfa_register 7 + 3543 0006 7860 str r0, [r7, #4] +2298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Prevent unused argument(s) compilation warning */ +2299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** UNUSED(hcan); +2300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* NOTE : This function Should not be modified, when the callback is needed, +2302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** the HAL_CAN_ErrorCallback could be implemented in the user file +2303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 3544 .loc 1 2304 1 + 3545 0008 00BF nop + 3546 000a 0C37 adds r7, r7, #12 + ARM GAS /tmp/ccM1MpQr.s page 121 + + + 3547 .cfi_def_cfa_offset 4 + 3548 000c BD46 mov sp, r7 + 3549 .cfi_def_cfa_register 13 + 3550 @ sp needed + 3551 000e 5DF8047B ldr r7, [sp], #4 + 3552 .cfi_restore 7 + 3553 .cfi_def_cfa_offset 0 + 3554 0012 7047 bx lr + 3555 .cfi_endproc + 3556 .LFE162: + 3558 .section .text.HAL_CAN_GetState,"ax",%progbits + 3559 .align 1 + 3560 .global HAL_CAN_GetState + 3561 .syntax unified + 3562 .thumb + 3563 .thumb_func + 3565 HAL_CAN_GetState: + 3566 .LFB163: +2305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +2307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @} +2308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** @defgroup CAN_Exported_Functions_Group6 Peripheral State and Error functions +2311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief CAN Peripheral State functions +2312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * +2313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** @verbatim +2314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ============================================================================== +2315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ##### Peripheral State and Error functions ##### +2316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** ============================================================================== +2317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** [..] +2318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** This subsection provides functions allowing to : +2319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_GetState() : Return the CAN state. +2320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_GetError() : Return the CAN error codes if any. +2321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (+) HAL_CAN_ResetError(): Reset the CAN error codes if any. +2322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** @endverbatim +2324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @{ +2325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +2328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Return the CAN state. +2329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains +2330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +2331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval HAL state +2332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_StateTypeDef HAL_CAN_GetState(const CAN_HandleTypeDef *hcan) +2334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 3567 .loc 1 2334 1 + 3568 .cfi_startproc + 3569 @ args = 0, pretend = 0, frame = 16 + 3570 @ frame_needed = 1, uses_anonymous_args = 0 + 3571 @ link register save eliminated. + 3572 0000 80B4 push {r7} + 3573 .cfi_def_cfa_offset 4 + 3574 .cfi_offset 7, -4 + 3575 0002 85B0 sub sp, sp, #20 + ARM GAS /tmp/ccM1MpQr.s page 122 + + + 3576 .cfi_def_cfa_offset 24 + 3577 0004 00AF add r7, sp, #0 + 3578 .cfi_def_cfa_register 7 + 3579 0006 7860 str r0, [r7, #4] +2335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_StateTypeDef state = hcan->State; + 3580 .loc 1 2335 24 + 3581 0008 7B68 ldr r3, [r7, #4] + 3582 000a 93F82030 ldrb r3, [r3, #32] + 3583 000e FB73 strb r3, [r7, #15] +2336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((state == HAL_CAN_STATE_READY) || + 3584 .loc 1 2337 6 + 3585 0010 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 3586 0012 012B cmp r3, #1 + 3587 0014 02D0 beq .L170 + 3588 .loc 1 2337 38 discriminator 1 + 3589 0016 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 3590 0018 022B cmp r3, #2 + 3591 001a 12D1 bne .L171 + 3592 .L170: +2338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (state == HAL_CAN_STATE_LISTENING)) +2339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +2340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check sleep mode acknowledge flag */ +2341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) + 3593 .loc 1 2341 14 + 3594 001c 7B68 ldr r3, [r7, #4] + 3595 001e 1B68 ldr r3, [r3] + 3596 .loc 1 2341 24 + 3597 0020 5B68 ldr r3, [r3, #4] + 3598 .loc 1 2341 30 + 3599 0022 03F00203 and r3, r3, #2 + 3600 .loc 1 2341 8 + 3601 0026 002B cmp r3, #0 + 3602 0028 02D0 beq .L172 +2342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +2343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Sleep mode is active */ +2344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** state = HAL_CAN_STATE_SLEEP_ACTIVE; + 3603 .loc 1 2344 13 + 3604 002a 0423 movs r3, #4 + 3605 002c FB73 strb r3, [r7, #15] + 3606 002e 08E0 b .L171 + 3607 .L172: +2345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +2346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Check sleep mode request flag */ +2347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else if ((hcan->Instance->MCR & CAN_MCR_SLEEP) != 0U) + 3608 .loc 1 2347 19 + 3609 0030 7B68 ldr r3, [r7, #4] + 3610 0032 1B68 ldr r3, [r3] + 3611 .loc 1 2347 29 + 3612 0034 1B68 ldr r3, [r3] + 3613 .loc 1 2347 35 + 3614 0036 03F00203 and r3, r3, #2 + 3615 .loc 1 2347 13 + 3616 003a 002B cmp r3, #0 + 3617 003c 01D0 beq .L171 +2348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +2349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Sleep mode request is pending */ + ARM GAS /tmp/ccM1MpQr.s page 123 + + +2350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** state = HAL_CAN_STATE_SLEEP_PENDING; + 3618 .loc 1 2350 13 + 3619 003e 0323 movs r3, #3 + 3620 0040 FB73 strb r3, [r7, #15] + 3621 .L171: +2351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +2352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else +2353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +2354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Neither sleep mode request nor sleep mode acknowledge */ +2355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +2356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +2357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return CAN state */ +2359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return state; + 3622 .loc 1 2359 10 + 3623 0042 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 +2360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 3624 .loc 1 2360 1 + 3625 0044 1846 mov r0, r3 + 3626 0046 1437 adds r7, r7, #20 + 3627 .cfi_def_cfa_offset 4 + 3628 0048 BD46 mov sp, r7 + 3629 .cfi_def_cfa_register 13 + 3630 @ sp needed + 3631 004a 5DF8047B ldr r7, [sp], #4 + 3632 .cfi_restore 7 + 3633 .cfi_def_cfa_offset 0 + 3634 004e 7047 bx lr + 3635 .cfi_endproc + 3636 .LFE163: + 3638 .section .text.HAL_CAN_GetError,"ax",%progbits + 3639 .align 1 + 3640 .global HAL_CAN_GetError + 3641 .syntax unified + 3642 .thumb + 3643 .thumb_func + 3645 HAL_CAN_GetError: + 3646 .LFB164: +2361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +2363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Return the CAN error code. +2364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains +2365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +2366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval CAN Error Code +2367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** uint32_t HAL_CAN_GetError(const CAN_HandleTypeDef *hcan) +2369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 3647 .loc 1 2369 1 + 3648 .cfi_startproc + 3649 @ args = 0, pretend = 0, frame = 8 + 3650 @ frame_needed = 1, uses_anonymous_args = 0 + 3651 @ link register save eliminated. + 3652 0000 80B4 push {r7} + 3653 .cfi_def_cfa_offset 4 + 3654 .cfi_offset 7, -4 + 3655 0002 83B0 sub sp, sp, #12 + 3656 .cfi_def_cfa_offset 16 + ARM GAS /tmp/ccM1MpQr.s page 124 + + + 3657 0004 00AF add r7, sp, #0 + 3658 .cfi_def_cfa_register 7 + 3659 0006 7860 str r0, [r7, #4] +2370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return CAN error code */ +2371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return hcan->ErrorCode; + 3660 .loc 1 2371 14 + 3661 0008 7B68 ldr r3, [r7, #4] + 3662 000a 5B6A ldr r3, [r3, #36] +2372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 3663 .loc 1 2372 1 + 3664 000c 1846 mov r0, r3 + 3665 000e 0C37 adds r7, r7, #12 + 3666 .cfi_def_cfa_offset 4 + 3667 0010 BD46 mov sp, r7 + 3668 .cfi_def_cfa_register 13 + 3669 @ sp needed + 3670 0012 5DF8047B ldr r7, [sp], #4 + 3671 .cfi_restore 7 + 3672 .cfi_def_cfa_offset 0 + 3673 0016 7047 bx lr + 3674 .cfi_endproc + 3675 .LFE164: + 3677 .section .text.HAL_CAN_ResetError,"ax",%progbits + 3678 .align 1 + 3679 .global HAL_CAN_ResetError + 3680 .syntax unified + 3681 .thumb + 3682 .thumb_func + 3684 HAL_CAN_ResetError: + 3685 .LFB165: +2373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /** +2375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @brief Reset the CAN error code. +2376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @param hcan pointer to a CAN_HandleTypeDef structure that contains +2377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * the configuration information for the specified CAN. +2378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** * @retval HAL status +2379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** */ +2380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan) +2381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { + 3686 .loc 1 2381 1 + 3687 .cfi_startproc + 3688 @ args = 0, pretend = 0, frame = 16 + 3689 @ frame_needed = 1, uses_anonymous_args = 0 + 3690 @ link register save eliminated. + 3691 0000 80B4 push {r7} + 3692 .cfi_def_cfa_offset 4 + 3693 .cfi_offset 7, -4 + 3694 0002 85B0 sub sp, sp, #20 + 3695 .cfi_def_cfa_offset 24 + 3696 0004 00AF add r7, sp, #0 + 3697 .cfi_def_cfa_register 7 + 3698 0006 7860 str r0, [r7, #4] +2382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_StatusTypeDef status = HAL_OK; + 3699 .loc 1 2382 21 + 3700 0008 0023 movs r3, #0 + 3701 000a FB73 strb r3, [r7, #15] +2383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** HAL_CAN_StateTypeDef state = hcan->State; + ARM GAS /tmp/ccM1MpQr.s page 125 + + + 3702 .loc 1 2383 24 + 3703 000c 7B68 ldr r3, [r7, #4] + 3704 000e 93F82030 ldrb r3, [r3, #32] + 3705 0012 BB73 strb r3, [r7, #14] +2384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** if ((state == HAL_CAN_STATE_READY) || + 3706 .loc 1 2385 6 + 3707 0014 BB7B ldrb r3, [r7, #14] @ zero_extendqisi2 + 3708 0016 012B cmp r3, #1 + 3709 0018 02D0 beq .L177 + 3710 .loc 1 2385 38 discriminator 1 + 3711 001a BB7B ldrb r3, [r7, #14] @ zero_extendqisi2 + 3712 001c 022B cmp r3, #2 + 3713 001e 03D1 bne .L178 + 3714 .L177: +2386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** (state == HAL_CAN_STATE_LISTENING)) +2387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +2388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Reset CAN error code */ +2389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode = 0U; + 3715 .loc 1 2389 21 + 3716 0020 7B68 ldr r3, [r7, #4] + 3717 0022 0022 movs r2, #0 + 3718 0024 5A62 str r2, [r3, #36] + 3719 0026 07E0 b .L179 + 3720 .L178: +2390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +2391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** else +2392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** { +2393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Update error code */ +2394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + 3721 .loc 1 2394 9 + 3722 0028 7B68 ldr r3, [r7, #4] + 3723 002a 5B6A ldr r3, [r3, #36] + 3724 .loc 1 2394 21 + 3725 002c 43F48022 orr r2, r3, #262144 + 3726 0030 7B68 ldr r3, [r7, #4] + 3727 0032 5A62 str r2, [r3, #36] +2395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** status = HAL_ERROR; + 3728 .loc 1 2396 12 + 3729 0034 0123 movs r3, #1 + 3730 0036 FB73 strb r3, [r7, #15] + 3731 .L179: +2397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } +2398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** +2399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** /* Return the status */ +2400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** return status; + 3732 .loc 1 2400 10 + 3733 0038 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 +2401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_can.c **** } + 3734 .loc 1 2401 1 + 3735 003a 1846 mov r0, r3 + 3736 003c 1437 adds r7, r7, #20 + 3737 .cfi_def_cfa_offset 4 + 3738 003e BD46 mov sp, r7 + 3739 .cfi_def_cfa_register 13 + 3740 @ sp needed + ARM GAS /tmp/ccM1MpQr.s page 126 + + + 3741 0040 5DF8047B ldr r7, [sp], #4 + 3742 .cfi_restore 7 + 3743 .cfi_def_cfa_offset 0 + 3744 0044 7047 bx lr + 3745 .cfi_endproc + 3746 .LFE165: + 3748 .text + 3749 .Letext0: + 3750 .file 3 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 3751 .file 4 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 3752 .file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + 3753 .file 6 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h" + 3754 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h" + 3755 .file 8 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h" + 3756 .file 9 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h" + ARM GAS /tmp/ccM1MpQr.s page 127 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f3xx_hal_can.c + /tmp/ccM1MpQr.s:21 .text.HAL_CAN_Init:00000000 $t + /tmp/ccM1MpQr.s:27 .text.HAL_CAN_Init:00000000 HAL_CAN_Init + /tmp/ccM1MpQr.s:421 .text.HAL_CAN_MspInit:00000000 HAL_CAN_MspInit + /tmp/ccM1MpQr.s:349 .text.HAL_CAN_DeInit:00000000 $t + /tmp/ccM1MpQr.s:355 .text.HAL_CAN_DeInit:00000000 HAL_CAN_DeInit + /tmp/ccM1MpQr.s:871 .text.HAL_CAN_Stop:00000000 HAL_CAN_Stop + /tmp/ccM1MpQr.s:457 .text.HAL_CAN_MspDeInit:00000000 HAL_CAN_MspDeInit + /tmp/ccM1MpQr.s:415 .text.HAL_CAN_MspInit:00000000 $t + /tmp/ccM1MpQr.s:451 .text.HAL_CAN_MspDeInit:00000000 $t + /tmp/ccM1MpQr.s:487 .text.HAL_CAN_ConfigFilter:00000000 $t + /tmp/ccM1MpQr.s:493 .text.HAL_CAN_ConfigFilter:00000000 HAL_CAN_ConfigFilter + /tmp/ccM1MpQr.s:755 .text.HAL_CAN_Start:00000000 $t + /tmp/ccM1MpQr.s:761 .text.HAL_CAN_Start:00000000 HAL_CAN_Start + /tmp/ccM1MpQr.s:865 .text.HAL_CAN_Stop:00000000 $t + /tmp/ccM1MpQr.s:979 .text.HAL_CAN_RequestSleep:00000000 $t + /tmp/ccM1MpQr.s:985 .text.HAL_CAN_RequestSleep:00000000 HAL_CAN_RequestSleep + /tmp/ccM1MpQr.s:1050 .text.HAL_CAN_WakeUp:00000000 $t + /tmp/ccM1MpQr.s:1056 .text.HAL_CAN_WakeUp:00000000 HAL_CAN_WakeUp + /tmp/ccM1MpQr.s:1158 .text.HAL_CAN_WakeUp:00000080 $d + /tmp/ccM1MpQr.s:1163 .text.HAL_CAN_IsSleepActive:00000000 $t + /tmp/ccM1MpQr.s:1169 .text.HAL_CAN_IsSleepActive:00000000 HAL_CAN_IsSleepActive + /tmp/ccM1MpQr.s:1231 .text.HAL_CAN_AddTxMessage:00000000 $t + /tmp/ccM1MpQr.s:1237 .text.HAL_CAN_AddTxMessage:00000000 HAL_CAN_AddTxMessage + /tmp/ccM1MpQr.s:1505 .text.HAL_CAN_AbortTxRequest:00000000 $t + /tmp/ccM1MpQr.s:1511 .text.HAL_CAN_AbortTxRequest:00000000 HAL_CAN_AbortTxRequest + /tmp/ccM1MpQr.s:1614 .text.HAL_CAN_GetTxMailboxesFreeLevel:00000000 $t + /tmp/ccM1MpQr.s:1620 .text.HAL_CAN_GetTxMailboxesFreeLevel:00000000 HAL_CAN_GetTxMailboxesFreeLevel + /tmp/ccM1MpQr.s:1713 .text.HAL_CAN_IsTxMessagePending:00000000 $t + /tmp/ccM1MpQr.s:1719 .text.HAL_CAN_IsTxMessagePending:00000000 HAL_CAN_IsTxMessagePending + /tmp/ccM1MpQr.s:1788 .text.HAL_CAN_GetTxTimestamp:00000000 $t + /tmp/ccM1MpQr.s:1794 .text.HAL_CAN_GetTxTimestamp:00000000 HAL_CAN_GetTxTimestamp + /tmp/ccM1MpQr.s:1883 .text.HAL_CAN_GetRxMessage:00000000 $t + /tmp/ccM1MpQr.s:1889 .text.HAL_CAN_GetRxMessage:00000000 HAL_CAN_GetRxMessage + /tmp/ccM1MpQr.s:2292 .text.HAL_CAN_GetRxFifoFillLevel:00000000 $t + /tmp/ccM1MpQr.s:2298 .text.HAL_CAN_GetRxFifoFillLevel:00000000 HAL_CAN_GetRxFifoFillLevel + /tmp/ccM1MpQr.s:2370 .text.HAL_CAN_ActivateNotification:00000000 $t + /tmp/ccM1MpQr.s:2376 .text.HAL_CAN_ActivateNotification:00000000 HAL_CAN_ActivateNotification + /tmp/ccM1MpQr.s:2443 .text.HAL_CAN_DeactivateNotification:00000000 $t + /tmp/ccM1MpQr.s:2449 .text.HAL_CAN_DeactivateNotification:00000000 HAL_CAN_DeactivateNotification + /tmp/ccM1MpQr.s:2517 .text.HAL_CAN_IRQHandler:00000000 $t + /tmp/ccM1MpQr.s:2523 .text.HAL_CAN_IRQHandler:00000000 HAL_CAN_IRQHandler + /tmp/ccM1MpQr.s:3097 .text.HAL_CAN_TxMailbox0CompleteCallback:00000000 HAL_CAN_TxMailbox0CompleteCallback + /tmp/ccM1MpQr.s:3205 .text.HAL_CAN_TxMailbox0AbortCallback:00000000 HAL_CAN_TxMailbox0AbortCallback + /tmp/ccM1MpQr.s:3133 .text.HAL_CAN_TxMailbox1CompleteCallback:00000000 HAL_CAN_TxMailbox1CompleteCallback + /tmp/ccM1MpQr.s:3241 .text.HAL_CAN_TxMailbox1AbortCallback:00000000 HAL_CAN_TxMailbox1AbortCallback + /tmp/ccM1MpQr.s:3169 .text.HAL_CAN_TxMailbox2CompleteCallback:00000000 HAL_CAN_TxMailbox2CompleteCallback + /tmp/ccM1MpQr.s:3277 .text.HAL_CAN_TxMailbox2AbortCallback:00000000 HAL_CAN_TxMailbox2AbortCallback + /tmp/ccM1MpQr.s:3349 .text.HAL_CAN_RxFifo0FullCallback:00000000 HAL_CAN_RxFifo0FullCallback + /tmp/ccM1MpQr.s:3313 .text.HAL_CAN_RxFifo0MsgPendingCallback:00000000 HAL_CAN_RxFifo0MsgPendingCallback + /tmp/ccM1MpQr.s:3421 .text.HAL_CAN_RxFifo1FullCallback:00000000 HAL_CAN_RxFifo1FullCallback + /tmp/ccM1MpQr.s:3385 .text.HAL_CAN_RxFifo1MsgPendingCallback:00000000 HAL_CAN_RxFifo1MsgPendingCallback + /tmp/ccM1MpQr.s:3457 .text.HAL_CAN_SleepCallback:00000000 HAL_CAN_SleepCallback + /tmp/ccM1MpQr.s:3493 .text.HAL_CAN_WakeUpFromRxMsgCallback:00000000 HAL_CAN_WakeUpFromRxMsgCallback + /tmp/ccM1MpQr.s:3529 .text.HAL_CAN_ErrorCallback:00000000 HAL_CAN_ErrorCallback + /tmp/ccM1MpQr.s:3091 .text.HAL_CAN_TxMailbox0CompleteCallback:00000000 $t + ARM GAS /tmp/ccM1MpQr.s page 128 + + + /tmp/ccM1MpQr.s:3127 .text.HAL_CAN_TxMailbox1CompleteCallback:00000000 $t + /tmp/ccM1MpQr.s:3163 .text.HAL_CAN_TxMailbox2CompleteCallback:00000000 $t + /tmp/ccM1MpQr.s:3199 .text.HAL_CAN_TxMailbox0AbortCallback:00000000 $t + /tmp/ccM1MpQr.s:3235 .text.HAL_CAN_TxMailbox1AbortCallback:00000000 $t + /tmp/ccM1MpQr.s:3271 .text.HAL_CAN_TxMailbox2AbortCallback:00000000 $t + /tmp/ccM1MpQr.s:3307 .text.HAL_CAN_RxFifo0MsgPendingCallback:00000000 $t + /tmp/ccM1MpQr.s:3343 .text.HAL_CAN_RxFifo0FullCallback:00000000 $t + /tmp/ccM1MpQr.s:3379 .text.HAL_CAN_RxFifo1MsgPendingCallback:00000000 $t + /tmp/ccM1MpQr.s:3415 .text.HAL_CAN_RxFifo1FullCallback:00000000 $t + /tmp/ccM1MpQr.s:3451 .text.HAL_CAN_SleepCallback:00000000 $t + /tmp/ccM1MpQr.s:3487 .text.HAL_CAN_WakeUpFromRxMsgCallback:00000000 $t + /tmp/ccM1MpQr.s:3523 .text.HAL_CAN_ErrorCallback:00000000 $t + /tmp/ccM1MpQr.s:3559 .text.HAL_CAN_GetState:00000000 $t + /tmp/ccM1MpQr.s:3565 .text.HAL_CAN_GetState:00000000 HAL_CAN_GetState + /tmp/ccM1MpQr.s:3639 .text.HAL_CAN_GetError:00000000 $t + /tmp/ccM1MpQr.s:3645 .text.HAL_CAN_GetError:00000000 HAL_CAN_GetError + /tmp/ccM1MpQr.s:3678 .text.HAL_CAN_ResetError:00000000 $t + /tmp/ccM1MpQr.s:3684 .text.HAL_CAN_ResetError:00000000 HAL_CAN_ResetError + +UNDEFINED SYMBOLS +HAL_GetTick diff --git a/Software/build/stm32f3xx_hal_can.o b/Software/build/stm32f3xx_hal_can.o new file mode 100644 index 0000000..c1e899a Binary files /dev/null and b/Software/build/stm32f3xx_hal_can.o differ diff --git a/Software/build/stm32f3xx_hal_cortex.d b/Software/build/stm32f3xx_hal_cortex.d new file mode 100644 index 0000000..c171c84 --- /dev/null +++ b/Software/build/stm32f3xx_hal_cortex.d @@ -0,0 +1,62 @@ +build/stm32f3xx_hal_cortex.o: \ + Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + Core/Inc/stm32f3xx_hal_conf.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h: diff --git a/Software/build/stm32f3xx_hal_cortex.lst b/Software/build/stm32f3xx_hal_cortex.lst new file mode 100644 index 0000000..8c8e019 --- /dev/null +++ b/Software/build/stm32f3xx_hal_cortex.lst @@ -0,0 +1,5558 @@ +ARM GAS /tmp/ccwFmvCn.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 6 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "stm32f3xx_hal_cortex.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c" + 20 .section .text.__NVIC_SetPriorityGrouping,"ax",%progbits + 21 .align 1 + 22 .syntax unified + 23 .thumb + 24 .thumb_func + 26 __NVIC_SetPriorityGrouping: + 27 .LFB102: + 28 .file 2 "Drivers/CMSIS/Include/core_cm4.h" + 1:Drivers/CMSIS/Include/core_cm4.h **** /**************************************************************************//** + 2:Drivers/CMSIS/Include/core_cm4.h **** * @file core_cm4.h + 3:Drivers/CMSIS/Include/core_cm4.h **** * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + 4:Drivers/CMSIS/Include/core_cm4.h **** * @version V5.0.8 + 5:Drivers/CMSIS/Include/core_cm4.h **** * @date 04. June 2018 + 6:Drivers/CMSIS/Include/core_cm4.h **** ******************************************************************************/ + 7:Drivers/CMSIS/Include/core_cm4.h **** /* + 8:Drivers/CMSIS/Include/core_cm4.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + 9:Drivers/CMSIS/Include/core_cm4.h **** * + 10:Drivers/CMSIS/Include/core_cm4.h **** * SPDX-License-Identifier: Apache-2.0 + 11:Drivers/CMSIS/Include/core_cm4.h **** * + 12:Drivers/CMSIS/Include/core_cm4.h **** * Licensed under the Apache License, Version 2.0 (the License); you may + 13:Drivers/CMSIS/Include/core_cm4.h **** * not use this file except in compliance with the License. + 14:Drivers/CMSIS/Include/core_cm4.h **** * You may obtain a copy of the License at + 15:Drivers/CMSIS/Include/core_cm4.h **** * + 16:Drivers/CMSIS/Include/core_cm4.h **** * www.apache.org/licenses/LICENSE-2.0 + 17:Drivers/CMSIS/Include/core_cm4.h **** * + 18:Drivers/CMSIS/Include/core_cm4.h **** * Unless required by applicable law or agreed to in writing, software + 19:Drivers/CMSIS/Include/core_cm4.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT + 20:Drivers/CMSIS/Include/core_cm4.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + 21:Drivers/CMSIS/Include/core_cm4.h **** * See the License for the specific language governing permissions and + 22:Drivers/CMSIS/Include/core_cm4.h **** * limitations under the License. + 23:Drivers/CMSIS/Include/core_cm4.h **** */ + 24:Drivers/CMSIS/Include/core_cm4.h **** + 25:Drivers/CMSIS/Include/core_cm4.h **** #if defined ( __ICCARM__ ) + 26:Drivers/CMSIS/Include/core_cm4.h **** #pragma system_include /* treat file as system include file for MISRA check */ + 27:Drivers/CMSIS/Include/core_cm4.h **** #elif defined (__clang__) + 28:Drivers/CMSIS/Include/core_cm4.h **** #pragma clang system_header /* treat file as system include file */ + 29:Drivers/CMSIS/Include/core_cm4.h **** #endif + 30:Drivers/CMSIS/Include/core_cm4.h **** + ARM GAS /tmp/ccwFmvCn.s page 2 + + + 31:Drivers/CMSIS/Include/core_cm4.h **** #ifndef __CORE_CM4_H_GENERIC + 32:Drivers/CMSIS/Include/core_cm4.h **** #define __CORE_CM4_H_GENERIC + 33:Drivers/CMSIS/Include/core_cm4.h **** + 34:Drivers/CMSIS/Include/core_cm4.h **** #include + 35:Drivers/CMSIS/Include/core_cm4.h **** + 36:Drivers/CMSIS/Include/core_cm4.h **** #ifdef __cplusplus + 37:Drivers/CMSIS/Include/core_cm4.h **** extern "C" { + 38:Drivers/CMSIS/Include/core_cm4.h **** #endif + 39:Drivers/CMSIS/Include/core_cm4.h **** + 40:Drivers/CMSIS/Include/core_cm4.h **** /** + 41:Drivers/CMSIS/Include/core_cm4.h **** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + 42:Drivers/CMSIS/Include/core_cm4.h **** CMSIS violates the following MISRA-C:2004 rules: + 43:Drivers/CMSIS/Include/core_cm4.h **** + 44:Drivers/CMSIS/Include/core_cm4.h **** \li Required Rule 8.5, object/function definition in header file.
+ 45:Drivers/CMSIS/Include/core_cm4.h **** Function definitions in header files are used to allow 'inlining'. + 46:Drivers/CMSIS/Include/core_cm4.h **** + 47:Drivers/CMSIS/Include/core_cm4.h **** \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ 48:Drivers/CMSIS/Include/core_cm4.h **** Unions are used for effective representation of core registers. + 49:Drivers/CMSIS/Include/core_cm4.h **** + 50:Drivers/CMSIS/Include/core_cm4.h **** \li Advisory Rule 19.7, Function-like macro defined.
+ 51:Drivers/CMSIS/Include/core_cm4.h **** Function-like macros are used to allow more efficient code. + 52:Drivers/CMSIS/Include/core_cm4.h **** */ + 53:Drivers/CMSIS/Include/core_cm4.h **** + 54:Drivers/CMSIS/Include/core_cm4.h **** + 55:Drivers/CMSIS/Include/core_cm4.h **** /******************************************************************************* + 56:Drivers/CMSIS/Include/core_cm4.h **** * CMSIS definitions + 57:Drivers/CMSIS/Include/core_cm4.h **** ******************************************************************************/ + 58:Drivers/CMSIS/Include/core_cm4.h **** /** + 59:Drivers/CMSIS/Include/core_cm4.h **** \ingroup Cortex_M4 + 60:Drivers/CMSIS/Include/core_cm4.h **** @{ + 61:Drivers/CMSIS/Include/core_cm4.h **** */ + 62:Drivers/CMSIS/Include/core_cm4.h **** + 63:Drivers/CMSIS/Include/core_cm4.h **** #include "cmsis_version.h" + 64:Drivers/CMSIS/Include/core_cm4.h **** + 65:Drivers/CMSIS/Include/core_cm4.h **** /* CMSIS CM4 definitions */ + 66:Drivers/CMSIS/Include/core_cm4.h **** #define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] C + 67:Drivers/CMSIS/Include/core_cm4.h **** #define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] C + 68:Drivers/CMSIS/Include/core_cm4.h **** #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + 69:Drivers/CMSIS/Include/core_cm4.h **** __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL + 70:Drivers/CMSIS/Include/core_cm4.h **** + 71:Drivers/CMSIS/Include/core_cm4.h **** #define __CORTEX_M (4U) /*!< Cortex-M Core */ + 72:Drivers/CMSIS/Include/core_cm4.h **** + 73:Drivers/CMSIS/Include/core_cm4.h **** /** __FPU_USED indicates whether an FPU is used or not. + 74:Drivers/CMSIS/Include/core_cm4.h **** For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and fun + 75:Drivers/CMSIS/Include/core_cm4.h **** */ + 76:Drivers/CMSIS/Include/core_cm4.h **** #if defined ( __CC_ARM ) + 77:Drivers/CMSIS/Include/core_cm4.h **** #if defined __TARGET_FPU_VFP + 78:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + 79:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 1U + 80:Drivers/CMSIS/Include/core_cm4.h **** #else + 81:Drivers/CMSIS/Include/core_cm4.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) + 82:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U + 83:Drivers/CMSIS/Include/core_cm4.h **** #endif + 84:Drivers/CMSIS/Include/core_cm4.h **** #else + 85:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U + 86:Drivers/CMSIS/Include/core_cm4.h **** #endif + 87:Drivers/CMSIS/Include/core_cm4.h **** + ARM GAS /tmp/ccwFmvCn.s page 3 + + + 88:Drivers/CMSIS/Include/core_cm4.h **** #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + 89:Drivers/CMSIS/Include/core_cm4.h **** #if defined __ARM_PCS_VFP + 90:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + 91:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 1U + 92:Drivers/CMSIS/Include/core_cm4.h **** #else + 93:Drivers/CMSIS/Include/core_cm4.h **** #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESEN + 94:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U + 95:Drivers/CMSIS/Include/core_cm4.h **** #endif + 96:Drivers/CMSIS/Include/core_cm4.h **** #else + 97:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U + 98:Drivers/CMSIS/Include/core_cm4.h **** #endif + 99:Drivers/CMSIS/Include/core_cm4.h **** + 100:Drivers/CMSIS/Include/core_cm4.h **** #elif defined ( __GNUC__ ) + 101:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__VFP_FP__) && !defined(__SOFTFP__) + 102:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + 103:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 1U + 104:Drivers/CMSIS/Include/core_cm4.h **** #else + 105:Drivers/CMSIS/Include/core_cm4.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) + 106:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U + 107:Drivers/CMSIS/Include/core_cm4.h **** #endif + 108:Drivers/CMSIS/Include/core_cm4.h **** #else + 109:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U + 110:Drivers/CMSIS/Include/core_cm4.h **** #endif + 111:Drivers/CMSIS/Include/core_cm4.h **** + 112:Drivers/CMSIS/Include/core_cm4.h **** #elif defined ( __ICCARM__ ) + 113:Drivers/CMSIS/Include/core_cm4.h **** #if defined __ARMVFP__ + 114:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + 115:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 1U + 116:Drivers/CMSIS/Include/core_cm4.h **** #else + 117:Drivers/CMSIS/Include/core_cm4.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) + 118:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U + 119:Drivers/CMSIS/Include/core_cm4.h **** #endif + 120:Drivers/CMSIS/Include/core_cm4.h **** #else + 121:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U + 122:Drivers/CMSIS/Include/core_cm4.h **** #endif + 123:Drivers/CMSIS/Include/core_cm4.h **** + 124:Drivers/CMSIS/Include/core_cm4.h **** #elif defined ( __TI_ARM__ ) + 125:Drivers/CMSIS/Include/core_cm4.h **** #if defined __TI_VFP_SUPPORT__ + 126:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + 127:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 1U + 128:Drivers/CMSIS/Include/core_cm4.h **** #else + 129:Drivers/CMSIS/Include/core_cm4.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) + 130:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U + 131:Drivers/CMSIS/Include/core_cm4.h **** #endif + 132:Drivers/CMSIS/Include/core_cm4.h **** #else + 133:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U + 134:Drivers/CMSIS/Include/core_cm4.h **** #endif + 135:Drivers/CMSIS/Include/core_cm4.h **** + 136:Drivers/CMSIS/Include/core_cm4.h **** #elif defined ( __TASKING__ ) + 137:Drivers/CMSIS/Include/core_cm4.h **** #if defined __FPU_VFP__ + 138:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + 139:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 1U + 140:Drivers/CMSIS/Include/core_cm4.h **** #else + 141:Drivers/CMSIS/Include/core_cm4.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) + 142:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U + 143:Drivers/CMSIS/Include/core_cm4.h **** #endif + 144:Drivers/CMSIS/Include/core_cm4.h **** #else + ARM GAS /tmp/ccwFmvCn.s page 4 + + + 145:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U + 146:Drivers/CMSIS/Include/core_cm4.h **** #endif + 147:Drivers/CMSIS/Include/core_cm4.h **** + 148:Drivers/CMSIS/Include/core_cm4.h **** #elif defined ( __CSMC__ ) + 149:Drivers/CMSIS/Include/core_cm4.h **** #if ( __CSMC__ & 0x400U) + 150:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + 151:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 1U + 152:Drivers/CMSIS/Include/core_cm4.h **** #else + 153:Drivers/CMSIS/Include/core_cm4.h **** #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT) + 154:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U + 155:Drivers/CMSIS/Include/core_cm4.h **** #endif + 156:Drivers/CMSIS/Include/core_cm4.h **** #else + 157:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_USED 0U + 158:Drivers/CMSIS/Include/core_cm4.h **** #endif + 159:Drivers/CMSIS/Include/core_cm4.h **** + 160:Drivers/CMSIS/Include/core_cm4.h **** #endif + 161:Drivers/CMSIS/Include/core_cm4.h **** + 162:Drivers/CMSIS/Include/core_cm4.h **** #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + 163:Drivers/CMSIS/Include/core_cm4.h **** + 164:Drivers/CMSIS/Include/core_cm4.h **** + 165:Drivers/CMSIS/Include/core_cm4.h **** #ifdef __cplusplus + 166:Drivers/CMSIS/Include/core_cm4.h **** } + 167:Drivers/CMSIS/Include/core_cm4.h **** #endif + 168:Drivers/CMSIS/Include/core_cm4.h **** + 169:Drivers/CMSIS/Include/core_cm4.h **** #endif /* __CORE_CM4_H_GENERIC */ + 170:Drivers/CMSIS/Include/core_cm4.h **** + 171:Drivers/CMSIS/Include/core_cm4.h **** #ifndef __CMSIS_GENERIC + 172:Drivers/CMSIS/Include/core_cm4.h **** + 173:Drivers/CMSIS/Include/core_cm4.h **** #ifndef __CORE_CM4_H_DEPENDANT + 174:Drivers/CMSIS/Include/core_cm4.h **** #define __CORE_CM4_H_DEPENDANT + 175:Drivers/CMSIS/Include/core_cm4.h **** + 176:Drivers/CMSIS/Include/core_cm4.h **** #ifdef __cplusplus + 177:Drivers/CMSIS/Include/core_cm4.h **** extern "C" { + 178:Drivers/CMSIS/Include/core_cm4.h **** #endif + 179:Drivers/CMSIS/Include/core_cm4.h **** + 180:Drivers/CMSIS/Include/core_cm4.h **** /* check device defines and use defaults */ + 181:Drivers/CMSIS/Include/core_cm4.h **** #if defined __CHECK_DEVICE_DEFINES + 182:Drivers/CMSIS/Include/core_cm4.h **** #ifndef __CM4_REV + 183:Drivers/CMSIS/Include/core_cm4.h **** #define __CM4_REV 0x0000U + 184:Drivers/CMSIS/Include/core_cm4.h **** #warning "__CM4_REV not defined in device header file; using default!" + 185:Drivers/CMSIS/Include/core_cm4.h **** #endif + 186:Drivers/CMSIS/Include/core_cm4.h **** + 187:Drivers/CMSIS/Include/core_cm4.h **** #ifndef __FPU_PRESENT + 188:Drivers/CMSIS/Include/core_cm4.h **** #define __FPU_PRESENT 0U + 189:Drivers/CMSIS/Include/core_cm4.h **** #warning "__FPU_PRESENT not defined in device header file; using default!" + 190:Drivers/CMSIS/Include/core_cm4.h **** #endif + 191:Drivers/CMSIS/Include/core_cm4.h **** + 192:Drivers/CMSIS/Include/core_cm4.h **** #ifndef __MPU_PRESENT + 193:Drivers/CMSIS/Include/core_cm4.h **** #define __MPU_PRESENT 0U + 194:Drivers/CMSIS/Include/core_cm4.h **** #warning "__MPU_PRESENT not defined in device header file; using default!" + 195:Drivers/CMSIS/Include/core_cm4.h **** #endif + 196:Drivers/CMSIS/Include/core_cm4.h **** + 197:Drivers/CMSIS/Include/core_cm4.h **** #ifndef __NVIC_PRIO_BITS + 198:Drivers/CMSIS/Include/core_cm4.h **** #define __NVIC_PRIO_BITS 3U + 199:Drivers/CMSIS/Include/core_cm4.h **** #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + 200:Drivers/CMSIS/Include/core_cm4.h **** #endif + 201:Drivers/CMSIS/Include/core_cm4.h **** + ARM GAS /tmp/ccwFmvCn.s page 5 + + + 202:Drivers/CMSIS/Include/core_cm4.h **** #ifndef __Vendor_SysTickConfig + 203:Drivers/CMSIS/Include/core_cm4.h **** #define __Vendor_SysTickConfig 0U + 204:Drivers/CMSIS/Include/core_cm4.h **** #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + 205:Drivers/CMSIS/Include/core_cm4.h **** #endif + 206:Drivers/CMSIS/Include/core_cm4.h **** #endif + 207:Drivers/CMSIS/Include/core_cm4.h **** + 208:Drivers/CMSIS/Include/core_cm4.h **** /* IO definitions (access restrictions to peripheral registers) */ + 209:Drivers/CMSIS/Include/core_cm4.h **** /** + 210:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_glob_defs CMSIS Global Defines + 211:Drivers/CMSIS/Include/core_cm4.h **** + 212:Drivers/CMSIS/Include/core_cm4.h **** IO Type Qualifiers are used + 213:Drivers/CMSIS/Include/core_cm4.h **** \li to specify the access to peripheral variables. + 214:Drivers/CMSIS/Include/core_cm4.h **** \li for automatic generation of peripheral register debug information. + 215:Drivers/CMSIS/Include/core_cm4.h **** */ + 216:Drivers/CMSIS/Include/core_cm4.h **** #ifdef __cplusplus + 217:Drivers/CMSIS/Include/core_cm4.h **** #define __I volatile /*!< Defines 'read only' permissions */ + 218:Drivers/CMSIS/Include/core_cm4.h **** #else + 219:Drivers/CMSIS/Include/core_cm4.h **** #define __I volatile const /*!< Defines 'read only' permissions */ + 220:Drivers/CMSIS/Include/core_cm4.h **** #endif + 221:Drivers/CMSIS/Include/core_cm4.h **** #define __O volatile /*!< Defines 'write only' permissions */ + 222:Drivers/CMSIS/Include/core_cm4.h **** #define __IO volatile /*!< Defines 'read / write' permissions */ + 223:Drivers/CMSIS/Include/core_cm4.h **** + 224:Drivers/CMSIS/Include/core_cm4.h **** /* following defines should be used for structure members */ + 225:Drivers/CMSIS/Include/core_cm4.h **** #define __IM volatile const /*! Defines 'read only' structure member permissions */ + 226:Drivers/CMSIS/Include/core_cm4.h **** #define __OM volatile /*! Defines 'write only' structure member permissions */ + 227:Drivers/CMSIS/Include/core_cm4.h **** #define __IOM volatile /*! Defines 'read / write' structure member permissions */ + 228:Drivers/CMSIS/Include/core_cm4.h **** + 229:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group Cortex_M4 */ + 230:Drivers/CMSIS/Include/core_cm4.h **** + 231:Drivers/CMSIS/Include/core_cm4.h **** + 232:Drivers/CMSIS/Include/core_cm4.h **** + 233:Drivers/CMSIS/Include/core_cm4.h **** /******************************************************************************* + 234:Drivers/CMSIS/Include/core_cm4.h **** * Register Abstraction + 235:Drivers/CMSIS/Include/core_cm4.h **** Core Register contain: + 236:Drivers/CMSIS/Include/core_cm4.h **** - Core Register + 237:Drivers/CMSIS/Include/core_cm4.h **** - Core NVIC Register + 238:Drivers/CMSIS/Include/core_cm4.h **** - Core SCB Register + 239:Drivers/CMSIS/Include/core_cm4.h **** - Core SysTick Register + 240:Drivers/CMSIS/Include/core_cm4.h **** - Core Debug Register + 241:Drivers/CMSIS/Include/core_cm4.h **** - Core MPU Register + 242:Drivers/CMSIS/Include/core_cm4.h **** - Core FPU Register + 243:Drivers/CMSIS/Include/core_cm4.h **** ******************************************************************************/ + 244:Drivers/CMSIS/Include/core_cm4.h **** /** + 245:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_core_register Defines and Type Definitions + 246:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions and defines for Cortex-M processor based devices. + 247:Drivers/CMSIS/Include/core_cm4.h **** */ + 248:Drivers/CMSIS/Include/core_cm4.h **** + 249:Drivers/CMSIS/Include/core_cm4.h **** /** + 250:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register + 251:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_CORE Status and Control Registers + 252:Drivers/CMSIS/Include/core_cm4.h **** \brief Core Register type definitions. + 253:Drivers/CMSIS/Include/core_cm4.h **** @{ + 254:Drivers/CMSIS/Include/core_cm4.h **** */ + 255:Drivers/CMSIS/Include/core_cm4.h **** + 256:Drivers/CMSIS/Include/core_cm4.h **** /** + 257:Drivers/CMSIS/Include/core_cm4.h **** \brief Union type to access the Application Program Status Register (APSR). + 258:Drivers/CMSIS/Include/core_cm4.h **** */ + ARM GAS /tmp/ccwFmvCn.s page 6 + + + 259:Drivers/CMSIS/Include/core_cm4.h **** typedef union + 260:Drivers/CMSIS/Include/core_cm4.h **** { + 261:Drivers/CMSIS/Include/core_cm4.h **** struct + 262:Drivers/CMSIS/Include/core_cm4.h **** { + 263:Drivers/CMSIS/Include/core_cm4.h **** uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + 264:Drivers/CMSIS/Include/core_cm4.h **** uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + 265:Drivers/CMSIS/Include/core_cm4.h **** uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + 266:Drivers/CMSIS/Include/core_cm4.h **** uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + 267:Drivers/CMSIS/Include/core_cm4.h **** uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + 268:Drivers/CMSIS/Include/core_cm4.h **** uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + 269:Drivers/CMSIS/Include/core_cm4.h **** uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + 270:Drivers/CMSIS/Include/core_cm4.h **** uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + 271:Drivers/CMSIS/Include/core_cm4.h **** } b; /*!< Structure used for bit access */ + 272:Drivers/CMSIS/Include/core_cm4.h **** uint32_t w; /*!< Type used for word access */ + 273:Drivers/CMSIS/Include/core_cm4.h **** } APSR_Type; + 274:Drivers/CMSIS/Include/core_cm4.h **** + 275:Drivers/CMSIS/Include/core_cm4.h **** /* APSR Register Definitions */ + 276:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_N_Pos 31U /*!< APSR + 277:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR + 278:Drivers/CMSIS/Include/core_cm4.h **** + 279:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_Z_Pos 30U /*!< APSR + 280:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR + 281:Drivers/CMSIS/Include/core_cm4.h **** + 282:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_C_Pos 29U /*!< APSR + 283:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR + 284:Drivers/CMSIS/Include/core_cm4.h **** + 285:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_V_Pos 28U /*!< APSR + 286:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR + 287:Drivers/CMSIS/Include/core_cm4.h **** + 288:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_Q_Pos 27U /*!< APSR + 289:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR + 290:Drivers/CMSIS/Include/core_cm4.h **** + 291:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_GE_Pos 16U /*!< APSR + 292:Drivers/CMSIS/Include/core_cm4.h **** #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR + 293:Drivers/CMSIS/Include/core_cm4.h **** + 294:Drivers/CMSIS/Include/core_cm4.h **** + 295:Drivers/CMSIS/Include/core_cm4.h **** /** + 296:Drivers/CMSIS/Include/core_cm4.h **** \brief Union type to access the Interrupt Program Status Register (IPSR). + 297:Drivers/CMSIS/Include/core_cm4.h **** */ + 298:Drivers/CMSIS/Include/core_cm4.h **** typedef union + 299:Drivers/CMSIS/Include/core_cm4.h **** { + 300:Drivers/CMSIS/Include/core_cm4.h **** struct + 301:Drivers/CMSIS/Include/core_cm4.h **** { + 302:Drivers/CMSIS/Include/core_cm4.h **** uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + 303:Drivers/CMSIS/Include/core_cm4.h **** uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + 304:Drivers/CMSIS/Include/core_cm4.h **** } b; /*!< Structure used for bit access */ + 305:Drivers/CMSIS/Include/core_cm4.h **** uint32_t w; /*!< Type used for word access */ + 306:Drivers/CMSIS/Include/core_cm4.h **** } IPSR_Type; + 307:Drivers/CMSIS/Include/core_cm4.h **** + 308:Drivers/CMSIS/Include/core_cm4.h **** /* IPSR Register Definitions */ + 309:Drivers/CMSIS/Include/core_cm4.h **** #define IPSR_ISR_Pos 0U /*!< IPSR + 310:Drivers/CMSIS/Include/core_cm4.h **** #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR + 311:Drivers/CMSIS/Include/core_cm4.h **** + 312:Drivers/CMSIS/Include/core_cm4.h **** + 313:Drivers/CMSIS/Include/core_cm4.h **** /** + 314:Drivers/CMSIS/Include/core_cm4.h **** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + 315:Drivers/CMSIS/Include/core_cm4.h **** */ + ARM GAS /tmp/ccwFmvCn.s page 7 + + + 316:Drivers/CMSIS/Include/core_cm4.h **** typedef union + 317:Drivers/CMSIS/Include/core_cm4.h **** { + 318:Drivers/CMSIS/Include/core_cm4.h **** struct + 319:Drivers/CMSIS/Include/core_cm4.h **** { + 320:Drivers/CMSIS/Include/core_cm4.h **** uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + 321:Drivers/CMSIS/Include/core_cm4.h **** uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + 322:Drivers/CMSIS/Include/core_cm4.h **** uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + 323:Drivers/CMSIS/Include/core_cm4.h **** uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + 324:Drivers/CMSIS/Include/core_cm4.h **** uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + 325:Drivers/CMSIS/Include/core_cm4.h **** uint32_t T:1; /*!< bit: 24 Thumb bit */ + 326:Drivers/CMSIS/Include/core_cm4.h **** uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + 327:Drivers/CMSIS/Include/core_cm4.h **** uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + 328:Drivers/CMSIS/Include/core_cm4.h **** uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + 329:Drivers/CMSIS/Include/core_cm4.h **** uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + 330:Drivers/CMSIS/Include/core_cm4.h **** uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + 331:Drivers/CMSIS/Include/core_cm4.h **** uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + 332:Drivers/CMSIS/Include/core_cm4.h **** } b; /*!< Structure used for bit access */ + 333:Drivers/CMSIS/Include/core_cm4.h **** uint32_t w; /*!< Type used for word access */ + 334:Drivers/CMSIS/Include/core_cm4.h **** } xPSR_Type; + 335:Drivers/CMSIS/Include/core_cm4.h **** + 336:Drivers/CMSIS/Include/core_cm4.h **** /* xPSR Register Definitions */ + 337:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_N_Pos 31U /*!< xPSR + 338:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR + 339:Drivers/CMSIS/Include/core_cm4.h **** + 340:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_Z_Pos 30U /*!< xPSR + 341:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR + 342:Drivers/CMSIS/Include/core_cm4.h **** + 343:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_C_Pos 29U /*!< xPSR + 344:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR + 345:Drivers/CMSIS/Include/core_cm4.h **** + 346:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_V_Pos 28U /*!< xPSR + 347:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR + 348:Drivers/CMSIS/Include/core_cm4.h **** + 349:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_Q_Pos 27U /*!< xPSR + 350:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR + 351:Drivers/CMSIS/Include/core_cm4.h **** + 352:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR + 353:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR + 354:Drivers/CMSIS/Include/core_cm4.h **** + 355:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_T_Pos 24U /*!< xPSR + 356:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR + 357:Drivers/CMSIS/Include/core_cm4.h **** + 358:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_GE_Pos 16U /*!< xPSR + 359:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR + 360:Drivers/CMSIS/Include/core_cm4.h **** + 361:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR + 362:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR + 363:Drivers/CMSIS/Include/core_cm4.h **** + 364:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_ISR_Pos 0U /*!< xPSR + 365:Drivers/CMSIS/Include/core_cm4.h **** #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR + 366:Drivers/CMSIS/Include/core_cm4.h **** + 367:Drivers/CMSIS/Include/core_cm4.h **** + 368:Drivers/CMSIS/Include/core_cm4.h **** /** + 369:Drivers/CMSIS/Include/core_cm4.h **** \brief Union type to access the Control Registers (CONTROL). + 370:Drivers/CMSIS/Include/core_cm4.h **** */ + 371:Drivers/CMSIS/Include/core_cm4.h **** typedef union + 372:Drivers/CMSIS/Include/core_cm4.h **** { + ARM GAS /tmp/ccwFmvCn.s page 8 + + + 373:Drivers/CMSIS/Include/core_cm4.h **** struct + 374:Drivers/CMSIS/Include/core_cm4.h **** { + 375:Drivers/CMSIS/Include/core_cm4.h **** uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + 376:Drivers/CMSIS/Include/core_cm4.h **** uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + 377:Drivers/CMSIS/Include/core_cm4.h **** uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + 378:Drivers/CMSIS/Include/core_cm4.h **** uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + 379:Drivers/CMSIS/Include/core_cm4.h **** } b; /*!< Structure used for bit access */ + 380:Drivers/CMSIS/Include/core_cm4.h **** uint32_t w; /*!< Type used for word access */ + 381:Drivers/CMSIS/Include/core_cm4.h **** } CONTROL_Type; + 382:Drivers/CMSIS/Include/core_cm4.h **** + 383:Drivers/CMSIS/Include/core_cm4.h **** /* CONTROL Register Definitions */ + 384:Drivers/CMSIS/Include/core_cm4.h **** #define CONTROL_FPCA_Pos 2U /*!< CONT + 385:Drivers/CMSIS/Include/core_cm4.h **** #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONT + 386:Drivers/CMSIS/Include/core_cm4.h **** + 387:Drivers/CMSIS/Include/core_cm4.h **** #define CONTROL_SPSEL_Pos 1U /*!< CONT + 388:Drivers/CMSIS/Include/core_cm4.h **** #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONT + 389:Drivers/CMSIS/Include/core_cm4.h **** + 390:Drivers/CMSIS/Include/core_cm4.h **** #define CONTROL_nPRIV_Pos 0U /*!< CONT + 391:Drivers/CMSIS/Include/core_cm4.h **** #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONT + 392:Drivers/CMSIS/Include/core_cm4.h **** + 393:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_CORE */ + 394:Drivers/CMSIS/Include/core_cm4.h **** + 395:Drivers/CMSIS/Include/core_cm4.h **** + 396:Drivers/CMSIS/Include/core_cm4.h **** /** + 397:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register + 398:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + 399:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the NVIC Registers + 400:Drivers/CMSIS/Include/core_cm4.h **** @{ + 401:Drivers/CMSIS/Include/core_cm4.h **** */ + 402:Drivers/CMSIS/Include/core_cm4.h **** + 403:Drivers/CMSIS/Include/core_cm4.h **** /** + 404:Drivers/CMSIS/Include/core_cm4.h **** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + 405:Drivers/CMSIS/Include/core_cm4.h **** */ + 406:Drivers/CMSIS/Include/core_cm4.h **** typedef struct + 407:Drivers/CMSIS/Include/core_cm4.h **** { + 408:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + 409:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED0[24U]; + 410:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register + 411:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RSERVED1[24U]; + 412:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register * + 413:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED2[24U]; + 414:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register + 415:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED3[24U]; + 416:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + 417:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED4[56U]; + 418:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bi + 419:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED5[644U]; + 420:Drivers/CMSIS/Include/core_cm4.h **** __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Regis + 421:Drivers/CMSIS/Include/core_cm4.h **** } NVIC_Type; + 422:Drivers/CMSIS/Include/core_cm4.h **** + 423:Drivers/CMSIS/Include/core_cm4.h **** /* Software Triggered Interrupt Register Definitions */ + 424:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_STIR_INTID_Pos 0U /*!< STIR: I + 425:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: I + 426:Drivers/CMSIS/Include/core_cm4.h **** + 427:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_NVIC */ + 428:Drivers/CMSIS/Include/core_cm4.h **** + 429:Drivers/CMSIS/Include/core_cm4.h **** + ARM GAS /tmp/ccwFmvCn.s page 9 + + + 430:Drivers/CMSIS/Include/core_cm4.h **** /** + 431:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register + 432:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_SCB System Control Block (SCB) + 433:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the System Control Block Registers + 434:Drivers/CMSIS/Include/core_cm4.h **** @{ + 435:Drivers/CMSIS/Include/core_cm4.h **** */ + 436:Drivers/CMSIS/Include/core_cm4.h **** + 437:Drivers/CMSIS/Include/core_cm4.h **** /** + 438:Drivers/CMSIS/Include/core_cm4.h **** \brief Structure type to access the System Control Block (SCB). + 439:Drivers/CMSIS/Include/core_cm4.h **** */ + 440:Drivers/CMSIS/Include/core_cm4.h **** typedef struct + 441:Drivers/CMSIS/Include/core_cm4.h **** { + 442:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + 443:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regi + 444:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + 445:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset + 446:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + 447:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register * + 448:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registe + 449:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State + 450:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Regist + 451:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + 452:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + 453:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register + 454:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + 455:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register + 456:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + 457:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + 458:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + 459:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + 460:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Regis + 461:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED0[5U]; + 462:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Regis + 463:Drivers/CMSIS/Include/core_cm4.h **** } SCB_Type; + 464:Drivers/CMSIS/Include/core_cm4.h **** + 465:Drivers/CMSIS/Include/core_cm4.h **** /* SCB CPUID Register Definitions */ + 466:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB + 467:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB + 468:Drivers/CMSIS/Include/core_cm4.h **** + 469:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB + 470:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB + 471:Drivers/CMSIS/Include/core_cm4.h **** + 472:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB + 473:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB + 474:Drivers/CMSIS/Include/core_cm4.h **** + 475:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB + 476:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB + 477:Drivers/CMSIS/Include/core_cm4.h **** + 478:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_REVISION_Pos 0U /*!< SCB + 479:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB + 480:Drivers/CMSIS/Include/core_cm4.h **** + 481:Drivers/CMSIS/Include/core_cm4.h **** /* SCB Interrupt Control State Register Definitions */ + 482:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB + 483:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB + 484:Drivers/CMSIS/Include/core_cm4.h **** + 485:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB + 486:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB + ARM GAS /tmp/ccwFmvCn.s page 10 + + + 487:Drivers/CMSIS/Include/core_cm4.h **** + 488:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB + 489:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB + 490:Drivers/CMSIS/Include/core_cm4.h **** + 491:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB + 492:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB + 493:Drivers/CMSIS/Include/core_cm4.h **** + 494:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB + 495:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB + 496:Drivers/CMSIS/Include/core_cm4.h **** + 497:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB + 498:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB + 499:Drivers/CMSIS/Include/core_cm4.h **** + 500:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB + 501:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB + 502:Drivers/CMSIS/Include/core_cm4.h **** + 503:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB + 504:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB + 505:Drivers/CMSIS/Include/core_cm4.h **** + 506:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB + 507:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB + 508:Drivers/CMSIS/Include/core_cm4.h **** + 509:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB + 510:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB + 511:Drivers/CMSIS/Include/core_cm4.h **** + 512:Drivers/CMSIS/Include/core_cm4.h **** /* SCB Vector Table Offset Register Definitions */ + 513:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB + 514:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB + 515:Drivers/CMSIS/Include/core_cm4.h **** + 516:Drivers/CMSIS/Include/core_cm4.h **** /* SCB Application Interrupt and Reset Control Register Definitions */ + 517:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB + 518:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB + 519:Drivers/CMSIS/Include/core_cm4.h **** + 520:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB + 521:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB + 522:Drivers/CMSIS/Include/core_cm4.h **** + 523:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB + 524:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB + 525:Drivers/CMSIS/Include/core_cm4.h **** + 526:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB + 527:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB + 528:Drivers/CMSIS/Include/core_cm4.h **** + 529:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB + 530:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB + 531:Drivers/CMSIS/Include/core_cm4.h **** + 532:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB + 533:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB + 534:Drivers/CMSIS/Include/core_cm4.h **** + 535:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB + 536:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB + 537:Drivers/CMSIS/Include/core_cm4.h **** + 538:Drivers/CMSIS/Include/core_cm4.h **** /* SCB System Control Register Definitions */ + 539:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB + 540:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB + 541:Drivers/CMSIS/Include/core_cm4.h **** + 542:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB + 543:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB + ARM GAS /tmp/ccwFmvCn.s page 11 + + + 544:Drivers/CMSIS/Include/core_cm4.h **** + 545:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB + 546:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB + 547:Drivers/CMSIS/Include/core_cm4.h **** + 548:Drivers/CMSIS/Include/core_cm4.h **** /* SCB Configuration Control Register Definitions */ + 549:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB + 550:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB + 551:Drivers/CMSIS/Include/core_cm4.h **** + 552:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB + 553:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB + 554:Drivers/CMSIS/Include/core_cm4.h **** + 555:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB + 556:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB + 557:Drivers/CMSIS/Include/core_cm4.h **** + 558:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB + 559:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB + 560:Drivers/CMSIS/Include/core_cm4.h **** + 561:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB + 562:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB + 563:Drivers/CMSIS/Include/core_cm4.h **** + 564:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB + 565:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB + 566:Drivers/CMSIS/Include/core_cm4.h **** + 567:Drivers/CMSIS/Include/core_cm4.h **** /* SCB System Handler Control and State Register Definitions */ + 568:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB + 569:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB + 570:Drivers/CMSIS/Include/core_cm4.h **** + 571:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB + 572:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB + 573:Drivers/CMSIS/Include/core_cm4.h **** + 574:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB + 575:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB + 576:Drivers/CMSIS/Include/core_cm4.h **** + 577:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB + 578:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB + 579:Drivers/CMSIS/Include/core_cm4.h **** + 580:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB + 581:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB + 582:Drivers/CMSIS/Include/core_cm4.h **** + 583:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB + 584:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB + 585:Drivers/CMSIS/Include/core_cm4.h **** + 586:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB + 587:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB + 588:Drivers/CMSIS/Include/core_cm4.h **** + 589:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB + 590:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB + 591:Drivers/CMSIS/Include/core_cm4.h **** + 592:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB + 593:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB + 594:Drivers/CMSIS/Include/core_cm4.h **** + 595:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB + 596:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB + 597:Drivers/CMSIS/Include/core_cm4.h **** + 598:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB + 599:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB + 600:Drivers/CMSIS/Include/core_cm4.h **** + ARM GAS /tmp/ccwFmvCn.s page 12 + + + 601:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB + 602:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB + 603:Drivers/CMSIS/Include/core_cm4.h **** + 604:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB + 605:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB + 606:Drivers/CMSIS/Include/core_cm4.h **** + 607:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB + 608:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB + 609:Drivers/CMSIS/Include/core_cm4.h **** + 610:Drivers/CMSIS/Include/core_cm4.h **** /* SCB Configurable Fault Status Register Definitions */ + 611:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB + 612:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB + 613:Drivers/CMSIS/Include/core_cm4.h **** + 614:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB + 615:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB + 616:Drivers/CMSIS/Include/core_cm4.h **** + 617:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB + 618:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB + 619:Drivers/CMSIS/Include/core_cm4.h **** + 620:Drivers/CMSIS/Include/core_cm4.h **** /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ + 621:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB + 622:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB + 623:Drivers/CMSIS/Include/core_cm4.h **** + 624:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB + 625:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB + 626:Drivers/CMSIS/Include/core_cm4.h **** + 627:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB + 628:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB + 629:Drivers/CMSIS/Include/core_cm4.h **** + 630:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB + 631:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB + 632:Drivers/CMSIS/Include/core_cm4.h **** + 633:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB + 634:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB + 635:Drivers/CMSIS/Include/core_cm4.h **** + 636:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB + 637:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB + 638:Drivers/CMSIS/Include/core_cm4.h **** + 639:Drivers/CMSIS/Include/core_cm4.h **** /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ + 640:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB + 641:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB + 642:Drivers/CMSIS/Include/core_cm4.h **** + 643:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB + 644:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB + 645:Drivers/CMSIS/Include/core_cm4.h **** + 646:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB + 647:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB + 648:Drivers/CMSIS/Include/core_cm4.h **** + 649:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB + 650:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB + 651:Drivers/CMSIS/Include/core_cm4.h **** + 652:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB + 653:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB + 654:Drivers/CMSIS/Include/core_cm4.h **** + 655:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB + 656:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB + 657:Drivers/CMSIS/Include/core_cm4.h **** + ARM GAS /tmp/ccwFmvCn.s page 13 + + + 658:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB + 659:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB + 660:Drivers/CMSIS/Include/core_cm4.h **** + 661:Drivers/CMSIS/Include/core_cm4.h **** /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ + 662:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB + 663:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB + 664:Drivers/CMSIS/Include/core_cm4.h **** + 665:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB + 666:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB + 667:Drivers/CMSIS/Include/core_cm4.h **** + 668:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB + 669:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB + 670:Drivers/CMSIS/Include/core_cm4.h **** + 671:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB + 672:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB + 673:Drivers/CMSIS/Include/core_cm4.h **** + 674:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB + 675:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB + 676:Drivers/CMSIS/Include/core_cm4.h **** + 677:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB + 678:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB + 679:Drivers/CMSIS/Include/core_cm4.h **** + 680:Drivers/CMSIS/Include/core_cm4.h **** /* SCB Hard Fault Status Register Definitions */ + 681:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB + 682:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB + 683:Drivers/CMSIS/Include/core_cm4.h **** + 684:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_HFSR_FORCED_Pos 30U /*!< SCB + 685:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB + 686:Drivers/CMSIS/Include/core_cm4.h **** + 687:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB + 688:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB + 689:Drivers/CMSIS/Include/core_cm4.h **** + 690:Drivers/CMSIS/Include/core_cm4.h **** /* SCB Debug Fault Status Register Definitions */ + 691:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB + 692:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB + 693:Drivers/CMSIS/Include/core_cm4.h **** + 694:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB + 695:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB + 696:Drivers/CMSIS/Include/core_cm4.h **** + 697:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB + 698:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB + 699:Drivers/CMSIS/Include/core_cm4.h **** + 700:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_BKPT_Pos 1U /*!< SCB + 701:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB + 702:Drivers/CMSIS/Include/core_cm4.h **** + 703:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_HALTED_Pos 0U /*!< SCB + 704:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB + 705:Drivers/CMSIS/Include/core_cm4.h **** + 706:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_SCB */ + 707:Drivers/CMSIS/Include/core_cm4.h **** + 708:Drivers/CMSIS/Include/core_cm4.h **** + 709:Drivers/CMSIS/Include/core_cm4.h **** /** + 710:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register + 711:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + 712:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the System Control and ID Register not in the SCB + 713:Drivers/CMSIS/Include/core_cm4.h **** @{ + 714:Drivers/CMSIS/Include/core_cm4.h **** */ + ARM GAS /tmp/ccwFmvCn.s page 14 + + + 715:Drivers/CMSIS/Include/core_cm4.h **** + 716:Drivers/CMSIS/Include/core_cm4.h **** /** + 717:Drivers/CMSIS/Include/core_cm4.h **** \brief Structure type to access the System Control and ID Register not in the SCB. + 718:Drivers/CMSIS/Include/core_cm4.h **** */ + 719:Drivers/CMSIS/Include/core_cm4.h **** typedef struct + 720:Drivers/CMSIS/Include/core_cm4.h **** { + 721:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED0[1U]; + 722:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Regist + 723:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + 724:Drivers/CMSIS/Include/core_cm4.h **** } SCnSCB_Type; + 725:Drivers/CMSIS/Include/core_cm4.h **** + 726:Drivers/CMSIS/Include/core_cm4.h **** /* Interrupt Controller Type Register Definitions */ + 727:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: I + 728:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: I + 729:Drivers/CMSIS/Include/core_cm4.h **** + 730:Drivers/CMSIS/Include/core_cm4.h **** /* Auxiliary Control Register Definitions */ + 731:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: + 732:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: + 733:Drivers/CMSIS/Include/core_cm4.h **** + 734:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: + 735:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: + 736:Drivers/CMSIS/Include/core_cm4.h **** + 737:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: + 738:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: + 739:Drivers/CMSIS/Include/core_cm4.h **** + 740:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: + 741:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: + 742:Drivers/CMSIS/Include/core_cm4.h **** + 743:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: + 744:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: + 745:Drivers/CMSIS/Include/core_cm4.h **** + 746:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_SCnotSCB */ + 747:Drivers/CMSIS/Include/core_cm4.h **** + 748:Drivers/CMSIS/Include/core_cm4.h **** + 749:Drivers/CMSIS/Include/core_cm4.h **** /** + 750:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register + 751:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_SysTick System Tick Timer (SysTick) + 752:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the System Timer Registers. + 753:Drivers/CMSIS/Include/core_cm4.h **** @{ + 754:Drivers/CMSIS/Include/core_cm4.h **** */ + 755:Drivers/CMSIS/Include/core_cm4.h **** + 756:Drivers/CMSIS/Include/core_cm4.h **** /** + 757:Drivers/CMSIS/Include/core_cm4.h **** \brief Structure type to access the System Timer (SysTick). + 758:Drivers/CMSIS/Include/core_cm4.h **** */ + 759:Drivers/CMSIS/Include/core_cm4.h **** typedef struct + 760:Drivers/CMSIS/Include/core_cm4.h **** { + 761:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regis + 762:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + 763:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register * + 764:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ + 765:Drivers/CMSIS/Include/core_cm4.h **** } SysTick_Type; + 766:Drivers/CMSIS/Include/core_cm4.h **** + 767:Drivers/CMSIS/Include/core_cm4.h **** /* SysTick Control / Status Register Definitions */ + 768:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysT + 769:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysT + 770:Drivers/CMSIS/Include/core_cm4.h **** + 771:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysT + ARM GAS /tmp/ccwFmvCn.s page 15 + + + 772:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysT + 773:Drivers/CMSIS/Include/core_cm4.h **** + 774:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysT + 775:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysT + 776:Drivers/CMSIS/Include/core_cm4.h **** + 777:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysT + 778:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysT + 779:Drivers/CMSIS/Include/core_cm4.h **** + 780:Drivers/CMSIS/Include/core_cm4.h **** /* SysTick Reload Register Definitions */ + 781:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysT + 782:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysT + 783:Drivers/CMSIS/Include/core_cm4.h **** + 784:Drivers/CMSIS/Include/core_cm4.h **** /* SysTick Current Register Definitions */ + 785:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_VAL_CURRENT_Pos 0U /*!< SysT + 786:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysT + 787:Drivers/CMSIS/Include/core_cm4.h **** + 788:Drivers/CMSIS/Include/core_cm4.h **** /* SysTick Calibration Register Definitions */ + 789:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CALIB_NOREF_Pos 31U /*!< SysT + 790:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysT + 791:Drivers/CMSIS/Include/core_cm4.h **** + 792:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CALIB_SKEW_Pos 30U /*!< SysT + 793:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysT + 794:Drivers/CMSIS/Include/core_cm4.h **** + 795:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CALIB_TENMS_Pos 0U /*!< SysT + 796:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysT + 797:Drivers/CMSIS/Include/core_cm4.h **** + 798:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_SysTick */ + 799:Drivers/CMSIS/Include/core_cm4.h **** + 800:Drivers/CMSIS/Include/core_cm4.h **** + 801:Drivers/CMSIS/Include/core_cm4.h **** /** + 802:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register + 803:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + 804:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + 805:Drivers/CMSIS/Include/core_cm4.h **** @{ + 806:Drivers/CMSIS/Include/core_cm4.h **** */ + 807:Drivers/CMSIS/Include/core_cm4.h **** + 808:Drivers/CMSIS/Include/core_cm4.h **** /** + 809:Drivers/CMSIS/Include/core_cm4.h **** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + 810:Drivers/CMSIS/Include/core_cm4.h **** */ + 811:Drivers/CMSIS/Include/core_cm4.h **** typedef struct + 812:Drivers/CMSIS/Include/core_cm4.h **** { + 813:Drivers/CMSIS/Include/core_cm4.h **** __OM union + 814:Drivers/CMSIS/Include/core_cm4.h **** { + 815:Drivers/CMSIS/Include/core_cm4.h **** __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + 816:Drivers/CMSIS/Include/core_cm4.h **** __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + 817:Drivers/CMSIS/Include/core_cm4.h **** __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + 818:Drivers/CMSIS/Include/core_cm4.h **** } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + 819:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED0[864U]; + 820:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + 821:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED1[15U]; + 822:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + 823:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED2[15U]; + 824:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + 825:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED3[29U]; + 826:Drivers/CMSIS/Include/core_cm4.h **** __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register * + 827:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + 828:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Reg + ARM GAS /tmp/ccwFmvCn.s page 16 + + + 829:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED4[43U]; + 830:Drivers/CMSIS/Include/core_cm4.h **** __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + 831:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + 832:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED5[6U]; + 833:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Re + 834:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Re + 835:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Re + 836:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Re + 837:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Re + 838:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Re + 839:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Re + 840:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Re + 841:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Re + 842:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Re + 843:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Re + 844:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Re + 845:Drivers/CMSIS/Include/core_cm4.h **** } ITM_Type; + 846:Drivers/CMSIS/Include/core_cm4.h **** + 847:Drivers/CMSIS/Include/core_cm4.h **** /* ITM Trace Privilege Register Definitions */ + 848:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM + 849:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM + 850:Drivers/CMSIS/Include/core_cm4.h **** + 851:Drivers/CMSIS/Include/core_cm4.h **** /* ITM Trace Control Register Definitions */ + 852:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_BUSY_Pos 23U /*!< ITM + 853:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM + 854:Drivers/CMSIS/Include/core_cm4.h **** + 855:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM + 856:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM + 857:Drivers/CMSIS/Include/core_cm4.h **** + 858:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM + 859:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM + 860:Drivers/CMSIS/Include/core_cm4.h **** + 861:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM + 862:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM + 863:Drivers/CMSIS/Include/core_cm4.h **** + 864:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_SWOENA_Pos 4U /*!< ITM + 865:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM + 866:Drivers/CMSIS/Include/core_cm4.h **** + 867:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_DWTENA_Pos 3U /*!< ITM + 868:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM + 869:Drivers/CMSIS/Include/core_cm4.h **** + 870:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM + 871:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM + 872:Drivers/CMSIS/Include/core_cm4.h **** + 873:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_TSENA_Pos 1U /*!< ITM + 874:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM + 875:Drivers/CMSIS/Include/core_cm4.h **** + 876:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_ITMENA_Pos 0U /*!< ITM + 877:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM + 878:Drivers/CMSIS/Include/core_cm4.h **** + 879:Drivers/CMSIS/Include/core_cm4.h **** /* ITM Integration Write Register Definitions */ + 880:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM + 881:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM + 882:Drivers/CMSIS/Include/core_cm4.h **** + 883:Drivers/CMSIS/Include/core_cm4.h **** /* ITM Integration Read Register Definitions */ + 884:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM + 885:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM + ARM GAS /tmp/ccwFmvCn.s page 17 + + + 886:Drivers/CMSIS/Include/core_cm4.h **** + 887:Drivers/CMSIS/Include/core_cm4.h **** /* ITM Integration Mode Control Register Definitions */ + 888:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM + 889:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM + 890:Drivers/CMSIS/Include/core_cm4.h **** + 891:Drivers/CMSIS/Include/core_cm4.h **** /* ITM Lock Status Register Definitions */ + 892:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM + 893:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM + 894:Drivers/CMSIS/Include/core_cm4.h **** + 895:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_LSR_Access_Pos 1U /*!< ITM + 896:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM + 897:Drivers/CMSIS/Include/core_cm4.h **** + 898:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_LSR_Present_Pos 0U /*!< ITM + 899:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM + 900:Drivers/CMSIS/Include/core_cm4.h **** + 901:Drivers/CMSIS/Include/core_cm4.h **** /*@}*/ /* end of group CMSIS_ITM */ + 902:Drivers/CMSIS/Include/core_cm4.h **** + 903:Drivers/CMSIS/Include/core_cm4.h **** + 904:Drivers/CMSIS/Include/core_cm4.h **** /** + 905:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register + 906:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + 907:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the Data Watchpoint and Trace (DWT) + 908:Drivers/CMSIS/Include/core_cm4.h **** @{ + 909:Drivers/CMSIS/Include/core_cm4.h **** */ + 910:Drivers/CMSIS/Include/core_cm4.h **** + 911:Drivers/CMSIS/Include/core_cm4.h **** /** + 912:Drivers/CMSIS/Include/core_cm4.h **** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + 913:Drivers/CMSIS/Include/core_cm4.h **** */ + 914:Drivers/CMSIS/Include/core_cm4.h **** typedef struct + 915:Drivers/CMSIS/Include/core_cm4.h **** { + 916:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + 917:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + 918:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + 919:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Registe + 920:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + 921:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + 922:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Registe + 923:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register + 924:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + 925:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + 926:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + 927:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED0[1U]; + 928:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + 929:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + 930:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + 931:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED1[1U]; + 932:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + 933:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + 934:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + 935:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED2[1U]; + 936:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + 937:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + 938:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + 939:Drivers/CMSIS/Include/core_cm4.h **** } DWT_Type; + 940:Drivers/CMSIS/Include/core_cm4.h **** + 941:Drivers/CMSIS/Include/core_cm4.h **** /* DWT Control Register Definitions */ + 942:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTR + ARM GAS /tmp/ccwFmvCn.s page 18 + + + 943:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTR + 944:Drivers/CMSIS/Include/core_cm4.h **** + 945:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTR + 946:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTR + 947:Drivers/CMSIS/Include/core_cm4.h **** + 948:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTR + 949:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTR + 950:Drivers/CMSIS/Include/core_cm4.h **** + 951:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTR + 952:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTR + 953:Drivers/CMSIS/Include/core_cm4.h **** + 954:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTR + 955:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTR + 956:Drivers/CMSIS/Include/core_cm4.h **** + 957:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTR + 958:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTR + 959:Drivers/CMSIS/Include/core_cm4.h **** + 960:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTR + 961:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTR + 962:Drivers/CMSIS/Include/core_cm4.h **** + 963:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTR + 964:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTR + 965:Drivers/CMSIS/Include/core_cm4.h **** + 966:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTR + 967:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTR + 968:Drivers/CMSIS/Include/core_cm4.h **** + 969:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTR + 970:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTR + 971:Drivers/CMSIS/Include/core_cm4.h **** + 972:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTR + 973:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTR + 974:Drivers/CMSIS/Include/core_cm4.h **** + 975:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTR + 976:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTR + 977:Drivers/CMSIS/Include/core_cm4.h **** + 978:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTR + 979:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTR + 980:Drivers/CMSIS/Include/core_cm4.h **** + 981:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTR + 982:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTR + 983:Drivers/CMSIS/Include/core_cm4.h **** + 984:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTR + 985:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTR + 986:Drivers/CMSIS/Include/core_cm4.h **** + 987:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTR + 988:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTR + 989:Drivers/CMSIS/Include/core_cm4.h **** + 990:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTR + 991:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTR + 992:Drivers/CMSIS/Include/core_cm4.h **** + 993:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTR + 994:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTR + 995:Drivers/CMSIS/Include/core_cm4.h **** + 996:Drivers/CMSIS/Include/core_cm4.h **** /* DWT CPI Count Register Definitions */ + 997:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPI + 998:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPI + 999:Drivers/CMSIS/Include/core_cm4.h **** + ARM GAS /tmp/ccwFmvCn.s page 19 + + +1000:Drivers/CMSIS/Include/core_cm4.h **** /* DWT Exception Overhead Count Register Definitions */ +1001:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXC +1002:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXC +1003:Drivers/CMSIS/Include/core_cm4.h **** +1004:Drivers/CMSIS/Include/core_cm4.h **** /* DWT Sleep Count Register Definitions */ +1005:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLE +1006:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLE +1007:Drivers/CMSIS/Include/core_cm4.h **** +1008:Drivers/CMSIS/Include/core_cm4.h **** /* DWT LSU Count Register Definitions */ +1009:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSU +1010:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSU +1011:Drivers/CMSIS/Include/core_cm4.h **** +1012:Drivers/CMSIS/Include/core_cm4.h **** /* DWT Folded-instruction Count Register Definitions */ +1013:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOL +1014:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOL +1015:Drivers/CMSIS/Include/core_cm4.h **** +1016:Drivers/CMSIS/Include/core_cm4.h **** /* DWT Comparator Mask Register Definitions */ +1017:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_MASK_MASK_Pos 0U /*!< DWT MAS +1018:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MAS +1019:Drivers/CMSIS/Include/core_cm4.h **** +1020:Drivers/CMSIS/Include/core_cm4.h **** /* DWT Comparator Function Register Definitions */ +1021:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUN +1022:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUN +1023:Drivers/CMSIS/Include/core_cm4.h **** +1024:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUN +1025:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUN +1026:Drivers/CMSIS/Include/core_cm4.h **** +1027:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUN +1028:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUN +1029:Drivers/CMSIS/Include/core_cm4.h **** +1030:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUN +1031:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUN +1032:Drivers/CMSIS/Include/core_cm4.h **** +1033:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUN +1034:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUN +1035:Drivers/CMSIS/Include/core_cm4.h **** +1036:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUN +1037:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUN +1038:Drivers/CMSIS/Include/core_cm4.h **** +1039:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUN +1040:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUN +1041:Drivers/CMSIS/Include/core_cm4.h **** +1042:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUN +1043:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUN +1044:Drivers/CMSIS/Include/core_cm4.h **** +1045:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUN +1046:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUN +1047:Drivers/CMSIS/Include/core_cm4.h **** +1048:Drivers/CMSIS/Include/core_cm4.h **** /*@}*/ /* end of group CMSIS_DWT */ +1049:Drivers/CMSIS/Include/core_cm4.h **** +1050:Drivers/CMSIS/Include/core_cm4.h **** +1051:Drivers/CMSIS/Include/core_cm4.h **** /** +1052:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register +1053:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_TPI Trace Port Interface (TPI) +1054:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the Trace Port Interface (TPI) +1055:Drivers/CMSIS/Include/core_cm4.h **** @{ +1056:Drivers/CMSIS/Include/core_cm4.h **** */ + ARM GAS /tmp/ccwFmvCn.s page 20 + + +1057:Drivers/CMSIS/Include/core_cm4.h **** +1058:Drivers/CMSIS/Include/core_cm4.h **** /** +1059:Drivers/CMSIS/Include/core_cm4.h **** \brief Structure type to access the Trace Port Interface Register (TPI). +1060:Drivers/CMSIS/Include/core_cm4.h **** */ +1061:Drivers/CMSIS/Include/core_cm4.h **** typedef struct +1062:Drivers/CMSIS/Include/core_cm4.h **** { +1063:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Reg +1064:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Regis +1065:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED0[2U]; +1066:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Reg +1067:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED1[55U]; +1068:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register * +1069:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED2[131U]; +1070:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Regis +1071:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Regi +1072:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counte +1073:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED3[759U]; +1074:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ +1075:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ +1076:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ +1077:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED4[1U]; +1078:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ +1079:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ +1080:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ +1081:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED5[39U]; +1082:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ +1083:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ +1084:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED7[8U]; +1085:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ +1086:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +1087:Drivers/CMSIS/Include/core_cm4.h **** } TPI_Type; +1088:Drivers/CMSIS/Include/core_cm4.h **** +1089:Drivers/CMSIS/Include/core_cm4.h **** /* TPI Asynchronous Clock Prescaler Register Definitions */ +1090:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACP +1091:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACP +1092:Drivers/CMSIS/Include/core_cm4.h **** +1093:Drivers/CMSIS/Include/core_cm4.h **** /* TPI Selected Pin Protocol Register Definitions */ +1094:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPP +1095:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPP +1096:Drivers/CMSIS/Include/core_cm4.h **** +1097:Drivers/CMSIS/Include/core_cm4.h **** /* TPI Formatter and Flush Status Register Definitions */ +1098:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFS +1099:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFS +1100:Drivers/CMSIS/Include/core_cm4.h **** +1101:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFS +1102:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFS +1103:Drivers/CMSIS/Include/core_cm4.h **** +1104:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFS +1105:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFS +1106:Drivers/CMSIS/Include/core_cm4.h **** +1107:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFS +1108:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFS +1109:Drivers/CMSIS/Include/core_cm4.h **** +1110:Drivers/CMSIS/Include/core_cm4.h **** /* TPI Formatter and Flush Control Register Definitions */ +1111:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFC +1112:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFC +1113:Drivers/CMSIS/Include/core_cm4.h **** + ARM GAS /tmp/ccwFmvCn.s page 21 + + +1114:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFC +1115:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFC +1116:Drivers/CMSIS/Include/core_cm4.h **** +1117:Drivers/CMSIS/Include/core_cm4.h **** /* TPI TRIGGER Register Definitions */ +1118:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRI +1119:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRI +1120:Drivers/CMSIS/Include/core_cm4.h **** +1121:Drivers/CMSIS/Include/core_cm4.h **** /* TPI Integration ETM Data Register Definitions (FIFO0) */ +1122:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIF +1123:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIF +1124:Drivers/CMSIS/Include/core_cm4.h **** +1125:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIF +1126:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIF +1127:Drivers/CMSIS/Include/core_cm4.h **** +1128:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIF +1129:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIF +1130:Drivers/CMSIS/Include/core_cm4.h **** +1131:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIF +1132:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIF +1133:Drivers/CMSIS/Include/core_cm4.h **** +1134:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIF +1135:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIF +1136:Drivers/CMSIS/Include/core_cm4.h **** +1137:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIF +1138:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIF +1139:Drivers/CMSIS/Include/core_cm4.h **** +1140:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIF +1141:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIF +1142:Drivers/CMSIS/Include/core_cm4.h **** +1143:Drivers/CMSIS/Include/core_cm4.h **** /* TPI ITATBCTR2 Register Definitions */ +1144:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITA +1145:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITA +1146:Drivers/CMSIS/Include/core_cm4.h **** +1147:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITA +1148:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITA +1149:Drivers/CMSIS/Include/core_cm4.h **** +1150:Drivers/CMSIS/Include/core_cm4.h **** /* TPI Integration ITM Data Register Definitions (FIFO1) */ +1151:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIF +1152:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIF +1153:Drivers/CMSIS/Include/core_cm4.h **** +1154:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIF +1155:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIF +1156:Drivers/CMSIS/Include/core_cm4.h **** +1157:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIF +1158:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIF +1159:Drivers/CMSIS/Include/core_cm4.h **** +1160:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIF +1161:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIF +1162:Drivers/CMSIS/Include/core_cm4.h **** +1163:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIF +1164:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIF +1165:Drivers/CMSIS/Include/core_cm4.h **** +1166:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIF +1167:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIF +1168:Drivers/CMSIS/Include/core_cm4.h **** +1169:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIF +1170:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIF + ARM GAS /tmp/ccwFmvCn.s page 22 + + +1171:Drivers/CMSIS/Include/core_cm4.h **** +1172:Drivers/CMSIS/Include/core_cm4.h **** /* TPI ITATBCTR0 Register Definitions */ +1173:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITA +1174:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITA +1175:Drivers/CMSIS/Include/core_cm4.h **** +1176:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITA +1177:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITA +1178:Drivers/CMSIS/Include/core_cm4.h **** +1179:Drivers/CMSIS/Include/core_cm4.h **** /* TPI Integration Mode Control Register Definitions */ +1180:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITC +1181:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITC +1182:Drivers/CMSIS/Include/core_cm4.h **** +1183:Drivers/CMSIS/Include/core_cm4.h **** /* TPI DEVID Register Definitions */ +1184:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEV +1185:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEV +1186:Drivers/CMSIS/Include/core_cm4.h **** +1187:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEV +1188:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEV +1189:Drivers/CMSIS/Include/core_cm4.h **** +1190:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEV +1191:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEV +1192:Drivers/CMSIS/Include/core_cm4.h **** +1193:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEV +1194:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEV +1195:Drivers/CMSIS/Include/core_cm4.h **** +1196:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEV +1197:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEV +1198:Drivers/CMSIS/Include/core_cm4.h **** +1199:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEV +1200:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEV +1201:Drivers/CMSIS/Include/core_cm4.h **** +1202:Drivers/CMSIS/Include/core_cm4.h **** /* TPI DEVTYPE Register Definitions */ +1203:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEV +1204:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEV +1205:Drivers/CMSIS/Include/core_cm4.h **** +1206:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEV +1207:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEV +1208:Drivers/CMSIS/Include/core_cm4.h **** +1209:Drivers/CMSIS/Include/core_cm4.h **** /*@}*/ /* end of group CMSIS_TPI */ +1210:Drivers/CMSIS/Include/core_cm4.h **** +1211:Drivers/CMSIS/Include/core_cm4.h **** +1212:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +1213:Drivers/CMSIS/Include/core_cm4.h **** /** +1214:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register +1215:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_MPU Memory Protection Unit (MPU) +1216:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the Memory Protection Unit (MPU) +1217:Drivers/CMSIS/Include/core_cm4.h **** @{ +1218:Drivers/CMSIS/Include/core_cm4.h **** */ +1219:Drivers/CMSIS/Include/core_cm4.h **** +1220:Drivers/CMSIS/Include/core_cm4.h **** /** +1221:Drivers/CMSIS/Include/core_cm4.h **** \brief Structure type to access the Memory Protection Unit (MPU). +1222:Drivers/CMSIS/Include/core_cm4.h **** */ +1223:Drivers/CMSIS/Include/core_cm4.h **** typedef struct +1224:Drivers/CMSIS/Include/core_cm4.h **** { +1225:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ +1226:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ +1227:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + ARM GAS /tmp/ccwFmvCn.s page 23 + + +1228:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register +1229:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Re +1230:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address +1231:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and +1232:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address +1233:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and +1234:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address +1235:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and +1236:Drivers/CMSIS/Include/core_cm4.h **** } MPU_Type; +1237:Drivers/CMSIS/Include/core_cm4.h **** +1238:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_TYPE_RALIASES 4U +1239:Drivers/CMSIS/Include/core_cm4.h **** +1240:Drivers/CMSIS/Include/core_cm4.h **** /* MPU Type Register Definitions */ +1241:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_TYPE_IREGION_Pos 16U /*!< MPU +1242:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU +1243:Drivers/CMSIS/Include/core_cm4.h **** +1244:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_TYPE_DREGION_Pos 8U /*!< MPU +1245:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU +1246:Drivers/CMSIS/Include/core_cm4.h **** +1247:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU +1248:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU +1249:Drivers/CMSIS/Include/core_cm4.h **** +1250:Drivers/CMSIS/Include/core_cm4.h **** /* MPU Control Register Definitions */ +1251:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU +1252:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU +1253:Drivers/CMSIS/Include/core_cm4.h **** +1254:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU +1255:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU +1256:Drivers/CMSIS/Include/core_cm4.h **** +1257:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU +1258:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU +1259:Drivers/CMSIS/Include/core_cm4.h **** +1260:Drivers/CMSIS/Include/core_cm4.h **** /* MPU Region Number Register Definitions */ +1261:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RNR_REGION_Pos 0U /*!< MPU +1262:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU +1263:Drivers/CMSIS/Include/core_cm4.h **** +1264:Drivers/CMSIS/Include/core_cm4.h **** /* MPU Region Base Address Register Definitions */ +1265:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RBAR_ADDR_Pos 5U /*!< MPU +1266:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU +1267:Drivers/CMSIS/Include/core_cm4.h **** +1268:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RBAR_VALID_Pos 4U /*!< MPU +1269:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU +1270:Drivers/CMSIS/Include/core_cm4.h **** +1271:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RBAR_REGION_Pos 0U /*!< MPU +1272:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU +1273:Drivers/CMSIS/Include/core_cm4.h **** +1274:Drivers/CMSIS/Include/core_cm4.h **** /* MPU Region Attribute and Size Register Definitions */ +1275:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_ATTRS_Pos 16U /*!< MPU +1276:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU +1277:Drivers/CMSIS/Include/core_cm4.h **** +1278:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_XN_Pos 28U /*!< MPU +1279:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU +1280:Drivers/CMSIS/Include/core_cm4.h **** +1281:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_AP_Pos 24U /*!< MPU +1282:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU +1283:Drivers/CMSIS/Include/core_cm4.h **** +1284:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_TEX_Pos 19U /*!< MPU + ARM GAS /tmp/ccwFmvCn.s page 24 + + +1285:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU +1286:Drivers/CMSIS/Include/core_cm4.h **** +1287:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_S_Pos 18U /*!< MPU +1288:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU +1289:Drivers/CMSIS/Include/core_cm4.h **** +1290:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_C_Pos 17U /*!< MPU +1291:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU +1292:Drivers/CMSIS/Include/core_cm4.h **** +1293:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_B_Pos 16U /*!< MPU +1294:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU +1295:Drivers/CMSIS/Include/core_cm4.h **** +1296:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_SRD_Pos 8U /*!< MPU +1297:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU +1298:Drivers/CMSIS/Include/core_cm4.h **** +1299:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_SIZE_Pos 1U /*!< MPU +1300:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU +1301:Drivers/CMSIS/Include/core_cm4.h **** +1302:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_ENABLE_Pos 0U /*!< MPU +1303:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU +1304:Drivers/CMSIS/Include/core_cm4.h **** +1305:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_MPU */ +1306:Drivers/CMSIS/Include/core_cm4.h **** #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ +1307:Drivers/CMSIS/Include/core_cm4.h **** +1308:Drivers/CMSIS/Include/core_cm4.h **** +1309:Drivers/CMSIS/Include/core_cm4.h **** /** +1310:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register +1311:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_FPU Floating Point Unit (FPU) +1312:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the Floating Point Unit (FPU) +1313:Drivers/CMSIS/Include/core_cm4.h **** @{ +1314:Drivers/CMSIS/Include/core_cm4.h **** */ +1315:Drivers/CMSIS/Include/core_cm4.h **** +1316:Drivers/CMSIS/Include/core_cm4.h **** /** +1317:Drivers/CMSIS/Include/core_cm4.h **** \brief Structure type to access the Floating Point Unit (FPU). +1318:Drivers/CMSIS/Include/core_cm4.h **** */ +1319:Drivers/CMSIS/Include/core_cm4.h **** typedef struct +1320:Drivers/CMSIS/Include/core_cm4.h **** { +1321:Drivers/CMSIS/Include/core_cm4.h **** uint32_t RESERVED0[1U]; +1322:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control R +1323:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address R +1324:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Co +1325:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 +1326:Drivers/CMSIS/Include/core_cm4.h **** __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 +1327:Drivers/CMSIS/Include/core_cm4.h **** } FPU_Type; +1328:Drivers/CMSIS/Include/core_cm4.h **** +1329:Drivers/CMSIS/Include/core_cm4.h **** /* Floating-Point Context Control Register Definitions */ +1330:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCC +1331:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCC +1332:Drivers/CMSIS/Include/core_cm4.h **** +1333:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCC +1334:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCC +1335:Drivers/CMSIS/Include/core_cm4.h **** +1336:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCC +1337:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCC +1338:Drivers/CMSIS/Include/core_cm4.h **** +1339:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCC +1340:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCC +1341:Drivers/CMSIS/Include/core_cm4.h **** + ARM GAS /tmp/ccwFmvCn.s page 25 + + +1342:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCC +1343:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCC +1344:Drivers/CMSIS/Include/core_cm4.h **** +1345:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCC +1346:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCC +1347:Drivers/CMSIS/Include/core_cm4.h **** +1348:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCC +1349:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCC +1350:Drivers/CMSIS/Include/core_cm4.h **** +1351:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_USER_Pos 1U /*!< FPCC +1352:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCC +1353:Drivers/CMSIS/Include/core_cm4.h **** +1354:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCC +1355:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCC +1356:Drivers/CMSIS/Include/core_cm4.h **** +1357:Drivers/CMSIS/Include/core_cm4.h **** /* Floating-Point Context Address Register Definitions */ +1358:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCA +1359:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCA +1360:Drivers/CMSIS/Include/core_cm4.h **** +1361:Drivers/CMSIS/Include/core_cm4.h **** /* Floating-Point Default Status Control Register Definitions */ +1362:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDS +1363:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDS +1364:Drivers/CMSIS/Include/core_cm4.h **** +1365:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_DN_Pos 25U /*!< FPDS +1366:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDS +1367:Drivers/CMSIS/Include/core_cm4.h **** +1368:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDS +1369:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDS +1370:Drivers/CMSIS/Include/core_cm4.h **** +1371:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDS +1372:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDS +1373:Drivers/CMSIS/Include/core_cm4.h **** +1374:Drivers/CMSIS/Include/core_cm4.h **** /* Media and FP Feature Register 0 Definitions */ +1375:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR +1376:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR +1377:Drivers/CMSIS/Include/core_cm4.h **** +1378:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR +1379:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR +1380:Drivers/CMSIS/Include/core_cm4.h **** +1381:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR +1382:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR +1383:Drivers/CMSIS/Include/core_cm4.h **** +1384:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR +1385:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR +1386:Drivers/CMSIS/Include/core_cm4.h **** +1387:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR +1388:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR +1389:Drivers/CMSIS/Include/core_cm4.h **** +1390:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR +1391:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR +1392:Drivers/CMSIS/Include/core_cm4.h **** +1393:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR +1394:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR +1395:Drivers/CMSIS/Include/core_cm4.h **** +1396:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR +1397:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR +1398:Drivers/CMSIS/Include/core_cm4.h **** + ARM GAS /tmp/ccwFmvCn.s page 26 + + +1399:Drivers/CMSIS/Include/core_cm4.h **** /* Media and FP Feature Register 1 Definitions */ +1400:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR +1401:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR +1402:Drivers/CMSIS/Include/core_cm4.h **** +1403:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR +1404:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR +1405:Drivers/CMSIS/Include/core_cm4.h **** +1406:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR +1407:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR +1408:Drivers/CMSIS/Include/core_cm4.h **** +1409:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR +1410:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR +1411:Drivers/CMSIS/Include/core_cm4.h **** +1412:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_FPU */ +1413:Drivers/CMSIS/Include/core_cm4.h **** +1414:Drivers/CMSIS/Include/core_cm4.h **** +1415:Drivers/CMSIS/Include/core_cm4.h **** /** +1416:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register +1417:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) +1418:Drivers/CMSIS/Include/core_cm4.h **** \brief Type definitions for the Core Debug Registers +1419:Drivers/CMSIS/Include/core_cm4.h **** @{ +1420:Drivers/CMSIS/Include/core_cm4.h **** */ +1421:Drivers/CMSIS/Include/core_cm4.h **** +1422:Drivers/CMSIS/Include/core_cm4.h **** /** +1423:Drivers/CMSIS/Include/core_cm4.h **** \brief Structure type to access the Core Debug Register (CoreDebug). +1424:Drivers/CMSIS/Include/core_cm4.h **** */ +1425:Drivers/CMSIS/Include/core_cm4.h **** typedef struct +1426:Drivers/CMSIS/Include/core_cm4.h **** { +1427:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status +1428:Drivers/CMSIS/Include/core_cm4.h **** __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Reg +1429:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Registe +1430:Drivers/CMSIS/Include/core_cm4.h **** __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Cont +1431:Drivers/CMSIS/Include/core_cm4.h **** } CoreDebug_Type; +1432:Drivers/CMSIS/Include/core_cm4.h **** +1433:Drivers/CMSIS/Include/core_cm4.h **** /* Debug Halting Control and Status Register Definitions */ +1434:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< Core +1435:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< Core +1436:Drivers/CMSIS/Include/core_cm4.h **** +1437:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< Core +1438:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< Core +1439:Drivers/CMSIS/Include/core_cm4.h **** +1440:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< Core +1441:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< Core +1442:Drivers/CMSIS/Include/core_cm4.h **** +1443:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< Core +1444:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< Core +1445:Drivers/CMSIS/Include/core_cm4.h **** +1446:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< Core +1447:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< Core +1448:Drivers/CMSIS/Include/core_cm4.h **** +1449:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< Core +1450:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< Core +1451:Drivers/CMSIS/Include/core_cm4.h **** +1452:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< Core +1453:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< Core +1454:Drivers/CMSIS/Include/core_cm4.h **** +1455:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< Core + ARM GAS /tmp/ccwFmvCn.s page 27 + + +1456:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< Core +1457:Drivers/CMSIS/Include/core_cm4.h **** +1458:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< Core +1459:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< Core +1460:Drivers/CMSIS/Include/core_cm4.h **** +1461:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< Core +1462:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< Core +1463:Drivers/CMSIS/Include/core_cm4.h **** +1464:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< Core +1465:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< Core +1466:Drivers/CMSIS/Include/core_cm4.h **** +1467:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< Core +1468:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< Core +1469:Drivers/CMSIS/Include/core_cm4.h **** +1470:Drivers/CMSIS/Include/core_cm4.h **** /* Debug Core Register Selector Register Definitions */ +1471:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< Core +1472:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< Core +1473:Drivers/CMSIS/Include/core_cm4.h **** +1474:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< Core +1475:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< Core +1476:Drivers/CMSIS/Include/core_cm4.h **** +1477:Drivers/CMSIS/Include/core_cm4.h **** /* Debug Exception and Monitor Control Register Definitions */ +1478:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< Core +1479:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< Core +1480:Drivers/CMSIS/Include/core_cm4.h **** +1481:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< Core +1482:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< Core +1483:Drivers/CMSIS/Include/core_cm4.h **** +1484:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< Core +1485:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< Core +1486:Drivers/CMSIS/Include/core_cm4.h **** +1487:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< Core +1488:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< Core +1489:Drivers/CMSIS/Include/core_cm4.h **** +1490:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< Core +1491:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< Core +1492:Drivers/CMSIS/Include/core_cm4.h **** +1493:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< Core +1494:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< Core +1495:Drivers/CMSIS/Include/core_cm4.h **** +1496:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< Core +1497:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< Core +1498:Drivers/CMSIS/Include/core_cm4.h **** +1499:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< Core +1500:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< Core +1501:Drivers/CMSIS/Include/core_cm4.h **** +1502:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< Core +1503:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< Core +1504:Drivers/CMSIS/Include/core_cm4.h **** +1505:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< Core +1506:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< Core +1507:Drivers/CMSIS/Include/core_cm4.h **** +1508:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< Core +1509:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< Core +1510:Drivers/CMSIS/Include/core_cm4.h **** +1511:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< Core +1512:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< Core + ARM GAS /tmp/ccwFmvCn.s page 28 + + +1513:Drivers/CMSIS/Include/core_cm4.h **** +1514:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< Core +1515:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< Core +1516:Drivers/CMSIS/Include/core_cm4.h **** +1517:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_CoreDebug */ +1518:Drivers/CMSIS/Include/core_cm4.h **** +1519:Drivers/CMSIS/Include/core_cm4.h **** +1520:Drivers/CMSIS/Include/core_cm4.h **** /** +1521:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register +1522:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_core_bitfield Core register bit field macros +1523:Drivers/CMSIS/Include/core_cm4.h **** \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). +1524:Drivers/CMSIS/Include/core_cm4.h **** @{ +1525:Drivers/CMSIS/Include/core_cm4.h **** */ +1526:Drivers/CMSIS/Include/core_cm4.h **** +1527:Drivers/CMSIS/Include/core_cm4.h **** /** +1528:Drivers/CMSIS/Include/core_cm4.h **** \brief Mask and shift a bit field value for use in a register bit range. +1529:Drivers/CMSIS/Include/core_cm4.h **** \param[in] field Name of the register bit field. +1530:Drivers/CMSIS/Include/core_cm4.h **** \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. +1531:Drivers/CMSIS/Include/core_cm4.h **** \return Masked and shifted value. +1532:Drivers/CMSIS/Include/core_cm4.h **** */ +1533:Drivers/CMSIS/Include/core_cm4.h **** #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) +1534:Drivers/CMSIS/Include/core_cm4.h **** +1535:Drivers/CMSIS/Include/core_cm4.h **** /** +1536:Drivers/CMSIS/Include/core_cm4.h **** \brief Mask and shift a register value to extract a bit filed value. +1537:Drivers/CMSIS/Include/core_cm4.h **** \param[in] field Name of the register bit field. +1538:Drivers/CMSIS/Include/core_cm4.h **** \param[in] value Value of register. This parameter is interpreted as an uint32_t type. +1539:Drivers/CMSIS/Include/core_cm4.h **** \return Masked and shifted bit field value. +1540:Drivers/CMSIS/Include/core_cm4.h **** */ +1541:Drivers/CMSIS/Include/core_cm4.h **** #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) +1542:Drivers/CMSIS/Include/core_cm4.h **** +1543:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of group CMSIS_core_bitfield */ +1544:Drivers/CMSIS/Include/core_cm4.h **** +1545:Drivers/CMSIS/Include/core_cm4.h **** +1546:Drivers/CMSIS/Include/core_cm4.h **** /** +1547:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_core_register +1548:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_core_base Core Definitions +1549:Drivers/CMSIS/Include/core_cm4.h **** \brief Definitions for base addresses, unions, and structures. +1550:Drivers/CMSIS/Include/core_cm4.h **** @{ +1551:Drivers/CMSIS/Include/core_cm4.h **** */ +1552:Drivers/CMSIS/Include/core_cm4.h **** +1553:Drivers/CMSIS/Include/core_cm4.h **** /* Memory mapping of Core Hardware */ +1554:Drivers/CMSIS/Include/core_cm4.h **** #define SCS_BASE (0xE000E000UL) /*!< System Control Space Bas +1555:Drivers/CMSIS/Include/core_cm4.h **** #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +1556:Drivers/CMSIS/Include/core_cm4.h **** #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +1557:Drivers/CMSIS/Include/core_cm4.h **** #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +1558:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address +1559:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +1560:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +1561:Drivers/CMSIS/Include/core_cm4.h **** #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Bas +1562:Drivers/CMSIS/Include/core_cm4.h **** +1563:Drivers/CMSIS/Include/core_cm4.h **** #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register +1564:Drivers/CMSIS/Include/core_cm4.h **** #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct +1565:Drivers/CMSIS/Include/core_cm4.h **** #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration st +1566:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struc +1567:Drivers/CMSIS/Include/core_cm4.h **** #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct +1568:Drivers/CMSIS/Include/core_cm4.h **** #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct +1569:Drivers/CMSIS/Include/core_cm4.h **** #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct + ARM GAS /tmp/ccwFmvCn.s page 29 + + +1570:Drivers/CMSIS/Include/core_cm4.h **** #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration +1571:Drivers/CMSIS/Include/core_cm4.h **** +1572:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +1573:Drivers/CMSIS/Include/core_cm4.h **** #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit * +1574:Drivers/CMSIS/Include/core_cm4.h **** #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit * +1575:Drivers/CMSIS/Include/core_cm4.h **** #endif +1576:Drivers/CMSIS/Include/core_cm4.h **** +1577:Drivers/CMSIS/Include/core_cm4.h **** #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +1578:Drivers/CMSIS/Include/core_cm4.h **** #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +1579:Drivers/CMSIS/Include/core_cm4.h **** +1580:Drivers/CMSIS/Include/core_cm4.h **** /*@} */ +1581:Drivers/CMSIS/Include/core_cm4.h **** +1582:Drivers/CMSIS/Include/core_cm4.h **** +1583:Drivers/CMSIS/Include/core_cm4.h **** +1584:Drivers/CMSIS/Include/core_cm4.h **** /******************************************************************************* +1585:Drivers/CMSIS/Include/core_cm4.h **** * Hardware Abstraction Layer +1586:Drivers/CMSIS/Include/core_cm4.h **** Core Function Interface contains: +1587:Drivers/CMSIS/Include/core_cm4.h **** - Core NVIC Functions +1588:Drivers/CMSIS/Include/core_cm4.h **** - Core SysTick Functions +1589:Drivers/CMSIS/Include/core_cm4.h **** - Core Debug Functions +1590:Drivers/CMSIS/Include/core_cm4.h **** - Core Register Access Functions +1591:Drivers/CMSIS/Include/core_cm4.h **** ******************************************************************************/ +1592:Drivers/CMSIS/Include/core_cm4.h **** /** +1593:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +1594:Drivers/CMSIS/Include/core_cm4.h **** */ +1595:Drivers/CMSIS/Include/core_cm4.h **** +1596:Drivers/CMSIS/Include/core_cm4.h **** +1597:Drivers/CMSIS/Include/core_cm4.h **** +1598:Drivers/CMSIS/Include/core_cm4.h **** /* ########################## NVIC functions #################################### */ +1599:Drivers/CMSIS/Include/core_cm4.h **** /** +1600:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_Core_FunctionInterface +1601:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_Core_NVICFunctions NVIC Functions +1602:Drivers/CMSIS/Include/core_cm4.h **** \brief Functions that manage interrupts and exceptions via the NVIC. +1603:Drivers/CMSIS/Include/core_cm4.h **** @{ +1604:Drivers/CMSIS/Include/core_cm4.h **** */ +1605:Drivers/CMSIS/Include/core_cm4.h **** +1606:Drivers/CMSIS/Include/core_cm4.h **** #ifdef CMSIS_NVIC_VIRTUAL +1607:Drivers/CMSIS/Include/core_cm4.h **** #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE +1608:Drivers/CMSIS/Include/core_cm4.h **** #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" +1609:Drivers/CMSIS/Include/core_cm4.h **** #endif +1610:Drivers/CMSIS/Include/core_cm4.h **** #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +1611:Drivers/CMSIS/Include/core_cm4.h **** #else +1612:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping +1613:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping +1614:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_EnableIRQ __NVIC_EnableIRQ +1615:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ +1616:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_DisableIRQ __NVIC_DisableIRQ +1617:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ +1618:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ +1619:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +1620:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_GetActive __NVIC_GetActive +1621:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_SetPriority __NVIC_SetPriority +1622:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_GetPriority __NVIC_GetPriority +1623:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_SystemReset __NVIC_SystemReset +1624:Drivers/CMSIS/Include/core_cm4.h **** #endif /* CMSIS_NVIC_VIRTUAL */ +1625:Drivers/CMSIS/Include/core_cm4.h **** +1626:Drivers/CMSIS/Include/core_cm4.h **** #ifdef CMSIS_VECTAB_VIRTUAL + ARM GAS /tmp/ccwFmvCn.s page 30 + + +1627:Drivers/CMSIS/Include/core_cm4.h **** #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE +1628:Drivers/CMSIS/Include/core_cm4.h **** #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" +1629:Drivers/CMSIS/Include/core_cm4.h **** #endif +1630:Drivers/CMSIS/Include/core_cm4.h **** #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +1631:Drivers/CMSIS/Include/core_cm4.h **** #else +1632:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_SetVector __NVIC_SetVector +1633:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_GetVector __NVIC_GetVector +1634:Drivers/CMSIS/Include/core_cm4.h **** #endif /* (CMSIS_VECTAB_VIRTUAL) */ +1635:Drivers/CMSIS/Include/core_cm4.h **** +1636:Drivers/CMSIS/Include/core_cm4.h **** #define NVIC_USER_IRQ_OFFSET 16 +1637:Drivers/CMSIS/Include/core_cm4.h **** +1638:Drivers/CMSIS/Include/core_cm4.h **** +1639:Drivers/CMSIS/Include/core_cm4.h **** /* The following EXC_RETURN values are saved the LR on exception entry */ +1640:Drivers/CMSIS/Include/core_cm4.h **** #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after ret +1641:Drivers/CMSIS/Include/core_cm4.h **** #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after retu +1642:Drivers/CMSIS/Include/core_cm4.h **** #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after retu +1643:Drivers/CMSIS/Include/core_cm4.h **** #define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after ret +1644:Drivers/CMSIS/Include/core_cm4.h **** #define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after retu +1645:Drivers/CMSIS/Include/core_cm4.h **** #define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after retu +1646:Drivers/CMSIS/Include/core_cm4.h **** +1647:Drivers/CMSIS/Include/core_cm4.h **** +1648:Drivers/CMSIS/Include/core_cm4.h **** /** +1649:Drivers/CMSIS/Include/core_cm4.h **** \brief Set Priority Grouping +1650:Drivers/CMSIS/Include/core_cm4.h **** \details Sets the priority grouping field using the required unlock sequence. +1651:Drivers/CMSIS/Include/core_cm4.h **** The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. +1652:Drivers/CMSIS/Include/core_cm4.h **** Only values from 0..7 are used. +1653:Drivers/CMSIS/Include/core_cm4.h **** In case of a conflict between priority grouping and available +1654:Drivers/CMSIS/Include/core_cm4.h **** priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. +1655:Drivers/CMSIS/Include/core_cm4.h **** \param [in] PriorityGroup Priority grouping field. +1656:Drivers/CMSIS/Include/core_cm4.h **** */ +1657:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +1658:Drivers/CMSIS/Include/core_cm4.h **** { + 29 .loc 2 1658 1 + 30 .cfi_startproc + 31 @ args = 0, pretend = 0, frame = 16 + 32 @ frame_needed = 1, uses_anonymous_args = 0 + 33 @ link register save eliminated. + 34 0000 80B4 push {r7} + 35 .cfi_def_cfa_offset 4 + 36 .cfi_offset 7, -4 + 37 0002 85B0 sub sp, sp, #20 + 38 .cfi_def_cfa_offset 24 + 39 0004 00AF add r7, sp, #0 + 40 .cfi_def_cfa_register 7 + 41 0006 7860 str r0, [r7, #4] +1659:Drivers/CMSIS/Include/core_cm4.h **** uint32_t reg_value; +1660:Drivers/CMSIS/Include/core_cm4.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 a + 42 .loc 2 1660 12 + 43 0008 7B68 ldr r3, [r7, #4] + 44 000a 03F00703 and r3, r3, #7 + 45 000e FB60 str r3, [r7, #12] +1661:Drivers/CMSIS/Include/core_cm4.h **** +1662:Drivers/CMSIS/Include/core_cm4.h **** reg_value = SCB->AIRCR; /* read old register + 46 .loc 2 1662 20 + 47 0010 0C4B ldr r3, .L2 + 48 .loc 2 1662 14 + 49 0012 DB68 ldr r3, [r3, #12] + ARM GAS /tmp/ccwFmvCn.s page 31 + + + 50 0014 BB60 str r3, [r7, #8] +1663:Drivers/CMSIS/Include/core_cm4.h **** reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to chan + 51 .loc 2 1663 13 + 52 0016 BA68 ldr r2, [r7, #8] + 53 0018 4FF6FF03 movw r3, #63743 + 54 001c 1340 ands r3, r3, r2 + 55 001e BB60 str r3, [r7, #8] +1664:Drivers/CMSIS/Include/core_cm4.h **** reg_value = (reg_value | +1665:Drivers/CMSIS/Include/core_cm4.h **** ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | +1666:Drivers/CMSIS/Include/core_cm4.h **** (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key a + 56 .loc 2 1666 35 + 57 0020 FB68 ldr r3, [r7, #12] + 58 0022 1A02 lsls r2, r3, #8 +1665:Drivers/CMSIS/Include/core_cm4.h **** (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key a + 59 .loc 2 1665 62 + 60 0024 BB68 ldr r3, [r7, #8] + 61 0026 1343 orrs r3, r3, r2 +1664:Drivers/CMSIS/Include/core_cm4.h **** reg_value = (reg_value | + 62 .loc 2 1664 14 + 63 0028 43F0BF63 orr r3, r3, #100139008 + 64 002c 43F40033 orr r3, r3, #131072 + 65 0030 BB60 str r3, [r7, #8] +1667:Drivers/CMSIS/Include/core_cm4.h **** SCB->AIRCR = reg_value; + 66 .loc 2 1667 6 + 67 0032 044A ldr r2, .L2 + 68 .loc 2 1667 14 + 69 0034 BB68 ldr r3, [r7, #8] + 70 0036 D360 str r3, [r2, #12] +1668:Drivers/CMSIS/Include/core_cm4.h **** } + 71 .loc 2 1668 1 + 72 0038 00BF nop + 73 003a 1437 adds r7, r7, #20 + 74 .cfi_def_cfa_offset 4 + 75 003c BD46 mov sp, r7 + 76 .cfi_def_cfa_register 13 + 77 @ sp needed + 78 003e 5DF8047B ldr r7, [sp], #4 + 79 .cfi_restore 7 + 80 .cfi_def_cfa_offset 0 + 81 0042 7047 bx lr + 82 .L3: + 83 .align 2 + 84 .L2: + 85 0044 00ED00E0 .word -536810240 + 86 .cfi_endproc + 87 .LFE102: + 89 .section .text.__NVIC_GetPriorityGrouping,"ax",%progbits + 90 .align 1 + 91 .syntax unified + 92 .thumb + 93 .thumb_func + 95 __NVIC_GetPriorityGrouping: + 96 .LFB103: +1669:Drivers/CMSIS/Include/core_cm4.h **** +1670:Drivers/CMSIS/Include/core_cm4.h **** +1671:Drivers/CMSIS/Include/core_cm4.h **** /** +1672:Drivers/CMSIS/Include/core_cm4.h **** \brief Get Priority Grouping + ARM GAS /tmp/ccwFmvCn.s page 32 + + +1673:Drivers/CMSIS/Include/core_cm4.h **** \details Reads the priority grouping field from the NVIC Interrupt Controller. +1674:Drivers/CMSIS/Include/core_cm4.h **** \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). +1675:Drivers/CMSIS/Include/core_cm4.h **** */ +1676:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +1677:Drivers/CMSIS/Include/core_cm4.h **** { + 97 .loc 2 1677 1 + 98 .cfi_startproc + 99 @ args = 0, pretend = 0, frame = 0 + 100 @ frame_needed = 1, uses_anonymous_args = 0 + 101 @ link register save eliminated. + 102 0000 80B4 push {r7} + 103 .cfi_def_cfa_offset 4 + 104 .cfi_offset 7, -4 + 105 0002 00AF add r7, sp, #0 + 106 .cfi_def_cfa_register 7 +1678:Drivers/CMSIS/Include/core_cm4.h **** return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); + 107 .loc 2 1678 26 + 108 0004 044B ldr r3, .L6 + 109 0006 DB68 ldr r3, [r3, #12] + 110 .loc 2 1678 11 + 111 0008 1B0A lsrs r3, r3, #8 + 112 000a 03F00703 and r3, r3, #7 +1679:Drivers/CMSIS/Include/core_cm4.h **** } + 113 .loc 2 1679 1 + 114 000e 1846 mov r0, r3 + 115 0010 BD46 mov sp, r7 + 116 .cfi_def_cfa_register 13 + 117 @ sp needed + 118 0012 5DF8047B ldr r7, [sp], #4 + 119 .cfi_restore 7 + 120 .cfi_def_cfa_offset 0 + 121 0016 7047 bx lr + 122 .L7: + 123 .align 2 + 124 .L6: + 125 0018 00ED00E0 .word -536810240 + 126 .cfi_endproc + 127 .LFE103: + 129 .section .text.__NVIC_EnableIRQ,"ax",%progbits + 130 .align 1 + 131 .syntax unified + 132 .thumb + 133 .thumb_func + 135 __NVIC_EnableIRQ: + 136 .LFB104: +1680:Drivers/CMSIS/Include/core_cm4.h **** +1681:Drivers/CMSIS/Include/core_cm4.h **** +1682:Drivers/CMSIS/Include/core_cm4.h **** /** +1683:Drivers/CMSIS/Include/core_cm4.h **** \brief Enable Interrupt +1684:Drivers/CMSIS/Include/core_cm4.h **** \details Enables a device specific interrupt in the NVIC interrupt controller. +1685:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Device specific interrupt number. +1686:Drivers/CMSIS/Include/core_cm4.h **** \note IRQn must not be negative. +1687:Drivers/CMSIS/Include/core_cm4.h **** */ +1688:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +1689:Drivers/CMSIS/Include/core_cm4.h **** { + 137 .loc 2 1689 1 + 138 .cfi_startproc + ARM GAS /tmp/ccwFmvCn.s page 33 + + + 139 @ args = 0, pretend = 0, frame = 8 + 140 @ frame_needed = 1, uses_anonymous_args = 0 + 141 @ link register save eliminated. + 142 0000 80B4 push {r7} + 143 .cfi_def_cfa_offset 4 + 144 .cfi_offset 7, -4 + 145 0002 83B0 sub sp, sp, #12 + 146 .cfi_def_cfa_offset 16 + 147 0004 00AF add r7, sp, #0 + 148 .cfi_def_cfa_register 7 + 149 0006 0346 mov r3, r0 + 150 0008 FB71 strb r3, [r7, #7] +1690:Drivers/CMSIS/Include/core_cm4.h **** if ((int32_t)(IRQn) >= 0) + 151 .loc 2 1690 6 + 152 000a 97F90730 ldrsb r3, [r7, #7] + 153 000e 002B cmp r3, #0 + 154 0010 0BDB blt .L10 +1691:Drivers/CMSIS/Include/core_cm4.h **** { +1692:Drivers/CMSIS/Include/core_cm4.h **** NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 155 .loc 2 1692 81 + 156 0012 FB79 ldrb r3, [r7, #7] @ zero_extendqisi2 + 157 0014 03F01F02 and r2, r3, #31 + 158 .loc 2 1692 9 + 159 0018 0749 ldr r1, .L11 + 160 .loc 2 1692 18 + 161 001a 97F90730 ldrsb r3, [r7, #7] + 162 .loc 2 1692 34 + 163 001e 5B09 lsrs r3, r3, #5 + 164 .loc 2 1692 45 + 165 0020 0120 movs r0, #1 + 166 0022 00FA02F2 lsl r2, r0, r2 + 167 .loc 2 1692 43 + 168 0026 41F82320 str r2, [r1, r3, lsl #2] + 169 .L10: +1693:Drivers/CMSIS/Include/core_cm4.h **** } +1694:Drivers/CMSIS/Include/core_cm4.h **** } + 170 .loc 2 1694 1 + 171 002a 00BF nop + 172 002c 0C37 adds r7, r7, #12 + 173 .cfi_def_cfa_offset 4 + 174 002e BD46 mov sp, r7 + 175 .cfi_def_cfa_register 13 + 176 @ sp needed + 177 0030 5DF8047B ldr r7, [sp], #4 + 178 .cfi_restore 7 + 179 .cfi_def_cfa_offset 0 + 180 0034 7047 bx lr + 181 .L12: + 182 0036 00BF .align 2 + 183 .L11: + 184 0038 00E100E0 .word -536813312 + 185 .cfi_endproc + 186 .LFE104: + 188 .section .text.__NVIC_DisableIRQ,"ax",%progbits + 189 .align 1 + 190 .syntax unified + 191 .thumb + ARM GAS /tmp/ccwFmvCn.s page 34 + + + 192 .thumb_func + 194 __NVIC_DisableIRQ: + 195 .LFB106: +1695:Drivers/CMSIS/Include/core_cm4.h **** +1696:Drivers/CMSIS/Include/core_cm4.h **** +1697:Drivers/CMSIS/Include/core_cm4.h **** /** +1698:Drivers/CMSIS/Include/core_cm4.h **** \brief Get Interrupt Enable status +1699:Drivers/CMSIS/Include/core_cm4.h **** \details Returns a device specific interrupt enable status from the NVIC interrupt controller. +1700:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Device specific interrupt number. +1701:Drivers/CMSIS/Include/core_cm4.h **** \return 0 Interrupt is not enabled. +1702:Drivers/CMSIS/Include/core_cm4.h **** \return 1 Interrupt is enabled. +1703:Drivers/CMSIS/Include/core_cm4.h **** \note IRQn must not be negative. +1704:Drivers/CMSIS/Include/core_cm4.h **** */ +1705:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +1706:Drivers/CMSIS/Include/core_cm4.h **** { +1707:Drivers/CMSIS/Include/core_cm4.h **** if ((int32_t)(IRQn) >= 0) +1708:Drivers/CMSIS/Include/core_cm4.h **** { +1709:Drivers/CMSIS/Include/core_cm4.h **** return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL) +1710:Drivers/CMSIS/Include/core_cm4.h **** } +1711:Drivers/CMSIS/Include/core_cm4.h **** else +1712:Drivers/CMSIS/Include/core_cm4.h **** { +1713:Drivers/CMSIS/Include/core_cm4.h **** return(0U); +1714:Drivers/CMSIS/Include/core_cm4.h **** } +1715:Drivers/CMSIS/Include/core_cm4.h **** } +1716:Drivers/CMSIS/Include/core_cm4.h **** +1717:Drivers/CMSIS/Include/core_cm4.h **** +1718:Drivers/CMSIS/Include/core_cm4.h **** /** +1719:Drivers/CMSIS/Include/core_cm4.h **** \brief Disable Interrupt +1720:Drivers/CMSIS/Include/core_cm4.h **** \details Disables a device specific interrupt in the NVIC interrupt controller. +1721:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Device specific interrupt number. +1722:Drivers/CMSIS/Include/core_cm4.h **** \note IRQn must not be negative. +1723:Drivers/CMSIS/Include/core_cm4.h **** */ +1724:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +1725:Drivers/CMSIS/Include/core_cm4.h **** { + 196 .loc 2 1725 1 + 197 .cfi_startproc + 198 @ args = 0, pretend = 0, frame = 8 + 199 @ frame_needed = 1, uses_anonymous_args = 0 + 200 @ link register save eliminated. + 201 0000 80B4 push {r7} + 202 .cfi_def_cfa_offset 4 + 203 .cfi_offset 7, -4 + 204 0002 83B0 sub sp, sp, #12 + 205 .cfi_def_cfa_offset 16 + 206 0004 00AF add r7, sp, #0 + 207 .cfi_def_cfa_register 7 + 208 0006 0346 mov r3, r0 + 209 0008 FB71 strb r3, [r7, #7] +1726:Drivers/CMSIS/Include/core_cm4.h **** if ((int32_t)(IRQn) >= 0) + 210 .loc 2 1726 6 + 211 000a 97F90730 ldrsb r3, [r7, #7] + 212 000e 002B cmp r3, #0 + 213 0010 12DB blt .L15 +1727:Drivers/CMSIS/Include/core_cm4.h **** { +1728:Drivers/CMSIS/Include/core_cm4.h **** NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 214 .loc 2 1728 81 + 215 0012 FB79 ldrb r3, [r7, #7] @ zero_extendqisi2 + ARM GAS /tmp/ccwFmvCn.s page 35 + + + 216 0014 03F01F02 and r2, r3, #31 + 217 .loc 2 1728 9 + 218 0018 0A49 ldr r1, .L16 + 219 .loc 2 1728 18 + 220 001a 97F90730 ldrsb r3, [r7, #7] + 221 .loc 2 1728 34 + 222 001e 5B09 lsrs r3, r3, #5 + 223 .loc 2 1728 45 + 224 0020 0120 movs r0, #1 + 225 0022 00FA02F2 lsl r2, r0, r2 + 226 .loc 2 1728 43 + 227 0026 2033 adds r3, r3, #32 + 228 0028 41F82320 str r2, [r1, r3, lsl #2] + 229 .LBB10: + 230 .LBB11: + 231 .file 3 "Drivers/CMSIS/Include/cmsis_gcc.h" + 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** + 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h + 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file + 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.0.4 + 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 09. April 2018 + 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ + 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* + 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 + 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may + 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. + 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at + 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 + 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software + 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT + 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and + 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. + 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 24:Drivers/CMSIS/Include/cmsis_gcc.h **** + 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H + 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H + 27:Drivers/CMSIS/Include/cmsis_gcc.h **** + 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ + 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" + 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" + 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" + 33:Drivers/CMSIS/Include/cmsis_gcc.h **** + 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ + 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin + 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) + 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 38:Drivers/CMSIS/Include/cmsis_gcc.h **** + 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ + 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM + 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm + ARM GAS /tmp/ccwFmvCn.s page 36 + + + 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE + 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline + 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE + 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline + 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE + 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline + 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN + 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) + 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED + 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) + 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK + 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) + 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED + 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) + 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT + 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION + 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) + 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ + 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE + 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- + 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ + 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add + 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE + 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + ARM GAS /tmp/ccwFmvCn.s page 37 + + + 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- + 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ + 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add + 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED + 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) + 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT + 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict + 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 116:Drivers/CMSIS/Include/cmsis_gcc.h **** + 117:Drivers/CMSIS/Include/cmsis_gcc.h **** + 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ + 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface + 120:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + 121:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 122:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 123:Drivers/CMSIS/Include/cmsis_gcc.h **** + 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts + 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + 127:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 128:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) + 130:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); + 132:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 133:Drivers/CMSIS/Include/cmsis_gcc.h **** + 134:Drivers/CMSIS/Include/cmsis_gcc.h **** + 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 136:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts + 137:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. + 138:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 139:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) + 141:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 142:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); + 143:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 144:Drivers/CMSIS/Include/cmsis_gcc.h **** + 145:Drivers/CMSIS/Include/cmsis_gcc.h **** + 146:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 147:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register + 148:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register. + 149:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value + 150:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) + 152:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 153:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 154:Drivers/CMSIS/Include/cmsis_gcc.h **** + 155:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) ); + ARM GAS /tmp/ccwFmvCn.s page 38 + + + 156:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 157:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 158:Drivers/CMSIS/Include/cmsis_gcc.h **** + 159:Drivers/CMSIS/Include/cmsis_gcc.h **** + 160:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 161:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 162:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register (non-secure) + 163:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the non-secure Control Register when in secure mode. + 164:Drivers/CMSIS/Include/cmsis_gcc.h **** \return non-secure Control Register value + 165:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 166:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) + 167:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 168:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 169:Drivers/CMSIS/Include/cmsis_gcc.h **** + 170:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + 171:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 172:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 174:Drivers/CMSIS/Include/cmsis_gcc.h **** + 175:Drivers/CMSIS/Include/cmsis_gcc.h **** + 176:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 177:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register + 178:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register. + 179:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 180:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 181:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) + 182:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 183:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + 184:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 185:Drivers/CMSIS/Include/cmsis_gcc.h **** + 186:Drivers/CMSIS/Include/cmsis_gcc.h **** + 187:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 188:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 189:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register (non-secure) + 190:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the non-secure Control Register when in secure state. + 191:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 192:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 193:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) + 194:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 195:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + 196:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 197:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 198:Drivers/CMSIS/Include/cmsis_gcc.h **** + 199:Drivers/CMSIS/Include/cmsis_gcc.h **** + 200:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 201:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register + 202:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register. + 203:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value + 204:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void) + 206:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 207:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 208:Drivers/CMSIS/Include/cmsis_gcc.h **** + 209:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 210:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 211:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 212:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccwFmvCn.s page 39 + + + 213:Drivers/CMSIS/Include/cmsis_gcc.h **** + 214:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 215:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register + 216:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register. + 217:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value + 218:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 219:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void) + 220:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 221:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 222:Drivers/CMSIS/Include/cmsis_gcc.h **** + 223:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + 224:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 225:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 226:Drivers/CMSIS/Include/cmsis_gcc.h **** + 227:Drivers/CMSIS/Include/cmsis_gcc.h **** + 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 229:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register + 230:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register. + 231:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value + 232:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void) + 234:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 235:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 236:Drivers/CMSIS/Include/cmsis_gcc.h **** + 237:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + 238:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 239:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 240:Drivers/CMSIS/Include/cmsis_gcc.h **** + 241:Drivers/CMSIS/Include/cmsis_gcc.h **** + 242:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 243:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer + 244:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP). + 245:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 246:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 247:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void) + 248:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 249:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 250:Drivers/CMSIS/Include/cmsis_gcc.h **** + 251:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp" : "=r" (result) ); + 252:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 253:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 254:Drivers/CMSIS/Include/cmsis_gcc.h **** + 255:Drivers/CMSIS/Include/cmsis_gcc.h **** + 256:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 257:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 258:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer (non-secure) + 259:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s + 260:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 261:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) + 263:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 264:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 265:Drivers/CMSIS/Include/cmsis_gcc.h **** + 266:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + 267:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 268:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 269:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + ARM GAS /tmp/ccwFmvCn.s page 40 + + + 270:Drivers/CMSIS/Include/cmsis_gcc.h **** + 271:Drivers/CMSIS/Include/cmsis_gcc.h **** + 272:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 273:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer + 274:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP). + 275:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 276:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 277:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) + 278:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 279:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); + 280:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 281:Drivers/CMSIS/Include/cmsis_gcc.h **** + 282:Drivers/CMSIS/Include/cmsis_gcc.h **** + 283:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 284:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 285:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + 286:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta + 287:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 288:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 289:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) + 290:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 291:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); + 292:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 293:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 294:Drivers/CMSIS/Include/cmsis_gcc.h **** + 295:Drivers/CMSIS/Include/cmsis_gcc.h **** + 296:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 297:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer + 298:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP). + 299:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 300:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 301:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void) + 302:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 303:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 304:Drivers/CMSIS/Include/cmsis_gcc.h **** + 305:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp" : "=r" (result) ); + 306:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 307:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 308:Drivers/CMSIS/Include/cmsis_gcc.h **** + 309:Drivers/CMSIS/Include/cmsis_gcc.h **** + 310:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 311:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 312:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer (non-secure) + 313:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat + 314:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 315:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 316:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) + 317:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 318:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 319:Drivers/CMSIS/Include/cmsis_gcc.h **** + 320:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + 321:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 322:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 324:Drivers/CMSIS/Include/cmsis_gcc.h **** + 325:Drivers/CMSIS/Include/cmsis_gcc.h **** + 326:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + ARM GAS /tmp/ccwFmvCn.s page 41 + + + 327:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer + 328:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP). + 329:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 330:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 331:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) + 332:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 333:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); + 334:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 335:Drivers/CMSIS/Include/cmsis_gcc.h **** + 336:Drivers/CMSIS/Include/cmsis_gcc.h **** + 337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 338:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 339:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer (non-secure) + 340:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + 341:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 342:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 343:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) + 344:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 345:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); + 346:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 347:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 348:Drivers/CMSIS/Include/cmsis_gcc.h **** + 349:Drivers/CMSIS/Include/cmsis_gcc.h **** + 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 352:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Stack Pointer (non-secure) + 353:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + 354:Drivers/CMSIS/Include/cmsis_gcc.h **** \return SP Register value + 355:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) + 357:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 358:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 359:Drivers/CMSIS/Include/cmsis_gcc.h **** + 360:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + 361:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 362:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 363:Drivers/CMSIS/Include/cmsis_gcc.h **** + 364:Drivers/CMSIS/Include/cmsis_gcc.h **** + 365:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 366:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Stack Pointer (non-secure) + 367:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + 368:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfStack Stack Pointer value to set + 369:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 370:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) + 371:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 372:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); + 373:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 374:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 375:Drivers/CMSIS/Include/cmsis_gcc.h **** + 376:Drivers/CMSIS/Include/cmsis_gcc.h **** + 377:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 378:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask + 379:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register. + 380:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 381:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 382:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) + 383:Drivers/CMSIS/Include/cmsis_gcc.h **** { + ARM GAS /tmp/ccwFmvCn.s page 42 + + + 384:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 385:Drivers/CMSIS/Include/cmsis_gcc.h **** + 386:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 387:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 388:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 389:Drivers/CMSIS/Include/cmsis_gcc.h **** + 390:Drivers/CMSIS/Include/cmsis_gcc.h **** + 391:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 392:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 393:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask (non-secure) + 394:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg + 395:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 396:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 397:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) + 398:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 399:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 400:Drivers/CMSIS/Include/cmsis_gcc.h **** + 401:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + 402:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 403:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 405:Drivers/CMSIS/Include/cmsis_gcc.h **** + 406:Drivers/CMSIS/Include/cmsis_gcc.h **** + 407:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 408:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask + 409:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register. + 410:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 411:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 412:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) + 413:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 414:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 415:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 416:Drivers/CMSIS/Include/cmsis_gcc.h **** + 417:Drivers/CMSIS/Include/cmsis_gcc.h **** + 418:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 419:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 420:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask (non-secure) + 421:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + 422:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 423:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 424:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) + 425:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 426:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); + 427:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 428:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 429:Drivers/CMSIS/Include/cmsis_gcc.h **** + 430:Drivers/CMSIS/Include/cmsis_gcc.h **** + 431:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 432:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 433:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + 434:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 435:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ + 436:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + 437:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 438:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 439:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void) + 440:Drivers/CMSIS/Include/cmsis_gcc.h **** { + ARM GAS /tmp/ccwFmvCn.s page 43 + + + 441:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory"); + 442:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 443:Drivers/CMSIS/Include/cmsis_gcc.h **** + 444:Drivers/CMSIS/Include/cmsis_gcc.h **** + 445:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 446:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ + 447:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR. + 448:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 449:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 450:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void) + 451:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 452:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory"); + 453:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 454:Drivers/CMSIS/Include/cmsis_gcc.h **** + 455:Drivers/CMSIS/Include/cmsis_gcc.h **** + 456:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 457:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority + 458:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register. + 459:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 460:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 461:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) + 462:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 463:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 464:Drivers/CMSIS/Include/cmsis_gcc.h **** + 465:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + 466:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 467:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 468:Drivers/CMSIS/Include/cmsis_gcc.h **** + 469:Drivers/CMSIS/Include/cmsis_gcc.h **** + 470:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 471:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 472:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority (non-secure) + 473:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Base Priority register when in secure state. + 474:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 475:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) + 477:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 478:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 479:Drivers/CMSIS/Include/cmsis_gcc.h **** + 480:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + 481:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 482:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 483:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 484:Drivers/CMSIS/Include/cmsis_gcc.h **** + 485:Drivers/CMSIS/Include/cmsis_gcc.h **** + 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 487:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority + 488:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register. + 489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 490:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) + 492:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 493:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); + 494:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 495:Drivers/CMSIS/Include/cmsis_gcc.h **** + 496:Drivers/CMSIS/Include/cmsis_gcc.h **** + 497:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + ARM GAS /tmp/ccwFmvCn.s page 44 + + + 498:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 499:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority (non-secure) + 500:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Base Priority register when in secure state. + 501:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 502:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 503:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) + 504:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 505:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); + 506:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 507:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 508:Drivers/CMSIS/Include/cmsis_gcc.h **** + 509:Drivers/CMSIS/Include/cmsis_gcc.h **** + 510:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 511:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition + 512:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable + 513:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level. + 514:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 515:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 516:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) + 517:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 518:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); + 519:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 520:Drivers/CMSIS/Include/cmsis_gcc.h **** + 521:Drivers/CMSIS/Include/cmsis_gcc.h **** + 522:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 523:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask + 524:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register. + 525:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 526:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) + 528:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 529:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 530:Drivers/CMSIS/Include/cmsis_gcc.h **** + 531:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + 532:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 533:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 534:Drivers/CMSIS/Include/cmsis_gcc.h **** + 535:Drivers/CMSIS/Include/cmsis_gcc.h **** + 536:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 537:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 538:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask (non-secure) + 539:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Fault Mask register when in secure state. + 540:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 541:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 542:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) + 543:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 544:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 545:Drivers/CMSIS/Include/cmsis_gcc.h **** + 546:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + 547:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 548:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 549:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 550:Drivers/CMSIS/Include/cmsis_gcc.h **** + 551:Drivers/CMSIS/Include/cmsis_gcc.h **** + 552:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 553:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask + 554:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register. + ARM GAS /tmp/ccwFmvCn.s page 45 + + + 555:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 556:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 557:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) + 558:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 559:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); + 560:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 561:Drivers/CMSIS/Include/cmsis_gcc.h **** + 562:Drivers/CMSIS/Include/cmsis_gcc.h **** + 563:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 564:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 565:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask (non-secure) + 566:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Fault Mask register when in secure state. + 567:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 568:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 569:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) + 570:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 571:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); + 572:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 573:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 574:Drivers/CMSIS/Include/cmsis_gcc.h **** + 575:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 576:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 577:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + 578:Drivers/CMSIS/Include/cmsis_gcc.h **** + 579:Drivers/CMSIS/Include/cmsis_gcc.h **** + 580:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 581:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + 582:Drivers/CMSIS/Include/cmsis_gcc.h **** + 583:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 584:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit + 585:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 586:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 587:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 588:Drivers/CMSIS/Include/cmsis_gcc.h **** + 589:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + 590:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 591:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 592:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) + 593:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 594:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 595:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 596:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 597:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 598:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 599:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 600:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + 601:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 602:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 603:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 604:Drivers/CMSIS/Include/cmsis_gcc.h **** + 605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) + 606:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 607:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit (non-secure) + 608:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 609:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + 610:Drivers/CMSIS/Include/cmsis_gcc.h **** + 611:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in + ARM GAS /tmp/ccwFmvCn.s page 46 + + + 612:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 613:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 614:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) + 615:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 617:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 618:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 619:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 620:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 621:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + 622:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 623:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 624:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 625:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 626:Drivers/CMSIS/Include/cmsis_gcc.h **** + 627:Drivers/CMSIS/Include/cmsis_gcc.h **** + 628:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 629:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer Limit + 630:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 631:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 632:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 633:Drivers/CMSIS/Include/cmsis_gcc.h **** + 634:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + 635:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 636:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 637:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) + 638:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 639:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 640:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 641:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 642:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 643:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 644:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); + 645:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 646:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 647:Drivers/CMSIS/Include/cmsis_gcc.h **** + 648:Drivers/CMSIS/Include/cmsis_gcc.h **** + 649:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 651:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + 652:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 653:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 654:Drivers/CMSIS/Include/cmsis_gcc.h **** + 655:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s + 656:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 657:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 658:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) + 659:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 661:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 662:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 663:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 664:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); + 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 666:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 667:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 668:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccwFmvCn.s page 47 + + + 669:Drivers/CMSIS/Include/cmsis_gcc.h **** + 670:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 671:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit + 672:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 673:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 674:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 675:Drivers/CMSIS/Include/cmsis_gcc.h **** + 676:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + 677:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 678:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) + 680:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 681:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 682:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 683:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 684:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 685:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 686:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 687:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + 688:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 689:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 690:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 691:Drivers/CMSIS/Include/cmsis_gcc.h **** + 692:Drivers/CMSIS/Include/cmsis_gcc.h **** + 693:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 694:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 695:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit (non-secure) + 696:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 697:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + 698:Drivers/CMSIS/Include/cmsis_gcc.h **** + 699:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec + 700:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 701:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 702:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) + 703:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 704:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 705:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 706:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 707:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 708:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 709:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + 710:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 711:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 712:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 713:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 714:Drivers/CMSIS/Include/cmsis_gcc.h **** + 715:Drivers/CMSIS/Include/cmsis_gcc.h **** + 716:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 717:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit + 718:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 719:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 720:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 721:Drivers/CMSIS/Include/cmsis_gcc.h **** + 722:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + 723:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + 724:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) + ARM GAS /tmp/ccwFmvCn.s page 48 + + + 726:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 728:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 729:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 730:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 731:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 732:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); + 733:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 734:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 735:Drivers/CMSIS/Include/cmsis_gcc.h **** + 736:Drivers/CMSIS/Include/cmsis_gcc.h **** + 737:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 738:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 739:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit (non-secure) + 740:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 741:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 742:Drivers/CMSIS/Include/cmsis_gcc.h **** + 743:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu + 744:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer value to set + 745:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) + 747:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 749:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 750:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 751:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 752:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); + 753:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 754:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 755:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 756:Drivers/CMSIS/Include/cmsis_gcc.h **** + 757:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 758:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + 759:Drivers/CMSIS/Include/cmsis_gcc.h **** + 760:Drivers/CMSIS/Include/cmsis_gcc.h **** + 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 762:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR + 763:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register. + 764:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value + 765:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 766:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) + 767:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 768:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 769:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 770:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) + 771:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + 772:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 773:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 774:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_arm_get_fpscr(); + 775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 776:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 777:Drivers/CMSIS/Include/cmsis_gcc.h **** + 778:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + 779:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 781:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 782:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0U); + ARM GAS /tmp/ccwFmvCn.s page 49 + + + 783:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 784:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 785:Drivers/CMSIS/Include/cmsis_gcc.h **** + 786:Drivers/CMSIS/Include/cmsis_gcc.h **** + 787:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 788:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR + 789:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register. + 790:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set + 791:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) + 793:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 795:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 796:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr) + 797:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + 798:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 799:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 800:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_arm_set_fpscr(fpscr); + 801:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 802:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); + 803:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 805:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)fpscr; + 806:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 807:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 808:Drivers/CMSIS/Include/cmsis_gcc.h **** + 809:Drivers/CMSIS/Include/cmsis_gcc.h **** + 810:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */ + 811:Drivers/CMSIS/Include/cmsis_gcc.h **** + 812:Drivers/CMSIS/Include/cmsis_gcc.h **** + 813:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */ + 814:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + 815:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions + 816:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 817:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 818:Drivers/CMSIS/Include/cmsis_gcc.h **** + 819:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2. + 820:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l" + 821:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */ + 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__) + 823:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r) + 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r) + 825:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r) + 826:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 827:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r) + 828:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r) + 829:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r) + 830:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 831:Drivers/CMSIS/Include/cmsis_gcc.h **** + 832:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 833:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation + 834:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes. + 835:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 836:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP() __ASM volatile ("nop") + 837:Drivers/CMSIS/Include/cmsis_gcc.h **** + 838:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 839:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt + ARM GAS /tmp/ccwFmvCn.s page 50 + + + 840:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o + 841:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI() __ASM volatile ("wfi") + 843:Drivers/CMSIS/Include/cmsis_gcc.h **** + 844:Drivers/CMSIS/Include/cmsis_gcc.h **** + 845:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 846:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event + 847:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter + 848:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs. + 849:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE() __ASM volatile ("wfe") + 851:Drivers/CMSIS/Include/cmsis_gcc.h **** + 852:Drivers/CMSIS/Include/cmsis_gcc.h **** + 853:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 854:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event + 855:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + 856:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 857:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev") + 858:Drivers/CMSIS/Include/cmsis_gcc.h **** + 859:Drivers/CMSIS/Include/cmsis_gcc.h **** + 860:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 861:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier + 862:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor, + 863:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory, + 864:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed. + 865:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 866:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void) + 867:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 868:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory"); + 869:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 870:Drivers/CMSIS/Include/cmsis_gcc.h **** + 871:Drivers/CMSIS/Include/cmsis_gcc.h **** + 872:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 873:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier + 874:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier. + 875:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete. + 876:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 877:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void) + 878:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 879:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory"); + 232 .loc 3 879 3 + 233 .syntax unified + 234 @ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 235 002c BFF34F8F dsb 0xF + 236 @ 0 "" 2 + 880:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 237 .loc 3 880 1 + 238 .thumb + 239 .syntax unified + 240 0030 00BF nop + 241 .LBE11: + 242 .LBE10: + 243 .LBB12: + 244 .LBB13: + 868:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 245 .loc 3 868 3 + 246 .syntax unified + ARM GAS /tmp/ccwFmvCn.s page 51 + + + 247 @ 868 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 248 0032 BFF36F8F isb 0xF + 249 @ 0 "" 2 + 869:Drivers/CMSIS/Include/cmsis_gcc.h **** + 250 .loc 3 869 1 + 251 .thumb + 252 .syntax unified + 253 0036 00BF nop + 254 .L15: + 255 .LBE13: + 256 .LBE12: +1729:Drivers/CMSIS/Include/core_cm4.h **** __DSB(); +1730:Drivers/CMSIS/Include/core_cm4.h **** __ISB(); +1731:Drivers/CMSIS/Include/core_cm4.h **** } +1732:Drivers/CMSIS/Include/core_cm4.h **** } + 257 .loc 2 1732 1 + 258 0038 00BF nop + 259 003a 0C37 adds r7, r7, #12 + 260 .cfi_def_cfa_offset 4 + 261 003c BD46 mov sp, r7 + 262 .cfi_def_cfa_register 13 + 263 @ sp needed + 264 003e 5DF8047B ldr r7, [sp], #4 + 265 .cfi_restore 7 + 266 .cfi_def_cfa_offset 0 + 267 0042 7047 bx lr + 268 .L17: + 269 .align 2 + 270 .L16: + 271 0044 00E100E0 .word -536813312 + 272 .cfi_endproc + 273 .LFE106: + 275 .section .text.__NVIC_GetPendingIRQ,"ax",%progbits + 276 .align 1 + 277 .syntax unified + 278 .thumb + 279 .thumb_func + 281 __NVIC_GetPendingIRQ: + 282 .LFB107: +1733:Drivers/CMSIS/Include/core_cm4.h **** +1734:Drivers/CMSIS/Include/core_cm4.h **** +1735:Drivers/CMSIS/Include/core_cm4.h **** /** +1736:Drivers/CMSIS/Include/core_cm4.h **** \brief Get Pending Interrupt +1737:Drivers/CMSIS/Include/core_cm4.h **** \details Reads the NVIC pending register and returns the pending bit for the specified device spe +1738:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Device specific interrupt number. +1739:Drivers/CMSIS/Include/core_cm4.h **** \return 0 Interrupt status is not pending. +1740:Drivers/CMSIS/Include/core_cm4.h **** \return 1 Interrupt status is pending. +1741:Drivers/CMSIS/Include/core_cm4.h **** \note IRQn must not be negative. +1742:Drivers/CMSIS/Include/core_cm4.h **** */ +1743:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +1744:Drivers/CMSIS/Include/core_cm4.h **** { + 283 .loc 2 1744 1 + 284 .cfi_startproc + 285 @ args = 0, pretend = 0, frame = 8 + 286 @ frame_needed = 1, uses_anonymous_args = 0 + 287 @ link register save eliminated. + 288 0000 80B4 push {r7} + ARM GAS /tmp/ccwFmvCn.s page 52 + + + 289 .cfi_def_cfa_offset 4 + 290 .cfi_offset 7, -4 + 291 0002 83B0 sub sp, sp, #12 + 292 .cfi_def_cfa_offset 16 + 293 0004 00AF add r7, sp, #0 + 294 .cfi_def_cfa_register 7 + 295 0006 0346 mov r3, r0 + 296 0008 FB71 strb r3, [r7, #7] +1745:Drivers/CMSIS/Include/core_cm4.h **** if ((int32_t)(IRQn) >= 0) + 297 .loc 2 1745 6 + 298 000a 97F90730 ldrsb r3, [r7, #7] + 299 000e 002B cmp r3, #0 + 300 0010 0EDB blt .L19 +1746:Drivers/CMSIS/Include/core_cm4.h **** { +1747:Drivers/CMSIS/Include/core_cm4.h **** return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL) + 301 .loc 2 1747 29 + 302 0012 0B4A ldr r2, .L21 + 303 .loc 2 1747 38 + 304 0014 97F90730 ldrsb r3, [r7, #7] + 305 .loc 2 1747 54 + 306 0018 5B09 lsrs r3, r3, #5 + 307 .loc 2 1747 35 + 308 001a 4033 adds r3, r3, #64 + 309 001c 52F82320 ldr r2, [r2, r3, lsl #2] + 310 .loc 2 1747 91 + 311 0020 FB79 ldrb r3, [r7, #7] @ zero_extendqisi2 + 312 0022 03F01F03 and r3, r3, #31 + 313 .loc 2 1747 103 + 314 0026 22FA03F3 lsr r3, r2, r3 + 315 .loc 2 1747 12 + 316 002a 03F00103 and r3, r3, #1 + 317 002e 00E0 b .L20 + 318 .L19: +1748:Drivers/CMSIS/Include/core_cm4.h **** } +1749:Drivers/CMSIS/Include/core_cm4.h **** else +1750:Drivers/CMSIS/Include/core_cm4.h **** { +1751:Drivers/CMSIS/Include/core_cm4.h **** return(0U); + 319 .loc 2 1751 11 + 320 0030 0023 movs r3, #0 + 321 .L20: +1752:Drivers/CMSIS/Include/core_cm4.h **** } +1753:Drivers/CMSIS/Include/core_cm4.h **** } + 322 .loc 2 1753 1 + 323 0032 1846 mov r0, r3 + 324 0034 0C37 adds r7, r7, #12 + 325 .cfi_def_cfa_offset 4 + 326 0036 BD46 mov sp, r7 + 327 .cfi_def_cfa_register 13 + 328 @ sp needed + 329 0038 5DF8047B ldr r7, [sp], #4 + 330 .cfi_restore 7 + 331 .cfi_def_cfa_offset 0 + 332 003c 7047 bx lr + 333 .L22: + 334 003e 00BF .align 2 + 335 .L21: + 336 0040 00E100E0 .word -536813312 + ARM GAS /tmp/ccwFmvCn.s page 53 + + + 337 .cfi_endproc + 338 .LFE107: + 340 .section .text.__NVIC_SetPendingIRQ,"ax",%progbits + 341 .align 1 + 342 .syntax unified + 343 .thumb + 344 .thumb_func + 346 __NVIC_SetPendingIRQ: + 347 .LFB108: +1754:Drivers/CMSIS/Include/core_cm4.h **** +1755:Drivers/CMSIS/Include/core_cm4.h **** +1756:Drivers/CMSIS/Include/core_cm4.h **** /** +1757:Drivers/CMSIS/Include/core_cm4.h **** \brief Set Pending Interrupt +1758:Drivers/CMSIS/Include/core_cm4.h **** \details Sets the pending bit of a device specific interrupt in the NVIC pending register. +1759:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Device specific interrupt number. +1760:Drivers/CMSIS/Include/core_cm4.h **** \note IRQn must not be negative. +1761:Drivers/CMSIS/Include/core_cm4.h **** */ +1762:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +1763:Drivers/CMSIS/Include/core_cm4.h **** { + 348 .loc 2 1763 1 + 349 .cfi_startproc + 350 @ args = 0, pretend = 0, frame = 8 + 351 @ frame_needed = 1, uses_anonymous_args = 0 + 352 @ link register save eliminated. + 353 0000 80B4 push {r7} + 354 .cfi_def_cfa_offset 4 + 355 .cfi_offset 7, -4 + 356 0002 83B0 sub sp, sp, #12 + 357 .cfi_def_cfa_offset 16 + 358 0004 00AF add r7, sp, #0 + 359 .cfi_def_cfa_register 7 + 360 0006 0346 mov r3, r0 + 361 0008 FB71 strb r3, [r7, #7] +1764:Drivers/CMSIS/Include/core_cm4.h **** if ((int32_t)(IRQn) >= 0) + 362 .loc 2 1764 6 + 363 000a 97F90730 ldrsb r3, [r7, #7] + 364 000e 002B cmp r3, #0 + 365 0010 0CDB blt .L25 +1765:Drivers/CMSIS/Include/core_cm4.h **** { +1766:Drivers/CMSIS/Include/core_cm4.h **** NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 366 .loc 2 1766 81 + 367 0012 FB79 ldrb r3, [r7, #7] @ zero_extendqisi2 + 368 0014 03F01F02 and r2, r3, #31 + 369 .loc 2 1766 9 + 370 0018 0749 ldr r1, .L26 + 371 .loc 2 1766 18 + 372 001a 97F90730 ldrsb r3, [r7, #7] + 373 .loc 2 1766 34 + 374 001e 5B09 lsrs r3, r3, #5 + 375 .loc 2 1766 45 + 376 0020 0120 movs r0, #1 + 377 0022 00FA02F2 lsl r2, r0, r2 + 378 .loc 2 1766 43 + 379 0026 4033 adds r3, r3, #64 + 380 0028 41F82320 str r2, [r1, r3, lsl #2] + 381 .L25: +1767:Drivers/CMSIS/Include/core_cm4.h **** } + ARM GAS /tmp/ccwFmvCn.s page 54 + + +1768:Drivers/CMSIS/Include/core_cm4.h **** } + 382 .loc 2 1768 1 + 383 002c 00BF nop + 384 002e 0C37 adds r7, r7, #12 + 385 .cfi_def_cfa_offset 4 + 386 0030 BD46 mov sp, r7 + 387 .cfi_def_cfa_register 13 + 388 @ sp needed + 389 0032 5DF8047B ldr r7, [sp], #4 + 390 .cfi_restore 7 + 391 .cfi_def_cfa_offset 0 + 392 0036 7047 bx lr + 393 .L27: + 394 .align 2 + 395 .L26: + 396 0038 00E100E0 .word -536813312 + 397 .cfi_endproc + 398 .LFE108: + 400 .section .text.__NVIC_ClearPendingIRQ,"ax",%progbits + 401 .align 1 + 402 .syntax unified + 403 .thumb + 404 .thumb_func + 406 __NVIC_ClearPendingIRQ: + 407 .LFB109: +1769:Drivers/CMSIS/Include/core_cm4.h **** +1770:Drivers/CMSIS/Include/core_cm4.h **** +1771:Drivers/CMSIS/Include/core_cm4.h **** /** +1772:Drivers/CMSIS/Include/core_cm4.h **** \brief Clear Pending Interrupt +1773:Drivers/CMSIS/Include/core_cm4.h **** \details Clears the pending bit of a device specific interrupt in the NVIC pending register. +1774:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Device specific interrupt number. +1775:Drivers/CMSIS/Include/core_cm4.h **** \note IRQn must not be negative. +1776:Drivers/CMSIS/Include/core_cm4.h **** */ +1777:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +1778:Drivers/CMSIS/Include/core_cm4.h **** { + 408 .loc 2 1778 1 + 409 .cfi_startproc + 410 @ args = 0, pretend = 0, frame = 8 + 411 @ frame_needed = 1, uses_anonymous_args = 0 + 412 @ link register save eliminated. + 413 0000 80B4 push {r7} + 414 .cfi_def_cfa_offset 4 + 415 .cfi_offset 7, -4 + 416 0002 83B0 sub sp, sp, #12 + 417 .cfi_def_cfa_offset 16 + 418 0004 00AF add r7, sp, #0 + 419 .cfi_def_cfa_register 7 + 420 0006 0346 mov r3, r0 + 421 0008 FB71 strb r3, [r7, #7] +1779:Drivers/CMSIS/Include/core_cm4.h **** if ((int32_t)(IRQn) >= 0) + 422 .loc 2 1779 6 + 423 000a 97F90730 ldrsb r3, [r7, #7] + 424 000e 002B cmp r3, #0 + 425 0010 0CDB blt .L30 +1780:Drivers/CMSIS/Include/core_cm4.h **** { +1781:Drivers/CMSIS/Include/core_cm4.h **** NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 426 .loc 2 1781 81 + ARM GAS /tmp/ccwFmvCn.s page 55 + + + 427 0012 FB79 ldrb r3, [r7, #7] @ zero_extendqisi2 + 428 0014 03F01F02 and r2, r3, #31 + 429 .loc 2 1781 9 + 430 0018 0749 ldr r1, .L31 + 431 .loc 2 1781 18 + 432 001a 97F90730 ldrsb r3, [r7, #7] + 433 .loc 2 1781 34 + 434 001e 5B09 lsrs r3, r3, #5 + 435 .loc 2 1781 45 + 436 0020 0120 movs r0, #1 + 437 0022 00FA02F2 lsl r2, r0, r2 + 438 .loc 2 1781 43 + 439 0026 6033 adds r3, r3, #96 + 440 0028 41F82320 str r2, [r1, r3, lsl #2] + 441 .L30: +1782:Drivers/CMSIS/Include/core_cm4.h **** } +1783:Drivers/CMSIS/Include/core_cm4.h **** } + 442 .loc 2 1783 1 + 443 002c 00BF nop + 444 002e 0C37 adds r7, r7, #12 + 445 .cfi_def_cfa_offset 4 + 446 0030 BD46 mov sp, r7 + 447 .cfi_def_cfa_register 13 + 448 @ sp needed + 449 0032 5DF8047B ldr r7, [sp], #4 + 450 .cfi_restore 7 + 451 .cfi_def_cfa_offset 0 + 452 0036 7047 bx lr + 453 .L32: + 454 .align 2 + 455 .L31: + 456 0038 00E100E0 .word -536813312 + 457 .cfi_endproc + 458 .LFE109: + 460 .section .text.__NVIC_GetActive,"ax",%progbits + 461 .align 1 + 462 .syntax unified + 463 .thumb + 464 .thumb_func + 466 __NVIC_GetActive: + 467 .LFB110: +1784:Drivers/CMSIS/Include/core_cm4.h **** +1785:Drivers/CMSIS/Include/core_cm4.h **** +1786:Drivers/CMSIS/Include/core_cm4.h **** /** +1787:Drivers/CMSIS/Include/core_cm4.h **** \brief Get Active Interrupt +1788:Drivers/CMSIS/Include/core_cm4.h **** \details Reads the active register in the NVIC and returns the active bit for the device specific +1789:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Device specific interrupt number. +1790:Drivers/CMSIS/Include/core_cm4.h **** \return 0 Interrupt status is not active. +1791:Drivers/CMSIS/Include/core_cm4.h **** \return 1 Interrupt status is active. +1792:Drivers/CMSIS/Include/core_cm4.h **** \note IRQn must not be negative. +1793:Drivers/CMSIS/Include/core_cm4.h **** */ +1794:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +1795:Drivers/CMSIS/Include/core_cm4.h **** { + 468 .loc 2 1795 1 + 469 .cfi_startproc + 470 @ args = 0, pretend = 0, frame = 8 + 471 @ frame_needed = 1, uses_anonymous_args = 0 + ARM GAS /tmp/ccwFmvCn.s page 56 + + + 472 @ link register save eliminated. + 473 0000 80B4 push {r7} + 474 .cfi_def_cfa_offset 4 + 475 .cfi_offset 7, -4 + 476 0002 83B0 sub sp, sp, #12 + 477 .cfi_def_cfa_offset 16 + 478 0004 00AF add r7, sp, #0 + 479 .cfi_def_cfa_register 7 + 480 0006 0346 mov r3, r0 + 481 0008 FB71 strb r3, [r7, #7] +1796:Drivers/CMSIS/Include/core_cm4.h **** if ((int32_t)(IRQn) >= 0) + 482 .loc 2 1796 6 + 483 000a 97F90730 ldrsb r3, [r7, #7] + 484 000e 002B cmp r3, #0 + 485 0010 0EDB blt .L34 +1797:Drivers/CMSIS/Include/core_cm4.h **** { +1798:Drivers/CMSIS/Include/core_cm4.h **** return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL) + 486 .loc 2 1798 29 + 487 0012 0B4A ldr r2, .L36 + 488 .loc 2 1798 38 + 489 0014 97F90730 ldrsb r3, [r7, #7] + 490 .loc 2 1798 54 + 491 0018 5B09 lsrs r3, r3, #5 + 492 .loc 2 1798 35 + 493 001a 8033 adds r3, r3, #128 + 494 001c 52F82320 ldr r2, [r2, r3, lsl #2] + 495 .loc 2 1798 91 + 496 0020 FB79 ldrb r3, [r7, #7] @ zero_extendqisi2 + 497 0022 03F01F03 and r3, r3, #31 + 498 .loc 2 1798 103 + 499 0026 22FA03F3 lsr r3, r2, r3 + 500 .loc 2 1798 12 + 501 002a 03F00103 and r3, r3, #1 + 502 002e 00E0 b .L35 + 503 .L34: +1799:Drivers/CMSIS/Include/core_cm4.h **** } +1800:Drivers/CMSIS/Include/core_cm4.h **** else +1801:Drivers/CMSIS/Include/core_cm4.h **** { +1802:Drivers/CMSIS/Include/core_cm4.h **** return(0U); + 504 .loc 2 1802 11 + 505 0030 0023 movs r3, #0 + 506 .L35: +1803:Drivers/CMSIS/Include/core_cm4.h **** } +1804:Drivers/CMSIS/Include/core_cm4.h **** } + 507 .loc 2 1804 1 + 508 0032 1846 mov r0, r3 + 509 0034 0C37 adds r7, r7, #12 + 510 .cfi_def_cfa_offset 4 + 511 0036 BD46 mov sp, r7 + 512 .cfi_def_cfa_register 13 + 513 @ sp needed + 514 0038 5DF8047B ldr r7, [sp], #4 + 515 .cfi_restore 7 + 516 .cfi_def_cfa_offset 0 + 517 003c 7047 bx lr + 518 .L37: + 519 003e 00BF .align 2 + ARM GAS /tmp/ccwFmvCn.s page 57 + + + 520 .L36: + 521 0040 00E100E0 .word -536813312 + 522 .cfi_endproc + 523 .LFE110: + 525 .section .text.__NVIC_SetPriority,"ax",%progbits + 526 .align 1 + 527 .syntax unified + 528 .thumb + 529 .thumb_func + 531 __NVIC_SetPriority: + 532 .LFB111: +1805:Drivers/CMSIS/Include/core_cm4.h **** +1806:Drivers/CMSIS/Include/core_cm4.h **** +1807:Drivers/CMSIS/Include/core_cm4.h **** /** +1808:Drivers/CMSIS/Include/core_cm4.h **** \brief Set Interrupt Priority +1809:Drivers/CMSIS/Include/core_cm4.h **** \details Sets the priority of a device specific interrupt or a processor exception. +1810:Drivers/CMSIS/Include/core_cm4.h **** The interrupt number can be positive to specify a device specific interrupt, +1811:Drivers/CMSIS/Include/core_cm4.h **** or negative to specify a processor exception. +1812:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Interrupt number. +1813:Drivers/CMSIS/Include/core_cm4.h **** \param [in] priority Priority to set. +1814:Drivers/CMSIS/Include/core_cm4.h **** \note The priority cannot be set for every processor exception. +1815:Drivers/CMSIS/Include/core_cm4.h **** */ +1816:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +1817:Drivers/CMSIS/Include/core_cm4.h **** { + 533 .loc 2 1817 1 + 534 .cfi_startproc + 535 @ args = 0, pretend = 0, frame = 8 + 536 @ frame_needed = 1, uses_anonymous_args = 0 + 537 @ link register save eliminated. + 538 0000 80B4 push {r7} + 539 .cfi_def_cfa_offset 4 + 540 .cfi_offset 7, -4 + 541 0002 83B0 sub sp, sp, #12 + 542 .cfi_def_cfa_offset 16 + 543 0004 00AF add r7, sp, #0 + 544 .cfi_def_cfa_register 7 + 545 0006 0346 mov r3, r0 + 546 0008 3960 str r1, [r7] + 547 000a FB71 strb r3, [r7, #7] +1818:Drivers/CMSIS/Include/core_cm4.h **** if ((int32_t)(IRQn) >= 0) + 548 .loc 2 1818 6 + 549 000c 97F90730 ldrsb r3, [r7, #7] + 550 0010 002B cmp r3, #0 + 551 0012 0ADB blt .L39 +1819:Drivers/CMSIS/Include/core_cm4.h **** { +1820:Drivers/CMSIS/Include/core_cm4.h **** NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (u + 552 .loc 2 1820 48 + 553 0014 3B68 ldr r3, [r7] + 554 0016 DAB2 uxtb r2, r3 + 555 .loc 2 1820 9 + 556 0018 0C49 ldr r1, .L42 + 557 .loc 2 1820 15 + 558 001a 97F90730 ldrsb r3, [r7, #7] + 559 .loc 2 1820 48 + 560 001e 1201 lsls r2, r2, #4 + 561 0020 D2B2 uxtb r2, r2 + 562 .loc 2 1820 46 + ARM GAS /tmp/ccwFmvCn.s page 58 + + + 563 0022 0B44 add r3, r3, r1 + 564 0024 83F80023 strb r2, [r3, #768] +1821:Drivers/CMSIS/Include/core_cm4.h **** } +1822:Drivers/CMSIS/Include/core_cm4.h **** else +1823:Drivers/CMSIS/Include/core_cm4.h **** { +1824:Drivers/CMSIS/Include/core_cm4.h **** SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (u +1825:Drivers/CMSIS/Include/core_cm4.h **** } +1826:Drivers/CMSIS/Include/core_cm4.h **** } + 565 .loc 2 1826 1 + 566 0028 0AE0 b .L41 + 567 .L39: +1824:Drivers/CMSIS/Include/core_cm4.h **** } + 568 .loc 2 1824 48 + 569 002a 3B68 ldr r3, [r7] + 570 002c DAB2 uxtb r2, r3 +1824:Drivers/CMSIS/Include/core_cm4.h **** } + 571 .loc 2 1824 8 + 572 002e 0849 ldr r1, .L42+4 +1824:Drivers/CMSIS/Include/core_cm4.h **** } + 573 .loc 2 1824 32 + 574 0030 FB79 ldrb r3, [r7, #7] @ zero_extendqisi2 + 575 0032 03F00F03 and r3, r3, #15 +1824:Drivers/CMSIS/Include/core_cm4.h **** } + 576 .loc 2 1824 40 + 577 0036 043B subs r3, r3, #4 +1824:Drivers/CMSIS/Include/core_cm4.h **** } + 578 .loc 2 1824 48 + 579 0038 1201 lsls r2, r2, #4 + 580 003a D2B2 uxtb r2, r2 +1824:Drivers/CMSIS/Include/core_cm4.h **** } + 581 .loc 2 1824 46 + 582 003c 0B44 add r3, r3, r1 + 583 003e 1A76 strb r2, [r3, #24] + 584 .L41: + 585 .loc 2 1826 1 + 586 0040 00BF nop + 587 0042 0C37 adds r7, r7, #12 + 588 .cfi_def_cfa_offset 4 + 589 0044 BD46 mov sp, r7 + 590 .cfi_def_cfa_register 13 + 591 @ sp needed + 592 0046 5DF8047B ldr r7, [sp], #4 + 593 .cfi_restore 7 + 594 .cfi_def_cfa_offset 0 + 595 004a 7047 bx lr + 596 .L43: + 597 .align 2 + 598 .L42: + 599 004c 00E100E0 .word -536813312 + 600 0050 00ED00E0 .word -536810240 + 601 .cfi_endproc + 602 .LFE111: + 604 .section .text.__NVIC_GetPriority,"ax",%progbits + 605 .align 1 + 606 .syntax unified + 607 .thumb + 608 .thumb_func + ARM GAS /tmp/ccwFmvCn.s page 59 + + + 610 __NVIC_GetPriority: + 611 .LFB112: +1827:Drivers/CMSIS/Include/core_cm4.h **** +1828:Drivers/CMSIS/Include/core_cm4.h **** +1829:Drivers/CMSIS/Include/core_cm4.h **** /** +1830:Drivers/CMSIS/Include/core_cm4.h **** \brief Get Interrupt Priority +1831:Drivers/CMSIS/Include/core_cm4.h **** \details Reads the priority of a device specific interrupt or a processor exception. +1832:Drivers/CMSIS/Include/core_cm4.h **** The interrupt number can be positive to specify a device specific interrupt, +1833:Drivers/CMSIS/Include/core_cm4.h **** or negative to specify a processor exception. +1834:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Interrupt number. +1835:Drivers/CMSIS/Include/core_cm4.h **** \return Interrupt Priority. +1836:Drivers/CMSIS/Include/core_cm4.h **** Value is aligned automatically to the implemented priority bits of the microc +1837:Drivers/CMSIS/Include/core_cm4.h **** */ +1838:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +1839:Drivers/CMSIS/Include/core_cm4.h **** { + 612 .loc 2 1839 1 + 613 .cfi_startproc + 614 @ args = 0, pretend = 0, frame = 8 + 615 @ frame_needed = 1, uses_anonymous_args = 0 + 616 @ link register save eliminated. + 617 0000 80B4 push {r7} + 618 .cfi_def_cfa_offset 4 + 619 .cfi_offset 7, -4 + 620 0002 83B0 sub sp, sp, #12 + 621 .cfi_def_cfa_offset 16 + 622 0004 00AF add r7, sp, #0 + 623 .cfi_def_cfa_register 7 + 624 0006 0346 mov r3, r0 + 625 0008 FB71 strb r3, [r7, #7] +1840:Drivers/CMSIS/Include/core_cm4.h **** +1841:Drivers/CMSIS/Include/core_cm4.h **** if ((int32_t)(IRQn) >= 0) + 626 .loc 2 1841 6 + 627 000a 97F90730 ldrsb r3, [r7, #7] + 628 000e 002B cmp r3, #0 + 629 0010 09DB blt .L45 +1842:Drivers/CMSIS/Include/core_cm4.h **** { +1843:Drivers/CMSIS/Include/core_cm4.h **** return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + 630 .loc 2 1843 27 + 631 0012 0D4A ldr r2, .L47 + 632 .loc 2 1843 33 + 633 0014 97F90730 ldrsb r3, [r7, #7] + 634 .loc 2 1843 31 + 635 0018 1344 add r3, r3, r2 + 636 001a 93F80033 ldrb r3, [r3, #768] + 637 001e DBB2 uxtb r3, r3 + 638 .loc 2 1843 64 + 639 0020 1B09 lsrs r3, r3, #4 + 640 0022 DBB2 uxtb r3, r3 + 641 0024 09E0 b .L46 + 642 .L45: +1844:Drivers/CMSIS/Include/core_cm4.h **** } +1845:Drivers/CMSIS/Include/core_cm4.h **** else +1846:Drivers/CMSIS/Include/core_cm4.h **** { +1847:Drivers/CMSIS/Include/core_cm4.h **** return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + 643 .loc 2 1847 26 + 644 0026 094A ldr r2, .L47+4 + 645 .loc 2 1847 50 + ARM GAS /tmp/ccwFmvCn.s page 60 + + + 646 0028 FB79 ldrb r3, [r7, #7] @ zero_extendqisi2 + 647 002a 03F00F03 and r3, r3, #15 + 648 .loc 2 1847 58 + 649 002e 043B subs r3, r3, #4 + 650 .loc 2 1847 31 + 651 0030 1344 add r3, r3, r2 + 652 0032 1B7E ldrb r3, [r3, #24] + 653 0034 DBB2 uxtb r3, r3 + 654 .loc 2 1847 64 + 655 0036 1B09 lsrs r3, r3, #4 + 656 0038 DBB2 uxtb r3, r3 + 657 .L46: +1848:Drivers/CMSIS/Include/core_cm4.h **** } +1849:Drivers/CMSIS/Include/core_cm4.h **** } + 658 .loc 2 1849 1 + 659 003a 1846 mov r0, r3 + 660 003c 0C37 adds r7, r7, #12 + 661 .cfi_def_cfa_offset 4 + 662 003e BD46 mov sp, r7 + 663 .cfi_def_cfa_register 13 + 664 @ sp needed + 665 0040 5DF8047B ldr r7, [sp], #4 + 666 .cfi_restore 7 + 667 .cfi_def_cfa_offset 0 + 668 0044 7047 bx lr + 669 .L48: + 670 0046 00BF .align 2 + 671 .L47: + 672 0048 00E100E0 .word -536813312 + 673 004c 00ED00E0 .word -536810240 + 674 .cfi_endproc + 675 .LFE112: + 677 .section .text.NVIC_EncodePriority,"ax",%progbits + 678 .align 1 + 679 .syntax unified + 680 .thumb + 681 .thumb_func + 683 NVIC_EncodePriority: + 684 .LFB113: +1850:Drivers/CMSIS/Include/core_cm4.h **** +1851:Drivers/CMSIS/Include/core_cm4.h **** +1852:Drivers/CMSIS/Include/core_cm4.h **** /** +1853:Drivers/CMSIS/Include/core_cm4.h **** \brief Encode Priority +1854:Drivers/CMSIS/Include/core_cm4.h **** \details Encodes the priority for an interrupt with the given priority group, +1855:Drivers/CMSIS/Include/core_cm4.h **** preemptive priority value, and subpriority value. +1856:Drivers/CMSIS/Include/core_cm4.h **** In case of a conflict between priority grouping and available +1857:Drivers/CMSIS/Include/core_cm4.h **** priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. +1858:Drivers/CMSIS/Include/core_cm4.h **** \param [in] PriorityGroup Used priority group. +1859:Drivers/CMSIS/Include/core_cm4.h **** \param [in] PreemptPriority Preemptive priority value (starting from 0). +1860:Drivers/CMSIS/Include/core_cm4.h **** \param [in] SubPriority Subpriority value (starting from 0). +1861:Drivers/CMSIS/Include/core_cm4.h **** \return Encoded priority. Value can be used in the function \ref NVIC_SetP +1862:Drivers/CMSIS/Include/core_cm4.h **** */ +1863:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uin +1864:Drivers/CMSIS/Include/core_cm4.h **** { + 685 .loc 2 1864 1 + 686 .cfi_startproc + 687 @ args = 0, pretend = 0, frame = 32 + ARM GAS /tmp/ccwFmvCn.s page 61 + + + 688 @ frame_needed = 1, uses_anonymous_args = 0 + 689 @ link register save eliminated. + 690 0000 80B4 push {r7} + 691 .cfi_def_cfa_offset 4 + 692 .cfi_offset 7, -4 + 693 0002 89B0 sub sp, sp, #36 + 694 .cfi_def_cfa_offset 40 + 695 0004 00AF add r7, sp, #0 + 696 .cfi_def_cfa_register 7 + 697 0006 F860 str r0, [r7, #12] + 698 0008 B960 str r1, [r7, #8] + 699 000a 7A60 str r2, [r7, #4] +1865:Drivers/CMSIS/Include/core_cm4.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used + 700 .loc 2 1865 12 + 701 000c FB68 ldr r3, [r7, #12] + 702 000e 03F00703 and r3, r3, #7 + 703 0012 FB61 str r3, [r7, #28] +1866:Drivers/CMSIS/Include/core_cm4.h **** uint32_t PreemptPriorityBits; +1867:Drivers/CMSIS/Include/core_cm4.h **** uint32_t SubPriorityBits; +1868:Drivers/CMSIS/Include/core_cm4.h **** +1869:Drivers/CMSIS/Include/core_cm4.h **** PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NV + 704 .loc 2 1869 31 + 705 0014 FB69 ldr r3, [r7, #28] + 706 0016 C3F10703 rsb r3, r3, #7 + 707 .loc 2 1869 23 + 708 001a 042B cmp r3, #4 + 709 001c 28BF it cs + 710 001e 0423 movcs r3, #4 + 711 0020 BB61 str r3, [r7, #24] +1870:Drivers/CMSIS/Include/core_cm4.h **** SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint + 712 .loc 2 1870 44 + 713 0022 FB69 ldr r3, [r7, #28] + 714 0024 0433 adds r3, r3, #4 + 715 .loc 2 1870 109 + 716 0026 062B cmp r3, #6 + 717 0028 02D9 bls .L50 + 718 .loc 2 1870 109 is_stmt 0 discriminator 1 + 719 002a FB69 ldr r3, [r7, #28] + 720 002c 033B subs r3, r3, #3 + 721 002e 00E0 b .L51 + 722 .L50: + 723 .loc 2 1870 109 discriminator 2 + 724 0030 0023 movs r3, #0 + 725 .L51: + 726 .loc 2 1870 23 is_stmt 1 discriminator 4 + 727 0032 7B61 str r3, [r7, #20] +1871:Drivers/CMSIS/Include/core_cm4.h **** +1872:Drivers/CMSIS/Include/core_cm4.h **** return ( +1873:Drivers/CMSIS/Include/core_cm4.h **** ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits + 728 .loc 2 1873 30 + 729 0034 4FF0FF32 mov r2, #-1 + 730 0038 BB69 ldr r3, [r7, #24] + 731 003a 02FA03F3 lsl r3, r2, r3 + 732 003e DA43 mvns r2, r3 + 733 0040 BB68 ldr r3, [r7, #8] + 734 0042 1A40 ands r2, r2, r3 + 735 .loc 2 1873 82 + ARM GAS /tmp/ccwFmvCn.s page 62 + + + 736 0044 7B69 ldr r3, [r7, #20] + 737 0046 9A40 lsls r2, r2, r3 +1874:Drivers/CMSIS/Include/core_cm4.h **** ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + 738 .loc 2 1874 30 + 739 0048 4FF0FF31 mov r1, #-1 + 740 004c 7B69 ldr r3, [r7, #20] + 741 004e 01FA03F3 lsl r3, r1, r3 + 742 0052 D943 mvns r1, r3 + 743 0054 7B68 ldr r3, [r7, #4] + 744 0056 0B40 ands r3, r3, r1 +1873:Drivers/CMSIS/Include/core_cm4.h **** ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + 745 .loc 2 1873 102 + 746 0058 1343 orrs r3, r3, r2 +1875:Drivers/CMSIS/Include/core_cm4.h **** ); +1876:Drivers/CMSIS/Include/core_cm4.h **** } + 747 .loc 2 1876 1 + 748 005a 1846 mov r0, r3 + 749 005c 2437 adds r7, r7, #36 + 750 .cfi_def_cfa_offset 4 + 751 005e BD46 mov sp, r7 + 752 .cfi_def_cfa_register 13 + 753 @ sp needed + 754 0060 5DF8047B ldr r7, [sp], #4 + 755 .cfi_restore 7 + 756 .cfi_def_cfa_offset 0 + 757 0064 7047 bx lr + 758 .cfi_endproc + 759 .LFE113: + 761 .section .text.NVIC_DecodePriority,"ax",%progbits + 762 .align 1 + 763 .syntax unified + 764 .thumb + 765 .thumb_func + 767 NVIC_DecodePriority: + 768 .LFB114: +1877:Drivers/CMSIS/Include/core_cm4.h **** +1878:Drivers/CMSIS/Include/core_cm4.h **** +1879:Drivers/CMSIS/Include/core_cm4.h **** /** +1880:Drivers/CMSIS/Include/core_cm4.h **** \brief Decode Priority +1881:Drivers/CMSIS/Include/core_cm4.h **** \details Decodes an interrupt priority value with a given priority group to +1882:Drivers/CMSIS/Include/core_cm4.h **** preemptive priority value and subpriority value. +1883:Drivers/CMSIS/Include/core_cm4.h **** In case of a conflict between priority grouping and available +1884:Drivers/CMSIS/Include/core_cm4.h **** priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. +1885:Drivers/CMSIS/Include/core_cm4.h **** \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC +1886:Drivers/CMSIS/Include/core_cm4.h **** \param [in] PriorityGroup Used priority group. +1887:Drivers/CMSIS/Include/core_cm4.h **** \param [out] pPreemptPriority Preemptive priority value (starting from 0). +1888:Drivers/CMSIS/Include/core_cm4.h **** \param [out] pSubPriority Subpriority value (starting from 0). +1889:Drivers/CMSIS/Include/core_cm4.h **** */ +1890:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* cons +1891:Drivers/CMSIS/Include/core_cm4.h **** { + 769 .loc 2 1891 1 + 770 .cfi_startproc + 771 @ args = 0, pretend = 0, frame = 32 + 772 @ frame_needed = 1, uses_anonymous_args = 0 + 773 @ link register save eliminated. + 774 0000 80B4 push {r7} + 775 .cfi_def_cfa_offset 4 + ARM GAS /tmp/ccwFmvCn.s page 63 + + + 776 .cfi_offset 7, -4 + 777 0002 89B0 sub sp, sp, #36 + 778 .cfi_def_cfa_offset 40 + 779 0004 00AF add r7, sp, #0 + 780 .cfi_def_cfa_register 7 + 781 0006 F860 str r0, [r7, #12] + 782 0008 B960 str r1, [r7, #8] + 783 000a 7A60 str r2, [r7, #4] + 784 000c 3B60 str r3, [r7] +1892:Drivers/CMSIS/Include/core_cm4.h **** uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used + 785 .loc 2 1892 12 + 786 000e BB68 ldr r3, [r7, #8] + 787 0010 03F00703 and r3, r3, #7 + 788 0014 FB61 str r3, [r7, #28] +1893:Drivers/CMSIS/Include/core_cm4.h **** uint32_t PreemptPriorityBits; +1894:Drivers/CMSIS/Include/core_cm4.h **** uint32_t SubPriorityBits; +1895:Drivers/CMSIS/Include/core_cm4.h **** +1896:Drivers/CMSIS/Include/core_cm4.h **** PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NV + 789 .loc 2 1896 31 + 790 0016 FB69 ldr r3, [r7, #28] + 791 0018 C3F10703 rsb r3, r3, #7 + 792 .loc 2 1896 23 + 793 001c 042B cmp r3, #4 + 794 001e 28BF it cs + 795 0020 0423 movcs r3, #4 + 796 0022 BB61 str r3, [r7, #24] +1897:Drivers/CMSIS/Include/core_cm4.h **** SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint + 797 .loc 2 1897 44 + 798 0024 FB69 ldr r3, [r7, #28] + 799 0026 0433 adds r3, r3, #4 + 800 .loc 2 1897 109 + 801 0028 062B cmp r3, #6 + 802 002a 02D9 bls .L54 + 803 .loc 2 1897 109 is_stmt 0 discriminator 1 + 804 002c FB69 ldr r3, [r7, #28] + 805 002e 033B subs r3, r3, #3 + 806 0030 00E0 b .L55 + 807 .L54: + 808 .loc 2 1897 109 discriminator 2 + 809 0032 0023 movs r3, #0 + 810 .L55: + 811 .loc 2 1897 23 is_stmt 1 discriminator 4 + 812 0034 7B61 str r3, [r7, #20] +1898:Drivers/CMSIS/Include/core_cm4.h **** +1899:Drivers/CMSIS/Include/core_cm4.h **** *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1 + 813 .loc 2 1899 33 + 814 0036 FA68 ldr r2, [r7, #12] + 815 0038 7B69 ldr r3, [r7, #20] + 816 003a DA40 lsrs r2, r2, r3 + 817 .loc 2 1899 53 + 818 003c 4FF0FF31 mov r1, #-1 + 819 0040 BB69 ldr r3, [r7, #24] + 820 0042 01FA03F3 lsl r3, r1, r3 + 821 0046 DB43 mvns r3, r3 + 822 0048 1A40 ands r2, r2, r3 + 823 .loc 2 1899 21 + 824 004a 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/ccwFmvCn.s page 64 + + + 825 004c 1A60 str r2, [r3] +1900:Drivers/CMSIS/Include/core_cm4.h **** *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1 + 826 .loc 2 1900 53 + 827 004e 4FF0FF32 mov r2, #-1 + 828 0052 7B69 ldr r3, [r7, #20] + 829 0054 02FA03F3 lsl r3, r2, r3 + 830 0058 DA43 mvns r2, r3 + 831 005a FB68 ldr r3, [r7, #12] + 832 005c 1A40 ands r2, r2, r3 + 833 .loc 2 1900 21 + 834 005e 3B68 ldr r3, [r7] + 835 0060 1A60 str r2, [r3] +1901:Drivers/CMSIS/Include/core_cm4.h **** } + 836 .loc 2 1901 1 + 837 0062 00BF nop + 838 0064 2437 adds r7, r7, #36 + 839 .cfi_def_cfa_offset 4 + 840 0066 BD46 mov sp, r7 + 841 .cfi_def_cfa_register 13 + 842 @ sp needed + 843 0068 5DF8047B ldr r7, [sp], #4 + 844 .cfi_restore 7 + 845 .cfi_def_cfa_offset 0 + 846 006c 7047 bx lr + 847 .cfi_endproc + 848 .LFE114: + 850 .section .text.__NVIC_SystemReset,"ax",%progbits + 851 .align 1 + 852 .syntax unified + 853 .thumb + 854 .thumb_func + 856 __NVIC_SystemReset: + 857 .LFB117: +1902:Drivers/CMSIS/Include/core_cm4.h **** +1903:Drivers/CMSIS/Include/core_cm4.h **** +1904:Drivers/CMSIS/Include/core_cm4.h **** /** +1905:Drivers/CMSIS/Include/core_cm4.h **** \brief Set Interrupt Vector +1906:Drivers/CMSIS/Include/core_cm4.h **** \details Sets an interrupt vector in SRAM based interrupt vector table. +1907:Drivers/CMSIS/Include/core_cm4.h **** The interrupt number can be positive to specify a device specific interrupt, +1908:Drivers/CMSIS/Include/core_cm4.h **** or negative to specify a processor exception. +1909:Drivers/CMSIS/Include/core_cm4.h **** VTOR must been relocated to SRAM before. +1910:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Interrupt number +1911:Drivers/CMSIS/Include/core_cm4.h **** \param [in] vector Address of interrupt handler function +1912:Drivers/CMSIS/Include/core_cm4.h **** */ +1913:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +1914:Drivers/CMSIS/Include/core_cm4.h **** { +1915:Drivers/CMSIS/Include/core_cm4.h **** uint32_t *vectors = (uint32_t *)SCB->VTOR; +1916:Drivers/CMSIS/Include/core_cm4.h **** vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +1917:Drivers/CMSIS/Include/core_cm4.h **** } +1918:Drivers/CMSIS/Include/core_cm4.h **** +1919:Drivers/CMSIS/Include/core_cm4.h **** +1920:Drivers/CMSIS/Include/core_cm4.h **** /** +1921:Drivers/CMSIS/Include/core_cm4.h **** \brief Get Interrupt Vector +1922:Drivers/CMSIS/Include/core_cm4.h **** \details Reads an interrupt vector from interrupt vector table. +1923:Drivers/CMSIS/Include/core_cm4.h **** The interrupt number can be positive to specify a device specific interrupt, +1924:Drivers/CMSIS/Include/core_cm4.h **** or negative to specify a processor exception. +1925:Drivers/CMSIS/Include/core_cm4.h **** \param [in] IRQn Interrupt number. + ARM GAS /tmp/ccwFmvCn.s page 65 + + +1926:Drivers/CMSIS/Include/core_cm4.h **** \return Address of interrupt handler function +1927:Drivers/CMSIS/Include/core_cm4.h **** */ +1928:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +1929:Drivers/CMSIS/Include/core_cm4.h **** { +1930:Drivers/CMSIS/Include/core_cm4.h **** uint32_t *vectors = (uint32_t *)SCB->VTOR; +1931:Drivers/CMSIS/Include/core_cm4.h **** return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +1932:Drivers/CMSIS/Include/core_cm4.h **** } +1933:Drivers/CMSIS/Include/core_cm4.h **** +1934:Drivers/CMSIS/Include/core_cm4.h **** +1935:Drivers/CMSIS/Include/core_cm4.h **** /** +1936:Drivers/CMSIS/Include/core_cm4.h **** \brief System Reset +1937:Drivers/CMSIS/Include/core_cm4.h **** \details Initiates a system reset request to reset the MCU. +1938:Drivers/CMSIS/Include/core_cm4.h **** */ +1939:Drivers/CMSIS/Include/core_cm4.h **** __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +1940:Drivers/CMSIS/Include/core_cm4.h **** { + 858 .loc 2 1940 1 + 859 .cfi_startproc + 860 @ args = 0, pretend = 0, frame = 0 + 861 @ frame_needed = 1, uses_anonymous_args = 0 + 862 @ link register save eliminated. + 863 0000 80B4 push {r7} + 864 .cfi_def_cfa_offset 4 + 865 .cfi_offset 7, -4 + 866 0002 00AF add r7, sp, #0 + 867 .cfi_def_cfa_register 7 + 868 .LBB14: + 869 .LBB15: + 879:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 870 .loc 3 879 3 + 871 .syntax unified + 872 @ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 873 0004 BFF34F8F dsb 0xF + 874 @ 0 "" 2 + 875 .loc 3 880 1 + 876 .thumb + 877 .syntax unified + 878 0008 00BF nop + 879 .LBE15: + 880 .LBE14: +1941:Drivers/CMSIS/Include/core_cm4.h **** __DSB(); /* Ensure all outstanding memor +1942:Drivers/CMSIS/Include/core_cm4.h **** buffered write are completed +1943:Drivers/CMSIS/Include/core_cm4.h **** SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | +1944:Drivers/CMSIS/Include/core_cm4.h **** (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + 881 .loc 2 1944 32 + 882 000a 064B ldr r3, .L58 + 883 000c DB68 ldr r3, [r3, #12] + 884 .loc 2 1944 40 + 885 000e 03F4E062 and r2, r3, #1792 +1943:Drivers/CMSIS/Include/core_cm4.h **** (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + 886 .loc 2 1943 6 + 887 0012 0449 ldr r1, .L58 +1943:Drivers/CMSIS/Include/core_cm4.h **** (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + 888 .loc 2 1943 17 + 889 0014 044B ldr r3, .L58+4 + 890 0016 1343 orrs r3, r3, r2 +1943:Drivers/CMSIS/Include/core_cm4.h **** (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + 891 .loc 2 1943 15 + ARM GAS /tmp/ccwFmvCn.s page 66 + + + 892 0018 CB60 str r3, [r1, #12] + 893 .LBB16: + 894 .LBB17: + 879:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 895 .loc 3 879 3 + 896 .syntax unified + 897 @ 879 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 898 001a BFF34F8F dsb 0xF + 899 @ 0 "" 2 + 900 .loc 3 880 1 + 901 .thumb + 902 .syntax unified + 903 001e 00BF nop + 904 .L57: + 905 .LBE17: + 906 .LBE16: +1945:Drivers/CMSIS/Include/core_cm4.h **** SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchange +1946:Drivers/CMSIS/Include/core_cm4.h **** __DSB(); /* Ensure completion of memory +1947:Drivers/CMSIS/Include/core_cm4.h **** +1948:Drivers/CMSIS/Include/core_cm4.h **** for(;;) /* wait until reset */ +1949:Drivers/CMSIS/Include/core_cm4.h **** { +1950:Drivers/CMSIS/Include/core_cm4.h **** __NOP(); + 907 .loc 2 1950 5 discriminator 1 + 908 .syntax unified + 909 @ 1950 "Drivers/CMSIS/Include/core_cm4.h" 1 + 910 0020 00BF nop + 911 @ 0 "" 2 + 912 .thumb + 913 .syntax unified + 914 0022 FDE7 b .L57 + 915 .L59: + 916 .align 2 + 917 .L58: + 918 0024 00ED00E0 .word -536810240 + 919 0028 0400FA05 .word 100270084 + 920 .cfi_endproc + 921 .LFE117: + 923 .section .text.SysTick_Config,"ax",%progbits + 924 .align 1 + 925 .syntax unified + 926 .thumb + 927 .thumb_func + 929 SysTick_Config: + 930 .LFB126: +1951:Drivers/CMSIS/Include/core_cm4.h **** } +1952:Drivers/CMSIS/Include/core_cm4.h **** } +1953:Drivers/CMSIS/Include/core_cm4.h **** +1954:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of CMSIS_Core_NVICFunctions */ +1955:Drivers/CMSIS/Include/core_cm4.h **** +1956:Drivers/CMSIS/Include/core_cm4.h **** /* ########################## MPU functions #################################### */ +1957:Drivers/CMSIS/Include/core_cm4.h **** +1958:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +1959:Drivers/CMSIS/Include/core_cm4.h **** +1960:Drivers/CMSIS/Include/core_cm4.h **** #include "mpu_armv7.h" +1961:Drivers/CMSIS/Include/core_cm4.h **** +1962:Drivers/CMSIS/Include/core_cm4.h **** #endif +1963:Drivers/CMSIS/Include/core_cm4.h **** + ARM GAS /tmp/ccwFmvCn.s page 67 + + +1964:Drivers/CMSIS/Include/core_cm4.h **** +1965:Drivers/CMSIS/Include/core_cm4.h **** /* ########################## FPU functions #################################### */ +1966:Drivers/CMSIS/Include/core_cm4.h **** /** +1967:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_Core_FunctionInterface +1968:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_Core_FpuFunctions FPU Functions +1969:Drivers/CMSIS/Include/core_cm4.h **** \brief Function that provides FPU type. +1970:Drivers/CMSIS/Include/core_cm4.h **** @{ +1971:Drivers/CMSIS/Include/core_cm4.h **** */ +1972:Drivers/CMSIS/Include/core_cm4.h **** +1973:Drivers/CMSIS/Include/core_cm4.h **** /** +1974:Drivers/CMSIS/Include/core_cm4.h **** \brief get FPU type +1975:Drivers/CMSIS/Include/core_cm4.h **** \details returns the FPU type +1976:Drivers/CMSIS/Include/core_cm4.h **** \returns +1977:Drivers/CMSIS/Include/core_cm4.h **** - \b 0: No FPU +1978:Drivers/CMSIS/Include/core_cm4.h **** - \b 1: Single precision FPU +1979:Drivers/CMSIS/Include/core_cm4.h **** - \b 2: Double + Single precision FPU +1980:Drivers/CMSIS/Include/core_cm4.h **** */ +1981:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t SCB_GetFPUType(void) +1982:Drivers/CMSIS/Include/core_cm4.h **** { +1983:Drivers/CMSIS/Include/core_cm4.h **** uint32_t mvfr0; +1984:Drivers/CMSIS/Include/core_cm4.h **** +1985:Drivers/CMSIS/Include/core_cm4.h **** mvfr0 = FPU->MVFR0; +1986:Drivers/CMSIS/Include/core_cm4.h **** if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) +1987:Drivers/CMSIS/Include/core_cm4.h **** { +1988:Drivers/CMSIS/Include/core_cm4.h **** return 1U; /* Single precision FPU */ +1989:Drivers/CMSIS/Include/core_cm4.h **** } +1990:Drivers/CMSIS/Include/core_cm4.h **** else +1991:Drivers/CMSIS/Include/core_cm4.h **** { +1992:Drivers/CMSIS/Include/core_cm4.h **** return 0U; /* No FPU */ +1993:Drivers/CMSIS/Include/core_cm4.h **** } +1994:Drivers/CMSIS/Include/core_cm4.h **** } +1995:Drivers/CMSIS/Include/core_cm4.h **** +1996:Drivers/CMSIS/Include/core_cm4.h **** +1997:Drivers/CMSIS/Include/core_cm4.h **** /*@} end of CMSIS_Core_FpuFunctions */ +1998:Drivers/CMSIS/Include/core_cm4.h **** +1999:Drivers/CMSIS/Include/core_cm4.h **** +2000:Drivers/CMSIS/Include/core_cm4.h **** +2001:Drivers/CMSIS/Include/core_cm4.h **** /* ################################## SysTick function ######################################## +2002:Drivers/CMSIS/Include/core_cm4.h **** /** +2003:Drivers/CMSIS/Include/core_cm4.h **** \ingroup CMSIS_Core_FunctionInterface +2004:Drivers/CMSIS/Include/core_cm4.h **** \defgroup CMSIS_Core_SysTickFunctions SysTick Functions +2005:Drivers/CMSIS/Include/core_cm4.h **** \brief Functions that configure the System. +2006:Drivers/CMSIS/Include/core_cm4.h **** @{ +2007:Drivers/CMSIS/Include/core_cm4.h **** */ +2008:Drivers/CMSIS/Include/core_cm4.h **** +2009:Drivers/CMSIS/Include/core_cm4.h **** #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) +2010:Drivers/CMSIS/Include/core_cm4.h **** +2011:Drivers/CMSIS/Include/core_cm4.h **** /** +2012:Drivers/CMSIS/Include/core_cm4.h **** \brief System Tick Configuration +2013:Drivers/CMSIS/Include/core_cm4.h **** \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. +2014:Drivers/CMSIS/Include/core_cm4.h **** Counter is in free running mode to generate periodic interrupts. +2015:Drivers/CMSIS/Include/core_cm4.h **** \param [in] ticks Number of ticks between two interrupts. +2016:Drivers/CMSIS/Include/core_cm4.h **** \return 0 Function succeeded. +2017:Drivers/CMSIS/Include/core_cm4.h **** \return 1 Function failed. +2018:Drivers/CMSIS/Include/core_cm4.h **** \note When the variable __Vendor_SysTickConfig is set to 1, then the +2019:Drivers/CMSIS/Include/core_cm4.h **** function SysTick_Config is not included. In this case, the file device. +2020:Drivers/CMSIS/Include/core_cm4.h **** must contain a vendor-specific implementation of this function. + ARM GAS /tmp/ccwFmvCn.s page 68 + + +2021:Drivers/CMSIS/Include/core_cm4.h **** */ +2022:Drivers/CMSIS/Include/core_cm4.h **** __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +2023:Drivers/CMSIS/Include/core_cm4.h **** { + 931 .loc 2 2023 1 + 932 .cfi_startproc + 933 @ args = 0, pretend = 0, frame = 8 + 934 @ frame_needed = 1, uses_anonymous_args = 0 + 935 0000 80B5 push {r7, lr} + 936 .cfi_def_cfa_offset 8 + 937 .cfi_offset 7, -8 + 938 .cfi_offset 14, -4 + 939 0002 82B0 sub sp, sp, #8 + 940 .cfi_def_cfa_offset 16 + 941 0004 00AF add r7, sp, #0 + 942 .cfi_def_cfa_register 7 + 943 0006 7860 str r0, [r7, #4] +2024:Drivers/CMSIS/Include/core_cm4.h **** if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + 944 .loc 2 2024 14 + 945 0008 7B68 ldr r3, [r7, #4] + 946 000a 013B subs r3, r3, #1 + 947 .loc 2 2024 6 + 948 000c B3F1807F cmp r3, #16777216 + 949 0010 01D3 bcc .L61 +2025:Drivers/CMSIS/Include/core_cm4.h **** { +2026:Drivers/CMSIS/Include/core_cm4.h **** return (1UL); /* Reload value impossible */ + 950 .loc 2 2026 12 + 951 0012 0123 movs r3, #1 + 952 0014 0FE0 b .L62 + 953 .L61: +2027:Drivers/CMSIS/Include/core_cm4.h **** } +2028:Drivers/CMSIS/Include/core_cm4.h **** +2029:Drivers/CMSIS/Include/core_cm4.h **** SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + 954 .loc 2 2029 10 + 955 0016 0A4A ldr r2, .L63 + 956 .loc 2 2029 20 + 957 0018 7B68 ldr r3, [r7, #4] + 958 001a 013B subs r3, r3, #1 + 959 .loc 2 2029 18 + 960 001c 5360 str r3, [r2, #4] +2030:Drivers/CMSIS/Include/core_cm4.h **** NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Int + 961 .loc 2 2030 3 + 962 001e 0F21 movs r1, #15 + 963 0020 4FF0FF30 mov r0, #-1 + 964 0024 FFF7FEFF bl __NVIC_SetPriority +2031:Drivers/CMSIS/Include/core_cm4.h **** SysTick->VAL = 0UL; /* Load the SysTick Counter Val + 965 .loc 2 2031 10 + 966 0028 054B ldr r3, .L63 + 967 .loc 2 2031 18 + 968 002a 0022 movs r2, #0 + 969 002c 9A60 str r2, [r3, #8] +2032:Drivers/CMSIS/Include/core_cm4.h **** SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + 970 .loc 2 2032 10 + 971 002e 044B ldr r3, .L63 + 972 .loc 2 2032 18 + 973 0030 0722 movs r2, #7 + 974 0032 1A60 str r2, [r3] +2033:Drivers/CMSIS/Include/core_cm4.h **** SysTick_CTRL_TICKINT_Msk | + ARM GAS /tmp/ccwFmvCn.s page 69 + + +2034:Drivers/CMSIS/Include/core_cm4.h **** SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTi +2035:Drivers/CMSIS/Include/core_cm4.h **** return (0UL); /* Function successful */ + 975 .loc 2 2035 10 + 976 0034 0023 movs r3, #0 + 977 .L62: +2036:Drivers/CMSIS/Include/core_cm4.h **** } + 978 .loc 2 2036 1 + 979 0036 1846 mov r0, r3 + 980 0038 0837 adds r7, r7, #8 + 981 .cfi_def_cfa_offset 8 + 982 003a BD46 mov sp, r7 + 983 .cfi_def_cfa_register 13 + 984 @ sp needed + 985 003c 80BD pop {r7, pc} + 986 .L64: + 987 003e 00BF .align 2 + 988 .L63: + 989 0040 10E000E0 .word -536813552 + 990 .cfi_endproc + 991 .LFE126: + 993 .section .text.HAL_NVIC_SetPriorityGrouping,"ax",%progbits + 994 .align 1 + 995 .global HAL_NVIC_SetPriorityGrouping + 996 .syntax unified + 997 .thumb + 998 .thumb_func + 1000 HAL_NVIC_SetPriorityGrouping: + 1001 .LFB130: + 1:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** + 2:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ****************************************************************************** + 3:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @file stm32f3xx_hal_cortex.c + 4:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @author MCD Application Team + 5:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief CORTEX HAL module driver. + 6:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * functionalities of the CORTEX: + 8:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * + Initialization and de-initialization functions + 9:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * + Peripheral Control functions + 10:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * + 11:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @verbatim + 12:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ============================================================================== + 13:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ##### How to use this driver ##### + 14:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ============================================================================== + 15:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 16:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** [..] + 17:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** *** How to configure Interrupts using CORTEX HAL driver *** + 18:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** =========================================================== + 19:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** [..] + 20:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** This section provides functions allowing to configure the NVIC interrupts (IRQ). + 21:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** The Cortex-M4 exceptions are managed by CMSIS functions. + 22:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 23:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function + 24:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 25:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority() + 26:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 27:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ() + 28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + ARM GAS /tmp/ccwFmvCn.s page 70 + + + 30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible. + 31:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** The pending IRQ priority will be managed only by the sub priority. + 32:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 33:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** -@- IRQ priority order (sorted by highest to lowest priority): + 34:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (+@) Lowest pre-emption priority + 35:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (+@) Lowest sub priority + 36:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (+@) Lowest hardware priority (IRQ number) + 37:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 38:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** [..] + 39:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** *** How to configure Systick using CORTEX HAL driver *** + 40:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ======================================================== + 41:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** [..] + 42:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** Setup SysTick Timer for time base + 43:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 44:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which + 45:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** is a CMSIS function that: + 46:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (++) Configures the SysTick Reload register with value passed as function parameter. + 47:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (++) Configures the SysTick IRQ priority to the lowest value (0x0FU). + 48:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (++) Resets the SysTick Counter register. + 49:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). + 50:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (++) Enables the SysTick Interrupt. + 51:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (++) Starts the SysTick Counter. + 52:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 53:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro + 54:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the + 55:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined + 56:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** inside the stm32f3xx_hal_cortex.h file. + 57:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 58:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (+) You can change the SysTick IRQ priority by calling the + 59:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function + 60:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS funct + 61:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 62:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (+) To adjust the SysTick time base, use the following formula: + 63:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 64:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) + 65:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function + 66:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (++) Reload Value should not exceed 0xFFFFFF + 67:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 68:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** @endverbatim + 69:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ****************************************************************************** + 70:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @attention + 71:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * + 72:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * Copyright (c) 2016 STMicroelectronics. + 73:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * All rights reserved. + 74:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * + 75:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * This software is licensed under terms that can be found in the LICENSE file in + 76:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * the root directory of this software component. + 77:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 78:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * + 79:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ****************************************************************************** + 80:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 81:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 82:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* + 83:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** Additional Tables: CORTEX_NVIC_Priority_Table + 84:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** The table below gives the allowed values of the pre-emption priority and subpriority according + 85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function + 86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ============================================================================================ + ARM GAS /tmp/ccwFmvCn.s page 71 + + + 87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | + 88:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ============================================================================================ + 89:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** NVIC_PRIORITYGROUP_0 | 0 | 0U-15 | + 90:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** | | | 4 + 91:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** -------------------------------------------------------------------------------------------- + 92:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** NVIC_PRIORITYGROUP_1 | 0U-1 | 0U-7 | + 93:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** | | | 3 + 94:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** -------------------------------------------------------------------------------------------- + 95:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** NVIC_PRIORITYGROUP_2 | 0U-3 | 0U-3 | + 96:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** | | | 2 + 97:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** -------------------------------------------------------------------------------------------- + 98:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** NVIC_PRIORITYGROUP_3 | 0U-7 | 0U-1 | + 99:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** | | | 1 + 100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** -------------------------------------------------------------------------------------------- + 101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** NVIC_PRIORITYGROUP_4 | 0U-15 | 0 | + 102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** | | | 0 + 103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ============================================================================================ + 104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Includes ------------------------------------------------------------------*/ + 108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** #include "stm32f3xx_hal.h" + 109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** @addtogroup STM32F3xx_HAL_Driver + 111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @{ + 112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** @defgroup CORTEX CORTEX + 115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief CORTEX CORTEX HAL module driver + 116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @{ + 117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** #ifdef HAL_CORTEX_MODULE_ENABLED + 120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Private typedef -----------------------------------------------------------*/ + 122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Private define ------------------------------------------------------------*/ + 123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Private macro -------------------------------------------------------------*/ + 124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Private variables ---------------------------------------------------------*/ + 125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Private function prototypes -----------------------------------------------*/ + 126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Exported functions ---------------------------------------------------------*/ + 127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions + 129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @{ + 130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions + 134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Initialization and Configuration functions + 135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * + 136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** @verbatim + 137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ============================================================================== + 138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ##### Initialization and de-initialization functions ##### + 139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ============================================================================== + 140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** [..] + 141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** This section provides the CORTEX HAL driver functions allowing to configure Interrupts + 142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** Systick functionalities + 143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + ARM GAS /tmp/ccwFmvCn.s page 72 + + + 144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** @endverbatim + 145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @{ + 146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** + 150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Sets the priority grouping field (pre-emption priority and subpriority) + 151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * using the required unlock sequence. + 152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param PriorityGroup The priority grouping bits length. + 153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * This parameter can be one of the following values: + 154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority + 155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * 4 bits for subpriority + 156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority + 157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * 3 bits for subpriority + 158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority + 159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * 2 bits for subpriority + 160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority + 161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * 1 bits for subpriority + 162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority + 163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * 0 bits for subpriority + 164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. + 165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * The pending IRQ priority will be managed only by the subpriority. + 166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval None + 167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) + 169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** { + 1002 .loc 1 169 1 + 1003 .cfi_startproc + 1004 @ args = 0, pretend = 0, frame = 8 + 1005 @ frame_needed = 1, uses_anonymous_args = 0 + 1006 0000 80B5 push {r7, lr} + 1007 .cfi_def_cfa_offset 8 + 1008 .cfi_offset 7, -8 + 1009 .cfi_offset 14, -4 + 1010 0002 82B0 sub sp, sp, #8 + 1011 .cfi_def_cfa_offset 16 + 1012 0004 00AF add r7, sp, #0 + 1013 .cfi_def_cfa_register 7 + 1014 0006 7860 str r0, [r7, #4] + 170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Check the parameters */ + 171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + 172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + 174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** NVIC_SetPriorityGrouping(PriorityGroup); + 1015 .loc 1 174 3 + 1016 0008 7868 ldr r0, [r7, #4] + 1017 000a FFF7FEFF bl __NVIC_SetPriorityGrouping + 175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 1018 .loc 1 175 1 + 1019 000e 00BF nop + 1020 0010 0837 adds r7, r7, #8 + 1021 .cfi_def_cfa_offset 8 + 1022 0012 BD46 mov sp, r7 + 1023 .cfi_def_cfa_register 13 + 1024 @ sp needed + 1025 0014 80BD pop {r7, pc} + 1026 .cfi_endproc + ARM GAS /tmp/ccwFmvCn.s page 73 + + + 1027 .LFE130: + 1029 .section .text.HAL_NVIC_SetPriority,"ax",%progbits + 1030 .align 1 + 1031 .global HAL_NVIC_SetPriority + 1032 .syntax unified + 1033 .thumb + 1034 .thumb_func + 1036 HAL_NVIC_SetPriority: + 1037 .LFB131: + 176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** + 178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Sets the priority of an interrupt. + 179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param IRQn External interrupt number + 180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration + 181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI + 182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param PreemptPriority The pre-emption priority for the IRQn channel. + 183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * This parameter can be a value between 0 and 15 as described in the table CORTEX_NVIC_Pr + 184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * A lower priority value indicates a higher priority + 185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param SubPriority the subpriority level for the IRQ channel. + 186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * This parameter can be a value between 0 and 15 as described in the table CORTEX_NVIC_Pr + 187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * A lower priority value indicates a higher priority. + 188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval None + 189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) + 191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** { + 1038 .loc 1 191 1 + 1039 .cfi_startproc + 1040 @ args = 0, pretend = 0, frame = 24 + 1041 @ frame_needed = 1, uses_anonymous_args = 0 + 1042 0000 80B5 push {r7, lr} + 1043 .cfi_def_cfa_offset 8 + 1044 .cfi_offset 7, -8 + 1045 .cfi_offset 14, -4 + 1046 0002 86B0 sub sp, sp, #24 + 1047 .cfi_def_cfa_offset 32 + 1048 0004 00AF add r7, sp, #0 + 1049 .cfi_def_cfa_register 7 + 1050 0006 0346 mov r3, r0 + 1051 0008 B960 str r1, [r7, #8] + 1052 000a 7A60 str r2, [r7, #4] + 1053 000c FB73 strb r3, [r7, #15] + 192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** uint32_t prioritygroup = 0x00U; + 1054 .loc 1 192 12 + 1055 000e 0023 movs r3, #0 + 1056 0010 7B61 str r3, [r7, #20] + 193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Check the parameters */ + 195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); + 196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + 197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** prioritygroup = NVIC_GetPriorityGrouping(); + 1057 .loc 1 198 19 + 1058 0012 FFF7FEFF bl __NVIC_GetPriorityGrouping + 1059 0016 7861 str r0, [r7, #20] + 199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); + 1060 .loc 1 200 3 + ARM GAS /tmp/ccwFmvCn.s page 74 + + + 1061 0018 7A68 ldr r2, [r7, #4] + 1062 001a B968 ldr r1, [r7, #8] + 1063 001c 7869 ldr r0, [r7, #20] + 1064 001e FFF7FEFF bl NVIC_EncodePriority + 1065 0022 0246 mov r2, r0 + 1066 .loc 1 200 3 is_stmt 0 discriminator 1 + 1067 0024 97F90F30 ldrsb r3, [r7, #15] + 1068 0028 1146 mov r1, r2 + 1069 002a 1846 mov r0, r3 + 1070 002c FFF7FEFF bl __NVIC_SetPriority + 201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 1071 .loc 1 201 1 is_stmt 1 + 1072 0030 00BF nop + 1073 0032 1837 adds r7, r7, #24 + 1074 .cfi_def_cfa_offset 8 + 1075 0034 BD46 mov sp, r7 + 1076 .cfi_def_cfa_register 13 + 1077 @ sp needed + 1078 0036 80BD pop {r7, pc} + 1079 .cfi_endproc + 1080 .LFE131: + 1082 .section .text.HAL_NVIC_EnableIRQ,"ax",%progbits + 1083 .align 1 + 1084 .global HAL_NVIC_EnableIRQ + 1085 .syntax unified + 1086 .thumb + 1087 .thumb_func + 1089 HAL_NVIC_EnableIRQ: + 1090 .LFB132: + 202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** + 204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Enables a device specific interrupt in the NVIC interrupt controller. + 205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() + 206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * function should be called before. + 207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param IRQn External interrupt number + 208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration + 209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI + 210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval None + 211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) + 213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** { + 1091 .loc 1 213 1 + 1092 .cfi_startproc + 1093 @ args = 0, pretend = 0, frame = 8 + 1094 @ frame_needed = 1, uses_anonymous_args = 0 + 1095 0000 80B5 push {r7, lr} + 1096 .cfi_def_cfa_offset 8 + 1097 .cfi_offset 7, -8 + 1098 .cfi_offset 14, -4 + 1099 0002 82B0 sub sp, sp, #8 + 1100 .cfi_def_cfa_offset 16 + 1101 0004 00AF add r7, sp, #0 + 1102 .cfi_def_cfa_register 7 + 1103 0006 0346 mov r3, r0 + 1104 0008 FB71 strb r3, [r7, #7] + 214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Check the parameters */ + 215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + ARM GAS /tmp/ccwFmvCn.s page 75 + + + 216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Enable interrupt */ + 218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** NVIC_EnableIRQ(IRQn); + 1105 .loc 1 218 3 + 1106 000a 97F90730 ldrsb r3, [r7, #7] + 1107 000e 1846 mov r0, r3 + 1108 0010 FFF7FEFF bl __NVIC_EnableIRQ + 219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 1109 .loc 1 219 1 + 1110 0014 00BF nop + 1111 0016 0837 adds r7, r7, #8 + 1112 .cfi_def_cfa_offset 8 + 1113 0018 BD46 mov sp, r7 + 1114 .cfi_def_cfa_register 13 + 1115 @ sp needed + 1116 001a 80BD pop {r7, pc} + 1117 .cfi_endproc + 1118 .LFE132: + 1120 .section .text.HAL_NVIC_DisableIRQ,"ax",%progbits + 1121 .align 1 + 1122 .global HAL_NVIC_DisableIRQ + 1123 .syntax unified + 1124 .thumb + 1125 .thumb_func + 1127 HAL_NVIC_DisableIRQ: + 1128 .LFB133: + 220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** + 222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Disables a device specific interrupt in the NVIC interrupt controller. + 223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param IRQn External interrupt number + 224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration + 225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI + 226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval None + 227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) + 229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** { + 1129 .loc 1 229 1 + 1130 .cfi_startproc + 1131 @ args = 0, pretend = 0, frame = 8 + 1132 @ frame_needed = 1, uses_anonymous_args = 0 + 1133 0000 80B5 push {r7, lr} + 1134 .cfi_def_cfa_offset 8 + 1135 .cfi_offset 7, -8 + 1136 .cfi_offset 14, -4 + 1137 0002 82B0 sub sp, sp, #8 + 1138 .cfi_def_cfa_offset 16 + 1139 0004 00AF add r7, sp, #0 + 1140 .cfi_def_cfa_register 7 + 1141 0006 0346 mov r3, r0 + 1142 0008 FB71 strb r3, [r7, #7] + 230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Check the parameters */ + 231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + 232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Disable interrupt */ + 234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** NVIC_DisableIRQ(IRQn); + 1143 .loc 1 234 3 + 1144 000a 97F90730 ldrsb r3, [r7, #7] + ARM GAS /tmp/ccwFmvCn.s page 76 + + + 1145 000e 1846 mov r0, r3 + 1146 0010 FFF7FEFF bl __NVIC_DisableIRQ + 235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 1147 .loc 1 235 1 + 1148 0014 00BF nop + 1149 0016 0837 adds r7, r7, #8 + 1150 .cfi_def_cfa_offset 8 + 1151 0018 BD46 mov sp, r7 + 1152 .cfi_def_cfa_register 13 + 1153 @ sp needed + 1154 001a 80BD pop {r7, pc} + 1155 .cfi_endproc + 1156 .LFE133: + 1158 .section .text.HAL_NVIC_SystemReset,"ax",%progbits + 1159 .align 1 + 1160 .global HAL_NVIC_SystemReset + 1161 .syntax unified + 1162 .thumb + 1163 .thumb_func + 1165 HAL_NVIC_SystemReset: + 1166 .LFB134: + 236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** + 238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Initiates a system reset request to reset the MCU. + 239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval None + 240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** void HAL_NVIC_SystemReset(void) + 242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** { + 1167 .loc 1 242 1 + 1168 .cfi_startproc + 1169 @ args = 0, pretend = 0, frame = 0 + 1170 @ frame_needed = 1, uses_anonymous_args = 0 + 1171 0000 80B5 push {r7, lr} + 1172 .cfi_def_cfa_offset 8 + 1173 .cfi_offset 7, -8 + 1174 .cfi_offset 14, -4 + 1175 0002 00AF add r7, sp, #0 + 1176 .cfi_def_cfa_register 7 + 243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* System Reset */ + 244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** NVIC_SystemReset(); + 1177 .loc 1 244 3 + 1178 0004 FFF7FEFF bl __NVIC_SystemReset + 1179 .cfi_endproc + 1180 .LFE134: + 1182 .section .text.HAL_SYSTICK_Config,"ax",%progbits + 1183 .align 1 + 1184 .global HAL_SYSTICK_Config + 1185 .syntax unified + 1186 .thumb + 1187 .thumb_func + 1189 HAL_SYSTICK_Config: + 1190 .LFB135: + 245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** + 248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. + 249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * Counter is in free running mode to generate periodic interrupts. + ARM GAS /tmp/ccwFmvCn.s page 77 + + + 250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. + 251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval status: - 0 Function succeeded. + 252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * - 1 Function failed. + 253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) + 255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** { + 1191 .loc 1 255 1 + 1192 .cfi_startproc + 1193 @ args = 0, pretend = 0, frame = 8 + 1194 @ frame_needed = 1, uses_anonymous_args = 0 + 1195 0000 80B5 push {r7, lr} + 1196 .cfi_def_cfa_offset 8 + 1197 .cfi_offset 7, -8 + 1198 .cfi_offset 14, -4 + 1199 0002 82B0 sub sp, sp, #8 + 1200 .cfi_def_cfa_offset 16 + 1201 0004 00AF add r7, sp, #0 + 1202 .cfi_def_cfa_register 7 + 1203 0006 7860 str r0, [r7, #4] + 256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** return SysTick_Config(TicksNumb); + 1204 .loc 1 256 11 + 1205 0008 7868 ldr r0, [r7, #4] + 1206 000a FFF7FEFF bl SysTick_Config + 1207 000e 0346 mov r3, r0 + 257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 1208 .loc 1 257 1 + 1209 0010 1846 mov r0, r3 + 1210 0012 0837 adds r7, r7, #8 + 1211 .cfi_def_cfa_offset 8 + 1212 0014 BD46 mov sp, r7 + 1213 .cfi_def_cfa_register 13 + 1214 @ sp needed + 1215 0016 80BD pop {r7, pc} + 1216 .cfi_endproc + 1217 .LFE135: + 1219 .section .text.HAL_MPU_Disable,"ax",%progbits + 1220 .align 1 + 1221 .global HAL_MPU_Disable + 1222 .syntax unified + 1223 .thumb + 1224 .thumb_func + 1226 HAL_MPU_Disable: + 1227 .LFB136: + 258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** + 259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @} + 260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions + 263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Cortex control functions + 264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * + 265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** @verbatim + 266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ============================================================================== + 267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ##### Peripheral Control functions ##### + 268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ============================================================================== + 269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** [..] + 270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** This subsection provides a set of functions allowing to control the CORTEX + 271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** (NVIC, SYSTICK, MPU) functionalities. + ARM GAS /tmp/ccwFmvCn.s page 78 + + + 272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** @endverbatim + 275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @{ + 276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** #if (__MPU_PRESENT == 1U) + 279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** + 281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Disables the MPU also clears the HFNMIENA bit (ARM recommendation) + 282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval None + 283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** void HAL_MPU_Disable(void) + 285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** { + 1228 .loc 1 285 1 + 1229 .cfi_startproc + 1230 @ args = 0, pretend = 0, frame = 0 + 1231 @ frame_needed = 1, uses_anonymous_args = 0 + 1232 @ link register save eliminated. + 1233 0000 80B4 push {r7} + 1234 .cfi_def_cfa_offset 4 + 1235 .cfi_offset 7, -4 + 1236 0002 00AF add r7, sp, #0 + 1237 .cfi_def_cfa_register 7 + 286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Disable fault exceptions */ + 287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; + 1238 .loc 1 287 6 + 1239 0004 064B ldr r3, .L73 + 1240 0006 5B6A ldr r3, [r3, #36] + 1241 0008 054A ldr r2, .L73 + 1242 .loc 1 287 14 + 1243 000a 23F48033 bic r3, r3, #65536 + 1244 000e 5362 str r3, [r2, #36] + 288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Disable the MPU */ + 290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** MPU->CTRL = 0U; + 1245 .loc 1 290 6 + 1246 0010 044B ldr r3, .L73+4 + 1247 .loc 1 290 13 + 1248 0012 0022 movs r2, #0 + 1249 0014 5A60 str r2, [r3, #4] + 291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 1250 .loc 1 291 1 + 1251 0016 00BF nop + 1252 0018 BD46 mov sp, r7 + 1253 .cfi_def_cfa_register 13 + 1254 @ sp needed + 1255 001a 5DF8047B ldr r7, [sp], #4 + 1256 .cfi_restore 7 + 1257 .cfi_def_cfa_offset 0 + 1258 001e 7047 bx lr + 1259 .L74: + 1260 .align 2 + 1261 .L73: + 1262 0020 00ED00E0 .word -536810240 + 1263 0024 90ED00E0 .word -536810096 + 1264 .cfi_endproc + ARM GAS /tmp/ccwFmvCn.s page 79 + + + 1265 .LFE136: + 1267 .section .text.HAL_MPU_Enable,"ax",%progbits + 1268 .align 1 + 1269 .global HAL_MPU_Enable + 1270 .syntax unified + 1271 .thumb + 1272 .thumb_func + 1274 HAL_MPU_Enable: + 1275 .LFB137: + 292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** + 294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Enables the MPU + 295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param MPU_Control Specifies the control mode of the MPU during hard fault, + 296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * NMI, FAULTMASK and privileged access to the default memory + 297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * This parameter can be one of the following values: + 298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @arg MPU_HFNMI_PRIVDEF_NONE + 299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @arg MPU_HARDFAULT_NMI + 300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @arg MPU_PRIVILEGED_DEFAULT + 301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @arg MPU_HFNMI_PRIVDEF + 302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval None + 303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** void HAL_MPU_Enable(uint32_t MPU_Control) + 305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** { + 1276 .loc 1 305 1 + 1277 .cfi_startproc + 1278 @ args = 0, pretend = 0, frame = 8 + 1279 @ frame_needed = 1, uses_anonymous_args = 0 + 1280 @ link register save eliminated. + 1281 0000 80B4 push {r7} + 1282 .cfi_def_cfa_offset 4 + 1283 .cfi_offset 7, -4 + 1284 0002 83B0 sub sp, sp, #12 + 1285 .cfi_def_cfa_offset 16 + 1286 0004 00AF add r7, sp, #0 + 1287 .cfi_def_cfa_register 7 + 1288 0006 7860 str r0, [r7, #4] + 306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Enable the MPU */ + 307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; + 1289 .loc 1 307 6 + 1290 0008 084A ldr r2, .L76 + 1291 .loc 1 307 29 + 1292 000a 7B68 ldr r3, [r7, #4] + 1293 000c 43F00103 orr r3, r3, #1 + 1294 .loc 1 307 15 + 1295 0010 5360 str r3, [r2, #4] + 308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Enable fault exceptions */ + 310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; + 1296 .loc 1 310 6 + 1297 0012 074B ldr r3, .L76+4 + 1298 0014 5B6A ldr r3, [r3, #36] + 1299 0016 064A ldr r2, .L76+4 + 1300 .loc 1 310 14 + 1301 0018 43F48033 orr r3, r3, #65536 + 1302 001c 5362 str r3, [r2, #36] + 311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 1303 .loc 1 311 1 + ARM GAS /tmp/ccwFmvCn.s page 80 + + + 1304 001e 00BF nop + 1305 0020 0C37 adds r7, r7, #12 + 1306 .cfi_def_cfa_offset 4 + 1307 0022 BD46 mov sp, r7 + 1308 .cfi_def_cfa_register 13 + 1309 @ sp needed + 1310 0024 5DF8047B ldr r7, [sp], #4 + 1311 .cfi_restore 7 + 1312 .cfi_def_cfa_offset 0 + 1313 0028 7047 bx lr + 1314 .L77: + 1315 002a 00BF .align 2 + 1316 .L76: + 1317 002c 90ED00E0 .word -536810096 + 1318 0030 00ED00E0 .word -536810240 + 1319 .cfi_endproc + 1320 .LFE137: + 1322 .section .text.HAL_MPU_ConfigRegion,"ax",%progbits + 1323 .align 1 + 1324 .global HAL_MPU_ConfigRegion + 1325 .syntax unified + 1326 .thumb + 1327 .thumb_func + 1329 HAL_MPU_ConfigRegion: + 1330 .LFB138: + 312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** + 314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Initializes and configures the Region and the memory to be protected. + 315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains + 316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * the initialization and configuration information. + 317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval None + 318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) + 320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** { + 1331 .loc 1 320 1 + 1332 .cfi_startproc + 1333 @ args = 0, pretend = 0, frame = 8 + 1334 @ frame_needed = 1, uses_anonymous_args = 0 + 1335 @ link register save eliminated. + 1336 0000 80B4 push {r7} + 1337 .cfi_def_cfa_offset 4 + 1338 .cfi_offset 7, -4 + 1339 0002 83B0 sub sp, sp, #12 + 1340 .cfi_def_cfa_offset 16 + 1341 0004 00AF add r7, sp, #0 + 1342 .cfi_def_cfa_register 7 + 1343 0006 7860 str r0, [r7, #4] + 321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Check the parameters */ + 322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); + 323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); + 324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Set the Region number */ + 326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** MPU->RNR = MPU_Init->Number; + 1344 .loc 1 326 22 + 1345 0008 7B68 ldr r3, [r7, #4] + 1346 000a 5A78 ldrb r2, [r3, #1] @ zero_extendqisi2 + 1347 .loc 1 326 6 + ARM GAS /tmp/ccwFmvCn.s page 81 + + + 1348 000c 1D4B ldr r3, .L82 + 1349 .loc 1 326 12 + 1350 000e 9A60 str r2, [r3, #8] + 327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** if ((MPU_Init->Enable) != RESET) + 1351 .loc 1 328 16 + 1352 0010 7B68 ldr r3, [r7, #4] + 1353 0012 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 1354 .loc 1 328 6 + 1355 0014 002B cmp r3, #0 + 1356 0016 29D0 beq .L79 + 329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** { + 330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Check the parameters */ + 331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); + 332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); + 333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); + 334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); + 335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); + 336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); + 337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); + 338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); + 339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** MPU->RBAR = MPU_Init->BaseAddress; + 1357 .loc 1 340 8 + 1358 0018 1A4A ldr r2, .L82 + 1359 .loc 1 340 25 + 1360 001a 7B68 ldr r3, [r7, #4] + 1361 001c 5B68 ldr r3, [r3, #4] + 1362 .loc 1 340 15 + 1363 001e D360 str r3, [r2, #12] + 341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | + 1364 .loc 1 341 36 + 1365 0020 7B68 ldr r3, [r7, #4] + 1366 0022 1B7B ldrb r3, [r3, #12] @ zero_extendqisi2 + 1367 .loc 1 341 62 + 1368 0024 1A07 lsls r2, r3, #28 + 342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | + 1369 .loc 1 342 36 + 1370 0026 7B68 ldr r3, [r7, #4] + 1371 0028 DB7A ldrb r3, [r3, #11] @ zero_extendqisi2 + 1372 .loc 1 342 62 + 1373 002a 1B06 lsls r3, r3, #24 + 341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | + 1374 .loc 1 341 84 + 1375 002c 1A43 orrs r2, r2, r3 + 343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | + 1376 .loc 1 343 36 + 1377 002e 7B68 ldr r3, [r7, #4] + 1378 0030 9B7A ldrb r3, [r3, #10] @ zero_extendqisi2 + 1379 .loc 1 343 62 + 1380 0032 DB04 lsls r3, r3, #19 + 342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | + 1381 .loc 1 342 84 + 1382 0034 1A43 orrs r2, r2, r3 + 344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | + 1383 .loc 1 344 36 + 1384 0036 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/ccwFmvCn.s page 82 + + + 1385 0038 5B7B ldrb r3, [r3, #13] @ zero_extendqisi2 + 1386 .loc 1 344 62 + 1387 003a 9B04 lsls r3, r3, #18 + 343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | + 1388 .loc 1 343 84 + 1389 003c 1A43 orrs r2, r2, r3 + 345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | + 1390 .loc 1 345 36 + 1391 003e 7B68 ldr r3, [r7, #4] + 1392 0040 9B7B ldrb r3, [r3, #14] @ zero_extendqisi2 + 1393 .loc 1 345 62 + 1394 0042 5B04 lsls r3, r3, #17 + 344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | + 1395 .loc 1 344 84 + 1396 0044 1A43 orrs r2, r2, r3 + 346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | + 1397 .loc 1 346 36 + 1398 0046 7B68 ldr r3, [r7, #4] + 1399 0048 DB7B ldrb r3, [r3, #15] @ zero_extendqisi2 + 1400 .loc 1 346 62 + 1401 004a 1B04 lsls r3, r3, #16 + 345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | + 1402 .loc 1 345 84 + 1403 004c 1A43 orrs r2, r2, r3 + 347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | + 1404 .loc 1 347 36 + 1405 004e 7B68 ldr r3, [r7, #4] + 1406 0050 5B7A ldrb r3, [r3, #9] @ zero_extendqisi2 + 1407 .loc 1 347 62 + 1408 0052 1B02 lsls r3, r3, #8 + 346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | + 1409 .loc 1 346 84 + 1410 0054 1A43 orrs r2, r2, r3 + 348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | + 1411 .loc 1 348 36 + 1412 0056 7B68 ldr r3, [r7, #4] + 1413 0058 1B7A ldrb r3, [r3, #8] @ zero_extendqisi2 + 1414 .loc 1 348 62 + 1415 005a 5B00 lsls r3, r3, #1 + 347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | + 1416 .loc 1 347 84 + 1417 005c 1343 orrs r3, r3, r2 + 349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); + 1418 .loc 1 349 36 + 1419 005e 7A68 ldr r2, [r7, #4] + 1420 0060 1278 ldrb r2, [r2] @ zero_extendqisi2 + 1421 .loc 1 349 62 + 1422 0062 1146 mov r1, r2 + 341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | + 1423 .loc 1 341 8 + 1424 0064 074A ldr r2, .L82 + 348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | + 1425 .loc 1 348 84 + 1426 0066 0B43 orrs r3, r3, r1 + 341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | + 1427 .loc 1 341 15 + 1428 0068 1361 str r3, [r2, #16] + ARM GAS /tmp/ccwFmvCn.s page 83 + + + 350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** else + 352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** { + 353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** MPU->RBAR = 0x00U; + 354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** MPU->RASR = 0x00U; + 355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 1429 .loc 1 356 1 + 1430 006a 05E0 b .L81 + 1431 .L79: + 353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** MPU->RASR = 0x00U; + 1432 .loc 1 353 8 + 1433 006c 054B ldr r3, .L82 + 353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** MPU->RASR = 0x00U; + 1434 .loc 1 353 15 + 1435 006e 0022 movs r2, #0 + 1436 0070 DA60 str r2, [r3, #12] + 354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 1437 .loc 1 354 8 + 1438 0072 044B ldr r3, .L82 + 354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 1439 .loc 1 354 15 + 1440 0074 0022 movs r2, #0 + 1441 0076 1A61 str r2, [r3, #16] + 1442 .L81: + 1443 .loc 1 356 1 + 1444 0078 00BF nop + 1445 007a 0C37 adds r7, r7, #12 + 1446 .cfi_def_cfa_offset 4 + 1447 007c BD46 mov sp, r7 + 1448 .cfi_def_cfa_register 13 + 1449 @ sp needed + 1450 007e 5DF8047B ldr r7, [sp], #4 + 1451 .cfi_restore 7 + 1452 .cfi_def_cfa_offset 0 + 1453 0082 7047 bx lr + 1454 .L83: + 1455 .align 2 + 1456 .L82: + 1457 0084 90ED00E0 .word -536810096 + 1458 .cfi_endproc + 1459 .LFE138: + 1461 .section .text.HAL_NVIC_GetPriorityGrouping,"ax",%progbits + 1462 .align 1 + 1463 .global HAL_NVIC_GetPriorityGrouping + 1464 .syntax unified + 1465 .thumb + 1466 .thumb_func + 1468 HAL_NVIC_GetPriorityGrouping: + 1469 .LFB139: + 357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** #endif /* __MPU_PRESENT */ + 358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** + 360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Gets the priority grouping field from the NVIC Interrupt Controller. + 361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) + 362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** uint32_t HAL_NVIC_GetPriorityGrouping(void) + ARM GAS /tmp/ccwFmvCn.s page 84 + + + 364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** { + 1470 .loc 1 364 1 + 1471 .cfi_startproc + 1472 @ args = 0, pretend = 0, frame = 0 + 1473 @ frame_needed = 1, uses_anonymous_args = 0 + 1474 0000 80B5 push {r7, lr} + 1475 .cfi_def_cfa_offset 8 + 1476 .cfi_offset 7, -8 + 1477 .cfi_offset 14, -4 + 1478 0002 00AF add r7, sp, #0 + 1479 .cfi_def_cfa_register 7 + 365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Get the PRIGROUP[10:8] field value */ + 366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** return NVIC_GetPriorityGrouping(); + 1480 .loc 1 366 10 + 1481 0004 FFF7FEFF bl __NVIC_GetPriorityGrouping + 1482 0008 0346 mov r3, r0 + 367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 1483 .loc 1 367 1 + 1484 000a 1846 mov r0, r3 + 1485 000c 80BD pop {r7, pc} + 1486 .cfi_endproc + 1487 .LFE139: + 1489 .section .text.HAL_NVIC_GetPriority,"ax",%progbits + 1490 .align 1 + 1491 .global HAL_NVIC_GetPriority + 1492 .syntax unified + 1493 .thumb + 1494 .thumb_func + 1496 HAL_NVIC_GetPriority: + 1497 .LFB140: + 368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** + 370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Gets the priority of an interrupt. + 371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param IRQn External interrupt number + 372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration + 373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI + 374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param PriorityGroup: the priority grouping bits length. + 375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * This parameter can be one of the following values: + 376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority + 377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * 4 bits for subpriority + 378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority + 379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * 3 bits for subpriority + 380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority + 381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * 2 bits for subpriority + 382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority + 383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * 1 bits for subpriority + 384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority + 385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * 0 bits for subpriority + 386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0). + 387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param pSubPriority Pointer on the Subpriority value (starting from 0). + 388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval None + 389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint3 + 391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** { + 1498 .loc 1 391 1 + 1499 .cfi_startproc + 1500 @ args = 0, pretend = 0, frame = 16 + ARM GAS /tmp/ccwFmvCn.s page 85 + + + 1501 @ frame_needed = 1, uses_anonymous_args = 0 + 1502 0000 80B5 push {r7, lr} + 1503 .cfi_def_cfa_offset 8 + 1504 .cfi_offset 7, -8 + 1505 .cfi_offset 14, -4 + 1506 0002 84B0 sub sp, sp, #16 + 1507 .cfi_def_cfa_offset 24 + 1508 0004 00AF add r7, sp, #0 + 1509 .cfi_def_cfa_register 7 + 1510 0006 B960 str r1, [r7, #8] + 1511 0008 7A60 str r2, [r7, #4] + 1512 000a 3B60 str r3, [r7] + 1513 000c 0346 mov r3, r0 + 1514 000e FB73 strb r3, [r7, #15] + 392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Check the parameters */ + 393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + 394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Get priority for Cortex-M system or device specific interrupts */ + 395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); + 1515 .loc 1 395 3 + 1516 0010 97F90F30 ldrsb r3, [r7, #15] + 1517 0014 1846 mov r0, r3 + 1518 0016 FFF7FEFF bl __NVIC_GetPriority + 1519 .loc 1 395 3 is_stmt 0 discriminator 1 + 1520 001a 3B68 ldr r3, [r7] + 1521 001c 7A68 ldr r2, [r7, #4] + 1522 001e B968 ldr r1, [r7, #8] + 1523 0020 FFF7FEFF bl NVIC_DecodePriority + 396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 1524 .loc 1 396 1 is_stmt 1 + 1525 0024 00BF nop + 1526 0026 1037 adds r7, r7, #16 + 1527 .cfi_def_cfa_offset 8 + 1528 0028 BD46 mov sp, r7 + 1529 .cfi_def_cfa_register 13 + 1530 @ sp needed + 1531 002a 80BD pop {r7, pc} + 1532 .cfi_endproc + 1533 .LFE140: + 1535 .section .text.HAL_NVIC_SetPendingIRQ,"ax",%progbits + 1536 .align 1 + 1537 .global HAL_NVIC_SetPendingIRQ + 1538 .syntax unified + 1539 .thumb + 1540 .thumb_func + 1542 HAL_NVIC_SetPendingIRQ: + 1543 .LFB141: + 397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** + 399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Sets Pending bit of an external interrupt. + 400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param IRQn External interrupt number + 401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration + 402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI + 403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval None + 404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) + 406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** { + 1544 .loc 1 406 1 + ARM GAS /tmp/ccwFmvCn.s page 86 + + + 1545 .cfi_startproc + 1546 @ args = 0, pretend = 0, frame = 8 + 1547 @ frame_needed = 1, uses_anonymous_args = 0 + 1548 0000 80B5 push {r7, lr} + 1549 .cfi_def_cfa_offset 8 + 1550 .cfi_offset 7, -8 + 1551 .cfi_offset 14, -4 + 1552 0002 82B0 sub sp, sp, #8 + 1553 .cfi_def_cfa_offset 16 + 1554 0004 00AF add r7, sp, #0 + 1555 .cfi_def_cfa_register 7 + 1556 0006 0346 mov r3, r0 + 1557 0008 FB71 strb r3, [r7, #7] + 407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Set interrupt pending */ + 408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** NVIC_SetPendingIRQ(IRQn); + 1558 .loc 1 408 3 + 1559 000a 97F90730 ldrsb r3, [r7, #7] + 1560 000e 1846 mov r0, r3 + 1561 0010 FFF7FEFF bl __NVIC_SetPendingIRQ + 409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 1562 .loc 1 409 1 + 1563 0014 00BF nop + 1564 0016 0837 adds r7, r7, #8 + 1565 .cfi_def_cfa_offset 8 + 1566 0018 BD46 mov sp, r7 + 1567 .cfi_def_cfa_register 13 + 1568 @ sp needed + 1569 001a 80BD pop {r7, pc} + 1570 .cfi_endproc + 1571 .LFE141: + 1573 .section .text.HAL_NVIC_GetPendingIRQ,"ax",%progbits + 1574 .align 1 + 1575 .global HAL_NVIC_GetPendingIRQ + 1576 .syntax unified + 1577 .thumb + 1578 .thumb_func + 1580 HAL_NVIC_GetPendingIRQ: + 1581 .LFB142: + 410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** + 412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Gets Pending Interrupt (reads the pending register in the NVIC + 413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * and returns the pending bit for the specified interrupt). + 414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param IRQn External interrupt number + 415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration + 416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI + 417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval status: - 0 Interrupt status is not pending. + 418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * - 1 Interrupt status is pending. + 419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) + 421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** { + 1582 .loc 1 421 1 + 1583 .cfi_startproc + 1584 @ args = 0, pretend = 0, frame = 8 + 1585 @ frame_needed = 1, uses_anonymous_args = 0 + 1586 0000 80B5 push {r7, lr} + 1587 .cfi_def_cfa_offset 8 + 1588 .cfi_offset 7, -8 + ARM GAS /tmp/ccwFmvCn.s page 87 + + + 1589 .cfi_offset 14, -4 + 1590 0002 82B0 sub sp, sp, #8 + 1591 .cfi_def_cfa_offset 16 + 1592 0004 00AF add r7, sp, #0 + 1593 .cfi_def_cfa_register 7 + 1594 0006 0346 mov r3, r0 + 1595 0008 FB71 strb r3, [r7, #7] + 422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Return 1 if pending else 0U */ + 423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** return NVIC_GetPendingIRQ(IRQn); + 1596 .loc 1 423 10 + 1597 000a 97F90730 ldrsb r3, [r7, #7] + 1598 000e 1846 mov r0, r3 + 1599 0010 FFF7FEFF bl __NVIC_GetPendingIRQ + 1600 0014 0346 mov r3, r0 + 424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 1601 .loc 1 424 1 + 1602 0016 1846 mov r0, r3 + 1603 0018 0837 adds r7, r7, #8 + 1604 .cfi_def_cfa_offset 8 + 1605 001a BD46 mov sp, r7 + 1606 .cfi_def_cfa_register 13 + 1607 @ sp needed + 1608 001c 80BD pop {r7, pc} + 1609 .cfi_endproc + 1610 .LFE142: + 1612 .section .text.HAL_NVIC_ClearPendingIRQ,"ax",%progbits + 1613 .align 1 + 1614 .global HAL_NVIC_ClearPendingIRQ + 1615 .syntax unified + 1616 .thumb + 1617 .thumb_func + 1619 HAL_NVIC_ClearPendingIRQ: + 1620 .LFB143: + 425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** + 427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Clears the pending bit of an external interrupt. + 428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param IRQn External interrupt number + 429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration + 430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI + 431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval None + 432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) + 434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** { + 1621 .loc 1 434 1 + 1622 .cfi_startproc + 1623 @ args = 0, pretend = 0, frame = 8 + 1624 @ frame_needed = 1, uses_anonymous_args = 0 + 1625 0000 80B5 push {r7, lr} + 1626 .cfi_def_cfa_offset 8 + 1627 .cfi_offset 7, -8 + 1628 .cfi_offset 14, -4 + 1629 0002 82B0 sub sp, sp, #8 + 1630 .cfi_def_cfa_offset 16 + 1631 0004 00AF add r7, sp, #0 + 1632 .cfi_def_cfa_register 7 + 1633 0006 0346 mov r3, r0 + 1634 0008 FB71 strb r3, [r7, #7] + ARM GAS /tmp/ccwFmvCn.s page 88 + + + 435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Clear pending interrupt */ + 436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** NVIC_ClearPendingIRQ(IRQn); + 1635 .loc 1 436 3 + 1636 000a 97F90730 ldrsb r3, [r7, #7] + 1637 000e 1846 mov r0, r3 + 1638 0010 FFF7FEFF bl __NVIC_ClearPendingIRQ + 437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 1639 .loc 1 437 1 + 1640 0014 00BF nop + 1641 0016 0837 adds r7, r7, #8 + 1642 .cfi_def_cfa_offset 8 + 1643 0018 BD46 mov sp, r7 + 1644 .cfi_def_cfa_register 13 + 1645 @ sp needed + 1646 001a 80BD pop {r7, pc} + 1647 .cfi_endproc + 1648 .LFE143: + 1650 .section .text.HAL_NVIC_GetActive,"ax",%progbits + 1651 .align 1 + 1652 .global HAL_NVIC_GetActive + 1653 .syntax unified + 1654 .thumb + 1655 .thumb_func + 1657 HAL_NVIC_GetActive: + 1658 .LFB144: + 438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** + 440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit). + 441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param IRQn External interrupt number + 442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * This parameter can be an enumerator of IRQn_Type enumeration + 443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSI + 444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval status: - 0 Interrupt status is not pending. + 445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * - 1 Interrupt status is pending. + 446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) + 448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** { + 1659 .loc 1 448 1 + 1660 .cfi_startproc + 1661 @ args = 0, pretend = 0, frame = 8 + 1662 @ frame_needed = 1, uses_anonymous_args = 0 + 1663 0000 80B5 push {r7, lr} + 1664 .cfi_def_cfa_offset 8 + 1665 .cfi_offset 7, -8 + 1666 .cfi_offset 14, -4 + 1667 0002 82B0 sub sp, sp, #8 + 1668 .cfi_def_cfa_offset 16 + 1669 0004 00AF add r7, sp, #0 + 1670 .cfi_def_cfa_register 7 + 1671 0006 0346 mov r3, r0 + 1672 0008 FB71 strb r3, [r7, #7] + 449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Return 1 if active else 0U */ + 450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** return NVIC_GetActive(IRQn); + 1673 .loc 1 450 10 + 1674 000a 97F90730 ldrsb r3, [r7, #7] + 1675 000e 1846 mov r0, r3 + 1676 0010 FFF7FEFF bl __NVIC_GetActive + 1677 0014 0346 mov r3, r0 + ARM GAS /tmp/ccwFmvCn.s page 89 + + + 451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 1678 .loc 1 451 1 + 1679 0016 1846 mov r0, r3 + 1680 0018 0837 adds r7, r7, #8 + 1681 .cfi_def_cfa_offset 8 + 1682 001a BD46 mov sp, r7 + 1683 .cfi_def_cfa_register 13 + 1684 @ sp needed + 1685 001c 80BD pop {r7, pc} + 1686 .cfi_endproc + 1687 .LFE144: + 1689 .section .text.HAL_SYSTICK_CLKSourceConfig,"ax",%progbits + 1690 .align 1 + 1691 .global HAL_SYSTICK_CLKSourceConfig + 1692 .syntax unified + 1693 .thumb + 1694 .thumb_func + 1696 HAL_SYSTICK_CLKSourceConfig: + 1697 .LFB145: + 452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** + 454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief Configures the SysTick clock source. + 455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @param CLKSource specifies the SysTick clock source. + 456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * This parameter can be one of the following values: + 457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock + 458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. + 459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval None + 460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) + 462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** { + 1698 .loc 1 462 1 + 1699 .cfi_startproc + 1700 @ args = 0, pretend = 0, frame = 8 + 1701 @ frame_needed = 1, uses_anonymous_args = 0 + 1702 @ link register save eliminated. + 1703 0000 80B4 push {r7} + 1704 .cfi_def_cfa_offset 4 + 1705 .cfi_offset 7, -4 + 1706 0002 83B0 sub sp, sp, #12 + 1707 .cfi_def_cfa_offset 16 + 1708 0004 00AF add r7, sp, #0 + 1709 .cfi_def_cfa_register 7 + 1710 0006 7860 str r0, [r7, #4] + 463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* Check the parameters */ + 464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); + 465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** if (CLKSource == SYSTICK_CLKSOURCE_HCLK) + 1711 .loc 1 465 6 + 1712 0008 7B68 ldr r3, [r7, #4] + 1713 000a 042B cmp r3, #4 + 1714 000c 06D1 bne .L94 + 466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** { + 467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; + 1715 .loc 1 467 12 + 1716 000e 094B ldr r3, .L97 + 1717 0010 1B68 ldr r3, [r3] + 1718 0012 084A ldr r2, .L97 + 1719 .loc 1 467 19 + ARM GAS /tmp/ccwFmvCn.s page 90 + + + 1720 0014 43F00403 orr r3, r3, #4 + 1721 0018 1360 str r3, [r2] + 468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** else + 470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** { + 471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; + 472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 1722 .loc 1 473 1 + 1723 001a 05E0 b .L96 + 1724 .L94: + 471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 1725 .loc 1 471 12 + 1726 001c 054B ldr r3, .L97 + 1727 001e 1B68 ldr r3, [r3] + 1728 0020 044A ldr r2, .L97 + 471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 1729 .loc 1 471 19 + 1730 0022 23F00403 bic r3, r3, #4 + 1731 0026 1360 str r3, [r2] + 1732 .L96: + 1733 .loc 1 473 1 + 1734 0028 00BF nop + 1735 002a 0C37 adds r7, r7, #12 + 1736 .cfi_def_cfa_offset 4 + 1737 002c BD46 mov sp, r7 + 1738 .cfi_def_cfa_register 13 + 1739 @ sp needed + 1740 002e 5DF8047B ldr r7, [sp], #4 + 1741 .cfi_restore 7 + 1742 .cfi_def_cfa_offset 0 + 1743 0032 7047 bx lr + 1744 .L98: + 1745 .align 2 + 1746 .L97: + 1747 0034 10E000E0 .word -536813552 + 1748 .cfi_endproc + 1749 .LFE145: + 1751 .section .text.HAL_SYSTICK_IRQHandler,"ax",%progbits + 1752 .align 1 + 1753 .global HAL_SYSTICK_IRQHandler + 1754 .syntax unified + 1755 .thumb + 1756 .thumb_func + 1758 HAL_SYSTICK_IRQHandler: + 1759 .LFB146: + 474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** + 476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief This function handles SYSTICK interrupt request. + 477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval None + 478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** void HAL_SYSTICK_IRQHandler(void) + 480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** { + 1760 .loc 1 480 1 + 1761 .cfi_startproc + 1762 @ args = 0, pretend = 0, frame = 0 + 1763 @ frame_needed = 1, uses_anonymous_args = 0 + ARM GAS /tmp/ccwFmvCn.s page 91 + + + 1764 0000 80B5 push {r7, lr} + 1765 .cfi_def_cfa_offset 8 + 1766 .cfi_offset 7, -8 + 1767 .cfi_offset 14, -4 + 1768 0002 00AF add r7, sp, #0 + 1769 .cfi_def_cfa_register 7 + 481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** HAL_SYSTICK_Callback(); + 1770 .loc 1 481 3 + 1771 0004 FFF7FEFF bl HAL_SYSTICK_Callback + 482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 1772 .loc 1 482 1 + 1773 0008 00BF nop + 1774 000a 80BD pop {r7, pc} + 1775 .cfi_endproc + 1776 .LFE146: + 1778 .section .text.HAL_SYSTICK_Callback,"ax",%progbits + 1779 .align 1 + 1780 .weak HAL_SYSTICK_Callback + 1781 .syntax unified + 1782 .thumb + 1783 .thumb_func + 1785 HAL_SYSTICK_Callback: + 1786 .LFB147: + 483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** + 484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /** + 485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @brief SYSTICK callback. + 486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** * @retval None + 487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** __weak void HAL_SYSTICK_Callback(void) + 489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** { + 1787 .loc 1 489 1 + 1788 .cfi_startproc + 1789 @ args = 0, pretend = 0, frame = 0 + 1790 @ frame_needed = 1, uses_anonymous_args = 0 + 1791 @ link register save eliminated. + 1792 0000 80B4 push {r7} + 1793 .cfi_def_cfa_offset 4 + 1794 .cfi_offset 7, -4 + 1795 0002 00AF add r7, sp, #0 + 1796 .cfi_def_cfa_register 7 + 490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** /* NOTE : This function Should not be modified, when the callback is needed, + 491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** the HAL_SYSTICK_Callback could be implemented in the user file + 492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** */ + 493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_cortex.c **** } + 1797 .loc 1 493 1 + 1798 0004 00BF nop + 1799 0006 BD46 mov sp, r7 + 1800 .cfi_def_cfa_register 13 + 1801 @ sp needed + 1802 0008 5DF8047B ldr r7, [sp], #4 + 1803 .cfi_restore 7 + 1804 .cfi_def_cfa_offset 0 + 1805 000c 7047 bx lr + 1806 .cfi_endproc + 1807 .LFE147: + 1809 .text + 1810 .Letext0: + ARM GAS /tmp/ccwFmvCn.s page 92 + + + 1811 .file 4 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + 1812 .file 5 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 1813 .file 6 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 1814 .file 7 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h" + 1815 .file 8 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h" + ARM GAS /tmp/ccwFmvCn.s page 93 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f3xx_hal_cortex.c + /tmp/ccwFmvCn.s:21 .text.__NVIC_SetPriorityGrouping:00000000 $t + /tmp/ccwFmvCn.s:26 .text.__NVIC_SetPriorityGrouping:00000000 __NVIC_SetPriorityGrouping + /tmp/ccwFmvCn.s:85 .text.__NVIC_SetPriorityGrouping:00000044 $d + /tmp/ccwFmvCn.s:90 .text.__NVIC_GetPriorityGrouping:00000000 $t + /tmp/ccwFmvCn.s:95 .text.__NVIC_GetPriorityGrouping:00000000 __NVIC_GetPriorityGrouping + /tmp/ccwFmvCn.s:125 .text.__NVIC_GetPriorityGrouping:00000018 $d + /tmp/ccwFmvCn.s:130 .text.__NVIC_EnableIRQ:00000000 $t + /tmp/ccwFmvCn.s:135 .text.__NVIC_EnableIRQ:00000000 __NVIC_EnableIRQ + /tmp/ccwFmvCn.s:184 .text.__NVIC_EnableIRQ:00000038 $d + /tmp/ccwFmvCn.s:189 .text.__NVIC_DisableIRQ:00000000 $t + /tmp/ccwFmvCn.s:194 .text.__NVIC_DisableIRQ:00000000 __NVIC_DisableIRQ + /tmp/ccwFmvCn.s:271 .text.__NVIC_DisableIRQ:00000044 $d + /tmp/ccwFmvCn.s:276 .text.__NVIC_GetPendingIRQ:00000000 $t + /tmp/ccwFmvCn.s:281 .text.__NVIC_GetPendingIRQ:00000000 __NVIC_GetPendingIRQ + /tmp/ccwFmvCn.s:336 .text.__NVIC_GetPendingIRQ:00000040 $d + /tmp/ccwFmvCn.s:341 .text.__NVIC_SetPendingIRQ:00000000 $t + /tmp/ccwFmvCn.s:346 .text.__NVIC_SetPendingIRQ:00000000 __NVIC_SetPendingIRQ + /tmp/ccwFmvCn.s:396 .text.__NVIC_SetPendingIRQ:00000038 $d + /tmp/ccwFmvCn.s:401 .text.__NVIC_ClearPendingIRQ:00000000 $t + /tmp/ccwFmvCn.s:406 .text.__NVIC_ClearPendingIRQ:00000000 __NVIC_ClearPendingIRQ + /tmp/ccwFmvCn.s:456 .text.__NVIC_ClearPendingIRQ:00000038 $d + /tmp/ccwFmvCn.s:461 .text.__NVIC_GetActive:00000000 $t + /tmp/ccwFmvCn.s:466 .text.__NVIC_GetActive:00000000 __NVIC_GetActive + /tmp/ccwFmvCn.s:521 .text.__NVIC_GetActive:00000040 $d + /tmp/ccwFmvCn.s:526 .text.__NVIC_SetPriority:00000000 $t + /tmp/ccwFmvCn.s:531 .text.__NVIC_SetPriority:00000000 __NVIC_SetPriority + /tmp/ccwFmvCn.s:599 .text.__NVIC_SetPriority:0000004c $d + /tmp/ccwFmvCn.s:605 .text.__NVIC_GetPriority:00000000 $t + /tmp/ccwFmvCn.s:610 .text.__NVIC_GetPriority:00000000 __NVIC_GetPriority + /tmp/ccwFmvCn.s:672 .text.__NVIC_GetPriority:00000048 $d + /tmp/ccwFmvCn.s:678 .text.NVIC_EncodePriority:00000000 $t + /tmp/ccwFmvCn.s:683 .text.NVIC_EncodePriority:00000000 NVIC_EncodePriority + /tmp/ccwFmvCn.s:762 .text.NVIC_DecodePriority:00000000 $t + /tmp/ccwFmvCn.s:767 .text.NVIC_DecodePriority:00000000 NVIC_DecodePriority + /tmp/ccwFmvCn.s:851 .text.__NVIC_SystemReset:00000000 $t + /tmp/ccwFmvCn.s:856 .text.__NVIC_SystemReset:00000000 __NVIC_SystemReset + /tmp/ccwFmvCn.s:918 .text.__NVIC_SystemReset:00000024 $d + /tmp/ccwFmvCn.s:924 .text.SysTick_Config:00000000 $t + /tmp/ccwFmvCn.s:929 .text.SysTick_Config:00000000 SysTick_Config + /tmp/ccwFmvCn.s:989 .text.SysTick_Config:00000040 $d + /tmp/ccwFmvCn.s:994 .text.HAL_NVIC_SetPriorityGrouping:00000000 $t + /tmp/ccwFmvCn.s:1000 .text.HAL_NVIC_SetPriorityGrouping:00000000 HAL_NVIC_SetPriorityGrouping + /tmp/ccwFmvCn.s:1030 .text.HAL_NVIC_SetPriority:00000000 $t + /tmp/ccwFmvCn.s:1036 .text.HAL_NVIC_SetPriority:00000000 HAL_NVIC_SetPriority + /tmp/ccwFmvCn.s:1083 .text.HAL_NVIC_EnableIRQ:00000000 $t + /tmp/ccwFmvCn.s:1089 .text.HAL_NVIC_EnableIRQ:00000000 HAL_NVIC_EnableIRQ + /tmp/ccwFmvCn.s:1121 .text.HAL_NVIC_DisableIRQ:00000000 $t + /tmp/ccwFmvCn.s:1127 .text.HAL_NVIC_DisableIRQ:00000000 HAL_NVIC_DisableIRQ + /tmp/ccwFmvCn.s:1159 .text.HAL_NVIC_SystemReset:00000000 $t + /tmp/ccwFmvCn.s:1165 .text.HAL_NVIC_SystemReset:00000000 HAL_NVIC_SystemReset + /tmp/ccwFmvCn.s:1183 .text.HAL_SYSTICK_Config:00000000 $t + /tmp/ccwFmvCn.s:1189 .text.HAL_SYSTICK_Config:00000000 HAL_SYSTICK_Config + /tmp/ccwFmvCn.s:1220 .text.HAL_MPU_Disable:00000000 $t + /tmp/ccwFmvCn.s:1226 .text.HAL_MPU_Disable:00000000 HAL_MPU_Disable + /tmp/ccwFmvCn.s:1262 .text.HAL_MPU_Disable:00000020 $d + ARM GAS /tmp/ccwFmvCn.s page 94 + + + /tmp/ccwFmvCn.s:1268 .text.HAL_MPU_Enable:00000000 $t + /tmp/ccwFmvCn.s:1274 .text.HAL_MPU_Enable:00000000 HAL_MPU_Enable + /tmp/ccwFmvCn.s:1317 .text.HAL_MPU_Enable:0000002c $d + /tmp/ccwFmvCn.s:1323 .text.HAL_MPU_ConfigRegion:00000000 $t + /tmp/ccwFmvCn.s:1329 .text.HAL_MPU_ConfigRegion:00000000 HAL_MPU_ConfigRegion + /tmp/ccwFmvCn.s:1457 .text.HAL_MPU_ConfigRegion:00000084 $d + /tmp/ccwFmvCn.s:1462 .text.HAL_NVIC_GetPriorityGrouping:00000000 $t + /tmp/ccwFmvCn.s:1468 .text.HAL_NVIC_GetPriorityGrouping:00000000 HAL_NVIC_GetPriorityGrouping + /tmp/ccwFmvCn.s:1490 .text.HAL_NVIC_GetPriority:00000000 $t + /tmp/ccwFmvCn.s:1496 .text.HAL_NVIC_GetPriority:00000000 HAL_NVIC_GetPriority + /tmp/ccwFmvCn.s:1536 .text.HAL_NVIC_SetPendingIRQ:00000000 $t + /tmp/ccwFmvCn.s:1542 .text.HAL_NVIC_SetPendingIRQ:00000000 HAL_NVIC_SetPendingIRQ + /tmp/ccwFmvCn.s:1574 .text.HAL_NVIC_GetPendingIRQ:00000000 $t + /tmp/ccwFmvCn.s:1580 .text.HAL_NVIC_GetPendingIRQ:00000000 HAL_NVIC_GetPendingIRQ + /tmp/ccwFmvCn.s:1613 .text.HAL_NVIC_ClearPendingIRQ:00000000 $t + /tmp/ccwFmvCn.s:1619 .text.HAL_NVIC_ClearPendingIRQ:00000000 HAL_NVIC_ClearPendingIRQ + /tmp/ccwFmvCn.s:1651 .text.HAL_NVIC_GetActive:00000000 $t + /tmp/ccwFmvCn.s:1657 .text.HAL_NVIC_GetActive:00000000 HAL_NVIC_GetActive + /tmp/ccwFmvCn.s:1690 .text.HAL_SYSTICK_CLKSourceConfig:00000000 $t + /tmp/ccwFmvCn.s:1696 .text.HAL_SYSTICK_CLKSourceConfig:00000000 HAL_SYSTICK_CLKSourceConfig + /tmp/ccwFmvCn.s:1747 .text.HAL_SYSTICK_CLKSourceConfig:00000034 $d + /tmp/ccwFmvCn.s:1752 .text.HAL_SYSTICK_IRQHandler:00000000 $t + /tmp/ccwFmvCn.s:1758 .text.HAL_SYSTICK_IRQHandler:00000000 HAL_SYSTICK_IRQHandler + /tmp/ccwFmvCn.s:1785 .text.HAL_SYSTICK_Callback:00000000 HAL_SYSTICK_Callback + /tmp/ccwFmvCn.s:1779 .text.HAL_SYSTICK_Callback:00000000 $t + +NO UNDEFINED SYMBOLS diff --git a/Software/build/stm32f3xx_hal_cortex.o b/Software/build/stm32f3xx_hal_cortex.o new file mode 100644 index 0000000..cf70b75 Binary files /dev/null and b/Software/build/stm32f3xx_hal_cortex.o differ diff --git a/Software/build/stm32f3xx_hal_dma.d b/Software/build/stm32f3xx_hal_dma.d new file mode 100644 index 0000000..d566e3c --- /dev/null +++ b/Software/build/stm32f3xx_hal_dma.d @@ -0,0 +1,62 @@ +build/stm32f3xx_hal_dma.o: \ + Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + Core/Inc/stm32f3xx_hal_conf.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h: diff --git a/Software/build/stm32f3xx_hal_dma.lst b/Software/build/stm32f3xx_hal_dma.lst new file mode 100644 index 0000000..94584cf --- /dev/null +++ b/Software/build/stm32f3xx_hal_dma.lst @@ -0,0 +1,2797 @@ +ARM GAS /tmp/ccDI3rYs.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 6 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "stm32f3xx_hal_dma.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c" + 20 .section .text.HAL_DMA_Init,"ax",%progbits + 21 .align 1 + 22 .global HAL_DMA_Init + 23 .syntax unified + 24 .thumb + 25 .thumb_func + 27 HAL_DMA_Init: + 28 .LFB130: + 1:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** + 2:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** ****************************************************************************** + 3:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @file stm32f3xx_hal_dma.c + 4:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @author MCD Application Team + 5:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @brief DMA HAL module driver. + 6:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * + 7:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * This file provides firmware functions to manage the following + 8:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * functionalities of the Direct Memory Access (DMA) peripheral: + 9:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * + Initialization and de-initialization functions + 10:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * + IO operation functions + 11:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * + Peripheral State and errors functions + 12:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** @verbatim + 13:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** ============================================================================== + 14:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** ##### How to use this driver ##### + 15:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** ============================================================================== + 16:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** [..] + 17:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** (#) Enable and configure the peripheral to be connected to the DMA Channel + 18:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** (except for internal SRAM / FLASH memories: no initialization is + 19:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** necessary). Please refer to Reference manual for connection between peripherals + 20:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** and DMA requests . + 21:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 22:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** (#) For a given Channel, program the required configuration through the following parameters: + 23:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** Transfer Direction, Source and Destination data formats, + 24:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** Circular or Normal mode, Channel Priority level, Source and Destination Increment mode, + 25:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** using HAL_DMA_Init() function. + 26:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 27:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of er + 28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** detection. + 29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** (#) Use HAL_DMA_Abort() function to abort the current transfer + ARM GAS /tmp/ccDI3rYs.s page 2 + + + 31:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 32:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. + 33:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** *** Polling mode IO operation *** + 34:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** ================================= + 35:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** [..] + 36:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source + 37:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** address and destination address and the Length of data to be transferred + 38:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this + 39:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** case a fixed Timeout can be configured by User depending from his application. + 40:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 41:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** *** Interrupt mode IO operation *** + 42:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** =================================== + 43:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** [..] + 44:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() + 45:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() + 46:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of + 47:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** Source address and destination address and the Length of data to be transferred. + 48:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** In this case the DMA interrupt is configured + 49:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** (+) Use HAL_DMA_Channel_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine + 50:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can + 51:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** add his own function by customization of function pointer XferCpltCallback and + 52:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** XferErrorCallback (i.e a member of DMA handle structure). + 53:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 54:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** *** DMA HAL driver macros list *** + 55:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** ============================================= + 56:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** [..] + 57:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** Below the list of most used macros in DMA HAL driver. + 58:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 59:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** [..] + 60:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** (@) You can refer to the DMA HAL driver header file for more useful macros + 61:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 62:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** @endverbatim + 63:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** ****************************************************************************** + 64:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @attention + 65:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * + 66:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * Copyright (c) 2016 STMicroelectronics. + 67:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * All rights reserved. + 68:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * + 69:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * This software is licensed under terms that can be found in the LICENSE file in + 70:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * the root directory of this software component. + 71:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 72:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * + 73:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** ****************************************************************************** + 74:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 75:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 76:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Includes ------------------------------------------------------------------*/ + 77:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** #include "stm32f3xx_hal.h" + 78:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 79:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** @addtogroup STM32F3xx_HAL_Driver + 80:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @{ + 81:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 82:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 83:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** @defgroup DMA DMA + 84:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @brief DMA HAL module driver + 85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @{ + 86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + ARM GAS /tmp/ccDI3rYs.s page 3 + + + 88:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** #ifdef HAL_DMA_MODULE_ENABLED + 89:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 90:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Private typedef -----------------------------------------------------------*/ + 91:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Private define ------------------------------------------------------------*/ + 92:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Private macro -------------------------------------------------------------*/ + 93:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Private variables ---------------------------------------------------------*/ + 94:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Private function prototypes -----------------------------------------------*/ + 95:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** @defgroup DMA_Private_Functions DMA Private Functions + 96:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @{ + 97:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 98:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32 + 99:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma); + 100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** + 101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @} + 102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Exported functions ---------------------------------------------------------*/ + 105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** @defgroup DMA_Exported_Functions DMA Exported Functions + 107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @{ + 108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions + 111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @brief Initialization and de-initialization functions + 112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * + 113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** @verbatim + 114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** =============================================================================== + 115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** ##### Initialization and de-initialization functions ##### + 116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** =============================================================================== + 117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** [..] + 118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** This section provides functions allowing to initialize the DMA Channel source + 119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** and destination addresses, incrementation and data sizes, transfer direction, + 120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** circular/normal mode selection, memory-to-memory mode selection and Channel priority value. + 121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** [..] + 122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** The HAL_DMA_Init() function follows the DMA configuration procedures as described in + 123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** reference manual. + 124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** @endverbatim + 126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @{ + 127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** + 130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @brief Initialize the DMA according to the specified + 131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * parameters in the DMA_InitTypeDef and initialize the associated handle. + 132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + 133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * the configuration information for the specified DMA Channel. + 134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @retval HAL status + 135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) + 137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 29 .loc 1 137 1 + 30 .cfi_startproc + 31 @ args = 0, pretend = 0, frame = 16 + 32 @ frame_needed = 1, uses_anonymous_args = 0 + 33 0000 80B5 push {r7, lr} + 34 .cfi_def_cfa_offset 8 + 35 .cfi_offset 7, -8 + ARM GAS /tmp/ccDI3rYs.s page 4 + + + 36 .cfi_offset 14, -4 + 37 0002 84B0 sub sp, sp, #16 + 38 .cfi_def_cfa_offset 24 + 39 0004 00AF add r7, sp, #0 + 40 .cfi_def_cfa_register 7 + 41 0006 7860 str r0, [r7, #4] + 138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** uint32_t tmp = 0U; + 42 .loc 1 138 12 + 43 0008 0023 movs r3, #0 + 44 000a FB60 str r3, [r7, #12] + 139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Check the DMA handle allocation */ + 141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if(NULL == hdma) + 45 .loc 1 141 5 + 46 000c 7B68 ldr r3, [r7, #4] + 47 000e 002B cmp r3, #0 + 48 0010 01D1 bne .L2 + 142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** return HAL_ERROR; + 49 .loc 1 143 12 + 50 0012 0123 movs r3, #1 + 51 0014 37E0 b .L3 + 52 .L2: + 144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Check the parameters */ + 147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + 148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); + 149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); + 150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); + 151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); + 152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); + 153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** assert_param(IS_DMA_MODE(hdma->Init.Mode)); + 154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); + 155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Change DMA peripheral state */ + 157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_BUSY; + 53 .loc 1 157 15 + 54 0016 7B68 ldr r3, [r7, #4] + 55 0018 0222 movs r2, #2 + 56 001a 83F82120 strb r2, [r3, #33] + 158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Get the CR register value */ + 160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** tmp = hdma->Instance->CCR; + 57 .loc 1 160 13 + 58 001e 7B68 ldr r3, [r7, #4] + 59 0020 1B68 ldr r3, [r3] + 60 .loc 1 160 7 + 61 0022 1B68 ldr r3, [r3] + 62 0024 FB60 str r3, [r7, #12] + 161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */ + 163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ + 63 .loc 1 163 7 + 64 0026 FB68 ldr r3, [r7, #12] + 65 0028 23F47F53 bic r3, r3, #16320 + 66 002c 23F03003 bic r3, r3, #48 + ARM GAS /tmp/ccDI3rYs.s page 5 + + + 67 0030 FB60 str r3, [r7, #12] + 164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ + 165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** DMA_CCR_DIR)); + 166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Prepare the DMA Channel configuration */ + 168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** tmp |= hdma->Init.Direction | + 68 .loc 1 168 21 + 69 0032 7B68 ldr r3, [r7, #4] + 70 0034 5A68 ldr r2, [r3, #4] + 169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Init.PeriphInc | hdma->Init.MemInc | + 71 .loc 1 169 21 + 72 0036 7B68 ldr r3, [r7, #4] + 73 0038 9B68 ldr r3, [r3, #8] + 168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Init.PeriphInc | hdma->Init.MemInc | + 74 .loc 1 168 39 + 75 003a 1A43 orrs r2, r2, r3 + 76 .loc 1 169 54 + 77 003c 7B68 ldr r3, [r7, #4] + 78 003e DB68 ldr r3, [r3, #12] + 79 .loc 1 169 42 + 80 0040 1A43 orrs r2, r2, r3 + 170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + 81 .loc 1 170 21 + 82 0042 7B68 ldr r3, [r7, #4] + 83 0044 1B69 ldr r3, [r3, #16] + 169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Init.PeriphInc | hdma->Init.MemInc | + 84 .loc 1 169 72 + 85 0046 1A43 orrs r2, r2, r3 + 86 .loc 1 170 54 + 87 0048 7B68 ldr r3, [r7, #4] + 88 004a 5B69 ldr r3, [r3, #20] + 89 .loc 1 170 42 + 90 004c 1A43 orrs r2, r2, r3 + 171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Init.Mode | hdma->Init.Priority; + 91 .loc 1 171 21 + 92 004e 7B68 ldr r3, [r7, #4] + 93 0050 9B69 ldr r3, [r3, #24] + 170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + 94 .loc 1 170 72 + 95 0052 1A43 orrs r2, r2, r3 + 96 .loc 1 171 54 + 97 0054 7B68 ldr r3, [r7, #4] + 98 0056 DB69 ldr r3, [r3, #28] + 99 .loc 1 171 42 + 100 0058 1343 orrs r3, r3, r2 + 168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Init.PeriphInc | hdma->Init.MemInc | + 101 .loc 1 168 7 + 102 005a FA68 ldr r2, [r7, #12] + 103 005c 1343 orrs r3, r3, r2 + 104 005e FB60 str r3, [r7, #12] + 172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Write to DMA Channel CR register */ + 174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CCR = tmp; + 105 .loc 1 174 7 + 106 0060 7B68 ldr r3, [r7, #4] + 107 0062 1B68 ldr r3, [r3] + 108 .loc 1 174 23 + ARM GAS /tmp/ccDI3rYs.s page 6 + + + 109 0064 FA68 ldr r2, [r7, #12] + 110 0066 1A60 str r2, [r3] + 175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Initialize DmaBaseAddress and ChannelIndex parameters used + 177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ + 178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** DMA_CalcBaseAndBitshift(hdma); + 111 .loc 1 178 3 + 112 0068 7868 ldr r0, [r7, #4] + 113 006a FFF7FEFF bl DMA_CalcBaseAndBitshift + 179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Initialise the error code */ + 181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_NONE; + 114 .loc 1 181 19 + 115 006e 7B68 ldr r3, [r7, #4] + 116 0070 0022 movs r2, #0 + 117 0072 9A63 str r2, [r3, #56] + 182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Initialize the DMA state*/ + 184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_READY; + 118 .loc 1 184 15 + 119 0074 7B68 ldr r3, [r7, #4] + 120 0076 0122 movs r2, #1 + 121 0078 83F82120 strb r2, [r3, #33] + 185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Allocate lock resource and initialize it */ + 187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Lock = HAL_UNLOCKED; + 122 .loc 1 187 14 + 123 007c 7B68 ldr r3, [r7, #4] + 124 007e 0022 movs r2, #0 + 125 0080 83F82020 strb r2, [r3, #32] + 188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** return HAL_OK; + 126 .loc 1 189 10 + 127 0084 0023 movs r3, #0 + 128 .L3: + 190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 129 .loc 1 190 1 + 130 0086 1846 mov r0, r3 + 131 0088 1037 adds r7, r7, #16 + 132 .cfi_def_cfa_offset 8 + 133 008a BD46 mov sp, r7 + 134 .cfi_def_cfa_register 13 + 135 @ sp needed + 136 008c 80BD pop {r7, pc} + 137 .cfi_endproc + 138 .LFE130: + 140 .section .text.HAL_DMA_DeInit,"ax",%progbits + 141 .align 1 + 142 .global HAL_DMA_DeInit + 143 .syntax unified + 144 .thumb + 145 .thumb_func + 147 HAL_DMA_DeInit: + 148 .LFB131: + 191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** + 193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @brief DeInitialize the DMA peripheral + ARM GAS /tmp/ccDI3rYs.s page 7 + + + 194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains + 195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * the configuration information for the specified DMA Channel. + 196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @retval HAL status + 197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) + 199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 149 .loc 1 199 1 + 150 .cfi_startproc + 151 @ args = 0, pretend = 0, frame = 8 + 152 @ frame_needed = 1, uses_anonymous_args = 0 + 153 0000 80B5 push {r7, lr} + 154 .cfi_def_cfa_offset 8 + 155 .cfi_offset 7, -8 + 156 .cfi_offset 14, -4 + 157 0002 82B0 sub sp, sp, #8 + 158 .cfi_def_cfa_offset 16 + 159 0004 00AF add r7, sp, #0 + 160 .cfi_def_cfa_register 7 + 161 0006 7860 str r0, [r7, #4] + 200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Check the DMA handle allocation */ + 201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if(NULL == hdma) + 162 .loc 1 201 5 + 163 0008 7B68 ldr r3, [r7, #4] + 164 000a 002B cmp r3, #0 + 165 000c 01D1 bne .L5 + 202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** return HAL_ERROR; + 166 .loc 1 203 12 + 167 000e 0123 movs r3, #1 + 168 0010 3AE0 b .L6 + 169 .L5: + 204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Check the parameters */ + 207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + 208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Disable the selected DMA Channelx */ + 210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CCR &= ~DMA_CCR_EN; + 170 .loc 1 210 7 + 171 0012 7B68 ldr r3, [r7, #4] + 172 0014 1B68 ldr r3, [r3] + 173 .loc 1 210 17 + 174 0016 1A68 ldr r2, [r3] + 175 .loc 1 210 7 + 176 0018 7B68 ldr r3, [r7, #4] + 177 001a 1B68 ldr r3, [r3] + 178 .loc 1 210 23 + 179 001c 22F00102 bic r2, r2, #1 + 180 0020 1A60 str r2, [r3] + 211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Reset DMA Channel control register */ + 213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CCR = 0U; + 181 .loc 1 213 7 + 182 0022 7B68 ldr r3, [r7, #4] + 183 0024 1B68 ldr r3, [r3] + 184 .loc 1 213 24 + 185 0026 0022 movs r2, #0 + ARM GAS /tmp/ccDI3rYs.s page 8 + + + 186 0028 1A60 str r2, [r3] + 214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Reset DMA Channel Number of Data to Transfer register */ + 216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CNDTR = 0U; + 187 .loc 1 216 7 + 188 002a 7B68 ldr r3, [r7, #4] + 189 002c 1B68 ldr r3, [r3] + 190 .loc 1 216 25 + 191 002e 0022 movs r2, #0 + 192 0030 5A60 str r2, [r3, #4] + 217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Reset DMA Channel peripheral address register */ + 219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CPAR = 0U; + 193 .loc 1 219 7 + 194 0032 7B68 ldr r3, [r7, #4] + 195 0034 1B68 ldr r3, [r3] + 196 .loc 1 219 25 + 197 0036 0022 movs r2, #0 + 198 0038 9A60 str r2, [r3, #8] + 220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Reset DMA Channel memory address register */ + 222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CMAR = 0U; + 199 .loc 1 222 7 + 200 003a 7B68 ldr r3, [r7, #4] + 201 003c 1B68 ldr r3, [r3] + 202 .loc 1 222 24 + 203 003e 0022 movs r2, #0 + 204 0040 DA60 str r2, [r3, #12] + 223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Get DMA Base Address */ + 225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** DMA_CalcBaseAndBitshift(hdma); + 205 .loc 1 225 3 + 206 0042 7868 ldr r0, [r7, #4] + 207 0044 FFF7FEFF bl DMA_CalcBaseAndBitshift + 226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Clear all flags */ + 228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex; + 208 .loc 1 228 52 + 209 0048 7B68 ldr r3, [r7, #4] + 210 004a 1A6C ldr r2, [r3, #64] + 211 .loc 1 228 7 + 212 004c 7B68 ldr r3, [r7, #4] + 213 004e DB6B ldr r3, [r3, #60] + 214 .loc 1 228 45 + 215 0050 0121 movs r1, #1 + 216 0052 01FA02F2 lsl r2, r1, r2 + 217 .loc 1 228 30 + 218 0056 5A60 str r2, [r3, #4] + 229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Clean callbacks */ + 231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferCpltCallback = NULL; + 219 .loc 1 231 26 + 220 0058 7B68 ldr r3, [r7, #4] + 221 005a 0022 movs r2, #0 + 222 005c 9A62 str r2, [r3, #40] + 232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferHalfCpltCallback = NULL; + 223 .loc 1 232 30 + ARM GAS /tmp/ccDI3rYs.s page 9 + + + 224 005e 7B68 ldr r3, [r7, #4] + 225 0060 0022 movs r2, #0 + 226 0062 DA62 str r2, [r3, #44] + 233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferErrorCallback = NULL; + 227 .loc 1 233 27 + 228 0064 7B68 ldr r3, [r7, #4] + 229 0066 0022 movs r2, #0 + 230 0068 1A63 str r2, [r3, #48] + 234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferAbortCallback = NULL; + 231 .loc 1 234 27 + 232 006a 7B68 ldr r3, [r7, #4] + 233 006c 0022 movs r2, #0 + 234 006e 5A63 str r2, [r3, #52] + 235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Reset the error code */ + 237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_NONE; + 235 .loc 1 237 19 + 236 0070 7B68 ldr r3, [r7, #4] + 237 0072 0022 movs r2, #0 + 238 0074 9A63 str r2, [r3, #56] + 238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Reset the DMA state */ + 240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_RESET; + 239 .loc 1 240 15 + 240 0076 7B68 ldr r3, [r7, #4] + 241 0078 0022 movs r2, #0 + 242 007a 83F82120 strb r2, [r3, #33] + 241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Release Lock */ + 243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 243 .loc 1 243 3 + 244 007e 7B68 ldr r3, [r7, #4] + 245 0080 0022 movs r2, #0 + 246 0082 83F82020 strb r2, [r3, #32] + 244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** return HAL_OK; + 247 .loc 1 245 10 + 248 0086 0023 movs r3, #0 + 249 .L6: + 246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 250 .loc 1 246 1 + 251 0088 1846 mov r0, r3 + 252 008a 0837 adds r7, r7, #8 + 253 .cfi_def_cfa_offset 8 + 254 008c BD46 mov sp, r7 + 255 .cfi_def_cfa_register 13 + 256 @ sp needed + 257 008e 80BD pop {r7, pc} + 258 .cfi_endproc + 259 .LFE131: + 261 .section .text.HAL_DMA_Start,"ax",%progbits + 262 .align 1 + 263 .global HAL_DMA_Start + 264 .syntax unified + 265 .thumb + 266 .thumb_func + 268 HAL_DMA_Start: + ARM GAS /tmp/ccDI3rYs.s page 10 + + + 269 .LFB132: + 247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** + 249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @} + 250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions + 253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @brief I/O operation functions + 254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * + 255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** @verbatim + 256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** =============================================================================== + 257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** ##### IO operation functions ##### + 258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** =============================================================================== + 259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** [..] This section provides functions allowing to: + 260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** (+) Configure the source, destination address and data length and Start DMA transfer + 261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** (+) Configure the source, destination address and data length and + 262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** Start DMA transfer with interrupt + 263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** (+) Abort DMA transfer + 264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** (+) Poll for transfer complete + 265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** (+) Handle DMA interrupt request + 266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** @endverbatim + 268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @{ + 269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** + 272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @brief Start the DMA Transfer. + 273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + 274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * the configuration information for the specified DMA Channel. + 275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param SrcAddress The source memory Buffer address + 276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param DstAddress The destination memory Buffer address + 277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param DataLength The length of data to be transferred from source to destination + 278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @retval HAL status + 279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, + 281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 270 .loc 1 281 1 + 271 .cfi_startproc + 272 @ args = 0, pretend = 0, frame = 24 + 273 @ frame_needed = 1, uses_anonymous_args = 0 + 274 0000 80B5 push {r7, lr} + 275 .cfi_def_cfa_offset 8 + 276 .cfi_offset 7, -8 + 277 .cfi_offset 14, -4 + 278 0002 86B0 sub sp, sp, #24 + 279 .cfi_def_cfa_offset 32 + 280 0004 00AF add r7, sp, #0 + 281 .cfi_def_cfa_register 7 + 282 0006 F860 str r0, [r7, #12] + 283 0008 B960 str r1, [r7, #8] + 284 000a 7A60 str r2, [r7, #4] + 285 000c 3B60 str r3, [r7] + 282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 286 .loc 1 282 20 + 287 000e 0023 movs r3, #0 + 288 0010 FB75 strb r3, [r7, #23] + 283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + ARM GAS /tmp/ccDI3rYs.s page 11 + + + 284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Check the parameters */ + 285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + 286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Process locked */ + 288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** __HAL_LOCK(hdma); + 289 .loc 1 288 3 + 290 0012 FB68 ldr r3, [r7, #12] + 291 0014 93F82030 ldrb r3, [r3, #32] @ zero_extendqisi2 + 292 0018 012B cmp r3, #1 + 293 001a 01D1 bne .L8 + 294 .loc 1 288 3 is_stmt 0 discriminator 1 + 295 001c 0223 movs r3, #2 + 296 .loc 1 288 3 + 297 001e 2DE0 b .L9 + 298 .L8: + 299 .loc 1 288 3 discriminator 2 + 300 0020 FB68 ldr r3, [r7, #12] + 301 0022 0122 movs r2, #1 + 302 0024 83F82020 strb r2, [r3, #32] + 289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if(HAL_DMA_STATE_READY == hdma->State) + 303 .loc 1 290 33 is_stmt 1 + 304 0028 FB68 ldr r3, [r7, #12] + 305 002a 93F82130 ldrb r3, [r3, #33] @ zero_extendqisi2 + 306 .loc 1 290 5 + 307 002e 012B cmp r3, #1 + 308 0030 1DD1 bne .L10 + 291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Change DMA peripheral state */ + 293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_BUSY; + 309 .loc 1 293 16 + 310 0032 FB68 ldr r3, [r7, #12] + 311 0034 0222 movs r2, #2 + 312 0036 83F82120 strb r2, [r3, #33] + 294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_NONE; + 313 .loc 1 295 20 + 314 003a FB68 ldr r3, [r7, #12] + 315 003c 0022 movs r2, #0 + 316 003e 9A63 str r2, [r3, #56] + 296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Disable the peripheral */ + 298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CCR &= ~DMA_CCR_EN; + 317 .loc 1 298 8 + 318 0040 FB68 ldr r3, [r7, #12] + 319 0042 1B68 ldr r3, [r3] + 320 .loc 1 298 18 + 321 0044 1A68 ldr r2, [r3] + 322 .loc 1 298 8 + 323 0046 FB68 ldr r3, [r7, #12] + 324 0048 1B68 ldr r3, [r3] + 325 .loc 1 298 24 + 326 004a 22F00102 bic r2, r2, #1 + 327 004e 1A60 str r2, [r3] + 299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Configure the source, destination address and the data length */ + 301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + ARM GAS /tmp/ccDI3rYs.s page 12 + + + 328 .loc 1 301 4 + 329 0050 3B68 ldr r3, [r7] + 330 0052 7A68 ldr r2, [r7, #4] + 331 0054 B968 ldr r1, [r7, #8] + 332 0056 F868 ldr r0, [r7, #12] + 333 0058 FFF7FEFF bl DMA_SetConfig + 302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Enable the Peripheral */ + 304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CCR |= DMA_CCR_EN; + 334 .loc 1 304 8 + 335 005c FB68 ldr r3, [r7, #12] + 336 005e 1B68 ldr r3, [r3] + 337 .loc 1 304 18 + 338 0060 1A68 ldr r2, [r3] + 339 .loc 1 304 8 + 340 0062 FB68 ldr r3, [r7, #12] + 341 0064 1B68 ldr r3, [r3] + 342 .loc 1 304 24 + 343 0066 42F00102 orr r2, r2, #1 + 344 006a 1A60 str r2, [r3] + 345 006c 05E0 b .L11 + 346 .L10: + 305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** else + 307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Process Unlocked */ + 309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 347 .loc 1 309 4 + 348 006e FB68 ldr r3, [r7, #12] + 349 0070 0022 movs r2, #0 + 350 0072 83F82020 strb r2, [r3, #32] + 310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Remain BUSY */ + 312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** status = HAL_BUSY; + 351 .loc 1 312 11 + 352 0076 0223 movs r3, #2 + 353 0078 FB75 strb r3, [r7, #23] + 354 .L11: + 313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** return status; + 355 .loc 1 315 10 + 356 007a FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 357 .L9: + 316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 358 .loc 1 316 1 + 359 007c 1846 mov r0, r3 + 360 007e 1837 adds r7, r7, #24 + 361 .cfi_def_cfa_offset 8 + 362 0080 BD46 mov sp, r7 + 363 .cfi_def_cfa_register 13 + 364 @ sp needed + 365 0082 80BD pop {r7, pc} + 366 .cfi_endproc + 367 .LFE132: + 369 .section .text.HAL_DMA_Start_IT,"ax",%progbits + 370 .align 1 + ARM GAS /tmp/ccDI3rYs.s page 13 + + + 371 .global HAL_DMA_Start_IT + 372 .syntax unified + 373 .thumb + 374 .thumb_func + 376 HAL_DMA_Start_IT: + 377 .LFB133: + 317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** + 319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @brief Start the DMA Transfer with interrupt enabled. + 320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains + 321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * the configuration information for the specified DMA Channel. + 322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param SrcAddress The source memory Buffer address + 323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param DstAddress The destination memory Buffer address + 324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param DataLength The length of data to be transferred from source to destination + 325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @retval HAL status + 326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddres + 328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 378 .loc 1 328 1 + 379 .cfi_startproc + 380 @ args = 0, pretend = 0, frame = 24 + 381 @ frame_needed = 1, uses_anonymous_args = 0 + 382 0000 80B5 push {r7, lr} + 383 .cfi_def_cfa_offset 8 + 384 .cfi_offset 7, -8 + 385 .cfi_offset 14, -4 + 386 0002 86B0 sub sp, sp, #24 + 387 .cfi_def_cfa_offset 32 + 388 0004 00AF add r7, sp, #0 + 389 .cfi_def_cfa_register 7 + 390 0006 F860 str r0, [r7, #12] + 391 0008 B960 str r1, [r7, #8] + 392 000a 7A60 str r2, [r7, #4] + 393 000c 3B60 str r3, [r7] + 329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 394 .loc 1 329 20 + 395 000e 0023 movs r3, #0 + 396 0010 FB75 strb r3, [r7, #23] + 330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Check the parameters */ + 332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + 333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Process locked */ + 335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** __HAL_LOCK(hdma); + 397 .loc 1 335 3 + 398 0012 FB68 ldr r3, [r7, #12] + 399 0014 93F82030 ldrb r3, [r3, #32] @ zero_extendqisi2 + 400 0018 012B cmp r3, #1 + 401 001a 01D1 bne .L13 + 402 .loc 1 335 3 is_stmt 0 discriminator 1 + 403 001c 0223 movs r3, #2 + 404 .loc 1 335 3 + 405 001e 4AE0 b .L14 + 406 .L13: + 407 .loc 1 335 3 discriminator 2 + 408 0020 FB68 ldr r3, [r7, #12] + 409 0022 0122 movs r2, #1 + ARM GAS /tmp/ccDI3rYs.s page 14 + + + 410 0024 83F82020 strb r2, [r3, #32] + 336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if(HAL_DMA_STATE_READY == hdma->State) + 411 .loc 1 337 33 is_stmt 1 + 412 0028 FB68 ldr r3, [r7, #12] + 413 002a 93F82130 ldrb r3, [r3, #33] @ zero_extendqisi2 + 414 .loc 1 337 5 + 415 002e 012B cmp r3, #1 + 416 0030 3AD1 bne .L15 + 338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Change DMA peripheral state */ + 340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_BUSY; + 417 .loc 1 340 16 + 418 0032 FB68 ldr r3, [r7, #12] + 419 0034 0222 movs r2, #2 + 420 0036 83F82120 strb r2, [r3, #33] + 341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_NONE; + 421 .loc 1 342 20 + 422 003a FB68 ldr r3, [r7, #12] + 423 003c 0022 movs r2, #0 + 424 003e 9A63 str r2, [r3, #56] + 343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Disable the peripheral */ + 345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CCR &= ~DMA_CCR_EN; + 425 .loc 1 345 8 + 426 0040 FB68 ldr r3, [r7, #12] + 427 0042 1B68 ldr r3, [r3] + 428 .loc 1 345 18 + 429 0044 1A68 ldr r2, [r3] + 430 .loc 1 345 8 + 431 0046 FB68 ldr r3, [r7, #12] + 432 0048 1B68 ldr r3, [r3] + 433 .loc 1 345 24 + 434 004a 22F00102 bic r2, r2, #1 + 435 004e 1A60 str r2, [r3] + 346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Configure the source, destination address and the data length */ + 348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + 436 .loc 1 348 4 + 437 0050 3B68 ldr r3, [r7] + 438 0052 7A68 ldr r2, [r7, #4] + 439 0054 B968 ldr r1, [r7, #8] + 440 0056 F868 ldr r0, [r7, #12] + 441 0058 FFF7FEFF bl DMA_SetConfig + 349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Enable the transfer complete, & transfer error interrupts */ + 351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Half transfer interrupt is optional: enable it only if associated callback is available */ + 352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if(NULL != hdma->XferHalfCpltCallback ) + 442 .loc 1 352 20 + 443 005c FB68 ldr r3, [r7, #12] + 444 005e DB6A ldr r3, [r3, #44] + 445 .loc 1 352 7 + 446 0060 002B cmp r3, #0 + 447 0062 08D0 beq .L16 + 353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); + ARM GAS /tmp/ccDI3rYs.s page 15 + + + 448 .loc 1 354 11 + 449 0064 FB68 ldr r3, [r7, #12] + 450 0066 1B68 ldr r3, [r3] + 451 .loc 1 354 21 + 452 0068 1A68 ldr r2, [r3] + 453 .loc 1 354 11 + 454 006a FB68 ldr r3, [r7, #12] + 455 006c 1B68 ldr r3, [r3] + 456 .loc 1 354 27 + 457 006e 42F00E02 orr r2, r2, #14 + 458 0072 1A60 str r2, [r3] + 459 0074 0FE0 b .L17 + 460 .L16: + 355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** else + 357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CCR |= (DMA_IT_TC | DMA_IT_TE); + 461 .loc 1 358 9 + 462 0076 FB68 ldr r3, [r7, #12] + 463 0078 1B68 ldr r3, [r3] + 464 .loc 1 358 19 + 465 007a 1A68 ldr r2, [r3] + 466 .loc 1 358 9 + 467 007c FB68 ldr r3, [r7, #12] + 468 007e 1B68 ldr r3, [r3] + 469 .loc 1 358 25 + 470 0080 42F00A02 orr r2, r2, #10 + 471 0084 1A60 str r2, [r3] + 359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CCR &= ~DMA_IT_HT; + 472 .loc 1 359 9 + 473 0086 FB68 ldr r3, [r7, #12] + 474 0088 1B68 ldr r3, [r3] + 475 .loc 1 359 19 + 476 008a 1A68 ldr r2, [r3] + 477 .loc 1 359 9 + 478 008c FB68 ldr r3, [r7, #12] + 479 008e 1B68 ldr r3, [r3] + 480 .loc 1 359 25 + 481 0090 22F00402 bic r2, r2, #4 + 482 0094 1A60 str r2, [r3] + 483 .L17: + 360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Enable the Peripheral */ + 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CCR |= DMA_CCR_EN; + 484 .loc 1 363 8 + 485 0096 FB68 ldr r3, [r7, #12] + 486 0098 1B68 ldr r3, [r3] + 487 .loc 1 363 18 + 488 009a 1A68 ldr r2, [r3] + 489 .loc 1 363 8 + 490 009c FB68 ldr r3, [r7, #12] + 491 009e 1B68 ldr r3, [r3] + 492 .loc 1 363 24 + 493 00a0 42F00102 orr r2, r2, #1 + 494 00a4 1A60 str r2, [r3] + 495 00a6 05E0 b .L18 + ARM GAS /tmp/ccDI3rYs.s page 16 + + + 496 .L15: + 364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** else + 366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Process Unlocked */ + 368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 497 .loc 1 368 5 + 498 00a8 FB68 ldr r3, [r7, #12] + 499 00aa 0022 movs r2, #0 + 500 00ac 83F82020 strb r2, [r3, #32] + 369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Remain BUSY */ + 371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** status = HAL_BUSY; + 501 .loc 1 371 12 + 502 00b0 0223 movs r3, #2 + 503 00b2 FB75 strb r3, [r7, #23] + 504 .L18: + 372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** return status; + 505 .loc 1 374 10 + 506 00b4 FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 507 .L14: + 375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 508 .loc 1 375 1 + 509 00b6 1846 mov r0, r3 + 510 00b8 1837 adds r7, r7, #24 + 511 .cfi_def_cfa_offset 8 + 512 00ba BD46 mov sp, r7 + 513 .cfi_def_cfa_register 13 + 514 @ sp needed + 515 00bc 80BD pop {r7, pc} + 516 .cfi_endproc + 517 .LFE133: + 519 .section .text.HAL_DMA_Abort,"ax",%progbits + 520 .align 1 + 521 .global HAL_DMA_Abort + 522 .syntax unified + 523 .thumb + 524 .thumb_func + 526 HAL_DMA_Abort: + 527 .LFB134: + 376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** + 378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @brief Abort the DMA Transfer. + 379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + 380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * the configuration information for the specified DMA Channel. + 381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @retval HAL status + 382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) + 384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 528 .loc 1 384 1 + 529 .cfi_startproc + 530 @ args = 0, pretend = 0, frame = 8 + 531 @ frame_needed = 1, uses_anonymous_args = 0 + 532 @ link register save eliminated. + 533 0000 80B4 push {r7} + ARM GAS /tmp/ccDI3rYs.s page 17 + + + 534 .cfi_def_cfa_offset 4 + 535 .cfi_offset 7, -4 + 536 0002 83B0 sub sp, sp, #12 + 537 .cfi_def_cfa_offset 16 + 538 0004 00AF add r7, sp, #0 + 539 .cfi_def_cfa_register 7 + 540 0006 7860 str r0, [r7, #4] + 385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if(hdma->State != HAL_DMA_STATE_BUSY) + 541 .loc 1 385 10 + 542 0008 7B68 ldr r3, [r7, #4] + 543 000a 93F82130 ldrb r3, [r3, #33] @ zero_extendqisi2 + 544 .loc 1 385 5 + 545 000e 022B cmp r3, #2 + 546 0010 08D0 beq .L20 + 386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* no transfer ongoing */ + 388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + 547 .loc 1 388 21 + 548 0012 7B68 ldr r3, [r7, #4] + 549 0014 0422 movs r2, #4 + 550 0016 9A63 str r2, [r3, #56] + 389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Process Unlocked */ + 391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 551 .loc 1 391 5 + 552 0018 7B68 ldr r3, [r7, #4] + 553 001a 0022 movs r2, #0 + 554 001c 83F82020 strb r2, [r3, #32] + 392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** return HAL_ERROR; + 555 .loc 1 393 12 + 556 0020 0123 movs r3, #1 + 557 0022 20E0 b .L21 + 558 .L20: + 394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** else + 396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Disable DMA IT */ + 398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); + 559 .loc 1 398 10 + 560 0024 7B68 ldr r3, [r7, #4] + 561 0026 1B68 ldr r3, [r3] + 562 .loc 1 398 20 + 563 0028 1A68 ldr r2, [r3] + 564 .loc 1 398 10 + 565 002a 7B68 ldr r3, [r7, #4] + 566 002c 1B68 ldr r3, [r3] + 567 .loc 1 398 26 + 568 002e 22F00E02 bic r2, r2, #14 + 569 0032 1A60 str r2, [r3] + 399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Disable the channel */ + 401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CCR &= ~DMA_CCR_EN; + 570 .loc 1 401 9 + 571 0034 7B68 ldr r3, [r7, #4] + 572 0036 1B68 ldr r3, [r3] + 573 .loc 1 401 19 + ARM GAS /tmp/ccDI3rYs.s page 18 + + + 574 0038 1A68 ldr r2, [r3] + 575 .loc 1 401 9 + 576 003a 7B68 ldr r3, [r7, #4] + 577 003c 1B68 ldr r3, [r3] + 578 .loc 1 401 25 + 579 003e 22F00102 bic r2, r2, #1 + 580 0042 1A60 str r2, [r3] + 402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Clear all flags */ + 404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex); + 581 .loc 1 404 55 + 582 0044 7B68 ldr r3, [r7, #4] + 583 0046 1A6C ldr r2, [r3, #64] + 584 .loc 1 404 9 + 585 0048 7B68 ldr r3, [r7, #4] + 586 004a DB6B ldr r3, [r3, #60] + 587 .loc 1 404 48 + 588 004c 0121 movs r1, #1 + 589 004e 01FA02F2 lsl r2, r1, r2 + 590 .loc 1 404 32 + 591 0052 5A60 str r2, [r3, #4] + 405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Change the DMA state*/ + 407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_READY; + 592 .loc 1 407 15 + 593 0054 7B68 ldr r3, [r7, #4] + 594 0056 0122 movs r2, #1 + 595 0058 83F82120 strb r2, [r3, #33] + 408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Process Unlocked */ + 410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 596 .loc 1 410 3 + 597 005c 7B68 ldr r3, [r7, #4] + 598 005e 0022 movs r2, #0 + 599 0060 83F82020 strb r2, [r3, #32] + 411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** return HAL_OK; + 600 .loc 1 412 10 + 601 0064 0023 movs r3, #0 + 602 .L21: + 413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 603 .loc 1 413 1 + 604 0066 1846 mov r0, r3 + 605 0068 0C37 adds r7, r7, #12 + 606 .cfi_def_cfa_offset 4 + 607 006a BD46 mov sp, r7 + 608 .cfi_def_cfa_register 13 + 609 @ sp needed + 610 006c 5DF8047B ldr r7, [sp], #4 + 611 .cfi_restore 7 + 612 .cfi_def_cfa_offset 0 + 613 0070 7047 bx lr + 614 .cfi_endproc + 615 .LFE134: + 617 .section .text.HAL_DMA_Abort_IT,"ax",%progbits + 618 .align 1 + 619 .global HAL_DMA_Abort_IT + ARM GAS /tmp/ccDI3rYs.s page 19 + + + 620 .syntax unified + 621 .thumb + 622 .thumb_func + 624 HAL_DMA_Abort_IT: + 625 .LFB135: + 414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** + 416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @brief Abort the DMA Transfer in Interrupt mode. + 417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + 418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * the configuration information for the specified DMA Stream. + 419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @retval HAL status + 420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) + 422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 626 .loc 1 422 1 + 627 .cfi_startproc + 628 @ args = 0, pretend = 0, frame = 16 + 629 @ frame_needed = 1, uses_anonymous_args = 0 + 630 0000 80B5 push {r7, lr} + 631 .cfi_def_cfa_offset 8 + 632 .cfi_offset 7, -8 + 633 .cfi_offset 14, -4 + 634 0002 84B0 sub sp, sp, #16 + 635 .cfi_def_cfa_offset 24 + 636 0004 00AF add r7, sp, #0 + 637 .cfi_def_cfa_register 7 + 638 0006 7860 str r0, [r7, #4] + 423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 639 .loc 1 423 21 + 640 0008 0023 movs r3, #0 + 641 000a FB73 strb r3, [r7, #15] + 424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if(HAL_DMA_STATE_BUSY != hdma->State) + 642 .loc 1 425 32 + 643 000c 7B68 ldr r3, [r7, #4] + 644 000e 93F82130 ldrb r3, [r3, #33] @ zero_extendqisi2 + 645 .loc 1 425 5 + 646 0012 022B cmp r3, #2 + 647 0014 05D0 beq .L23 + 426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* no transfer ongoing */ + 428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + 648 .loc 1 428 21 + 649 0016 7B68 ldr r3, [r7, #4] + 650 0018 0422 movs r2, #4 + 651 001a 9A63 str r2, [r3, #56] + 429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** status = HAL_ERROR; + 652 .loc 1 430 12 + 653 001c 0123 movs r3, #1 + 654 001e FB73 strb r3, [r7, #15] + 655 0020 27E0 b .L24 + 656 .L23: + 431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** else + 433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + ARM GAS /tmp/ccDI3rYs.s page 20 + + + 435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Disable DMA IT */ + 436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); + 657 .loc 1 436 9 + 658 0022 7B68 ldr r3, [r7, #4] + 659 0024 1B68 ldr r3, [r3] + 660 .loc 1 436 19 + 661 0026 1A68 ldr r2, [r3] + 662 .loc 1 436 9 + 663 0028 7B68 ldr r3, [r7, #4] + 664 002a 1B68 ldr r3, [r3] + 665 .loc 1 436 25 + 666 002c 22F00E02 bic r2, r2, #14 + 667 0030 1A60 str r2, [r3] + 437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Disable the channel */ + 439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CCR &= ~DMA_CCR_EN; + 668 .loc 1 439 9 + 669 0032 7B68 ldr r3, [r7, #4] + 670 0034 1B68 ldr r3, [r3] + 671 .loc 1 439 19 + 672 0036 1A68 ldr r2, [r3] + 673 .loc 1 439 9 + 674 0038 7B68 ldr r3, [r7, #4] + 675 003a 1B68 ldr r3, [r3] + 676 .loc 1 439 25 + 677 003c 22F00102 bic r2, r2, #1 + 678 0040 1A60 str r2, [r3] + 440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Clear all flags */ + 442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex; + 679 .loc 1 442 54 + 680 0042 7B68 ldr r3, [r7, #4] + 681 0044 1A6C ldr r2, [r3, #64] + 682 .loc 1 442 9 + 683 0046 7B68 ldr r3, [r7, #4] + 684 0048 DB6B ldr r3, [r3, #60] + 685 .loc 1 442 47 + 686 004a 0121 movs r1, #1 + 687 004c 01FA02F2 lsl r2, r1, r2 + 688 .loc 1 442 32 + 689 0050 5A60 str r2, [r3, #4] + 443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Change the DMA state */ + 445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_READY; + 690 .loc 1 445 17 + 691 0052 7B68 ldr r3, [r7, #4] + 692 0054 0122 movs r2, #1 + 693 0056 83F82120 strb r2, [r3, #33] + 446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Process Unlocked */ + 448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 694 .loc 1 448 5 + 695 005a 7B68 ldr r3, [r7, #4] + 696 005c 0022 movs r2, #0 + 697 005e 83F82020 strb r2, [r3, #32] + 449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Call User Abort callback */ + ARM GAS /tmp/ccDI3rYs.s page 21 + + + 451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if(hdma->XferAbortCallback != NULL) + 698 .loc 1 451 12 + 699 0062 7B68 ldr r3, [r7, #4] + 700 0064 5B6B ldr r3, [r3, #52] + 701 .loc 1 451 7 + 702 0066 002B cmp r3, #0 + 703 0068 03D0 beq .L24 + 452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferAbortCallback(hdma); + 704 .loc 1 453 11 + 705 006a 7B68 ldr r3, [r7, #4] + 706 006c 5B6B ldr r3, [r3, #52] + 707 .loc 1 453 7 + 708 006e 7868 ldr r0, [r7, #4] + 709 0070 9847 blx r3 + 710 .LVL0: + 711 .L24: + 454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** return status; + 712 .loc 1 456 10 + 713 0072 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 714 .loc 1 457 1 + 715 0074 1846 mov r0, r3 + 716 0076 1037 adds r7, r7, #16 + 717 .cfi_def_cfa_offset 8 + 718 0078 BD46 mov sp, r7 + 719 .cfi_def_cfa_register 13 + 720 @ sp needed + 721 007a 80BD pop {r7, pc} + 722 .cfi_endproc + 723 .LFE135: + 725 .section .text.HAL_DMA_PollForTransfer,"ax",%progbits + 726 .align 1 + 727 .global HAL_DMA_PollForTransfer + 728 .syntax unified + 729 .thumb + 730 .thumb_func + 732 HAL_DMA_PollForTransfer: + 733 .LFB136: + 458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** + 460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @brief Polling for transfer complete. + 461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains + 462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * the configuration information for the specified DMA Channel. + 463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param CompleteLevel Specifies the DMA level complete. + 464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param Timeout Timeout duration. + 465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @retval HAL status + 466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t + 468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 734 .loc 1 468 1 + 735 .cfi_startproc + 736 @ args = 0, pretend = 0, frame = 24 + 737 @ frame_needed = 1, uses_anonymous_args = 0 + 738 0000 80B5 push {r7, lr} + ARM GAS /tmp/ccDI3rYs.s page 22 + + + 739 .cfi_def_cfa_offset 8 + 740 .cfi_offset 7, -8 + 741 .cfi_offset 14, -4 + 742 0002 86B0 sub sp, sp, #24 + 743 .cfi_def_cfa_offset 32 + 744 0004 00AF add r7, sp, #0 + 745 .cfi_def_cfa_register 7 + 746 0006 F860 str r0, [r7, #12] + 747 0008 B960 str r1, [r7, #8] + 748 000a 7A60 str r2, [r7, #4] + 469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** uint32_t temp; + 470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** uint32_t tickstart = 0U; + 749 .loc 1 470 12 + 750 000c 0023 movs r3, #0 + 751 000e 3B61 str r3, [r7, #16] + 471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if(HAL_DMA_STATE_BUSY != hdma->State) + 752 .loc 1 472 32 + 753 0010 FB68 ldr r3, [r7, #12] + 754 0012 93F82130 ldrb r3, [r3, #33] @ zero_extendqisi2 + 755 .loc 1 472 5 + 756 0016 022B cmp r3, #2 + 757 0018 08D0 beq .L27 + 473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* no transfer ongoing */ + 475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + 758 .loc 1 475 21 + 759 001a FB68 ldr r3, [r7, #12] + 760 001c 0422 movs r2, #4 + 761 001e 9A63 str r2, [r3, #56] + 476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 762 .loc 1 476 5 + 763 0020 FB68 ldr r3, [r7, #12] + 764 0022 0022 movs r2, #0 + 765 0024 83F82020 strb r2, [r3, #32] + 477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** return HAL_ERROR; + 766 .loc 1 477 12 + 767 0028 0123 movs r3, #1 + 768 002a 80E0 b .L28 + 769 .L27: + 478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Polling mode not supported in circular mode */ + 481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC)) + 770 .loc 1 481 21 + 771 002c FB68 ldr r3, [r7, #12] + 772 002e 1B68 ldr r3, [r3] + 773 .loc 1 481 31 + 774 0030 1B68 ldr r3, [r3] + 775 .loc 1 481 37 + 776 0032 03F02003 and r3, r3, #32 + 777 .loc 1 481 6 + 778 0036 002B cmp r3, #0 + 779 0038 05D0 beq .L29 + 482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + 780 .loc 1 483 21 + ARM GAS /tmp/ccDI3rYs.s page 23 + + + 781 003a FB68 ldr r3, [r7, #12] + 782 003c 4FF48072 mov r2, #256 + 783 0040 9A63 str r2, [r3, #56] + 484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** return HAL_ERROR; + 784 .loc 1 484 12 + 785 0042 0123 movs r3, #1 + 786 0044 73E0 b .L28 + 787 .L29: + 485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Get the level transfer complete flag */ + 488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if(HAL_DMA_FULL_TRANSFER == CompleteLevel) + 788 .loc 1 488 5 + 789 0046 BB68 ldr r3, [r7, #8] + 790 0048 002B cmp r3, #0 + 791 004a 06D1 bne .L30 + 489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Transfer Complete flag */ + 491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** temp = DMA_FLAG_TC1 << hdma->ChannelIndex; + 792 .loc 1 491 32 + 793 004c FB68 ldr r3, [r7, #12] + 794 004e 1B6C ldr r3, [r3, #64] + 795 .loc 1 491 10 + 796 0050 0222 movs r2, #2 + 797 0052 02FA03F3 lsl r3, r2, r3 + 798 0056 7B61 str r3, [r7, #20] + 799 0058 05E0 b .L31 + 800 .L30: + 492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** else + 494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Half Transfer Complete flag */ + 496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** temp = DMA_FLAG_HT1 << hdma->ChannelIndex; + 801 .loc 1 496 32 + 802 005a FB68 ldr r3, [r7, #12] + 803 005c 1B6C ldr r3, [r3, #64] + 804 .loc 1 496 10 + 805 005e 0422 movs r2, #4 + 806 0060 02FA03F3 lsl r3, r2, r3 + 807 0064 7B61 str r3, [r7, #20] + 808 .L31: + 497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Get tick */ + 500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** tickstart = HAL_GetTick(); + 809 .loc 1 500 15 + 810 0066 FFF7FEFF bl HAL_GetTick + 811 006a 3861 str r0, [r7, #16] + 501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** while(RESET == (hdma->DmaBaseAddress->ISR & temp)) + 812 .loc 1 502 8 + 813 006c 3BE0 b .L34 + 814 .L36: + 503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if(RESET != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << hdma->ChannelIndex))) + 815 .loc 1 504 22 + 816 006e FB68 ldr r3, [r7, #12] + ARM GAS /tmp/ccDI3rYs.s page 24 + + + 817 0070 DB6B ldr r3, [r3, #60] + 818 .loc 1 504 38 + 819 0072 1A68 ldr r2, [r3] + 820 .loc 1 504 67 + 821 0074 FB68 ldr r3, [r7, #12] + 822 0076 1B6C ldr r3, [r3, #64] + 823 .loc 1 504 60 + 824 0078 0821 movs r1, #8 + 825 007a 01FA03F3 lsl r3, r1, r3 + 826 .loc 1 504 44 + 827 007e 1340 ands r3, r3, r2 + 828 .loc 1 504 7 + 829 0080 002B cmp r3, #0 + 830 0082 14D0 beq .L33 + 505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* When a DMA transfer error occurs */ + 507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* A hardware clear of its EN bits is performed */ + 508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Clear all flags */ + 509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex; + 831 .loc 1 509 56 + 832 0084 FB68 ldr r3, [r7, #12] + 833 0086 1A6C ldr r2, [r3, #64] + 834 .loc 1 509 11 + 835 0088 FB68 ldr r3, [r7, #12] + 836 008a DB6B ldr r3, [r3, #60] + 837 .loc 1 509 49 + 838 008c 0121 movs r1, #1 + 839 008e 01FA02F2 lsl r2, r1, r2 + 840 .loc 1 509 34 + 841 0092 5A60 str r2, [r3, #4] + 510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Update error code */ + 512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_TE; + 842 .loc 1 512 23 + 843 0094 FB68 ldr r3, [r7, #12] + 844 0096 0122 movs r2, #1 + 845 0098 9A63 str r2, [r3, #56] + 513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Change the DMA state */ + 515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->State= HAL_DMA_STATE_READY; + 846 .loc 1 515 18 + 847 009a FB68 ldr r3, [r7, #12] + 848 009c 0122 movs r2, #1 + 849 009e 83F82120 strb r2, [r3, #33] + 516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Process Unlocked */ + 518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 850 .loc 1 518 7 + 851 00a2 FB68 ldr r3, [r7, #12] + 852 00a4 0022 movs r2, #0 + 853 00a6 83F82020 strb r2, [r3, #32] + 519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** return HAL_ERROR; + 854 .loc 1 520 14 + 855 00aa 0123 movs r3, #1 + 856 00ac 3FE0 b .L28 + 857 .L33: + ARM GAS /tmp/ccDI3rYs.s page 25 + + + 521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Check for the Timeout */ + 523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if(Timeout != HAL_MAX_DELAY) + 858 .loc 1 523 7 + 859 00ae 7B68 ldr r3, [r7, #4] + 860 00b0 B3F1FF3F cmp r3, #-1 + 861 00b4 17D0 beq .L34 + 524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + 862 .loc 1 525 9 + 863 00b6 7B68 ldr r3, [r7, #4] + 864 00b8 002B cmp r3, #0 + 865 00ba 07D0 beq .L35 + 866 .loc 1 525 31 discriminator 1 + 867 00bc FFF7FEFF bl HAL_GetTick + 868 00c0 0246 mov r2, r0 + 869 .loc 1 525 45 discriminator 1 + 870 00c2 3B69 ldr r3, [r7, #16] + 871 00c4 D31A subs r3, r2, r3 + 872 .loc 1 525 26 discriminator 1 + 873 00c6 7A68 ldr r2, [r7, #4] + 874 00c8 9A42 cmp r2, r3 + 875 00ca 0CD2 bcs .L34 + 876 .L35: + 526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Update error code */ + 528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + 877 .loc 1 528 25 + 878 00cc FB68 ldr r3, [r7, #12] + 879 00ce 2022 movs r2, #32 + 880 00d0 9A63 str r2, [r3, #56] + 529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Change the DMA state */ + 531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_READY; + 881 .loc 1 531 21 + 882 00d2 FB68 ldr r3, [r7, #12] + 883 00d4 0122 movs r2, #1 + 884 00d6 83F82120 strb r2, [r3, #33] + 532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Process Unlocked */ + 534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 885 .loc 1 534 9 + 886 00da FB68 ldr r3, [r7, #12] + 887 00dc 0022 movs r2, #0 + 888 00de 83F82020 strb r2, [r3, #32] + 535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** return HAL_ERROR; + 889 .loc 1 536 16 + 890 00e2 0123 movs r3, #1 + 891 00e4 23E0 b .L28 + 892 .L34: + 502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 893 .loc 1 502 23 + 894 00e6 FB68 ldr r3, [r7, #12] + 895 00e8 DB6B ldr r3, [r3, #60] + 502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 896 .loc 1 502 39 + ARM GAS /tmp/ccDI3rYs.s page 26 + + + 897 00ea 1A68 ldr r2, [r3] + 502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 898 .loc 1 502 45 + 899 00ec 7B69 ldr r3, [r7, #20] + 900 00ee 1340 ands r3, r3, r2 + 502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 901 .loc 1 502 15 + 902 00f0 002B cmp r3, #0 + 903 00f2 BCD0 beq .L36 + 537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if(HAL_DMA_FULL_TRANSFER == CompleteLevel) + 904 .loc 1 541 5 + 905 00f4 BB68 ldr r3, [r7, #8] + 906 00f6 002B cmp r3, #0 + 907 00f8 0CD1 bne .L37 + 542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Clear the transfer complete flag */ + 544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex; + 908 .loc 1 544 54 + 909 00fa FB68 ldr r3, [r7, #12] + 910 00fc 1A6C ldr r2, [r3, #64] + 911 .loc 1 544 9 + 912 00fe FB68 ldr r3, [r7, #12] + 913 0100 DB6B ldr r3, [r3, #60] + 914 .loc 1 544 47 + 915 0102 0221 movs r1, #2 + 916 0104 01FA02F2 lsl r2, r1, r2 + 917 .loc 1 544 32 + 918 0108 5A60 str r2, [r3, #4] + 545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* The selected Channelx EN bit is cleared (DMA is disabled and + 547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** all transfers are complete) */ + 548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_READY; + 919 .loc 1 548 17 + 920 010a FB68 ldr r3, [r7, #12] + 921 010c 0122 movs r2, #1 + 922 010e 83F82120 strb r2, [r3, #33] + 923 0112 07E0 b .L38 + 924 .L37: + 549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** else + 551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Clear the half transfer complete flag */ + 553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex; + 925 .loc 1 553 54 + 926 0114 FB68 ldr r3, [r7, #12] + 927 0116 1A6C ldr r2, [r3, #64] + 928 .loc 1 553 9 + 929 0118 FB68 ldr r3, [r7, #12] + 930 011a DB6B ldr r3, [r3, #60] + 931 .loc 1 553 47 + 932 011c 0421 movs r1, #4 + 933 011e 01FA02F2 lsl r2, r1, r2 + 934 .loc 1 553 32 + ARM GAS /tmp/ccDI3rYs.s page 27 + + + 935 0122 5A60 str r2, [r3, #4] + 936 .L38: + 554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Process unlocked */ + 557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 937 .loc 1 557 3 + 938 0124 FB68 ldr r3, [r7, #12] + 939 0126 0022 movs r2, #0 + 940 0128 83F82020 strb r2, [r3, #32] + 558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** return HAL_OK; + 941 .loc 1 559 10 + 942 012c 0023 movs r3, #0 + 943 .L28: + 560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 944 .loc 1 560 1 + 945 012e 1846 mov r0, r3 + 946 0130 1837 adds r7, r7, #24 + 947 .cfi_def_cfa_offset 8 + 948 0132 BD46 mov sp, r7 + 949 .cfi_def_cfa_register 13 + 950 @ sp needed + 951 0134 80BD pop {r7, pc} + 952 .cfi_endproc + 953 .LFE136: + 955 .section .text.HAL_DMA_IRQHandler,"ax",%progbits + 956 .align 1 + 957 .global HAL_DMA_IRQHandler + 958 .syntax unified + 959 .thumb + 960 .thumb_func + 962 HAL_DMA_IRQHandler: + 963 .LFB137: + 561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** + 563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @brief Handle DMA interrupt request. + 564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains + 565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * the configuration information for the specified DMA Channel. + 566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @retval None + 567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) + 569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 964 .loc 1 569 1 + 965 .cfi_startproc + 966 @ args = 0, pretend = 0, frame = 16 + 967 @ frame_needed = 1, uses_anonymous_args = 0 + 968 0000 80B5 push {r7, lr} + 969 .cfi_def_cfa_offset 8 + 970 .cfi_offset 7, -8 + 971 .cfi_offset 14, -4 + 972 0002 84B0 sub sp, sp, #16 + 973 .cfi_def_cfa_offset 24 + 974 0004 00AF add r7, sp, #0 + 975 .cfi_def_cfa_register 7 + 976 0006 7860 str r0, [r7, #4] + 570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** uint32_t flag_it = hdma->DmaBaseAddress->ISR; + ARM GAS /tmp/ccDI3rYs.s page 28 + + + 977 .loc 1 570 25 + 978 0008 7B68 ldr r3, [r7, #4] + 979 000a DB6B ldr r3, [r3, #60] + 980 .loc 1 570 11 + 981 000c 1B68 ldr r3, [r3] + 982 000e FB60 str r3, [r7, #12] + 571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** uint32_t source_it = hdma->Instance->CCR; + 983 .loc 1 571 28 + 984 0010 7B68 ldr r3, [r7, #4] + 985 0012 1B68 ldr r3, [r3] + 986 .loc 1 571 12 + 987 0014 1B68 ldr r3, [r3] + 988 0016 BB60 str r3, [r7, #8] + 572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Half Transfer Complete Interrupt management ******************************/ + 574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if ((RESET != (flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_ + 989 .loc 1 574 49 + 990 0018 7B68 ldr r3, [r7, #4] + 991 001a 1B6C ldr r3, [r3, #64] + 992 .loc 1 574 42 + 993 001c 0422 movs r2, #4 + 994 001e 9A40 lsls r2, r2, r3 + 995 .loc 1 574 26 + 996 0020 FB68 ldr r3, [r7, #12] + 997 0022 1340 ands r3, r3, r2 + 998 .loc 1 574 6 + 999 0024 002B cmp r3, #0 + 1000 0026 24D0 beq .L40 + 1001 .loc 1 574 91 discriminator 1 + 1002 0028 BB68 ldr r3, [r7, #8] + 1003 002a 03F00403 and r3, r3, #4 + 1004 .loc 1 574 67 discriminator 1 + 1005 002e 002B cmp r3, #0 + 1006 0030 1FD0 beq .L40 + 575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ + 577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + 1007 .loc 1 577 12 + 1008 0032 7B68 ldr r3, [r7, #4] + 1009 0034 1B68 ldr r3, [r3] + 1010 .loc 1 577 22 + 1011 0036 1B68 ldr r3, [r3] + 1012 .loc 1 577 28 + 1013 0038 03F02003 and r3, r3, #32 + 1014 .loc 1 577 6 + 1015 003c 002B cmp r3, #0 + 1016 003e 07D1 bne .L41 + 578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Disable the half transfer interrupt */ + 580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CCR &= ~DMA_IT_HT; + 1017 .loc 1 580 9 + 1018 0040 7B68 ldr r3, [r7, #4] + 1019 0042 1B68 ldr r3, [r3] + 1020 .loc 1 580 19 + 1021 0044 1A68 ldr r2, [r3] + 1022 .loc 1 580 9 + 1023 0046 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/ccDI3rYs.s page 29 + + + 1024 0048 1B68 ldr r3, [r3] + 1025 .loc 1 580 25 + 1026 004a 22F00402 bic r2, r2, #4 + 1027 004e 1A60 str r2, [r3] + 1028 .L41: + 581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Clear the half transfer complete flag */ + 584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->DmaBaseAddress->IFCR = DMA_FLAG_HT1 << hdma->ChannelIndex; + 1029 .loc 1 584 53 + 1030 0050 7B68 ldr r3, [r7, #4] + 1031 0052 1A6C ldr r2, [r3, #64] + 1032 .loc 1 584 8 + 1033 0054 7B68 ldr r3, [r7, #4] + 1034 0056 DB6B ldr r3, [r3, #60] + 1035 .loc 1 584 46 + 1036 0058 0421 movs r1, #4 + 1037 005a 01FA02F2 lsl r2, r1, r2 + 1038 .loc 1 584 31 + 1039 005e 5A60 str r2, [r3, #4] + 585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* DMA peripheral state is not updated in Half Transfer */ + 587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* State is updated only in Transfer Complete case */ + 588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if(hdma->XferHalfCpltCallback != NULL) + 1040 .loc 1 589 11 + 1041 0060 7B68 ldr r3, [r7, #4] + 1042 0062 DB6A ldr r3, [r3, #44] + 1043 .loc 1 589 6 + 1044 0064 002B cmp r3, #0 + 1045 0066 6AD0 beq .L43 + 590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Half transfer callback */ + 592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferHalfCpltCallback(hdma); + 1046 .loc 1 592 9 + 1047 0068 7B68 ldr r3, [r7, #4] + 1048 006a DB6A ldr r3, [r3, #44] + 1049 .loc 1 592 5 + 1050 006c 7868 ldr r0, [r7, #4] + 1051 006e 9847 blx r3 + 1052 .LVL1: + 589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 1053 .loc 1 589 6 + 1054 0070 65E0 b .L43 + 1055 .L40: + 593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Transfer Complete Interrupt management ***********************************/ + 597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** else if ((RESET != (flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex))) && (RESET != (source_it & DM + 1056 .loc 1 597 54 + 1057 0072 7B68 ldr r3, [r7, #4] + 1058 0074 1B6C ldr r3, [r3, #64] + 1059 .loc 1 597 47 + 1060 0076 0222 movs r2, #2 + 1061 0078 9A40 lsls r2, r2, r3 + 1062 .loc 1 597 31 + ARM GAS /tmp/ccDI3rYs.s page 30 + + + 1063 007a FB68 ldr r3, [r7, #12] + 1064 007c 1340 ands r3, r3, r2 + 1065 .loc 1 597 11 + 1066 007e 002B cmp r3, #0 + 1067 0080 2CD0 beq .L44 + 1068 .loc 1 597 96 discriminator 1 + 1069 0082 BB68 ldr r3, [r7, #8] + 1070 0084 03F00203 and r3, r3, #2 + 1071 .loc 1 597 72 discriminator 1 + 1072 0088 002B cmp r3, #0 + 1073 008a 27D0 beq .L44 + 598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + 1074 .loc 1 599 12 + 1075 008c 7B68 ldr r3, [r7, #4] + 1076 008e 1B68 ldr r3, [r3] + 1077 .loc 1 599 22 + 1078 0090 1B68 ldr r3, [r3] + 1079 .loc 1 599 28 + 1080 0092 03F02003 and r3, r3, #32 + 1081 .loc 1 599 6 + 1082 0096 002B cmp r3, #0 + 1083 0098 0BD1 bne .L45 + 600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Disable the transfer complete & transfer error interrupts */ + 602:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* if the DMA mode is not CIRCULAR */ + 603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_TE); + 1084 .loc 1 603 9 + 1085 009a 7B68 ldr r3, [r7, #4] + 1086 009c 1B68 ldr r3, [r3] + 1087 .loc 1 603 19 + 1088 009e 1A68 ldr r2, [r3] + 1089 .loc 1 603 9 + 1090 00a0 7B68 ldr r3, [r7, #4] + 1091 00a2 1B68 ldr r3, [r3] + 1092 .loc 1 603 25 + 1093 00a4 22F00A02 bic r2, r2, #10 + 1094 00a8 1A60 str r2, [r3] + 604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Change the DMA state */ + 606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_READY; + 1095 .loc 1 606 17 + 1096 00aa 7B68 ldr r3, [r7, #4] + 1097 00ac 0122 movs r2, #1 + 1098 00ae 83F82120 strb r2, [r3, #33] + 1099 .L45: + 607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Clear the transfer complete flag */ + 610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->DmaBaseAddress->IFCR = DMA_FLAG_TC1 << hdma->ChannelIndex; + 1100 .loc 1 610 53 + 1101 00b2 7B68 ldr r3, [r7, #4] + 1102 00b4 1A6C ldr r2, [r3, #64] + 1103 .loc 1 610 8 + 1104 00b6 7B68 ldr r3, [r7, #4] + 1105 00b8 DB6B ldr r3, [r3, #60] + 1106 .loc 1 610 46 + ARM GAS /tmp/ccDI3rYs.s page 31 + + + 1107 00ba 0221 movs r1, #2 + 1108 00bc 01FA02F2 lsl r2, r1, r2 + 1109 .loc 1 610 31 + 1110 00c0 5A60 str r2, [r3, #4] + 611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 612:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Process Unlocked */ + 613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 1111 .loc 1 613 4 + 1112 00c2 7B68 ldr r3, [r7, #4] + 1113 00c4 0022 movs r2, #0 + 1114 00c6 83F82020 strb r2, [r3, #32] + 614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if(hdma->XferCpltCallback != NULL) + 1115 .loc 1 615 11 + 1116 00ca 7B68 ldr r3, [r7, #4] + 1117 00cc 9B6A ldr r3, [r3, #40] + 1118 .loc 1 615 6 + 1119 00ce 002B cmp r3, #0 + 1120 00d0 35D0 beq .L43 + 616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Transfer complete callback */ + 618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferCpltCallback(hdma); + 1121 .loc 1 618 9 + 1122 00d2 7B68 ldr r3, [r7, #4] + 1123 00d4 9B6A ldr r3, [r3, #40] + 1124 .loc 1 618 5 + 1125 00d6 7868 ldr r0, [r7, #4] + 1126 00d8 9847 blx r3 + 1127 .LVL2: + 615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 1128 .loc 1 615 6 + 1129 00da 30E0 b .L43 + 1130 .L44: + 619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Transfer Error Interrupt management ***************************************/ + 623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & D + 1131 .loc 1 623 55 + 1132 00dc 7B68 ldr r3, [r7, #4] + 1133 00de 1B6C ldr r3, [r3, #64] + 1134 .loc 1 623 48 + 1135 00e0 0822 movs r2, #8 + 1136 00e2 9A40 lsls r2, r2, r3 + 1137 .loc 1 623 32 + 1138 00e4 FB68 ldr r3, [r7, #12] + 1139 00e6 1340 ands r3, r3, r2 + 1140 .loc 1 623 11 + 1141 00e8 002B cmp r3, #0 + 1142 00ea 28D0 beq .L47 + 1143 .loc 1 623 97 discriminator 1 + 1144 00ec BB68 ldr r3, [r7, #8] + 1145 00ee 03F00803 and r3, r3, #8 + 1146 .loc 1 623 73 discriminator 1 + 1147 00f2 002B cmp r3, #0 + 1148 00f4 23D0 beq .L47 + 624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + ARM GAS /tmp/ccDI3rYs.s page 32 + + + 625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* When a DMA transfer error occurs */ + 626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* A hardware clear of its EN bits is performed */ + 627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Then, disable all DMA interrupts */ + 628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE); + 1149 .loc 1 628 9 + 1150 00f6 7B68 ldr r3, [r7, #4] + 1151 00f8 1B68 ldr r3, [r3] + 1152 .loc 1 628 19 + 1153 00fa 1A68 ldr r2, [r3] + 1154 .loc 1 628 9 + 1155 00fc 7B68 ldr r3, [r7, #4] + 1156 00fe 1B68 ldr r3, [r3] + 1157 .loc 1 628 25 + 1158 0100 22F00E02 bic r2, r2, #14 + 1159 0104 1A60 str r2, [r3] + 629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Clear all flags */ + 631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex; + 1160 .loc 1 631 54 + 1161 0106 7B68 ldr r3, [r7, #4] + 1162 0108 1A6C ldr r2, [r3, #64] + 1163 .loc 1 631 9 + 1164 010a 7B68 ldr r3, [r7, #4] + 1165 010c DB6B ldr r3, [r3, #60] + 1166 .loc 1 631 47 + 1167 010e 0121 movs r1, #1 + 1168 0110 01FA02F2 lsl r2, r1, r2 + 1169 .loc 1 631 32 + 1170 0114 5A60 str r2, [r3, #4] + 632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Update error code */ + 634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->ErrorCode = HAL_DMA_ERROR_TE; + 1171 .loc 1 634 21 + 1172 0116 7B68 ldr r3, [r7, #4] + 1173 0118 0122 movs r2, #1 + 1174 011a 9A63 str r2, [r3, #56] + 635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Change the DMA state */ + 637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->State = HAL_DMA_STATE_READY; + 1175 .loc 1 637 17 + 1176 011c 7B68 ldr r3, [r7, #4] + 1177 011e 0122 movs r2, #1 + 1178 0120 83F82120 strb r2, [r3, #33] + 638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Process Unlocked */ + 640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 1179 .loc 1 640 5 + 1180 0124 7B68 ldr r3, [r7, #4] + 1181 0126 0022 movs r2, #0 + 1182 0128 83F82020 strb r2, [r3, #32] + 641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 642:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if(hdma->XferErrorCallback != NULL) + 1183 .loc 1 642 12 + 1184 012c 7B68 ldr r3, [r7, #4] + 1185 012e 1B6B ldr r3, [r3, #48] + 1186 .loc 1 642 7 + 1187 0130 002B cmp r3, #0 + ARM GAS /tmp/ccDI3rYs.s page 33 + + + 1188 0132 04D0 beq .L47 + 643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Transfer error callback */ + 645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferErrorCallback(hdma); + 1189 .loc 1 645 10 + 1190 0134 7B68 ldr r3, [r7, #4] + 1191 0136 1B6B ldr r3, [r3, #48] + 1192 .loc 1 645 6 + 1193 0138 7868 ldr r0, [r7, #4] + 1194 013a 9847 blx r3 + 1195 .LVL3: + 646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 1196 .loc 1 648 1 + 1197 013c FFE7 b .L47 + 1198 .L43: + 1199 .L47: + 1200 013e 00BF nop + 1201 0140 1037 adds r7, r7, #16 + 1202 .cfi_def_cfa_offset 8 + 1203 0142 BD46 mov sp, r7 + 1204 .cfi_def_cfa_register 13 + 1205 @ sp needed + 1206 0144 80BD pop {r7, pc} + 1207 .cfi_endproc + 1208 .LFE137: + 1210 .section .text.HAL_DMA_RegisterCallback,"ax",%progbits + 1211 .align 1 + 1212 .global HAL_DMA_RegisterCallback + 1213 .syntax unified + 1214 .thumb + 1215 .thumb_func + 1217 HAL_DMA_RegisterCallback: + 1218 .LFB138: + 649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** + 651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @brief Register callbacks + 652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains + 653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * the configuration information for the specified DMA Stream. + 654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param CallbackID User Callback identifier + 655:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. + 656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param pCallback pointer to private callback function which has pointer to + 657:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * a DMA_HandleTypeDef structure as parameter. + 658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @retval HAL status + 659:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef Callb + 661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 1219 .loc 1 661 1 + 1220 .cfi_startproc + 1221 @ args = 0, pretend = 0, frame = 24 + 1222 @ frame_needed = 1, uses_anonymous_args = 0 + 1223 @ link register save eliminated. + 1224 0000 80B4 push {r7} + 1225 .cfi_def_cfa_offset 4 + 1226 .cfi_offset 7, -4 + 1227 0002 87B0 sub sp, sp, #28 + ARM GAS /tmp/ccDI3rYs.s page 34 + + + 1228 .cfi_def_cfa_offset 32 + 1229 0004 00AF add r7, sp, #0 + 1230 .cfi_def_cfa_register 7 + 1231 0006 F860 str r0, [r7, #12] + 1232 0008 0B46 mov r3, r1 + 1233 000a 7A60 str r2, [r7, #4] + 1234 000c FB72 strb r3, [r7, #11] + 662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 1235 .loc 1 662 21 + 1236 000e 0023 movs r3, #0 + 1237 0010 FB75 strb r3, [r7, #23] + 663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 664:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Process locked */ + 665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** __HAL_LOCK(hdma); + 1238 .loc 1 665 3 + 1239 0012 FB68 ldr r3, [r7, #12] + 1240 0014 93F82030 ldrb r3, [r3, #32] @ zero_extendqisi2 + 1241 0018 012B cmp r3, #1 + 1242 001a 01D1 bne .L49 + 1243 .loc 1 665 3 is_stmt 0 discriminator 1 + 1244 001c 0223 movs r3, #2 + 1245 .loc 1 665 3 + 1246 001e 31E0 b .L50 + 1247 .L49: + 1248 .loc 1 665 3 discriminator 2 + 1249 0020 FB68 ldr r3, [r7, #12] + 1250 0022 0122 movs r2, #1 + 1251 0024 83F82020 strb r2, [r3, #32] + 666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if(HAL_DMA_STATE_READY == hdma->State) + 1252 .loc 1 667 33 is_stmt 1 + 1253 0028 FB68 ldr r3, [r7, #12] + 1254 002a 93F82130 ldrb r3, [r3, #33] @ zero_extendqisi2 + 1255 .loc 1 667 5 + 1256 002e 012B cmp r3, #1 + 1257 0030 21D1 bne .L51 + 668:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** switch (CallbackID) + 1258 .loc 1 669 5 + 1259 0032 FB7A ldrb r3, [r7, #11] @ zero_extendqisi2 + 1260 0034 032B cmp r3, #3 + 1261 0036 1BD8 bhi .L52 + 1262 0038 01A2 adr r2, .L54 + 1263 003a 52F823F0 ldr pc, [r2, r3, lsl #2] + 1264 003e 00BF .p2align 2 + 1265 .L54: + 1266 0040 51000000 .word .L57+1 + 1267 0044 59000000 .word .L56+1 + 1268 0048 61000000 .word .L55+1 + 1269 004c 69000000 .word .L53+1 + 1270 .p2align 1 + 1271 .L57: + 670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** case HAL_DMA_XFER_CPLT_CB_ID: + 672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferCpltCallback = pCallback; + 1272 .loc 1 672 35 + 1273 0050 FB68 ldr r3, [r7, #12] + ARM GAS /tmp/ccDI3rYs.s page 35 + + + 1274 0052 7A68 ldr r2, [r7, #4] + 1275 0054 9A62 str r2, [r3, #40] + 673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** break; + 1276 .loc 1 673 12 + 1277 0056 10E0 b .L59 + 1278 .L56: + 674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** case HAL_DMA_XFER_HALFCPLT_CB_ID: + 676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferHalfCpltCallback = pCallback; + 1279 .loc 1 676 39 + 1280 0058 FB68 ldr r3, [r7, #12] + 1281 005a 7A68 ldr r2, [r7, #4] + 1282 005c DA62 str r2, [r3, #44] + 677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** break; + 1283 .loc 1 677 12 + 1284 005e 0CE0 b .L59 + 1285 .L55: + 678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** case HAL_DMA_XFER_ERROR_CB_ID: + 680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferErrorCallback = pCallback; + 1286 .loc 1 680 36 + 1287 0060 FB68 ldr r3, [r7, #12] + 1288 0062 7A68 ldr r2, [r7, #4] + 1289 0064 1A63 str r2, [r3, #48] + 681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** break; + 1290 .loc 1 681 12 + 1291 0066 08E0 b .L59 + 1292 .L53: + 682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** case HAL_DMA_XFER_ABORT_CB_ID: + 684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferAbortCallback = pCallback; + 1293 .loc 1 684 36 + 1294 0068 FB68 ldr r3, [r7, #12] + 1295 006a 7A68 ldr r2, [r7, #4] + 1296 006c 5A63 str r2, [r3, #52] + 685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** break; + 1297 .loc 1 685 12 + 1298 006e 04E0 b .L59 + 1299 .L52: + 686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** default: + 688:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** status = HAL_ERROR; + 1300 .loc 1 688 19 + 1301 0070 0123 movs r3, #1 + 1302 0072 FB75 strb r3, [r7, #23] + 689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** break; + 1303 .loc 1 689 12 + 1304 0074 01E0 b .L59 + 1305 .L51: + 690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** else + 693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 694:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** status = HAL_ERROR; + 1306 .loc 1 694 12 + 1307 0076 0123 movs r3, #1 + 1308 0078 FB75 strb r3, [r7, #23] + ARM GAS /tmp/ccDI3rYs.s page 36 + + + 1309 .L59: + 695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Release Lock */ + 698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 1310 .loc 1 698 3 + 1311 007a FB68 ldr r3, [r7, #12] + 1312 007c 0022 movs r2, #0 + 1313 007e 83F82020 strb r2, [r3, #32] + 699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 700:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** return status; + 1314 .loc 1 700 10 + 1315 0082 FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 1316 .L50: + 701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 1317 .loc 1 701 1 + 1318 0084 1846 mov r0, r3 + 1319 0086 1C37 adds r7, r7, #28 + 1320 .cfi_def_cfa_offset 4 + 1321 0088 BD46 mov sp, r7 + 1322 .cfi_def_cfa_register 13 + 1323 @ sp needed + 1324 008a 5DF8047B ldr r7, [sp], #4 + 1325 .cfi_restore 7 + 1326 .cfi_def_cfa_offset 0 + 1327 008e 7047 bx lr + 1328 .cfi_endproc + 1329 .LFE138: + 1331 .section .text.HAL_DMA_UnRegisterCallback,"ax",%progbits + 1332 .align 1 + 1333 .global HAL_DMA_UnRegisterCallback + 1334 .syntax unified + 1335 .thumb + 1336 .thumb_func + 1338 HAL_DMA_UnRegisterCallback: + 1339 .LFB139: + 702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** + 704:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @brief UnRegister callbacks + 705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains + 706:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * the configuration information for the specified DMA Stream. + 707:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param CallbackID User Callback identifier + 708:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. + 709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @retval HAL status + 710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef Cal + 712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 1340 .loc 1 712 1 + 1341 .cfi_startproc + 1342 @ args = 0, pretend = 0, frame = 16 + 1343 @ frame_needed = 1, uses_anonymous_args = 0 + 1344 @ link register save eliminated. + 1345 0000 80B4 push {r7} + 1346 .cfi_def_cfa_offset 4 + 1347 .cfi_offset 7, -4 + 1348 0002 85B0 sub sp, sp, #20 + 1349 .cfi_def_cfa_offset 24 + ARM GAS /tmp/ccDI3rYs.s page 37 + + + 1350 0004 00AF add r7, sp, #0 + 1351 .cfi_def_cfa_register 7 + 1352 0006 7860 str r0, [r7, #4] + 1353 0008 0B46 mov r3, r1 + 1354 000a FB70 strb r3, [r7, #3] + 713:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** HAL_StatusTypeDef status = HAL_OK; + 1355 .loc 1 713 21 + 1356 000c 0023 movs r3, #0 + 1357 000e FB73 strb r3, [r7, #15] + 714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Process locked */ + 716:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** __HAL_LOCK(hdma); + 1358 .loc 1 716 3 + 1359 0010 7B68 ldr r3, [r7, #4] + 1360 0012 93F82030 ldrb r3, [r3, #32] @ zero_extendqisi2 + 1361 0016 012B cmp r3, #1 + 1362 0018 01D1 bne .L61 + 1363 .loc 1 716 3 is_stmt 0 discriminator 1 + 1364 001a 0223 movs r3, #2 + 1365 .loc 1 716 3 + 1366 001c 3FE0 b .L62 + 1367 .L61: + 1368 .loc 1 716 3 discriminator 2 + 1369 001e 7B68 ldr r3, [r7, #4] + 1370 0020 0122 movs r2, #1 + 1371 0022 83F82020 strb r2, [r3, #32] + 717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 718:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if(HAL_DMA_STATE_READY == hdma->State) + 1372 .loc 1 718 33 is_stmt 1 + 1373 0026 7B68 ldr r3, [r7, #4] + 1374 0028 93F82130 ldrb r3, [r3, #33] @ zero_extendqisi2 + 1375 .loc 1 718 5 + 1376 002c 012B cmp r3, #1 + 1377 002e 2FD1 bne .L63 + 719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 720:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** switch (CallbackID) + 1378 .loc 1 720 5 + 1379 0030 FB78 ldrb r3, [r7, #3] @ zero_extendqisi2 + 1380 0032 042B cmp r3, #4 + 1381 0034 29D8 bhi .L64 + 1382 0036 01A2 adr r2, .L66 + 1383 0038 52F823F0 ldr pc, [r2, r3, lsl #2] + 1384 .p2align 2 + 1385 .L66: + 1386 003c 51000000 .word .L70+1 + 1387 0040 59000000 .word .L69+1 + 1388 0044 61000000 .word .L68+1 + 1389 0048 69000000 .word .L67+1 + 1390 004c 71000000 .word .L65+1 + 1391 .p2align 1 + 1392 .L70: + 721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 722:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** case HAL_DMA_XFER_CPLT_CB_ID: + 723:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferCpltCallback = NULL; + 1393 .loc 1 723 35 + 1394 0050 7B68 ldr r3, [r7, #4] + 1395 0052 0022 movs r2, #0 + ARM GAS /tmp/ccDI3rYs.s page 38 + + + 1396 0054 9A62 str r2, [r3, #40] + 724:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** break; + 1397 .loc 1 724 12 + 1398 0056 1DE0 b .L72 + 1399 .L69: + 725:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** case HAL_DMA_XFER_HALFCPLT_CB_ID: + 727:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferHalfCpltCallback = NULL; + 1400 .loc 1 727 39 + 1401 0058 7B68 ldr r3, [r7, #4] + 1402 005a 0022 movs r2, #0 + 1403 005c DA62 str r2, [r3, #44] + 728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** break; + 1404 .loc 1 728 12 + 1405 005e 19E0 b .L72 + 1406 .L68: + 729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** case HAL_DMA_XFER_ERROR_CB_ID: + 731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferErrorCallback = NULL; + 1407 .loc 1 731 36 + 1408 0060 7B68 ldr r3, [r7, #4] + 1409 0062 0022 movs r2, #0 + 1410 0064 1A63 str r2, [r3, #48] + 732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** break; + 1411 .loc 1 732 12 + 1412 0066 15E0 b .L72 + 1413 .L67: + 733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 734:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** case HAL_DMA_XFER_ABORT_CB_ID: + 735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferAbortCallback = NULL; + 1414 .loc 1 735 36 + 1415 0068 7B68 ldr r3, [r7, #4] + 1416 006a 0022 movs r2, #0 + 1417 006c 5A63 str r2, [r3, #52] + 736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** break; + 1418 .loc 1 736 12 + 1419 006e 11E0 b .L72 + 1420 .L65: + 737:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** case HAL_DMA_XFER_ALL_CB_ID: + 739:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferCpltCallback = NULL; + 1421 .loc 1 739 35 + 1422 0070 7B68 ldr r3, [r7, #4] + 1423 0072 0022 movs r2, #0 + 1424 0074 9A62 str r2, [r3, #40] + 740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferHalfCpltCallback = NULL; + 1425 .loc 1 740 39 + 1426 0076 7B68 ldr r3, [r7, #4] + 1427 0078 0022 movs r2, #0 + 1428 007a DA62 str r2, [r3, #44] + 741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferErrorCallback = NULL; + 1429 .loc 1 741 36 + 1430 007c 7B68 ldr r3, [r7, #4] + 1431 007e 0022 movs r2, #0 + 1432 0080 1A63 str r2, [r3, #48] + 742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->XferAbortCallback = NULL; + 1433 .loc 1 742 36 + ARM GAS /tmp/ccDI3rYs.s page 39 + + + 1434 0082 7B68 ldr r3, [r7, #4] + 1435 0084 0022 movs r2, #0 + 1436 0086 5A63 str r2, [r3, #52] + 743:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** break; + 1437 .loc 1 743 12 + 1438 0088 04E0 b .L72 + 1439 .L64: + 744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 745:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** default: + 746:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** status = HAL_ERROR; + 1440 .loc 1 746 19 + 1441 008a 0123 movs r3, #1 + 1442 008c FB73 strb r3, [r7, #15] + 747:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** break; + 1443 .loc 1 747 12 + 1444 008e 01E0 b .L72 + 1445 .L63: + 748:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** else + 751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 752:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** status = HAL_ERROR; + 1446 .loc 1 752 12 + 1447 0090 0123 movs r3, #1 + 1448 0092 FB73 strb r3, [r7, #15] + 1449 .L72: + 753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 755:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Release Lock */ + 756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** __HAL_UNLOCK(hdma); + 1450 .loc 1 756 3 + 1451 0094 7B68 ldr r3, [r7, #4] + 1452 0096 0022 movs r2, #0 + 1453 0098 83F82020 strb r2, [r3, #32] + 757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 758:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** return status; + 1454 .loc 1 758 10 + 1455 009c FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 1456 .L62: + 759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 1457 .loc 1 759 1 + 1458 009e 1846 mov r0, r3 + 1459 00a0 1437 adds r7, r7, #20 + 1460 .cfi_def_cfa_offset 4 + 1461 00a2 BD46 mov sp, r7 + 1462 .cfi_def_cfa_register 13 + 1463 @ sp needed + 1464 00a4 5DF8047B ldr r7, [sp], #4 + 1465 .cfi_restore 7 + 1466 .cfi_def_cfa_offset 0 + 1467 00a8 7047 bx lr + 1468 .cfi_endproc + 1469 .LFE139: + 1471 00aa 00BF .section .text.HAL_DMA_GetState,"ax",%progbits + 1472 .align 1 + 1473 .global HAL_DMA_GetState + 1474 .syntax unified + ARM GAS /tmp/ccDI3rYs.s page 40 + + + 1475 .thumb + 1476 .thumb_func + 1478 HAL_DMA_GetState: + 1479 .LFB140: + 760:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 761:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** + 762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @} + 763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 764:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions + 766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @brief Peripheral State functions + 767:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * + 768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** @verbatim + 769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** =============================================================================== + 770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** ##### State and Errors functions ##### + 771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** =============================================================================== + 772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** [..] + 773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** This subsection provides functions allowing to + 774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** (+) Check the DMA state + 775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** (+) Get error code + 776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 777:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** @endverbatim + 778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @{ + 779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 780:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** + 782:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @brief Returns the DMA state. + 783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains + 784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * the configuration information for the specified DMA Channel. + 785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @retval HAL state + 786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 787:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) + 788:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 1480 .loc 1 788 1 + 1481 .cfi_startproc + 1482 @ args = 0, pretend = 0, frame = 8 + 1483 @ frame_needed = 1, uses_anonymous_args = 0 + 1484 @ link register save eliminated. + 1485 0000 80B4 push {r7} + 1486 .cfi_def_cfa_offset 4 + 1487 .cfi_offset 7, -4 + 1488 0002 83B0 sub sp, sp, #12 + 1489 .cfi_def_cfa_offset 16 + 1490 0004 00AF add r7, sp, #0 + 1491 .cfi_def_cfa_register 7 + 1492 0006 7860 str r0, [r7, #4] + 789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** return hdma->State; + 1493 .loc 1 789 14 + 1494 0008 7B68 ldr r3, [r7, #4] + 1495 000a 93F82130 ldrb r3, [r3, #33] @ zero_extendqisi2 + 790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 1496 .loc 1 790 1 + 1497 000e 1846 mov r0, r3 + 1498 0010 0C37 adds r7, r7, #12 + 1499 .cfi_def_cfa_offset 4 + 1500 0012 BD46 mov sp, r7 + 1501 .cfi_def_cfa_register 13 + ARM GAS /tmp/ccDI3rYs.s page 41 + + + 1502 @ sp needed + 1503 0014 5DF8047B ldr r7, [sp], #4 + 1504 .cfi_restore 7 + 1505 .cfi_def_cfa_offset 0 + 1506 0018 7047 bx lr + 1507 .cfi_endproc + 1508 .LFE140: + 1510 .section .text.HAL_DMA_GetError,"ax",%progbits + 1511 .align 1 + 1512 .global HAL_DMA_GetError + 1513 .syntax unified + 1514 .thumb + 1515 .thumb_func + 1517 HAL_DMA_GetError: + 1518 .LFB141: + 791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** + 793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @brief Return the DMA error code + 794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains + 795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * the configuration information for the specified DMA Channel. + 796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @retval DMA Error Code + 797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 798:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) + 799:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 1519 .loc 1 799 1 + 1520 .cfi_startproc + 1521 @ args = 0, pretend = 0, frame = 8 + 1522 @ frame_needed = 1, uses_anonymous_args = 0 + 1523 @ link register save eliminated. + 1524 0000 80B4 push {r7} + 1525 .cfi_def_cfa_offset 4 + 1526 .cfi_offset 7, -4 + 1527 0002 83B0 sub sp, sp, #12 + 1528 .cfi_def_cfa_offset 16 + 1529 0004 00AF add r7, sp, #0 + 1530 .cfi_def_cfa_register 7 + 1531 0006 7860 str r0, [r7, #4] + 800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** return hdma->ErrorCode; + 1532 .loc 1 800 14 + 1533 0008 7B68 ldr r3, [r7, #4] + 1534 000a 9B6B ldr r3, [r3, #56] + 801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 1535 .loc 1 801 1 + 1536 000c 1846 mov r0, r3 + 1537 000e 0C37 adds r7, r7, #12 + 1538 .cfi_def_cfa_offset 4 + 1539 0010 BD46 mov sp, r7 + 1540 .cfi_def_cfa_register 13 + 1541 @ sp needed + 1542 0012 5DF8047B ldr r7, [sp], #4 + 1543 .cfi_restore 7 + 1544 .cfi_def_cfa_offset 0 + 1545 0016 7047 bx lr + 1546 .cfi_endproc + 1547 .LFE141: + 1549 .section .text.DMA_SetConfig,"ax",%progbits + 1550 .align 1 + ARM GAS /tmp/ccDI3rYs.s page 42 + + + 1551 .syntax unified + 1552 .thumb + 1553 .thumb_func + 1555 DMA_SetConfig: + 1556 .LFB142: + 802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 803:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** + 804:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @} + 805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 806:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 807:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** + 808:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @} + 809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 811:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** @addtogroup DMA_Private_Functions + 812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @{ + 813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 814:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** + 816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @brief Set the DMA Transfer parameters. + 817:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains + 818:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * the configuration information for the specified DMA Channel. + 819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param SrcAddress The source memory Buffer address + 820:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param DstAddress The destination memory Buffer address + 821:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param DataLength The length of data to be transferred from source to destination + 822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @retval HAL status + 823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32 + 825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 1557 .loc 1 825 1 + 1558 .cfi_startproc + 1559 @ args = 0, pretend = 0, frame = 16 + 1560 @ frame_needed = 1, uses_anonymous_args = 0 + 1561 @ link register save eliminated. + 1562 0000 80B4 push {r7} + 1563 .cfi_def_cfa_offset 4 + 1564 .cfi_offset 7, -4 + 1565 0002 85B0 sub sp, sp, #20 + 1566 .cfi_def_cfa_offset 24 + 1567 0004 00AF add r7, sp, #0 + 1568 .cfi_def_cfa_register 7 + 1569 0006 F860 str r0, [r7, #12] + 1570 0008 B960 str r1, [r7, #8] + 1571 000a 7A60 str r2, [r7, #4] + 1572 000c 3B60 str r3, [r7] + 826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Clear all flags */ + 827:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex); + 1573 .loc 1 827 54 + 1574 000e FB68 ldr r3, [r7, #12] + 1575 0010 1A6C ldr r2, [r3, #64] + 1576 .loc 1 827 7 + 1577 0012 FB68 ldr r3, [r7, #12] + 1578 0014 DB6B ldr r3, [r3, #60] + 1579 .loc 1 827 47 + 1580 0016 0121 movs r1, #1 + 1581 0018 01FA02F2 lsl r2, r1, r2 + 1582 .loc 1 827 31 + ARM GAS /tmp/ccDI3rYs.s page 43 + + + 1583 001c 5A60 str r2, [r3, #4] + 828:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 829:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Configure DMA Channel data length */ + 830:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CNDTR = DataLength; + 1584 .loc 1 830 7 + 1585 001e FB68 ldr r3, [r7, #12] + 1586 0020 1B68 ldr r3, [r3] + 1587 .loc 1 830 25 + 1588 0022 3A68 ldr r2, [r7] + 1589 0024 5A60 str r2, [r3, #4] + 831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 832:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Peripheral to Memory */ + 833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + 1590 .loc 1 833 17 + 1591 0026 FB68 ldr r3, [r7, #12] + 1592 0028 5B68 ldr r3, [r3, #4] + 1593 .loc 1 833 5 + 1594 002a 102B cmp r3, #16 + 1595 002c 08D1 bne .L78 + 834:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 835:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Configure DMA Channel destination address */ + 836:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CPAR = DstAddress; + 1596 .loc 1 836 9 + 1597 002e FB68 ldr r3, [r7, #12] + 1598 0030 1B68 ldr r3, [r3] + 1599 .loc 1 836 26 + 1600 0032 7A68 ldr r2, [r7, #4] + 1601 0034 9A60 str r2, [r3, #8] + 837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Configure DMA Channel source address */ + 839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CMAR = SrcAddress; + 1602 .loc 1 839 9 + 1603 0036 FB68 ldr r3, [r7, #12] + 1604 0038 1B68 ldr r3, [r3] + 1605 .loc 1 839 26 + 1606 003a BA68 ldr r2, [r7, #8] + 1607 003c DA60 str r2, [r3, #12] + 840:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Memory to Peripheral */ + 842:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** else + 843:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 844:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Configure DMA Channel source address */ + 845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CPAR = SrcAddress; + 846:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* Configure DMA Channel destination address */ + 848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->Instance->CMAR = DstAddress; + 849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 1608 .loc 1 850 1 + 1609 003e 07E0 b .L80 + 1610 .L78: + 845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1611 .loc 1 845 9 + 1612 0040 FB68 ldr r3, [r7, #12] + 1613 0042 1B68 ldr r3, [r3] + 845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 1614 .loc 1 845 26 + ARM GAS /tmp/ccDI3rYs.s page 44 + + + 1615 0044 BA68 ldr r2, [r7, #8] + 1616 0046 9A60 str r2, [r3, #8] + 848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 1617 .loc 1 848 9 + 1618 0048 FB68 ldr r3, [r7, #12] + 1619 004a 1B68 ldr r3, [r3] + 848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 1620 .loc 1 848 26 + 1621 004c 7A68 ldr r2, [r7, #4] + 1622 004e DA60 str r2, [r3, #12] + 1623 .L80: + 1624 .loc 1 850 1 + 1625 0050 00BF nop + 1626 0052 1437 adds r7, r7, #20 + 1627 .cfi_def_cfa_offset 4 + 1628 0054 BD46 mov sp, r7 + 1629 .cfi_def_cfa_register 13 + 1630 @ sp needed + 1631 0056 5DF8047B ldr r7, [sp], #4 + 1632 .cfi_restore 7 + 1633 .cfi_def_cfa_offset 0 + 1634 005a 7047 bx lr + 1635 .cfi_endproc + 1636 .LFE142: + 1638 .section .text.DMA_CalcBaseAndBitshift,"ax",%progbits + 1639 .align 1 + 1640 .syntax unified + 1641 .thumb + 1642 .thumb_func + 1644 DMA_CalcBaseAndBitshift: + 1645 .LFB143: + 851:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** + 852:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /** + 853:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @brief Set the DMA base address and channel index depending on DMA instance + 854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains + 855:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * the configuration information for the specified DMA Stream. + 856:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** * @retval None + 857:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** */ + 858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) + 859:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 1646 .loc 1 859 1 + 1647 .cfi_startproc + 1648 @ args = 0, pretend = 0, frame = 8 + 1649 @ frame_needed = 1, uses_anonymous_args = 0 + 1650 @ link register save eliminated. + 1651 0000 80B4 push {r7} + 1652 .cfi_def_cfa_offset 4 + 1653 .cfi_offset 7, -4 + 1654 0002 83B0 sub sp, sp, #12 + 1655 .cfi_def_cfa_offset 16 + 1656 0004 00AF add r7, sp, #0 + 1657 .cfi_def_cfa_register 7 + 1658 0006 7860 str r0, [r7, #4] + 860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** #if defined (DMA2) + 861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* calculation of the channel index */ + 862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) + 1659 .loc 1 862 22 + ARM GAS /tmp/ccDI3rYs.s page 45 + + + 1660 0008 7B68 ldr r3, [r7, #4] + 1661 000a 1B68 ldr r3, [r3] + 1662 .loc 1 862 7 + 1663 000c 1A46 mov r2, r3 + 1664 .loc 1 862 6 + 1665 000e 144B ldr r3, .L85 + 1666 0010 9A42 cmp r2, r3 + 1667 0012 0FD8 bhi .L82 + 863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 864:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* DMA1 */ + 865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Ch + 1668 .loc 1 865 42 + 1669 0014 7B68 ldr r3, [r7, #4] + 1670 0016 1B68 ldr r3, [r3] + 1671 .loc 1 865 28 + 1672 0018 1A46 mov r2, r3 + 1673 .loc 1 865 53 + 1674 001a 124B ldr r3, .L85+4 + 1675 001c 1344 add r3, r3, r2 + 1676 .loc 1 865 80 + 1677 001e 124A ldr r2, .L85+8 + 1678 0020 A2FB0323 umull r2, r3, r2, r3 + 1679 0024 1B09 lsrs r3, r3, #4 + 1680 .loc 1 865 135 + 1681 0026 9A00 lsls r2, r3, #2 + 1682 .loc 1 865 24 + 1683 0028 7B68 ldr r3, [r7, #4] + 1684 002a 1A64 str r2, [r3, #64] + 866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->DmaBaseAddress = DMA1; + 1685 .loc 1 866 26 + 1686 002c 7B68 ldr r3, [r7, #4] + 1687 002e 0F4A ldr r2, .L85+12 + 1688 0030 DA63 str r2, [r3, #60] + 867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 868:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** else + 869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** { + 870:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* DMA2 */ + 871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Ch + 872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->DmaBaseAddress = DMA2; + 873:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** #else + 875:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* calculation of the channel index */ + 876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** /* DMA1 */ + 877:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Chan + 878:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->DmaBaseAddress = DMA1; + 879:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** #endif + 880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 1689 .loc 1 880 1 + 1690 0032 0EE0 b .L84 + 1691 .L82: + 871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->DmaBaseAddress = DMA2; + 1692 .loc 1 871 42 + 1693 0034 7B68 ldr r3, [r7, #4] + 1694 0036 1B68 ldr r3, [r3] + 871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->DmaBaseAddress = DMA2; + 1695 .loc 1 871 28 + 1696 0038 1A46 mov r2, r3 + ARM GAS /tmp/ccDI3rYs.s page 46 + + + 871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->DmaBaseAddress = DMA2; + 1697 .loc 1 871 53 + 1698 003a 0D4B ldr r3, .L85+16 + 1699 003c 1344 add r3, r3, r2 + 871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->DmaBaseAddress = DMA2; + 1700 .loc 1 871 80 + 1701 003e 0A4A ldr r2, .L85+8 + 1702 0040 A2FB0323 umull r2, r3, r2, r3 + 1703 0044 1B09 lsrs r3, r3, #4 + 871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->DmaBaseAddress = DMA2; + 1704 .loc 1 871 135 + 1705 0046 9A00 lsls r2, r3, #2 + 871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** hdma->DmaBaseAddress = DMA2; + 1706 .loc 1 871 24 + 1707 0048 7B68 ldr r3, [r7, #4] + 1708 004a 1A64 str r2, [r3, #64] + 872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_dma.c **** } + 1709 .loc 1 872 26 + 1710 004c 7B68 ldr r3, [r7, #4] + 1711 004e 094A ldr r2, .L85+20 + 1712 0050 DA63 str r2, [r3, #60] + 1713 .L84: + 1714 .loc 1 880 1 + 1715 0052 00BF nop + 1716 0054 0C37 adds r7, r7, #12 + 1717 .cfi_def_cfa_offset 4 + 1718 0056 BD46 mov sp, r7 + 1719 .cfi_def_cfa_register 13 + 1720 @ sp needed + 1721 0058 5DF8047B ldr r7, [sp], #4 + 1722 .cfi_restore 7 + 1723 .cfi_def_cfa_offset 0 + 1724 005c 7047 bx lr + 1725 .L86: + 1726 005e 00BF .align 2 + 1727 .L85: + 1728 0060 07040240 .word 1073873927 + 1729 0064 F8FFFDBF .word -1073872904 + 1730 0068 CDCCCCCC .word -858993459 + 1731 006c 00000240 .word 1073872896 + 1732 0070 F8FBFDBF .word -1073873928 + 1733 0074 00040240 .word 1073873920 + 1734 .cfi_endproc + 1735 .LFE143: + 1737 .text + 1738 .Letext0: + 1739 .file 2 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 1740 .file 3 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 1741 .file 4 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + 1742 .file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h" + 1743 .file 6 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h" + 1744 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h" + 1745 .file 8 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h" + ARM GAS /tmp/ccDI3rYs.s page 47 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f3xx_hal_dma.c + /tmp/ccDI3rYs.s:21 .text.HAL_DMA_Init:00000000 $t + /tmp/ccDI3rYs.s:27 .text.HAL_DMA_Init:00000000 HAL_DMA_Init + /tmp/ccDI3rYs.s:1644 .text.DMA_CalcBaseAndBitshift:00000000 DMA_CalcBaseAndBitshift + /tmp/ccDI3rYs.s:141 .text.HAL_DMA_DeInit:00000000 $t + /tmp/ccDI3rYs.s:147 .text.HAL_DMA_DeInit:00000000 HAL_DMA_DeInit + /tmp/ccDI3rYs.s:262 .text.HAL_DMA_Start:00000000 $t + /tmp/ccDI3rYs.s:268 .text.HAL_DMA_Start:00000000 HAL_DMA_Start + /tmp/ccDI3rYs.s:1555 .text.DMA_SetConfig:00000000 DMA_SetConfig + /tmp/ccDI3rYs.s:370 .text.HAL_DMA_Start_IT:00000000 $t + /tmp/ccDI3rYs.s:376 .text.HAL_DMA_Start_IT:00000000 HAL_DMA_Start_IT + /tmp/ccDI3rYs.s:520 .text.HAL_DMA_Abort:00000000 $t + /tmp/ccDI3rYs.s:526 .text.HAL_DMA_Abort:00000000 HAL_DMA_Abort + /tmp/ccDI3rYs.s:618 .text.HAL_DMA_Abort_IT:00000000 $t + /tmp/ccDI3rYs.s:624 .text.HAL_DMA_Abort_IT:00000000 HAL_DMA_Abort_IT + /tmp/ccDI3rYs.s:726 .text.HAL_DMA_PollForTransfer:00000000 $t + /tmp/ccDI3rYs.s:732 .text.HAL_DMA_PollForTransfer:00000000 HAL_DMA_PollForTransfer + /tmp/ccDI3rYs.s:956 .text.HAL_DMA_IRQHandler:00000000 $t + /tmp/ccDI3rYs.s:962 .text.HAL_DMA_IRQHandler:00000000 HAL_DMA_IRQHandler + /tmp/ccDI3rYs.s:1211 .text.HAL_DMA_RegisterCallback:00000000 $t + /tmp/ccDI3rYs.s:1217 .text.HAL_DMA_RegisterCallback:00000000 HAL_DMA_RegisterCallback + /tmp/ccDI3rYs.s:1266 .text.HAL_DMA_RegisterCallback:00000040 $d + /tmp/ccDI3rYs.s:1270 .text.HAL_DMA_RegisterCallback:00000050 $t + /tmp/ccDI3rYs.s:1332 .text.HAL_DMA_UnRegisterCallback:00000000 $t + /tmp/ccDI3rYs.s:1338 .text.HAL_DMA_UnRegisterCallback:00000000 HAL_DMA_UnRegisterCallback + /tmp/ccDI3rYs.s:1386 .text.HAL_DMA_UnRegisterCallback:0000003c $d + /tmp/ccDI3rYs.s:1391 .text.HAL_DMA_UnRegisterCallback:00000050 $t + /tmp/ccDI3rYs.s:1472 .text.HAL_DMA_GetState:00000000 $t + /tmp/ccDI3rYs.s:1478 .text.HAL_DMA_GetState:00000000 HAL_DMA_GetState + /tmp/ccDI3rYs.s:1511 .text.HAL_DMA_GetError:00000000 $t + /tmp/ccDI3rYs.s:1517 .text.HAL_DMA_GetError:00000000 HAL_DMA_GetError + /tmp/ccDI3rYs.s:1550 .text.DMA_SetConfig:00000000 $t + /tmp/ccDI3rYs.s:1639 .text.DMA_CalcBaseAndBitshift:00000000 $t + /tmp/ccDI3rYs.s:1728 .text.DMA_CalcBaseAndBitshift:00000060 $d + +UNDEFINED SYMBOLS +HAL_GetTick diff --git a/Software/build/stm32f3xx_hal_dma.o b/Software/build/stm32f3xx_hal_dma.o new file mode 100644 index 0000000..300d455 Binary files /dev/null and b/Software/build/stm32f3xx_hal_dma.o differ diff --git a/Software/build/stm32f3xx_hal_exti.d b/Software/build/stm32f3xx_hal_exti.d new file mode 100644 index 0000000..12116ed --- /dev/null +++ b/Software/build/stm32f3xx_hal_exti.d @@ -0,0 +1,62 @@ +build/stm32f3xx_hal_exti.o: \ + Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + Core/Inc/stm32f3xx_hal_conf.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h: diff --git a/Software/build/stm32f3xx_hal_exti.lst b/Software/build/stm32f3xx_hal_exti.lst new file mode 100644 index 0000000..2cf399b --- /dev/null +++ b/Software/build/stm32f3xx_hal_exti.lst @@ -0,0 +1,1895 @@ +ARM GAS /tmp/cc2L1WXV.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 6 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "stm32f3xx_hal_exti.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c" + 20 .section .text.HAL_EXTI_SetConfigLine,"ax",%progbits + 21 .align 1 + 22 .global HAL_EXTI_SetConfigLine + 23 .syntax unified + 24 .thumb + 25 .thumb_func + 27 HAL_EXTI_SetConfigLine: + 28 .LFB130: + 1:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /** + 2:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** ****************************************************************************** + 3:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @file stm32f3xx_hal_exti.c + 4:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @author MCD Application Team + 5:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @brief EXTI HAL module driver. + 6:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * functionalities of the Extended Interrupts and events controller (EXTI) peripheral: + 8:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * + Initialization and de-initialization functions + 9:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * + IO operation functions + 10:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * + 11:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** ****************************************************************************** + 12:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @attention + 13:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * + 14:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * Copyright (c) 2019 STMicroelectronics. + 15:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * All rights reserved. + 16:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * + 17:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * This software is licensed under terms that can be found in the LICENSE file + 18:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * in the root directory of this software component. + 19:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 20:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * + 21:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** ****************************************************************************** + 22:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** @verbatim + 23:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** ============================================================================== + 24:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** ##### EXTI Peripheral features ##### + 25:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** ============================================================================== + 26:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** [..] + 27:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (+) Each Exti line can be configured within this driver. + 28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (+) Exti line can be configured in 3 different modes + 30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (++) Interrupt + ARM GAS /tmp/cc2L1WXV.s page 2 + + + 31:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (++) Event + 32:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (++) Both of them + 33:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 34:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (+) Configurable Exti lines can be configured with 3 different triggers + 35:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (++) Rising + 36:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (++) Falling + 37:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (++) Both of them + 38:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 39:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (+) When set in interrupt mode, configurable Exti lines have two different + 40:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** interrupts pending registers which allow to distinguish which transition + 41:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** occurs: + 42:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (++) Rising edge pending interrupt + 43:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (++) Falling + 44:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 45:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can + 46:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** be selected through multiplexer. + 47:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 48:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** ##### How to use this driver ##### + 49:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** ============================================================================== + 50:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** [..] + 51:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 52:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (#) Configure the EXTI line using HAL_EXTI_SetConfigLine(). + 53:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (++) Choose the interrupt line number by setting "Line" member from + 54:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** EXTI_ConfigTypeDef structure. + 55:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (++) Configure the interrupt and/or event mode using "Mode" member from + 56:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** EXTI_ConfigTypeDef structure. + 57:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (++) For configurable lines, configure rising and/or falling trigger + 58:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** "Trigger" member from EXTI_ConfigTypeDef structure. + 59:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel" + 60:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** member from GPIO_InitTypeDef structure. + 61:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 62:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (#) Get current Exti configuration of a dedicated line using + 63:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** HAL_EXTI_GetConfigLine(). + 64:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (++) Provide exiting handle as parameter. + 65:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter. + 66:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 67:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine(). + 68:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (++) Provide exiting handle as parameter. + 69:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 70:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback(). + 71:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (++) Provide exiting handle as first parameter. + 72:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (++) Provide which callback will be registered using one value from + 73:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** EXTI_CallbackIDTypeDef. + 74:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (++) Provide callback function pointer. + 75:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 76:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (#) Get interrupt pending bit using HAL_EXTI_GetPending(). + 77:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 78:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (#) Clear interrupt pending bit using HAL_EXTI_GetPending(). + 79:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 80:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** (#) Generate software interrupt using HAL_EXTI_GenerateSWI(). + 81:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 82:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** @endverbatim + 83:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** */ + 84:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Includes ------------------------------------------------------------------*/ + 86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** #include "stm32f3xx_hal.h" + 87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + ARM GAS /tmp/cc2L1WXV.s page 3 + + + 88:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /** @addtogroup STM32F3xx_HAL_Driver + 89:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @{ + 90:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** */ + 91:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 92:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /** @addtogroup EXTI + 93:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @{ + 94:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** */ + 95:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /** MISRA C:2012 deviation rule has been granted for following rule: + 96:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out + 97:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * of bounds [0,3] in following API : + 98:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * HAL_EXTI_SetConfigLine + 99:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * HAL_EXTI_GetConfigLine + 100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * HAL_EXTI_ClearConfigLine + 101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** */ + 102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** #ifdef HAL_EXTI_MODULE_ENABLED + 104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Private typedef -----------------------------------------------------------*/ + 106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Private defines -----------------------------------------------------------*/ + 107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /** @defgroup EXTI_Private_Constants EXTI Private Constants + 108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @{ + 109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** */ + 110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** #define EXTI_MODE_OFFSET 0x08u /* 0x20: offset between CPU IMR/EMR registers * + 111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** #define EXTI_CONFIG_OFFSET 0x08u /* 0x20: offset between CPU Rising/Falling conf + 112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /** + 113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @} + 114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** */ + 115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Private macros ------------------------------------------------------------*/ + 117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Private variables ---------------------------------------------------------*/ + 118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Private function prototypes -----------------------------------------------*/ + 119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Exported functions --------------------------------------------------------*/ + 120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /** @addtogroup EXTI_Exported_Functions + 122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @{ + 123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** */ + 124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /** @addtogroup EXTI_Exported_Functions_Group1 + 126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @brief Configuration functions + 127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * + 128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** @verbatim + 129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** =============================================================================== + 130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** ##### Configuration functions ##### + 131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** =============================================================================== + 132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** @endverbatim + 134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @{ + 135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** */ + 136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /** + 138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @brief Set configuration of a dedicated Exti line. + 139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @param hexti Exti handle. + 140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @param pExtiConfig Pointer on EXTI configuration to be set. + 141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @retval HAL Status. + 142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** */ + 143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig + 144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + ARM GAS /tmp/cc2L1WXV.s page 4 + + + 29 .loc 1 144 1 + 30 .cfi_startproc + 31 @ args = 0, pretend = 0, frame = 32 + 32 @ frame_needed = 1, uses_anonymous_args = 0 + 33 @ link register save eliminated. + 34 0000 80B4 push {r7} + 35 .cfi_def_cfa_offset 4 + 36 .cfi_offset 7, -4 + 37 0002 89B0 sub sp, sp, #36 + 38 .cfi_def_cfa_offset 40 + 39 0004 00AF add r7, sp, #0 + 40 .cfi_def_cfa_register 7 + 41 0006 7860 str r0, [r7, #4] + 42 0008 3960 str r1, [r7] + 145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** __IO uint32_t *regaddr; + 146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** uint32_t regval; + 147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** uint32_t linepos; + 148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** uint32_t maskline; + 149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** uint32_t offset; + 150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Check null pointer */ + 152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** if ((hexti == NULL) || (pExtiConfig == NULL)) + 43 .loc 1 152 6 + 44 000a 7B68 ldr r3, [r7, #4] + 45 000c 002B cmp r3, #0 + 46 000e 02D0 beq .L2 + 47 .loc 1 152 23 discriminator 1 + 48 0010 3B68 ldr r3, [r7] + 49 0012 002B cmp r3, #0 + 50 0014 01D1 bne .L3 + 51 .L2: + 153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** return HAL_ERROR; + 52 .loc 1 154 12 + 53 0016 0123 movs r3, #1 + 54 0018 B3E0 b .L4 + 55 .L3: + 155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Check parameters */ + 158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** assert_param(IS_EXTI_LINE(pExtiConfig->Line)); + 159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** assert_param(IS_EXTI_MODE(pExtiConfig->Mode)); + 160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Assign line number to handle */ + 162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** hexti->Line = pExtiConfig->Line; + 56 .loc 1 162 28 + 57 001a 3B68 ldr r3, [r7] + 58 001c 1A68 ldr r2, [r3] + 59 .loc 1 162 15 + 60 001e 7B68 ldr r3, [r7, #4] + 61 0020 1A60 str r2, [r3] + 163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Compute line register offset and line mask */ + 165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + 62 .loc 1 165 25 + 63 0022 3B68 ldr r3, [r7] + 64 0024 1B68 ldr r3, [r3] + ARM GAS /tmp/cc2L1WXV.s page 5 + + + 65 .loc 1 165 49 + 66 0026 1B0C lsrs r3, r3, #16 + 67 .loc 1 165 10 + 68 0028 03F00103 and r3, r3, #1 + 69 002c BB61 str r3, [r7, #24] + 166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + 70 .loc 1 166 25 + 71 002e 3B68 ldr r3, [r7] + 72 0030 1B68 ldr r3, [r3] + 73 .loc 1 166 11 + 74 0032 03F01F03 and r3, r3, #31 + 75 0036 7B61 str r3, [r7, #20] + 167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** maskline = (1uL << linepos); + 76 .loc 1 167 12 + 77 0038 0122 movs r2, #1 + 78 003a 7B69 ldr r3, [r7, #20] + 79 003c 02FA03F3 lsl r3, r2, r3 + 80 0040 3B61 str r3, [r7, #16] + 168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Configure triggers for configurable lines */ + 170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) + 81 .loc 1 170 19 + 82 0042 3B68 ldr r3, [r7] + 83 0044 1B68 ldr r3, [r3] + 84 .loc 1 170 26 + 85 0046 03F00073 and r3, r3, #33554432 + 86 .loc 1 170 6 + 87 004a 002B cmp r3, #0 + 88 004c 60D0 beq .L5 + 171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger)); + 173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Configure rising trigger */ + 175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regaddr = (&EXTI->RTSR + (EXTI_CONFIG_OFFSET * offset)); + 89 .loc 1 175 28 + 90 004e BB69 ldr r3, [r7, #24] + 91 0050 5A01 lsls r2, r3, #5 + 92 .loc 1 175 13 + 93 0052 4F4B ldr r3, .L14 + 94 0054 1344 add r3, r3, r2 + 95 0056 FB60 str r3, [r7, #12] + 176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval = *regaddr; + 96 .loc 1 176 12 + 97 0058 FB68 ldr r3, [r7, #12] + 98 005a 1B68 ldr r3, [r3] + 99 005c FB61 str r3, [r7, #28] + 177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Mask or set line */ + 179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u) + 100 .loc 1 179 21 + 101 005e 3B68 ldr r3, [r7] + 102 0060 9B68 ldr r3, [r3, #8] + 103 .loc 1 179 31 + 104 0062 03F00103 and r3, r3, #1 + 105 .loc 1 179 8 + 106 0066 002B cmp r3, #0 + 107 0068 04D0 beq .L6 + ARM GAS /tmp/cc2L1WXV.s page 6 + + + 180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval |= maskline; + 108 .loc 1 181 14 + 109 006a FA69 ldr r2, [r7, #28] + 110 006c 3B69 ldr r3, [r7, #16] + 111 006e 1343 orrs r3, r3, r2 + 112 0070 FB61 str r3, [r7, #28] + 113 0072 04E0 b .L7 + 114 .L6: + 182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** else + 184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval &= ~maskline; + 115 .loc 1 185 17 + 116 0074 3B69 ldr r3, [r7, #16] + 117 0076 DB43 mvns r3, r3 + 118 .loc 1 185 14 + 119 0078 FA69 ldr r2, [r7, #28] + 120 007a 1340 ands r3, r3, r2 + 121 007c FB61 str r3, [r7, #28] + 122 .L7: + 186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Store rising trigger mode */ + 189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** *regaddr = regval; + 123 .loc 1 189 14 + 124 007e FB68 ldr r3, [r7, #12] + 125 0080 FA69 ldr r2, [r7, #28] + 126 0082 1A60 str r2, [r3] + 190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Configure falling trigger */ + 192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regaddr = (&EXTI->FTSR + (EXTI_CONFIG_OFFSET * offset)); + 127 .loc 1 192 28 + 128 0084 BB69 ldr r3, [r7, #24] + 129 0086 5A01 lsls r2, r3, #5 + 130 .loc 1 192 13 + 131 0088 424B ldr r3, .L14+4 + 132 008a 1344 add r3, r3, r2 + 133 008c FB60 str r3, [r7, #12] + 193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval = *regaddr; + 134 .loc 1 193 12 + 135 008e FB68 ldr r3, [r7, #12] + 136 0090 1B68 ldr r3, [r3] + 137 0092 FB61 str r3, [r7, #28] + 194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Mask or set line */ + 196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u) + 138 .loc 1 196 21 + 139 0094 3B68 ldr r3, [r7] + 140 0096 9B68 ldr r3, [r3, #8] + 141 .loc 1 196 31 + 142 0098 03F00203 and r3, r3, #2 + 143 .loc 1 196 8 + 144 009c 002B cmp r3, #0 + 145 009e 04D0 beq .L8 + 197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval |= maskline; + ARM GAS /tmp/cc2L1WXV.s page 7 + + + 146 .loc 1 198 14 + 147 00a0 FA69 ldr r2, [r7, #28] + 148 00a2 3B69 ldr r3, [r7, #16] + 149 00a4 1343 orrs r3, r3, r2 + 150 00a6 FB61 str r3, [r7, #28] + 151 00a8 04E0 b .L9 + 152 .L8: + 199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** else + 201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval &= ~maskline; + 153 .loc 1 202 17 + 154 00aa 3B69 ldr r3, [r7, #16] + 155 00ac DB43 mvns r3, r3 + 156 .loc 1 202 14 + 157 00ae FA69 ldr r2, [r7, #28] + 158 00b0 1340 ands r3, r3, r2 + 159 00b2 FB61 str r3, [r7, #28] + 160 .L9: + 203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Store falling trigger mode */ + 206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** *regaddr = regval; + 161 .loc 1 206 14 + 162 00b4 FB68 ldr r3, [r7, #12] + 163 00b6 FA69 ldr r2, [r7, #28] + 164 00b8 1A60 str r2, [r3] + 207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Configure gpio port selection in case of gpio exti line */ + 209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + 165 .loc 1 209 21 + 166 00ba 3B68 ldr r3, [r7] + 167 00bc 1B68 ldr r3, [r3] + 168 .loc 1 209 28 + 169 00be 03F0C063 and r3, r3, #100663296 + 170 .loc 1 209 8 + 171 00c2 B3F1C06F cmp r3, #100663296 + 172 00c6 23D1 bne .L5 + 210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel)); + 212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** assert_param(IS_EXTI_GPIO_PIN(linepos)); + 213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval = SYSCFG->EXTICR[linepos >> 2u]; + 173 .loc 1 214 22 + 174 00c8 334A ldr r2, .L14+8 + 175 .loc 1 214 39 + 176 00ca 7B69 ldr r3, [r7, #20] + 177 00cc 9B08 lsrs r3, r3, #2 + 178 .loc 1 214 14 + 179 00ce 0233 adds r3, r3, #2 + 180 00d0 52F82330 ldr r3, [r2, r3, lsl #2] + 181 00d4 FB61 str r3, [r7, #28] + 215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + 182 .loc 1 215 80 + 183 00d6 7B69 ldr r3, [r7, #20] + 184 00d8 03F00303 and r3, r3, #3 + 185 .loc 1 215 69 + ARM GAS /tmp/cc2L1WXV.s page 8 + + + 186 00dc 9B00 lsls r3, r3, #2 + 187 .loc 1 215 40 + 188 00de 0F22 movs r2, #15 + 189 00e0 02FA03F3 lsl r3, r2, r3 + 190 .loc 1 215 17 + 191 00e4 DB43 mvns r3, r3 + 192 .loc 1 215 14 + 193 00e6 FA69 ldr r2, [r7, #28] + 194 00e8 1340 ands r3, r3, r2 + 195 00ea FB61 str r3, [r7, #28] + 216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + 196 .loc 1 216 29 + 197 00ec 3B68 ldr r3, [r7] + 198 00ee DA68 ldr r2, [r3, #12] + 199 .loc 1 216 79 + 200 00f0 7B69 ldr r3, [r7, #20] + 201 00f2 03F00303 and r3, r3, #3 + 202 .loc 1 216 68 + 203 00f6 9B00 lsls r3, r3, #2 + 204 .loc 1 216 39 + 205 00f8 02FA03F3 lsl r3, r2, r3 + 206 .loc 1 216 14 + 207 00fc FA69 ldr r2, [r7, #28] + 208 00fe 1343 orrs r3, r3, r2 + 209 0100 FB61 str r3, [r7, #28] + 217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** SYSCFG->EXTICR[linepos >> 2u] = regval; + 210 .loc 1 217 13 + 211 0102 2549 ldr r1, .L14+8 + 212 .loc 1 217 30 + 213 0104 7B69 ldr r3, [r7, #20] + 214 0106 9B08 lsrs r3, r3, #2 + 215 .loc 1 217 37 + 216 0108 0233 adds r3, r3, #2 + 217 010a FA69 ldr r2, [r7, #28] + 218 010c 41F82320 str r2, [r1, r3, lsl #2] + 219 .L5: + 218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Configure interrupt mode : read current mode */ + 222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regaddr = (&EXTI->IMR + (EXTI_MODE_OFFSET * offset)); + 220 .loc 1 222 25 + 221 0110 BB69 ldr r3, [r7, #24] + 222 0112 5B01 lsls r3, r3, #5 + 223 .loc 1 222 11 + 224 0114 03F18043 add r3, r3, #1073741824 + 225 0118 03F58233 add r3, r3, #66560 + 226 011c FB60 str r3, [r7, #12] + 223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval = *regaddr; + 227 .loc 1 223 10 + 228 011e FB68 ldr r3, [r7, #12] + 229 0120 1B68 ldr r3, [r3] + 230 0122 FB61 str r3, [r7, #28] + 224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Mask or set line */ + 226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u) + 231 .loc 1 226 19 + ARM GAS /tmp/cc2L1WXV.s page 9 + + + 232 0124 3B68 ldr r3, [r7] + 233 0126 5B68 ldr r3, [r3, #4] + 234 .loc 1 226 26 + 235 0128 03F00103 and r3, r3, #1 + 236 .loc 1 226 6 + 237 012c 002B cmp r3, #0 + 238 012e 04D0 beq .L10 + 227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval |= maskline; + 239 .loc 1 228 12 + 240 0130 FA69 ldr r2, [r7, #28] + 241 0132 3B69 ldr r3, [r7, #16] + 242 0134 1343 orrs r3, r3, r2 + 243 0136 FB61 str r3, [r7, #28] + 244 0138 04E0 b .L11 + 245 .L10: + 229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** else + 231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval &= ~maskline; + 246 .loc 1 232 15 + 247 013a 3B69 ldr r3, [r7, #16] + 248 013c DB43 mvns r3, r3 + 249 .loc 1 232 12 + 250 013e FA69 ldr r2, [r7, #28] + 251 0140 1340 ands r3, r3, r2 + 252 0142 FB61 str r3, [r7, #28] + 253 .L11: + 233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Store interrupt mode */ + 236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** *regaddr = regval; + 254 .loc 1 236 12 + 255 0144 FB68 ldr r3, [r7, #12] + 256 0146 FA69 ldr r2, [r7, #28] + 257 0148 1A60 str r2, [r3] + 237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Configure event mode : read current mode */ + 239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regaddr = (&EXTI->EMR + (EXTI_MODE_OFFSET * offset)); + 258 .loc 1 239 25 + 259 014a BB69 ldr r3, [r7, #24] + 260 014c 5A01 lsls r2, r3, #5 + 261 .loc 1 239 11 + 262 014e 134B ldr r3, .L14+12 + 263 0150 1344 add r3, r3, r2 + 264 0152 FB60 str r3, [r7, #12] + 240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval = *regaddr; + 265 .loc 1 240 10 + 266 0154 FB68 ldr r3, [r7, #12] + 267 0156 1B68 ldr r3, [r3] + 268 0158 FB61 str r3, [r7, #28] + 241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Mask or set line */ + 243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u) + 269 .loc 1 243 19 + 270 015a 3B68 ldr r3, [r7] + 271 015c 5B68 ldr r3, [r3, #4] + ARM GAS /tmp/cc2L1WXV.s page 10 + + + 272 .loc 1 243 26 + 273 015e 03F00203 and r3, r3, #2 + 274 .loc 1 243 6 + 275 0162 002B cmp r3, #0 + 276 0164 04D0 beq .L12 + 244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval |= maskline; + 277 .loc 1 245 12 + 278 0166 FA69 ldr r2, [r7, #28] + 279 0168 3B69 ldr r3, [r7, #16] + 280 016a 1343 orrs r3, r3, r2 + 281 016c FB61 str r3, [r7, #28] + 282 016e 04E0 b .L13 + 283 .L12: + 246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** else + 248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval &= ~maskline; + 284 .loc 1 249 15 + 285 0170 3B69 ldr r3, [r7, #16] + 286 0172 DB43 mvns r3, r3 + 287 .loc 1 249 12 + 288 0174 FA69 ldr r2, [r7, #28] + 289 0176 1340 ands r3, r3, r2 + 290 0178 FB61 str r3, [r7, #28] + 291 .L13: + 250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Store event mode */ + 253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** *regaddr = regval; + 292 .loc 1 253 12 + 293 017a FB68 ldr r3, [r7, #12] + 294 017c FA69 ldr r2, [r7, #28] + 295 017e 1A60 str r2, [r3] + 254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** return HAL_OK; + 296 .loc 1 255 10 + 297 0180 0023 movs r3, #0 + 298 .L4: + 256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 299 .loc 1 256 1 + 300 0182 1846 mov r0, r3 + 301 0184 2437 adds r7, r7, #36 + 302 .cfi_def_cfa_offset 4 + 303 0186 BD46 mov sp, r7 + 304 .cfi_def_cfa_register 13 + 305 @ sp needed + 306 0188 5DF8047B ldr r7, [sp], #4 + 307 .cfi_restore 7 + 308 .cfi_def_cfa_offset 0 + 309 018c 7047 bx lr + 310 .L15: + 311 018e 00BF .align 2 + 312 .L14: + 313 0190 08040140 .word 1073808392 + 314 0194 0C040140 .word 1073808396 + 315 0198 00000140 .word 1073807360 + ARM GAS /tmp/cc2L1WXV.s page 11 + + + 316 019c 04040140 .word 1073808388 + 317 .cfi_endproc + 318 .LFE130: + 320 .section .text.HAL_EXTI_GetConfigLine,"ax",%progbits + 321 .align 1 + 322 .global HAL_EXTI_GetConfigLine + 323 .syntax unified + 324 .thumb + 325 .thumb_func + 327 HAL_EXTI_GetConfigLine: + 328 .LFB131: + 257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /** + 259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @brief Get configuration of a dedicated Exti line. + 260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @param hexti Exti handle. + 261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @param pExtiConfig Pointer on structure to store Exti configuration. + 262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @retval HAL Status. + 263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** */ + 264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig + 265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 329 .loc 1 265 1 + 330 .cfi_startproc + 331 @ args = 0, pretend = 0, frame = 32 + 332 @ frame_needed = 1, uses_anonymous_args = 0 + 333 @ link register save eliminated. + 334 0000 80B4 push {r7} + 335 .cfi_def_cfa_offset 4 + 336 .cfi_offset 7, -4 + 337 0002 89B0 sub sp, sp, #36 + 338 .cfi_def_cfa_offset 40 + 339 0004 00AF add r7, sp, #0 + 340 .cfi_def_cfa_register 7 + 341 0006 7860 str r0, [r7, #4] + 342 0008 3960 str r1, [r7] + 266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** __IO uint32_t *regaddr; + 267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** uint32_t regval; + 268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** uint32_t linepos; + 269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** uint32_t maskline; + 270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** uint32_t offset; + 271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Check null pointer */ + 273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** if ((hexti == NULL) || (pExtiConfig == NULL)) + 343 .loc 1 273 6 + 344 000a 7B68 ldr r3, [r7, #4] + 345 000c 002B cmp r3, #0 + 346 000e 02D0 beq .L17 + 347 .loc 1 273 23 discriminator 1 + 348 0010 3B68 ldr r3, [r7] + 349 0012 002B cmp r3, #0 + 350 0014 01D1 bne .L18 + 351 .L17: + 274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** return HAL_ERROR; + 352 .loc 1 275 12 + 353 0016 0123 movs r3, #1 + 354 0018 85E0 b .L19 + 355 .L18: + ARM GAS /tmp/cc2L1WXV.s page 12 + + + 276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Check the parameter */ + 279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** assert_param(IS_EXTI_LINE(hexti->Line)); + 280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Store handle line number to configuration structure */ + 282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** pExtiConfig->Line = hexti->Line; + 356 .loc 1 282 28 + 357 001a 7B68 ldr r3, [r7, #4] + 358 001c 1A68 ldr r2, [r3] + 359 .loc 1 282 21 + 360 001e 3B68 ldr r3, [r7] + 361 0020 1A60 str r2, [r3] + 283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* compute line register offset and line mask */ + 285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + 362 .loc 1 285 25 + 363 0022 3B68 ldr r3, [r7] + 364 0024 1B68 ldr r3, [r3] + 365 .loc 1 285 49 + 366 0026 1B0C lsrs r3, r3, #16 + 367 .loc 1 285 10 + 368 0028 03F00103 and r3, r3, #1 + 369 002c FB61 str r3, [r7, #28] + 286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + 370 .loc 1 286 25 + 371 002e 3B68 ldr r3, [r7] + 372 0030 1B68 ldr r3, [r3] + 373 .loc 1 286 11 + 374 0032 03F01F03 and r3, r3, #31 + 375 0036 BB61 str r3, [r7, #24] + 287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** maskline = (1uL << linepos); + 376 .loc 1 287 12 + 377 0038 0122 movs r2, #1 + 378 003a BB69 ldr r3, [r7, #24] + 379 003c 02FA03F3 lsl r3, r2, r3 + 380 0040 7B61 str r3, [r7, #20] + 288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* 1] Get core mode : interrupt */ + 290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regaddr = (&EXTI->IMR + (EXTI_MODE_OFFSET * offset)); + 381 .loc 1 290 25 + 382 0042 FB69 ldr r3, [r7, #28] + 383 0044 5B01 lsls r3, r3, #5 + 384 .loc 1 290 11 + 385 0046 03F18043 add r3, r3, #1073741824 + 386 004a 03F58233 add r3, r3, #66560 + 387 004e 3B61 str r3, [r7, #16] + 291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval = *regaddr; + 388 .loc 1 291 10 + 389 0050 3B69 ldr r3, [r7, #16] + 390 0052 1B68 ldr r3, [r3] + 391 0054 FB60 str r3, [r7, #12] + 292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Check if selected line is enable */ + 294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** if ((regval & maskline) != 0x00u) + 392 .loc 1 294 15 + 393 0056 FA68 ldr r2, [r7, #12] + ARM GAS /tmp/cc2L1WXV.s page 13 + + + 394 0058 7B69 ldr r3, [r7, #20] + 395 005a 1340 ands r3, r3, r2 + 396 .loc 1 294 6 + 397 005c 002B cmp r3, #0 + 398 005e 03D0 beq .L20 + 295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** pExtiConfig->Mode = EXTI_MODE_INTERRUPT; + 399 .loc 1 296 23 + 400 0060 3B68 ldr r3, [r7] + 401 0062 0122 movs r2, #1 + 402 0064 5A60 str r2, [r3, #4] + 403 0066 02E0 b .L21 + 404 .L20: + 297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** else + 299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** pExtiConfig->Mode = EXTI_MODE_NONE; + 405 .loc 1 300 23 + 406 0068 3B68 ldr r3, [r7] + 407 006a 0022 movs r2, #0 + 408 006c 5A60 str r2, [r3, #4] + 409 .L21: + 301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Get event mode */ + 304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regaddr = (&EXTI->EMR + (EXTI_MODE_OFFSET * offset)); + 410 .loc 1 304 25 + 411 006e FB69 ldr r3, [r7, #28] + 412 0070 5A01 lsls r2, r3, #5 + 413 .loc 1 304 11 + 414 0072 304B ldr r3, .L26 + 415 0074 1344 add r3, r3, r2 + 416 0076 3B61 str r3, [r7, #16] + 305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval = *regaddr; + 417 .loc 1 305 10 + 418 0078 3B69 ldr r3, [r7, #16] + 419 007a 1B68 ldr r3, [r3] + 420 007c FB60 str r3, [r7, #12] + 306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Check if selected line is enable */ + 308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** if ((regval & maskline) != 0x00u) + 421 .loc 1 308 15 + 422 007e FA68 ldr r2, [r7, #12] + 423 0080 7B69 ldr r3, [r7, #20] + 424 0082 1340 ands r3, r3, r2 + 425 .loc 1 308 6 + 426 0084 002B cmp r3, #0 + 427 0086 05D0 beq .L22 + 309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** pExtiConfig->Mode |= EXTI_MODE_EVENT; + 428 .loc 1 310 16 + 429 0088 3B68 ldr r3, [r7] + 430 008a 5B68 ldr r3, [r3, #4] + 431 .loc 1 310 23 + 432 008c 43F00202 orr r2, r3, #2 + 433 0090 3B68 ldr r3, [r7] + 434 0092 5A60 str r2, [r3, #4] + ARM GAS /tmp/cc2L1WXV.s page 14 + + + 435 .L22: + 311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Get default Trigger and GPIOSel configuration */ + 314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + 436 .loc 1 314 24 + 437 0094 3B68 ldr r3, [r7] + 438 0096 0022 movs r2, #0 + 439 0098 9A60 str r2, [r3, #8] + 315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** pExtiConfig->GPIOSel = 0x00u; + 440 .loc 1 315 24 + 441 009a 3B68 ldr r3, [r7] + 442 009c 0022 movs r2, #0 + 443 009e DA60 str r2, [r3, #12] + 316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* 2] Get trigger for configurable lines : rising */ + 318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) + 444 .loc 1 318 19 + 445 00a0 3B68 ldr r3, [r7] + 446 00a2 1B68 ldr r3, [r3] + 447 .loc 1 318 26 + 448 00a4 03F00073 and r3, r3, #33554432 + 449 .loc 1 318 6 + 450 00a8 002B cmp r3, #0 + 451 00aa 3BD0 beq .L23 + 319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regaddr = (&EXTI->RTSR + (EXTI_CONFIG_OFFSET * offset)); + 452 .loc 1 320 28 + 453 00ac FB69 ldr r3, [r7, #28] + 454 00ae 5A01 lsls r2, r3, #5 + 455 .loc 1 320 13 + 456 00b0 214B ldr r3, .L26+4 + 457 00b2 1344 add r3, r3, r2 + 458 00b4 3B61 str r3, [r7, #16] + 321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval = *regaddr; + 459 .loc 1 321 12 + 460 00b6 3B69 ldr r3, [r7, #16] + 461 00b8 1B68 ldr r3, [r3] + 462 00ba FB60 str r3, [r7, #12] + 322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Check if configuration of selected line is enable */ + 324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** if ((regval & maskline) != 0x00u) + 463 .loc 1 324 17 + 464 00bc FA68 ldr r2, [r7, #12] + 465 00be 7B69 ldr r3, [r7, #20] + 466 00c0 1340 ands r3, r3, r2 + 467 .loc 1 324 8 + 468 00c2 002B cmp r3, #0 + 469 00c4 02D0 beq .L24 + 325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** pExtiConfig->Trigger = EXTI_TRIGGER_RISING; + 470 .loc 1 326 28 + 471 00c6 3B68 ldr r3, [r7] + 472 00c8 0122 movs r2, #1 + 473 00ca 9A60 str r2, [r3, #8] + 474 .L24: + 327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + ARM GAS /tmp/cc2L1WXV.s page 15 + + + 328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Get falling configuration */ + 330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regaddr = (&EXTI->FTSR + (EXTI_CONFIG_OFFSET * offset)); + 475 .loc 1 330 28 + 476 00cc FB69 ldr r3, [r7, #28] + 477 00ce 5A01 lsls r2, r3, #5 + 478 .loc 1 330 13 + 479 00d0 1A4B ldr r3, .L26+8 + 480 00d2 1344 add r3, r3, r2 + 481 00d4 3B61 str r3, [r7, #16] + 331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval = *regaddr; + 482 .loc 1 331 12 + 483 00d6 3B69 ldr r3, [r7, #16] + 484 00d8 1B68 ldr r3, [r3] + 485 00da FB60 str r3, [r7, #12] + 332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Check if configuration of selected line is enable */ + 334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** if ((regval & maskline) != 0x00u) + 486 .loc 1 334 17 + 487 00dc FA68 ldr r2, [r7, #12] + 488 00de 7B69 ldr r3, [r7, #20] + 489 00e0 1340 ands r3, r3, r2 + 490 .loc 1 334 8 + 491 00e2 002B cmp r3, #0 + 492 00e4 05D0 beq .L25 + 335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING; + 493 .loc 1 336 18 + 494 00e6 3B68 ldr r3, [r7] + 495 00e8 9B68 ldr r3, [r3, #8] + 496 .loc 1 336 28 + 497 00ea 43F00202 orr r2, r3, #2 + 498 00ee 3B68 ldr r3, [r7] + 499 00f0 9A60 str r2, [r3, #8] + 500 .L25: + 337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Get Gpio port selection for gpio lines */ + 340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + 501 .loc 1 340 21 + 502 00f2 3B68 ldr r3, [r7] + 503 00f4 1B68 ldr r3, [r3] + 504 .loc 1 340 28 + 505 00f6 03F0C063 and r3, r3, #100663296 + 506 .loc 1 340 8 + 507 00fa B3F1C06F cmp r3, #100663296 + 508 00fe 11D1 bne .L23 + 341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** assert_param(IS_EXTI_GPIO_PIN(linepos)); + 343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval = SYSCFG->EXTICR[linepos >> 2u]; + 509 .loc 1 344 22 + 510 0100 0F4A ldr r2, .L26+12 + 511 .loc 1 344 39 + 512 0102 BB69 ldr r3, [r7, #24] + 513 0104 9B08 lsrs r3, r3, #2 + 514 .loc 1 344 14 + ARM GAS /tmp/cc2L1WXV.s page 16 + + + 515 0106 0233 adds r3, r3, #2 + 516 0108 52F82330 ldr r3, [r2, r3, lsl #2] + 517 010c FB60 str r3, [r7, #12] + 345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** pExtiConfig->GPIOSel = (regval >> (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))) & SYSCFG_EX + 518 .loc 1 345 78 + 519 010e BB69 ldr r3, [r7, #24] + 520 0110 03F00303 and r3, r3, #3 + 521 .loc 1 345 67 + 522 0114 9B00 lsls r3, r3, #2 + 523 .loc 1 345 38 + 524 0116 FA68 ldr r2, [r7, #12] + 525 0118 22FA03F3 lsr r3, r2, r3 + 526 .loc 1 345 89 + 527 011c 03F00F02 and r2, r3, #15 + 528 .loc 1 345 28 + 529 0120 3B68 ldr r3, [r7] + 530 0122 DA60 str r2, [r3, #12] + 531 .L23: + 346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** return HAL_OK; + 532 .loc 1 349 10 + 533 0124 0023 movs r3, #0 + 534 .L19: + 350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 535 .loc 1 350 1 + 536 0126 1846 mov r0, r3 + 537 0128 2437 adds r7, r7, #36 + 538 .cfi_def_cfa_offset 4 + 539 012a BD46 mov sp, r7 + 540 .cfi_def_cfa_register 13 + 541 @ sp needed + 542 012c 5DF8047B ldr r7, [sp], #4 + 543 .cfi_restore 7 + 544 .cfi_def_cfa_offset 0 + 545 0130 7047 bx lr + 546 .L27: + 547 0132 00BF .align 2 + 548 .L26: + 549 0134 04040140 .word 1073808388 + 550 0138 08040140 .word 1073808392 + 551 013c 0C040140 .word 1073808396 + 552 0140 00000140 .word 1073807360 + 553 .cfi_endproc + 554 .LFE131: + 556 .section .text.HAL_EXTI_ClearConfigLine,"ax",%progbits + 557 .align 1 + 558 .global HAL_EXTI_ClearConfigLine + 559 .syntax unified + 560 .thumb + 561 .thumb_func + 563 HAL_EXTI_ClearConfigLine: + 564 .LFB132: + 351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /** + 353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @brief Clear whole configuration of a dedicated Exti line. + ARM GAS /tmp/cc2L1WXV.s page 17 + + + 354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @param hexti Exti handle. + 355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @retval HAL Status. + 356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** */ + 357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti) + 358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 565 .loc 1 358 1 + 566 .cfi_startproc + 567 @ args = 0, pretend = 0, frame = 32 + 568 @ frame_needed = 1, uses_anonymous_args = 0 + 569 @ link register save eliminated. + 570 0000 80B4 push {r7} + 571 .cfi_def_cfa_offset 4 + 572 .cfi_offset 7, -4 + 573 0002 89B0 sub sp, sp, #36 + 574 .cfi_def_cfa_offset 40 + 575 0004 00AF add r7, sp, #0 + 576 .cfi_def_cfa_register 7 + 577 0006 7860 str r0, [r7, #4] + 359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** __IO uint32_t *regaddr; + 360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** uint32_t regval; + 361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** uint32_t linepos; + 362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** uint32_t maskline; + 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** uint32_t offset; + 364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Check null pointer */ + 366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** if (hexti == NULL) + 578 .loc 1 366 6 + 579 0008 7B68 ldr r3, [r7, #4] + 580 000a 002B cmp r3, #0 + 581 000c 01D1 bne .L29 + 367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** return HAL_ERROR; + 582 .loc 1 368 12 + 583 000e 0123 movs r3, #1 + 584 0010 70E0 b .L30 + 585 .L29: + 369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Check the parameter */ + 372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** assert_param(IS_EXTI_LINE(hexti->Line)); + 373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* compute line register offset and line mask */ + 375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + 586 .loc 1 375 19 + 587 0012 7B68 ldr r3, [r7, #4] + 588 0014 1B68 ldr r3, [r3] + 589 .loc 1 375 43 + 590 0016 1B0C lsrs r3, r3, #16 + 591 .loc 1 375 10 + 592 0018 03F00103 and r3, r3, #1 + 593 001c FB61 str r3, [r7, #28] + 376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** linepos = (hexti->Line & EXTI_PIN_MASK); + 594 .loc 1 376 19 + 595 001e 7B68 ldr r3, [r7, #4] + 596 0020 1B68 ldr r3, [r3] + 597 .loc 1 376 11 + 598 0022 03F01F03 and r3, r3, #31 + ARM GAS /tmp/cc2L1WXV.s page 18 + + + 599 0026 BB61 str r3, [r7, #24] + 377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** maskline = (1uL << linepos); + 600 .loc 1 377 12 + 601 0028 0122 movs r2, #1 + 602 002a BB69 ldr r3, [r7, #24] + 603 002c 02FA03F3 lsl r3, r2, r3 + 604 0030 7B61 str r3, [r7, #20] + 378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* 1] Clear interrupt mode */ + 380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regaddr = (&EXTI->IMR + (EXTI_MODE_OFFSET * offset)); + 605 .loc 1 380 25 + 606 0032 FB69 ldr r3, [r7, #28] + 607 0034 5B01 lsls r3, r3, #5 + 608 .loc 1 380 11 + 609 0036 03F18043 add r3, r3, #1073741824 + 610 003a 03F58233 add r3, r3, #66560 + 611 003e 3B61 str r3, [r7, #16] + 381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval = (*regaddr & ~maskline); + 612 .loc 1 381 13 + 613 0040 3B69 ldr r3, [r7, #16] + 614 0042 1A68 ldr r2, [r3] + 615 .loc 1 381 24 + 616 0044 7B69 ldr r3, [r7, #20] + 617 0046 DB43 mvns r3, r3 + 618 .loc 1 381 10 + 619 0048 1340 ands r3, r3, r2 + 620 004a FB60 str r3, [r7, #12] + 382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** *regaddr = regval; + 621 .loc 1 382 12 + 622 004c 3B69 ldr r3, [r7, #16] + 623 004e FA68 ldr r2, [r7, #12] + 624 0050 1A60 str r2, [r3] + 383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* 2] Clear event mode */ + 385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regaddr = (&EXTI->EMR + (EXTI_MODE_OFFSET * offset)); + 625 .loc 1 385 25 + 626 0052 FB69 ldr r3, [r7, #28] + 627 0054 5A01 lsls r2, r3, #5 + 628 .loc 1 385 11 + 629 0056 2A4B ldr r3, .L32 + 630 0058 1344 add r3, r3, r2 + 631 005a 3B61 str r3, [r7, #16] + 386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval = (*regaddr & ~maskline); + 632 .loc 1 386 13 + 633 005c 3B69 ldr r3, [r7, #16] + 634 005e 1A68 ldr r2, [r3] + 635 .loc 1 386 24 + 636 0060 7B69 ldr r3, [r7, #20] + 637 0062 DB43 mvns r3, r3 + 638 .loc 1 386 10 + 639 0064 1340 ands r3, r3, r2 + 640 0066 FB60 str r3, [r7, #12] + 387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** *regaddr = regval; + 641 .loc 1 387 12 + 642 0068 3B69 ldr r3, [r7, #16] + 643 006a FA68 ldr r2, [r7, #12] + 644 006c 1A60 str r2, [r3] + ARM GAS /tmp/cc2L1WXV.s page 19 + + + 388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* 3] Clear triggers in case of configurable lines */ + 390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** if ((hexti->Line & EXTI_CONFIG) != 0x00u) + 645 .loc 1 390 13 + 646 006e 7B68 ldr r3, [r7, #4] + 647 0070 1B68 ldr r3, [r3] + 648 .loc 1 390 20 + 649 0072 03F00073 and r3, r3, #33554432 + 650 .loc 1 390 6 + 651 0076 002B cmp r3, #0 + 652 0078 3BD0 beq .L31 + 391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regaddr = (&EXTI->RTSR + (EXTI_CONFIG_OFFSET * offset)); + 653 .loc 1 392 28 + 654 007a FB69 ldr r3, [r7, #28] + 655 007c 5A01 lsls r2, r3, #5 + 656 .loc 1 392 13 + 657 007e 214B ldr r3, .L32+4 + 658 0080 1344 add r3, r3, r2 + 659 0082 3B61 str r3, [r7, #16] + 393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval = (*regaddr & ~maskline); + 660 .loc 1 393 15 + 661 0084 3B69 ldr r3, [r7, #16] + 662 0086 1A68 ldr r2, [r3] + 663 .loc 1 393 26 + 664 0088 7B69 ldr r3, [r7, #20] + 665 008a DB43 mvns r3, r3 + 666 .loc 1 393 12 + 667 008c 1340 ands r3, r3, r2 + 668 008e FB60 str r3, [r7, #12] + 394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** *regaddr = regval; + 669 .loc 1 394 14 + 670 0090 3B69 ldr r3, [r7, #16] + 671 0092 FA68 ldr r2, [r7, #12] + 672 0094 1A60 str r2, [r3] + 395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regaddr = (&EXTI->FTSR + (EXTI_CONFIG_OFFSET * offset)); + 673 .loc 1 396 28 + 674 0096 FB69 ldr r3, [r7, #28] + 675 0098 5A01 lsls r2, r3, #5 + 676 .loc 1 396 13 + 677 009a 1B4B ldr r3, .L32+8 + 678 009c 1344 add r3, r3, r2 + 679 009e 3B61 str r3, [r7, #16] + 397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval = (*regaddr & ~maskline); + 680 .loc 1 397 15 + 681 00a0 3B69 ldr r3, [r7, #16] + 682 00a2 1A68 ldr r2, [r3] + 683 .loc 1 397 26 + 684 00a4 7B69 ldr r3, [r7, #20] + 685 00a6 DB43 mvns r3, r3 + 686 .loc 1 397 12 + 687 00a8 1340 ands r3, r3, r2 + 688 00aa FB60 str r3, [r7, #12] + 398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** *regaddr = regval; + 689 .loc 1 398 14 + 690 00ac 3B69 ldr r3, [r7, #16] + ARM GAS /tmp/cc2L1WXV.s page 20 + + + 691 00ae FA68 ldr r2, [r7, #12] + 692 00b0 1A60 str r2, [r3] + 399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Get Gpio port selection for gpio lines */ + 401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO) + 693 .loc 1 401 15 + 694 00b2 7B68 ldr r3, [r7, #4] + 695 00b4 1B68 ldr r3, [r3] + 696 .loc 1 401 22 + 697 00b6 03F0C063 and r3, r3, #100663296 + 698 .loc 1 401 8 + 699 00ba B3F1C06F cmp r3, #100663296 + 700 00be 18D1 bne .L31 + 402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** assert_param(IS_EXTI_GPIO_PIN(linepos)); + 404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval = SYSCFG->EXTICR[linepos >> 2u]; + 701 .loc 1 405 22 + 702 00c0 124A ldr r2, .L32+12 + 703 .loc 1 405 39 + 704 00c2 BB69 ldr r3, [r7, #24] + 705 00c4 9B08 lsrs r3, r3, #2 + 706 .loc 1 405 14 + 707 00c6 0233 adds r3, r3, #2 + 708 00c8 52F82330 ldr r3, [r2, r3, lsl #2] + 709 00cc FB60 str r3, [r7, #12] + 406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + 710 .loc 1 406 80 + 711 00ce BB69 ldr r3, [r7, #24] + 712 00d0 03F00303 and r3, r3, #3 + 713 .loc 1 406 69 + 714 00d4 9B00 lsls r3, r3, #2 + 715 .loc 1 406 40 + 716 00d6 0F22 movs r2, #15 + 717 00d8 02FA03F3 lsl r3, r2, r3 + 718 .loc 1 406 17 + 719 00dc DB43 mvns r3, r3 + 720 .loc 1 406 14 + 721 00de FA68 ldr r2, [r7, #12] + 722 00e0 1340 ands r3, r3, r2 + 723 00e2 FB60 str r3, [r7, #12] + 407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** SYSCFG->EXTICR[linepos >> 2u] = regval; + 724 .loc 1 407 13 + 725 00e4 0949 ldr r1, .L32+12 + 726 .loc 1 407 30 + 727 00e6 BB69 ldr r3, [r7, #24] + 728 00e8 9B08 lsrs r3, r3, #2 + 729 .loc 1 407 37 + 730 00ea 0233 adds r3, r3, #2 + 731 00ec FA68 ldr r2, [r7, #12] + 732 00ee 41F82320 str r2, [r1, r3, lsl #2] + 733 .L31: + 408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** return HAL_OK; + 734 .loc 1 411 10 + ARM GAS /tmp/cc2L1WXV.s page 21 + + + 735 00f2 0023 movs r3, #0 + 736 .L30: + 412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 737 .loc 1 412 1 + 738 00f4 1846 mov r0, r3 + 739 00f6 2437 adds r7, r7, #36 + 740 .cfi_def_cfa_offset 4 + 741 00f8 BD46 mov sp, r7 + 742 .cfi_def_cfa_register 13 + 743 @ sp needed + 744 00fa 5DF8047B ldr r7, [sp], #4 + 745 .cfi_restore 7 + 746 .cfi_def_cfa_offset 0 + 747 00fe 7047 bx lr + 748 .L33: + 749 .align 2 + 750 .L32: + 751 0100 04040140 .word 1073808388 + 752 0104 08040140 .word 1073808392 + 753 0108 0C040140 .word 1073808396 + 754 010c 00000140 .word 1073807360 + 755 .cfi_endproc + 756 .LFE132: + 758 .section .text.HAL_EXTI_RegisterCallback,"ax",%progbits + 759 .align 1 + 760 .global HAL_EXTI_RegisterCallback + 761 .syntax unified + 762 .thumb + 763 .thumb_func + 765 HAL_EXTI_RegisterCallback: + 766 .LFB133: + 413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /** + 415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @brief Register callback for a dedicated Exti line. + 416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @param hexti Exti handle. + 417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @param CallbackID User callback identifier. + 418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values. + 419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @param pPendingCbfn function pointer to be stored as callback. + 420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @retval HAL Status. + 421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** */ + 422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef Callb + 423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 767 .loc 1 423 1 + 768 .cfi_startproc + 769 @ args = 0, pretend = 0, frame = 24 + 770 @ frame_needed = 1, uses_anonymous_args = 0 + 771 @ link register save eliminated. + 772 0000 80B4 push {r7} + 773 .cfi_def_cfa_offset 4 + 774 .cfi_offset 7, -4 + 775 0002 87B0 sub sp, sp, #28 + 776 .cfi_def_cfa_offset 32 + 777 0004 00AF add r7, sp, #0 + 778 .cfi_def_cfa_register 7 + 779 0006 F860 str r0, [r7, #12] + 780 0008 0B46 mov r3, r1 + 781 000a 7A60 str r2, [r7, #4] + ARM GAS /tmp/cc2L1WXV.s page 22 + + + 782 000c FB72 strb r3, [r7, #11] + 424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** HAL_StatusTypeDef status = HAL_OK; + 783 .loc 1 424 21 + 784 000e 0023 movs r3, #0 + 785 0010 FB75 strb r3, [r7, #23] + 425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** switch (CallbackID) + 786 .loc 1 426 3 + 787 0012 FB7A ldrb r3, [r7, #11] @ zero_extendqisi2 + 788 0014 002B cmp r3, #0 + 789 0016 03D1 bne .L35 + 427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** case HAL_EXTI_COMMON_CB_ID: + 429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** hexti->PendingCallback = pPendingCbfn; + 790 .loc 1 429 30 + 791 0018 FB68 ldr r3, [r7, #12] + 792 001a 7A68 ldr r2, [r7, #4] + 793 001c 5A60 str r2, [r3, #4] + 430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** break; + 794 .loc 1 430 7 + 795 001e 02E0 b .L36 + 796 .L35: + 431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** default: + 433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** status = HAL_ERROR; + 797 .loc 1 433 14 + 798 0020 0123 movs r3, #1 + 799 0022 FB75 strb r3, [r7, #23] + 434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** break; + 800 .loc 1 434 7 + 801 0024 00BF nop + 802 .L36: + 435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** return status; + 803 .loc 1 437 10 + 804 0026 FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 805 .loc 1 438 1 + 806 0028 1846 mov r0, r3 + 807 002a 1C37 adds r7, r7, #28 + 808 .cfi_def_cfa_offset 4 + 809 002c BD46 mov sp, r7 + 810 .cfi_def_cfa_register 13 + 811 @ sp needed + 812 002e 5DF8047B ldr r7, [sp], #4 + 813 .cfi_restore 7 + 814 .cfi_def_cfa_offset 0 + 815 0032 7047 bx lr + 816 .cfi_endproc + 817 .LFE133: + 819 .section .text.HAL_EXTI_GetHandle,"ax",%progbits + 820 .align 1 + 821 .global HAL_EXTI_GetHandle + 822 .syntax unified + 823 .thumb + 824 .thumb_func + ARM GAS /tmp/cc2L1WXV.s page 23 + + + 826 HAL_EXTI_GetHandle: + 827 .LFB134: + 439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /** + 441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @brief Store line number as handle private field. + 442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @param hexti Exti handle. + 443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @param ExtiLine Exti line number. + 444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * This parameter can be from 0 to @ref EXTI_LINE_NB. + 445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @retval HAL Status. + 446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** */ + 447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine) + 448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 828 .loc 1 448 1 + 829 .cfi_startproc + 830 @ args = 0, pretend = 0, frame = 8 + 831 @ frame_needed = 1, uses_anonymous_args = 0 + 832 @ link register save eliminated. + 833 0000 80B4 push {r7} + 834 .cfi_def_cfa_offset 4 + 835 .cfi_offset 7, -4 + 836 0002 83B0 sub sp, sp, #12 + 837 .cfi_def_cfa_offset 16 + 838 0004 00AF add r7, sp, #0 + 839 .cfi_def_cfa_register 7 + 840 0006 7860 str r0, [r7, #4] + 841 0008 3960 str r1, [r7] + 449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Check the parameters */ + 450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** assert_param(IS_EXTI_LINE(ExtiLine)); + 451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Check null pointer */ + 453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** if (hexti == NULL) + 842 .loc 1 453 6 + 843 000a 7B68 ldr r3, [r7, #4] + 844 000c 002B cmp r3, #0 + 845 000e 01D1 bne .L39 + 454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** return HAL_ERROR; + 846 .loc 1 455 12 + 847 0010 0123 movs r3, #1 + 848 0012 03E0 b .L40 + 849 .L39: + 456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** else + 458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Store line number as handle private field */ + 460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** hexti->Line = ExtiLine; + 850 .loc 1 460 17 + 851 0014 7B68 ldr r3, [r7, #4] + 852 0016 3A68 ldr r2, [r7] + 853 0018 1A60 str r2, [r3] + 461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** return HAL_OK; + 854 .loc 1 462 12 + 855 001a 0023 movs r3, #0 + 856 .L40: + 463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + ARM GAS /tmp/cc2L1WXV.s page 24 + + + 857 .loc 1 464 1 + 858 001c 1846 mov r0, r3 + 859 001e 0C37 adds r7, r7, #12 + 860 .cfi_def_cfa_offset 4 + 861 0020 BD46 mov sp, r7 + 862 .cfi_def_cfa_register 13 + 863 @ sp needed + 864 0022 5DF8047B ldr r7, [sp], #4 + 865 .cfi_restore 7 + 866 .cfi_def_cfa_offset 0 + 867 0026 7047 bx lr + 868 .cfi_endproc + 869 .LFE134: + 871 .section .text.HAL_EXTI_IRQHandler,"ax",%progbits + 872 .align 1 + 873 .global HAL_EXTI_IRQHandler + 874 .syntax unified + 875 .thumb + 876 .thumb_func + 878 HAL_EXTI_IRQHandler: + 879 .LFB135: + 465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /** + 467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @} + 468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** */ + 469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /** @addtogroup EXTI_Exported_Functions_Group2 + 471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @brief EXTI IO functions. + 472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * + 473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** @verbatim + 474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** =============================================================================== + 475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** ##### IO operation functions ##### + 476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** =============================================================================== + 477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** @endverbatim + 479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @{ + 480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** */ + 481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /** + 483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @brief Handle EXTI interrupt request. + 484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @param hexti Exti handle. + 485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @retval none. + 486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** */ + 487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) + 488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 880 .loc 1 488 1 + 881 .cfi_startproc + 882 @ args = 0, pretend = 0, frame = 24 + 883 @ frame_needed = 1, uses_anonymous_args = 0 + 884 0000 80B5 push {r7, lr} + 885 .cfi_def_cfa_offset 8 + 886 .cfi_offset 7, -8 + 887 .cfi_offset 14, -4 + 888 0002 86B0 sub sp, sp, #24 + 889 .cfi_def_cfa_offset 32 + 890 0004 00AF add r7, sp, #0 + 891 .cfi_def_cfa_register 7 + ARM GAS /tmp/cc2L1WXV.s page 25 + + + 892 0006 7860 str r0, [r7, #4] + 489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** __IO uint32_t *regaddr; + 490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** uint32_t regval; + 491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** uint32_t maskline; + 492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** uint32_t offset; + 493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Compute line register offset and line mask */ + 495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + 893 .loc 1 495 19 + 894 0008 7B68 ldr r3, [r7, #4] + 895 000a 1B68 ldr r3, [r3] + 896 .loc 1 495 43 + 897 000c 1B0C lsrs r3, r3, #16 + 898 .loc 1 495 10 + 899 000e 03F00103 and r3, r3, #1 + 900 0012 7B61 str r3, [r7, #20] + 496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + 901 .loc 1 496 28 + 902 0014 7B68 ldr r3, [r7, #4] + 903 0016 1B68 ldr r3, [r3] + 904 .loc 1 496 35 + 905 0018 03F01F03 and r3, r3, #31 + 906 .loc 1 496 12 + 907 001c 0122 movs r2, #1 + 908 001e 02FA03F3 lsl r3, r2, r3 + 909 0022 3B61 str r3, [r7, #16] + 497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Get pending bit */ + 499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regaddr = (&EXTI->PR + (EXTI_CONFIG_OFFSET * offset)); + 910 .loc 1 499 24 + 911 0024 7B69 ldr r3, [r7, #20] + 912 0026 5A01 lsls r2, r3, #5 + 913 .loc 1 499 11 + 914 0028 0C4B ldr r3, .L44 + 915 002a 1344 add r3, r3, r2 + 916 002c FB60 str r3, [r7, #12] + 500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval = (*regaddr & maskline); + 917 .loc 1 500 13 + 918 002e FB68 ldr r3, [r7, #12] + 919 0030 1B68 ldr r3, [r3] + 920 .loc 1 500 10 + 921 0032 3A69 ldr r2, [r7, #16] + 922 0034 1340 ands r3, r3, r2 + 923 0036 BB60 str r3, [r7, #8] + 501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** if (regval != 0x00u) + 924 .loc 1 502 6 + 925 0038 BB68 ldr r3, [r7, #8] + 926 003a 002B cmp r3, #0 + 927 003c 09D0 beq .L43 + 503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Clear pending bit */ + 505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** EXTI->PR = maskline; + 928 .loc 1 505 9 + 929 003e 084A ldr r2, .L44+4 + 930 .loc 1 505 14 + 931 0040 3B69 ldr r3, [r7, #16] + ARM GAS /tmp/cc2L1WXV.s page 26 + + + 932 0042 5361 str r3, [r2, #20] + 506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Call callback */ + 508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** if (hexti->PendingCallback != NULL) + 933 .loc 1 508 14 + 934 0044 7B68 ldr r3, [r7, #4] + 935 0046 5B68 ldr r3, [r3, #4] + 936 .loc 1 508 8 + 937 0048 002B cmp r3, #0 + 938 004a 02D0 beq .L43 + 509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** hexti->PendingCallback(); + 939 .loc 1 510 12 + 940 004c 7B68 ldr r3, [r7, #4] + 941 004e 5B68 ldr r3, [r3, #4] + 942 .loc 1 510 7 + 943 0050 9847 blx r3 + 944 .LVL0: + 945 .L43: + 511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 946 .loc 1 513 1 + 947 0052 00BF nop + 948 0054 1837 adds r7, r7, #24 + 949 .cfi_def_cfa_offset 8 + 950 0056 BD46 mov sp, r7 + 951 .cfi_def_cfa_register 13 + 952 @ sp needed + 953 0058 80BD pop {r7, pc} + 954 .L45: + 955 005a 00BF .align 2 + 956 .L44: + 957 005c 14040140 .word 1073808404 + 958 0060 00040140 .word 1073808384 + 959 .cfi_endproc + 960 .LFE135: + 962 .section .text.HAL_EXTI_GetPending,"ax",%progbits + 963 .align 1 + 964 .global HAL_EXTI_GetPending + 965 .syntax unified + 966 .thumb + 967 .thumb_func + 969 HAL_EXTI_GetPending: + 970 .LFB136: + 514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /** + 516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @brief Get interrupt pending bit of a dedicated line. + 517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @param hexti Exti handle. + 518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @param Edge Specify which pending edge as to be checked. + 519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * This parameter can be one of the following values: + 520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @arg @ref EXTI_TRIGGER_RISING_FALLING + 521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * This parameter is kept for compatibility with other series. + 522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @retval 1 if interrupt is pending else 0. + 523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** */ + 524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) + 525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + ARM GAS /tmp/cc2L1WXV.s page 27 + + + 971 .loc 1 525 1 + 972 .cfi_startproc + 973 @ args = 0, pretend = 0, frame = 32 + 974 @ frame_needed = 1, uses_anonymous_args = 0 + 975 @ link register save eliminated. + 976 0000 80B4 push {r7} + 977 .cfi_def_cfa_offset 4 + 978 .cfi_offset 7, -4 + 979 0002 89B0 sub sp, sp, #36 + 980 .cfi_def_cfa_offset 40 + 981 0004 00AF add r7, sp, #0 + 982 .cfi_def_cfa_register 7 + 983 0006 7860 str r0, [r7, #4] + 984 0008 3960 str r1, [r7] + 526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** __IO uint32_t *regaddr; + 527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** uint32_t regval; + 528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** uint32_t linepos; + 529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** uint32_t maskline; + 530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** uint32_t offset; + 531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Check parameters */ + 533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** assert_param(IS_EXTI_LINE(hexti->Line)); + 534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + 535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** assert_param(IS_EXTI_PENDING_EDGE(Edge)); + 536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* compute line register offset and line mask */ + 538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + 985 .loc 1 538 19 + 986 000a 7B68 ldr r3, [r7, #4] + 987 000c 1B68 ldr r3, [r3] + 988 .loc 1 538 43 + 989 000e 1B0C lsrs r3, r3, #16 + 990 .loc 1 538 10 + 991 0010 03F00103 and r3, r3, #1 + 992 0014 FB61 str r3, [r7, #28] + 539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** linepos = (hexti->Line & EXTI_PIN_MASK); + 993 .loc 1 539 19 + 994 0016 7B68 ldr r3, [r7, #4] + 995 0018 1B68 ldr r3, [r3] + 996 .loc 1 539 11 + 997 001a 03F01F03 and r3, r3, #31 + 998 001e BB61 str r3, [r7, #24] + 540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** maskline = (1uL << linepos); + 999 .loc 1 540 12 + 1000 0020 0122 movs r2, #1 + 1001 0022 BB69 ldr r3, [r7, #24] + 1002 0024 02FA03F3 lsl r3, r2, r3 + 1003 0028 7B61 str r3, [r7, #20] + 541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Get pending bit */ + 543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regaddr = (&EXTI->PR + (EXTI_CONFIG_OFFSET * offset)); + 1004 .loc 1 543 24 + 1005 002a FB69 ldr r3, [r7, #28] + 1006 002c 5A01 lsls r2, r3, #5 + 1007 .loc 1 543 11 + 1008 002e 094B ldr r3, .L48 + 1009 0030 1344 add r3, r3, r2 + ARM GAS /tmp/cc2L1WXV.s page 28 + + + 1010 0032 3B61 str r3, [r7, #16] + 544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* return 1 if bit is set else 0 */ + 545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regval = ((*regaddr & maskline) >> linepos); + 1011 .loc 1 545 14 + 1012 0034 3B69 ldr r3, [r7, #16] + 1013 0036 1A68 ldr r2, [r3] + 1014 .loc 1 545 23 + 1015 0038 7B69 ldr r3, [r7, #20] + 1016 003a 1A40 ands r2, r2, r3 + 1017 .loc 1 545 10 + 1018 003c BB69 ldr r3, [r7, #24] + 1019 003e 22FA03F3 lsr r3, r2, r3 + 1020 0042 FB60 str r3, [r7, #12] + 546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** return regval; + 1021 .loc 1 546 10 + 1022 0044 FB68 ldr r3, [r7, #12] + 547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 1023 .loc 1 547 1 + 1024 0046 1846 mov r0, r3 + 1025 0048 2437 adds r7, r7, #36 + 1026 .cfi_def_cfa_offset 4 + 1027 004a BD46 mov sp, r7 + 1028 .cfi_def_cfa_register 13 + 1029 @ sp needed + 1030 004c 5DF8047B ldr r7, [sp], #4 + 1031 .cfi_restore 7 + 1032 .cfi_def_cfa_offset 0 + 1033 0050 7047 bx lr + 1034 .L49: + 1035 0052 00BF .align 2 + 1036 .L48: + 1037 0054 14040140 .word 1073808404 + 1038 .cfi_endproc + 1039 .LFE136: + 1041 .section .text.HAL_EXTI_ClearPending,"ax",%progbits + 1042 .align 1 + 1043 .global HAL_EXTI_ClearPending + 1044 .syntax unified + 1045 .thumb + 1046 .thumb_func + 1048 HAL_EXTI_ClearPending: + 1049 .LFB137: + 548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /** + 550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @brief Clear interrupt pending bit of a dedicated line. + 551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @param hexti Exti handle. + 552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @param Edge Specify which pending edge as to be clear. + 553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * This parameter can be one of the following values: + 554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @arg @ref EXTI_TRIGGER_RISING_FALLING + 555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * This parameter is kept for compatibility with other series. + 556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @retval None. + 557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** */ + 558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) + 559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 1050 .loc 1 559 1 + 1051 .cfi_startproc + 1052 @ args = 0, pretend = 0, frame = 24 + ARM GAS /tmp/cc2L1WXV.s page 29 + + + 1053 @ frame_needed = 1, uses_anonymous_args = 0 + 1054 @ link register save eliminated. + 1055 0000 80B4 push {r7} + 1056 .cfi_def_cfa_offset 4 + 1057 .cfi_offset 7, -4 + 1058 0002 87B0 sub sp, sp, #28 + 1059 .cfi_def_cfa_offset 32 + 1060 0004 00AF add r7, sp, #0 + 1061 .cfi_def_cfa_register 7 + 1062 0006 7860 str r0, [r7, #4] + 1063 0008 3960 str r1, [r7] + 560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** __IO uint32_t *regaddr; + 561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** uint32_t maskline; + 562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** uint32_t offset; + 563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Check parameters */ + 565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** assert_param(IS_EXTI_LINE(hexti->Line)); + 566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + 567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** assert_param(IS_EXTI_PENDING_EDGE(Edge)); + 568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* compute line register offset and line mask */ + 570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + 1064 .loc 1 570 19 + 1065 000a 7B68 ldr r3, [r7, #4] + 1066 000c 1B68 ldr r3, [r3] + 1067 .loc 1 570 43 + 1068 000e 1B0C lsrs r3, r3, #16 + 1069 .loc 1 570 10 + 1070 0010 03F00103 and r3, r3, #1 + 1071 0014 7B61 str r3, [r7, #20] + 571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + 1072 .loc 1 571 28 + 1073 0016 7B68 ldr r3, [r7, #4] + 1074 0018 1B68 ldr r3, [r3] + 1075 .loc 1 571 35 + 1076 001a 03F01F03 and r3, r3, #31 + 1077 .loc 1 571 12 + 1078 001e 0122 movs r2, #1 + 1079 0020 02FA03F3 lsl r3, r2, r3 + 1080 0024 3B61 str r3, [r7, #16] + 572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Get pending bit */ + 574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regaddr = (&EXTI->PR + (EXTI_CONFIG_OFFSET * offset)); + 1081 .loc 1 574 24 + 1082 0026 7B69 ldr r3, [r7, #20] + 1083 0028 5A01 lsls r2, r3, #5 + 1084 .loc 1 574 11 + 1085 002a 064B ldr r3, .L51 + 1086 002c 1344 add r3, r3, r2 + 1087 002e FB60 str r3, [r7, #12] + 575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Clear Pending bit */ + 577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** *regaddr = maskline; + 1088 .loc 1 577 12 + 1089 0030 FB68 ldr r3, [r7, #12] + 1090 0032 3A69 ldr r2, [r7, #16] + 1091 0034 1A60 str r2, [r3] + ARM GAS /tmp/cc2L1WXV.s page 30 + + + 578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 1092 .loc 1 578 1 + 1093 0036 00BF nop + 1094 0038 1C37 adds r7, r7, #28 + 1095 .cfi_def_cfa_offset 4 + 1096 003a BD46 mov sp, r7 + 1097 .cfi_def_cfa_register 13 + 1098 @ sp needed + 1099 003c 5DF8047B ldr r7, [sp], #4 + 1100 .cfi_restore 7 + 1101 .cfi_def_cfa_offset 0 + 1102 0040 7047 bx lr + 1103 .L52: + 1104 0042 00BF .align 2 + 1105 .L51: + 1106 0044 14040140 .word 1073808404 + 1107 .cfi_endproc + 1108 .LFE137: + 1110 .section .text.HAL_EXTI_GenerateSWI,"ax",%progbits + 1111 .align 1 + 1112 .global HAL_EXTI_GenerateSWI + 1113 .syntax unified + 1114 .thumb + 1115 .thumb_func + 1117 HAL_EXTI_GenerateSWI: + 1118 .LFB138: + 579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /** + 581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @brief Generate a software interrupt for a dedicated line. + 582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @param hexti Exti handle. + 583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** * @retval None. + 584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** */ + 585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) + 586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** { + 1119 .loc 1 586 1 + 1120 .cfi_startproc + 1121 @ args = 0, pretend = 0, frame = 24 + 1122 @ frame_needed = 1, uses_anonymous_args = 0 + 1123 @ link register save eliminated. + 1124 0000 80B4 push {r7} + 1125 .cfi_def_cfa_offset 4 + 1126 .cfi_offset 7, -4 + 1127 0002 87B0 sub sp, sp, #28 + 1128 .cfi_def_cfa_offset 32 + 1129 0004 00AF add r7, sp, #0 + 1130 .cfi_def_cfa_register 7 + 1131 0006 7860 str r0, [r7, #4] + 587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** __IO uint32_t *regaddr; + 588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** uint32_t maskline; + 589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** uint32_t offset; + 590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* Check parameters */ + 592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** assert_param(IS_EXTI_LINE(hexti->Line)); + 593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + 594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** /* compute line register offset and line mask */ + 596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); + ARM GAS /tmp/cc2L1WXV.s page 31 + + + 1132 .loc 1 596 19 + 1133 0008 7B68 ldr r3, [r7, #4] + 1134 000a 1B68 ldr r3, [r3] + 1135 .loc 1 596 43 + 1136 000c 1B0C lsrs r3, r3, #16 + 1137 .loc 1 596 10 + 1138 000e 03F00103 and r3, r3, #1 + 1139 0012 7B61 str r3, [r7, #20] + 597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + 1140 .loc 1 597 28 + 1141 0014 7B68 ldr r3, [r7, #4] + 1142 0016 1B68 ldr r3, [r3] + 1143 .loc 1 597 35 + 1144 0018 03F01F03 and r3, r3, #31 + 1145 .loc 1 597 12 + 1146 001c 0122 movs r2, #1 + 1147 001e 02FA03F3 lsl r3, r2, r3 + 1148 0022 3B61 str r3, [r7, #16] + 598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** + 599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** regaddr = (&EXTI->SWIER + (EXTI_CONFIG_OFFSET * offset)); + 1149 .loc 1 599 27 + 1150 0024 7B69 ldr r3, [r7, #20] + 1151 0026 5A01 lsls r2, r3, #5 + 1152 .loc 1 599 11 + 1153 0028 054B ldr r3, .L54 + 1154 002a 1344 add r3, r3, r2 + 1155 002c FB60 str r3, [r7, #12] + 600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** *regaddr = maskline; + 1156 .loc 1 600 12 + 1157 002e FB68 ldr r3, [r7, #12] + 1158 0030 3A69 ldr r2, [r7, #16] + 1159 0032 1A60 str r2, [r3] + 601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c **** } + 1160 .loc 1 601 1 + 1161 0034 00BF nop + 1162 0036 1C37 adds r7, r7, #28 + 1163 .cfi_def_cfa_offset 4 + 1164 0038 BD46 mov sp, r7 + 1165 .cfi_def_cfa_register 13 + 1166 @ sp needed + 1167 003a 5DF8047B ldr r7, [sp], #4 + 1168 .cfi_restore 7 + 1169 .cfi_def_cfa_offset 0 + 1170 003e 7047 bx lr + 1171 .L55: + 1172 .align 2 + 1173 .L54: + 1174 0040 10040140 .word 1073808400 + 1175 .cfi_endproc + 1176 .LFE138: + 1178 .text + 1179 .Letext0: + 1180 .file 2 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 1181 .file 3 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 1182 .file 4 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + 1183 .file 5 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h" + 1184 .file 6 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h" + ARM GAS /tmp/cc2L1WXV.s page 32 + + + ARM GAS /tmp/cc2L1WXV.s page 33 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f3xx_hal_exti.c + /tmp/cc2L1WXV.s:21 .text.HAL_EXTI_SetConfigLine:00000000 $t + /tmp/cc2L1WXV.s:27 .text.HAL_EXTI_SetConfigLine:00000000 HAL_EXTI_SetConfigLine + /tmp/cc2L1WXV.s:313 .text.HAL_EXTI_SetConfigLine:00000190 $d + /tmp/cc2L1WXV.s:321 .text.HAL_EXTI_GetConfigLine:00000000 $t + /tmp/cc2L1WXV.s:327 .text.HAL_EXTI_GetConfigLine:00000000 HAL_EXTI_GetConfigLine + /tmp/cc2L1WXV.s:549 .text.HAL_EXTI_GetConfigLine:00000134 $d + /tmp/cc2L1WXV.s:557 .text.HAL_EXTI_ClearConfigLine:00000000 $t + /tmp/cc2L1WXV.s:563 .text.HAL_EXTI_ClearConfigLine:00000000 HAL_EXTI_ClearConfigLine + /tmp/cc2L1WXV.s:751 .text.HAL_EXTI_ClearConfigLine:00000100 $d + /tmp/cc2L1WXV.s:759 .text.HAL_EXTI_RegisterCallback:00000000 $t + /tmp/cc2L1WXV.s:765 .text.HAL_EXTI_RegisterCallback:00000000 HAL_EXTI_RegisterCallback + /tmp/cc2L1WXV.s:820 .text.HAL_EXTI_GetHandle:00000000 $t + /tmp/cc2L1WXV.s:826 .text.HAL_EXTI_GetHandle:00000000 HAL_EXTI_GetHandle + /tmp/cc2L1WXV.s:872 .text.HAL_EXTI_IRQHandler:00000000 $t + /tmp/cc2L1WXV.s:878 .text.HAL_EXTI_IRQHandler:00000000 HAL_EXTI_IRQHandler + /tmp/cc2L1WXV.s:957 .text.HAL_EXTI_IRQHandler:0000005c $d + /tmp/cc2L1WXV.s:963 .text.HAL_EXTI_GetPending:00000000 $t + /tmp/cc2L1WXV.s:969 .text.HAL_EXTI_GetPending:00000000 HAL_EXTI_GetPending + /tmp/cc2L1WXV.s:1037 .text.HAL_EXTI_GetPending:00000054 $d + /tmp/cc2L1WXV.s:1042 .text.HAL_EXTI_ClearPending:00000000 $t + /tmp/cc2L1WXV.s:1048 .text.HAL_EXTI_ClearPending:00000000 HAL_EXTI_ClearPending + /tmp/cc2L1WXV.s:1106 .text.HAL_EXTI_ClearPending:00000044 $d + /tmp/cc2L1WXV.s:1111 .text.HAL_EXTI_GenerateSWI:00000000 $t + /tmp/cc2L1WXV.s:1117 .text.HAL_EXTI_GenerateSWI:00000000 HAL_EXTI_GenerateSWI + /tmp/cc2L1WXV.s:1174 .text.HAL_EXTI_GenerateSWI:00000040 $d + +NO UNDEFINED SYMBOLS diff --git a/Software/build/stm32f3xx_hal_exti.o b/Software/build/stm32f3xx_hal_exti.o new file mode 100644 index 0000000..15efdda Binary files /dev/null and b/Software/build/stm32f3xx_hal_exti.o differ diff --git a/Software/build/stm32f3xx_hal_flash.d b/Software/build/stm32f3xx_hal_flash.d new file mode 100644 index 0000000..86de5f9 --- /dev/null +++ b/Software/build/stm32f3xx_hal_flash.d @@ -0,0 +1,62 @@ +build/stm32f3xx_hal_flash.o: \ + Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + Core/Inc/stm32f3xx_hal_conf.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h: diff --git a/Software/build/stm32f3xx_hal_flash.lst b/Software/build/stm32f3xx_hal_flash.lst new file mode 100644 index 0000000..a7e9557 --- /dev/null +++ b/Software/build/stm32f3xx_hal_flash.lst @@ -0,0 +1,2041 @@ +ARM GAS /tmp/ccv5crZT.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 6 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "stm32f3xx_hal_flash.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c" + 20 .global pFlash + 21 .section .bss.pFlash,"aw",%nobits + 22 .align 3 + 25 pFlash: + 26 0000 00000000 .space 32 + 26 00000000 + 26 00000000 + 26 00000000 + 26 00000000 + 27 .section .text.HAL_FLASH_Program,"ax",%progbits + 28 .align 1 + 29 .global HAL_FLASH_Program + 30 .syntax unified + 31 .thumb + 32 .thumb_func + 34 HAL_FLASH_Program: + 35 .LFB130: + 1:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** + 2:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** ****************************************************************************** + 3:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @file stm32f3xx_hal_flash.c + 4:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @author MCD Application Team + 5:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @brief FLASH HAL module driver. + 6:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * functionalities of the internal FLASH memory: + 8:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * + Program operations functions + 9:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * + Memory Control functions + 10:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * + Peripheral State functions + 11:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * + 12:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** @verbatim + 13:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** ============================================================================== + 14:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** ##### FLASH peripheral features ##### + 15:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** ============================================================================== + 16:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses + 17:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** to the Flash memory. It implements the erase and program Flash memory operations + 18:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** and the read and write protection mechanisms. + 19:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 20:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** [..] The Flash memory interface accelerates code execution with a system of instruction + 21:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** prefetch. + ARM GAS /tmp/ccv5crZT.s page 2 + + + 22:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 23:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** [..] The FLASH main features are: + 24:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (+) Flash memory read operations + 25:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (+) Flash memory program/erase operations + 26:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (+) Read / write protections + 27:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (+) Prefetch on I-Code + 28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (+) Option Bytes programming + 29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 31:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** ##### How to use this driver ##### + 32:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** ============================================================================== + 33:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** [..] + 34:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** This driver provides functions and macros to configure and program the FLASH + 35:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** memory of all STM32F3xx devices. + 36:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 37:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (#) FLASH Memory I/O Programming functions: this group includes all needed + 38:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** functions to erase and program the main memory: + 39:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (++) Lock and Unlock the FLASH interface + 40:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (++) Erase function: Erase page, erase all pages + 41:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (++) Program functions: half word, word and doubleword + 42:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (#) FLASH Option Bytes Programming functions: this group includes all needed + 43:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** functions to manage the Option Bytes: + 44:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (++) Lock and Unlock the Option Bytes + 45:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (++) Set/Reset the write protection + 46:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (++) Set the Read protection Level + 47:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (++) Program the user Option Bytes + 48:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (++) Launch the Option Bytes loader + 49:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (++) Erase Option Bytes + 50:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (++) Program the data Option Bytes + 51:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (++) Get the Write protection. + 52:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (++) Get the user option bytes. + 53:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 54:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (#) Interrupts and flags management functions : this group + 55:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** includes all needed functions to: + 56:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (++) Handle FLASH interrupts + 57:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (++) Wait for last FLASH operation according to its status + 58:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (++) Get error flag status + 59:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 60:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** [..] In addition to these function, this driver includes a set of macros allowing + 61:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** to handle the following operations: + 62:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 63:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (+) Set/Get the latency + 64:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (+) Enable/Disable the prefetch buffer + 65:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (+) Enable/Disable the half cycle access + 66:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (+) Enable/Disable the FLASH interrupts + 67:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** (+) Monitor the FLASH flags status + 68:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 69:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** @endverbatim + 70:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** ****************************************************************************** + 71:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @attention + 72:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * + 73:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * Copyright (c) 2016 STMicroelectronics. + 74:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * All rights reserved. + 75:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * + 76:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * This software is licensed under terms that can be found in the LICENSE file in + 77:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * the root directory of this software component. + 78:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + ARM GAS /tmp/ccv5crZT.s page 3 + + + 79:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** ****************************************************************************** + 80:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 81:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 82:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Includes ------------------------------------------------------------------*/ + 83:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** #include "stm32f3xx_hal.h" + 84:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** @addtogroup STM32F3xx_HAL_Driver + 86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @{ + 87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 88:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 89:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** #ifdef HAL_FLASH_MODULE_ENABLED + 90:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 91:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** @defgroup FLASH FLASH + 92:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @brief FLASH HAL module driver + 93:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @{ + 94:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 95:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 96:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Private typedef -----------------------------------------------------------*/ + 97:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Private define ------------------------------------------------------------*/ + 98:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** @defgroup FLASH_Private_Constants FLASH Private Constants + 99:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @{ + 100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** + 102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @} + 103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Private macro ---------------------------- ---------------------------------*/ + 106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** @defgroup FLASH_Private_Macros FLASH Private Macros + 107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @{ + 108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** + 111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @} + 112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Private variables ---------------------------------------------------------*/ + 115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** @defgroup FLASH_Private_Variables FLASH Private Variables + 116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @{ + 117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Variables used for Erase pages under interruption*/ + 119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** FLASH_ProcessTypeDef pFlash; + 120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** + 121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @} + 122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Private function prototypes -----------------------------------------------*/ + 125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** @defgroup FLASH_Private_Functions FLASH Private Functions + 126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @{ + 127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data); + 129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** static void FLASH_SetErrorCode(void); + 130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** extern void FLASH_PageErase(uint32_t PageAddress); + 131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** + 132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @} + 133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Exported functions ---------------------------------------------------------*/ + ARM GAS /tmp/ccv5crZT.s page 4 + + + 136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** @defgroup FLASH_Exported_Functions FLASH Exported Functions + 137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @{ + 138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions + 141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @brief Programming operation functions + 142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * + 143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** @verbatim + 144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** @endverbatim + 145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @{ + 146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** + 149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @brief Program halfword, word or double word at a specified address + 150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface + 151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface + 152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * + 153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @note If an erase and a program operations are requested simultaneously, + 154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * the erase operation is performed before the program one. + 155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * + 156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @note FLASH should be previously erased before new programming (only exception to this + 157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * is when 0x0000 is programmed) + 158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * + 159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @param TypeProgram Indicate the way to program at a specified address. + 160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * This parameter can be a value of @ref FLASH_Type_Program + 161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @param Address Specifie the address to be programmed. + 162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @param Data Specifie the data to be programmed + 163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * + 164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @retval HAL_StatusTypeDef HAL Status + 165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) + 167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 36 .loc 1 167 1 + 37 .cfi_startproc + 38 @ args = 0, pretend = 0, frame = 24 + 39 @ frame_needed = 1, uses_anonymous_args = 0 + 40 0000 F0B5 push {r4, r5, r6, r7, lr} + 41 .cfi_def_cfa_offset 20 + 42 .cfi_offset 4, -20 + 43 .cfi_offset 5, -16 + 44 .cfi_offset 6, -12 + 45 .cfi_offset 7, -8 + 46 .cfi_offset 14, -4 + 47 0002 87B0 sub sp, sp, #28 + 48 .cfi_def_cfa_offset 48 + 49 0004 00AF add r7, sp, #0 + 50 .cfi_def_cfa_register 7 + 51 0006 F860 str r0, [r7, #12] + 52 0008 B960 str r1, [r7, #8] + 53 000a C7E90023 strd r2, [r7] + 168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** HAL_StatusTypeDef status = HAL_ERROR; + 54 .loc 1 168 21 + 55 000e 0123 movs r3, #1 + 56 0010 FB75 strb r3, [r7, #23] + 169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** uint8_t index = 0U; + 57 .loc 1 169 11 + 58 0012 0023 movs r3, #0 + ARM GAS /tmp/ccv5crZT.s page 5 + + + 59 0014 BB75 strb r3, [r7, #22] + 170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** uint8_t nbiterations = 0U; + 60 .loc 1 170 11 + 61 0016 0023 movs r3, #0 + 62 0018 7B75 strb r3, [r7, #21] + 171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Process Locked */ + 173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** __HAL_LOCK(&pFlash); + 63 .loc 1 173 3 + 64 001a 2F4B ldr r3, .L12 + 65 001c 1B7E ldrb r3, [r3, #24] @ zero_extendqisi2 + 66 001e 012B cmp r3, #1 + 67 0020 01D1 bne .L2 + 68 .loc 1 173 3 is_stmt 0 discriminator 1 + 69 0022 0223 movs r3, #2 + 70 .loc 1 173 3 + 71 0024 54E0 b .L3 + 72 .L2: + 73 .loc 1 173 3 discriminator 2 + 74 0026 2C4B ldr r3, .L12 + 75 0028 0122 movs r2, #1 + 76 002a 1A76 strb r2, [r3, #24] + 174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Check the parameters */ + 176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + 177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + 178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Wait for last operation to be completed */ + 180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + 77 .loc 1 180 14 is_stmt 1 + 78 002c 4CF25030 movw r0, #50000 + 79 0030 FFF7FEFF bl FLASH_WaitForLastOperation + 80 0034 0346 mov r3, r0 + 81 0036 FB75 strb r3, [r7, #23] + 181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** if(status == HAL_OK) + 82 .loc 1 182 5 + 83 0038 FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 84 003a 002B cmp r3, #0 + 85 003c 44D1 bne .L4 + 183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) + 86 .loc 1 184 7 + 87 003e FB68 ldr r3, [r7, #12] + 88 0040 012B cmp r3, #1 + 89 0042 02D1 bne .L5 + 185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Program halfword (16-bit) at a specified address. */ + 187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** nbiterations = 1U; + 90 .loc 1 187 20 + 91 0044 0123 movs r3, #1 + 92 0046 7B75 strb r3, [r7, #21] + 93 0048 07E0 b .L6 + 94 .L5: + 188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** else if(TypeProgram == FLASH_TYPEPROGRAM_WORD) + 95 .loc 1 189 12 + ARM GAS /tmp/ccv5crZT.s page 6 + + + 96 004a FB68 ldr r3, [r7, #12] + 97 004c 022B cmp r3, #2 + 98 004e 02D1 bne .L7 + 190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Program word (32-bit = 2*16-bit) at a specified address. */ + 192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** nbiterations = 2U; + 99 .loc 1 192 20 + 100 0050 0223 movs r3, #2 + 101 0052 7B75 strb r3, [r7, #21] + 102 0054 01E0 b .L6 + 103 .L7: + 193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** else + 195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Program double word (64-bit = 4*16-bit) at a specified address. */ + 197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** nbiterations = 4U; + 104 .loc 1 197 20 + 105 0056 0423 movs r3, #4 + 106 0058 7B75 strb r3, [r7, #21] + 107 .L6: + 198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** for (index = 0U; index < nbiterations; index++) + 108 .loc 1 200 16 + 109 005a 0023 movs r3, #0 + 110 005c BB75 strb r3, [r7, #22] + 111 .loc 1 200 5 + 112 005e 2DE0 b .L8 + 113 .L10: + 201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** FLASH_Program_HalfWord((Address + (2U*index)), (uint16_t)(Data >> (16U*index))); + 114 .loc 1 202 44 + 115 0060 BB7D ldrb r3, [r7, #22] @ zero_extendqisi2 + 116 0062 5A00 lsls r2, r3, #1 + 117 .loc 1 202 7 + 118 0064 BB68 ldr r3, [r7, #8] + 119 0066 02EB030C add ip, r2, r3 + 120 .loc 1 202 77 + 121 006a BB7D ldrb r3, [r7, #22] @ zero_extendqisi2 + 122 006c 1901 lsls r1, r3, #4 + 123 .loc 1 202 70 + 124 006e D7E90023 ldrd r2, [r7] + 125 0072 C1F12006 rsb r6, r1, #32 + 126 0076 A1F12000 sub r0, r1, #32 + 127 007a 22FA01F4 lsr r4, r2, r1 + 128 007e 03FA06F6 lsl r6, r3, r6 + 129 0082 3443 orrs r4, r4, r6 + 130 0084 23FA00F0 lsr r0, r3, r0 + 131 0088 0443 orrs r4, r4, r0 + 132 008a 23FA01F5 lsr r5, r3, r1 + 133 .loc 1 202 7 + 134 008e A3B2 uxth r3, r4 + 135 0090 1946 mov r1, r3 + 136 0092 6046 mov r0, ip + 137 0094 FFF7FEFF bl FLASH_Program_HalfWord + 203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Wait for last operation to be completed */ + ARM GAS /tmp/ccv5crZT.s page 7 + + + 205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + 138 .loc 1 205 18 + 139 0098 4CF25030 movw r0, #50000 + 140 009c FFF7FEFF bl FLASH_WaitForLastOperation + 141 00a0 0346 mov r3, r0 + 142 00a2 FB75 strb r3, [r7, #23] + 206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* If the program operation is completed, disable the PG Bit */ + 208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** CLEAR_BIT(FLASH->CR, FLASH_CR_PG); + 143 .loc 1 208 9 + 144 00a4 0D4B ldr r3, .L12+4 + 145 00a6 1B69 ldr r3, [r3, #16] + 146 00a8 0C4A ldr r2, .L12+4 + 147 00aa 23F00103 bic r3, r3, #1 + 148 00ae 1361 str r3, [r2, #16] + 209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* In case of error, stop programming procedure */ + 210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** if (status != HAL_OK) + 149 .loc 1 210 10 + 150 00b0 FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 151 00b2 002B cmp r3, #0 + 152 00b4 07D1 bne .L11 + 200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 153 .loc 1 200 49 discriminator 2 + 154 00b6 BB7D ldrb r3, [r7, #22] @ zero_extendqisi2 + 155 00b8 0133 adds r3, r3, #1 + 156 00ba BB75 strb r3, [r7, #22] + 157 .L8: + 200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 158 .loc 1 200 28 discriminator 1 + 159 00bc BA7D ldrb r2, [r7, #22] @ zero_extendqisi2 + 160 00be 7B7D ldrb r3, [r7, #21] @ zero_extendqisi2 + 161 00c0 9A42 cmp r2, r3 + 162 00c2 CDD3 bcc .L10 + 163 00c4 00E0 b .L4 + 164 .L11: + 211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** break; + 165 .loc 1 212 9 + 166 00c6 00BF nop + 167 .L4: + 213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Process Unlocked */ + 218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** __HAL_UNLOCK(&pFlash); + 168 .loc 1 218 3 + 169 00c8 034B ldr r3, .L12 + 170 00ca 0022 movs r2, #0 + 171 00cc 1A76 strb r2, [r3, #24] + 219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** return status; + 172 .loc 1 220 10 + 173 00ce FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 174 .L3: + 221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 175 .loc 1 221 1 + ARM GAS /tmp/ccv5crZT.s page 8 + + + 176 00d0 1846 mov r0, r3 + 177 00d2 1C37 adds r7, r7, #28 + 178 .cfi_def_cfa_offset 20 + 179 00d4 BD46 mov sp, r7 + 180 .cfi_def_cfa_register 13 + 181 @ sp needed + 182 00d6 F0BD pop {r4, r5, r6, r7, pc} + 183 .L13: + 184 .align 2 + 185 .L12: + 186 00d8 00000000 .word pFlash + 187 00dc 00200240 .word 1073881088 + 188 .cfi_endproc + 189 .LFE130: + 191 .section .text.HAL_FLASH_Program_IT,"ax",%progbits + 192 .align 1 + 193 .global HAL_FLASH_Program_IT + 194 .syntax unified + 195 .thumb + 196 .thumb_func + 198 HAL_FLASH_Program_IT: + 199 .LFB131: + 222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** + 224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @brief Program halfword, word or double word at a specified address with interrupt enabled. + 225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @note The function HAL_FLASH_Unlock() should be called before to unlock the FLASH interface + 226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * The function HAL_FLASH_Lock() should be called after to lock the FLASH interface + 227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * + 228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @note If an erase and a program operations are requested simultaneously, + 229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * the erase operation is performed before the program one. + 230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * + 231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @param TypeProgram Indicate the way to program at a specified address. + 232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * This parameter can be a value of @ref FLASH_Type_Program + 233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @param Address Specifie the address to be programmed. + 234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @param Data Specifie the data to be programmed + 235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * + 236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @retval HAL_StatusTypeDef HAL Status + 237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data) + 239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 200 .loc 1 239 1 + 201 .cfi_startproc + 202 @ args = 0, pretend = 0, frame = 24 + 203 @ frame_needed = 1, uses_anonymous_args = 0 + 204 0000 80B5 push {r7, lr} + 205 .cfi_def_cfa_offset 8 + 206 .cfi_offset 7, -8 + 207 .cfi_offset 14, -4 + 208 0002 86B0 sub sp, sp, #24 + 209 .cfi_def_cfa_offset 32 + 210 0004 00AF add r7, sp, #0 + 211 .cfi_def_cfa_register 7 + 212 0006 F860 str r0, [r7, #12] + 213 0008 B960 str r1, [r7, #8] + 214 000a C7E90023 strd r2, [r7] + 240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** HAL_StatusTypeDef status = HAL_OK; + 215 .loc 1 240 21 + ARM GAS /tmp/ccv5crZT.s page 9 + + + 216 000e 0023 movs r3, #0 + 217 0010 FB75 strb r3, [r7, #23] + 241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Process Locked */ + 243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** __HAL_LOCK(&pFlash); + 218 .loc 1 243 3 + 219 0012 1D4B ldr r3, .L20 + 220 0014 1B7E ldrb r3, [r3, #24] @ zero_extendqisi2 + 221 0016 012B cmp r3, #1 + 222 0018 01D1 bne .L15 + 223 .loc 1 243 3 is_stmt 0 discriminator 1 + 224 001a 0223 movs r3, #2 + 225 .loc 1 243 3 + 226 001c 30E0 b .L16 + 227 .L15: + 228 .loc 1 243 3 discriminator 2 + 229 001e 1A4B ldr r3, .L20 + 230 0020 0122 movs r2, #1 + 231 0022 1A76 strb r2, [r3, #24] + 244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Check the parameters */ + 246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + 247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + 248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Enable End of FLASH Operation and Error source interrupts */ + 250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); + 232 .loc 1 250 3 is_stmt 1 + 233 0024 194B ldr r3, .L20+4 + 234 0026 1B69 ldr r3, [r3, #16] + 235 0028 184A ldr r2, .L20+4 + 236 002a 43F4A053 orr r3, r3, #5120 + 237 002e 1361 str r3, [r2, #16] + 251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.Address = Address; + 238 .loc 1 252 18 + 239 0030 154A ldr r2, .L20 + 240 0032 BB68 ldr r3, [r7, #8] + 241 0034 9360 str r3, [r2, #8] + 253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.Data = Data; + 242 .loc 1 253 15 + 243 0036 1449 ldr r1, .L20 + 244 0038 D7E90023 ldrd r2, [r7] + 245 003c C1E90423 strd r2, [r1, #16] + 254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) + 246 .loc 1 255 5 + 247 0040 FB68 ldr r3, [r7, #12] + 248 0042 012B cmp r3, #1 + 249 0044 06D1 bne .L17 + 256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMHALFWORD; + 250 .loc 1 257 29 + 251 0046 104B ldr r3, .L20 + 252 0048 0322 movs r2, #3 + 253 004a 1A70 strb r2, [r3] + 258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Program halfword (16-bit) at a specified address. */ + 259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.DataRemaining = 1U; + ARM GAS /tmp/ccv5crZT.s page 10 + + + 254 .loc 1 259 26 + 255 004c 0E4B ldr r3, .L20 + 256 004e 0122 movs r2, #1 + 257 0050 5A60 str r2, [r3, #4] + 258 0052 0FE0 b .L18 + 259 .L17: + 260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** else if(TypeProgram == FLASH_TYPEPROGRAM_WORD) + 260 .loc 1 261 10 + 261 0054 FB68 ldr r3, [r7, #12] + 262 0056 022B cmp r3, #2 + 263 0058 06D1 bne .L19 + 262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMWORD; + 264 .loc 1 263 29 + 265 005a 0B4B ldr r3, .L20 + 266 005c 0422 movs r2, #4 + 267 005e 1A70 strb r2, [r3] + 264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Program word (32-bit : 2*16-bit) at a specified address. */ + 265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.DataRemaining = 2U; + 268 .loc 1 265 26 + 269 0060 094B ldr r3, .L20 + 270 0062 0222 movs r2, #2 + 271 0064 5A60 str r2, [r3, #4] + 272 0066 05E0 b .L18 + 273 .L19: + 266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** else + 268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAMDOUBLEWORD; + 274 .loc 1 269 29 + 275 0068 074B ldr r3, .L20 + 276 006a 0522 movs r2, #5 + 277 006c 1A70 strb r2, [r3] + 270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Program double word (64-bit : 4*16-bit) at a specified address. */ + 271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.DataRemaining = 4U; + 278 .loc 1 271 26 + 279 006e 064B ldr r3, .L20 + 280 0070 0422 movs r2, #4 + 281 0072 5A60 str r2, [r3, #4] + 282 .L18: + 272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Program halfword (16-bit) at a specified address. */ + 275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** FLASH_Program_HalfWord(Address, (uint16_t)Data); + 283 .loc 1 275 3 + 284 0074 3B88 ldrh r3, [r7] + 285 0076 1946 mov r1, r3 + 286 0078 B868 ldr r0, [r7, #8] + 287 007a FFF7FEFF bl FLASH_Program_HalfWord + 276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** return status; + 288 .loc 1 277 10 + 289 007e FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 290 .L16: + 278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 291 .loc 1 278 1 + ARM GAS /tmp/ccv5crZT.s page 11 + + + 292 0080 1846 mov r0, r3 + 293 0082 1837 adds r7, r7, #24 + 294 .cfi_def_cfa_offset 8 + 295 0084 BD46 mov sp, r7 + 296 .cfi_def_cfa_register 13 + 297 @ sp needed + 298 0086 80BD pop {r7, pc} + 299 .L21: + 300 .align 2 + 301 .L20: + 302 0088 00000000 .word pFlash + 303 008c 00200240 .word 1073881088 + 304 .cfi_endproc + 305 .LFE131: + 307 .section .text.HAL_FLASH_IRQHandler,"ax",%progbits + 308 .align 1 + 309 .global HAL_FLASH_IRQHandler + 310 .syntax unified + 311 .thumb + 312 .thumb_func + 314 HAL_FLASH_IRQHandler: + 315 .LFB132: + 279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** + 281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @brief This function handles FLASH interrupt request. + 282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @retval None + 283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** void HAL_FLASH_IRQHandler(void) + 285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 316 .loc 1 285 1 + 317 .cfi_startproc + 318 @ args = 0, pretend = 0, frame = 8 + 319 @ frame_needed = 1, uses_anonymous_args = 0 + 320 0000 80B5 push {r7, lr} + 321 .cfi_def_cfa_offset 8 + 322 .cfi_offset 7, -8 + 323 .cfi_offset 14, -4 + 324 0002 82B0 sub sp, sp, #8 + 325 .cfi_def_cfa_offset 16 + 326 0004 00AF add r7, sp, #0 + 327 .cfi_def_cfa_register 7 + 286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** uint32_t addresstmp = 0U; + 328 .loc 1 286 12 + 329 0006 0023 movs r3, #0 + 330 0008 7B60 str r3, [r7, #4] + 287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Check FLASH operation error flags */ + 289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) + 331 .loc 1 289 6 + 332 000a 6D4B ldr r3, .L35 + 333 000c DB68 ldr r3, [r3, #12] + 334 000e 03F01003 and r3, r3, #16 + 335 .loc 1 289 5 + 336 0012 102B cmp r3, #16 + 337 0014 05D0 beq .L23 + 338 .loc 1 289 48 discriminator 1 + 339 0016 6A4B ldr r3, .L35 + ARM GAS /tmp/ccv5crZT.s page 12 + + + 340 0018 DB68 ldr r3, [r3, #12] + 341 001a 03F00403 and r3, r3, #4 + 342 .loc 1 289 46 discriminator 1 + 343 001e 042B cmp r3, #4 + 344 0020 0ED1 bne .L24 + 345 .L23: + 290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Return the faulty address */ + 292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** addresstmp = pFlash.Address; + 346 .loc 1 292 16 + 347 0022 684B ldr r3, .L35+4 + 348 0024 9B68 ldr r3, [r3, #8] + 349 0026 7B60 str r3, [r7, #4] + 293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Reset address */ + 294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.Address = 0xFFFFFFFFU; + 350 .loc 1 294 20 + 351 0028 664B ldr r3, .L35+4 + 352 002a 4FF0FF32 mov r2, #-1 + 353 002e 9A60 str r2, [r3, #8] + 295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Save the Error code */ + 297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** FLASH_SetErrorCode(); + 354 .loc 1 297 5 + 355 0030 FFF7FEFF bl FLASH_SetErrorCode + 298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* FLASH error interrupt user callback */ + 300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** HAL_FLASH_OperationErrorCallback(addresstmp); + 356 .loc 1 300 5 + 357 0034 7868 ldr r0, [r7, #4] + 358 0036 FFF7FEFF bl HAL_FLASH_OperationErrorCallback + 301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Stop the procedure ongoing */ + 303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + 359 .loc 1 303 29 + 360 003a 624B ldr r3, .L35+4 + 361 003c 0022 movs r2, #0 + 362 003e 1A70 strb r2, [r3] + 363 .L24: + 304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Check FLASH End of Operation flag */ + 307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) + 364 .loc 1 307 6 + 365 0040 5F4B ldr r3, .L35 + 366 0042 DB68 ldr r3, [r3, #12] + 367 0044 03F02003 and r3, r3, #32 + 368 .loc 1 307 5 + 369 0048 202B cmp r3, #32 + 370 004a 40F0A080 bne .L25 + 308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Clear FLASH End of Operation pending bit */ + 310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + 371 .loc 1 310 5 + 372 004e 5C4B ldr r3, .L35 + 373 0050 2022 movs r2, #32 + 374 0052 DA60 str r2, [r3, #12] + 311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + ARM GAS /tmp/ccv5crZT.s page 13 + + + 312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Process can continue only if no error detected */ + 313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE) + 375 .loc 1 313 14 + 376 0054 5B4B ldr r3, .L35+4 + 377 0056 1B78 ldrb r3, [r3] + 378 0058 DBB2 uxtb r3, r3 + 379 .loc 1 313 7 + 380 005a 002B cmp r3, #0 + 381 005c 00F09780 beq .L25 + 314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) + 382 .loc 1 315 16 + 383 0060 584B ldr r3, .L35+4 + 384 0062 1B78 ldrb r3, [r3] + 385 0064 DBB2 uxtb r3, r3 + 386 .loc 1 315 9 + 387 0066 012B cmp r3, #1 + 388 0068 2DD1 bne .L26 + 316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Nb of pages to erased can be decreased */ + 318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.DataRemaining--; + 389 .loc 1 318 15 + 390 006a 564B ldr r3, .L35+4 + 391 006c 5B68 ldr r3, [r3, #4] + 392 .loc 1 318 29 + 393 006e 013B subs r3, r3, #1 + 394 0070 544A ldr r2, .L35+4 + 395 0072 5360 str r3, [r2, #4] + 319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Check if there are still pages to erase */ + 321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** if(pFlash.DataRemaining != 0U) + 396 .loc 1 321 18 + 397 0074 534B ldr r3, .L35+4 + 398 0076 5B68 ldr r3, [r3, #4] + 399 .loc 1 321 11 + 400 0078 002B cmp r3, #0 + 401 007a 17D0 beq .L27 + 322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** addresstmp = pFlash.Address; + 402 .loc 1 323 22 + 403 007c 514B ldr r3, .L35+4 + 404 007e 9B68 ldr r3, [r3, #8] + 405 0080 7B60 str r3, [r7, #4] + 324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /*Indicate user which sector has been erased */ + 325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** HAL_FLASH_EndOfOperationCallback(addresstmp); + 406 .loc 1 325 11 + 407 0082 7868 ldr r0, [r7, #4] + 408 0084 FFF7FEFF bl HAL_FLASH_EndOfOperationCallback + 326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /*Increment sector number*/ + 328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** addresstmp = pFlash.Address + FLASH_PAGE_SIZE; + 409 .loc 1 328 30 + 410 0088 4E4B ldr r3, .L35+4 + 411 008a 9B68 ldr r3, [r3, #8] + 412 .loc 1 328 22 + 413 008c 03F50063 add r3, r3, #2048 + 414 0090 7B60 str r3, [r7, #4] + ARM GAS /tmp/ccv5crZT.s page 14 + + + 329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.Address = addresstmp; + 415 .loc 1 329 26 + 416 0092 4C4A ldr r2, .L35+4 + 417 0094 7B68 ldr r3, [r7, #4] + 418 0096 9360 str r3, [r2, #8] + 330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* If the erase operation is completed, disable the PER Bit */ + 332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** CLEAR_BIT(FLASH->CR, FLASH_CR_PER); + 419 .loc 1 332 11 + 420 0098 494B ldr r3, .L35 + 421 009a 1B69 ldr r3, [r3, #16] + 422 009c 484A ldr r2, .L35 + 423 009e 23F00203 bic r3, r3, #2 + 424 00a2 1361 str r3, [r2, #16] + 333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** FLASH_PageErase(addresstmp); + 425 .loc 1 334 11 + 426 00a4 7868 ldr r0, [r7, #4] + 427 00a6 FFF7FEFF bl FLASH_PageErase + 428 00aa 70E0 b .L25 + 429 .L27: + 335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** else + 337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* No more pages to Erase, user callback can be called. */ + 339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Reset Sector and stop Erase pages procedure */ + 340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.Address = addresstmp = 0xFFFFFFFFU; + 430 .loc 1 340 39 + 431 00ac 4FF0FF33 mov r3, #-1 + 432 00b0 7B60 str r3, [r7, #4] + 433 .loc 1 340 26 + 434 00b2 444A ldr r2, .L35+4 + 435 00b4 7B68 ldr r3, [r7, #4] + 436 00b6 9360 str r3, [r2, #8] + 341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + 437 .loc 1 341 35 + 438 00b8 424B ldr r3, .L35+4 + 439 00ba 0022 movs r2, #0 + 440 00bc 1A70 strb r2, [r3] + 342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* FLASH EOP interrupt user callback */ + 343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** HAL_FLASH_EndOfOperationCallback(addresstmp); + 441 .loc 1 343 11 + 442 00be 7868 ldr r0, [r7, #4] + 443 00c0 FFF7FEFF bl HAL_FLASH_EndOfOperationCallback + 444 00c4 63E0 b .L25 + 445 .L26: + 344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) + 446 .loc 1 346 21 + 447 00c6 3F4B ldr r3, .L35+4 + 448 00c8 1B78 ldrb r3, [r3] + 449 00ca DBB2 uxtb r3, r3 + 450 .loc 1 346 14 + 451 00cc 022B cmp r3, #2 + 452 00ce 0CD1 bne .L28 + 347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + ARM GAS /tmp/ccv5crZT.s page 15 + + + 348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Operation is completed, disable the MER Bit */ + 349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** CLEAR_BIT(FLASH->CR, FLASH_CR_MER); + 453 .loc 1 349 9 + 454 00d0 3B4B ldr r3, .L35 + 455 00d2 1B69 ldr r3, [r3, #16] + 456 00d4 3A4A ldr r2, .L35 + 457 00d6 23F00403 bic r3, r3, #4 + 458 00da 1361 str r3, [r2, #16] + 350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* MassErase ended. Return the selected bank */ + 352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* FLASH EOP interrupt user callback */ + 353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** HAL_FLASH_EndOfOperationCallback(0U); + 459 .loc 1 353 11 + 460 00dc 0020 movs r0, #0 + 461 00de FFF7FEFF bl HAL_FLASH_EndOfOperationCallback + 354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Stop Mass Erase procedure*/ + 356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + 462 .loc 1 356 35 + 463 00e2 384B ldr r3, .L35+4 + 464 00e4 0022 movs r2, #0 + 465 00e6 1A70 strb r2, [r3] + 466 00e8 51E0 b .L25 + 467 .L28: + 357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** else + 359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Nb of 16-bit data to program can be decreased */ + 361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.DataRemaining--; + 468 .loc 1 361 15 + 469 00ea 364B ldr r3, .L35+4 + 470 00ec 5B68 ldr r3, [r3, #4] + 471 .loc 1 361 29 + 472 00ee 013B subs r3, r3, #1 + 473 00f0 344A ldr r2, .L35+4 + 474 00f2 5360 str r3, [r2, #4] + 362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Check if there are still 16-bit data to program */ + 364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** if(pFlash.DataRemaining != 0U) + 475 .loc 1 364 18 + 476 00f4 334B ldr r3, .L35+4 + 477 00f6 5B68 ldr r3, [r3, #4] + 478 .loc 1 364 11 + 479 00f8 002B cmp r3, #0 + 480 00fa 24D0 beq .L29 + 365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Increment address to 16-bit */ + 367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.Address += 2U; + 481 .loc 1 367 17 + 482 00fc 314B ldr r3, .L35+4 + 483 00fe 9B68 ldr r3, [r3, #8] + 484 .loc 1 367 26 + 485 0100 0233 adds r3, r3, #2 + 486 0102 304A ldr r2, .L35+4 + 487 0104 9360 str r3, [r2, #8] + 368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** addresstmp = pFlash.Address; + 488 .loc 1 368 22 + ARM GAS /tmp/ccv5crZT.s page 16 + + + 489 0106 2F4B ldr r3, .L35+4 + 490 0108 9B68 ldr r3, [r3, #8] + 491 010a 7B60 str r3, [r7, #4] + 369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Shift to have next 16-bit data */ + 371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.Data = (pFlash.Data >> 16U); + 492 .loc 1 371 32 + 493 010c 2D4B ldr r3, .L35+4 + 494 010e D3E90401 ldrd r0, [r3, #16] + 495 .loc 1 371 38 + 496 0112 4FF00002 mov r2, #0 + 497 0116 4FF00003 mov r3, #0 + 498 011a 020C lsrs r2, r0, #16 + 499 011c 42EA0142 orr r2, r2, r1, lsl #16 + 500 0120 0B0C lsrs r3, r1, #16 + 501 .loc 1 371 23 + 502 0122 2849 ldr r1, .L35+4 + 503 0124 C1E90423 strd r2, [r1, #16] + 372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Operation is completed, disable the PG Bit */ + 374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** CLEAR_BIT(FLASH->CR, FLASH_CR_PG); + 504 .loc 1 374 11 + 505 0128 254B ldr r3, .L35 + 506 012a 1B69 ldr r3, [r3, #16] + 507 012c 244A ldr r2, .L35 + 508 012e 23F00103 bic r3, r3, #1 + 509 0132 1361 str r3, [r2, #16] + 375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /*Program halfword (16-bit) at a specified address.*/ + 377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** FLASH_Program_HalfWord(addresstmp, (uint16_t)pFlash.Data); + 510 .loc 1 377 62 + 511 0134 234B ldr r3, .L35+4 + 512 0136 D3E90423 ldrd r2, [r3, #16] + 513 .loc 1 377 11 + 514 013a 93B2 uxth r3, r2 + 515 013c 1946 mov r1, r3 + 516 013e 7868 ldr r0, [r7, #4] + 517 0140 FFF7FEFF bl FLASH_Program_HalfWord + 518 0144 23E0 b .L25 + 519 .L29: + 378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** else + 380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Program ended. Return the selected address */ + 382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* FLASH EOP interrupt user callback */ + 383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMHALFWORD) + 520 .loc 1 383 21 + 521 0146 1F4B ldr r3, .L35+4 + 522 0148 1B78 ldrb r3, [r3] + 523 014a DBB2 uxtb r3, r3 + 524 .loc 1 383 14 + 525 014c 032B cmp r3, #3 + 526 014e 05D1 bne .L30 + 384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** HAL_FLASH_EndOfOperationCallback(pFlash.Address); + 527 .loc 1 385 52 + 528 0150 1C4B ldr r3, .L35+4 + ARM GAS /tmp/ccv5crZT.s page 17 + + + 529 0152 9B68 ldr r3, [r3, #8] + 530 .loc 1 385 13 + 531 0154 1846 mov r0, r3 + 532 0156 FFF7FEFF bl HAL_FLASH_EndOfOperationCallback + 533 015a 11E0 b .L31 + 534 .L30: + 386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** else if (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAMWORD) + 535 .loc 1 387 26 + 536 015c 194B ldr r3, .L35+4 + 537 015e 1B78 ldrb r3, [r3] + 538 0160 DBB2 uxtb r3, r3 + 539 .loc 1 387 19 + 540 0162 042B cmp r3, #4 + 541 0164 06D1 bne .L32 + 388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** HAL_FLASH_EndOfOperationCallback(pFlash.Address - 2U); + 542 .loc 1 389 52 + 543 0166 174B ldr r3, .L35+4 + 544 0168 9B68 ldr r3, [r3, #8] + 545 .loc 1 389 13 + 546 016a 023B subs r3, r3, #2 + 547 016c 1846 mov r0, r3 + 548 016e FFF7FEFF bl HAL_FLASH_EndOfOperationCallback + 549 0172 05E0 b .L31 + 550 .L32: + 390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** else + 392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** HAL_FLASH_EndOfOperationCallback(pFlash.Address - 6U); + 551 .loc 1 393 52 + 552 0174 134B ldr r3, .L35+4 + 553 0176 9B68 ldr r3, [r3, #8] + 554 .loc 1 393 13 + 555 0178 063B subs r3, r3, #6 + 556 017a 1846 mov r0, r3 + 557 017c FFF7FEFF bl HAL_FLASH_EndOfOperationCallback + 558 .L31: + 394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Reset Address and stop Program procedure */ + 397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.Address = 0xFFFFFFFFU; + 559 .loc 1 397 26 + 560 0180 104B ldr r3, .L35+4 + 561 0182 4FF0FF32 mov r2, #-1 + 562 0186 9A60 str r2, [r3, #8] + 398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + 563 .loc 1 398 35 + 564 0188 0E4B ldr r3, .L35+4 + 565 018a 0022 movs r2, #0 + 566 018c 1A70 strb r2, [r3] + 567 .L25: + 399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + ARM GAS /tmp/ccv5crZT.s page 18 + + + 404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE) + 568 .loc 1 405 12 + 569 018e 0D4B ldr r3, .L35+4 + 570 0190 1B78 ldrb r3, [r3] + 571 0192 DBB2 uxtb r3, r3 + 572 .loc 1 405 5 + 573 0194 002B cmp r3, #0 + 574 0196 0ED1 bne .L34 + 406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Operation is completed, disable the PG, PER and MER Bits */ + 408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_PER | FLASH_CR_MER)); + 575 .loc 1 408 5 + 576 0198 094B ldr r3, .L35 + 577 019a 1B69 ldr r3, [r3, #16] + 578 019c 084A ldr r2, .L35 + 579 019e 23F00703 bic r3, r3, #7 + 580 01a2 1361 str r3, [r2, #16] + 409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Disable End of FLASH Operation and Error source interrupts */ + 411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); + 581 .loc 1 411 5 + 582 01a4 064B ldr r3, .L35 + 583 01a6 1B69 ldr r3, [r3, #16] + 584 01a8 054A ldr r2, .L35 + 585 01aa 23F4A053 bic r3, r3, #5120 + 586 01ae 1361 str r3, [r2, #16] + 412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Process Unlocked */ + 414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** __HAL_UNLOCK(&pFlash); + 587 .loc 1 414 5 + 588 01b0 044B ldr r3, .L35+4 + 589 01b2 0022 movs r2, #0 + 590 01b4 1A76 strb r2, [r3, #24] + 591 .L34: + 415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 592 .loc 1 416 1 + 593 01b6 00BF nop + 594 01b8 0837 adds r7, r7, #8 + 595 .cfi_def_cfa_offset 8 + 596 01ba BD46 mov sp, r7 + 597 .cfi_def_cfa_register 13 + 598 @ sp needed + 599 01bc 80BD pop {r7, pc} + 600 .L36: + 601 01be 00BF .align 2 + 602 .L35: + 603 01c0 00200240 .word 1073881088 + 604 01c4 00000000 .word pFlash + 605 .cfi_endproc + 606 .LFE132: + 608 .section .text.HAL_FLASH_EndOfOperationCallback,"ax",%progbits + 609 .align 1 + 610 .weak HAL_FLASH_EndOfOperationCallback + 611 .syntax unified + 612 .thumb + ARM GAS /tmp/ccv5crZT.s page 19 + + + 613 .thumb_func + 615 HAL_FLASH_EndOfOperationCallback: + 616 .LFB133: + 417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** + 419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @brief FLASH end of operation interrupt callback + 420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + 421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * - Mass Erase: No return value expected + 422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * - Pages Erase: Address of the page which has been erased + 423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * (if 0xFFFFFFFF, it means that all the selected pages have been erased) + 424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * - Program: Address which was selected for data program + 425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @retval none + 426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) + 428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 617 .loc 1 428 1 + 618 .cfi_startproc + 619 @ args = 0, pretend = 0, frame = 8 + 620 @ frame_needed = 1, uses_anonymous_args = 0 + 621 @ link register save eliminated. + 622 0000 80B4 push {r7} + 623 .cfi_def_cfa_offset 4 + 624 .cfi_offset 7, -4 + 625 0002 83B0 sub sp, sp, #12 + 626 .cfi_def_cfa_offset 16 + 627 0004 00AF add r7, sp, #0 + 628 .cfi_def_cfa_register 7 + 629 0006 7860 str r0, [r7, #4] + 429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Prevent unused argument(s) compilation warning */ + 430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** UNUSED(ReturnValue); + 431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* NOTE : This function Should not be modified, when the callback is needed, + 433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** the HAL_FLASH_EndOfOperationCallback could be implemented in the user file + 434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 630 .loc 1 435 1 + 631 0008 00BF nop + 632 000a 0C37 adds r7, r7, #12 + 633 .cfi_def_cfa_offset 4 + 634 000c BD46 mov sp, r7 + 635 .cfi_def_cfa_register 13 + 636 @ sp needed + 637 000e 5DF8047B ldr r7, [sp], #4 + 638 .cfi_restore 7 + 639 .cfi_def_cfa_offset 0 + 640 0012 7047 bx lr + 641 .cfi_endproc + 642 .LFE133: + 644 .section .text.HAL_FLASH_OperationErrorCallback,"ax",%progbits + 645 .align 1 + 646 .weak HAL_FLASH_OperationErrorCallback + 647 .syntax unified + 648 .thumb + 649 .thumb_func + 651 HAL_FLASH_OperationErrorCallback: + 652 .LFB134: + 436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + ARM GAS /tmp/ccv5crZT.s page 20 + + + 437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** + 438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @brief FLASH operation error interrupt callback + 439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + 440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * - Mass Erase: No return value expected + 441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * - Pages Erase: Address of the page which returned an error + 442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * - Program: Address which was selected for data program + 443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @retval none + 444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) + 446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 653 .loc 1 446 1 + 654 .cfi_startproc + 655 @ args = 0, pretend = 0, frame = 8 + 656 @ frame_needed = 1, uses_anonymous_args = 0 + 657 @ link register save eliminated. + 658 0000 80B4 push {r7} + 659 .cfi_def_cfa_offset 4 + 660 .cfi_offset 7, -4 + 661 0002 83B0 sub sp, sp, #12 + 662 .cfi_def_cfa_offset 16 + 663 0004 00AF add r7, sp, #0 + 664 .cfi_def_cfa_register 7 + 665 0006 7860 str r0, [r7, #4] + 447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Prevent unused argument(s) compilation warning */ + 448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** UNUSED(ReturnValue); + 449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* NOTE : This function Should not be modified, when the callback is needed, + 451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** the HAL_FLASH_OperationErrorCallback could be implemented in the user file + 452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 666 .loc 1 453 1 + 667 0008 00BF nop + 668 000a 0C37 adds r7, r7, #12 + 669 .cfi_def_cfa_offset 4 + 670 000c BD46 mov sp, r7 + 671 .cfi_def_cfa_register 13 + 672 @ sp needed + 673 000e 5DF8047B ldr r7, [sp], #4 + 674 .cfi_restore 7 + 675 .cfi_def_cfa_offset 0 + 676 0012 7047 bx lr + 677 .cfi_endproc + 678 .LFE134: + 680 .section .text.HAL_FLASH_Unlock,"ax",%progbits + 681 .align 1 + 682 .global HAL_FLASH_Unlock + 683 .syntax unified + 684 .thumb + 685 .thumb_func + 687 HAL_FLASH_Unlock: + 688 .LFB135: + 454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** + 456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @} + 457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions + ARM GAS /tmp/ccv5crZT.s page 21 + + + 460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @brief management functions + 461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * + 462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** @verbatim + 463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** =============================================================================== + 464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** ##### Peripheral Control functions ##### + 465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** =============================================================================== + 466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** [..] + 467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** This subsection provides a set of functions allowing to control the FLASH + 468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** memory operations. + 469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** @endverbatim + 471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @{ + 472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** + 475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @brief Unlock the FLASH control register access + 476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @retval HAL Status + 477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_Unlock(void) + 479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 689 .loc 1 479 1 + 690 .cfi_startproc + 691 @ args = 0, pretend = 0, frame = 8 + 692 @ frame_needed = 1, uses_anonymous_args = 0 + 693 @ link register save eliminated. + 694 0000 80B4 push {r7} + 695 .cfi_def_cfa_offset 4 + 696 .cfi_offset 7, -4 + 697 0002 83B0 sub sp, sp, #12 + 698 .cfi_def_cfa_offset 16 + 699 0004 00AF add r7, sp, #0 + 700 .cfi_def_cfa_register 7 + 480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** HAL_StatusTypeDef status = HAL_OK; + 701 .loc 1 480 21 + 702 0006 0023 movs r3, #0 + 703 0008 FB71 strb r3, [r7, #7] + 481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) + 704 .loc 1 482 6 + 705 000a 0D4B ldr r3, .L42 + 706 000c 1B69 ldr r3, [r3, #16] + 707 000e 03F08003 and r3, r3, #128 + 708 .loc 1 482 5 + 709 0012 002B cmp r3, #0 + 710 0014 0DD0 beq .L40 + 483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Authorize the FLASH Registers access */ + 485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** WRITE_REG(FLASH->KEYR, FLASH_KEY1); + 711 .loc 1 485 5 + 712 0016 0A4B ldr r3, .L42 + 713 0018 0A4A ldr r2, .L42+4 + 714 001a 5A60 str r2, [r3, #4] + 486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** WRITE_REG(FLASH->KEYR, FLASH_KEY2); + 715 .loc 1 486 5 + 716 001c 084B ldr r3, .L42 + 717 001e 0A4A ldr r2, .L42+8 + 718 0020 5A60 str r2, [r3, #4] + ARM GAS /tmp/ccv5crZT.s page 22 + + + 487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Verify Flash is unlocked */ + 489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) + 719 .loc 1 489 8 + 720 0022 074B ldr r3, .L42 + 721 0024 1B69 ldr r3, [r3, #16] + 722 0026 03F08003 and r3, r3, #128 + 723 .loc 1 489 7 + 724 002a 002B cmp r3, #0 + 725 002c 01D0 beq .L40 + 490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** status = HAL_ERROR; + 726 .loc 1 491 14 + 727 002e 0123 movs r3, #1 + 728 0030 FB71 strb r3, [r7, #7] + 729 .L40: + 492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** return status; + 730 .loc 1 495 10 + 731 0032 FB79 ldrb r3, [r7, #7] @ zero_extendqisi2 + 496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 732 .loc 1 496 1 + 733 0034 1846 mov r0, r3 + 734 0036 0C37 adds r7, r7, #12 + 735 .cfi_def_cfa_offset 4 + 736 0038 BD46 mov sp, r7 + 737 .cfi_def_cfa_register 13 + 738 @ sp needed + 739 003a 5DF8047B ldr r7, [sp], #4 + 740 .cfi_restore 7 + 741 .cfi_def_cfa_offset 0 + 742 003e 7047 bx lr + 743 .L43: + 744 .align 2 + 745 .L42: + 746 0040 00200240 .word 1073881088 + 747 0044 23016745 .word 1164378403 + 748 0048 AB89EFCD .word -839939669 + 749 .cfi_endproc + 750 .LFE135: + 752 .section .text.HAL_FLASH_Lock,"ax",%progbits + 753 .align 1 + 754 .global HAL_FLASH_Lock + 755 .syntax unified + 756 .thumb + 757 .thumb_func + 759 HAL_FLASH_Lock: + 760 .LFB136: + 497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** + 499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @brief Locks the FLASH control register access + 500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @retval HAL Status + 501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_Lock(void) + 503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + ARM GAS /tmp/ccv5crZT.s page 23 + + + 761 .loc 1 503 1 + 762 .cfi_startproc + 763 @ args = 0, pretend = 0, frame = 0 + 764 @ frame_needed = 1, uses_anonymous_args = 0 + 765 @ link register save eliminated. + 766 0000 80B4 push {r7} + 767 .cfi_def_cfa_offset 4 + 768 .cfi_offset 7, -4 + 769 0002 00AF add r7, sp, #0 + 770 .cfi_def_cfa_register 7 + 504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Set the LOCK Bit to lock the FLASH Registers access */ + 505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** SET_BIT(FLASH->CR, FLASH_CR_LOCK); + 771 .loc 1 505 3 + 772 0004 054B ldr r3, .L46 + 773 0006 1B69 ldr r3, [r3, #16] + 774 0008 044A ldr r2, .L46 + 775 000a 43F08003 orr r3, r3, #128 + 776 000e 1361 str r3, [r2, #16] + 506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** return HAL_OK; + 777 .loc 1 507 10 + 778 0010 0023 movs r3, #0 + 508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 779 .loc 1 508 1 + 780 0012 1846 mov r0, r3 + 781 0014 BD46 mov sp, r7 + 782 .cfi_def_cfa_register 13 + 783 @ sp needed + 784 0016 5DF8047B ldr r7, [sp], #4 + 785 .cfi_restore 7 + 786 .cfi_def_cfa_offset 0 + 787 001a 7047 bx lr + 788 .L47: + 789 .align 2 + 790 .L46: + 791 001c 00200240 .word 1073881088 + 792 .cfi_endproc + 793 .LFE136: + 795 .section .text.HAL_FLASH_OB_Unlock,"ax",%progbits + 796 .align 1 + 797 .global HAL_FLASH_OB_Unlock + 798 .syntax unified + 799 .thumb + 800 .thumb_func + 802 HAL_FLASH_OB_Unlock: + 803 .LFB137: + 509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** + 511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @brief Unlock the FLASH Option Control Registers access. + 512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @retval HAL Status + 513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) + 515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 804 .loc 1 515 1 + 805 .cfi_startproc + 806 @ args = 0, pretend = 0, frame = 0 + 807 @ frame_needed = 1, uses_anonymous_args = 0 + ARM GAS /tmp/ccv5crZT.s page 24 + + + 808 @ link register save eliminated. + 809 0000 80B4 push {r7} + 810 .cfi_def_cfa_offset 4 + 811 .cfi_offset 7, -4 + 812 0002 00AF add r7, sp, #0 + 813 .cfi_def_cfa_register 7 + 516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** if (HAL_IS_BIT_CLR(FLASH->CR, FLASH_CR_OPTWRE)) + 814 .loc 1 516 7 + 815 0004 094B ldr r3, .L52 + 816 0006 1B69 ldr r3, [r3, #16] + 817 0008 03F40073 and r3, r3, #512 + 818 .loc 1 516 6 + 819 000c 002B cmp r3, #0 + 820 000e 07D1 bne .L49 + 517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Authorizes the Option Byte register programming */ + 519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1); + 821 .loc 1 519 5 + 822 0010 064B ldr r3, .L52 + 823 0012 074A ldr r2, .L52+4 + 824 0014 9A60 str r2, [r3, #8] + 520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2); + 825 .loc 1 520 5 + 826 0016 054B ldr r3, .L52 + 827 0018 064A ldr r2, .L52+8 + 828 001a 9A60 str r2, [r3, #8] + 521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** else + 523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** return HAL_ERROR; + 525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** return HAL_OK; + 829 .loc 1 527 10 + 830 001c 0023 movs r3, #0 + 831 001e 00E0 b .L51 + 832 .L49: + 524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 833 .loc 1 524 12 + 834 0020 0123 movs r3, #1 + 835 .L51: + 528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 836 .loc 1 528 1 + 837 0022 1846 mov r0, r3 + 838 0024 BD46 mov sp, r7 + 839 .cfi_def_cfa_register 13 + 840 @ sp needed + 841 0026 5DF8047B ldr r7, [sp], #4 + 842 .cfi_restore 7 + 843 .cfi_def_cfa_offset 0 + 844 002a 7047 bx lr + 845 .L53: + 846 .align 2 + 847 .L52: + 848 002c 00200240 .word 1073881088 + 849 0030 23016745 .word 1164378403 + 850 0034 AB89EFCD .word -839939669 + ARM GAS /tmp/ccv5crZT.s page 25 + + + 851 .cfi_endproc + 852 .LFE137: + 854 .section .text.HAL_FLASH_OB_Lock,"ax",%progbits + 855 .align 1 + 856 .global HAL_FLASH_OB_Lock + 857 .syntax unified + 858 .thumb + 859 .thumb_func + 861 HAL_FLASH_OB_Lock: + 862 .LFB138: + 529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** + 531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @brief Lock the FLASH Option Control Registers access. + 532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @retval HAL Status + 533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) + 535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 863 .loc 1 535 1 + 864 .cfi_startproc + 865 @ args = 0, pretend = 0, frame = 0 + 866 @ frame_needed = 1, uses_anonymous_args = 0 + 867 @ link register save eliminated. + 868 0000 80B4 push {r7} + 869 .cfi_def_cfa_offset 4 + 870 .cfi_offset 7, -4 + 871 0002 00AF add r7, sp, #0 + 872 .cfi_def_cfa_register 7 + 536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Clear the OPTWRE Bit to lock the FLASH Option Byte Registers access */ + 537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** CLEAR_BIT(FLASH->CR, FLASH_CR_OPTWRE); + 873 .loc 1 537 3 + 874 0004 054B ldr r3, .L56 + 875 0006 1B69 ldr r3, [r3, #16] + 876 0008 044A ldr r2, .L56 + 877 000a 23F40073 bic r3, r3, #512 + 878 000e 1361 str r3, [r2, #16] + 538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** return HAL_OK; + 879 .loc 1 539 10 + 880 0010 0023 movs r3, #0 + 540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 881 .loc 1 540 1 + 882 0012 1846 mov r0, r3 + 883 0014 BD46 mov sp, r7 + 884 .cfi_def_cfa_register 13 + 885 @ sp needed + 886 0016 5DF8047B ldr r7, [sp], #4 + 887 .cfi_restore 7 + 888 .cfi_def_cfa_offset 0 + 889 001a 7047 bx lr + 890 .L57: + 891 .align 2 + 892 .L56: + 893 001c 00200240 .word 1073881088 + 894 .cfi_endproc + 895 .LFE138: + 897 .section .text.HAL_FLASH_OB_Launch,"ax",%progbits + 898 .align 1 + ARM GAS /tmp/ccv5crZT.s page 26 + + + 899 .global HAL_FLASH_OB_Launch + 900 .syntax unified + 901 .thumb + 902 .thumb_func + 904 HAL_FLASH_OB_Launch: + 905 .LFB139: + 541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** + 543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @brief Launch the option byte loading. + 544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @note This function will reset automatically the MCU. + 545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @retval HAL Status + 546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) + 548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 906 .loc 1 548 1 + 907 .cfi_startproc + 908 @ args = 0, pretend = 0, frame = 0 + 909 @ frame_needed = 1, uses_anonymous_args = 0 + 910 0000 80B5 push {r7, lr} + 911 .cfi_def_cfa_offset 8 + 912 .cfi_offset 7, -8 + 913 .cfi_offset 14, -4 + 914 0002 00AF add r7, sp, #0 + 915 .cfi_def_cfa_register 7 + 549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Set the OBL_Launch bit to launch the option byte loading */ + 550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH); + 916 .loc 1 550 3 + 917 0004 064B ldr r3, .L60 + 918 0006 1B69 ldr r3, [r3, #16] + 919 0008 054A ldr r2, .L60 + 920 000a 43F40053 orr r3, r3, #8192 + 921 000e 1361 str r3, [r2, #16] + 551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Wait for last operation to be completed */ + 553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** return(FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE)); + 922 .loc 1 553 10 + 923 0010 4CF25030 movw r0, #50000 + 924 0014 FFF7FEFF bl FLASH_WaitForLastOperation + 925 0018 0346 mov r3, r0 + 554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 926 .loc 1 554 1 + 927 001a 1846 mov r0, r3 + 928 001c 80BD pop {r7, pc} + 929 .L61: + 930 001e 00BF .align 2 + 931 .L60: + 932 0020 00200240 .word 1073881088 + 933 .cfi_endproc + 934 .LFE139: + 936 .section .text.HAL_FLASH_GetError,"ax",%progbits + 937 .align 1 + 938 .global HAL_FLASH_GetError + 939 .syntax unified + 940 .thumb + 941 .thumb_func + 943 HAL_FLASH_GetError: + 944 .LFB140: + ARM GAS /tmp/ccv5crZT.s page 27 + + + 555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** + 557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @} + 558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** @defgroup FLASH_Exported_Functions_Group3 Peripheral errors functions + 561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @brief Peripheral errors functions + 562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * + 563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** @verbatim + 564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** =============================================================================== + 565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** ##### Peripheral Errors functions ##### + 566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** =============================================================================== + 567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** [..] + 568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** This subsection permit to get in run-time errors of the FLASH peripheral. + 569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** @endverbatim + 571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @{ + 572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** + 575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @brief Get the specific FLASH error flag. + 576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @retval FLASH_ErrorCode The returned value can be: + 577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @ref FLASH_Error_Codes + 578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** uint32_t HAL_FLASH_GetError(void) + 580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 945 .loc 1 580 1 + 946 .cfi_startproc + 947 @ args = 0, pretend = 0, frame = 0 + 948 @ frame_needed = 1, uses_anonymous_args = 0 + 949 @ link register save eliminated. + 950 0000 80B4 push {r7} + 951 .cfi_def_cfa_offset 4 + 952 .cfi_offset 7, -4 + 953 0002 00AF add r7, sp, #0 + 954 .cfi_def_cfa_register 7 + 581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** return pFlash.ErrorCode; + 955 .loc 1 581 17 + 956 0004 034B ldr r3, .L64 + 957 0006 DB69 ldr r3, [r3, #28] + 582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 958 .loc 1 582 1 + 959 0008 1846 mov r0, r3 + 960 000a BD46 mov sp, r7 + 961 .cfi_def_cfa_register 13 + 962 @ sp needed + 963 000c 5DF8047B ldr r7, [sp], #4 + 964 .cfi_restore 7 + 965 .cfi_def_cfa_offset 0 + 966 0010 7047 bx lr + 967 .L65: + 968 0012 00BF .align 2 + 969 .L64: + 970 0014 00000000 .word pFlash + 971 .cfi_endproc + 972 .LFE140: + 974 .section .text.FLASH_Program_HalfWord,"ax",%progbits + ARM GAS /tmp/ccv5crZT.s page 28 + + + 975 .align 1 + 976 .syntax unified + 977 .thumb + 978 .thumb_func + 980 FLASH_Program_HalfWord: + 981 .LFB141: + 583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** + 585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @} + 586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** + 589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @} + 590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** @addtogroup FLASH_Private_Functions + 593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @{ + 594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** + 597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @brief Program a half-word (16-bit) at a specified address. + 598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @param Address specify the address to be programmed. + 599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @param Data specify the data to be programmed. + 600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @retval None + 601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 602:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) + 603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 982 .loc 1 603 1 + 983 .cfi_startproc + 984 @ args = 0, pretend = 0, frame = 8 + 985 @ frame_needed = 1, uses_anonymous_args = 0 + 986 @ link register save eliminated. + 987 0000 80B4 push {r7} + 988 .cfi_def_cfa_offset 4 + 989 .cfi_offset 7, -4 + 990 0002 83B0 sub sp, sp, #12 + 991 .cfi_def_cfa_offset 16 + 992 0004 00AF add r7, sp, #0 + 993 .cfi_def_cfa_register 7 + 994 0006 7860 str r0, [r7, #4] + 995 0008 0B46 mov r3, r1 + 996 000a 7B80 strh r3, [r7, #2] @ movhi + 604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Clean the error context */ + 605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + 997 .loc 1 605 20 + 998 000c 084B ldr r3, .L67 + 999 000e 0022 movs r2, #0 + 1000 0010 DA61 str r2, [r3, #28] + 606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Proceed to program the new data */ + 608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** SET_BIT(FLASH->CR, FLASH_CR_PG); + 1001 .loc 1 608 5 + 1002 0012 084B ldr r3, .L67+4 + 1003 0014 1B69 ldr r3, [r3, #16] + 1004 0016 074A ldr r2, .L67+4 + 1005 0018 43F00103 orr r3, r3, #1 + 1006 001c 1361 str r3, [r2, #16] + ARM GAS /tmp/ccv5crZT.s page 29 + + + 609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Write data in the address */ + 611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** *(__IO uint16_t*)Address = Data; + 1007 .loc 1 611 4 + 1008 001e 7B68 ldr r3, [r7, #4] + 1009 .loc 1 611 28 + 1010 0020 7A88 ldrh r2, [r7, #2] @ movhi + 1011 0022 1A80 strh r2, [r3] @ movhi + 612:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 1012 .loc 1 612 1 + 1013 0024 00BF nop + 1014 0026 0C37 adds r7, r7, #12 + 1015 .cfi_def_cfa_offset 4 + 1016 0028 BD46 mov sp, r7 + 1017 .cfi_def_cfa_register 13 + 1018 @ sp needed + 1019 002a 5DF8047B ldr r7, [sp], #4 + 1020 .cfi_restore 7 + 1021 .cfi_def_cfa_offset 0 + 1022 002e 7047 bx lr + 1023 .L68: + 1024 .align 2 + 1025 .L67: + 1026 0030 00000000 .word pFlash + 1027 0034 00200240 .word 1073881088 + 1028 .cfi_endproc + 1029 .LFE141: + 1031 .section .text.FLASH_WaitForLastOperation,"ax",%progbits + 1032 .align 1 + 1033 .global FLASH_WaitForLastOperation + 1034 .syntax unified + 1035 .thumb + 1036 .thumb_func + 1038 FLASH_WaitForLastOperation: + 1039 .LFB142: + 613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** + 615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @brief Wait for a FLASH operation to complete. + 616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @param Timeout maximum flash operation timeout + 617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @retval HAL Status + 618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) + 620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 1040 .loc 1 620 1 + 1041 .cfi_startproc + 1042 @ args = 0, pretend = 0, frame = 16 + 1043 @ frame_needed = 1, uses_anonymous_args = 0 + 1044 0000 80B5 push {r7, lr} + 1045 .cfi_def_cfa_offset 8 + 1046 .cfi_offset 7, -8 + 1047 .cfi_offset 14, -4 + 1048 0002 84B0 sub sp, sp, #16 + 1049 .cfi_def_cfa_offset 24 + 1050 0004 00AF add r7, sp, #0 + 1051 .cfi_def_cfa_register 7 + 1052 0006 7860 str r0, [r7, #4] + 621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. + ARM GAS /tmp/ccv5crZT.s page 30 + + + 622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** Even if the FLASH operation fails, the BUSY flag will be reset and an error + 623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** flag will be set */ + 624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** uint32_t tickstart = HAL_GetTick(); + 1053 .loc 1 625 24 + 1054 0008 FFF7FEFF bl HAL_GetTick + 1055 000c F860 str r0, [r7, #12] + 626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) + 1056 .loc 1 627 8 + 1057 000e 10E0 b .L71 + 1058 .L74: + 628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** if (Timeout != HAL_MAX_DELAY) + 1059 .loc 1 629 8 + 1060 0010 7B68 ldr r3, [r7, #4] + 1061 0012 B3F1FF3F cmp r3, #-1 + 1062 0016 0CD0 beq .L71 + 630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) + 1063 .loc 1 631 9 + 1064 0018 7B68 ldr r3, [r7, #4] + 1065 001a 002B cmp r3, #0 + 1066 001c 07D0 beq .L72 + 1067 .loc 1 631 31 discriminator 1 + 1068 001e FFF7FEFF bl HAL_GetTick + 1069 0022 0246 mov r2, r0 + 1070 .loc 1 631 44 discriminator 1 + 1071 0024 FB68 ldr r3, [r7, #12] + 1072 0026 D31A subs r3, r2, r3 + 1073 .loc 1 631 26 discriminator 1 + 1074 0028 7A68 ldr r2, [r7, #4] + 1075 002a 9A42 cmp r2, r3 + 1076 002c 01D2 bcs .L71 + 1077 .L72: + 632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** return HAL_TIMEOUT; + 1078 .loc 1 633 16 + 1079 002e 0323 movs r3, #3 + 1080 0030 1FE0 b .L73 + 1081 .L71: + 627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 1082 .loc 1 627 9 + 1083 0032 124B ldr r3, .L78 + 1084 0034 DB68 ldr r3, [r3, #12] + 1085 0036 03F00103 and r3, r3, #1 + 1086 003a 012B cmp r3, #1 + 1087 003c E8D0 beq .L74 + 634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Check FLASH End of Operation flag */ + 639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) + 1088 .loc 1 639 7 + 1089 003e 0F4B ldr r3, .L78 + 1090 0040 DB68 ldr r3, [r3, #12] + ARM GAS /tmp/ccv5crZT.s page 31 + + + 1091 0042 03F02003 and r3, r3, #32 + 1092 .loc 1 639 6 + 1093 0046 202B cmp r3, #32 + 1094 0048 02D1 bne .L75 + 640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Clear FLASH End of Operation pending bit */ + 642:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + 1095 .loc 1 642 5 + 1096 004a 0C4B ldr r3, .L78 + 1097 004c 2022 movs r2, #32 + 1098 004e DA60 str r2, [r3, #12] + 1099 .L75: + 643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || + 1100 .loc 1 645 6 + 1101 0050 0A4B ldr r3, .L78 + 1102 0052 DB68 ldr r3, [r3, #12] + 1103 0054 03F01003 and r3, r3, #16 + 1104 .loc 1 645 5 + 1105 0058 102B cmp r3, #16 + 1106 005a 05D0 beq .L76 + 646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) + 1107 .loc 1 646 6 + 1108 005c 074B ldr r3, .L78 + 1109 005e DB68 ldr r3, [r3, #12] + 1110 0060 03F00403 and r3, r3, #4 + 645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) + 1111 .loc 1 645 47 discriminator 1 + 1112 0064 042B cmp r3, #4 + 1113 0066 03D1 bne .L77 + 1114 .L76: + 647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /*Save the error code*/ + 649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** FLASH_SetErrorCode(); + 1115 .loc 1 649 5 + 1116 0068 FFF7FEFF bl FLASH_SetErrorCode + 650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** return HAL_ERROR; + 1117 .loc 1 650 12 + 1118 006c 0123 movs r3, #1 + 1119 006e 00E0 b .L73 + 1120 .L77: + 651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* There is no error flag set */ + 654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** return HAL_OK; + 1121 .loc 1 654 10 + 1122 0070 0023 movs r3, #0 + 1123 .L73: + 655:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 1124 .loc 1 655 1 + 1125 0072 1846 mov r0, r3 + 1126 0074 1037 adds r7, r7, #16 + 1127 .cfi_def_cfa_offset 8 + 1128 0076 BD46 mov sp, r7 + 1129 .cfi_def_cfa_register 13 + 1130 @ sp needed + ARM GAS /tmp/ccv5crZT.s page 32 + + + 1131 0078 80BD pop {r7, pc} + 1132 .L79: + 1133 007a 00BF .align 2 + 1134 .L78: + 1135 007c 00200240 .word 1073881088 + 1136 .cfi_endproc + 1137 .LFE142: + 1139 .section .text.FLASH_SetErrorCode,"ax",%progbits + 1140 .align 1 + 1141 .syntax unified + 1142 .thumb + 1143 .thumb_func + 1145 FLASH_SetErrorCode: + 1146 .LFB143: + 656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 657:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /** + 659:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @brief Set the specific FLASH error flag. + 660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** * @retval None + 661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** */ + 662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** static void FLASH_SetErrorCode(void) + 663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 1147 .loc 1 663 1 + 1148 .cfi_startproc + 1149 @ args = 0, pretend = 0, frame = 8 + 1150 @ frame_needed = 1, uses_anonymous_args = 0 + 1151 @ link register save eliminated. + 1152 0000 80B4 push {r7} + 1153 .cfi_def_cfa_offset 4 + 1154 .cfi_offset 7, -4 + 1155 0002 83B0 sub sp, sp, #12 + 1156 .cfi_def_cfa_offset 16 + 1157 0004 00AF add r7, sp, #0 + 1158 .cfi_def_cfa_register 7 + 664:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** uint32_t flags = 0U; + 1159 .loc 1 664 12 + 1160 0006 0023 movs r3, #0 + 1161 0008 7B60 str r3, [r7, #4] + 665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** + 666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) + 1162 .loc 1 666 6 + 1163 000a 144B ldr r3, .L83 + 1164 000c DB68 ldr r3, [r3, #12] + 1165 000e 03F01003 and r3, r3, #16 + 1166 .loc 1 666 5 + 1167 0012 102B cmp r3, #16 + 1168 0014 09D1 bne .L81 + 667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 668:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; + 1169 .loc 1 668 11 + 1170 0016 124B ldr r3, .L83+4 + 1171 0018 DB69 ldr r3, [r3, #28] + 1172 .loc 1 668 22 + 1173 001a 43F00203 orr r3, r3, #2 + 1174 001e 104A ldr r2, .L83+4 + 1175 0020 D361 str r3, [r2, #28] + 669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** flags |= FLASH_FLAG_WRPERR; + ARM GAS /tmp/ccv5crZT.s page 33 + + + 1176 .loc 1 669 11 + 1177 0022 7B68 ldr r3, [r7, #4] + 1178 0024 43F01003 orr r3, r3, #16 + 1179 0028 7B60 str r3, [r7, #4] + 1180 .L81: + 670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) + 1181 .loc 1 671 6 + 1182 002a 0C4B ldr r3, .L83 + 1183 002c DB68 ldr r3, [r3, #12] + 1184 002e 03F00403 and r3, r3, #4 + 1185 .loc 1 671 5 + 1186 0032 042B cmp r3, #4 + 1187 0034 09D1 bne .L82 + 672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** { + 673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG; + 1188 .loc 1 673 11 + 1189 0036 0A4B ldr r3, .L83+4 + 1190 0038 DB69 ldr r3, [r3, #28] + 1191 .loc 1 673 22 + 1192 003a 43F00103 orr r3, r3, #1 + 1193 003e 084A ldr r2, .L83+4 + 1194 0040 D361 str r3, [r2, #28] + 674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** flags |= FLASH_FLAG_PGERR; + 1195 .loc 1 674 11 + 1196 0042 7B68 ldr r3, [r7, #4] + 1197 0044 43F00403 orr r3, r3, #4 + 1198 0048 7B60 str r3, [r7, #4] + 1199 .L82: + 675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** /* Clear FLASH error pending bits */ + 677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** __HAL_FLASH_CLEAR_FLAG(flags); + 1200 .loc 1 677 3 + 1201 004a 044A ldr r2, .L83 + 1202 004c 7B68 ldr r3, [r7, #4] + 1203 004e D360 str r3, [r2, #12] + 678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash.c **** } + 1204 .loc 1 678 1 + 1205 0050 00BF nop + 1206 0052 0C37 adds r7, r7, #12 + 1207 .cfi_def_cfa_offset 4 + 1208 0054 BD46 mov sp, r7 + 1209 .cfi_def_cfa_register 13 + 1210 @ sp needed + 1211 0056 5DF8047B ldr r7, [sp], #4 + 1212 .cfi_restore 7 + 1213 .cfi_def_cfa_offset 0 + 1214 005a 7047 bx lr + 1215 .L84: + 1216 .align 2 + 1217 .L83: + 1218 005c 00200240 .word 1073881088 + 1219 0060 00000000 .word pFlash + 1220 .cfi_endproc + 1221 .LFE143: + 1223 .text + 1224 .Letext0: + ARM GAS /tmp/ccv5crZT.s page 34 + + + 1225 .file 2 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 1226 .file 3 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 1227 .file 4 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + 1228 .file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h" + 1229 .file 6 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h" + 1230 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h" + 1231 .file 8 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h" + ARM GAS /tmp/ccv5crZT.s page 35 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f3xx_hal_flash.c + /tmp/ccv5crZT.s:25 .bss.pFlash:00000000 pFlash + /tmp/ccv5crZT.s:22 .bss.pFlash:00000000 $d + /tmp/ccv5crZT.s:28 .text.HAL_FLASH_Program:00000000 $t + /tmp/ccv5crZT.s:34 .text.HAL_FLASH_Program:00000000 HAL_FLASH_Program + /tmp/ccv5crZT.s:1038 .text.FLASH_WaitForLastOperation:00000000 FLASH_WaitForLastOperation + /tmp/ccv5crZT.s:980 .text.FLASH_Program_HalfWord:00000000 FLASH_Program_HalfWord + /tmp/ccv5crZT.s:186 .text.HAL_FLASH_Program:000000d8 $d + /tmp/ccv5crZT.s:192 .text.HAL_FLASH_Program_IT:00000000 $t + /tmp/ccv5crZT.s:198 .text.HAL_FLASH_Program_IT:00000000 HAL_FLASH_Program_IT + /tmp/ccv5crZT.s:302 .text.HAL_FLASH_Program_IT:00000088 $d + /tmp/ccv5crZT.s:308 .text.HAL_FLASH_IRQHandler:00000000 $t + /tmp/ccv5crZT.s:314 .text.HAL_FLASH_IRQHandler:00000000 HAL_FLASH_IRQHandler + /tmp/ccv5crZT.s:1145 .text.FLASH_SetErrorCode:00000000 FLASH_SetErrorCode + /tmp/ccv5crZT.s:651 .text.HAL_FLASH_OperationErrorCallback:00000000 HAL_FLASH_OperationErrorCallback + /tmp/ccv5crZT.s:615 .text.HAL_FLASH_EndOfOperationCallback:00000000 HAL_FLASH_EndOfOperationCallback + /tmp/ccv5crZT.s:603 .text.HAL_FLASH_IRQHandler:000001c0 $d + /tmp/ccv5crZT.s:609 .text.HAL_FLASH_EndOfOperationCallback:00000000 $t + /tmp/ccv5crZT.s:645 .text.HAL_FLASH_OperationErrorCallback:00000000 $t + /tmp/ccv5crZT.s:681 .text.HAL_FLASH_Unlock:00000000 $t + /tmp/ccv5crZT.s:687 .text.HAL_FLASH_Unlock:00000000 HAL_FLASH_Unlock + /tmp/ccv5crZT.s:746 .text.HAL_FLASH_Unlock:00000040 $d + /tmp/ccv5crZT.s:753 .text.HAL_FLASH_Lock:00000000 $t + /tmp/ccv5crZT.s:759 .text.HAL_FLASH_Lock:00000000 HAL_FLASH_Lock + /tmp/ccv5crZT.s:791 .text.HAL_FLASH_Lock:0000001c $d + /tmp/ccv5crZT.s:796 .text.HAL_FLASH_OB_Unlock:00000000 $t + /tmp/ccv5crZT.s:802 .text.HAL_FLASH_OB_Unlock:00000000 HAL_FLASH_OB_Unlock + /tmp/ccv5crZT.s:848 .text.HAL_FLASH_OB_Unlock:0000002c $d + /tmp/ccv5crZT.s:855 .text.HAL_FLASH_OB_Lock:00000000 $t + /tmp/ccv5crZT.s:861 .text.HAL_FLASH_OB_Lock:00000000 HAL_FLASH_OB_Lock + /tmp/ccv5crZT.s:893 .text.HAL_FLASH_OB_Lock:0000001c $d + /tmp/ccv5crZT.s:898 .text.HAL_FLASH_OB_Launch:00000000 $t + /tmp/ccv5crZT.s:904 .text.HAL_FLASH_OB_Launch:00000000 HAL_FLASH_OB_Launch + /tmp/ccv5crZT.s:932 .text.HAL_FLASH_OB_Launch:00000020 $d + /tmp/ccv5crZT.s:937 .text.HAL_FLASH_GetError:00000000 $t + /tmp/ccv5crZT.s:943 .text.HAL_FLASH_GetError:00000000 HAL_FLASH_GetError + /tmp/ccv5crZT.s:970 .text.HAL_FLASH_GetError:00000014 $d + /tmp/ccv5crZT.s:975 .text.FLASH_Program_HalfWord:00000000 $t + /tmp/ccv5crZT.s:1026 .text.FLASH_Program_HalfWord:00000030 $d + /tmp/ccv5crZT.s:1032 .text.FLASH_WaitForLastOperation:00000000 $t + /tmp/ccv5crZT.s:1135 .text.FLASH_WaitForLastOperation:0000007c $d + /tmp/ccv5crZT.s:1140 .text.FLASH_SetErrorCode:00000000 $t + /tmp/ccv5crZT.s:1218 .text.FLASH_SetErrorCode:0000005c $d + +UNDEFINED SYMBOLS +FLASH_PageErase +HAL_GetTick diff --git a/Software/build/stm32f3xx_hal_flash.o b/Software/build/stm32f3xx_hal_flash.o new file mode 100644 index 0000000..c69bed0 Binary files /dev/null and b/Software/build/stm32f3xx_hal_flash.o differ diff --git a/Software/build/stm32f3xx_hal_flash_ex.d b/Software/build/stm32f3xx_hal_flash_ex.d new file mode 100644 index 0000000..aef6e8b --- /dev/null +++ b/Software/build/stm32f3xx_hal_flash_ex.d @@ -0,0 +1,62 @@ +build/stm32f3xx_hal_flash_ex.o: \ + Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + Core/Inc/stm32f3xx_hal_conf.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h: diff --git a/Software/build/stm32f3xx_hal_flash_ex.lst b/Software/build/stm32f3xx_hal_flash_ex.lst new file mode 100644 index 0000000..0b01798 --- /dev/null +++ b/Software/build/stm32f3xx_hal_flash_ex.lst @@ -0,0 +1,3929 @@ +ARM GAS /tmp/ccMLQ7U7.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 6 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "stm32f3xx_hal_flash_ex.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c" + 20 .section .text.HAL_FLASHEx_Erase,"ax",%progbits + 21 .align 1 + 22 .global HAL_FLASHEx_Erase + 23 .syntax unified + 24 .thumb + 25 .thumb_func + 27 HAL_FLASHEx_Erase: + 28 .LFB130: + 1:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + 2:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** ****************************************************************************** + 3:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @file stm32f3xx_hal_flash_ex.c + 4:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @author MCD Application Team + 5:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @brief Extended FLASH HAL module driver. + 6:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * + 7:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * This file provides firmware functions to manage the following + 8:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * functionalities of the FLASH peripheral: + 9:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * + Extended Initialization/de-initialization functions + 10:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * + Extended I/O operation functions + 11:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * + Extended Peripheral Control functions + 12:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * + 13:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** @verbatim + 14:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** ============================================================================== + 15:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** ##### Flash peripheral extended features ##### + 16:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** ============================================================================== + 17:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 18:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** ##### How to use this driver ##### + 19:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** ============================================================================== + 20:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** [..] This driver provides functions to configure and program the FLASH memory + 21:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** of all STM32F3xxx devices. It includes + 22:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 23:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** (++) Set/Reset the write protection + 24:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** (++) Program the user Option Bytes + 25:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** (++) Get the Read protection Level + 26:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 27:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** @endverbatim + 28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** ****************************************************************************** + 29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @attention + 30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * + ARM GAS /tmp/ccMLQ7U7.s page 2 + + + 31:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * Copyright (c) 2016 STMicroelectronics. + 32:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * All rights reserved. + 33:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * + 34:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * This software is licensed under terms that can be found in the LICENSE file in + 35:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * the root directory of this software component. + 36:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 37:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** ****************************************************************************** + 38:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 39:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 40:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Includes ------------------------------------------------------------------*/ + 41:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #include "stm32f3xx_hal.h" + 42:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 43:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** @addtogroup STM32F3xx_HAL_Driver + 44:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @{ + 45:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 46:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #ifdef HAL_FLASH_MODULE_ENABLED + 47:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 48:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** @addtogroup FLASH + 49:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @{ + 50:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 51:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** @addtogroup FLASH_Private_Variables + 52:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @{ + 53:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 54:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Variables used for Erase pages under interruption*/ + 55:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** extern FLASH_ProcessTypeDef pFlash; + 56:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + 57:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @} + 58:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 59:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 60:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + 61:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @} + 62:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 63:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 64:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** @defgroup FLASHEx FLASHEx + 65:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @brief FLASH HAL Extension module driver + 66:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @{ + 67:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 68:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 69:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Private typedef -----------------------------------------------------------*/ + 70:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Private define ------------------------------------------------------------*/ + 71:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants + 72:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @{ + 73:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 74:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #define FLASH_POSITION_IWDGSW_BIT (uint32_t)POSITION_VAL(FLASH_OBR_IWDG_SW) + 75:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #define FLASH_POSITION_OB_USERDATA0_BIT (uint32_t)POSITION_VAL(FLASH_OBR_DATA0) + 76:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #define FLASH_POSITION_OB_USERDATA1_BIT (uint32_t)POSITION_VAL(FLASH_OBR_DATA1) + 77:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + 78:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @} + 79:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 80:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 81:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Private macro -------------------------------------------------------------*/ + 82:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros + 83:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @{ + 84:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + 86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @} + 87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + ARM GAS /tmp/ccMLQ7U7.s page 3 + + + 88:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 89:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Private variables ---------------------------------------------------------*/ + 90:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Private function prototypes -----------------------------------------------*/ + 91:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions + 92:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @{ + 93:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 94:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Erase operations */ + 95:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** static void FLASH_MassErase(void); + 96:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** void FLASH_PageErase(uint32_t PageAddress); + 97:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 98:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Option bytes control */ + 99:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage); + 100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage); + 101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel); + 102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig); + 103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data); + 104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** static uint32_t FLASH_OB_GetWRP(void); + 105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** static uint32_t FLASH_OB_GetRDP(void); + 106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** static uint8_t FLASH_OB_GetUser(void); + 107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + 109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @} + 110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Exported functions ---------------------------------------------------------*/ + 113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions + 114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @{ + 115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** @defgroup FLASHEx_Exported_Functions_Group1 FLASHEx Memory Erasing functions + 118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @brief FLASH Memory Erasing functions + 119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * + 120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** @verbatim + 121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** ============================================================================== + 122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** ##### FLASH Erasing Programming functions ##### + 123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** ============================================================================== + 124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** [..] The FLASH Memory Erasing functions, includes the following functions: + 126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** (+) HAL_FLASHEx_Erase: return only when erase has been done + 127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** (+) HAL_FLASHEx_Erase_IT: end of erase is done when HAL_FLASH_EndOfOperationCallback + 128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** is called with parameter 0xFFFFFFFF + 129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** [..] Any operation of erase should follow these steps: + 131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** (#) Call the HAL_FLASH_Unlock() function to enable the flash control register and + 132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** program memory access. + 133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** (#) Call the desired function to erase page. + 134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** (#) Call the HAL_FLASH_Lock() to disable the flash program memory access + 135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** (recommended to protect the FLASH memory against possible unwanted operation). + 136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** @endverbatim + 138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @{ + 139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + 143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @brief Perform a mass erase or erase the specified FLASH memory pages + 144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function + ARM GAS /tmp/ccMLQ7U7.s page 4 + + + 145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * must be called before. + 146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * Call the @ref HAL_FLASH_Lock() to disable the flash memory access + 147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * (recommended to protect the FLASH memory against possible unwanted operation) + 148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + 149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * contains the configuration information for the erasing. + 150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * + 151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @param[out] PageError pointer to variable that + 152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * contains the configuration information on faulty page in case of error + 153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * (0xFFFFFFFF means that all the pages have been correctly erased) + 154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * + 155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @retval HAL_StatusTypeDef HAL Status + 156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) + 158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 29 .loc 1 158 1 + 30 .cfi_startproc + 31 @ args = 0, pretend = 0, frame = 16 + 32 @ frame_needed = 1, uses_anonymous_args = 0 + 33 0000 80B5 push {r7, lr} + 34 .cfi_def_cfa_offset 8 + 35 .cfi_offset 7, -8 + 36 .cfi_offset 14, -4 + 37 0002 84B0 sub sp, sp, #16 + 38 .cfi_def_cfa_offset 24 + 39 0004 00AF add r7, sp, #0 + 40 .cfi_def_cfa_register 7 + 41 0006 7860 str r0, [r7, #4] + 42 0008 3960 str r1, [r7] + 159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_ERROR; + 43 .loc 1 159 21 + 44 000a 0123 movs r3, #1 + 45 000c FB73 strb r3, [r7, #15] + 160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** uint32_t address = 0U; + 46 .loc 1 160 12 + 47 000e 0023 movs r3, #0 + 48 0010 BB60 str r3, [r7, #8] + 161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Process Locked */ + 163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** __HAL_LOCK(&pFlash); + 49 .loc 1 163 3 + 50 0012 2E4B ldr r3, .L9 + 51 0014 1B7E ldrb r3, [r3, #24] @ zero_extendqisi2 + 52 0016 012B cmp r3, #1 + 53 0018 01D1 bne .L2 + 54 .loc 1 163 3 is_stmt 0 discriminator 1 + 55 001a 0223 movs r3, #2 + 56 .loc 1 163 3 + 57 001c 52E0 b .L3 + 58 .L2: + 59 .loc 1 163 3 discriminator 2 + 60 001e 2B4B ldr r3, .L9 + 61 0020 0122 movs r2, #1 + 62 0022 1A76 strb r2, [r3, #24] + 164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Check the parameters */ + 166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + 167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + ARM GAS /tmp/ccMLQ7U7.s page 5 + + + 168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) + 63 .loc 1 168 17 is_stmt 1 + 64 0024 7B68 ldr r3, [r7, #4] + 65 0026 1B68 ldr r3, [r3] + 66 .loc 1 168 6 + 67 0028 012B cmp r3, #1 + 68 002a 15D1 bne .L4 + 169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Mass Erase requested for Bank1 */ + 171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) + 69 .loc 1 172 11 + 70 002c 4CF25030 movw r0, #50000 + 71 0030 FFF7FEFF bl FLASH_WaitForLastOperation + 72 0034 0346 mov r3, r0 + 73 .loc 1 172 10 discriminator 1 + 74 0036 002B cmp r3, #0 + 75 0038 40D1 bne .L5 + 173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /*Mass erase to be done*/ + 175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** FLASH_MassErase(); + 76 .loc 1 175 9 + 77 003a FFF7FEFF bl FLASH_MassErase + 176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 78 .loc 1 178 18 + 79 003e 4CF25030 movw r0, #50000 + 80 0042 FFF7FEFF bl FLASH_WaitForLastOperation + 81 0046 0346 mov r3, r0 + 82 0048 FB73 strb r3, [r7, #15] + 179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* If the erase operation is completed, disable the MER Bit */ + 181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** CLEAR_BIT(FLASH->CR, FLASH_CR_MER); + 83 .loc 1 181 9 + 84 004a 214B ldr r3, .L9+4 + 85 004c 1B69 ldr r3, [r3, #16] + 86 004e 204A ldr r2, .L9+4 + 87 0050 23F00403 bic r3, r3, #4 + 88 0054 1361 str r3, [r2, #16] + 89 0056 31E0 b .L5 + 90 .L4: + 182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** else + 185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Page Erase is requested */ + 187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Check the parameters */ + 188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); + 189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages)); + 190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Page Erase requested on address located on bank1 */ + 192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if (FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE) == HAL_OK) + 91 .loc 1 193 11 + 92 0058 4CF25030 movw r0, #50000 + 93 005c FFF7FEFF bl FLASH_WaitForLastOperation + ARM GAS /tmp/ccMLQ7U7.s page 6 + + + 94 0060 0346 mov r3, r0 + 95 .loc 1 193 10 discriminator 1 + 96 0062 002B cmp r3, #0 + 97 0064 2AD1 bne .L5 + 194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /*Initialization of PageError variable*/ + 196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** *PageError = 0xFFFFFFFFU; + 98 .loc 1 196 20 + 99 0066 3B68 ldr r3, [r7] + 100 0068 4FF0FF32 mov r2, #-1 + 101 006c 1A60 str r2, [r3] + 197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Erase page by page to be done*/ + 199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** for(address = pEraseInit->PageAddress; + 102 .loc 1 199 21 + 103 006e 7B68 ldr r3, [r7, #4] + 104 0070 5B68 ldr r3, [r3, #4] + 105 0072 BB60 str r3, [r7, #8] + 106 .loc 1 199 9 + 107 0074 19E0 b .L6 + 108 .L8: + 200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress); + 201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** address += FLASH_PAGE_SIZE) + 202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** FLASH_PageErase(address); + 109 .loc 1 203 11 + 110 0076 B868 ldr r0, [r7, #8] + 111 0078 FFF7FEFF bl FLASH_PageErase + 204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 112 .loc 1 206 20 + 113 007c 4CF25030 movw r0, #50000 + 114 0080 FFF7FEFF bl FLASH_WaitForLastOperation + 115 0084 0346 mov r3, r0 + 116 0086 FB73 strb r3, [r7, #15] + 207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* If the erase operation is completed, disable the PER Bit */ + 209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** CLEAR_BIT(FLASH->CR, FLASH_CR_PER); + 117 .loc 1 209 11 + 118 0088 114B ldr r3, .L9+4 + 119 008a 1B69 ldr r3, [r3, #16] + 120 008c 104A ldr r2, .L9+4 + 121 008e 23F00203 bic r3, r3, #2 + 122 0092 1361 str r3, [r2, #16] + 210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if (status != HAL_OK) + 123 .loc 1 211 14 + 124 0094 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 125 0096 002B cmp r3, #0 + 126 0098 03D0 beq .L7 + 212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* In case of error, stop erase procedure and return the faulty address */ + 214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** *PageError = address; + 127 .loc 1 214 24 + 128 009a 3B68 ldr r3, [r7] + 129 009c BA68 ldr r2, [r7, #8] + ARM GAS /tmp/ccMLQ7U7.s page 7 + + + 130 009e 1A60 str r2, [r3] + 215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** break; + 131 .loc 1 215 13 + 132 00a0 0CE0 b .L5 + 133 .L7: + 201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 134 .loc 1 201 21 + 135 00a2 BB68 ldr r3, [r7, #8] + 136 00a4 03F50063 add r3, r3, #2048 + 137 00a8 BB60 str r3, [r7, #8] + 138 .L6: + 200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** address += FLASH_PAGE_SIZE) + 139 .loc 1 200 35 + 140 00aa 7B68 ldr r3, [r7, #4] + 141 00ac 9B68 ldr r3, [r3, #8] + 200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** address += FLASH_PAGE_SIZE) + 142 .loc 1 200 45 + 143 00ae DA02 lsls r2, r3, #11 + 200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** address += FLASH_PAGE_SIZE) + 144 .loc 1 200 76 + 145 00b0 7B68 ldr r3, [r7, #4] + 146 00b2 5B68 ldr r3, [r3, #4] + 200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** address += FLASH_PAGE_SIZE) + 147 .loc 1 200 64 + 148 00b4 1344 add r3, r3, r2 + 200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** address += FLASH_PAGE_SIZE) + 149 .loc 1 200 21 + 150 00b6 BA68 ldr r2, [r7, #8] + 151 00b8 9A42 cmp r2, r3 + 152 00ba DCD3 bcc .L8 + 153 .L5: + 216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Process Unlocked */ + 222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** __HAL_UNLOCK(&pFlash); + 154 .loc 1 222 3 + 155 00bc 034B ldr r3, .L9 + 156 00be 0022 movs r2, #0 + 157 00c0 1A76 strb r2, [r3, #24] + 223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return status; + 158 .loc 1 224 10 + 159 00c2 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 160 .L3: + 225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 161 .loc 1 225 1 + 162 00c4 1846 mov r0, r3 + 163 00c6 1037 adds r7, r7, #16 + 164 .cfi_def_cfa_offset 8 + 165 00c8 BD46 mov sp, r7 + 166 .cfi_def_cfa_register 13 + 167 @ sp needed + 168 00ca 80BD pop {r7, pc} + 169 .L10: + ARM GAS /tmp/ccMLQ7U7.s page 8 + + + 170 .align 2 + 171 .L9: + 172 00cc 00000000 .word pFlash + 173 00d0 00200240 .word 1073881088 + 174 .cfi_endproc + 175 .LFE130: + 177 .section .text.HAL_FLASHEx_Erase_IT,"ax",%progbits + 178 .align 1 + 179 .global HAL_FLASHEx_Erase_IT + 180 .syntax unified + 181 .thumb + 182 .thumb_func + 184 HAL_FLASHEx_Erase_IT: + 185 .LFB131: + 226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + 228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled + 229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function + 230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * must be called before. + 231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * Call the @ref HAL_FLASH_Lock() to disable the flash memory access + 232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * (recommended to protect the FLASH memory against possible unwanted operation) + 233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + 234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * contains the configuration information for the erasing. + 235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * + 236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @retval HAL_StatusTypeDef HAL Status + 237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) + 239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 186 .loc 1 239 1 + 187 .cfi_startproc + 188 @ args = 0, pretend = 0, frame = 16 + 189 @ frame_needed = 1, uses_anonymous_args = 0 + 190 0000 80B5 push {r7, lr} + 191 .cfi_def_cfa_offset 8 + 192 .cfi_offset 7, -8 + 193 .cfi_offset 14, -4 + 194 0002 84B0 sub sp, sp, #16 + 195 .cfi_def_cfa_offset 24 + 196 0004 00AF add r7, sp, #0 + 197 .cfi_def_cfa_register 7 + 198 0006 7860 str r0, [r7, #4] + 240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 199 .loc 1 240 21 + 200 0008 0023 movs r3, #0 + 201 000a FB73 strb r3, [r7, #15] + 241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Process Locked */ + 243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** __HAL_LOCK(&pFlash); + 202 .loc 1 243 3 + 203 000c 1A4B ldr r3, .L17 + 204 000e 1B7E ldrb r3, [r3, #24] @ zero_extendqisi2 + 205 0010 012B cmp r3, #1 + 206 0012 01D1 bne .L12 + 207 .loc 1 243 3 is_stmt 0 discriminator 1 + 208 0014 0223 movs r3, #2 + 209 .loc 1 243 3 + 210 0016 2AE0 b .L13 + ARM GAS /tmp/ccMLQ7U7.s page 9 + + + 211 .L12: + 212 .loc 1 243 3 discriminator 2 + 213 0018 174B ldr r3, .L17 + 214 001a 0122 movs r2, #1 + 215 001c 1A76 strb r2, [r3, #24] + 244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* If procedure already ongoing, reject the next one */ + 246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE) + 216 .loc 1 246 13 is_stmt 1 + 217 001e 164B ldr r3, .L17 + 218 0020 1B78 ldrb r3, [r3] + 219 0022 DBB2 uxtb r3, r3 + 220 .loc 1 246 6 + 221 0024 002B cmp r3, #0 + 222 0026 01D0 beq .L14 + 247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return HAL_ERROR; + 223 .loc 1 248 12 + 224 0028 0123 movs r3, #1 + 225 002a 20E0 b .L13 + 226 .L14: + 249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Check the parameters */ + 252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + 253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Enable End of FLASH Operation and Error source interrupts */ + 255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); + 227 .loc 1 255 3 + 228 002c 134B ldr r3, .L17+4 + 229 002e 1B69 ldr r3, [r3, #16] + 230 0030 124A ldr r2, .L17+4 + 231 0032 43F4A053 orr r3, r3, #5120 + 232 0036 1361 str r3, [r2, #16] + 256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) + 233 .loc 1 257 17 + 234 0038 7B68 ldr r3, [r7, #4] + 235 003a 1B68 ldr r3, [r3] + 236 .loc 1 257 6 + 237 003c 012B cmp r3, #1 + 238 003e 05D1 bne .L15 + 258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /*Mass erase to be done*/ + 260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE; + 239 .loc 1 260 29 + 240 0040 0D4B ldr r3, .L17 + 241 0042 0222 movs r2, #2 + 242 0044 1A70 strb r2, [r3] + 261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** FLASH_MassErase(); + 243 .loc 1 261 9 + 244 0046 FFF7FEFF bl FLASH_MassErase + 245 004a 0FE0 b .L16 + 246 .L15: + 262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** else + 264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + ARM GAS /tmp/ccMLQ7U7.s page 10 + + + 265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Erase by page to be done*/ + 266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Check the parameters */ + 268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); + 269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** assert_param(IS_FLASH_NB_PAGES(pEraseInit->PageAddress, pEraseInit->NbPages)); + 270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** pFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE; + 247 .loc 1 271 29 + 248 004c 0A4B ldr r3, .L17 + 249 004e 0122 movs r2, #1 + 250 0050 1A70 strb r2, [r3] + 272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** pFlash.DataRemaining = pEraseInit->NbPages; + 251 .loc 1 272 38 + 252 0052 7B68 ldr r3, [r7, #4] + 253 0054 9B68 ldr r3, [r3, #8] + 254 .loc 1 272 26 + 255 0056 084A ldr r2, .L17 + 256 0058 5360 str r3, [r2, #4] + 273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** pFlash.Address = pEraseInit->PageAddress; + 257 .loc 1 273 32 + 258 005a 7B68 ldr r3, [r7, #4] + 259 005c 5B68 ldr r3, [r3, #4] + 260 .loc 1 273 20 + 261 005e 064A ldr r2, .L17 + 262 0060 9360 str r3, [r2, #8] + 274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /*Erase 1st page and wait for IT*/ + 276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** FLASH_PageErase(pEraseInit->PageAddress); + 263 .loc 1 276 5 + 264 0062 7B68 ldr r3, [r7, #4] + 265 0064 5B68 ldr r3, [r3, #4] + 266 0066 1846 mov r0, r3 + 267 0068 FFF7FEFF bl FLASH_PageErase + 268 .L16: + 277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return status; + 269 .loc 1 279 10 + 270 006c FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 271 .L13: + 280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 272 .loc 1 280 1 + 273 006e 1846 mov r0, r3 + 274 0070 1037 adds r7, r7, #16 + 275 .cfi_def_cfa_offset 8 + 276 0072 BD46 mov sp, r7 + 277 .cfi_def_cfa_register 13 + 278 @ sp needed + 279 0074 80BD pop {r7, pc} + 280 .L18: + 281 0076 00BF .align 2 + 282 .L17: + 283 0078 00000000 .word pFlash + 284 007c 00200240 .word 1073881088 + 285 .cfi_endproc + 286 .LFE131: + 288 .section .text.HAL_FLASHEx_OBErase,"ax",%progbits + ARM GAS /tmp/ccMLQ7U7.s page 11 + + + 289 .align 1 + 290 .global HAL_FLASHEx_OBErase + 291 .syntax unified + 292 .thumb + 293 .thumb_func + 295 HAL_FLASHEx_OBErase: + 296 .LFB132: + 281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + 283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @} + 284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** @defgroup FLASHEx_Exported_Functions_Group2 Option Bytes Programming functions + 287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @brief Option Bytes Programming functions + 288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * + 289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** @verbatim + 290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** ============================================================================== + 291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** ##### Option Bytes Programming functions ##### + 292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** ============================================================================== + 293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** [..] + 294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** This subsection provides a set of functions allowing to control the FLASH + 295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** option bytes operations. + 296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** @endverbatim + 298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @{ + 299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + 302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @brief Erases the FLASH option bytes. + 303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @note This functions erases all option bytes except the Read protection (RDP). + 304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interf + 305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options b + 306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of t + 307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * (system reset will occur) + 308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @retval HAL status + 309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** HAL_StatusTypeDef HAL_FLASHEx_OBErase(void) + 312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 297 .loc 1 312 1 + 298 .cfi_startproc + 299 @ args = 0, pretend = 0, frame = 8 + 300 @ frame_needed = 1, uses_anonymous_args = 0 + 301 0000 80B5 push {r7, lr} + 302 .cfi_def_cfa_offset 8 + 303 .cfi_offset 7, -8 + 304 .cfi_offset 14, -4 + 305 0002 82B0 sub sp, sp, #8 + 306 .cfi_def_cfa_offset 16 + 307 0004 00AF add r7, sp, #0 + 308 .cfi_def_cfa_register 7 + 313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** uint8_t rdptmp = OB_RDP_LEVEL_0; + 309 .loc 1 313 11 + 310 0006 AA23 movs r3, #170 + 311 0008 BB71 strb r3, [r7, #6] + 314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_ERROR; + 312 .loc 1 314 21 + ARM GAS /tmp/ccMLQ7U7.s page 12 + + + 313 000a 0123 movs r3, #1 + 314 000c FB71 strb r3, [r7, #7] + 315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Get the actual read protection Option Byte value */ + 317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** rdptmp = FLASH_OB_GetRDP(); + 315 .loc 1 317 12 + 316 000e FFF7FEFF bl FLASH_OB_GetRDP + 317 0012 0346 mov r3, r0 + 318 .loc 1 317 10 discriminator 1 + 319 0014 BB71 strb r3, [r7, #6] + 318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 320 .loc 1 320 12 + 321 0016 4CF25030 movw r0, #50000 + 322 001a FFF7FEFF bl FLASH_WaitForLastOperation + 323 001e 0346 mov r3, r0 + 324 0020 FB71 strb r3, [r7, #7] + 321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if(status == HAL_OK) + 325 .loc 1 322 5 + 326 0022 FB79 ldrb r3, [r7, #7] @ zero_extendqisi2 + 327 0024 002B cmp r3, #0 + 328 0026 23D1 bne .L20 + 323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Clean the error context */ + 325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + 329 .loc 1 325 22 + 330 0028 144B ldr r3, .L22 + 331 002a 0022 movs r2, #0 + 332 002c DA61 str r2, [r3, #28] + 326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* If the previous operation is completed, proceed to erase the option bytes */ + 328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** SET_BIT(FLASH->CR, FLASH_CR_OPTER); + 333 .loc 1 328 5 + 334 002e 144B ldr r3, .L22+4 + 335 0030 1B69 ldr r3, [r3, #16] + 336 0032 134A ldr r2, .L22+4 + 337 0034 43F02003 orr r3, r3, #32 + 338 0038 1361 str r3, [r2, #16] + 329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** SET_BIT(FLASH->CR, FLASH_CR_STRT); + 339 .loc 1 329 5 + 340 003a 114B ldr r3, .L22+4 + 341 003c 1B69 ldr r3, [r3, #16] + 342 003e 104A ldr r2, .L22+4 + 343 0040 43F04003 orr r3, r3, #64 + 344 0044 1361 str r3, [r2, #16] + 330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 345 .loc 1 332 14 + 346 0046 4CF25030 movw r0, #50000 + 347 004a FFF7FEFF bl FLASH_WaitForLastOperation + 348 004e 0346 mov r3, r0 + 349 0050 FB71 strb r3, [r7, #7] + 333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* If the erase operation is completed, disable the OPTER Bit */ + ARM GAS /tmp/ccMLQ7U7.s page 13 + + + 335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER); + 350 .loc 1 335 5 + 351 0052 0B4B ldr r3, .L22+4 + 352 0054 1B69 ldr r3, [r3, #16] + 353 0056 0A4A ldr r2, .L22+4 + 354 0058 23F02003 bic r3, r3, #32 + 355 005c 1361 str r3, [r2, #16] + 336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if(status == HAL_OK) + 356 .loc 1 337 7 + 357 005e FB79 ldrb r3, [r7, #7] @ zero_extendqisi2 + 358 0060 002B cmp r3, #0 + 359 0062 05D1 bne .L20 + 338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Restore the last read protection Option Byte value */ + 340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_OB_RDP_LevelConfig(rdptmp); + 360 .loc 1 340 16 + 361 0064 BB79 ldrb r3, [r7, #6] @ zero_extendqisi2 + 362 0066 1846 mov r0, r3 + 363 0068 FFF7FEFF bl FLASH_OB_RDP_LevelConfig + 364 006c 0346 mov r3, r0 + 365 006e FB71 strb r3, [r7, #7] + 366 .L20: + 341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Return the erase status */ + 345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return status; + 367 .loc 1 345 10 + 368 0070 FB79 ldrb r3, [r7, #7] @ zero_extendqisi2 + 346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 369 .loc 1 346 1 + 370 0072 1846 mov r0, r3 + 371 0074 0837 adds r7, r7, #8 + 372 .cfi_def_cfa_offset 8 + 373 0076 BD46 mov sp, r7 + 374 .cfi_def_cfa_register 13 + 375 @ sp needed + 376 0078 80BD pop {r7, pc} + 377 .L23: + 378 007a 00BF .align 2 + 379 .L22: + 380 007c 00000000 .word pFlash + 381 0080 00200240 .word 1073881088 + 382 .cfi_endproc + 383 .LFE132: + 385 .section .text.HAL_FLASHEx_OBProgram,"ax",%progbits + 386 .align 1 + 387 .global HAL_FLASHEx_OBProgram + 388 .syntax unified + 389 .thumb + 390 .thumb_func + 392 HAL_FLASHEx_OBProgram: + 393 .LFB133: + 347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + 349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @brief Program option bytes + ARM GAS /tmp/ccMLQ7U7.s page 14 + + + 350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interf + 351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options b + 352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of t + 353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * (system reset will occur) + 354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * + 355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @param pOBInit pointer to an FLASH_OBInitStruct structure that + 356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * contains the configuration information for the programming. + 357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * + 358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @retval HAL_StatusTypeDef HAL Status + 359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) + 361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 394 .loc 1 361 1 + 395 .cfi_startproc + 396 @ args = 0, pretend = 0, frame = 16 + 397 @ frame_needed = 1, uses_anonymous_args = 0 + 398 0000 80B5 push {r7, lr} + 399 .cfi_def_cfa_offset 8 + 400 .cfi_offset 7, -8 + 401 .cfi_offset 14, -4 + 402 0002 84B0 sub sp, sp, #16 + 403 .cfi_def_cfa_offset 24 + 404 0004 00AF add r7, sp, #0 + 405 .cfi_def_cfa_register 7 + 406 0006 7860 str r0, [r7, #4] + 362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_ERROR; + 407 .loc 1 362 21 + 408 0008 0123 movs r3, #1 + 409 000a FB73 strb r3, [r7, #15] + 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Process Locked */ + 365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** __HAL_LOCK(&pFlash); + 410 .loc 1 365 3 + 411 000c 394B ldr r3, .L33 + 412 000e 1B7E ldrb r3, [r3, #24] @ zero_extendqisi2 + 413 0010 012B cmp r3, #1 + 414 0012 01D1 bne .L25 + 415 .loc 1 365 3 is_stmt 0 discriminator 1 + 416 0014 0223 movs r3, #2 + 417 .loc 1 365 3 + 418 0016 69E0 b .L26 + 419 .L25: + 420 .loc 1 365 3 discriminator 2 + 421 0018 364B ldr r3, .L33 + 422 001a 0122 movs r2, #1 + 423 001c 1A76 strb r2, [r3, #24] + 366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Check the parameters */ + 368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); + 369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Write protection configuration */ + 371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP) + 424 .loc 1 371 14 is_stmt 1 + 425 001e 7B68 ldr r3, [r7, #4] + 426 0020 1B68 ldr r3, [r3] + 427 .loc 1 371 27 + 428 0022 03F00103 and r3, r3, #1 + ARM GAS /tmp/ccMLQ7U7.s page 15 + + + 429 .loc 1 371 5 + 430 0026 002B cmp r3, #0 + 431 0028 1AD0 beq .L27 + 372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** assert_param(IS_WRPSTATE(pOBInit->WRPState)); + 374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if (pOBInit->WRPState == OB_WRPSTATE_ENABLE) + 432 .loc 1 374 16 + 433 002a 7B68 ldr r3, [r7, #4] + 434 002c 5B68 ldr r3, [r3, #4] + 435 .loc 1 374 8 + 436 002e 012B cmp r3, #1 + 437 0030 07D1 bne .L28 + 375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Enable of Write protection on the selected page */ + 377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_OB_EnableWRP(pOBInit->WRPPage); + 438 .loc 1 377 16 + 439 0032 7B68 ldr r3, [r7, #4] + 440 0034 9B68 ldr r3, [r3, #8] + 441 0036 1846 mov r0, r3 + 442 0038 FFF7FEFF bl FLASH_OB_EnableWRP + 443 003c 0346 mov r3, r0 + 444 003e FB73 strb r3, [r7, #15] + 445 0040 06E0 b .L29 + 446 .L28: + 378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** else + 380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Disable of Write protection on the selected page */ + 382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_OB_DisableWRP(pOBInit->WRPPage); + 447 .loc 1 382 16 + 448 0042 7B68 ldr r3, [r7, #4] + 449 0044 9B68 ldr r3, [r3, #8] + 450 0046 1846 mov r0, r3 + 451 0048 FFF7FEFF bl FLASH_OB_DisableWRP + 452 004c 0346 mov r3, r0 + 453 004e FB73 strb r3, [r7, #15] + 454 .L29: + 383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if (status != HAL_OK) + 455 .loc 1 384 8 + 456 0050 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 457 0052 002B cmp r3, #0 + 458 0054 04D0 beq .L27 + 385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Process Unlocked */ + 387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** __HAL_UNLOCK(&pFlash); + 459 .loc 1 387 7 + 460 0056 274B ldr r3, .L33 + 461 0058 0022 movs r2, #0 + 462 005a 1A76 strb r2, [r3, #24] + 388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return status; + 463 .loc 1 388 14 + 464 005c FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 465 005e 45E0 b .L26 + 466 .L27: + 389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + ARM GAS /tmp/ccMLQ7U7.s page 16 + + + 391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Read protection configuration */ + 393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP) + 467 .loc 1 393 14 + 468 0060 7B68 ldr r3, [r7, #4] + 469 0062 1B68 ldr r3, [r3] + 470 .loc 1 393 27 + 471 0064 03F00203 and r3, r3, #2 + 472 .loc 1 393 5 + 473 0068 002B cmp r3, #0 + 474 006a 0ED0 beq .L30 + 394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel); + 475 .loc 1 395 14 + 476 006c 7B68 ldr r3, [r7, #4] + 477 006e 1B7B ldrb r3, [r3, #12] @ zero_extendqisi2 + 478 0070 1846 mov r0, r3 + 479 0072 FFF7FEFF bl FLASH_OB_RDP_LevelConfig + 480 0076 0346 mov r3, r0 + 481 0078 FB73 strb r3, [r7, #15] + 396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if (status != HAL_OK) + 482 .loc 1 396 8 + 483 007a FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 484 007c 002B cmp r3, #0 + 485 007e 04D0 beq .L30 + 397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Process Unlocked */ + 399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** __HAL_UNLOCK(&pFlash); + 486 .loc 1 399 7 + 487 0080 1C4B ldr r3, .L33 + 488 0082 0022 movs r2, #0 + 489 0084 1A76 strb r2, [r3, #24] + 400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return status; + 490 .loc 1 400 14 + 491 0086 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 492 0088 30E0 b .L26 + 493 .L30: + 401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* USER configuration */ + 405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER) + 494 .loc 1 405 14 + 495 008a 7B68 ldr r3, [r7, #4] + 496 008c 1B68 ldr r3, [r3] + 497 .loc 1 405 27 + 498 008e 03F00403 and r3, r3, #4 + 499 .loc 1 405 5 + 500 0092 002B cmp r3, #0 + 501 0094 0ED0 beq .L31 + 406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_OB_UserConfig(pOBInit->USERConfig); + 502 .loc 1 407 14 + 503 0096 7B68 ldr r3, [r7, #4] + 504 0098 5B7B ldrb r3, [r3, #13] @ zero_extendqisi2 + 505 009a 1846 mov r0, r3 + 506 009c FFF7FEFF bl FLASH_OB_UserConfig + ARM GAS /tmp/ccMLQ7U7.s page 17 + + + 507 00a0 0346 mov r3, r0 + 508 00a2 FB73 strb r3, [r7, #15] + 408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if (status != HAL_OK) + 509 .loc 1 408 8 + 510 00a4 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 511 00a6 002B cmp r3, #0 + 512 00a8 04D0 beq .L31 + 409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Process Unlocked */ + 411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** __HAL_UNLOCK(&pFlash); + 513 .loc 1 411 7 + 514 00aa 124B ldr r3, .L33 + 515 00ac 0022 movs r2, #0 + 516 00ae 1A76 strb r2, [r3, #24] + 412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return status; + 517 .loc 1 412 14 + 518 00b0 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 519 00b2 1BE0 b .L26 + 520 .L31: + 413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* DATA configuration*/ + 417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if((pOBInit->OptionType & OPTIONBYTE_DATA) == OPTIONBYTE_DATA) + 521 .loc 1 417 14 + 522 00b4 7B68 ldr r3, [r7, #4] + 523 00b6 1B68 ldr r3, [r3] + 524 .loc 1 417 27 + 525 00b8 03F00803 and r3, r3, #8 + 526 .loc 1 417 5 + 527 00bc 002B cmp r3, #0 + 528 00be 11D0 beq .L32 + 418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_OB_ProgramData(pOBInit->DATAAddress, pOBInit->DATAData); + 529 .loc 1 419 14 + 530 00c0 7B68 ldr r3, [r7, #4] + 531 00c2 1A69 ldr r2, [r3, #16] + 532 00c4 7B68 ldr r3, [r7, #4] + 533 00c6 1B7D ldrb r3, [r3, #20] @ zero_extendqisi2 + 534 00c8 1946 mov r1, r3 + 535 00ca 1046 mov r0, r2 + 536 00cc FFF7FEFF bl FLASH_OB_ProgramData + 537 00d0 0346 mov r3, r0 + 538 00d2 FB73 strb r3, [r7, #15] + 420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if (status != HAL_OK) + 539 .loc 1 420 8 + 540 00d4 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 541 00d6 002B cmp r3, #0 + 542 00d8 04D0 beq .L32 + 421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Process Unlocked */ + 423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** __HAL_UNLOCK(&pFlash); + 543 .loc 1 423 7 + 544 00da 064B ldr r3, .L33 + 545 00dc 0022 movs r2, #0 + 546 00de 1A76 strb r2, [r3, #24] + 424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return status; + ARM GAS /tmp/ccMLQ7U7.s page 18 + + + 547 .loc 1 424 14 + 548 00e0 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 549 00e2 03E0 b .L26 + 550 .L32: + 425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Process Unlocked */ + 429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** __HAL_UNLOCK(&pFlash); + 551 .loc 1 429 3 + 552 00e4 034B ldr r3, .L33 + 553 00e6 0022 movs r2, #0 + 554 00e8 1A76 strb r2, [r3, #24] + 430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return status; + 555 .loc 1 431 10 + 556 00ea FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 557 .L26: + 432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 558 .loc 1 432 1 + 559 00ec 1846 mov r0, r3 + 560 00ee 1037 adds r7, r7, #16 + 561 .cfi_def_cfa_offset 8 + 562 00f0 BD46 mov sp, r7 + 563 .cfi_def_cfa_register 13 + 564 @ sp needed + 565 00f2 80BD pop {r7, pc} + 566 .L34: + 567 .align 2 + 568 .L33: + 569 00f4 00000000 .word pFlash + 570 .cfi_endproc + 571 .LFE133: + 573 .section .text.HAL_FLASHEx_OBGetConfig,"ax",%progbits + 574 .align 1 + 575 .global HAL_FLASHEx_OBGetConfig + 576 .syntax unified + 577 .thumb + 578 .thumb_func + 580 HAL_FLASHEx_OBGetConfig: + 581 .LFB134: + 433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + 435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @brief Get the Option byte configuration + 436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @param pOBInit pointer to an FLASH_OBInitStruct structure that + 437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * contains the configuration information for the programming. + 438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * + 439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @retval None + 440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) + 442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 582 .loc 1 442 1 + 583 .cfi_startproc + 584 @ args = 0, pretend = 0, frame = 8 + 585 @ frame_needed = 1, uses_anonymous_args = 0 + 586 0000 80B5 push {r7, lr} + 587 .cfi_def_cfa_offset 8 + ARM GAS /tmp/ccMLQ7U7.s page 19 + + + 588 .cfi_offset 7, -8 + 589 .cfi_offset 14, -4 + 590 0002 82B0 sub sp, sp, #8 + 591 .cfi_def_cfa_offset 16 + 592 0004 00AF add r7, sp, #0 + 593 .cfi_def_cfa_register 7 + 594 0006 7860 str r0, [r7, #4] + 443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER; + 595 .loc 1 443 23 + 596 0008 7B68 ldr r3, [r7, #4] + 597 000a 0722 movs r2, #7 + 598 000c 1A60 str r2, [r3] + 444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /*Get WRP*/ + 446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** pOBInit->WRPPage = FLASH_OB_GetWRP(); + 599 .loc 1 446 22 + 600 000e FFF7FEFF bl FLASH_OB_GetWRP + 601 0012 0246 mov r2, r0 + 602 .loc 1 446 20 discriminator 1 + 603 0014 7B68 ldr r3, [r7, #4] + 604 0016 9A60 str r2, [r3, #8] + 447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /*Get RDP Level*/ + 449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** pOBInit->RDPLevel = FLASH_OB_GetRDP(); + 605 .loc 1 449 23 + 606 0018 FFF7FEFF bl FLASH_OB_GetRDP + 607 001c 0346 mov r3, r0 + 608 .loc 1 449 21 discriminator 1 + 609 001e DAB2 uxtb r2, r3 + 610 0020 7B68 ldr r3, [r7, #4] + 611 0022 1A73 strb r2, [r3, #12] + 450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /*Get USER*/ + 452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** pOBInit->USERConfig = FLASH_OB_GetUser(); + 612 .loc 1 452 25 + 613 0024 FFF7FEFF bl FLASH_OB_GetUser + 614 0028 0346 mov r3, r0 + 615 002a 1A46 mov r2, r3 + 616 .loc 1 452 23 discriminator 1 + 617 002c 7B68 ldr r3, [r7, #4] + 618 002e 5A73 strb r2, [r3, #13] + 453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 619 .loc 1 453 1 + 620 0030 00BF nop + 621 0032 0837 adds r7, r7, #8 + 622 .cfi_def_cfa_offset 8 + 623 0034 BD46 mov sp, r7 + 624 .cfi_def_cfa_register 13 + 625 @ sp needed + 626 0036 80BD pop {r7, pc} + 627 .cfi_endproc + 628 .LFE134: + 630 .section .text.HAL_FLASHEx_OBGetUserData,"ax",%progbits + 631 .align 1 + 632 .global HAL_FLASHEx_OBGetUserData + 633 .syntax unified + 634 .thumb + ARM GAS /tmp/ccMLQ7U7.s page 20 + + + 635 .thumb_func + 637 HAL_FLASHEx_OBGetUserData: + 638 .LFB135: + 454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + 456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @brief Get the Option byte user data + 457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @param DATAAdress Address of the option byte DATA + 458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * This parameter can be one of the following values: + 459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @arg @ref OB_DATA_ADDRESS_DATA0 + 460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @arg @ref OB_DATA_ADDRESS_DATA1 + 461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @retval Value programmed in USER data + 462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress) + 464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 639 .loc 1 464 1 + 640 .cfi_startproc + 641 @ args = 0, pretend = 0, frame = 32 + 642 @ frame_needed = 1, uses_anonymous_args = 0 + 643 @ link register save eliminated. + 644 0000 80B4 push {r7} + 645 .cfi_def_cfa_offset 4 + 646 .cfi_offset 7, -4 + 647 0002 89B0 sub sp, sp, #36 + 648 .cfi_def_cfa_offset 40 + 649 0004 00AF add r7, sp, #0 + 650 .cfi_def_cfa_register 7 + 651 0006 7860 str r0, [r7, #4] + 465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** uint32_t value = 0U; + 652 .loc 1 465 12 + 653 0008 0023 movs r3, #0 + 654 000a FB61 str r3, [r7, #28] + 466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if (DATAAdress == OB_DATA_ADDRESS_DATA0) + 655 .loc 1 467 6 + 656 000c 7B68 ldr r3, [r7, #4] + 657 000e 164A ldr r2, .L42 + 658 0010 9342 cmp r3, r2 + 659 0012 11D1 bne .L37 + 468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Get value programmed in OB USER Data0 */ + 470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA0) >> FLASH_POSITION_OB_USERDATA0_BIT; + 660 .loc 1 470 13 + 661 0014 154B ldr r3, .L42+4 + 662 0016 DB69 ldr r3, [r3, #28] + 663 0018 03F47F03 and r3, r3, #16711680 + 664 001c 4FF47F02 mov r2, #16711680 + 665 0020 BA61 str r2, [r7, #24] + 666 .LBB8: + 667 .LBB9: + 668 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h" + 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** + 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h + 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file + 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.0.4 + 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 09. April 2018 + 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ + 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* + ARM GAS /tmp/ccMLQ7U7.s page 21 + + + 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 + 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may + 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. + 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at + 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 + 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software + 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT + 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and + 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. + 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 24:Drivers/CMSIS/Include/cmsis_gcc.h **** + 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H + 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H + 27:Drivers/CMSIS/Include/cmsis_gcc.h **** + 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ + 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" + 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" + 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" + 33:Drivers/CMSIS/Include/cmsis_gcc.h **** + 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ + 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin + 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) + 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 38:Drivers/CMSIS/Include/cmsis_gcc.h **** + 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ + 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM + 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm + 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE + 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline + 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE + 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline + 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE + 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline + 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN + 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) + 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED + 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) + 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK + 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) + 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED + 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) + 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT + ARM GAS /tmp/ccMLQ7U7.s page 22 + + + 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION + 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) + 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ + 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE + 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- + 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ + 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add + 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE + 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- + 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ + 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add + 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED + 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) + 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT + 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict + 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 116:Drivers/CMSIS/Include/cmsis_gcc.h **** + 117:Drivers/CMSIS/Include/cmsis_gcc.h **** + 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ + 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface + 120:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + 121:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + ARM GAS /tmp/ccMLQ7U7.s page 23 + + + 122:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 123:Drivers/CMSIS/Include/cmsis_gcc.h **** + 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts + 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + 127:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 128:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) + 130:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); + 132:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 133:Drivers/CMSIS/Include/cmsis_gcc.h **** + 134:Drivers/CMSIS/Include/cmsis_gcc.h **** + 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 136:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts + 137:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. + 138:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 139:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) + 141:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 142:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); + 143:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 144:Drivers/CMSIS/Include/cmsis_gcc.h **** + 145:Drivers/CMSIS/Include/cmsis_gcc.h **** + 146:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 147:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register + 148:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register. + 149:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value + 150:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) + 152:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 153:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 154:Drivers/CMSIS/Include/cmsis_gcc.h **** + 155:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) ); + 156:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 157:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 158:Drivers/CMSIS/Include/cmsis_gcc.h **** + 159:Drivers/CMSIS/Include/cmsis_gcc.h **** + 160:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 161:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 162:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register (non-secure) + 163:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the non-secure Control Register when in secure mode. + 164:Drivers/CMSIS/Include/cmsis_gcc.h **** \return non-secure Control Register value + 165:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 166:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) + 167:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 168:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 169:Drivers/CMSIS/Include/cmsis_gcc.h **** + 170:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + 171:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 172:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 174:Drivers/CMSIS/Include/cmsis_gcc.h **** + 175:Drivers/CMSIS/Include/cmsis_gcc.h **** + 176:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 177:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register + 178:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register. + ARM GAS /tmp/ccMLQ7U7.s page 24 + + + 179:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 180:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 181:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) + 182:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 183:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + 184:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 185:Drivers/CMSIS/Include/cmsis_gcc.h **** + 186:Drivers/CMSIS/Include/cmsis_gcc.h **** + 187:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 188:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 189:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register (non-secure) + 190:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the non-secure Control Register when in secure state. + 191:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 192:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 193:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) + 194:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 195:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + 196:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 197:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 198:Drivers/CMSIS/Include/cmsis_gcc.h **** + 199:Drivers/CMSIS/Include/cmsis_gcc.h **** + 200:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 201:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register + 202:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register. + 203:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value + 204:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void) + 206:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 207:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 208:Drivers/CMSIS/Include/cmsis_gcc.h **** + 209:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 210:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 211:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 212:Drivers/CMSIS/Include/cmsis_gcc.h **** + 213:Drivers/CMSIS/Include/cmsis_gcc.h **** + 214:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 215:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register + 216:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register. + 217:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value + 218:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 219:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void) + 220:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 221:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 222:Drivers/CMSIS/Include/cmsis_gcc.h **** + 223:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + 224:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 225:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 226:Drivers/CMSIS/Include/cmsis_gcc.h **** + 227:Drivers/CMSIS/Include/cmsis_gcc.h **** + 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 229:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register + 230:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register. + 231:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value + 232:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void) + 234:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 235:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + ARM GAS /tmp/ccMLQ7U7.s page 25 + + + 236:Drivers/CMSIS/Include/cmsis_gcc.h **** + 237:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + 238:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 239:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 240:Drivers/CMSIS/Include/cmsis_gcc.h **** + 241:Drivers/CMSIS/Include/cmsis_gcc.h **** + 242:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 243:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer + 244:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP). + 245:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 246:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 247:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void) + 248:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 249:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 250:Drivers/CMSIS/Include/cmsis_gcc.h **** + 251:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp" : "=r" (result) ); + 252:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 253:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 254:Drivers/CMSIS/Include/cmsis_gcc.h **** + 255:Drivers/CMSIS/Include/cmsis_gcc.h **** + 256:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 257:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 258:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer (non-secure) + 259:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s + 260:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 261:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) + 263:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 264:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 265:Drivers/CMSIS/Include/cmsis_gcc.h **** + 266:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + 267:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 268:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 269:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 270:Drivers/CMSIS/Include/cmsis_gcc.h **** + 271:Drivers/CMSIS/Include/cmsis_gcc.h **** + 272:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 273:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer + 274:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP). + 275:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 276:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 277:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) + 278:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 279:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); + 280:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 281:Drivers/CMSIS/Include/cmsis_gcc.h **** + 282:Drivers/CMSIS/Include/cmsis_gcc.h **** + 283:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 284:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 285:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + 286:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta + 287:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 288:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 289:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) + 290:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 291:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); + 292:Drivers/CMSIS/Include/cmsis_gcc.h **** } + ARM GAS /tmp/ccMLQ7U7.s page 26 + + + 293:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 294:Drivers/CMSIS/Include/cmsis_gcc.h **** + 295:Drivers/CMSIS/Include/cmsis_gcc.h **** + 296:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 297:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer + 298:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP). + 299:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 300:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 301:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void) + 302:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 303:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 304:Drivers/CMSIS/Include/cmsis_gcc.h **** + 305:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp" : "=r" (result) ); + 306:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 307:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 308:Drivers/CMSIS/Include/cmsis_gcc.h **** + 309:Drivers/CMSIS/Include/cmsis_gcc.h **** + 310:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 311:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 312:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer (non-secure) + 313:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat + 314:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 315:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 316:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) + 317:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 318:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 319:Drivers/CMSIS/Include/cmsis_gcc.h **** + 320:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + 321:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 322:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 324:Drivers/CMSIS/Include/cmsis_gcc.h **** + 325:Drivers/CMSIS/Include/cmsis_gcc.h **** + 326:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 327:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer + 328:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP). + 329:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 330:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 331:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) + 332:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 333:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); + 334:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 335:Drivers/CMSIS/Include/cmsis_gcc.h **** + 336:Drivers/CMSIS/Include/cmsis_gcc.h **** + 337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 338:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 339:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer (non-secure) + 340:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + 341:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 342:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 343:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) + 344:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 345:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); + 346:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 347:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 348:Drivers/CMSIS/Include/cmsis_gcc.h **** + 349:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccMLQ7U7.s page 27 + + + 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 352:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Stack Pointer (non-secure) + 353:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + 354:Drivers/CMSIS/Include/cmsis_gcc.h **** \return SP Register value + 355:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) + 357:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 358:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 359:Drivers/CMSIS/Include/cmsis_gcc.h **** + 360:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + 361:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 362:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 363:Drivers/CMSIS/Include/cmsis_gcc.h **** + 364:Drivers/CMSIS/Include/cmsis_gcc.h **** + 365:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 366:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Stack Pointer (non-secure) + 367:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + 368:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfStack Stack Pointer value to set + 369:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 370:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) + 371:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 372:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); + 373:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 374:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 375:Drivers/CMSIS/Include/cmsis_gcc.h **** + 376:Drivers/CMSIS/Include/cmsis_gcc.h **** + 377:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 378:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask + 379:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register. + 380:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 381:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 382:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) + 383:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 384:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 385:Drivers/CMSIS/Include/cmsis_gcc.h **** + 386:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 387:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 388:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 389:Drivers/CMSIS/Include/cmsis_gcc.h **** + 390:Drivers/CMSIS/Include/cmsis_gcc.h **** + 391:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 392:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 393:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask (non-secure) + 394:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg + 395:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 396:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 397:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) + 398:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 399:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 400:Drivers/CMSIS/Include/cmsis_gcc.h **** + 401:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + 402:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 403:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 405:Drivers/CMSIS/Include/cmsis_gcc.h **** + 406:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccMLQ7U7.s page 28 + + + 407:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 408:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask + 409:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register. + 410:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 411:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 412:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) + 413:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 414:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 415:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 416:Drivers/CMSIS/Include/cmsis_gcc.h **** + 417:Drivers/CMSIS/Include/cmsis_gcc.h **** + 418:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 419:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 420:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask (non-secure) + 421:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + 422:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 423:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 424:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) + 425:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 426:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); + 427:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 428:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 429:Drivers/CMSIS/Include/cmsis_gcc.h **** + 430:Drivers/CMSIS/Include/cmsis_gcc.h **** + 431:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 432:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 433:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + 434:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 435:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ + 436:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + 437:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 438:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 439:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void) + 440:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 441:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory"); + 442:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 443:Drivers/CMSIS/Include/cmsis_gcc.h **** + 444:Drivers/CMSIS/Include/cmsis_gcc.h **** + 445:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 446:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ + 447:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR. + 448:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 449:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 450:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void) + 451:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 452:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory"); + 453:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 454:Drivers/CMSIS/Include/cmsis_gcc.h **** + 455:Drivers/CMSIS/Include/cmsis_gcc.h **** + 456:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 457:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority + 458:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register. + 459:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 460:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 461:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) + 462:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 463:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + ARM GAS /tmp/ccMLQ7U7.s page 29 + + + 464:Drivers/CMSIS/Include/cmsis_gcc.h **** + 465:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + 466:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 467:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 468:Drivers/CMSIS/Include/cmsis_gcc.h **** + 469:Drivers/CMSIS/Include/cmsis_gcc.h **** + 470:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 471:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 472:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority (non-secure) + 473:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Base Priority register when in secure state. + 474:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 475:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) + 477:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 478:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 479:Drivers/CMSIS/Include/cmsis_gcc.h **** + 480:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + 481:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 482:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 483:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 484:Drivers/CMSIS/Include/cmsis_gcc.h **** + 485:Drivers/CMSIS/Include/cmsis_gcc.h **** + 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 487:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority + 488:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register. + 489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 490:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) + 492:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 493:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); + 494:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 495:Drivers/CMSIS/Include/cmsis_gcc.h **** + 496:Drivers/CMSIS/Include/cmsis_gcc.h **** + 497:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 498:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 499:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority (non-secure) + 500:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Base Priority register when in secure state. + 501:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 502:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 503:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) + 504:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 505:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); + 506:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 507:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 508:Drivers/CMSIS/Include/cmsis_gcc.h **** + 509:Drivers/CMSIS/Include/cmsis_gcc.h **** + 510:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 511:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition + 512:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable + 513:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level. + 514:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 515:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 516:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) + 517:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 518:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); + 519:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 520:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccMLQ7U7.s page 30 + + + 521:Drivers/CMSIS/Include/cmsis_gcc.h **** + 522:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 523:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask + 524:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register. + 525:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 526:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) + 528:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 529:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 530:Drivers/CMSIS/Include/cmsis_gcc.h **** + 531:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + 532:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 533:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 534:Drivers/CMSIS/Include/cmsis_gcc.h **** + 535:Drivers/CMSIS/Include/cmsis_gcc.h **** + 536:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 537:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 538:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask (non-secure) + 539:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Fault Mask register when in secure state. + 540:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 541:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 542:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) + 543:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 544:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 545:Drivers/CMSIS/Include/cmsis_gcc.h **** + 546:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + 547:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 548:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 549:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 550:Drivers/CMSIS/Include/cmsis_gcc.h **** + 551:Drivers/CMSIS/Include/cmsis_gcc.h **** + 552:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 553:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask + 554:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register. + 555:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 556:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 557:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) + 558:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 559:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); + 560:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 561:Drivers/CMSIS/Include/cmsis_gcc.h **** + 562:Drivers/CMSIS/Include/cmsis_gcc.h **** + 563:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 564:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 565:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask (non-secure) + 566:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Fault Mask register when in secure state. + 567:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 568:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 569:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) + 570:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 571:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); + 572:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 573:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 574:Drivers/CMSIS/Include/cmsis_gcc.h **** + 575:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 576:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 577:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + ARM GAS /tmp/ccMLQ7U7.s page 31 + + + 578:Drivers/CMSIS/Include/cmsis_gcc.h **** + 579:Drivers/CMSIS/Include/cmsis_gcc.h **** + 580:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 581:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + 582:Drivers/CMSIS/Include/cmsis_gcc.h **** + 583:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 584:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit + 585:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 586:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 587:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 588:Drivers/CMSIS/Include/cmsis_gcc.h **** + 589:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + 590:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 591:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 592:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) + 593:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 594:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 595:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 596:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 597:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 598:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 599:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 600:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + 601:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 602:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 603:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 604:Drivers/CMSIS/Include/cmsis_gcc.h **** + 605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) + 606:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 607:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit (non-secure) + 608:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 609:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + 610:Drivers/CMSIS/Include/cmsis_gcc.h **** + 611:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in + 612:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 613:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 614:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) + 615:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 617:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 618:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 619:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 620:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 621:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + 622:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 623:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 624:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 625:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 626:Drivers/CMSIS/Include/cmsis_gcc.h **** + 627:Drivers/CMSIS/Include/cmsis_gcc.h **** + 628:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 629:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer Limit + 630:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 631:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 632:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 633:Drivers/CMSIS/Include/cmsis_gcc.h **** + 634:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + ARM GAS /tmp/ccMLQ7U7.s page 32 + + + 635:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 636:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 637:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) + 638:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 639:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 640:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 641:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 642:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 643:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 644:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); + 645:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 646:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 647:Drivers/CMSIS/Include/cmsis_gcc.h **** + 648:Drivers/CMSIS/Include/cmsis_gcc.h **** + 649:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 651:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + 652:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 653:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 654:Drivers/CMSIS/Include/cmsis_gcc.h **** + 655:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s + 656:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 657:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 658:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) + 659:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 661:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 662:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 663:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 664:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); + 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 666:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 667:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 668:Drivers/CMSIS/Include/cmsis_gcc.h **** + 669:Drivers/CMSIS/Include/cmsis_gcc.h **** + 670:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 671:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit + 672:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 673:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 674:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 675:Drivers/CMSIS/Include/cmsis_gcc.h **** + 676:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + 677:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 678:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) + 680:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 681:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 682:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 683:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 684:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 685:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 686:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 687:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + 688:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 689:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 690:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 691:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccMLQ7U7.s page 33 + + + 692:Drivers/CMSIS/Include/cmsis_gcc.h **** + 693:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 694:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 695:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit (non-secure) + 696:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 697:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + 698:Drivers/CMSIS/Include/cmsis_gcc.h **** + 699:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec + 700:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 701:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 702:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) + 703:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 704:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 705:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 706:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 707:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 708:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 709:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + 710:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 711:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 712:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 713:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 714:Drivers/CMSIS/Include/cmsis_gcc.h **** + 715:Drivers/CMSIS/Include/cmsis_gcc.h **** + 716:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 717:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit + 718:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 719:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 720:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 721:Drivers/CMSIS/Include/cmsis_gcc.h **** + 722:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + 723:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + 724:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) + 726:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 728:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 729:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 730:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 731:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 732:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); + 733:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 734:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 735:Drivers/CMSIS/Include/cmsis_gcc.h **** + 736:Drivers/CMSIS/Include/cmsis_gcc.h **** + 737:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 738:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 739:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit (non-secure) + 740:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 741:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 742:Drivers/CMSIS/Include/cmsis_gcc.h **** + 743:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu + 744:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer value to set + 745:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) + 747:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + ARM GAS /tmp/ccMLQ7U7.s page 34 + + + 749:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 750:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 751:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 752:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); + 753:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 754:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 755:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 756:Drivers/CMSIS/Include/cmsis_gcc.h **** + 757:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 758:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + 759:Drivers/CMSIS/Include/cmsis_gcc.h **** + 760:Drivers/CMSIS/Include/cmsis_gcc.h **** + 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 762:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR + 763:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register. + 764:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value + 765:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 766:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) + 767:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 768:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 769:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 770:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) + 771:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + 772:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 773:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 774:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_arm_get_fpscr(); + 775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 776:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 777:Drivers/CMSIS/Include/cmsis_gcc.h **** + 778:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + 779:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 781:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 782:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0U); + 783:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 784:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 785:Drivers/CMSIS/Include/cmsis_gcc.h **** + 786:Drivers/CMSIS/Include/cmsis_gcc.h **** + 787:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 788:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR + 789:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register. + 790:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set + 791:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) + 793:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 795:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 796:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr) + 797:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + 798:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 799:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 800:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_arm_set_fpscr(fpscr); + 801:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 802:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); + 803:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 805:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)fpscr; + ARM GAS /tmp/ccMLQ7U7.s page 35 + + + 806:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 807:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 808:Drivers/CMSIS/Include/cmsis_gcc.h **** + 809:Drivers/CMSIS/Include/cmsis_gcc.h **** + 810:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */ + 811:Drivers/CMSIS/Include/cmsis_gcc.h **** + 812:Drivers/CMSIS/Include/cmsis_gcc.h **** + 813:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */ + 814:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + 815:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions + 816:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 817:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 818:Drivers/CMSIS/Include/cmsis_gcc.h **** + 819:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2. + 820:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l" + 821:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */ + 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__) + 823:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r) + 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r) + 825:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r) + 826:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 827:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r) + 828:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r) + 829:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r) + 830:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 831:Drivers/CMSIS/Include/cmsis_gcc.h **** + 832:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 833:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation + 834:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes. + 835:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 836:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP() __ASM volatile ("nop") + 837:Drivers/CMSIS/Include/cmsis_gcc.h **** + 838:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 839:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt + 840:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o + 841:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI() __ASM volatile ("wfi") + 843:Drivers/CMSIS/Include/cmsis_gcc.h **** + 844:Drivers/CMSIS/Include/cmsis_gcc.h **** + 845:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 846:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event + 847:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter + 848:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs. + 849:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE() __ASM volatile ("wfe") + 851:Drivers/CMSIS/Include/cmsis_gcc.h **** + 852:Drivers/CMSIS/Include/cmsis_gcc.h **** + 853:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 854:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event + 855:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + 856:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 857:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev") + 858:Drivers/CMSIS/Include/cmsis_gcc.h **** + 859:Drivers/CMSIS/Include/cmsis_gcc.h **** + 860:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 861:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier + 862:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor, + ARM GAS /tmp/ccMLQ7U7.s page 36 + + + 863:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory, + 864:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed. + 865:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 866:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void) + 867:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 868:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory"); + 869:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 870:Drivers/CMSIS/Include/cmsis_gcc.h **** + 871:Drivers/CMSIS/Include/cmsis_gcc.h **** + 872:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 873:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier + 874:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier. + 875:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete. + 876:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 877:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void) + 878:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 879:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory"); + 880:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 881:Drivers/CMSIS/Include/cmsis_gcc.h **** + 882:Drivers/CMSIS/Include/cmsis_gcc.h **** + 883:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 884:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Memory Barrier + 885:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Ensures the apparent order of the explicit memory operations before + 886:Drivers/CMSIS/Include/cmsis_gcc.h **** and after the instruction, without ensuring their completion. + 887:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 888:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void) + 889:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 890:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dmb 0xF":::"memory"); + 891:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 892:Drivers/CMSIS/Include/cmsis_gcc.h **** + 893:Drivers/CMSIS/Include/cmsis_gcc.h **** + 894:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 895:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (32 bit) + 896:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x785 + 897:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 898:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 899:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 900:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV(uint32_t value) + 901:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 902:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + 903:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_bswap32(value); + 904:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 905:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 906:Drivers/CMSIS/Include/cmsis_gcc.h **** + 907:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + 908:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 909:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 910:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 911:Drivers/CMSIS/Include/cmsis_gcc.h **** + 912:Drivers/CMSIS/Include/cmsis_gcc.h **** + 913:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 914:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) + 915:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes + 916:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 917:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 918:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 919:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) + ARM GAS /tmp/ccMLQ7U7.s page 37 + + + 920:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 921:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 922:Drivers/CMSIS/Include/cmsis_gcc.h **** + 923:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + 924:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 925:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 926:Drivers/CMSIS/Include/cmsis_gcc.h **** + 927:Drivers/CMSIS/Include/cmsis_gcc.h **** + 928:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 929:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) + 930:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For exam + 931:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 932:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 933:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 934:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE int16_t __REVSH(int16_t value) + 935:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 936:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + 937:Drivers/CMSIS/Include/cmsis_gcc.h **** return (int16_t)__builtin_bswap16(value); + 938:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 939:Drivers/CMSIS/Include/cmsis_gcc.h **** int16_t result; + 940:Drivers/CMSIS/Include/cmsis_gcc.h **** + 941:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + 942:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 943:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 944:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 945:Drivers/CMSIS/Include/cmsis_gcc.h **** + 946:Drivers/CMSIS/Include/cmsis_gcc.h **** + 947:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 948:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Rotate Right in unsigned value (32 bit) + 949:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v + 950:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op1 Value to rotate + 951:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op2 Number of Bits to rotate + 952:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Rotated value + 953:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 954:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) + 955:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 956:Drivers/CMSIS/Include/cmsis_gcc.h **** op2 %= 32U; + 957:Drivers/CMSIS/Include/cmsis_gcc.h **** if (op2 == 0U) + 958:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 959:Drivers/CMSIS/Include/cmsis_gcc.h **** return op1; + 960:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 961:Drivers/CMSIS/Include/cmsis_gcc.h **** return (op1 >> op2) | (op1 << (32U - op2)); + 962:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 963:Drivers/CMSIS/Include/cmsis_gcc.h **** + 964:Drivers/CMSIS/Include/cmsis_gcc.h **** + 965:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 966:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Breakpoint + 967:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Causes the processor to enter Debug state. + 968:Drivers/CMSIS/Include/cmsis_gcc.h **** Debug tools can use this to investigate system state when the instruction at a particula + 969:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value is ignored by the processor. + 970:Drivers/CMSIS/Include/cmsis_gcc.h **** If required, a debugger can use it to store additional information about the break + 971:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 972:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __BKPT(value) __ASM volatile ("bkpt "#value) + 973:Drivers/CMSIS/Include/cmsis_gcc.h **** + 974:Drivers/CMSIS/Include/cmsis_gcc.h **** + 975:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 976:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse bit order of value + ARM GAS /tmp/ccMLQ7U7.s page 38 + + + 977:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the bit order of the given value. + 978:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 979:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 980:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) + 982:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 984:Drivers/CMSIS/Include/cmsis_gcc.h **** + 985:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 986:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 987:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 669 .loc 2 988 4 + 670 0022 BA69 ldr r2, [r7, #24] + 671 .syntax unified + 672 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 673 0024 92FAA2F2 rbit r2, r2 + 674 @ 0 "" 2 + 675 .thumb + 676 .syntax unified + 677 0028 7A61 str r2, [r7, #20] + 989:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 990:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + 991:Drivers/CMSIS/Include/cmsis_gcc.h **** + 992:Drivers/CMSIS/Include/cmsis_gcc.h **** result = value; /* r will be reversed bits of v; first get LSB of v */ + 993:Drivers/CMSIS/Include/cmsis_gcc.h **** for (value >>= 1U; value != 0U; value >>= 1U) + 994:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 995:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= 1U; + 996:Drivers/CMSIS/Include/cmsis_gcc.h **** result |= value & 1U; + 997:Drivers/CMSIS/Include/cmsis_gcc.h **** s--; + 998:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 999:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= s; /* shift when v's highest bits are zero */ +1000:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif +1001:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 678 .loc 2 1001 10 + 679 002a 7A69 ldr r2, [r7, #20] + 680 .LBE9: + 681 .LBE8: + 682 .loc 1 470 54 discriminator 1 + 683 002c B2FA82F2 clz r2, r2 + 684 .loc 1 470 54 is_stmt 0 discriminator 2 + 685 0030 D2B2 uxtb r2, r2 + 686 .loc 1 470 11 is_stmt 1 discriminator 2 + 687 0032 D340 lsrs r3, r3, r2 + 688 0034 FB61 str r3, [r7, #28] + 689 0036 10E0 b .L39 + 690 .L37: + 471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** else + 473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Get value programmed in OB USER Data1 */ + 475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** value = READ_BIT(FLASH->OBR, FLASH_OBR_DATA1) >> FLASH_POSITION_OB_USERDATA1_BIT; + 691 .loc 1 475 13 + 692 0038 0C4B ldr r3, .L42+4 + 693 003a DB69 ldr r3, [r3, #28] + 694 003c 03F07F43 and r3, r3, #-16777216 + 695 0040 4FF07F42 mov r2, #-16777216 + ARM GAS /tmp/ccMLQ7U7.s page 39 + + + 696 0044 3A61 str r2, [r7, #16] + 697 .LBB10: + 698 .LBB11: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 699 .loc 2 988 4 + 700 0046 3A69 ldr r2, [r7, #16] + 701 .syntax unified + 702 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 703 0048 92FAA2F2 rbit r2, r2 + 704 @ 0 "" 2 + 705 .thumb + 706 .syntax unified + 707 004c FA60 str r2, [r7, #12] + 708 .loc 2 1001 10 + 709 004e FA68 ldr r2, [r7, #12] + 710 .LBE11: + 711 .LBE10: + 712 .loc 1 475 54 discriminator 1 + 713 0050 B2FA82F2 clz r2, r2 + 714 .loc 1 475 54 is_stmt 0 discriminator 2 + 715 0054 D2B2 uxtb r2, r2 + 716 .loc 1 475 11 is_stmt 1 discriminator 2 + 717 0056 D340 lsrs r3, r3, r2 + 718 0058 FB61 str r3, [r7, #28] + 719 .L39: + 476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return value; + 720 .loc 1 478 10 + 721 005a FB69 ldr r3, [r7, #28] + 479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 722 .loc 1 479 1 + 723 005c 1846 mov r0, r3 + 724 005e 2437 adds r7, r7, #36 + 725 .cfi_def_cfa_offset 4 + 726 0060 BD46 mov sp, r7 + 727 .cfi_def_cfa_register 13 + 728 @ sp needed + 729 0062 5DF8047B ldr r7, [sp], #4 + 730 .cfi_restore 7 + 731 .cfi_def_cfa_offset 0 + 732 0066 7047 bx lr + 733 .L43: + 734 .align 2 + 735 .L42: + 736 0068 04F8FF1F .word 536868868 + 737 006c 00200240 .word 1073881088 + 738 .cfi_endproc + 739 .LFE135: + 741 .section .text.FLASH_MassErase,"ax",%progbits + 742 .align 1 + 743 .syntax unified + 744 .thumb + 745 .thumb_func + 747 FLASH_MassErase: + 748 .LFB136: + 480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + ARM GAS /tmp/ccMLQ7U7.s page 40 + + + 481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + 482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @} + 483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + 486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @} + 487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** @addtogroup FLASHEx_Private_Functions + 490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @{ + 491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + 494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @brief Full erase of FLASH memory Bank + 495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * + 496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @retval None + 497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** static void FLASH_MassErase(void) + 499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 749 .loc 1 499 1 + 750 .cfi_startproc + 751 @ args = 0, pretend = 0, frame = 0 + 752 @ frame_needed = 1, uses_anonymous_args = 0 + 753 @ link register save eliminated. + 754 0000 80B4 push {r7} + 755 .cfi_def_cfa_offset 4 + 756 .cfi_offset 7, -4 + 757 0002 00AF add r7, sp, #0 + 758 .cfi_def_cfa_register 7 + 500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Clean the error context */ + 501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + 759 .loc 1 501 20 + 760 0004 094B ldr r3, .L45 + 761 0006 0022 movs r2, #0 + 762 0008 DA61 str r2, [r3, #28] + 502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Only bank1 will be erased*/ + 504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** SET_BIT(FLASH->CR, FLASH_CR_MER); + 763 .loc 1 504 5 + 764 000a 094B ldr r3, .L45+4 + 765 000c 1B69 ldr r3, [r3, #16] + 766 000e 084A ldr r2, .L45+4 + 767 0010 43F00403 orr r3, r3, #4 + 768 0014 1361 str r3, [r2, #16] + 505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** SET_BIT(FLASH->CR, FLASH_CR_STRT); + 769 .loc 1 505 5 + 770 0016 064B ldr r3, .L45+4 + 771 0018 1B69 ldr r3, [r3, #16] + 772 001a 054A ldr r2, .L45+4 + 773 001c 43F04003 orr r3, r3, #64 + 774 0020 1361 str r3, [r2, #16] + 506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 775 .loc 1 506 1 + 776 0022 00BF nop + 777 0024 BD46 mov sp, r7 + 778 .cfi_def_cfa_register 13 + 779 @ sp needed + ARM GAS /tmp/ccMLQ7U7.s page 41 + + + 780 0026 5DF8047B ldr r7, [sp], #4 + 781 .cfi_restore 7 + 782 .cfi_def_cfa_offset 0 + 783 002a 7047 bx lr + 784 .L46: + 785 .align 2 + 786 .L45: + 787 002c 00000000 .word pFlash + 788 0030 00200240 .word 1073881088 + 789 .cfi_endproc + 790 .LFE136: + 792 .section .text.FLASH_OB_EnableWRP,"ax",%progbits + 793 .align 1 + 794 .syntax unified + 795 .thumb + 796 .thumb_func + 798 FLASH_OB_EnableWRP: + 799 .LFB137: + 507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + 509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @brief Enable the write protection of the desired pages + 510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @note An option byte erase is done automatically in this function. + 511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @note When the memory read protection level is selected (RDP level = 1), + 512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * it is not possible to program or erase the flash page i if + 513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + 514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * + 515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @param WriteProtectPage specifies the page(s) to be write protected. + 516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * The value of this parameter depend on device used within the same series + 517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @retval HAL status + 518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WriteProtectPage) + 520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 800 .loc 1 520 1 + 801 .cfi_startproc + 802 @ args = 0, pretend = 0, frame = 24 + 803 @ frame_needed = 1, uses_anonymous_args = 0 + 804 0000 80B5 push {r7, lr} + 805 .cfi_def_cfa_offset 8 + 806 .cfi_offset 7, -8 + 807 .cfi_offset 14, -4 + 808 0002 86B0 sub sp, sp, #24 + 809 .cfi_def_cfa_offset 32 + 810 0004 00AF add r7, sp, #0 + 811 .cfi_def_cfa_register 7 + 812 0006 7860 str r0, [r7, #4] + 521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 813 .loc 1 521 21 + 814 0008 0023 movs r3, #0 + 815 000a FB75 strb r3, [r7, #23] + 522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** uint16_t WRP0_Data = 0xFFFFU; + 816 .loc 1 522 12 + 817 000c 4FF6FF73 movw r3, #65535 + 818 0010 BB82 strh r3, [r7, #20] @ movhi + 523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(OB_WRP1_WRP1) + 524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** uint16_t WRP1_Data = 0xFFFFU; + 819 .loc 1 524 12 + 820 0012 4FF6FF73 movw r3, #65535 + ARM GAS /tmp/ccMLQ7U7.s page 42 + + + 821 0016 7B82 strh r3, [r7, #18] @ movhi + 525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP1_WRP1 */ + 526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(OB_WRP2_WRP2) + 527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** uint16_t WRP2_Data = 0xFFFFU; + 822 .loc 1 527 12 + 823 0018 4FF6FF73 movw r3, #65535 + 824 001c 3B82 strh r3, [r7, #16] @ movhi + 528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP2_WRP2 */ + 529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(OB_WRP3_WRP3) + 530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** uint16_t WRP3_Data = 0xFFFFU; + 825 .loc 1 530 12 + 826 001e 4FF6FF73 movw r3, #65535 + 827 0022 FB81 strh r3, [r7, #14] @ movhi + 531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP3_WRP3 */ + 532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Check the parameters */ + 534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** assert_param(IS_OB_WRP(WriteProtectPage)); + 535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Get current write protected pages and the new pages to be protected ******/ + 537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** WriteProtectPage = (uint32_t)(~((~FLASH_OB_GetWRP()) | WriteProtectPage)); + 828 .loc 1 537 37 + 829 0024 FFF7FEFF bl FLASH_OB_GetWRP + 830 0028 0246 mov r2, r0 + 831 .loc 1 537 33 discriminator 1 + 832 002a 7B68 ldr r3, [r7, #4] + 833 002c DB43 mvns r3, r3 + 834 .loc 1 537 20 discriminator 1 + 835 002e 1340 ands r3, r3, r2 + 836 0030 7B60 str r3, [r7, #4] + 538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(OB_WRP_PAGES0TO15MASK) + 540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK); + 837 .loc 1 540 15 + 838 0032 7B68 ldr r3, [r7, #4] + 839 0034 9BB2 uxth r3, r3 + 840 .loc 1 540 13 + 841 0036 DBB2 uxtb r3, r3 + 842 0038 BB82 strh r3, [r7, #20] @ movhi + 541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP_PAGES0TO31MASK */ + 542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(OB_WRP_PAGES16TO31MASK) + 544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U); + 843 .loc 1 544 70 + 844 003a 7B68 ldr r3, [r7, #4] + 845 003c 1B0A lsrs r3, r3, #8 + 846 .loc 1 544 15 + 847 003e 9BB2 uxth r3, r3 + 848 .loc 1 544 13 + 849 0040 DBB2 uxtb r3, r3 + 850 0042 7B82 strh r3, [r7, #18] @ movhi + 545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP_PAGES32TO63MASK */ + 546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(OB_WRP_PAGES32TO47MASK) + 548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U); + 851 .loc 1 548 70 + 852 0044 7B68 ldr r3, [r7, #4] + 853 0046 1B0C lsrs r3, r3, #16 + ARM GAS /tmp/ccMLQ7U7.s page 43 + + + 854 .loc 1 548 15 + 855 0048 9BB2 uxth r3, r3 + 856 .loc 1 548 13 + 857 004a DBB2 uxtb r3, r3 + 858 004c 3B82 strh r3, [r7, #16] @ movhi + 549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP_PAGES32TO47MASK */ + 550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(OB_WRP_PAGES48TO127MASK) + 552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U); + 859 .loc 1 552 71 + 860 004e 7B68 ldr r3, [r7, #4] + 861 0050 1B0E lsrs r3, r3, #24 + 862 .loc 1 552 13 + 863 0052 FB81 strh r3, [r7, #14] @ movhi + 553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #elif defined(OB_WRP_PAGES48TO255MASK) + 554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U); + 555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP_PAGES48TO63MASK */ + 556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 864 .loc 1 558 12 + 865 0054 4CF25030 movw r0, #50000 + 866 0058 FFF7FEFF bl FLASH_WaitForLastOperation + 867 005c 0346 mov r3, r0 + 868 005e FB75 strb r3, [r7, #23] + 559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if(status == HAL_OK) + 869 .loc 1 560 5 + 870 0060 FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 871 0062 002B cmp r3, #0 + 872 0064 62D1 bne .L48 + 561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Clean the error context */ + 563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + 873 .loc 1 563 22 + 874 0066 344B ldr r3, .L54 + 875 0068 0022 movs r2, #0 + 876 006a DA61 str r2, [r3, #28] + 564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* To be able to write again option byte, need to perform a option byte erase */ + 566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = HAL_FLASHEx_OBErase(); + 877 .loc 1 566 14 + 878 006c FFF7FEFF bl HAL_FLASHEx_OBErase + 879 0070 0346 mov r3, r0 + 880 0072 FB75 strb r3, [r7, #23] + 567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if (status == HAL_OK) + 881 .loc 1 567 8 + 882 0074 FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 883 0076 002B cmp r3, #0 + 884 0078 58D1 bne .L48 + 568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Enable write protection */ + 570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + 885 .loc 1 570 7 + 886 007a 304B ldr r3, .L54+4 + 887 007c 1B69 ldr r3, [r3, #16] + 888 007e 2F4A ldr r2, .L54+4 + ARM GAS /tmp/ccMLQ7U7.s page 44 + + + 889 0080 43F01003 orr r3, r3, #16 + 890 0084 1361 str r3, [r2, #16] + 571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(OB_WRP0_WRP0) + 573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if(WRP0_Data != 0xFFU) + 891 .loc 1 573 9 + 892 0086 BB8A ldrh r3, [r7, #20] + 893 0088 FF2B cmp r3, #255 + 894 008a 0DD0 beq .L49 + 574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** OB->WRP0 &= WRP0_Data; + 895 .loc 1 575 11 + 896 008c 2C4B ldr r3, .L54+8 + 897 008e 1B89 ldrh r3, [r3, #8] @ movhi + 898 0090 9AB2 uxth r2, r3 + 899 0092 2B49 ldr r1, .L54+8 + 900 .loc 1 575 18 + 901 0094 BB8A ldrh r3, [r7, #20] @ movhi + 902 0096 1340 ands r3, r3, r2 + 903 0098 9BB2 uxth r3, r3 + 904 009a 0B81 strh r3, [r1, #8] @ movhi + 576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 905 .loc 1 578 18 + 906 009c 4CF25030 movw r0, #50000 + 907 00a0 FFF7FEFF bl FLASH_WaitForLastOperation + 908 00a4 0346 mov r3, r0 + 909 00a6 FB75 strb r3, [r7, #23] + 910 .L49: + 579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP0_WRP0 */ + 581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(OB_WRP1_WRP1) + 583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if((status == HAL_OK) && (WRP1_Data != 0xFFU)) + 911 .loc 1 583 9 + 912 00a8 FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 913 00aa 002B cmp r3, #0 + 914 00ac 10D1 bne .L50 + 915 .loc 1 583 29 discriminator 1 + 916 00ae 7B8A ldrh r3, [r7, #18] + 917 00b0 FF2B cmp r3, #255 + 918 00b2 0DD0 beq .L50 + 584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** OB->WRP1 &= WRP1_Data; + 919 .loc 1 585 11 + 920 00b4 224B ldr r3, .L54+8 + 921 00b6 5B89 ldrh r3, [r3, #10] @ movhi + 922 00b8 9AB2 uxth r2, r3 + 923 00ba 2149 ldr r1, .L54+8 + 924 .loc 1 585 18 + 925 00bc 7B8A ldrh r3, [r7, #18] @ movhi + 926 00be 1340 ands r3, r3, r2 + 927 00c0 9BB2 uxth r3, r3 + 928 00c2 4B81 strh r3, [r1, #10] @ movhi + 586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + ARM GAS /tmp/ccMLQ7U7.s page 45 + + + 588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 929 .loc 1 588 18 + 930 00c4 4CF25030 movw r0, #50000 + 931 00c8 FFF7FEFF bl FLASH_WaitForLastOperation + 932 00cc 0346 mov r3, r0 + 933 00ce FB75 strb r3, [r7, #23] + 934 .L50: + 589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP1_WRP1 */ + 591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(OB_WRP2_WRP2) + 593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if((status == HAL_OK) && (WRP2_Data != 0xFFU)) + 935 .loc 1 593 9 + 936 00d0 FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 937 00d2 002B cmp r3, #0 + 938 00d4 10D1 bne .L51 + 939 .loc 1 593 29 discriminator 1 + 940 00d6 3B8A ldrh r3, [r7, #16] + 941 00d8 FF2B cmp r3, #255 + 942 00da 0DD0 beq .L51 + 594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** OB->WRP2 &= WRP2_Data; + 943 .loc 1 595 11 + 944 00dc 184B ldr r3, .L54+8 + 945 00de 9B89 ldrh r3, [r3, #12] @ movhi + 946 00e0 9AB2 uxth r2, r3 + 947 00e2 1749 ldr r1, .L54+8 + 948 .loc 1 595 18 + 949 00e4 3B8A ldrh r3, [r7, #16] @ movhi + 950 00e6 1340 ands r3, r3, r2 + 951 00e8 9BB2 uxth r3, r3 + 952 00ea 8B81 strh r3, [r1, #12] @ movhi + 596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 953 .loc 1 598 18 + 954 00ec 4CF25030 movw r0, #50000 + 955 00f0 FFF7FEFF bl FLASH_WaitForLastOperation + 956 00f4 0346 mov r3, r0 + 957 00f6 FB75 strb r3, [r7, #23] + 958 .L51: + 599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP2_WRP2 */ + 601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 602:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(OB_WRP3_WRP3) + 603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if((status == HAL_OK) && (WRP3_Data != 0xFFU)) + 959 .loc 1 603 9 + 960 00f8 FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 961 00fa 002B cmp r3, #0 + 962 00fc 10D1 bne .L52 + 963 .loc 1 603 29 discriminator 1 + 964 00fe FB89 ldrh r3, [r7, #14] + 965 0100 FF2B cmp r3, #255 + 966 0102 0DD0 beq .L52 + 604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** OB->WRP3 &= WRP3_Data; + 967 .loc 1 605 11 + ARM GAS /tmp/ccMLQ7U7.s page 46 + + + 968 0104 0E4B ldr r3, .L54+8 + 969 0106 DB89 ldrh r3, [r3, #14] @ movhi + 970 0108 9AB2 uxth r2, r3 + 971 010a 0D49 ldr r1, .L54+8 + 972 .loc 1 605 18 + 973 010c FB89 ldrh r3, [r7, #14] @ movhi + 974 010e 1340 ands r3, r3, r2 + 975 0110 9BB2 uxth r3, r3 + 976 0112 CB81 strh r3, [r1, #14] @ movhi + 606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 977 .loc 1 608 18 + 978 0114 4CF25030 movw r0, #50000 + 979 0118 FFF7FEFF bl FLASH_WaitForLastOperation + 980 011c 0346 mov r3, r0 + 981 011e FB75 strb r3, [r7, #23] + 982 .L52: + 609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP3_WRP3 */ + 611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 612:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* if the program operation is completed, disable the OPTPG Bit */ + 613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + 983 .loc 1 613 7 + 984 0120 064B ldr r3, .L54+4 + 985 0122 1B69 ldr r3, [r3, #16] + 986 0124 054A ldr r2, .L54+4 + 987 0126 23F01003 bic r3, r3, #16 + 988 012a 1361 str r3, [r2, #16] + 989 .L48: + 614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return status; + 990 .loc 1 617 10 + 991 012c FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 992 .loc 1 618 1 + 993 012e 1846 mov r0, r3 + 994 0130 1837 adds r7, r7, #24 + 995 .cfi_def_cfa_offset 8 + 996 0132 BD46 mov sp, r7 + 997 .cfi_def_cfa_register 13 + 998 @ sp needed + 999 0134 80BD pop {r7, pc} + 1000 .L55: + 1001 0136 00BF .align 2 + 1002 .L54: + 1003 0138 00000000 .word pFlash + 1004 013c 00200240 .word 1073881088 + 1005 0140 00F8FF1F .word 536868864 + 1006 .cfi_endproc + 1007 .LFE137: + 1009 .section .text.FLASH_OB_DisableWRP,"ax",%progbits + 1010 .align 1 + 1011 .syntax unified + 1012 .thumb + ARM GAS /tmp/ccMLQ7U7.s page 47 + + + 1013 .thumb_func + 1015 FLASH_OB_DisableWRP: + 1016 .LFB138: + 619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + 621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @brief Disable the write protection of the desired pages + 622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @note An option byte erase is done automatically in this function. + 623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @note When the memory read protection level is selected (RDP level = 1), + 624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * it is not possible to program or erase the flash page i if + 625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + 626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * + 627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @param WriteProtectPage specifies the page(s) to be write unprotected. + 628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * The value of this parameter depend on device used within the same series + 629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @retval HAL status + 630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WriteProtectPage) + 632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 1017 .loc 1 632 1 + 1018 .cfi_startproc + 1019 @ args = 0, pretend = 0, frame = 24 + 1020 @ frame_needed = 1, uses_anonymous_args = 0 + 1021 0000 80B5 push {r7, lr} + 1022 .cfi_def_cfa_offset 8 + 1023 .cfi_offset 7, -8 + 1024 .cfi_offset 14, -4 + 1025 0002 86B0 sub sp, sp, #24 + 1026 .cfi_def_cfa_offset 32 + 1027 0004 00AF add r7, sp, #0 + 1028 .cfi_def_cfa_register 7 + 1029 0006 7860 str r0, [r7, #4] + 633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 1030 .loc 1 633 21 + 1031 0008 0023 movs r3, #0 + 1032 000a FB75 strb r3, [r7, #23] + 634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** uint16_t WRP0_Data = 0xFFFFU; + 1033 .loc 1 634 12 + 1034 000c 4FF6FF73 movw r3, #65535 + 1035 0010 BB82 strh r3, [r7, #20] @ movhi + 635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(OB_WRP1_WRP1) + 636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** uint16_t WRP1_Data = 0xFFFFU; + 1036 .loc 1 636 12 + 1037 0012 4FF6FF73 movw r3, #65535 + 1038 0016 7B82 strh r3, [r7, #18] @ movhi + 637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP1_WRP1 */ + 638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(OB_WRP2_WRP2) + 639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** uint16_t WRP2_Data = 0xFFFFU; + 1039 .loc 1 639 12 + 1040 0018 4FF6FF73 movw r3, #65535 + 1041 001c 3B82 strh r3, [r7, #16] @ movhi + 640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP2_WRP2 */ + 641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(OB_WRP3_WRP3) + 642:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** uint16_t WRP3_Data = 0xFFFFU; + 1042 .loc 1 642 12 + 1043 001e 4FF6FF73 movw r3, #65535 + 1044 0022 FB81 strh r3, [r7, #14] @ movhi + 643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP3_WRP3 */ + 644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + ARM GAS /tmp/ccMLQ7U7.s page 48 + + + 645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Check the parameters */ + 646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** assert_param(IS_OB_WRP(WriteProtectPage)); + 647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Get current write protected pages and the new pages to be unprotected ******/ + 649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** WriteProtectPage = (FLASH_OB_GetWRP() | WriteProtectPage); + 1045 .loc 1 649 23 + 1046 0024 FFF7FEFF bl FLASH_OB_GetWRP + 1047 0028 0246 mov r2, r0 + 1048 .loc 1 649 20 discriminator 1 + 1049 002a 7B68 ldr r3, [r7, #4] + 1050 002c 1343 orrs r3, r3, r2 + 1051 002e 7B60 str r3, [r7, #4] + 650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(OB_WRP_PAGES0TO15MASK) + 652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** WRP0_Data = (uint16_t)(WriteProtectPage & OB_WRP_PAGES0TO15MASK); + 1052 .loc 1 652 15 + 1053 0030 7B68 ldr r3, [r7, #4] + 1054 0032 9BB2 uxth r3, r3 + 1055 .loc 1 652 13 + 1056 0034 DBB2 uxtb r3, r3 + 1057 0036 BB82 strh r3, [r7, #20] @ movhi + 653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP_PAGES0TO31MASK */ + 654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 655:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(OB_WRP_PAGES16TO31MASK) + 656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** WRP1_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES16TO31MASK) >> 8U); + 1058 .loc 1 656 70 + 1059 0038 7B68 ldr r3, [r7, #4] + 1060 003a 1B0A lsrs r3, r3, #8 + 1061 .loc 1 656 15 + 1062 003c 9BB2 uxth r3, r3 + 1063 .loc 1 656 13 + 1064 003e DBB2 uxtb r3, r3 + 1065 0040 7B82 strh r3, [r7, #18] @ movhi + 657:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP_PAGES32TO63MASK */ + 658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 659:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(OB_WRP_PAGES32TO47MASK) + 660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** WRP2_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES32TO47MASK) >> 16U); + 1066 .loc 1 660 70 + 1067 0042 7B68 ldr r3, [r7, #4] + 1068 0044 1B0C lsrs r3, r3, #16 + 1069 .loc 1 660 15 + 1070 0046 9BB2 uxth r3, r3 + 1071 .loc 1 660 13 + 1072 0048 DBB2 uxtb r3, r3 + 1073 004a 3B82 strh r3, [r7, #16] @ movhi + 661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP_PAGES32TO47MASK */ + 662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(OB_WRP_PAGES48TO127MASK) + 664:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO127MASK) >> 24U); + 1074 .loc 1 664 71 + 1075 004c 7B68 ldr r3, [r7, #4] + 1076 004e 1B0E lsrs r3, r3, #24 + 1077 .loc 1 664 13 + 1078 0050 FB81 strh r3, [r7, #14] @ movhi + 665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #elif defined(OB_WRP_PAGES48TO255MASK) + 666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** WRP3_Data = (uint16_t)((WriteProtectPage & OB_WRP_PAGES48TO255MASK) >> 24U); + 667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP_PAGES48TO63MASK */ + ARM GAS /tmp/ccMLQ7U7.s page 49 + + + 668:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 1079 .loc 1 671 12 + 1080 0052 4CF25030 movw r0, #50000 + 1081 0056 FFF7FEFF bl FLASH_WaitForLastOperation + 1082 005a 0346 mov r3, r0 + 1083 005c FB75 strb r3, [r7, #23] + 672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if(status == HAL_OK) + 1084 .loc 1 673 5 + 1085 005e FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 1086 0060 002B cmp r3, #0 + 1087 0062 62D1 bne .L57 + 674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Clean the error context */ + 676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + 1088 .loc 1 676 22 + 1089 0064 334B ldr r3, .L63 + 1090 0066 0022 movs r2, #0 + 1091 0068 DA61 str r2, [r3, #28] + 677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* To be able to write again option byte, need to perform a option byte erase */ + 679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = HAL_FLASHEx_OBErase(); + 1092 .loc 1 679 14 + 1093 006a FFF7FEFF bl HAL_FLASHEx_OBErase + 1094 006e 0346 mov r3, r0 + 1095 0070 FB75 strb r3, [r7, #23] + 680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if (status == HAL_OK) + 1096 .loc 1 680 8 + 1097 0072 FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 1098 0074 002B cmp r3, #0 + 1099 0076 58D1 bne .L57 + 681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + 1100 .loc 1 682 7 + 1101 0078 2F4B ldr r3, .L63+4 + 1102 007a 1B69 ldr r3, [r3, #16] + 1103 007c 2E4A ldr r2, .L63+4 + 1104 007e 43F01003 orr r3, r3, #16 + 1105 0082 1361 str r3, [r2, #16] + 683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(OB_WRP0_WRP0) + 685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if(WRP0_Data != 0xFFU) + 1106 .loc 1 685 9 + 1107 0084 BB8A ldrh r3, [r7, #20] + 1108 0086 FF2B cmp r3, #255 + 1109 0088 0DD0 beq .L58 + 686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** OB->WRP0 |= WRP0_Data; + 1110 .loc 1 687 11 + 1111 008a 2C4B ldr r3, .L63+8 + 1112 008c 1B89 ldrh r3, [r3, #8] @ movhi + 1113 008e 9AB2 uxth r2, r3 + 1114 0090 2A49 ldr r1, .L63+8 + 1115 .loc 1 687 18 + ARM GAS /tmp/ccMLQ7U7.s page 50 + + + 1116 0092 BB8A ldrh r3, [r7, #20] @ movhi + 1117 0094 1343 orrs r3, r3, r2 + 1118 0096 9BB2 uxth r3, r3 + 1119 0098 0B81 strh r3, [r1, #8] @ movhi + 688:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 1120 .loc 1 690 18 + 1121 009a 4CF25030 movw r0, #50000 + 1122 009e FFF7FEFF bl FLASH_WaitForLastOperation + 1123 00a2 0346 mov r3, r0 + 1124 00a4 FB75 strb r3, [r7, #23] + 1125 .L58: + 691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP0_WRP0 */ + 693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 694:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(OB_WRP1_WRP1) + 695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if((status == HAL_OK) && (WRP1_Data != 0xFFU)) + 1126 .loc 1 695 9 + 1127 00a6 FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 1128 00a8 002B cmp r3, #0 + 1129 00aa 10D1 bne .L59 + 1130 .loc 1 695 29 discriminator 1 + 1131 00ac 7B8A ldrh r3, [r7, #18] + 1132 00ae FF2B cmp r3, #255 + 1133 00b0 0DD0 beq .L59 + 696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** OB->WRP1 |= WRP1_Data; + 1134 .loc 1 697 11 + 1135 00b2 224B ldr r3, .L63+8 + 1136 00b4 5B89 ldrh r3, [r3, #10] @ movhi + 1137 00b6 9AB2 uxth r2, r3 + 1138 00b8 2049 ldr r1, .L63+8 + 1139 .loc 1 697 18 + 1140 00ba 7B8A ldrh r3, [r7, #18] @ movhi + 1141 00bc 1343 orrs r3, r3, r2 + 1142 00be 9BB2 uxth r3, r3 + 1143 00c0 4B81 strh r3, [r1, #10] @ movhi + 698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 700:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 1144 .loc 1 700 18 + 1145 00c2 4CF25030 movw r0, #50000 + 1146 00c6 FFF7FEFF bl FLASH_WaitForLastOperation + 1147 00ca 0346 mov r3, r0 + 1148 00cc FB75 strb r3, [r7, #23] + 1149 .L59: + 701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP1_WRP1 */ + 703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 704:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(OB_WRP2_WRP2) + 705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if((status == HAL_OK) && (WRP2_Data != 0xFFU)) + 1150 .loc 1 705 9 + 1151 00ce FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 1152 00d0 002B cmp r3, #0 + 1153 00d2 10D1 bne .L60 + 1154 .loc 1 705 29 discriminator 1 + ARM GAS /tmp/ccMLQ7U7.s page 51 + + + 1155 00d4 3B8A ldrh r3, [r7, #16] + 1156 00d6 FF2B cmp r3, #255 + 1157 00d8 0DD0 beq .L60 + 706:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 707:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** OB->WRP2 |= WRP2_Data; + 1158 .loc 1 707 11 + 1159 00da 184B ldr r3, .L63+8 + 1160 00dc 9B89 ldrh r3, [r3, #12] @ movhi + 1161 00de 9AB2 uxth r2, r3 + 1162 00e0 1649 ldr r1, .L63+8 + 1163 .loc 1 707 18 + 1164 00e2 3B8A ldrh r3, [r7, #16] @ movhi + 1165 00e4 1343 orrs r3, r3, r2 + 1166 00e6 9BB2 uxth r3, r3 + 1167 00e8 8B81 strh r3, [r1, #12] @ movhi + 708:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 1168 .loc 1 710 18 + 1169 00ea 4CF25030 movw r0, #50000 + 1170 00ee FFF7FEFF bl FLASH_WaitForLastOperation + 1171 00f2 0346 mov r3, r0 + 1172 00f4 FB75 strb r3, [r7, #23] + 1173 .L60: + 711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP2_WRP2 */ + 713:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(OB_WRP3_WRP3) + 715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if((status == HAL_OK) && (WRP3_Data != 0xFFU)) + 1174 .loc 1 715 9 + 1175 00f6 FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 1176 00f8 002B cmp r3, #0 + 1177 00fa 10D1 bne .L61 + 1178 .loc 1 715 29 discriminator 1 + 1179 00fc FB89 ldrh r3, [r7, #14] + 1180 00fe FF2B cmp r3, #255 + 1181 0100 0DD0 beq .L61 + 716:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** OB->WRP3 |= WRP3_Data; + 1182 .loc 1 717 11 + 1183 0102 0E4B ldr r3, .L63+8 + 1184 0104 DB89 ldrh r3, [r3, #14] @ movhi + 1185 0106 9AB2 uxth r2, r3 + 1186 0108 0C49 ldr r1, .L63+8 + 1187 .loc 1 717 18 + 1188 010a FB89 ldrh r3, [r7, #14] @ movhi + 1189 010c 1343 orrs r3, r3, r2 + 1190 010e 9BB2 uxth r3, r3 + 1191 0110 CB81 strh r3, [r1, #14] @ movhi + 718:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 720:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 1192 .loc 1 720 18 + 1193 0112 4CF25030 movw r0, #50000 + 1194 0116 FFF7FEFF bl FLASH_WaitForLastOperation + 1195 011a 0346 mov r3, r0 + 1196 011c FB75 strb r3, [r7, #23] + ARM GAS /tmp/ccMLQ7U7.s page 52 + + + 1197 .L61: + 721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 722:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* OB_WRP3_WRP3 */ + 723:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 724:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* if the program operation is completed, disable the OPTPG Bit */ + 725:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + 1198 .loc 1 725 7 + 1199 011e 064B ldr r3, .L63+4 + 1200 0120 1B69 ldr r3, [r3, #16] + 1201 0122 054A ldr r2, .L63+4 + 1202 0124 23F01003 bic r3, r3, #16 + 1203 0128 1361 str r3, [r2, #16] + 1204 .L57: + 726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 727:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return status; + 1205 .loc 1 728 10 + 1206 012a FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 1207 .loc 1 729 1 + 1208 012c 1846 mov r0, r3 + 1209 012e 1837 adds r7, r7, #24 + 1210 .cfi_def_cfa_offset 8 + 1211 0130 BD46 mov sp, r7 + 1212 .cfi_def_cfa_register 13 + 1213 @ sp needed + 1214 0132 80BD pop {r7, pc} + 1215 .L64: + 1216 .align 2 + 1217 .L63: + 1218 0134 00000000 .word pFlash + 1219 0138 00200240 .word 1073881088 + 1220 013c 00F8FF1F .word 536868864 + 1221 .cfi_endproc + 1222 .LFE138: + 1224 .section .text.FLASH_OB_RDP_LevelConfig,"ax",%progbits + 1225 .align 1 + 1226 .syntax unified + 1227 .thumb + 1228 .thumb_func + 1230 FLASH_OB_RDP_LevelConfig: + 1231 .LFB139: + 730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + 732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @brief Set the read protection level. + 733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @param ReadProtectLevel specifies the read protection level. + 734:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * This parameter can be one of the following values: + 735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @arg @ref OB_RDP_LEVEL_0 No protection + 736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory + 737:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @arg @ref OB_RDP_LEVEL_2 Full chip protection + 738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @note Warning: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0 + 739:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @retval HAL status + 740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t ReadProtectLevel) + 742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 1232 .loc 1 742 1 + 1233 .cfi_startproc + ARM GAS /tmp/ccMLQ7U7.s page 53 + + + 1234 @ args = 0, pretend = 0, frame = 16 + 1235 @ frame_needed = 1, uses_anonymous_args = 0 + 1236 0000 80B5 push {r7, lr} + 1237 .cfi_def_cfa_offset 8 + 1238 .cfi_offset 7, -8 + 1239 .cfi_offset 14, -4 + 1240 0002 84B0 sub sp, sp, #16 + 1241 .cfi_def_cfa_offset 24 + 1242 0004 00AF add r7, sp, #0 + 1243 .cfi_def_cfa_register 7 + 1244 0006 0346 mov r3, r0 + 1245 0008 FB71 strb r3, [r7, #7] + 743:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 1246 .loc 1 743 21 + 1247 000a 0023 movs r3, #0 + 1248 000c FB73 strb r3, [r7, #15] + 744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 745:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Check the parameters */ + 746:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** assert_param(IS_OB_RDP_LEVEL(ReadProtectLevel)); + 747:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 748:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 1249 .loc 1 749 12 + 1250 000e 4CF25030 movw r0, #50000 + 1251 0012 FFF7FEFF bl FLASH_WaitForLastOperation + 1252 0016 0346 mov r3, r0 + 1253 0018 FB73 strb r3, [r7, #15] + 750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if(status == HAL_OK) + 1254 .loc 1 751 5 + 1255 001a FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 1256 001c 002B cmp r3, #0 + 1257 001e 33D1 bne .L66 + 752:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Clean the error context */ + 754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + 1258 .loc 1 754 22 + 1259 0020 1C4B ldr r3, .L68 + 1260 0022 0022 movs r2, #0 + 1261 0024 DA61 str r2, [r3, #28] + 755:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* If the previous operation is completed, proceed to erase the option bytes */ + 757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** SET_BIT(FLASH->CR, FLASH_CR_OPTER); + 1262 .loc 1 757 5 + 1263 0026 1C4B ldr r3, .L68+4 + 1264 0028 1B69 ldr r3, [r3, #16] + 1265 002a 1B4A ldr r2, .L68+4 + 1266 002c 43F02003 orr r3, r3, #32 + 1267 0030 1361 str r3, [r2, #16] + 758:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** SET_BIT(FLASH->CR, FLASH_CR_STRT); + 1268 .loc 1 758 5 + 1269 0032 194B ldr r3, .L68+4 + 1270 0034 1B69 ldr r3, [r3, #16] + 1271 0036 184A ldr r2, .L68+4 + 1272 0038 43F04003 orr r3, r3, #64 + 1273 003c 1361 str r3, [r2, #16] + 759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + ARM GAS /tmp/ccMLQ7U7.s page 54 + + + 760:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 761:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 1274 .loc 1 761 14 + 1275 003e 4CF25030 movw r0, #50000 + 1276 0042 FFF7FEFF bl FLASH_WaitForLastOperation + 1277 0046 0346 mov r3, r0 + 1278 0048 FB73 strb r3, [r7, #15] + 762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* If the erase operation is completed, disable the OPTER Bit */ + 764:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** CLEAR_BIT(FLASH->CR, FLASH_CR_OPTER); + 1279 .loc 1 764 5 + 1280 004a 134B ldr r3, .L68+4 + 1281 004c 1B69 ldr r3, [r3, #16] + 1282 004e 124A ldr r2, .L68+4 + 1283 0050 23F02003 bic r3, r3, #32 + 1284 0054 1361 str r3, [r2, #16] + 765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if(status == HAL_OK) + 1285 .loc 1 766 7 + 1286 0056 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 1287 0058 002B cmp r3, #0 + 1288 005a 15D1 bne .L66 + 767:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Enable the Option Bytes Programming operation */ + 769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + 1289 .loc 1 769 7 + 1290 005c 0E4B ldr r3, .L68+4 + 1291 005e 1B69 ldr r3, [r3, #16] + 1292 0060 0D4A ldr r2, .L68+4 + 1293 0062 43F01003 orr r3, r3, #16 + 1294 0066 1361 str r3, [r2, #16] + 770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** WRITE_REG(OB->RDP, ReadProtectLevel); + 1295 .loc 1 771 7 + 1296 0068 0C4B ldr r3, .L68+8 + 1297 006a FA79 ldrb r2, [r7, #7] @ zero_extendqisi2 + 1298 006c 92B2 uxth r2, r2 + 1299 006e 1A80 strh r2, [r3] @ movhi + 772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 1300 .loc 1 774 16 + 1301 0070 4CF25030 movw r0, #50000 + 1302 0074 FFF7FEFF bl FLASH_WaitForLastOperation + 1303 0078 0346 mov r3, r0 + 1304 007a FB73 strb r3, [r7, #15] + 775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* if the program operation is completed, disable the OPTPG Bit */ + 777:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + 1305 .loc 1 777 7 + 1306 007c 064B ldr r3, .L68+4 + 1307 007e 1B69 ldr r3, [r3, #16] + 1308 0080 054A ldr r2, .L68+4 + 1309 0082 23F01003 bic r3, r3, #16 + 1310 0086 1361 str r3, [r2, #16] + 1311 .L66: + 778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + ARM GAS /tmp/ccMLQ7U7.s page 55 + + + 779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 780:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return status; + 1312 .loc 1 781 10 + 1313 0088 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 782:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 1314 .loc 1 782 1 + 1315 008a 1846 mov r0, r3 + 1316 008c 1037 adds r7, r7, #16 + 1317 .cfi_def_cfa_offset 8 + 1318 008e BD46 mov sp, r7 + 1319 .cfi_def_cfa_register 13 + 1320 @ sp needed + 1321 0090 80BD pop {r7, pc} + 1322 .L69: + 1323 0092 00BF .align 2 + 1324 .L68: + 1325 0094 00000000 .word pFlash + 1326 0098 00200240 .word 1073881088 + 1327 009c 00F8FF1F .word 536868864 + 1328 .cfi_endproc + 1329 .LFE139: + 1331 .section .text.FLASH_OB_UserConfig,"ax",%progbits + 1332 .align 1 + 1333 .syntax unified + 1334 .thumb + 1335 .thumb_func + 1337 FLASH_OB_UserConfig: + 1338 .LFB140: + 783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + 785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @brief Program the FLASH User Option Byte. + 786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @note Programming of the OB should be performed only after an erase (otherwise PGERR occurs) + 787:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @param UserConfig The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY + 788:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6). + 789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * And SDADC12_VDD_MONITOR(Bit7) for STM32F373 or STM32F378 . + 790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @retval HAL status + 791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t UserConfig) + 793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 1339 .loc 1 793 1 + 1340 .cfi_startproc + 1341 @ args = 0, pretend = 0, frame = 16 + 1342 @ frame_needed = 1, uses_anonymous_args = 0 + 1343 0000 80B5 push {r7, lr} + 1344 .cfi_def_cfa_offset 8 + 1345 .cfi_offset 7, -8 + 1346 .cfi_offset 14, -4 + 1347 0002 84B0 sub sp, sp, #16 + 1348 .cfi_def_cfa_offset 24 + 1349 0004 00AF add r7, sp, #0 + 1350 .cfi_def_cfa_register 7 + 1351 0006 0346 mov r3, r0 + 1352 0008 FB71 strb r3, [r7, #7] + 794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 1353 .loc 1 794 21 + 1354 000a 0023 movs r3, #0 + ARM GAS /tmp/ccMLQ7U7.s page 56 + + + 1355 000c FB73 strb r3, [r7, #15] + 795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Check the parameters */ + 797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** assert_param(IS_OB_IWDG_SOURCE((UserConfig&OB_IWDG_SW))); + 798:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** assert_param(IS_OB_STOP_SOURCE((UserConfig&OB_STOP_NO_RST))); + 799:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** assert_param(IS_OB_STDBY_SOURCE((UserConfig&OB_STDBY_NO_RST))); + 800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** assert_param(IS_OB_BOOT1((UserConfig&OB_BOOT1_SET))); + 801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** assert_param(IS_OB_VDDA_ANALOG((UserConfig&OB_VDDA_ANALOG_ON))); + 802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** assert_param(IS_OB_SRAM_PARITY((UserConfig&OB_SRAM_PARITY_RESET))); + 803:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(FLASH_OBR_SDADC12_VDD_MONITOR) + 804:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** assert_param(IS_OB_SDACD_VDD_MONITOR((UserConfig&OB_SDACD_VDD_MONITOR_SET))); + 805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* FLASH_OBR_SDADC12_VDD_MONITOR */ + 806:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 807:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 808:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 1356 .loc 1 808 12 + 1357 000e 4CF25030 movw r0, #50000 + 1358 0012 FFF7FEFF bl FLASH_WaitForLastOperation + 1359 0016 0346 mov r3, r0 + 1360 0018 FB73 strb r3, [r7, #15] + 809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if(status == HAL_OK) + 1361 .loc 1 810 5 + 1362 001a FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 1363 001c 002B cmp r3, #0 + 1364 001e 1AD1 bne .L71 + 811:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Clean the error context */ + 813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + 1365 .loc 1 813 22 + 1366 0020 0F4B ldr r3, .L73 + 1367 0022 0022 movs r2, #0 + 1368 0024 DA61 str r2, [r3, #28] + 814:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Enable the Option Bytes Programming operation */ + 816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + 1369 .loc 1 816 5 + 1370 0026 0F4B ldr r3, .L73+4 + 1371 0028 1B69 ldr r3, [r3, #16] + 1372 002a 0E4A ldr r2, .L73+4 + 1373 002c 43F01003 orr r3, r3, #16 + 1374 0030 1361 str r3, [r2, #16] + 817:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 818:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(FLASH_OBR_SDADC12_VDD_MONITOR) + 819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** OB->USER = (UserConfig | 0x08U); + 820:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #else + 821:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** OB->USER = (UserConfig | 0x88U); + 1375 .loc 1 821 14 + 1376 0032 FB79 ldrb r3, [r7, #7] + 1377 0034 63F07703 orn r3, r3, #119 + 1378 0038 DAB2 uxtb r2, r3 + 1379 .loc 1 821 7 + 1380 003a 0B4B ldr r3, .L73+8 + 1381 .loc 1 821 14 + 1382 003c 5A80 strh r2, [r3, #2] @ movhi + 822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif + 823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + ARM GAS /tmp/ccMLQ7U7.s page 57 + + + 824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 1383 .loc 1 825 14 + 1384 003e 4CF25030 movw r0, #50000 + 1385 0042 FFF7FEFF bl FLASH_WaitForLastOperation + 1386 0046 0346 mov r3, r0 + 1387 0048 FB73 strb r3, [r7, #15] + 826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 827:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* if the program operation is completed, disable the OPTPG Bit */ + 828:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + 1388 .loc 1 828 5 + 1389 004a 064B ldr r3, .L73+4 + 1390 004c 1B69 ldr r3, [r3, #16] + 1391 004e 054A ldr r2, .L73+4 + 1392 0050 23F01003 bic r3, r3, #16 + 1393 0054 1361 str r3, [r2, #16] + 1394 .L71: + 829:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 830:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return status; + 1395 .loc 1 831 10 + 1396 0056 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 832:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 1397 .loc 1 832 1 + 1398 0058 1846 mov r0, r3 + 1399 005a 1037 adds r7, r7, #16 + 1400 .cfi_def_cfa_offset 8 + 1401 005c BD46 mov sp, r7 + 1402 .cfi_def_cfa_register 13 + 1403 @ sp needed + 1404 005e 80BD pop {r7, pc} + 1405 .L74: + 1406 .align 2 + 1407 .L73: + 1408 0060 00000000 .word pFlash + 1409 0064 00200240 .word 1073881088 + 1410 0068 00F8FF1F .word 536868864 + 1411 .cfi_endproc + 1412 .LFE140: + 1414 .section .text.FLASH_OB_ProgramData,"ax",%progbits + 1415 .align 1 + 1416 .syntax unified + 1417 .thumb + 1418 .thumb_func + 1420 FLASH_OB_ProgramData: + 1421 .LFB141: + 833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 834:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + 835:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @brief Programs a half word at a specified Option Byte Data address. + 836:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @note The function @ref HAL_FLASH_Unlock() should be called before to unlock the FLASH interf + 837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * The function @ref HAL_FLASH_OB_Unlock() should be called before to unlock the options b + 838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * The function @ref HAL_FLASH_OB_Launch() should be called after to force the reload of t + 839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * (system reset will occur) + 840:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * Programming of the OB should be performed only after an erase (otherwise PGERR occurs) + 841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @param Address specifies the address to be programmed. + 842:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * This parameter can be 0x1FFFF804 or 0x1FFFF806. + 843:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @param Data specifies the data to be programmed. + ARM GAS /tmp/ccMLQ7U7.s page 58 + + + 844:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @retval HAL status + 845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 846:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** static HAL_StatusTypeDef FLASH_OB_ProgramData(uint32_t Address, uint8_t Data) + 847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 1422 .loc 1 847 1 + 1423 .cfi_startproc + 1424 @ args = 0, pretend = 0, frame = 16 + 1425 @ frame_needed = 1, uses_anonymous_args = 0 + 1426 0000 80B5 push {r7, lr} + 1427 .cfi_def_cfa_offset 8 + 1428 .cfi_offset 7, -8 + 1429 .cfi_offset 14, -4 + 1430 0002 84B0 sub sp, sp, #16 + 1431 .cfi_def_cfa_offset 24 + 1432 0004 00AF add r7, sp, #0 + 1433 .cfi_def_cfa_register 7 + 1434 0006 7860 str r0, [r7, #4] + 1435 0008 0B46 mov r3, r1 + 1436 000a FB70 strb r3, [r7, #3] + 848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** HAL_StatusTypeDef status = HAL_ERROR; + 1437 .loc 1 848 21 + 1438 000c 0123 movs r3, #1 + 1439 000e FB73 strb r3, [r7, #15] + 849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Check the parameters */ + 851:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** assert_param(IS_OB_DATA_ADDRESS(Address)); + 852:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 853:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 1440 .loc 1 854 12 + 1441 0010 4CF25030 movw r0, #50000 + 1442 0014 FFF7FEFF bl FLASH_WaitForLastOperation + 1443 0018 0346 mov r3, r0 + 1444 001a FB73 strb r3, [r7, #15] + 855:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 856:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if(status == HAL_OK) + 1445 .loc 1 856 5 + 1446 001c FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 1447 001e 002B cmp r3, #0 + 1448 0020 18D1 bne .L76 + 857:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Clean the error context */ + 859:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + 1449 .loc 1 859 22 + 1450 0022 0F4B ldr r3, .L78 + 1451 0024 0022 movs r2, #0 + 1452 0026 DA61 str r2, [r3, #28] + 860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Enables the Option Bytes Programming operation */ + 862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** SET_BIT(FLASH->CR, FLASH_CR_OPTPG); + 1453 .loc 1 862 5 + 1454 0028 0E4B ldr r3, .L78+4 + 1455 002a 1B69 ldr r3, [r3, #16] + 1456 002c 0D4A ldr r2, .L78+4 + 1457 002e 43F01003 orr r3, r3, #16 + 1458 0032 1361 str r3, [r2, #16] + 863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** *(__IO uint16_t*)Address = Data; + ARM GAS /tmp/ccMLQ7U7.s page 59 + + + 1459 .loc 1 863 6 + 1460 0034 7B68 ldr r3, [r7, #4] + 1461 .loc 1 863 30 + 1462 0036 FA78 ldrb r2, [r7, #3] @ zero_extendqisi2 + 1463 0038 92B2 uxth r2, r2 + 1464 003a 1A80 strh r2, [r3] @ movhi + 864:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Wait for last operation to be completed */ + 866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + 1465 .loc 1 866 14 + 1466 003c 4CF25030 movw r0, #50000 + 1467 0040 FFF7FEFF bl FLASH_WaitForLastOperation + 1468 0044 0346 mov r3, r0 + 1469 0046 FB73 strb r3, [r7, #15] + 867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 868:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* If the program operation is completed, disable the OPTPG Bit */ + 869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** CLEAR_BIT(FLASH->CR, FLASH_CR_OPTPG); + 1470 .loc 1 869 5 + 1471 0048 064B ldr r3, .L78+4 + 1472 004a 1B69 ldr r3, [r3, #16] + 1473 004c 054A ldr r2, .L78+4 + 1474 004e 23F01003 bic r3, r3, #16 + 1475 0052 1361 str r3, [r2, #16] + 1476 .L76: + 870:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Return the Option Byte Data Program Status */ + 872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return status; + 1477 .loc 1 872 10 + 1478 0054 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 873:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 1479 .loc 1 873 1 + 1480 0056 1846 mov r0, r3 + 1481 0058 1037 adds r7, r7, #16 + 1482 .cfi_def_cfa_offset 8 + 1483 005a BD46 mov sp, r7 + 1484 .cfi_def_cfa_register 13 + 1485 @ sp needed + 1486 005c 80BD pop {r7, pc} + 1487 .L79: + 1488 005e 00BF .align 2 + 1489 .L78: + 1490 0060 00000000 .word pFlash + 1491 0064 00200240 .word 1073881088 + 1492 .cfi_endproc + 1493 .LFE141: + 1495 .section .text.FLASH_OB_GetWRP,"ax",%progbits + 1496 .align 1 + 1497 .syntax unified + 1498 .thumb + 1499 .thumb_func + 1501 FLASH_OB_GetWRP: + 1502 .LFB142: + 874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 875:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + 876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @brief Return the FLASH Write Protection Option Bytes value. + 877:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @retval The FLASH Write Protection Option Bytes value + 878:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + ARM GAS /tmp/ccMLQ7U7.s page 60 + + + 879:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** static uint32_t FLASH_OB_GetWRP(void) + 880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 1503 .loc 1 880 1 + 1504 .cfi_startproc + 1505 @ args = 0, pretend = 0, frame = 0 + 1506 @ frame_needed = 1, uses_anonymous_args = 0 + 1507 @ link register save eliminated. + 1508 0000 80B4 push {r7} + 1509 .cfi_def_cfa_offset 4 + 1510 .cfi_offset 7, -4 + 1511 0002 00AF add r7, sp, #0 + 1512 .cfi_def_cfa_register 7 + 881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Return the FLASH write protection Register value */ + 882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return (uint32_t)(READ_REG(FLASH->WRPR)); + 1513 .loc 1 882 21 + 1514 0004 034B ldr r3, .L82 + 1515 .loc 1 882 10 + 1516 0006 1B6A ldr r3, [r3, #32] + 883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 1517 .loc 1 883 1 + 1518 0008 1846 mov r0, r3 + 1519 000a BD46 mov sp, r7 + 1520 .cfi_def_cfa_register 13 + 1521 @ sp needed + 1522 000c 5DF8047B ldr r7, [sp], #4 + 1523 .cfi_restore 7 + 1524 .cfi_def_cfa_offset 0 + 1525 0010 7047 bx lr + 1526 .L83: + 1527 0012 00BF .align 2 + 1528 .L82: + 1529 0014 00200240 .word 1073881088 + 1530 .cfi_endproc + 1531 .LFE142: + 1533 .section .text.FLASH_OB_GetRDP,"ax",%progbits + 1534 .align 1 + 1535 .syntax unified + 1536 .thumb + 1537 .thumb_func + 1539 FLASH_OB_GetRDP: + 1540 .LFB143: + 884:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + 886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @brief Returns the FLASH Read Protection level. + 887:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @retval FLASH RDP level + 888:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * This parameter can be one of the following values: + 889:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @arg @ref OB_RDP_LEVEL_0 No protection + 890:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory + 891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @arg @ref OB_RDP_LEVEL_2 Full chip protection + 892:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** static uint32_t FLASH_OB_GetRDP(void) + 894:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 1541 .loc 1 894 1 + 1542 .cfi_startproc + 1543 @ args = 0, pretend = 0, frame = 8 + 1544 @ frame_needed = 1, uses_anonymous_args = 0 + 1545 @ link register save eliminated. + ARM GAS /tmp/ccMLQ7U7.s page 61 + + + 1546 0000 80B4 push {r7} + 1547 .cfi_def_cfa_offset 4 + 1548 .cfi_offset 7, -4 + 1549 0002 83B0 sub sp, sp, #12 + 1550 .cfi_def_cfa_offset 16 + 1551 0004 00AF add r7, sp, #0 + 1552 .cfi_def_cfa_register 7 + 895:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** uint32_t tmp_reg = 0U; + 1553 .loc 1 895 12 + 1554 0006 0023 movs r3, #0 + 1555 0008 7B60 str r3, [r7, #4] + 896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 897:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Read RDP level bits */ + 898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(FLASH_OBR_RDPRT) + 899:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** tmp_reg = READ_BIT(FLASH->OBR, FLASH_OBR_RDPRT); + 1556 .loc 1 899 13 + 1557 000a 0B4B ldr r3, .L88 + 1558 000c DB69 ldr r3, [r3, #28] + 1559 .loc 1 899 11 + 1560 000e 03F00603 and r3, r3, #6 + 1561 0012 7B60 str r3, [r7, #4] + 900:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #elif defined(FLASH_OBR_LEVEL1_PROT) + 901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** tmp_reg = READ_BIT(FLASH->OBR, (FLASH_OBR_LEVEL1_PROT | FLASH_OBR_LEVEL2_PROT)); + 902:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* FLASH_OBR_RDPRT */ + 903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 904:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #if defined(FLASH_OBR_RDPRT) + 905:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if (tmp_reg == FLASH_OBR_RDPRT_2) + 1562 .loc 1 905 6 + 1563 0014 7B68 ldr r3, [r7, #4] + 1564 0016 062B cmp r3, #6 + 1565 0018 01D1 bne .L85 + 906:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #elif defined(FLASH_OBR_LEVEL1_PROT) + 907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** if (tmp_reg == FLASH_OBR_LEVEL2_PROT) + 908:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** #endif /* FLASH_OBR_RDPRT */ + 909:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return OB_RDP_LEVEL_2; + 1566 .loc 1 910 12 + 1567 001a CC23 movs r3, #204 + 1568 001c 05E0 b .L86 + 1569 .L85: + 911:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** else if (tmp_reg == 0U) + 1570 .loc 1 912 11 + 1571 001e 7B68 ldr r3, [r7, #4] + 1572 0020 002B cmp r3, #0 + 1573 0022 01D1 bne .L87 + 913:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 914:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return OB_RDP_LEVEL_0; + 1574 .loc 1 914 12 + 1575 0024 AA23 movs r3, #170 + 1576 0026 00E0 b .L86 + 1577 .L87: + 915:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 916:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** else + 917:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 918:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return OB_RDP_LEVEL_1; + 1578 .loc 1 918 12 + ARM GAS /tmp/ccMLQ7U7.s page 62 + + + 1579 0028 BB23 movs r3, #187 + 1580 .L86: + 919:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 920:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 1581 .loc 1 920 1 + 1582 002a 1846 mov r0, r3 + 1583 002c 0C37 adds r7, r7, #12 + 1584 .cfi_def_cfa_offset 4 + 1585 002e BD46 mov sp, r7 + 1586 .cfi_def_cfa_register 13 + 1587 @ sp needed + 1588 0030 5DF8047B ldr r7, [sp], #4 + 1589 .cfi_restore 7 + 1590 .cfi_def_cfa_offset 0 + 1591 0034 7047 bx lr + 1592 .L89: + 1593 0036 00BF .align 2 + 1594 .L88: + 1595 0038 00200240 .word 1073881088 + 1596 .cfi_endproc + 1597 .LFE143: + 1599 .section .text.FLASH_OB_GetUser,"ax",%progbits + 1600 .align 1 + 1601 .syntax unified + 1602 .thumb + 1603 .thumb_func + 1605 FLASH_OB_GetUser: + 1606 .LFB144: + 921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 922:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + 923:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @brief Return the FLASH User Option Byte value. + 924:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @retval The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1), RST_STDBY(Bit2), nB + 925:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * VDDA_Analog_Monitoring(Bit5) and SRAM_Parity_Enable(Bit6). + 926:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * And SDADC12_VDD_MONITOR(Bit7) for STM32F373 or STM32F378 . + 927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 928:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** static uint8_t FLASH_OB_GetUser(void) + 929:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 1607 .loc 1 929 1 + 1608 .cfi_startproc + 1609 @ args = 0, pretend = 0, frame = 8 + 1610 @ frame_needed = 1, uses_anonymous_args = 0 + 1611 @ link register save eliminated. + 1612 0000 80B4 push {r7} + 1613 .cfi_def_cfa_offset 4 + 1614 .cfi_offset 7, -4 + 1615 0002 83B0 sub sp, sp, #12 + 1616 .cfi_def_cfa_offset 16 + 1617 0004 00AF add r7, sp, #0 + 1618 .cfi_def_cfa_register 7 + 930:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Return the User Option Byte */ + 931:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** return (uint8_t)((READ_REG(FLASH->OBR) & FLASH_OBR_USER) >> FLASH_POSITION_IWDGSW_BIT); + 1619 .loc 1 931 21 + 1620 0006 0B4B ldr r3, .L93 + 1621 0008 DB69 ldr r3, [r3, #28] + 1622 .loc 1 931 42 + 1623 000a 03F4EE43 and r3, r3, #30464 + 1624 000e 4FF48072 mov r2, #256 + ARM GAS /tmp/ccMLQ7U7.s page 63 + + + 1625 0012 7A60 str r2, [r7, #4] + 1626 .LBB12: + 1627 .LBB13: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 1628 .loc 2 988 4 + 1629 0014 7A68 ldr r2, [r7, #4] + 1630 .syntax unified + 1631 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1632 0016 92FAA2F2 rbit r2, r2 + 1633 @ 0 "" 2 + 1634 .thumb + 1635 .syntax unified + 1636 001a 3A60 str r2, [r7] + 1637 .loc 2 1001 10 + 1638 001c 3A68 ldr r2, [r7] + 1639 .LBE13: + 1640 .LBE12: + 1641 .loc 1 931 63 discriminator 1 + 1642 001e B2FA82F2 clz r2, r2 + 1643 .loc 1 931 63 is_stmt 0 discriminator 2 + 1644 0022 D2B2 uxtb r2, r2 + 1645 .loc 1 931 60 is_stmt 1 discriminator 2 + 1646 0024 D340 lsrs r3, r3, r2 + 1647 .loc 1 931 10 discriminator 2 + 1648 0026 DBB2 uxtb r3, r3 + 932:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 1649 .loc 1 932 1 + 1650 0028 1846 mov r0, r3 + 1651 002a 0C37 adds r7, r7, #12 + 1652 .cfi_def_cfa_offset 4 + 1653 002c BD46 mov sp, r7 + 1654 .cfi_def_cfa_register 13 + 1655 @ sp needed + 1656 002e 5DF8047B ldr r7, [sp], #4 + 1657 .cfi_restore 7 + 1658 .cfi_def_cfa_offset 0 + 1659 0032 7047 bx lr + 1660 .L94: + 1661 .align 2 + 1662 .L93: + 1663 0034 00200240 .word 1073881088 + 1664 .cfi_endproc + 1665 .LFE144: + 1667 .section .text.FLASH_PageErase,"ax",%progbits + 1668 .align 1 + 1669 .global FLASH_PageErase + 1670 .syntax unified + 1671 .thumb + 1672 .thumb_func + 1674 FLASH_PageErase: + 1675 .LFB145: + 933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 934:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + 935:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @} + 936:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + ARM GAS /tmp/ccMLQ7U7.s page 64 + + + 939:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @} + 940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 941:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** @addtogroup FLASH + 943:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @{ + 944:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** @addtogroup FLASH_Private_Functions + 947:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @{ + 948:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 950:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /** + 951:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @brief Erase the specified FLASH memory page + 952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @param PageAddress FLASH page to erase + 953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * The value of this parameter depend on device used within the same series + 954:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * + 955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** * @retval None + 956:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** */ + 957:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** void FLASH_PageErase(uint32_t PageAddress) + 958:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** { + 1676 .loc 1 958 1 + 1677 .cfi_startproc + 1678 @ args = 0, pretend = 0, frame = 8 + 1679 @ frame_needed = 1, uses_anonymous_args = 0 + 1680 @ link register save eliminated. + 1681 0000 80B4 push {r7} + 1682 .cfi_def_cfa_offset 4 + 1683 .cfi_offset 7, -4 + 1684 0002 83B0 sub sp, sp, #12 + 1685 .cfi_def_cfa_offset 16 + 1686 0004 00AF add r7, sp, #0 + 1687 .cfi_def_cfa_register 7 + 1688 0006 7860 str r0, [r7, #4] + 959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Clean the error context */ + 960:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + 1689 .loc 1 960 20 + 1690 0008 0B4B ldr r3, .L96 + 1691 000a 0022 movs r2, #0 + 1692 000c DA61 str r2, [r3, #28] + 961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** + 962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** /* Proceed to erase the page */ + 963:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** SET_BIT(FLASH->CR, FLASH_CR_PER); + 1693 .loc 1 963 5 + 1694 000e 0B4B ldr r3, .L96+4 + 1695 0010 1B69 ldr r3, [r3, #16] + 1696 0012 0A4A ldr r2, .L96+4 + 1697 0014 43F00203 orr r3, r3, #2 + 1698 0018 1361 str r3, [r2, #16] + 964:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** WRITE_REG(FLASH->AR, PageAddress); + 1699 .loc 1 964 5 + 1700 001a 084A ldr r2, .L96+4 + 1701 001c 7B68 ldr r3, [r7, #4] + 1702 001e 5361 str r3, [r2, #20] + 965:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** SET_BIT(FLASH->CR, FLASH_CR_STRT); + 1703 .loc 1 965 5 + 1704 0020 064B ldr r3, .L96+4 + 1705 0022 1B69 ldr r3, [r3, #16] + ARM GAS /tmp/ccMLQ7U7.s page 65 + + + 1706 0024 054A ldr r2, .L96+4 + 1707 0026 43F04003 orr r3, r3, #64 + 1708 002a 1361 str r3, [r2, #16] + 966:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c **** } + 1709 .loc 1 966 1 + 1710 002c 00BF nop + 1711 002e 0C37 adds r7, r7, #12 + 1712 .cfi_def_cfa_offset 4 + 1713 0030 BD46 mov sp, r7 + 1714 .cfi_def_cfa_register 13 + 1715 @ sp needed + 1716 0032 5DF8047B ldr r7, [sp], #4 + 1717 .cfi_restore 7 + 1718 .cfi_def_cfa_offset 0 + 1719 0036 7047 bx lr + 1720 .L97: + 1721 .align 2 + 1722 .L96: + 1723 0038 00000000 .word pFlash + 1724 003c 00200240 .word 1073881088 + 1725 .cfi_endproc + 1726 .LFE145: + 1728 .text + 1729 .Letext0: + 1730 .file 3 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 1731 .file 4 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 1732 .file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + 1733 .file 6 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h" + 1734 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h" + 1735 .file 8 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h" + ARM GAS /tmp/ccMLQ7U7.s page 66 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f3xx_hal_flash_ex.c + /tmp/ccMLQ7U7.s:21 .text.HAL_FLASHEx_Erase:00000000 $t + /tmp/ccMLQ7U7.s:27 .text.HAL_FLASHEx_Erase:00000000 HAL_FLASHEx_Erase + /tmp/ccMLQ7U7.s:747 .text.FLASH_MassErase:00000000 FLASH_MassErase + /tmp/ccMLQ7U7.s:1674 .text.FLASH_PageErase:00000000 FLASH_PageErase + /tmp/ccMLQ7U7.s:172 .text.HAL_FLASHEx_Erase:000000cc $d + /tmp/ccMLQ7U7.s:178 .text.HAL_FLASHEx_Erase_IT:00000000 $t + /tmp/ccMLQ7U7.s:184 .text.HAL_FLASHEx_Erase_IT:00000000 HAL_FLASHEx_Erase_IT + /tmp/ccMLQ7U7.s:283 .text.HAL_FLASHEx_Erase_IT:00000078 $d + /tmp/ccMLQ7U7.s:289 .text.HAL_FLASHEx_OBErase:00000000 $t + /tmp/ccMLQ7U7.s:295 .text.HAL_FLASHEx_OBErase:00000000 HAL_FLASHEx_OBErase + /tmp/ccMLQ7U7.s:1539 .text.FLASH_OB_GetRDP:00000000 FLASH_OB_GetRDP + /tmp/ccMLQ7U7.s:1230 .text.FLASH_OB_RDP_LevelConfig:00000000 FLASH_OB_RDP_LevelConfig + /tmp/ccMLQ7U7.s:380 .text.HAL_FLASHEx_OBErase:0000007c $d + /tmp/ccMLQ7U7.s:386 .text.HAL_FLASHEx_OBProgram:00000000 $t + /tmp/ccMLQ7U7.s:392 .text.HAL_FLASHEx_OBProgram:00000000 HAL_FLASHEx_OBProgram + /tmp/ccMLQ7U7.s:798 .text.FLASH_OB_EnableWRP:00000000 FLASH_OB_EnableWRP + /tmp/ccMLQ7U7.s:1015 .text.FLASH_OB_DisableWRP:00000000 FLASH_OB_DisableWRP + /tmp/ccMLQ7U7.s:1337 .text.FLASH_OB_UserConfig:00000000 FLASH_OB_UserConfig + /tmp/ccMLQ7U7.s:1420 .text.FLASH_OB_ProgramData:00000000 FLASH_OB_ProgramData + /tmp/ccMLQ7U7.s:569 .text.HAL_FLASHEx_OBProgram:000000f4 $d + /tmp/ccMLQ7U7.s:574 .text.HAL_FLASHEx_OBGetConfig:00000000 $t + /tmp/ccMLQ7U7.s:580 .text.HAL_FLASHEx_OBGetConfig:00000000 HAL_FLASHEx_OBGetConfig + /tmp/ccMLQ7U7.s:1501 .text.FLASH_OB_GetWRP:00000000 FLASH_OB_GetWRP + /tmp/ccMLQ7U7.s:1605 .text.FLASH_OB_GetUser:00000000 FLASH_OB_GetUser + /tmp/ccMLQ7U7.s:631 .text.HAL_FLASHEx_OBGetUserData:00000000 $t + /tmp/ccMLQ7U7.s:637 .text.HAL_FLASHEx_OBGetUserData:00000000 HAL_FLASHEx_OBGetUserData + /tmp/ccMLQ7U7.s:736 .text.HAL_FLASHEx_OBGetUserData:00000068 $d + /tmp/ccMLQ7U7.s:742 .text.FLASH_MassErase:00000000 $t + /tmp/ccMLQ7U7.s:787 .text.FLASH_MassErase:0000002c $d + /tmp/ccMLQ7U7.s:793 .text.FLASH_OB_EnableWRP:00000000 $t + /tmp/ccMLQ7U7.s:1003 .text.FLASH_OB_EnableWRP:00000138 $d + /tmp/ccMLQ7U7.s:1010 .text.FLASH_OB_DisableWRP:00000000 $t + /tmp/ccMLQ7U7.s:1218 .text.FLASH_OB_DisableWRP:00000134 $d + /tmp/ccMLQ7U7.s:1225 .text.FLASH_OB_RDP_LevelConfig:00000000 $t + /tmp/ccMLQ7U7.s:1325 .text.FLASH_OB_RDP_LevelConfig:00000094 $d + /tmp/ccMLQ7U7.s:1332 .text.FLASH_OB_UserConfig:00000000 $t + /tmp/ccMLQ7U7.s:1408 .text.FLASH_OB_UserConfig:00000060 $d + /tmp/ccMLQ7U7.s:1415 .text.FLASH_OB_ProgramData:00000000 $t + /tmp/ccMLQ7U7.s:1490 .text.FLASH_OB_ProgramData:00000060 $d + /tmp/ccMLQ7U7.s:1496 .text.FLASH_OB_GetWRP:00000000 $t + /tmp/ccMLQ7U7.s:1529 .text.FLASH_OB_GetWRP:00000014 $d + /tmp/ccMLQ7U7.s:1534 .text.FLASH_OB_GetRDP:00000000 $t + /tmp/ccMLQ7U7.s:1595 .text.FLASH_OB_GetRDP:00000038 $d + /tmp/ccMLQ7U7.s:1600 .text.FLASH_OB_GetUser:00000000 $t + /tmp/ccMLQ7U7.s:1663 .text.FLASH_OB_GetUser:00000034 $d + /tmp/ccMLQ7U7.s:1668 .text.FLASH_PageErase:00000000 $t + /tmp/ccMLQ7U7.s:1723 .text.FLASH_PageErase:00000038 $d + +UNDEFINED SYMBOLS +FLASH_WaitForLastOperation +pFlash diff --git a/Software/build/stm32f3xx_hal_flash_ex.o b/Software/build/stm32f3xx_hal_flash_ex.o new file mode 100644 index 0000000..063a94f Binary files /dev/null and b/Software/build/stm32f3xx_hal_flash_ex.o differ diff --git a/Software/build/stm32f3xx_hal_gpio.d b/Software/build/stm32f3xx_hal_gpio.d new file mode 100644 index 0000000..b39fa5a --- /dev/null +++ b/Software/build/stm32f3xx_hal_gpio.d @@ -0,0 +1,62 @@ +build/stm32f3xx_hal_gpio.o: \ + Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + Core/Inc/stm32f3xx_hal_conf.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h: diff --git a/Software/build/stm32f3xx_hal_gpio.lst b/Software/build/stm32f3xx_hal_gpio.lst new file mode 100644 index 0000000..aa04837 --- /dev/null +++ b/Software/build/stm32f3xx_hal_gpio.lst @@ -0,0 +1,1842 @@ +ARM GAS /tmp/cc63nak4.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 6 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "stm32f3xx_hal_gpio.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c" + 20 .section .text.HAL_GPIO_Init,"ax",%progbits + 21 .align 1 + 22 .global HAL_GPIO_Init + 23 .syntax unified + 24 .thumb + 25 .thumb_func + 27 HAL_GPIO_Init: + 28 .LFB130: + 1:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /** + 2:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** ****************************************************************************** + 3:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @file stm32f3xx_hal_gpio.c + 4:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @author MCD Application Team + 5:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @brief GPIO HAL module driver. + 6:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * functionalities of the General Purpose Input/Output (GPIO) peripheral: + 8:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * + Initialization and de-initialization functions + 9:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * + IO operation functions + 10:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * + 11:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** ****************************************************************************** + 12:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @attention + 13:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * + 14:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * Copyright (c) 2016 STMicroelectronics. + 15:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * All rights reserved. + 16:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * + 17:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * This software is licensed under terms that can be found in the LICENSE file + 18:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * in the root directory of this software component. + 19:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 20:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * + 21:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** ****************************************************************************** + 22:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** @verbatim + 23:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** ============================================================================== + 24:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** ##### GPIO Peripheral features ##### + 25:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** ============================================================================== + 26:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** [..] + 27:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually + 28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** configured by software in several modes: + 29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** (++) Input mode + 30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** (++) Analog mode + ARM GAS /tmp/cc63nak4.s page 2 + + + 31:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** (++) Output mode + 32:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** (++) Alternate function mode + 33:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** (++) External interrupt/event lines + 34:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 35:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** (+) During and just after reset, the alternate functions and external interrupt + 36:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** lines are not active and the I/O ports are configured in input floating mode. + 37:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 38:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be + 39:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** activated or not. + 40:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 41:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull + 42:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** type and the IO speed can be selected depending on the VDD value. + 43:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 44:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** (+) The microcontroller IO pins are connected to onboard peripherals/modules through a + 45:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** multiplexer that allows only one peripheral alternate function (AF) connected + 46:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** to an IO pin at a time. In this way, there can be no conflict between peripherals + 47:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** sharing the same IO pin. + 48:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 49:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** (+) All ports have external interrupt/event capability. To use external interrupt + 50:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** lines, the port must be configured in input mode. All available GPIO pins are + 51:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. + 52:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 53:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** (+) The external interrupt/event controller consists of up to 23 edge detectors + 54:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** (16 lines are connected to GPIO) for generating event/interrupt requests (each + 55:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** input line can be independently configured to select the type (interrupt or event) + 56:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** and the corresponding trigger event (rising or falling or both). Each line can + 57:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** also be masked independently. + 58:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 59:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** ##### How to use this driver ##### + 60:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** ============================================================================== + 61:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** [..] + 62:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(). + 63:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 64:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). + 65:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure + 66:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef + 67:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** structure. + 68:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** (++) In case of Output or alternate function mode selection: the speed is + 69:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** configured through "Speed" member from GPIO_InitTypeDef structure. + 70:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** (++) In alternate mode is selection, the alternate function connected to the IO + 71:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** is configured through "Alternate" member from GPIO_InitTypeDef structure. + 72:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** (++) Analog mode is required when a pin is to be used as ADC channel + 73:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** or DAC output. + 74:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** (++) In case of external interrupt/event selection the "Mode" member from + 75:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** GPIO_InitTypeDef structure select the type (interrupt or event) and + 76:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** the corresponding trigger event (rising or falling or both). + 77:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 78:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority + 79:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using + 80:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** HAL_NVIC_EnableIRQ(). + 81:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 82:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). + 83:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 84:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** (#) To set/reset the level of a pin configured in output mode use + 85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). + 86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). + ARM GAS /tmp/cc63nak4.s page 3 + + + 88:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 89:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** (#) During and just after reset, the alternate functions are not + 90:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** active and the GPIO pins are configured in input floating mode (except JTAG + 91:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** pins). + 92:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 93:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose + 94:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** (PC14 and PC15U, respectively) when the LSE oscillator is off. The LSE has + 95:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** priority over the GPIO function. + 96:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 97:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as + 98:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** general purpose PF0 and PF1, respectively, when the HSE oscillator is off. + 99:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** The HSE has priority over the GPIO function. + 100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** @endverbatim + 102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** ****************************************************************************** + 103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** */ + 104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Includes ------------------------------------------------------------------*/ + 106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** #include "stm32f3xx_hal.h" + 107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /** @addtogroup STM32F3xx_HAL_Driver + 109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @{ + 110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** */ + 111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /** @defgroup GPIO GPIO + 113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @brief GPIO HAL module driver + 114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @{ + 115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** */ + 116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /** MISRA C:2012 deviation rule has been granted for following rules: + 118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * Rule-18.1_d - Medium: Array pointer `GPIOx' is accessed with index [..,..] + 119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * which may be out of array bounds [..,UNKNOWN] in following APIs: + 120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * HAL_GPIO_Init + 121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * HAL_GPIO_DeInit + 122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** */ + 123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** #ifdef HAL_GPIO_MODULE_ENABLED + 125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Private typedef -----------------------------------------------------------*/ + 127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Private defines -----------------------------------------------------------*/ + 128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /** @addtogroup GPIO_Private_Constants + 129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @{ + 130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** */ + 131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** #define GPIO_NUMBER (16U) + 132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /** + 133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @} + 134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** */ + 135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Private macros ------------------------------------------------------------*/ + 137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Private macros ------------------------------------------------------------*/ + 138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /** @defgroup GPIO_Private_Macros GPIO Private Macros + 139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @{ + 140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** */ + 141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /** + 142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @} + 143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** */ + 144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Private variables ---------------------------------------------------------*/ + ARM GAS /tmp/cc63nak4.s page 4 + + + 145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Private function prototypes -----------------------------------------------*/ + 146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Exported functions --------------------------------------------------------*/ + 147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /** @defgroup GPIO_Exported_Functions GPIO Exported Functions + 149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @{ + 150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** */ + 151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions + 153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @brief Initialization and Configuration functions + 154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * + 155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** @verbatim + 156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** =============================================================================== + 157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** ##### Initialization and de-initialization functions ##### + 158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** =============================================================================== + 159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** @endverbatim + 161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @{ + 162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** */ + 163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /** + 165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @brief Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init. + 166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F3 family devices + 167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains + 168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * the configuration information for the specified GPIO peripheral. + 169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @retval None + 170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** */ + 171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) + 172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 29 .loc 1 172 1 + 30 .cfi_startproc + 31 @ args = 0, pretend = 0, frame = 24 + 32 @ frame_needed = 1, uses_anonymous_args = 0 + 33 @ link register save eliminated. + 34 0000 80B4 push {r7} + 35 .cfi_def_cfa_offset 4 + 36 .cfi_offset 7, -4 + 37 0002 87B0 sub sp, sp, #28 + 38 .cfi_def_cfa_offset 32 + 39 0004 00AF add r7, sp, #0 + 40 .cfi_def_cfa_register 7 + 41 0006 7860 str r0, [r7, #4] + 42 0008 3960 str r1, [r7] + 173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** uint32_t position = 0x00u; + 43 .loc 1 173 12 + 44 000a 0023 movs r3, #0 + 45 000c 7B61 str r3, [r7, #20] + 174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** uint32_t iocurrent; + 175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** uint32_t temp; + 176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Check the parameters */ + 178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + 179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + 180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + 181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Configure the port pins */ + 183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** while (((GPIO_Init->Pin) >> position) != 0x00u) + 46 .loc 1 183 9 + ARM GAS /tmp/cc63nak4.s page 5 + + + 47 000e 54E1 b .L2 + 48 .L22: + 184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Get current io position */ + 186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** iocurrent = (GPIO_Init->Pin) & (1uL << position); + 49 .loc 1 186 27 + 50 0010 3B68 ldr r3, [r7] + 51 0012 1A68 ldr r2, [r3] + 52 .loc 1 186 41 + 53 0014 0121 movs r1, #1 + 54 0016 7B69 ldr r3, [r7, #20] + 55 0018 01FA03F3 lsl r3, r1, r3 + 56 .loc 1 186 15 + 57 001c 1340 ands r3, r3, r2 + 58 001e FB60 str r3, [r7, #12] + 187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** if (iocurrent != 0x00u) + 59 .loc 1 188 8 + 60 0020 FB68 ldr r3, [r7, #12] + 61 0022 002B cmp r3, #0 + 62 0024 00F04681 beq .L3 + 189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /*--------------------- GPIO Mode Configuration ------------------------*/ + 191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* In case of Output or Alternate function mode selection */ + 192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_A + 63 .loc 1 192 21 + 64 0028 3B68 ldr r3, [r7] + 65 002a 5B68 ldr r3, [r3, #4] + 66 .loc 1 192 28 + 67 002c 03F00303 and r3, r3, #3 + 68 .loc 1 192 9 + 69 0030 012B cmp r3, #1 + 70 0032 05D0 beq .L4 + 71 .loc 1 192 71 discriminator 1 + 72 0034 3B68 ldr r3, [r7] + 73 0036 5B68 ldr r3, [r3, #4] + 74 .loc 1 192 78 discriminator 1 + 75 0038 03F00303 and r3, r3, #3 + 76 .loc 1 192 57 discriminator 1 + 77 003c 022B cmp r3, #2 + 78 003e 30D1 bne .L5 + 79 .L4: + 193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Check the Speed parameter */ + 195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + 196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Configure the IO Speed */ + 197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp = GPIOx->OSPEEDR; + 80 .loc 1 197 14 + 81 0040 7B68 ldr r3, [r7, #4] + 82 0042 9B68 ldr r3, [r3, #8] + 83 0044 3B61 str r3, [r7, #16] + 198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u)); + 84 .loc 1 198 55 + 85 0046 7B69 ldr r3, [r7, #20] + 86 0048 5B00 lsls r3, r3, #1 + 87 .loc 1 198 42 + 88 004a 0322 movs r2, #3 + ARM GAS /tmp/cc63nak4.s page 6 + + + 89 004c 02FA03F3 lsl r3, r2, r3 + 90 .loc 1 198 17 + 91 0050 DB43 mvns r3, r3 + 92 .loc 1 198 14 + 93 0052 3A69 ldr r2, [r7, #16] + 94 0054 1340 ands r3, r3, r2 + 95 0056 3B61 str r3, [r7, #16] + 199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp |= (GPIO_Init->Speed << (position * 2u)); + 96 .loc 1 199 27 + 97 0058 3B68 ldr r3, [r7] + 98 005a DA68 ldr r2, [r3, #12] + 99 .loc 1 199 48 + 100 005c 7B69 ldr r3, [r7, #20] + 101 005e 5B00 lsls r3, r3, #1 + 102 .loc 1 199 35 + 103 0060 02FA03F3 lsl r3, r2, r3 + 104 .loc 1 199 14 + 105 0064 3A69 ldr r2, [r7, #16] + 106 0066 1343 orrs r3, r3, r2 + 107 0068 3B61 str r3, [r7, #16] + 200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** GPIOx->OSPEEDR = temp; + 108 .loc 1 200 24 + 109 006a 7B68 ldr r3, [r7, #4] + 110 006c 3A69 ldr r2, [r7, #16] + 111 006e 9A60 str r2, [r3, #8] + 201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Configure the IO Output Type */ + 203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp = GPIOx->OTYPER; + 112 .loc 1 203 14 + 113 0070 7B68 ldr r3, [r7, #4] + 114 0072 5B68 ldr r3, [r3, #4] + 115 0074 3B61 str r3, [r7, #16] + 204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp &= ~(GPIO_OTYPER_OT_0 << position) ; + 116 .loc 1 204 36 + 117 0076 0122 movs r2, #1 + 118 0078 7B69 ldr r3, [r7, #20] + 119 007a 02FA03F3 lsl r3, r2, r3 + 120 .loc 1 204 17 + 121 007e DB43 mvns r3, r3 + 122 .loc 1 204 14 + 123 0080 3A69 ldr r2, [r7, #16] + 124 0082 1340 ands r3, r3, r2 + 125 0084 3B61 str r3, [r7, #16] + 205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); + 126 .loc 1 205 29 + 127 0086 3B68 ldr r3, [r7] + 128 0088 5B68 ldr r3, [r3, #4] + 129 .loc 1 205 51 + 130 008a 1B09 lsrs r3, r3, #4 + 131 008c 03F00102 and r2, r3, #1 + 132 .loc 1 205 71 + 133 0090 7B69 ldr r3, [r7, #20] + 134 0092 02FA03F3 lsl r3, r2, r3 + 135 .loc 1 205 14 + 136 0096 3A69 ldr r2, [r7, #16] + 137 0098 1343 orrs r3, r3, r2 + 138 009a 3B61 str r3, [r7, #16] + ARM GAS /tmp/cc63nak4.s page 7 + + + 206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** GPIOx->OTYPER = temp; + 139 .loc 1 206 23 + 140 009c 7B68 ldr r3, [r7, #4] + 141 009e 3A69 ldr r2, [r7, #16] + 142 00a0 5A60 str r2, [r3, #4] + 143 .L5: + 207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) + 144 .loc 1 209 20 + 145 00a2 3B68 ldr r3, [r7] + 146 00a4 5B68 ldr r3, [r3, #4] + 147 .loc 1 209 27 + 148 00a6 03F00303 and r3, r3, #3 + 149 .loc 1 209 9 + 150 00aa 032B cmp r3, #3 + 151 00ac 17D0 beq .L6 + 210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Check the Pull parameter */ + 212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + 213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Activate the Pull-up or Pull down resistor for the current IO */ + 215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp = GPIOx->PUPDR; + 152 .loc 1 215 14 + 153 00ae 7B68 ldr r3, [r7, #4] + 154 00b0 DB68 ldr r3, [r3, #12] + 155 00b2 3B61 str r3, [r7, #16] + 216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u)); + 156 .loc 1 216 50 + 157 00b4 7B69 ldr r3, [r7, #20] + 158 00b6 5B00 lsls r3, r3, #1 + 159 .loc 1 216 37 + 160 00b8 0322 movs r2, #3 + 161 00ba 02FA03F3 lsl r3, r2, r3 + 162 .loc 1 216 17 + 163 00be DB43 mvns r3, r3 + 164 .loc 1 216 14 + 165 00c0 3A69 ldr r2, [r7, #16] + 166 00c2 1340 ands r3, r3, r2 + 167 00c4 3B61 str r3, [r7, #16] + 217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp |= ((GPIO_Init->Pull) << (position * 2u)); + 168 .loc 1 217 28 + 169 00c6 3B68 ldr r3, [r7] + 170 00c8 9A68 ldr r2, [r3, #8] + 171 .loc 1 217 49 + 172 00ca 7B69 ldr r3, [r7, #20] + 173 00cc 5B00 lsls r3, r3, #1 + 174 .loc 1 217 36 + 175 00ce 02FA03F3 lsl r3, r2, r3 + 176 .loc 1 217 14 + 177 00d2 3A69 ldr r2, [r7, #16] + 178 00d4 1343 orrs r3, r3, r2 + 179 00d6 3B61 str r3, [r7, #16] + 218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** GPIOx->PUPDR = temp; + 180 .loc 1 218 22 + 181 00d8 7B68 ldr r3, [r7, #4] + 182 00da 3A69 ldr r2, [r7, #16] + ARM GAS /tmp/cc63nak4.s page 8 + + + 183 00dc DA60 str r2, [r3, #12] + 184 .L6: + 219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /*--------------------- GPIO Mode Configuration ------------------------*/ + 222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* In case of Alternate function mode selection */ + 223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) + 185 .loc 1 223 20 + 186 00de 3B68 ldr r3, [r7] + 187 00e0 5B68 ldr r3, [r3, #4] + 188 .loc 1 223 27 + 189 00e2 03F00303 and r3, r3, #3 + 190 .loc 1 223 9 + 191 00e6 022B cmp r3, #2 + 192 00e8 23D1 bne .L7 + 224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Check the Alternate function parameters */ + 226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + 227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + 228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Configure Alternate function mapped with the current IO */ + 230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp = GPIOx->AFR[position >> 3u]; + 193 .loc 1 230 36 + 194 00ea 7B69 ldr r3, [r7, #20] + 195 00ec DA08 lsrs r2, r3, #3 + 196 .loc 1 230 14 + 197 00ee 7B68 ldr r3, [r7, #4] + 198 00f0 0832 adds r2, r2, #8 + 199 00f2 53F82230 ldr r3, [r3, r2, lsl #2] + 200 00f6 3B61 str r3, [r7, #16] + 231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp &= ~(0xFu << ((position & 0x07u) * 4u)); + 201 .loc 1 231 38 + 202 00f8 7B69 ldr r3, [r7, #20] + 203 00fa 03F00703 and r3, r3, #7 + 204 .loc 1 231 47 + 205 00fe 9B00 lsls r3, r3, #2 + 206 .loc 1 231 24 + 207 0100 0F22 movs r2, #15 + 208 0102 02FA03F3 lsl r3, r2, r3 + 209 .loc 1 231 17 + 210 0106 DB43 mvns r3, r3 + 211 .loc 1 231 14 + 212 0108 3A69 ldr r2, [r7, #16] + 213 010a 1340 ands r3, r3, r2 + 214 010c 3B61 str r3, [r7, #16] + 232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u)); + 215 .loc 1 232 28 + 216 010e 3B68 ldr r3, [r7] + 217 0110 1A69 ldr r2, [r3, #16] + 218 .loc 1 232 55 + 219 0112 7B69 ldr r3, [r7, #20] + 220 0114 03F00703 and r3, r3, #7 + 221 .loc 1 232 64 + 222 0118 9B00 lsls r3, r3, #2 + 223 .loc 1 232 41 + 224 011a 02FA03F3 lsl r3, r2, r3 + 225 .loc 1 232 14 + ARM GAS /tmp/cc63nak4.s page 9 + + + 226 011e 3A69 ldr r2, [r7, #16] + 227 0120 1343 orrs r3, r3, r2 + 228 0122 3B61 str r3, [r7, #16] + 233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** GPIOx->AFR[position >> 3u] = temp; + 229 .loc 1 233 29 + 230 0124 7B69 ldr r3, [r7, #20] + 231 0126 DA08 lsrs r2, r3, #3 + 232 .loc 1 233 36 + 233 0128 7B68 ldr r3, [r7, #4] + 234 012a 0832 adds r2, r2, #8 + 235 012c 3969 ldr r1, [r7, #16] + 236 012e 43F82210 str r1, [r3, r2, lsl #2] + 237 .L7: + 234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + 237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp = GPIOx->MODER; + 238 .loc 1 237 12 + 239 0132 7B68 ldr r3, [r7, #4] + 240 0134 1B68 ldr r3, [r3] + 241 0136 3B61 str r3, [r7, #16] + 238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp &= ~(GPIO_MODER_MODER0 << (position * 2u)); + 242 .loc 1 238 48 + 243 0138 7B69 ldr r3, [r7, #20] + 244 013a 5B00 lsls r3, r3, #1 + 245 .loc 1 238 35 + 246 013c 0322 movs r2, #3 + 247 013e 02FA03F3 lsl r3, r2, r3 + 248 .loc 1 238 15 + 249 0142 DB43 mvns r3, r3 + 250 .loc 1 238 12 + 251 0144 3A69 ldr r2, [r7, #16] + 252 0146 1340 ands r3, r3, r2 + 253 0148 3B61 str r3, [r7, #16] + 239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u)); + 254 .loc 1 239 26 + 255 014a 3B68 ldr r3, [r7] + 256 014c 5B68 ldr r3, [r3, #4] + 257 .loc 1 239 33 + 258 014e 03F00302 and r2, r3, #3 + 259 .loc 1 239 59 + 260 0152 7B69 ldr r3, [r7, #20] + 261 0154 5B00 lsls r3, r3, #1 + 262 .loc 1 239 46 + 263 0156 02FA03F3 lsl r3, r2, r3 + 264 .loc 1 239 12 + 265 015a 3A69 ldr r2, [r7, #16] + 266 015c 1343 orrs r3, r3, r2 + 267 015e 3B61 str r3, [r7, #16] + 240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** GPIOx->MODER = temp; + 268 .loc 1 240 20 + 269 0160 7B68 ldr r3, [r7, #4] + 270 0162 3A69 ldr r2, [r7, #16] + 271 0164 1A60 str r2, [r3] + 241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /*--------------------- EXTI Mode Configuration ------------------------*/ + 243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Configure the External Interrupt or event for the current IO */ + ARM GAS /tmp/cc63nak4.s page 10 + + + 244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** if((GPIO_Init->Mode & EXTI_MODE) != 0x00u) + 272 .loc 1 244 20 + 273 0166 3B68 ldr r3, [r7] + 274 0168 5B68 ldr r3, [r3, #4] + 275 .loc 1 244 27 + 276 016a 03F44033 and r3, r3, #196608 + 277 .loc 1 244 9 + 278 016e 002B cmp r3, #0 + 279 0170 00F0A080 beq .L3 + 280 .LBB2: + 245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Enable SYSCFG Clock */ + 247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** __HAL_RCC_SYSCFG_CLK_ENABLE(); + 281 .loc 1 247 9 + 282 0174 584B ldr r3, .L23 + 283 0176 9B69 ldr r3, [r3, #24] + 284 0178 574A ldr r2, .L23 + 285 017a 43F00103 orr r3, r3, #1 + 286 017e 9361 str r3, [r2, #24] + 287 0180 554B ldr r3, .L23 + 288 0182 9B69 ldr r3, [r3, #24] + 289 0184 03F00103 and r3, r3, #1 + 290 0188 BB60 str r3, [r7, #8] + 291 018a BB68 ldr r3, [r7, #8] + 292 .LBE2: + 248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp = SYSCFG->EXTICR[position >> 2u]; + 293 .loc 1 249 22 + 294 018c 534A ldr r2, .L23+4 + 295 .loc 1 249 40 + 296 018e 7B69 ldr r3, [r7, #20] + 297 0190 9B08 lsrs r3, r3, #2 + 298 .loc 1 249 14 + 299 0192 0233 adds r3, r3, #2 + 300 0194 52F82330 ldr r3, [r2, r3, lsl #2] + 301 0198 3B61 str r3, [r7, #16] + 250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp &= ~(0x0FuL << (4u * (position & 0x03u))); + 302 .loc 1 250 45 + 303 019a 7B69 ldr r3, [r7, #20] + 304 019c 03F00303 and r3, r3, #3 + 305 .loc 1 250 33 + 306 01a0 9B00 lsls r3, r3, #2 + 307 .loc 1 250 26 + 308 01a2 0F22 movs r2, #15 + 309 01a4 02FA03F3 lsl r3, r2, r3 + 310 .loc 1 250 17 + 311 01a8 DB43 mvns r3, r3 + 312 .loc 1 250 14 + 313 01aa 3A69 ldr r2, [r7, #16] + 314 01ac 1340 ands r3, r3, r2 + 315 01ae 3B61 str r3, [r7, #16] + 251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u))); + 316 .loc 1 251 18 + 317 01b0 7B68 ldr r3, [r7, #4] + 318 01b2 B3F1904F cmp r3, #1207959552 + 319 01b6 19D0 beq .L8 + 320 .loc 1 251 18 is_stmt 0 discriminator 1 + ARM GAS /tmp/cc63nak4.s page 11 + + + 321 01b8 7B68 ldr r3, [r7, #4] + 322 01ba 494A ldr r2, .L23+8 + 323 01bc 9342 cmp r3, r2 + 324 01be 13D0 beq .L9 + 325 .loc 1 251 18 discriminator 3 + 326 01c0 7B68 ldr r3, [r7, #4] + 327 01c2 484A ldr r2, .L23+12 + 328 01c4 9342 cmp r3, r2 + 329 01c6 0DD0 beq .L10 + 330 .loc 1 251 18 discriminator 5 + 331 01c8 7B68 ldr r3, [r7, #4] + 332 01ca 474A ldr r2, .L23+16 + 333 01cc 9342 cmp r3, r2 + 334 01ce 07D0 beq .L11 + 335 .loc 1 251 18 discriminator 7 + 336 01d0 7B68 ldr r3, [r7, #4] + 337 01d2 464A ldr r2, .L23+20 + 338 01d4 9342 cmp r3, r2 + 339 01d6 01D1 bne .L12 + 340 .loc 1 251 18 discriminator 9 + 341 01d8 0423 movs r3, #4 + 342 01da 08E0 b .L17 + 343 .L12: + 344 .loc 1 251 18 discriminator 10 + 345 01dc 0523 movs r3, #5 + 346 01de 06E0 b .L17 + 347 .L11: + 348 .loc 1 251 18 discriminator 8 + 349 01e0 0323 movs r3, #3 + 350 01e2 04E0 b .L17 + 351 .L10: + 352 .loc 1 251 18 discriminator 6 + 353 01e4 0223 movs r3, #2 + 354 01e6 02E0 b .L17 + 355 .L9: + 356 .loc 1 251 18 discriminator 4 + 357 01e8 0123 movs r3, #1 + 358 01ea 00E0 b .L17 + 359 .L8: + 360 .loc 1 251 18 discriminator 2 + 361 01ec 0023 movs r3, #0 + 362 .L17: + 363 .loc 1 251 59 is_stmt 1 discriminator 20 + 364 01ee 7A69 ldr r2, [r7, #20] + 365 01f0 02F00302 and r2, r2, #3 + 366 .loc 1 251 47 discriminator 20 + 367 01f4 9200 lsls r2, r2, #2 + 368 .loc 1 251 40 discriminator 20 + 369 01f6 9340 lsls r3, r3, r2 + 370 .loc 1 251 14 discriminator 20 + 371 01f8 3A69 ldr r2, [r7, #16] + 372 01fa 1343 orrs r3, r3, r2 + 373 01fc 3B61 str r3, [r7, #16] + 252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2u] = temp; + 374 .loc 1 252 15 + 375 01fe 3749 ldr r1, .L23+4 + 376 .loc 1 252 33 + ARM GAS /tmp/cc63nak4.s page 12 + + + 377 0200 7B69 ldr r3, [r7, #20] + 378 0202 9B08 lsrs r3, r3, #2 + 379 .loc 1 252 40 + 380 0204 0233 adds r3, r3, #2 + 381 0206 3A69 ldr r2, [r7, #16] + 382 0208 41F82320 str r2, [r1, r3, lsl #2] + 253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Clear Rising Falling edge configuration */ + 255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp = EXTI->RTSR; + 383 .loc 1 255 20 + 384 020c 384B ldr r3, .L23+24 + 385 .loc 1 255 14 + 386 020e 9B68 ldr r3, [r3, #8] + 387 0210 3B61 str r3, [r7, #16] + 256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp &= ~(iocurrent); + 388 .loc 1 256 17 + 389 0212 FB68 ldr r3, [r7, #12] + 390 0214 DB43 mvns r3, r3 + 391 .loc 1 256 14 + 392 0216 3A69 ldr r2, [r7, #16] + 393 0218 1340 ands r3, r3, r2 + 394 021a 3B61 str r3, [r7, #16] + 257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u) + 395 .loc 1 257 22 + 396 021c 3B68 ldr r3, [r7] + 397 021e 5B68 ldr r3, [r3, #4] + 398 .loc 1 257 29 + 399 0220 03F48013 and r3, r3, #1048576 + 400 .loc 1 257 11 + 401 0224 002B cmp r3, #0 + 402 0226 03D0 beq .L18 + 258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp |= iocurrent; + 403 .loc 1 259 16 + 404 0228 3A69 ldr r2, [r7, #16] + 405 022a FB68 ldr r3, [r7, #12] + 406 022c 1343 orrs r3, r3, r2 + 407 022e 3B61 str r3, [r7, #16] + 408 .L18: + 260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** EXTI->RTSR = temp; + 409 .loc 1 261 13 + 410 0230 2F4A ldr r2, .L23+24 + 411 .loc 1 261 20 + 412 0232 3B69 ldr r3, [r7, #16] + 413 0234 9360 str r3, [r2, #8] + 262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp = EXTI->FTSR; + 414 .loc 1 263 20 + 415 0236 2E4B ldr r3, .L23+24 + 416 .loc 1 263 14 + 417 0238 DB68 ldr r3, [r3, #12] + 418 023a 3B61 str r3, [r7, #16] + 264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp &= ~(iocurrent); + 419 .loc 1 264 17 + 420 023c FB68 ldr r3, [r7, #12] + 421 023e DB43 mvns r3, r3 + ARM GAS /tmp/cc63nak4.s page 13 + + + 422 .loc 1 264 14 + 423 0240 3A69 ldr r2, [r7, #16] + 424 0242 1340 ands r3, r3, r2 + 425 0244 3B61 str r3, [r7, #16] + 265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u) + 426 .loc 1 265 22 + 427 0246 3B68 ldr r3, [r7] + 428 0248 5B68 ldr r3, [r3, #4] + 429 .loc 1 265 29 + 430 024a 03F40013 and r3, r3, #2097152 + 431 .loc 1 265 11 + 432 024e 002B cmp r3, #0 + 433 0250 03D0 beq .L19 + 266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp |= iocurrent; + 434 .loc 1 267 16 + 435 0252 3A69 ldr r2, [r7, #16] + 436 0254 FB68 ldr r3, [r7, #12] + 437 0256 1343 orrs r3, r3, r2 + 438 0258 3B61 str r3, [r7, #16] + 439 .L19: + 268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** EXTI->FTSR = temp; + 440 .loc 1 269 13 + 441 025a 254A ldr r2, .L23+24 + 442 .loc 1 269 20 + 443 025c 3B69 ldr r3, [r7, #16] + 444 025e D360 str r3, [r2, #12] + 270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp = EXTI->EMR; + 445 .loc 1 271 20 + 446 0260 234B ldr r3, .L23+24 + 447 .loc 1 271 14 + 448 0262 5B68 ldr r3, [r3, #4] + 449 0264 3B61 str r3, [r7, #16] + 272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp &= ~(iocurrent); + 450 .loc 1 272 17 + 451 0266 FB68 ldr r3, [r7, #12] + 452 0268 DB43 mvns r3, r3 + 453 .loc 1 272 14 + 454 026a 3A69 ldr r2, [r7, #16] + 455 026c 1340 ands r3, r3, r2 + 456 026e 3B61 str r3, [r7, #16] + 273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** if((GPIO_Init->Mode & EXTI_EVT) != 0x00u) + 457 .loc 1 273 22 + 458 0270 3B68 ldr r3, [r7] + 459 0272 5B68 ldr r3, [r3, #4] + 460 .loc 1 273 29 + 461 0274 03F40033 and r3, r3, #131072 + 462 .loc 1 273 11 + 463 0278 002B cmp r3, #0 + 464 027a 03D0 beq .L20 + 274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp |= iocurrent; + 465 .loc 1 275 16 + 466 027c 3A69 ldr r2, [r7, #16] + 467 027e FB68 ldr r3, [r7, #12] + ARM GAS /tmp/cc63nak4.s page 14 + + + 468 0280 1343 orrs r3, r3, r2 + 469 0282 3B61 str r3, [r7, #16] + 470 .L20: + 276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** EXTI->EMR = temp; + 471 .loc 1 277 13 + 472 0284 1A4A ldr r2, .L23+24 + 473 .loc 1 277 19 + 474 0286 3B69 ldr r3, [r7, #16] + 475 0288 5360 str r3, [r2, #4] + 278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Clear EXTI line configuration */ + 280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp = EXTI->IMR; + 476 .loc 1 280 20 + 477 028a 194B ldr r3, .L23+24 + 478 .loc 1 280 14 + 479 028c 1B68 ldr r3, [r3] + 480 028e 3B61 str r3, [r7, #16] + 281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp &= ~(iocurrent); + 481 .loc 1 281 17 + 482 0290 FB68 ldr r3, [r7, #12] + 483 0292 DB43 mvns r3, r3 + 484 .loc 1 281 14 + 485 0294 3A69 ldr r2, [r7, #16] + 486 0296 1340 ands r3, r3, r2 + 487 0298 3B61 str r3, [r7, #16] + 282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** if((GPIO_Init->Mode & EXTI_IT) != 0x00u) + 488 .loc 1 282 22 + 489 029a 3B68 ldr r3, [r7] + 490 029c 5B68 ldr r3, [r3, #4] + 491 .loc 1 282 29 + 492 029e 03F48033 and r3, r3, #65536 + 493 .loc 1 282 11 + 494 02a2 002B cmp r3, #0 + 495 02a4 03D0 beq .L21 + 283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** temp |= iocurrent; + 496 .loc 1 284 16 + 497 02a6 3A69 ldr r2, [r7, #16] + 498 02a8 FB68 ldr r3, [r7, #12] + 499 02aa 1343 orrs r3, r3, r2 + 500 02ac 3B61 str r3, [r7, #16] + 501 .L21: + 285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** EXTI->IMR = temp; + 502 .loc 1 286 13 + 503 02ae 104A ldr r2, .L23+24 + 504 .loc 1 286 19 + 505 02b0 3B69 ldr r3, [r7, #16] + 506 02b2 1360 str r3, [r2] + 507 .L3: + 287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** position++; + 508 .loc 1 290 13 + 509 02b4 7B69 ldr r3, [r7, #20] + ARM GAS /tmp/cc63nak4.s page 15 + + + 510 02b6 0133 adds r3, r3, #1 + 511 02b8 7B61 str r3, [r7, #20] + 512 .L2: + 183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 513 .loc 1 183 21 + 514 02ba 3B68 ldr r3, [r7] + 515 02bc 1A68 ldr r2, [r3] + 183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 516 .loc 1 183 28 + 517 02be 7B69 ldr r3, [r7, #20] + 518 02c0 22FA03F3 lsr r3, r2, r3 + 183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 519 .loc 1 183 41 + 520 02c4 002B cmp r3, #0 + 521 02c6 7FF4A3AE bne .L22 + 291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 522 .loc 1 292 1 + 523 02ca 00BF nop + 524 02cc 00BF nop + 525 02ce 1C37 adds r7, r7, #28 + 526 .cfi_def_cfa_offset 4 + 527 02d0 BD46 mov sp, r7 + 528 .cfi_def_cfa_register 13 + 529 @ sp needed + 530 02d2 5DF8047B ldr r7, [sp], #4 + 531 .cfi_restore 7 + 532 .cfi_def_cfa_offset 0 + 533 02d6 7047 bx lr + 534 .L24: + 535 .align 2 + 536 .L23: + 537 02d8 00100240 .word 1073876992 + 538 02dc 00000140 .word 1073807360 + 539 02e0 00040048 .word 1207960576 + 540 02e4 00080048 .word 1207961600 + 541 02e8 000C0048 .word 1207962624 + 542 02ec 00100048 .word 1207963648 + 543 02f0 00040140 .word 1073808384 + 544 .cfi_endproc + 545 .LFE130: + 547 .section .text.HAL_GPIO_DeInit,"ax",%progbits + 548 .align 1 + 549 .global HAL_GPIO_DeInit + 550 .syntax unified + 551 .thumb + 552 .thumb_func + 554 HAL_GPIO_DeInit: + 555 .LFB131: + 293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /** + 295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @brief De-initialize the GPIOx peripheral registers to their default reset values. + 296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F30X device or STM32 + 297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @param GPIO_Pin specifies the port bit to be written. + 298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * This parameter can be one of GPIO_PIN_x where x can be (0..15). + 299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @retval None + 300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** */ + ARM GAS /tmp/cc63nak4.s page 16 + + + 301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) + 302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 556 .loc 1 302 1 + 557 .cfi_startproc + 558 @ args = 0, pretend = 0, frame = 24 + 559 @ frame_needed = 1, uses_anonymous_args = 0 + 560 @ link register save eliminated. + 561 0000 80B4 push {r7} + 562 .cfi_def_cfa_offset 4 + 563 .cfi_offset 7, -4 + 564 0002 87B0 sub sp, sp, #28 + 565 .cfi_def_cfa_offset 32 + 566 0004 00AF add r7, sp, #0 + 567 .cfi_def_cfa_register 7 + 568 0006 7860 str r0, [r7, #4] + 569 0008 3960 str r1, [r7] + 303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** uint32_t position = 0x00u; + 570 .loc 1 303 12 + 571 000a 0023 movs r3, #0 + 572 000c 7B61 str r3, [r7, #20] + 304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** uint32_t iocurrent; + 305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** uint32_t tmp; + 306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Check the parameters */ + 308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + 309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** assert_param(IS_GPIO_PIN(GPIO_Pin)); + 310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Configure the port pins */ + 312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** while ((GPIO_Pin >> position) != 0x00u) + 573 .loc 1 312 9 + 574 000e B8E0 b .L26 + 575 .L39: + 313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Get current io position */ + 315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** iocurrent = (GPIO_Pin) & (1uL << position); + 576 .loc 1 315 35 + 577 0010 0122 movs r2, #1 + 578 0012 7B69 ldr r3, [r7, #20] + 579 0014 02FA03F3 lsl r3, r2, r3 + 580 .loc 1 315 15 + 581 0018 3A68 ldr r2, [r7] + 582 001a 1340 ands r3, r3, r2 + 583 001c 3B61 str r3, [r7, #16] + 316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** if (iocurrent != 0x00u) + 584 .loc 1 317 8 + 585 001e 3B69 ldr r3, [r7, #16] + 586 0020 002B cmp r3, #0 + 587 0022 00F0AB80 beq .L27 + 318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /*------------------------- EXTI Mode Configuration --------------------*/ + 320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Clear the External Interrupt or Event for the current IO */ + 321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** tmp = SYSCFG->EXTICR[position >> 2u]; + 588 .loc 1 322 19 + 589 0026 5E4A ldr r2, .L40 + 590 .loc 1 322 37 + ARM GAS /tmp/cc63nak4.s page 17 + + + 591 0028 7B69 ldr r3, [r7, #20] + 592 002a 9B08 lsrs r3, r3, #2 + 593 .loc 1 322 11 + 594 002c 0233 adds r3, r3, #2 + 595 002e 52F82330 ldr r3, [r2, r3, lsl #2] + 596 0032 FB60 str r3, [r7, #12] + 323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** tmp &= (0x0FuL << (4u * (position & 0x03u))); + 597 .loc 1 323 41 + 598 0034 7B69 ldr r3, [r7, #20] + 599 0036 03F00303 and r3, r3, #3 + 600 .loc 1 323 29 + 601 003a 9B00 lsls r3, r3, #2 + 602 .loc 1 323 22 + 603 003c 0F22 movs r2, #15 + 604 003e 02FA03F3 lsl r3, r2, r3 + 605 .loc 1 323 11 + 606 0042 FA68 ldr r2, [r7, #12] + 607 0044 1340 ands r3, r3, r2 + 608 0046 FB60 str r3, [r7, #12] + 324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** if (tmp == (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)))) + 609 .loc 1 324 19 + 610 0048 7B68 ldr r3, [r7, #4] + 611 004a B3F1904F cmp r3, #1207959552 + 612 004e 19D0 beq .L28 + 613 .loc 1 324 19 is_stmt 0 discriminator 1 + 614 0050 7B68 ldr r3, [r7, #4] + 615 0052 544A ldr r2, .L40+4 + 616 0054 9342 cmp r3, r2 + 617 0056 13D0 beq .L29 + 618 .loc 1 324 19 discriminator 3 + 619 0058 7B68 ldr r3, [r7, #4] + 620 005a 534A ldr r2, .L40+8 + 621 005c 9342 cmp r3, r2 + 622 005e 0DD0 beq .L30 + 623 .loc 1 324 19 discriminator 5 + 624 0060 7B68 ldr r3, [r7, #4] + 625 0062 524A ldr r2, .L40+12 + 626 0064 9342 cmp r3, r2 + 627 0066 07D0 beq .L31 + 628 .loc 1 324 19 discriminator 7 + 629 0068 7B68 ldr r3, [r7, #4] + 630 006a 514A ldr r2, .L40+16 + 631 006c 9342 cmp r3, r2 + 632 006e 01D1 bne .L32 + 633 .loc 1 324 19 discriminator 9 + 634 0070 0423 movs r3, #4 + 635 0072 08E0 b .L37 + 636 .L32: + 637 .loc 1 324 19 discriminator 10 + 638 0074 0523 movs r3, #5 + 639 0076 06E0 b .L37 + 640 .L31: + 641 .loc 1 324 19 discriminator 8 + 642 0078 0323 movs r3, #3 + 643 007a 04E0 b .L37 + 644 .L30: + 645 .loc 1 324 19 discriminator 6 + ARM GAS /tmp/cc63nak4.s page 18 + + + 646 007c 0223 movs r3, #2 + 647 007e 02E0 b .L37 + 648 .L29: + 649 .loc 1 324 19 discriminator 4 + 650 0080 0123 movs r3, #1 + 651 0082 00E0 b .L37 + 652 .L28: + 653 .loc 1 324 19 discriminator 2 + 654 0084 0023 movs r3, #0 + 655 .L37: + 656 .loc 1 324 60 is_stmt 1 discriminator 20 + 657 0086 7A69 ldr r2, [r7, #20] + 658 0088 02F00302 and r2, r2, #3 + 659 .loc 1 324 48 discriminator 20 + 660 008c 9200 lsls r2, r2, #2 + 661 .loc 1 324 41 discriminator 20 + 662 008e 9340 lsls r3, r3, r2 + 663 .loc 1 324 10 discriminator 20 + 664 0090 FA68 ldr r2, [r7, #12] + 665 0092 9A42 cmp r2, r3 + 666 0094 32D1 bne .L38 + 325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Clear EXTI line configuration */ + 327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** EXTI->IMR &= ~((uint32_t)iocurrent); + 667 .loc 1 327 13 + 668 0096 474B ldr r3, .L40+20 + 669 0098 1A68 ldr r2, [r3] + 670 .loc 1 327 22 + 671 009a 3B69 ldr r3, [r7, #16] + 672 009c DB43 mvns r3, r3 + 673 .loc 1 327 13 + 674 009e 4549 ldr r1, .L40+20 + 675 .loc 1 327 19 + 676 00a0 1340 ands r3, r3, r2 + 677 00a2 0B60 str r3, [r1] + 328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** EXTI->EMR &= ~((uint32_t)iocurrent); + 678 .loc 1 328 13 + 679 00a4 434B ldr r3, .L40+20 + 680 00a6 5A68 ldr r2, [r3, #4] + 681 .loc 1 328 22 + 682 00a8 3B69 ldr r3, [r7, #16] + 683 00aa DB43 mvns r3, r3 + 684 .loc 1 328 13 + 685 00ac 4149 ldr r1, .L40+20 + 686 .loc 1 328 19 + 687 00ae 1340 ands r3, r3, r2 + 688 00b0 4B60 str r3, [r1, #4] + 329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Clear Rising Falling edge configuration */ + 331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** EXTI->FTSR &= ~((uint32_t)iocurrent); + 689 .loc 1 331 13 + 690 00b2 404B ldr r3, .L40+20 + 691 00b4 DA68 ldr r2, [r3, #12] + 692 .loc 1 331 23 + 693 00b6 3B69 ldr r3, [r7, #16] + 694 00b8 DB43 mvns r3, r3 + 695 .loc 1 331 13 + ARM GAS /tmp/cc63nak4.s page 19 + + + 696 00ba 3E49 ldr r1, .L40+20 + 697 .loc 1 331 20 + 698 00bc 1340 ands r3, r3, r2 + 699 00be CB60 str r3, [r1, #12] + 332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** EXTI->RTSR &= ~((uint32_t)iocurrent); + 700 .loc 1 332 13 + 701 00c0 3C4B ldr r3, .L40+20 + 702 00c2 9A68 ldr r2, [r3, #8] + 703 .loc 1 332 23 + 704 00c4 3B69 ldr r3, [r7, #16] + 705 00c6 DB43 mvns r3, r3 + 706 .loc 1 332 13 + 707 00c8 3A49 ldr r1, .L40+20 + 708 .loc 1 332 20 + 709 00ca 1340 ands r3, r3, r2 + 710 00cc 8B60 str r3, [r1, #8] + 333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Configure the External Interrupt or event for the current IO */ + 335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** tmp = 0x0FuL << (4u * (position & 0x03u)); + 711 .loc 1 335 41 + 712 00ce 7B69 ldr r3, [r7, #20] + 713 00d0 03F00303 and r3, r3, #3 + 714 .loc 1 335 29 + 715 00d4 9B00 lsls r3, r3, #2 + 716 .loc 1 335 13 + 717 00d6 0F22 movs r2, #15 + 718 00d8 02FA03F3 lsl r3, r2, r3 + 719 00dc FB60 str r3, [r7, #12] + 336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** SYSCFG->EXTICR[position >> 2u] &= ~tmp; + 720 .loc 1 336 15 + 721 00de 304A ldr r2, .L40 + 722 .loc 1 336 23 + 723 00e0 7B69 ldr r3, [r7, #20] + 724 00e2 9B08 lsrs r3, r3, #2 + 725 00e4 0233 adds r3, r3, #2 + 726 00e6 52F82310 ldr r1, [r2, r3, lsl #2] + 727 .loc 1 336 43 + 728 00ea FB68 ldr r3, [r7, #12] + 729 00ec DA43 mvns r2, r3 + 730 .loc 1 336 15 + 731 00ee 2C48 ldr r0, .L40 + 732 .loc 1 336 23 + 733 00f0 7B69 ldr r3, [r7, #20] + 734 00f2 9B08 lsrs r3, r3, #2 + 735 .loc 1 336 40 + 736 00f4 0A40 ands r2, r2, r1 + 737 00f6 0233 adds r3, r3, #2 + 738 00f8 40F82320 str r2, [r0, r3, lsl #2] + 739 .L38: + 337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /*------------------------- GPIO Mode Configuration --------------------*/ + 340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Configure IO Direction in Input Floating Mode */ + 341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2u)); + 740 .loc 1 341 12 + 741 00fc 7B68 ldr r3, [r7, #4] + 742 00fe 1A68 ldr r2, [r3] + ARM GAS /tmp/cc63nak4.s page 20 + + + 743 .loc 1 341 56 + 744 0100 7B69 ldr r3, [r7, #20] + 745 0102 5B00 lsls r3, r3, #1 + 746 .loc 1 341 43 + 747 0104 0321 movs r1, #3 + 748 0106 01FA03F3 lsl r3, r1, r3 + 749 .loc 1 341 23 + 750 010a DB43 mvns r3, r3 + 751 .loc 1 341 20 + 752 010c 1A40 ands r2, r2, r3 + 753 010e 7B68 ldr r3, [r7, #4] + 754 0110 1A60 str r2, [r3] + 342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Configure the default Alternate Function in current IO */ + 344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** GPIOx->AFR[position >> 3u] &= ~(0xFu << ((uint32_t)(position & 0x07u) * 4u)) ; + 755 .loc 1 344 17 + 756 0112 7B69 ldr r3, [r7, #20] + 757 0114 DA08 lsrs r2, r3, #3 + 758 0116 7B68 ldr r3, [r7, #4] + 759 0118 0832 adds r2, r2, #8 + 760 011a 53F82210 ldr r1, [r3, r2, lsl #2] + 761 .loc 1 344 48 + 762 011e 7B69 ldr r3, [r7, #20] + 763 0120 03F00703 and r3, r3, #7 + 764 .loc 1 344 77 + 765 0124 9B00 lsls r3, r3, #2 + 766 .loc 1 344 44 + 767 0126 0F22 movs r2, #15 + 768 0128 02FA03F3 lsl r3, r2, r3 + 769 .loc 1 344 37 + 770 012c DB43 mvns r3, r3 + 771 .loc 1 344 17 + 772 012e 7A69 ldr r2, [r7, #20] + 773 0130 D208 lsrs r2, r2, #3 + 774 .loc 1 344 34 + 775 0132 1940 ands r1, r1, r3 + 776 0134 7B68 ldr r3, [r7, #4] + 777 0136 0832 adds r2, r2, #8 + 778 0138 43F82210 str r1, [r3, r2, lsl #2] + 345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Deactivate the Pull-up and Pull-down resistor for the current IO */ + 347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u)); + 779 .loc 1 347 12 + 780 013c 7B68 ldr r3, [r7, #4] + 781 013e DA68 ldr r2, [r3, #12] + 782 .loc 1 347 56 + 783 0140 7B69 ldr r3, [r7, #20] + 784 0142 5B00 lsls r3, r3, #1 + 785 .loc 1 347 43 + 786 0144 0321 movs r1, #3 + 787 0146 01FA03F3 lsl r3, r1, r3 + 788 .loc 1 347 23 + 789 014a DB43 mvns r3, r3 + 790 .loc 1 347 20 + 791 014c 1A40 ands r2, r2, r3 + 792 014e 7B68 ldr r3, [r7, #4] + 793 0150 DA60 str r2, [r3, #12] + ARM GAS /tmp/cc63nak4.s page 21 + + + 348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Configure the default value IO Output Type */ + 350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ; + 794 .loc 1 350 12 + 795 0152 7B68 ldr r3, [r7, #4] + 796 0154 5A68 ldr r2, [r3, #4] + 797 .loc 1 350 44 + 798 0156 0121 movs r1, #1 + 799 0158 7B69 ldr r3, [r7, #20] + 800 015a 01FA03F3 lsl r3, r1, r3 + 801 .loc 1 350 25 + 802 015e DB43 mvns r3, r3 + 803 .loc 1 350 22 + 804 0160 1A40 ands r2, r2, r3 + 805 0162 7B68 ldr r3, [r7, #4] + 806 0164 5A60 str r2, [r3, #4] + 351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Configure the default value for IO Speed */ + 353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u)); + 807 .loc 1 353 12 + 808 0166 7B68 ldr r3, [r7, #4] + 809 0168 9A68 ldr r2, [r3, #8] + 810 .loc 1 353 63 + 811 016a 7B69 ldr r3, [r7, #20] + 812 016c 5B00 lsls r3, r3, #1 + 813 .loc 1 353 50 + 814 016e 0321 movs r1, #3 + 815 0170 01FA03F3 lsl r3, r1, r3 + 816 .loc 1 353 25 + 817 0174 DB43 mvns r3, r3 + 818 .loc 1 353 22 + 819 0176 1A40 ands r2, r2, r3 + 820 0178 7B68 ldr r3, [r7, #4] + 821 017a 9A60 str r2, [r3, #8] + 822 .L27: + 354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** position++; + 823 .loc 1 356 13 + 824 017c 7B69 ldr r3, [r7, #20] + 825 017e 0133 adds r3, r3, #1 + 826 0180 7B61 str r3, [r7, #20] + 827 .L26: + 312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 828 .loc 1 312 20 + 829 0182 3A68 ldr r2, [r7] + 830 0184 7B69 ldr r3, [r7, #20] + 831 0186 22FA03F3 lsr r3, r2, r3 + 312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 832 .loc 1 312 33 + 833 018a 002B cmp r3, #0 + 834 018c 7FF440AF bne .L39 + 357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 835 .loc 1 358 1 + 836 0190 00BF nop + 837 0192 00BF nop + ARM GAS /tmp/cc63nak4.s page 22 + + + 838 0194 1C37 adds r7, r7, #28 + 839 .cfi_def_cfa_offset 4 + 840 0196 BD46 mov sp, r7 + 841 .cfi_def_cfa_register 13 + 842 @ sp needed + 843 0198 5DF8047B ldr r7, [sp], #4 + 844 .cfi_restore 7 + 845 .cfi_def_cfa_offset 0 + 846 019c 7047 bx lr + 847 .L41: + 848 019e 00BF .align 2 + 849 .L40: + 850 01a0 00000140 .word 1073807360 + 851 01a4 00040048 .word 1207960576 + 852 01a8 00080048 .word 1207961600 + 853 01ac 000C0048 .word 1207962624 + 854 01b0 00100048 .word 1207963648 + 855 01b4 00040140 .word 1073808384 + 856 .cfi_endproc + 857 .LFE131: + 859 .section .text.HAL_GPIO_ReadPin,"ax",%progbits + 860 .align 1 + 861 .global HAL_GPIO_ReadPin + 862 .syntax unified + 863 .thumb + 864 .thumb_func + 866 HAL_GPIO_ReadPin: + 867 .LFB132: + 359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /** + 361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @} + 362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** */ + 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /** @defgroup GPIO_Exported_Functions_Group2 IO operation functions + 365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @brief GPIO Read, Write, Toggle, Lock and EXTI management functions. + 366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * + 367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** @verbatim + 368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** =============================================================================== + 369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** ##### IO operation functions ##### + 370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** =============================================================================== + 371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** @endverbatim + 373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @{ + 374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** */ + 375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /** + 377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @brief Read the specified input port pin. + 378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F3 family + 379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @param GPIO_Pin specifies the port bit to read. + 380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * This parameter can be GPIO_PIN_x where x can be (0..15). + 381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @retval The input port pin value. + 382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** */ + 383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) + 384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 868 .loc 1 384 1 + 869 .cfi_startproc + 870 @ args = 0, pretend = 0, frame = 16 + ARM GAS /tmp/cc63nak4.s page 23 + + + 871 @ frame_needed = 1, uses_anonymous_args = 0 + 872 @ link register save eliminated. + 873 0000 80B4 push {r7} + 874 .cfi_def_cfa_offset 4 + 875 .cfi_offset 7, -4 + 876 0002 85B0 sub sp, sp, #20 + 877 .cfi_def_cfa_offset 24 + 878 0004 00AF add r7, sp, #0 + 879 .cfi_def_cfa_register 7 + 880 0006 7860 str r0, [r7, #4] + 881 0008 0B46 mov r3, r1 + 882 000a 7B80 strh r3, [r7, #2] @ movhi + 385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** GPIO_PinState bitstatus; + 386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Check the parameters */ + 388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** assert_param(IS_GPIO_PIN(GPIO_Pin)); + 389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) + 883 .loc 1 390 12 + 884 000c 7B68 ldr r3, [r7, #4] + 885 000e 1A69 ldr r2, [r3, #16] + 886 .loc 1 390 18 + 887 0010 7B88 ldrh r3, [r7, #2] + 888 0012 1340 ands r3, r3, r2 + 889 .loc 1 390 5 + 890 0014 002B cmp r3, #0 + 891 0016 02D0 beq .L43 + 391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** bitstatus = GPIO_PIN_SET; + 892 .loc 1 392 15 + 893 0018 0123 movs r3, #1 + 894 001a FB73 strb r3, [r7, #15] + 895 001c 01E0 b .L44 + 896 .L43: + 393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** else + 395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** bitstatus = GPIO_PIN_RESET; + 897 .loc 1 396 15 + 898 001e 0023 movs r3, #0 + 899 0020 FB73 strb r3, [r7, #15] + 900 .L44: + 397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** return bitstatus; + 901 .loc 1 398 10 + 902 0022 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 903 .loc 1 399 1 + 904 0024 1846 mov r0, r3 + 905 0026 1437 adds r7, r7, #20 + 906 .cfi_def_cfa_offset 4 + 907 0028 BD46 mov sp, r7 + 908 .cfi_def_cfa_register 13 + 909 @ sp needed + 910 002a 5DF8047B ldr r7, [sp], #4 + 911 .cfi_restore 7 + 912 .cfi_def_cfa_offset 0 + ARM GAS /tmp/cc63nak4.s page 24 + + + 913 002e 7047 bx lr + 914 .cfi_endproc + 915 .LFE132: + 917 .section .text.HAL_GPIO_WritePin,"ax",%progbits + 918 .align 1 + 919 .global HAL_GPIO_WritePin + 920 .syntax unified + 921 .thumb + 922 .thumb_func + 924 HAL_GPIO_WritePin: + 925 .LFB133: + 400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /** + 402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @brief Set or clear the selected data port bit. + 403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * + 404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify + 405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * accesses. In this way, there is no risk of an IRQ occurring between + 406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * the read and the modify access. + 407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * + 408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F3 family + 409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @param GPIO_Pin specifies the port bit to be written. + 410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * This parameter can be one of GPIO_PIN_x where x can be (0..15). + 411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @param PinState specifies the value to be written to the selected bit. + 412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * This parameter can be one of the GPIO_PinState enum values: + 413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @arg GPIO_PIN_RESET: to clear the port pin + 414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @arg GPIO_PIN_SET: to set the port pin + 415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @retval None + 416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** */ + 417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) + 418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 926 .loc 1 418 1 + 927 .cfi_startproc + 928 @ args = 0, pretend = 0, frame = 8 + 929 @ frame_needed = 1, uses_anonymous_args = 0 + 930 @ link register save eliminated. + 931 0000 80B4 push {r7} + 932 .cfi_def_cfa_offset 4 + 933 .cfi_offset 7, -4 + 934 0002 83B0 sub sp, sp, #12 + 935 .cfi_def_cfa_offset 16 + 936 0004 00AF add r7, sp, #0 + 937 .cfi_def_cfa_register 7 + 938 0006 7860 str r0, [r7, #4] + 939 0008 0B46 mov r3, r1 + 940 000a 7B80 strh r3, [r7, #2] @ movhi + 941 000c 1346 mov r3, r2 + 942 000e 7B70 strb r3, [r7, #1] + 419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Check the parameters */ + 420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** assert_param(IS_GPIO_PIN(GPIO_Pin)); + 421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** assert_param(IS_GPIO_PIN_ACTION(PinState)); + 422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** if(PinState != GPIO_PIN_RESET) + 943 .loc 1 423 5 + 944 0010 7B78 ldrb r3, [r7, #1] @ zero_extendqisi2 + 945 0012 002B cmp r3, #0 + 946 0014 03D0 beq .L47 + 424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + ARM GAS /tmp/cc63nak4.s page 25 + + + 425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** GPIOx->BSRR = (uint32_t)GPIO_Pin; + 947 .loc 1 425 19 + 948 0016 7A88 ldrh r2, [r7, #2] + 949 .loc 1 425 17 + 950 0018 7B68 ldr r3, [r7, #4] + 951 001a 9A61 str r2, [r3, #24] + 426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** else + 428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** GPIOx->BRR = (uint32_t)GPIO_Pin; + 430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 952 .loc 1 431 1 + 953 001c 02E0 b .L49 + 954 .L47: + 429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 955 .loc 1 429 18 + 956 001e 7A88 ldrh r2, [r7, #2] + 429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 957 .loc 1 429 16 + 958 0020 7B68 ldr r3, [r7, #4] + 959 0022 9A62 str r2, [r3, #40] + 960 .L49: + 961 .loc 1 431 1 + 962 0024 00BF nop + 963 0026 0C37 adds r7, r7, #12 + 964 .cfi_def_cfa_offset 4 + 965 0028 BD46 mov sp, r7 + 966 .cfi_def_cfa_register 13 + 967 @ sp needed + 968 002a 5DF8047B ldr r7, [sp], #4 + 969 .cfi_restore 7 + 970 .cfi_def_cfa_offset 0 + 971 002e 7047 bx lr + 972 .cfi_endproc + 973 .LFE133: + 975 .section .text.HAL_GPIO_TogglePin,"ax",%progbits + 976 .align 1 + 977 .global HAL_GPIO_TogglePin + 978 .syntax unified + 979 .thumb + 980 .thumb_func + 982 HAL_GPIO_TogglePin: + 983 .LFB134: + 432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /** + 434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @brief Toggle the specified GPIO pin. + 435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F3 family + 436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @param GPIO_Pin specifies the pin to be toggled. + 437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @retval None + 438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** */ + 439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) + 440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 984 .loc 1 440 1 + 985 .cfi_startproc + 986 @ args = 0, pretend = 0, frame = 16 + 987 @ frame_needed = 1, uses_anonymous_args = 0 + ARM GAS /tmp/cc63nak4.s page 26 + + + 988 @ link register save eliminated. + 989 0000 80B4 push {r7} + 990 .cfi_def_cfa_offset 4 + 991 .cfi_offset 7, -4 + 992 0002 85B0 sub sp, sp, #20 + 993 .cfi_def_cfa_offset 24 + 994 0004 00AF add r7, sp, #0 + 995 .cfi_def_cfa_register 7 + 996 0006 7860 str r0, [r7, #4] + 997 0008 0B46 mov r3, r1 + 998 000a 7B80 strh r3, [r7, #2] @ movhi + 441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** uint32_t odr; + 442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Check the parameters */ + 444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** assert_param(IS_GPIO_PIN(GPIO_Pin)); + 445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* get current Output Data Register value */ + 447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** odr = GPIOx->ODR; + 999 .loc 1 447 7 + 1000 000c 7B68 ldr r3, [r7, #4] + 1001 000e 5B69 ldr r3, [r3, #20] + 1002 0010 FB60 str r3, [r7, #12] + 448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Set selected pins that were at low level, and reset ones that were high */ + 450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); + 1003 .loc 1 450 23 + 1004 0012 7A88 ldrh r2, [r7, #2] + 1005 0014 FB68 ldr r3, [r7, #12] + 1006 0016 1340 ands r3, r3, r2 + 1007 .loc 1 450 35 + 1008 0018 1A04 lsls r2, r3, #16 + 1009 .loc 1 450 54 + 1010 001a FB68 ldr r3, [r7, #12] + 1011 001c D943 mvns r1, r3 + 1012 .loc 1 450 59 + 1013 001e 7B88 ldrh r3, [r7, #2] + 1014 0020 0B40 ands r3, r3, r1 + 1015 .loc 1 450 51 + 1016 0022 1A43 orrs r2, r2, r3 + 1017 .loc 1 450 15 + 1018 0024 7B68 ldr r3, [r7, #4] + 1019 0026 9A61 str r2, [r3, #24] + 451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 1020 .loc 1 451 1 + 1021 0028 00BF nop + 1022 002a 1437 adds r7, r7, #20 + 1023 .cfi_def_cfa_offset 4 + 1024 002c BD46 mov sp, r7 + 1025 .cfi_def_cfa_register 13 + 1026 @ sp needed + 1027 002e 5DF8047B ldr r7, [sp], #4 + 1028 .cfi_restore 7 + 1029 .cfi_def_cfa_offset 0 + 1030 0032 7047 bx lr + 1031 .cfi_endproc + 1032 .LFE134: + 1034 .section .text.HAL_GPIO_LockPin,"ax",%progbits + ARM GAS /tmp/cc63nak4.s page 27 + + + 1035 .align 1 + 1036 .global HAL_GPIO_LockPin + 1037 .syntax unified + 1038 .thumb + 1039 .thumb_func + 1041 HAL_GPIO_LockPin: + 1042 .LFB135: + 452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /** + 454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @brief Lock GPIO Pins configuration registers. + 455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, + 456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. + 457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @note The configuration of the locked GPIO pins can no longer be modified + 458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * until the next reset. + 459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F3 family + 460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @param GPIO_Pin specifies the port bits to be locked. + 461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + 462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @retval None + 463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** */ + 464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) + 465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 1043 .loc 1 465 1 + 1044 .cfi_startproc + 1045 @ args = 0, pretend = 0, frame = 16 + 1046 @ frame_needed = 1, uses_anonymous_args = 0 + 1047 @ link register save eliminated. + 1048 0000 80B4 push {r7} + 1049 .cfi_def_cfa_offset 4 + 1050 .cfi_offset 7, -4 + 1051 0002 85B0 sub sp, sp, #20 + 1052 .cfi_def_cfa_offset 24 + 1053 0004 00AF add r7, sp, #0 + 1054 .cfi_def_cfa_register 7 + 1055 0006 7860 str r0, [r7, #4] + 1056 0008 0B46 mov r3, r1 + 1057 000a 7B80 strh r3, [r7, #2] @ movhi + 466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** __IO uint32_t tmp = GPIO_LCKR_LCKK; + 1058 .loc 1 466 17 + 1059 000c 4FF48033 mov r3, #65536 + 1060 0010 FB60 str r3, [r7, #12] + 467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Check the parameters */ + 469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx)); + 470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** assert_param(IS_GPIO_PIN(GPIO_Pin)); + 471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Apply lock key write sequence */ + 473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** tmp |= GPIO_Pin; + 1061 .loc 1 473 7 + 1062 0012 7A88 ldrh r2, [r7, #2] + 1063 0014 FB68 ldr r3, [r7, #12] + 1064 0016 1343 orrs r3, r3, r2 + 1065 0018 FB60 str r3, [r7, #12] + 474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Set LCKx bit(s): LCKK='1' + LCK[15U-0] */ + 475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** GPIOx->LCKR = tmp; + 1066 .loc 1 475 15 + 1067 001a FA68 ldr r2, [r7, #12] + 1068 001c 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/cc63nak4.s page 28 + + + 1069 001e DA61 str r2, [r3, #28] + 476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Reset LCKx bit(s): LCKK='0' + LCK[15U-0] */ + 477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** GPIOx->LCKR = GPIO_Pin; + 1070 .loc 1 477 15 + 1071 0020 7A88 ldrh r2, [r7, #2] + 1072 0022 7B68 ldr r3, [r7, #4] + 1073 0024 DA61 str r2, [r3, #28] + 478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Set LCKx bit(s): LCKK='1' + LCK[15U-0] */ + 479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** GPIOx->LCKR = tmp; + 1074 .loc 1 479 15 + 1075 0026 FA68 ldr r2, [r7, #12] + 1076 0028 7B68 ldr r3, [r7, #4] + 1077 002a DA61 str r2, [r3, #28] + 480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Read LCKK register. This read is mandatory to complete key lock sequence */ + 481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** tmp = GPIOx->LCKR; + 1078 .loc 1 481 14 + 1079 002c 7B68 ldr r3, [r7, #4] + 1080 002e DB69 ldr r3, [r3, #28] + 1081 .loc 1 481 7 + 1082 0030 FB60 str r3, [r7, #12] + 482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* read again in order to confirm lock is active */ + 484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** if((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00u) + 1083 .loc 1 484 11 + 1084 0032 7B68 ldr r3, [r7, #4] + 1085 0034 DB69 ldr r3, [r3, #28] + 1086 .loc 1 484 18 + 1087 0036 03F48033 and r3, r3, #65536 + 1088 .loc 1 484 4 + 1089 003a 002B cmp r3, #0 + 1090 003c 01D0 beq .L52 + 485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** return HAL_OK; + 1091 .loc 1 486 12 + 1092 003e 0023 movs r3, #0 + 1093 0040 00E0 b .L53 + 1094 .L52: + 487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** else + 489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** return HAL_ERROR; + 1095 .loc 1 490 12 + 1096 0042 0123 movs r3, #1 + 1097 .L53: + 491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 1098 .loc 1 492 1 + 1099 0044 1846 mov r0, r3 + 1100 0046 1437 adds r7, r7, #20 + 1101 .cfi_def_cfa_offset 4 + 1102 0048 BD46 mov sp, r7 + 1103 .cfi_def_cfa_register 13 + 1104 @ sp needed + 1105 004a 5DF8047B ldr r7, [sp], #4 + 1106 .cfi_restore 7 + 1107 .cfi_def_cfa_offset 0 + 1108 004e 7047 bx lr + ARM GAS /tmp/cc63nak4.s page 29 + + + 1109 .cfi_endproc + 1110 .LFE135: + 1112 .section .text.HAL_GPIO_EXTI_IRQHandler,"ax",%progbits + 1113 .align 1 + 1114 .global HAL_GPIO_EXTI_IRQHandler + 1115 .syntax unified + 1116 .thumb + 1117 .thumb_func + 1119 HAL_GPIO_EXTI_IRQHandler: + 1120 .LFB136: + 493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /** + 495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @brief Handle EXTI interrupt request. + 496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. + 497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @retval None + 498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** */ + 499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) + 500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 1121 .loc 1 500 1 + 1122 .cfi_startproc + 1123 @ args = 0, pretend = 0, frame = 8 + 1124 @ frame_needed = 1, uses_anonymous_args = 0 + 1125 0000 80B5 push {r7, lr} + 1126 .cfi_def_cfa_offset 8 + 1127 .cfi_offset 7, -8 + 1128 .cfi_offset 14, -4 + 1129 0002 82B0 sub sp, sp, #8 + 1130 .cfi_def_cfa_offset 16 + 1131 0004 00AF add r7, sp, #0 + 1132 .cfi_def_cfa_register 7 + 1133 0006 0346 mov r3, r0 + 1134 0008 FB80 strh r3, [r7, #6] @ movhi + 501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* EXTI line interrupt detected */ + 502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u) + 1135 .loc 1 502 6 + 1136 000a 084B ldr r3, .L57 + 1137 000c 5A69 ldr r2, [r3, #20] + 1138 000e FB88 ldrh r3, [r7, #6] + 1139 0010 1340 ands r3, r3, r2 + 1140 .loc 1 502 5 + 1141 0012 002B cmp r3, #0 + 1142 0014 06D0 beq .L56 + 503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); + 1143 .loc 1 504 5 + 1144 0016 054A ldr r2, .L57 + 1145 0018 FB88 ldrh r3, [r7, #6] + 1146 001a 5361 str r3, [r2, #20] + 505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** HAL_GPIO_EXTI_Callback(GPIO_Pin); + 1147 .loc 1 505 5 + 1148 001c FB88 ldrh r3, [r7, #6] + 1149 001e 1846 mov r0, r3 + 1150 0020 FFF7FEFF bl HAL_GPIO_EXTI_Callback + 1151 .L56: + 506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 1152 .loc 1 507 1 + ARM GAS /tmp/cc63nak4.s page 30 + + + 1153 0024 00BF nop + 1154 0026 0837 adds r7, r7, #8 + 1155 .cfi_def_cfa_offset 8 + 1156 0028 BD46 mov sp, r7 + 1157 .cfi_def_cfa_register 13 + 1158 @ sp needed + 1159 002a 80BD pop {r7, pc} + 1160 .L58: + 1161 .align 2 + 1162 .L57: + 1163 002c 00040140 .word 1073808384 + 1164 .cfi_endproc + 1165 .LFE136: + 1167 .section .text.HAL_GPIO_EXTI_Callback,"ax",%progbits + 1168 .align 1 + 1169 .weak HAL_GPIO_EXTI_Callback + 1170 .syntax unified + 1171 .thumb + 1172 .thumb_func + 1174 HAL_GPIO_EXTI_Callback: + 1175 .LFB137: + 508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /** + 510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @brief EXTI line detection callback. + 511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. + 512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** * @retval None + 513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** */ + 514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) + 515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** { + 1176 .loc 1 515 1 + 1177 .cfi_startproc + 1178 @ args = 0, pretend = 0, frame = 8 + 1179 @ frame_needed = 1, uses_anonymous_args = 0 + 1180 @ link register save eliminated. + 1181 0000 80B4 push {r7} + 1182 .cfi_def_cfa_offset 4 + 1183 .cfi_offset 7, -4 + 1184 0002 83B0 sub sp, sp, #12 + 1185 .cfi_def_cfa_offset 16 + 1186 0004 00AF add r7, sp, #0 + 1187 .cfi_def_cfa_register 7 + 1188 0006 0346 mov r3, r0 + 1189 0008 FB80 strh r3, [r7, #6] @ movhi + 516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* Prevent unused argument(s) compilation warning */ + 517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** UNUSED(GPIO_Pin); + 518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** + 519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** /* NOTE: This function should not be modified, when the callback is needed, + 520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** the HAL_GPIO_EXTI_Callback could be implemented in the user file + 521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** */ + 522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_gpio.c **** } + 1190 .loc 1 522 1 + 1191 000a 00BF nop + 1192 000c 0C37 adds r7, r7, #12 + 1193 .cfi_def_cfa_offset 4 + 1194 000e BD46 mov sp, r7 + 1195 .cfi_def_cfa_register 13 + 1196 @ sp needed + ARM GAS /tmp/cc63nak4.s page 31 + + + 1197 0010 5DF8047B ldr r7, [sp], #4 + 1198 .cfi_restore 7 + 1199 .cfi_def_cfa_offset 0 + 1200 0014 7047 bx lr + 1201 .cfi_endproc + 1202 .LFE137: + 1204 .text + 1205 .Letext0: + 1206 .file 2 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 1207 .file 3 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 1208 .file 4 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + 1209 .file 5 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h" + 1210 .file 6 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h" + ARM GAS /tmp/cc63nak4.s page 32 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f3xx_hal_gpio.c + /tmp/cc63nak4.s:21 .text.HAL_GPIO_Init:00000000 $t + /tmp/cc63nak4.s:27 .text.HAL_GPIO_Init:00000000 HAL_GPIO_Init + /tmp/cc63nak4.s:537 .text.HAL_GPIO_Init:000002d8 $d + /tmp/cc63nak4.s:548 .text.HAL_GPIO_DeInit:00000000 $t + /tmp/cc63nak4.s:554 .text.HAL_GPIO_DeInit:00000000 HAL_GPIO_DeInit + /tmp/cc63nak4.s:850 .text.HAL_GPIO_DeInit:000001a0 $d + /tmp/cc63nak4.s:860 .text.HAL_GPIO_ReadPin:00000000 $t + /tmp/cc63nak4.s:866 .text.HAL_GPIO_ReadPin:00000000 HAL_GPIO_ReadPin + /tmp/cc63nak4.s:918 .text.HAL_GPIO_WritePin:00000000 $t + /tmp/cc63nak4.s:924 .text.HAL_GPIO_WritePin:00000000 HAL_GPIO_WritePin + /tmp/cc63nak4.s:976 .text.HAL_GPIO_TogglePin:00000000 $t + /tmp/cc63nak4.s:982 .text.HAL_GPIO_TogglePin:00000000 HAL_GPIO_TogglePin + /tmp/cc63nak4.s:1035 .text.HAL_GPIO_LockPin:00000000 $t + /tmp/cc63nak4.s:1041 .text.HAL_GPIO_LockPin:00000000 HAL_GPIO_LockPin + /tmp/cc63nak4.s:1113 .text.HAL_GPIO_EXTI_IRQHandler:00000000 $t + /tmp/cc63nak4.s:1119 .text.HAL_GPIO_EXTI_IRQHandler:00000000 HAL_GPIO_EXTI_IRQHandler + /tmp/cc63nak4.s:1174 .text.HAL_GPIO_EXTI_Callback:00000000 HAL_GPIO_EXTI_Callback + /tmp/cc63nak4.s:1163 .text.HAL_GPIO_EXTI_IRQHandler:0000002c $d + /tmp/cc63nak4.s:1168 .text.HAL_GPIO_EXTI_Callback:00000000 $t + +NO UNDEFINED SYMBOLS diff --git a/Software/build/stm32f3xx_hal_gpio.o b/Software/build/stm32f3xx_hal_gpio.o new file mode 100644 index 0000000..92a88d9 Binary files /dev/null and b/Software/build/stm32f3xx_hal_gpio.o differ diff --git a/Software/build/stm32f3xx_hal_i2c.d b/Software/build/stm32f3xx_hal_i2c.d new file mode 100644 index 0000000..edab4bc --- /dev/null +++ b/Software/build/stm32f3xx_hal_i2c.d @@ -0,0 +1,62 @@ +build/stm32f3xx_hal_i2c.o: \ + Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + Core/Inc/stm32f3xx_hal_conf.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h: diff --git a/Software/build/stm32f3xx_hal_i2c.lst b/Software/build/stm32f3xx_hal_i2c.lst new file mode 100644 index 0000000..e58a3a3 --- /dev/null +++ b/Software/build/stm32f3xx_hal_i2c.lst @@ -0,0 +1,23904 @@ +ARM GAS /tmp/cc5G5cqz.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 6 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "stm32f3xx_hal_i2c.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c" + 20 .section .text.HAL_I2C_Init,"ax",%progbits + 21 .align 1 + 22 .global HAL_I2C_Init + 23 .syntax unified + 24 .thumb + 25 .thumb_func + 27 HAL_I2C_Init: + 28 .LFB130: + 1:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** + 2:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** ****************************************************************************** + 3:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @file stm32f3xx_hal_i2c.c + 4:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @author MCD Application Team + 5:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief I2C HAL module driver. + 6:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * functionalities of the Inter Integrated Circuit (I2C) peripheral: + 8:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * + Initialization and de-initialization functions + 9:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * + IO operation functions + 10:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * + Peripheral State and Errors functions + 11:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * + 12:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** ****************************************************************************** + 13:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @attention + 14:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * + 15:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * Copyright (c) 2016 STMicroelectronics. + 16:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * All rights reserved. + 17:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * + 18:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * This software is licensed under terms that can be found in the LICENSE file + 19:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * in the root directory of this software component. + 20:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 21:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * + 22:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** ****************************************************************************** + 23:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** @verbatim + 24:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** ============================================================================== + 25:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** ##### How to use this driver ##### + 26:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** ============================================================================== + 27:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** [..] + 28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** The I2C HAL driver can be used as follows: + 29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (#) Declare a I2C_HandleTypeDef handle structure, for example: + ARM GAS /tmp/cc5G5cqz.s page 2 + + + 31:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_HandleTypeDef hi2c; + 32:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 33:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API: + 34:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (##) Enable the I2Cx interface clock + 35:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (##) I2C pins configuration + 36:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+++) Enable the clock for the I2C GPIOs + 37:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+++) Configure I2C pins as alternate function open-drain + 38:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (##) NVIC configuration if you need to use interrupt process + 39:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+++) Configure the I2Cx interrupt priority + 40:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+++) Enable the NVIC I2C IRQ Channel + 41:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (##) DMA Configuration if you need to use DMA process + 42:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+++) Declare a DMA_HandleTypeDef handle structure for + 43:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** the transmit or receive channel + 44:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+++) Enable the DMAx interface clock using + 45:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+++) Configure the DMA handle parameters + 46:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+++) Configure the DMA Tx or Rx channel + 47:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle + 48:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on + 49:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** the DMA Tx or Rx channel + 50:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 51:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addres + 52:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure + 53:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 54:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level H + 55:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API. + 56:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 57:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceRead + 58:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 59:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : + 60:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 61:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** *** Polling mode IO operation *** + 62:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** ================================= + 63:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** [..] + 64:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit( + 65:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive() + 66:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit() + 67:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive() + 68:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 69:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** *** Polling mode IO MEM operation *** + 70:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** ===================================== + 71:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** [..] + 72:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_W + 73:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_ + 74:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 75:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 76:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** *** Interrupt mode IO operation *** + 77:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** =================================== + 78:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** [..] + 79:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Trans + 80:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can + 81:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + 82:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receiv + 83:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can + 84:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + 85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmi + 86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can + 87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + ARM GAS /tmp/cc5G5cqz.s page 3 + + + 88:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_ + 89:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can + 90:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + 91:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + 92:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_ErrorCallback() + 93:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + 94:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can + 95:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() + 96:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + 97:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** This action will inform Master to generate a Stop condition to discard the communication + 98:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 99:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** *** Interrupt mode or DMA mode IO sequential operation *** + 101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** ========================================================== + 102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** [..] + 103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (@) These interfaces allow to manage a sequential transfer with a repeated start condition + 104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** when a direction change during transfer + 105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** [..] + 106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) A specific option field manage the different steps of a sequential transfer + 107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Option field values are defined through I2C_XFEROPTIONS and are listed below: + 108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfac + 109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** no sequential mode + 110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start con + 111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** and data to transfer without a final stop condition + 112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a + 113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** start condition, address and data to transfer without a final stop cond + 114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** an then permit a call the same master sequential interface several time + 115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit + 116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_D + 117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart + 118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** and with new data to transfer if the direction change or manage only th + 119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** transfer + 120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if no direction change and without a final stop condition in both cases + 121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart + 122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** and with new data to transfer if the direction change or manage only th + 123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** transfer + 124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if no direction change and with a final stop condition in both cases + 125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a re + 126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** after several call of the same master sequential interface several time + 127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (link with option I2C_FIRST_AND_NEXT_FRAME). + 128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** Usage can, transfer several bytes one by one using + 129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_Master_Seq_Transmit_IT + 130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** or HAL_I2C_Master_Seq_Receive_IT + 131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** or HAL_I2C_Master_Seq_Transmit_DMA + 132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** or HAL_I2C_Master_Seq_Receive_DMA + 133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** with option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME. + 134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit + 135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** Receive sequence permit to call the opposite interface Receive or Tra + 136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** without stopping the communication and so generate a restart conditio + 137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart c + 138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** each call of the same master sequential + 139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** interface. + 140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** Usage can, transfer several bytes one by one with a restart with slave + 141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** each bytes using + 142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_Master_Seq_Transmit_IT + 143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** or HAL_I2C_Master_Seq_Receive_IT + 144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** or HAL_I2C_Master_Seq_Transmit_DMA + ARM GAS /tmp/cc5G5cqz.s page 4 + + + 145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** or HAL_I2C_Master_Seq_Receive_DMA + 146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** with option I2C_FIRST_FRAME then I2C_OTHER_FRAME. + 147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to + 148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** generation of STOP condition. + 149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Different sequential I2C interfaces are listed below: + 151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using + 152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_Master_Seq_Transmit_IT() or using HAL_I2C_Master_Seq_Transmit_DMA() + 153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is execut + 154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** users can add their own code by customization of function pointer HAL_I2C_MasterTxCpltC + 155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using + 156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA() + 157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed + 158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + 159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_A + 160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can + 161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() + 162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() + 163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_DisableListen_IT() + 164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and users can + 165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** add their own code to check the Address Match Code and the transmission direction reques + 166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (Write/Read). + 167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and users can + 168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_ListenCpltCallback() + 169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using + 170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_Slave_Seq_Transmit_IT() or using HAL_I2C_Slave_Seq_Transmit_DMA() + 171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is execute + 172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** users can add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCa + 173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using + 174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_Slave_Seq_Receive_IT() or using HAL_I2C_Slave_Seq_Receive_DMA() + 175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed a + 176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + 177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + 178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_ErrorCallback() + 179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + 180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** This action will inform Master to generate a Stop condition to discard the communication + 181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** *** Interrupt mode IO MEM operation *** + 183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** ======================================= + 184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** [..] + 185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address + 186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_Mem_Write_IT() + 187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can + 188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback() + 189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address + 190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_Mem_Read_IT() + 191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can + 192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback() + 193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + 194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_ErrorCallback() + 195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** *** DMA mode IO operation *** + 197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** ============================== + 198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** [..] + 199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using + 200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_Master_Transmit_DMA() + 201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can + ARM GAS /tmp/cc5G5cqz.s page 5 + + + 202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + 203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Receive in master mode an amount of data in non-blocking mode (DMA) using + 204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_Master_Receive_DMA() + 205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can + 206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + 207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using + 208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_Slave_Transmit_DMA() + 209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can + 210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + 211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using + 212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_Slave_Receive_DMA() + 213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can + 214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + 215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + 216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_ErrorCallback() + 217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + 218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can + 219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() + 220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + 221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** This action will inform Master to generate a Stop condition to discard the communication + 222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** *** DMA mode IO MEM operation *** + 224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** ================================= + 225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** [..] + 226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using + 227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_Mem_Write_DMA() + 228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can + 229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback() + 230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using + 231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_Mem_Read_DMA() + 232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can + 233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback() + 234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + 235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** add their own code by customization of function pointer HAL_I2C_ErrorCallback() + 236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** *** I2C HAL driver macros list *** + 239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** ================================== + 240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** [..] + 241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** Below the list of most used macros in I2C HAL driver. + 242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) __HAL_I2C_ENABLE: Enable the I2C peripheral + 244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) __HAL_I2C_DISABLE: Disable the I2C peripheral + 245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode + 246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not + 247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag + 248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt + 249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt + 250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** *** Callback registration *** + 252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** ============================================= + 253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** [..] + 254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1 + 255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** allows the user to configure dynamically the driver callbacks. + 256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback() + 257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to register an interrupt callback. + 258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** [..] + ARM GAS /tmp/cc5G5cqz.s page 6 + + + 259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** Function HAL_I2C_RegisterCallback() allows to register following callbacks: + 260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + 261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) MasterRxCpltCallback : callback for Master reception end of transfer. + 262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + 263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + 264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) ListenCpltCallback : callback for end of listen mode. + 265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) MemTxCpltCallback : callback for Memory transmission end of transfer. + 266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) MemRxCpltCallback : callback for Memory reception end of transfer. + 267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) ErrorCallback : callback for error detection. + 268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) AbortCpltCallback : callback for abort completion process. + 269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) MspInitCallback : callback for Msp Init. + 270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) MspDeInitCallback : callback for Msp DeInit. + 271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** This function takes as parameters the HAL peripheral handle, the Callback ID + 272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** and a pointer to the user callback function. + 273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** [..] + 274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCall + 275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** [..] + 276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** Use function HAL_I2C_UnRegisterCallback to reset a callback to the default + 277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** weak function. + 278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle, + 279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** and the Callback ID. + 280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** This function allows to reset following callbacks: + 281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + 282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) MasterRxCpltCallback : callback for Master reception end of transfer. + 283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + 284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + 285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) ListenCpltCallback : callback for end of listen mode. + 286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) MemTxCpltCallback : callback for Memory transmission end of transfer. + 287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) MemRxCpltCallback : callback for Memory reception end of transfer. + 288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) ErrorCallback : callback for error detection. + 289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) AbortCpltCallback : callback for abort completion process. + 290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) MspInitCallback : callback for Msp Init. + 291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) MspDeInitCallback : callback for Msp DeInit. + 292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** [..] + 293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback(). + 294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** [..] + 295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET + 296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** all callbacks are set to the corresponding weak functions: + 297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback(). + 298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** Exception done for MspInit and MspDeInit functions that are + 299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when + 300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** these callbacks are null (not registered beforehand). + 301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit() + 302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + 303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** [..] + 304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only. + 305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** Exception done MspInit/MspDeInit functions that can be registered/unregistered + 306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state, + 307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + 308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** Then, the user first registers the MspInit/MspDeInit user callbacks + 309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit() + 310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** or HAL_I2C_Init() function. + 311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** [..] + 312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or + 313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** not defined, the callback registration feature is not available and all callbacks + 314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** are set to the corresponding weak functions. + 315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/cc5G5cqz.s page 7 + + + 316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** [..] + 317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (@) You can refer to the I2C HAL driver header file for more useful macros + 318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** @endverbatim + 320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ + 321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Includes ------------------------------------------------------------------*/ + 323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #include "stm32f3xx_hal.h" + 324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** @addtogroup STM32F3xx_HAL_Driver + 326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @{ + 327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ + 328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** @defgroup I2C I2C + 330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief I2C HAL module driver + 331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @{ + 332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ + 333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #ifdef HAL_I2C_MODULE_ENABLED + 335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Private typedef -----------------------------------------------------------*/ + 337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Private define ------------------------------------------------------------*/ + 338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** @defgroup I2C_Private_Define I2C Private Define + 340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @{ + 341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ + 342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */ + 343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */ + 344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */ + 345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */ + 346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */ + 347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */ + 348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define I2C_TIMEOUT_TC (25U) /*!< 25 ms */ + 349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */ + 350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */ + 351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */ + 352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define MAX_NBYTE_SIZE 255U + 354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define SLAVE_ADDR_SHIFT 7U + 355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define SLAVE_ADDR_MSK 0x06U + 356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Private define for @ref PreviousState usage */ + 358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \ + 359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (uint32_t)HAL_I2C_STATE_BUSY_RX) & \ + 360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) + 361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /*!< Mask State define, keep only RX and TX bits */ + 362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) + 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /*!< Default Value */ + 364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + 365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (uint32_t)HAL_I2C_MODE_MASTER)) + 366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /*!< Master Busy TX, combinaison of State LSB and Mode enum */ + 367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + 368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (uint32_t)HAL_I2C_MODE_MASTER)) + 369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /*!< Master Busy RX, combinaison of State LSB and Mode enum */ + 370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + 371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (uint32_t)HAL_I2C_MODE_SLAVE)) + 372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /*!< Slave Busy TX, combinaison of State LSB and Mode enum */ + ARM GAS /tmp/cc5G5cqz.s page 8 + + + 373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + 374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (uint32_t)HAL_I2C_MODE_SLAVE)) + 375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /*!< Slave Busy RX, combinaison of State LSB and Mode enum */ + 376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + 377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (uint32_t)HAL_I2C_MODE_MEM)) + 378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /*!< Memory Busy TX, combinaison of State LSB and Mode enum */ + 379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + 380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (uint32_t)HAL_I2C_MODE_MEM)) + 381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /*!< Memory Busy RX, combinaison of State LSB and Mode enum */ + 382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Private define to centralize the enable/disable of Interrupts */ + 385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define I2C_XFER_TX_IT (uint16_t)(0x0001U) /*!< Bit field can be combinated with + 386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** @ref I2C_XFER_LISTEN_IT */ + 387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define I2C_XFER_RX_IT (uint16_t)(0x0002U) /*!< Bit field can be combinated with + 388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** @ref I2C_XFER_LISTEN_IT */ + 389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /*!< Bit field can be combinated with @ref I2 + 390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** and @ref I2C_XFER_RX_IT */ + 391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /*!< Bit definition to manage addition of glo + 393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** and NACK treatment */ + 394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /*!< Bit definition to manage only STOP evene + 395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /*!< Bit definition to manage only Reload of + 396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Private define Sequential Transfer Options default/reset value */ + 398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define I2C_NO_OPTION_FRAME (0xFFFF0000U) + 399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** + 400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @} + 401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ + 402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Private macros ------------------------------------------------------------*/ + 404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** @addtogroup I2C_Private_Macro + 405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @{ + 406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ + 407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Macro to get remaining data to transfer on DMA side */ + 408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) __HAL_DMA_GET_COUNTER(__HANDLE__) + 409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** + 410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @} + 411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ + 412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Private variables ---------------------------------------------------------*/ + 414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Private function prototypes -----------------------------------------------*/ + 415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** @defgroup I2C_Private_Functions I2C Private Functions + 417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @{ + 418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ + 419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Private functions to handle DMA transfer */ + 420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma); + 421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma); + 422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma); + 423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma); + 424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_DMAError(DMA_HandleTypeDef *hdma); + 425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); + 426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Private functions to handle IT transfer */ + 429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); + ARM GAS /tmp/cc5G5cqz.s page 9 + + + 430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c); + 431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c); + 432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); + 433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); + 434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); + 435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode); + 436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Private functions to handle IT transfer */ + 438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + 439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t MemAddress, uint16_t MemAddSize, uint32_t + 440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t Tickstart); + 441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + 442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t MemAddress, uint16_t MemAddSize, uint32_t T + 443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t Tickstart); + 444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Private functions for I2C transfer IRQ handler */ + 446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + 447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t ITSources); + 448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + 449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t ITSources); + 450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + 451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t ITSources); + 452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + 453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t ITSources); + 454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + 455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t ITSources); + 456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + 457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t ITSources); + 458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Private functions to handle flags during polling transfer */ + 460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagSta + 461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t Timeout, uint32_t Tickstart); + 462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + 463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t Tickstart); + 464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + 465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t Tickstart); + 466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + 467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t Tickstart); + 468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + 469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t Tickstart); + 470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Private functions to centralize the enable/disable of Interrupts */ + 472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); + 473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); + 474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Private function to treat different error callback */ + 476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c); + 477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Private function to flush TXDR register */ + 479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c); + 480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Private function to handle start, restart or stop a transfer */ + 482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t + 483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t Request); + 484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Private function to Convert Specific options */ + 486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c); + ARM GAS /tmp/cc5G5cqz.s page 10 + + + 487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** + 488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @} + 489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ + 490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Exported functions --------------------------------------------------------*/ + 492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** @defgroup I2C_Exported_Functions I2C Exported Functions + 494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @{ + 495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ + 496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions + 498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Initialization and Configuration functions + 499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * + 500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** @verbatim + 501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** =============================================================================== + 502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** ##### Initialization and de-initialization functions ##### + 503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** =============================================================================== + 504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** [..] This subsection provides a set of functions allowing to initialize and + 505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** deinitialize the I2Cx peripheral: + 506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) User must Implement HAL_I2C_MspInit() function in which he configures + 508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + 509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Call the function HAL_I2C_Init() to configure the selected device with + 511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** the selected configuration: + 512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) Clock Timing + 513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) Own Address 1 + 514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) Addressing mode (Master, Slave) + 515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) Dual Addressing mode + 516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) Own Address 2 + 517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) Own Address 2 Mask + 518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) General call mode + 519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) Nostretch mode + 520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (+) Call the function HAL_I2C_DeInit() to restore the default configuration + 522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** of the selected I2Cx peripheral. + 523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** @endverbatim + 525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @{ + 526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ + 527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** + 529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Initializes the I2C according to the specified parameters + 530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * in the I2C_InitTypeDef and initialize the associated handle. + 531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. + 533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status + 534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ + 535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) + 536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 29 .loc 1 536 1 + 30 .cfi_startproc + 31 @ args = 0, pretend = 0, frame = 8 + 32 @ frame_needed = 1, uses_anonymous_args = 0 + 33 0000 80B5 push {r7, lr} + 34 .cfi_def_cfa_offset 8 + 35 .cfi_offset 7, -8 + ARM GAS /tmp/cc5G5cqz.s page 11 + + + 36 .cfi_offset 14, -4 + 37 0002 82B0 sub sp, sp, #8 + 38 .cfi_def_cfa_offset 16 + 39 0004 00AF add r7, sp, #0 + 40 .cfi_def_cfa_register 7 + 41 0006 7860 str r0, [r7, #4] + 537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check the I2C handle allocation */ + 538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c == NULL) + 42 .loc 1 538 6 + 43 0008 7B68 ldr r3, [r7, #4] + 44 000a 002B cmp r3, #0 + 45 000c 01D1 bne .L2 + 539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 46 .loc 1 540 12 + 47 000e 0123 movs r3, #1 + 48 0010 81E0 b .L3 + 49 .L2: + 541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check the parameters */ + 544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + 545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); + 546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); + 547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); + 548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); + 549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks)); + 550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); + 551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); + 552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_RESET) + 50 .loc 1 553 11 + 51 0012 7B68 ldr r3, [r7, #4] + 52 0014 93F84130 ldrb r3, [r3, #65] + 53 0018 DBB2 uxtb r3, r3 + 54 .loc 1 553 6 + 55 001a 002B cmp r3, #0 + 56 001c 06D1 bne .L4 + 554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Allocate lock resource and initialize it */ + 556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Lock = HAL_UNLOCKED; + 57 .loc 1 556 16 + 58 001e 7B68 ldr r3, [r7, #4] + 59 0020 0022 movs r2, #0 + 60 0022 83F84020 strb r2, [r3, #64] + 557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + 559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Init the I2C Callback settings */ + 560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback + 561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback + 562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback + 563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback + 564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback + 565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback + 566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback + 567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback + 568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback + ARM GAS /tmp/cc5G5cqz.s page 12 + + + 569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback + 570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->MspInitCallback == NULL) + 572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + 574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + 577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MspInitCallback(hi2c); + 578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #else + 579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + 580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_MspInit(hi2c); + 61 .loc 1 580 5 + 62 0026 7868 ldr r0, [r7, #4] + 63 0028 FFF7FEFF bl HAL_I2C_MspInit + 64 .L4: + 581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY; + 65 .loc 1 584 15 + 66 002c 7B68 ldr r3, [r7, #4] + 67 002e 2422 movs r2, #36 + 68 0030 83F84120 strb r2, [r3, #65] + 585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable the selected I2C peripheral */ + 587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_DISABLE(hi2c); + 69 .loc 1 587 3 + 70 0034 7B68 ldr r3, [r7, #4] + 71 0036 1B68 ldr r3, [r3] + 72 0038 1A68 ldr r2, [r3] + 73 003a 7B68 ldr r3, [r7, #4] + 74 003c 1B68 ldr r3, [r3] + 75 003e 22F00102 bic r2, r2, #1 + 76 0042 1A60 str r2, [r3] + 588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /*---------------------------- I2Cx TIMINGR Configuration ------------------*/ + 590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Configure I2Cx: Frequency range */ + 591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK; + 77 .loc 1 591 39 + 78 0044 7B68 ldr r3, [r7, #4] + 79 0046 5A68 ldr r2, [r3, #4] + 80 .loc 1 591 7 + 81 0048 7B68 ldr r3, [r7, #4] + 82 004a 1B68 ldr r3, [r3] + 83 .loc 1 591 47 + 84 004c 22F07062 bic r2, r2, #251658240 + 85 .loc 1 591 27 + 86 0050 1A61 str r2, [r3, #16] + 592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ + 594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Own Address1 before set the Own Address1 configuration */ + 595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; + 87 .loc 1 595 7 + 88 0052 7B68 ldr r3, [r7, #4] + 89 0054 1B68 ldr r3, [r3] + 90 .loc 1 595 17 + ARM GAS /tmp/cc5G5cqz.s page 13 + + + 91 0056 9A68 ldr r2, [r3, #8] + 92 .loc 1 595 7 + 93 0058 7B68 ldr r3, [r7, #4] + 94 005a 1B68 ldr r3, [r3] + 95 .loc 1 595 24 + 96 005c 22F40042 bic r2, r2, #32768 + 97 0060 9A60 str r2, [r3, #8] + 596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Configure I2Cx: Own Address1 and ack own address1 mode */ + 598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + 98 .loc 1 598 17 + 99 0062 7B68 ldr r3, [r7, #4] + 100 0064 DB68 ldr r3, [r3, #12] + 101 .loc 1 598 6 + 102 0066 012B cmp r3, #1 + 103 0068 07D1 bne .L5 + 599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); + 104 .loc 1 600 56 + 105 006a 7B68 ldr r3, [r7, #4] + 106 006c 9A68 ldr r2, [r3, #8] + 107 .loc 1 600 9 + 108 006e 7B68 ldr r3, [r7, #4] + 109 0070 1B68 ldr r3, [r3] + 110 .loc 1 600 44 + 111 0072 42F40042 orr r2, r2, #32768 + 112 .loc 1 600 26 + 113 0076 9A60 str r2, [r3, #8] + 114 0078 06E0 b .L6 + 115 .L5: + 601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 602:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else /* I2C_ADDRESSINGMODE_10BIT */ + 603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1); + 116 .loc 1 604 75 + 117 007a 7B68 ldr r3, [r7, #4] + 118 007c 9A68 ldr r2, [r3, #8] + 119 .loc 1 604 9 + 120 007e 7B68 ldr r3, [r7, #4] + 121 0080 1B68 ldr r3, [r3] + 122 .loc 1 604 63 + 123 0082 42F40442 orr r2, r2, #33792 + 124 .loc 1 604 26 + 125 0086 9A60 str r2, [r3, #8] + 126 .L6: + 605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /*---------------------------- I2Cx CR2 Configuration ----------------------*/ + 608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Configure I2Cx: Addressing Master mode */ + 609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + 127 .loc 1 609 17 + 128 0088 7B68 ldr r3, [r7, #4] + 129 008a DB68 ldr r3, [r3, #12] + 130 .loc 1 609 6 + 131 008c 022B cmp r3, #2 + 132 008e 04D1 bne .L7 + 610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + ARM GAS /tmp/cc5G5cqz.s page 14 + + + 611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 = (I2C_CR2_ADD10); + 133 .loc 1 611 9 + 134 0090 7B68 ldr r3, [r7, #4] + 135 0092 1B68 ldr r3, [r3] + 136 .loc 1 611 25 + 137 0094 4FF40062 mov r2, #2048 + 138 0098 5A60 str r2, [r3, #4] + 139 .L7: + 612:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ + 614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); + 140 .loc 1 614 7 + 141 009a 7B68 ldr r3, [r7, #4] + 142 009c 1B68 ldr r3, [r3] + 143 .loc 1 614 17 + 144 009e 5B68 ldr r3, [r3, #4] + 145 .loc 1 614 7 + 146 00a0 7A68 ldr r2, [r7, #4] + 147 00a2 1268 ldr r2, [r2] + 148 .loc 1 614 23 + 149 00a4 43F00073 orr r3, r3, #33554432 + 150 00a8 43F40043 orr r3, r3, #32768 + 151 00ac 5360 str r3, [r2, #4] + 615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ + 617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Own Address2 before set the Own Address2 configuration */ + 618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; + 152 .loc 1 618 7 + 153 00ae 7B68 ldr r3, [r7, #4] + 154 00b0 1B68 ldr r3, [r3] + 155 .loc 1 618 17 + 156 00b2 DA68 ldr r2, [r3, #12] + 157 .loc 1 618 7 + 158 00b4 7B68 ldr r3, [r7, #4] + 159 00b6 1B68 ldr r3, [r3] + 160 .loc 1 618 24 + 161 00b8 22F40042 bic r2, r2, #32768 + 162 00bc DA60 str r2, [r3, #12] + 619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Configure I2Cx: Dual mode and Own Address2 */ + 621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \ + 163 .loc 1 621 37 + 164 00be 7B68 ldr r3, [r7, #4] + 165 00c0 1A69 ldr r2, [r3, #16] + 166 .loc 1 621 66 + 167 00c2 7B68 ldr r3, [r7, #4] + 168 00c4 5B69 ldr r3, [r3, #20] + 169 .loc 1 621 54 + 170 00c6 42EA0301 orr r1, r2, r3 + 622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (hi2c->Init.OwnAddress2Masks << 8)); + 171 .loc 1 622 38 + 172 00ca 7B68 ldr r3, [r7, #4] + 173 00cc 9B69 ldr r3, [r3, #24] + 174 .loc 1 622 56 + 175 00ce 1A02 lsls r2, r3, #8 + 621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (hi2c->Init.OwnAddress2Masks << 8)); + 176 .loc 1 621 7 + ARM GAS /tmp/cc5G5cqz.s page 15 + + + 177 00d0 7B68 ldr r3, [r7, #4] + 178 00d2 1B68 ldr r3, [r3] + 621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (hi2c->Init.OwnAddress2Masks << 8)); + 179 .loc 1 621 79 + 180 00d4 0A43 orrs r2, r2, r1 + 621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (hi2c->Init.OwnAddress2Masks << 8)); + 181 .loc 1 621 24 + 182 00d6 DA60 str r2, [r3, #12] + 623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /*---------------------------- I2Cx CR1 Configuration ----------------------*/ + 625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Configure I2Cx: Generalcall and NoStretch mode */ + 626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); + 183 .loc 1 626 36 + 184 00d8 7B68 ldr r3, [r7, #4] + 185 00da D969 ldr r1, [r3, #28] + 186 .loc 1 626 65 + 187 00dc 7B68 ldr r3, [r7, #4] + 188 00de 1A6A ldr r2, [r3, #32] + 189 .loc 1 626 7 + 190 00e0 7B68 ldr r3, [r7, #4] + 191 00e2 1B68 ldr r3, [r3] + 192 .loc 1 626 53 + 193 00e4 0A43 orrs r2, r2, r1 + 194 .loc 1 626 23 + 195 00e6 1A60 str r2, [r3] + 627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable the selected I2C peripheral */ + 629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_ENABLE(hi2c); + 196 .loc 1 629 3 + 197 00e8 7B68 ldr r3, [r7, #4] + 198 00ea 1B68 ldr r3, [r3] + 199 00ec 1A68 ldr r2, [r3] + 200 00ee 7B68 ldr r3, [r7, #4] + 201 00f0 1B68 ldr r3, [r3] + 202 00f2 42F00102 orr r2, r2, #1 + 203 00f6 1A60 str r2, [r3] + 630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 204 .loc 1 631 19 + 205 00f8 7B68 ldr r3, [r7, #4] + 206 00fa 0022 movs r2, #0 + 207 00fc 5A64 str r2, [r3, #68] + 632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 208 .loc 1 632 15 + 209 00fe 7B68 ldr r3, [r7, #4] + 210 0100 2022 movs r2, #32 + 211 0102 83F84120 strb r2, [r3, #65] + 633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 212 .loc 1 633 23 + 213 0106 7B68 ldr r3, [r7, #4] + 214 0108 0022 movs r2, #0 + 215 010a 1A63 str r2, [r3, #48] + 634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 216 .loc 1 634 14 + 217 010c 7B68 ldr r3, [r7, #4] + 218 010e 0022 movs r2, #0 + 219 0110 83F84220 strb r2, [r3, #66] + ARM GAS /tmp/cc5G5cqz.s page 16 + + + 635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; + 220 .loc 1 636 10 + 221 0114 0023 movs r3, #0 + 222 .L3: + 637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 223 .loc 1 637 1 + 224 0116 1846 mov r0, r3 + 225 0118 0837 adds r7, r7, #8 + 226 .cfi_def_cfa_offset 8 + 227 011a BD46 mov sp, r7 + 228 .cfi_def_cfa_register 13 + 229 @ sp needed + 230 011c 80BD pop {r7, pc} + 231 .cfi_endproc + 232 .LFE130: + 234 .section .text.HAL_I2C_DeInit,"ax",%progbits + 235 .align 1 + 236 .global HAL_I2C_DeInit + 237 .syntax unified + 238 .thumb + 239 .thumb_func + 241 HAL_I2C_DeInit: + 242 .LFB131: + 638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** + 640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief DeInitialize the I2C peripheral. + 641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 642:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. + 643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status + 644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ + 645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) + 646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 243 .loc 1 646 1 + 244 .cfi_startproc + 245 @ args = 0, pretend = 0, frame = 8 + 246 @ frame_needed = 1, uses_anonymous_args = 0 + 247 0000 80B5 push {r7, lr} + 248 .cfi_def_cfa_offset 8 + 249 .cfi_offset 7, -8 + 250 .cfi_offset 14, -4 + 251 0002 82B0 sub sp, sp, #8 + 252 .cfi_def_cfa_offset 16 + 253 0004 00AF add r7, sp, #0 + 254 .cfi_def_cfa_register 7 + 255 0006 7860 str r0, [r7, #4] + 647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check the I2C handle allocation */ + 648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c == NULL) + 256 .loc 1 648 6 + 257 0008 7B68 ldr r3, [r7, #4] + 258 000a 002B cmp r3, #0 + 259 000c 01D1 bne .L9 + 649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 260 .loc 1 650 12 + 261 000e 0123 movs r3, #1 + 262 0010 21E0 b .L10 + ARM GAS /tmp/cc5G5cqz.s page 17 + + + 263 .L9: + 651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check the parameters */ + 654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + 655:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY; + 264 .loc 1 656 15 + 265 0012 7B68 ldr r3, [r7, #4] + 266 0014 2422 movs r2, #36 + 267 0016 83F84120 strb r2, [r3, #65] + 657:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable the I2C Peripheral Clock */ + 659:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_DISABLE(hi2c); + 268 .loc 1 659 3 + 269 001a 7B68 ldr r3, [r7, #4] + 270 001c 1B68 ldr r3, [r3] + 271 001e 1A68 ldr r2, [r3] + 272 0020 7B68 ldr r3, [r7, #4] + 273 0022 1B68 ldr r3, [r3] + 274 0024 22F00102 bic r2, r2, #1 + 275 0028 1A60 str r2, [r3] + 660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + 662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->MspDeInitCallback == NULL) + 663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 664:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + 665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + 668:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MspDeInitCallback(hi2c); + 669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #else + 670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + 671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_MspDeInit(hi2c); + 276 .loc 1 671 3 + 277 002a 7868 ldr r0, [r7, #4] + 278 002c FFF7FEFF bl HAL_I2C_MspDeInit + 672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 279 .loc 1 674 19 + 280 0030 7B68 ldr r3, [r7, #4] + 281 0032 0022 movs r2, #0 + 282 0034 5A64 str r2, [r3, #68] + 675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_RESET; + 283 .loc 1 675 15 + 284 0036 7B68 ldr r3, [r7, #4] + 285 0038 0022 movs r2, #0 + 286 003a 83F84120 strb r2, [r3, #65] + 676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 287 .loc 1 676 23 + 288 003e 7B68 ldr r3, [r7, #4] + 289 0040 0022 movs r2, #0 + 290 0042 1A63 str r2, [r3, #48] + 677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 291 .loc 1 677 14 + 292 0044 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/cc5G5cqz.s page 18 + + + 293 0046 0022 movs r2, #0 + 294 0048 83F84220 strb r2, [r3, #66] + 678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Release Lock */ + 680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 295 .loc 1 680 3 + 296 004c 7B68 ldr r3, [r7, #4] + 297 004e 0022 movs r2, #0 + 298 0050 83F84020 strb r2, [r3, #64] + 681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; + 299 .loc 1 682 10 + 300 0054 0023 movs r3, #0 + 301 .L10: + 683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 302 .loc 1 683 1 + 303 0056 1846 mov r0, r3 + 304 0058 0837 adds r7, r7, #8 + 305 .cfi_def_cfa_offset 8 + 306 005a BD46 mov sp, r7 + 307 .cfi_def_cfa_register 13 + 308 @ sp needed + 309 005c 80BD pop {r7, pc} + 310 .cfi_endproc + 311 .LFE131: + 313 .section .text.HAL_I2C_MspInit,"ax",%progbits + 314 .align 1 + 315 .weak HAL_I2C_MspInit + 316 .syntax unified + 317 .thumb + 318 .thumb_func + 320 HAL_I2C_MspInit: + 321 .LFB132: + 684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** + 686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Initialize the I2C MSP. + 687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 688:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. + 689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None + 690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ + 691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) + 692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 322 .loc 1 692 1 + 323 .cfi_startproc + 324 @ args = 0, pretend = 0, frame = 8 + 325 @ frame_needed = 1, uses_anonymous_args = 0 + 326 @ link register save eliminated. + 327 0000 80B4 push {r7} + 328 .cfi_def_cfa_offset 4 + 329 .cfi_offset 7, -4 + 330 0002 83B0 sub sp, sp, #12 + 331 .cfi_def_cfa_offset 16 + 332 0004 00AF add r7, sp, #0 + 333 .cfi_def_cfa_register 7 + 334 0006 7860 str r0, [r7, #4] + 693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 694:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** UNUSED(hi2c); + ARM GAS /tmp/cc5G5cqz.s page 19 + + + 695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, + 697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** the HAL_I2C_MspInit could be implemented in the user file + 698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ + 699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 335 .loc 1 699 1 + 336 0008 00BF nop + 337 000a 0C37 adds r7, r7, #12 + 338 .cfi_def_cfa_offset 4 + 339 000c BD46 mov sp, r7 + 340 .cfi_def_cfa_register 13 + 341 @ sp needed + 342 000e 5DF8047B ldr r7, [sp], #4 + 343 .cfi_restore 7 + 344 .cfi_def_cfa_offset 0 + 345 0012 7047 bx lr + 346 .cfi_endproc + 347 .LFE132: + 349 .section .text.HAL_I2C_MspDeInit,"ax",%progbits + 350 .align 1 + 351 .weak HAL_I2C_MspDeInit + 352 .syntax unified + 353 .thumb + 354 .thumb_func + 356 HAL_I2C_MspDeInit: + 357 .LFB133: + 700:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** + 702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief DeInitialize the I2C MSP. + 703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 704:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. + 705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None + 706:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ + 707:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) + 708:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 358 .loc 1 708 1 + 359 .cfi_startproc + 360 @ args = 0, pretend = 0, frame = 8 + 361 @ frame_needed = 1, uses_anonymous_args = 0 + 362 @ link register save eliminated. + 363 0000 80B4 push {r7} + 364 .cfi_def_cfa_offset 4 + 365 .cfi_offset 7, -4 + 366 0002 83B0 sub sp, sp, #12 + 367 .cfi_def_cfa_offset 16 + 368 0004 00AF add r7, sp, #0 + 369 .cfi_def_cfa_register 7 + 370 0006 7860 str r0, [r7, #4] + 709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ + 710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** UNUSED(hi2c); + 711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, + 713:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** the HAL_I2C_MspDeInit could be implemented in the user file + 714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ + 715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 371 .loc 1 715 1 + 372 0008 00BF nop + ARM GAS /tmp/cc5G5cqz.s page 20 + + + 373 000a 0C37 adds r7, r7, #12 + 374 .cfi_def_cfa_offset 4 + 375 000c BD46 mov sp, r7 + 376 .cfi_def_cfa_register 13 + 377 @ sp needed + 378 000e 5DF8047B ldr r7, [sp], #4 + 379 .cfi_restore 7 + 380 .cfi_def_cfa_offset 0 + 381 0012 7047 bx lr + 382 .cfi_endproc + 383 .LFE133: + 385 .section .text.HAL_I2C_Master_Transmit,"ax",%progbits + 386 .align 1 + 387 .global HAL_I2C_Master_Transmit + 388 .syntax unified + 389 .thumb + 390 .thumb_func + 392 HAL_I2C_Master_Transmit: + 393 .LFB134: + 716:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + 718:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** + 719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Register a User I2C Callback + 720:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * To be used instead of the weak predefined callback + 721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @note The HAL_I2C_RegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RES + 722:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * to register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID. + 723:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 724:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. + 725:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param CallbackID ID of the callback to be registered + 726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * This parameter can be one of the following values: + 727:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + 728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + 729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + 730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + 731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + 732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID + 733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID + 734:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID + 735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID + 736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID + 737:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID + 738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pCallback pointer to the Callback function + 739:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status + 740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ + 741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef Callb + 742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** pI2C_CallbackTypeDef pCallback) + 743:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef status = HAL_OK; + 745:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 746:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (pCallback == NULL) + 747:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 748:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update the error code */ + 749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + 750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 752:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/cc5G5cqz.s page 21 + + + 754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (HAL_I2C_STATE_READY == hi2c->State) + 755:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** switch (CallbackID) + 757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 758:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : + 759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MasterTxCpltCallback = pCallback; + 760:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 761:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : + 763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MasterRxCpltCallback = pCallback; + 764:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : + 767:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->SlaveTxCpltCallback = pCallback; + 768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : + 771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->SlaveRxCpltCallback = pCallback; + 772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_LISTEN_COMPLETE_CB_ID : + 775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ListenCpltCallback = pCallback; + 776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 777:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_MEM_TX_COMPLETE_CB_ID : + 779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MemTxCpltCallback = pCallback; + 780:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 782:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_MEM_RX_COMPLETE_CB_ID : + 783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MemRxCpltCallback = pCallback; + 784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_ERROR_CB_ID : + 787:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCallback = pCallback; + 788:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_ABORT_CB_ID : + 791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->AbortCpltCallback = pCallback; + 792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_MSPINIT_CB_ID : + 795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MspInitCallback = pCallback; + 796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 798:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_MSPDEINIT_CB_ID : + 799:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MspDeInitCallback = pCallback; + 800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** default : + 803:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update the error code */ + 804:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + 805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 806:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Return error status */ + 807:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** status = HAL_ERROR; + 808:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/cc5G5cqz.s page 22 + + + 811:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if (HAL_I2C_STATE_RESET == hi2c->State) + 812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** switch (CallbackID) + 814:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_MSPINIT_CB_ID : + 816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MspInitCallback = pCallback; + 817:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 818:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_MSPDEINIT_CB_ID : + 820:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MspDeInitCallback = pCallback; + 821:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** default : + 824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update the error code */ + 825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + 826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 827:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Return error status */ + 828:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** status = HAL_ERROR; + 829:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 830:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 832:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else + 833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 834:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update the error code */ + 835:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + 836:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Return error status */ + 838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** status = HAL_ERROR; + 839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 840:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return status; + 842:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 843:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 844:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** + 845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Unregister an I2C Callback + 846:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * I2C callback is redirected to the weak predefined callback + 847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @note The HAL_I2C_UnRegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_R + 848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * to un-register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID. + 849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. + 851:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param CallbackID ID of the callback to be unregistered + 852:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * This parameter can be one of the following values: + 853:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * This parameter can be one of the following values: + 854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + 855:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + 856:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + 857:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + 858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + 859:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID + 860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID + 861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID + 862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID + 863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID + 864:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID + 865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status + 866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ + 867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef Cal + ARM GAS /tmp/cc5G5cqz.s page 23 + + + 868:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef status = HAL_OK; + 870:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (HAL_I2C_STATE_READY == hi2c->State) + 872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 873:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** switch (CallbackID) + 874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 875:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : + 876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallb + 877:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 878:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 879:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : + 880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallb + 881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : + 884:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallba + 885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 887:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : + 888:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallba + 889:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 890:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_LISTEN_COMPLETE_CB_ID : + 892:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallbac + 893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 894:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 895:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_MEM_TX_COMPLETE_CB_ID : + 896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback + 897:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 899:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_MEM_RX_COMPLETE_CB_ID : + 900:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback + 901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 902:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_ERROR_CB_ID : + 904:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback + 905:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 906:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_ABORT_CB_ID : + 908:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback + 909:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 911:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_MSPINIT_CB_ID : + 912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit + 913:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 914:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 915:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_MSPDEINIT_CB_ID : + 916:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit + 917:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 918:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 919:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** default : + 920:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update the error code */ + 921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + 922:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 923:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Return error status */ + 924:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** status = HAL_ERROR; + ARM GAS /tmp/cc5G5cqz.s page 24 + + + 925:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 926:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 928:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if (HAL_I2C_STATE_RESET == hi2c->State) + 929:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 930:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** switch (CallbackID) + 931:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 932:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_MSPINIT_CB_ID : + 933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit + 934:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 935:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 936:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** case HAL_I2C_MSPDEINIT_CB_ID : + 937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit + 938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 939:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** default : + 941:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update the error code */ + 942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + 943:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 944:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Return error status */ + 945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** status = HAL_ERROR; + 946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 947:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 948:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else + 950:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 951:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update the error code */ + 952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + 953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 954:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Return error status */ + 955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** status = HAL_ERROR; + 956:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 957:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 958:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return status; + 959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 960:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** + 962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Register the Slave Address Match I2C Callback + 963:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback + 964:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 965:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. + 966:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pCallback pointer to the Address Match Callback function + 967:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status + 968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ + 969:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pC + 970:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 971:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef status = HAL_OK; + 972:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 973:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (pCallback == NULL) + 974:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 975:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update the error code */ + 976:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + 977:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 978:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 979:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 981:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (HAL_I2C_STATE_READY == hi2c->State) + ARM GAS /tmp/cc5G5cqz.s page 25 + + + 982:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 983:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->AddrCallback = pCallback; + 984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 985:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else + 986:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 987:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update the error code */ + 988:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + 989:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 990:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Return error status */ + 991:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** status = HAL_ERROR; + 992:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 993:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 994:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return status; + 995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 996:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 997:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** + 998:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief UnRegister the Slave Address Match I2C Callback + 999:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined cal +1000:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1001:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +1002:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +1003:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +1004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) +1005:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1006:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef status = HAL_OK; +1007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1008:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (HAL_I2C_STATE_READY == hi2c->State) +1009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1010:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ +1011:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +1013:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1014:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update the error code */ +1015:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; +1016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1017:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Return error status */ +1018:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** status = HAL_ERROR; +1019:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1021:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return status; +1022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1023:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +1025:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +1027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @} +1028:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +1029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1030:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions +1031:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Data transfers functions +1032:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * +1033:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** @verbatim +1034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** =============================================================================== +1035:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** ##### IO operation functions ##### +1036:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** =============================================================================== +1037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** [..] +1038:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** This subsection provides a set of functions allowing to manage the I2C data + ARM GAS /tmp/cc5G5cqz.s page 26 + + +1039:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** transfers. +1040:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1041:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (#) There are two modes of transfer: +1042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) Blocking mode : The communication is performed in the polling mode. +1043:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** The status of all data processing is returned by the same function +1044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** after finishing transfer. +1045:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) No-Blocking mode : The communication is performed using Interrupts +1046:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** or DMA. These functions return the status of the transfer startup. +1047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** The end of the data processing will be indicated through the +1048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when +1049:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** using DMA mode. +1050:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (#) Blocking mode functions are : +1052:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Master_Transmit() +1053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Master_Receive() +1054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Slave_Transmit() +1055:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Slave_Receive() +1056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Mem_Write() +1057:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Mem_Read() +1058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_IsDeviceReady() +1059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1060:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (#) No-Blocking mode functions with Interrupt are : +1061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Master_Transmit_IT() +1062:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Master_Receive_IT() +1063:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Slave_Transmit_IT() +1064:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Slave_Receive_IT() +1065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Mem_Write_IT() +1066:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Mem_Read_IT() +1067:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Master_Seq_Transmit_IT() +1068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Master_Seq_Receive_IT() +1069:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Slave_Seq_Transmit_IT() +1070:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Slave_Seq_Receive_IT() +1071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_EnableListen_IT() +1072:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_DisableListen_IT() +1073:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Master_Abort_IT() +1074:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1075:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (#) No-Blocking mode functions with DMA are : +1076:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Master_Transmit_DMA() +1077:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Master_Receive_DMA() +1078:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Slave_Transmit_DMA() +1079:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Slave_Receive_DMA() +1080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Mem_Write_DMA() +1081:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Mem_Read_DMA() +1082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Master_Seq_Transmit_DMA() +1083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Master_Seq_Receive_DMA() +1084:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Slave_Seq_Transmit_DMA() +1085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_Slave_Seq_Receive_DMA() +1086:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1087:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: +1088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_MasterTxCpltCallback() +1089:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_MasterRxCpltCallback() +1090:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_SlaveTxCpltCallback() +1091:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_SlaveRxCpltCallback() +1092:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_MemTxCpltCallback() +1093:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_MemRxCpltCallback() +1094:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_AddrCallback() +1095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_ListenCpltCallback() + ARM GAS /tmp/cc5G5cqz.s page 27 + + +1096:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_ErrorCallback() +1097:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (++) HAL_I2C_AbortCpltCallback() +1098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1099:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** @endverbatim +1100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @{ +1101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +1102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +1104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Transmits in master mode an amount of data in blocking mode. +1105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +1107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +1108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +1109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer +1110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be sent +1111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Timeout Timeout duration +1112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +1113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +1114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pD +1115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t Size, uint32_t Timeout) +1116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 394 .loc 1 1116 1 + 395 .cfi_startproc + 396 @ args = 4, pretend = 0, frame = 24 + 397 @ frame_needed = 1, uses_anonymous_args = 0 + 398 0000 80B5 push {r7, lr} + 399 .cfi_def_cfa_offset 8 + 400 .cfi_offset 7, -8 + 401 .cfi_offset 14, -4 + 402 0002 88B0 sub sp, sp, #32 + 403 .cfi_def_cfa_offset 40 + 404 0004 02AF add r7, sp, #8 + 405 .cfi_def_cfa 7, 32 + 406 0006 F860 str r0, [r7, #12] + 407 0008 7A60 str r2, [r7, #4] + 408 000a 1A46 mov r2, r3 + 409 000c 0B46 mov r3, r1 @ movhi + 410 000e 7B81 strh r3, [r7, #10] @ movhi + 411 0010 1346 mov r3, r2 @ movhi + 412 0012 3B81 strh r3, [r7, #8] @ movhi +1117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tickstart; +1118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 413 .loc 1 1119 11 + 414 0014 FB68 ldr r3, [r7, #12] + 415 0016 93F84130 ldrb r3, [r3, #65] + 416 001a DBB2 uxtb r3, r3 + 417 .loc 1 1119 6 + 418 001c 202B cmp r3, #32 + 419 001e 40F0DA80 bne .L14 +1120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +1122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); + 420 .loc 1 1122 5 + 421 0022 FB68 ldr r3, [r7, #12] + 422 0024 93F84030 ldrb r3, [r3, #64] @ zero_extendqisi2 + 423 0028 012B cmp r3, #1 + ARM GAS /tmp/cc5G5cqz.s page 28 + + + 424 002a 01D1 bne .L15 + 425 .loc 1 1122 5 is_stmt 0 discriminator 1 + 426 002c 0223 movs r3, #2 + 427 .loc 1 1122 5 + 428 002e D3E0 b .L16 + 429 .L15: + 430 .loc 1 1122 5 discriminator 2 + 431 0030 FB68 ldr r3, [r7, #12] + 432 0032 0122 movs r2, #1 + 433 0034 83F84020 strb r2, [r3, #64] +1123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Init tickstart for timeout management*/ +1125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tickstart = HAL_GetTick(); + 434 .loc 1 1125 17 is_stmt 1 + 435 0038 FFF7FEFF bl HAL_GetTick + 436 003c 7861 str r0, [r7, #20] +1126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK + 437 .loc 1 1127 9 + 438 003e 7B69 ldr r3, [r7, #20] + 439 0040 0093 str r3, [sp] + 440 0042 1923 movs r3, #25 + 441 0044 0122 movs r2, #1 + 442 0046 4FF40041 mov r1, #32768 + 443 004a F868 ldr r0, [r7, #12] + 444 004c FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 445 0050 0346 mov r3, r0 + 446 .loc 1 1127 8 discriminator 1 + 447 0052 002B cmp r3, #0 + 448 0054 01D0 beq .L17 +1128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 449 .loc 1 1129 14 + 450 0056 0123 movs r3, #1 + 451 0058 BEE0 b .L16 + 452 .L17: +1130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; + 453 .loc 1 1132 21 + 454 005a FB68 ldr r3, [r7, #12] + 455 005c 2122 movs r2, #33 + 456 005e 83F84120 strb r2, [r3, #65] +1133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 457 .loc 1 1133 21 + 458 0062 FB68 ldr r3, [r7, #12] + 459 0064 1022 movs r2, #16 + 460 0066 83F84220 strb r2, [r3, #66] +1134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 461 .loc 1 1134 21 + 462 006a FB68 ldr r3, [r7, #12] + 463 006c 0022 movs r2, #0 + 464 006e 5A64 str r2, [r3, #68] +1135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ +1137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; + 465 .loc 1 1137 21 + ARM GAS /tmp/cc5G5cqz.s page 29 + + + 466 0070 FB68 ldr r3, [r7, #12] + 467 0072 7A68 ldr r2, [r7, #4] + 468 0074 5A62 str r2, [r3, #36] +1138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 469 .loc 1 1138 21 + 470 0076 FB68 ldr r3, [r7, #12] + 471 0078 3A89 ldrh r2, [r7, #8] @ movhi + 472 007a 5A85 strh r2, [r3, #42] @ movhi +1139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = NULL; + 473 .loc 1 1139 21 + 474 007c FB68 ldr r3, [r7, #12] + 475 007e 0022 movs r2, #0 + 476 0080 5A63 str r2, [r3, #52] +1140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send Slave Address */ +1142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ +1143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) + 477 .loc 1 1143 13 + 478 0082 FB68 ldr r3, [r7, #12] + 479 0084 5B8D ldrh r3, [r3, #42] @ movhi + 480 0086 9BB2 uxth r3, r3 + 481 .loc 1 1143 8 + 482 0088 FF2B cmp r3, #255 + 483 008a 0ED9 bls .L18 +1144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; + 484 .loc 1 1145 22 + 485 008c FB68 ldr r3, [r7, #12] + 486 008e FF22 movs r2, #255 + 487 0090 1A85 strh r2, [r3, #40] @ movhi +1146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 488 .loc 1 1146 57 + 489 0092 FB68 ldr r3, [r7, #12] + 490 0094 1B8D ldrh r3, [r3, #40] + 491 .loc 1 1146 7 + 492 0096 DAB2 uxtb r2, r3 + 493 0098 7989 ldrh r1, [r7, #10] + 494 009a 514B ldr r3, .L27 + 495 009c 0093 str r3, [sp] + 496 009e 4FF08073 mov r3, #16777216 + 497 00a2 F868 ldr r0, [r7, #12] + 498 00a4 FFF7FEFF bl I2C_TransferConfig + 499 00a8 6CE0 b .L20 + 500 .L18: +1147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_GENERATE_START_WRITE); +1148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +1150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 501 .loc 1 1151 28 + 502 00aa FB68 ldr r3, [r7, #12] + 503 00ac 5B8D ldrh r3, [r3, #42] @ movhi + 504 00ae 9AB2 uxth r2, r3 + 505 .loc 1 1151 22 + 506 00b0 FB68 ldr r3, [r7, #12] + 507 00b2 1A85 strh r2, [r3, #40] @ movhi +1152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + ARM GAS /tmp/cc5G5cqz.s page 30 + + + 508 .loc 1 1152 57 + 509 00b4 FB68 ldr r3, [r7, #12] + 510 00b6 1B8D ldrh r3, [r3, #40] + 511 .loc 1 1152 7 + 512 00b8 DAB2 uxtb r2, r3 + 513 00ba 7989 ldrh r1, [r7, #10] + 514 00bc 484B ldr r3, .L27 + 515 00be 0093 str r3, [sp] + 516 00c0 4FF00073 mov r3, #33554432 + 517 00c4 F868 ldr r0, [r7, #12] + 518 00c6 FFF7FEFF bl I2C_TransferConfig +1153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_GENERATE_START_WRITE); +1154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** while (hi2c->XferCount > 0U) + 519 .loc 1 1156 11 + 520 00ca 5BE0 b .L20 + 521 .L25: +1157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until TXIS flag is set */ +1159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + 522 .loc 1 1159 11 + 523 00cc 7A69 ldr r2, [r7, #20] + 524 00ce 396A ldr r1, [r7, #32] + 525 00d0 F868 ldr r0, [r7, #12] + 526 00d2 FFF7FEFF bl I2C_WaitOnTXISFlagUntilTimeout + 527 00d6 0346 mov r3, r0 + 528 .loc 1 1159 10 discriminator 1 + 529 00d8 002B cmp r3, #0 + 530 00da 01D0 beq .L21 +1160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 531 .loc 1 1161 16 + 532 00dc 0123 movs r3, #1 + 533 00de 7BE0 b .L16 + 534 .L21: +1162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Write data to TXDR */ +1164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->TXDR = *hi2c->pBuffPtr; + 535 .loc 1 1164 35 + 536 00e0 FB68 ldr r3, [r7, #12] + 537 00e2 5B6A ldr r3, [r3, #36] + 538 .loc 1 1164 30 + 539 00e4 1A78 ldrb r2, [r3] @ zero_extendqisi2 + 540 .loc 1 1164 11 + 541 00e6 FB68 ldr r3, [r7, #12] + 542 00e8 1B68 ldr r3, [r3] + 543 .loc 1 1164 28 + 544 00ea 9A62 str r2, [r3, #40] +1165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Increment Buffer pointer */ +1167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr++; + 545 .loc 1 1167 11 + 546 00ec FB68 ldr r3, [r7, #12] + 547 00ee 5B6A ldr r3, [r3, #36] + 548 .loc 1 1167 21 + 549 00f0 5A1C adds r2, r3, #1 + ARM GAS /tmp/cc5G5cqz.s page 31 + + + 550 00f2 FB68 ldr r3, [r7, #12] + 551 00f4 5A62 str r2, [r3, #36] +1168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount--; + 552 .loc 1 1169 11 + 553 00f6 FB68 ldr r3, [r7, #12] + 554 00f8 5B8D ldrh r3, [r3, #42] @ movhi + 555 00fa 9BB2 uxth r3, r3 + 556 .loc 1 1169 22 + 557 00fc 013B subs r3, r3, #1 + 558 00fe 9AB2 uxth r2, r3 + 559 0100 FB68 ldr r3, [r7, #12] + 560 0102 5A85 strh r2, [r3, #42] @ movhi +1170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize--; + 561 .loc 1 1170 11 + 562 0104 FB68 ldr r3, [r7, #12] + 563 0106 1B8D ldrh r3, [r3, #40] + 564 .loc 1 1170 21 + 565 0108 013B subs r3, r3, #1 + 566 010a 9AB2 uxth r2, r3 + 567 010c FB68 ldr r3, [r7, #12] + 568 010e 1A85 strh r2, [r3, #40] @ movhi +1171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + 569 .loc 1 1172 16 + 570 0110 FB68 ldr r3, [r7, #12] + 571 0112 5B8D ldrh r3, [r3, #42] @ movhi + 572 0114 9BB2 uxth r3, r3 + 573 .loc 1 1172 10 + 574 0116 002B cmp r3, #0 + 575 0118 34D0 beq .L20 + 576 .loc 1 1172 43 discriminator 1 + 577 011a FB68 ldr r3, [r7, #12] + 578 011c 1B8D ldrh r3, [r3, #40] + 579 .loc 1 1172 35 discriminator 1 + 580 011e 002B cmp r3, #0 + 581 0120 30D1 bne .L20 +1173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until TCR flag is set */ +1175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + 582 .loc 1 1175 13 + 583 0122 7B69 ldr r3, [r7, #20] + 584 0124 0093 str r3, [sp] + 585 0126 3B6A ldr r3, [r7, #32] + 586 0128 0022 movs r2, #0 + 587 012a 8021 movs r1, #128 + 588 012c F868 ldr r0, [r7, #12] + 589 012e FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 590 0132 0346 mov r3, r0 + 591 .loc 1 1175 12 discriminator 1 + 592 0134 002B cmp r3, #0 + 593 0136 01D0 beq .L23 +1176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 594 .loc 1 1177 18 + 595 0138 0123 movs r3, #1 + 596 013a 4DE0 b .L16 + ARM GAS /tmp/cc5G5cqz.s page 32 + + + 597 .L23: +1178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) + 598 .loc 1 1180 17 + 599 013c FB68 ldr r3, [r7, #12] + 600 013e 5B8D ldrh r3, [r3, #42] @ movhi + 601 0140 9BB2 uxth r3, r3 + 602 .loc 1 1180 12 + 603 0142 FF2B cmp r3, #255 + 604 0144 0ED9 bls .L24 +1181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; + 605 .loc 1 1182 26 + 606 0146 FB68 ldr r3, [r7, #12] + 607 0148 FF22 movs r2, #255 + 608 014a 1A85 strh r2, [r3, #40] @ movhi +1183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 609 .loc 1 1183 61 + 610 014c FB68 ldr r3, [r7, #12] + 611 014e 1B8D ldrh r3, [r3, #40] + 612 .loc 1 1183 11 + 613 0150 DAB2 uxtb r2, r3 + 614 0152 7989 ldrh r1, [r7, #10] + 615 0154 0023 movs r3, #0 + 616 0156 0093 str r3, [sp] + 617 0158 4FF08073 mov r3, #16777216 + 618 015c F868 ldr r0, [r7, #12] + 619 015e FFF7FEFF bl I2C_TransferConfig + 620 0162 0FE0 b .L20 + 621 .L24: +1184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_NO_STARTSTOP); +1185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +1187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 622 .loc 1 1188 32 + 623 0164 FB68 ldr r3, [r7, #12] + 624 0166 5B8D ldrh r3, [r3, #42] @ movhi + 625 0168 9AB2 uxth r2, r3 + 626 .loc 1 1188 26 + 627 016a FB68 ldr r3, [r7, #12] + 628 016c 1A85 strh r2, [r3, #40] @ movhi +1189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 629 .loc 1 1189 61 + 630 016e FB68 ldr r3, [r7, #12] + 631 0170 1B8D ldrh r3, [r3, #40] + 632 .loc 1 1189 11 + 633 0172 DAB2 uxtb r2, r3 + 634 0174 7989 ldrh r1, [r7, #10] + 635 0176 0023 movs r3, #0 + 636 0178 0093 str r3, [sp] + 637 017a 4FF00073 mov r3, #33554432 + 638 017e F868 ldr r0, [r7, #12] + 639 0180 FFF7FEFF bl I2C_TransferConfig + 640 .L20: +1156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + ARM GAS /tmp/cc5G5cqz.s page 33 + + + 641 .loc 1 1156 16 + 642 0184 FB68 ldr r3, [r7, #12] + 643 0186 5B8D ldrh r3, [r3, #42] @ movhi + 644 0188 9BB2 uxth r3, r3 +1156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 645 .loc 1 1156 28 + 646 018a 002B cmp r3, #0 + 647 018c 9ED1 bne .L25 +1190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_NO_STARTSTOP); +1191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ +1196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until STOPF flag is set */ +1197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + 648 .loc 1 1197 9 + 649 018e 7A69 ldr r2, [r7, #20] + 650 0190 396A ldr r1, [r7, #32] + 651 0192 F868 ldr r0, [r7, #12] + 652 0194 FFF7FEFF bl I2C_WaitOnSTOPFlagUntilTimeout + 653 0198 0346 mov r3, r0 + 654 .loc 1 1197 8 discriminator 1 + 655 019a 002B cmp r3, #0 + 656 019c 01D0 beq .L26 +1198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 657 .loc 1 1199 14 + 658 019e 0123 movs r3, #1 + 659 01a0 1AE0 b .L16 + 660 .L26: +1200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear STOP Flag */ +1203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + 661 .loc 1 1203 5 + 662 01a2 FB68 ldr r3, [r7, #12] + 663 01a4 1B68 ldr r3, [r3] + 664 01a6 2022 movs r2, #32 + 665 01a8 DA61 str r2, [r3, #28] +1204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear Configuration Register 2 */ +1206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_RESET_CR2(hi2c); + 666 .loc 1 1206 5 + 667 01aa FB68 ldr r3, [r7, #12] + 668 01ac 1B68 ldr r3, [r3] + 669 01ae 5968 ldr r1, [r3, #4] + 670 01b0 FB68 ldr r3, [r7, #12] + 671 01b2 1A68 ldr r2, [r3] + 672 01b4 0B4B ldr r3, .L27+4 + 673 01b6 0B40 ands r3, r3, r1 + 674 01b8 5360 str r3, [r2, #4] +1207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 675 .loc 1 1208 17 + 676 01ba FB68 ldr r3, [r7, #12] + 677 01bc 2022 movs r2, #32 + ARM GAS /tmp/cc5G5cqz.s page 34 + + + 678 01be 83F84120 strb r2, [r3, #65] +1209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 679 .loc 1 1209 17 + 680 01c2 FB68 ldr r3, [r7, #12] + 681 01c4 0022 movs r2, #0 + 682 01c6 83F84220 strb r2, [r3, #66] +1210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +1212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 683 .loc 1 1212 5 + 684 01ca FB68 ldr r3, [r7, #12] + 685 01cc 0022 movs r2, #0 + 686 01ce 83F84020 strb r2, [r3, #64] +1213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; + 687 .loc 1 1214 12 + 688 01d2 0023 movs r3, #0 + 689 01d4 00E0 b .L16 + 690 .L14: +1215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +1217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; + 691 .loc 1 1218 12 + 692 01d6 0223 movs r3, #2 + 693 .L16: +1219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 694 .loc 1 1220 1 + 695 01d8 1846 mov r0, r3 + 696 01da 1837 adds r7, r7, #24 + 697 .cfi_def_cfa_offset 8 + 698 01dc BD46 mov sp, r7 + 699 .cfi_def_cfa_register 13 + 700 @ sp needed + 701 01de 80BD pop {r7, pc} + 702 .L28: + 703 .align 2 + 704 .L27: + 705 01e0 00200080 .word -2147475456 + 706 01e4 00E800FE .word -33495040 + 707 .cfi_endproc + 708 .LFE134: + 710 .section .text.HAL_I2C_Master_Receive,"ax",%progbits + 711 .align 1 + 712 .global HAL_I2C_Master_Receive + 713 .syntax unified + 714 .thumb + 715 .thumb_func + 717 HAL_I2C_Master_Receive: + 718 .LFB135: +1221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +1223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Receives in master mode an amount of data in blocking mode. +1224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +1226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value + ARM GAS /tmp/cc5G5cqz.s page 35 + + +1227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +1228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer +1229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be sent +1230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Timeout Timeout duration +1231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +1232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +1233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pDa +1234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t Size, uint32_t Timeout) +1235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 719 .loc 1 1235 1 + 720 .cfi_startproc + 721 @ args = 4, pretend = 0, frame = 24 + 722 @ frame_needed = 1, uses_anonymous_args = 0 + 723 0000 80B5 push {r7, lr} + 724 .cfi_def_cfa_offset 8 + 725 .cfi_offset 7, -8 + 726 .cfi_offset 14, -4 + 727 0002 88B0 sub sp, sp, #32 + 728 .cfi_def_cfa_offset 40 + 729 0004 02AF add r7, sp, #8 + 730 .cfi_def_cfa 7, 32 + 731 0006 F860 str r0, [r7, #12] + 732 0008 7A60 str r2, [r7, #4] + 733 000a 1A46 mov r2, r3 + 734 000c 0B46 mov r3, r1 @ movhi + 735 000e 7B81 strh r3, [r7, #10] @ movhi + 736 0010 1346 mov r3, r2 @ movhi + 737 0012 3B81 strh r3, [r7, #8] @ movhi +1236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tickstart; +1237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 738 .loc 1 1238 11 + 739 0014 FB68 ldr r3, [r7, #12] + 740 0016 93F84130 ldrb r3, [r3, #65] + 741 001a DBB2 uxtb r3, r3 + 742 .loc 1 1238 6 + 743 001c 202B cmp r3, #32 + 744 001e 40F0DB80 bne .L30 +1239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +1241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); + 745 .loc 1 1241 5 + 746 0022 FB68 ldr r3, [r7, #12] + 747 0024 93F84030 ldrb r3, [r3, #64] @ zero_extendqisi2 + 748 0028 012B cmp r3, #1 + 749 002a 01D1 bne .L31 + 750 .loc 1 1241 5 is_stmt 0 discriminator 1 + 751 002c 0223 movs r3, #2 + 752 .loc 1 1241 5 + 753 002e D4E0 b .L32 + 754 .L31: + 755 .loc 1 1241 5 discriminator 2 + 756 0030 FB68 ldr r3, [r7, #12] + 757 0032 0122 movs r2, #1 + 758 0034 83F84020 strb r2, [r3, #64] +1242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Init tickstart for timeout management*/ + ARM GAS /tmp/cc5G5cqz.s page 36 + + +1244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tickstart = HAL_GetTick(); + 759 .loc 1 1244 17 is_stmt 1 + 760 0038 FFF7FEFF bl HAL_GetTick + 761 003c 7861 str r0, [r7, #20] +1245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK + 762 .loc 1 1246 9 + 763 003e 7B69 ldr r3, [r7, #20] + 764 0040 0093 str r3, [sp] + 765 0042 1923 movs r3, #25 + 766 0044 0122 movs r2, #1 + 767 0046 4FF40041 mov r1, #32768 + 768 004a F868 ldr r0, [r7, #12] + 769 004c FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 770 0050 0346 mov r3, r0 + 771 .loc 1 1246 8 discriminator 1 + 772 0052 002B cmp r3, #0 + 773 0054 01D0 beq .L33 +1247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 774 .loc 1 1248 14 + 775 0056 0123 movs r3, #1 + 776 0058 BFE0 b .L32 + 777 .L33: +1249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; + 778 .loc 1 1251 21 + 779 005a FB68 ldr r3, [r7, #12] + 780 005c 2222 movs r2, #34 + 781 005e 83F84120 strb r2, [r3, #65] +1252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 782 .loc 1 1252 21 + 783 0062 FB68 ldr r3, [r7, #12] + 784 0064 1022 movs r2, #16 + 785 0066 83F84220 strb r2, [r3, #66] +1253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 786 .loc 1 1253 21 + 787 006a FB68 ldr r3, [r7, #12] + 788 006c 0022 movs r2, #0 + 789 006e 5A64 str r2, [r3, #68] +1254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ +1256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; + 790 .loc 1 1256 21 + 791 0070 FB68 ldr r3, [r7, #12] + 792 0072 7A68 ldr r2, [r7, #4] + 793 0074 5A62 str r2, [r3, #36] +1257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 794 .loc 1 1257 21 + 795 0076 FB68 ldr r3, [r7, #12] + 796 0078 3A89 ldrh r2, [r7, #8] @ movhi + 797 007a 5A85 strh r2, [r3, #42] @ movhi +1258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = NULL; + 798 .loc 1 1258 21 + 799 007c FB68 ldr r3, [r7, #12] + 800 007e 0022 movs r2, #0 + ARM GAS /tmp/cc5G5cqz.s page 37 + + + 801 0080 5A63 str r2, [r3, #52] +1259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send Slave Address */ +1261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ +1262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) + 802 .loc 1 1262 13 + 803 0082 FB68 ldr r3, [r7, #12] + 804 0084 5B8D ldrh r3, [r3, #42] @ movhi + 805 0086 9BB2 uxth r3, r3 + 806 .loc 1 1262 8 + 807 0088 FF2B cmp r3, #255 + 808 008a 0ED9 bls .L34 +1263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; + 809 .loc 1 1264 22 + 810 008c FB68 ldr r3, [r7, #12] + 811 008e FF22 movs r2, #255 + 812 0090 1A85 strh r2, [r3, #40] @ movhi +1265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 813 .loc 1 1265 57 + 814 0092 FB68 ldr r3, [r7, #12] + 815 0094 1B8D ldrh r3, [r3, #40] + 816 .loc 1 1265 7 + 817 0096 DAB2 uxtb r2, r3 + 818 0098 7989 ldrh r1, [r7, #10] + 819 009a 524B ldr r3, .L43 + 820 009c 0093 str r3, [sp] + 821 009e 4FF08073 mov r3, #16777216 + 822 00a2 F868 ldr r0, [r7, #12] + 823 00a4 FFF7FEFF bl I2C_TransferConfig + 824 00a8 6DE0 b .L36 + 825 .L34: +1266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_GENERATE_START_READ); +1267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +1269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 826 .loc 1 1270 28 + 827 00aa FB68 ldr r3, [r7, #12] + 828 00ac 5B8D ldrh r3, [r3, #42] @ movhi + 829 00ae 9AB2 uxth r2, r3 + 830 .loc 1 1270 22 + 831 00b0 FB68 ldr r3, [r7, #12] + 832 00b2 1A85 strh r2, [r3, #40] @ movhi +1271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 833 .loc 1 1271 57 + 834 00b4 FB68 ldr r3, [r7, #12] + 835 00b6 1B8D ldrh r3, [r3, #40] + 836 .loc 1 1271 7 + 837 00b8 DAB2 uxtb r2, r3 + 838 00ba 7989 ldrh r1, [r7, #10] + 839 00bc 494B ldr r3, .L43 + 840 00be 0093 str r3, [sp] + 841 00c0 4FF00073 mov r3, #33554432 + 842 00c4 F868 ldr r0, [r7, #12] + 843 00c6 FFF7FEFF bl I2C_TransferConfig +1272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_GENERATE_START_READ); + ARM GAS /tmp/cc5G5cqz.s page 38 + + +1273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** while (hi2c->XferCount > 0U) + 844 .loc 1 1275 11 + 845 00ca 5CE0 b .L36 + 846 .L41: +1276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until RXNE flag is set */ +1278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + 847 .loc 1 1278 11 + 848 00cc 7A69 ldr r2, [r7, #20] + 849 00ce 396A ldr r1, [r7, #32] + 850 00d0 F868 ldr r0, [r7, #12] + 851 00d2 FFF7FEFF bl I2C_WaitOnRXNEFlagUntilTimeout + 852 00d6 0346 mov r3, r0 + 853 .loc 1 1278 10 discriminator 1 + 854 00d8 002B cmp r3, #0 + 855 00da 01D0 beq .L37 +1279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 856 .loc 1 1280 16 + 857 00dc 0123 movs r3, #1 + 858 00de 7CE0 b .L32 + 859 .L37: +1281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Read data from RXDR */ +1284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + 860 .loc 1 1284 38 + 861 00e0 FB68 ldr r3, [r7, #12] + 862 00e2 1B68 ldr r3, [r3] + 863 .loc 1 1284 48 + 864 00e4 5A6A ldr r2, [r3, #36] + 865 .loc 1 1284 12 + 866 00e6 FB68 ldr r3, [r7, #12] + 867 00e8 5B6A ldr r3, [r3, #36] + 868 .loc 1 1284 25 + 869 00ea D2B2 uxtb r2, r2 + 870 .loc 1 1284 23 + 871 00ec 1A70 strb r2, [r3] +1285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Increment Buffer pointer */ +1287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr++; + 872 .loc 1 1287 11 + 873 00ee FB68 ldr r3, [r7, #12] + 874 00f0 5B6A ldr r3, [r3, #36] + 875 .loc 1 1287 21 + 876 00f2 5A1C adds r2, r3, #1 + 877 00f4 FB68 ldr r3, [r7, #12] + 878 00f6 5A62 str r2, [r3, #36] +1288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize--; + 879 .loc 1 1289 11 + 880 00f8 FB68 ldr r3, [r7, #12] + 881 00fa 1B8D ldrh r3, [r3, #40] + 882 .loc 1 1289 21 + 883 00fc 013B subs r3, r3, #1 + ARM GAS /tmp/cc5G5cqz.s page 39 + + + 884 00fe 9AB2 uxth r2, r3 + 885 0100 FB68 ldr r3, [r7, #12] + 886 0102 1A85 strh r2, [r3, #40] @ movhi +1290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount--; + 887 .loc 1 1290 11 + 888 0104 FB68 ldr r3, [r7, #12] + 889 0106 5B8D ldrh r3, [r3, #42] @ movhi + 890 0108 9BB2 uxth r3, r3 + 891 .loc 1 1290 22 + 892 010a 013B subs r3, r3, #1 + 893 010c 9AB2 uxth r2, r3 + 894 010e FB68 ldr r3, [r7, #12] + 895 0110 5A85 strh r2, [r3, #42] @ movhi +1291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + 896 .loc 1 1292 16 + 897 0112 FB68 ldr r3, [r7, #12] + 898 0114 5B8D ldrh r3, [r3, #42] @ movhi + 899 0116 9BB2 uxth r3, r3 + 900 .loc 1 1292 10 + 901 0118 002B cmp r3, #0 + 902 011a 34D0 beq .L36 + 903 .loc 1 1292 43 discriminator 1 + 904 011c FB68 ldr r3, [r7, #12] + 905 011e 1B8D ldrh r3, [r3, #40] + 906 .loc 1 1292 35 discriminator 1 + 907 0120 002B cmp r3, #0 + 908 0122 30D1 bne .L36 +1293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until TCR flag is set */ +1295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + 909 .loc 1 1295 13 + 910 0124 7B69 ldr r3, [r7, #20] + 911 0126 0093 str r3, [sp] + 912 0128 3B6A ldr r3, [r7, #32] + 913 012a 0022 movs r2, #0 + 914 012c 8021 movs r1, #128 + 915 012e F868 ldr r0, [r7, #12] + 916 0130 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 917 0134 0346 mov r3, r0 + 918 .loc 1 1295 12 discriminator 1 + 919 0136 002B cmp r3, #0 + 920 0138 01D0 beq .L39 +1296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 921 .loc 1 1297 18 + 922 013a 0123 movs r3, #1 + 923 013c 4DE0 b .L32 + 924 .L39: +1298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) + 925 .loc 1 1300 17 + 926 013e FB68 ldr r3, [r7, #12] + 927 0140 5B8D ldrh r3, [r3, #42] @ movhi + 928 0142 9BB2 uxth r3, r3 + 929 .loc 1 1300 12 + ARM GAS /tmp/cc5G5cqz.s page 40 + + + 930 0144 FF2B cmp r3, #255 + 931 0146 0ED9 bls .L40 +1301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; + 932 .loc 1 1302 26 + 933 0148 FB68 ldr r3, [r7, #12] + 934 014a FF22 movs r2, #255 + 935 014c 1A85 strh r2, [r3, #40] @ movhi +1303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 936 .loc 1 1303 61 + 937 014e FB68 ldr r3, [r7, #12] + 938 0150 1B8D ldrh r3, [r3, #40] + 939 .loc 1 1303 11 + 940 0152 DAB2 uxtb r2, r3 + 941 0154 7989 ldrh r1, [r7, #10] + 942 0156 0023 movs r3, #0 + 943 0158 0093 str r3, [sp] + 944 015a 4FF08073 mov r3, #16777216 + 945 015e F868 ldr r0, [r7, #12] + 946 0160 FFF7FEFF bl I2C_TransferConfig + 947 0164 0FE0 b .L36 + 948 .L40: +1304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_NO_STARTSTOP); +1305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +1307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 949 .loc 1 1308 32 + 950 0166 FB68 ldr r3, [r7, #12] + 951 0168 5B8D ldrh r3, [r3, #42] @ movhi + 952 016a 9AB2 uxth r2, r3 + 953 .loc 1 1308 26 + 954 016c FB68 ldr r3, [r7, #12] + 955 016e 1A85 strh r2, [r3, #40] @ movhi +1309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 956 .loc 1 1309 61 + 957 0170 FB68 ldr r3, [r7, #12] + 958 0172 1B8D ldrh r3, [r3, #40] + 959 .loc 1 1309 11 + 960 0174 DAB2 uxtb r2, r3 + 961 0176 7989 ldrh r1, [r7, #10] + 962 0178 0023 movs r3, #0 + 963 017a 0093 str r3, [sp] + 964 017c 4FF00073 mov r3, #33554432 + 965 0180 F868 ldr r0, [r7, #12] + 966 0182 FFF7FEFF bl I2C_TransferConfig + 967 .L36: +1275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 968 .loc 1 1275 16 + 969 0186 FB68 ldr r3, [r7, #12] + 970 0188 5B8D ldrh r3, [r3, #42] @ movhi + 971 018a 9BB2 uxth r3, r3 +1275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 972 .loc 1 1275 28 + 973 018c 002B cmp r3, #0 + 974 018e 9DD1 bne .L41 +1310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_NO_STARTSTOP); + ARM GAS /tmp/cc5G5cqz.s page 41 + + +1311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ +1316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until STOPF flag is set */ +1317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + 975 .loc 1 1317 9 + 976 0190 7A69 ldr r2, [r7, #20] + 977 0192 396A ldr r1, [r7, #32] + 978 0194 F868 ldr r0, [r7, #12] + 979 0196 FFF7FEFF bl I2C_WaitOnSTOPFlagUntilTimeout + 980 019a 0346 mov r3, r0 + 981 .loc 1 1317 8 discriminator 1 + 982 019c 002B cmp r3, #0 + 983 019e 01D0 beq .L42 +1318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 984 .loc 1 1319 14 + 985 01a0 0123 movs r3, #1 + 986 01a2 1AE0 b .L32 + 987 .L42: +1320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear STOP Flag */ +1323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + 988 .loc 1 1323 5 + 989 01a4 FB68 ldr r3, [r7, #12] + 990 01a6 1B68 ldr r3, [r3] + 991 01a8 2022 movs r2, #32 + 992 01aa DA61 str r2, [r3, #28] +1324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear Configuration Register 2 */ +1326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_RESET_CR2(hi2c); + 993 .loc 1 1326 5 + 994 01ac FB68 ldr r3, [r7, #12] + 995 01ae 1B68 ldr r3, [r3] + 996 01b0 5968 ldr r1, [r3, #4] + 997 01b2 FB68 ldr r3, [r7, #12] + 998 01b4 1A68 ldr r2, [r3] + 999 01b6 0C4B ldr r3, .L43+4 + 1000 01b8 0B40 ands r3, r3, r1 + 1001 01ba 5360 str r3, [r2, #4] +1327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 1002 .loc 1 1328 17 + 1003 01bc FB68 ldr r3, [r7, #12] + 1004 01be 2022 movs r2, #32 + 1005 01c0 83F84120 strb r2, [r3, #65] +1329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 1006 .loc 1 1329 17 + 1007 01c4 FB68 ldr r3, [r7, #12] + 1008 01c6 0022 movs r2, #0 + 1009 01c8 83F84220 strb r2, [r3, #66] +1330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +1332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + ARM GAS /tmp/cc5G5cqz.s page 42 + + + 1010 .loc 1 1332 5 + 1011 01cc FB68 ldr r3, [r7, #12] + 1012 01ce 0022 movs r2, #0 + 1013 01d0 83F84020 strb r2, [r3, #64] +1333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; + 1014 .loc 1 1334 12 + 1015 01d4 0023 movs r3, #0 + 1016 01d6 00E0 b .L32 + 1017 .L30: +1335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +1337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; + 1018 .loc 1 1338 12 + 1019 01d8 0223 movs r3, #2 + 1020 .L32: +1339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 1021 .loc 1 1340 1 + 1022 01da 1846 mov r0, r3 + 1023 01dc 1837 adds r7, r7, #24 + 1024 .cfi_def_cfa_offset 8 + 1025 01de BD46 mov sp, r7 + 1026 .cfi_def_cfa_register 13 + 1027 @ sp needed + 1028 01e0 80BD pop {r7, pc} + 1029 .L44: + 1030 01e2 00BF .align 2 + 1031 .L43: + 1032 01e4 00240080 .word -2147474432 + 1033 01e8 00E800FE .word -33495040 + 1034 .cfi_endproc + 1035 .LFE135: + 1037 .section .text.HAL_I2C_Slave_Transmit,"ax",%progbits + 1038 .align 1 + 1039 .global HAL_I2C_Slave_Transmit + 1040 .syntax unified + 1041 .thumb + 1042 .thumb_func + 1044 HAL_I2C_Slave_Transmit: + 1045 .LFB136: +1341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +1343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Transmits in slave mode an amount of data in blocking mode. +1344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +1346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer +1347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be sent +1348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Timeout Timeout duration +1349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +1350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +1351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, +1352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t Timeout) +1353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1046 .loc 1 1353 1 + 1047 .cfi_startproc + ARM GAS /tmp/cc5G5cqz.s page 43 + + + 1048 @ args = 0, pretend = 0, frame = 24 + 1049 @ frame_needed = 1, uses_anonymous_args = 0 + 1050 0000 80B5 push {r7, lr} + 1051 .cfi_def_cfa_offset 8 + 1052 .cfi_offset 7, -8 + 1053 .cfi_offset 14, -4 + 1054 0002 88B0 sub sp, sp, #32 + 1055 .cfi_def_cfa_offset 40 + 1056 0004 02AF add r7, sp, #8 + 1057 .cfi_def_cfa 7, 32 + 1058 0006 F860 str r0, [r7, #12] + 1059 0008 B960 str r1, [r7, #8] + 1060 000a 3B60 str r3, [r7] + 1061 000c 1346 mov r3, r2 @ movhi + 1062 000e FB80 strh r3, [r7, #6] @ movhi +1354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tickstart; +1355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 1063 .loc 1 1356 11 + 1064 0010 FB68 ldr r3, [r7, #12] + 1065 0012 93F84130 ldrb r3, [r3, #65] + 1066 0016 DBB2 uxtb r3, r3 + 1067 .loc 1 1356 6 + 1068 0018 202B cmp r3, #32 + 1069 001a 40F02081 bne .L46 +1357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) + 1070 .loc 1 1358 8 + 1071 001e BB68 ldr r3, [r7, #8] + 1072 0020 002B cmp r3, #0 + 1073 0022 02D0 beq .L47 + 1074 .loc 1 1358 25 discriminator 1 + 1075 0024 FB88 ldrh r3, [r7, #6] + 1076 0026 002B cmp r3, #0 + 1077 0028 05D1 bne .L48 + 1078 .L47: +1359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + 1079 .loc 1 1360 23 + 1080 002a FB68 ldr r3, [r7, #12] + 1081 002c 4FF40072 mov r2, #512 + 1082 0030 5A64 str r2, [r3, #68] +1361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 1083 .loc 1 1361 15 + 1084 0032 0123 movs r3, #1 + 1085 0034 14E1 b .L49 + 1086 .L48: +1362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +1364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); + 1087 .loc 1 1364 5 + 1088 0036 FB68 ldr r3, [r7, #12] + 1089 0038 93F84030 ldrb r3, [r3, #64] @ zero_extendqisi2 + 1090 003c 012B cmp r3, #1 + 1091 003e 01D1 bne .L50 + 1092 .loc 1 1364 5 is_stmt 0 discriminator 1 + 1093 0040 0223 movs r3, #2 + ARM GAS /tmp/cc5G5cqz.s page 44 + + + 1094 .loc 1 1364 5 + 1095 0042 0DE1 b .L49 + 1096 .L50: + 1097 .loc 1 1364 5 discriminator 2 + 1098 0044 FB68 ldr r3, [r7, #12] + 1099 0046 0122 movs r2, #1 + 1100 0048 83F84020 strb r2, [r3, #64] +1365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Init tickstart for timeout management*/ +1367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tickstart = HAL_GetTick(); + 1101 .loc 1 1367 17 is_stmt 1 + 1102 004c FFF7FEFF bl HAL_GetTick + 1103 0050 7861 str r0, [r7, #20] +1368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; + 1104 .loc 1 1369 21 + 1105 0052 FB68 ldr r3, [r7, #12] + 1106 0054 2122 movs r2, #33 + 1107 0056 83F84120 strb r2, [r3, #65] +1370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 1108 .loc 1 1370 21 + 1109 005a FB68 ldr r3, [r7, #12] + 1110 005c 2022 movs r2, #32 + 1111 005e 83F84220 strb r2, [r3, #66] +1371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 1112 .loc 1 1371 21 + 1113 0062 FB68 ldr r3, [r7, #12] + 1114 0064 0022 movs r2, #0 + 1115 0066 5A64 str r2, [r3, #68] +1372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ +1374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; + 1116 .loc 1 1374 21 + 1117 0068 FB68 ldr r3, [r7, #12] + 1118 006a BA68 ldr r2, [r7, #8] + 1119 006c 5A62 str r2, [r3, #36] +1375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 1120 .loc 1 1375 21 + 1121 006e FB68 ldr r3, [r7, #12] + 1122 0070 FA88 ldrh r2, [r7, #6] @ movhi + 1123 0072 5A85 strh r2, [r3, #42] @ movhi +1376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = NULL; + 1124 .loc 1 1376 21 + 1125 0074 FB68 ldr r3, [r7, #12] + 1126 0076 0022 movs r2, #0 + 1127 0078 5A63 str r2, [r3, #52] +1377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable Address Acknowledge */ +1379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + 1128 .loc 1 1379 9 + 1129 007a FB68 ldr r3, [r7, #12] + 1130 007c 1B68 ldr r3, [r3] + 1131 .loc 1 1379 19 + 1132 007e 5A68 ldr r2, [r3, #4] + 1133 .loc 1 1379 9 + 1134 0080 FB68 ldr r3, [r7, #12] + 1135 0082 1B68 ldr r3, [r3] + ARM GAS /tmp/cc5G5cqz.s page 45 + + + 1136 .loc 1 1379 25 + 1137 0084 22F40042 bic r2, r2, #32768 + 1138 0088 5A60 str r2, [r3, #4] +1380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until ADDR flag is set */ +1382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + 1139 .loc 1 1382 9 + 1140 008a 7B69 ldr r3, [r7, #20] + 1141 008c 0093 str r3, [sp] + 1142 008e 3B68 ldr r3, [r7] + 1143 0090 0022 movs r2, #0 + 1144 0092 0821 movs r1, #8 + 1145 0094 F868 ldr r0, [r7, #12] + 1146 0096 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 1147 009a 0346 mov r3, r0 + 1148 .loc 1 1382 8 discriminator 1 + 1149 009c 002B cmp r3, #0 + 1150 009e 09D0 beq .L51 +1383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; + 1151 .loc 1 1385 11 + 1152 00a0 FB68 ldr r3, [r7, #12] + 1153 00a2 1B68 ldr r3, [r3] + 1154 .loc 1 1385 21 + 1155 00a4 5A68 ldr r2, [r3, #4] + 1156 .loc 1 1385 11 + 1157 00a6 FB68 ldr r3, [r7, #12] + 1158 00a8 1B68 ldr r3, [r3] + 1159 .loc 1 1385 27 + 1160 00aa 42F40042 orr r2, r2, #32768 + 1161 00ae 5A60 str r2, [r3, #4] +1386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 1162 .loc 1 1386 14 + 1163 00b0 0123 movs r3, #1 + 1164 00b2 D5E0 b .L49 + 1165 .L51: +1387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Preload TX data if no stretch enable */ +1390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) + 1166 .loc 1 1390 19 + 1167 00b4 FB68 ldr r3, [r7, #12] + 1168 00b6 1B6A ldr r3, [r3, #32] + 1169 .loc 1 1390 8 + 1170 00b8 B3F5003F cmp r3, #131072 + 1171 00bc 11D1 bne .L52 +1391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Preload TX register */ +1393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Write data to TXDR */ +1394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->TXDR = *hi2c->pBuffPtr; + 1172 .loc 1 1394 35 + 1173 00be FB68 ldr r3, [r7, #12] + 1174 00c0 5B6A ldr r3, [r3, #36] + 1175 .loc 1 1394 30 + 1176 00c2 1A78 ldrb r2, [r3] @ zero_extendqisi2 + 1177 .loc 1 1394 11 + ARM GAS /tmp/cc5G5cqz.s page 46 + + + 1178 00c4 FB68 ldr r3, [r7, #12] + 1179 00c6 1B68 ldr r3, [r3] + 1180 .loc 1 1394 28 + 1181 00c8 9A62 str r2, [r3, #40] +1395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Increment Buffer pointer */ +1397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr++; + 1182 .loc 1 1397 11 + 1183 00ca FB68 ldr r3, [r7, #12] + 1184 00cc 5B6A ldr r3, [r3, #36] + 1185 .loc 1 1397 21 + 1186 00ce 5A1C adds r2, r3, #1 + 1187 00d0 FB68 ldr r3, [r7, #12] + 1188 00d2 5A62 str r2, [r3, #36] +1398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount--; + 1189 .loc 1 1399 11 + 1190 00d4 FB68 ldr r3, [r7, #12] + 1191 00d6 5B8D ldrh r3, [r3, #42] @ movhi + 1192 00d8 9BB2 uxth r3, r3 + 1193 .loc 1 1399 22 + 1194 00da 013B subs r3, r3, #1 + 1195 00dc 9AB2 uxth r2, r3 + 1196 00de FB68 ldr r3, [r7, #12] + 1197 00e0 5A85 strh r2, [r3, #42] @ movhi + 1198 .L52: +1400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear ADDR flag */ +1403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + 1199 .loc 1 1403 5 + 1200 00e2 FB68 ldr r3, [r7, #12] + 1201 00e4 1B68 ldr r3, [r3] + 1202 00e6 0822 movs r2, #8 + 1203 00e8 DA61 str r2, [r3, #28] +1404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* If 10bit addressing mode is selected */ +1406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + 1204 .loc 1 1406 19 + 1205 00ea FB68 ldr r3, [r7, #12] + 1206 00ec DB68 ldr r3, [r3, #12] + 1207 .loc 1 1406 8 + 1208 00ee 022B cmp r3, #2 + 1209 00f0 18D1 bne .L53 +1407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until ADDR flag is set */ +1409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + 1210 .loc 1 1409 11 + 1211 00f2 7B69 ldr r3, [r7, #20] + 1212 00f4 0093 str r3, [sp] + 1213 00f6 3B68 ldr r3, [r7] + 1214 00f8 0022 movs r2, #0 + 1215 00fa 0821 movs r1, #8 + 1216 00fc F868 ldr r0, [r7, #12] + 1217 00fe FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 1218 0102 0346 mov r3, r0 + 1219 .loc 1 1409 10 discriminator 1 + ARM GAS /tmp/cc5G5cqz.s page 47 + + + 1220 0104 002B cmp r3, #0 + 1221 0106 09D0 beq .L54 +1410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; + 1222 .loc 1 1412 13 + 1223 0108 FB68 ldr r3, [r7, #12] + 1224 010a 1B68 ldr r3, [r3] + 1225 .loc 1 1412 23 + 1226 010c 5A68 ldr r2, [r3, #4] + 1227 .loc 1 1412 13 + 1228 010e FB68 ldr r3, [r7, #12] + 1229 0110 1B68 ldr r3, [r3] + 1230 .loc 1 1412 29 + 1231 0112 42F40042 orr r2, r2, #32768 + 1232 0116 5A60 str r2, [r3, #4] +1413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 1233 .loc 1 1413 16 + 1234 0118 0123 movs r3, #1 + 1235 011a A1E0 b .L49 + 1236 .L54: +1414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear ADDR flag */ +1417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + 1237 .loc 1 1417 7 + 1238 011c FB68 ldr r3, [r7, #12] + 1239 011e 1B68 ldr r3, [r3] + 1240 0120 0822 movs r2, #8 + 1241 0122 DA61 str r2, [r3, #28] + 1242 .L53: +1418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until DIR flag is set Transmitter mode */ +1421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK) + 1243 .loc 1 1421 9 + 1244 0124 7B69 ldr r3, [r7, #20] + 1245 0126 0093 str r3, [sp] + 1246 0128 3B68 ldr r3, [r7] + 1247 012a 0022 movs r2, #0 + 1248 012c 4FF48031 mov r1, #65536 + 1249 0130 F868 ldr r0, [r7, #12] + 1250 0132 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 1251 0136 0346 mov r3, r0 + 1252 .loc 1 1421 8 discriminator 1 + 1253 0138 002B cmp r3, #0 + 1254 013a 2DD0 beq .L56 +1422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; + 1255 .loc 1 1424 11 + 1256 013c FB68 ldr r3, [r7, #12] + 1257 013e 1B68 ldr r3, [r3] + 1258 .loc 1 1424 21 + 1259 0140 5A68 ldr r2, [r3, #4] + 1260 .loc 1 1424 11 + 1261 0142 FB68 ldr r3, [r7, #12] + ARM GAS /tmp/cc5G5cqz.s page 48 + + + 1262 0144 1B68 ldr r3, [r3] + 1263 .loc 1 1424 27 + 1264 0146 42F40042 orr r2, r2, #32768 + 1265 014a 5A60 str r2, [r3, #4] +1425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 1266 .loc 1 1425 14 + 1267 014c 0123 movs r3, #1 + 1268 014e 87E0 b .L49 + 1269 .L58: +1426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** while (hi2c->XferCount > 0U) +1429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until TXIS flag is set */ +1431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + 1270 .loc 1 1431 11 + 1271 0150 7A69 ldr r2, [r7, #20] + 1272 0152 3968 ldr r1, [r7] + 1273 0154 F868 ldr r0, [r7, #12] + 1274 0156 FFF7FEFF bl I2C_WaitOnTXISFlagUntilTimeout + 1275 015a 0346 mov r3, r0 + 1276 .loc 1 1431 10 discriminator 1 + 1277 015c 002B cmp r3, #0 + 1278 015e 09D0 beq .L57 +1432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; + 1279 .loc 1 1434 13 + 1280 0160 FB68 ldr r3, [r7, #12] + 1281 0162 1B68 ldr r3, [r3] + 1282 .loc 1 1434 23 + 1283 0164 5A68 ldr r2, [r3, #4] + 1284 .loc 1 1434 13 + 1285 0166 FB68 ldr r3, [r7, #12] + 1286 0168 1B68 ldr r3, [r3] + 1287 .loc 1 1434 29 + 1288 016a 42F40042 orr r2, r2, #32768 + 1289 016e 5A60 str r2, [r3, #4] +1435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 1290 .loc 1 1435 16 + 1291 0170 0123 movs r3, #1 + 1292 0172 75E0 b .L49 + 1293 .L57: +1436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Write data to TXDR */ +1439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->TXDR = *hi2c->pBuffPtr; + 1294 .loc 1 1439 35 + 1295 0174 FB68 ldr r3, [r7, #12] + 1296 0176 5B6A ldr r3, [r3, #36] + 1297 .loc 1 1439 30 + 1298 0178 1A78 ldrb r2, [r3] @ zero_extendqisi2 + 1299 .loc 1 1439 11 + 1300 017a FB68 ldr r3, [r7, #12] + 1301 017c 1B68 ldr r3, [r3] + 1302 .loc 1 1439 28 + 1303 017e 9A62 str r2, [r3, #40] + ARM GAS /tmp/cc5G5cqz.s page 49 + + +1440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Increment Buffer pointer */ +1442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr++; + 1304 .loc 1 1442 11 + 1305 0180 FB68 ldr r3, [r7, #12] + 1306 0182 5B6A ldr r3, [r3, #36] + 1307 .loc 1 1442 21 + 1308 0184 5A1C adds r2, r3, #1 + 1309 0186 FB68 ldr r3, [r7, #12] + 1310 0188 5A62 str r2, [r3, #36] +1443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount--; + 1311 .loc 1 1444 11 + 1312 018a FB68 ldr r3, [r7, #12] + 1313 018c 5B8D ldrh r3, [r3, #42] @ movhi + 1314 018e 9BB2 uxth r3, r3 + 1315 .loc 1 1444 22 + 1316 0190 013B subs r3, r3, #1 + 1317 0192 9AB2 uxth r2, r3 + 1318 0194 FB68 ldr r3, [r7, #12] + 1319 0196 5A85 strh r2, [r3, #42] @ movhi + 1320 .L56: +1428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1321 .loc 1 1428 16 + 1322 0198 FB68 ldr r3, [r7, #12] + 1323 019a 5B8D ldrh r3, [r3, #42] @ movhi + 1324 019c 9BB2 uxth r3, r3 +1428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1325 .loc 1 1428 28 + 1326 019e 002B cmp r3, #0 + 1327 01a0 D6D1 bne .L58 +1445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until AF flag is set */ +1448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK) + 1328 .loc 1 1448 9 + 1329 01a2 7B69 ldr r3, [r7, #20] + 1330 01a4 0093 str r3, [sp] + 1331 01a6 3B68 ldr r3, [r7] + 1332 01a8 0022 movs r2, #0 + 1333 01aa 1021 movs r1, #16 + 1334 01ac F868 ldr r0, [r7, #12] + 1335 01ae FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 1336 01b2 0346 mov r3, r0 + 1337 .loc 1 1448 8 discriminator 1 + 1338 01b4 002B cmp r3, #0 + 1339 01b6 09D0 beq .L59 +1449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; + 1340 .loc 1 1451 11 + 1341 01b8 FB68 ldr r3, [r7, #12] + 1342 01ba 1B68 ldr r3, [r3] + 1343 .loc 1 1451 21 + 1344 01bc 5A68 ldr r2, [r3, #4] + 1345 .loc 1 1451 11 + 1346 01be FB68 ldr r3, [r7, #12] + ARM GAS /tmp/cc5G5cqz.s page 50 + + + 1347 01c0 1B68 ldr r3, [r3] + 1348 .loc 1 1451 27 + 1349 01c2 42F40042 orr r2, r2, #32768 + 1350 01c6 5A60 str r2, [r3, #4] +1452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 1351 .loc 1 1452 14 + 1352 01c8 0123 movs r3, #1 + 1353 01ca 49E0 b .L49 + 1354 .L59: +1453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Flush TX register */ +1456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); + 1355 .loc 1 1456 5 + 1356 01cc F868 ldr r0, [r7, #12] + 1357 01ce FFF7FEFF bl I2C_Flush_TXDR +1457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear AF flag */ +1459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + 1358 .loc 1 1459 5 + 1359 01d2 FB68 ldr r3, [r7, #12] + 1360 01d4 1B68 ldr r3, [r3] + 1361 01d6 1022 movs r2, #16 + 1362 01d8 DA61 str r2, [r3, #28] +1460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until STOP flag is set */ +1462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + 1363 .loc 1 1462 9 + 1364 01da 7A69 ldr r2, [r7, #20] + 1365 01dc 3968 ldr r1, [r7] + 1366 01de F868 ldr r0, [r7, #12] + 1367 01e0 FFF7FEFF bl I2C_WaitOnSTOPFlagUntilTimeout + 1368 01e4 0346 mov r3, r0 + 1369 .loc 1 1462 8 discriminator 1 + 1370 01e6 002B cmp r3, #0 + 1371 01e8 09D0 beq .L60 +1463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; + 1372 .loc 1 1465 11 + 1373 01ea FB68 ldr r3, [r7, #12] + 1374 01ec 1B68 ldr r3, [r3] + 1375 .loc 1 1465 21 + 1376 01ee 5A68 ldr r2, [r3, #4] + 1377 .loc 1 1465 11 + 1378 01f0 FB68 ldr r3, [r7, #12] + 1379 01f2 1B68 ldr r3, [r3] + 1380 .loc 1 1465 27 + 1381 01f4 42F40042 orr r2, r2, #32768 + 1382 01f8 5A60 str r2, [r3, #4] +1466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 1383 .loc 1 1467 14 + 1384 01fa 0123 movs r3, #1 + 1385 01fc 30E0 b .L49 + 1386 .L60: +1468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/cc5G5cqz.s page 51 + + +1469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear STOP flag */ +1471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + 1387 .loc 1 1471 5 + 1388 01fe FB68 ldr r3, [r7, #12] + 1389 0200 1B68 ldr r3, [r3] + 1390 0202 2022 movs r2, #32 + 1391 0204 DA61 str r2, [r3, #28] +1472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until BUSY flag is reset */ +1474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) + 1392 .loc 1 1474 9 + 1393 0206 7B69 ldr r3, [r7, #20] + 1394 0208 0093 str r3, [sp] + 1395 020a 3B68 ldr r3, [r7] + 1396 020c 0122 movs r2, #1 + 1397 020e 4FF40041 mov r1, #32768 + 1398 0212 F868 ldr r0, [r7, #12] + 1399 0214 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 1400 0218 0346 mov r3, r0 + 1401 .loc 1 1474 8 discriminator 1 + 1402 021a 002B cmp r3, #0 + 1403 021c 09D0 beq .L61 +1475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; + 1404 .loc 1 1477 11 + 1405 021e FB68 ldr r3, [r7, #12] + 1406 0220 1B68 ldr r3, [r3] + 1407 .loc 1 1477 21 + 1408 0222 5A68 ldr r2, [r3, #4] + 1409 .loc 1 1477 11 + 1410 0224 FB68 ldr r3, [r7, #12] + 1411 0226 1B68 ldr r3, [r3] + 1412 .loc 1 1477 27 + 1413 0228 42F40042 orr r2, r2, #32768 + 1414 022c 5A60 str r2, [r3, #4] +1478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 1415 .loc 1 1478 14 + 1416 022e 0123 movs r3, #1 + 1417 0230 16E0 b .L49 + 1418 .L61: +1479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; + 1419 .loc 1 1482 9 + 1420 0232 FB68 ldr r3, [r7, #12] + 1421 0234 1B68 ldr r3, [r3] + 1422 .loc 1 1482 19 + 1423 0236 5A68 ldr r2, [r3, #4] + 1424 .loc 1 1482 9 + 1425 0238 FB68 ldr r3, [r7, #12] + 1426 023a 1B68 ldr r3, [r3] + 1427 .loc 1 1482 25 + 1428 023c 42F40042 orr r2, r2, #32768 + 1429 0240 5A60 str r2, [r3, #4] + ARM GAS /tmp/cc5G5cqz.s page 52 + + +1483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 1430 .loc 1 1484 17 + 1431 0242 FB68 ldr r3, [r7, #12] + 1432 0244 2022 movs r2, #32 + 1433 0246 83F84120 strb r2, [r3, #65] +1485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 1434 .loc 1 1485 17 + 1435 024a FB68 ldr r3, [r7, #12] + 1436 024c 0022 movs r2, #0 + 1437 024e 83F84220 strb r2, [r3, #66] +1486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +1488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 1438 .loc 1 1488 5 + 1439 0252 FB68 ldr r3, [r7, #12] + 1440 0254 0022 movs r2, #0 + 1441 0256 83F84020 strb r2, [r3, #64] +1489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; + 1442 .loc 1 1490 12 + 1443 025a 0023 movs r3, #0 + 1444 025c 00E0 b .L49 + 1445 .L46: +1491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +1493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; + 1446 .loc 1 1494 12 + 1447 025e 0223 movs r3, #2 + 1448 .L49: +1495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 1449 .loc 1 1496 1 + 1450 0260 1846 mov r0, r3 + 1451 0262 1837 adds r7, r7, #24 + 1452 .cfi_def_cfa_offset 8 + 1453 0264 BD46 mov sp, r7 + 1454 .cfi_def_cfa_register 13 + 1455 @ sp needed + 1456 0266 80BD pop {r7, pc} + 1457 .cfi_endproc + 1458 .LFE136: + 1460 .section .text.HAL_I2C_Slave_Receive,"ax",%progbits + 1461 .align 1 + 1462 .global HAL_I2C_Slave_Receive + 1463 .syntax unified + 1464 .thumb + 1465 .thumb_func + 1467 HAL_I2C_Slave_Receive: + 1468 .LFB137: +1497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +1499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Receive in slave mode an amount of data in blocking mode +1500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +1502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer + ARM GAS /tmp/cc5G5cqz.s page 53 + + +1503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be sent +1504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Timeout Timeout duration +1505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +1506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +1507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, +1508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t Timeout) +1509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1469 .loc 1 1509 1 + 1470 .cfi_startproc + 1471 @ args = 0, pretend = 0, frame = 24 + 1472 @ frame_needed = 1, uses_anonymous_args = 0 + 1473 0000 80B5 push {r7, lr} + 1474 .cfi_def_cfa_offset 8 + 1475 .cfi_offset 7, -8 + 1476 .cfi_offset 14, -4 + 1477 0002 88B0 sub sp, sp, #32 + 1478 .cfi_def_cfa_offset 40 + 1479 0004 02AF add r7, sp, #8 + 1480 .cfi_def_cfa 7, 32 + 1481 0006 F860 str r0, [r7, #12] + 1482 0008 B960 str r1, [r7, #8] + 1483 000a 3B60 str r3, [r7] + 1484 000c 1346 mov r3, r2 @ movhi + 1485 000e FB80 strh r3, [r7, #6] @ movhi +1510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tickstart; +1511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 1486 .loc 1 1512 11 + 1487 0010 FB68 ldr r3, [r7, #12] + 1488 0012 93F84130 ldrb r3, [r3, #65] + 1489 0016 DBB2 uxtb r3, r3 + 1490 .loc 1 1512 6 + 1491 0018 202B cmp r3, #32 + 1492 001a 40F0FC80 bne .L63 +1513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) + 1493 .loc 1 1514 8 + 1494 001e BB68 ldr r3, [r7, #8] + 1495 0020 002B cmp r3, #0 + 1496 0022 02D0 beq .L64 + 1497 .loc 1 1514 25 discriminator 1 + 1498 0024 FB88 ldrh r3, [r7, #6] + 1499 0026 002B cmp r3, #0 + 1500 0028 05D1 bne .L65 + 1501 .L64: +1515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + 1502 .loc 1 1516 23 + 1503 002a FB68 ldr r3, [r7, #12] + 1504 002c 4FF40072 mov r2, #512 + 1505 0030 5A64 str r2, [r3, #68] +1517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 1506 .loc 1 1517 15 + 1507 0032 0123 movs r3, #1 + 1508 0034 F0E0 b .L66 + 1509 .L65: +1518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/cc5G5cqz.s page 54 + + +1519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +1520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); + 1510 .loc 1 1520 5 + 1511 0036 FB68 ldr r3, [r7, #12] + 1512 0038 93F84030 ldrb r3, [r3, #64] @ zero_extendqisi2 + 1513 003c 012B cmp r3, #1 + 1514 003e 01D1 bne .L67 + 1515 .loc 1 1520 5 is_stmt 0 discriminator 1 + 1516 0040 0223 movs r3, #2 + 1517 .loc 1 1520 5 + 1518 0042 E9E0 b .L66 + 1519 .L67: + 1520 .loc 1 1520 5 discriminator 2 + 1521 0044 FB68 ldr r3, [r7, #12] + 1522 0046 0122 movs r2, #1 + 1523 0048 83F84020 strb r2, [r3, #64] +1521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Init tickstart for timeout management*/ +1523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tickstart = HAL_GetTick(); + 1524 .loc 1 1523 17 is_stmt 1 + 1525 004c FFF7FEFF bl HAL_GetTick + 1526 0050 7861 str r0, [r7, #20] +1524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; + 1527 .loc 1 1525 21 + 1528 0052 FB68 ldr r3, [r7, #12] + 1529 0054 2222 movs r2, #34 + 1530 0056 83F84120 strb r2, [r3, #65] +1526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 1531 .loc 1 1526 21 + 1532 005a FB68 ldr r3, [r7, #12] + 1533 005c 2022 movs r2, #32 + 1534 005e 83F84220 strb r2, [r3, #66] +1527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 1535 .loc 1 1527 21 + 1536 0062 FB68 ldr r3, [r7, #12] + 1537 0064 0022 movs r2, #0 + 1538 0066 5A64 str r2, [r3, #68] +1528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ +1530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; + 1539 .loc 1 1530 21 + 1540 0068 FB68 ldr r3, [r7, #12] + 1541 006a BA68 ldr r2, [r7, #8] + 1542 006c 5A62 str r2, [r3, #36] +1531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 1543 .loc 1 1531 21 + 1544 006e FB68 ldr r3, [r7, #12] + 1545 0070 FA88 ldrh r2, [r7, #6] @ movhi + 1546 0072 5A85 strh r2, [r3, #42] @ movhi +1532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 1547 .loc 1 1532 26 + 1548 0074 FB68 ldr r3, [r7, #12] + 1549 0076 5B8D ldrh r3, [r3, #42] @ movhi + 1550 0078 9AB2 uxth r2, r3 + 1551 .loc 1 1532 20 + 1552 007a FB68 ldr r3, [r7, #12] + ARM GAS /tmp/cc5G5cqz.s page 55 + + + 1553 007c 1A85 strh r2, [r3, #40] @ movhi +1533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = NULL; + 1554 .loc 1 1533 21 + 1555 007e FB68 ldr r3, [r7, #12] + 1556 0080 0022 movs r2, #0 + 1557 0082 5A63 str r2, [r3, #52] +1534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable Address Acknowledge */ +1536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + 1558 .loc 1 1536 9 + 1559 0084 FB68 ldr r3, [r7, #12] + 1560 0086 1B68 ldr r3, [r3] + 1561 .loc 1 1536 19 + 1562 0088 5A68 ldr r2, [r3, #4] + 1563 .loc 1 1536 9 + 1564 008a FB68 ldr r3, [r7, #12] + 1565 008c 1B68 ldr r3, [r3] + 1566 .loc 1 1536 25 + 1567 008e 22F40042 bic r2, r2, #32768 + 1568 0092 5A60 str r2, [r3, #4] +1537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until ADDR flag is set */ +1539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + 1569 .loc 1 1539 9 + 1570 0094 7B69 ldr r3, [r7, #20] + 1571 0096 0093 str r3, [sp] + 1572 0098 3B68 ldr r3, [r7] + 1573 009a 0022 movs r2, #0 + 1574 009c 0821 movs r1, #8 + 1575 009e F868 ldr r0, [r7, #12] + 1576 00a0 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 1577 00a4 0346 mov r3, r0 + 1578 .loc 1 1539 8 discriminator 1 + 1579 00a6 002B cmp r3, #0 + 1580 00a8 09D0 beq .L68 +1540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; + 1581 .loc 1 1542 11 + 1582 00aa FB68 ldr r3, [r7, #12] + 1583 00ac 1B68 ldr r3, [r3] + 1584 .loc 1 1542 21 + 1585 00ae 5A68 ldr r2, [r3, #4] + 1586 .loc 1 1542 11 + 1587 00b0 FB68 ldr r3, [r7, #12] + 1588 00b2 1B68 ldr r3, [r3] + 1589 .loc 1 1542 27 + 1590 00b4 42F40042 orr r2, r2, #32768 + 1591 00b8 5A60 str r2, [r3, #4] +1543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 1592 .loc 1 1543 14 + 1593 00ba 0123 movs r3, #1 + 1594 00bc ACE0 b .L66 + 1595 .L68: +1544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear ADDR flag */ + ARM GAS /tmp/cc5G5cqz.s page 56 + + +1547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + 1596 .loc 1 1547 5 + 1597 00be FB68 ldr r3, [r7, #12] + 1598 00c0 1B68 ldr r3, [r3] + 1599 00c2 0822 movs r2, #8 + 1600 00c4 DA61 str r2, [r3, #28] +1548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until DIR flag is reset Receiver mode */ +1550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK) + 1601 .loc 1 1550 9 + 1602 00c6 7B69 ldr r3, [r7, #20] + 1603 00c8 0093 str r3, [sp] + 1604 00ca 3B68 ldr r3, [r7] + 1605 00cc 0122 movs r2, #1 + 1606 00ce 4FF48031 mov r1, #65536 + 1607 00d2 F868 ldr r0, [r7, #12] + 1608 00d4 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 1609 00d8 0346 mov r3, r0 + 1610 .loc 1 1550 8 discriminator 1 + 1611 00da 002B cmp r3, #0 + 1612 00dc 54D0 beq .L70 +1551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; + 1613 .loc 1 1553 11 + 1614 00de FB68 ldr r3, [r7, #12] + 1615 00e0 1B68 ldr r3, [r3] + 1616 .loc 1 1553 21 + 1617 00e2 5A68 ldr r2, [r3, #4] + 1618 .loc 1 1553 11 + 1619 00e4 FB68 ldr r3, [r7, #12] + 1620 00e6 1B68 ldr r3, [r3] + 1621 .loc 1 1553 27 + 1622 00e8 42F40042 orr r2, r2, #32768 + 1623 00ec 5A60 str r2, [r3, #4] +1554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 1624 .loc 1 1554 14 + 1625 00ee 0123 movs r3, #1 + 1626 00f0 92E0 b .L66 + 1627 .L73: +1555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** while (hi2c->XferCount > 0U) +1558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until RXNE flag is set */ +1560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + 1628 .loc 1 1560 11 + 1629 00f2 7A69 ldr r2, [r7, #20] + 1630 00f4 3968 ldr r1, [r7] + 1631 00f6 F868 ldr r0, [r7, #12] + 1632 00f8 FFF7FEFF bl I2C_WaitOnRXNEFlagUntilTimeout + 1633 00fc 0346 mov r3, r0 + 1634 .loc 1 1560 10 discriminator 1 + 1635 00fe 002B cmp r3, #0 + 1636 0100 29D0 beq .L71 +1561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Address Acknowledge */ + ARM GAS /tmp/cc5G5cqz.s page 57 + + +1563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; + 1637 .loc 1 1563 13 + 1638 0102 FB68 ldr r3, [r7, #12] + 1639 0104 1B68 ldr r3, [r3] + 1640 .loc 1 1563 23 + 1641 0106 5A68 ldr r2, [r3, #4] + 1642 .loc 1 1563 13 + 1643 0108 FB68 ldr r3, [r7, #12] + 1644 010a 1B68 ldr r3, [r3] + 1645 .loc 1 1563 29 + 1646 010c 42F40042 orr r2, r2, #32768 + 1647 0110 5A60 str r2, [r3, #4] +1564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Store Last receive data if any */ +1566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + 1648 .loc 1 1566 13 + 1649 0112 FB68 ldr r3, [r7, #12] + 1650 0114 1B68 ldr r3, [r3] + 1651 0116 9B69 ldr r3, [r3, #24] + 1652 0118 03F00403 and r3, r3, #4 + 1653 .loc 1 1566 12 + 1654 011c 042B cmp r3, #4 + 1655 011e 18D1 bne .L72 +1567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Read data from RXDR */ +1569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + 1656 .loc 1 1569 42 + 1657 0120 FB68 ldr r3, [r7, #12] + 1658 0122 1B68 ldr r3, [r3] + 1659 .loc 1 1569 52 + 1660 0124 5A6A ldr r2, [r3, #36] + 1661 .loc 1 1569 16 + 1662 0126 FB68 ldr r3, [r7, #12] + 1663 0128 5B6A ldr r3, [r3, #36] + 1664 .loc 1 1569 29 + 1665 012a D2B2 uxtb r2, r2 + 1666 .loc 1 1569 27 + 1667 012c 1A70 strb r2, [r3] +1570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Increment Buffer pointer */ +1572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr++; + 1668 .loc 1 1572 15 + 1669 012e FB68 ldr r3, [r7, #12] + 1670 0130 5B6A ldr r3, [r3, #36] + 1671 .loc 1 1572 25 + 1672 0132 5A1C adds r2, r3, #1 + 1673 0134 FB68 ldr r3, [r7, #12] + 1674 0136 5A62 str r2, [r3, #36] +1573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount--; + 1675 .loc 1 1574 15 + 1676 0138 FB68 ldr r3, [r7, #12] + 1677 013a 5B8D ldrh r3, [r3, #42] @ movhi + 1678 013c 9BB2 uxth r3, r3 + 1679 .loc 1 1574 26 + 1680 013e 013B subs r3, r3, #1 + 1681 0140 9AB2 uxth r2, r3 + ARM GAS /tmp/cc5G5cqz.s page 58 + + + 1682 0142 FB68 ldr r3, [r7, #12] + 1683 0144 5A85 strh r2, [r3, #42] @ movhi +1575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize--; + 1684 .loc 1 1575 15 + 1685 0146 FB68 ldr r3, [r7, #12] + 1686 0148 1B8D ldrh r3, [r3, #40] + 1687 .loc 1 1575 25 + 1688 014a 013B subs r3, r3, #1 + 1689 014c 9AB2 uxth r2, r3 + 1690 014e FB68 ldr r3, [r7, #12] + 1691 0150 1A85 strh r2, [r3, #40] @ movhi + 1692 .L72: +1576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 1693 .loc 1 1578 16 + 1694 0152 0123 movs r3, #1 + 1695 0154 60E0 b .L66 + 1696 .L71: +1579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Read data from RXDR */ +1582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + 1697 .loc 1 1582 38 + 1698 0156 FB68 ldr r3, [r7, #12] + 1699 0158 1B68 ldr r3, [r3] + 1700 .loc 1 1582 48 + 1701 015a 5A6A ldr r2, [r3, #36] + 1702 .loc 1 1582 12 + 1703 015c FB68 ldr r3, [r7, #12] + 1704 015e 5B6A ldr r3, [r3, #36] + 1705 .loc 1 1582 25 + 1706 0160 D2B2 uxtb r2, r2 + 1707 .loc 1 1582 23 + 1708 0162 1A70 strb r2, [r3] +1583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Increment Buffer pointer */ +1585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr++; + 1709 .loc 1 1585 11 + 1710 0164 FB68 ldr r3, [r7, #12] + 1711 0166 5B6A ldr r3, [r3, #36] + 1712 .loc 1 1585 21 + 1713 0168 5A1C adds r2, r3, #1 + 1714 016a FB68 ldr r3, [r7, #12] + 1715 016c 5A62 str r2, [r3, #36] +1586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount--; + 1716 .loc 1 1587 11 + 1717 016e FB68 ldr r3, [r7, #12] + 1718 0170 5B8D ldrh r3, [r3, #42] @ movhi + 1719 0172 9BB2 uxth r3, r3 + 1720 .loc 1 1587 22 + 1721 0174 013B subs r3, r3, #1 + 1722 0176 9AB2 uxth r2, r3 + 1723 0178 FB68 ldr r3, [r7, #12] + 1724 017a 5A85 strh r2, [r3, #42] @ movhi +1588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize--; + ARM GAS /tmp/cc5G5cqz.s page 59 + + + 1725 .loc 1 1588 11 + 1726 017c FB68 ldr r3, [r7, #12] + 1727 017e 1B8D ldrh r3, [r3, #40] + 1728 .loc 1 1588 21 + 1729 0180 013B subs r3, r3, #1 + 1730 0182 9AB2 uxth r2, r3 + 1731 0184 FB68 ldr r3, [r7, #12] + 1732 0186 1A85 strh r2, [r3, #40] @ movhi + 1733 .L70: +1557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1734 .loc 1 1557 16 + 1735 0188 FB68 ldr r3, [r7, #12] + 1736 018a 5B8D ldrh r3, [r3, #42] @ movhi + 1737 018c 9BB2 uxth r3, r3 +1557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1738 .loc 1 1557 28 + 1739 018e 002B cmp r3, #0 + 1740 0190 AFD1 bne .L73 +1589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until STOP flag is set */ +1592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + 1741 .loc 1 1592 9 + 1742 0192 7A69 ldr r2, [r7, #20] + 1743 0194 3968 ldr r1, [r7] + 1744 0196 F868 ldr r0, [r7, #12] + 1745 0198 FFF7FEFF bl I2C_WaitOnSTOPFlagUntilTimeout + 1746 019c 0346 mov r3, r0 + 1747 .loc 1 1592 8 discriminator 1 + 1748 019e 002B cmp r3, #0 + 1749 01a0 09D0 beq .L74 +1593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; + 1750 .loc 1 1595 11 + 1751 01a2 FB68 ldr r3, [r7, #12] + 1752 01a4 1B68 ldr r3, [r3] + 1753 .loc 1 1595 21 + 1754 01a6 5A68 ldr r2, [r3, #4] + 1755 .loc 1 1595 11 + 1756 01a8 FB68 ldr r3, [r7, #12] + 1757 01aa 1B68 ldr r3, [r3] + 1758 .loc 1 1595 27 + 1759 01ac 42F40042 orr r2, r2, #32768 + 1760 01b0 5A60 str r2, [r3, #4] +1596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 1761 .loc 1 1596 14 + 1762 01b2 0123 movs r3, #1 + 1763 01b4 30E0 b .L66 + 1764 .L74: +1597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear STOP flag */ +1600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + 1765 .loc 1 1600 5 + 1766 01b6 FB68 ldr r3, [r7, #12] + 1767 01b8 1B68 ldr r3, [r3] + ARM GAS /tmp/cc5G5cqz.s page 60 + + + 1768 01ba 2022 movs r2, #32 + 1769 01bc DA61 str r2, [r3, #28] +1601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1602:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until BUSY flag is reset */ +1603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) + 1770 .loc 1 1603 9 + 1771 01be 7B69 ldr r3, [r7, #20] + 1772 01c0 0093 str r3, [sp] + 1773 01c2 3B68 ldr r3, [r7] + 1774 01c4 0122 movs r2, #1 + 1775 01c6 4FF40041 mov r1, #32768 + 1776 01ca F868 ldr r0, [r7, #12] + 1777 01cc FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 1778 01d0 0346 mov r3, r0 + 1779 .loc 1 1603 8 discriminator 1 + 1780 01d2 002B cmp r3, #0 + 1781 01d4 09D0 beq .L75 +1604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; + 1782 .loc 1 1606 11 + 1783 01d6 FB68 ldr r3, [r7, #12] + 1784 01d8 1B68 ldr r3, [r3] + 1785 .loc 1 1606 21 + 1786 01da 5A68 ldr r2, [r3, #4] + 1787 .loc 1 1606 11 + 1788 01dc FB68 ldr r3, [r7, #12] + 1789 01de 1B68 ldr r3, [r3] + 1790 .loc 1 1606 27 + 1791 01e0 42F40042 orr r2, r2, #32768 + 1792 01e4 5A60 str r2, [r3, #4] +1607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 1793 .loc 1 1607 14 + 1794 01e6 0123 movs r3, #1 + 1795 01e8 16E0 b .L66 + 1796 .L75: +1608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Address Acknowledge */ +1611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; + 1797 .loc 1 1611 9 + 1798 01ea FB68 ldr r3, [r7, #12] + 1799 01ec 1B68 ldr r3, [r3] + 1800 .loc 1 1611 19 + 1801 01ee 5A68 ldr r2, [r3, #4] + 1802 .loc 1 1611 9 + 1803 01f0 FB68 ldr r3, [r7, #12] + 1804 01f2 1B68 ldr r3, [r3] + 1805 .loc 1 1611 25 + 1806 01f4 42F40042 orr r2, r2, #32768 + 1807 01f8 5A60 str r2, [r3, #4] +1612:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 1808 .loc 1 1613 17 + 1809 01fa FB68 ldr r3, [r7, #12] + 1810 01fc 2022 movs r2, #32 + 1811 01fe 83F84120 strb r2, [r3, #65] + ARM GAS /tmp/cc5G5cqz.s page 61 + + +1614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 1812 .loc 1 1614 17 + 1813 0202 FB68 ldr r3, [r7, #12] + 1814 0204 0022 movs r2, #0 + 1815 0206 83F84220 strb r2, [r3, #66] +1615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +1617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 1816 .loc 1 1617 5 + 1817 020a FB68 ldr r3, [r7, #12] + 1818 020c 0022 movs r2, #0 + 1819 020e 83F84020 strb r2, [r3, #64] +1618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; + 1820 .loc 1 1619 12 + 1821 0212 0023 movs r3, #0 + 1822 0214 00E0 b .L66 + 1823 .L63: +1620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +1622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; + 1824 .loc 1 1623 12 + 1825 0216 0223 movs r3, #2 + 1826 .L66: +1624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 1827 .loc 1 1625 1 + 1828 0218 1846 mov r0, r3 + 1829 021a 1837 adds r7, r7, #24 + 1830 .cfi_def_cfa_offset 8 + 1831 021c BD46 mov sp, r7 + 1832 .cfi_def_cfa_register 13 + 1833 @ sp needed + 1834 021e 80BD pop {r7, pc} + 1835 .cfi_endproc + 1836 .LFE137: + 1838 .section .text.HAL_I2C_Master_Transmit_IT,"ax",%progbits + 1839 .align 1 + 1840 .global HAL_I2C_Master_Transmit_IT + 1841 .syntax unified + 1842 .thumb + 1843 .thumb_func + 1845 HAL_I2C_Master_Transmit_IT: + 1846 .LFB138: +1626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +1628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt +1629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +1631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +1632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +1633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer +1634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be sent +1635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +1636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +1637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t + ARM GAS /tmp/cc5G5cqz.s page 62 + + +1638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t Size) +1639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 1847 .loc 1 1639 1 + 1848 .cfi_startproc + 1849 @ args = 0, pretend = 0, frame = 24 + 1850 @ frame_needed = 1, uses_anonymous_args = 0 + 1851 0000 80B5 push {r7, lr} + 1852 .cfi_def_cfa_offset 8 + 1853 .cfi_offset 7, -8 + 1854 .cfi_offset 14, -4 + 1855 0002 88B0 sub sp, sp, #32 + 1856 .cfi_def_cfa_offset 40 + 1857 0004 02AF add r7, sp, #8 + 1858 .cfi_def_cfa 7, 32 + 1859 0006 F860 str r0, [r7, #12] + 1860 0008 7A60 str r2, [r7, #4] + 1861 000a 1A46 mov r2, r3 + 1862 000c 0B46 mov r3, r1 @ movhi + 1863 000e 7B81 strh r3, [r7, #10] @ movhi + 1864 0010 1346 mov r3, r2 @ movhi + 1865 0012 3B81 strh r3, [r7, #8] @ movhi +1640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xfermode; +1641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1642:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 1866 .loc 1 1642 11 + 1867 0014 FB68 ldr r3, [r7, #12] + 1868 0016 93F84130 ldrb r3, [r3, #65] + 1869 001a DBB2 uxtb r3, r3 + 1870 .loc 1 1642 6 + 1871 001c 202B cmp r3, #32 + 1872 001e 53D1 bne .L77 +1643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + 1873 .loc 1 1644 9 + 1874 0020 FB68 ldr r3, [r7, #12] + 1875 0022 1B68 ldr r3, [r3] + 1876 0024 9B69 ldr r3, [r3, #24] + 1877 0026 03F40043 and r3, r3, #32768 + 1878 .loc 1 1644 8 + 1879 002a B3F5004F cmp r3, #32768 + 1880 002e 01D1 bne .L78 +1645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; + 1881 .loc 1 1646 14 + 1882 0030 0223 movs r3, #2 + 1883 0032 4AE0 b .L79 + 1884 .L78: +1647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +1650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); + 1885 .loc 1 1650 5 + 1886 0034 FB68 ldr r3, [r7, #12] + 1887 0036 93F84030 ldrb r3, [r3, #64] @ zero_extendqisi2 + 1888 003a 012B cmp r3, #1 + 1889 003c 01D1 bne .L80 + 1890 .loc 1 1650 5 is_stmt 0 discriminator 1 + ARM GAS /tmp/cc5G5cqz.s page 63 + + + 1891 003e 0223 movs r3, #2 + 1892 .loc 1 1650 5 + 1893 0040 43E0 b .L79 + 1894 .L80: + 1895 .loc 1 1650 5 discriminator 2 + 1896 0042 FB68 ldr r3, [r7, #12] + 1897 0044 0122 movs r2, #1 + 1898 0046 83F84020 strb r2, [r3, #64] +1651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; + 1899 .loc 1 1652 23 is_stmt 1 + 1900 004a FB68 ldr r3, [r7, #12] + 1901 004c 2122 movs r2, #33 + 1902 004e 83F84120 strb r2, [r3, #65] +1653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 1903 .loc 1 1653 23 + 1904 0052 FB68 ldr r3, [r7, #12] + 1905 0054 1022 movs r2, #16 + 1906 0056 83F84220 strb r2, [r3, #66] +1654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 1907 .loc 1 1654 23 + 1908 005a FB68 ldr r3, [r7, #12] + 1909 005c 0022 movs r2, #0 + 1910 005e 5A64 str r2, [r3, #68] +1655:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ +1657:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; + 1911 .loc 1 1657 23 + 1912 0060 FB68 ldr r3, [r7, #12] + 1913 0062 7A68 ldr r2, [r7, #4] + 1914 0064 5A62 str r2, [r3, #36] +1658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 1915 .loc 1 1658 23 + 1916 0066 FB68 ldr r3, [r7, #12] + 1917 0068 3A89 ldrh r2, [r7, #8] @ movhi + 1918 006a 5A85 strh r2, [r3, #42] @ movhi +1659:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 1919 .loc 1 1659 23 + 1920 006c FB68 ldr r3, [r7, #12] + 1921 006e 194A ldr r2, .L83 + 1922 0070 DA62 str r2, [r3, #44] +1660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 1923 .loc 1 1660 23 + 1924 0072 FB68 ldr r3, [r7, #12] + 1925 0074 184A ldr r2, .L83+4 + 1926 0076 5A63 str r2, [r3, #52] +1661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) + 1927 .loc 1 1662 13 + 1928 0078 FB68 ldr r3, [r7, #12] + 1929 007a 5B8D ldrh r3, [r3, #42] @ movhi + 1930 007c 9BB2 uxth r3, r3 + 1931 .loc 1 1662 8 + 1932 007e FF2B cmp r3, #255 + 1933 0080 06D9 bls .L81 +1663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1664:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; + ARM GAS /tmp/cc5G5cqz.s page 64 + + + 1934 .loc 1 1664 22 + 1935 0082 FB68 ldr r3, [r7, #12] + 1936 0084 FF22 movs r2, #255 + 1937 0086 1A85 strh r2, [r3, #40] @ movhi +1665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 1938 .loc 1 1665 16 + 1939 0088 4FF08073 mov r3, #16777216 + 1940 008c 7B61 str r3, [r7, #20] + 1941 008e 07E0 b .L82 + 1942 .L81: +1666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +1668:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 1943 .loc 1 1669 28 + 1944 0090 FB68 ldr r3, [r7, #12] + 1945 0092 5B8D ldrh r3, [r3, #42] @ movhi + 1946 0094 9AB2 uxth r2, r3 + 1947 .loc 1 1669 22 + 1948 0096 FB68 ldr r3, [r7, #12] + 1949 0098 1A85 strh r2, [r3, #40] @ movhi +1670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 1950 .loc 1 1670 16 + 1951 009a 4FF00073 mov r3, #33554432 + 1952 009e 7B61 str r3, [r7, #20] + 1953 .L82: +1671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send Slave Address */ +1674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ +1675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRIT + 1954 .loc 1 1675 55 + 1955 00a0 FB68 ldr r3, [r7, #12] + 1956 00a2 1B8D ldrh r3, [r3, #40] + 1957 .loc 1 1675 5 + 1958 00a4 DAB2 uxtb r2, r3 + 1959 00a6 7989 ldrh r1, [r7, #10] + 1960 00a8 0C4B ldr r3, .L83+8 + 1961 00aa 0093 str r3, [sp] + 1962 00ac 7B69 ldr r3, [r7, #20] + 1963 00ae F868 ldr r0, [r7, #12] + 1964 00b0 FFF7FEFF bl I2C_TransferConfig +1676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +1678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 1965 .loc 1 1678 5 + 1966 00b4 FB68 ldr r3, [r7, #12] + 1967 00b6 0022 movs r2, #0 + 1968 00b8 83F84020 strb r2, [r3, #64] +1679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +1681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +1682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** process unlock */ +1683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, TXI interrupt */ +1685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* possible to enable all of these */ +1686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + ARM GAS /tmp/cc5G5cqz.s page 65 + + +1687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ +1688:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + 1969 .loc 1 1688 5 + 1970 00bc 0121 movs r1, #1 + 1971 00be F868 ldr r0, [r7, #12] + 1972 00c0 FFF7FEFF bl I2C_Enable_IRQ +1689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; + 1973 .loc 1 1690 12 + 1974 00c4 0023 movs r3, #0 + 1975 00c6 00E0 b .L79 + 1976 .L77: +1691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +1693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1694:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; + 1977 .loc 1 1694 12 + 1978 00c8 0223 movs r3, #2 + 1979 .L79: +1695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 1980 .loc 1 1696 1 + 1981 00ca 1846 mov r0, r3 + 1982 00cc 1837 adds r7, r7, #24 + 1983 .cfi_def_cfa_offset 8 + 1984 00ce BD46 mov sp, r7 + 1985 .cfi_def_cfa_register 13 + 1986 @ sp needed + 1987 00d0 80BD pop {r7, pc} + 1988 .L84: + 1989 00d2 00BF .align 2 + 1990 .L83: + 1991 00d4 0000FFFF .word -65536 + 1992 00d8 00000000 .word I2C_Master_ISR_IT + 1993 00dc 00200080 .word -2147475456 + 1994 .cfi_endproc + 1995 .LFE138: + 1997 .section .text.HAL_I2C_Master_Receive_IT,"ax",%progbits + 1998 .align 1 + 1999 .global HAL_I2C_Master_Receive_IT + 2000 .syntax unified + 2001 .thumb + 2002 .thumb_func + 2004 HAL_I2C_Master_Receive_IT: + 2005 .LFB139: +1697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +1699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt +1700:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +1702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +1703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +1704:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer +1705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be sent +1706:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +1707:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +1708:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t * + ARM GAS /tmp/cc5G5cqz.s page 66 + + +1709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t Size) +1710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2006 .loc 1 1710 1 + 2007 .cfi_startproc + 2008 @ args = 0, pretend = 0, frame = 24 + 2009 @ frame_needed = 1, uses_anonymous_args = 0 + 2010 0000 80B5 push {r7, lr} + 2011 .cfi_def_cfa_offset 8 + 2012 .cfi_offset 7, -8 + 2013 .cfi_offset 14, -4 + 2014 0002 88B0 sub sp, sp, #32 + 2015 .cfi_def_cfa_offset 40 + 2016 0004 02AF add r7, sp, #8 + 2017 .cfi_def_cfa 7, 32 + 2018 0006 F860 str r0, [r7, #12] + 2019 0008 7A60 str r2, [r7, #4] + 2020 000a 1A46 mov r2, r3 + 2021 000c 0B46 mov r3, r1 @ movhi + 2022 000e 7B81 strh r3, [r7, #10] @ movhi + 2023 0010 1346 mov r3, r2 @ movhi + 2024 0012 3B81 strh r3, [r7, #8] @ movhi +1711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xfermode; +1712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1713:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 2025 .loc 1 1713 11 + 2026 0014 FB68 ldr r3, [r7, #12] + 2027 0016 93F84130 ldrb r3, [r3, #65] + 2028 001a DBB2 uxtb r3, r3 + 2029 .loc 1 1713 6 + 2030 001c 202B cmp r3, #32 + 2031 001e 53D1 bne .L86 +1714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + 2032 .loc 1 1715 9 + 2033 0020 FB68 ldr r3, [r7, #12] + 2034 0022 1B68 ldr r3, [r3] + 2035 0024 9B69 ldr r3, [r3, #24] + 2036 0026 03F40043 and r3, r3, #32768 + 2037 .loc 1 1715 8 + 2038 002a B3F5004F cmp r3, #32768 + 2039 002e 01D1 bne .L87 +1716:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; + 2040 .loc 1 1717 14 + 2041 0030 0223 movs r3, #2 + 2042 0032 4AE0 b .L88 + 2043 .L87: +1718:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1720:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +1721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); + 2044 .loc 1 1721 5 + 2045 0034 FB68 ldr r3, [r7, #12] + 2046 0036 93F84030 ldrb r3, [r3, #64] @ zero_extendqisi2 + 2047 003a 012B cmp r3, #1 + 2048 003c 01D1 bne .L89 + 2049 .loc 1 1721 5 is_stmt 0 discriminator 1 + ARM GAS /tmp/cc5G5cqz.s page 67 + + + 2050 003e 0223 movs r3, #2 + 2051 .loc 1 1721 5 + 2052 0040 43E0 b .L88 + 2053 .L89: + 2054 .loc 1 1721 5 discriminator 2 + 2055 0042 FB68 ldr r3, [r7, #12] + 2056 0044 0122 movs r2, #1 + 2057 0046 83F84020 strb r2, [r3, #64] +1722:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1723:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; + 2058 .loc 1 1723 23 is_stmt 1 + 2059 004a FB68 ldr r3, [r7, #12] + 2060 004c 2222 movs r2, #34 + 2061 004e 83F84120 strb r2, [r3, #65] +1724:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 2062 .loc 1 1724 23 + 2063 0052 FB68 ldr r3, [r7, #12] + 2064 0054 1022 movs r2, #16 + 2065 0056 83F84220 strb r2, [r3, #66] +1725:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 2066 .loc 1 1725 23 + 2067 005a FB68 ldr r3, [r7, #12] + 2068 005c 0022 movs r2, #0 + 2069 005e 5A64 str r2, [r3, #68] +1726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1727:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ +1728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; + 2070 .loc 1 1728 23 + 2071 0060 FB68 ldr r3, [r7, #12] + 2072 0062 7A68 ldr r2, [r7, #4] + 2073 0064 5A62 str r2, [r3, #36] +1729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 2074 .loc 1 1729 23 + 2075 0066 FB68 ldr r3, [r7, #12] + 2076 0068 3A89 ldrh r2, [r7, #8] @ movhi + 2077 006a 5A85 strh r2, [r3, #42] @ movhi +1730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 2078 .loc 1 1730 23 + 2079 006c FB68 ldr r3, [r7, #12] + 2080 006e 194A ldr r2, .L92 + 2081 0070 DA62 str r2, [r3, #44] +1731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 2082 .loc 1 1731 23 + 2083 0072 FB68 ldr r3, [r7, #12] + 2084 0074 184A ldr r2, .L92+4 + 2085 0076 5A63 str r2, [r3, #52] +1732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) + 2086 .loc 1 1733 13 + 2087 0078 FB68 ldr r3, [r7, #12] + 2088 007a 5B8D ldrh r3, [r3, #42] @ movhi + 2089 007c 9BB2 uxth r3, r3 + 2090 .loc 1 1733 8 + 2091 007e FF2B cmp r3, #255 + 2092 0080 06D9 bls .L90 +1734:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; + ARM GAS /tmp/cc5G5cqz.s page 68 + + + 2093 .loc 1 1735 22 + 2094 0082 FB68 ldr r3, [r7, #12] + 2095 0084 FF22 movs r2, #255 + 2096 0086 1A85 strh r2, [r3, #40] @ movhi +1736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 2097 .loc 1 1736 16 + 2098 0088 4FF08073 mov r3, #16777216 + 2099 008c 7B61 str r3, [r7, #20] + 2100 008e 07E0 b .L91 + 2101 .L90: +1737:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +1739:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 2102 .loc 1 1740 28 + 2103 0090 FB68 ldr r3, [r7, #12] + 2104 0092 5B8D ldrh r3, [r3, #42] @ movhi + 2105 0094 9AB2 uxth r2, r3 + 2106 .loc 1 1740 22 + 2107 0096 FB68 ldr r3, [r7, #12] + 2108 0098 1A85 strh r2, [r3, #40] @ movhi +1741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 2109 .loc 1 1741 16 + 2110 009a 4FF00073 mov r3, #33554432 + 2111 009e 7B61 str r3, [r7, #20] + 2112 .L91: +1742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1743:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send Slave Address */ +1745:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ +1746:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ + 2113 .loc 1 1746 55 + 2114 00a0 FB68 ldr r3, [r7, #12] + 2115 00a2 1B8D ldrh r3, [r3, #40] + 2116 .loc 1 1746 5 + 2117 00a4 DAB2 uxtb r2, r3 + 2118 00a6 7989 ldrh r1, [r7, #10] + 2119 00a8 0C4B ldr r3, .L92+8 + 2120 00aa 0093 str r3, [sp] + 2121 00ac 7B69 ldr r3, [r7, #20] + 2122 00ae F868 ldr r0, [r7, #12] + 2123 00b0 FFF7FEFF bl I2C_TransferConfig +1747:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1748:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +1749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 2124 .loc 1 1749 5 + 2125 00b4 FB68 ldr r3, [r7, #12] + 2126 00b6 0022 movs r2, #0 + 2127 00b8 83F84020 strb r2, [r3, #64] +1750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +1752:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +1753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** process unlock */ +1754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1755:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, RXI interrupt */ +1756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* possible to enable all of these */ +1757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + ARM GAS /tmp/cc5G5cqz.s page 69 + + +1758:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ +1759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + 2128 .loc 1 1759 5 + 2129 00bc 0221 movs r1, #2 + 2130 00be F868 ldr r0, [r7, #12] + 2131 00c0 FFF7FEFF bl I2C_Enable_IRQ +1760:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1761:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; + 2132 .loc 1 1761 12 + 2133 00c4 0023 movs r3, #0 + 2134 00c6 00E0 b .L88 + 2135 .L86: +1762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +1764:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; + 2136 .loc 1 1765 12 + 2137 00c8 0223 movs r3, #2 + 2138 .L88: +1766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1767:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2139 .loc 1 1767 1 + 2140 00ca 1846 mov r0, r3 + 2141 00cc 1837 adds r7, r7, #24 + 2142 .cfi_def_cfa_offset 8 + 2143 00ce BD46 mov sp, r7 + 2144 .cfi_def_cfa_register 13 + 2145 @ sp needed + 2146 00d0 80BD pop {r7, pc} + 2147 .L93: + 2148 00d2 00BF .align 2 + 2149 .L92: + 2150 00d4 0000FFFF .word -65536 + 2151 00d8 00000000 .word I2C_Master_ISR_IT + 2152 00dc 00240080 .word -2147474432 + 2153 .cfi_endproc + 2154 .LFE139: + 2156 .section .text.HAL_I2C_Slave_Transmit_IT,"ax",%progbits + 2157 .align 1 + 2158 .global HAL_I2C_Slave_Transmit_IT + 2159 .syntax unified + 2160 .thumb + 2161 .thumb_func + 2163 HAL_I2C_Slave_Transmit_IT: + 2164 .LFB140: +1768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +1770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt +1771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +1773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer +1774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be sent +1775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +1776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +1777:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +1778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2165 .loc 1 1778 1 + ARM GAS /tmp/cc5G5cqz.s page 70 + + + 2166 .cfi_startproc + 2167 @ args = 0, pretend = 0, frame = 16 + 2168 @ frame_needed = 1, uses_anonymous_args = 0 + 2169 0000 80B5 push {r7, lr} + 2170 .cfi_def_cfa_offset 8 + 2171 .cfi_offset 7, -8 + 2172 .cfi_offset 14, -4 + 2173 0002 84B0 sub sp, sp, #16 + 2174 .cfi_def_cfa_offset 24 + 2175 0004 00AF add r7, sp, #0 + 2176 .cfi_def_cfa_register 7 + 2177 0006 F860 str r0, [r7, #12] + 2178 0008 B960 str r1, [r7, #8] + 2179 000a 1346 mov r3, r2 + 2180 000c FB80 strh r3, [r7, #6] @ movhi +1779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 2181 .loc 1 1779 11 + 2182 000e FB68 ldr r3, [r7, #12] + 2183 0010 93F84130 ldrb r3, [r3, #65] + 2184 0014 DBB2 uxtb r3, r3 + 2185 .loc 1 1779 6 + 2186 0016 202B cmp r3, #32 + 2187 0018 56D1 bne .L95 +1780:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +1782:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); + 2188 .loc 1 1782 5 + 2189 001a FB68 ldr r3, [r7, #12] + 2190 001c 93F84030 ldrb r3, [r3, #64] @ zero_extendqisi2 + 2191 0020 012B cmp r3, #1 + 2192 0022 01D1 bne .L96 + 2193 .loc 1 1782 5 is_stmt 0 discriminator 1 + 2194 0024 0223 movs r3, #2 + 2195 .loc 1 1782 5 + 2196 0026 50E0 b .L97 + 2197 .L96: + 2198 .loc 1 1782 5 discriminator 2 + 2199 0028 FB68 ldr r3, [r7, #12] + 2200 002a 0122 movs r2, #1 + 2201 002c 83F84020 strb r2, [r3, #64] +1783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; + 2202 .loc 1 1784 23 is_stmt 1 + 2203 0030 FB68 ldr r3, [r7, #12] + 2204 0032 2122 movs r2, #33 + 2205 0034 83F84120 strb r2, [r3, #65] +1785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 2206 .loc 1 1785 23 + 2207 0038 FB68 ldr r3, [r7, #12] + 2208 003a 2022 movs r2, #32 + 2209 003c 83F84220 strb r2, [r3, #66] +1786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 2210 .loc 1 1786 23 + 2211 0040 FB68 ldr r3, [r7, #12] + 2212 0042 0022 movs r2, #0 + 2213 0044 5A64 str r2, [r3, #68] +1787:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/cc5G5cqz.s page 71 + + +1788:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable Address Acknowledge */ +1789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + 2214 .loc 1 1789 9 + 2215 0046 FB68 ldr r3, [r7, #12] + 2216 0048 1B68 ldr r3, [r3] + 2217 .loc 1 1789 19 + 2218 004a 5A68 ldr r2, [r3, #4] + 2219 .loc 1 1789 9 + 2220 004c FB68 ldr r3, [r7, #12] + 2221 004e 1B68 ldr r3, [r3] + 2222 .loc 1 1789 25 + 2223 0050 22F40042 bic r2, r2, #32768 + 2224 0054 5A60 str r2, [r3, #4] +1790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ +1792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; + 2225 .loc 1 1792 23 + 2226 0056 FB68 ldr r3, [r7, #12] + 2227 0058 BA68 ldr r2, [r7, #8] + 2228 005a 5A62 str r2, [r3, #36] +1793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 2229 .loc 1 1793 23 + 2230 005c FB68 ldr r3, [r7, #12] + 2231 005e FA88 ldrh r2, [r7, #6] @ movhi + 2232 0060 5A85 strh r2, [r3, #42] @ movhi +1794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 2233 .loc 1 1794 29 + 2234 0062 FB68 ldr r3, [r7, #12] + 2235 0064 5B8D ldrh r3, [r3, #42] @ movhi + 2236 0066 9AB2 uxth r2, r3 + 2237 .loc 1 1794 23 + 2238 0068 FB68 ldr r3, [r7, #12] + 2239 006a 1A85 strh r2, [r3, #40] @ movhi +1795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 2240 .loc 1 1795 23 + 2241 006c FB68 ldr r3, [r7, #12] + 2242 006e 194A ldr r2, .L99 + 2243 0070 DA62 str r2, [r3, #44] +1796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 2244 .loc 1 1796 23 + 2245 0072 FB68 ldr r3, [r7, #12] + 2246 0074 184A ldr r2, .L99+4 + 2247 0076 5A63 str r2, [r3, #52] +1797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1798:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Preload TX data if no stretch enable */ +1799:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) + 2248 .loc 1 1799 19 + 2249 0078 FB68 ldr r3, [r7, #12] + 2250 007a 1B6A ldr r3, [r3, #32] + 2251 .loc 1 1799 8 + 2252 007c B3F5003F cmp r3, #131072 + 2253 0080 17D1 bne .L98 +1800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Preload TX register */ +1802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Write data to TXDR */ +1803:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->TXDR = *hi2c->pBuffPtr; + 2254 .loc 1 1803 35 + ARM GAS /tmp/cc5G5cqz.s page 72 + + + 2255 0082 FB68 ldr r3, [r7, #12] + 2256 0084 5B6A ldr r3, [r3, #36] + 2257 .loc 1 1803 30 + 2258 0086 1A78 ldrb r2, [r3] @ zero_extendqisi2 + 2259 .loc 1 1803 11 + 2260 0088 FB68 ldr r3, [r7, #12] + 2261 008a 1B68 ldr r3, [r3] + 2262 .loc 1 1803 28 + 2263 008c 9A62 str r2, [r3, #40] +1804:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Increment Buffer pointer */ +1806:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr++; + 2264 .loc 1 1806 11 + 2265 008e FB68 ldr r3, [r7, #12] + 2266 0090 5B6A ldr r3, [r3, #36] + 2267 .loc 1 1806 21 + 2268 0092 5A1C adds r2, r3, #1 + 2269 0094 FB68 ldr r3, [r7, #12] + 2270 0096 5A62 str r2, [r3, #36] +1807:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1808:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount--; + 2271 .loc 1 1808 11 + 2272 0098 FB68 ldr r3, [r7, #12] + 2273 009a 5B8D ldrh r3, [r3, #42] @ movhi + 2274 009c 9BB2 uxth r3, r3 + 2275 .loc 1 1808 22 + 2276 009e 013B subs r3, r3, #1 + 2277 00a0 9AB2 uxth r2, r3 + 2278 00a2 FB68 ldr r3, [r7, #12] + 2279 00a4 5A85 strh r2, [r3, #42] @ movhi +1809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize--; + 2280 .loc 1 1809 11 + 2281 00a6 FB68 ldr r3, [r7, #12] + 2282 00a8 1B8D ldrh r3, [r3, #40] + 2283 .loc 1 1809 21 + 2284 00aa 013B subs r3, r3, #1 + 2285 00ac 9AB2 uxth r2, r3 + 2286 00ae FB68 ldr r3, [r7, #12] + 2287 00b0 1A85 strh r2, [r3, #40] @ movhi + 2288 .L98: +1810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1811:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +1813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 2289 .loc 1 1813 5 + 2290 00b2 FB68 ldr r3, [r7, #12] + 2291 00b4 0022 movs r2, #0 + 2292 00b6 83F84020 strb r2, [r3, #64] +1814:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +1816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +1817:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** process unlock */ +1818:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, TXI interrupt */ +1820:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* possible to enable all of these */ +1821:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | +1822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + ARM GAS /tmp/cc5G5cqz.s page 73 + + +1823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); + 2293 .loc 1 1823 5 + 2294 00ba 48F20101 movw r1, #32769 + 2295 00be F868 ldr r0, [r7, #12] + 2296 00c0 FFF7FEFF bl I2C_Enable_IRQ +1824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; + 2297 .loc 1 1825 12 + 2298 00c4 0023 movs r3, #0 + 2299 00c6 00E0 b .L97 + 2300 .L95: +1826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1827:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +1828:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1829:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; + 2301 .loc 1 1829 12 + 2302 00c8 0223 movs r3, #2 + 2303 .L97: +1830:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2304 .loc 1 1831 1 + 2305 00ca 1846 mov r0, r3 + 2306 00cc 1037 adds r7, r7, #16 + 2307 .cfi_def_cfa_offset 8 + 2308 00ce BD46 mov sp, r7 + 2309 .cfi_def_cfa_register 13 + 2310 @ sp needed + 2311 00d0 80BD pop {r7, pc} + 2312 .L100: + 2313 00d2 00BF .align 2 + 2314 .L99: + 2315 00d4 0000FFFF .word -65536 + 2316 00d8 00000000 .word I2C_Slave_ISR_IT + 2317 .cfi_endproc + 2318 .LFE140: + 2320 .section .text.HAL_I2C_Slave_Receive_IT,"ax",%progbits + 2321 .align 1 + 2322 .global HAL_I2C_Slave_Receive_IT + 2323 .syntax unified + 2324 .thumb + 2325 .thumb_func + 2327 HAL_I2C_Slave_Receive_IT: + 2328 .LFB141: +1832:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +1834:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt +1835:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1836:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +1837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer +1838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be sent +1839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +1840:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +1841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +1842:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2329 .loc 1 1842 1 + 2330 .cfi_startproc + 2331 @ args = 0, pretend = 0, frame = 16 + ARM GAS /tmp/cc5G5cqz.s page 74 + + + 2332 @ frame_needed = 1, uses_anonymous_args = 0 + 2333 0000 80B5 push {r7, lr} + 2334 .cfi_def_cfa_offset 8 + 2335 .cfi_offset 7, -8 + 2336 .cfi_offset 14, -4 + 2337 0002 84B0 sub sp, sp, #16 + 2338 .cfi_def_cfa_offset 24 + 2339 0004 00AF add r7, sp, #0 + 2340 .cfi_def_cfa_register 7 + 2341 0006 F860 str r0, [r7, #12] + 2342 0008 B960 str r1, [r7, #8] + 2343 000a 1346 mov r3, r2 + 2344 000c FB80 strh r3, [r7, #6] @ movhi +1843:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 2345 .loc 1 1843 11 + 2346 000e FB68 ldr r3, [r7, #12] + 2347 0010 93F84130 ldrb r3, [r3, #65] + 2348 0014 DBB2 uxtb r3, r3 + 2349 .loc 1 1843 6 + 2350 0016 202B cmp r3, #32 + 2351 0018 39D1 bne .L102 +1844:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +1846:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); + 2352 .loc 1 1846 5 + 2353 001a FB68 ldr r3, [r7, #12] + 2354 001c 93F84030 ldrb r3, [r3, #64] @ zero_extendqisi2 + 2355 0020 012B cmp r3, #1 + 2356 0022 01D1 bne .L103 + 2357 .loc 1 1846 5 is_stmt 0 discriminator 1 + 2358 0024 0223 movs r3, #2 + 2359 .loc 1 1846 5 + 2360 0026 33E0 b .L104 + 2361 .L103: + 2362 .loc 1 1846 5 discriminator 2 + 2363 0028 FB68 ldr r3, [r7, #12] + 2364 002a 0122 movs r2, #1 + 2365 002c 83F84020 strb r2, [r3, #64] +1847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; + 2366 .loc 1 1848 23 is_stmt 1 + 2367 0030 FB68 ldr r3, [r7, #12] + 2368 0032 2222 movs r2, #34 + 2369 0034 83F84120 strb r2, [r3, #65] +1849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 2370 .loc 1 1849 23 + 2371 0038 FB68 ldr r3, [r7, #12] + 2372 003a 2022 movs r2, #32 + 2373 003c 83F84220 strb r2, [r3, #66] +1850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 2374 .loc 1 1850 23 + 2375 0040 FB68 ldr r3, [r7, #12] + 2376 0042 0022 movs r2, #0 + 2377 0044 5A64 str r2, [r3, #68] +1851:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1852:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable Address Acknowledge */ +1853:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + ARM GAS /tmp/cc5G5cqz.s page 75 + + + 2378 .loc 1 1853 9 + 2379 0046 FB68 ldr r3, [r7, #12] + 2380 0048 1B68 ldr r3, [r3] + 2381 .loc 1 1853 19 + 2382 004a 5A68 ldr r2, [r3, #4] + 2383 .loc 1 1853 9 + 2384 004c FB68 ldr r3, [r7, #12] + 2385 004e 1B68 ldr r3, [r3] + 2386 .loc 1 1853 25 + 2387 0050 22F40042 bic r2, r2, #32768 + 2388 0054 5A60 str r2, [r3, #4] +1854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1855:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ +1856:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; + 2389 .loc 1 1856 23 + 2390 0056 FB68 ldr r3, [r7, #12] + 2391 0058 BA68 ldr r2, [r7, #8] + 2392 005a 5A62 str r2, [r3, #36] +1857:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 2393 .loc 1 1857 23 + 2394 005c FB68 ldr r3, [r7, #12] + 2395 005e FA88 ldrh r2, [r7, #6] @ movhi + 2396 0060 5A85 strh r2, [r3, #42] @ movhi +1858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 2397 .loc 1 1858 29 + 2398 0062 FB68 ldr r3, [r7, #12] + 2399 0064 5B8D ldrh r3, [r3, #42] @ movhi + 2400 0066 9AB2 uxth r2, r3 + 2401 .loc 1 1858 23 + 2402 0068 FB68 ldr r3, [r7, #12] + 2403 006a 1A85 strh r2, [r3, #40] @ movhi +1859:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 2404 .loc 1 1859 23 + 2405 006c FB68 ldr r3, [r7, #12] + 2406 006e 0A4A ldr r2, .L105 + 2407 0070 DA62 str r2, [r3, #44] +1860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 2408 .loc 1 1860 23 + 2409 0072 FB68 ldr r3, [r7, #12] + 2410 0074 094A ldr r2, .L105+4 + 2411 0076 5A63 str r2, [r3, #52] +1861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +1863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 2412 .loc 1 1863 5 + 2413 0078 FB68 ldr r3, [r7, #12] + 2414 007a 0022 movs r2, #0 + 2415 007c 83F84020 strb r2, [r3, #64] +1864:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +1866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +1867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** process unlock */ +1868:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, RXI interrupt */ +1870:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* possible to enable all of these */ +1871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | +1872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + ARM GAS /tmp/cc5G5cqz.s page 76 + + +1873:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + 2416 .loc 1 1873 5 + 2417 0080 48F20201 movw r1, #32770 + 2418 0084 F868 ldr r0, [r7, #12] + 2419 0086 FFF7FEFF bl I2C_Enable_IRQ +1874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1875:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; + 2420 .loc 1 1875 12 + 2421 008a 0023 movs r3, #0 + 2422 008c 00E0 b .L104 + 2423 .L102: +1876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1877:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +1878:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1879:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; + 2424 .loc 1 1879 12 + 2425 008e 0223 movs r3, #2 + 2426 .L104: +1880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2427 .loc 1 1881 1 + 2428 0090 1846 mov r0, r3 + 2429 0092 1037 adds r7, r7, #16 + 2430 .cfi_def_cfa_offset 8 + 2431 0094 BD46 mov sp, r7 + 2432 .cfi_def_cfa_register 13 + 2433 @ sp needed + 2434 0096 80BD pop {r7, pc} + 2435 .L106: + 2436 .align 2 + 2437 .L105: + 2438 0098 0000FFFF .word -65536 + 2439 009c 00000000 .word I2C_Slave_ISR_IT + 2440 .cfi_endproc + 2441 .LFE141: + 2443 .section .text.HAL_I2C_Master_Transmit_DMA,"ax",%progbits + 2444 .align 1 + 2445 .global HAL_I2C_Master_Transmit_DMA + 2446 .syntax unified + 2447 .thumb + 2448 .thumb_func + 2450 HAL_I2C_Master_Transmit_DMA: + 2451 .LFB142: +1882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +1884:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Transmit in master mode an amount of data in non-blocking mode with DMA +1885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +1886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +1887:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +1888:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +1889:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer +1890:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be sent +1891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +1892:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +1893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t +1894:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t Size) +1895:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + ARM GAS /tmp/cc5G5cqz.s page 77 + + + 2452 .loc 1 1895 1 + 2453 .cfi_startproc + 2454 @ args = 0, pretend = 0, frame = 24 + 2455 @ frame_needed = 1, uses_anonymous_args = 0 + 2456 0000 80B5 push {r7, lr} + 2457 .cfi_def_cfa_offset 8 + 2458 .cfi_offset 7, -8 + 2459 .cfi_offset 14, -4 + 2460 0002 88B0 sub sp, sp, #32 + 2461 .cfi_def_cfa_offset 40 + 2462 0004 02AF add r7, sp, #8 + 2463 .cfi_def_cfa 7, 32 + 2464 0006 F860 str r0, [r7, #12] + 2465 0008 7A60 str r2, [r7, #4] + 2466 000a 1A46 mov r2, r3 + 2467 000c 0B46 mov r3, r1 @ movhi + 2468 000e 7B81 strh r3, [r7, #10] @ movhi + 2469 0010 1346 mov r3, r2 @ movhi + 2470 0012 3B81 strh r3, [r7, #8] @ movhi +1896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xfermode; +1897:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; +1898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1899:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 2471 .loc 1 1899 11 + 2472 0014 FB68 ldr r3, [r7, #12] + 2473 0016 93F84130 ldrb r3, [r3, #65] + 2474 001a DBB2 uxtb r3, r3 + 2475 .loc 1 1899 6 + 2476 001c 202B cmp r3, #32 + 2477 001e 40F0CD80 bne .L108 +1900:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + 2478 .loc 1 1901 9 + 2479 0022 FB68 ldr r3, [r7, #12] + 2480 0024 1B68 ldr r3, [r3] + 2481 0026 9B69 ldr r3, [r3, #24] + 2482 0028 03F40043 and r3, r3, #32768 + 2483 .loc 1 1901 8 + 2484 002c B3F5004F cmp r3, #32768 + 2485 0030 01D1 bne .L109 +1902:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; + 2486 .loc 1 1903 14 + 2487 0032 0223 movs r3, #2 + 2488 0034 C3E0 b .L110 + 2489 .L109: +1904:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1905:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1906:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +1907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); + 2490 .loc 1 1907 5 + 2491 0036 FB68 ldr r3, [r7, #12] + 2492 0038 93F84030 ldrb r3, [r3, #64] @ zero_extendqisi2 + 2493 003c 012B cmp r3, #1 + 2494 003e 01D1 bne .L111 + 2495 .loc 1 1907 5 is_stmt 0 discriminator 1 + 2496 0040 0223 movs r3, #2 + ARM GAS /tmp/cc5G5cqz.s page 78 + + + 2497 .loc 1 1907 5 + 2498 0042 BCE0 b .L110 + 2499 .L111: + 2500 .loc 1 1907 5 discriminator 2 + 2501 0044 FB68 ldr r3, [r7, #12] + 2502 0046 0122 movs r2, #1 + 2503 0048 83F84020 strb r2, [r3, #64] +1908:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1909:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; + 2504 .loc 1 1909 23 is_stmt 1 + 2505 004c FB68 ldr r3, [r7, #12] + 2506 004e 2122 movs r2, #33 + 2507 0050 83F84120 strb r2, [r3, #65] +1910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 2508 .loc 1 1910 23 + 2509 0054 FB68 ldr r3, [r7, #12] + 2510 0056 1022 movs r2, #16 + 2511 0058 83F84220 strb r2, [r3, #66] +1911:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 2512 .loc 1 1911 23 + 2513 005c FB68 ldr r3, [r7, #12] + 2514 005e 0022 movs r2, #0 + 2515 0060 5A64 str r2, [r3, #68] +1912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1913:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ +1914:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; + 2516 .loc 1 1914 23 + 2517 0062 FB68 ldr r3, [r7, #12] + 2518 0064 7A68 ldr r2, [r7, #4] + 2519 0066 5A62 str r2, [r3, #36] +1915:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 2520 .loc 1 1915 23 + 2521 0068 FB68 ldr r3, [r7, #12] + 2522 006a 3A89 ldrh r2, [r7, #8] @ movhi + 2523 006c 5A85 strh r2, [r3, #42] @ movhi +1916:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 2524 .loc 1 1916 23 + 2525 006e FB68 ldr r3, [r7, #12] + 2526 0070 554A ldr r2, .L120 + 2527 0072 DA62 str r2, [r3, #44] +1917:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 2528 .loc 1 1917 23 + 2529 0074 FB68 ldr r3, [r7, #12] + 2530 0076 554A ldr r2, .L120+4 + 2531 0078 5A63 str r2, [r3, #52] +1918:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1919:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) + 2532 .loc 1 1919 13 + 2533 007a FB68 ldr r3, [r7, #12] + 2534 007c 5B8D ldrh r3, [r3, #42] @ movhi + 2535 007e 9BB2 uxth r3, r3 + 2536 .loc 1 1919 8 + 2537 0080 FF2B cmp r3, #255 + 2538 0082 06D9 bls .L112 +1920:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; + 2539 .loc 1 1921 22 + ARM GAS /tmp/cc5G5cqz.s page 79 + + + 2540 0084 FB68 ldr r3, [r7, #12] + 2541 0086 FF22 movs r2, #255 + 2542 0088 1A85 strh r2, [r3, #40] @ movhi +1922:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 2543 .loc 1 1922 16 + 2544 008a 4FF08073 mov r3, #16777216 + 2545 008e 7B61 str r3, [r7, #20] + 2546 0090 07E0 b .L113 + 2547 .L112: +1923:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1924:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +1925:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1926:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 2548 .loc 1 1926 28 + 2549 0092 FB68 ldr r3, [r7, #12] + 2550 0094 5B8D ldrh r3, [r3, #42] @ movhi + 2551 0096 9AB2 uxth r2, r3 + 2552 .loc 1 1926 22 + 2553 0098 FB68 ldr r3, [r7, #12] + 2554 009a 1A85 strh r2, [r3, #40] @ movhi +1927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 2555 .loc 1 1927 16 + 2556 009c 4FF00073 mov r3, #33554432 + 2557 00a0 7B61 str r3, [r7, #20] + 2558 .L113: +1928:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1929:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1930:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferSize > 0U) + 2559 .loc 1 1930 13 + 2560 00a2 FB68 ldr r3, [r7, #12] + 2561 00a4 1B8D ldrh r3, [r3, #40] + 2562 .loc 1 1930 8 + 2563 00a6 002B cmp r3, #0 + 2564 00a8 70D0 beq .L114 +1931:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1932:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) + 2565 .loc 1 1932 15 + 2566 00aa FB68 ldr r3, [r7, #12] + 2567 00ac 9B6B ldr r3, [r3, #56] + 2568 .loc 1 1932 10 + 2569 00ae 002B cmp r3, #0 + 2570 00b0 20D0 beq .L115 +1933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1934:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +1935:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + 2571 .loc 1 1935 13 + 2572 00b2 FB68 ldr r3, [r7, #12] + 2573 00b4 9B6B ldr r3, [r3, #56] + 2574 .loc 1 1935 40 + 2575 00b6 464A ldr r2, .L120+8 + 2576 00b8 9A62 str r2, [r3, #40] +1936:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the DMA error callback */ +1938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + 2577 .loc 1 1938 13 + 2578 00ba FB68 ldr r3, [r7, #12] + 2579 00bc 9B6B ldr r3, [r3, #56] + ARM GAS /tmp/cc5G5cqz.s page 80 + + + 2580 .loc 1 1938 41 + 2581 00be 454A ldr r2, .L120+12 + 2582 00c0 1A63 str r2, [r3, #48] +1939:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +1941:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferHalfCpltCallback = NULL; + 2583 .loc 1 1941 13 + 2584 00c2 FB68 ldr r3, [r7, #12] + 2585 00c4 9B6B ldr r3, [r3, #56] + 2586 .loc 1 1941 44 + 2587 00c6 0022 movs r2, #0 + 2588 00c8 DA62 str r2, [r3, #44] +1942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 2589 .loc 1 1942 13 + 2590 00ca FB68 ldr r3, [r7, #12] + 2591 00cc 9B6B ldr r3, [r3, #56] + 2592 .loc 1 1942 41 + 2593 00ce 0022 movs r2, #0 + 2594 00d0 5A63 str r2, [r3, #52] +1943:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1944:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable the DMA channel */ +1945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance-> + 2595 .loc 1 1945 25 + 2596 00d2 FB68 ldr r3, [r7, #12] + 2597 00d4 986B ldr r0, [r3, #56] + 2598 00d6 7968 ldr r1, [r7, #4] + 2599 .loc 1 1945 88 + 2600 00d8 FB68 ldr r3, [r7, #12] + 2601 00da 1B68 ldr r3, [r3] + 2602 .loc 1 1945 83 + 2603 00dc 2833 adds r3, r3, #40 + 2604 .loc 1 1945 25 + 2605 00de 1A46 mov r2, r3 +1946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); + 2606 .loc 1 1946 46 + 2607 00e0 FB68 ldr r3, [r7, #12] + 2608 00e2 1B8D ldrh r3, [r3, #40] +1945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); + 2609 .loc 1 1945 25 + 2610 00e4 FFF7FEFF bl HAL_DMA_Start_IT + 2611 00e8 0346 mov r3, r0 + 2612 00ea FB74 strb r3, [r7, #19] +1947:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1948:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +1949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1950:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C state */ +1951:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +1952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +1953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1954:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C error code */ +1955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; +1956:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1957:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +1958:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +1959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1960:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +1961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/cc5G5cqz.s page 81 + + +1962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1963:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (dmaxferstatus == HAL_OK) + 2613 .loc 1 1963 10 + 2614 00ec FB7C ldrb r3, [r7, #19] @ zero_extendqisi2 + 2615 00ee 002B cmp r3, #0 + 2616 00f0 38D1 bne .L117 + 2617 00f2 13E0 b .L119 + 2618 .L115: +1951:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 2619 .loc 1 1951 25 + 2620 00f4 FB68 ldr r3, [r7, #12] + 2621 00f6 2022 movs r2, #32 + 2622 00f8 83F84120 strb r2, [r3, #65] +1952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2623 .loc 1 1952 25 + 2624 00fc FB68 ldr r3, [r7, #12] + 2625 00fe 0022 movs r2, #0 + 2626 0100 83F84220 strb r2, [r3, #66] +1955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2627 .loc 1 1955 13 + 2628 0104 FB68 ldr r3, [r7, #12] + 2629 0106 5B6C ldr r3, [r3, #68] +1955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2630 .loc 1 1955 25 + 2631 0108 43F08002 orr r2, r3, #128 + 2632 010c FB68 ldr r3, [r7, #12] + 2633 010e 5A64 str r2, [r3, #68] +1958:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2634 .loc 1 1958 9 + 2635 0110 FB68 ldr r3, [r7, #12] + 2636 0112 0022 movs r2, #0 + 2637 0114 83F84020 strb r2, [r3, #64] +1960:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2638 .loc 1 1960 16 + 2639 0118 0123 movs r3, #1 + 2640 011a 50E0 b .L110 + 2641 .L119: +1964:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1965:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send Slave Address */ +1966:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART +1967:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_ + 2642 .loc 1 1967 59 + 2643 011c FB68 ldr r3, [r7, #12] + 2644 011e 1B8D ldrh r3, [r3, #40] + 2645 .loc 1 1967 9 + 2646 0120 DAB2 uxtb r2, r3 + 2647 0122 7989 ldrh r1, [r7, #10] + 2648 0124 2C4B ldr r3, .L120+16 + 2649 0126 0093 str r3, [sp] + 2650 0128 7B69 ldr r3, [r7, #20] + 2651 012a F868 ldr r0, [r7, #12] + 2652 012c FFF7FEFF bl I2C_TransferConfig +1968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1969:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update XferCount value */ +1970:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount -= hi2c->XferSize; + 2653 .loc 1 1970 13 + 2654 0130 FB68 ldr r3, [r7, #12] + ARM GAS /tmp/cc5G5cqz.s page 82 + + + 2655 0132 5B8D ldrh r3, [r3, #42] @ movhi + 2656 0134 9AB2 uxth r2, r3 + 2657 .loc 1 1970 32 + 2658 0136 FB68 ldr r3, [r7, #12] + 2659 0138 1B8D ldrh r3, [r3, #40] + 2660 .loc 1 1970 25 + 2661 013a D31A subs r3, r2, r3 + 2662 013c 9AB2 uxth r2, r3 + 2663 013e FB68 ldr r3, [r7, #12] + 2664 0140 5A85 strh r2, [r3, #42] @ movhi +1971:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1972:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +1973:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 2665 .loc 1 1973 9 + 2666 0142 FB68 ldr r3, [r7, #12] + 2667 0144 0022 movs r2, #0 + 2668 0146 83F84020 strb r2, [r3, #64] +1974:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1975:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +1976:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +1977:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** process unlock */ +1978:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR and NACK interrupts */ +1979:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + 2669 .loc 1 1979 9 + 2670 014a 1021 movs r1, #16 + 2671 014c F868 ldr r0, [r7, #12] + 2672 014e FFF7FEFF bl I2C_Enable_IRQ +1980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1981:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable DMA Request */ +1982:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + 2673 .loc 1 1982 13 + 2674 0152 FB68 ldr r3, [r7, #12] + 2675 0154 1B68 ldr r3, [r3] + 2676 .loc 1 1982 23 + 2677 0156 1A68 ldr r2, [r3] + 2678 .loc 1 1982 13 + 2679 0158 FB68 ldr r3, [r7, #12] + 2680 015a 1B68 ldr r3, [r3] + 2681 .loc 1 1982 29 + 2682 015c 42F48042 orr r2, r2, #16384 + 2683 0160 1A60 str r2, [r3] + 2684 0162 29E0 b .L118 + 2685 .L117: +1983:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +1985:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +1986:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C state */ +1987:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 2686 .loc 1 1987 25 + 2687 0164 FB68 ldr r3, [r7, #12] + 2688 0166 2022 movs r2, #32 + 2689 0168 83F84120 strb r2, [r3, #65] +1988:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 2690 .loc 1 1988 25 + 2691 016c FB68 ldr r3, [r7, #12] + 2692 016e 0022 movs r2, #0 + 2693 0170 83F84220 strb r2, [r3, #66] + ARM GAS /tmp/cc5G5cqz.s page 83 + + +1989:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1990:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C error code */ +1991:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + 2694 .loc 1 1991 13 + 2695 0174 FB68 ldr r3, [r7, #12] + 2696 0176 5B6C ldr r3, [r3, #68] + 2697 .loc 1 1991 25 + 2698 0178 43F01002 orr r2, r3, #16 + 2699 017c FB68 ldr r3, [r7, #12] + 2700 017e 5A64 str r2, [r3, #68] +1992:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1993:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +1994:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 2701 .loc 1 1994 9 + 2702 0180 FB68 ldr r3, [r7, #12] + 2703 0182 0022 movs r2, #0 + 2704 0184 83F84020 strb r2, [r3, #64] +1995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +1996:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 2705 .loc 1 1996 16 + 2706 0188 0123 movs r3, #1 + 2707 018a 18E0 b .L110 + 2708 .L114: +1997:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1998:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +1999:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +2000:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2001:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update Transfer ISR function pointer */ +2002:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 2709 .loc 1 2002 21 + 2710 018c FB68 ldr r3, [r7, #12] + 2711 018e 134A ldr r2, .L120+20 + 2712 0190 5A63 str r2, [r3, #52] +2003:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send Slave Address */ +2005:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set NBYTES to write and generate START condition */ +2006:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 2713 .loc 1 2006 57 + 2714 0192 FB68 ldr r3, [r7, #12] + 2715 0194 1B8D ldrh r3, [r3, #40] + 2716 .loc 1 2006 7 + 2717 0196 DAB2 uxtb r2, r3 + 2718 0198 7989 ldrh r1, [r7, #10] + 2719 019a 0F4B ldr r3, .L120+16 + 2720 019c 0093 str r3, [sp] + 2721 019e 4FF00073 mov r3, #33554432 + 2722 01a2 F868 ldr r0, [r7, #12] + 2723 01a4 FFF7FEFF bl I2C_TransferConfig +2007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_GENERATE_START_WRITE); +2008:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +2010:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 2724 .loc 1 2010 7 + 2725 01a8 FB68 ldr r3, [r7, #12] + 2726 01aa 0022 movs r2, #0 + 2727 01ac 83F84020 strb r2, [r3, #64] +2011:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/cc5G5cqz.s page 84 + + +2012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +2013:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +2014:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** process unlock */ +2015:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, TXI interrupt */ +2016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* possible to enable all of these */ +2017:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | +2018:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ +2019:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + 2728 .loc 1 2019 7 + 2729 01b0 0121 movs r1, #1 + 2730 01b2 F868 ldr r0, [r7, #12] + 2731 01b4 FFF7FEFF bl I2C_Enable_IRQ + 2732 .L118: +2020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2021:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; + 2733 .loc 1 2022 12 + 2734 01b8 0023 movs r3, #0 + 2735 01ba 00E0 b .L110 + 2736 .L108: +2023:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +2025:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; + 2737 .loc 1 2026 12 + 2738 01bc 0223 movs r3, #2 + 2739 .L110: +2027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2028:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2740 .loc 1 2028 1 + 2741 01be 1846 mov r0, r3 + 2742 01c0 1837 adds r7, r7, #24 + 2743 .cfi_def_cfa_offset 8 + 2744 01c2 BD46 mov sp, r7 + 2745 .cfi_def_cfa_register 13 + 2746 @ sp needed + 2747 01c4 80BD pop {r7, pc} + 2748 .L121: + 2749 01c6 00BF .align 2 + 2750 .L120: + 2751 01c8 0000FFFF .word -65536 + 2752 01cc 00000000 .word I2C_Master_ISR_DMA + 2753 01d0 00000000 .word I2C_DMAMasterTransmitCplt + 2754 01d4 00000000 .word I2C_DMAError + 2755 01d8 00200080 .word -2147475456 + 2756 01dc 00000000 .word I2C_Master_ISR_IT + 2757 .cfi_endproc + 2758 .LFE142: + 2760 .section .text.HAL_I2C_Master_Receive_DMA,"ax",%progbits + 2761 .align 1 + 2762 .global HAL_I2C_Master_Receive_DMA + 2763 .syntax unified + 2764 .thumb + 2765 .thumb_func + 2767 HAL_I2C_Master_Receive_DMA: + 2768 .LFB143: +2029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/cc5G5cqz.s page 85 + + +2030:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +2031:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Receive in master mode an amount of data in non-blocking mode with DMA +2032:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2033:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +2034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +2035:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +2036:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer +2037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be sent +2038:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +2039:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +2040:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t +2041:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t Size) +2042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 2769 .loc 1 2042 1 + 2770 .cfi_startproc + 2771 @ args = 0, pretend = 0, frame = 24 + 2772 @ frame_needed = 1, uses_anonymous_args = 0 + 2773 0000 80B5 push {r7, lr} + 2774 .cfi_def_cfa_offset 8 + 2775 .cfi_offset 7, -8 + 2776 .cfi_offset 14, -4 + 2777 0002 88B0 sub sp, sp, #32 + 2778 .cfi_def_cfa_offset 40 + 2779 0004 02AF add r7, sp, #8 + 2780 .cfi_def_cfa 7, 32 + 2781 0006 F860 str r0, [r7, #12] + 2782 0008 7A60 str r2, [r7, #4] + 2783 000a 1A46 mov r2, r3 + 2784 000c 0B46 mov r3, r1 @ movhi + 2785 000e 7B81 strh r3, [r7, #10] @ movhi + 2786 0010 1346 mov r3, r2 @ movhi + 2787 0012 3B81 strh r3, [r7, #8] @ movhi +2043:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xfermode; +2044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; +2045:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2046:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 2788 .loc 1 2046 11 + 2789 0014 FB68 ldr r3, [r7, #12] + 2790 0016 93F84130 ldrb r3, [r3, #65] + 2791 001a DBB2 uxtb r3, r3 + 2792 .loc 1 2046 6 + 2793 001c 202B cmp r3, #32 + 2794 001e 40F0CD80 bne .L123 +2047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + 2795 .loc 1 2048 9 + 2796 0022 FB68 ldr r3, [r7, #12] + 2797 0024 1B68 ldr r3, [r3] + 2798 0026 9B69 ldr r3, [r3, #24] + 2799 0028 03F40043 and r3, r3, #32768 + 2800 .loc 1 2048 8 + 2801 002c B3F5004F cmp r3, #32768 + 2802 0030 01D1 bne .L124 +2049:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2050:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; + 2803 .loc 1 2050 14 + 2804 0032 0223 movs r3, #2 + ARM GAS /tmp/cc5G5cqz.s page 86 + + + 2805 0034 C3E0 b .L125 + 2806 .L124: +2051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2052:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +2054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); + 2807 .loc 1 2054 5 + 2808 0036 FB68 ldr r3, [r7, #12] + 2809 0038 93F84030 ldrb r3, [r3, #64] @ zero_extendqisi2 + 2810 003c 012B cmp r3, #1 + 2811 003e 01D1 bne .L126 + 2812 .loc 1 2054 5 is_stmt 0 discriminator 1 + 2813 0040 0223 movs r3, #2 + 2814 .loc 1 2054 5 + 2815 0042 BCE0 b .L125 + 2816 .L126: + 2817 .loc 1 2054 5 discriminator 2 + 2818 0044 FB68 ldr r3, [r7, #12] + 2819 0046 0122 movs r2, #1 + 2820 0048 83F84020 strb r2, [r3, #64] +2055:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; + 2821 .loc 1 2056 23 is_stmt 1 + 2822 004c FB68 ldr r3, [r7, #12] + 2823 004e 2222 movs r2, #34 + 2824 0050 83F84120 strb r2, [r3, #65] +2057:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 2825 .loc 1 2057 23 + 2826 0054 FB68 ldr r3, [r7, #12] + 2827 0056 1022 movs r2, #16 + 2828 0058 83F84220 strb r2, [r3, #66] +2058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 2829 .loc 1 2058 23 + 2830 005c FB68 ldr r3, [r7, #12] + 2831 005e 0022 movs r2, #0 + 2832 0060 5A64 str r2, [r3, #68] +2059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2060:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ +2061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; + 2833 .loc 1 2061 23 + 2834 0062 FB68 ldr r3, [r7, #12] + 2835 0064 7A68 ldr r2, [r7, #4] + 2836 0066 5A62 str r2, [r3, #36] +2062:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 2837 .loc 1 2062 23 + 2838 0068 FB68 ldr r3, [r7, #12] + 2839 006a 3A89 ldrh r2, [r7, #8] @ movhi + 2840 006c 5A85 strh r2, [r3, #42] @ movhi +2063:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 2841 .loc 1 2063 23 + 2842 006e FB68 ldr r3, [r7, #12] + 2843 0070 554A ldr r2, .L135 + 2844 0072 DA62 str r2, [r3, #44] +2064:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 2845 .loc 1 2064 23 + 2846 0074 FB68 ldr r3, [r7, #12] + 2847 0076 554A ldr r2, .L135+4 + ARM GAS /tmp/cc5G5cqz.s page 87 + + + 2848 0078 5A63 str r2, [r3, #52] +2065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2066:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) + 2849 .loc 1 2066 13 + 2850 007a FB68 ldr r3, [r7, #12] + 2851 007c 5B8D ldrh r3, [r3, #42] @ movhi + 2852 007e 9BB2 uxth r3, r3 + 2853 .loc 1 2066 8 + 2854 0080 FF2B cmp r3, #255 + 2855 0082 06D9 bls .L127 +2067:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; + 2856 .loc 1 2068 22 + 2857 0084 FB68 ldr r3, [r7, #12] + 2858 0086 FF22 movs r2, #255 + 2859 0088 1A85 strh r2, [r3, #40] @ movhi +2069:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 2860 .loc 1 2069 16 + 2861 008a 4FF08073 mov r3, #16777216 + 2862 008e 7B61 str r3, [r7, #20] + 2863 0090 07E0 b .L128 + 2864 .L127: +2070:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +2072:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2073:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 2865 .loc 1 2073 28 + 2866 0092 FB68 ldr r3, [r7, #12] + 2867 0094 5B8D ldrh r3, [r3, #42] @ movhi + 2868 0096 9AB2 uxth r2, r3 + 2869 .loc 1 2073 22 + 2870 0098 FB68 ldr r3, [r7, #12] + 2871 009a 1A85 strh r2, [r3, #40] @ movhi +2074:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 2872 .loc 1 2074 16 + 2873 009c 4FF00073 mov r3, #33554432 + 2874 00a0 7B61 str r3, [r7, #20] + 2875 .L128: +2075:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2076:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2077:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferSize > 0U) + 2876 .loc 1 2077 13 + 2877 00a2 FB68 ldr r3, [r7, #12] + 2878 00a4 1B8D ldrh r3, [r3, #40] + 2879 .loc 1 2077 8 + 2880 00a6 002B cmp r3, #0 + 2881 00a8 70D0 beq .L129 +2078:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2079:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) + 2882 .loc 1 2079 15 + 2883 00aa FB68 ldr r3, [r7, #12] + 2884 00ac DB6B ldr r3, [r3, #60] + 2885 .loc 1 2079 10 + 2886 00ae 002B cmp r3, #0 + 2887 00b0 20D0 beq .L130 +2080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2081:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ + ARM GAS /tmp/cc5G5cqz.s page 88 + + +2082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + 2888 .loc 1 2082 13 + 2889 00b2 FB68 ldr r3, [r7, #12] + 2890 00b4 DB6B ldr r3, [r3, #60] + 2891 .loc 1 2082 40 + 2892 00b6 464A ldr r2, .L135+8 + 2893 00b8 9A62 str r2, [r3, #40] +2083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2084:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the DMA error callback */ +2085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + 2894 .loc 1 2085 13 + 2895 00ba FB68 ldr r3, [r7, #12] + 2896 00bc DB6B ldr r3, [r3, #60] + 2897 .loc 1 2085 41 + 2898 00be 454A ldr r2, .L135+12 + 2899 00c0 1A63 str r2, [r3, #48] +2086:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2087:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +2088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferHalfCpltCallback = NULL; + 2900 .loc 1 2088 13 + 2901 00c2 FB68 ldr r3, [r7, #12] + 2902 00c4 DB6B ldr r3, [r3, #60] + 2903 .loc 1 2088 44 + 2904 00c6 0022 movs r2, #0 + 2905 00c8 DA62 str r2, [r3, #44] +2089:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 2906 .loc 1 2089 13 + 2907 00ca FB68 ldr r3, [r7, #12] + 2908 00cc DB6B ldr r3, [r3, #60] + 2909 .loc 1 2089 41 + 2910 00ce 0022 movs r2, #0 + 2911 00d0 5A63 str r2, [r3, #52] +2090:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2091:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable the DMA channel */ +2092:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)p + 2912 .loc 1 2092 25 + 2913 00d2 FB68 ldr r3, [r7, #12] + 2914 00d4 D86B ldr r0, [r3, #60] + 2915 .loc 1 2092 71 + 2916 00d6 FB68 ldr r3, [r7, #12] + 2917 00d8 1B68 ldr r3, [r3] + 2918 .loc 1 2092 66 + 2919 00da 2433 adds r3, r3, #36 + 2920 .loc 1 2092 25 + 2921 00dc 1946 mov r1, r3 + 2922 00de 7A68 ldr r2, [r7, #4] +2093:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); + 2923 .loc 1 2093 46 + 2924 00e0 FB68 ldr r3, [r7, #12] + 2925 00e2 1B8D ldrh r3, [r3, #40] +2092:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); + 2926 .loc 1 2092 25 + 2927 00e4 FFF7FEFF bl HAL_DMA_Start_IT + 2928 00e8 0346 mov r3, r0 + 2929 00ea FB74 strb r3, [r7, #19] +2094:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else + ARM GAS /tmp/cc5G5cqz.s page 89 + + +2096:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2097:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C state */ +2098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +2099:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +2100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C error code */ +2102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; +2103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +2105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +2108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (dmaxferstatus == HAL_OK) + 2930 .loc 1 2110 10 + 2931 00ec FB7C ldrb r3, [r7, #19] @ zero_extendqisi2 + 2932 00ee 002B cmp r3, #0 + 2933 00f0 38D1 bne .L132 + 2934 00f2 13E0 b .L134 + 2935 .L130: +2098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 2936 .loc 1 2098 25 + 2937 00f4 FB68 ldr r3, [r7, #12] + 2938 00f6 2022 movs r2, #32 + 2939 00f8 83F84120 strb r2, [r3, #65] +2099:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2940 .loc 1 2099 25 + 2941 00fc FB68 ldr r3, [r7, #12] + 2942 00fe 0022 movs r2, #0 + 2943 0100 83F84220 strb r2, [r3, #66] +2102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2944 .loc 1 2102 13 + 2945 0104 FB68 ldr r3, [r7, #12] + 2946 0106 5B6C ldr r3, [r3, #68] +2102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2947 .loc 1 2102 25 + 2948 0108 43F08002 orr r2, r3, #128 + 2949 010c FB68 ldr r3, [r7, #12] + 2950 010e 5A64 str r2, [r3, #68] +2105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 2951 .loc 1 2105 9 + 2952 0110 FB68 ldr r3, [r7, #12] + 2953 0112 0022 movs r2, #0 + 2954 0114 83F84020 strb r2, [r3, #64] +2107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 2955 .loc 1 2107 16 + 2956 0118 0123 movs r3, #1 + 2957 011a 50E0 b .L125 + 2958 .L134: +2111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send Slave Address */ +2113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART * +2114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_ + 2959 .loc 1 2114 59 + 2960 011c FB68 ldr r3, [r7, #12] + 2961 011e 1B8D ldrh r3, [r3, #40] + ARM GAS /tmp/cc5G5cqz.s page 90 + + + 2962 .loc 1 2114 9 + 2963 0120 DAB2 uxtb r2, r3 + 2964 0122 7989 ldrh r1, [r7, #10] + 2965 0124 2C4B ldr r3, .L135+16 + 2966 0126 0093 str r3, [sp] + 2967 0128 7B69 ldr r3, [r7, #20] + 2968 012a F868 ldr r0, [r7, #12] + 2969 012c FFF7FEFF bl I2C_TransferConfig +2115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update XferCount value */ +2117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount -= hi2c->XferSize; + 2970 .loc 1 2117 13 + 2971 0130 FB68 ldr r3, [r7, #12] + 2972 0132 5B8D ldrh r3, [r3, #42] @ movhi + 2973 0134 9AB2 uxth r2, r3 + 2974 .loc 1 2117 32 + 2975 0136 FB68 ldr r3, [r7, #12] + 2976 0138 1B8D ldrh r3, [r3, #40] + 2977 .loc 1 2117 25 + 2978 013a D31A subs r3, r2, r3 + 2979 013c 9AB2 uxth r2, r3 + 2980 013e FB68 ldr r3, [r7, #12] + 2981 0140 5A85 strh r2, [r3, #42] @ movhi +2118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +2120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 2982 .loc 1 2120 9 + 2983 0142 FB68 ldr r3, [r7, #12] + 2984 0144 0022 movs r2, #0 + 2985 0146 83F84020 strb r2, [r3, #64] +2121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +2123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +2124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** process unlock */ +2125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR and NACK interrupts */ +2126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + 2986 .loc 1 2126 9 + 2987 014a 1021 movs r1, #16 + 2988 014c F868 ldr r0, [r7, #12] + 2989 014e FFF7FEFF bl I2C_Enable_IRQ +2127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable DMA Request */ +2129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + 2990 .loc 1 2129 13 + 2991 0152 FB68 ldr r3, [r7, #12] + 2992 0154 1B68 ldr r3, [r3] + 2993 .loc 1 2129 23 + 2994 0156 1A68 ldr r2, [r3] + 2995 .loc 1 2129 13 + 2996 0158 FB68 ldr r3, [r7, #12] + 2997 015a 1B68 ldr r3, [r3] + 2998 .loc 1 2129 29 + 2999 015c 42F40042 orr r2, r2, #32768 + 3000 0160 1A60 str r2, [r3] + 3001 0162 29E0 b .L133 + 3002 .L132: +2130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/cc5G5cqz.s page 91 + + +2131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +2132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C state */ +2134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 3003 .loc 1 2134 25 + 3004 0164 FB68 ldr r3, [r7, #12] + 3005 0166 2022 movs r2, #32 + 3006 0168 83F84120 strb r2, [r3, #65] +2135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 3007 .loc 1 2135 25 + 3008 016c FB68 ldr r3, [r7, #12] + 3009 016e 0022 movs r2, #0 + 3010 0170 83F84220 strb r2, [r3, #66] +2136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C error code */ +2138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + 3011 .loc 1 2138 13 + 3012 0174 FB68 ldr r3, [r7, #12] + 3013 0176 5B6C ldr r3, [r3, #68] + 3014 .loc 1 2138 25 + 3015 0178 43F01002 orr r2, r3, #16 + 3016 017c FB68 ldr r3, [r7, #12] + 3017 017e 5A64 str r2, [r3, #68] +2139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +2141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 3018 .loc 1 2141 9 + 3019 0180 FB68 ldr r3, [r7, #12] + 3020 0182 0022 movs r2, #0 + 3021 0184 83F84020 strb r2, [r3, #64] +2142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 3022 .loc 1 2143 16 + 3023 0188 0123 movs r3, #1 + 3024 018a 18E0 b .L125 + 3025 .L129: +2144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +2147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update Transfer ISR function pointer */ +2149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 3026 .loc 1 2149 21 + 3027 018c FB68 ldr r3, [r7, #12] + 3028 018e 134A ldr r2, .L135+20 + 3029 0190 5A63 str r2, [r3, #52] +2150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send Slave Address */ +2152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set NBYTES to read and generate START condition */ +2153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 3030 .loc 1 2153 57 + 3031 0192 FB68 ldr r3, [r7, #12] + 3032 0194 1B8D ldrh r3, [r3, #40] + 3033 .loc 1 2153 7 + 3034 0196 DAB2 uxtb r2, r3 + 3035 0198 7989 ldrh r1, [r7, #10] + 3036 019a 0F4B ldr r3, .L135+16 + ARM GAS /tmp/cc5G5cqz.s page 92 + + + 3037 019c 0093 str r3, [sp] + 3038 019e 4FF00073 mov r3, #33554432 + 3039 01a2 F868 ldr r0, [r7, #12] + 3040 01a4 FFF7FEFF bl I2C_TransferConfig +2154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_GENERATE_START_READ); +2155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +2157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 3041 .loc 1 2157 7 + 3042 01a8 FB68 ldr r3, [r7, #12] + 3043 01aa 0022 movs r2, #0 + 3044 01ac 83F84020 strb r2, [r3, #64] +2158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +2160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +2161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** process unlock */ +2162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, TXI interrupt */ +2163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* possible to enable all of these */ +2164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | +2165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ +2166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + 3045 .loc 1 2166 7 + 3046 01b0 0121 movs r1, #1 + 3047 01b2 F868 ldr r0, [r7, #12] + 3048 01b4 FFF7FEFF bl I2C_Enable_IRQ + 3049 .L133: +2167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; + 3050 .loc 1 2169 12 + 3051 01b8 0023 movs r3, #0 + 3052 01ba 00E0 b .L125 + 3053 .L123: +2170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +2172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; + 3054 .loc 1 2173 12 + 3055 01bc 0223 movs r3, #2 + 3056 .L125: +2174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3057 .loc 1 2175 1 + 3058 01be 1846 mov r0, r3 + 3059 01c0 1837 adds r7, r7, #24 + 3060 .cfi_def_cfa_offset 8 + 3061 01c2 BD46 mov sp, r7 + 3062 .cfi_def_cfa_register 13 + 3063 @ sp needed + 3064 01c4 80BD pop {r7, pc} + 3065 .L136: + 3066 01c6 00BF .align 2 + 3067 .L135: + 3068 01c8 0000FFFF .word -65536 + 3069 01cc 00000000 .word I2C_Master_ISR_DMA + 3070 01d0 00000000 .word I2C_DMAMasterReceiveCplt + 3071 01d4 00000000 .word I2C_DMAError + ARM GAS /tmp/cc5G5cqz.s page 93 + + + 3072 01d8 00240080 .word -2147474432 + 3073 01dc 00000000 .word I2C_Master_ISR_IT + 3074 .cfi_endproc + 3075 .LFE143: + 3077 .section .text.HAL_I2C_Slave_Transmit_DMA,"ax",%progbits + 3078 .align 1 + 3079 .global HAL_I2C_Slave_Transmit_DMA + 3080 .syntax unified + 3081 .thumb + 3082 .thumb_func + 3084 HAL_I2C_Slave_Transmit_DMA: + 3085 .LFB144: +2176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +2178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA +2179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +2181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer +2182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be sent +2183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +2184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +2185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size +2186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3086 .loc 1 2186 1 + 3087 .cfi_startproc + 3088 @ args = 0, pretend = 0, frame = 24 + 3089 @ frame_needed = 1, uses_anonymous_args = 0 + 3090 0000 80B5 push {r7, lr} + 3091 .cfi_def_cfa_offset 8 + 3092 .cfi_offset 7, -8 + 3093 .cfi_offset 14, -4 + 3094 0002 86B0 sub sp, sp, #24 + 3095 .cfi_def_cfa_offset 32 + 3096 0004 00AF add r7, sp, #0 + 3097 .cfi_def_cfa_register 7 + 3098 0006 F860 str r0, [r7, #12] + 3099 0008 B960 str r1, [r7, #8] + 3100 000a 1346 mov r3, r2 + 3101 000c FB80 strh r3, [r7, #6] @ movhi +2187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; +2188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 3102 .loc 1 2189 11 + 3103 000e FB68 ldr r3, [r7, #12] + 3104 0010 93F84130 ldrb r3, [r3, #65] + 3105 0014 DBB2 uxtb r3, r3 + 3106 .loc 1 2189 6 + 3107 0016 202B cmp r3, #32 + 3108 0018 40F0D180 bne .L138 +2190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) + 3109 .loc 1 2191 8 + 3110 001c BB68 ldr r3, [r7, #8] + 3111 001e 002B cmp r3, #0 + 3112 0020 02D0 beq .L139 + 3113 .loc 1 2191 25 discriminator 1 + 3114 0022 FB88 ldrh r3, [r7, #6] + ARM GAS /tmp/cc5G5cqz.s page 94 + + + 3115 0024 002B cmp r3, #0 + 3116 0026 05D1 bne .L140 + 3117 .L139: +2192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + 3118 .loc 1 2193 23 + 3119 0028 FB68 ldr r3, [r7, #12] + 3120 002a 4FF40072 mov r2, #512 + 3121 002e 5A64 str r2, [r3, #68] +2194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 3122 .loc 1 2194 15 + 3123 0030 0123 movs r3, #1 + 3124 0032 C5E0 b .L141 + 3125 .L140: +2195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +2197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); + 3126 .loc 1 2197 5 + 3127 0034 FB68 ldr r3, [r7, #12] + 3128 0036 93F84030 ldrb r3, [r3, #64] @ zero_extendqisi2 + 3129 003a 012B cmp r3, #1 + 3130 003c 01D1 bne .L142 + 3131 .loc 1 2197 5 is_stmt 0 discriminator 1 + 3132 003e 0223 movs r3, #2 + 3133 .loc 1 2197 5 + 3134 0040 BEE0 b .L141 + 3135 .L142: + 3136 .loc 1 2197 5 discriminator 2 + 3137 0042 FB68 ldr r3, [r7, #12] + 3138 0044 0122 movs r2, #1 + 3139 0046 83F84020 strb r2, [r3, #64] +2198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; + 3140 .loc 1 2199 23 is_stmt 1 + 3141 004a FB68 ldr r3, [r7, #12] + 3142 004c 2122 movs r2, #33 + 3143 004e 83F84120 strb r2, [r3, #65] +2200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 3144 .loc 1 2200 23 + 3145 0052 FB68 ldr r3, [r7, #12] + 3146 0054 2022 movs r2, #32 + 3147 0056 83F84220 strb r2, [r3, #66] +2201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 3148 .loc 1 2201 23 + 3149 005a FB68 ldr r3, [r7, #12] + 3150 005c 0022 movs r2, #0 + 3151 005e 5A64 str r2, [r3, #68] +2202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ +2204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; + 3152 .loc 1 2204 23 + 3153 0060 FB68 ldr r3, [r7, #12] + 3154 0062 BA68 ldr r2, [r7, #8] + 3155 0064 5A62 str r2, [r3, #36] +2205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 3156 .loc 1 2205 23 + 3157 0066 FB68 ldr r3, [r7, #12] + ARM GAS /tmp/cc5G5cqz.s page 95 + + + 3158 0068 FA88 ldrh r2, [r7, #6] @ movhi + 3159 006a 5A85 strh r2, [r3, #42] @ movhi +2206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 3160 .loc 1 2206 29 + 3161 006c FB68 ldr r3, [r7, #12] + 3162 006e 5B8D ldrh r3, [r3, #42] @ movhi + 3163 0070 9AB2 uxth r2, r3 + 3164 .loc 1 2206 23 + 3165 0072 FB68 ldr r3, [r7, #12] + 3166 0074 1A85 strh r2, [r3, #40] @ movhi +2207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3167 .loc 1 2207 23 + 3168 0076 FB68 ldr r3, [r7, #12] + 3169 0078 534A ldr r2, .L150 + 3170 007a DA62 str r2, [r3, #44] +2208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; + 3171 .loc 1 2208 23 + 3172 007c FB68 ldr r3, [r7, #12] + 3173 007e 534A ldr r2, .L150+4 + 3174 0080 5A63 str r2, [r3, #52] +2209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Preload TX data if no stretch enable */ +2211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) + 3175 .loc 1 2211 19 + 3176 0082 FB68 ldr r3, [r7, #12] + 3177 0084 1B6A ldr r3, [r3, #32] + 3178 .loc 1 2211 8 + 3179 0086 B3F5003F cmp r3, #131072 + 3180 008a 17D1 bne .L143 +2212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Preload TX register */ +2214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Write data to TXDR */ +2215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->TXDR = *hi2c->pBuffPtr; + 3181 .loc 1 2215 35 + 3182 008c FB68 ldr r3, [r7, #12] + 3183 008e 5B6A ldr r3, [r3, #36] + 3184 .loc 1 2215 30 + 3185 0090 1A78 ldrb r2, [r3] @ zero_extendqisi2 + 3186 .loc 1 2215 11 + 3187 0092 FB68 ldr r3, [r7, #12] + 3188 0094 1B68 ldr r3, [r3] + 3189 .loc 1 2215 28 + 3190 0096 9A62 str r2, [r3, #40] +2216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Increment Buffer pointer */ +2218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr++; + 3191 .loc 1 2218 11 + 3192 0098 FB68 ldr r3, [r7, #12] + 3193 009a 5B6A ldr r3, [r3, #36] + 3194 .loc 1 2218 21 + 3195 009c 5A1C adds r2, r3, #1 + 3196 009e FB68 ldr r3, [r7, #12] + 3197 00a0 5A62 str r2, [r3, #36] +2219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount--; + 3198 .loc 1 2220 11 + 3199 00a2 FB68 ldr r3, [r7, #12] + ARM GAS /tmp/cc5G5cqz.s page 96 + + + 3200 00a4 5B8D ldrh r3, [r3, #42] @ movhi + 3201 00a6 9BB2 uxth r3, r3 + 3202 .loc 1 2220 22 + 3203 00a8 013B subs r3, r3, #1 + 3204 00aa 9AB2 uxth r2, r3 + 3205 00ac FB68 ldr r3, [r7, #12] + 3206 00ae 5A85 strh r2, [r3, #42] @ movhi +2221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize--; + 3207 .loc 1 2221 11 + 3208 00b0 FB68 ldr r3, [r7, #12] + 3209 00b2 1B8D ldrh r3, [r3, #40] + 3210 .loc 1 2221 21 + 3211 00b4 013B subs r3, r3, #1 + 3212 00b6 9AB2 uxth r2, r3 + 3213 00b8 FB68 ldr r3, [r7, #12] + 3214 00ba 1A85 strh r2, [r3, #40] @ movhi + 3215 .L143: +2222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount != 0U) + 3216 .loc 1 2224 13 + 3217 00bc FB68 ldr r3, [r7, #12] + 3218 00be 5B8D ldrh r3, [r3, #42] @ movhi + 3219 00c0 9BB2 uxth r3, r3 + 3220 .loc 1 2224 8 + 3221 00c2 002B cmp r3, #0 + 3222 00c4 68D0 beq .L144 +2225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) + 3223 .loc 1 2226 15 + 3224 00c6 FB68 ldr r3, [r7, #12] + 3225 00c8 9B6B ldr r3, [r3, #56] + 3226 .loc 1 2226 10 + 3227 00ca 002B cmp r3, #0 + 3228 00cc 22D0 beq .L145 +2227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +2229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; + 3229 .loc 1 2229 13 + 3230 00ce FB68 ldr r3, [r7, #12] + 3231 00d0 9B6B ldr r3, [r3, #56] + 3232 .loc 1 2229 40 + 3233 00d2 3F4A ldr r2, .L150+8 + 3234 00d4 9A62 str r2, [r3, #40] +2230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the DMA error callback */ +2232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + 3235 .loc 1 2232 13 + 3236 00d6 FB68 ldr r3, [r7, #12] + 3237 00d8 9B6B ldr r3, [r3, #56] + 3238 .loc 1 2232 41 + 3239 00da 3E4A ldr r2, .L150+12 + 3240 00dc 1A63 str r2, [r3, #48] +2233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +2235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferHalfCpltCallback = NULL; + 3241 .loc 1 2235 13 + ARM GAS /tmp/cc5G5cqz.s page 97 + + + 3242 00de FB68 ldr r3, [r7, #12] + 3243 00e0 9B6B ldr r3, [r3, #56] + 3244 .loc 1 2235 44 + 3245 00e2 0022 movs r2, #0 + 3246 00e4 DA62 str r2, [r3, #44] +2236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 3247 .loc 1 2236 13 + 3248 00e6 FB68 ldr r3, [r7, #12] + 3249 00e8 9B6B ldr r3, [r3, #56] + 3250 .loc 1 2236 41 + 3251 00ea 0022 movs r2, #0 + 3252 00ec 5A63 str r2, [r3, #52] +2237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable the DMA channel */ +2239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, + 3253 .loc 1 2239 25 + 3254 00ee FB68 ldr r3, [r7, #12] + 3255 00f0 986B ldr r0, [r3, #56] +2240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, + 3256 .loc 1 2240 56 + 3257 00f2 FB68 ldr r3, [r7, #12] + 3258 00f4 5B6A ldr r3, [r3, #36] +2239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, + 3259 .loc 1 2239 25 + 3260 00f6 1946 mov r1, r3 + 3261 .loc 1 2240 83 + 3262 00f8 FB68 ldr r3, [r7, #12] + 3263 00fa 1B68 ldr r3, [r3] + 3264 .loc 1 2240 78 + 3265 00fc 2833 adds r3, r3, #40 +2239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, + 3266 .loc 1 2239 25 + 3267 00fe 1A46 mov r2, r3 +2241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); + 3268 .loc 1 2241 46 + 3269 0100 FB68 ldr r3, [r7, #12] + 3270 0102 1B8D ldrh r3, [r3, #40] +2239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, + 3271 .loc 1 2239 25 + 3272 0104 FFF7FEFF bl HAL_DMA_Start_IT + 3273 0108 0346 mov r3, r0 + 3274 010a FB75 strb r3, [r7, #23] +2242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +2244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C state */ +2246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +2247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +2248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C error code */ +2250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; +2251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +2253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +2256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/cc5G5cqz.s page 98 + + +2257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (dmaxferstatus == HAL_OK) + 3275 .loc 1 2258 10 + 3276 010c FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 3277 010e 002B cmp r3, #0 + 3278 0110 2ED1 bne .L147 + 3279 0112 13E0 b .L149 + 3280 .L145: +2246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 3281 .loc 1 2246 25 + 3282 0114 FB68 ldr r3, [r7, #12] + 3283 0116 2822 movs r2, #40 + 3284 0118 83F84120 strb r2, [r3, #65] +2247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3285 .loc 1 2247 25 + 3286 011c FB68 ldr r3, [r7, #12] + 3287 011e 0022 movs r2, #0 + 3288 0120 83F84220 strb r2, [r3, #66] +2250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3289 .loc 1 2250 13 + 3290 0124 FB68 ldr r3, [r7, #12] + 3291 0126 5B6C ldr r3, [r3, #68] +2250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3292 .loc 1 2250 25 + 3293 0128 43F08002 orr r2, r3, #128 + 3294 012c FB68 ldr r3, [r7, #12] + 3295 012e 5A64 str r2, [r3, #68] +2253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3296 .loc 1 2253 9 + 3297 0130 FB68 ldr r3, [r7, #12] + 3298 0132 0022 movs r2, #0 + 3299 0134 83F84020 strb r2, [r3, #64] +2255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3300 .loc 1 2255 16 + 3301 0138 0123 movs r3, #1 + 3302 013a 41E0 b .L141 + 3303 .L149: +2259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable Address Acknowledge */ +2261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + 3304 .loc 1 2261 13 + 3305 013c FB68 ldr r3, [r7, #12] + 3306 013e 1B68 ldr r3, [r3] + 3307 .loc 1 2261 23 + 3308 0140 5A68 ldr r2, [r3, #4] + 3309 .loc 1 2261 13 + 3310 0142 FB68 ldr r3, [r7, #12] + 3311 0144 1B68 ldr r3, [r3] + 3312 .loc 1 2261 29 + 3313 0146 22F40042 bic r2, r2, #32768 + 3314 014a 5A60 str r2, [r3, #4] +2262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +2264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 3315 .loc 1 2264 9 + 3316 014c FB68 ldr r3, [r7, #12] + 3317 014e 0022 movs r2, #0 + ARM GAS /tmp/cc5G5cqz.s page 99 + + + 3318 0150 83F84020 strb r2, [r3, #64] +2265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +2267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +2268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** process unlock */ +2269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR, STOP, NACK, ADDR interrupts */ +2270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + 3319 .loc 1 2270 9 + 3320 0154 4FF40041 mov r1, #32768 + 3321 0158 F868 ldr r0, [r7, #12] + 3322 015a FFF7FEFF bl I2C_Enable_IRQ +2271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable DMA Request */ +2273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + 3323 .loc 1 2273 13 + 3324 015e FB68 ldr r3, [r7, #12] + 3325 0160 1B68 ldr r3, [r3] + 3326 .loc 1 2273 23 + 3327 0162 1A68 ldr r2, [r3] + 3328 .loc 1 2273 13 + 3329 0164 FB68 ldr r3, [r7, #12] + 3330 0166 1B68 ldr r3, [r3] + 3331 .loc 1 2273 29 + 3332 0168 42F48042 orr r2, r2, #16384 + 3333 016c 1A60 str r2, [r3] + 3334 016e 24E0 b .L148 + 3335 .L147: +2274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +2276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C state */ +2278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; + 3336 .loc 1 2278 25 + 3337 0170 FB68 ldr r3, [r7, #12] + 3338 0172 2822 movs r2, #40 + 3339 0174 83F84120 strb r2, [r3, #65] +2279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 3340 .loc 1 2279 25 + 3341 0178 FB68 ldr r3, [r7, #12] + 3342 017a 0022 movs r2, #0 + 3343 017c 83F84220 strb r2, [r3, #66] +2280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C error code */ +2282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + 3344 .loc 1 2282 13 + 3345 0180 FB68 ldr r3, [r7, #12] + 3346 0182 5B6C ldr r3, [r3, #68] + 3347 .loc 1 2282 25 + 3348 0184 43F01002 orr r2, r3, #16 + 3349 0188 FB68 ldr r3, [r7, #12] + 3350 018a 5A64 str r2, [r3, #68] +2283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +2285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 3351 .loc 1 2285 9 + 3352 018c FB68 ldr r3, [r7, #12] + 3353 018e 0022 movs r2, #0 + ARM GAS /tmp/cc5G5cqz.s page 100 + + + 3354 0190 83F84020 strb r2, [r3, #64] +2286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 3355 .loc 1 2287 16 + 3356 0194 0123 movs r3, #1 + 3357 0196 13E0 b .L141 + 3358 .L144: +2288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +2291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable Address Acknowledge */ +2293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + 3359 .loc 1 2293 11 + 3360 0198 FB68 ldr r3, [r7, #12] + 3361 019a 1B68 ldr r3, [r3] + 3362 .loc 1 2293 21 + 3363 019c 5A68 ldr r2, [r3, #4] + 3364 .loc 1 2293 11 + 3365 019e FB68 ldr r3, [r7, #12] + 3366 01a0 1B68 ldr r3, [r3] + 3367 .loc 1 2293 27 + 3368 01a2 22F40042 bic r2, r2, #32768 + 3369 01a6 5A60 str r2, [r3, #4] +2294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +2296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 3370 .loc 1 2296 7 + 3371 01a8 FB68 ldr r3, [r7, #12] + 3372 01aa 0022 movs r2, #0 + 3373 01ac 83F84020 strb r2, [r3, #64] +2297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +2299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +2300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** process unlock */ +2301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR, STOP, NACK, ADDR interrupts */ +2302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + 3374 .loc 1 2302 7 + 3375 01b0 4FF40041 mov r1, #32768 + 3376 01b4 F868 ldr r0, [r7, #12] + 3377 01b6 FFF7FEFF bl I2C_Enable_IRQ + 3378 .L148: +2303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; + 3379 .loc 1 2305 12 + 3380 01ba 0023 movs r3, #0 + 3381 01bc 00E0 b .L141 + 3382 .L138: +2306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +2308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; + 3383 .loc 1 2309 12 + 3384 01be 0223 movs r3, #2 + 3385 .L141: +2310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/cc5G5cqz.s page 101 + + +2311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3386 .loc 1 2311 1 + 3387 01c0 1846 mov r0, r3 + 3388 01c2 1837 adds r7, r7, #24 + 3389 .cfi_def_cfa_offset 8 + 3390 01c4 BD46 mov sp, r7 + 3391 .cfi_def_cfa_register 13 + 3392 @ sp needed + 3393 01c6 80BD pop {r7, pc} + 3394 .L151: + 3395 .align 2 + 3396 .L150: + 3397 01c8 0000FFFF .word -65536 + 3398 01cc 00000000 .word I2C_Slave_ISR_DMA + 3399 01d0 00000000 .word I2C_DMASlaveTransmitCplt + 3400 01d4 00000000 .word I2C_DMAError + 3401 .cfi_endproc + 3402 .LFE144: + 3404 .section .text.HAL_I2C_Slave_Receive_DMA,"ax",%progbits + 3405 .align 1 + 3406 .global HAL_I2C_Slave_Receive_DMA + 3407 .syntax unified + 3408 .thumb + 3409 .thumb_func + 3411 HAL_I2C_Slave_Receive_DMA: + 3412 .LFB145: +2312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +2314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Receive in slave mode an amount of data in non-blocking mode with DMA +2315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +2317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer +2318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be sent +2319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +2320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +2321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +2322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3413 .loc 1 2322 1 + 3414 .cfi_startproc + 3415 @ args = 0, pretend = 0, frame = 24 + 3416 @ frame_needed = 1, uses_anonymous_args = 0 + 3417 0000 80B5 push {r7, lr} + 3418 .cfi_def_cfa_offset 8 + 3419 .cfi_offset 7, -8 + 3420 .cfi_offset 14, -4 + 3421 0002 86B0 sub sp, sp, #24 + 3422 .cfi_def_cfa_offset 32 + 3423 0004 00AF add r7, sp, #0 + 3424 .cfi_def_cfa_register 7 + 3425 0006 F860 str r0, [r7, #12] + 3426 0008 B960 str r1, [r7, #8] + 3427 000a 1346 mov r3, r2 + 3428 000c FB80 strh r3, [r7, #6] @ movhi +2323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; +2324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 3429 .loc 1 2325 11 + ARM GAS /tmp/cc5G5cqz.s page 102 + + + 3430 000e FB68 ldr r3, [r7, #12] + 3431 0010 93F84130 ldrb r3, [r3, #65] + 3432 0014 DBB2 uxtb r3, r3 + 3433 .loc 1 2325 6 + 3434 0016 202B cmp r3, #32 + 3435 0018 40F09B80 bne .L153 +2326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) + 3436 .loc 1 2327 8 + 3437 001c BB68 ldr r3, [r7, #8] + 3438 001e 002B cmp r3, #0 + 3439 0020 02D0 beq .L154 + 3440 .loc 1 2327 25 discriminator 1 + 3441 0022 FB88 ldrh r3, [r7, #6] + 3442 0024 002B cmp r3, #0 + 3443 0026 05D1 bne .L155 + 3444 .L154: +2328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + 3445 .loc 1 2329 23 + 3446 0028 FB68 ldr r3, [r7, #12] + 3447 002a 4FF40072 mov r2, #512 + 3448 002e 5A64 str r2, [r3, #68] +2330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 3449 .loc 1 2330 15 + 3450 0030 0123 movs r3, #1 + 3451 0032 8FE0 b .L156 + 3452 .L155: +2331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +2333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); + 3453 .loc 1 2333 5 + 3454 0034 FB68 ldr r3, [r7, #12] + 3455 0036 93F84030 ldrb r3, [r3, #64] @ zero_extendqisi2 + 3456 003a 012B cmp r3, #1 + 3457 003c 01D1 bne .L157 + 3458 .loc 1 2333 5 is_stmt 0 discriminator 1 + 3459 003e 0223 movs r3, #2 + 3460 .loc 1 2333 5 + 3461 0040 88E0 b .L156 + 3462 .L157: + 3463 .loc 1 2333 5 discriminator 2 + 3464 0042 FB68 ldr r3, [r7, #12] + 3465 0044 0122 movs r2, #1 + 3466 0046 83F84020 strb r2, [r3, #64] +2334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; + 3467 .loc 1 2335 23 is_stmt 1 + 3468 004a FB68 ldr r3, [r7, #12] + 3469 004c 2222 movs r2, #34 + 3470 004e 83F84120 strb r2, [r3, #65] +2336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 3471 .loc 1 2336 23 + 3472 0052 FB68 ldr r3, [r7, #12] + 3473 0054 2022 movs r2, #32 + 3474 0056 83F84220 strb r2, [r3, #66] +2337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + ARM GAS /tmp/cc5G5cqz.s page 103 + + + 3475 .loc 1 2337 23 + 3476 005a FB68 ldr r3, [r7, #12] + 3477 005c 0022 movs r2, #0 + 3478 005e 5A64 str r2, [r3, #68] +2338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ +2340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; + 3479 .loc 1 2340 23 + 3480 0060 FB68 ldr r3, [r7, #12] + 3481 0062 BA68 ldr r2, [r7, #8] + 3482 0064 5A62 str r2, [r3, #36] +2341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 3483 .loc 1 2341 23 + 3484 0066 FB68 ldr r3, [r7, #12] + 3485 0068 FA88 ldrh r2, [r7, #6] @ movhi + 3486 006a 5A85 strh r2, [r3, #42] @ movhi +2342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 3487 .loc 1 2342 29 + 3488 006c FB68 ldr r3, [r7, #12] + 3489 006e 5B8D ldrh r3, [r3, #42] @ movhi + 3490 0070 9AB2 uxth r2, r3 + 3491 .loc 1 2342 23 + 3492 0072 FB68 ldr r3, [r7, #12] + 3493 0074 1A85 strh r2, [r3, #40] @ movhi +2343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 3494 .loc 1 2343 23 + 3495 0076 FB68 ldr r3, [r7, #12] + 3496 0078 384A ldr r2, .L163 + 3497 007a DA62 str r2, [r3, #44] +2344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; + 3498 .loc 1 2344 23 + 3499 007c FB68 ldr r3, [r7, #12] + 3500 007e 384A ldr r2, .L163+4 + 3501 0080 5A63 str r2, [r3, #52] +2345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) + 3502 .loc 1 2346 13 + 3503 0082 FB68 ldr r3, [r7, #12] + 3504 0084 DB6B ldr r3, [r3, #60] + 3505 .loc 1 2346 8 + 3506 0086 002B cmp r3, #0 + 3507 0088 20D0 beq .L158 +2347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +2349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; + 3508 .loc 1 2349 11 + 3509 008a FB68 ldr r3, [r7, #12] + 3510 008c DB6B ldr r3, [r3, #60] + 3511 .loc 1 2349 38 + 3512 008e 354A ldr r2, .L163+8 + 3513 0090 9A62 str r2, [r3, #40] +2350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the DMA error callback */ +2352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + 3514 .loc 1 2352 11 + 3515 0092 FB68 ldr r3, [r7, #12] + 3516 0094 DB6B ldr r3, [r3, #60] + ARM GAS /tmp/cc5G5cqz.s page 104 + + + 3517 .loc 1 2352 39 + 3518 0096 344A ldr r2, .L163+12 + 3519 0098 1A63 str r2, [r3, #48] +2353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +2355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferHalfCpltCallback = NULL; + 3520 .loc 1 2355 11 + 3521 009a FB68 ldr r3, [r7, #12] + 3522 009c DB6B ldr r3, [r3, #60] + 3523 .loc 1 2355 42 + 3524 009e 0022 movs r2, #0 + 3525 00a0 DA62 str r2, [r3, #44] +2356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 3526 .loc 1 2356 11 + 3527 00a2 FB68 ldr r3, [r7, #12] + 3528 00a4 DB6B ldr r3, [r3, #60] + 3529 .loc 1 2356 39 + 3530 00a6 0022 movs r2, #0 + 3531 00a8 5A63 str r2, [r3, #52] +2357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable the DMA channel */ +2359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pDa + 3532 .loc 1 2359 23 + 3533 00aa FB68 ldr r3, [r7, #12] + 3534 00ac D86B ldr r0, [r3, #60] + 3535 .loc 1 2359 69 + 3536 00ae FB68 ldr r3, [r7, #12] + 3537 00b0 1B68 ldr r3, [r3] + 3538 .loc 1 2359 64 + 3539 00b2 2433 adds r3, r3, #36 + 3540 .loc 1 2359 23 + 3541 00b4 1946 mov r1, r3 + 3542 00b6 BA68 ldr r2, [r7, #8] +2360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); + 3543 .loc 1 2360 44 + 3544 00b8 FB68 ldr r3, [r7, #12] + 3545 00ba 1B8D ldrh r3, [r3, #40] +2359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); + 3546 .loc 1 2359 23 + 3547 00bc FFF7FEFF bl HAL_DMA_Start_IT + 3548 00c0 0346 mov r3, r0 + 3549 00c2 FB75 strb r3, [r7, #23] +2361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +2363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C state */ +2365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +2366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +2367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C error code */ +2369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; +2370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +2372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +2375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/cc5G5cqz.s page 105 + + +2376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (dmaxferstatus == HAL_OK) + 3550 .loc 1 2377 8 + 3551 00c4 FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 3552 00c6 002B cmp r3, #0 + 3553 00c8 2FD1 bne .L160 + 3554 00ca 13E0 b .L162 + 3555 .L158: +2365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 3556 .loc 1 2365 23 + 3557 00cc FB68 ldr r3, [r7, #12] + 3558 00ce 2822 movs r2, #40 + 3559 00d0 83F84120 strb r2, [r3, #65] +2366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3560 .loc 1 2366 23 + 3561 00d4 FB68 ldr r3, [r7, #12] + 3562 00d6 0022 movs r2, #0 + 3563 00d8 83F84220 strb r2, [r3, #66] +2369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3564 .loc 1 2369 11 + 3565 00dc FB68 ldr r3, [r7, #12] + 3566 00de 5B6C ldr r3, [r3, #68] +2369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3567 .loc 1 2369 23 + 3568 00e0 43F08002 orr r2, r3, #128 + 3569 00e4 FB68 ldr r3, [r7, #12] + 3570 00e6 5A64 str r2, [r3, #68] +2372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3571 .loc 1 2372 7 + 3572 00e8 FB68 ldr r3, [r7, #12] + 3573 00ea 0022 movs r2, #0 + 3574 00ec 83F84020 strb r2, [r3, #64] +2374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3575 .loc 1 2374 14 + 3576 00f0 0123 movs r3, #1 + 3577 00f2 2FE0 b .L156 + 3578 .L162: +2378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable Address Acknowledge */ +2380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + 3579 .loc 1 2380 11 + 3580 00f4 FB68 ldr r3, [r7, #12] + 3581 00f6 1B68 ldr r3, [r3] + 3582 .loc 1 2380 21 + 3583 00f8 5A68 ldr r2, [r3, #4] + 3584 .loc 1 2380 11 + 3585 00fa FB68 ldr r3, [r7, #12] + 3586 00fc 1B68 ldr r3, [r3] + 3587 .loc 1 2380 27 + 3588 00fe 22F40042 bic r2, r2, #32768 + 3589 0102 5A60 str r2, [r3, #4] +2381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +2383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 3590 .loc 1 2383 7 + 3591 0104 FB68 ldr r3, [r7, #12] + 3592 0106 0022 movs r2, #0 + ARM GAS /tmp/cc5G5cqz.s page 106 + + + 3593 0108 83F84020 strb r2, [r3, #64] +2384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +2386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +2387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** process unlock */ +2388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR, STOP, NACK, ADDR interrupts */ +2389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + 3594 .loc 1 2389 7 + 3595 010c 4FF40041 mov r1, #32768 + 3596 0110 F868 ldr r0, [r7, #12] + 3597 0112 FFF7FEFF bl I2C_Enable_IRQ +2390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable DMA Request */ +2392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + 3598 .loc 1 2392 11 + 3599 0116 FB68 ldr r3, [r7, #12] + 3600 0118 1B68 ldr r3, [r3] + 3601 .loc 1 2392 21 + 3602 011a 1A68 ldr r2, [r3] + 3603 .loc 1 2392 11 + 3604 011c FB68 ldr r3, [r7, #12] + 3605 011e 1B68 ldr r3, [r3] + 3606 .loc 1 2392 27 + 3607 0120 42F40042 orr r2, r2, #32768 + 3608 0124 1A60 str r2, [r3] +2393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +2395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C state */ +2397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +2398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +2399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C error code */ +2401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; +2402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +2404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +2407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; + 3609 .loc 1 2409 12 + 3610 0126 0023 movs r3, #0 + 3611 0128 14E0 b .L156 + 3612 .L160: +2397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 3613 .loc 1 2397 23 + 3614 012a FB68 ldr r3, [r7, #12] + 3615 012c 2822 movs r2, #40 + 3616 012e 83F84120 strb r2, [r3, #65] +2398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3617 .loc 1 2398 23 + 3618 0132 FB68 ldr r3, [r7, #12] + 3619 0134 0022 movs r2, #0 + 3620 0136 83F84220 strb r2, [r3, #66] +2401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/cc5G5cqz.s page 107 + + + 3621 .loc 1 2401 11 + 3622 013a FB68 ldr r3, [r7, #12] + 3623 013c 5B6C ldr r3, [r3, #68] +2401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3624 .loc 1 2401 23 + 3625 013e 43F01002 orr r2, r3, #16 + 3626 0142 FB68 ldr r3, [r7, #12] + 3627 0144 5A64 str r2, [r3, #68] +2404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 3628 .loc 1 2404 7 + 3629 0146 FB68 ldr r3, [r7, #12] + 3630 0148 0022 movs r2, #0 + 3631 014a 83F84020 strb r2, [r3, #64] +2406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3632 .loc 1 2406 14 + 3633 014e 0123 movs r3, #1 + 3634 0150 00E0 b .L156 + 3635 .L153: +2410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +2412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; + 3636 .loc 1 2413 12 + 3637 0152 0223 movs r3, #2 + 3638 .L156: +2414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 3639 .loc 1 2415 1 + 3640 0154 1846 mov r0, r3 + 3641 0156 1837 adds r7, r7, #24 + 3642 .cfi_def_cfa_offset 8 + 3643 0158 BD46 mov sp, r7 + 3644 .cfi_def_cfa_register 13 + 3645 @ sp needed + 3646 015a 80BD pop {r7, pc} + 3647 .L164: + 3648 .align 2 + 3649 .L163: + 3650 015c 0000FFFF .word -65536 + 3651 0160 00000000 .word I2C_Slave_ISR_DMA + 3652 0164 00000000 .word I2C_DMASlaveReceiveCplt + 3653 0168 00000000 .word I2C_DMAError + 3654 .cfi_endproc + 3655 .LFE145: + 3657 .section .text.HAL_I2C_Mem_Write,"ax",%progbits + 3658 .align 1 + 3659 .global HAL_I2C_Mem_Write + 3660 .syntax unified + 3661 .thumb + 3662 .thumb_func + 3664 HAL_I2C_Mem_Write: + 3665 .LFB146: +2416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +2418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Write an amount of data in blocking mode to a specific memory address +2419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. + ARM GAS /tmp/cc5G5cqz.s page 108 + + +2421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +2422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +2423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param MemAddress Internal memory address +2424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param MemAddSize Size of internal memory address +2425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer +2426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be sent +2427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Timeout Timeout duration +2428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +2429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +2430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddre +2431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Ti +2432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 3666 .loc 1 2432 1 + 3667 .cfi_startproc + 3668 @ args = 12, pretend = 0, frame = 24 + 3669 @ frame_needed = 1, uses_anonymous_args = 0 + 3670 0000 80B5 push {r7, lr} + 3671 .cfi_def_cfa_offset 8 + 3672 .cfi_offset 7, -8 + 3673 .cfi_offset 14, -4 + 3674 0002 88B0 sub sp, sp, #32 + 3675 .cfi_def_cfa_offset 40 + 3676 0004 02AF add r7, sp, #8 + 3677 .cfi_def_cfa 7, 32 + 3678 0006 F860 str r0, [r7, #12] + 3679 0008 0846 mov r0, r1 + 3680 000a 1146 mov r1, r2 + 3681 000c 1A46 mov r2, r3 + 3682 000e 0346 mov r3, r0 @ movhi + 3683 0010 7B81 strh r3, [r7, #10] @ movhi + 3684 0012 0B46 mov r3, r1 @ movhi + 3685 0014 3B81 strh r3, [r7, #8] @ movhi + 3686 0016 1346 mov r3, r2 @ movhi + 3687 0018 FB80 strh r3, [r7, #6] @ movhi +2433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tickstart; +2434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check the parameters */ +2436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); +2437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 3688 .loc 1 2438 11 + 3689 001a FB68 ldr r3, [r7, #12] + 3690 001c 93F84130 ldrb r3, [r3, #65] + 3691 0020 DBB2 uxtb r3, r3 + 3692 .loc 1 2438 6 + 3693 0022 202B cmp r3, #32 + 3694 0024 40F0F980 bne .L166 +2439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) + 3695 .loc 1 2440 8 + 3696 0028 3B6A ldr r3, [r7, #32] + 3697 002a 002B cmp r3, #0 + 3698 002c 02D0 beq .L167 + 3699 .loc 1 2440 25 discriminator 1 + 3700 002e BB8C ldrh r3, [r7, #36] + 3701 0030 002B cmp r3, #0 + 3702 0032 05D1 bne .L168 + ARM GAS /tmp/cc5G5cqz.s page 109 + + + 3703 .L167: +2441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + 3704 .loc 1 2442 23 + 3705 0034 FB68 ldr r3, [r7, #12] + 3706 0036 4FF40072 mov r2, #512 + 3707 003a 5A64 str r2, [r3, #68] +2443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 3708 .loc 1 2443 15 + 3709 003c 0123 movs r3, #1 + 3710 003e EDE0 b .L169 + 3711 .L168: +2444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +2447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); + 3712 .loc 1 2447 5 + 3713 0040 FB68 ldr r3, [r7, #12] + 3714 0042 93F84030 ldrb r3, [r3, #64] @ zero_extendqisi2 + 3715 0046 012B cmp r3, #1 + 3716 0048 01D1 bne .L170 + 3717 .loc 1 2447 5 is_stmt 0 discriminator 1 + 3718 004a 0223 movs r3, #2 + 3719 .loc 1 2447 5 + 3720 004c E6E0 b .L169 + 3721 .L170: + 3722 .loc 1 2447 5 discriminator 2 + 3723 004e FB68 ldr r3, [r7, #12] + 3724 0050 0122 movs r2, #1 + 3725 0052 83F84020 strb r2, [r3, #64] +2448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Init tickstart for timeout management*/ +2450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tickstart = HAL_GetTick(); + 3726 .loc 1 2450 17 is_stmt 1 + 3727 0056 FFF7FEFF bl HAL_GetTick + 3728 005a 7861 str r0, [r7, #20] +2451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK + 3729 .loc 1 2452 9 + 3730 005c 7B69 ldr r3, [r7, #20] + 3731 005e 0093 str r3, [sp] + 3732 0060 1923 movs r3, #25 + 3733 0062 0122 movs r2, #1 + 3734 0064 4FF40041 mov r1, #32768 + 3735 0068 F868 ldr r0, [r7, #12] + 3736 006a FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 3737 006e 0346 mov r3, r0 + 3738 .loc 1 2452 8 discriminator 1 + 3739 0070 002B cmp r3, #0 + 3740 0072 01D0 beq .L171 +2453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 3741 .loc 1 2454 14 + 3742 0074 0123 movs r3, #1 + 3743 0076 D1E0 b .L169 + 3744 .L171: +2455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/cc5G5cqz.s page 110 + + +2456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; + 3745 .loc 1 2457 21 + 3746 0078 FB68 ldr r3, [r7, #12] + 3747 007a 2122 movs r2, #33 + 3748 007c 83F84120 strb r2, [r3, #65] +2458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 3749 .loc 1 2458 21 + 3750 0080 FB68 ldr r3, [r7, #12] + 3751 0082 4022 movs r2, #64 + 3752 0084 83F84220 strb r2, [r3, #66] +2459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 3753 .loc 1 2459 21 + 3754 0088 FB68 ldr r3, [r7, #12] + 3755 008a 0022 movs r2, #0 + 3756 008c 5A64 str r2, [r3, #68] +2460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ +2462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; + 3757 .loc 1 2462 21 + 3758 008e FB68 ldr r3, [r7, #12] + 3759 0090 3A6A ldr r2, [r7, #32] + 3760 0092 5A62 str r2, [r3, #36] +2463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 3761 .loc 1 2463 21 + 3762 0094 FB68 ldr r3, [r7, #12] + 3763 0096 BA8C ldrh r2, [r7, #36] @ movhi + 3764 0098 5A85 strh r2, [r3, #42] @ movhi +2464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = NULL; + 3765 .loc 1 2464 21 + 3766 009a FB68 ldr r3, [r7, #12] + 3767 009c 0022 movs r2, #0 + 3768 009e 5A63 str r2, [r3, #52] +2465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send Slave Address and Memory Address */ +2467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL + 3769 .loc 1 2467 9 + 3770 00a0 F888 ldrh r0, [r7, #6] + 3771 00a2 3A89 ldrh r2, [r7, #8] + 3772 00a4 7989 ldrh r1, [r7, #10] + 3773 00a6 7B69 ldr r3, [r7, #20] + 3774 00a8 0193 str r3, [sp, #4] + 3775 00aa BB6A ldr r3, [r7, #40] + 3776 00ac 0093 str r3, [sp] + 3777 00ae 0346 mov r3, r0 + 3778 00b0 F868 ldr r0, [r7, #12] + 3779 00b2 FFF7FEFF bl I2C_RequestMemoryWrite + 3780 00b6 0346 mov r3, r0 + 3781 .loc 1 2467 8 discriminator 1 + 3782 00b8 002B cmp r3, #0 + 3783 00ba 05D0 beq .L172 +2468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +2470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 3784 .loc 1 2470 7 + 3785 00bc FB68 ldr r3, [r7, #12] + 3786 00be 0022 movs r2, #0 + ARM GAS /tmp/cc5G5cqz.s page 111 + + + 3787 00c0 83F84020 strb r2, [r3, #64] +2471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 3788 .loc 1 2471 14 + 3789 00c4 0123 movs r3, #1 + 3790 00c6 A9E0 b .L169 + 3791 .L172: +2472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ +2475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) + 3792 .loc 1 2475 13 + 3793 00c8 FB68 ldr r3, [r7, #12] + 3794 00ca 5B8D ldrh r3, [r3, #42] @ movhi + 3795 00cc 9BB2 uxth r3, r3 + 3796 .loc 1 2475 8 + 3797 00ce FF2B cmp r3, #255 + 3798 00d0 0ED9 bls .L173 +2476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; + 3799 .loc 1 2477 22 + 3800 00d2 FB68 ldr r3, [r7, #12] + 3801 00d4 FF22 movs r2, #255 + 3802 00d6 1A85 strh r2, [r3, #40] @ movhi +2478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTST + 3803 .loc 1 2478 57 + 3804 00d8 FB68 ldr r3, [r7, #12] + 3805 00da 1B8D ldrh r3, [r3, #40] + 3806 .loc 1 2478 7 + 3807 00dc DAB2 uxtb r2, r3 + 3808 00de 7989 ldrh r1, [r7, #10] + 3809 00e0 0023 movs r3, #0 + 3810 00e2 0093 str r3, [sp] + 3811 00e4 4FF08073 mov r3, #16777216 + 3812 00e8 F868 ldr r0, [r7, #12] + 3813 00ea FFF7FEFF bl I2C_TransferConfig + 3814 00ee 0FE0 b .L179 + 3815 .L173: +2479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +2481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 3816 .loc 1 2482 28 + 3817 00f0 FB68 ldr r3, [r7, #12] + 3818 00f2 5B8D ldrh r3, [r3, #42] @ movhi + 3819 00f4 9AB2 uxth r2, r3 + 3820 .loc 1 2482 22 + 3821 00f6 FB68 ldr r3, [r7, #12] + 3822 00f8 1A85 strh r2, [r3, #40] @ movhi +2483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTS + 3823 .loc 1 2483 57 + 3824 00fa FB68 ldr r3, [r7, #12] + 3825 00fc 1B8D ldrh r3, [r3, #40] + 3826 .loc 1 2483 7 + 3827 00fe DAB2 uxtb r2, r3 + 3828 0100 7989 ldrh r1, [r7, #10] + 3829 0102 0023 movs r3, #0 + 3830 0104 0093 str r3, [sp] + ARM GAS /tmp/cc5G5cqz.s page 112 + + + 3831 0106 4FF00073 mov r3, #33554432 + 3832 010a F868 ldr r0, [r7, #12] + 3833 010c FFF7FEFF bl I2C_TransferConfig + 3834 .L179: +2484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** do +2487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until TXIS flag is set */ +2489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + 3835 .loc 1 2489 11 + 3836 0110 7A69 ldr r2, [r7, #20] + 3837 0112 B96A ldr r1, [r7, #40] + 3838 0114 F868 ldr r0, [r7, #12] + 3839 0116 FFF7FEFF bl I2C_WaitOnTXISFlagUntilTimeout + 3840 011a 0346 mov r3, r0 + 3841 .loc 1 2489 10 discriminator 1 + 3842 011c 002B cmp r3, #0 + 3843 011e 01D0 beq .L175 +2490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 3844 .loc 1 2491 16 + 3845 0120 0123 movs r3, #1 + 3846 0122 7BE0 b .L169 + 3847 .L175: +2492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Write data to TXDR */ +2495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->TXDR = *hi2c->pBuffPtr; + 3848 .loc 1 2495 35 + 3849 0124 FB68 ldr r3, [r7, #12] + 3850 0126 5B6A ldr r3, [r3, #36] + 3851 .loc 1 2495 30 + 3852 0128 1A78 ldrb r2, [r3] @ zero_extendqisi2 + 3853 .loc 1 2495 11 + 3854 012a FB68 ldr r3, [r7, #12] + 3855 012c 1B68 ldr r3, [r3] + 3856 .loc 1 2495 28 + 3857 012e 9A62 str r2, [r3, #40] +2496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Increment Buffer pointer */ +2498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr++; + 3858 .loc 1 2498 11 + 3859 0130 FB68 ldr r3, [r7, #12] + 3860 0132 5B6A ldr r3, [r3, #36] + 3861 .loc 1 2498 21 + 3862 0134 5A1C adds r2, r3, #1 + 3863 0136 FB68 ldr r3, [r7, #12] + 3864 0138 5A62 str r2, [r3, #36] +2499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount--; + 3865 .loc 1 2500 11 + 3866 013a FB68 ldr r3, [r7, #12] + 3867 013c 5B8D ldrh r3, [r3, #42] @ movhi + 3868 013e 9BB2 uxth r3, r3 + 3869 .loc 1 2500 22 + 3870 0140 013B subs r3, r3, #1 + ARM GAS /tmp/cc5G5cqz.s page 113 + + + 3871 0142 9AB2 uxth r2, r3 + 3872 0144 FB68 ldr r3, [r7, #12] + 3873 0146 5A85 strh r2, [r3, #42] @ movhi +2501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize--; + 3874 .loc 1 2501 11 + 3875 0148 FB68 ldr r3, [r7, #12] + 3876 014a 1B8D ldrh r3, [r3, #40] + 3877 .loc 1 2501 21 + 3878 014c 013B subs r3, r3, #1 + 3879 014e 9AB2 uxth r2, r3 + 3880 0150 FB68 ldr r3, [r7, #12] + 3881 0152 1A85 strh r2, [r3, #40] @ movhi +2502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + 3882 .loc 1 2503 16 + 3883 0154 FB68 ldr r3, [r7, #12] + 3884 0156 5B8D ldrh r3, [r3, #42] @ movhi + 3885 0158 9BB2 uxth r3, r3 + 3886 .loc 1 2503 10 + 3887 015a 002B cmp r3, #0 + 3888 015c 34D0 beq .L176 + 3889 .loc 1 2503 43 discriminator 1 + 3890 015e FB68 ldr r3, [r7, #12] + 3891 0160 1B8D ldrh r3, [r3, #40] + 3892 .loc 1 2503 35 discriminator 1 + 3893 0162 002B cmp r3, #0 + 3894 0164 30D1 bne .L176 +2504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until TCR flag is set */ +2506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + 3895 .loc 1 2506 13 + 3896 0166 7B69 ldr r3, [r7, #20] + 3897 0168 0093 str r3, [sp] + 3898 016a BB6A ldr r3, [r7, #40] + 3899 016c 0022 movs r2, #0 + 3900 016e 8021 movs r1, #128 + 3901 0170 F868 ldr r0, [r7, #12] + 3902 0172 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 3903 0176 0346 mov r3, r0 + 3904 .loc 1 2506 12 discriminator 1 + 3905 0178 002B cmp r3, #0 + 3906 017a 01D0 beq .L177 +2507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 3907 .loc 1 2508 18 + 3908 017c 0123 movs r3, #1 + 3909 017e 4DE0 b .L169 + 3910 .L177: +2509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) + 3911 .loc 1 2511 17 + 3912 0180 FB68 ldr r3, [r7, #12] + 3913 0182 5B8D ldrh r3, [r3, #42] @ movhi + 3914 0184 9BB2 uxth r3, r3 + 3915 .loc 1 2511 12 + 3916 0186 FF2B cmp r3, #255 + ARM GAS /tmp/cc5G5cqz.s page 114 + + + 3917 0188 0ED9 bls .L178 +2512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; + 3918 .loc 1 2513 26 + 3919 018a FB68 ldr r3, [r7, #12] + 3920 018c FF22 movs r2, #255 + 3921 018e 1A85 strh r2, [r3, #40] @ movhi +2514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 3922 .loc 1 2514 61 + 3923 0190 FB68 ldr r3, [r7, #12] + 3924 0192 1B8D ldrh r3, [r3, #40] + 3925 .loc 1 2514 11 + 3926 0194 DAB2 uxtb r2, r3 + 3927 0196 7989 ldrh r1, [r7, #10] + 3928 0198 0023 movs r3, #0 + 3929 019a 0093 str r3, [sp] + 3930 019c 4FF08073 mov r3, #16777216 + 3931 01a0 F868 ldr r0, [r7, #12] + 3932 01a2 FFF7FEFF bl I2C_TransferConfig + 3933 01a6 0FE0 b .L176 + 3934 .L178: +2515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_NO_STARTSTOP); +2516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +2518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 3935 .loc 1 2519 32 + 3936 01a8 FB68 ldr r3, [r7, #12] + 3937 01aa 5B8D ldrh r3, [r3, #42] @ movhi + 3938 01ac 9AB2 uxth r2, r3 + 3939 .loc 1 2519 26 + 3940 01ae FB68 ldr r3, [r7, #12] + 3941 01b0 1A85 strh r2, [r3, #40] @ movhi +2520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 3942 .loc 1 2520 61 + 3943 01b2 FB68 ldr r3, [r7, #12] + 3944 01b4 1B8D ldrh r3, [r3, #40] + 3945 .loc 1 2520 11 + 3946 01b6 DAB2 uxtb r2, r3 + 3947 01b8 7989 ldrh r1, [r7, #10] + 3948 01ba 0023 movs r3, #0 + 3949 01bc 0093 str r3, [sp] + 3950 01be 4FF00073 mov r3, #33554432 + 3951 01c2 F868 ldr r0, [r7, #12] + 3952 01c4 FFF7FEFF bl I2C_TransferConfig + 3953 .L176: +2521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_NO_STARTSTOP); +2522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } while (hi2c->XferCount > 0U); + 3954 .loc 1 2525 18 + 3955 01c8 FB68 ldr r3, [r7, #12] + 3956 01ca 5B8D ldrh r3, [r3, #42] @ movhi + 3957 01cc 9BB2 uxth r3, r3 + 3958 .loc 1 2525 30 + 3959 01ce 002B cmp r3, #0 + ARM GAS /tmp/cc5G5cqz.s page 115 + + + 3960 01d0 9ED1 bne .L179 +2526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ +2528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until STOPF flag is reset */ +2529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + 3961 .loc 1 2529 9 + 3962 01d2 7A69 ldr r2, [r7, #20] + 3963 01d4 B96A ldr r1, [r7, #40] + 3964 01d6 F868 ldr r0, [r7, #12] + 3965 01d8 FFF7FEFF bl I2C_WaitOnSTOPFlagUntilTimeout + 3966 01dc 0346 mov r3, r0 + 3967 .loc 1 2529 8 discriminator 1 + 3968 01de 002B cmp r3, #0 + 3969 01e0 01D0 beq .L180 +2530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 3970 .loc 1 2531 14 + 3971 01e2 0123 movs r3, #1 + 3972 01e4 1AE0 b .L169 + 3973 .L180: +2532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear STOP Flag */ +2535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + 3974 .loc 1 2535 5 + 3975 01e6 FB68 ldr r3, [r7, #12] + 3976 01e8 1B68 ldr r3, [r3] + 3977 01ea 2022 movs r2, #32 + 3978 01ec DA61 str r2, [r3, #28] +2536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear Configuration Register 2 */ +2538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_RESET_CR2(hi2c); + 3979 .loc 1 2538 5 + 3980 01ee FB68 ldr r3, [r7, #12] + 3981 01f0 1B68 ldr r3, [r3] + 3982 01f2 5968 ldr r1, [r3, #4] + 3983 01f4 FB68 ldr r3, [r7, #12] + 3984 01f6 1A68 ldr r2, [r3] + 3985 01f8 0A4B ldr r3, .L181 + 3986 01fa 0B40 ands r3, r3, r1 + 3987 01fc 5360 str r3, [r2, #4] +2539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 3988 .loc 1 2540 17 + 3989 01fe FB68 ldr r3, [r7, #12] + 3990 0200 2022 movs r2, #32 + 3991 0202 83F84120 strb r2, [r3, #65] +2541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 3992 .loc 1 2541 17 + 3993 0206 FB68 ldr r3, [r7, #12] + 3994 0208 0022 movs r2, #0 + 3995 020a 83F84220 strb r2, [r3, #66] +2542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +2544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 3996 .loc 1 2544 5 + 3997 020e FB68 ldr r3, [r7, #12] + ARM GAS /tmp/cc5G5cqz.s page 116 + + + 3998 0210 0022 movs r2, #0 + 3999 0212 83F84020 strb r2, [r3, #64] +2545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; + 4000 .loc 1 2546 12 + 4001 0216 0023 movs r3, #0 + 4002 0218 00E0 b .L169 + 4003 .L166: +2547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +2549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; + 4004 .loc 1 2550 12 + 4005 021a 0223 movs r3, #2 + 4006 .L169: +2551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 4007 .loc 1 2552 1 + 4008 021c 1846 mov r0, r3 + 4009 021e 1837 adds r7, r7, #24 + 4010 .cfi_def_cfa_offset 8 + 4011 0220 BD46 mov sp, r7 + 4012 .cfi_def_cfa_register 13 + 4013 @ sp needed + 4014 0222 80BD pop {r7, pc} + 4015 .L182: + 4016 .align 2 + 4017 .L181: + 4018 0224 00E800FE .word -33495040 + 4019 .cfi_endproc + 4020 .LFE146: + 4022 .section .text.HAL_I2C_Mem_Read,"ax",%progbits + 4023 .align 1 + 4024 .global HAL_I2C_Mem_Read + 4025 .syntax unified + 4026 .thumb + 4027 .thumb_func + 4029 HAL_I2C_Mem_Read: + 4030 .LFB147: +2553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +2555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Read an amount of data in blocking mode from a specific memory address +2556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +2558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +2559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +2560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param MemAddress Internal memory address +2561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param MemAddSize Size of internal memory address +2562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer +2563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be sent +2564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Timeout Timeout duration +2565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +2566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +2567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddres +2568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Tim +2569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4031 .loc 1 2569 1 + ARM GAS /tmp/cc5G5cqz.s page 117 + + + 4032 .cfi_startproc + 4033 @ args = 12, pretend = 0, frame = 24 + 4034 @ frame_needed = 1, uses_anonymous_args = 0 + 4035 0000 80B5 push {r7, lr} + 4036 .cfi_def_cfa_offset 8 + 4037 .cfi_offset 7, -8 + 4038 .cfi_offset 14, -4 + 4039 0002 88B0 sub sp, sp, #32 + 4040 .cfi_def_cfa_offset 40 + 4041 0004 02AF add r7, sp, #8 + 4042 .cfi_def_cfa 7, 32 + 4043 0006 F860 str r0, [r7, #12] + 4044 0008 0846 mov r0, r1 + 4045 000a 1146 mov r1, r2 + 4046 000c 1A46 mov r2, r3 + 4047 000e 0346 mov r3, r0 @ movhi + 4048 0010 7B81 strh r3, [r7, #10] @ movhi + 4049 0012 0B46 mov r3, r1 @ movhi + 4050 0014 3B81 strh r3, [r7, #8] @ movhi + 4051 0016 1346 mov r3, r2 @ movhi + 4052 0018 FB80 strh r3, [r7, #6] @ movhi +2570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tickstart; +2571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check the parameters */ +2573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); +2574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 4053 .loc 1 2575 11 + 4054 001a FB68 ldr r3, [r7, #12] + 4055 001c 93F84130 ldrb r3, [r3, #65] + 4056 0020 DBB2 uxtb r3, r3 + 4057 .loc 1 2575 6 + 4058 0022 202B cmp r3, #32 + 4059 0024 40F0FD80 bne .L184 +2576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) + 4060 .loc 1 2577 8 + 4061 0028 3B6A ldr r3, [r7, #32] + 4062 002a 002B cmp r3, #0 + 4063 002c 02D0 beq .L185 + 4064 .loc 1 2577 25 discriminator 1 + 4065 002e BB8C ldrh r3, [r7, #36] + 4066 0030 002B cmp r3, #0 + 4067 0032 05D1 bne .L186 + 4068 .L185: +2578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + 4069 .loc 1 2579 23 + 4070 0034 FB68 ldr r3, [r7, #12] + 4071 0036 4FF40072 mov r2, #512 + 4072 003a 5A64 str r2, [r3, #68] +2580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 4073 .loc 1 2580 15 + 4074 003c 0123 movs r3, #1 + 4075 003e F1E0 b .L187 + 4076 .L186: +2581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/cc5G5cqz.s page 118 + + +2582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +2584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); + 4077 .loc 1 2584 5 + 4078 0040 FB68 ldr r3, [r7, #12] + 4079 0042 93F84030 ldrb r3, [r3, #64] @ zero_extendqisi2 + 4080 0046 012B cmp r3, #1 + 4081 0048 01D1 bne .L188 + 4082 .loc 1 2584 5 is_stmt 0 discriminator 1 + 4083 004a 0223 movs r3, #2 + 4084 .loc 1 2584 5 + 4085 004c EAE0 b .L187 + 4086 .L188: + 4087 .loc 1 2584 5 discriminator 2 + 4088 004e FB68 ldr r3, [r7, #12] + 4089 0050 0122 movs r2, #1 + 4090 0052 83F84020 strb r2, [r3, #64] +2585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Init tickstart for timeout management*/ +2587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tickstart = HAL_GetTick(); + 4091 .loc 1 2587 17 is_stmt 1 + 4092 0056 FFF7FEFF bl HAL_GetTick + 4093 005a 7861 str r0, [r7, #20] +2588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK + 4094 .loc 1 2589 9 + 4095 005c 7B69 ldr r3, [r7, #20] + 4096 005e 0093 str r3, [sp] + 4097 0060 1923 movs r3, #25 + 4098 0062 0122 movs r2, #1 + 4099 0064 4FF40041 mov r1, #32768 + 4100 0068 F868 ldr r0, [r7, #12] + 4101 006a FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 4102 006e 0346 mov r3, r0 + 4103 .loc 1 2589 8 discriminator 1 + 4104 0070 002B cmp r3, #0 + 4105 0072 01D0 beq .L189 +2590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 4106 .loc 1 2591 14 + 4107 0074 0123 movs r3, #1 + 4108 0076 D5E0 b .L187 + 4109 .L189: +2592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; + 4110 .loc 1 2594 21 + 4111 0078 FB68 ldr r3, [r7, #12] + 4112 007a 2222 movs r2, #34 + 4113 007c 83F84120 strb r2, [r3, #65] +2595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 4114 .loc 1 2595 21 + 4115 0080 FB68 ldr r3, [r7, #12] + 4116 0082 4022 movs r2, #64 + 4117 0084 83F84220 strb r2, [r3, #66] +2596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 4118 .loc 1 2596 21 + ARM GAS /tmp/cc5G5cqz.s page 119 + + + 4119 0088 FB68 ldr r3, [r7, #12] + 4120 008a 0022 movs r2, #0 + 4121 008c 5A64 str r2, [r3, #68] +2597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ +2599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; + 4122 .loc 1 2599 21 + 4123 008e FB68 ldr r3, [r7, #12] + 4124 0090 3A6A ldr r2, [r7, #32] + 4125 0092 5A62 str r2, [r3, #36] +2600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 4126 .loc 1 2600 21 + 4127 0094 FB68 ldr r3, [r7, #12] + 4128 0096 BA8C ldrh r2, [r7, #36] @ movhi + 4129 0098 5A85 strh r2, [r3, #42] @ movhi +2601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = NULL; + 4130 .loc 1 2601 21 + 4131 009a FB68 ldr r3, [r7, #12] + 4132 009c 0022 movs r2, #0 + 4133 009e 5A63 str r2, [r3, #52] +2602:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send Slave Address and Memory Address */ +2604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_ + 4134 .loc 1 2604 9 + 4135 00a0 F888 ldrh r0, [r7, #6] + 4136 00a2 3A89 ldrh r2, [r7, #8] + 4137 00a4 7989 ldrh r1, [r7, #10] + 4138 00a6 7B69 ldr r3, [r7, #20] + 4139 00a8 0193 str r3, [sp, #4] + 4140 00aa BB6A ldr r3, [r7, #40] + 4141 00ac 0093 str r3, [sp] + 4142 00ae 0346 mov r3, r0 + 4143 00b0 F868 ldr r0, [r7, #12] + 4144 00b2 FFF7FEFF bl I2C_RequestMemoryRead + 4145 00b6 0346 mov r3, r0 + 4146 .loc 1 2604 8 discriminator 1 + 4147 00b8 002B cmp r3, #0 + 4148 00ba 05D0 beq .L190 +2605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +2607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 4149 .loc 1 2607 7 + 4150 00bc FB68 ldr r3, [r7, #12] + 4151 00be 0022 movs r2, #0 + 4152 00c0 83F84020 strb r2, [r3, #64] +2608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 4153 .loc 1 2608 14 + 4154 00c4 0123 movs r3, #1 + 4155 00c6 ADE0 b .L187 + 4156 .L190: +2609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send Slave Address */ +2612:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ +2613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) + 4157 .loc 1 2613 13 + 4158 00c8 FB68 ldr r3, [r7, #12] + ARM GAS /tmp/cc5G5cqz.s page 120 + + + 4159 00ca 5B8D ldrh r3, [r3, #42] @ movhi + 4160 00cc 9BB2 uxth r3, r3 + 4161 .loc 1 2613 8 + 4162 00ce FF2B cmp r3, #255 + 4163 00d0 0ED9 bls .L191 +2614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; + 4164 .loc 1 2615 22 + 4165 00d2 FB68 ldr r3, [r7, #12] + 4166 00d4 FF22 movs r2, #255 + 4167 00d6 1A85 strh r2, [r3, #40] @ movhi +2616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + 4168 .loc 1 2616 57 + 4169 00d8 FB68 ldr r3, [r7, #12] + 4170 00da 1B8D ldrh r3, [r3, #40] + 4171 .loc 1 2616 7 + 4172 00dc DAB2 uxtb r2, r3 + 4173 00de 7989 ldrh r1, [r7, #10] + 4174 00e0 524B ldr r3, .L199 + 4175 00e2 0093 str r3, [sp] + 4176 00e4 4FF08073 mov r3, #16777216 + 4177 00e8 F868 ldr r0, [r7, #12] + 4178 00ea FFF7FEFF bl I2C_TransferConfig + 4179 00ee 0FE0 b .L197 + 4180 .L191: +2617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_GENERATE_START_READ); +2618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +2620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 4181 .loc 1 2621 28 + 4182 00f0 FB68 ldr r3, [r7, #12] + 4183 00f2 5B8D ldrh r3, [r3, #42] @ movhi + 4184 00f4 9AB2 uxth r2, r3 + 4185 .loc 1 2621 22 + 4186 00f6 FB68 ldr r3, [r7, #12] + 4187 00f8 1A85 strh r2, [r3, #40] @ movhi +2622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 4188 .loc 1 2622 57 + 4189 00fa FB68 ldr r3, [r7, #12] + 4190 00fc 1B8D ldrh r3, [r3, #40] + 4191 .loc 1 2622 7 + 4192 00fe DAB2 uxtb r2, r3 + 4193 0100 7989 ldrh r1, [r7, #10] + 4194 0102 4A4B ldr r3, .L199 + 4195 0104 0093 str r3, [sp] + 4196 0106 4FF00073 mov r3, #33554432 + 4197 010a F868 ldr r0, [r7, #12] + 4198 010c FFF7FEFF bl I2C_TransferConfig + 4199 .L197: +2623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_GENERATE_START_READ); +2624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** do +2627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until RXNE flag is set */ +2629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) + ARM GAS /tmp/cc5G5cqz.s page 121 + + + 4200 .loc 1 2629 11 + 4201 0110 7B69 ldr r3, [r7, #20] + 4202 0112 0093 str r3, [sp] + 4203 0114 BB6A ldr r3, [r7, #40] + 4204 0116 0022 movs r2, #0 + 4205 0118 0421 movs r1, #4 + 4206 011a F868 ldr r0, [r7, #12] + 4207 011c FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 4208 0120 0346 mov r3, r0 + 4209 .loc 1 2629 10 discriminator 1 + 4210 0122 002B cmp r3, #0 + 4211 0124 01D0 beq .L193 +2630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 4212 .loc 1 2631 16 + 4213 0126 0123 movs r3, #1 + 4214 0128 7CE0 b .L187 + 4215 .L193: +2632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Read data from RXDR */ +2635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + 4216 .loc 1 2635 38 + 4217 012a FB68 ldr r3, [r7, #12] + 4218 012c 1B68 ldr r3, [r3] + 4219 .loc 1 2635 48 + 4220 012e 5A6A ldr r2, [r3, #36] + 4221 .loc 1 2635 12 + 4222 0130 FB68 ldr r3, [r7, #12] + 4223 0132 5B6A ldr r3, [r3, #36] + 4224 .loc 1 2635 25 + 4225 0134 D2B2 uxtb r2, r2 + 4226 .loc 1 2635 23 + 4227 0136 1A70 strb r2, [r3] +2636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Increment Buffer pointer */ +2638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr++; + 4228 .loc 1 2638 11 + 4229 0138 FB68 ldr r3, [r7, #12] + 4230 013a 5B6A ldr r3, [r3, #36] + 4231 .loc 1 2638 21 + 4232 013c 5A1C adds r2, r3, #1 + 4233 013e FB68 ldr r3, [r7, #12] + 4234 0140 5A62 str r2, [r3, #36] +2639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize--; + 4235 .loc 1 2640 11 + 4236 0142 FB68 ldr r3, [r7, #12] + 4237 0144 1B8D ldrh r3, [r3, #40] + 4238 .loc 1 2640 21 + 4239 0146 013B subs r3, r3, #1 + 4240 0148 9AB2 uxth r2, r3 + 4241 014a FB68 ldr r3, [r7, #12] + 4242 014c 1A85 strh r2, [r3, #40] @ movhi +2641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount--; + 4243 .loc 1 2641 11 + 4244 014e FB68 ldr r3, [r7, #12] + ARM GAS /tmp/cc5G5cqz.s page 122 + + + 4245 0150 5B8D ldrh r3, [r3, #42] @ movhi + 4246 0152 9BB2 uxth r3, r3 + 4247 .loc 1 2641 22 + 4248 0154 013B subs r3, r3, #1 + 4249 0156 9AB2 uxth r2, r3 + 4250 0158 FB68 ldr r3, [r7, #12] + 4251 015a 5A85 strh r2, [r3, #42] @ movhi +2642:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + 4252 .loc 1 2643 16 + 4253 015c FB68 ldr r3, [r7, #12] + 4254 015e 5B8D ldrh r3, [r3, #42] @ movhi + 4255 0160 9BB2 uxth r3, r3 + 4256 .loc 1 2643 10 + 4257 0162 002B cmp r3, #0 + 4258 0164 34D0 beq .L194 + 4259 .loc 1 2643 43 discriminator 1 + 4260 0166 FB68 ldr r3, [r7, #12] + 4261 0168 1B8D ldrh r3, [r3, #40] + 4262 .loc 1 2643 35 discriminator 1 + 4263 016a 002B cmp r3, #0 + 4264 016c 30D1 bne .L194 +2644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until TCR flag is set */ +2646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + 4265 .loc 1 2646 13 + 4266 016e 7B69 ldr r3, [r7, #20] + 4267 0170 0093 str r3, [sp] + 4268 0172 BB6A ldr r3, [r7, #40] + 4269 0174 0022 movs r2, #0 + 4270 0176 8021 movs r1, #128 + 4271 0178 F868 ldr r0, [r7, #12] + 4272 017a FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 4273 017e 0346 mov r3, r0 + 4274 .loc 1 2646 12 discriminator 1 + 4275 0180 002B cmp r3, #0 + 4276 0182 01D0 beq .L195 +2647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 4277 .loc 1 2648 18 + 4278 0184 0123 movs r3, #1 + 4279 0186 4DE0 b .L187 + 4280 .L195: +2649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) + 4281 .loc 1 2651 17 + 4282 0188 FB68 ldr r3, [r7, #12] + 4283 018a 5B8D ldrh r3, [r3, #42] @ movhi + 4284 018c 9BB2 uxth r3, r3 + 4285 .loc 1 2651 12 + 4286 018e FF2B cmp r3, #255 + 4287 0190 0ED9 bls .L196 +2652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; + 4288 .loc 1 2653 26 + 4289 0192 FB68 ldr r3, [r7, #12] + ARM GAS /tmp/cc5G5cqz.s page 123 + + + 4290 0194 FF22 movs r2, #255 + 4291 0196 1A85 strh r2, [r3, #40] @ movhi +2654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, + 4292 .loc 1 2654 62 + 4293 0198 FB68 ldr r3, [r7, #12] + 4294 019a 1B8D ldrh r3, [r3, #40] + 4295 .loc 1 2654 11 + 4296 019c DAB2 uxtb r2, r3 + 4297 019e 7989 ldrh r1, [r7, #10] + 4298 01a0 0023 movs r3, #0 + 4299 01a2 0093 str r3, [sp] + 4300 01a4 4FF08073 mov r3, #16777216 + 4301 01a8 F868 ldr r0, [r7, #12] + 4302 01aa FFF7FEFF bl I2C_TransferConfig + 4303 01ae 0FE0 b .L194 + 4304 .L196: +2655:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_NO_STARTSTOP); +2656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2657:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +2658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2659:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 4305 .loc 1 2659 32 + 4306 01b0 FB68 ldr r3, [r7, #12] + 4307 01b2 5B8D ldrh r3, [r3, #42] @ movhi + 4308 01b4 9AB2 uxth r2, r3 + 4309 .loc 1 2659 26 + 4310 01b6 FB68 ldr r3, [r7, #12] + 4311 01b8 1A85 strh r2, [r3, #40] @ movhi +2660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 4312 .loc 1 2660 61 + 4313 01ba FB68 ldr r3, [r7, #12] + 4314 01bc 1B8D ldrh r3, [r3, #40] + 4315 .loc 1 2660 11 + 4316 01be DAB2 uxtb r2, r3 + 4317 01c0 7989 ldrh r1, [r7, #10] + 4318 01c2 0023 movs r3, #0 + 4319 01c4 0093 str r3, [sp] + 4320 01c6 4FF00073 mov r3, #33554432 + 4321 01ca F868 ldr r0, [r7, #12] + 4322 01cc FFF7FEFF bl I2C_TransferConfig + 4323 .L194: +2661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_NO_STARTSTOP); +2662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2664:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } while (hi2c->XferCount > 0U); + 4324 .loc 1 2664 18 + 4325 01d0 FB68 ldr r3, [r7, #12] + 4326 01d2 5B8D ldrh r3, [r3, #42] @ movhi + 4327 01d4 9BB2 uxth r3, r3 + 4328 .loc 1 2664 30 + 4329 01d6 002B cmp r3, #0 + 4330 01d8 9AD1 bne .L197 +2665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ +2667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until STOPF flag is reset */ +2668:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + 4331 .loc 1 2668 9 + ARM GAS /tmp/cc5G5cqz.s page 124 + + + 4332 01da 7A69 ldr r2, [r7, #20] + 4333 01dc B96A ldr r1, [r7, #40] + 4334 01de F868 ldr r0, [r7, #12] + 4335 01e0 FFF7FEFF bl I2C_WaitOnSTOPFlagUntilTimeout + 4336 01e4 0346 mov r3, r0 + 4337 .loc 1 2668 8 discriminator 1 + 4338 01e6 002B cmp r3, #0 + 4339 01e8 01D0 beq .L198 +2669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 4340 .loc 1 2670 14 + 4341 01ea 0123 movs r3, #1 + 4342 01ec 1AE0 b .L187 + 4343 .L198: +2671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear STOP Flag */ +2674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + 4344 .loc 1 2674 5 + 4345 01ee FB68 ldr r3, [r7, #12] + 4346 01f0 1B68 ldr r3, [r3] + 4347 01f2 2022 movs r2, #32 + 4348 01f4 DA61 str r2, [r3, #28] +2675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear Configuration Register 2 */ +2677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_RESET_CR2(hi2c); + 4349 .loc 1 2677 5 + 4350 01f6 FB68 ldr r3, [r7, #12] + 4351 01f8 1B68 ldr r3, [r3] + 4352 01fa 5968 ldr r1, [r3, #4] + 4353 01fc FB68 ldr r3, [r7, #12] + 4354 01fe 1A68 ldr r2, [r3] + 4355 0200 0B4B ldr r3, .L199+4 + 4356 0202 0B40 ands r3, r3, r1 + 4357 0204 5360 str r3, [r2, #4] +2678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 4358 .loc 1 2679 17 + 4359 0206 FB68 ldr r3, [r7, #12] + 4360 0208 2022 movs r2, #32 + 4361 020a 83F84120 strb r2, [r3, #65] +2680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 4362 .loc 1 2680 17 + 4363 020e FB68 ldr r3, [r7, #12] + 4364 0210 0022 movs r2, #0 + 4365 0212 83F84220 strb r2, [r3, #66] +2681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +2683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 4366 .loc 1 2683 5 + 4367 0216 FB68 ldr r3, [r7, #12] + 4368 0218 0022 movs r2, #0 + 4369 021a 83F84020 strb r2, [r3, #64] +2684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; + 4370 .loc 1 2685 12 + 4371 021e 0023 movs r3, #0 + ARM GAS /tmp/cc5G5cqz.s page 125 + + + 4372 0220 00E0 b .L187 + 4373 .L184: +2686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +2688:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; + 4374 .loc 1 2689 12 + 4375 0222 0223 movs r3, #2 + 4376 .L187: +2690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 4377 .loc 1 2691 1 + 4378 0224 1846 mov r0, r3 + 4379 0226 1837 adds r7, r7, #24 + 4380 .cfi_def_cfa_offset 8 + 4381 0228 BD46 mov sp, r7 + 4382 .cfi_def_cfa_register 13 + 4383 @ sp needed + 4384 022a 80BD pop {r7, pc} + 4385 .L200: + 4386 .align 2 + 4387 .L199: + 4388 022c 00240080 .word -2147474432 + 4389 0230 00E800FE .word -33495040 + 4390 .cfi_endproc + 4391 .LFE147: + 4393 .section .text.HAL_I2C_Mem_Write_IT,"ax",%progbits + 4394 .align 1 + 4395 .global HAL_I2C_Mem_Write_IT + 4396 .syntax unified + 4397 .thumb + 4398 .thumb_func + 4400 HAL_I2C_Mem_Write_IT: + 4401 .LFB148: +2692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +2693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory addres +2694:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +2696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +2697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +2698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param MemAddress Internal memory address +2699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param MemAddSize Size of internal memory address +2700:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer +2701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be sent +2702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +2703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +2704:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAd +2705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +2706:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4402 .loc 1 2706 1 + 4403 .cfi_startproc + 4404 @ args = 8, pretend = 0, frame = 16 + 4405 @ frame_needed = 1, uses_anonymous_args = 0 + 4406 0000 80B5 push {r7, lr} + 4407 .cfi_def_cfa_offset 8 + 4408 .cfi_offset 7, -8 + 4409 .cfi_offset 14, -4 + ARM GAS /tmp/cc5G5cqz.s page 126 + + + 4410 0002 86B0 sub sp, sp, #24 + 4411 .cfi_def_cfa_offset 32 + 4412 0004 02AF add r7, sp, #8 + 4413 .cfi_def_cfa 7, 24 + 4414 0006 F860 str r0, [r7, #12] + 4415 0008 0846 mov r0, r1 + 4416 000a 1146 mov r1, r2 + 4417 000c 1A46 mov r2, r3 + 4418 000e 0346 mov r3, r0 @ movhi + 4419 0010 7B81 strh r3, [r7, #10] @ movhi + 4420 0012 0B46 mov r3, r1 @ movhi + 4421 0014 3B81 strh r3, [r7, #8] @ movhi + 4422 0016 1346 mov r3, r2 @ movhi + 4423 0018 FB80 strh r3, [r7, #6] @ movhi +2707:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check the parameters */ +2708:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); +2709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 4424 .loc 1 2710 11 + 4425 001a FB68 ldr r3, [r7, #12] + 4426 001c 93F84130 ldrb r3, [r3, #65] + 4427 0020 DBB2 uxtb r3, r3 + 4428 .loc 1 2710 6 + 4429 0022 202B cmp r3, #32 + 4430 0024 67D1 bne .L202 +2711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) + 4431 .loc 1 2712 8 + 4432 0026 BB69 ldr r3, [r7, #24] + 4433 0028 002B cmp r3, #0 + 4434 002a 02D0 beq .L203 + 4435 .loc 1 2712 25 discriminator 1 + 4436 002c BB8B ldrh r3, [r7, #28] + 4437 002e 002B cmp r3, #0 + 4438 0030 05D1 bne .L204 + 4439 .L203: +2713:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + 4440 .loc 1 2714 23 + 4441 0032 FB68 ldr r3, [r7, #12] + 4442 0034 4FF40072 mov r2, #512 + 4443 0038 5A64 str r2, [r3, #68] +2715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 4444 .loc 1 2715 15 + 4445 003a 0123 movs r3, #1 + 4446 003c 5CE0 b .L205 + 4447 .L204: +2716:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2718:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + 4448 .loc 1 2718 9 + 4449 003e FB68 ldr r3, [r7, #12] + 4450 0040 1B68 ldr r3, [r3] + 4451 0042 9B69 ldr r3, [r3, #24] + 4452 0044 03F40043 and r3, r3, #32768 + 4453 .loc 1 2718 8 + 4454 0048 B3F5004F cmp r3, #32768 + ARM GAS /tmp/cc5G5cqz.s page 127 + + + 4455 004c 01D1 bne .L206 +2719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2720:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; + 4456 .loc 1 2720 14 + 4457 004e 0223 movs r3, #2 + 4458 0050 52E0 b .L205 + 4459 .L206: +2721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2722:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2723:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +2724:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); + 4460 .loc 1 2724 5 + 4461 0052 FB68 ldr r3, [r7, #12] + 4462 0054 93F84030 ldrb r3, [r3, #64] @ zero_extendqisi2 + 4463 0058 012B cmp r3, #1 + 4464 005a 01D1 bne .L207 + 4465 .loc 1 2724 5 is_stmt 0 discriminator 1 + 4466 005c 0223 movs r3, #2 + 4467 .loc 1 2724 5 + 4468 005e 4BE0 b .L205 + 4469 .L207: + 4470 .loc 1 2724 5 discriminator 2 + 4471 0060 FB68 ldr r3, [r7, #12] + 4472 0062 0122 movs r2, #1 + 4473 0064 83F84020 strb r2, [r3, #64] +2725:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; + 4474 .loc 1 2726 23 is_stmt 1 + 4475 0068 FB68 ldr r3, [r7, #12] + 4476 006a 2122 movs r2, #33 + 4477 006c 83F84120 strb r2, [r3, #65] +2727:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 4478 .loc 1 2727 23 + 4479 0070 FB68 ldr r3, [r7, #12] + 4480 0072 4022 movs r2, #64 + 4481 0074 83F84220 strb r2, [r3, #66] +2728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 4482 .loc 1 2728 23 + 4483 0078 FB68 ldr r3, [r7, #12] + 4484 007a 0022 movs r2, #0 + 4485 007c 5A64 str r2, [r3, #68] +2729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ +2731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; + 4486 .loc 1 2731 23 + 4487 007e FB68 ldr r3, [r7, #12] + 4488 0080 BA69 ldr r2, [r7, #24] + 4489 0082 5A62 str r2, [r3, #36] +2732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 4490 .loc 1 2732 23 + 4491 0084 FB68 ldr r3, [r7, #12] + 4492 0086 BA8B ldrh r2, [r7, #28] @ movhi + 4493 0088 5A85 strh r2, [r3, #42] @ movhi +2733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 4494 .loc 1 2733 23 + 4495 008a FB68 ldr r3, [r7, #12] + 4496 008c 1C4A ldr r2, .L210 + ARM GAS /tmp/cc5G5cqz.s page 128 + + + 4497 008e DA62 str r2, [r3, #44] +2734:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Mem_ISR_IT; + 4498 .loc 1 2734 23 + 4499 0090 FB68 ldr r3, [r7, #12] + 4500 0092 1C4A ldr r2, .L210+4 + 4501 0094 5A63 str r2, [r3, #52] +2735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Devaddress = DevAddress; + 4502 .loc 1 2735 23 + 4503 0096 7A89 ldrh r2, [r7, #10] + 4504 0098 FB68 ldr r3, [r7, #12] + 4505 009a DA64 str r2, [r3, #76] +2736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2737:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* If Memory address size is 8Bit */ +2738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + 4506 .loc 1 2738 8 + 4507 009c FB88 ldrh r3, [r7, #6] + 4508 009e 012B cmp r3, #1 + 4509 00a0 09D1 bne .L208 +2739:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prefetch Memory Address */ +2741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + 4510 .loc 1 2741 30 + 4511 00a2 3B89 ldrh r3, [r7, #8] @ movhi + 4512 00a4 DAB2 uxtb r2, r3 + 4513 .loc 1 2741 11 + 4514 00a6 FB68 ldr r3, [r7, #12] + 4515 00a8 1B68 ldr r3, [r3] + 4516 .loc 1 2741 28 + 4517 00aa 9A62 str r2, [r3, #40] +2742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2743:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Reset Memaddress content */ +2744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Memaddress = 0xFFFFFFFFU; + 4518 .loc 1 2744 24 + 4519 00ac FB68 ldr r3, [r7, #12] + 4520 00ae 4FF0FF32 mov r2, #-1 + 4521 00b2 1A65 str r2, [r3, #80] + 4522 00b4 0BE0 b .L209 + 4523 .L208: +2745:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2746:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* If Memory address size is 16Bit */ +2747:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +2748:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ +2750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + 4524 .loc 1 2750 30 + 4525 00b6 3B89 ldrh r3, [r7, #8] + 4526 00b8 1B0A lsrs r3, r3, #8 + 4527 00ba 9BB2 uxth r3, r3 + 4528 00bc DAB2 uxtb r2, r3 + 4529 .loc 1 2750 11 + 4530 00be FB68 ldr r3, [r7, #12] + 4531 00c0 1B68 ldr r3, [r3] + 4532 .loc 1 2750 28 + 4533 00c2 9A62 str r2, [r3, #40] +2751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2752:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare Memaddress buffer for LSB part */ +2753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); + ARM GAS /tmp/cc5G5cqz.s page 129 + + + 4534 .loc 1 2753 26 + 4535 00c4 3B89 ldrh r3, [r7, #8] @ movhi + 4536 00c6 DBB2 uxtb r3, r3 + 4537 00c8 1A46 mov r2, r3 + 4538 .loc 1 2753 24 + 4539 00ca FB68 ldr r3, [r7, #12] + 4540 00cc 1A65 str r2, [r3, #80] + 4541 .L209: +2754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2755:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send Slave Address and Memory Address */ +2756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_W + 4542 .loc 1 2756 5 + 4543 00ce FB88 ldrh r3, [r7, #6] @ movhi + 4544 00d0 DAB2 uxtb r2, r3 + 4545 00d2 7989 ldrh r1, [r7, #10] + 4546 00d4 0C4B ldr r3, .L210+8 + 4547 00d6 0093 str r3, [sp] + 4548 00d8 4FF08073 mov r3, #16777216 + 4549 00dc F868 ldr r0, [r7, #12] + 4550 00de FFF7FEFF bl I2C_TransferConfig +2757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2758:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +2759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 4551 .loc 1 2759 5 + 4552 00e2 FB68 ldr r3, [r7, #12] + 4553 00e4 0022 movs r2, #0 + 4554 00e6 83F84020 strb r2, [r3, #64] +2760:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2761:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +2762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +2763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** process unlock */ +2764:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, TXI interrupt */ +2766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* possible to enable all of these */ +2767:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | +2768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ +2769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + 4555 .loc 1 2769 5 + 4556 00ea 0121 movs r1, #1 + 4557 00ec F868 ldr r0, [r7, #12] + 4558 00ee FFF7FEFF bl I2C_Enable_IRQ +2770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; + 4559 .loc 1 2771 12 + 4560 00f2 0023 movs r3, #0 + 4561 00f4 00E0 b .L205 + 4562 .L202: +2772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +2774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; + 4563 .loc 1 2775 12 + 4564 00f6 0223 movs r3, #2 + 4565 .L205: +2776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2777:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 4566 .loc 1 2777 1 + ARM GAS /tmp/cc5G5cqz.s page 130 + + + 4567 00f8 1846 mov r0, r3 + 4568 00fa 1037 adds r7, r7, #16 + 4569 .cfi_def_cfa_offset 8 + 4570 00fc BD46 mov sp, r7 + 4571 .cfi_def_cfa_register 13 + 4572 @ sp needed + 4573 00fe 80BD pop {r7, pc} + 4574 .L211: + 4575 .align 2 + 4576 .L210: + 4577 0100 0000FFFF .word -65536 + 4578 0104 00000000 .word I2C_Mem_ISR_IT + 4579 0108 00200080 .word -2147475456 + 4580 .cfi_endproc + 4581 .LFE148: + 4583 .section .text.HAL_I2C_Mem_Read_IT,"ax",%progbits + 4584 .align 1 + 4585 .global HAL_I2C_Mem_Read_IT + 4586 .syntax unified + 4587 .thumb + 4588 .thumb_func + 4590 HAL_I2C_Mem_Read_IT: + 4591 .LFB149: +2778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +2780:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory addre +2781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2782:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +2783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +2784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +2785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param MemAddress Internal memory address +2786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param MemAddSize Size of internal memory address +2787:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer +2788:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be sent +2789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +2790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +2791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAdd +2792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +2793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4592 .loc 1 2793 1 + 4593 .cfi_startproc + 4594 @ args = 8, pretend = 0, frame = 16 + 4595 @ frame_needed = 1, uses_anonymous_args = 0 + 4596 0000 80B5 push {r7, lr} + 4597 .cfi_def_cfa_offset 8 + 4598 .cfi_offset 7, -8 + 4599 .cfi_offset 14, -4 + 4600 0002 86B0 sub sp, sp, #24 + 4601 .cfi_def_cfa_offset 32 + 4602 0004 02AF add r7, sp, #8 + 4603 .cfi_def_cfa 7, 24 + 4604 0006 F860 str r0, [r7, #12] + 4605 0008 0846 mov r0, r1 + 4606 000a 1146 mov r1, r2 + 4607 000c 1A46 mov r2, r3 + 4608 000e 0346 mov r3, r0 @ movhi + 4609 0010 7B81 strh r3, [r7, #10] @ movhi + ARM GAS /tmp/cc5G5cqz.s page 131 + + + 4610 0012 0B46 mov r3, r1 @ movhi + 4611 0014 3B81 strh r3, [r7, #8] @ movhi + 4612 0016 1346 mov r3, r2 @ movhi + 4613 0018 FB80 strh r3, [r7, #6] @ movhi +2794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check the parameters */ +2795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); +2796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 4614 .loc 1 2797 11 + 4615 001a FB68 ldr r3, [r7, #12] + 4616 001c 93F84130 ldrb r3, [r3, #65] + 4617 0020 DBB2 uxtb r3, r3 + 4618 .loc 1 2797 6 + 4619 0022 202B cmp r3, #32 + 4620 0024 66D1 bne .L213 +2798:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2799:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) + 4621 .loc 1 2799 8 + 4622 0026 BB69 ldr r3, [r7, #24] + 4623 0028 002B cmp r3, #0 + 4624 002a 02D0 beq .L214 + 4625 .loc 1 2799 25 discriminator 1 + 4626 002c BB8B ldrh r3, [r7, #28] + 4627 002e 002B cmp r3, #0 + 4628 0030 05D1 bne .L215 + 4629 .L214: +2800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + 4630 .loc 1 2801 23 + 4631 0032 FB68 ldr r3, [r7, #12] + 4632 0034 4FF40072 mov r2, #512 + 4633 0038 5A64 str r2, [r3, #68] +2802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 4634 .loc 1 2802 15 + 4635 003a 0123 movs r3, #1 + 4636 003c 5BE0 b .L216 + 4637 .L215: +2803:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2804:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + 4638 .loc 1 2805 9 + 4639 003e FB68 ldr r3, [r7, #12] + 4640 0040 1B68 ldr r3, [r3] + 4641 0042 9B69 ldr r3, [r3, #24] + 4642 0044 03F40043 and r3, r3, #32768 + 4643 .loc 1 2805 8 + 4644 0048 B3F5004F cmp r3, #32768 + 4645 004c 01D1 bne .L217 +2806:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2807:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; + 4646 .loc 1 2807 14 + 4647 004e 0223 movs r3, #2 + 4648 0050 51E0 b .L216 + 4649 .L217: +2808:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ + ARM GAS /tmp/cc5G5cqz.s page 132 + + +2811:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); + 4650 .loc 1 2811 5 + 4651 0052 FB68 ldr r3, [r7, #12] + 4652 0054 93F84030 ldrb r3, [r3, #64] @ zero_extendqisi2 + 4653 0058 012B cmp r3, #1 + 4654 005a 01D1 bne .L218 + 4655 .loc 1 2811 5 is_stmt 0 discriminator 1 + 4656 005c 0223 movs r3, #2 + 4657 .loc 1 2811 5 + 4658 005e 4AE0 b .L216 + 4659 .L218: + 4660 .loc 1 2811 5 discriminator 2 + 4661 0060 FB68 ldr r3, [r7, #12] + 4662 0062 0122 movs r2, #1 + 4663 0064 83F84020 strb r2, [r3, #64] +2812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; + 4664 .loc 1 2813 23 is_stmt 1 + 4665 0068 FB68 ldr r3, [r7, #12] + 4666 006a 2222 movs r2, #34 + 4667 006c 83F84120 strb r2, [r3, #65] +2814:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 4668 .loc 1 2814 23 + 4669 0070 FB68 ldr r3, [r7, #12] + 4670 0072 4022 movs r2, #64 + 4671 0074 83F84220 strb r2, [r3, #66] +2815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 4672 .loc 1 2815 23 + 4673 0078 FB68 ldr r3, [r7, #12] + 4674 007a 0022 movs r2, #0 + 4675 007c 5A64 str r2, [r3, #68] +2816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2817:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ +2818:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; + 4676 .loc 1 2818 23 + 4677 007e FB68 ldr r3, [r7, #12] + 4678 0080 BA69 ldr r2, [r7, #24] + 4679 0082 5A62 str r2, [r3, #36] +2819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 4680 .loc 1 2819 23 + 4681 0084 FB68 ldr r3, [r7, #12] + 4682 0086 BA8B ldrh r2, [r7, #28] @ movhi + 4683 0088 5A85 strh r2, [r3, #42] @ movhi +2820:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 4684 .loc 1 2820 23 + 4685 008a FB68 ldr r3, [r7, #12] + 4686 008c 1C4A ldr r2, .L221 + 4687 008e DA62 str r2, [r3, #44] +2821:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Mem_ISR_IT; + 4688 .loc 1 2821 23 + 4689 0090 FB68 ldr r3, [r7, #12] + 4690 0092 1C4A ldr r2, .L221+4 + 4691 0094 5A63 str r2, [r3, #52] +2822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Devaddress = DevAddress; + 4692 .loc 1 2822 23 + 4693 0096 7A89 ldrh r2, [r7, #10] + 4694 0098 FB68 ldr r3, [r7, #12] + ARM GAS /tmp/cc5G5cqz.s page 133 + + + 4695 009a DA64 str r2, [r3, #76] +2823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* If Memory address size is 8Bit */ +2825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + 4696 .loc 1 2825 8 + 4697 009c FB88 ldrh r3, [r7, #6] + 4698 009e 012B cmp r3, #1 + 4699 00a0 09D1 bne .L219 +2826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2827:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prefetch Memory Address */ +2828:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + 4700 .loc 1 2828 30 + 4701 00a2 3B89 ldrh r3, [r7, #8] @ movhi + 4702 00a4 DAB2 uxtb r2, r3 + 4703 .loc 1 2828 11 + 4704 00a6 FB68 ldr r3, [r7, #12] + 4705 00a8 1B68 ldr r3, [r3] + 4706 .loc 1 2828 28 + 4707 00aa 9A62 str r2, [r3, #40] +2829:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2830:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Reset Memaddress content */ +2831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Memaddress = 0xFFFFFFFFU; + 4708 .loc 1 2831 24 + 4709 00ac FB68 ldr r3, [r7, #12] + 4710 00ae 4FF0FF32 mov r2, #-1 + 4711 00b2 1A65 str r2, [r3, #80] + 4712 00b4 0BE0 b .L220 + 4713 .L219: +2832:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* If Memory address size is 16Bit */ +2834:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +2835:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2836:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ +2837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + 4714 .loc 1 2837 30 + 4715 00b6 3B89 ldrh r3, [r7, #8] + 4716 00b8 1B0A lsrs r3, r3, #8 + 4717 00ba 9BB2 uxth r3, r3 + 4718 00bc DAB2 uxtb r2, r3 + 4719 .loc 1 2837 11 + 4720 00be FB68 ldr r3, [r7, #12] + 4721 00c0 1B68 ldr r3, [r3] + 4722 .loc 1 2837 28 + 4723 00c2 9A62 str r2, [r3, #40] +2838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare Memaddress buffer for LSB part */ +2840:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); + 4724 .loc 1 2840 26 + 4725 00c4 3B89 ldrh r3, [r7, #8] @ movhi + 4726 00c6 DBB2 uxtb r3, r3 + 4727 00c8 1A46 mov r2, r3 + 4728 .loc 1 2840 24 + 4729 00ca FB68 ldr r3, [r7, #12] + 4730 00cc 1A65 str r2, [r3, #80] + 4731 .L220: +2841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2842:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send Slave Address and Memory Address */ + ARM GAS /tmp/cc5G5cqz.s page 134 + + +2843:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_ + 4732 .loc 1 2843 5 + 4733 00ce FB88 ldrh r3, [r7, #6] @ movhi + 4734 00d0 DAB2 uxtb r2, r3 + 4735 00d2 7989 ldrh r1, [r7, #10] + 4736 00d4 0C4B ldr r3, .L221+8 + 4737 00d6 0093 str r3, [sp] + 4738 00d8 0023 movs r3, #0 + 4739 00da F868 ldr r0, [r7, #12] + 4740 00dc FFF7FEFF bl I2C_TransferConfig +2844:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +2846:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 4741 .loc 1 2846 5 + 4742 00e0 FB68 ldr r3, [r7, #12] + 4743 00e2 0022 movs r2, #0 + 4744 00e4 83F84020 strb r2, [r3, #64] +2847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +2849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +2850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** process unlock */ +2851:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2852:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, RXI interrupt */ +2853:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* possible to enable all of these */ +2854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | +2855:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ +2856:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, (I2C_XFER_TX_IT | I2C_XFER_RX_IT)); + 4745 .loc 1 2856 5 + 4746 00e8 0321 movs r1, #3 + 4747 00ea F868 ldr r0, [r7, #12] + 4748 00ec FFF7FEFF bl I2C_Enable_IRQ +2857:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; + 4749 .loc 1 2858 12 + 4750 00f0 0023 movs r3, #0 + 4751 00f2 00E0 b .L216 + 4752 .L213: +2859:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +2861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; + 4753 .loc 1 2862 12 + 4754 00f4 0223 movs r3, #2 + 4755 .L216: +2863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2864:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 4756 .loc 1 2864 1 + 4757 00f6 1846 mov r0, r3 + 4758 00f8 1037 adds r7, r7, #16 + 4759 .cfi_def_cfa_offset 8 + 4760 00fa BD46 mov sp, r7 + 4761 .cfi_def_cfa_register 13 + 4762 @ sp needed + 4763 00fc 80BD pop {r7, pc} + 4764 .L222: + 4765 00fe 00BF .align 2 + 4766 .L221: + ARM GAS /tmp/cc5G5cqz.s page 135 + + + 4767 0100 0000FFFF .word -65536 + 4768 0104 00000000 .word I2C_Mem_ISR_IT + 4769 0108 00200080 .word -2147475456 + 4770 .cfi_endproc + 4771 .LFE149: + 4773 .section .text.HAL_I2C_Mem_Write_DMA,"ax",%progbits + 4774 .align 1 + 4775 .global HAL_I2C_Mem_Write_DMA + 4776 .syntax unified + 4777 .thumb + 4778 .thumb_func + 4780 HAL_I2C_Mem_Write_DMA: + 4781 .LFB150: +2865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +2867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address +2868:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +2869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +2870:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +2871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +2872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param MemAddress Internal memory address +2873:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param MemAddSize Size of internal memory address +2874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer +2875:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be sent +2876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +2877:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +2878:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemA +2879:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +2880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 4782 .loc 1 2880 1 + 4783 .cfi_startproc + 4784 @ args = 8, pretend = 0, frame = 24 + 4785 @ frame_needed = 1, uses_anonymous_args = 0 + 4786 0000 80B5 push {r7, lr} + 4787 .cfi_def_cfa_offset 8 + 4788 .cfi_offset 7, -8 + 4789 .cfi_offset 14, -4 + 4790 0002 88B0 sub sp, sp, #32 + 4791 .cfi_def_cfa_offset 40 + 4792 0004 02AF add r7, sp, #8 + 4793 .cfi_def_cfa 7, 32 + 4794 0006 F860 str r0, [r7, #12] + 4795 0008 0846 mov r0, r1 + 4796 000a 1146 mov r1, r2 + 4797 000c 1A46 mov r2, r3 + 4798 000e 0346 mov r3, r0 @ movhi + 4799 0010 7B81 strh r3, [r7, #10] @ movhi + 4800 0012 0B46 mov r3, r1 @ movhi + 4801 0014 3B81 strh r3, [r7, #8] @ movhi + 4802 0016 1346 mov r3, r2 @ movhi + 4803 0018 FB80 strh r3, [r7, #6] @ movhi +2881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; +2882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check the parameters */ +2884:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); +2885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + ARM GAS /tmp/cc5G5cqz.s page 136 + + + 4804 .loc 1 2886 11 + 4805 001a FB68 ldr r3, [r7, #12] + 4806 001c 93F84130 ldrb r3, [r3, #65] + 4807 0020 DBB2 uxtb r3, r3 + 4808 .loc 1 2886 6 + 4809 0022 202B cmp r3, #32 + 4810 0024 40F0C380 bne .L224 +2887:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2888:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) + 4811 .loc 1 2888 8 + 4812 0028 3B6A ldr r3, [r7, #32] + 4813 002a 002B cmp r3, #0 + 4814 002c 02D0 beq .L225 + 4815 .loc 1 2888 25 discriminator 1 + 4816 002e BB8C ldrh r3, [r7, #36] + 4817 0030 002B cmp r3, #0 + 4818 0032 05D1 bne .L226 + 4819 .L225: +2889:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2890:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + 4820 .loc 1 2890 23 + 4821 0034 FB68 ldr r3, [r7, #12] + 4822 0036 4FF40072 mov r2, #512 + 4823 003a 5A64 str r2, [r3, #68] +2891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 4824 .loc 1 2891 15 + 4825 003c 0123 movs r3, #1 + 4826 003e B7E0 b .L227 + 4827 .L226: +2892:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2894:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + 4828 .loc 1 2894 9 + 4829 0040 FB68 ldr r3, [r7, #12] + 4830 0042 1B68 ldr r3, [r3] + 4831 0044 9B69 ldr r3, [r3, #24] + 4832 0046 03F40043 and r3, r3, #32768 + 4833 .loc 1 2894 8 + 4834 004a B3F5004F cmp r3, #32768 + 4835 004e 01D1 bne .L228 +2895:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; + 4836 .loc 1 2896 14 + 4837 0050 0223 movs r3, #2 + 4838 0052 ADE0 b .L227 + 4839 .L228: +2897:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2899:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +2900:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); + 4840 .loc 1 2900 5 + 4841 0054 FB68 ldr r3, [r7, #12] + 4842 0056 93F84030 ldrb r3, [r3, #64] @ zero_extendqisi2 + 4843 005a 012B cmp r3, #1 + 4844 005c 01D1 bne .L229 + 4845 .loc 1 2900 5 is_stmt 0 discriminator 1 + 4846 005e 0223 movs r3, #2 + ARM GAS /tmp/cc5G5cqz.s page 137 + + + 4847 .loc 1 2900 5 + 4848 0060 A6E0 b .L227 + 4849 .L229: + 4850 .loc 1 2900 5 discriminator 2 + 4851 0062 FB68 ldr r3, [r7, #12] + 4852 0064 0122 movs r2, #1 + 4853 0066 83F84020 strb r2, [r3, #64] +2901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2902:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; + 4854 .loc 1 2902 23 is_stmt 1 + 4855 006a FB68 ldr r3, [r7, #12] + 4856 006c 2122 movs r2, #33 + 4857 006e 83F84120 strb r2, [r3, #65] +2903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 4858 .loc 1 2903 23 + 4859 0072 FB68 ldr r3, [r7, #12] + 4860 0074 4022 movs r2, #64 + 4861 0076 83F84220 strb r2, [r3, #66] +2904:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 4862 .loc 1 2904 23 + 4863 007a FB68 ldr r3, [r7, #12] + 4864 007c 0022 movs r2, #0 + 4865 007e 5A64 str r2, [r3, #68] +2905:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2906:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ +2907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; + 4866 .loc 1 2907 23 + 4867 0080 FB68 ldr r3, [r7, #12] + 4868 0082 3A6A ldr r2, [r7, #32] + 4869 0084 5A62 str r2, [r3, #36] +2908:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 4870 .loc 1 2908 23 + 4871 0086 FB68 ldr r3, [r7, #12] + 4872 0088 BA8C ldrh r2, [r7, #36] @ movhi + 4873 008a 5A85 strh r2, [r3, #42] @ movhi +2909:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 4874 .loc 1 2909 23 + 4875 008c FB68 ldr r3, [r7, #12] + 4876 008e 4A4A ldr r2, .L239 + 4877 0090 DA62 str r2, [r3, #44] +2910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Mem_ISR_DMA; + 4878 .loc 1 2910 23 + 4879 0092 FB68 ldr r3, [r7, #12] + 4880 0094 494A ldr r2, .L239+4 + 4881 0096 5A63 str r2, [r3, #52] +2911:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Devaddress = DevAddress; + 4882 .loc 1 2911 23 + 4883 0098 7A89 ldrh r2, [r7, #10] + 4884 009a FB68 ldr r3, [r7, #12] + 4885 009c DA64 str r2, [r3, #76] +2912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2913:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) + 4886 .loc 1 2913 13 + 4887 009e FB68 ldr r3, [r7, #12] + 4888 00a0 5B8D ldrh r3, [r3, #42] @ movhi + 4889 00a2 9BB2 uxth r3, r3 + 4890 .loc 1 2913 8 + ARM GAS /tmp/cc5G5cqz.s page 138 + + + 4891 00a4 FF2B cmp r3, #255 + 4892 00a6 03D9 bls .L230 +2914:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2915:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; + 4893 .loc 1 2915 22 + 4894 00a8 FB68 ldr r3, [r7, #12] + 4895 00aa FF22 movs r2, #255 + 4896 00ac 1A85 strh r2, [r3, #40] @ movhi + 4897 00ae 04E0 b .L231 + 4898 .L230: +2916:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2917:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +2918:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2919:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 4899 .loc 1 2919 28 + 4900 00b0 FB68 ldr r3, [r7, #12] + 4901 00b2 5B8D ldrh r3, [r3, #42] @ movhi + 4902 00b4 9AB2 uxth r2, r3 + 4903 .loc 1 2919 22 + 4904 00b6 FB68 ldr r3, [r7, #12] + 4905 00b8 1A85 strh r2, [r3, #40] @ movhi + 4906 .L231: +2920:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2922:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* If Memory address size is 8Bit */ +2923:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + 4907 .loc 1 2923 8 + 4908 00ba FB88 ldrh r3, [r7, #6] + 4909 00bc 012B cmp r3, #1 + 4910 00be 09D1 bne .L232 +2924:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2925:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prefetch Memory Address */ +2926:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + 4911 .loc 1 2926 30 + 4912 00c0 3B89 ldrh r3, [r7, #8] @ movhi + 4913 00c2 DAB2 uxtb r2, r3 + 4914 .loc 1 2926 11 + 4915 00c4 FB68 ldr r3, [r7, #12] + 4916 00c6 1B68 ldr r3, [r3] + 4917 .loc 1 2926 28 + 4918 00c8 9A62 str r2, [r3, #40] +2927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2928:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Reset Memaddress content */ +2929:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Memaddress = 0xFFFFFFFFU; + 4919 .loc 1 2929 24 + 4920 00ca FB68 ldr r3, [r7, #12] + 4921 00cc 4FF0FF32 mov r2, #-1 + 4922 00d0 1A65 str r2, [r3, #80] + 4923 00d2 0BE0 b .L233 + 4924 .L232: +2930:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2931:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* If Memory address size is 16Bit */ +2932:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +2933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2934:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ +2935:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + 4925 .loc 1 2935 30 + ARM GAS /tmp/cc5G5cqz.s page 139 + + + 4926 00d4 3B89 ldrh r3, [r7, #8] + 4927 00d6 1B0A lsrs r3, r3, #8 + 4928 00d8 9BB2 uxth r3, r3 + 4929 00da DAB2 uxtb r2, r3 + 4930 .loc 1 2935 11 + 4931 00dc FB68 ldr r3, [r7, #12] + 4932 00de 1B68 ldr r3, [r3] + 4933 .loc 1 2935 28 + 4934 00e0 9A62 str r2, [r3, #40] +2936:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare Memaddress buffer for LSB part */ +2938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); + 4935 .loc 1 2938 26 + 4936 00e2 3B89 ldrh r3, [r7, #8] @ movhi + 4937 00e4 DBB2 uxtb r3, r3 + 4938 00e6 1A46 mov r2, r3 + 4939 .loc 1 2938 24 + 4940 00e8 FB68 ldr r3, [r7, #12] + 4941 00ea 1A65 str r2, [r3, #80] + 4942 .L233: +2939:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2941:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) + 4943 .loc 1 2941 13 + 4944 00ec FB68 ldr r3, [r7, #12] + 4945 00ee 9B6B ldr r3, [r3, #56] + 4946 .loc 1 2941 8 + 4947 00f0 002B cmp r3, #0 + 4948 00f2 20D0 beq .L234 +2942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2943:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +2944:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + 4949 .loc 1 2944 11 + 4950 00f4 FB68 ldr r3, [r7, #12] + 4951 00f6 9B6B ldr r3, [r3, #56] + 4952 .loc 1 2944 38 + 4953 00f8 314A ldr r2, .L239+8 + 4954 00fa 9A62 str r2, [r3, #40] +2945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the DMA error callback */ +2947:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + 4955 .loc 1 2947 11 + 4956 00fc FB68 ldr r3, [r7, #12] + 4957 00fe 9B6B ldr r3, [r3, #56] + 4958 .loc 1 2947 39 + 4959 0100 304A ldr r2, .L239+12 + 4960 0102 1A63 str r2, [r3, #48] +2948:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +2950:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferHalfCpltCallback = NULL; + 4961 .loc 1 2950 11 + 4962 0104 FB68 ldr r3, [r7, #12] + 4963 0106 9B6B ldr r3, [r3, #56] + 4964 .loc 1 2950 42 + 4965 0108 0022 movs r2, #0 + 4966 010a DA62 str r2, [r3, #44] +2951:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + ARM GAS /tmp/cc5G5cqz.s page 140 + + + 4967 .loc 1 2951 11 + 4968 010c FB68 ldr r3, [r7, #12] + 4969 010e 9B6B ldr r3, [r3, #56] + 4970 .loc 1 2951 39 + 4971 0110 0022 movs r2, #0 + 4972 0112 5A63 str r2, [r3, #52] +2952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable the DMA channel */ +2954:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TX + 4973 .loc 1 2954 23 + 4974 0114 FB68 ldr r3, [r7, #12] + 4975 0116 986B ldr r0, [r3, #56] + 4976 0118 396A ldr r1, [r7, #32] + 4977 .loc 1 2954 86 + 4978 011a FB68 ldr r3, [r7, #12] + 4979 011c 1B68 ldr r3, [r3] + 4980 .loc 1 2954 81 + 4981 011e 2833 adds r3, r3, #40 + 4982 .loc 1 2954 23 + 4983 0120 1A46 mov r2, r3 +2955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); + 4984 .loc 1 2955 44 + 4985 0122 FB68 ldr r3, [r7, #12] + 4986 0124 1B8D ldrh r3, [r3, #40] +2954:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); + 4987 .loc 1 2954 23 + 4988 0126 FFF7FEFF bl HAL_DMA_Start_IT + 4989 012a 0346 mov r3, r0 + 4990 012c FB75 strb r3, [r7, #23] +2956:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2957:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +2958:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C state */ +2960:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +2961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +2962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2963:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C error code */ +2964:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; +2965:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2966:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +2967:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +2968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2969:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +2970:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +2971:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2972:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (dmaxferstatus == HAL_OK) + 4991 .loc 1 2972 8 + 4992 012e FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 4993 0130 002B cmp r3, #0 + 4994 0132 28D1 bne .L236 + 4995 0134 13E0 b .L238 + 4996 .L234: +2960:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 4997 .loc 1 2960 23 + 4998 0136 FB68 ldr r3, [r7, #12] + 4999 0138 2022 movs r2, #32 + 5000 013a 83F84120 strb r2, [r3, #65] + ARM GAS /tmp/cc5G5cqz.s page 141 + + +2961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5001 .loc 1 2961 23 + 5002 013e FB68 ldr r3, [r7, #12] + 5003 0140 0022 movs r2, #0 + 5004 0142 83F84220 strb r2, [r3, #66] +2964:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5005 .loc 1 2964 11 + 5006 0146 FB68 ldr r3, [r7, #12] + 5007 0148 5B6C ldr r3, [r3, #68] +2964:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5008 .loc 1 2964 23 + 5009 014a 43F08002 orr r2, r3, #128 + 5010 014e FB68 ldr r3, [r7, #12] + 5011 0150 5A64 str r2, [r3, #68] +2967:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5012 .loc 1 2967 7 + 5013 0152 FB68 ldr r3, [r7, #12] + 5014 0154 0022 movs r2, #0 + 5015 0156 83F84020 strb r2, [r3, #64] +2969:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5016 .loc 1 2969 14 + 5017 015a 0123 movs r3, #1 + 5018 015c 28E0 b .L227 + 5019 .L238: +2973:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2974:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send Slave Address and Memory Address */ +2975:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START + 5020 .loc 1 2975 7 + 5021 015e FB88 ldrh r3, [r7, #6] @ movhi + 5022 0160 DAB2 uxtb r2, r3 + 5023 0162 7989 ldrh r1, [r7, #10] + 5024 0164 184B ldr r3, .L239+16 + 5025 0166 0093 str r3, [sp] + 5026 0168 4FF08073 mov r3, #16777216 + 5027 016c F868 ldr r0, [r7, #12] + 5028 016e FFF7FEFF bl I2C_TransferConfig +2976:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2977:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +2978:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 5029 .loc 1 2978 7 + 5030 0172 FB68 ldr r3, [r7, #12] + 5031 0174 0022 movs r2, #0 + 5032 0176 83F84020 strb r2, [r3, #64] +2979:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +2981:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +2982:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** process unlock */ +2983:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, TXI interrupt */ +2984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* possible to enable all of these */ +2985:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | +2986:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ +2987:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + 5033 .loc 1 2987 7 + 5034 017a 0121 movs r1, #1 + 5035 017c F868 ldr r0, [r7, #12] + 5036 017e FFF7FEFF bl I2C_Enable_IRQ +2988:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/cc5G5cqz.s page 142 + + +2989:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +2990:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +2991:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C state */ +2992:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +2993:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +2994:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C error code */ +2996:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; +2997:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +2998:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +2999:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3000:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3001:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +3002:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3003:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; + 5037 .loc 1 3004 12 + 5038 0182 0023 movs r3, #0 + 5039 0184 14E0 b .L227 + 5040 .L236: +2992:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 5041 .loc 1 2992 23 + 5042 0186 FB68 ldr r3, [r7, #12] + 5043 0188 2022 movs r2, #32 + 5044 018a 83F84120 strb r2, [r3, #65] +2993:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5045 .loc 1 2993 23 + 5046 018e FB68 ldr r3, [r7, #12] + 5047 0190 0022 movs r2, #0 + 5048 0192 83F84220 strb r2, [r3, #66] +2996:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5049 .loc 1 2996 11 + 5050 0196 FB68 ldr r3, [r7, #12] + 5051 0198 5B6C ldr r3, [r3, #68] +2996:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5052 .loc 1 2996 23 + 5053 019a 43F01002 orr r2, r3, #16 + 5054 019e FB68 ldr r3, [r7, #12] + 5055 01a0 5A64 str r2, [r3, #68] +2999:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5056 .loc 1 2999 7 + 5057 01a2 FB68 ldr r3, [r7, #12] + 5058 01a4 0022 movs r2, #0 + 5059 01a6 83F84020 strb r2, [r3, #64] +3001:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5060 .loc 1 3001 14 + 5061 01aa 0123 movs r3, #1 + 5062 01ac 00E0 b .L227 + 5063 .L224: +3005:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3006:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3008:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; + 5064 .loc 1 3008 12 + 5065 01ae 0223 movs r3, #2 + 5066 .L227: +3009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/cc5G5cqz.s page 143 + + +3010:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5067 .loc 1 3010 1 + 5068 01b0 1846 mov r0, r3 + 5069 01b2 1837 adds r7, r7, #24 + 5070 .cfi_def_cfa_offset 8 + 5071 01b4 BD46 mov sp, r7 + 5072 .cfi_def_cfa_register 13 + 5073 @ sp needed + 5074 01b6 80BD pop {r7, pc} + 5075 .L240: + 5076 .align 2 + 5077 .L239: + 5078 01b8 0000FFFF .word -65536 + 5079 01bc 00000000 .word I2C_Mem_ISR_DMA + 5080 01c0 00000000 .word I2C_DMAMasterTransmitCplt + 5081 01c4 00000000 .word I2C_DMAError + 5082 01c8 00200080 .word -2147475456 + 5083 .cfi_endproc + 5084 .LFE150: + 5086 .section .text.HAL_I2C_Mem_Read_DMA,"ax",%progbits + 5087 .align 1 + 5088 .global HAL_I2C_Mem_Read_DMA + 5089 .syntax unified + 5090 .thumb + 5091 .thumb_func + 5093 HAL_I2C_Mem_Read_DMA: + 5094 .LFB151: +3011:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +3013:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. +3014:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3015:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +3016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +3017:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +3018:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param MemAddress Internal memory address +3019:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param MemAddSize Size of internal memory address +3020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer +3021:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be read +3022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +3023:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +3024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAd +3025:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +3026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5095 .loc 1 3026 1 + 5096 .cfi_startproc + 5097 @ args = 8, pretend = 0, frame = 24 + 5098 @ frame_needed = 1, uses_anonymous_args = 0 + 5099 0000 80B5 push {r7, lr} + 5100 .cfi_def_cfa_offset 8 + 5101 .cfi_offset 7, -8 + 5102 .cfi_offset 14, -4 + 5103 0002 88B0 sub sp, sp, #32 + 5104 .cfi_def_cfa_offset 40 + 5105 0004 02AF add r7, sp, #8 + 5106 .cfi_def_cfa 7, 32 + 5107 0006 F860 str r0, [r7, #12] + 5108 0008 0846 mov r0, r1 + ARM GAS /tmp/cc5G5cqz.s page 144 + + + 5109 000a 1146 mov r1, r2 + 5110 000c 1A46 mov r2, r3 + 5111 000e 0346 mov r3, r0 @ movhi + 5112 0010 7B81 strh r3, [r7, #10] @ movhi + 5113 0012 0B46 mov r3, r1 @ movhi + 5114 0014 3B81 strh r3, [r7, #8] @ movhi + 5115 0016 1346 mov r3, r2 @ movhi + 5116 0018 FB80 strh r3, [r7, #6] @ movhi +3027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; +3028:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check the parameters */ +3030:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); +3031:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3032:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 5117 .loc 1 3032 11 + 5118 001a FB68 ldr r3, [r7, #12] + 5119 001c 93F84130 ldrb r3, [r3, #65] + 5120 0020 DBB2 uxtb r3, r3 + 5121 .loc 1 3032 6 + 5122 0022 202B cmp r3, #32 + 5123 0024 40F0C280 bne .L242 +3033:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) + 5124 .loc 1 3034 8 + 5125 0028 3B6A ldr r3, [r7, #32] + 5126 002a 002B cmp r3, #0 + 5127 002c 02D0 beq .L243 + 5128 .loc 1 3034 25 discriminator 1 + 5129 002e BB8C ldrh r3, [r7, #36] + 5130 0030 002B cmp r3, #0 + 5131 0032 05D1 bne .L244 + 5132 .L243: +3035:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3036:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + 5133 .loc 1 3036 23 + 5134 0034 FB68 ldr r3, [r7, #12] + 5135 0036 4FF40072 mov r2, #512 + 5136 003a 5A64 str r2, [r3, #68] +3037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 5137 .loc 1 3037 15 + 5138 003c 0123 movs r3, #1 + 5139 003e B6E0 b .L245 + 5140 .L244: +3038:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3039:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3040:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + 5141 .loc 1 3040 9 + 5142 0040 FB68 ldr r3, [r7, #12] + 5143 0042 1B68 ldr r3, [r3] + 5144 0044 9B69 ldr r3, [r3, #24] + 5145 0046 03F40043 and r3, r3, #32768 + 5146 .loc 1 3040 8 + 5147 004a B3F5004F cmp r3, #32768 + 5148 004e 01D1 bne .L246 +3041:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; + 5149 .loc 1 3042 14 + ARM GAS /tmp/cc5G5cqz.s page 145 + + + 5150 0050 0223 movs r3, #2 + 5151 0052 ACE0 b .L245 + 5152 .L246: +3043:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3045:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +3046:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); + 5153 .loc 1 3046 5 + 5154 0054 FB68 ldr r3, [r7, #12] + 5155 0056 93F84030 ldrb r3, [r3, #64] @ zero_extendqisi2 + 5156 005a 012B cmp r3, #1 + 5157 005c 01D1 bne .L247 + 5158 .loc 1 3046 5 is_stmt 0 discriminator 1 + 5159 005e 0223 movs r3, #2 + 5160 .loc 1 3046 5 + 5161 0060 A5E0 b .L245 + 5162 .L247: + 5163 .loc 1 3046 5 discriminator 2 + 5164 0062 FB68 ldr r3, [r7, #12] + 5165 0064 0122 movs r2, #1 + 5166 0066 83F84020 strb r2, [r3, #64] +3047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; + 5167 .loc 1 3048 23 is_stmt 1 + 5168 006a FB68 ldr r3, [r7, #12] + 5169 006c 2222 movs r2, #34 + 5170 006e 83F84120 strb r2, [r3, #65] +3049:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MEM; + 5171 .loc 1 3049 23 + 5172 0072 FB68 ldr r3, [r7, #12] + 5173 0074 4022 movs r2, #64 + 5174 0076 83F84220 strb r2, [r3, #66] +3050:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 5175 .loc 1 3050 23 + 5176 007a FB68 ldr r3, [r7, #12] + 5177 007c 0022 movs r2, #0 + 5178 007e 5A64 str r2, [r3, #68] +3051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3052:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ +3053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; + 5179 .loc 1 3053 23 + 5180 0080 FB68 ldr r3, [r7, #12] + 5181 0082 3A6A ldr r2, [r7, #32] + 5182 0084 5A62 str r2, [r3, #36] +3054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 5183 .loc 1 3054 23 + 5184 0086 FB68 ldr r3, [r7, #12] + 5185 0088 BA8C ldrh r2, [r7, #36] @ movhi + 5186 008a 5A85 strh r2, [r3, #42] @ movhi +3055:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 5187 .loc 1 3055 23 + 5188 008c FB68 ldr r3, [r7, #12] + 5189 008e 4A4A ldr r2, .L257 + 5190 0090 DA62 str r2, [r3, #44] +3056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Mem_ISR_DMA; + 5191 .loc 1 3056 23 + 5192 0092 FB68 ldr r3, [r7, #12] + ARM GAS /tmp/cc5G5cqz.s page 146 + + + 5193 0094 494A ldr r2, .L257+4 + 5194 0096 5A63 str r2, [r3, #52] +3057:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Devaddress = DevAddress; + 5195 .loc 1 3057 23 + 5196 0098 7A89 ldrh r2, [r7, #10] + 5197 009a FB68 ldr r3, [r7, #12] + 5198 009c DA64 str r2, [r3, #76] +3058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) + 5199 .loc 1 3059 13 + 5200 009e FB68 ldr r3, [r7, #12] + 5201 00a0 5B8D ldrh r3, [r3, #42] @ movhi + 5202 00a2 9BB2 uxth r3, r3 + 5203 .loc 1 3059 8 + 5204 00a4 FF2B cmp r3, #255 + 5205 00a6 03D9 bls .L248 +3060:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; + 5206 .loc 1 3061 22 + 5207 00a8 FB68 ldr r3, [r7, #12] + 5208 00aa FF22 movs r2, #255 + 5209 00ac 1A85 strh r2, [r3, #40] @ movhi + 5210 00ae 04E0 b .L249 + 5211 .L248: +3062:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3063:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3064:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 5212 .loc 1 3065 28 + 5213 00b0 FB68 ldr r3, [r7, #12] + 5214 00b2 5B8D ldrh r3, [r3, #42] @ movhi + 5215 00b4 9AB2 uxth r2, r3 + 5216 .loc 1 3065 22 + 5217 00b6 FB68 ldr r3, [r7, #12] + 5218 00b8 1A85 strh r2, [r3, #40] @ movhi + 5219 .L249: +3066:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3067:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* If Memory address size is 8Bit */ +3069:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + 5220 .loc 1 3069 8 + 5221 00ba FB88 ldrh r3, [r7, #6] + 5222 00bc 012B cmp r3, #1 + 5223 00be 09D1 bne .L250 +3070:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prefetch Memory Address */ +3072:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + 5224 .loc 1 3072 30 + 5225 00c0 3B89 ldrh r3, [r7, #8] @ movhi + 5226 00c2 DAB2 uxtb r2, r3 + 5227 .loc 1 3072 11 + 5228 00c4 FB68 ldr r3, [r7, #12] + 5229 00c6 1B68 ldr r3, [r3] + 5230 .loc 1 3072 28 + 5231 00c8 9A62 str r2, [r3, #40] +3073:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3074:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Reset Memaddress content */ + ARM GAS /tmp/cc5G5cqz.s page 147 + + +3075:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Memaddress = 0xFFFFFFFFU; + 5232 .loc 1 3075 24 + 5233 00ca FB68 ldr r3, [r7, #12] + 5234 00cc 4FF0FF32 mov r2, #-1 + 5235 00d0 1A65 str r2, [r3, #80] + 5236 00d2 0BE0 b .L251 + 5237 .L250: +3076:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3077:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* If Memory address size is 16Bit */ +3078:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3079:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ +3081:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + 5238 .loc 1 3081 30 + 5239 00d4 3B89 ldrh r3, [r7, #8] + 5240 00d6 1B0A lsrs r3, r3, #8 + 5241 00d8 9BB2 uxth r3, r3 + 5242 00da DAB2 uxtb r2, r3 + 5243 .loc 1 3081 11 + 5244 00dc FB68 ldr r3, [r7, #12] + 5245 00de 1B68 ldr r3, [r3] + 5246 .loc 1 3081 28 + 5247 00e0 9A62 str r2, [r3, #40] +3082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare Memaddress buffer for LSB part */ +3084:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); + 5248 .loc 1 3084 26 + 5249 00e2 3B89 ldrh r3, [r7, #8] @ movhi + 5250 00e4 DBB2 uxtb r3, r3 + 5251 00e6 1A46 mov r2, r3 + 5252 .loc 1 3084 24 + 5253 00e8 FB68 ldr r3, [r7, #12] + 5254 00ea 1A65 str r2, [r3, #80] + 5255 .L251: +3085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3086:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3087:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) + 5256 .loc 1 3087 13 + 5257 00ec FB68 ldr r3, [r7, #12] + 5258 00ee DB6B ldr r3, [r3, #60] + 5259 .loc 1 3087 8 + 5260 00f0 002B cmp r3, #0 + 5261 00f2 20D0 beq .L252 +3088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3089:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +3090:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + 5262 .loc 1 3090 11 + 5263 00f4 FB68 ldr r3, [r7, #12] + 5264 00f6 DB6B ldr r3, [r3, #60] + 5265 .loc 1 3090 38 + 5266 00f8 314A ldr r2, .L257+8 + 5267 00fa 9A62 str r2, [r3, #40] +3091:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3092:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the DMA error callback */ +3093:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + 5268 .loc 1 3093 11 + 5269 00fc FB68 ldr r3, [r7, #12] + ARM GAS /tmp/cc5G5cqz.s page 148 + + + 5270 00fe DB6B ldr r3, [r3, #60] + 5271 .loc 1 3093 39 + 5272 0100 304A ldr r2, .L257+12 + 5273 0102 1A63 str r2, [r3, #48] +3094:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +3096:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferHalfCpltCallback = NULL; + 5274 .loc 1 3096 11 + 5275 0104 FB68 ldr r3, [r7, #12] + 5276 0106 DB6B ldr r3, [r3, #60] + 5277 .loc 1 3096 42 + 5278 0108 0022 movs r2, #0 + 5279 010a DA62 str r2, [r3, #44] +3097:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 5280 .loc 1 3097 11 + 5281 010c FB68 ldr r3, [r7, #12] + 5282 010e DB6B ldr r3, [r3, #60] + 5283 .loc 1 3097 39 + 5284 0110 0022 movs r2, #0 + 5285 0112 5A63 str r2, [r3, #52] +3098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3099:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable the DMA channel */ +3100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pDa + 5286 .loc 1 3100 23 + 5287 0114 FB68 ldr r3, [r7, #12] + 5288 0116 D86B ldr r0, [r3, #60] + 5289 .loc 1 3100 69 + 5290 0118 FB68 ldr r3, [r7, #12] + 5291 011a 1B68 ldr r3, [r3] + 5292 .loc 1 3100 64 + 5293 011c 2433 adds r3, r3, #36 + 5294 .loc 1 3100 23 + 5295 011e 1946 mov r1, r3 + 5296 0120 3A6A ldr r2, [r7, #32] +3101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); + 5297 .loc 1 3101 44 + 5298 0122 FB68 ldr r3, [r7, #12] + 5299 0124 1B8D ldrh r3, [r3, #40] +3100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); + 5300 .loc 1 3100 23 + 5301 0126 FFF7FEFF bl HAL_DMA_Start_IT + 5302 012a 0346 mov r3, r0 + 5303 012c FB75 strb r3, [r7, #23] +3102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C state */ +3106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +3107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +3108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C error code */ +3110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; +3111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +3113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + ARM GAS /tmp/cc5G5cqz.s page 149 + + +3116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (dmaxferstatus == HAL_OK) + 5304 .loc 1 3118 8 + 5305 012e FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 5306 0130 002B cmp r3, #0 + 5307 0132 27D1 bne .L254 + 5308 0134 13E0 b .L256 + 5309 .L252: +3106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 5310 .loc 1 3106 23 + 5311 0136 FB68 ldr r3, [r7, #12] + 5312 0138 2022 movs r2, #32 + 5313 013a 83F84120 strb r2, [r3, #65] +3107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5314 .loc 1 3107 23 + 5315 013e FB68 ldr r3, [r7, #12] + 5316 0140 0022 movs r2, #0 + 5317 0142 83F84220 strb r2, [r3, #66] +3110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5318 .loc 1 3110 11 + 5319 0146 FB68 ldr r3, [r7, #12] + 5320 0148 5B6C ldr r3, [r3, #68] +3110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5321 .loc 1 3110 23 + 5322 014a 43F08002 orr r2, r3, #128 + 5323 014e FB68 ldr r3, [r7, #12] + 5324 0150 5A64 str r2, [r3, #68] +3113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5325 .loc 1 3113 7 + 5326 0152 FB68 ldr r3, [r7, #12] + 5327 0154 0022 movs r2, #0 + 5328 0156 83F84020 strb r2, [r3, #64] +3115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5329 .loc 1 3115 14 + 5330 015a 0123 movs r3, #1 + 5331 015c 27E0 b .L245 + 5332 .L256: +3119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send Slave Address and Memory Address */ +3121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_STAR + 5333 .loc 1 3121 7 + 5334 015e FB88 ldrh r3, [r7, #6] @ movhi + 5335 0160 DAB2 uxtb r2, r3 + 5336 0162 7989 ldrh r1, [r7, #10] + 5337 0164 184B ldr r3, .L257+16 + 5338 0166 0093 str r3, [sp] + 5339 0168 0023 movs r3, #0 + 5340 016a F868 ldr r0, [r7, #12] + 5341 016c FFF7FEFF bl I2C_TransferConfig +3122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +3124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 5342 .loc 1 3124 7 + 5343 0170 FB68 ldr r3, [r7, #12] + 5344 0172 0022 movs r2, #0 + 5345 0174 83F84020 strb r2, [r3, #64] + ARM GAS /tmp/cc5G5cqz.s page 150 + + +3125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +3127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +3128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** process unlock */ +3129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, TXI interrupt */ +3130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* possible to enable all of these */ +3131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | +3132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ +3133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + 5346 .loc 1 3133 7 + 5347 0178 0121 movs r1, #1 + 5348 017a F868 ldr r0, [r7, #12] + 5349 017c FFF7FEFF bl I2C_Enable_IRQ +3134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C state */ +3138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +3139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +3140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C error code */ +3142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; +3143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +3145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +3148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; + 5350 .loc 1 3150 12 + 5351 0180 0023 movs r3, #0 + 5352 0182 14E0 b .L245 + 5353 .L254: +3138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 5354 .loc 1 3138 23 + 5355 0184 FB68 ldr r3, [r7, #12] + 5356 0186 2022 movs r2, #32 + 5357 0188 83F84120 strb r2, [r3, #65] +3139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5358 .loc 1 3139 23 + 5359 018c FB68 ldr r3, [r7, #12] + 5360 018e 0022 movs r2, #0 + 5361 0190 83F84220 strb r2, [r3, #66] +3142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5362 .loc 1 3142 11 + 5363 0194 FB68 ldr r3, [r7, #12] + 5364 0196 5B6C ldr r3, [r3, #68] +3142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5365 .loc 1 3142 23 + 5366 0198 43F01002 orr r2, r3, #16 + 5367 019c FB68 ldr r3, [r7, #12] + 5368 019e 5A64 str r2, [r3, #68] +3145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 5369 .loc 1 3145 7 + 5370 01a0 FB68 ldr r3, [r7, #12] + 5371 01a2 0022 movs r2, #0 + ARM GAS /tmp/cc5G5cqz.s page 151 + + + 5372 01a4 83F84020 strb r2, [r3, #64] +3147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5373 .loc 1 3147 14 + 5374 01a8 0123 movs r3, #1 + 5375 01aa 00E0 b .L245 + 5376 .L242: +3151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; + 5377 .loc 1 3154 12 + 5378 01ac 0223 movs r3, #2 + 5379 .L245: +3155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5380 .loc 1 3156 1 + 5381 01ae 1846 mov r0, r3 + 5382 01b0 1837 adds r7, r7, #24 + 5383 .cfi_def_cfa_offset 8 + 5384 01b2 BD46 mov sp, r7 + 5385 .cfi_def_cfa_register 13 + 5386 @ sp needed + 5387 01b4 80BD pop {r7, pc} + 5388 .L258: + 5389 01b6 00BF .align 2 + 5390 .L257: + 5391 01b8 0000FFFF .word -65536 + 5392 01bc 00000000 .word I2C_Mem_ISR_DMA + 5393 01c0 00000000 .word I2C_DMAMasterReceiveCplt + 5394 01c4 00000000 .word I2C_DMAError + 5395 01c8 00200080 .word -2147475456 + 5396 .cfi_endproc + 5397 .LFE151: + 5399 .section .text.HAL_I2C_IsDeviceReady,"ax",%progbits + 5400 .align 1 + 5401 .global HAL_I2C_IsDeviceReady + 5402 .syntax unified + 5403 .thumb + 5404 .thumb_func + 5406 HAL_I2C_IsDeviceReady: + 5407 .LFB152: +3157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +3159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Checks if target device is ready for communication. +3160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @note This function is used with Memory devices +3161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +3163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +3164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +3165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Trials Number of trials +3166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Timeout Timeout duration +3167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +3168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +3169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Tria +3170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t Timeout) +3171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5408 .loc 1 3171 1 + ARM GAS /tmp/cc5G5cqz.s page 152 + + + 5409 .cfi_startproc + 5410 @ args = 0, pretend = 0, frame = 32 + 5411 @ frame_needed = 1, uses_anonymous_args = 0 + 5412 0000 80B5 push {r7, lr} + 5413 .cfi_def_cfa_offset 8 + 5414 .cfi_offset 7, -8 + 5415 .cfi_offset 14, -4 + 5416 0002 8AB0 sub sp, sp, #40 + 5417 .cfi_def_cfa_offset 48 + 5418 0004 02AF add r7, sp, #8 + 5419 .cfi_def_cfa 7, 40 + 5420 0006 F860 str r0, [r7, #12] + 5421 0008 7A60 str r2, [r7, #4] + 5422 000a 3B60 str r3, [r7] + 5423 000c 0B46 mov r3, r1 @ movhi + 5424 000e 7B81 strh r3, [r7, #10] @ movhi +3172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tickstart; +3173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __IO uint32_t I2C_Trials = 0UL; + 5425 .loc 1 3174 17 + 5426 0010 0023 movs r3, #0 + 5427 0012 7B61 str r3, [r7, #20] +3175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** FlagStatus tmp1; +3177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** FlagStatus tmp2; +3178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 5428 .loc 1 3179 11 + 5429 0014 FB68 ldr r3, [r7, #12] + 5430 0016 93F84130 ldrb r3, [r3, #65] + 5431 001a DBB2 uxtb r3, r3 + 5432 .loc 1 3179 6 + 5433 001c 202B cmp r3, #32 + 5434 001e 40F0F380 bne .L260 +3180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + 5435 .loc 1 3181 9 + 5436 0022 FB68 ldr r3, [r7, #12] + 5437 0024 1B68 ldr r3, [r3] + 5438 0026 9B69 ldr r3, [r3, #24] + 5439 0028 03F40043 and r3, r3, #32768 + 5440 .loc 1 3181 8 + 5441 002c B3F5004F cmp r3, #32768 + 5442 0030 01D1 bne .L261 +3182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; + 5443 .loc 1 3183 14 + 5444 0032 0223 movs r3, #2 + 5445 0034 E9E0 b .L262 + 5446 .L261: +3184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +3187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); + 5447 .loc 1 3187 5 + 5448 0036 FB68 ldr r3, [r7, #12] + 5449 0038 93F84030 ldrb r3, [r3, #64] @ zero_extendqisi2 + ARM GAS /tmp/cc5G5cqz.s page 153 + + + 5450 003c 012B cmp r3, #1 + 5451 003e 01D1 bne .L263 + 5452 .loc 1 3187 5 is_stmt 0 discriminator 1 + 5453 0040 0223 movs r3, #2 + 5454 .loc 1 3187 5 + 5455 0042 E2E0 b .L262 + 5456 .L263: + 5457 .loc 1 3187 5 discriminator 2 + 5458 0044 FB68 ldr r3, [r7, #12] + 5459 0046 0122 movs r2, #1 + 5460 0048 83F84020 strb r2, [r3, #64] +3188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY; + 5461 .loc 1 3189 17 is_stmt 1 + 5462 004c FB68 ldr r3, [r7, #12] + 5463 004e 2422 movs r2, #36 + 5464 0050 83F84120 strb r2, [r3, #65] +3190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 5465 .loc 1 3190 21 + 5466 0054 FB68 ldr r3, [r7, #12] + 5467 0056 0022 movs r2, #0 + 5468 0058 5A64 str r2, [r3, #68] + 5469 .L276: +3191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** do +3193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Generate Start */ +3195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress); + 5470 .loc 1 3195 29 + 5471 005a FB68 ldr r3, [r7, #12] + 5472 005c DB68 ldr r3, [r3, #12] + 5473 005e 012B cmp r3, #1 + 5474 0060 07D1 bne .L264 + 5475 .loc 1 3195 29 is_stmt 0 discriminator 1 + 5476 0062 7B89 ldrh r3, [r7, #10] + 5477 0064 C3F30903 ubfx r3, r3, #0, #10 + 5478 0068 43F00073 orr r3, r3, #33554432 + 5479 006c 43F40053 orr r3, r3, #8192 + 5480 0070 06E0 b .L265 + 5481 .L264: + 5482 .loc 1 3195 29 discriminator 2 + 5483 0072 7B89 ldrh r3, [r7, #10] + 5484 0074 C3F30903 ubfx r3, r3, #0, #10 + 5485 0078 43F00073 orr r3, r3, #33554432 + 5486 007c 43F42053 orr r3, r3, #10240 + 5487 .L265: + 5488 .loc 1 3195 11 is_stmt 1 discriminator 4 + 5489 0080 FA68 ldr r2, [r7, #12] + 5490 0082 1268 ldr r2, [r2] + 5491 .loc 1 3195 27 discriminator 4 + 5492 0084 5360 str r3, [r2, #4] +3196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ +3198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until STOPF flag is set or a NACK flag is set*/ +3199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tickstart = HAL_GetTick(); + 5493 .loc 1 3199 19 + 5494 0086 FFF7FEFF bl HAL_GetTick + ARM GAS /tmp/cc5G5cqz.s page 154 + + + 5495 008a B861 str r0, [r7, #24] +3200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF); + 5496 .loc 1 3201 14 + 5497 008c FB68 ldr r3, [r7, #12] + 5498 008e 1B68 ldr r3, [r3] + 5499 0090 9B69 ldr r3, [r3, #24] + 5500 0092 03F02003 and r3, r3, #32 + 5501 0096 202B cmp r3, #32 + 5502 0098 0CBF ite eq + 5503 009a 0123 moveq r3, #1 + 5504 009c 0023 movne r3, #0 + 5505 009e DBB2 uxtb r3, r3 + 5506 .loc 1 3201 12 + 5507 00a0 FB77 strb r3, [r7, #31] +3202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + 5508 .loc 1 3202 14 + 5509 00a2 FB68 ldr r3, [r7, #12] + 5510 00a4 1B68 ldr r3, [r3] + 5511 00a6 9B69 ldr r3, [r3, #24] + 5512 00a8 03F01003 and r3, r3, #16 + 5513 00ac 102B cmp r3, #16 + 5514 00ae 0CBF ite eq + 5515 00b0 0123 moveq r3, #1 + 5516 00b2 0023 movne r3, #0 + 5517 00b4 DBB2 uxtb r3, r3 + 5518 .loc 1 3202 12 + 5519 00b6 BB77 strb r3, [r7, #30] +3203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** while ((tmp1 == RESET) && (tmp2 == RESET)) + 5520 .loc 1 3204 13 + 5521 00b8 34E0 b .L266 + 5522 .L270: +3205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (Timeout != HAL_MAX_DELAY) + 5523 .loc 1 3206 12 + 5524 00ba 3B68 ldr r3, [r7] + 5525 00bc B3F1FF3F cmp r3, #-1 + 5526 00c0 1AD0 beq .L267 +3207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + 5527 .loc 1 3208 17 + 5528 00c2 FFF7FEFF bl HAL_GetTick + 5529 00c6 0246 mov r2, r0 + 5530 .loc 1 3208 31 discriminator 1 + 5531 00c8 BB69 ldr r3, [r7, #24] + 5532 00ca D31A subs r3, r2, r3 + 5533 .loc 1 3208 14 discriminator 1 + 5534 00cc 3A68 ldr r2, [r7] + 5535 00ce 9A42 cmp r2, r3 + 5536 00d0 02D3 bcc .L268 + 5537 .loc 1 3208 55 discriminator 1 + 5538 00d2 3B68 ldr r3, [r7] + 5539 00d4 002B cmp r3, #0 + 5540 00d6 0FD1 bne .L267 + 5541 .L268: +3209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + ARM GAS /tmp/cc5G5cqz.s page 155 + + +3210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C state */ +3211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 5542 .loc 1 3211 25 + 5543 00d8 FB68 ldr r3, [r7, #12] + 5544 00da 2022 movs r2, #32 + 5545 00dc 83F84120 strb r2, [r3, #65] +3212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C error code */ +3214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + 5546 .loc 1 3214 17 + 5547 00e0 FB68 ldr r3, [r7, #12] + 5548 00e2 5B6C ldr r3, [r3, #68] + 5549 .loc 1 3214 29 + 5550 00e4 43F02002 orr r2, r3, #32 + 5551 00e8 FB68 ldr r3, [r7, #12] + 5552 00ea 5A64 str r2, [r3, #68] +3215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +3217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 5553 .loc 1 3217 13 + 5554 00ec FB68 ldr r3, [r7, #12] + 5555 00ee 0022 movs r2, #0 + 5556 00f0 83F84020 strb r2, [r3, #64] +3218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 5557 .loc 1 3219 20 + 5558 00f4 0123 movs r3, #1 + 5559 00f6 88E0 b .L262 + 5560 .L267: +3220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF); + 5561 .loc 1 3223 16 + 5562 00f8 FB68 ldr r3, [r7, #12] + 5563 00fa 1B68 ldr r3, [r3] + 5564 00fc 9B69 ldr r3, [r3, #24] + 5565 00fe 03F02003 and r3, r3, #32 + 5566 0102 202B cmp r3, #32 + 5567 0104 0CBF ite eq + 5568 0106 0123 moveq r3, #1 + 5569 0108 0023 movne r3, #0 + 5570 010a DBB2 uxtb r3, r3 + 5571 .loc 1 3223 14 + 5572 010c FB77 strb r3, [r7, #31] +3224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + 5573 .loc 1 3224 16 + 5574 010e FB68 ldr r3, [r7, #12] + 5575 0110 1B68 ldr r3, [r3] + 5576 0112 9B69 ldr r3, [r3, #24] + 5577 0114 03F01003 and r3, r3, #16 + 5578 0118 102B cmp r3, #16 + 5579 011a 0CBF ite eq + 5580 011c 0123 moveq r3, #1 + 5581 011e 0023 movne r3, #0 + 5582 0120 DBB2 uxtb r3, r3 + 5583 .loc 1 3224 14 + ARM GAS /tmp/cc5G5cqz.s page 156 + + + 5584 0122 BB77 strb r3, [r7, #30] + 5585 .L266: +3204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5586 .loc 1 3204 30 + 5587 0124 FB7F ldrb r3, [r7, #31] @ zero_extendqisi2 + 5588 0126 002B cmp r3, #0 + 5589 0128 02D1 bne .L269 +3204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5590 .loc 1 3204 30 is_stmt 0 discriminator 1 + 5591 012a BB7F ldrb r3, [r7, #30] @ zero_extendqisi2 + 5592 012c 002B cmp r3, #0 + 5593 012e C4D0 beq .L270 + 5594 .L269: +3225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check if the NACKF flag has not been set */ +3228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) + 5595 .loc 1 3228 11 is_stmt 1 + 5596 0130 FB68 ldr r3, [r7, #12] + 5597 0132 1B68 ldr r3, [r3] + 5598 0134 9B69 ldr r3, [r3, #24] + 5599 0136 03F01003 and r3, r3, #16 + 5600 .loc 1 3228 10 + 5601 013a 102B cmp r3, #16 + 5602 013c 1AD0 beq .L271 +3229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until STOPF flag is reset */ +3231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + 5603 .loc 1 3231 13 + 5604 013e BB69 ldr r3, [r7, #24] + 5605 0140 0093 str r3, [sp] + 5606 0142 3B68 ldr r3, [r7] + 5607 0144 0022 movs r2, #0 + 5608 0146 2021 movs r1, #32 + 5609 0148 F868 ldr r0, [r7, #12] + 5610 014a FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 5611 014e 0346 mov r3, r0 + 5612 .loc 1 3231 12 discriminator 1 + 5613 0150 002B cmp r3, #0 + 5614 0152 01D0 beq .L272 +3232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 5615 .loc 1 3233 18 + 5616 0154 0123 movs r3, #1 + 5617 0156 58E0 b .L262 + 5618 .L272: +3234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear STOP Flag */ +3237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + 5619 .loc 1 3237 9 + 5620 0158 FB68 ldr r3, [r7, #12] + 5621 015a 1B68 ldr r3, [r3] + 5622 015c 2022 movs r2, #32 + 5623 015e DA61 str r2, [r3, #28] +3238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Device is ready */ + ARM GAS /tmp/cc5G5cqz.s page 157 + + +3240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 5624 .loc 1 3240 21 + 5625 0160 FB68 ldr r3, [r7, #12] + 5626 0162 2022 movs r2, #32 + 5627 0164 83F84120 strb r2, [r3, #65] +3241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +3243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 5628 .loc 1 3243 9 + 5629 0168 FB68 ldr r3, [r7, #12] + 5630 016a 0022 movs r2, #0 + 5631 016c 83F84020 strb r2, [r3, #64] +3244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; + 5632 .loc 1 3245 16 + 5633 0170 0023 movs r3, #0 + 5634 0172 4AE0 b .L262 + 5635 .L271: +3246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until STOPF flag is reset */ +3250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + 5636 .loc 1 3250 13 + 5637 0174 BB69 ldr r3, [r7, #24] + 5638 0176 0093 str r3, [sp] + 5639 0178 3B68 ldr r3, [r7] + 5640 017a 0022 movs r2, #0 + 5641 017c 2021 movs r1, #32 + 5642 017e F868 ldr r0, [r7, #12] + 5643 0180 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 5644 0184 0346 mov r3, r0 + 5645 .loc 1 3250 12 discriminator 1 + 5646 0186 002B cmp r3, #0 + 5647 0188 01D0 beq .L273 +3251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 5648 .loc 1 3252 18 + 5649 018a 0123 movs r3, #1 + 5650 018c 3DE0 b .L262 + 5651 .L273: +3253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear NACK Flag */ +3256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + 5652 .loc 1 3256 9 + 5653 018e FB68 ldr r3, [r7, #12] + 5654 0190 1B68 ldr r3, [r3] + 5655 0192 1022 movs r2, #16 + 5656 0194 DA61 str r2, [r3, #28] +3257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear STOP Flag, auto generated with autoend*/ +3259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + 5657 .loc 1 3259 9 + 5658 0196 FB68 ldr r3, [r7, #12] + 5659 0198 1B68 ldr r3, [r3] + 5660 019a 2022 movs r2, #32 + ARM GAS /tmp/cc5G5cqz.s page 158 + + + 5661 019c DA61 str r2, [r3, #28] +3260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check if the maximum allowed number of trials has been reached */ +3263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_Trials == Trials) + 5662 .loc 1 3263 22 + 5663 019e 7B69 ldr r3, [r7, #20] + 5664 .loc 1 3263 10 + 5665 01a0 7A68 ldr r2, [r7, #4] + 5666 01a2 9A42 cmp r2, r3 + 5667 01a4 18D1 bne .L274 +3264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Generate Stop */ +3266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_STOP; + 5668 .loc 1 3266 13 + 5669 01a6 FB68 ldr r3, [r7, #12] + 5670 01a8 1B68 ldr r3, [r3] + 5671 .loc 1 3266 23 + 5672 01aa 5A68 ldr r2, [r3, #4] + 5673 .loc 1 3266 13 + 5674 01ac FB68 ldr r3, [r7, #12] + 5675 01ae 1B68 ldr r3, [r3] + 5676 .loc 1 3266 29 + 5677 01b0 42F48042 orr r2, r2, #16384 + 5678 01b4 5A60 str r2, [r3, #4] +3267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until STOPF flag is reset */ +3269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + 5679 .loc 1 3269 13 + 5680 01b6 BB69 ldr r3, [r7, #24] + 5681 01b8 0093 str r3, [sp] + 5682 01ba 3B68 ldr r3, [r7] + 5683 01bc 0022 movs r2, #0 + 5684 01be 2021 movs r1, #32 + 5685 01c0 F868 ldr r0, [r7, #12] + 5686 01c2 FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 5687 01c6 0346 mov r3, r0 + 5688 .loc 1 3269 12 discriminator 1 + 5689 01c8 002B cmp r3, #0 + 5690 01ca 01D0 beq .L275 +3270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 5691 .loc 1 3271 18 + 5692 01cc 0123 movs r3, #1 + 5693 01ce 1CE0 b .L262 + 5694 .L275: +3272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear STOP Flag */ +3275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + 5695 .loc 1 3275 9 + 5696 01d0 FB68 ldr r3, [r7, #12] + 5697 01d2 1B68 ldr r3, [r3] + 5698 01d4 2022 movs r2, #32 + 5699 01d6 DA61 str r2, [r3, #28] + 5700 .L274: +3276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/cc5G5cqz.s page 159 + + +3277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Increment Trials */ +3279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Trials++; + 5701 .loc 1 3279 17 + 5702 01d8 7B69 ldr r3, [r7, #20] + 5703 01da 0133 adds r3, r3, #1 + 5704 01dc 7B61 str r3, [r7, #20] +3280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } while (I2C_Trials < Trials); + 5705 .loc 1 3280 25 + 5706 01de 7B69 ldr r3, [r7, #20] + 5707 01e0 7A68 ldr r2, [r7, #4] + 5708 01e2 9A42 cmp r2, r3 + 5709 01e4 3FF639AF bhi .L276 +3281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C state */ +3283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 5710 .loc 1 3283 17 + 5711 01e8 FB68 ldr r3, [r7, #12] + 5712 01ea 2022 movs r2, #32 + 5713 01ec 83F84120 strb r2, [r3, #65] +3284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C error code */ +3286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + 5714 .loc 1 3286 9 + 5715 01f0 FB68 ldr r3, [r7, #12] + 5716 01f2 5B6C ldr r3, [r3, #68] + 5717 .loc 1 3286 21 + 5718 01f4 43F02002 orr r2, r3, #32 + 5719 01f8 FB68 ldr r3, [r7, #12] + 5720 01fa 5A64 str r2, [r3, #68] +3287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +3289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 5721 .loc 1 3289 5 + 5722 01fc FB68 ldr r3, [r7, #12] + 5723 01fe 0022 movs r2, #0 + 5724 0200 83F84020 strb r2, [r3, #64] +3290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 5725 .loc 1 3291 12 + 5726 0204 0123 movs r3, #1 + 5727 0206 00E0 b .L262 + 5728 .L260: +3292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; + 5729 .loc 1 3295 12 + 5730 0208 0223 movs r3, #2 + 5731 .L262: +3296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5732 .loc 1 3297 1 + 5733 020a 1846 mov r0, r3 + 5734 020c 2037 adds r7, r7, #32 + 5735 .cfi_def_cfa_offset 8 + 5736 020e BD46 mov sp, r7 + ARM GAS /tmp/cc5G5cqz.s page 160 + + + 5737 .cfi_def_cfa_register 13 + 5738 @ sp needed + 5739 0210 80BD pop {r7, pc} + 5740 .cfi_endproc + 5741 .LFE152: + 5743 .section .text.HAL_I2C_Master_Seq_Transmit_IT,"ax",%progbits + 5744 .align 1 + 5745 .global HAL_I2C_Master_Seq_Transmit_IT + 5746 .syntax unified + 5747 .thumb + 5748 .thumb_func + 5750 HAL_I2C_Master_Seq_Transmit_IT: + 5751 .LFB153: +3298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +3300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Inte +3301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @note This interface allow to manage repeated start condition when a direction change during +3302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +3304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +3305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +3306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer +3307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be sent +3308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS +3309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +3310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +3311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint +3312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t Size, uint32_t XferOptions) +3313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5752 .loc 1 3313 1 + 5753 .cfi_startproc + 5754 @ args = 4, pretend = 0, frame = 24 + 5755 @ frame_needed = 1, uses_anonymous_args = 0 + 5756 0000 80B5 push {r7, lr} + 5757 .cfi_def_cfa_offset 8 + 5758 .cfi_offset 7, -8 + 5759 .cfi_offset 14, -4 + 5760 0002 88B0 sub sp, sp, #32 + 5761 .cfi_def_cfa_offset 40 + 5762 0004 02AF add r7, sp, #8 + 5763 .cfi_def_cfa 7, 32 + 5764 0006 F860 str r0, [r7, #12] + 5765 0008 7A60 str r2, [r7, #4] + 5766 000a 1A46 mov r2, r3 + 5767 000c 0B46 mov r3, r1 @ movhi + 5768 000e 7B81 strh r3, [r7, #10] @ movhi + 5769 0010 1346 mov r3, r2 @ movhi + 5770 0012 3B81 strh r3, [r7, #8] @ movhi +3314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xfermode; +3315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xferrequest = I2C_GENERATE_START_WRITE; + 5771 .loc 1 3315 12 + 5772 0014 3A4B ldr r3, .L288 + 5773 0016 3B61 str r3, [r7, #16] +3316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check the parameters */ +3318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); +3319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/cc5G5cqz.s page 161 + + +3320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 5774 .loc 1 3320 11 + 5775 0018 FB68 ldr r3, [r7, #12] + 5776 001a 93F84130 ldrb r3, [r3, #65] + 5777 001e DBB2 uxtb r3, r3 + 5778 .loc 1 3320 6 + 5779 0020 202B cmp r3, #32 + 5780 0022 67D1 bne .L278 +3321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +3323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); + 5781 .loc 1 3323 5 + 5782 0024 FB68 ldr r3, [r7, #12] + 5783 0026 93F84030 ldrb r3, [r3, #64] @ zero_extendqisi2 + 5784 002a 012B cmp r3, #1 + 5785 002c 01D1 bne .L279 + 5786 .loc 1 3323 5 is_stmt 0 discriminator 1 + 5787 002e 0223 movs r3, #2 + 5788 .loc 1 3323 5 + 5789 0030 61E0 b .L280 + 5790 .L279: + 5791 .loc 1 3323 5 discriminator 2 + 5792 0032 FB68 ldr r3, [r7, #12] + 5793 0034 0122 movs r2, #1 + 5794 0036 83F84020 strb r2, [r3, #64] +3324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; + 5795 .loc 1 3325 21 is_stmt 1 + 5796 003a FB68 ldr r3, [r7, #12] + 5797 003c 2122 movs r2, #33 + 5798 003e 83F84120 strb r2, [r3, #65] +3326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 5799 .loc 1 3326 21 + 5800 0042 FB68 ldr r3, [r7, #12] + 5801 0044 1022 movs r2, #16 + 5802 0046 83F84220 strb r2, [r3, #66] +3327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 5803 .loc 1 3327 21 + 5804 004a FB68 ldr r3, [r7, #12] + 5805 004c 0022 movs r2, #0 + 5806 004e 5A64 str r2, [r3, #68] +3328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ +3330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; + 5807 .loc 1 3330 23 + 5808 0050 FB68 ldr r3, [r7, #12] + 5809 0052 7A68 ldr r2, [r7, #4] + 5810 0054 5A62 str r2, [r3, #36] +3331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 5811 .loc 1 3331 23 + 5812 0056 FB68 ldr r3, [r7, #12] + 5813 0058 3A89 ldrh r2, [r7, #8] @ movhi + 5814 005a 5A85 strh r2, [r3, #42] @ movhi +3332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 5815 .loc 1 3332 23 + 5816 005c FB68 ldr r3, [r7, #12] + 5817 005e 3A6A ldr r2, [r7, #32] + ARM GAS /tmp/cc5G5cqz.s page 162 + + + 5818 0060 DA62 str r2, [r3, #44] +3333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 5819 .loc 1 3333 23 + 5820 0062 FB68 ldr r3, [r7, #12] + 5821 0064 274A ldr r2, .L288+4 + 5822 0066 5A63 str r2, [r3, #52] +3334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ +3336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) + 5823 .loc 1 3336 13 + 5824 0068 FB68 ldr r3, [r7, #12] + 5825 006a 5B8D ldrh r3, [r3, #42] @ movhi + 5826 006c 9BB2 uxth r3, r3 + 5827 .loc 1 3336 8 + 5828 006e FF2B cmp r3, #255 + 5829 0070 06D9 bls .L281 +3337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; + 5830 .loc 1 3338 22 + 5831 0072 FB68 ldr r3, [r7, #12] + 5832 0074 FF22 movs r2, #255 + 5833 0076 1A85 strh r2, [r3, #40] @ movhi +3339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 5834 .loc 1 3339 16 + 5835 0078 4FF08073 mov r3, #16777216 + 5836 007c 7B61 str r3, [r7, #20] + 5837 007e 07E0 b .L282 + 5838 .L281: +3340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 5839 .loc 1 3343 28 + 5840 0080 FB68 ldr r3, [r7, #12] + 5841 0082 5B8D ldrh r3, [r3, #42] @ movhi + 5842 0084 9AB2 uxth r2, r3 + 5843 .loc 1 3343 22 + 5844 0086 FB68 ldr r3, [r7, #12] + 5845 0088 1A85 strh r2, [r3, #40] @ movhi +3344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 5846 .loc 1 3344 16 + 5847 008a FB68 ldr r3, [r7, #12] + 5848 008c DB6A ldr r3, [r3, #44] + 5849 008e 7B61 str r3, [r7, #20] + 5850 .L282: +3345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* If transfer direction not change and there is no request to start another frame, +3348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** do not generate Restart Condition */ +3349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Mean Previous state is same as current state */ +3350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \ + 5851 .loc 1 3350 14 + 5852 0090 FB68 ldr r3, [r7, #12] + 5853 0092 1B6B ldr r3, [r3, #48] + 5854 .loc 1 3350 8 + 5855 0094 112B cmp r3, #17 + 5856 0096 0ED1 bne .L283 + ARM GAS /tmp/cc5G5cqz.s page 163 + + +3351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + 5857 .loc 1 3351 10 + 5858 0098 3B6A ldr r3, [r7, #32] + 5859 009a AA2B cmp r3, #170 + 5860 009c 03D0 beq .L284 + 5861 .loc 1 3351 10 is_stmt 0 discriminator 2 + 5862 009e 3B6A ldr r3, [r7, #32] + 5863 00a0 B3F52A4F cmp r3, #43520 + 5864 00a4 01D1 bne .L285 + 5865 .L284: + 5866 .loc 1 3351 10 discriminator 3 + 5867 00a6 0123 movs r3, #1 + 5868 .loc 1 3351 10 + 5869 00a8 00E0 b .L286 + 5870 .L285: + 5871 .loc 1 3351 10 discriminator 4 + 5872 00aa 0023 movs r3, #0 + 5873 .L286: +3350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + 5874 .loc 1 3350 59 is_stmt 1 + 5875 00ac 002B cmp r3, #0 + 5876 00ae 02D1 bne .L283 +3352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xferrequest = I2C_NO_STARTSTOP; + 5877 .loc 1 3353 19 + 5878 00b0 0023 movs r3, #0 + 5879 00b2 3B61 str r3, [r7, #16] + 5880 00b4 0AE0 b .L287 + 5881 .L283: +3354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Convert OTHER_xxx XferOptions if any */ +3358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ConvertOtherXferOptions(hi2c); + 5882 .loc 1 3358 7 + 5883 00b6 F868 ldr r0, [r7, #12] + 5884 00b8 FFF7FEFF bl I2C_ConvertOtherXferOptions +3359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update xfermode accordingly if no reload is necessary */ +3361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount <= MAX_NBYTE_SIZE) + 5885 .loc 1 3361 15 + 5886 00bc FB68 ldr r3, [r7, #12] + 5887 00be 5B8D ldrh r3, [r3, #42] @ movhi + 5888 00c0 9BB2 uxth r3, r3 + 5889 .loc 1 3361 10 + 5890 00c2 FF2B cmp r3, #255 + 5891 00c4 02D8 bhi .L287 +3362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 5892 .loc 1 3363 18 + 5893 00c6 FB68 ldr r3, [r7, #12] + 5894 00c8 DB6A ldr r3, [r3, #44] + 5895 00ca 7B61 str r3, [r7, #20] + 5896 .L287: +3364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/cc5G5cqz.s page 164 + + +3367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send Slave Address and set NBYTES to write */ +3368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + 5897 .loc 1 3368 55 + 5898 00cc FB68 ldr r3, [r7, #12] + 5899 00ce 1B8D ldrh r3, [r3, #40] + 5900 .loc 1 3368 5 + 5901 00d0 DAB2 uxtb r2, r3 + 5902 00d2 7989 ldrh r1, [r7, #10] + 5903 00d4 3B69 ldr r3, [r7, #16] + 5904 00d6 0093 str r3, [sp] + 5905 00d8 7B69 ldr r3, [r7, #20] + 5906 00da F868 ldr r0, [r7, #12] + 5907 00dc FFF7FEFF bl I2C_TransferConfig +3369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +3371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 5908 .loc 1 3371 5 + 5909 00e0 FB68 ldr r3, [r7, #12] + 5910 00e2 0022 movs r2, #0 + 5911 00e4 83F84020 strb r2, [r3, #64] +3372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +3374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +3375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** process unlock */ +3376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, TXI interrupt */ +3377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* possible to enable all of these */ +3378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | +3379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ +3380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + 5912 .loc 1 3380 5 + 5913 00e8 0121 movs r1, #1 + 5914 00ea F868 ldr r0, [r7, #12] + 5915 00ec FFF7FEFF bl I2C_Enable_IRQ +3381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; + 5916 .loc 1 3382 12 + 5917 00f0 0023 movs r3, #0 + 5918 00f2 00E0 b .L280 + 5919 .L278: +3383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; + 5920 .loc 1 3386 12 + 5921 00f4 0223 movs r3, #2 + 5922 .L280: +3387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 5923 .loc 1 3388 1 + 5924 00f6 1846 mov r0, r3 + 5925 00f8 1837 adds r7, r7, #24 + 5926 .cfi_def_cfa_offset 8 + 5927 00fa BD46 mov sp, r7 + 5928 .cfi_def_cfa_register 13 + 5929 @ sp needed + 5930 00fc 80BD pop {r7, pc} + 5931 .L289: + ARM GAS /tmp/cc5G5cqz.s page 165 + + + 5932 00fe 00BF .align 2 + 5933 .L288: + 5934 0100 00200080 .word -2147475456 + 5935 0104 00000000 .word I2C_Master_ISR_IT + 5936 .cfi_endproc + 5937 .LFE153: + 5939 .section .text.HAL_I2C_Master_Seq_Transmit_DMA,"ax",%progbits + 5940 .align 1 + 5941 .global HAL_I2C_Master_Seq_Transmit_DMA + 5942 .syntax unified + 5943 .thumb + 5944 .thumb_func + 5946 HAL_I2C_Master_Seq_Transmit_DMA: + 5947 .LFB154: +3389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +3391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA. +3392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @note This interface allow to manage repeated start condition when a direction change during +3393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +3395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +3396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +3397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer +3398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be sent +3399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS +3400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +3401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +3402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uin +3403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t Size, uint32_t XferOptions) +3404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 5948 .loc 1 3404 1 + 5949 .cfi_startproc + 5950 @ args = 4, pretend = 0, frame = 32 + 5951 @ frame_needed = 1, uses_anonymous_args = 0 + 5952 0000 80B5 push {r7, lr} + 5953 .cfi_def_cfa_offset 8 + 5954 .cfi_offset 7, -8 + 5955 .cfi_offset 14, -4 + 5956 0002 8AB0 sub sp, sp, #40 + 5957 .cfi_def_cfa_offset 48 + 5958 0004 02AF add r7, sp, #8 + 5959 .cfi_def_cfa 7, 40 + 5960 0006 F860 str r0, [r7, #12] + 5961 0008 7A60 str r2, [r7, #4] + 5962 000a 1A46 mov r2, r3 + 5963 000c 0B46 mov r3, r1 @ movhi + 5964 000e 7B81 strh r3, [r7, #10] @ movhi + 5965 0010 1346 mov r3, r2 @ movhi + 5966 0012 3B81 strh r3, [r7, #8] @ movhi +3405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xfermode; +3406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xferrequest = I2C_GENERATE_START_WRITE; + 5967 .loc 1 3406 12 + 5968 0014 774B ldr r3, .L307 + 5969 0016 BB61 str r3, [r7, #24] +3407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; +3408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check the parameters */ + ARM GAS /tmp/cc5G5cqz.s page 166 + + +3410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); +3411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 5970 .loc 1 3412 11 + 5971 0018 FB68 ldr r3, [r7, #12] + 5972 001a 93F84130 ldrb r3, [r3, #65] + 5973 001e DBB2 uxtb r3, r3 + 5974 .loc 1 3412 6 + 5975 0020 202B cmp r3, #32 + 5976 0022 40F0E180 bne .L291 +3413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +3415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); + 5977 .loc 1 3415 5 + 5978 0026 FB68 ldr r3, [r7, #12] + 5979 0028 93F84030 ldrb r3, [r3, #64] @ zero_extendqisi2 + 5980 002c 012B cmp r3, #1 + 5981 002e 01D1 bne .L292 + 5982 .loc 1 3415 5 is_stmt 0 discriminator 1 + 5983 0030 0223 movs r3, #2 + 5984 .loc 1 3415 5 + 5985 0032 DAE0 b .L293 + 5986 .L292: + 5987 .loc 1 3415 5 discriminator 2 + 5988 0034 FB68 ldr r3, [r7, #12] + 5989 0036 0122 movs r2, #1 + 5990 0038 83F84020 strb r2, [r3, #64] +3416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX; + 5991 .loc 1 3417 21 is_stmt 1 + 5992 003c FB68 ldr r3, [r7, #12] + 5993 003e 2122 movs r2, #33 + 5994 0040 83F84120 strb r2, [r3, #65] +3418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 5995 .loc 1 3418 21 + 5996 0044 FB68 ldr r3, [r7, #12] + 5997 0046 1022 movs r2, #16 + 5998 0048 83F84220 strb r2, [r3, #66] +3419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 5999 .loc 1 3419 21 + 6000 004c FB68 ldr r3, [r7, #12] + 6001 004e 0022 movs r2, #0 + 6002 0050 5A64 str r2, [r3, #68] +3420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ +3422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; + 6003 .loc 1 3422 23 + 6004 0052 FB68 ldr r3, [r7, #12] + 6005 0054 7A68 ldr r2, [r7, #4] + 6006 0056 5A62 str r2, [r3, #36] +3423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 6007 .loc 1 3423 23 + 6008 0058 FB68 ldr r3, [r7, #12] + 6009 005a 3A89 ldrh r2, [r7, #8] @ movhi + 6010 005c 5A85 strh r2, [r3, #42] @ movhi +3424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 6011 .loc 1 3424 23 + ARM GAS /tmp/cc5G5cqz.s page 167 + + + 6012 005e FB68 ldr r3, [r7, #12] + 6013 0060 BA6A ldr r2, [r7, #40] + 6014 0062 DA62 str r2, [r3, #44] +3425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 6015 .loc 1 3425 23 + 6016 0064 FB68 ldr r3, [r7, #12] + 6017 0066 644A ldr r2, .L307+4 + 6018 0068 5A63 str r2, [r3, #52] +3426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ +3428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) + 6019 .loc 1 3428 13 + 6020 006a FB68 ldr r3, [r7, #12] + 6021 006c 5B8D ldrh r3, [r3, #42] @ movhi + 6022 006e 9BB2 uxth r3, r3 + 6023 .loc 1 3428 8 + 6024 0070 FF2B cmp r3, #255 + 6025 0072 06D9 bls .L294 +3429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; + 6026 .loc 1 3430 22 + 6027 0074 FB68 ldr r3, [r7, #12] + 6028 0076 FF22 movs r2, #255 + 6029 0078 1A85 strh r2, [r3, #40] @ movhi +3431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 6030 .loc 1 3431 16 + 6031 007a 4FF08073 mov r3, #16777216 + 6032 007e FB61 str r3, [r7, #28] + 6033 0080 07E0 b .L295 + 6034 .L294: +3432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 6035 .loc 1 3435 28 + 6036 0082 FB68 ldr r3, [r7, #12] + 6037 0084 5B8D ldrh r3, [r3, #42] @ movhi + 6038 0086 9AB2 uxth r2, r3 + 6039 .loc 1 3435 22 + 6040 0088 FB68 ldr r3, [r7, #12] + 6041 008a 1A85 strh r2, [r3, #40] @ movhi +3436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 6042 .loc 1 3436 16 + 6043 008c FB68 ldr r3, [r7, #12] + 6044 008e DB6A ldr r3, [r3, #44] + 6045 0090 FB61 str r3, [r7, #28] + 6046 .L295: +3437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* If transfer direction not change and there is no request to start another frame, +3440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** do not generate Restart Condition */ +3441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Mean Previous state is same as current state */ +3442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \ + 6047 .loc 1 3442 14 + 6048 0092 FB68 ldr r3, [r7, #12] + 6049 0094 1B6B ldr r3, [r3, #48] + 6050 .loc 1 3442 8 + ARM GAS /tmp/cc5G5cqz.s page 168 + + + 6051 0096 112B cmp r3, #17 + 6052 0098 0ED1 bne .L296 +3443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + 6053 .loc 1 3443 10 + 6054 009a BB6A ldr r3, [r7, #40] + 6055 009c AA2B cmp r3, #170 + 6056 009e 03D0 beq .L297 + 6057 .loc 1 3443 10 is_stmt 0 discriminator 2 + 6058 00a0 BB6A ldr r3, [r7, #40] + 6059 00a2 B3F52A4F cmp r3, #43520 + 6060 00a6 01D1 bne .L298 + 6061 .L297: + 6062 .loc 1 3443 10 discriminator 3 + 6063 00a8 0123 movs r3, #1 + 6064 .loc 1 3443 10 + 6065 00aa 00E0 b .L299 + 6066 .L298: + 6067 .loc 1 3443 10 discriminator 4 + 6068 00ac 0023 movs r3, #0 + 6069 .L299: +3442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + 6070 .loc 1 3442 59 is_stmt 1 + 6071 00ae 002B cmp r3, #0 + 6072 00b0 02D1 bne .L296 +3444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xferrequest = I2C_NO_STARTSTOP; + 6073 .loc 1 3445 19 + 6074 00b2 0023 movs r3, #0 + 6075 00b4 BB61 str r3, [r7, #24] + 6076 00b6 0AE0 b .L300 + 6077 .L296: +3446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Convert OTHER_xxx XferOptions if any */ +3450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ConvertOtherXferOptions(hi2c); + 6078 .loc 1 3450 7 + 6079 00b8 F868 ldr r0, [r7, #12] + 6080 00ba FFF7FEFF bl I2C_ConvertOtherXferOptions +3451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update xfermode accordingly if no reload is necessary */ +3453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount <= MAX_NBYTE_SIZE) + 6081 .loc 1 3453 15 + 6082 00be FB68 ldr r3, [r7, #12] + 6083 00c0 5B8D ldrh r3, [r3, #42] @ movhi + 6084 00c2 9BB2 uxth r3, r3 + 6085 .loc 1 3453 10 + 6086 00c4 FF2B cmp r3, #255 + 6087 00c6 02D8 bhi .L300 +3454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 6088 .loc 1 3455 18 + 6089 00c8 FB68 ldr r3, [r7, #12] + 6090 00ca DB6A ldr r3, [r3, #44] + 6091 00cc FB61 str r3, [r7, #28] + 6092 .L300: +3456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/cc5G5cqz.s page 169 + + +3457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferSize > 0U) + 6093 .loc 1 3459 13 + 6094 00ce FB68 ldr r3, [r7, #12] + 6095 00d0 1B8D ldrh r3, [r3, #40] + 6096 .loc 1 3459 8 + 6097 00d2 002B cmp r3, #0 + 6098 00d4 70D0 beq .L301 +3460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) + 6099 .loc 1 3461 15 + 6100 00d6 FB68 ldr r3, [r7, #12] + 6101 00d8 9B6B ldr r3, [r3, #56] + 6102 .loc 1 3461 10 + 6103 00da 002B cmp r3, #0 + 6104 00dc 20D0 beq .L302 +3462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +3464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + 6105 .loc 1 3464 13 + 6106 00de FB68 ldr r3, [r7, #12] + 6107 00e0 9B6B ldr r3, [r3, #56] + 6108 .loc 1 3464 40 + 6109 00e2 464A ldr r2, .L307+8 + 6110 00e4 9A62 str r2, [r3, #40] +3465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the DMA error callback */ +3467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + 6111 .loc 1 3467 13 + 6112 00e6 FB68 ldr r3, [r7, #12] + 6113 00e8 9B6B ldr r3, [r3, #56] + 6114 .loc 1 3467 41 + 6115 00ea 454A ldr r2, .L307+12 + 6116 00ec 1A63 str r2, [r3, #48] +3468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +3470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferHalfCpltCallback = NULL; + 6117 .loc 1 3470 13 + 6118 00ee FB68 ldr r3, [r7, #12] + 6119 00f0 9B6B ldr r3, [r3, #56] + 6120 .loc 1 3470 44 + 6121 00f2 0022 movs r2, #0 + 6122 00f4 DA62 str r2, [r3, #44] +3471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 6123 .loc 1 3471 13 + 6124 00f6 FB68 ldr r3, [r7, #12] + 6125 00f8 9B6B ldr r3, [r3, #56] + 6126 .loc 1 3471 41 + 6127 00fa 0022 movs r2, #0 + 6128 00fc 5A63 str r2, [r3, #52] +3472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable the DMA channel */ +3474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance-> + 6129 .loc 1 3474 25 + 6130 00fe FB68 ldr r3, [r7, #12] + 6131 0100 986B ldr r0, [r3, #56] + ARM GAS /tmp/cc5G5cqz.s page 170 + + + 6132 0102 7968 ldr r1, [r7, #4] + 6133 .loc 1 3474 88 + 6134 0104 FB68 ldr r3, [r7, #12] + 6135 0106 1B68 ldr r3, [r3] + 6136 .loc 1 3474 83 + 6137 0108 2833 adds r3, r3, #40 + 6138 .loc 1 3474 25 + 6139 010a 1A46 mov r2, r3 +3475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); + 6140 .loc 1 3475 46 + 6141 010c FB68 ldr r3, [r7, #12] + 6142 010e 1B8D ldrh r3, [r3, #40] +3474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); + 6143 .loc 1 3474 25 + 6144 0110 FFF7FEFF bl HAL_DMA_Start_IT + 6145 0114 0346 mov r3, r0 + 6146 0116 FB75 strb r3, [r7, #23] +3476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C state */ +3480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +3481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +3482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C error code */ +3484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; +3485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +3487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +3490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (dmaxferstatus == HAL_OK) + 6147 .loc 1 3492 10 + 6148 0118 FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 6149 011a 002B cmp r3, #0 + 6150 011c 38D1 bne .L304 + 6151 011e 13E0 b .L306 + 6152 .L302: +3480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 6153 .loc 1 3480 25 + 6154 0120 FB68 ldr r3, [r7, #12] + 6155 0122 2022 movs r2, #32 + 6156 0124 83F84120 strb r2, [r3, #65] +3481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6157 .loc 1 3481 25 + 6158 0128 FB68 ldr r3, [r7, #12] + 6159 012a 0022 movs r2, #0 + 6160 012c 83F84220 strb r2, [r3, #66] +3484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6161 .loc 1 3484 13 + 6162 0130 FB68 ldr r3, [r7, #12] + 6163 0132 5B6C ldr r3, [r3, #68] +3484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6164 .loc 1 3484 25 + 6165 0134 43F08002 orr r2, r3, #128 + ARM GAS /tmp/cc5G5cqz.s page 171 + + + 6166 0138 FB68 ldr r3, [r7, #12] + 6167 013a 5A64 str r2, [r3, #68] +3487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6168 .loc 1 3487 9 + 6169 013c FB68 ldr r3, [r7, #12] + 6170 013e 0022 movs r2, #0 + 6171 0140 83F84020 strb r2, [r3, #64] +3489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6172 .loc 1 3489 16 + 6173 0144 0123 movs r3, #1 + 6174 0146 50E0 b .L293 + 6175 .L306: +3493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send Slave Address and set NBYTES to write */ +3495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + 6176 .loc 1 3495 59 + 6177 0148 FB68 ldr r3, [r7, #12] + 6178 014a 1B8D ldrh r3, [r3, #40] + 6179 .loc 1 3495 9 + 6180 014c DAB2 uxtb r2, r3 + 6181 014e 7989 ldrh r1, [r7, #10] + 6182 0150 BB69 ldr r3, [r7, #24] + 6183 0152 0093 str r3, [sp] + 6184 0154 FB69 ldr r3, [r7, #28] + 6185 0156 F868 ldr r0, [r7, #12] + 6186 0158 FFF7FEFF bl I2C_TransferConfig +3496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update XferCount value */ +3498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount -= hi2c->XferSize; + 6187 .loc 1 3498 13 + 6188 015c FB68 ldr r3, [r7, #12] + 6189 015e 5B8D ldrh r3, [r3, #42] @ movhi + 6190 0160 9AB2 uxth r2, r3 + 6191 .loc 1 3498 32 + 6192 0162 FB68 ldr r3, [r7, #12] + 6193 0164 1B8D ldrh r3, [r3, #40] + 6194 .loc 1 3498 25 + 6195 0166 D31A subs r3, r2, r3 + 6196 0168 9AB2 uxth r2, r3 + 6197 016a FB68 ldr r3, [r7, #12] + 6198 016c 5A85 strh r2, [r3, #42] @ movhi +3499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +3501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 6199 .loc 1 3501 9 + 6200 016e FB68 ldr r3, [r7, #12] + 6201 0170 0022 movs r2, #0 + 6202 0172 83F84020 strb r2, [r3, #64] +3502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +3504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +3505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** process unlock */ +3506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR and NACK interrupts */ +3507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + 6203 .loc 1 3507 9 + 6204 0176 1021 movs r1, #16 + 6205 0178 F868 ldr r0, [r7, #12] + ARM GAS /tmp/cc5G5cqz.s page 172 + + + 6206 017a FFF7FEFF bl I2C_Enable_IRQ +3508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable DMA Request */ +3510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + 6207 .loc 1 3510 13 + 6208 017e FB68 ldr r3, [r7, #12] + 6209 0180 1B68 ldr r3, [r3] + 6210 .loc 1 3510 23 + 6211 0182 1A68 ldr r2, [r3] + 6212 .loc 1 3510 13 + 6213 0184 FB68 ldr r3, [r7, #12] + 6214 0186 1B68 ldr r3, [r3] + 6215 .loc 1 3510 29 + 6216 0188 42F48042 orr r2, r2, #16384 + 6217 018c 1A60 str r2, [r3] + 6218 018e 29E0 b .L305 + 6219 .L304: +3511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C state */ +3515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 6220 .loc 1 3515 25 + 6221 0190 FB68 ldr r3, [r7, #12] + 6222 0192 2022 movs r2, #32 + 6223 0194 83F84120 strb r2, [r3, #65] +3516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 6224 .loc 1 3516 25 + 6225 0198 FB68 ldr r3, [r7, #12] + 6226 019a 0022 movs r2, #0 + 6227 019c 83F84220 strb r2, [r3, #66] +3517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C error code */ +3519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + 6228 .loc 1 3519 13 + 6229 01a0 FB68 ldr r3, [r7, #12] + 6230 01a2 5B6C ldr r3, [r3, #68] + 6231 .loc 1 3519 25 + 6232 01a4 43F01002 orr r2, r3, #16 + 6233 01a8 FB68 ldr r3, [r7, #12] + 6234 01aa 5A64 str r2, [r3, #68] +3520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +3522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 6235 .loc 1 3522 9 + 6236 01ac FB68 ldr r3, [r7, #12] + 6237 01ae 0022 movs r2, #0 + 6238 01b0 83F84020 strb r2, [r3, #64] +3523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 6239 .loc 1 3524 16 + 6240 01b4 0123 movs r3, #1 + 6241 01b6 18E0 b .L293 + 6242 .L301: +3525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else + ARM GAS /tmp/cc5G5cqz.s page 173 + + +3528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update Transfer ISR function pointer */ +3530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 6243 .loc 1 3530 21 + 6244 01b8 FB68 ldr r3, [r7, #12] + 6245 01ba 124A ldr r2, .L307+16 + 6246 01bc 5A63 str r2, [r3, #52] +3531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send Slave Address */ +3533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set NBYTES to write and generate START condition */ +3534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 6247 .loc 1 3534 57 + 6248 01be FB68 ldr r3, [r7, #12] + 6249 01c0 1B8D ldrh r3, [r3, #40] + 6250 .loc 1 3534 7 + 6251 01c2 DAB2 uxtb r2, r3 + 6252 01c4 7989 ldrh r1, [r7, #10] + 6253 01c6 0B4B ldr r3, .L307 + 6254 01c8 0093 str r3, [sp] + 6255 01ca 4FF00073 mov r3, #33554432 + 6256 01ce F868 ldr r0, [r7, #12] + 6257 01d0 FFF7FEFF bl I2C_TransferConfig +3535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_GENERATE_START_WRITE); +3536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +3538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 6258 .loc 1 3538 7 + 6259 01d4 FB68 ldr r3, [r7, #12] + 6260 01d6 0022 movs r2, #0 + 6261 01d8 83F84020 strb r2, [r3, #64] +3539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +3541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +3542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** process unlock */ +3543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, TXI interrupt */ +3544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* possible to enable all of these */ +3545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | +3546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ +3547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + 6262 .loc 1 3547 7 + 6263 01dc 0121 movs r1, #1 + 6264 01de F868 ldr r0, [r7, #12] + 6265 01e0 FFF7FEFF bl I2C_Enable_IRQ + 6266 .L305: +3548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; + 6267 .loc 1 3550 12 + 6268 01e4 0023 movs r3, #0 + 6269 01e6 00E0 b .L293 + 6270 .L291: +3551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; + 6271 .loc 1 3554 12 + 6272 01e8 0223 movs r3, #2 + ARM GAS /tmp/cc5G5cqz.s page 174 + + + 6273 .L293: +3555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6274 .loc 1 3556 1 + 6275 01ea 1846 mov r0, r3 + 6276 01ec 2037 adds r7, r7, #32 + 6277 .cfi_def_cfa_offset 8 + 6278 01ee BD46 mov sp, r7 + 6279 .cfi_def_cfa_register 13 + 6280 @ sp needed + 6281 01f0 80BD pop {r7, pc} + 6282 .L308: + 6283 01f2 00BF .align 2 + 6284 .L307: + 6285 01f4 00200080 .word -2147475456 + 6286 01f8 00000000 .word I2C_Master_ISR_DMA + 6287 01fc 00000000 .word I2C_DMAMasterTransmitCplt + 6288 0200 00000000 .word I2C_DMAError + 6289 0204 00000000 .word I2C_Master_ISR_IT + 6290 .cfi_endproc + 6291 .LFE154: + 6293 .section .text.HAL_I2C_Master_Seq_Receive_IT,"ax",%progbits + 6294 .align 1 + 6295 .global HAL_I2C_Master_Seq_Receive_IT + 6296 .syntax unified + 6297 .thumb + 6298 .thumb_func + 6300 HAL_I2C_Master_Seq_Receive_IT: + 6301 .LFB155: +3557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +3559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Inter +3560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @note This interface allow to manage repeated start condition when a direction change during +3561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +3563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +3564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +3565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer +3566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be sent +3567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS +3568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +3569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +3570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8 +3571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t Size, uint32_t XferOptions) +3572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6302 .loc 1 3572 1 + 6303 .cfi_startproc + 6304 @ args = 4, pretend = 0, frame = 24 + 6305 @ frame_needed = 1, uses_anonymous_args = 0 + 6306 0000 80B5 push {r7, lr} + 6307 .cfi_def_cfa_offset 8 + 6308 .cfi_offset 7, -8 + 6309 .cfi_offset 14, -4 + 6310 0002 88B0 sub sp, sp, #32 + 6311 .cfi_def_cfa_offset 40 + 6312 0004 02AF add r7, sp, #8 + 6313 .cfi_def_cfa 7, 32 + ARM GAS /tmp/cc5G5cqz.s page 175 + + + 6314 0006 F860 str r0, [r7, #12] + 6315 0008 7A60 str r2, [r7, #4] + 6316 000a 1A46 mov r2, r3 + 6317 000c 0B46 mov r3, r1 @ movhi + 6318 000e 7B81 strh r3, [r7, #10] @ movhi + 6319 0010 1346 mov r3, r2 @ movhi + 6320 0012 3B81 strh r3, [r7, #8] @ movhi +3573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xfermode; +3574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xferrequest = I2C_GENERATE_START_READ; + 6321 .loc 1 3574 12 + 6322 0014 3A4B ldr r3, .L320 + 6323 0016 3B61 str r3, [r7, #16] +3575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check the parameters */ +3577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); +3578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 6324 .loc 1 3579 11 + 6325 0018 FB68 ldr r3, [r7, #12] + 6326 001a 93F84130 ldrb r3, [r3, #65] + 6327 001e DBB2 uxtb r3, r3 + 6328 .loc 1 3579 6 + 6329 0020 202B cmp r3, #32 + 6330 0022 67D1 bne .L310 +3580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +3582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); + 6331 .loc 1 3582 5 + 6332 0024 FB68 ldr r3, [r7, #12] + 6333 0026 93F84030 ldrb r3, [r3, #64] @ zero_extendqisi2 + 6334 002a 012B cmp r3, #1 + 6335 002c 01D1 bne .L311 + 6336 .loc 1 3582 5 is_stmt 0 discriminator 1 + 6337 002e 0223 movs r3, #2 + 6338 .loc 1 3582 5 + 6339 0030 61E0 b .L312 + 6340 .L311: + 6341 .loc 1 3582 5 discriminator 2 + 6342 0032 FB68 ldr r3, [r7, #12] + 6343 0034 0122 movs r2, #1 + 6344 0036 83F84020 strb r2, [r3, #64] +3583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; + 6345 .loc 1 3584 21 is_stmt 1 + 6346 003a FB68 ldr r3, [r7, #12] + 6347 003c 2222 movs r2, #34 + 6348 003e 83F84120 strb r2, [r3, #65] +3585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 6349 .loc 1 3585 21 + 6350 0042 FB68 ldr r3, [r7, #12] + 6351 0044 1022 movs r2, #16 + 6352 0046 83F84220 strb r2, [r3, #66] +3586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 6353 .loc 1 3586 21 + 6354 004a FB68 ldr r3, [r7, #12] + 6355 004c 0022 movs r2, #0 + 6356 004e 5A64 str r2, [r3, #68] + ARM GAS /tmp/cc5G5cqz.s page 176 + + +3587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ +3589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; + 6357 .loc 1 3589 23 + 6358 0050 FB68 ldr r3, [r7, #12] + 6359 0052 7A68 ldr r2, [r7, #4] + 6360 0054 5A62 str r2, [r3, #36] +3590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 6361 .loc 1 3590 23 + 6362 0056 FB68 ldr r3, [r7, #12] + 6363 0058 3A89 ldrh r2, [r7, #8] @ movhi + 6364 005a 5A85 strh r2, [r3, #42] @ movhi +3591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 6365 .loc 1 3591 23 + 6366 005c FB68 ldr r3, [r7, #12] + 6367 005e 3A6A ldr r2, [r7, #32] + 6368 0060 DA62 str r2, [r3, #44] +3592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 6369 .loc 1 3592 23 + 6370 0062 FB68 ldr r3, [r7, #12] + 6371 0064 274A ldr r2, .L320+4 + 6372 0066 5A63 str r2, [r3, #52] +3593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ +3595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) + 6373 .loc 1 3595 13 + 6374 0068 FB68 ldr r3, [r7, #12] + 6375 006a 5B8D ldrh r3, [r3, #42] @ movhi + 6376 006c 9BB2 uxth r3, r3 + 6377 .loc 1 3595 8 + 6378 006e FF2B cmp r3, #255 + 6379 0070 06D9 bls .L313 +3596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; + 6380 .loc 1 3597 22 + 6381 0072 FB68 ldr r3, [r7, #12] + 6382 0074 FF22 movs r2, #255 + 6383 0076 1A85 strh r2, [r3, #40] @ movhi +3598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 6384 .loc 1 3598 16 + 6385 0078 4FF08073 mov r3, #16777216 + 6386 007c 7B61 str r3, [r7, #20] + 6387 007e 07E0 b .L314 + 6388 .L313: +3599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3602:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 6389 .loc 1 3602 28 + 6390 0080 FB68 ldr r3, [r7, #12] + 6391 0082 5B8D ldrh r3, [r3, #42] @ movhi + 6392 0084 9AB2 uxth r2, r3 + 6393 .loc 1 3602 22 + 6394 0086 FB68 ldr r3, [r7, #12] + 6395 0088 1A85 strh r2, [r3, #40] @ movhi +3603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 6396 .loc 1 3603 16 + ARM GAS /tmp/cc5G5cqz.s page 177 + + + 6397 008a FB68 ldr r3, [r7, #12] + 6398 008c DB6A ldr r3, [r3, #44] + 6399 008e 7B61 str r3, [r7, #20] + 6400 .L314: +3604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* If transfer direction not change and there is no request to start another frame, +3607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** do not generate Restart Condition */ +3608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Mean Previous state is same as current state */ +3609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \ + 6401 .loc 1 3609 14 + 6402 0090 FB68 ldr r3, [r7, #12] + 6403 0092 1B6B ldr r3, [r3, #48] + 6404 .loc 1 3609 8 + 6405 0094 122B cmp r3, #18 + 6406 0096 0ED1 bne .L315 +3610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + 6407 .loc 1 3610 10 + 6408 0098 3B6A ldr r3, [r7, #32] + 6409 009a AA2B cmp r3, #170 + 6410 009c 03D0 beq .L316 + 6411 .loc 1 3610 10 is_stmt 0 discriminator 2 + 6412 009e 3B6A ldr r3, [r7, #32] + 6413 00a0 B3F52A4F cmp r3, #43520 + 6414 00a4 01D1 bne .L317 + 6415 .L316: + 6416 .loc 1 3610 10 discriminator 3 + 6417 00a6 0123 movs r3, #1 + 6418 .loc 1 3610 10 + 6419 00a8 00E0 b .L318 + 6420 .L317: + 6421 .loc 1 3610 10 discriminator 4 + 6422 00aa 0023 movs r3, #0 + 6423 .L318: +3609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + 6424 .loc 1 3609 59 is_stmt 1 + 6425 00ac 002B cmp r3, #0 + 6426 00ae 02D1 bne .L315 +3611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3612:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xferrequest = I2C_NO_STARTSTOP; + 6427 .loc 1 3612 19 + 6428 00b0 0023 movs r3, #0 + 6429 00b2 3B61 str r3, [r7, #16] + 6430 00b4 0AE0 b .L319 + 6431 .L315: +3613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Convert OTHER_xxx XferOptions if any */ +3617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ConvertOtherXferOptions(hi2c); + 6432 .loc 1 3617 7 + 6433 00b6 F868 ldr r0, [r7, #12] + 6434 00b8 FFF7FEFF bl I2C_ConvertOtherXferOptions +3618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update xfermode accordingly if no reload is necessary */ +3620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount <= MAX_NBYTE_SIZE) + 6435 .loc 1 3620 15 + ARM GAS /tmp/cc5G5cqz.s page 178 + + + 6436 00bc FB68 ldr r3, [r7, #12] + 6437 00be 5B8D ldrh r3, [r3, #42] @ movhi + 6438 00c0 9BB2 uxth r3, r3 + 6439 .loc 1 3620 10 + 6440 00c2 FF2B cmp r3, #255 + 6441 00c4 02D8 bhi .L319 +3621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 6442 .loc 1 3622 18 + 6443 00c6 FB68 ldr r3, [r7, #12] + 6444 00c8 DB6A ldr r3, [r3, #44] + 6445 00ca 7B61 str r3, [r7, #20] + 6446 .L319: +3623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send Slave Address and set NBYTES to read */ +3627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + 6447 .loc 1 3627 55 + 6448 00cc FB68 ldr r3, [r7, #12] + 6449 00ce 1B8D ldrh r3, [r3, #40] + 6450 .loc 1 3627 5 + 6451 00d0 DAB2 uxtb r2, r3 + 6452 00d2 7989 ldrh r1, [r7, #10] + 6453 00d4 3B69 ldr r3, [r7, #16] + 6454 00d6 0093 str r3, [sp] + 6455 00d8 7B69 ldr r3, [r7, #20] + 6456 00da F868 ldr r0, [r7, #12] + 6457 00dc FFF7FEFF bl I2C_TransferConfig +3628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +3630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 6458 .loc 1 3630 5 + 6459 00e0 FB68 ldr r3, [r7, #12] + 6460 00e2 0022 movs r2, #0 + 6461 00e4 83F84020 strb r2, [r3, #64] +3631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +3633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +3634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** process unlock */ +3635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + 6462 .loc 1 3635 5 + 6463 00e8 0221 movs r1, #2 + 6464 00ea F868 ldr r0, [r7, #12] + 6465 00ec FFF7FEFF bl I2C_Enable_IRQ +3636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; + 6466 .loc 1 3637 12 + 6467 00f0 0023 movs r3, #0 + 6468 00f2 00E0 b .L312 + 6469 .L310: +3638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; + 6470 .loc 1 3641 12 + 6471 00f4 0223 movs r3, #2 + ARM GAS /tmp/cc5G5cqz.s page 179 + + + 6472 .L312: +3642:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6473 .loc 1 3643 1 + 6474 00f6 1846 mov r0, r3 + 6475 00f8 1837 adds r7, r7, #24 + 6476 .cfi_def_cfa_offset 8 + 6477 00fa BD46 mov sp, r7 + 6478 .cfi_def_cfa_register 13 + 6479 @ sp needed + 6480 00fc 80BD pop {r7, pc} + 6481 .L321: + 6482 00fe 00BF .align 2 + 6483 .L320: + 6484 0100 00240080 .word -2147474432 + 6485 0104 00000000 .word I2C_Master_ISR_IT + 6486 .cfi_endproc + 6487 .LFE155: + 6489 .section .text.HAL_I2C_Master_Seq_Receive_DMA,"ax",%progbits + 6490 .align 1 + 6491 .global HAL_I2C_Master_Seq_Receive_DMA + 6492 .syntax unified + 6493 .thumb + 6494 .thumb_func + 6496 HAL_I2C_Master_Seq_Receive_DMA: + 6497 .LFB156: +3644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +3646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA +3647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @note This interface allow to manage repeated start condition when a direction change during +3648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +3650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +3651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +3652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer +3653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be sent +3654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS +3655:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +3656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +3657:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint +3658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t Size, uint32_t XferOptions) +3659:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6498 .loc 1 3659 1 + 6499 .cfi_startproc + 6500 @ args = 4, pretend = 0, frame = 32 + 6501 @ frame_needed = 1, uses_anonymous_args = 0 + 6502 0000 80B5 push {r7, lr} + 6503 .cfi_def_cfa_offset 8 + 6504 .cfi_offset 7, -8 + 6505 .cfi_offset 14, -4 + 6506 0002 8AB0 sub sp, sp, #40 + 6507 .cfi_def_cfa_offset 48 + 6508 0004 02AF add r7, sp, #8 + 6509 .cfi_def_cfa 7, 40 + 6510 0006 F860 str r0, [r7, #12] + 6511 0008 7A60 str r2, [r7, #4] + 6512 000a 1A46 mov r2, r3 + ARM GAS /tmp/cc5G5cqz.s page 180 + + + 6513 000c 0B46 mov r3, r1 @ movhi + 6514 000e 7B81 strh r3, [r7, #10] @ movhi + 6515 0010 1346 mov r3, r2 @ movhi + 6516 0012 3B81 strh r3, [r7, #8] @ movhi +3660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xfermode; +3661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xferrequest = I2C_GENERATE_START_READ; + 6517 .loc 1 3661 12 + 6518 0014 774B ldr r3, .L339 + 6519 0016 BB61 str r3, [r7, #24] +3662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; +3663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3664:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check the parameters */ +3665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); +3666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 6520 .loc 1 3667 11 + 6521 0018 FB68 ldr r3, [r7, #12] + 6522 001a 93F84130 ldrb r3, [r3, #65] + 6523 001e DBB2 uxtb r3, r3 + 6524 .loc 1 3667 6 + 6525 0020 202B cmp r3, #32 + 6526 0022 40F0E180 bne .L323 +3668:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +3670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); + 6527 .loc 1 3670 5 + 6528 0026 FB68 ldr r3, [r7, #12] + 6529 0028 93F84030 ldrb r3, [r3, #64] @ zero_extendqisi2 + 6530 002c 012B cmp r3, #1 + 6531 002e 01D1 bne .L324 + 6532 .loc 1 3670 5 is_stmt 0 discriminator 1 + 6533 0030 0223 movs r3, #2 + 6534 .loc 1 3670 5 + 6535 0032 DAE0 b .L325 + 6536 .L324: + 6537 .loc 1 3670 5 discriminator 2 + 6538 0034 FB68 ldr r3, [r7, #12] + 6539 0036 0122 movs r2, #1 + 6540 0038 83F84020 strb r2, [r3, #64] +3671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX; + 6541 .loc 1 3672 21 is_stmt 1 + 6542 003c FB68 ldr r3, [r7, #12] + 6543 003e 2222 movs r2, #34 + 6544 0040 83F84120 strb r2, [r3, #65] +3673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_MASTER; + 6545 .loc 1 3673 21 + 6546 0044 FB68 ldr r3, [r7, #12] + 6547 0046 1022 movs r2, #16 + 6548 0048 83F84220 strb r2, [r3, #66] +3674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 6549 .loc 1 3674 21 + 6550 004c FB68 ldr r3, [r7, #12] + 6551 004e 0022 movs r2, #0 + 6552 0050 5A64 str r2, [r3, #68] +3675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ + ARM GAS /tmp/cc5G5cqz.s page 181 + + +3677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; + 6553 .loc 1 3677 23 + 6554 0052 FB68 ldr r3, [r7, #12] + 6555 0054 7A68 ldr r2, [r7, #4] + 6556 0056 5A62 str r2, [r3, #36] +3678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 6557 .loc 1 3678 23 + 6558 0058 FB68 ldr r3, [r7, #12] + 6559 005a 3A89 ldrh r2, [r7, #8] @ movhi + 6560 005c 5A85 strh r2, [r3, #42] @ movhi +3679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 6561 .loc 1 3679 23 + 6562 005e FB68 ldr r3, [r7, #12] + 6563 0060 BA6A ldr r2, [r7, #40] + 6564 0062 DA62 str r2, [r3, #44] +3680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_DMA; + 6565 .loc 1 3680 23 + 6566 0064 FB68 ldr r3, [r7, #12] + 6567 0066 644A ldr r2, .L339+4 + 6568 0068 5A63 str r2, [r3, #52] +3681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ +3683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) + 6569 .loc 1 3683 13 + 6570 006a FB68 ldr r3, [r7, #12] + 6571 006c 5B8D ldrh r3, [r3, #42] @ movhi + 6572 006e 9BB2 uxth r3, r3 + 6573 .loc 1 3683 8 + 6574 0070 FF2B cmp r3, #255 + 6575 0072 06D9 bls .L326 +3684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; + 6576 .loc 1 3685 22 + 6577 0074 FB68 ldr r3, [r7, #12] + 6578 0076 FF22 movs r2, #255 + 6579 0078 1A85 strh r2, [r3, #40] @ movhi +3686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 6580 .loc 1 3686 16 + 6581 007a 4FF08073 mov r3, #16777216 + 6582 007e FB61 str r3, [r7, #28] + 6583 0080 07E0 b .L327 + 6584 .L326: +3687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3688:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 6585 .loc 1 3690 28 + 6586 0082 FB68 ldr r3, [r7, #12] + 6587 0084 5B8D ldrh r3, [r3, #42] @ movhi + 6588 0086 9AB2 uxth r2, r3 + 6589 .loc 1 3690 22 + 6590 0088 FB68 ldr r3, [r7, #12] + 6591 008a 1A85 strh r2, [r3, #40] @ movhi +3691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 6592 .loc 1 3691 16 + 6593 008c FB68 ldr r3, [r7, #12] + 6594 008e DB6A ldr r3, [r3, #44] + ARM GAS /tmp/cc5G5cqz.s page 182 + + + 6595 0090 FB61 str r3, [r7, #28] + 6596 .L327: +3692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3694:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* If transfer direction not change and there is no request to start another frame, +3695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** do not generate Restart Condition */ +3696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Mean Previous state is same as current state */ +3697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \ + 6597 .loc 1 3697 14 + 6598 0092 FB68 ldr r3, [r7, #12] + 6599 0094 1B6B ldr r3, [r3, #48] + 6600 .loc 1 3697 8 + 6601 0096 122B cmp r3, #18 + 6602 0098 0ED1 bne .L328 +3698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + 6603 .loc 1 3698 10 + 6604 009a BB6A ldr r3, [r7, #40] + 6605 009c AA2B cmp r3, #170 + 6606 009e 03D0 beq .L329 + 6607 .loc 1 3698 10 is_stmt 0 discriminator 2 + 6608 00a0 BB6A ldr r3, [r7, #40] + 6609 00a2 B3F52A4F cmp r3, #43520 + 6610 00a6 01D1 bne .L330 + 6611 .L329: + 6612 .loc 1 3698 10 discriminator 3 + 6613 00a8 0123 movs r3, #1 + 6614 .loc 1 3698 10 + 6615 00aa 00E0 b .L331 + 6616 .L330: + 6617 .loc 1 3698 10 discriminator 4 + 6618 00ac 0023 movs r3, #0 + 6619 .L331: +3697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + 6620 .loc 1 3697 59 is_stmt 1 + 6621 00ae 002B cmp r3, #0 + 6622 00b0 02D1 bne .L328 +3699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3700:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xferrequest = I2C_NO_STARTSTOP; + 6623 .loc 1 3700 19 + 6624 00b2 0023 movs r3, #0 + 6625 00b4 BB61 str r3, [r7, #24] + 6626 00b6 0AE0 b .L332 + 6627 .L328: +3701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3704:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Convert OTHER_xxx XferOptions if any */ +3705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ConvertOtherXferOptions(hi2c); + 6628 .loc 1 3705 7 + 6629 00b8 F868 ldr r0, [r7, #12] + 6630 00ba FFF7FEFF bl I2C_ConvertOtherXferOptions +3706:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3707:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update xfermode accordingly if no reload is necessary */ +3708:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount <= MAX_NBYTE_SIZE) + 6631 .loc 1 3708 15 + 6632 00be FB68 ldr r3, [r7, #12] + 6633 00c0 5B8D ldrh r3, [r3, #42] @ movhi + ARM GAS /tmp/cc5G5cqz.s page 183 + + + 6634 00c2 9BB2 uxth r3, r3 + 6635 .loc 1 3708 10 + 6636 00c4 FF2B cmp r3, #255 + 6637 00c6 02D8 bhi .L332 +3709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 6638 .loc 1 3710 18 + 6639 00c8 FB68 ldr r3, [r7, #12] + 6640 00ca DB6A ldr r3, [r3, #44] + 6641 00cc FB61 str r3, [r7, #28] + 6642 .L332: +3711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3713:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferSize > 0U) + 6643 .loc 1 3714 13 + 6644 00ce FB68 ldr r3, [r7, #12] + 6645 00d0 1B8D ldrh r3, [r3, #40] + 6646 .loc 1 3714 8 + 6647 00d2 002B cmp r3, #0 + 6648 00d4 70D0 beq .L333 +3715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3716:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) + 6649 .loc 1 3716 15 + 6650 00d6 FB68 ldr r3, [r7, #12] + 6651 00d8 DB6B ldr r3, [r3, #60] + 6652 .loc 1 3716 10 + 6653 00da 002B cmp r3, #0 + 6654 00dc 20D0 beq .L334 +3717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3718:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +3719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + 6655 .loc 1 3719 13 + 6656 00de FB68 ldr r3, [r7, #12] + 6657 00e0 DB6B ldr r3, [r3, #60] + 6658 .loc 1 3719 40 + 6659 00e2 464A ldr r2, .L339+8 + 6660 00e4 9A62 str r2, [r3, #40] +3720:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the DMA error callback */ +3722:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + 6661 .loc 1 3722 13 + 6662 00e6 FB68 ldr r3, [r7, #12] + 6663 00e8 DB6B ldr r3, [r3, #60] + 6664 .loc 1 3722 41 + 6665 00ea 454A ldr r2, .L339+12 + 6666 00ec 1A63 str r2, [r3, #48] +3723:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3724:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +3725:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferHalfCpltCallback = NULL; + 6667 .loc 1 3725 13 + 6668 00ee FB68 ldr r3, [r7, #12] + 6669 00f0 DB6B ldr r3, [r3, #60] + 6670 .loc 1 3725 44 + 6671 00f2 0022 movs r2, #0 + 6672 00f4 DA62 str r2, [r3, #44] +3726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + ARM GAS /tmp/cc5G5cqz.s page 184 + + + 6673 .loc 1 3726 13 + 6674 00f6 FB68 ldr r3, [r7, #12] + 6675 00f8 DB6B ldr r3, [r3, #60] + 6676 .loc 1 3726 41 + 6677 00fa 0022 movs r2, #0 + 6678 00fc 5A63 str r2, [r3, #52] +3727:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable the DMA channel */ +3729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)p + 6679 .loc 1 3729 25 + 6680 00fe FB68 ldr r3, [r7, #12] + 6681 0100 D86B ldr r0, [r3, #60] + 6682 .loc 1 3729 71 + 6683 0102 FB68 ldr r3, [r7, #12] + 6684 0104 1B68 ldr r3, [r3] + 6685 .loc 1 3729 66 + 6686 0106 2433 adds r3, r3, #36 + 6687 .loc 1 3729 25 + 6688 0108 1946 mov r1, r3 + 6689 010a 7A68 ldr r2, [r7, #4] +3730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); + 6690 .loc 1 3730 46 + 6691 010c FB68 ldr r3, [r7, #12] + 6692 010e 1B8D ldrh r3, [r3, #40] +3729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); + 6693 .loc 1 3729 25 + 6694 0110 FFF7FEFF bl HAL_DMA_Start_IT + 6695 0114 0346 mov r3, r0 + 6696 0116 FB75 strb r3, [r7, #23] +3731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3734:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C state */ +3735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +3736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +3737:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C error code */ +3739:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; +3740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +3742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +3743:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +3745:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3746:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3747:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (dmaxferstatus == HAL_OK) + 6697 .loc 1 3747 10 + 6698 0118 FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 6699 011a 002B cmp r3, #0 + 6700 011c 38D1 bne .L336 + 6701 011e 13E0 b .L338 + 6702 .L334: +3735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 6703 .loc 1 3735 25 + 6704 0120 FB68 ldr r3, [r7, #12] + 6705 0122 2022 movs r2, #32 + 6706 0124 83F84120 strb r2, [r3, #65] + ARM GAS /tmp/cc5G5cqz.s page 185 + + +3736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6707 .loc 1 3736 25 + 6708 0128 FB68 ldr r3, [r7, #12] + 6709 012a 0022 movs r2, #0 + 6710 012c 83F84220 strb r2, [r3, #66] +3739:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6711 .loc 1 3739 13 + 6712 0130 FB68 ldr r3, [r7, #12] + 6713 0132 5B6C ldr r3, [r3, #68] +3739:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6714 .loc 1 3739 25 + 6715 0134 43F08002 orr r2, r3, #128 + 6716 0138 FB68 ldr r3, [r7, #12] + 6717 013a 5A64 str r2, [r3, #68] +3742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 6718 .loc 1 3742 9 + 6719 013c FB68 ldr r3, [r7, #12] + 6720 013e 0022 movs r2, #0 + 6721 0140 83F84020 strb r2, [r3, #64] +3744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6722 .loc 1 3744 16 + 6723 0144 0123 movs r3, #1 + 6724 0146 50E0 b .L325 + 6725 .L338: +3748:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send Slave Address and set NBYTES to read */ +3750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + 6726 .loc 1 3750 59 + 6727 0148 FB68 ldr r3, [r7, #12] + 6728 014a 1B8D ldrh r3, [r3, #40] + 6729 .loc 1 3750 9 + 6730 014c DAB2 uxtb r2, r3 + 6731 014e 7989 ldrh r1, [r7, #10] + 6732 0150 BB69 ldr r3, [r7, #24] + 6733 0152 0093 str r3, [sp] + 6734 0154 FB69 ldr r3, [r7, #28] + 6735 0156 F868 ldr r0, [r7, #12] + 6736 0158 FFF7FEFF bl I2C_TransferConfig +3751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3752:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update XferCount value */ +3753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount -= hi2c->XferSize; + 6737 .loc 1 3753 13 + 6738 015c FB68 ldr r3, [r7, #12] + 6739 015e 5B8D ldrh r3, [r3, #42] @ movhi + 6740 0160 9AB2 uxth r2, r3 + 6741 .loc 1 3753 32 + 6742 0162 FB68 ldr r3, [r7, #12] + 6743 0164 1B8D ldrh r3, [r3, #40] + 6744 .loc 1 3753 25 + 6745 0166 D31A subs r3, r2, r3 + 6746 0168 9AB2 uxth r2, r3 + 6747 016a FB68 ldr r3, [r7, #12] + 6748 016c 5A85 strh r2, [r3, #42] @ movhi +3754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3755:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +3756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 6749 .loc 1 3756 9 + ARM GAS /tmp/cc5G5cqz.s page 186 + + + 6750 016e FB68 ldr r3, [r7, #12] + 6751 0170 0022 movs r2, #0 + 6752 0172 83F84020 strb r2, [r3, #64] +3757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3758:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +3759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +3760:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** process unlock */ +3761:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR and NACK interrupts */ +3762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + 6753 .loc 1 3762 9 + 6754 0176 1021 movs r1, #16 + 6755 0178 F868 ldr r0, [r7, #12] + 6756 017a FFF7FEFF bl I2C_Enable_IRQ +3763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3764:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable DMA Request */ +3765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + 6757 .loc 1 3765 13 + 6758 017e FB68 ldr r3, [r7, #12] + 6759 0180 1B68 ldr r3, [r3] + 6760 .loc 1 3765 23 + 6761 0182 1A68 ldr r2, [r3] + 6762 .loc 1 3765 13 + 6763 0184 FB68 ldr r3, [r7, #12] + 6764 0186 1B68 ldr r3, [r3] + 6765 .loc 1 3765 29 + 6766 0188 42F40042 orr r2, r2, #32768 + 6767 018c 1A60 str r2, [r3] + 6768 018e 29E0 b .L337 + 6769 .L336: +3766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3767:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C state */ +3770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 6770 .loc 1 3770 25 + 6771 0190 FB68 ldr r3, [r7, #12] + 6772 0192 2022 movs r2, #32 + 6773 0194 83F84120 strb r2, [r3, #65] +3771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 6774 .loc 1 3771 25 + 6775 0198 FB68 ldr r3, [r7, #12] + 6776 019a 0022 movs r2, #0 + 6777 019c 83F84220 strb r2, [r3, #66] +3772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C error code */ +3774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + 6778 .loc 1 3774 13 + 6779 01a0 FB68 ldr r3, [r7, #12] + 6780 01a2 5B6C ldr r3, [r3, #68] + 6781 .loc 1 3774 25 + 6782 01a4 43F01002 orr r2, r3, #16 + 6783 01a8 FB68 ldr r3, [r7, #12] + 6784 01aa 5A64 str r2, [r3, #68] +3775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +3777:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 6785 .loc 1 3777 9 + ARM GAS /tmp/cc5G5cqz.s page 187 + + + 6786 01ac FB68 ldr r3, [r7, #12] + 6787 01ae 0022 movs r2, #0 + 6788 01b0 83F84020 strb r2, [r3, #64] +3778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 6789 .loc 1 3779 16 + 6790 01b4 0123 movs r3, #1 + 6791 01b6 18E0 b .L325 + 6792 .L333: +3780:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3782:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update Transfer ISR function pointer */ +3785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Master_ISR_IT; + 6793 .loc 1 3785 21 + 6794 01b8 FB68 ldr r3, [r7, #12] + 6795 01ba 124A ldr r2, .L339+16 + 6796 01bc 5A63 str r2, [r3, #52] +3786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3787:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send Slave Address */ +3788:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set NBYTES to read and generate START condition */ +3789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + 6797 .loc 1 3789 57 + 6798 01be FB68 ldr r3, [r7, #12] + 6799 01c0 1B8D ldrh r3, [r3, #40] + 6800 .loc 1 3789 7 + 6801 01c2 DAB2 uxtb r2, r3 + 6802 01c4 7989 ldrh r1, [r7, #10] + 6803 01c6 0B4B ldr r3, .L339 + 6804 01c8 0093 str r3, [sp] + 6805 01ca 4FF00073 mov r3, #33554432 + 6806 01ce F868 ldr r0, [r7, #12] + 6807 01d0 FFF7FEFF bl I2C_TransferConfig +3790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_GENERATE_START_READ); +3791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +3793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 6808 .loc 1 3793 7 + 6809 01d4 FB68 ldr r3, [r7, #12] + 6810 01d6 0022 movs r2, #0 + 6811 01d8 83F84020 strb r2, [r3, #64] +3794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +3796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +3797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** process unlock */ +3798:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK, TXI interrupt */ +3799:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* possible to enable all of these */ +3800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | +3801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ +3802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + 6812 .loc 1 3802 7 + 6813 01dc 0121 movs r1, #1 + 6814 01de F868 ldr r0, [r7, #12] + 6815 01e0 FFF7FEFF bl I2C_Enable_IRQ + 6816 .L337: +3803:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/cc5G5cqz.s page 188 + + +3804:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; + 6817 .loc 1 3805 12 + 6818 01e4 0023 movs r3, #0 + 6819 01e6 00E0 b .L325 + 6820 .L323: +3806:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3807:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3808:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; + 6821 .loc 1 3809 12 + 6822 01e8 0223 movs r3, #2 + 6823 .L325: +3810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3811:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 6824 .loc 1 3811 1 + 6825 01ea 1846 mov r0, r3 + 6826 01ec 2037 adds r7, r7, #32 + 6827 .cfi_def_cfa_offset 8 + 6828 01ee BD46 mov sp, r7 + 6829 .cfi_def_cfa_register 13 + 6830 @ sp needed + 6831 01f0 80BD pop {r7, pc} + 6832 .L340: + 6833 01f2 00BF .align 2 + 6834 .L339: + 6835 01f4 00240080 .word -2147474432 + 6836 01f8 00000000 .word I2C_Master_ISR_DMA + 6837 01fc 00000000 .word I2C_DMAMasterReceiveCplt + 6838 0200 00000000 .word I2C_DMAError + 6839 0204 00000000 .word I2C_Master_ISR_IT + 6840 .cfi_endproc + 6841 .LFE156: + 6843 .section .text.HAL_I2C_Slave_Seq_Transmit_IT,"ax",%progbits + 6844 .align 1 + 6845 .global HAL_I2C_Slave_Seq_Transmit_IT + 6846 .syntax unified + 6847 .thumb + 6848 .thumb_func + 6850 HAL_I2C_Slave_Seq_Transmit_IT: + 6851 .LFB157: +3812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +3814:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode wit +3815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @note This interface allow to manage repeated start condition when a direction change during +3816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3817:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +3818:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer +3819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be sent +3820:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS +3821:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +3822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +3823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t S +3824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t XferOptions) +3825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 6852 .loc 1 3825 1 + 6853 .cfi_startproc + ARM GAS /tmp/cc5G5cqz.s page 189 + + + 6854 @ args = 0, pretend = 0, frame = 24 + 6855 @ frame_needed = 1, uses_anonymous_args = 0 + 6856 0000 80B5 push {r7, lr} + 6857 .cfi_def_cfa_offset 8 + 6858 .cfi_offset 7, -8 + 6859 .cfi_offset 14, -4 + 6860 0002 86B0 sub sp, sp, #24 + 6861 .cfi_def_cfa_offset 32 + 6862 0004 00AF add r7, sp, #0 + 6863 .cfi_def_cfa_register 7 + 6864 0006 F860 str r0, [r7, #12] + 6865 0008 B960 str r1, [r7, #8] + 6866 000a 3B60 str r3, [r7] + 6867 000c 1346 mov r3, r2 @ movhi + 6868 000e FB80 strh r3, [r7, #6] @ movhi +3826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Declaration of tmp to prevent undefined behavior of volatile usage */ +3827:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** FlagStatus tmp; +3828:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3829:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check the parameters */ +3830:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); +3831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3832:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + 6869 .loc 1 3832 22 + 6870 0010 FB68 ldr r3, [r7, #12] + 6871 0012 93F84130 ldrb r3, [r3, #65] + 6872 0016 DBB2 uxtb r3, r3 + 6873 .loc 1 3832 30 + 6874 0018 03F02803 and r3, r3, #40 + 6875 .loc 1 3832 6 + 6876 001c 282B cmp r3, #40 + 6877 001e 40F09880 bne .L342 +3833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3834:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) + 6878 .loc 1 3834 8 + 6879 0022 BB68 ldr r3, [r7, #8] + 6880 0024 002B cmp r3, #0 + 6881 0026 02D0 beq .L343 + 6882 .loc 1 3834 25 discriminator 1 + 6883 0028 FB88 ldrh r3, [r7, #6] + 6884 002a 002B cmp r3, #0 + 6885 002c 05D1 bne .L344 + 6886 .L343: +3835:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3836:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + 6887 .loc 1 3836 23 + 6888 002e FB68 ldr r3, [r7, #12] + 6889 0030 4FF40072 mov r2, #512 + 6890 0034 5A64 str r2, [r3, #68] +3837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 6891 .loc 1 3837 15 + 6892 0036 0123 movs r3, #1 + 6893 0038 8CE0 b .L345 + 6894 .L344: +3838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3840:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ +3841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + ARM GAS /tmp/cc5G5cqz.s page 190 + + + 6895 .loc 1 3841 5 + 6896 003a 48F20101 movw r1, #32769 + 6897 003e F868 ldr r0, [r7, #12] + 6898 0040 FFF7FEFF bl I2C_Disable_IRQ +3842:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3843:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +3844:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); + 6899 .loc 1 3844 5 + 6900 0044 FB68 ldr r3, [r7, #12] + 6901 0046 93F84030 ldrb r3, [r3, #64] @ zero_extendqisi2 + 6902 004a 012B cmp r3, #1 + 6903 004c 01D1 bne .L346 + 6904 .loc 1 3844 5 is_stmt 0 discriminator 1 + 6905 004e 0223 movs r3, #2 + 6906 .loc 1 3844 5 + 6907 0050 80E0 b .L345 + 6908 .L346: + 6909 .loc 1 3844 5 discriminator 2 + 6910 0052 FB68 ldr r3, [r7, #12] + 6911 0054 0122 movs r2, #1 + 6912 0056 83F84020 strb r2, [r3, #64] +3845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3846:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ +3847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* and then toggle the HAL slave RX state to TX state */ +3848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + 6913 .loc 1 3848 13 is_stmt 1 + 6914 005a FB68 ldr r3, [r7, #12] + 6915 005c 93F84130 ldrb r3, [r3, #65] + 6916 0060 DBB2 uxtb r3, r3 + 6917 .loc 1 3848 8 + 6918 0062 2A2B cmp r3, #42 + 6919 0064 2AD1 bne .L347 +3849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable associated Interrupts */ +3851:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + 6920 .loc 1 3851 7 + 6921 0066 0221 movs r1, #2 + 6922 0068 F868 ldr r0, [r7, #12] + 6923 006a FFF7FEFF bl I2C_Disable_IRQ +3852:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3853:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Abort DMA Xfer if any */ +3854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + 6924 .loc 1 3854 16 + 6925 006e FB68 ldr r3, [r7, #12] + 6926 0070 1B68 ldr r3, [r3] + 6927 .loc 1 3854 26 + 6928 0072 1B68 ldr r3, [r3] + 6929 .loc 1 3854 32 + 6930 0074 03F40043 and r3, r3, #32768 + 6931 .loc 1 3854 10 + 6932 0078 B3F5004F cmp r3, #32768 + 6933 007c 1ED1 bne .L347 +3855:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3856:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + 6934 .loc 1 3856 13 + 6935 007e FB68 ldr r3, [r7, #12] + 6936 0080 1B68 ldr r3, [r3] + ARM GAS /tmp/cc5G5cqz.s page 191 + + + 6937 .loc 1 3856 23 + 6938 0082 1A68 ldr r2, [r3] + 6939 .loc 1 3856 13 + 6940 0084 FB68 ldr r3, [r7, #12] + 6941 0086 1B68 ldr r3, [r3] + 6942 .loc 1 3856 29 + 6943 0088 22F40042 bic r2, r2, #32768 + 6944 008c 1A60 str r2, [r3] +3857:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) + 6945 .loc 1 3858 17 + 6946 008e FB68 ldr r3, [r7, #12] + 6947 0090 DB6B ldr r3, [r3, #60] + 6948 .loc 1 3858 12 + 6949 0092 002B cmp r3, #0 + 6950 0094 12D0 beq .L347 +3859:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the I2C DMA Abort callback : +3861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ +3862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + 6951 .loc 1 3862 15 + 6952 0096 FB68 ldr r3, [r7, #12] + 6953 0098 DB6B ldr r3, [r3, #60] + 6954 .loc 1 3862 43 + 6955 009a 304A ldr r2, .L349 + 6956 009c 5A63 str r2, [r3, #52] +3863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3864:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Abort DMA RX */ +3865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + 6957 .loc 1 3865 15 + 6958 009e FB68 ldr r3, [r7, #12] + 6959 00a0 DB6B ldr r3, [r3, #60] + 6960 00a2 1846 mov r0, r3 + 6961 00a4 FFF7FEFF bl HAL_DMA_Abort_IT + 6962 00a8 0346 mov r3, r0 + 6963 .loc 1 3865 14 discriminator 1 + 6964 00aa 002B cmp r3, #0 + 6965 00ac 06D0 beq .L347 +3866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call Directly XferAbortCallback function in case of error */ +3868:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + 6966 .loc 1 3868 17 + 6967 00ae FB68 ldr r3, [r7, #12] + 6968 00b0 DB6B ldr r3, [r3, #60] + 6969 .loc 1 3868 25 + 6970 00b2 5B6B ldr r3, [r3, #52] + 6971 .loc 1 3868 49 + 6972 00b4 FA68 ldr r2, [r7, #12] + 6973 00b6 D26B ldr r2, [r2, #60] + 6974 .loc 1 3868 13 + 6975 00b8 1046 mov r0, r2 + 6976 00ba 9847 blx r3 + 6977 .LVL0: + 6978 .L347: +3869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3870:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/cc5G5cqz.s page 192 + + +3872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3873:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; + 6979 .loc 1 3874 21 + 6980 00bc FB68 ldr r3, [r7, #12] + 6981 00be 2922 movs r2, #41 + 6982 00c0 83F84120 strb r2, [r3, #65] +3875:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 6983 .loc 1 3875 21 + 6984 00c4 FB68 ldr r3, [r7, #12] + 6985 00c6 2022 movs r2, #32 + 6986 00c8 83F84220 strb r2, [r3, #66] +3876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 6987 .loc 1 3876 21 + 6988 00cc FB68 ldr r3, [r7, #12] + 6989 00ce 0022 movs r2, #0 + 6990 00d0 5A64 str r2, [r3, #68] +3877:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3878:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable Address Acknowledge */ +3879:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + 6991 .loc 1 3879 9 + 6992 00d2 FB68 ldr r3, [r7, #12] + 6993 00d4 1B68 ldr r3, [r3] + 6994 .loc 1 3879 19 + 6995 00d6 5A68 ldr r2, [r3, #4] + 6996 .loc 1 3879 9 + 6997 00d8 FB68 ldr r3, [r7, #12] + 6998 00da 1B68 ldr r3, [r3] + 6999 .loc 1 3879 25 + 7000 00dc 22F40042 bic r2, r2, #32768 + 7001 00e0 5A60 str r2, [r3, #4] +3880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ +3882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; + 7002 .loc 1 3882 23 + 7003 00e2 FB68 ldr r3, [r7, #12] + 7004 00e4 BA68 ldr r2, [r7, #8] + 7005 00e6 5A62 str r2, [r3, #36] +3883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 7006 .loc 1 3883 23 + 7007 00e8 FB68 ldr r3, [r7, #12] + 7008 00ea FA88 ldrh r2, [r7, #6] @ movhi + 7009 00ec 5A85 strh r2, [r3, #42] @ movhi +3884:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 7010 .loc 1 3884 29 + 7011 00ee FB68 ldr r3, [r7, #12] + 7012 00f0 5B8D ldrh r3, [r3, #42] @ movhi + 7013 00f2 9AB2 uxth r2, r3 + 7014 .loc 1 3884 23 + 7015 00f4 FB68 ldr r3, [r7, #12] + 7016 00f6 1A85 strh r2, [r3, #40] @ movhi +3885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 7017 .loc 1 3885 23 + 7018 00f8 FB68 ldr r3, [r7, #12] + 7019 00fa 3A68 ldr r2, [r7] + 7020 00fc DA62 str r2, [r3, #44] +3886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + ARM GAS /tmp/cc5G5cqz.s page 193 + + + 7021 .loc 1 3886 23 + 7022 00fe FB68 ldr r3, [r7, #12] + 7023 0100 174A ldr r2, .L349+4 + 7024 0102 5A63 str r2, [r3, #52] +3887:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3888:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + 7025 .loc 1 3888 11 + 7026 0104 FB68 ldr r3, [r7, #12] + 7027 0106 1B68 ldr r3, [r3] + 7028 0108 9B69 ldr r3, [r3, #24] + 7029 010a 03F00803 and r3, r3, #8 + 7030 010e 082B cmp r3, #8 + 7031 0110 0CBF ite eq + 7032 0112 0123 moveq r3, #1 + 7033 0114 0023 movne r3, #0 + 7034 0116 DBB2 uxtb r3, r3 + 7035 .loc 1 3888 9 + 7036 0118 FB75 strb r3, [r7, #23] +3889:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET)) + 7037 .loc 1 3889 10 + 7038 011a FB68 ldr r3, [r7, #12] + 7039 011c 1B68 ldr r3, [r3] + 7040 011e 9B69 ldr r3, [r3, #24] + 7041 0120 1B0C lsrs r3, r3, #16 + 7042 0122 DBB2 uxtb r3, r3 + 7043 0124 03F00103 and r3, r3, #1 + 7044 0128 DBB2 uxtb r3, r3 + 7045 .loc 1 3889 8 + 7046 012a 012B cmp r3, #1 + 7047 012c 06D1 bne .L348 + 7048 .loc 1 3889 54 discriminator 1 + 7049 012e FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 7050 0130 002B cmp r3, #0 + 7051 0132 03D0 beq .L348 +3890:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear ADDR flag after prepare the transfer parameters */ +3892:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* This action will generate an acknowledge to the Master */ +3893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + 7052 .loc 1 3893 7 + 7053 0134 FB68 ldr r3, [r7, #12] + 7054 0136 1B68 ldr r3, [r3] + 7055 0138 0822 movs r2, #8 + 7056 013a DA61 str r2, [r3, #28] + 7057 .L348: +3894:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3895:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +3897:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 7058 .loc 1 3897 5 + 7059 013c FB68 ldr r3, [r7, #12] + 7060 013e 0022 movs r2, #0 + 7061 0140 83F84020 strb r2, [r3, #64] +3898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3899:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +3900:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +3901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** process unlock */ +3902:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* REnable ADDR interrupt */ + ARM GAS /tmp/cc5G5cqz.s page 194 + + +3903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); + 7062 .loc 1 3903 5 + 7063 0144 48F20101 movw r1, #32769 + 7064 0148 F868 ldr r0, [r7, #12] + 7065 014a FFF7FEFF bl I2C_Enable_IRQ +3904:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3905:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; + 7066 .loc 1 3905 12 + 7067 014e 0023 movs r3, #0 + 7068 0150 00E0 b .L345 + 7069 .L342: +3906:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3908:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3909:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 7070 .loc 1 3909 12 + 7071 0152 0123 movs r3, #1 + 7072 .L345: +3910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3911:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7073 .loc 1 3911 1 + 7074 0154 1846 mov r0, r3 + 7075 0156 1837 adds r7, r7, #24 + 7076 .cfi_def_cfa_offset 8 + 7077 0158 BD46 mov sp, r7 + 7078 .cfi_def_cfa_register 13 + 7079 @ sp needed + 7080 015a 80BD pop {r7, pc} + 7081 .L350: + 7082 .align 2 + 7083 .L349: + 7084 015c 00000000 .word I2C_DMAAbort + 7085 0160 00000000 .word I2C_Slave_ISR_IT + 7086 .cfi_endproc + 7087 .LFE157: + 7089 .section .text.HAL_I2C_Slave_Seq_Transmit_DMA,"ax",%progbits + 7090 .align 1 + 7091 .global HAL_I2C_Slave_Seq_Transmit_DMA + 7092 .syntax unified + 7093 .thumb + 7094 .thumb_func + 7096 HAL_I2C_Slave_Seq_Transmit_DMA: + 7097 .LFB158: +3912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3913:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +3914:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode wit +3915:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @note This interface allow to manage repeated start condition when a direction change during +3916:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +3917:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +3918:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer +3919:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be sent +3920:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS +3921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +3922:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +3923:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t +3924:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t XferOptions) +3925:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + ARM GAS /tmp/cc5G5cqz.s page 195 + + + 7098 .loc 1 3925 1 + 7099 .cfi_startproc + 7100 @ args = 0, pretend = 0, frame = 24 + 7101 @ frame_needed = 1, uses_anonymous_args = 0 + 7102 0000 80B5 push {r7, lr} + 7103 .cfi_def_cfa_offset 8 + 7104 .cfi_offset 7, -8 + 7105 .cfi_offset 14, -4 + 7106 0002 86B0 sub sp, sp, #24 + 7107 .cfi_def_cfa_offset 32 + 7108 0004 00AF add r7, sp, #0 + 7109 .cfi_def_cfa_register 7 + 7110 0006 F860 str r0, [r7, #12] + 7111 0008 B960 str r1, [r7, #8] + 7112 000a 3B60 str r3, [r7] + 7113 000c 1346 mov r3, r2 @ movhi + 7114 000e FB80 strh r3, [r7, #6] @ movhi +3926:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Declaration of tmp to prevent undefined behavior of volatile usage */ +3927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** FlagStatus tmp; +3928:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; +3929:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3930:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check the parameters */ +3931:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); +3932:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + 7115 .loc 1 3933 22 + 7116 0010 FB68 ldr r3, [r7, #12] + 7117 0012 93F84130 ldrb r3, [r3, #65] + 7118 0016 DBB2 uxtb r3, r3 + 7119 .loc 1 3933 30 + 7120 0018 03F02803 and r3, r3, #40 + 7121 .loc 1 3933 6 + 7122 001c 282B cmp r3, #40 + 7123 001e 40F02881 bne .L352 +3934:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3935:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) + 7124 .loc 1 3935 8 + 7125 0022 BB68 ldr r3, [r7, #8] + 7126 0024 002B cmp r3, #0 + 7127 0026 02D0 beq .L353 + 7128 .loc 1 3935 25 discriminator 1 + 7129 0028 FB88 ldrh r3, [r7, #6] + 7130 002a 002B cmp r3, #0 + 7131 002c 05D1 bne .L354 + 7132 .L353: +3936:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + 7133 .loc 1 3937 23 + 7134 002e FB68 ldr r3, [r7, #12] + 7135 0030 4FF40072 mov r2, #512 + 7136 0034 5A64 str r2, [r3, #68] +3938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 7137 .loc 1 3938 15 + 7138 0036 0123 movs r3, #1 + 7139 0038 1CE1 b .L355 + 7140 .L354: +3939:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/cc5G5cqz.s page 196 + + +3940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3941:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +3942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); + 7141 .loc 1 3942 5 + 7142 003a FB68 ldr r3, [r7, #12] + 7143 003c 93F84030 ldrb r3, [r3, #64] @ zero_extendqisi2 + 7144 0040 012B cmp r3, #1 + 7145 0042 01D1 bne .L356 + 7146 .loc 1 3942 5 is_stmt 0 discriminator 1 + 7147 0044 0223 movs r3, #2 + 7148 .loc 1 3942 5 + 7149 0046 15E1 b .L355 + 7150 .L356: + 7151 .loc 1 3942 5 discriminator 2 + 7152 0048 FB68 ldr r3, [r7, #12] + 7153 004a 0122 movs r2, #1 + 7154 004c 83F84020 strb r2, [r3, #64] +3943:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3944:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ +3945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + 7155 .loc 1 3945 5 is_stmt 1 + 7156 0050 48F20101 movw r1, #32769 + 7157 0054 F868 ldr r0, [r7, #12] + 7158 0056 FFF7FEFF bl I2C_Disable_IRQ +3946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3947:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ +3948:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* and then toggle the HAL slave RX state to TX state */ +3949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + 7159 .loc 1 3949 13 + 7160 005a FB68 ldr r3, [r7, #12] + 7161 005c 93F84130 ldrb r3, [r3, #65] + 7162 0060 DBB2 uxtb r3, r3 + 7163 .loc 1 3949 8 + 7164 0062 2A2B cmp r3, #42 + 7165 0064 2BD1 bne .L357 +3950:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3951:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable associated Interrupts */ +3952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + 7166 .loc 1 3952 7 + 7167 0066 0221 movs r1, #2 + 7168 0068 F868 ldr r0, [r7, #12] + 7169 006a FFF7FEFF bl I2C_Disable_IRQ +3953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3954:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + 7170 .loc 1 3954 16 + 7171 006e FB68 ldr r3, [r7, #12] + 7172 0070 1B68 ldr r3, [r3] + 7173 .loc 1 3954 26 + 7174 0072 1B68 ldr r3, [r3] + 7175 .loc 1 3954 32 + 7176 0074 03F40043 and r3, r3, #32768 + 7177 .loc 1 3954 10 + 7178 0078 B3F5004F cmp r3, #32768 + 7179 007c 4CD1 bne .L358 +3955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3956:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Abort DMA Xfer if any */ +3957:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) + ARM GAS /tmp/cc5G5cqz.s page 197 + + + 7180 .loc 1 3957 17 + 7181 007e FB68 ldr r3, [r7, #12] + 7182 0080 DB6B ldr r3, [r3, #60] + 7183 .loc 1 3957 12 + 7184 0082 002B cmp r3, #0 + 7185 0084 48D0 beq .L358 +3958:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + 7186 .loc 1 3959 15 + 7187 0086 FB68 ldr r3, [r7, #12] + 7188 0088 1B68 ldr r3, [r3] + 7189 .loc 1 3959 25 + 7190 008a 1A68 ldr r2, [r3] + 7191 .loc 1 3959 15 + 7192 008c FB68 ldr r3, [r7, #12] + 7193 008e 1B68 ldr r3, [r3] + 7194 .loc 1 3959 31 + 7195 0090 22F40042 bic r2, r2, #32768 + 7196 0094 1A60 str r2, [r3] +3960:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the I2C DMA Abort callback : +3962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ +3963:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + 7197 .loc 1 3963 15 + 7198 0096 FB68 ldr r3, [r7, #12] + 7199 0098 DB6B ldr r3, [r3, #60] + 7200 .loc 1 3963 43 + 7201 009a 784A ldr r2, .L366 + 7202 009c 5A63 str r2, [r3, #52] +3964:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3965:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Abort DMA RX */ +3966:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + 7203 .loc 1 3966 15 + 7204 009e FB68 ldr r3, [r7, #12] + 7205 00a0 DB6B ldr r3, [r3, #60] + 7206 00a2 1846 mov r0, r3 + 7207 00a4 FFF7FEFF bl HAL_DMA_Abort_IT + 7208 00a8 0346 mov r3, r0 + 7209 .loc 1 3966 14 discriminator 1 + 7210 00aa 002B cmp r3, #0 + 7211 00ac 34D0 beq .L358 +3967:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call Directly XferAbortCallback function in case of error */ +3969:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + 7212 .loc 1 3969 17 + 7213 00ae FB68 ldr r3, [r7, #12] + 7214 00b0 DB6B ldr r3, [r3, #60] + 7215 .loc 1 3969 25 + 7216 00b2 5B6B ldr r3, [r3, #52] + 7217 .loc 1 3969 49 + 7218 00b4 FA68 ldr r2, [r7, #12] + 7219 00b6 D26B ldr r2, [r2, #60] + 7220 .loc 1 3969 13 + 7221 00b8 1046 mov r0, r2 + 7222 00ba 9847 blx r3 + 7223 .LVL1: + 7224 00bc 2CE0 b .L358 + ARM GAS /tmp/cc5G5cqz.s page 198 + + + 7225 .L357: +3970:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3971:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3972:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3973:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3974:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + 7226 .loc 1 3974 18 + 7227 00be FB68 ldr r3, [r7, #12] + 7228 00c0 93F84130 ldrb r3, [r3, #65] + 7229 00c4 DBB2 uxtb r3, r3 + 7230 .loc 1 3974 13 + 7231 00c6 292B cmp r3, #41 + 7232 00c8 26D1 bne .L358 +3975:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3976:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + 7233 .loc 1 3976 16 + 7234 00ca FB68 ldr r3, [r7, #12] + 7235 00cc 1B68 ldr r3, [r3] + 7236 .loc 1 3976 26 + 7237 00ce 1B68 ldr r3, [r3] + 7238 .loc 1 3976 32 + 7239 00d0 03F48043 and r3, r3, #16384 + 7240 .loc 1 3976 10 + 7241 00d4 B3F5804F cmp r3, #16384 + 7242 00d8 1ED1 bne .L358 +3977:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3978:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + 7243 .loc 1 3978 13 + 7244 00da FB68 ldr r3, [r7, #12] + 7245 00dc 1B68 ldr r3, [r3] + 7246 .loc 1 3978 23 + 7247 00de 1A68 ldr r2, [r3] + 7248 .loc 1 3978 13 + 7249 00e0 FB68 ldr r3, [r7, #12] + 7250 00e2 1B68 ldr r3, [r3] + 7251 .loc 1 3978 29 + 7252 00e4 22F48042 bic r2, r2, #16384 + 7253 00e8 1A60 str r2, [r3] +3979:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Abort DMA Xfer if any */ +3981:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) + 7254 .loc 1 3981 17 + 7255 00ea FB68 ldr r3, [r7, #12] + 7256 00ec 9B6B ldr r3, [r3, #56] + 7257 .loc 1 3981 12 + 7258 00ee 002B cmp r3, #0 + 7259 00f0 12D0 beq .L358 +3982:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3983:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the I2C DMA Abort callback : +3984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ +3985:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + 7260 .loc 1 3985 15 + 7261 00f2 FB68 ldr r3, [r7, #12] + 7262 00f4 9B6B ldr r3, [r3, #56] + 7263 .loc 1 3985 43 + 7264 00f6 614A ldr r2, .L366 + 7265 00f8 5A63 str r2, [r3, #52] + ARM GAS /tmp/cc5G5cqz.s page 199 + + +3986:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +3987:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Abort DMA TX */ +3988:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + 7266 .loc 1 3988 15 + 7267 00fa FB68 ldr r3, [r7, #12] + 7268 00fc 9B6B ldr r3, [r3, #56] + 7269 00fe 1846 mov r0, r3 + 7270 0100 FFF7FEFF bl HAL_DMA_Abort_IT + 7271 0104 0346 mov r3, r0 + 7272 .loc 1 3988 14 discriminator 1 + 7273 0106 002B cmp r3, #0 + 7274 0108 06D0 beq .L358 +3989:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3990:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call Directly XferAbortCallback function in case of error */ +3991:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + 7275 .loc 1 3991 17 + 7276 010a FB68 ldr r3, [r7, #12] + 7277 010c 9B6B ldr r3, [r3, #56] + 7278 .loc 1 3991 25 + 7279 010e 5B6B ldr r3, [r3, #52] + 7280 .loc 1 3991 49 + 7281 0110 FA68 ldr r2, [r7, #12] + 7282 0112 926B ldr r2, [r2, #56] + 7283 .loc 1 3991 13 + 7284 0114 1046 mov r0, r2 + 7285 0116 9847 blx r3 + 7286 .LVL2: + 7287 .L358: +3992:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3993:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3994:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +3996:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +3997:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +3998:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Nothing to do */ +3999:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4000:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4001:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; + 7288 .loc 1 4001 21 + 7289 0118 FB68 ldr r3, [r7, #12] + 7290 011a 2922 movs r2, #41 + 7291 011c 83F84120 strb r2, [r3, #65] +4002:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 7292 .loc 1 4002 21 + 7293 0120 FB68 ldr r3, [r7, #12] + 7294 0122 2022 movs r2, #32 + 7295 0124 83F84220 strb r2, [r3, #66] +4003:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 7296 .loc 1 4003 21 + 7297 0128 FB68 ldr r3, [r7, #12] + 7298 012a 0022 movs r2, #0 + 7299 012c 5A64 str r2, [r3, #68] +4004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4005:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable Address Acknowledge */ +4006:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + 7300 .loc 1 4006 9 + 7301 012e FB68 ldr r3, [r7, #12] + ARM GAS /tmp/cc5G5cqz.s page 200 + + + 7302 0130 1B68 ldr r3, [r3] + 7303 .loc 1 4006 19 + 7304 0132 5A68 ldr r2, [r3, #4] + 7305 .loc 1 4006 9 + 7306 0134 FB68 ldr r3, [r7, #12] + 7307 0136 1B68 ldr r3, [r3] + 7308 .loc 1 4006 25 + 7309 0138 22F40042 bic r2, r2, #32768 + 7310 013c 5A60 str r2, [r3, #4] +4007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4008:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ +4009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; + 7311 .loc 1 4009 23 + 7312 013e FB68 ldr r3, [r7, #12] + 7313 0140 BA68 ldr r2, [r7, #8] + 7314 0142 5A62 str r2, [r3, #36] +4010:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 7315 .loc 1 4010 23 + 7316 0144 FB68 ldr r3, [r7, #12] + 7317 0146 FA88 ldrh r2, [r7, #6] @ movhi + 7318 0148 5A85 strh r2, [r3, #42] @ movhi +4011:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 7319 .loc 1 4011 29 + 7320 014a FB68 ldr r3, [r7, #12] + 7321 014c 5B8D ldrh r3, [r3, #42] @ movhi + 7322 014e 9AB2 uxth r2, r3 + 7323 .loc 1 4011 23 + 7324 0150 FB68 ldr r3, [r7, #12] + 7325 0152 1A85 strh r2, [r3, #40] @ movhi +4012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 7326 .loc 1 4012 23 + 7327 0154 FB68 ldr r3, [r7, #12] + 7328 0156 3A68 ldr r2, [r7] + 7329 0158 DA62 str r2, [r3, #44] +4013:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; + 7330 .loc 1 4013 23 + 7331 015a FB68 ldr r3, [r7, #12] + 7332 015c 484A ldr r2, .L366+4 + 7333 015e 5A63 str r2, [r3, #52] +4014:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4015:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) + 7334 .loc 1 4015 13 + 7335 0160 FB68 ldr r3, [r7, #12] + 7336 0162 9B6B ldr r3, [r3, #56] + 7337 .loc 1 4015 8 + 7338 0164 002B cmp r3, #0 + 7339 0166 20D0 beq .L359 +4016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4017:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +4018:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; + 7340 .loc 1 4018 11 + 7341 0168 FB68 ldr r3, [r7, #12] + 7342 016a 9B6B ldr r3, [r3, #56] + 7343 .loc 1 4018 38 + 7344 016c 454A ldr r2, .L366+8 + 7345 016e 9A62 str r2, [r3, #40] +4019:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/cc5G5cqz.s page 201 + + +4020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the DMA error callback */ +4021:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + 7346 .loc 1 4021 11 + 7347 0170 FB68 ldr r3, [r7, #12] + 7348 0172 9B6B ldr r3, [r3, #56] + 7349 .loc 1 4021 39 + 7350 0174 444A ldr r2, .L366+12 + 7351 0176 1A63 str r2, [r3, #48] +4022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4023:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +4024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferHalfCpltCallback = NULL; + 7352 .loc 1 4024 11 + 7353 0178 FB68 ldr r3, [r7, #12] + 7354 017a 9B6B ldr r3, [r3, #56] + 7355 .loc 1 4024 42 + 7356 017c 0022 movs r2, #0 + 7357 017e DA62 str r2, [r3, #44] +4025:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 7358 .loc 1 4025 11 + 7359 0180 FB68 ldr r3, [r7, #12] + 7360 0182 9B6B ldr r3, [r3, #56] + 7361 .loc 1 4025 39 + 7362 0184 0022 movs r2, #0 + 7363 0186 5A63 str r2, [r3, #52] +4026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable the DMA channel */ +4028:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TX + 7364 .loc 1 4028 23 + 7365 0188 FB68 ldr r3, [r7, #12] + 7366 018a 986B ldr r0, [r3, #56] + 7367 018c B968 ldr r1, [r7, #8] + 7368 .loc 1 4028 86 + 7369 018e FB68 ldr r3, [r7, #12] + 7370 0190 1B68 ldr r3, [r3] + 7371 .loc 1 4028 81 + 7372 0192 2833 adds r3, r3, #40 + 7373 .loc 1 4028 23 + 7374 0194 1A46 mov r2, r3 +4029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); + 7375 .loc 1 4029 44 + 7376 0196 FB68 ldr r3, [r7, #12] + 7377 0198 1B8D ldrh r3, [r3, #40] +4028:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize); + 7378 .loc 1 4028 23 + 7379 019a FFF7FEFF bl HAL_DMA_Start_IT + 7380 019e 0346 mov r3, r0 + 7381 01a0 FB75 strb r3, [r7, #23] +4030:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4031:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +4032:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4033:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C state */ +4034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +4035:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +4036:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C error code */ +4038:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; +4039:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/cc5G5cqz.s page 202 + + +4040:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +4041:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +4042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4043:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +4044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4045:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4046:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (dmaxferstatus == HAL_OK) + 7382 .loc 1 4046 8 + 7383 01a2 FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 7384 01a4 002B cmp r3, #0 + 7385 01a6 36D1 bne .L361 + 7386 01a8 13E0 b .L364 + 7387 .L359: +4034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 7388 .loc 1 4034 23 + 7389 01aa FB68 ldr r3, [r7, #12] + 7390 01ac 2822 movs r2, #40 + 7391 01ae 83F84120 strb r2, [r3, #65] +4035:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7392 .loc 1 4035 23 + 7393 01b2 FB68 ldr r3, [r7, #12] + 7394 01b4 0022 movs r2, #0 + 7395 01b6 83F84220 strb r2, [r3, #66] +4038:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7396 .loc 1 4038 11 + 7397 01ba FB68 ldr r3, [r7, #12] + 7398 01bc 5B6C ldr r3, [r3, #68] +4038:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7399 .loc 1 4038 23 + 7400 01be 43F08002 orr r2, r3, #128 + 7401 01c2 FB68 ldr r3, [r7, #12] + 7402 01c4 5A64 str r2, [r3, #68] +4041:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7403 .loc 1 4041 7 + 7404 01c6 FB68 ldr r3, [r7, #12] + 7405 01c8 0022 movs r2, #0 + 7406 01ca 83F84020 strb r2, [r3, #64] +4043:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7407 .loc 1 4043 14 + 7408 01ce 0123 movs r3, #1 + 7409 01d0 50E0 b .L355 + 7410 .L364: +4047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update XferCount value */ +4049:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount -= hi2c->XferSize; + 7411 .loc 1 4049 11 + 7412 01d2 FB68 ldr r3, [r7, #12] + 7413 01d4 5B8D ldrh r3, [r3, #42] @ movhi + 7414 01d6 9AB2 uxth r2, r3 + 7415 .loc 1 4049 30 + 7416 01d8 FB68 ldr r3, [r7, #12] + 7417 01da 1B8D ldrh r3, [r3, #40] + 7418 .loc 1 4049 23 + 7419 01dc D31A subs r3, r2, r3 + 7420 01de 9AB2 uxth r2, r3 + 7421 01e0 FB68 ldr r3, [r7, #12] + 7422 01e2 5A85 strh r2, [r3, #42] @ movhi + ARM GAS /tmp/cc5G5cqz.s page 203 + + +4050:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Reset XferSize */ +4052:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = 0; + 7423 .loc 1 4052 22 + 7424 01e4 FB68 ldr r3, [r7, #12] + 7425 01e6 0022 movs r2, #0 + 7426 01e8 1A85 strh r2, [r3, #40] @ movhi +4053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +4055:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C state */ +4057:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +4058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +4059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4060:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C error code */ +4061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; +4062:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4063:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +4064:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +4065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4066:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +4067:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4069:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + 7427 .loc 1 4069 11 + 7428 01ea FB68 ldr r3, [r7, #12] + 7429 01ec 1B68 ldr r3, [r3] + 7430 01ee 9B69 ldr r3, [r3, #24] + 7431 01f0 03F00803 and r3, r3, #8 + 7432 01f4 082B cmp r3, #8 + 7433 01f6 0CBF ite eq + 7434 01f8 0123 moveq r3, #1 + 7435 01fa 0023 movne r3, #0 + 7436 01fc DBB2 uxtb r3, r3 + 7437 .loc 1 4069 9 + 7438 01fe BB75 strb r3, [r7, #22] +4070:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET)) + 7439 .loc 1 4070 10 + 7440 0200 FB68 ldr r3, [r7, #12] + 7441 0202 1B68 ldr r3, [r3] + 7442 0204 9B69 ldr r3, [r3, #24] + 7443 0206 1B0C lsrs r3, r3, #16 + 7444 0208 DBB2 uxtb r3, r3 + 7445 020a 03F00103 and r3, r3, #1 + 7446 020e DBB2 uxtb r3, r3 + 7447 .loc 1 4070 8 + 7448 0210 012B cmp r3, #1 + 7449 0212 1BD1 bne .L363 + 7450 0214 13E0 b .L365 + 7451 .L361: +4057:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 7452 .loc 1 4057 23 + 7453 0216 FB68 ldr r3, [r7, #12] + 7454 0218 2822 movs r2, #40 + 7455 021a 83F84120 strb r2, [r3, #65] +4058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7456 .loc 1 4058 23 + ARM GAS /tmp/cc5G5cqz.s page 204 + + + 7457 021e FB68 ldr r3, [r7, #12] + 7458 0220 0022 movs r2, #0 + 7459 0222 83F84220 strb r2, [r3, #66] +4061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7460 .loc 1 4061 11 + 7461 0226 FB68 ldr r3, [r7, #12] + 7462 0228 5B6C ldr r3, [r3, #68] +4061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7463 .loc 1 4061 23 + 7464 022a 43F01002 orr r2, r3, #16 + 7465 022e FB68 ldr r3, [r7, #12] + 7466 0230 5A64 str r2, [r3, #68] +4064:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 7467 .loc 1 4064 7 + 7468 0232 FB68 ldr r3, [r7, #12] + 7469 0234 0022 movs r2, #0 + 7470 0236 83F84020 strb r2, [r3, #64] +4066:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7471 .loc 1 4066 14 + 7472 023a 0123 movs r3, #1 + 7473 023c 1AE0 b .L355 + 7474 .L365: + 7475 .loc 1 4070 54 discriminator 1 + 7476 023e BB7D ldrb r3, [r7, #22] @ zero_extendqisi2 + 7477 0240 002B cmp r3, #0 + 7478 0242 03D0 beq .L363 +4071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4072:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear ADDR flag after prepare the transfer parameters */ +4073:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* This action will generate an acknowledge to the Master */ +4074:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + 7479 .loc 1 4074 7 + 7480 0244 FB68 ldr r3, [r7, #12] + 7481 0246 1B68 ldr r3, [r3] + 7482 0248 0822 movs r2, #8 + 7483 024a DA61 str r2, [r3, #28] + 7484 .L363: +4075:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4076:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4077:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +4078:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 7485 .loc 1 4078 5 + 7486 024c FB68 ldr r3, [r7, #12] + 7487 024e 0022 movs r2, #0 + 7488 0250 83F84020 strb r2, [r3, #64] +4079:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable DMA Request */ +4081:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + 7489 .loc 1 4081 9 + 7490 0254 FB68 ldr r3, [r7, #12] + 7491 0256 1B68 ldr r3, [r3] + 7492 .loc 1 4081 19 + 7493 0258 1A68 ldr r2, [r3] + 7494 .loc 1 4081 9 + 7495 025a FB68 ldr r3, [r7, #12] + 7496 025c 1B68 ldr r3, [r3] + 7497 .loc 1 4081 25 + 7498 025e 42F48042 orr r2, r2, #16384 + ARM GAS /tmp/cc5G5cqz.s page 205 + + + 7499 0262 1A60 str r2, [r3] +4082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +4084:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +4085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** process unlock */ +4086:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR, STOP, NACK, ADDR interrupts */ +4087:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + 7500 .loc 1 4087 5 + 7501 0264 4FF40041 mov r1, #32768 + 7502 0268 F868 ldr r0, [r7, #12] + 7503 026a FFF7FEFF bl I2C_Enable_IRQ +4088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4089:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; + 7504 .loc 1 4089 12 + 7505 026e 0023 movs r3, #0 + 7506 0270 00E0 b .L355 + 7507 .L352: +4090:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4091:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +4092:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4093:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 7508 .loc 1 4093 12 + 7509 0272 0123 movs r3, #1 + 7510 .L355: +4094:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7511 .loc 1 4095 1 + 7512 0274 1846 mov r0, r3 + 7513 0276 1837 adds r7, r7, #24 + 7514 .cfi_def_cfa_offset 8 + 7515 0278 BD46 mov sp, r7 + 7516 .cfi_def_cfa_register 13 + 7517 @ sp needed + 7518 027a 80BD pop {r7, pc} + 7519 .L367: + 7520 .align 2 + 7521 .L366: + 7522 027c 00000000 .word I2C_DMAAbort + 7523 0280 00000000 .word I2C_Slave_ISR_DMA + 7524 0284 00000000 .word I2C_DMASlaveTransmitCplt + 7525 0288 00000000 .word I2C_DMAError + 7526 .cfi_endproc + 7527 .LFE158: + 7529 .section .text.HAL_I2C_Slave_Seq_Receive_IT,"ax",%progbits + 7530 .align 1 + 7531 .global HAL_I2C_Slave_Seq_Receive_IT + 7532 .syntax unified + 7533 .thumb + 7534 .thumb_func + 7536 HAL_I2C_Slave_Seq_Receive_IT: + 7537 .LFB159: +4096:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4097:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +4098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with +4099:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @note This interface allow to manage repeated start condition when a direction change during +4100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. + ARM GAS /tmp/cc5G5cqz.s page 206 + + +4102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer +4103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be sent +4104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS +4105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +4106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Si +4108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t XferOptions) +4109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7538 .loc 1 4109 1 + 7539 .cfi_startproc + 7540 @ args = 0, pretend = 0, frame = 24 + 7541 @ frame_needed = 1, uses_anonymous_args = 0 + 7542 0000 80B5 push {r7, lr} + 7543 .cfi_def_cfa_offset 8 + 7544 .cfi_offset 7, -8 + 7545 .cfi_offset 14, -4 + 7546 0002 86B0 sub sp, sp, #24 + 7547 .cfi_def_cfa_offset 32 + 7548 0004 00AF add r7, sp, #0 + 7549 .cfi_def_cfa_register 7 + 7550 0006 F860 str r0, [r7, #12] + 7551 0008 B960 str r1, [r7, #8] + 7552 000a 3B60 str r3, [r7] + 7553 000c 1346 mov r3, r2 @ movhi + 7554 000e FB80 strh r3, [r7, #6] @ movhi +4110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Declaration of tmp to prevent undefined behavior of volatile usage */ +4111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** FlagStatus tmp; +4112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check the parameters */ +4114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); +4115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + 7555 .loc 1 4116 22 + 7556 0010 FB68 ldr r3, [r7, #12] + 7557 0012 93F84130 ldrb r3, [r3, #65] + 7558 0016 DBB2 uxtb r3, r3 + 7559 .loc 1 4116 30 + 7560 0018 03F02803 and r3, r3, #40 + 7561 .loc 1 4116 6 + 7562 001c 282B cmp r3, #40 + 7563 001e 40F09880 bne .L369 +4117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) + 7564 .loc 1 4118 8 + 7565 0022 BB68 ldr r3, [r7, #8] + 7566 0024 002B cmp r3, #0 + 7567 0026 02D0 beq .L370 + 7568 .loc 1 4118 25 discriminator 1 + 7569 0028 FB88 ldrh r3, [r7, #6] + 7570 002a 002B cmp r3, #0 + 7571 002c 05D1 bne .L371 + 7572 .L370: +4119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + 7573 .loc 1 4120 23 + 7574 002e FB68 ldr r3, [r7, #12] + 7575 0030 4FF40072 mov r2, #512 + ARM GAS /tmp/cc5G5cqz.s page 207 + + + 7576 0034 5A64 str r2, [r3, #68] +4121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 7577 .loc 1 4121 15 + 7578 0036 0123 movs r3, #1 + 7579 0038 8CE0 b .L372 + 7580 .L371: +4122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ +4125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + 7581 .loc 1 4125 5 + 7582 003a 48F20201 movw r1, #32770 + 7583 003e F868 ldr r0, [r7, #12] + 7584 0040 FFF7FEFF bl I2C_Disable_IRQ +4126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +4128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); + 7585 .loc 1 4128 5 + 7586 0044 FB68 ldr r3, [r7, #12] + 7587 0046 93F84030 ldrb r3, [r3, #64] @ zero_extendqisi2 + 7588 004a 012B cmp r3, #1 + 7589 004c 01D1 bne .L373 + 7590 .loc 1 4128 5 is_stmt 0 discriminator 1 + 7591 004e 0223 movs r3, #2 + 7592 .loc 1 4128 5 + 7593 0050 80E0 b .L372 + 7594 .L373: + 7595 .loc 1 4128 5 discriminator 2 + 7596 0052 FB68 ldr r3, [r7, #12] + 7597 0054 0122 movs r2, #1 + 7598 0056 83F84020 strb r2, [r3, #64] +4129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ +4131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* and then toggle the HAL slave TX state to RX state */ +4132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + 7599 .loc 1 4132 13 is_stmt 1 + 7600 005a FB68 ldr r3, [r7, #12] + 7601 005c 93F84130 ldrb r3, [r3, #65] + 7602 0060 DBB2 uxtb r3, r3 + 7603 .loc 1 4132 8 + 7604 0062 292B cmp r3, #41 + 7605 0064 2AD1 bne .L374 +4133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable associated Interrupts */ +4135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + 7606 .loc 1 4135 7 + 7607 0066 0121 movs r1, #1 + 7608 0068 F868 ldr r0, [r7, #12] + 7609 006a FFF7FEFF bl I2C_Disable_IRQ +4136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + 7610 .loc 1 4137 16 + 7611 006e FB68 ldr r3, [r7, #12] + 7612 0070 1B68 ldr r3, [r3] + 7613 .loc 1 4137 26 + 7614 0072 1B68 ldr r3, [r3] + 7615 .loc 1 4137 32 + ARM GAS /tmp/cc5G5cqz.s page 208 + + + 7616 0074 03F48043 and r3, r3, #16384 + 7617 .loc 1 4137 10 + 7618 0078 B3F5804F cmp r3, #16384 + 7619 007c 1ED1 bne .L374 +4138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + 7620 .loc 1 4139 13 + 7621 007e FB68 ldr r3, [r7, #12] + 7622 0080 1B68 ldr r3, [r3] + 7623 .loc 1 4139 23 + 7624 0082 1A68 ldr r2, [r3] + 7625 .loc 1 4139 13 + 7626 0084 FB68 ldr r3, [r7, #12] + 7627 0086 1B68 ldr r3, [r3] + 7628 .loc 1 4139 29 + 7629 0088 22F48042 bic r2, r2, #16384 + 7630 008c 1A60 str r2, [r3] +4140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Abort DMA Xfer if any */ +4142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) + 7631 .loc 1 4142 17 + 7632 008e FB68 ldr r3, [r7, #12] + 7633 0090 9B6B ldr r3, [r3, #56] + 7634 .loc 1 4142 12 + 7635 0092 002B cmp r3, #0 + 7636 0094 12D0 beq .L374 +4143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the I2C DMA Abort callback : +4145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ +4146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + 7637 .loc 1 4146 15 + 7638 0096 FB68 ldr r3, [r7, #12] + 7639 0098 9B6B ldr r3, [r3, #56] + 7640 .loc 1 4146 43 + 7641 009a 304A ldr r2, .L376 + 7642 009c 5A63 str r2, [r3, #52] +4147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Abort DMA TX */ +4149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + 7643 .loc 1 4149 15 + 7644 009e FB68 ldr r3, [r7, #12] + 7645 00a0 9B6B ldr r3, [r3, #56] + 7646 00a2 1846 mov r0, r3 + 7647 00a4 FFF7FEFF bl HAL_DMA_Abort_IT + 7648 00a8 0346 mov r3, r0 + 7649 .loc 1 4149 14 discriminator 1 + 7650 00aa 002B cmp r3, #0 + 7651 00ac 06D0 beq .L374 +4150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call Directly XferAbortCallback function in case of error */ +4152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + 7652 .loc 1 4152 17 + 7653 00ae FB68 ldr r3, [r7, #12] + 7654 00b0 9B6B ldr r3, [r3, #56] + 7655 .loc 1 4152 25 + 7656 00b2 5B6B ldr r3, [r3, #52] + 7657 .loc 1 4152 49 + ARM GAS /tmp/cc5G5cqz.s page 209 + + + 7658 00b4 FA68 ldr r2, [r7, #12] + 7659 00b6 926B ldr r2, [r2, #56] + 7660 .loc 1 4152 13 + 7661 00b8 1046 mov r0, r2 + 7662 00ba 9847 blx r3 + 7663 .LVL3: + 7664 .L374: +4153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; + 7665 .loc 1 4158 21 + 7666 00bc FB68 ldr r3, [r7, #12] + 7667 00be 2A22 movs r2, #42 + 7668 00c0 83F84120 strb r2, [r3, #65] +4159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 7669 .loc 1 4159 21 + 7670 00c4 FB68 ldr r3, [r7, #12] + 7671 00c6 2022 movs r2, #32 + 7672 00c8 83F84220 strb r2, [r3, #66] +4160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 7673 .loc 1 4160 21 + 7674 00cc FB68 ldr r3, [r7, #12] + 7675 00ce 0022 movs r2, #0 + 7676 00d0 5A64 str r2, [r3, #68] +4161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable Address Acknowledge */ +4163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + 7677 .loc 1 4163 9 + 7678 00d2 FB68 ldr r3, [r7, #12] + 7679 00d4 1B68 ldr r3, [r3] + 7680 .loc 1 4163 19 + 7681 00d6 5A68 ldr r2, [r3, #4] + 7682 .loc 1 4163 9 + 7683 00d8 FB68 ldr r3, [r7, #12] + 7684 00da 1B68 ldr r3, [r3] + 7685 .loc 1 4163 25 + 7686 00dc 22F40042 bic r2, r2, #32768 + 7687 00e0 5A60 str r2, [r3, #4] +4164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ +4166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; + 7688 .loc 1 4166 23 + 7689 00e2 FB68 ldr r3, [r7, #12] + 7690 00e4 BA68 ldr r2, [r7, #8] + 7691 00e6 5A62 str r2, [r3, #36] +4167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 7692 .loc 1 4167 23 + 7693 00e8 FB68 ldr r3, [r7, #12] + 7694 00ea FA88 ldrh r2, [r7, #6] @ movhi + 7695 00ec 5A85 strh r2, [r3, #42] @ movhi +4168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 7696 .loc 1 4168 29 + 7697 00ee FB68 ldr r3, [r7, #12] + 7698 00f0 5B8D ldrh r3, [r3, #42] @ movhi + ARM GAS /tmp/cc5G5cqz.s page 210 + + + 7699 00f2 9AB2 uxth r2, r3 + 7700 .loc 1 4168 23 + 7701 00f4 FB68 ldr r3, [r7, #12] + 7702 00f6 1A85 strh r2, [r3, #40] @ movhi +4169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 7703 .loc 1 4169 23 + 7704 00f8 FB68 ldr r3, [r7, #12] + 7705 00fa 3A68 ldr r2, [r7] + 7706 00fc DA62 str r2, [r3, #44] +4170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 7707 .loc 1 4170 23 + 7708 00fe FB68 ldr r3, [r7, #12] + 7709 0100 174A ldr r2, .L376+4 + 7710 0102 5A63 str r2, [r3, #52] +4171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + 7711 .loc 1 4172 11 + 7712 0104 FB68 ldr r3, [r7, #12] + 7713 0106 1B68 ldr r3, [r3] + 7714 0108 9B69 ldr r3, [r3, #24] + 7715 010a 03F00803 and r3, r3, #8 + 7716 010e 082B cmp r3, #8 + 7717 0110 0CBF ite eq + 7718 0112 0123 moveq r3, #1 + 7719 0114 0023 movne r3, #0 + 7720 0116 DBB2 uxtb r3, r3 + 7721 .loc 1 4172 9 + 7722 0118 FB75 strb r3, [r7, #23] +4173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET)) + 7723 .loc 1 4173 10 + 7724 011a FB68 ldr r3, [r7, #12] + 7725 011c 1B68 ldr r3, [r3] + 7726 011e 9B69 ldr r3, [r3, #24] + 7727 0120 1B0C lsrs r3, r3, #16 + 7728 0122 DBB2 uxtb r3, r3 + 7729 0124 03F00103 and r3, r3, #1 + 7730 0128 DBB2 uxtb r3, r3 + 7731 .loc 1 4173 8 + 7732 012a 002B cmp r3, #0 + 7733 012c 06D1 bne .L375 + 7734 .loc 1 4173 55 discriminator 1 + 7735 012e FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 7736 0130 002B cmp r3, #0 + 7737 0132 03D0 beq .L375 +4174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear ADDR flag after prepare the transfer parameters */ +4176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* This action will generate an acknowledge to the Master */ +4177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + 7738 .loc 1 4177 7 + 7739 0134 FB68 ldr r3, [r7, #12] + 7740 0136 1B68 ldr r3, [r3] + 7741 0138 0822 movs r2, #8 + 7742 013a DA61 str r2, [r3, #28] + 7743 .L375: +4178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ + ARM GAS /tmp/cc5G5cqz.s page 211 + + +4181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 7744 .loc 1 4181 5 + 7745 013c FB68 ldr r3, [r7, #12] + 7746 013e 0022 movs r2, #0 + 7747 0140 83F84020 strb r2, [r3, #64] +4182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +4184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +4185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** process unlock */ +4186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* REnable ADDR interrupt */ +4187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + 7748 .loc 1 4187 5 + 7749 0144 48F20201 movw r1, #32770 + 7750 0148 F868 ldr r0, [r7, #12] + 7751 014a FFF7FEFF bl I2C_Enable_IRQ +4188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; + 7752 .loc 1 4189 12 + 7753 014e 0023 movs r3, #0 + 7754 0150 00E0 b .L372 + 7755 .L369: +4190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +4192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 7756 .loc 1 4193 12 + 7757 0152 0123 movs r3, #1 + 7758 .L372: +4194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 7759 .loc 1 4195 1 + 7760 0154 1846 mov r0, r3 + 7761 0156 1837 adds r7, r7, #24 + 7762 .cfi_def_cfa_offset 8 + 7763 0158 BD46 mov sp, r7 + 7764 .cfi_def_cfa_register 13 + 7765 @ sp needed + 7766 015a 80BD pop {r7, pc} + 7767 .L377: + 7768 .align 2 + 7769 .L376: + 7770 015c 00000000 .word I2C_DMAAbort + 7771 0160 00000000 .word I2C_Slave_ISR_IT + 7772 .cfi_endproc + 7773 .LFE159: + 7775 .section .text.HAL_I2C_Slave_Seq_Receive_DMA,"ax",%progbits + 7776 .align 1 + 7777 .global HAL_I2C_Slave_Seq_Receive_DMA + 7778 .syntax unified + 7779 .thumb + 7780 .thumb_func + 7782 HAL_I2C_Slave_Seq_Receive_DMA: + 7783 .LFB160: +4196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +4198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with +4199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @note This interface allow to manage repeated start condition when a direction change during + ARM GAS /tmp/cc5G5cqz.s page 212 + + +4200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +4202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param pData Pointer to data buffer +4203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Amount of data to be sent +4204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS +4205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +4206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t S +4208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t XferOptions) +4209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 7784 .loc 1 4209 1 + 7785 .cfi_startproc + 7786 @ args = 0, pretend = 0, frame = 24 + 7787 @ frame_needed = 1, uses_anonymous_args = 0 + 7788 0000 80B5 push {r7, lr} + 7789 .cfi_def_cfa_offset 8 + 7790 .cfi_offset 7, -8 + 7791 .cfi_offset 14, -4 + 7792 0002 86B0 sub sp, sp, #24 + 7793 .cfi_def_cfa_offset 32 + 7794 0004 00AF add r7, sp, #0 + 7795 .cfi_def_cfa_register 7 + 7796 0006 F860 str r0, [r7, #12] + 7797 0008 B960 str r1, [r7, #8] + 7798 000a 3B60 str r3, [r7] + 7799 000c 1346 mov r3, r2 @ movhi + 7800 000e FB80 strh r3, [r7, #6] @ movhi +4210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Declaration of tmp to prevent undefined behavior of volatile usage */ +4211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** FlagStatus tmp; +4212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef dmaxferstatus; +4213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check the parameters */ +4215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); +4216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + 7801 .loc 1 4217 22 + 7802 0010 FB68 ldr r3, [r7, #12] + 7803 0012 93F84130 ldrb r3, [r3, #65] + 7804 0016 DBB2 uxtb r3, r3 + 7805 .loc 1 4217 30 + 7806 0018 03F02803 and r3, r3, #40 + 7807 .loc 1 4217 6 + 7808 001c 282B cmp r3, #40 + 7809 001e 40F02881 bne .L379 +4218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((pData == NULL) || (Size == 0U)) + 7810 .loc 1 4219 8 + 7811 0022 BB68 ldr r3, [r7, #8] + 7812 0024 002B cmp r3, #0 + 7813 0026 02D0 beq .L380 + 7814 .loc 1 4219 25 discriminator 1 + 7815 0028 FB88 ldrh r3, [r7, #6] + 7816 002a 002B cmp r3, #0 + 7817 002c 05D1 bne .L381 + 7818 .L380: +4220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + ARM GAS /tmp/cc5G5cqz.s page 213 + + + 7819 .loc 1 4221 23 + 7820 002e FB68 ldr r3, [r7, #12] + 7821 0030 4FF40072 mov r2, #512 + 7822 0034 5A64 str r2, [r3, #68] +4222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 7823 .loc 1 4222 15 + 7824 0036 0123 movs r3, #1 + 7825 0038 1CE1 b .L382 + 7826 .L381: +4223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ +4226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + 7827 .loc 1 4226 5 + 7828 003a 48F20201 movw r1, #32770 + 7829 003e F868 ldr r0, [r7, #12] + 7830 0040 FFF7FEFF bl I2C_Disable_IRQ +4227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +4229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); + 7831 .loc 1 4229 5 + 7832 0044 FB68 ldr r3, [r7, #12] + 7833 0046 93F84030 ldrb r3, [r3, #64] @ zero_extendqisi2 + 7834 004a 012B cmp r3, #1 + 7835 004c 01D1 bne .L383 + 7836 .loc 1 4229 5 is_stmt 0 discriminator 1 + 7837 004e 0223 movs r3, #2 + 7838 .loc 1 4229 5 + 7839 0050 10E1 b .L382 + 7840 .L383: + 7841 .loc 1 4229 5 discriminator 2 + 7842 0052 FB68 ldr r3, [r7, #12] + 7843 0054 0122 movs r2, #1 + 7844 0056 83F84020 strb r2, [r3, #64] +4230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ +4232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* and then toggle the HAL slave TX state to RX state */ +4233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + 7845 .loc 1 4233 13 is_stmt 1 + 7846 005a FB68 ldr r3, [r7, #12] + 7847 005c 93F84130 ldrb r3, [r3, #65] + 7848 0060 DBB2 uxtb r3, r3 + 7849 .loc 1 4233 8 + 7850 0062 292B cmp r3, #41 + 7851 0064 2BD1 bne .L384 +4234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable associated Interrupts */ +4236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + 7852 .loc 1 4236 7 + 7853 0066 0121 movs r1, #1 + 7854 0068 F868 ldr r0, [r7, #12] + 7855 006a FFF7FEFF bl I2C_Disable_IRQ +4237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + 7856 .loc 1 4238 16 + 7857 006e FB68 ldr r3, [r7, #12] + 7858 0070 1B68 ldr r3, [r3] + ARM GAS /tmp/cc5G5cqz.s page 214 + + + 7859 .loc 1 4238 26 + 7860 0072 1B68 ldr r3, [r3] + 7861 .loc 1 4238 32 + 7862 0074 03F48043 and r3, r3, #16384 + 7863 .loc 1 4238 10 + 7864 0078 B3F5804F cmp r3, #16384 + 7865 007c 4CD1 bne .L385 +4239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Abort DMA Xfer if any */ +4241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) + 7866 .loc 1 4241 17 + 7867 007e FB68 ldr r3, [r7, #12] + 7868 0080 9B6B ldr r3, [r3, #56] + 7869 .loc 1 4241 12 + 7870 0082 002B cmp r3, #0 + 7871 0084 48D0 beq .L385 +4242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + 7872 .loc 1 4243 15 + 7873 0086 FB68 ldr r3, [r7, #12] + 7874 0088 1B68 ldr r3, [r3] + 7875 .loc 1 4243 25 + 7876 008a 1A68 ldr r2, [r3] + 7877 .loc 1 4243 15 + 7878 008c FB68 ldr r3, [r7, #12] + 7879 008e 1B68 ldr r3, [r3] + 7880 .loc 1 4243 31 + 7881 0090 22F48042 bic r2, r2, #16384 + 7882 0094 1A60 str r2, [r3] +4244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the I2C DMA Abort callback : +4246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ +4247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + 7883 .loc 1 4247 15 + 7884 0096 FB68 ldr r3, [r7, #12] + 7885 0098 9B6B ldr r3, [r3, #56] + 7886 .loc 1 4247 43 + 7887 009a 784A ldr r2, .L393 + 7888 009c 5A63 str r2, [r3, #52] +4248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Abort DMA TX */ +4250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + 7889 .loc 1 4250 15 + 7890 009e FB68 ldr r3, [r7, #12] + 7891 00a0 9B6B ldr r3, [r3, #56] + 7892 00a2 1846 mov r0, r3 + 7893 00a4 FFF7FEFF bl HAL_DMA_Abort_IT + 7894 00a8 0346 mov r3, r0 + 7895 .loc 1 4250 14 discriminator 1 + 7896 00aa 002B cmp r3, #0 + 7897 00ac 34D0 beq .L385 +4251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call Directly XferAbortCallback function in case of error */ +4253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + 7898 .loc 1 4253 17 + 7899 00ae FB68 ldr r3, [r7, #12] + 7900 00b0 9B6B ldr r3, [r3, #56] + ARM GAS /tmp/cc5G5cqz.s page 215 + + + 7901 .loc 1 4253 25 + 7902 00b2 5B6B ldr r3, [r3, #52] + 7903 .loc 1 4253 49 + 7904 00b4 FA68 ldr r2, [r7, #12] + 7905 00b6 926B ldr r2, [r2, #56] + 7906 .loc 1 4253 13 + 7907 00b8 1046 mov r0, r2 + 7908 00ba 9847 blx r3 + 7909 .LVL4: + 7910 00bc 2CE0 b .L385 + 7911 .L384: +4254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + 7912 .loc 1 4258 18 + 7913 00be FB68 ldr r3, [r7, #12] + 7914 00c0 93F84130 ldrb r3, [r3, #65] + 7915 00c4 DBB2 uxtb r3, r3 + 7916 .loc 1 4258 13 + 7917 00c6 2A2B cmp r3, #42 + 7918 00c8 26D1 bne .L385 +4259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + 7919 .loc 1 4260 16 + 7920 00ca FB68 ldr r3, [r7, #12] + 7921 00cc 1B68 ldr r3, [r3] + 7922 .loc 1 4260 26 + 7923 00ce 1B68 ldr r3, [r3] + 7924 .loc 1 4260 32 + 7925 00d0 03F40043 and r3, r3, #32768 + 7926 .loc 1 4260 10 + 7927 00d4 B3F5004F cmp r3, #32768 + 7928 00d8 1ED1 bne .L385 +4261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + 7929 .loc 1 4262 13 + 7930 00da FB68 ldr r3, [r7, #12] + 7931 00dc 1B68 ldr r3, [r3] + 7932 .loc 1 4262 23 + 7933 00de 1A68 ldr r2, [r3] + 7934 .loc 1 4262 13 + 7935 00e0 FB68 ldr r3, [r7, #12] + 7936 00e2 1B68 ldr r3, [r3] + 7937 .loc 1 4262 29 + 7938 00e4 22F40042 bic r2, r2, #32768 + 7939 00e8 1A60 str r2, [r3] +4263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Abort DMA Xfer if any */ +4265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) + 7940 .loc 1 4265 17 + 7941 00ea FB68 ldr r3, [r7, #12] + 7942 00ec DB6B ldr r3, [r3, #60] + 7943 .loc 1 4265 12 + 7944 00ee 002B cmp r3, #0 + 7945 00f0 12D0 beq .L385 + ARM GAS /tmp/cc5G5cqz.s page 216 + + +4266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the I2C DMA Abort callback : +4268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ +4269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + 7946 .loc 1 4269 15 + 7947 00f2 FB68 ldr r3, [r7, #12] + 7948 00f4 DB6B ldr r3, [r3, #60] + 7949 .loc 1 4269 43 + 7950 00f6 614A ldr r2, .L393 + 7951 00f8 5A63 str r2, [r3, #52] +4270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Abort DMA RX */ +4272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + 7952 .loc 1 4272 15 + 7953 00fa FB68 ldr r3, [r7, #12] + 7954 00fc DB6B ldr r3, [r3, #60] + 7955 00fe 1846 mov r0, r3 + 7956 0100 FFF7FEFF bl HAL_DMA_Abort_IT + 7957 0104 0346 mov r3, r0 + 7958 .loc 1 4272 14 discriminator 1 + 7959 0106 002B cmp r3, #0 + 7960 0108 06D0 beq .L385 +4273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call Directly XferAbortCallback function in case of error */ +4275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + 7961 .loc 1 4275 17 + 7962 010a FB68 ldr r3, [r7, #12] + 7963 010c DB6B ldr r3, [r3, #60] + 7964 .loc 1 4275 25 + 7965 010e 5B6B ldr r3, [r3, #52] + 7966 .loc 1 4275 49 + 7967 0110 FA68 ldr r2, [r7, #12] + 7968 0112 D26B ldr r2, [r2, #60] + 7969 .loc 1 4275 13 + 7970 0114 1046 mov r0, r2 + 7971 0116 9847 blx r3 + 7972 .LVL5: + 7973 .L385: +4276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +4281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Nothing to do */ +4283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; + 7974 .loc 1 4285 21 + 7975 0118 FB68 ldr r3, [r7, #12] + 7976 011a 2A22 movs r2, #42 + 7977 011c 83F84120 strb r2, [r3, #65] +4286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_SLAVE; + 7978 .loc 1 4286 21 + 7979 0120 FB68 ldr r3, [r7, #12] + 7980 0122 2022 movs r2, #32 + 7981 0124 83F84220 strb r2, [r3, #66] + ARM GAS /tmp/cc5G5cqz.s page 217 + + +4287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 7982 .loc 1 4287 21 + 7983 0128 FB68 ldr r3, [r7, #12] + 7984 012a 0022 movs r2, #0 + 7985 012c 5A64 str r2, [r3, #68] +4288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable Address Acknowledge */ +4290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + 7986 .loc 1 4290 9 + 7987 012e FB68 ldr r3, [r7, #12] + 7988 0130 1B68 ldr r3, [r3] + 7989 .loc 1 4290 19 + 7990 0132 5A68 ldr r2, [r3, #4] + 7991 .loc 1 4290 9 + 7992 0134 FB68 ldr r3, [r7, #12] + 7993 0136 1B68 ldr r3, [r3] + 7994 .loc 1 4290 25 + 7995 0138 22F40042 bic r2, r2, #32768 + 7996 013c 5A60 str r2, [r3, #4] +4291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare transfer parameters */ +4293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr = pData; + 7997 .loc 1 4293 23 + 7998 013e FB68 ldr r3, [r7, #12] + 7999 0140 BA68 ldr r2, [r7, #8] + 8000 0142 5A62 str r2, [r3, #36] +4294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = Size; + 8001 .loc 1 4294 23 + 8002 0144 FB68 ldr r3, [r7, #12] + 8003 0146 FA88 ldrh r2, [r7, #6] @ movhi + 8004 0148 5A85 strh r2, [r3, #42] @ movhi +4295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 8005 .loc 1 4295 29 + 8006 014a FB68 ldr r3, [r7, #12] + 8007 014c 5B8D ldrh r3, [r3, #42] @ movhi + 8008 014e 9AB2 uxth r2, r3 + 8009 .loc 1 4295 23 + 8010 0150 FB68 ldr r3, [r7, #12] + 8011 0152 1A85 strh r2, [r3, #40] @ movhi +4296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = XferOptions; + 8012 .loc 1 4296 23 + 8013 0154 FB68 ldr r3, [r7, #12] + 8014 0156 3A68 ldr r2, [r7] + 8015 0158 DA62 str r2, [r3, #44] +4297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_DMA; + 8016 .loc 1 4297 23 + 8017 015a FB68 ldr r3, [r7, #12] + 8018 015c 484A ldr r2, .L393+4 + 8019 015e 5A63 str r2, [r3, #52] +4298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) + 8020 .loc 1 4299 13 + 8021 0160 FB68 ldr r3, [r7, #12] + 8022 0162 DB6B ldr r3, [r3, #60] + 8023 .loc 1 4299 8 + 8024 0164 002B cmp r3, #0 + 8025 0166 20D0 beq .L386 + ARM GAS /tmp/cc5G5cqz.s page 218 + + +4300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the I2C DMA transfer complete callback */ +4302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; + 8026 .loc 1 4302 11 + 8027 0168 FB68 ldr r3, [r7, #12] + 8028 016a DB6B ldr r3, [r3, #60] + 8029 .loc 1 4302 38 + 8030 016c 454A ldr r2, .L393+8 + 8031 016e 9A62 str r2, [r3, #40] +4303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the DMA error callback */ +4305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + 8032 .loc 1 4305 11 + 8033 0170 FB68 ldr r3, [r7, #12] + 8034 0172 DB6B ldr r3, [r3, #60] + 8035 .loc 1 4305 39 + 8036 0174 444A ldr r2, .L393+12 + 8037 0176 1A63 str r2, [r3, #48] +4306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the unused DMA callbacks to NULL */ +4308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferHalfCpltCallback = NULL; + 8038 .loc 1 4308 11 + 8039 0178 FB68 ldr r3, [r7, #12] + 8040 017a DB6B ldr r3, [r3, #60] + 8041 .loc 1 4308 42 + 8042 017c 0022 movs r2, #0 + 8043 017e DA62 str r2, [r3, #44] +4309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 8044 .loc 1 4309 11 + 8045 0180 FB68 ldr r3, [r7, #12] + 8046 0182 DB6B ldr r3, [r3, #60] + 8047 .loc 1 4309 39 + 8048 0184 0022 movs r2, #0 + 8049 0186 5A63 str r2, [r3, #52] +4310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable the DMA channel */ +4312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, + 8050 .loc 1 4312 23 + 8051 0188 FB68 ldr r3, [r7, #12] + 8052 018a D86B ldr r0, [r3, #60] + 8053 .loc 1 4312 69 + 8054 018c FB68 ldr r3, [r7, #12] + 8055 018e 1B68 ldr r3, [r3] + 8056 .loc 1 4312 64 + 8057 0190 2433 adds r3, r3, #36 + 8058 .loc 1 4312 23 + 8059 0192 1946 mov r1, r3 + 8060 0194 BA68 ldr r2, [r7, #8] +4313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (uint32_t)pData, hi2c->XferSize); + 8061 .loc 1 4313 61 + 8062 0196 FB68 ldr r3, [r7, #12] + 8063 0198 1B8D ldrh r3, [r3, #40] +4312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (uint32_t)pData, hi2c->XferSize); + 8064 .loc 1 4312 23 + 8065 019a FFF7FEFF bl HAL_DMA_Start_IT + 8066 019e 0346 mov r3, r0 + 8067 01a0 FB75 strb r3, [r7, #23] + ARM GAS /tmp/cc5G5cqz.s page 219 + + +4314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +4316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C state */ +4318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +4319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +4320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C error code */ +4322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; +4323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +4325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +4326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +4328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (dmaxferstatus == HAL_OK) + 8068 .loc 1 4330 8 + 8069 01a2 FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 8070 01a4 002B cmp r3, #0 + 8071 01a6 36D1 bne .L388 + 8072 01a8 13E0 b .L391 + 8073 .L386: +4318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 8074 .loc 1 4318 23 + 8075 01aa FB68 ldr r3, [r7, #12] + 8076 01ac 2822 movs r2, #40 + 8077 01ae 83F84120 strb r2, [r3, #65] +4319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8078 .loc 1 4319 23 + 8079 01b2 FB68 ldr r3, [r7, #12] + 8080 01b4 0022 movs r2, #0 + 8081 01b6 83F84220 strb r2, [r3, #66] +4322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8082 .loc 1 4322 11 + 8083 01ba FB68 ldr r3, [r7, #12] + 8084 01bc 5B6C ldr r3, [r3, #68] +4322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8085 .loc 1 4322 23 + 8086 01be 43F08002 orr r2, r3, #128 + 8087 01c2 FB68 ldr r3, [r7, #12] + 8088 01c4 5A64 str r2, [r3, #68] +4325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8089 .loc 1 4325 7 + 8090 01c6 FB68 ldr r3, [r7, #12] + 8091 01c8 0022 movs r2, #0 + 8092 01ca 83F84020 strb r2, [r3, #64] +4327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8093 .loc 1 4327 14 + 8094 01ce 0123 movs r3, #1 + 8095 01d0 50E0 b .L382 + 8096 .L391: +4331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update XferCount value */ +4333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount -= hi2c->XferSize; + 8097 .loc 1 4333 11 + 8098 01d2 FB68 ldr r3, [r7, #12] + ARM GAS /tmp/cc5G5cqz.s page 220 + + + 8099 01d4 5B8D ldrh r3, [r3, #42] @ movhi + 8100 01d6 9AB2 uxth r2, r3 + 8101 .loc 1 4333 30 + 8102 01d8 FB68 ldr r3, [r7, #12] + 8103 01da 1B8D ldrh r3, [r3, #40] + 8104 .loc 1 4333 23 + 8105 01dc D31A subs r3, r2, r3 + 8106 01de 9AB2 uxth r2, r3 + 8107 01e0 FB68 ldr r3, [r7, #12] + 8108 01e2 5A85 strh r2, [r3, #42] @ movhi +4334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Reset XferSize */ +4336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = 0; + 8109 .loc 1 4336 22 + 8110 01e4 FB68 ldr r3, [r7, #12] + 8111 01e6 0022 movs r2, #0 + 8112 01e8 1A85 strh r2, [r3, #40] @ movhi +4337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +4339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C state */ +4341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +4342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +4343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update I2C error code */ +4345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; +4346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +4348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +4349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; +4351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + 8113 .loc 1 4353 11 + 8114 01ea FB68 ldr r3, [r7, #12] + 8115 01ec 1B68 ldr r3, [r3] + 8116 01ee 9B69 ldr r3, [r3, #24] + 8117 01f0 03F00803 and r3, r3, #8 + 8118 01f4 082B cmp r3, #8 + 8119 01f6 0CBF ite eq + 8120 01f8 0123 moveq r3, #1 + 8121 01fa 0023 movne r3, #0 + 8122 01fc DBB2 uxtb r3, r3 + 8123 .loc 1 4353 9 + 8124 01fe BB75 strb r3, [r7, #22] +4354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET)) + 8125 .loc 1 4354 10 + 8126 0200 FB68 ldr r3, [r7, #12] + 8127 0202 1B68 ldr r3, [r3] + 8128 0204 9B69 ldr r3, [r3, #24] + 8129 0206 1B0C lsrs r3, r3, #16 + 8130 0208 DBB2 uxtb r3, r3 + 8131 020a 03F00103 and r3, r3, #1 + 8132 020e DBB2 uxtb r3, r3 + 8133 .loc 1 4354 8 + 8134 0210 002B cmp r3, #0 + ARM GAS /tmp/cc5G5cqz.s page 221 + + + 8135 0212 1BD1 bne .L390 + 8136 0214 13E0 b .L392 + 8137 .L388: +4341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 8138 .loc 1 4341 23 + 8139 0216 FB68 ldr r3, [r7, #12] + 8140 0218 2822 movs r2, #40 + 8141 021a 83F84120 strb r2, [r3, #65] +4342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8142 .loc 1 4342 23 + 8143 021e FB68 ldr r3, [r7, #12] + 8144 0220 0022 movs r2, #0 + 8145 0222 83F84220 strb r2, [r3, #66] +4345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8146 .loc 1 4345 11 + 8147 0226 FB68 ldr r3, [r7, #12] + 8148 0228 5B6C ldr r3, [r3, #68] +4345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8149 .loc 1 4345 23 + 8150 022a 43F01002 orr r2, r3, #16 + 8151 022e FB68 ldr r3, [r7, #12] + 8152 0230 5A64 str r2, [r3, #68] +4348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 8153 .loc 1 4348 7 + 8154 0232 FB68 ldr r3, [r7, #12] + 8155 0234 0022 movs r2, #0 + 8156 0236 83F84020 strb r2, [r3, #64] +4350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8157 .loc 1 4350 14 + 8158 023a 0123 movs r3, #1 + 8159 023c 1AE0 b .L382 + 8160 .L392: + 8161 .loc 1 4354 55 discriminator 1 + 8162 023e BB7D ldrb r3, [r7, #22] @ zero_extendqisi2 + 8163 0240 002B cmp r3, #0 + 8164 0242 03D0 beq .L390 +4355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear ADDR flag after prepare the transfer parameters */ +4357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* This action will generate an acknowledge to the Master */ +4358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + 8165 .loc 1 4358 7 + 8166 0244 FB68 ldr r3, [r7, #12] + 8167 0246 1B68 ldr r3, [r3] + 8168 0248 0822 movs r2, #8 + 8169 024a DA61 str r2, [r3, #28] + 8170 .L390: +4359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +4362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 8171 .loc 1 4362 5 + 8172 024c FB68 ldr r3, [r7, #12] + 8173 024e 0022 movs r2, #0 + 8174 0250 83F84020 strb r2, [r3, #64] +4363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable DMA Request */ +4365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + ARM GAS /tmp/cc5G5cqz.s page 222 + + + 8175 .loc 1 4365 9 + 8176 0254 FB68 ldr r3, [r7, #12] + 8177 0256 1B68 ldr r3, [r3] + 8178 .loc 1 4365 19 + 8179 0258 1A68 ldr r2, [r3] + 8180 .loc 1 4365 9 + 8181 025a FB68 ldr r3, [r7, #12] + 8182 025c 1B68 ldr r3, [r3] + 8183 .loc 1 4365 25 + 8184 025e 42F40042 orr r2, r2, #32768 + 8185 0262 1A60 str r2, [r3] +4366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +4368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +4369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** process unlock */ +4370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* REnable ADDR interrupt */ +4371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + 8186 .loc 1 4371 5 + 8187 0264 48F20201 movw r1, #32770 + 8188 0268 F868 ldr r0, [r7, #12] + 8189 026a FFF7FEFF bl I2C_Enable_IRQ +4372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; + 8190 .loc 1 4373 12 + 8191 026e 0023 movs r3, #0 + 8192 0270 00E0 b .L382 + 8193 .L379: +4374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +4376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 8194 .loc 1 4377 12 + 8195 0272 0123 movs r3, #1 + 8196 .L382: +4378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8197 .loc 1 4379 1 + 8198 0274 1846 mov r0, r3 + 8199 0276 1837 adds r7, r7, #24 + 8200 .cfi_def_cfa_offset 8 + 8201 0278 BD46 mov sp, r7 + 8202 .cfi_def_cfa_register 13 + 8203 @ sp needed + 8204 027a 80BD pop {r7, pc} + 8205 .L394: + 8206 .align 2 + 8207 .L393: + 8208 027c 00000000 .word I2C_DMAAbort + 8209 0280 00000000 .word I2C_Slave_ISR_DMA + 8210 0284 00000000 .word I2C_DMASlaveReceiveCplt + 8211 0288 00000000 .word I2C_DMAError + 8212 .cfi_endproc + 8213 .LFE160: + 8215 .section .text.HAL_I2C_EnableListen_IT,"ax",%progbits + 8216 .align 1 + 8217 .global HAL_I2C_EnableListen_IT + 8218 .syntax unified + ARM GAS /tmp/cc5G5cqz.s page 223 + + + 8219 .thumb + 8220 .thumb_func + 8222 HAL_I2C_EnableListen_IT: + 8223 .LFB161: +4380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +4382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Enable the Address listen mode with Interrupt. +4383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +4385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +4386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) +4388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8224 .loc 1 4388 1 + 8225 .cfi_startproc + 8226 @ args = 0, pretend = 0, frame = 8 + 8227 @ frame_needed = 1, uses_anonymous_args = 0 + 8228 0000 80B5 push {r7, lr} + 8229 .cfi_def_cfa_offset 8 + 8230 .cfi_offset 7, -8 + 8231 .cfi_offset 14, -4 + 8232 0002 82B0 sub sp, sp, #8 + 8233 .cfi_def_cfa_offset 16 + 8234 0004 00AF add r7, sp, #0 + 8235 .cfi_def_cfa_register 7 + 8236 0006 7860 str r0, [r7, #4] +4389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 8237 .loc 1 4389 11 + 8238 0008 7B68 ldr r3, [r7, #4] + 8239 000a 93F84130 ldrb r3, [r3, #65] + 8240 000e DBB2 uxtb r3, r3 + 8241 .loc 1 4389 6 + 8242 0010 202B cmp r3, #32 + 8243 0012 0DD1 bne .L396 +4390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; + 8244 .loc 1 4391 17 + 8245 0014 7B68 ldr r3, [r7, #4] + 8246 0016 2822 movs r2, #40 + 8247 0018 83F84120 strb r2, [r3, #65] +4392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 8248 .loc 1 4392 19 + 8249 001c 7B68 ldr r3, [r7, #4] + 8250 001e 074A ldr r2, .L398 + 8251 0020 5A63 str r2, [r3, #52] +4393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable the Address Match interrupt */ +4395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + 8252 .loc 1 4395 5 + 8253 0022 4FF40041 mov r1, #32768 + 8254 0026 7868 ldr r0, [r7, #4] + 8255 0028 FFF7FEFF bl I2C_Enable_IRQ +4396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; + 8256 .loc 1 4397 12 + 8257 002c 0023 movs r3, #0 + 8258 002e 00E0 b .L397 + ARM GAS /tmp/cc5G5cqz.s page 224 + + + 8259 .L396: +4398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +4400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; + 8260 .loc 1 4401 12 + 8261 0030 0223 movs r3, #2 + 8262 .L397: +4402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8263 .loc 1 4403 1 + 8264 0032 1846 mov r0, r3 + 8265 0034 0837 adds r7, r7, #8 + 8266 .cfi_def_cfa_offset 8 + 8267 0036 BD46 mov sp, r7 + 8268 .cfi_def_cfa_register 13 + 8269 @ sp needed + 8270 0038 80BD pop {r7, pc} + 8271 .L399: + 8272 003a 00BF .align 2 + 8273 .L398: + 8274 003c 00000000 .word I2C_Slave_ISR_IT + 8275 .cfi_endproc + 8276 .LFE161: + 8278 .section .text.HAL_I2C_DisableListen_IT,"ax",%progbits + 8279 .align 1 + 8280 .global HAL_I2C_DisableListen_IT + 8281 .syntax unified + 8282 .thumb + 8283 .thumb_func + 8285 HAL_I2C_DisableListen_IT: + 8286 .LFB162: +4404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +4406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Disable the Address listen mode with Interrupt. +4407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C +4409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +4410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) +4412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8287 .loc 1 4412 1 + 8288 .cfi_startproc + 8289 @ args = 0, pretend = 0, frame = 16 + 8290 @ frame_needed = 1, uses_anonymous_args = 0 + 8291 0000 80B5 push {r7, lr} + 8292 .cfi_def_cfa_offset 8 + 8293 .cfi_offset 7, -8 + 8294 .cfi_offset 14, -4 + 8295 0002 84B0 sub sp, sp, #16 + 8296 .cfi_def_cfa_offset 24 + 8297 0004 00AF add r7, sp, #0 + 8298 .cfi_def_cfa_register 7 + 8299 0006 7860 str r0, [r7, #4] +4413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Declaration of tmp to prevent undefined behavior of volatile usage */ +4414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmp; +4415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/cc5G5cqz.s page 225 + + +4416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Address listen mode only if a transfer is not ongoing */ +4417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_LISTEN) + 8300 .loc 1 4417 11 + 8301 0008 7B68 ldr r3, [r7, #4] + 8302 000a 93F84130 ldrb r3, [r3, #65] + 8303 000e DBB2 uxtb r3, r3 + 8304 .loc 1 4417 6 + 8305 0010 282B cmp r3, #40 + 8306 0012 21D1 bne .L401 +4418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; + 8307 .loc 1 4419 26 + 8308 0014 7B68 ldr r3, [r7, #4] + 8309 0016 93F84130 ldrb r3, [r3, #65] + 8310 001a DBB2 uxtb r3, r3 + 8311 .loc 1 4419 9 + 8312 001c 03F00303 and r3, r3, #3 + 8313 0020 FB60 str r3, [r7, #12] +4420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); + 8314 .loc 1 4420 48 + 8315 0022 7B68 ldr r3, [r7, #4] + 8316 0024 93F84230 ldrb r3, [r3, #66] + 8317 0028 DBB2 uxtb r3, r3 + 8318 .loc 1 4420 33 + 8319 002a 1A46 mov r2, r3 + 8320 .loc 1 4420 31 + 8321 002c FB68 ldr r3, [r7, #12] + 8322 002e 1A43 orrs r2, r2, r3 + 8323 .loc 1 4420 25 + 8324 0030 7B68 ldr r3, [r7, #4] + 8325 0032 1A63 str r2, [r3, #48] +4421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 8326 .loc 1 4421 17 + 8327 0034 7B68 ldr r3, [r7, #4] + 8328 0036 2022 movs r2, #32 + 8329 0038 83F84120 strb r2, [r3, #65] +4422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 8330 .loc 1 4422 16 + 8331 003c 7B68 ldr r3, [r7, #4] + 8332 003e 0022 movs r2, #0 + 8333 0040 83F84220 strb r2, [r3, #66] +4423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = NULL; + 8334 .loc 1 4423 19 + 8335 0044 7B68 ldr r3, [r7, #4] + 8336 0046 0022 movs r2, #0 + 8337 0048 5A63 str r2, [r3, #52] +4424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable the Address Match interrupt */ +4426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + 8338 .loc 1 4426 5 + 8339 004a 4FF40041 mov r1, #32768 + 8340 004e 7868 ldr r0, [r7, #4] + 8341 0050 FFF7FEFF bl I2C_Disable_IRQ +4427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; + 8342 .loc 1 4428 12 + 8343 0054 0023 movs r3, #0 + ARM GAS /tmp/cc5G5cqz.s page 226 + + + 8344 0056 00E0 b .L402 + 8345 .L401: +4429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +4431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_BUSY; + 8346 .loc 1 4432 12 + 8347 0058 0223 movs r3, #2 + 8348 .L402: +4433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8349 .loc 1 4434 1 + 8350 005a 1846 mov r0, r3 + 8351 005c 1037 adds r7, r7, #16 + 8352 .cfi_def_cfa_offset 8 + 8353 005e BD46 mov sp, r7 + 8354 .cfi_def_cfa_register 13 + 8355 @ sp needed + 8356 0060 80BD pop {r7, pc} + 8357 .cfi_endproc + 8358 .LFE162: + 8360 .section .text.HAL_I2C_Master_Abort_IT,"ax",%progbits + 8361 .align 1 + 8362 .global HAL_I2C_Master_Abort_IT + 8363 .syntax unified + 8364 .thumb + 8365 .thumb_func + 8367 HAL_I2C_Master_Abort_IT: + 8368 .LFB163: +4435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +4437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Abort a master I2C IT or DMA process communication with Interrupt. +4438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +4440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +4441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +4442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +4443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) +4445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8369 .loc 1 4445 1 + 8370 .cfi_startproc + 8371 @ args = 0, pretend = 0, frame = 8 + 8372 @ frame_needed = 1, uses_anonymous_args = 0 + 8373 0000 80B5 push {r7, lr} + 8374 .cfi_def_cfa_offset 8 + 8375 .cfi_offset 7, -8 + 8376 .cfi_offset 14, -4 + 8377 0002 84B0 sub sp, sp, #16 + 8378 .cfi_def_cfa_offset 24 + 8379 0004 02AF add r7, sp, #8 + 8380 .cfi_def_cfa 7, 16 + 8381 0006 7860 str r0, [r7, #4] + 8382 0008 0B46 mov r3, r1 + 8383 000a 7B80 strh r3, [r7, #2] @ movhi +4446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->Mode == HAL_I2C_MODE_MASTER) + 8384 .loc 1 4446 11 + ARM GAS /tmp/cc5G5cqz.s page 227 + + + 8385 000c 7B68 ldr r3, [r7, #4] + 8386 000e 93F84230 ldrb r3, [r3, #66] + 8387 0012 DBB2 uxtb r3, r3 + 8388 .loc 1 4446 6 + 8389 0014 102B cmp r3, #16 + 8390 0016 3CD1 bne .L404 +4447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +4449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); + 8391 .loc 1 4449 5 + 8392 0018 7B68 ldr r3, [r7, #4] + 8393 001a 93F84030 ldrb r3, [r3, #64] @ zero_extendqisi2 + 8394 001e 012B cmp r3, #1 + 8395 0020 01D1 bne .L405 + 8396 .loc 1 4449 5 is_stmt 0 discriminator 1 + 8397 0022 0223 movs r3, #2 + 8398 .loc 1 4449 5 + 8399 0024 36E0 b .L406 + 8400 .L405: + 8401 .loc 1 4449 5 discriminator 2 + 8402 0026 7B68 ldr r3, [r7, #4] + 8403 0028 0122 movs r2, #1 + 8404 002a 83F84020 strb r2, [r3, #64] +4450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Interrupts and Store Previous state */ +4452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + 8405 .loc 1 4452 13 is_stmt 1 + 8406 002e 7B68 ldr r3, [r7, #4] + 8407 0030 93F84130 ldrb r3, [r3, #65] + 8408 0034 DBB2 uxtb r3, r3 + 8409 .loc 1 4452 8 + 8410 0036 212B cmp r3, #33 + 8411 0038 07D1 bne .L407 +4453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + 8412 .loc 1 4454 7 + 8413 003a 0121 movs r1, #1 + 8414 003c 7868 ldr r0, [r7, #4] + 8415 003e FFF7FEFF bl I2C_Disable_IRQ +4455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + 8416 .loc 1 4455 27 + 8417 0042 7B68 ldr r3, [r7, #4] + 8418 0044 1122 movs r2, #17 + 8419 0046 1A63 str r2, [r3, #48] + 8420 0048 0CE0 b .L408 + 8421 .L407: +4456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + 8422 .loc 1 4457 18 + 8423 004a 7B68 ldr r3, [r7, #4] + 8424 004c 93F84130 ldrb r3, [r3, #65] + 8425 0050 DBB2 uxtb r3, r3 + 8426 .loc 1 4457 13 + 8427 0052 222B cmp r3, #34 + 8428 0054 06D1 bne .L408 +4458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + ARM GAS /tmp/cc5G5cqz.s page 228 + + + 8429 .loc 1 4459 7 + 8430 0056 0221 movs r1, #2 + 8431 0058 7868 ldr r0, [r7, #4] + 8432 005a FFF7FEFF bl I2C_Disable_IRQ +4460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + 8433 .loc 1 4460 27 + 8434 005e 7B68 ldr r3, [r7, #4] + 8435 0060 1222 movs r2, #18 + 8436 0062 1A63 str r2, [r3, #48] + 8437 .L408: +4461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +4463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Do nothing */ +4465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set State at HAL_I2C_STATE_ABORT */ +4468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_ABORT; + 8438 .loc 1 4468 17 + 8439 0064 7B68 ldr r3, [r7, #4] + 8440 0066 6022 movs r2, #96 + 8441 0068 83F84120 strb r2, [r3, #65] +4469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */ +4471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfe +4472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP); + 8442 .loc 1 4472 5 + 8443 006c 7988 ldrh r1, [r7, #2] + 8444 006e 0B4B ldr r3, .L409 + 8445 0070 0093 str r3, [sp] + 8446 0072 4FF00073 mov r3, #33554432 + 8447 0076 0122 movs r2, #1 + 8448 0078 7868 ldr r0, [r7, #4] + 8449 007a FFF7FEFF bl I2C_TransferConfig +4473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +4475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 8450 .loc 1 4475 5 + 8451 007e 7B68 ldr r3, [r7, #4] + 8452 0080 0022 movs r2, #0 + 8453 0082 83F84020 strb r2, [r3, #64] +4476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Note : The I2C interrupts must be enabled after unlocking current process +4478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** to avoid the risk of I2C interrupt handle execution before current +4479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** process unlock */ +4480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + 8454 .loc 1 4480 5 + 8455 0086 2021 movs r1, #32 + 8456 0088 7868 ldr r0, [r7, #4] + 8457 008a FFF7FEFF bl I2C_Enable_IRQ +4481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; + 8458 .loc 1 4482 12 + 8459 008e 0023 movs r3, #0 + 8460 0090 00E0 b .L406 + 8461 .L404: +4483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/cc5G5cqz.s page 229 + + +4484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +4485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wrong usage of abort function */ +4487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* This function should be used only in case of abort monitored by master device */ +4488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 8462 .loc 1 4488 12 + 8463 0092 0123 movs r3, #1 + 8464 .L406: +4489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8465 .loc 1 4490 1 + 8466 0094 1846 mov r0, r3 + 8467 0096 0837 adds r7, r7, #8 + 8468 .cfi_def_cfa_offset 8 + 8469 0098 BD46 mov sp, r7 + 8470 .cfi_def_cfa_register 13 + 8471 @ sp needed + 8472 009a 80BD pop {r7, pc} + 8473 .L410: + 8474 .align 2 + 8475 .L409: + 8476 009c 00400080 .word -2147467264 + 8477 .cfi_endproc + 8478 .LFE163: + 8480 .section .text.HAL_I2C_EV_IRQHandler,"ax",%progbits + 8481 .align 1 + 8482 .global HAL_I2C_EV_IRQHandler + 8483 .syntax unified + 8484 .thumb + 8485 .thumb_func + 8487 HAL_I2C_EV_IRQHandler: + 8488 .LFB164: +4491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +4493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @} +4494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks +4497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @{ +4498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +4501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief This function handles I2C event interrupt request. +4502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +4504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +4505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /* Derogation MISRAC2012-Rule-8.13 */ +4507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8489 .loc 1 4507 1 + 8490 .cfi_startproc + 8491 @ args = 0, pretend = 0, frame = 16 + 8492 @ frame_needed = 1, uses_anonymous_args = 0 + 8493 0000 80B5 push {r7, lr} + 8494 .cfi_def_cfa_offset 8 + 8495 .cfi_offset 7, -8 + 8496 .cfi_offset 14, -4 + ARM GAS /tmp/cc5G5cqz.s page 230 + + + 8497 0002 84B0 sub sp, sp, #16 + 8498 .cfi_def_cfa_offset 24 + 8499 0004 00AF add r7, sp, #0 + 8500 .cfi_def_cfa_register 7 + 8501 0006 7860 str r0, [r7, #4] +4508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Get current IT Flags and IT sources value */ +4509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t itflags = READ_REG(hi2c->Instance->ISR); + 8502 .loc 1 4509 24 + 8503 0008 7B68 ldr r3, [r7, #4] + 8504 000a 1B68 ldr r3, [r3] + 8505 .loc 1 4509 12 + 8506 000c 9B69 ldr r3, [r3, #24] + 8507 000e FB60 str r3, [r7, #12] +4510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t itsources = READ_REG(hi2c->Instance->CR1); + 8508 .loc 1 4510 24 + 8509 0010 7B68 ldr r3, [r7, #4] + 8510 0012 1B68 ldr r3, [r3] + 8511 .loc 1 4510 12 + 8512 0014 1B68 ldr r3, [r3] + 8513 0016 BB60 str r3, [r7, #8] +4511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* I2C events treatment -------------------------------------*/ +4513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferISR != NULL) + 8514 .loc 1 4513 11 + 8515 0018 7B68 ldr r3, [r7, #4] + 8516 001a 5B6B ldr r3, [r3, #52] + 8517 .loc 1 4513 6 + 8518 001c 002B cmp r3, #0 + 8519 001e 05D0 beq .L413 +4514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR(hi2c, itflags, itsources); + 8520 .loc 1 4515 9 + 8521 0020 7B68 ldr r3, [r7, #4] + 8522 0022 5B6B ldr r3, [r3, #52] + 8523 .loc 1 4515 5 + 8524 0024 BA68 ldr r2, [r7, #8] + 8525 0026 F968 ldr r1, [r7, #12] + 8526 0028 7868 ldr r0, [r7, #4] + 8527 002a 9847 blx r3 + 8528 .LVL6: + 8529 .L413: +4516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8530 .loc 1 4517 1 + 8531 002c 00BF nop + 8532 002e 1037 adds r7, r7, #16 + 8533 .cfi_def_cfa_offset 8 + 8534 0030 BD46 mov sp, r7 + 8535 .cfi_def_cfa_register 13 + 8536 @ sp needed + 8537 0032 80BD pop {r7, pc} + 8538 .cfi_endproc + 8539 .LFE164: + 8541 .section .text.HAL_I2C_ER_IRQHandler,"ax",%progbits + 8542 .align 1 + 8543 .global HAL_I2C_ER_IRQHandler + 8544 .syntax unified + ARM GAS /tmp/cc5G5cqz.s page 231 + + + 8545 .thumb + 8546 .thumb_func + 8548 HAL_I2C_ER_IRQHandler: + 8549 .LFB165: +4518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +4520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief This function handles I2C error interrupt request. +4521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +4523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +4524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) +4526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8550 .loc 1 4526 1 + 8551 .cfi_startproc + 8552 @ args = 0, pretend = 0, frame = 24 + 8553 @ frame_needed = 1, uses_anonymous_args = 0 + 8554 0000 80B5 push {r7, lr} + 8555 .cfi_def_cfa_offset 8 + 8556 .cfi_offset 7, -8 + 8557 .cfi_offset 14, -4 + 8558 0002 86B0 sub sp, sp, #24 + 8559 .cfi_def_cfa_offset 32 + 8560 0004 00AF add r7, sp, #0 + 8561 .cfi_def_cfa_register 7 + 8562 0006 7860 str r0, [r7, #4] +4527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t itflags = READ_REG(hi2c->Instance->ISR); + 8563 .loc 1 4527 24 + 8564 0008 7B68 ldr r3, [r7, #4] + 8565 000a 1B68 ldr r3, [r3] + 8566 .loc 1 4527 12 + 8567 000c 9B69 ldr r3, [r3, #24] + 8568 000e 7B61 str r3, [r7, #20] +4528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t itsources = READ_REG(hi2c->Instance->CR1); + 8569 .loc 1 4528 24 + 8570 0010 7B68 ldr r3, [r7, #4] + 8571 0012 1B68 ldr r3, [r3] + 8572 .loc 1 4528 12 + 8573 0014 1B68 ldr r3, [r3] + 8574 0016 3B61 str r3, [r7, #16] +4529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmperror; +4530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* I2C Bus error interrupt occurred ------------------------------------*/ +4532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \ + 8575 .loc 1 4532 8 + 8576 0018 7B69 ldr r3, [r7, #20] + 8577 001a 1B0A lsrs r3, r3, #8 + 8578 001c 03F00103 and r3, r3, #1 + 8579 .loc 1 4532 6 + 8580 0020 002B cmp r3, #0 + 8581 0022 10D0 beq .L415 +4533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + 8582 .loc 1 4533 8 + 8583 0024 3B69 ldr r3, [r7, #16] + 8584 0026 DB09 lsrs r3, r3, #7 + 8585 0028 03F00103 and r3, r3, #1 +4532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + ARM GAS /tmp/cc5G5cqz.s page 232 + + + 8586 .loc 1 4532 57 discriminator 1 + 8587 002c 002B cmp r3, #0 + 8588 002e 0AD0 beq .L415 +4534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; + 8589 .loc 1 4535 9 + 8590 0030 7B68 ldr r3, [r7, #4] + 8591 0032 5B6C ldr r3, [r3, #68] + 8592 .loc 1 4535 21 + 8593 0034 43F00102 orr r2, r3, #1 + 8594 0038 7B68 ldr r3, [r7, #4] + 8595 003a 5A64 str r2, [r3, #68] +4536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear BERR flag */ +4538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); + 8596 .loc 1 4538 5 + 8597 003c 7B68 ldr r3, [r7, #4] + 8598 003e 1B68 ldr r3, [r3] + 8599 0040 4FF48072 mov r2, #256 + 8600 0044 DA61 str r2, [r3, #28] + 8601 .L415: +4539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ +4542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \ + 8602 .loc 1 4542 8 + 8603 0046 7B69 ldr r3, [r7, #20] + 8604 0048 9B0A lsrs r3, r3, #10 + 8605 004a 03F00103 and r3, r3, #1 + 8606 .loc 1 4542 6 + 8607 004e 002B cmp r3, #0 + 8608 0050 10D0 beq .L416 +4543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + 8609 .loc 1 4543 8 + 8610 0052 3B69 ldr r3, [r7, #16] + 8611 0054 DB09 lsrs r3, r3, #7 + 8612 0056 03F00103 and r3, r3, #1 +4542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + 8613 .loc 1 4542 56 discriminator 1 + 8614 005a 002B cmp r3, #0 + 8615 005c 0AD0 beq .L416 +4544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; + 8616 .loc 1 4545 9 + 8617 005e 7B68 ldr r3, [r7, #4] + 8618 0060 5B6C ldr r3, [r3, #68] + 8619 .loc 1 4545 21 + 8620 0062 43F00802 orr r2, r3, #8 + 8621 0066 7B68 ldr r3, [r7, #4] + 8622 0068 5A64 str r2, [r3, #68] +4546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear OVR flag */ +4548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); + 8623 .loc 1 4548 5 + 8624 006a 7B68 ldr r3, [r7, #4] + 8625 006c 1B68 ldr r3, [r3] + 8626 006e 4FF48062 mov r2, #1024 + ARM GAS /tmp/cc5G5cqz.s page 233 + + + 8627 0072 DA61 str r2, [r3, #28] + 8628 .L416: +4549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ +4552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \ + 8629 .loc 1 4552 8 + 8630 0074 7B69 ldr r3, [r7, #20] + 8631 0076 5B0A lsrs r3, r3, #9 + 8632 0078 03F00103 and r3, r3, #1 + 8633 .loc 1 4552 6 + 8634 007c 002B cmp r3, #0 + 8635 007e 10D0 beq .L417 +4553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + 8636 .loc 1 4553 8 + 8637 0080 3B69 ldr r3, [r7, #16] + 8638 0082 DB09 lsrs r3, r3, #7 + 8639 0084 03F00103 and r3, r3, #1 +4552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + 8640 .loc 1 4552 57 discriminator 1 + 8641 0088 002B cmp r3, #0 + 8642 008a 0AD0 beq .L417 +4554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; + 8643 .loc 1 4555 9 + 8644 008c 7B68 ldr r3, [r7, #4] + 8645 008e 5B6C ldr r3, [r3, #68] + 8646 .loc 1 4555 21 + 8647 0090 43F00202 orr r2, r3, #2 + 8648 0094 7B68 ldr r3, [r7, #4] + 8649 0096 5A64 str r2, [r3, #68] +4556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear ARLO flag */ +4558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); + 8650 .loc 1 4558 5 + 8651 0098 7B68 ldr r3, [r7, #4] + 8652 009a 1B68 ldr r3, [r3] + 8653 009c 4FF40072 mov r2, #512 + 8654 00a0 DA61 str r2, [r3, #28] + 8655 .L417: +4559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Store current volatile hi2c->ErrorCode, misra rule */ +4562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmperror = hi2c->ErrorCode; + 8656 .loc 1 4562 12 + 8657 00a2 7B68 ldr r3, [r7, #4] + 8658 00a4 5B6C ldr r3, [r3, #68] + 8659 00a6 FB60 str r3, [r7, #12] +4563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the Error Callback in case of Error detected */ +4565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_ + 8660 .loc 1 4565 17 + 8661 00a8 FB68 ldr r3, [r7, #12] + 8662 00aa 03F00B03 and r3, r3, #11 + 8663 .loc 1 4565 6 + 8664 00ae 002B cmp r3, #0 + 8665 00b0 03D0 beq .L419 + ARM GAS /tmp/cc5G5cqz.s page 234 + + +4566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITError(hi2c, tmperror); + 8666 .loc 1 4567 5 + 8667 00b2 F968 ldr r1, [r7, #12] + 8668 00b4 7868 ldr r0, [r7, #4] + 8669 00b6 FFF7FEFF bl I2C_ITError + 8670 .L419: +4568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8671 .loc 1 4569 1 + 8672 00ba 00BF nop + 8673 00bc 1837 adds r7, r7, #24 + 8674 .cfi_def_cfa_offset 8 + 8675 00be BD46 mov sp, r7 + 8676 .cfi_def_cfa_register 13 + 8677 @ sp needed + 8678 00c0 80BD pop {r7, pc} + 8679 .cfi_endproc + 8680 .LFE165: + 8682 .section .text.HAL_I2C_MasterTxCpltCallback,"ax",%progbits + 8683 .align 1 + 8684 .weak HAL_I2C_MasterTxCpltCallback + 8685 .syntax unified + 8686 .thumb + 8687 .thumb_func + 8689 HAL_I2C_MasterTxCpltCallback: + 8690 .LFB166: +4570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +4572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Master Tx Transfer completed callback. +4573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +4575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +4576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) +4578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8691 .loc 1 4578 1 + 8692 .cfi_startproc + 8693 @ args = 0, pretend = 0, frame = 8 + 8694 @ frame_needed = 1, uses_anonymous_args = 0 + 8695 @ link register save eliminated. + 8696 0000 80B4 push {r7} + 8697 .cfi_def_cfa_offset 4 + 8698 .cfi_offset 7, -4 + 8699 0002 83B0 sub sp, sp, #12 + 8700 .cfi_def_cfa_offset 16 + 8701 0004 00AF add r7, sp, #0 + 8702 .cfi_def_cfa_register 7 + 8703 0006 7860 str r0, [r7, #4] +4579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** UNUSED(hi2c); +4581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +4583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** the HAL_I2C_MasterTxCpltCallback could be implemented in the user file +4584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8704 .loc 1 4585 1 + ARM GAS /tmp/cc5G5cqz.s page 235 + + + 8705 0008 00BF nop + 8706 000a 0C37 adds r7, r7, #12 + 8707 .cfi_def_cfa_offset 4 + 8708 000c BD46 mov sp, r7 + 8709 .cfi_def_cfa_register 13 + 8710 @ sp needed + 8711 000e 5DF8047B ldr r7, [sp], #4 + 8712 .cfi_restore 7 + 8713 .cfi_def_cfa_offset 0 + 8714 0012 7047 bx lr + 8715 .cfi_endproc + 8716 .LFE166: + 8718 .section .text.HAL_I2C_MasterRxCpltCallback,"ax",%progbits + 8719 .align 1 + 8720 .weak HAL_I2C_MasterRxCpltCallback + 8721 .syntax unified + 8722 .thumb + 8723 .thumb_func + 8725 HAL_I2C_MasterRxCpltCallback: + 8726 .LFB167: +4586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +4588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Master Rx Transfer completed callback. +4589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +4591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +4592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) +4594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8727 .loc 1 4594 1 + 8728 .cfi_startproc + 8729 @ args = 0, pretend = 0, frame = 8 + 8730 @ frame_needed = 1, uses_anonymous_args = 0 + 8731 @ link register save eliminated. + 8732 0000 80B4 push {r7} + 8733 .cfi_def_cfa_offset 4 + 8734 .cfi_offset 7, -4 + 8735 0002 83B0 sub sp, sp, #12 + 8736 .cfi_def_cfa_offset 16 + 8737 0004 00AF add r7, sp, #0 + 8738 .cfi_def_cfa_register 7 + 8739 0006 7860 str r0, [r7, #4] +4595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** UNUSED(hi2c); +4597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +4599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** the HAL_I2C_MasterRxCpltCallback could be implemented in the user file +4600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8740 .loc 1 4601 1 + 8741 0008 00BF nop + 8742 000a 0C37 adds r7, r7, #12 + 8743 .cfi_def_cfa_offset 4 + 8744 000c BD46 mov sp, r7 + 8745 .cfi_def_cfa_register 13 + 8746 @ sp needed + 8747 000e 5DF8047B ldr r7, [sp], #4 + ARM GAS /tmp/cc5G5cqz.s page 236 + + + 8748 .cfi_restore 7 + 8749 .cfi_def_cfa_offset 0 + 8750 0012 7047 bx lr + 8751 .cfi_endproc + 8752 .LFE167: + 8754 .section .text.HAL_I2C_SlaveTxCpltCallback,"ax",%progbits + 8755 .align 1 + 8756 .weak HAL_I2C_SlaveTxCpltCallback + 8757 .syntax unified + 8758 .thumb + 8759 .thumb_func + 8761 HAL_I2C_SlaveTxCpltCallback: + 8762 .LFB168: +4602:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** @brief Slave Tx Transfer completed callback. +4604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +4606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +4607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) +4609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8763 .loc 1 4609 1 + 8764 .cfi_startproc + 8765 @ args = 0, pretend = 0, frame = 8 + 8766 @ frame_needed = 1, uses_anonymous_args = 0 + 8767 @ link register save eliminated. + 8768 0000 80B4 push {r7} + 8769 .cfi_def_cfa_offset 4 + 8770 .cfi_offset 7, -4 + 8771 0002 83B0 sub sp, sp, #12 + 8772 .cfi_def_cfa_offset 16 + 8773 0004 00AF add r7, sp, #0 + 8774 .cfi_def_cfa_register 7 + 8775 0006 7860 str r0, [r7, #4] +4610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** UNUSED(hi2c); +4612:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +4614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file +4615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8776 .loc 1 4616 1 + 8777 0008 00BF nop + 8778 000a 0C37 adds r7, r7, #12 + 8779 .cfi_def_cfa_offset 4 + 8780 000c BD46 mov sp, r7 + 8781 .cfi_def_cfa_register 13 + 8782 @ sp needed + 8783 000e 5DF8047B ldr r7, [sp], #4 + 8784 .cfi_restore 7 + 8785 .cfi_def_cfa_offset 0 + 8786 0012 7047 bx lr + 8787 .cfi_endproc + 8788 .LFE168: + 8790 .section .text.HAL_I2C_SlaveRxCpltCallback,"ax",%progbits + 8791 .align 1 + 8792 .weak HAL_I2C_SlaveRxCpltCallback + ARM GAS /tmp/cc5G5cqz.s page 237 + + + 8793 .syntax unified + 8794 .thumb + 8795 .thumb_func + 8797 HAL_I2C_SlaveRxCpltCallback: + 8798 .LFB169: +4617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +4619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Slave Rx Transfer completed callback. +4620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +4622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +4623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) +4625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8799 .loc 1 4625 1 + 8800 .cfi_startproc + 8801 @ args = 0, pretend = 0, frame = 8 + 8802 @ frame_needed = 1, uses_anonymous_args = 0 + 8803 @ link register save eliminated. + 8804 0000 80B4 push {r7} + 8805 .cfi_def_cfa_offset 4 + 8806 .cfi_offset 7, -4 + 8807 0002 83B0 sub sp, sp, #12 + 8808 .cfi_def_cfa_offset 16 + 8809 0004 00AF add r7, sp, #0 + 8810 .cfi_def_cfa_register 7 + 8811 0006 7860 str r0, [r7, #4] +4626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** UNUSED(hi2c); +4628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +4630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file +4631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8812 .loc 1 4632 1 + 8813 0008 00BF nop + 8814 000a 0C37 adds r7, r7, #12 + 8815 .cfi_def_cfa_offset 4 + 8816 000c BD46 mov sp, r7 + 8817 .cfi_def_cfa_register 13 + 8818 @ sp needed + 8819 000e 5DF8047B ldr r7, [sp], #4 + 8820 .cfi_restore 7 + 8821 .cfi_def_cfa_offset 0 + 8822 0012 7047 bx lr + 8823 .cfi_endproc + 8824 .LFE169: + 8826 .section .text.HAL_I2C_AddrCallback,"ax",%progbits + 8827 .align 1 + 8828 .weak HAL_I2C_AddrCallback + 8829 .syntax unified + 8830 .thumb + 8831 .thumb_func + 8833 HAL_I2C_AddrCallback: + 8834 .LFB170: +4633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** + ARM GAS /tmp/cc5G5cqz.s page 238 + + +4635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Slave Address Match callback. +4636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +4638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFE +4639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param AddrMatchCode Address Match Code +4640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +4641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4642:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrM +4643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8835 .loc 1 4643 1 + 8836 .cfi_startproc + 8837 @ args = 0, pretend = 0, frame = 8 + 8838 @ frame_needed = 1, uses_anonymous_args = 0 + 8839 @ link register save eliminated. + 8840 0000 80B4 push {r7} + 8841 .cfi_def_cfa_offset 4 + 8842 .cfi_offset 7, -4 + 8843 0002 83B0 sub sp, sp, #12 + 8844 .cfi_def_cfa_offset 16 + 8845 0004 00AF add r7, sp, #0 + 8846 .cfi_def_cfa_register 7 + 8847 0006 7860 str r0, [r7, #4] + 8848 0008 0B46 mov r3, r1 + 8849 000a FB70 strb r3, [r7, #3] + 8850 000c 1346 mov r3, r2 @ movhi + 8851 000e 3B80 strh r3, [r7] @ movhi +4644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** UNUSED(hi2c); +4646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** UNUSED(TransferDirection); +4647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** UNUSED(AddrMatchCode); +4648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +4650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** the HAL_I2C_AddrCallback() could be implemented in the user file +4651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8852 .loc 1 4652 1 + 8853 0010 00BF nop + 8854 0012 0C37 adds r7, r7, #12 + 8855 .cfi_def_cfa_offset 4 + 8856 0014 BD46 mov sp, r7 + 8857 .cfi_def_cfa_register 13 + 8858 @ sp needed + 8859 0016 5DF8047B ldr r7, [sp], #4 + 8860 .cfi_restore 7 + 8861 .cfi_def_cfa_offset 0 + 8862 001a 7047 bx lr + 8863 .cfi_endproc + 8864 .LFE170: + 8866 .section .text.HAL_I2C_ListenCpltCallback,"ax",%progbits + 8867 .align 1 + 8868 .weak HAL_I2C_ListenCpltCallback + 8869 .syntax unified + 8870 .thumb + 8871 .thumb_func + 8873 HAL_I2C_ListenCpltCallback: + 8874 .LFB171: +4653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/cc5G5cqz.s page 239 + + +4654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +4655:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Listen Complete callback. +4656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4657:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +4658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +4659:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) +4661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8875 .loc 1 4661 1 + 8876 .cfi_startproc + 8877 @ args = 0, pretend = 0, frame = 8 + 8878 @ frame_needed = 1, uses_anonymous_args = 0 + 8879 @ link register save eliminated. + 8880 0000 80B4 push {r7} + 8881 .cfi_def_cfa_offset 4 + 8882 .cfi_offset 7, -4 + 8883 0002 83B0 sub sp, sp, #12 + 8884 .cfi_def_cfa_offset 16 + 8885 0004 00AF add r7, sp, #0 + 8886 .cfi_def_cfa_register 7 + 8887 0006 7860 str r0, [r7, #4] +4662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** UNUSED(hi2c); +4664:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +4666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** the HAL_I2C_ListenCpltCallback() could be implemented in the user file +4667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4668:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8888 .loc 1 4668 1 + 8889 0008 00BF nop + 8890 000a 0C37 adds r7, r7, #12 + 8891 .cfi_def_cfa_offset 4 + 8892 000c BD46 mov sp, r7 + 8893 .cfi_def_cfa_register 13 + 8894 @ sp needed + 8895 000e 5DF8047B ldr r7, [sp], #4 + 8896 .cfi_restore 7 + 8897 .cfi_def_cfa_offset 0 + 8898 0012 7047 bx lr + 8899 .cfi_endproc + 8900 .LFE171: + 8902 .section .text.HAL_I2C_MemTxCpltCallback,"ax",%progbits + 8903 .align 1 + 8904 .weak HAL_I2C_MemTxCpltCallback + 8905 .syntax unified + 8906 .thumb + 8907 .thumb_func + 8909 HAL_I2C_MemTxCpltCallback: + 8910 .LFB172: +4669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +4671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Memory Tx Transfer completed callback. +4672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +4674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +4675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) + ARM GAS /tmp/cc5G5cqz.s page 240 + + +4677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8911 .loc 1 4677 1 + 8912 .cfi_startproc + 8913 @ args = 0, pretend = 0, frame = 8 + 8914 @ frame_needed = 1, uses_anonymous_args = 0 + 8915 @ link register save eliminated. + 8916 0000 80B4 push {r7} + 8917 .cfi_def_cfa_offset 4 + 8918 .cfi_offset 7, -4 + 8919 0002 83B0 sub sp, sp, #12 + 8920 .cfi_def_cfa_offset 16 + 8921 0004 00AF add r7, sp, #0 + 8922 .cfi_def_cfa_register 7 + 8923 0006 7860 str r0, [r7, #4] +4678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** UNUSED(hi2c); +4680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +4682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** the HAL_I2C_MemTxCpltCallback could be implemented in the user file +4683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8924 .loc 1 4684 1 + 8925 0008 00BF nop + 8926 000a 0C37 adds r7, r7, #12 + 8927 .cfi_def_cfa_offset 4 + 8928 000c BD46 mov sp, r7 + 8929 .cfi_def_cfa_register 13 + 8930 @ sp needed + 8931 000e 5DF8047B ldr r7, [sp], #4 + 8932 .cfi_restore 7 + 8933 .cfi_def_cfa_offset 0 + 8934 0012 7047 bx lr + 8935 .cfi_endproc + 8936 .LFE172: + 8938 .section .text.HAL_I2C_MemRxCpltCallback,"ax",%progbits + 8939 .align 1 + 8940 .weak HAL_I2C_MemRxCpltCallback + 8941 .syntax unified + 8942 .thumb + 8943 .thumb_func + 8945 HAL_I2C_MemRxCpltCallback: + 8946 .LFB173: +4685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +4687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Memory Rx Transfer completed callback. +4688:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +4690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +4691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) +4693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8947 .loc 1 4693 1 + 8948 .cfi_startproc + 8949 @ args = 0, pretend = 0, frame = 8 + 8950 @ frame_needed = 1, uses_anonymous_args = 0 + 8951 @ link register save eliminated. + 8952 0000 80B4 push {r7} + ARM GAS /tmp/cc5G5cqz.s page 241 + + + 8953 .cfi_def_cfa_offset 4 + 8954 .cfi_offset 7, -4 + 8955 0002 83B0 sub sp, sp, #12 + 8956 .cfi_def_cfa_offset 16 + 8957 0004 00AF add r7, sp, #0 + 8958 .cfi_def_cfa_register 7 + 8959 0006 7860 str r0, [r7, #4] +4694:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** UNUSED(hi2c); +4696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +4698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** the HAL_I2C_MemRxCpltCallback could be implemented in the user file +4699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4700:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8960 .loc 1 4700 1 + 8961 0008 00BF nop + 8962 000a 0C37 adds r7, r7, #12 + 8963 .cfi_def_cfa_offset 4 + 8964 000c BD46 mov sp, r7 + 8965 .cfi_def_cfa_register 13 + 8966 @ sp needed + 8967 000e 5DF8047B ldr r7, [sp], #4 + 8968 .cfi_restore 7 + 8969 .cfi_def_cfa_offset 0 + 8970 0012 7047 bx lr + 8971 .cfi_endproc + 8972 .LFE173: + 8974 .section .text.HAL_I2C_ErrorCallback,"ax",%progbits + 8975 .align 1 + 8976 .weak HAL_I2C_ErrorCallback + 8977 .syntax unified + 8978 .thumb + 8979 .thumb_func + 8981 HAL_I2C_ErrorCallback: + 8982 .LFB174: +4701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +4703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief I2C error callback. +4704:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +4706:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +4707:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4708:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) +4709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 8983 .loc 1 4709 1 + 8984 .cfi_startproc + 8985 @ args = 0, pretend = 0, frame = 8 + 8986 @ frame_needed = 1, uses_anonymous_args = 0 + 8987 @ link register save eliminated. + 8988 0000 80B4 push {r7} + 8989 .cfi_def_cfa_offset 4 + 8990 .cfi_offset 7, -4 + 8991 0002 83B0 sub sp, sp, #12 + 8992 .cfi_def_cfa_offset 16 + 8993 0004 00AF add r7, sp, #0 + 8994 .cfi_def_cfa_register 7 + 8995 0006 7860 str r0, [r7, #4] + ARM GAS /tmp/cc5G5cqz.s page 242 + + +4710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** UNUSED(hi2c); +4712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4713:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +4714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** the HAL_I2C_ErrorCallback could be implemented in the user file +4715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4716:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 8996 .loc 1 4716 1 + 8997 0008 00BF nop + 8998 000a 0C37 adds r7, r7, #12 + 8999 .cfi_def_cfa_offset 4 + 9000 000c BD46 mov sp, r7 + 9001 .cfi_def_cfa_register 13 + 9002 @ sp needed + 9003 000e 5DF8047B ldr r7, [sp], #4 + 9004 .cfi_restore 7 + 9005 .cfi_def_cfa_offset 0 + 9006 0012 7047 bx lr + 9007 .cfi_endproc + 9008 .LFE174: + 9010 .section .text.HAL_I2C_AbortCpltCallback,"ax",%progbits + 9011 .align 1 + 9012 .weak HAL_I2C_AbortCpltCallback + 9013 .syntax unified + 9014 .thumb + 9015 .thumb_func + 9017 HAL_I2C_AbortCpltCallback: + 9018 .LFB175: +4717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4718:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +4719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief I2C abort callback. +4720:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +4722:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +4723:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4724:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) +4725:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9019 .loc 1 4725 1 + 9020 .cfi_startproc + 9021 @ args = 0, pretend = 0, frame = 8 + 9022 @ frame_needed = 1, uses_anonymous_args = 0 + 9023 @ link register save eliminated. + 9024 0000 80B4 push {r7} + 9025 .cfi_def_cfa_offset 4 + 9026 .cfi_offset 7, -4 + 9027 0002 83B0 sub sp, sp, #12 + 9028 .cfi_def_cfa_offset 16 + 9029 0004 00AF add r7, sp, #0 + 9030 .cfi_def_cfa_register 7 + 9031 0006 7860 str r0, [r7, #4] +4726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +4727:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** UNUSED(hi2c); +4728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* NOTE : This function should not be modified, when the callback is needed, +4730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** the HAL_I2C_AbortCpltCallback could be implemented in the user file +4731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/cc5G5cqz.s page 243 + + + 9032 .loc 1 4732 1 + 9033 0008 00BF nop + 9034 000a 0C37 adds r7, r7, #12 + 9035 .cfi_def_cfa_offset 4 + 9036 000c BD46 mov sp, r7 + 9037 .cfi_def_cfa_register 13 + 9038 @ sp needed + 9039 000e 5DF8047B ldr r7, [sp], #4 + 9040 .cfi_restore 7 + 9041 .cfi_def_cfa_offset 0 + 9042 0012 7047 bx lr + 9043 .cfi_endproc + 9044 .LFE175: + 9046 .section .text.HAL_I2C_GetState,"ax",%progbits + 9047 .align 1 + 9048 .global HAL_I2C_GetState + 9049 .syntax unified + 9050 .thumb + 9051 .thumb_func + 9053 HAL_I2C_GetState: + 9054 .LFB176: +4733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4734:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +4735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @} +4736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4737:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions +4739:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Peripheral State, Mode and Error functions +4740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * +4741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** @verbatim +4742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** =============================================================================== +4743:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** ##### Peripheral State, Mode and Error functions ##### +4744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** =============================================================================== +4745:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** [..] +4746:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** This subsection permit to get in run-time the status of the peripheral +4747:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** and the data flow. +4748:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** @endverbatim +4750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @{ +4751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4752:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +4754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Return the I2C handle state. +4755:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +4757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL state +4758:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c) +4760:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9055 .loc 1 4760 1 + 9056 .cfi_startproc + 9057 @ args = 0, pretend = 0, frame = 8 + 9058 @ frame_needed = 1, uses_anonymous_args = 0 + 9059 @ link register save eliminated. + 9060 0000 80B4 push {r7} + 9061 .cfi_def_cfa_offset 4 + 9062 .cfi_offset 7, -4 + ARM GAS /tmp/cc5G5cqz.s page 244 + + + 9063 0002 83B0 sub sp, sp, #12 + 9064 .cfi_def_cfa_offset 16 + 9065 0004 00AF add r7, sp, #0 + 9066 .cfi_def_cfa_register 7 + 9067 0006 7860 str r0, [r7, #4] +4761:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Return I2C handle state */ +4762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return hi2c->State; + 9068 .loc 1 4762 14 + 9069 0008 7B68 ldr r3, [r7, #4] + 9070 000a 93F84130 ldrb r3, [r3, #65] + 9071 000e DBB2 uxtb r3, r3 +4763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 9072 .loc 1 4763 1 + 9073 0010 1846 mov r0, r3 + 9074 0012 0C37 adds r7, r7, #12 + 9075 .cfi_def_cfa_offset 4 + 9076 0014 BD46 mov sp, r7 + 9077 .cfi_def_cfa_register 13 + 9078 @ sp needed + 9079 0016 5DF8047B ldr r7, [sp], #4 + 9080 .cfi_restore 7 + 9081 .cfi_def_cfa_offset 0 + 9082 001a 7047 bx lr + 9083 .cfi_endproc + 9084 .LFE176: + 9086 .section .text.HAL_I2C_GetMode,"ax",%progbits + 9087 .align 1 + 9088 .global HAL_I2C_GetMode + 9089 .syntax unified + 9090 .thumb + 9091 .thumb_func + 9093 HAL_I2C_GetMode: + 9094 .LFB177: +4764:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +4766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Returns the I2C Master, Slave, Memory or no mode. +4767:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for I2C module +4769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL mode +4770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c) +4772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9095 .loc 1 4772 1 + 9096 .cfi_startproc + 9097 @ args = 0, pretend = 0, frame = 8 + 9098 @ frame_needed = 1, uses_anonymous_args = 0 + 9099 @ link register save eliminated. + 9100 0000 80B4 push {r7} + 9101 .cfi_def_cfa_offset 4 + 9102 .cfi_offset 7, -4 + 9103 0002 83B0 sub sp, sp, #12 + 9104 .cfi_def_cfa_offset 16 + 9105 0004 00AF add r7, sp, #0 + 9106 .cfi_def_cfa_register 7 + 9107 0006 7860 str r0, [r7, #4] +4773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return hi2c->Mode; + 9108 .loc 1 4773 14 + ARM GAS /tmp/cc5G5cqz.s page 245 + + + 9109 0008 7B68 ldr r3, [r7, #4] + 9110 000a 93F84230 ldrb r3, [r3, #66] + 9111 000e DBB2 uxtb r3, r3 +4774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 9112 .loc 1 4774 1 + 9113 0010 1846 mov r0, r3 + 9114 0012 0C37 adds r7, r7, #12 + 9115 .cfi_def_cfa_offset 4 + 9116 0014 BD46 mov sp, r7 + 9117 .cfi_def_cfa_register 13 + 9118 @ sp needed + 9119 0016 5DF8047B ldr r7, [sp], #4 + 9120 .cfi_restore 7 + 9121 .cfi_def_cfa_offset 0 + 9122 001a 7047 bx lr + 9123 .cfi_endproc + 9124 .LFE177: + 9126 .section .text.HAL_I2C_GetError,"ax",%progbits + 9127 .align 1 + 9128 .global HAL_I2C_GetError + 9129 .syntax unified + 9130 .thumb + 9131 .thumb_func + 9133 HAL_I2C_GetError: + 9134 .LFB178: +4775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +4777:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Return the I2C error code. +4778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +4780:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval I2C Error Code +4781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4782:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c) +4783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9135 .loc 1 4783 1 + 9136 .cfi_startproc + 9137 @ args = 0, pretend = 0, frame = 8 + 9138 @ frame_needed = 1, uses_anonymous_args = 0 + 9139 @ link register save eliminated. + 9140 0000 80B4 push {r7} + 9141 .cfi_def_cfa_offset 4 + 9142 .cfi_offset 7, -4 + 9143 0002 83B0 sub sp, sp, #12 + 9144 .cfi_def_cfa_offset 16 + 9145 0004 00AF add r7, sp, #0 + 9146 .cfi_def_cfa_register 7 + 9147 0006 7860 str r0, [r7, #4] +4784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return hi2c->ErrorCode; + 9148 .loc 1 4784 14 + 9149 0008 7B68 ldr r3, [r7, #4] + 9150 000a 5B6C ldr r3, [r3, #68] +4785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 9151 .loc 1 4785 1 + 9152 000c 1846 mov r0, r3 + 9153 000e 0C37 adds r7, r7, #12 + 9154 .cfi_def_cfa_offset 4 + 9155 0010 BD46 mov sp, r7 + ARM GAS /tmp/cc5G5cqz.s page 246 + + + 9156 .cfi_def_cfa_register 13 + 9157 @ sp needed + 9158 0012 5DF8047B ldr r7, [sp], #4 + 9159 .cfi_restore 7 + 9160 .cfi_def_cfa_offset 0 + 9161 0016 7047 bx lr + 9162 .cfi_endproc + 9163 .LFE178: + 9165 .section .text.I2C_Master_ISR_IT,"ax",%progbits + 9166 .align 1 + 9167 .syntax unified + 9168 .thumb + 9169 .thumb_func + 9171 I2C_Master_ISR_IT: + 9172 .LFB179: +4786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4787:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +4788:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @} +4789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +4792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @} +4793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** @addtogroup I2C_Private_Functions +4796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @{ +4797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4798:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4799:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +4800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt. +4801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +4803:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. +4804:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param ITSources Interrupt sources enabled. +4805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +4806:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4807:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, +4808:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t ITSources) +4809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9173 .loc 1 4809 1 + 9174 .cfi_startproc + 9175 @ args = 0, pretend = 0, frame = 24 + 9176 @ frame_needed = 1, uses_anonymous_args = 0 + 9177 0000 80B5 push {r7, lr} + 9178 .cfi_def_cfa_offset 8 + 9179 .cfi_offset 7, -8 + 9180 .cfi_offset 14, -4 + 9181 0002 88B0 sub sp, sp, #32 + 9182 .cfi_def_cfa_offset 40 + 9183 0004 02AF add r7, sp, #8 + 9184 .cfi_def_cfa 7, 32 + 9185 0006 F860 str r0, [r7, #12] + 9186 0008 B960 str r1, [r7, #8] + 9187 000a 7A60 str r2, [r7, #4] +4810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t devaddress; +4811:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; + 9188 .loc 1 4811 12 + ARM GAS /tmp/cc5G5cqz.s page 247 + + + 9189 000c BB68 ldr r3, [r7, #8] + 9190 000e 7B61 str r3, [r7, #20] +4812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +4814:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); + 9191 .loc 1 4814 3 + 9192 0010 FB68 ldr r3, [r7, #12] + 9193 0012 93F84030 ldrb r3, [r3, #64] @ zero_extendqisi2 + 9194 0016 012B cmp r3, #1 + 9195 0018 01D1 bne .L437 + 9196 .loc 1 4814 3 is_stmt 0 discriminator 1 + 9197 001a 0223 movs r3, #2 + 9198 .loc 1 4814 3 + 9199 001c 14E1 b .L438 + 9200 .L437: + 9201 .loc 1 4814 3 discriminator 2 + 9202 001e FB68 ldr r3, [r7, #12] + 9203 0020 0122 movs r2, #1 + 9204 0022 83F84020 strb r2, [r3, #64] +4815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + 9205 .loc 1 4816 8 is_stmt 1 + 9206 0026 7B69 ldr r3, [r7, #20] + 9207 0028 1B09 lsrs r3, r3, #4 + 9208 002a 03F00103 and r3, r3, #1 + 9209 .loc 1 4816 6 + 9210 002e 002B cmp r3, #0 + 9211 0030 13D0 beq .L439 +4817:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 9212 .loc 1 4817 8 + 9213 0032 7B68 ldr r3, [r7, #4] + 9214 0034 1B09 lsrs r3, r3, #4 + 9215 0036 03F00103 and r3, r3, #1 +4816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 9216 .loc 1 4816 58 discriminator 1 + 9217 003a 002B cmp r3, #0 + 9218 003c 0DD0 beq .L439 +4818:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear NACK Flag */ +4820:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + 9219 .loc 1 4820 5 + 9220 003e FB68 ldr r3, [r7, #12] + 9221 0040 1B68 ldr r3, [r3] + 9222 0042 1022 movs r2, #16 + 9223 0044 DA61 str r2, [r3, #28] +4821:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set corresponding Error Code */ +4823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* No need to generate STOP, it is automatically done */ +4824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Error callback will be send during stop flag treatment */ +4825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + 9224 .loc 1 4825 9 + 9225 0046 FB68 ldr r3, [r7, #12] + 9226 0048 5B6C ldr r3, [r3, #68] + 9227 .loc 1 4825 21 + 9228 004a 43F00402 orr r2, r3, #4 + 9229 004e FB68 ldr r3, [r7, #12] + 9230 0050 5A64 str r2, [r3, #68] + ARM GAS /tmp/cc5G5cqz.s page 248 + + +4826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4827:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Flush TX register */ +4828:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); + 9231 .loc 1 4828 5 + 9232 0052 F868 ldr r0, [r7, #12] + 9233 0054 FFF7FEFF bl I2C_Flush_TXDR + 9234 0058 E1E0 b .L440 + 9235 .L439: +4829:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4830:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ + 9236 .loc 1 4830 13 + 9237 005a 7B69 ldr r3, [r7, #20] + 9238 005c 9B08 lsrs r3, r3, #2 + 9239 005e 03F00103 and r3, r3, #1 + 9240 .loc 1 4830 11 + 9241 0062 002B cmp r3, #0 + 9242 0064 23D0 beq .L441 +4831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + 9243 .loc 1 4831 13 + 9244 0066 7B68 ldr r3, [r7, #4] + 9245 0068 9B08 lsrs r3, r3, #2 + 9246 006a 03F00103 and r3, r3, #1 +4830:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + 9247 .loc 1 4830 65 discriminator 1 + 9248 006e 002B cmp r3, #0 + 9249 0070 1DD0 beq .L441 +4832:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Remove RXNE flag on temporary variable as read done */ +4834:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmpITFlags &= ~I2C_FLAG_RXNE; + 9250 .loc 1 4834 16 + 9251 0072 7B69 ldr r3, [r7, #20] + 9252 0074 23F00403 bic r3, r3, #4 + 9253 0078 7B61 str r3, [r7, #20] +4835:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4836:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Read data from RXDR */ +4837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + 9254 .loc 1 4837 36 + 9255 007a FB68 ldr r3, [r7, #12] + 9256 007c 1B68 ldr r3, [r3] + 9257 .loc 1 4837 46 + 9258 007e 5A6A ldr r2, [r3, #36] + 9259 .loc 1 4837 10 + 9260 0080 FB68 ldr r3, [r7, #12] + 9261 0082 5B6A ldr r3, [r3, #36] + 9262 .loc 1 4837 23 + 9263 0084 D2B2 uxtb r2, r2 + 9264 .loc 1 4837 21 + 9265 0086 1A70 strb r2, [r3] +4838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Increment Buffer pointer */ +4840:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr++; + 9266 .loc 1 4840 9 + 9267 0088 FB68 ldr r3, [r7, #12] + 9268 008a 5B6A ldr r3, [r3, #36] + 9269 .loc 1 4840 19 + 9270 008c 5A1C adds r2, r3, #1 + 9271 008e FB68 ldr r3, [r7, #12] + ARM GAS /tmp/cc5G5cqz.s page 249 + + + 9272 0090 5A62 str r2, [r3, #36] +4841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4842:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize--; + 9273 .loc 1 4842 9 + 9274 0092 FB68 ldr r3, [r7, #12] + 9275 0094 1B8D ldrh r3, [r3, #40] + 9276 .loc 1 4842 19 + 9277 0096 013B subs r3, r3, #1 + 9278 0098 9AB2 uxth r2, r3 + 9279 009a FB68 ldr r3, [r7, #12] + 9280 009c 1A85 strh r2, [r3, #40] @ movhi +4843:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount--; + 9281 .loc 1 4843 9 + 9282 009e FB68 ldr r3, [r7, #12] + 9283 00a0 5B8D ldrh r3, [r3, #42] @ movhi + 9284 00a2 9BB2 uxth r3, r3 + 9285 .loc 1 4843 20 + 9286 00a4 013B subs r3, r3, #1 + 9287 00a6 9AB2 uxth r2, r3 + 9288 00a8 FB68 ldr r3, [r7, #12] + 9289 00aa 5A85 strh r2, [r3, #42] @ movhi + 9290 00ac B7E0 b .L440 + 9291 .L441: +4844:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + 9292 .loc 1 4845 13 + 9293 00ae 7B69 ldr r3, [r7, #20] + 9294 00b0 5B08 lsrs r3, r3, #1 + 9295 00b2 03F00103 and r3, r3, #1 + 9296 .loc 1 4845 11 + 9297 00b6 002B cmp r3, #0 + 9298 00b8 1ED0 beq .L442 +4846:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + 9299 .loc 1 4846 13 + 9300 00ba 7B68 ldr r3, [r7, #4] + 9301 00bc 5B08 lsrs r3, r3, #1 + 9302 00be 03F00103 and r3, r3, #1 +4845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + 9303 .loc 1 4845 65 discriminator 1 + 9304 00c2 002B cmp r3, #0 + 9305 00c4 18D0 beq .L442 +4847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Write data to TXDR */ +4849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->TXDR = *hi2c->pBuffPtr; + 9306 .loc 1 4849 33 + 9307 00c6 FB68 ldr r3, [r7, #12] + 9308 00c8 5B6A ldr r3, [r3, #36] + 9309 .loc 1 4849 28 + 9310 00ca 1A78 ldrb r2, [r3] @ zero_extendqisi2 + 9311 .loc 1 4849 9 + 9312 00cc FB68 ldr r3, [r7, #12] + 9313 00ce 1B68 ldr r3, [r3] + 9314 .loc 1 4849 26 + 9315 00d0 9A62 str r2, [r3, #40] +4850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4851:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Increment Buffer pointer */ +4852:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr++; + ARM GAS /tmp/cc5G5cqz.s page 250 + + + 9316 .loc 1 4852 9 + 9317 00d2 FB68 ldr r3, [r7, #12] + 9318 00d4 5B6A ldr r3, [r3, #36] + 9319 .loc 1 4852 19 + 9320 00d6 5A1C adds r2, r3, #1 + 9321 00d8 FB68 ldr r3, [r7, #12] + 9322 00da 5A62 str r2, [r3, #36] +4853:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize--; + 9323 .loc 1 4854 9 + 9324 00dc FB68 ldr r3, [r7, #12] + 9325 00de 1B8D ldrh r3, [r3, #40] + 9326 .loc 1 4854 19 + 9327 00e0 013B subs r3, r3, #1 + 9328 00e2 9AB2 uxth r2, r3 + 9329 00e4 FB68 ldr r3, [r7, #12] + 9330 00e6 1A85 strh r2, [r3, #40] @ movhi +4855:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount--; + 9331 .loc 1 4855 9 + 9332 00e8 FB68 ldr r3, [r7, #12] + 9333 00ea 5B8D ldrh r3, [r3, #42] @ movhi + 9334 00ec 9BB2 uxth r3, r3 + 9335 .loc 1 4855 20 + 9336 00ee 013B subs r3, r3, #1 + 9337 00f0 9AB2 uxth r2, r3 + 9338 00f2 FB68 ldr r3, [r7, #12] + 9339 00f4 5A85 strh r2, [r3, #42] @ movhi + 9340 00f6 92E0 b .L440 + 9341 .L442: +4856:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4857:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \ + 9342 .loc 1 4857 13 + 9343 00f8 7B69 ldr r3, [r7, #20] + 9344 00fa DB09 lsrs r3, r3, #7 + 9345 00fc 03F00103 and r3, r3, #1 + 9346 .loc 1 4857 11 + 9347 0100 002B cmp r3, #0 + 9348 0102 5DD0 beq .L443 +4858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 9349 .loc 1 4858 13 + 9350 0104 7B68 ldr r3, [r7, #4] + 9351 0106 9B09 lsrs r3, r3, #6 + 9352 0108 03F00103 and r3, r3, #1 +4857:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 9353 .loc 1 4857 64 discriminator 1 + 9354 010c 002B cmp r3, #0 + 9355 010e 57D0 beq .L443 +4859:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + 9356 .loc 1 4860 14 + 9357 0110 FB68 ldr r3, [r7, #12] + 9358 0112 5B8D ldrh r3, [r3, #42] @ movhi + 9359 0114 9BB2 uxth r3, r3 + 9360 .loc 1 4860 8 + 9361 0116 002B cmp r3, #0 + 9362 0118 40D0 beq .L444 + 9363 .loc 1 4860 41 discriminator 1 + ARM GAS /tmp/cc5G5cqz.s page 251 + + + 9364 011a FB68 ldr r3, [r7, #12] + 9365 011c 1B8D ldrh r3, [r3, #40] + 9366 .loc 1 4860 33 discriminator 1 + 9367 011e 002B cmp r3, #0 + 9368 0120 3CD1 bne .L444 +4861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); + 9369 .loc 1 4862 35 + 9370 0122 FB68 ldr r3, [r7, #12] + 9371 0124 1B68 ldr r3, [r3] + 9372 .loc 1 4862 45 + 9373 0126 5B68 ldr r3, [r3, #4] + 9374 .loc 1 4862 20 + 9375 0128 9BB2 uxth r3, r3 + 9376 .loc 1 4862 18 + 9377 012a C3F30903 ubfx r3, r3, #0, #10 + 9378 012e 7B82 strh r3, [r7, #18] @ movhi +4863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4864:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) + 9379 .loc 1 4864 15 + 9380 0130 FB68 ldr r3, [r7, #12] + 9381 0132 5B8D ldrh r3, [r3, #42] @ movhi + 9382 0134 9BB2 uxth r3, r3 + 9383 .loc 1 4864 10 + 9384 0136 FF2B cmp r3, #255 + 9385 0138 0ED9 bls .L445 +4865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; + 9386 .loc 1 4866 24 + 9387 013a FB68 ldr r3, [r7, #12] + 9388 013c FF22 movs r2, #255 + 9389 013e 1A85 strh r2, [r3, #40] @ movhi +4867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_START + 9390 .loc 1 4867 59 + 9391 0140 FB68 ldr r3, [r7, #12] + 9392 0142 1B8D ldrh r3, [r3, #40] + 9393 .loc 1 4867 9 + 9394 0144 DAB2 uxtb r2, r3 + 9395 0146 798A ldrh r1, [r7, #18] + 9396 0148 0023 movs r3, #0 + 9397 014a 0093 str r3, [sp] + 9398 014c 4FF08073 mov r3, #16777216 + 9399 0150 F868 ldr r0, [r7, #12] + 9400 0152 FFF7FEFF bl I2C_TransferConfig +4864:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9401 .loc 1 4864 10 + 9402 0156 32E0 b .L448 + 9403 .L445: +4868:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +4870:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 9404 .loc 1 4871 30 + 9405 0158 FB68 ldr r3, [r7, #12] + 9406 015a 5B8D ldrh r3, [r3, #42] @ movhi + 9407 015c 9AB2 uxth r2, r3 + 9408 .loc 1 4871 24 + ARM GAS /tmp/cc5G5cqz.s page 252 + + + 9409 015e FB68 ldr r3, [r7, #12] + 9410 0160 1A85 strh r2, [r3, #40] @ movhi +4872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + 9411 .loc 1 4872 17 + 9412 0162 FB68 ldr r3, [r7, #12] + 9413 0164 DB6A ldr r3, [r3, #44] + 9414 .loc 1 4872 12 + 9415 0166 13F5803F cmn r3, #65536 + 9416 016a 0BD0 beq .L447 +4873:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, + 9417 .loc 1 4874 61 + 9418 016c FB68 ldr r3, [r7, #12] + 9419 016e 1B8D ldrh r3, [r3, #40] + 9420 .loc 1 4874 11 + 9421 0170 DAB2 uxtb r2, r3 +4875:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions, I2C_NO_STARTSTOP); + 9422 .loc 1 4875 34 + 9423 0172 FB68 ldr r3, [r7, #12] + 9424 0174 DB6A ldr r3, [r3, #44] +4874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions, I2C_NO_STARTSTOP); + 9425 .loc 1 4874 11 + 9426 0176 798A ldrh r1, [r7, #18] + 9427 0178 0020 movs r0, #0 + 9428 017a 0090 str r0, [sp] + 9429 017c F868 ldr r0, [r7, #12] + 9430 017e FFF7FEFF bl I2C_TransferConfig +4864:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9431 .loc 1 4864 10 + 9432 0182 1CE0 b .L448 + 9433 .L447: +4876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4877:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +4878:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4879:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, + 9434 .loc 1 4879 61 + 9435 0184 FB68 ldr r3, [r7, #12] + 9436 0186 1B8D ldrh r3, [r3, #40] + 9437 .loc 1 4879 11 + 9438 0188 DAB2 uxtb r2, r3 + 9439 018a 798A ldrh r1, [r7, #18] + 9440 018c 0023 movs r3, #0 + 9441 018e 0093 str r3, [sp] + 9442 0190 4FF00073 mov r3, #33554432 + 9443 0194 F868 ldr r0, [r7, #12] + 9444 0196 FFF7FEFF bl I2C_TransferConfig +4864:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9445 .loc 1 4864 10 + 9446 019a 10E0 b .L448 + 9447 .L444: +4880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); +4881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4884:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +4885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call TxCpltCallback() if no stop mode is set */ + ARM GAS /tmp/cc5G5cqz.s page 253 + + +4887:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + 9448 .loc 1 4887 11 + 9449 019c FB68 ldr r3, [r7, #12] + 9450 019e 1B68 ldr r3, [r3] + 9451 01a0 5B68 ldr r3, [r3, #4] + 9452 01a2 03F00073 and r3, r3, #33554432 + 9453 .loc 1 4887 10 + 9454 01a6 B3F1007F cmp r3, #33554432 + 9455 01aa 03D0 beq .L449 +4888:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4889:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call I2C Master Sequential complete process */ +4890:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITMasterSeqCplt(hi2c); + 9456 .loc 1 4890 9 + 9457 01ac F868 ldr r0, [r7, #12] + 9458 01ae FFF7FEFF bl I2C_ITMasterSeqCplt +4860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9459 .loc 1 4860 8 + 9460 01b2 34E0 b .L440 + 9461 .L449: +4891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4892:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +4893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4894:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wrong size Status regarding TCR flag event */ +4895:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +4896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + 9462 .loc 1 4896 9 + 9463 01b4 4021 movs r1, #64 + 9464 01b6 F868 ldr r0, [r7, #12] + 9465 01b8 FFF7FEFF bl I2C_ITError +4860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9466 .loc 1 4860 8 + 9467 01bc 2FE0 b .L440 + 9468 .L448: + 9469 01be 2EE0 b .L440 + 9470 .L443: +4897:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4899:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4900:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \ + 9471 .loc 1 4900 13 + 9472 01c0 7B69 ldr r3, [r7, #20] + 9473 01c2 9B09 lsrs r3, r3, #6 + 9474 01c4 03F00103 and r3, r3, #1 + 9475 .loc 1 4900 11 + 9476 01c8 002B cmp r3, #0 + 9477 01ca 28D0 beq .L440 +4901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 9478 .loc 1 4901 13 + 9479 01cc 7B68 ldr r3, [r7, #4] + 9480 01ce 9B09 lsrs r3, r3, #6 + 9481 01d0 03F00103 and r3, r3, #1 +4900:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 9482 .loc 1 4900 63 discriminator 1 + 9483 01d4 002B cmp r3, #0 + 9484 01d6 22D0 beq .L440 +4902:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount == 0U) + ARM GAS /tmp/cc5G5cqz.s page 254 + + + 9485 .loc 1 4903 13 + 9486 01d8 FB68 ldr r3, [r7, #12] + 9487 01da 5B8D ldrh r3, [r3, #42] @ movhi + 9488 01dc 9BB2 uxth r3, r3 + 9489 .loc 1 4903 8 + 9490 01de 002B cmp r3, #0 + 9491 01e0 19D1 bne .L450 +4904:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4905:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + 9492 .loc 1 4905 11 + 9493 01e2 FB68 ldr r3, [r7, #12] + 9494 01e4 1B68 ldr r3, [r3] + 9495 01e6 5B68 ldr r3, [r3, #4] + 9496 01e8 03F00073 and r3, r3, #33554432 + 9497 .loc 1 4905 10 + 9498 01ec B3F1007F cmp r3, #33554432 + 9499 01f0 15D0 beq .L440 +4906:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Generate a stop condition in case of no transfer option */ +4908:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) + 9500 .loc 1 4908 17 + 9501 01f2 FB68 ldr r3, [r7, #12] + 9502 01f4 DB6A ldr r3, [r3, #44] + 9503 .loc 1 4908 12 + 9504 01f6 13F5803F cmn r3, #65536 + 9505 01fa 08D1 bne .L451 +4909:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Generate Stop */ +4911:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_STOP; + 9506 .loc 1 4911 15 + 9507 01fc FB68 ldr r3, [r7, #12] + 9508 01fe 1B68 ldr r3, [r3] + 9509 .loc 1 4911 25 + 9510 0200 5A68 ldr r2, [r3, #4] + 9511 .loc 1 4911 15 + 9512 0202 FB68 ldr r3, [r7, #12] + 9513 0204 1B68 ldr r3, [r3] + 9514 .loc 1 4911 31 + 9515 0206 42F48042 orr r2, r2, #16384 + 9516 020a 5A60 str r2, [r3, #4] + 9517 020c 07E0 b .L440 + 9518 .L451: +4912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4913:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +4914:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4915:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call I2C Master Sequential complete process */ +4916:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITMasterSeqCplt(hi2c); + 9519 .loc 1 4916 11 + 9520 020e F868 ldr r0, [r7, #12] + 9521 0210 FFF7FEFF bl I2C_ITMasterSeqCplt + 9522 0214 03E0 b .L440 + 9523 .L450: +4917:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4918:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4919:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4920:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +4921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + ARM GAS /tmp/cc5G5cqz.s page 255 + + +4922:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wrong size Status regarding TC flag event */ +4923:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +4924:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + 9524 .loc 1 4924 7 + 9525 0216 4021 movs r1, #64 + 9526 0218 F868 ldr r0, [r7, #12] + 9527 021a FFF7FEFF bl I2C_ITError + 9528 .L440: +4925:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4926:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +4928:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4929:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Nothing to do */ +4930:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4931:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4932:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ + 9529 .loc 1 4932 8 + 9530 021e 7B69 ldr r3, [r7, #20] + 9531 0220 5B09 lsrs r3, r3, #5 + 9532 0222 03F00103 and r3, r3, #1 + 9533 .loc 1 4932 6 + 9534 0226 002B cmp r3, #0 + 9535 0228 09D0 beq .L452 +4933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 9536 .loc 1 4933 8 + 9537 022a 7B68 ldr r3, [r7, #4] + 9538 022c 5B09 lsrs r3, r3, #5 + 9539 022e 03F00103 and r3, r3, #1 +4932:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 9540 .loc 1 4932 61 discriminator 1 + 9541 0232 002B cmp r3, #0 + 9542 0234 03D0 beq .L452 +4934:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4935:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call I2C Master complete process */ +4936:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITMasterCplt(hi2c, tmpITFlags); + 9543 .loc 1 4936 5 + 9544 0236 7969 ldr r1, [r7, #20] + 9545 0238 F868 ldr r0, [r7, #12] + 9546 023a FFF7FEFF bl I2C_ITMasterCplt + 9547 .L452: +4937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4939:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +4940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 9548 .loc 1 4940 3 + 9549 023e FB68 ldr r3, [r7, #12] + 9550 0240 0022 movs r2, #0 + 9551 0242 83F84020 strb r2, [r3, #64] +4941:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; + 9552 .loc 1 4942 10 + 9553 0246 0023 movs r3, #0 + 9554 .L438: +4943:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 9555 .loc 1 4943 1 + 9556 0248 1846 mov r0, r3 + 9557 024a 1837 adds r7, r7, #24 + ARM GAS /tmp/cc5G5cqz.s page 256 + + + 9558 .cfi_def_cfa_offset 8 + 9559 024c BD46 mov sp, r7 + 9560 .cfi_def_cfa_register 13 + 9561 @ sp needed + 9562 024e 80BD pop {r7, pc} + 9563 .cfi_endproc + 9564 .LFE179: + 9566 .section .text.I2C_Mem_ISR_IT,"ax",%progbits + 9567 .align 1 + 9568 .syntax unified + 9569 .thumb + 9570 .thumb_func + 9572 I2C_Mem_ISR_IT: + 9573 .LFB180: +4944:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +4946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with Interrupt. +4947:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +4948:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +4949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. +4950:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param ITSources Interrupt sources enabled. +4951:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +4952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +4953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, +4954:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t ITSources) +4955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9574 .loc 1 4955 1 + 9575 .cfi_startproc + 9576 @ args = 0, pretend = 0, frame = 24 + 9577 @ frame_needed = 1, uses_anonymous_args = 0 + 9578 0000 80B5 push {r7, lr} + 9579 .cfi_def_cfa_offset 8 + 9580 .cfi_offset 7, -8 + 9581 .cfi_offset 14, -4 + 9582 0002 88B0 sub sp, sp, #32 + 9583 .cfi_def_cfa_offset 40 + 9584 0004 02AF add r7, sp, #8 + 9585 .cfi_def_cfa 7, 32 + 9586 0006 F860 str r0, [r7, #12] + 9587 0008 B960 str r1, [r7, #8] + 9588 000a 7A60 str r2, [r7, #4] +4956:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t direction = I2C_GENERATE_START_WRITE; + 9589 .loc 1 4956 12 + 9590 000c 8F4B ldr r3, .L470 + 9591 000e 7B61 str r3, [r7, #20] +4957:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; + 9592 .loc 1 4957 12 + 9593 0010 BB68 ldr r3, [r7, #8] + 9594 0012 3B61 str r3, [r7, #16] +4958:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +4960:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); + 9595 .loc 1 4960 3 + 9596 0014 FB68 ldr r3, [r7, #12] + 9597 0016 93F84030 ldrb r3, [r3, #64] @ zero_extendqisi2 + 9598 001a 012B cmp r3, #1 + 9599 001c 01D1 bne .L454 + ARM GAS /tmp/cc5G5cqz.s page 257 + + + 9600 .loc 1 4960 3 is_stmt 0 discriminator 1 + 9601 001e 0223 movs r3, #2 + 9602 .loc 1 4960 3 + 9603 0020 10E1 b .L455 + 9604 .L454: + 9605 .loc 1 4960 3 discriminator 2 + 9606 0022 FB68 ldr r3, [r7, #12] + 9607 0024 0122 movs r2, #1 + 9608 0026 83F84020 strb r2, [r3, #64] +4961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + 9609 .loc 1 4962 8 is_stmt 1 + 9610 002a 3B69 ldr r3, [r7, #16] + 9611 002c 1B09 lsrs r3, r3, #4 + 9612 002e 03F00103 and r3, r3, #1 + 9613 .loc 1 4962 6 + 9614 0032 002B cmp r3, #0 + 9615 0034 13D0 beq .L456 +4963:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 9616 .loc 1 4963 8 + 9617 0036 7B68 ldr r3, [r7, #4] + 9618 0038 1B09 lsrs r3, r3, #4 + 9619 003a 03F00103 and r3, r3, #1 +4962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 9620 .loc 1 4962 58 discriminator 1 + 9621 003e 002B cmp r3, #0 + 9622 0040 0DD0 beq .L456 +4964:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4965:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear NACK Flag */ +4966:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + 9623 .loc 1 4966 5 + 9624 0042 FB68 ldr r3, [r7, #12] + 9625 0044 1B68 ldr r3, [r3] + 9626 0046 1022 movs r2, #16 + 9627 0048 DA61 str r2, [r3, #28] +4967:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set corresponding Error Code */ +4969:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* No need to generate STOP, it is automatically done */ +4970:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Error callback will be send during stop flag treatment */ +4971:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + 9628 .loc 1 4971 9 + 9629 004a FB68 ldr r3, [r7, #12] + 9630 004c 5B6C ldr r3, [r3, #68] + 9631 .loc 1 4971 21 + 9632 004e 43F00402 orr r2, r3, #4 + 9633 0052 FB68 ldr r3, [r7, #12] + 9634 0054 5A64 str r2, [r3, #68] +4972:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4973:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Flush TX register */ +4974:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); + 9635 .loc 1 4974 5 + 9636 0056 F868 ldr r0, [r7, #12] + 9637 0058 FFF7FEFF bl I2C_Flush_TXDR + 9638 005c DDE0 b .L457 + 9639 .L456: +4975:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4976:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ + ARM GAS /tmp/cc5G5cqz.s page 258 + + + 9640 .loc 1 4976 13 + 9641 005e 3B69 ldr r3, [r7, #16] + 9642 0060 9B08 lsrs r3, r3, #2 + 9643 0062 03F00103 and r3, r3, #1 + 9644 .loc 1 4976 11 + 9645 0066 002B cmp r3, #0 + 9646 0068 23D0 beq .L458 +4977:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + 9647 .loc 1 4977 13 + 9648 006a 7B68 ldr r3, [r7, #4] + 9649 006c 9B08 lsrs r3, r3, #2 + 9650 006e 03F00103 and r3, r3, #1 +4976:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + 9651 .loc 1 4976 65 discriminator 1 + 9652 0072 002B cmp r3, #0 + 9653 0074 1DD0 beq .L458 +4978:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4979:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Remove RXNE flag on temporary variable as read done */ +4980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmpITFlags &= ~I2C_FLAG_RXNE; + 9654 .loc 1 4980 16 + 9655 0076 3B69 ldr r3, [r7, #16] + 9656 0078 23F00403 bic r3, r3, #4 + 9657 007c 3B61 str r3, [r7, #16] +4981:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4982:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Read data from RXDR */ +4983:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + 9658 .loc 1 4983 36 + 9659 007e FB68 ldr r3, [r7, #12] + 9660 0080 1B68 ldr r3, [r3] + 9661 .loc 1 4983 46 + 9662 0082 5A6A ldr r2, [r3, #36] + 9663 .loc 1 4983 10 + 9664 0084 FB68 ldr r3, [r7, #12] + 9665 0086 5B6A ldr r3, [r3, #36] + 9666 .loc 1 4983 23 + 9667 0088 D2B2 uxtb r2, r2 + 9668 .loc 1 4983 21 + 9669 008a 1A70 strb r2, [r3] +4984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4985:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Increment Buffer pointer */ +4986:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr++; + 9670 .loc 1 4986 9 + 9671 008c FB68 ldr r3, [r7, #12] + 9672 008e 5B6A ldr r3, [r3, #36] + 9673 .loc 1 4986 19 + 9674 0090 5A1C adds r2, r3, #1 + 9675 0092 FB68 ldr r3, [r7, #12] + 9676 0094 5A62 str r2, [r3, #36] +4987:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4988:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize--; + 9677 .loc 1 4988 9 + 9678 0096 FB68 ldr r3, [r7, #12] + 9679 0098 1B8D ldrh r3, [r3, #40] + 9680 .loc 1 4988 19 + 9681 009a 013B subs r3, r3, #1 + 9682 009c 9AB2 uxth r2, r3 + 9683 009e FB68 ldr r3, [r7, #12] + ARM GAS /tmp/cc5G5cqz.s page 259 + + + 9684 00a0 1A85 strh r2, [r3, #40] @ movhi +4989:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount--; + 9685 .loc 1 4989 9 + 9686 00a2 FB68 ldr r3, [r7, #12] + 9687 00a4 5B8D ldrh r3, [r3, #42] @ movhi + 9688 00a6 9BB2 uxth r3, r3 + 9689 .loc 1 4989 20 + 9690 00a8 013B subs r3, r3, #1 + 9691 00aa 9AB2 uxth r2, r3 + 9692 00ac FB68 ldr r3, [r7, #12] + 9693 00ae 5A85 strh r2, [r3, #42] @ movhi + 9694 00b0 B3E0 b .L457 + 9695 .L458: +4990:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +4991:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + 9696 .loc 1 4991 13 + 9697 00b2 3B69 ldr r3, [r7, #16] + 9698 00b4 5B08 lsrs r3, r3, #1 + 9699 00b6 03F00103 and r3, r3, #1 + 9700 .loc 1 4991 11 + 9701 00ba 002B cmp r3, #0 + 9702 00bc 2DD0 beq .L459 +4992:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + 9703 .loc 1 4992 13 + 9704 00be 7B68 ldr r3, [r7, #4] + 9705 00c0 5B08 lsrs r3, r3, #1 + 9706 00c2 03F00103 and r3, r3, #1 +4991:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + 9707 .loc 1 4991 65 discriminator 1 + 9708 00c6 002B cmp r3, #0 + 9709 00c8 27D0 beq .L459 +4993:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4994:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->Memaddress == 0xFFFFFFFFU) + 9710 .loc 1 4994 13 + 9711 00ca FB68 ldr r3, [r7, #12] + 9712 00cc 1B6D ldr r3, [r3, #80] + 9713 .loc 1 4994 8 + 9714 00ce B3F1FF3F cmp r3, #-1 + 9715 00d2 18D1 bne .L460 +4995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +4996:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Write data to TXDR */ +4997:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->TXDR = *hi2c->pBuffPtr; + 9716 .loc 1 4997 35 + 9717 00d4 FB68 ldr r3, [r7, #12] + 9718 00d6 5B6A ldr r3, [r3, #36] + 9719 .loc 1 4997 30 + 9720 00d8 1A78 ldrb r2, [r3] @ zero_extendqisi2 + 9721 .loc 1 4997 11 + 9722 00da FB68 ldr r3, [r7, #12] + 9723 00dc 1B68 ldr r3, [r3] + 9724 .loc 1 4997 28 + 9725 00de 9A62 str r2, [r3, #40] +4998:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +4999:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Increment Buffer pointer */ +5000:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr++; + 9726 .loc 1 5000 11 + 9727 00e0 FB68 ldr r3, [r7, #12] + ARM GAS /tmp/cc5G5cqz.s page 260 + + + 9728 00e2 5B6A ldr r3, [r3, #36] + 9729 .loc 1 5000 21 + 9730 00e4 5A1C adds r2, r3, #1 + 9731 00e6 FB68 ldr r3, [r7, #12] + 9732 00e8 5A62 str r2, [r3, #36] +5001:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5002:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize--; + 9733 .loc 1 5002 11 + 9734 00ea FB68 ldr r3, [r7, #12] + 9735 00ec 1B8D ldrh r3, [r3, #40] + 9736 .loc 1 5002 21 + 9737 00ee 013B subs r3, r3, #1 + 9738 00f0 9AB2 uxth r2, r3 + 9739 00f2 FB68 ldr r3, [r7, #12] + 9740 00f4 1A85 strh r2, [r3, #40] @ movhi +5003:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount--; + 9741 .loc 1 5003 11 + 9742 00f6 FB68 ldr r3, [r7, #12] + 9743 00f8 5B8D ldrh r3, [r3, #42] @ movhi + 9744 00fa 9BB2 uxth r3, r3 + 9745 .loc 1 5003 22 + 9746 00fc 013B subs r3, r3, #1 + 9747 00fe 9AB2 uxth r2, r3 + 9748 0100 FB68 ldr r3, [r7, #12] + 9749 0102 5A85 strh r2, [r3, #42] @ movhi +4994:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9750 .loc 1 4994 8 + 9751 0104 89E0 b .L457 + 9752 .L460: +5004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5005:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5006:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Write LSB part of Memory Address */ +5008:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->TXDR = hi2c->Memaddress; + 9753 .loc 1 5008 11 + 9754 0106 FB68 ldr r3, [r7, #12] + 9755 0108 1B68 ldr r3, [r3] + 9756 .loc 1 5008 34 + 9757 010a FA68 ldr r2, [r7, #12] + 9758 010c 126D ldr r2, [r2, #80] + 9759 .loc 1 5008 28 + 9760 010e 9A62 str r2, [r3, #40] +5009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5010:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Reset Memaddress content */ +5011:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Memaddress = 0xFFFFFFFFU; + 9761 .loc 1 5011 24 + 9762 0110 FB68 ldr r3, [r7, #12] + 9763 0112 4FF0FF32 mov r2, #-1 + 9764 0116 1A65 str r2, [r3, #80] +4994:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9765 .loc 1 4994 8 + 9766 0118 7FE0 b .L457 + 9767 .L459: +5012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5013:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5014:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \ + 9768 .loc 1 5014 13 + ARM GAS /tmp/cc5G5cqz.s page 261 + + + 9769 011a 3B69 ldr r3, [r7, #16] + 9770 011c DB09 lsrs r3, r3, #7 + 9771 011e 03F00103 and r3, r3, #1 + 9772 .loc 1 5014 11 + 9773 0122 002B cmp r3, #0 + 9774 0124 3DD0 beq .L462 +5015:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 9775 .loc 1 5015 13 + 9776 0126 7B68 ldr r3, [r7, #4] + 9777 0128 9B09 lsrs r3, r3, #6 + 9778 012a 03F00103 and r3, r3, #1 +5014:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 9779 .loc 1 5014 64 discriminator 1 + 9780 012e 002B cmp r3, #0 + 9781 0130 37D0 beq .L462 +5016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5017:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + 9782 .loc 1 5017 14 + 9783 0132 FB68 ldr r3, [r7, #12] + 9784 0134 5B8D ldrh r3, [r3, #42] @ movhi + 9785 0136 9BB2 uxth r3, r3 + 9786 .loc 1 5017 8 + 9787 0138 002B cmp r3, #0 + 9788 013a 2CD0 beq .L463 + 9789 .loc 1 5017 41 discriminator 1 + 9790 013c FB68 ldr r3, [r7, #12] + 9791 013e 1B8D ldrh r3, [r3, #40] + 9792 .loc 1 5017 33 discriminator 1 + 9793 0140 002B cmp r3, #0 + 9794 0142 28D1 bne .L463 +5018:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5019:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) + 9795 .loc 1 5019 15 + 9796 0144 FB68 ldr r3, [r7, #12] + 9797 0146 5B8D ldrh r3, [r3, #42] @ movhi + 9798 0148 9BB2 uxth r3, r3 + 9799 .loc 1 5019 10 + 9800 014a FF2B cmp r3, #255 + 9801 014c 10D9 bls .L464 +5020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5021:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; + 9802 .loc 1 5021 24 + 9803 014e FB68 ldr r3, [r7, #12] + 9804 0150 FF22 movs r2, #255 + 9805 0152 1A85 strh r2, [r3, #40] @ movhi +5022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + 9806 .loc 1 5022 48 + 9807 0154 FB68 ldr r3, [r7, #12] + 9808 0156 DB6C ldr r3, [r3, #76] + 9809 .loc 1 5022 9 + 9810 0158 99B2 uxth r1, r3 + 9811 .loc 1 5022 75 + 9812 015a FB68 ldr r3, [r7, #12] + 9813 015c 1B8D ldrh r3, [r3, #40] + 9814 .loc 1 5022 9 + 9815 015e DAB2 uxtb r2, r3 + 9816 0160 0023 movs r3, #0 + ARM GAS /tmp/cc5G5cqz.s page 262 + + + 9817 0162 0093 str r3, [sp] + 9818 0164 4FF08073 mov r3, #16777216 + 9819 0168 F868 ldr r0, [r7, #12] + 9820 016a FFF7FEFF bl I2C_TransferConfig +5019:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9821 .loc 1 5019 10 + 9822 016e 17E0 b .L466 + 9823 .L464: +5023:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_RELOAD_MODE, I2C_NO_STARTSTOP); +5024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5025:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 9824 .loc 1 5027 30 + 9825 0170 FB68 ldr r3, [r7, #12] + 9826 0172 5B8D ldrh r3, [r3, #42] @ movhi + 9827 0174 9AB2 uxth r2, r3 + 9828 .loc 1 5027 24 + 9829 0176 FB68 ldr r3, [r7, #12] + 9830 0178 1A85 strh r2, [r3, #40] @ movhi +5028:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + 9831 .loc 1 5028 48 + 9832 017a FB68 ldr r3, [r7, #12] + 9833 017c DB6C ldr r3, [r3, #76] + 9834 .loc 1 5028 9 + 9835 017e 99B2 uxth r1, r3 + 9836 .loc 1 5028 75 + 9837 0180 FB68 ldr r3, [r7, #12] + 9838 0182 1B8D ldrh r3, [r3, #40] + 9839 .loc 1 5028 9 + 9840 0184 DAB2 uxtb r2, r3 + 9841 0186 0023 movs r3, #0 + 9842 0188 0093 str r3, [sp] + 9843 018a 4FF00073 mov r3, #33554432 + 9844 018e F868 ldr r0, [r7, #12] + 9845 0190 FFF7FEFF bl I2C_TransferConfig +5019:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9846 .loc 1 5019 10 + 9847 0194 04E0 b .L466 + 9848 .L463: +5029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); +5030:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5031:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5032:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5033:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wrong size Status regarding TCR flag event */ +5035:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5036:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + 9849 .loc 1 5036 7 + 9850 0196 4021 movs r1, #64 + 9851 0198 F868 ldr r0, [r7, #12] + 9852 019a FFF7FEFF bl I2C_ITError +5017:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9853 .loc 1 5017 8 + 9854 019e 3CE0 b .L457 + 9855 .L466: + 9856 01a0 3BE0 b .L457 + ARM GAS /tmp/cc5G5cqz.s page 263 + + + 9857 .L462: +5037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5038:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5039:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \ + 9858 .loc 1 5039 13 + 9859 01a2 3B69 ldr r3, [r7, #16] + 9860 01a4 9B09 lsrs r3, r3, #6 + 9861 01a6 03F00103 and r3, r3, #1 + 9862 .loc 1 5039 11 + 9863 01aa 002B cmp r3, #0 + 9864 01ac 35D0 beq .L457 +5040:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 9865 .loc 1 5040 13 + 9866 01ae 7B68 ldr r3, [r7, #4] + 9867 01b0 9B09 lsrs r3, r3, #6 + 9868 01b2 03F00103 and r3, r3, #1 +5039:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 9869 .loc 1 5039 63 discriminator 1 + 9870 01b6 002B cmp r3, #0 + 9871 01b8 2FD0 beq .L457 +5041:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + 9872 .loc 1 5042 13 + 9873 01ba FB68 ldr r3, [r7, #12] + 9874 01bc 93F84130 ldrb r3, [r3, #65] + 9875 01c0 DBB2 uxtb r3, r3 + 9876 .loc 1 5042 8 + 9877 01c2 222B cmp r3, #34 + 9878 01c4 01D1 bne .L467 +5043:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** direction = I2C_GENERATE_START_READ; + 9879 .loc 1 5044 17 + 9880 01c6 224B ldr r3, .L470+4 + 9881 01c8 7B61 str r3, [r7, #20] + 9882 .L467: +5045:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5046:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) + 9883 .loc 1 5047 13 + 9884 01ca FB68 ldr r3, [r7, #12] + 9885 01cc 5B8D ldrh r3, [r3, #42] @ movhi + 9886 01ce 9BB2 uxth r3, r3 + 9887 .loc 1 5047 8 + 9888 01d0 FF2B cmp r3, #255 + 9889 01d2 10D9 bls .L468 +5048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5049:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; + 9890 .loc 1 5049 22 + 9891 01d4 FB68 ldr r3, [r7, #12] + 9892 01d6 FF22 movs r2, #255 + 9893 01d8 1A85 strh r2, [r3, #40] @ movhi +5050:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ +5052:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + 9894 .loc 1 5052 46 + 9895 01da FB68 ldr r3, [r7, #12] + 9896 01dc DB6C ldr r3, [r3, #76] + ARM GAS /tmp/cc5G5cqz.s page 264 + + + 9897 .loc 1 5052 7 + 9898 01de 99B2 uxth r1, r3 + 9899 .loc 1 5052 73 + 9900 01e0 FB68 ldr r3, [r7, #12] + 9901 01e2 1B8D ldrh r3, [r3, #40] + 9902 .loc 1 5052 7 + 9903 01e4 DAB2 uxtb r2, r3 + 9904 01e6 7B69 ldr r3, [r7, #20] + 9905 01e8 0093 str r3, [sp] + 9906 01ea 4FF08073 mov r3, #16777216 + 9907 01ee F868 ldr r0, [r7, #12] + 9908 01f0 FFF7FEFF bl I2C_TransferConfig + 9909 01f4 11E0 b .L457 + 9910 .L468: +5053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_RELOAD_MODE, direction); +5054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5055:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5057:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 9911 .loc 1 5057 28 + 9912 01f6 FB68 ldr r3, [r7, #12] + 9913 01f8 5B8D ldrh r3, [r3, #42] @ movhi + 9914 01fa 9AB2 uxth r2, r3 + 9915 .loc 1 5057 22 + 9916 01fc FB68 ldr r3, [r7, #12] + 9917 01fe 1A85 strh r2, [r3, #40] @ movhi +5058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set NBYTES to write and generate RESTART */ +5060:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + 9918 .loc 1 5060 46 + 9919 0200 FB68 ldr r3, [r7, #12] + 9920 0202 DB6C ldr r3, [r3, #76] + 9921 .loc 1 5060 7 + 9922 0204 99B2 uxth r1, r3 + 9923 .loc 1 5060 73 + 9924 0206 FB68 ldr r3, [r7, #12] + 9925 0208 1B8D ldrh r3, [r3, #40] + 9926 .loc 1 5060 7 + 9927 020a DAB2 uxtb r2, r3 + 9928 020c 7B69 ldr r3, [r7, #20] + 9929 020e 0093 str r3, [sp] + 9930 0210 4FF00073 mov r3, #33554432 + 9931 0214 F868 ldr r0, [r7, #12] + 9932 0216 FFF7FEFF bl I2C_TransferConfig + 9933 .L457: +5061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_AUTOEND_MODE, direction); +5062:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5063:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5064:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5066:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Nothing to do */ +5067:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5069:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ + 9934 .loc 1 5069 8 + 9935 021a 3B69 ldr r3, [r7, #16] + 9936 021c 5B09 lsrs r3, r3, #5 + ARM GAS /tmp/cc5G5cqz.s page 265 + + + 9937 021e 03F00103 and r3, r3, #1 + 9938 .loc 1 5069 6 + 9939 0222 002B cmp r3, #0 + 9940 0224 09D0 beq .L469 +5070:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 9941 .loc 1 5070 8 + 9942 0226 7B68 ldr r3, [r7, #4] + 9943 0228 5B09 lsrs r3, r3, #5 + 9944 022a 03F00103 and r3, r3, #1 +5069:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 9945 .loc 1 5069 61 discriminator 1 + 9946 022e 002B cmp r3, #0 + 9947 0230 03D0 beq .L469 +5071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5072:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call I2C Master complete process */ +5073:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITMasterCplt(hi2c, tmpITFlags); + 9948 .loc 1 5073 5 + 9949 0232 3969 ldr r1, [r7, #16] + 9950 0234 F868 ldr r0, [r7, #12] + 9951 0236 FFF7FEFF bl I2C_ITMasterCplt + 9952 .L469: +5074:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5075:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5076:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +5077:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 9953 .loc 1 5077 3 + 9954 023a FB68 ldr r3, [r7, #12] + 9955 023c 0022 movs r2, #0 + 9956 023e 83F84020 strb r2, [r3, #64] +5078:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5079:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; + 9957 .loc 1 5079 10 + 9958 0242 0023 movs r3, #0 + 9959 .L455: +5080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 9960 .loc 1 5080 1 + 9961 0244 1846 mov r0, r3 + 9962 0246 1837 adds r7, r7, #24 + 9963 .cfi_def_cfa_offset 8 + 9964 0248 BD46 mov sp, r7 + 9965 .cfi_def_cfa_register 13 + 9966 @ sp needed + 9967 024a 80BD pop {r7, pc} + 9968 .L471: + 9969 .align 2 + 9970 .L470: + 9971 024c 00200080 .word -2147475456 + 9972 0250 00240080 .word -2147474432 + 9973 .cfi_endproc + 9974 .LFE180: + 9976 .section .text.I2C_Slave_ISR_IT,"ax",%progbits + 9977 .align 1 + 9978 .syntax unified + 9979 .thumb + 9980 .thumb_func + 9982 I2C_Slave_ISR_IT: + 9983 .LFB181: + ARM GAS /tmp/cc5G5cqz.s page 266 + + +5081:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +5083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt. +5084:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +5085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +5086:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. +5087:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param ITSources Interrupt sources enabled. +5088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +5089:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +5090:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, +5091:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t ITSources) +5092:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 9984 .loc 1 5092 1 + 9985 .cfi_startproc + 9986 @ args = 0, pretend = 0, frame = 24 + 9987 @ frame_needed = 1, uses_anonymous_args = 0 + 9988 0000 80B5 push {r7, lr} + 9989 .cfi_def_cfa_offset 8 + 9990 .cfi_offset 7, -8 + 9991 .cfi_offset 14, -4 + 9992 0002 86B0 sub sp, sp, #24 + 9993 .cfi_def_cfa_offset 32 + 9994 0004 00AF add r7, sp, #0 + 9995 .cfi_def_cfa_register 7 + 9996 0006 F860 str r0, [r7, #12] + 9997 0008 B960 str r1, [r7, #8] + 9998 000a 7A60 str r2, [r7, #4] +5093:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; + 9999 .loc 1 5093 12 + 10000 000c FB68 ldr r3, [r7, #12] + 10001 000e DB6A ldr r3, [r3, #44] + 10002 0010 7B61 str r3, [r7, #20] +5094:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; + 10003 .loc 1 5094 12 + 10004 0012 BB68 ldr r3, [r7, #8] + 10005 0014 3B61 str r3, [r7, #16] +5095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5096:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process locked */ +5097:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); + 10006 .loc 1 5097 3 + 10007 0016 FB68 ldr r3, [r7, #12] + 10008 0018 93F84030 ldrb r3, [r3, #64] @ zero_extendqisi2 + 10009 001c 012B cmp r3, #1 + 10010 001e 01D1 bne .L473 + 10011 .loc 1 5097 3 is_stmt 0 discriminator 1 + 10012 0020 0223 movs r3, #2 + 10013 .loc 1 5097 3 + 10014 0022 ECE0 b .L474 + 10015 .L473: + 10016 .loc 1 5097 3 discriminator 2 + 10017 0024 FB68 ldr r3, [r7, #12] + 10018 0026 0122 movs r2, #1 + 10019 0028 83F84020 strb r2, [r3, #64] +5098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5099:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check if STOPF is set */ +5100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ + 10020 .loc 1 5100 8 is_stmt 1 + ARM GAS /tmp/cc5G5cqz.s page 267 + + + 10021 002c 3B69 ldr r3, [r7, #16] + 10022 002e 5B09 lsrs r3, r3, #5 + 10023 0030 03F00103 and r3, r3, #1 + 10024 .loc 1 5100 6 + 10025 0034 002B cmp r3, #0 + 10026 0036 09D0 beq .L475 +5101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 10027 .loc 1 5101 8 + 10028 0038 7B68 ldr r3, [r7, #4] + 10029 003a 5B09 lsrs r3, r3, #5 + 10030 003c 03F00103 and r3, r3, #1 +5100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 10031 .loc 1 5100 61 discriminator 1 + 10032 0040 002B cmp r3, #0 + 10033 0042 03D0 beq .L475 +5102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call I2C Slave complete process */ +5104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITSlaveCplt(hi2c, tmpITFlags); + 10034 .loc 1 5104 5 + 10035 0044 3969 ldr r1, [r7, #16] + 10036 0046 F868 ldr r0, [r7, #12] + 10037 0048 FFF7FEFF bl I2C_ITSlaveCplt + 10038 .L475: +5105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + 10039 .loc 1 5107 8 + 10040 004c 3B69 ldr r3, [r7, #16] + 10041 004e 1B09 lsrs r3, r3, #4 + 10042 0050 03F00103 and r3, r3, #1 + 10043 .loc 1 5107 6 + 10044 0054 002B cmp r3, #0 + 10045 0056 4DD0 beq .L476 +5108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 10046 .loc 1 5108 8 + 10047 0058 7B68 ldr r3, [r7, #4] + 10048 005a 1B09 lsrs r3, r3, #4 + 10049 005c 03F00103 and r3, r3, #1 +5107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 10050 .loc 1 5107 58 discriminator 1 + 10051 0060 002B cmp r3, #0 + 10052 0062 47D0 beq .L476 +5109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check that I2C transfer finished */ +5111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ +5112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Mean XferCount == 0*/ +5113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* So clear Flag NACKF only */ +5114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount == 0U) + 10053 .loc 1 5114 13 + 10054 0064 FB68 ldr r3, [r7, #12] + 10055 0066 5B8D ldrh r3, [r3, #42] @ movhi + 10056 0068 9BB2 uxth r3, r3 + 10057 .loc 1 5114 8 + 10058 006a 002B cmp r3, #0 + 10059 006c 28D1 bne .L477 +5115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) + ARM GAS /tmp/cc5G5cqz.s page 268 + + + 10060 .loc 1 5116 16 + 10061 006e FB68 ldr r3, [r7, #12] + 10062 0070 93F84130 ldrb r3, [r3, #65] + 10063 0074 DBB2 uxtb r3, r3 + 10064 .loc 1 5116 10 + 10065 0076 282B cmp r3, #40 + 10066 0078 08D1 bne .L478 + 10067 .loc 1 5116 49 discriminator 1 + 10068 007a 7B69 ldr r3, [r7, #20] + 10069 007c B3F1007F cmp r3, #33554432 + 10070 0080 04D1 bne .L478 +5117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for +5118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** Warning[Pa134]: left and right operands are identical */ +5119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call I2C Listen complete process */ +5121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITListenCplt(hi2c, tmpITFlags); + 10071 .loc 1 5121 9 + 10072 0082 3969 ldr r1, [r7, #16] + 10073 0084 F868 ldr r0, [r7, #12] + 10074 0086 FFF7FEFF bl I2C_ITListenCplt + 10075 008a 32E0 b .L481 + 10076 .L478: +5122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME) + 10077 .loc 1 5123 21 + 10078 008c FB68 ldr r3, [r7, #12] + 10079 008e 93F84130 ldrb r3, [r3, #65] + 10080 0092 DBB2 uxtb r3, r3 + 10081 .loc 1 5123 15 + 10082 0094 292B cmp r3, #41 + 10083 0096 0ED1 bne .L480 + 10084 .loc 1 5123 62 discriminator 1 + 10085 0098 7B69 ldr r3, [r7, #20] + 10086 009a 13F5803F cmn r3, #65536 + 10087 009e 0AD0 beq .L480 +5124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear NACK Flag */ +5126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + 10088 .loc 1 5126 9 + 10089 00a0 FB68 ldr r3, [r7, #12] + 10090 00a2 1B68 ldr r3, [r3] + 10091 00a4 1022 movs r2, #16 + 10092 00a6 DA61 str r2, [r3, #28] +5127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Flush TX register */ +5129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); + 10093 .loc 1 5129 9 + 10094 00a8 F868 ldr r0, [r7, #12] + 10095 00aa FFF7FEFF bl I2C_Flush_TXDR +5130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Last Byte is Transmitted */ +5132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call I2C Slave Sequential complete process */ +5133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITSlaveSeqCplt(hi2c); + 10096 .loc 1 5133 9 + 10097 00ae F868 ldr r0, [r7, #12] + 10098 00b0 FFF7FEFF bl I2C_ITSlaveSeqCplt + 10099 00b4 1DE0 b .L481 + ARM GAS /tmp/cc5G5cqz.s page 269 + + + 10100 .L480: +5134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear NACK Flag */ +5138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + 10101 .loc 1 5138 9 + 10102 00b6 FB68 ldr r3, [r7, #12] + 10103 00b8 1B68 ldr r3, [r3] + 10104 00ba 1022 movs r2, #16 + 10105 00bc DA61 str r2, [r3, #28] +5114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10106 .loc 1 5114 8 + 10107 00be 96E0 b .L490 + 10108 .L477: +5139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ +5144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear NACK Flag */ +5145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + 10109 .loc 1 5145 7 + 10110 00c0 FB68 ldr r3, [r7, #12] + 10111 00c2 1B68 ldr r3, [r3] + 10112 00c4 1022 movs r2, #16 + 10113 00c6 DA61 str r2, [r3, #28] +5146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set ErrorCode corresponding to a Non-Acknowledge */ +5148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + 10114 .loc 1 5148 11 + 10115 00c8 FB68 ldr r3, [r7, #12] + 10116 00ca 5B6C ldr r3, [r3, #68] + 10117 .loc 1 5148 23 + 10118 00cc 43F00402 orr r2, r3, #4 + 10119 00d0 FB68 ldr r3, [r7, #12] + 10120 00d2 5A64 str r2, [r3, #68] +5149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) + 10121 .loc 1 5150 10 + 10122 00d4 7B69 ldr r3, [r7, #20] + 10123 00d6 002B cmp r3, #0 + 10124 00d8 04D0 beq .L482 + 10125 .loc 1 5150 43 discriminator 1 + 10126 00da 7B69 ldr r3, [r7, #20] + 10127 00dc B3F1807F cmp r3, #16777216 + 10128 00e0 40F08580 bne .L490 + 10129 .L482: +5151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITError(hi2c, hi2c->ErrorCode); + 10130 .loc 1 5153 31 + 10131 00e4 FB68 ldr r3, [r7, #12] + 10132 00e6 5B6C ldr r3, [r3, #68] + 10133 .loc 1 5153 9 + 10134 00e8 1946 mov r1, r3 + 10135 00ea F868 ldr r0, [r7, #12] + ARM GAS /tmp/cc5G5cqz.s page 270 + + + 10136 00ec FFF7FEFF bl I2C_ITError +5114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10137 .loc 1 5114 8 + 10138 00f0 7DE0 b .L490 + 10139 .L481: + 10140 00f2 7CE0 b .L490 + 10141 .L476: +5154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ + 10142 .loc 1 5157 13 + 10143 00f4 3B69 ldr r3, [r7, #16] + 10144 00f6 9B08 lsrs r3, r3, #2 + 10145 00f8 03F00103 and r3, r3, #1 + 10146 .loc 1 5157 11 + 10147 00fc 002B cmp r3, #0 + 10148 00fe 30D0 beq .L484 +5158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + 10149 .loc 1 5158 13 + 10150 0100 7B68 ldr r3, [r7, #4] + 10151 0102 9B08 lsrs r3, r3, #2 + 10152 0104 03F00103 and r3, r3, #1 +5157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + 10153 .loc 1 5157 65 discriminator 1 + 10154 0108 002B cmp r3, #0 + 10155 010a 2AD0 beq .L484 +5159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > 0U) + 10156 .loc 1 5160 13 + 10157 010c FB68 ldr r3, [r7, #12] + 10158 010e 5B8D ldrh r3, [r3, #42] @ movhi + 10159 0110 9BB2 uxth r3, r3 + 10160 .loc 1 5160 8 + 10161 0112 002B cmp r3, #0 + 10162 0114 18D0 beq .L485 +5161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Read data from RXDR */ +5163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + 10163 .loc 1 5163 38 + 10164 0116 FB68 ldr r3, [r7, #12] + 10165 0118 1B68 ldr r3, [r3] + 10166 .loc 1 5163 48 + 10167 011a 5A6A ldr r2, [r3, #36] + 10168 .loc 1 5163 12 + 10169 011c FB68 ldr r3, [r7, #12] + 10170 011e 5B6A ldr r3, [r3, #36] + 10171 .loc 1 5163 25 + 10172 0120 D2B2 uxtb r2, r2 + 10173 .loc 1 5163 23 + 10174 0122 1A70 strb r2, [r3] +5164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Increment Buffer pointer */ +5166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr++; + 10175 .loc 1 5166 11 + 10176 0124 FB68 ldr r3, [r7, #12] + 10177 0126 5B6A ldr r3, [r3, #36] + ARM GAS /tmp/cc5G5cqz.s page 271 + + + 10178 .loc 1 5166 21 + 10179 0128 5A1C adds r2, r3, #1 + 10180 012a FB68 ldr r3, [r7, #12] + 10181 012c 5A62 str r2, [r3, #36] +5167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize--; + 10182 .loc 1 5168 11 + 10183 012e FB68 ldr r3, [r7, #12] + 10184 0130 1B8D ldrh r3, [r3, #40] + 10185 .loc 1 5168 21 + 10186 0132 013B subs r3, r3, #1 + 10187 0134 9AB2 uxth r2, r3 + 10188 0136 FB68 ldr r3, [r7, #12] + 10189 0138 1A85 strh r2, [r3, #40] @ movhi +5169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount--; + 10190 .loc 1 5169 11 + 10191 013a FB68 ldr r3, [r7, #12] + 10192 013c 5B8D ldrh r3, [r3, #42] @ movhi + 10193 013e 9BB2 uxth r3, r3 + 10194 .loc 1 5169 22 + 10195 0140 013B subs r3, r3, #1 + 10196 0142 9AB2 uxth r2, r3 + 10197 0144 FB68 ldr r3, [r7, #12] + 10198 0146 5A85 strh r2, [r3, #42] @ movhi + 10199 .L485: +5170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->XferCount == 0U) && \ + 10200 .loc 1 5172 14 + 10201 0148 FB68 ldr r3, [r7, #12] + 10202 014a 5B8D ldrh r3, [r3, #42] @ movhi + 10203 014c 9BB2 uxth r3, r3 + 10204 .loc 1 5172 8 + 10205 014e 002B cmp r3, #0 + 10206 0150 4FD1 bne .L491 + 10207 .loc 1 5172 33 discriminator 1 + 10208 0152 7B69 ldr r3, [r7, #20] + 10209 0154 13F5803F cmn r3, #65536 + 10210 0158 4BD0 beq .L491 +5173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) +5174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call I2C Slave Sequential complete process */ +5176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITSlaveSeqCplt(hi2c); + 10211 .loc 1 5176 7 + 10212 015a F868 ldr r0, [r7, #12] + 10213 015c FFF7FEFF bl I2C_ITSlaveSeqCplt +5172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 10214 .loc 1 5172 8 + 10215 0160 47E0 b .L491 + 10216 .L484: +5177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \ + 10217 .loc 1 5179 13 + 10218 0162 3B69 ldr r3, [r7, #16] + 10219 0164 DB08 lsrs r3, r3, #3 + 10220 0166 03F00103 and r3, r3, #1 + ARM GAS /tmp/cc5G5cqz.s page 272 + + + 10221 .loc 1 5179 11 + 10222 016a 002B cmp r3, #0 + 10223 016c 0AD0 beq .L487 +5180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + 10224 .loc 1 5180 13 + 10225 016e 7B68 ldr r3, [r7, #4] + 10226 0170 DB08 lsrs r3, r3, #3 + 10227 0172 03F00103 and r3, r3, #1 +5179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + 10228 .loc 1 5179 65 discriminator 1 + 10229 0176 002B cmp r3, #0 + 10230 0178 04D0 beq .L487 +5181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITAddrCplt(hi2c, tmpITFlags); + 10231 .loc 1 5182 5 + 10232 017a 3969 ldr r1, [r7, #16] + 10233 017c F868 ldr r0, [r7, #12] + 10234 017e FFF7FEFF bl I2C_ITAddrCplt + 10235 0182 37E0 b .L483 + 10236 .L487: +5183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + 10237 .loc 1 5184 13 + 10238 0184 3B69 ldr r3, [r7, #16] + 10239 0186 5B08 lsrs r3, r3, #1 + 10240 0188 03F00103 and r3, r3, #1 + 10241 .loc 1 5184 11 + 10242 018c 002B cmp r3, #0 + 10243 018e 31D0 beq .L483 +5185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + 10244 .loc 1 5185 13 + 10245 0190 7B68 ldr r3, [r7, #4] + 10246 0192 5B08 lsrs r3, r3, #1 + 10247 0194 03F00103 and r3, r3, #1 +5184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + 10248 .loc 1 5184 65 discriminator 1 + 10249 0198 002B cmp r3, #0 + 10250 019a 2BD0 beq .L483 +5186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Write data to TXDR only if XferCount not reach "0" */ +5188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* A TXIS flag can be set, during STOP treatment */ +5189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check if all Data have already been sent */ +5190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ +5191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > 0U) + 10251 .loc 1 5191 13 + 10252 019c FB68 ldr r3, [r7, #12] + 10253 019e 5B8D ldrh r3, [r3, #42] @ movhi + 10254 01a0 9BB2 uxth r3, r3 + 10255 .loc 1 5191 8 + 10256 01a2 002B cmp r3, #0 + 10257 01a4 18D0 beq .L488 +5192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Write data to TXDR */ +5194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->TXDR = *hi2c->pBuffPtr; + 10258 .loc 1 5194 35 + 10259 01a6 FB68 ldr r3, [r7, #12] + 10260 01a8 5B6A ldr r3, [r3, #36] + ARM GAS /tmp/cc5G5cqz.s page 273 + + + 10261 .loc 1 5194 30 + 10262 01aa 1A78 ldrb r2, [r3] @ zero_extendqisi2 + 10263 .loc 1 5194 11 + 10264 01ac FB68 ldr r3, [r7, #12] + 10265 01ae 1B68 ldr r3, [r3] + 10266 .loc 1 5194 28 + 10267 01b0 9A62 str r2, [r3, #40] +5195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Increment Buffer pointer */ +5197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr++; + 10268 .loc 1 5197 11 + 10269 01b2 FB68 ldr r3, [r7, #12] + 10270 01b4 5B6A ldr r3, [r3, #36] + 10271 .loc 1 5197 21 + 10272 01b6 5A1C adds r2, r3, #1 + 10273 01b8 FB68 ldr r3, [r7, #12] + 10274 01ba 5A62 str r2, [r3, #36] +5198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount--; + 10275 .loc 1 5199 11 + 10276 01bc FB68 ldr r3, [r7, #12] + 10277 01be 5B8D ldrh r3, [r3, #42] @ movhi + 10278 01c0 9BB2 uxth r3, r3 + 10279 .loc 1 5199 22 + 10280 01c2 013B subs r3, r3, #1 + 10281 01c4 9AB2 uxth r2, r3 + 10282 01c6 FB68 ldr r3, [r7, #12] + 10283 01c8 5A85 strh r2, [r3, #42] @ movhi +5200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize--; + 10284 .loc 1 5200 11 + 10285 01ca FB68 ldr r3, [r7, #12] + 10286 01cc 1B8D ldrh r3, [r3, #40] + 10287 .loc 1 5200 21 + 10288 01ce 013B subs r3, r3, #1 + 10289 01d0 9AB2 uxth r2, r3 + 10290 01d2 FB68 ldr r3, [r7, #12] + 10291 01d4 1A85 strh r2, [r3, #40] @ movhi + 10292 01d6 0DE0 b .L483 + 10293 .L488: +5201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) + 10294 .loc 1 5204 10 + 10295 01d8 7B69 ldr r3, [r7, #20] + 10296 01da B3F1807F cmp r3, #16777216 + 10297 01de 02D0 beq .L489 + 10298 .loc 1 5204 42 discriminator 1 + 10299 01e0 7B69 ldr r3, [r7, #20] + 10300 01e2 002B cmp r3, #0 + 10301 01e4 06D1 bne .L483 + 10302 .L489: +5205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Last Byte is Transmitted */ +5207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call I2C Slave Sequential complete process */ +5208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITSlaveSeqCplt(hi2c); + 10303 .loc 1 5208 9 + ARM GAS /tmp/cc5G5cqz.s page 274 + + + 10304 01e6 F868 ldr r0, [r7, #12] + 10305 01e8 FFF7FEFF bl I2C_ITSlaveSeqCplt + 10306 01ec 02E0 b .L483 + 10307 .L490: +5114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10308 .loc 1 5114 8 + 10309 01ee 00BF nop + 10310 01f0 00E0 b .L483 + 10311 .L491: +5172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) + 10312 .loc 1 5172 8 + 10313 01f2 00BF nop + 10314 .L483: +5209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Nothing to do */ +5215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +5218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 10315 .loc 1 5218 3 + 10316 01f4 FB68 ldr r3, [r7, #12] + 10317 01f6 0022 movs r2, #0 + 10318 01f8 83F84020 strb r2, [r3, #64] +5219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; + 10319 .loc 1 5220 10 + 10320 01fc 0023 movs r3, #0 + 10321 .L474: +5221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10322 .loc 1 5221 1 + 10323 01fe 1846 mov r0, r3 + 10324 0200 1837 adds r7, r7, #24 + 10325 .cfi_def_cfa_offset 8 + 10326 0202 BD46 mov sp, r7 + 10327 .cfi_def_cfa_register 13 + 10328 @ sp needed + 10329 0204 80BD pop {r7, pc} + 10330 .cfi_endproc + 10331 .LFE181: + 10333 .section .text.I2C_Master_ISR_DMA,"ax",%progbits + 10334 .align 1 + 10335 .syntax unified + 10336 .thumb + 10337 .thumb_func + 10339 I2C_Master_ISR_DMA: + 10340 .LFB182: +5222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +5224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA. +5225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +5226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +5227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. +5228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param ITSources Interrupt sources enabled. + ARM GAS /tmp/cc5G5cqz.s page 275 + + +5229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +5230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +5231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, +5232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t ITSources) +5233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10341 .loc 1 5233 1 + 10342 .cfi_startproc + 10343 @ args = 0, pretend = 0, frame = 24 + 10344 @ frame_needed = 1, uses_anonymous_args = 0 + 10345 0000 80B5 push {r7, lr} + 10346 .cfi_def_cfa_offset 8 + 10347 .cfi_offset 7, -8 + 10348 .cfi_offset 14, -4 + 10349 0002 88B0 sub sp, sp, #32 + 10350 .cfi_def_cfa_offset 40 + 10351 0004 02AF add r7, sp, #8 + 10352 .cfi_def_cfa 7, 32 + 10353 0006 F860 str r0, [r7, #12] + 10354 0008 B960 str r1, [r7, #8] + 10355 000a 7A60 str r2, [r7, #4] +5234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t devaddress; +5235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t xfermode; +5236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +5238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); + 10356 .loc 1 5238 3 + 10357 000c FB68 ldr r3, [r7, #12] + 10358 000e 93F84030 ldrb r3, [r3, #64] @ zero_extendqisi2 + 10359 0012 012B cmp r3, #1 + 10360 0014 01D1 bne .L493 + 10361 .loc 1 5238 3 is_stmt 0 discriminator 1 + 10362 0016 0223 movs r3, #2 + 10363 .loc 1 5238 3 + 10364 0018 E1E0 b .L494 + 10365 .L493: + 10366 .loc 1 5238 3 discriminator 2 + 10367 001a FB68 ldr r3, [r7, #12] + 10368 001c 0122 movs r2, #1 + 10369 001e 83F84020 strb r2, [r3, #64] +5239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + 10370 .loc 1 5240 8 is_stmt 1 + 10371 0022 BB68 ldr r3, [r7, #8] + 10372 0024 1B09 lsrs r3, r3, #4 + 10373 0026 03F00103 and r3, r3, #1 + 10374 .loc 1 5240 6 + 10375 002a 002B cmp r3, #0 + 10376 002c 17D0 beq .L495 +5241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 10377 .loc 1 5241 8 + 10378 002e 7B68 ldr r3, [r7, #4] + 10379 0030 1B09 lsrs r3, r3, #4 + 10380 0032 03F00103 and r3, r3, #1 +5240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 10381 .loc 1 5240 55 discriminator 1 + 10382 0036 002B cmp r3, #0 + 10383 0038 11D0 beq .L495 + ARM GAS /tmp/cc5G5cqz.s page 276 + + +5242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear NACK Flag */ +5244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + 10384 .loc 1 5244 5 + 10385 003a FB68 ldr r3, [r7, #12] + 10386 003c 1B68 ldr r3, [r3] + 10387 003e 1022 movs r2, #16 + 10388 0040 DA61 str r2, [r3, #28] +5245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set corresponding Error Code */ +5247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + 10389 .loc 1 5247 9 + 10390 0042 FB68 ldr r3, [r7, #12] + 10391 0044 5B6C ldr r3, [r3, #68] + 10392 .loc 1 5247 21 + 10393 0046 43F00402 orr r2, r3, #4 + 10394 004a FB68 ldr r3, [r7, #12] + 10395 004c 5A64 str r2, [r3, #68] +5248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* No need to generate STOP, it is automatically done */ +5250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* But enable STOP interrupt, to treat it */ +5251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Error callback will be send during stop flag treatment */ +5252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + 10396 .loc 1 5252 5 + 10397 004e 2021 movs r1, #32 + 10398 0050 F868 ldr r0, [r7, #12] + 10399 0052 FFF7FEFF bl I2C_Enable_IRQ +5253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Flush TX register */ +5255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); + 10400 .loc 1 5255 5 + 10401 0056 F868 ldr r0, [r7, #12] + 10402 0058 FFF7FEFF bl I2C_Flush_TXDR + 10403 005c BAE0 b .L496 + 10404 .L495: +5256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ + 10405 .loc 1 5257 13 + 10406 005e BB68 ldr r3, [r7, #8] + 10407 0060 DB09 lsrs r3, r3, #7 + 10408 0062 03F00103 and r3, r3, #1 + 10409 .loc 1 5257 11 + 10410 0066 002B cmp r3, #0 + 10411 0068 72D0 beq .L497 +5258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 10412 .loc 1 5258 13 + 10413 006a 7B68 ldr r3, [r7, #4] + 10414 006c 9B09 lsrs r3, r3, #6 + 10415 006e 03F00103 and r3, r3, #1 +5257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 10416 .loc 1 5257 61 discriminator 1 + 10417 0072 002B cmp r3, #0 + 10418 0074 6CD0 beq .L497 +5259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable TC interrupt */ +5261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI); + 10419 .loc 1 5261 5 + ARM GAS /tmp/cc5G5cqz.s page 277 + + + 10420 0076 FB68 ldr r3, [r7, #12] + 10421 0078 1B68 ldr r3, [r3] + 10422 007a 1A68 ldr r2, [r3] + 10423 007c FB68 ldr r3, [r7, #12] + 10424 007e 1B68 ldr r3, [r3] + 10425 0080 22F04002 bic r2, r2, #64 + 10426 0084 1A60 str r2, [r3] +5262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount != 0U) + 10427 .loc 1 5263 13 + 10428 0086 FB68 ldr r3, [r7, #12] + 10429 0088 5B8D ldrh r3, [r3, #42] @ movhi + 10430 008a 9BB2 uxth r3, r3 + 10431 .loc 1 5263 8 + 10432 008c 002B cmp r3, #0 + 10433 008e 4ED0 beq .L498 +5264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Recover Slave address */ +5266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); + 10434 .loc 1 5266 35 + 10435 0090 FB68 ldr r3, [r7, #12] + 10436 0092 1B68 ldr r3, [r3] + 10437 .loc 1 5266 45 + 10438 0094 5B68 ldr r3, [r3, #4] + 10439 .loc 1 5266 20 + 10440 0096 9BB2 uxth r3, r3 + 10441 .loc 1 5266 18 + 10442 0098 C3F30903 ubfx r3, r3, #0, #10 + 10443 009c 7B82 strh r3, [r7, #18] @ movhi +5267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare the new XferSize to transfer */ +5269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) + 10444 .loc 1 5269 15 + 10445 009e FB68 ldr r3, [r7, #12] + 10446 00a0 5B8D ldrh r3, [r3, #42] @ movhi + 10447 00a2 9BB2 uxth r3, r3 + 10448 .loc 1 5269 10 + 10449 00a4 FF2B cmp r3, #255 + 10450 00a6 06D9 bls .L499 +5270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; + 10451 .loc 1 5271 24 + 10452 00a8 FB68 ldr r3, [r7, #12] + 10453 00aa FF22 movs r2, #255 + 10454 00ac 1A85 strh r2, [r3, #40] @ movhi +5272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_RELOAD_MODE; + 10455 .loc 1 5272 18 + 10456 00ae 4FF08073 mov r3, #16777216 + 10457 00b2 7B61 str r3, [r7, #20] + 10458 00b4 10E0 b .L500 + 10459 .L499: +5273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 10460 .loc 1 5276 30 + 10461 00b6 FB68 ldr r3, [r7, #12] + ARM GAS /tmp/cc5G5cqz.s page 278 + + + 10462 00b8 5B8D ldrh r3, [r3, #42] @ movhi + 10463 00ba 9AB2 uxth r2, r3 + 10464 .loc 1 5276 24 + 10465 00bc FB68 ldr r3, [r7, #12] + 10466 00be 1A85 strh r2, [r3, #40] @ movhi +5277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + 10467 .loc 1 5277 17 + 10468 00c0 FB68 ldr r3, [r7, #12] + 10469 00c2 DB6A ldr r3, [r3, #44] + 10470 .loc 1 5277 12 + 10471 00c4 13F5803F cmn r3, #65536 + 10472 00c8 03D0 beq .L501 +5278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = hi2c->XferOptions; + 10473 .loc 1 5279 20 + 10474 00ca FB68 ldr r3, [r7, #12] + 10475 00cc DB6A ldr r3, [r3, #44] + 10476 00ce 7B61 str r3, [r7, #20] + 10477 00d0 02E0 b .L500 + 10478 .L501: +5280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** xfermode = I2C_AUTOEND_MODE; + 10479 .loc 1 5283 20 + 10480 00d2 4FF00073 mov r3, #33554432 + 10481 00d6 7B61 str r3, [r7, #20] + 10482 .L500: +5284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the new XferSize in Nbytes register */ +5288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + 10483 .loc 1 5288 57 + 10484 00d8 FB68 ldr r3, [r7, #12] + 10485 00da 1B8D ldrh r3, [r3, #40] + 10486 .loc 1 5288 7 + 10487 00dc DAB2 uxtb r2, r3 + 10488 00de 798A ldrh r1, [r7, #18] + 10489 00e0 0023 movs r3, #0 + 10490 00e2 0093 str r3, [sp] + 10491 00e4 7B69 ldr r3, [r7, #20] + 10492 00e6 F868 ldr r0, [r7, #12] + 10493 00e8 FFF7FEFF bl I2C_TransferConfig +5289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update XferCount value */ +5291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount -= hi2c->XferSize; + 10494 .loc 1 5291 11 + 10495 00ec FB68 ldr r3, [r7, #12] + 10496 00ee 5B8D ldrh r3, [r3, #42] @ movhi + 10497 00f0 9AB2 uxth r2, r3 + 10498 .loc 1 5291 30 + 10499 00f2 FB68 ldr r3, [r7, #12] + 10500 00f4 1B8D ldrh r3, [r3, #40] + 10501 .loc 1 5291 23 + 10502 00f6 D31A subs r3, r2, r3 + 10503 00f8 9AB2 uxth r2, r3 + ARM GAS /tmp/cc5G5cqz.s page 279 + + + 10504 00fa FB68 ldr r3, [r7, #12] + 10505 00fc 5A85 strh r2, [r3, #42] @ movhi +5292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable DMA Request */ +5294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + 10506 .loc 1 5294 15 + 10507 00fe FB68 ldr r3, [r7, #12] + 10508 0100 93F84130 ldrb r3, [r3, #65] + 10509 0104 DBB2 uxtb r3, r3 + 10510 .loc 1 5294 10 + 10511 0106 222B cmp r3, #34 + 10512 0108 08D1 bne .L502 +5295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + 10513 .loc 1 5296 13 + 10514 010a FB68 ldr r3, [r7, #12] + 10515 010c 1B68 ldr r3, [r3] + 10516 .loc 1 5296 23 + 10517 010e 1A68 ldr r2, [r3] + 10518 .loc 1 5296 13 + 10519 0110 FB68 ldr r3, [r7, #12] + 10520 0112 1B68 ldr r3, [r3] + 10521 .loc 1 5296 29 + 10522 0114 42F40042 orr r2, r2, #32768 + 10523 0118 1A60 str r2, [r3] +5263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10524 .loc 1 5263 8 + 10525 011a 5BE0 b .L496 + 10526 .L502: +5297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + 10527 .loc 1 5300 13 + 10528 011c FB68 ldr r3, [r7, #12] + 10529 011e 1B68 ldr r3, [r3] + 10530 .loc 1 5300 23 + 10531 0120 1A68 ldr r2, [r3] + 10532 .loc 1 5300 13 + 10533 0122 FB68 ldr r3, [r7, #12] + 10534 0124 1B68 ldr r3, [r3] + 10535 .loc 1 5300 29 + 10536 0126 42F48042 orr r2, r2, #16384 + 10537 012a 1A60 str r2, [r3] +5263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10538 .loc 1 5263 8 + 10539 012c 52E0 b .L496 + 10540 .L498: +5301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call TxCpltCallback() if no stop mode is set */ +5306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + 10541 .loc 1 5306 11 + 10542 012e FB68 ldr r3, [r7, #12] + 10543 0130 1B68 ldr r3, [r3] + ARM GAS /tmp/cc5G5cqz.s page 280 + + + 10544 0132 5B68 ldr r3, [r3, #4] + 10545 0134 03F00073 and r3, r3, #33554432 + 10546 .loc 1 5306 10 + 10547 0138 B3F1007F cmp r3, #33554432 + 10548 013c 03D0 beq .L504 +5307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call I2C Master Sequential complete process */ +5309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITMasterSeqCplt(hi2c); + 10549 .loc 1 5309 9 + 10550 013e F868 ldr r0, [r7, #12] + 10551 0140 FFF7FEFF bl I2C_ITMasterSeqCplt +5263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10552 .loc 1 5263 8 + 10553 0144 46E0 b .L496 + 10554 .L504: +5310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wrong size Status regarding TCR flag event */ +5314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + 10555 .loc 1 5315 9 + 10556 0146 4021 movs r1, #64 + 10557 0148 F868 ldr r0, [r7, #12] + 10558 014a FFF7FEFF bl I2C_ITError +5263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10559 .loc 1 5263 8 + 10560 014e 41E0 b .L496 + 10561 .L497: +5316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ + 10562 .loc 1 5319 13 + 10563 0150 BB68 ldr r3, [r7, #8] + 10564 0152 9B09 lsrs r3, r3, #6 + 10565 0154 03F00103 and r3, r3, #1 + 10566 .loc 1 5319 11 + 10567 0158 002B cmp r3, #0 + 10568 015a 29D0 beq .L505 +5320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 10569 .loc 1 5320 13 + 10570 015c 7B68 ldr r3, [r7, #4] + 10571 015e 9B09 lsrs r3, r3, #6 + 10572 0160 03F00103 and r3, r3, #1 +5319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 10573 .loc 1 5319 60 discriminator 1 + 10574 0164 002B cmp r3, #0 + 10575 0166 23D0 beq .L505 +5321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount == 0U) + 10576 .loc 1 5322 13 + 10577 0168 FB68 ldr r3, [r7, #12] + 10578 016a 5B8D ldrh r3, [r3, #42] @ movhi + 10579 016c 9BB2 uxth r3, r3 + 10580 .loc 1 5322 8 + 10581 016e 002B cmp r3, #0 + ARM GAS /tmp/cc5G5cqz.s page 281 + + + 10582 0170 19D1 bne .L506 +5323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + 10583 .loc 1 5324 11 + 10584 0172 FB68 ldr r3, [r7, #12] + 10585 0174 1B68 ldr r3, [r3] + 10586 0176 5B68 ldr r3, [r3, #4] + 10587 0178 03F00073 and r3, r3, #33554432 + 10588 .loc 1 5324 10 + 10589 017c B3F1007F cmp r3, #33554432 + 10590 0180 27D0 beq .L509 +5325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Generate a stop condition in case of no transfer option */ +5327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) + 10591 .loc 1 5327 17 + 10592 0182 FB68 ldr r3, [r7, #12] + 10593 0184 DB6A ldr r3, [r3, #44] + 10594 .loc 1 5327 12 + 10595 0186 13F5803F cmn r3, #65536 + 10596 018a 08D1 bne .L508 +5328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Generate Stop */ +5330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_STOP; + 10597 .loc 1 5330 15 + 10598 018c FB68 ldr r3, [r7, #12] + 10599 018e 1B68 ldr r3, [r3] + 10600 .loc 1 5330 25 + 10601 0190 5A68 ldr r2, [r3, #4] + 10602 .loc 1 5330 15 + 10603 0192 FB68 ldr r3, [r7, #12] + 10604 0194 1B68 ldr r3, [r3] + 10605 .loc 1 5330 31 + 10606 0196 42F48042 orr r2, r2, #16384 + 10607 019a 5A60 str r2, [r3, #4] +5322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10608 .loc 1 5322 8 + 10609 019c 19E0 b .L509 + 10610 .L508: +5331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call I2C Master Sequential complete process */ +5335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITMasterSeqCplt(hi2c); + 10611 .loc 1 5335 11 + 10612 019e F868 ldr r0, [r7, #12] + 10613 01a0 FFF7FEFF bl I2C_ITMasterSeqCplt +5322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10614 .loc 1 5322 8 + 10615 01a4 15E0 b .L509 + 10616 .L506: +5336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wrong size Status regarding TC flag event */ +5342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ + ARM GAS /tmp/cc5G5cqz.s page 282 + + +5343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + 10617 .loc 1 5343 7 + 10618 01a6 4021 movs r1, #64 + 10619 01a8 F868 ldr r0, [r7, #12] + 10620 01aa FFF7FEFF bl I2C_ITError +5322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10621 .loc 1 5322 8 + 10622 01ae 10E0 b .L509 + 10623 .L505: +5344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ + 10624 .loc 1 5346 13 + 10625 01b0 BB68 ldr r3, [r7, #8] + 10626 01b2 5B09 lsrs r3, r3, #5 + 10627 01b4 03F00103 and r3, r3, #1 + 10628 .loc 1 5346 11 + 10629 01b8 002B cmp r3, #0 + 10630 01ba 0BD0 beq .L496 +5347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 10631 .loc 1 5347 13 + 10632 01bc 7B68 ldr r3, [r7, #4] + 10633 01be 5B09 lsrs r3, r3, #5 + 10634 01c0 03F00103 and r3, r3, #1 +5346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 10635 .loc 1 5346 63 discriminator 1 + 10636 01c4 002B cmp r3, #0 + 10637 01c6 05D0 beq .L496 +5348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call I2C Master complete process */ +5350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITMasterCplt(hi2c, ITFlags); + 10638 .loc 1 5350 5 + 10639 01c8 B968 ldr r1, [r7, #8] + 10640 01ca F868 ldr r0, [r7, #12] + 10641 01cc FFF7FEFF bl I2C_ITMasterCplt + 10642 01d0 00E0 b .L496 + 10643 .L509: +5322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10644 .loc 1 5322 8 + 10645 01d2 00BF nop + 10646 .L496: +5351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Nothing to do */ +5355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +5358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 10647 .loc 1 5358 3 + 10648 01d4 FB68 ldr r3, [r7, #12] + 10649 01d6 0022 movs r2, #0 + 10650 01d8 83F84020 strb r2, [r3, #64] +5359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; + 10651 .loc 1 5360 10 + 10652 01dc 0023 movs r3, #0 + ARM GAS /tmp/cc5G5cqz.s page 283 + + + 10653 .L494: +5361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 10654 .loc 1 5361 1 + 10655 01de 1846 mov r0, r3 + 10656 01e0 1837 adds r7, r7, #24 + 10657 .cfi_def_cfa_offset 8 + 10658 01e2 BD46 mov sp, r7 + 10659 .cfi_def_cfa_register 13 + 10660 @ sp needed + 10661 01e4 80BD pop {r7, pc} + 10662 .cfi_endproc + 10663 .LFE182: + 10665 .section .text.I2C_Mem_ISR_DMA,"ax",%progbits + 10666 .align 1 + 10667 .syntax unified + 10668 .thumb + 10669 .thumb_func + 10671 I2C_Mem_ISR_DMA: + 10672 .LFB183: +5362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +5364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with DMA. +5365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +5366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +5367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. +5368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param ITSources Interrupt sources enabled. +5369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +5370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +5371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, +5372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t ITSources) +5373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10673 .loc 1 5373 1 + 10674 .cfi_startproc + 10675 @ args = 0, pretend = 0, frame = 24 + 10676 @ frame_needed = 1, uses_anonymous_args = 0 + 10677 0000 80B5 push {r7, lr} + 10678 .cfi_def_cfa_offset 8 + 10679 .cfi_offset 7, -8 + 10680 .cfi_offset 14, -4 + 10681 0002 88B0 sub sp, sp, #32 + 10682 .cfi_def_cfa_offset 40 + 10683 0004 02AF add r7, sp, #8 + 10684 .cfi_def_cfa 7, 32 + 10685 0006 F860 str r0, [r7, #12] + 10686 0008 B960 str r1, [r7, #8] + 10687 000a 7A60 str r2, [r7, #4] +5374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t direction = I2C_GENERATE_START_WRITE; + 10688 .loc 1 5374 12 + 10689 000c 8C4B ldr r3, .L528 + 10690 000e 7B61 str r3, [r7, #20] +5375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Locked */ +5377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); + 10691 .loc 1 5377 3 + 10692 0010 FB68 ldr r3, [r7, #12] + 10693 0012 93F84030 ldrb r3, [r3, #64] @ zero_extendqisi2 + 10694 0016 012B cmp r3, #1 + ARM GAS /tmp/cc5G5cqz.s page 284 + + + 10695 0018 01D1 bne .L511 + 10696 .loc 1 5377 3 is_stmt 0 discriminator 1 + 10697 001a 0223 movs r3, #2 + 10698 .loc 1 5377 3 + 10699 001c 0CE1 b .L512 + 10700 .L511: + 10701 .loc 1 5377 3 discriminator 2 + 10702 001e FB68 ldr r3, [r7, #12] + 10703 0020 0122 movs r2, #1 + 10704 0022 83F84020 strb r2, [r3, #64] +5378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + 10705 .loc 1 5379 8 is_stmt 1 + 10706 0026 BB68 ldr r3, [r7, #8] + 10707 0028 1B09 lsrs r3, r3, #4 + 10708 002a 03F00103 and r3, r3, #1 + 10709 .loc 1 5379 6 + 10710 002e 002B cmp r3, #0 + 10711 0030 17D0 beq .L513 +5380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 10712 .loc 1 5380 8 + 10713 0032 7B68 ldr r3, [r7, #4] + 10714 0034 1B09 lsrs r3, r3, #4 + 10715 0036 03F00103 and r3, r3, #1 +5379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 10716 .loc 1 5379 55 discriminator 1 + 10717 003a 002B cmp r3, #0 + 10718 003c 11D0 beq .L513 +5381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear NACK Flag */ +5383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + 10719 .loc 1 5383 5 + 10720 003e FB68 ldr r3, [r7, #12] + 10721 0040 1B68 ldr r3, [r3] + 10722 0042 1022 movs r2, #16 + 10723 0044 DA61 str r2, [r3, #28] +5384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set corresponding Error Code */ +5386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + 10724 .loc 1 5386 9 + 10725 0046 FB68 ldr r3, [r7, #12] + 10726 0048 5B6C ldr r3, [r3, #68] + 10727 .loc 1 5386 21 + 10728 004a 43F00402 orr r2, r3, #4 + 10729 004e FB68 ldr r3, [r7, #12] + 10730 0050 5A64 str r2, [r3, #68] +5387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* No need to generate STOP, it is automatically done */ +5389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* But enable STOP interrupt, to treat it */ +5390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Error callback will be send during stop flag treatment */ +5391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + 10731 .loc 1 5391 5 + 10732 0052 2021 movs r1, #32 + 10733 0054 F868 ldr r0, [r7, #12] + 10734 0056 FFF7FEFF bl I2C_Enable_IRQ +5392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Flush TX register */ + ARM GAS /tmp/cc5G5cqz.s page 285 + + +5394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); + 10735 .loc 1 5394 5 + 10736 005a F868 ldr r0, [r7, #12] + 10737 005c FFF7FEFF bl I2C_Flush_TXDR + 10738 0060 E5E0 b .L514 + 10739 .L513: +5395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \ + 10740 .loc 1 5396 13 + 10741 0062 BB68 ldr r3, [r7, #8] + 10742 0064 5B08 lsrs r3, r3, #1 + 10743 0066 03F00103 and r3, r3, #1 + 10744 .loc 1 5396 11 + 10745 006a 002B cmp r3, #0 + 10746 006c 0FD0 beq .L515 +5397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + 10747 .loc 1 5397 13 + 10748 006e 7B68 ldr r3, [r7, #4] + 10749 0070 5B08 lsrs r3, r3, #1 + 10750 0072 03F00103 and r3, r3, #1 +5396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + 10751 .loc 1 5396 62 discriminator 1 + 10752 0076 002B cmp r3, #0 + 10753 0078 09D0 beq .L515 +5398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Write LSB part of Memory Address */ +5400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->TXDR = hi2c->Memaddress; + 10754 .loc 1 5400 9 + 10755 007a FB68 ldr r3, [r7, #12] + 10756 007c 1B68 ldr r3, [r3] + 10757 .loc 1 5400 32 + 10758 007e FA68 ldr r2, [r7, #12] + 10759 0080 126D ldr r2, [r2, #80] + 10760 .loc 1 5400 26 + 10761 0082 9A62 str r2, [r3, #40] +5401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Reset Memaddress content */ +5403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Memaddress = 0xFFFFFFFFU; + 10762 .loc 1 5403 22 + 10763 0084 FB68 ldr r3, [r7, #12] + 10764 0086 4FF0FF32 mov r2, #-1 + 10765 008a 1A65 str r2, [r3, #80] + 10766 008c CFE0 b .L514 + 10767 .L515: +5404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ + 10768 .loc 1 5405 13 + 10769 008e BB68 ldr r3, [r7, #8] + 10770 0090 DB09 lsrs r3, r3, #7 + 10771 0092 03F00103 and r3, r3, #1 + 10772 .loc 1 5405 11 + 10773 0096 002B cmp r3, #0 + 10774 0098 5CD0 beq .L516 +5406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 10775 .loc 1 5406 13 + 10776 009a 7B68 ldr r3, [r7, #4] + 10777 009c 9B09 lsrs r3, r3, #6 + ARM GAS /tmp/cc5G5cqz.s page 286 + + + 10778 009e 03F00103 and r3, r3, #1 +5405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 10779 .loc 1 5405 61 discriminator 1 + 10780 00a2 002B cmp r3, #0 + 10781 00a4 56D0 beq .L516 +5407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable only Error interrupt */ +5409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + 10782 .loc 1 5409 5 + 10783 00a6 1021 movs r1, #16 + 10784 00a8 F868 ldr r0, [r7, #12] + 10785 00aa FFF7FEFF bl I2C_Enable_IRQ +5410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount != 0U) + 10786 .loc 1 5411 13 + 10787 00ae FB68 ldr r3, [r7, #12] + 10788 00b0 5B8D ldrh r3, [r3, #42] @ movhi + 10789 00b2 9BB2 uxth r3, r3 + 10790 .loc 1 5411 8 + 10791 00b4 002B cmp r3, #0 + 10792 00b6 48D0 beq .L517 +5412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prepare the new XferSize to transfer */ +5414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) + 10793 .loc 1 5414 15 + 10794 00b8 FB68 ldr r3, [r7, #12] + 10795 00ba 5B8D ldrh r3, [r3, #42] @ movhi + 10796 00bc 9BB2 uxth r3, r3 + 10797 .loc 1 5414 10 + 10798 00be FF2B cmp r3, #255 + 10799 00c0 10D9 bls .L518 +5415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; + 10800 .loc 1 5416 24 + 10801 00c2 FB68 ldr r3, [r7, #12] + 10802 00c4 FF22 movs r2, #255 + 10803 00c6 1A85 strh r2, [r3, #40] @ movhi +5417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + 10804 .loc 1 5417 48 + 10805 00c8 FB68 ldr r3, [r7, #12] + 10806 00ca DB6C ldr r3, [r3, #76] + 10807 .loc 1 5417 9 + 10808 00cc 99B2 uxth r1, r3 + 10809 .loc 1 5417 75 + 10810 00ce FB68 ldr r3, [r7, #12] + 10811 00d0 1B8D ldrh r3, [r3, #40] + 10812 .loc 1 5417 9 + 10813 00d2 DAB2 uxtb r2, r3 + 10814 00d4 0023 movs r3, #0 + 10815 00d6 0093 str r3, [sp] + 10816 00d8 4FF08073 mov r3, #16777216 + 10817 00dc F868 ldr r0, [r7, #12] + 10818 00de FFF7FEFF bl I2C_TransferConfig + 10819 00e2 11E0 b .L519 + 10820 .L518: +5418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_RELOAD_MODE, I2C_NO_STARTSTOP); +5419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/cc5G5cqz.s page 287 + + +5420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 10821 .loc 1 5422 30 + 10822 00e4 FB68 ldr r3, [r7, #12] + 10823 00e6 5B8D ldrh r3, [r3, #42] @ movhi + 10824 00e8 9AB2 uxth r2, r3 + 10825 .loc 1 5422 24 + 10826 00ea FB68 ldr r3, [r7, #12] + 10827 00ec 1A85 strh r2, [r3, #40] @ movhi +5423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + 10828 .loc 1 5423 48 + 10829 00ee FB68 ldr r3, [r7, #12] + 10830 00f0 DB6C ldr r3, [r3, #76] + 10831 .loc 1 5423 9 + 10832 00f2 99B2 uxth r1, r3 + 10833 .loc 1 5423 75 + 10834 00f4 FB68 ldr r3, [r7, #12] + 10835 00f6 1B8D ldrh r3, [r3, #40] + 10836 .loc 1 5423 9 + 10837 00f8 DAB2 uxtb r2, r3 + 10838 00fa 0023 movs r3, #0 + 10839 00fc 0093 str r3, [sp] + 10840 00fe 4FF00073 mov r3, #33554432 + 10841 0102 F868 ldr r0, [r7, #12] + 10842 0104 FFF7FEFF bl I2C_TransferConfig + 10843 .L519: +5424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); +5425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update XferCount value */ +5428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount -= hi2c->XferSize; + 10844 .loc 1 5428 11 + 10845 0108 FB68 ldr r3, [r7, #12] + 10846 010a 5B8D ldrh r3, [r3, #42] @ movhi + 10847 010c 9AB2 uxth r2, r3 + 10848 .loc 1 5428 30 + 10849 010e FB68 ldr r3, [r7, #12] + 10850 0110 1B8D ldrh r3, [r3, #40] + 10851 .loc 1 5428 23 + 10852 0112 D31A subs r3, r2, r3 + 10853 0114 9AB2 uxth r2, r3 + 10854 0116 FB68 ldr r3, [r7, #12] + 10855 0118 5A85 strh r2, [r3, #42] @ movhi +5429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable DMA Request */ +5431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + 10856 .loc 1 5431 15 + 10857 011a FB68 ldr r3, [r7, #12] + 10858 011c 93F84130 ldrb r3, [r3, #65] + 10859 0120 DBB2 uxtb r3, r3 + 10860 .loc 1 5431 10 + 10861 0122 222B cmp r3, #34 + 10862 0124 08D1 bne .L520 +5432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + 10863 .loc 1 5433 13 + ARM GAS /tmp/cc5G5cqz.s page 288 + + + 10864 0126 FB68 ldr r3, [r7, #12] + 10865 0128 1B68 ldr r3, [r3] + 10866 .loc 1 5433 23 + 10867 012a 1A68 ldr r2, [r3] + 10868 .loc 1 5433 13 + 10869 012c FB68 ldr r3, [r7, #12] + 10870 012e 1B68 ldr r3, [r3] + 10871 .loc 1 5433 29 + 10872 0130 42F40042 orr r2, r2, #32768 + 10873 0134 1A60 str r2, [r3] +5411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10874 .loc 1 5411 8 + 10875 0136 7AE0 b .L514 + 10876 .L520: +5434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + 10877 .loc 1 5437 13 + 10878 0138 FB68 ldr r3, [r7, #12] + 10879 013a 1B68 ldr r3, [r3] + 10880 .loc 1 5437 23 + 10881 013c 1A68 ldr r2, [r3] + 10882 .loc 1 5437 13 + 10883 013e FB68 ldr r3, [r7, #12] + 10884 0140 1B68 ldr r3, [r3] + 10885 .loc 1 5437 29 + 10886 0142 42F48042 orr r2, r2, #16384 + 10887 0146 1A60 str r2, [r3] +5411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10888 .loc 1 5411 8 + 10889 0148 71E0 b .L514 + 10890 .L517: +5438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wrong size Status regarding TCR flag event */ +5443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + 10891 .loc 1 5444 7 + 10892 014a 4021 movs r1, #64 + 10893 014c F868 ldr r0, [r7, #12] + 10894 014e FFF7FEFF bl I2C_ITError +5411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 10895 .loc 1 5411 8 + 10896 0152 6CE0 b .L514 + 10897 .L516: +5445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ + 10898 .loc 1 5447 13 + 10899 0154 BB68 ldr r3, [r7, #8] + 10900 0156 9B09 lsrs r3, r3, #6 + 10901 0158 03F00103 and r3, r3, #1 + 10902 .loc 1 5447 11 + 10903 015c 002B cmp r3, #0 + ARM GAS /tmp/cc5G5cqz.s page 289 + + + 10904 015e 56D0 beq .L522 +5448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 10905 .loc 1 5448 13 + 10906 0160 7B68 ldr r3, [r7, #4] + 10907 0162 9B09 lsrs r3, r3, #6 + 10908 0164 03F00103 and r3, r3, #1 +5447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + 10909 .loc 1 5447 60 discriminator 1 + 10910 0168 002B cmp r3, #0 + 10911 016a 50D0 beq .L522 +5449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + 10912 .loc 1 5450 13 + 10913 016c FB68 ldr r3, [r7, #12] + 10914 016e 93F84130 ldrb r3, [r3, #65] + 10915 0172 DBB2 uxtb r3, r3 + 10916 .loc 1 5450 8 + 10917 0174 222B cmp r3, #34 + 10918 0176 01D1 bne .L523 +5451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** direction = I2C_GENERATE_START_READ; + 10919 .loc 1 5452 17 + 10920 0178 324B ldr r3, .L528+4 + 10921 017a 7B61 str r3, [r7, #20] + 10922 .L523: +5453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) + 10923 .loc 1 5455 13 + 10924 017c FB68 ldr r3, [r7, #12] + 10925 017e 5B8D ldrh r3, [r3, #42] @ movhi + 10926 0180 9BB2 uxth r3, r3 + 10927 .loc 1 5455 8 + 10928 0182 FF2B cmp r3, #255 + 10929 0184 10D9 bls .L524 +5456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; + 10930 .loc 1 5457 22 + 10931 0186 FB68 ldr r3, [r7, #12] + 10932 0188 FF22 movs r2, #255 + 10933 018a 1A85 strh r2, [r3, #40] @ movhi +5458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ +5460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + 10934 .loc 1 5460 46 + 10935 018c FB68 ldr r3, [r7, #12] + 10936 018e DB6C ldr r3, [r3, #76] + 10937 .loc 1 5460 7 + 10938 0190 99B2 uxth r1, r3 + 10939 .loc 1 5460 73 + 10940 0192 FB68 ldr r3, [r7, #12] + 10941 0194 1B8D ldrh r3, [r3, #40] + 10942 .loc 1 5460 7 + 10943 0196 DAB2 uxtb r2, r3 + 10944 0198 7B69 ldr r3, [r7, #20] + 10945 019a 0093 str r3, [sp] + 10946 019c 4FF08073 mov r3, #16777216 + ARM GAS /tmp/cc5G5cqz.s page 290 + + + 10947 01a0 F868 ldr r0, [r7, #12] + 10948 01a2 FFF7FEFF bl I2C_TransferConfig + 10949 01a6 11E0 b .L525 + 10950 .L524: +5461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_RELOAD_MODE, direction); +5462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; + 10951 .loc 1 5465 28 + 10952 01a8 FB68 ldr r3, [r7, #12] + 10953 01aa 5B8D ldrh r3, [r3, #42] @ movhi + 10954 01ac 9AB2 uxth r2, r3 + 10955 .loc 1 5465 22 + 10956 01ae FB68 ldr r3, [r7, #12] + 10957 01b0 1A85 strh r2, [r3, #40] @ movhi +5466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set NBYTES to write and generate RESTART */ +5468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + 10958 .loc 1 5468 46 + 10959 01b2 FB68 ldr r3, [r7, #12] + 10960 01b4 DB6C ldr r3, [r3, #76] + 10961 .loc 1 5468 7 + 10962 01b6 99B2 uxth r1, r3 + 10963 .loc 1 5468 73 + 10964 01b8 FB68 ldr r3, [r7, #12] + 10965 01ba 1B8D ldrh r3, [r3, #40] + 10966 .loc 1 5468 7 + 10967 01bc DAB2 uxtb r2, r3 + 10968 01be 7B69 ldr r3, [r7, #20] + 10969 01c0 0093 str r3, [sp] + 10970 01c2 4FF00073 mov r3, #33554432 + 10971 01c6 F868 ldr r0, [r7, #12] + 10972 01c8 FFF7FEFF bl I2C_TransferConfig + 10973 .L525: +5469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_AUTOEND_MODE, direction); +5470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update XferCount value */ +5473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount -= hi2c->XferSize; + 10974 .loc 1 5473 9 + 10975 01cc FB68 ldr r3, [r7, #12] + 10976 01ce 5B8D ldrh r3, [r3, #42] @ movhi + 10977 01d0 9AB2 uxth r2, r3 + 10978 .loc 1 5473 28 + 10979 01d2 FB68 ldr r3, [r7, #12] + 10980 01d4 1B8D ldrh r3, [r3, #40] + 10981 .loc 1 5473 21 + 10982 01d6 D31A subs r3, r2, r3 + 10983 01d8 9AB2 uxth r2, r3 + 10984 01da FB68 ldr r3, [r7, #12] + 10985 01dc 5A85 strh r2, [r3, #42] @ movhi +5474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable DMA Request */ +5476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + 10986 .loc 1 5476 13 + 10987 01de FB68 ldr r3, [r7, #12] + ARM GAS /tmp/cc5G5cqz.s page 291 + + + 10988 01e0 93F84130 ldrb r3, [r3, #65] + 10989 01e4 DBB2 uxtb r3, r3 + 10990 .loc 1 5476 8 + 10991 01e6 222B cmp r3, #34 + 10992 01e8 08D1 bne .L526 +5477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + 10993 .loc 1 5478 11 + 10994 01ea FB68 ldr r3, [r7, #12] + 10995 01ec 1B68 ldr r3, [r3] + 10996 .loc 1 5478 21 + 10997 01ee 1A68 ldr r2, [r3] + 10998 .loc 1 5478 11 + 10999 01f0 FB68 ldr r3, [r7, #12] + 11000 01f2 1B68 ldr r3, [r3] + 11001 .loc 1 5478 27 + 11002 01f4 42F40042 orr r2, r2, #32768 + 11003 01f8 1A60 str r2, [r3] +5476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11004 .loc 1 5476 8 + 11005 01fa 18E0 b .L514 + 11006 .L526: +5479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + 11007 .loc 1 5482 11 + 11008 01fc FB68 ldr r3, [r7, #12] + 11009 01fe 1B68 ldr r3, [r3] + 11010 .loc 1 5482 21 + 11011 0200 1A68 ldr r2, [r3] + 11012 .loc 1 5482 11 + 11013 0202 FB68 ldr r3, [r7, #12] + 11014 0204 1B68 ldr r3, [r3] + 11015 .loc 1 5482 27 + 11016 0206 42F48042 orr r2, r2, #16384 + 11017 020a 1A60 str r2, [r3] +5476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11018 .loc 1 5476 8 + 11019 020c 0FE0 b .L514 + 11020 .L522: +5483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ + 11021 .loc 1 5485 13 + 11022 020e BB68 ldr r3, [r7, #8] + 11023 0210 5B09 lsrs r3, r3, #5 + 11024 0212 03F00103 and r3, r3, #1 + 11025 .loc 1 5485 11 + 11026 0216 002B cmp r3, #0 + 11027 0218 09D0 beq .L514 +5486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 11028 .loc 1 5486 13 + 11029 021a 7B68 ldr r3, [r7, #4] + 11030 021c 5B09 lsrs r3, r3, #5 + 11031 021e 03F00103 and r3, r3, #1 +5485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + ARM GAS /tmp/cc5G5cqz.s page 292 + + + 11032 .loc 1 5485 63 discriminator 1 + 11033 0222 002B cmp r3, #0 + 11034 0224 03D0 beq .L514 +5487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call I2C Master complete process */ +5489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITMasterCplt(hi2c, ITFlags); + 11035 .loc 1 5489 5 + 11036 0226 B968 ldr r1, [r7, #8] + 11037 0228 F868 ldr r0, [r7, #12] + 11038 022a FFF7FEFF bl I2C_ITMasterCplt + 11039 .L514: +5490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Nothing to do */ +5494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +5497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 11040 .loc 1 5497 3 + 11041 022e FB68 ldr r3, [r7, #12] + 11042 0230 0022 movs r2, #0 + 11043 0232 83F84020 strb r2, [r3, #64] +5498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; + 11044 .loc 1 5499 10 + 11045 0236 0023 movs r3, #0 + 11046 .L512: +5500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11047 .loc 1 5500 1 + 11048 0238 1846 mov r0, r3 + 11049 023a 1837 adds r7, r7, #24 + 11050 .cfi_def_cfa_offset 8 + 11051 023c BD46 mov sp, r7 + 11052 .cfi_def_cfa_register 13 + 11053 @ sp needed + 11054 023e 80BD pop {r7, pc} + 11055 .L529: + 11056 .align 2 + 11057 .L528: + 11058 0240 00200080 .word -2147475456 + 11059 0244 00240080 .word -2147474432 + 11060 .cfi_endproc + 11061 .LFE183: + 11063 .section .text.I2C_Slave_ISR_DMA,"ax",%progbits + 11064 .align 1 + 11065 .syntax unified + 11066 .thumb + 11067 .thumb_func + 11069 I2C_Slave_ISR_DMA: + 11070 .LFB184: +5501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +5503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA. +5504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +5505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +5506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. + ARM GAS /tmp/cc5G5cqz.s page 293 + + +5507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param ITSources Interrupt sources enabled. +5508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +5509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +5510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, +5511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t ITSources) +5512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11071 .loc 1 5512 1 + 11072 .cfi_startproc + 11073 @ args = 0, pretend = 0, frame = 32 + 11074 @ frame_needed = 1, uses_anonymous_args = 0 + 11075 0000 80B5 push {r7, lr} + 11076 .cfi_def_cfa_offset 8 + 11077 .cfi_offset 7, -8 + 11078 .cfi_offset 14, -4 + 11079 0002 88B0 sub sp, sp, #32 + 11080 .cfi_def_cfa_offset 40 + 11081 0004 00AF add r7, sp, #0 + 11082 .cfi_def_cfa_register 7 + 11083 0006 F860 str r0, [r7, #12] + 11084 0008 B960 str r1, [r7, #8] + 11085 000a 7A60 str r2, [r7, #4] +5513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; + 11086 .loc 1 5513 12 + 11087 000c FB68 ldr r3, [r7, #12] + 11088 000e DB6A ldr r3, [r3, #44] + 11089 0010 BB61 str r3, [r7, #24] +5514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t treatdmanack = 0U; + 11090 .loc 1 5514 12 + 11091 0012 0023 movs r3, #0 + 11092 0014 FB61 str r3, [r7, #28] +5515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_StateTypeDef tmpstate; +5516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process locked */ +5518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_LOCK(hi2c); + 11093 .loc 1 5518 3 + 11094 0016 FB68 ldr r3, [r7, #12] + 11095 0018 93F84030 ldrb r3, [r3, #64] @ zero_extendqisi2 + 11096 001c 012B cmp r3, #1 + 11097 001e 01D1 bne .L531 + 11098 .loc 1 5518 3 is_stmt 0 discriminator 1 + 11099 0020 0223 movs r3, #2 + 11100 .loc 1 5518 3 + 11101 0022 C9E0 b .L532 + 11102 .L531: + 11103 .loc 1 5518 3 discriminator 2 + 11104 0024 FB68 ldr r3, [r7, #12] + 11105 0026 0122 movs r2, #1 + 11106 0028 83F84020 strb r2, [r3, #64] +5519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check if STOPF is set */ +5521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ + 11107 .loc 1 5521 8 is_stmt 1 + 11108 002c BB68 ldr r3, [r7, #8] + 11109 002e 5B09 lsrs r3, r3, #5 + 11110 0030 03F00103 and r3, r3, #1 + 11111 .loc 1 5521 6 + 11112 0034 002B cmp r3, #0 + ARM GAS /tmp/cc5G5cqz.s page 294 + + + 11113 0036 09D0 beq .L533 +5522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 11114 .loc 1 5522 8 + 11115 0038 7B68 ldr r3, [r7, #4] + 11116 003a 5B09 lsrs r3, r3, #5 + 11117 003c 03F00103 and r3, r3, #1 +5521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + 11118 .loc 1 5521 58 discriminator 1 + 11119 0040 002B cmp r3, #0 + 11120 0042 03D0 beq .L533 +5523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call I2C Slave complete process */ +5525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITSlaveCplt(hi2c, ITFlags); + 11121 .loc 1 5525 5 + 11122 0044 B968 ldr r1, [r7, #8] + 11123 0046 F868 ldr r0, [r7, #12] + 11124 0048 FFF7FEFF bl I2C_ITSlaveCplt + 11125 .L533: +5526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + 11126 .loc 1 5528 8 + 11127 004c BB68 ldr r3, [r7, #8] + 11128 004e 1B09 lsrs r3, r3, #4 + 11129 0050 03F00103 and r3, r3, #1 + 11130 .loc 1 5528 6 + 11131 0054 002B cmp r3, #0 + 11132 0056 00F09A80 beq .L534 +5529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 11133 .loc 1 5529 8 + 11134 005a 7B68 ldr r3, [r7, #4] + 11135 005c 1B09 lsrs r3, r3, #4 + 11136 005e 03F00103 and r3, r3, #1 +5528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + 11137 .loc 1 5528 55 discriminator 1 + 11138 0062 002B cmp r3, #0 + 11139 0064 00F09380 beq .L534 +5530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check that I2C transfer finished */ +5532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ +5533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Mean XferCount == 0 */ +5534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* So clear Flag NACKF only */ +5535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) || + 11140 .loc 1 5535 10 + 11141 0068 7B68 ldr r3, [r7, #4] + 11142 006a 9B0B lsrs r3, r3, #14 + 11143 006c 03F00103 and r3, r3, #1 + 11144 .loc 1 5535 8 + 11145 0070 002B cmp r3, #0 + 11146 0072 05D1 bne .L535 +5536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)) + 11147 .loc 1 5536 10 + 11148 0074 7B68 ldr r3, [r7, #4] + 11149 0076 DB0B lsrs r3, r3, #15 + 11150 0078 03F00103 and r3, r3, #1 +5535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)) + 11151 .loc 1 5535 68 discriminator 1 + ARM GAS /tmp/cc5G5cqz.s page 295 + + + 11152 007c 002B cmp r3, #0 + 11153 007e 7FD0 beq .L536 + 11154 .L535: +5537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Split check of hdmarx, for MISRA compliance */ +5539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) + 11155 .loc 1 5539 15 + 11156 0080 FB68 ldr r3, [r7, #12] + 11157 0082 DB6B ldr r3, [r3, #60] + 11158 .loc 1 5539 10 + 11159 0084 002B cmp r3, #0 + 11160 0086 0DD0 beq .L537 +5540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET) + 11161 .loc 1 5541 13 + 11162 0088 7B68 ldr r3, [r7, #4] + 11163 008a DB0B lsrs r3, r3, #15 + 11164 008c 03F00103 and r3, r3, #1 + 11165 .loc 1 5541 12 + 11166 0090 002B cmp r3, #0 + 11167 0092 07D0 beq .L537 +5542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) + 11168 .loc 1 5543 15 + 11169 0094 FB68 ldr r3, [r7, #12] + 11170 0096 DB6B ldr r3, [r3, #60] + 11171 0098 1B68 ldr r3, [r3] + 11172 009a 5B68 ldr r3, [r3, #4] + 11173 .loc 1 5543 14 + 11174 009c 002B cmp r3, #0 + 11175 009e 01D1 bne .L537 +5544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** treatdmanack = 1U; + 11176 .loc 1 5545 26 + 11177 00a0 0123 movs r3, #1 + 11178 00a2 FB61 str r3, [r7, #28] + 11179 .L537: +5546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Split check of hdmatx, for MISRA compliance */ +5551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) + 11180 .loc 1 5551 15 + 11181 00a4 FB68 ldr r3, [r7, #12] + 11182 00a6 9B6B ldr r3, [r3, #56] + 11183 .loc 1 5551 10 + 11184 00a8 002B cmp r3, #0 + 11185 00aa 0DD0 beq .L538 +5552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) + 11186 .loc 1 5553 13 + 11187 00ac 7B68 ldr r3, [r7, #4] + 11188 00ae 9B0B lsrs r3, r3, #14 + 11189 00b0 03F00103 and r3, r3, #1 + 11190 .loc 1 5553 12 + 11191 00b4 002B cmp r3, #0 + ARM GAS /tmp/cc5G5cqz.s page 296 + + + 11192 00b6 07D0 beq .L538 +5554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U) + 11193 .loc 1 5555 15 + 11194 00b8 FB68 ldr r3, [r7, #12] + 11195 00ba 9B6B ldr r3, [r3, #56] + 11196 00bc 1B68 ldr r3, [r3] + 11197 00be 5B68 ldr r3, [r3, #4] + 11198 .loc 1 5555 14 + 11199 00c0 002B cmp r3, #0 + 11200 00c2 01D1 bne .L538 +5556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** treatdmanack = 1U; + 11201 .loc 1 5557 26 + 11202 00c4 0123 movs r3, #1 + 11203 00c6 FB61 str r3, [r7, #28] + 11204 .L538: +5558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (treatdmanack == 1U) + 11205 .loc 1 5562 10 + 11206 00c8 FB69 ldr r3, [r7, #28] + 11207 00ca 012B cmp r3, #1 + 11208 00cc 28D1 bne .L539 +5563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) + 11209 .loc 1 5564 18 + 11210 00ce FB68 ldr r3, [r7, #12] + 11211 00d0 93F84130 ldrb r3, [r3, #65] + 11212 00d4 DBB2 uxtb r3, r3 + 11213 .loc 1 5564 12 + 11214 00d6 282B cmp r3, #40 + 11215 00d8 08D1 bne .L540 + 11216 .loc 1 5564 51 discriminator 1 + 11217 00da BB69 ldr r3, [r7, #24] + 11218 00dc B3F1007F cmp r3, #33554432 + 11219 00e0 04D1 bne .L540 +5565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for +5566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** Warning[Pa134]: left and right operands are identical */ +5567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call I2C Listen complete process */ +5569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITListenCplt(hi2c, ITFlags); + 11220 .loc 1 5569 11 + 11221 00e2 B968 ldr r1, [r7, #8] + 11222 00e4 F868 ldr r0, [r7, #12] + 11223 00e6 FFF7FEFF bl I2C_ITListenCplt + 11224 00ea 48E0 b .L543 + 11225 .L540: +5570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAM + 11226 .loc 1 5571 23 + 11227 00ec FB68 ldr r3, [r7, #12] + 11228 00ee 93F84130 ldrb r3, [r3, #65] + 11229 00f2 DBB2 uxtb r3, r3 + 11230 .loc 1 5571 17 + ARM GAS /tmp/cc5G5cqz.s page 297 + + + 11231 00f4 292B cmp r3, #41 + 11232 00f6 0ED1 bne .L542 + 11233 .loc 1 5571 64 discriminator 1 + 11234 00f8 BB69 ldr r3, [r7, #24] + 11235 00fa 13F5803F cmn r3, #65536 + 11236 00fe 0AD0 beq .L542 +5572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear NACK Flag */ +5574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + 11237 .loc 1 5574 11 + 11238 0100 FB68 ldr r3, [r7, #12] + 11239 0102 1B68 ldr r3, [r3] + 11240 0104 1022 movs r2, #16 + 11241 0106 DA61 str r2, [r3, #28] +5575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Flush TX register */ +5577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); + 11242 .loc 1 5577 11 + 11243 0108 F868 ldr r0, [r7, #12] + 11244 010a FFF7FEFF bl I2C_Flush_TXDR +5578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Last Byte is Transmitted */ +5580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call I2C Slave Sequential complete process */ +5581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITSlaveSeqCplt(hi2c); + 11245 .loc 1 5581 11 + 11246 010e F868 ldr r0, [r7, #12] + 11247 0110 FFF7FEFF bl I2C_ITSlaveSeqCplt + 11248 0114 33E0 b .L543 + 11249 .L542: +5582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear NACK Flag */ +5586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + 11250 .loc 1 5586 11 + 11251 0116 FB68 ldr r3, [r7, #12] + 11252 0118 1B68 ldr r3, [r3] + 11253 011a 1022 movs r2, #16 + 11254 011c DA61 str r2, [r3, #28] +5562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11255 .loc 1 5562 10 + 11256 011e 34E0 b .L551 + 11257 .L539: +5587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ +5592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear NACK Flag */ +5593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + 11258 .loc 1 5593 9 + 11259 0120 FB68 ldr r3, [r7, #12] + 11260 0122 1B68 ldr r3, [r3] + 11261 0124 1022 movs r2, #16 + 11262 0126 DA61 str r2, [r3, #28] +5594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set ErrorCode corresponding to a Non-Acknowledge */ + ARM GAS /tmp/cc5G5cqz.s page 298 + + +5596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + 11263 .loc 1 5596 13 + 11264 0128 FB68 ldr r3, [r7, #12] + 11265 012a 5B6C ldr r3, [r3, #68] + 11266 .loc 1 5596 25 + 11267 012c 43F00402 orr r2, r3, #4 + 11268 0130 FB68 ldr r3, [r7, #12] + 11269 0132 5A64 str r2, [r3, #68] +5597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */ +5599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmpstate = hi2c->State; + 11270 .loc 1 5599 18 + 11271 0134 FB68 ldr r3, [r7, #12] + 11272 0136 93F84130 ldrb r3, [r3, #65] + 11273 013a FB75 strb r3, [r7, #23] +5600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) + 11274 .loc 1 5601 12 + 11275 013c BB69 ldr r3, [r7, #24] + 11276 013e 002B cmp r3, #0 + 11277 0140 03D0 beq .L544 + 11278 .loc 1 5601 45 discriminator 1 + 11279 0142 BB69 ldr r3, [r7, #24] + 11280 0144 B3F1807F cmp r3, #16777216 + 11281 0148 1FD1 bne .L551 + 11282 .L544: +5602:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) + 11283 .loc 1 5603 14 + 11284 014a FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 11285 014c 212B cmp r3, #33 + 11286 014e 02D0 beq .L545 + 11287 .loc 1 5603 51 discriminator 1 + 11288 0150 FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 11289 0152 292B cmp r3, #41 + 11290 0154 03D1 bne .L546 + 11291 .L545: +5604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + 11292 .loc 1 5605 33 + 11293 0156 FB68 ldr r3, [r7, #12] + 11294 0158 2122 movs r2, #33 + 11295 015a 1A63 str r2, [r3, #48] + 11296 015c 08E0 b .L547 + 11297 .L546: +5606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN + 11298 .loc 1 5607 19 + 11299 015e FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 11300 0160 222B cmp r3, #34 + 11301 0162 02D0 beq .L548 + 11302 .loc 1 5607 56 discriminator 1 + 11303 0164 FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 11304 0166 2A2B cmp r3, #42 + 11305 0168 02D1 bne .L547 + 11306 .L548: +5608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + ARM GAS /tmp/cc5G5cqz.s page 299 + + +5609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + 11307 .loc 1 5609 33 + 11308 016a FB68 ldr r3, [r7, #12] + 11309 016c 2222 movs r2, #34 + 11310 016e 1A63 str r2, [r3, #48] + 11311 .L547: +5610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5612:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Do nothing */ +5614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITError(hi2c, hi2c->ErrorCode); + 11312 .loc 1 5617 33 + 11313 0170 FB68 ldr r3, [r7, #12] + 11314 0172 5B6C ldr r3, [r3, #68] + 11315 .loc 1 5617 11 + 11316 0174 1946 mov r1, r3 + 11317 0176 F868 ldr r0, [r7, #12] + 11318 0178 FFF7FEFF bl I2C_ITError +5562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11319 .loc 1 5562 10 + 11320 017c 05E0 b .L551 + 11321 .L543: + 11322 017e 04E0 b .L551 + 11323 .L536: +5618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Only Clear NACK Flag, no DMA treatment is pending */ +5624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + 11324 .loc 1 5624 7 + 11325 0180 FB68 ldr r3, [r7, #12] + 11326 0182 1B68 ldr r3, [r3] + 11327 0184 1022 movs r2, #16 + 11328 0186 DA61 str r2, [r3, #28] +5535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)) + 11329 .loc 1 5535 8 + 11330 0188 11E0 b .L550 + 11331 .L551: +5562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11332 .loc 1 5562 10 + 11333 018a 00BF nop +5535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)) + 11334 .loc 1 5535 8 + 11335 018c 0FE0 b .L550 + 11336 .L534: +5625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \ + 11337 .loc 1 5627 13 + 11338 018e BB68 ldr r3, [r7, #8] + 11339 0190 DB08 lsrs r3, r3, #3 + 11340 0192 03F00103 and r3, r3, #1 + ARM GAS /tmp/cc5G5cqz.s page 300 + + + 11341 .loc 1 5627 11 + 11342 0196 002B cmp r3, #0 + 11343 0198 09D0 beq .L550 +5628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + 11344 .loc 1 5628 13 + 11345 019a 7B68 ldr r3, [r7, #4] + 11346 019c DB08 lsrs r3, r3, #3 + 11347 019e 03F00103 and r3, r3, #1 +5627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + 11348 .loc 1 5627 62 discriminator 1 + 11349 01a2 002B cmp r3, #0 + 11350 01a4 03D0 beq .L550 +5629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITAddrCplt(hi2c, ITFlags); + 11351 .loc 1 5630 5 + 11352 01a6 B968 ldr r1, [r7, #8] + 11353 01a8 F868 ldr r0, [r7, #12] + 11354 01aa FFF7FEFF bl I2C_ITAddrCplt + 11355 .L550: +5631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Nothing to do */ +5635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +5638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 11356 .loc 1 5638 3 + 11357 01ae FB68 ldr r3, [r7, #12] + 11358 01b0 0022 movs r2, #0 + 11359 01b2 83F84020 strb r2, [r3, #64] +5639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; + 11360 .loc 1 5640 10 + 11361 01b6 0023 movs r3, #0 + 11362 .L532: +5641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11363 .loc 1 5641 1 + 11364 01b8 1846 mov r0, r3 + 11365 01ba 2037 adds r7, r7, #32 + 11366 .cfi_def_cfa_offset 8 + 11367 01bc BD46 mov sp, r7 + 11368 .cfi_def_cfa_register 13 + 11369 @ sp needed + 11370 01be 80BD pop {r7, pc} + 11371 .cfi_endproc + 11372 .LFE184: + 11374 .section .text.I2C_RequestMemoryWrite,"ax",%progbits + 11375 .align 1 + 11376 .syntax unified + 11377 .thumb + 11378 .thumb_func + 11380 I2C_RequestMemoryWrite: + 11381 .LFB185: +5642:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +5644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Master sends target device address followed by internal memory address for write reques + ARM GAS /tmp/cc5G5cqz.s page 301 + + +5645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +5646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +5647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +5648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +5649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param MemAddress Internal memory address +5650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param MemAddSize Size of internal memory address +5651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Timeout Timeout duration +5652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Tickstart Tick start value +5653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +5654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +5655:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, +5656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t MemAddress, uint16_t MemAddSize, uint32_t +5657:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t Tickstart) +5658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11382 .loc 1 5658 1 + 11383 .cfi_startproc + 11384 @ args = 8, pretend = 0, frame = 16 + 11385 @ frame_needed = 1, uses_anonymous_args = 0 + 11386 0000 80B5 push {r7, lr} + 11387 .cfi_def_cfa_offset 8 + 11388 .cfi_offset 7, -8 + 11389 .cfi_offset 14, -4 + 11390 0002 86B0 sub sp, sp, #24 + 11391 .cfi_def_cfa_offset 32 + 11392 0004 02AF add r7, sp, #8 + 11393 .cfi_def_cfa 7, 24 + 11394 0006 F860 str r0, [r7, #12] + 11395 0008 0846 mov r0, r1 + 11396 000a 1146 mov r1, r2 + 11397 000c 1A46 mov r2, r3 + 11398 000e 0346 mov r3, r0 @ movhi + 11399 0010 7B81 strh r3, [r7, #10] @ movhi + 11400 0012 0B46 mov r3, r1 @ movhi + 11401 0014 3B81 strh r3, [r7, #8] @ movhi + 11402 0016 1346 mov r3, r2 @ movhi + 11403 0018 FB80 strh r3, [r7, #6] @ movhi +5659:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRI + 11404 .loc 1 5659 3 + 11405 001a FB88 ldrh r3, [r7, #6] @ movhi + 11406 001c DAB2 uxtb r2, r3 + 11407 001e 7989 ldrh r1, [r7, #10] + 11408 0020 204B ldr r3, .L559 + 11409 0022 0093 str r3, [sp] + 11410 0024 4FF08073 mov r3, #16777216 + 11411 0028 F868 ldr r0, [r7, #12] + 11412 002a FFF7FEFF bl I2C_TransferConfig +5660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until TXIS flag is set */ +5662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + 11413 .loc 1 5662 7 + 11414 002e FA69 ldr r2, [r7, #28] + 11415 0030 B969 ldr r1, [r7, #24] + 11416 0032 F868 ldr r0, [r7, #12] + 11417 0034 FFF7FEFF bl I2C_WaitOnTXISFlagUntilTimeout + 11418 0038 0346 mov r3, r0 + 11419 .loc 1 5662 6 discriminator 1 + 11420 003a 002B cmp r3, #0 + ARM GAS /tmp/cc5G5cqz.s page 302 + + + 11421 003c 01D0 beq .L553 +5663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5664:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 11422 .loc 1 5664 12 + 11423 003e 0123 movs r3, #1 + 11424 0040 2CE0 b .L554 + 11425 .L553: +5665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* If Memory address size is 8Bit */ +5668:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + 11426 .loc 1 5668 6 + 11427 0042 FB88 ldrh r3, [r7, #6] + 11428 0044 012B cmp r3, #1 + 11429 0046 05D1 bne .L555 +5669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send Memory Address */ +5671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + 11430 .loc 1 5671 28 + 11431 0048 3B89 ldrh r3, [r7, #8] @ movhi + 11432 004a DAB2 uxtb r2, r3 + 11433 .loc 1 5671 9 + 11434 004c FB68 ldr r3, [r7, #12] + 11435 004e 1B68 ldr r3, [r3] + 11436 .loc 1 5671 26 + 11437 0050 9A62 str r2, [r3, #40] + 11438 0052 15E0 b .L556 + 11439 .L555: +5672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* If Memory address size is 16Bit */ +5674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send MSB of Memory Address */ +5677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + 11440 .loc 1 5677 28 + 11441 0054 3B89 ldrh r3, [r7, #8] + 11442 0056 1B0A lsrs r3, r3, #8 + 11443 0058 9BB2 uxth r3, r3 + 11444 005a DAB2 uxtb r2, r3 + 11445 .loc 1 5677 9 + 11446 005c FB68 ldr r3, [r7, #12] + 11447 005e 1B68 ldr r3, [r3] + 11448 .loc 1 5677 26 + 11449 0060 9A62 str r2, [r3, #40] +5678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until TXIS flag is set */ +5680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + 11450 .loc 1 5680 9 + 11451 0062 FA69 ldr r2, [r7, #28] + 11452 0064 B969 ldr r1, [r7, #24] + 11453 0066 F868 ldr r0, [r7, #12] + 11454 0068 FFF7FEFF bl I2C_WaitOnTXISFlagUntilTimeout + 11455 006c 0346 mov r3, r0 + 11456 .loc 1 5680 8 discriminator 1 + 11457 006e 002B cmp r3, #0 + 11458 0070 01D0 beq .L557 +5681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + ARM GAS /tmp/cc5G5cqz.s page 303 + + +5682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 11459 .loc 1 5682 14 + 11460 0072 0123 movs r3, #1 + 11461 0074 12E0 b .L554 + 11462 .L557: +5683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send LSB of Memory Address */ +5686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + 11463 .loc 1 5686 28 + 11464 0076 3B89 ldrh r3, [r7, #8] @ movhi + 11465 0078 DAB2 uxtb r2, r3 + 11466 .loc 1 5686 9 + 11467 007a FB68 ldr r3, [r7, #12] + 11468 007c 1B68 ldr r3, [r3] + 11469 .loc 1 5686 26 + 11470 007e 9A62 str r2, [r3, #40] + 11471 .L556: +5687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5688:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until TCR flag is set */ +5690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) + 11472 .loc 1 5690 7 + 11473 0080 FB69 ldr r3, [r7, #28] + 11474 0082 0093 str r3, [sp] + 11475 0084 BB69 ldr r3, [r7, #24] + 11476 0086 0022 movs r2, #0 + 11477 0088 8021 movs r1, #128 + 11478 008a F868 ldr r0, [r7, #12] + 11479 008c FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 11480 0090 0346 mov r3, r0 + 11481 .loc 1 5690 6 discriminator 1 + 11482 0092 002B cmp r3, #0 + 11483 0094 01D0 beq .L558 +5691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 11484 .loc 1 5692 12 + 11485 0096 0123 movs r3, #1 + 11486 0098 00E0 b .L554 + 11487 .L558: +5693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5694:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; + 11488 .loc 1 5695 10 + 11489 009a 0023 movs r3, #0 + 11490 .L554: +5696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11491 .loc 1 5696 1 + 11492 009c 1846 mov r0, r3 + 11493 009e 1037 adds r7, r7, #16 + 11494 .cfi_def_cfa_offset 8 + 11495 00a0 BD46 mov sp, r7 + 11496 .cfi_def_cfa_register 13 + 11497 @ sp needed + 11498 00a2 80BD pop {r7, pc} + 11499 .L560: + 11500 .align 2 + ARM GAS /tmp/cc5G5cqz.s page 304 + + + 11501 .L559: + 11502 00a4 00200080 .word -2147475456 + 11503 .cfi_endproc + 11504 .LFE185: + 11506 .section .text.I2C_RequestMemoryRead,"ax",%progbits + 11507 .align 1 + 11508 .syntax unified + 11509 .thumb + 11510 .thumb_func + 11512 I2C_RequestMemoryRead: + 11513 .LFB186: +5697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +5699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Master sends target device address followed by internal memory address for read request +5700:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +5701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +5702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param DevAddress Target device address: The device 7 bits address value +5703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * in datasheet must be shifted to the left before calling the interface +5704:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param MemAddress Internal memory address +5705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param MemAddSize Size of internal memory address +5706:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Timeout Timeout duration +5707:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Tickstart Tick start value +5708:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +5709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +5710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, +5711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t MemAddress, uint16_t MemAddSize, uint32_t T +5712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t Tickstart) +5713:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11514 .loc 1 5713 1 + 11515 .cfi_startproc + 11516 @ args = 8, pretend = 0, frame = 16 + 11517 @ frame_needed = 1, uses_anonymous_args = 0 + 11518 0000 80B5 push {r7, lr} + 11519 .cfi_def_cfa_offset 8 + 11520 .cfi_offset 7, -8 + 11521 .cfi_offset 14, -4 + 11522 0002 86B0 sub sp, sp, #24 + 11523 .cfi_def_cfa_offset 32 + 11524 0004 02AF add r7, sp, #8 + 11525 .cfi_def_cfa 7, 24 + 11526 0006 F860 str r0, [r7, #12] + 11527 0008 0846 mov r0, r1 + 11528 000a 1146 mov r1, r2 + 11529 000c 1A46 mov r2, r3 + 11530 000e 0346 mov r3, r0 @ movhi + 11531 0010 7B81 strh r3, [r7, #10] @ movhi + 11532 0012 0B46 mov r3, r1 @ movhi + 11533 0014 3B81 strh r3, [r7, #8] @ movhi + 11534 0016 1346 mov r3, r2 @ movhi + 11535 0018 FB80 strh r3, [r7, #6] @ movhi +5714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WR + 11536 .loc 1 5714 3 + 11537 001a FB88 ldrh r3, [r7, #6] @ movhi + 11538 001c DAB2 uxtb r2, r3 + 11539 001e 7989 ldrh r1, [r7, #10] + 11540 0020 204B ldr r3, .L568 + 11541 0022 0093 str r3, [sp] + ARM GAS /tmp/cc5G5cqz.s page 305 + + + 11542 0024 0023 movs r3, #0 + 11543 0026 F868 ldr r0, [r7, #12] + 11544 0028 FFF7FEFF bl I2C_TransferConfig +5715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5716:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until TXIS flag is set */ +5717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + 11545 .loc 1 5717 7 + 11546 002c FA69 ldr r2, [r7, #28] + 11547 002e B969 ldr r1, [r7, #24] + 11548 0030 F868 ldr r0, [r7, #12] + 11549 0032 FFF7FEFF bl I2C_WaitOnTXISFlagUntilTimeout + 11550 0036 0346 mov r3, r0 + 11551 .loc 1 5717 6 discriminator 1 + 11552 0038 002B cmp r3, #0 + 11553 003a 01D0 beq .L562 +5718:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 11554 .loc 1 5719 12 + 11555 003c 0123 movs r3, #1 + 11556 003e 2CE0 b .L563 + 11557 .L562: +5720:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5722:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* If Memory address size is 8Bit */ +5723:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + 11558 .loc 1 5723 6 + 11559 0040 FB88 ldrh r3, [r7, #6] + 11560 0042 012B cmp r3, #1 + 11561 0044 05D1 bne .L564 +5724:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5725:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send Memory Address */ +5726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + 11562 .loc 1 5726 28 + 11563 0046 3B89 ldrh r3, [r7, #8] @ movhi + 11564 0048 DAB2 uxtb r2, r3 + 11565 .loc 1 5726 9 + 11566 004a FB68 ldr r3, [r7, #12] + 11567 004c 1B68 ldr r3, [r3] + 11568 .loc 1 5726 26 + 11569 004e 9A62 str r2, [r3, #40] + 11570 0050 15E0 b .L565 + 11571 .L564: +5727:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* If Memory address size is 16Bit */ +5729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send MSB of Memory Address */ +5732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + 11572 .loc 1 5732 28 + 11573 0052 3B89 ldrh r3, [r7, #8] + 11574 0054 1B0A lsrs r3, r3, #8 + 11575 0056 9BB2 uxth r3, r3 + 11576 0058 DAB2 uxtb r2, r3 + 11577 .loc 1 5732 9 + 11578 005a FB68 ldr r3, [r7, #12] + 11579 005c 1B68 ldr r3, [r3] + 11580 .loc 1 5732 26 + ARM GAS /tmp/cc5G5cqz.s page 306 + + + 11581 005e 9A62 str r2, [r3, #40] +5733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5734:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until TXIS flag is set */ +5735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + 11582 .loc 1 5735 9 + 11583 0060 FA69 ldr r2, [r7, #28] + 11584 0062 B969 ldr r1, [r7, #24] + 11585 0064 F868 ldr r0, [r7, #12] + 11586 0066 FFF7FEFF bl I2C_WaitOnTXISFlagUntilTimeout + 11587 006a 0346 mov r3, r0 + 11588 .loc 1 5735 8 discriminator 1 + 11589 006c 002B cmp r3, #0 + 11590 006e 01D0 beq .L566 +5736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5737:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 11591 .loc 1 5737 14 + 11592 0070 0123 movs r3, #1 + 11593 0072 12E0 b .L563 + 11594 .L566: +5738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5739:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Send LSB of Memory Address */ +5741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + 11595 .loc 1 5741 28 + 11596 0074 3B89 ldrh r3, [r7, #8] @ movhi + 11597 0076 DAB2 uxtb r2, r3 + 11598 .loc 1 5741 9 + 11599 0078 FB68 ldr r3, [r7, #12] + 11600 007a 1B68 ldr r3, [r3] + 11601 .loc 1 5741 26 + 11602 007c 9A62 str r2, [r3, #40] + 11603 .L565: +5742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5743:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until TC flag is set */ +5745:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) + 11604 .loc 1 5745 7 + 11605 007e FB69 ldr r3, [r7, #28] + 11606 0080 0093 str r3, [sp] + 11607 0082 BB69 ldr r3, [r7, #24] + 11608 0084 0022 movs r2, #0 + 11609 0086 4021 movs r1, #64 + 11610 0088 F868 ldr r0, [r7, #12] + 11611 008a FFF7FEFF bl I2C_WaitOnFlagUntilTimeout + 11612 008e 0346 mov r3, r0 + 11613 .loc 1 5745 6 discriminator 1 + 11614 0090 002B cmp r3, #0 + 11615 0092 01D0 beq .L567 +5746:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5747:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 11616 .loc 1 5747 12 + 11617 0094 0123 movs r3, #1 + 11618 0096 00E0 b .L563 + 11619 .L567: +5748:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; + ARM GAS /tmp/cc5G5cqz.s page 307 + + + 11620 .loc 1 5750 10 + 11621 0098 0023 movs r3, #0 + 11622 .L563: +5751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11623 .loc 1 5751 1 + 11624 009a 1846 mov r0, r3 + 11625 009c 1037 adds r7, r7, #16 + 11626 .cfi_def_cfa_offset 8 + 11627 009e BD46 mov sp, r7 + 11628 .cfi_def_cfa_register 13 + 11629 @ sp needed + 11630 00a0 80BD pop {r7, pc} + 11631 .L569: + 11632 00a2 00BF .align 2 + 11633 .L568: + 11634 00a4 00200080 .word -2147475456 + 11635 .cfi_endproc + 11636 .LFE186: + 11638 .section .text.I2C_ITAddrCplt,"ax",%progbits + 11639 .align 1 + 11640 .syntax unified + 11641 .thumb + 11642 .thumb_func + 11644 I2C_ITAddrCplt: + 11645 .LFB187: +5752:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +5754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief I2C Address complete process callback. +5755:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c I2C handle. +5756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. +5757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +5758:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +5759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +5760:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11646 .loc 1 5760 1 + 11647 .cfi_startproc + 11648 @ args = 0, pretend = 0, frame = 16 + 11649 @ frame_needed = 1, uses_anonymous_args = 0 + 11650 0000 80B5 push {r7, lr} + 11651 .cfi_def_cfa_offset 8 + 11652 .cfi_offset 7, -8 + 11653 .cfi_offset 14, -4 + 11654 0002 84B0 sub sp, sp, #16 + 11655 .cfi_def_cfa_offset 24 + 11656 0004 00AF add r7, sp, #0 + 11657 .cfi_def_cfa_register 7 + 11658 0006 7860 str r0, [r7, #4] + 11659 0008 3960 str r1, [r7] +5761:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint8_t transferdirection; +5762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t slaveaddrcode; +5763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t ownadd1code; +5764:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint16_t ownadd2code; +5765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Prevent unused argument(s) compilation warning */ +5767:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** UNUSED(ITFlags); +5768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* In case of Listen state, need to inform upper layer of address match code event */ + ARM GAS /tmp/cc5G5cqz.s page 308 + + +5770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + 11660 .loc 1 5770 22 + 11661 000a 7B68 ldr r3, [r7, #4] + 11662 000c 93F84130 ldrb r3, [r3, #65] + 11663 0010 DBB2 uxtb r3, r3 + 11664 .loc 1 5770 30 + 11665 0012 03F02803 and r3, r3, #40 + 11666 .loc 1 5770 6 + 11667 0016 282B cmp r3, #40 + 11668 0018 6AD1 bne .L571 +5771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** transferdirection = I2C_GET_DIR(hi2c); + 11669 .loc 1 5772 25 + 11670 001a 7B68 ldr r3, [r7, #4] + 11671 001c 1B68 ldr r3, [r3] + 11672 001e 9B69 ldr r3, [r3, #24] + 11673 0020 1B0C lsrs r3, r3, #16 + 11674 0022 DBB2 uxtb r3, r3 + 11675 .loc 1 5772 23 + 11676 0024 03F00103 and r3, r3, #1 + 11677 0028 FB73 strb r3, [r7, #15] +5773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); + 11678 .loc 1 5773 25 + 11679 002a 7B68 ldr r3, [r7, #4] + 11680 002c 1B68 ldr r3, [r3] + 11681 002e 9B69 ldr r3, [r3, #24] + 11682 0030 1B0C lsrs r3, r3, #16 + 11683 0032 9BB2 uxth r3, r3 + 11684 .loc 1 5773 23 + 11685 0034 03F0FE03 and r3, r3, #254 + 11686 0038 BB81 strh r3, [r7, #12] @ movhi +5774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); + 11687 .loc 1 5774 25 + 11688 003a 7B68 ldr r3, [r7, #4] + 11689 003c 1B68 ldr r3, [r3] + 11690 003e 9B68 ldr r3, [r3, #8] + 11691 0040 9BB2 uxth r3, r3 + 11692 .loc 1 5774 23 + 11693 0042 C3F30903 ubfx r3, r3, #0, #10 + 11694 0046 7B81 strh r3, [r7, #10] @ movhi +5775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); + 11695 .loc 1 5775 25 + 11696 0048 7B68 ldr r3, [r7, #4] + 11697 004a 1B68 ldr r3, [r3] + 11698 004c DB68 ldr r3, [r3, #12] + 11699 004e 9BB2 uxth r3, r3 + 11700 .loc 1 5775 23 + 11701 0050 03F0FE03 and r3, r3, #254 + 11702 0054 3B81 strh r3, [r7, #8] @ movhi +5776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5777:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* If 10bits addressing mode is selected */ +5778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + 11703 .loc 1 5778 19 + 11704 0056 7B68 ldr r3, [r7, #4] + 11705 0058 DB68 ldr r3, [r3, #12] + 11706 .loc 1 5778 8 + 11707 005a 022B cmp r3, #2 + ARM GAS /tmp/cc5G5cqz.s page 309 + + + 11708 005c 38D1 bne .L572 +5779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5780:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK)) + 11709 .loc 1 5780 44 + 11710 005e 7B89 ldrh r3, [r7, #10] + 11711 0060 DB09 lsrs r3, r3, #7 + 11712 0062 9AB2 uxth r2, r3 + 11713 0064 BB89 ldrh r3, [r7, #12] @ movhi + 11714 0066 5340 eors r3, r3, r2 + 11715 0068 9BB2 uxth r3, r3 + 11716 006a 03F00603 and r3, r3, #6 + 11717 .loc 1 5780 10 + 11718 006e 002B cmp r3, #0 + 11719 0070 1CD1 bne .L573 +5781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5782:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** slaveaddrcode = ownadd1code; + 11720 .loc 1 5782 23 + 11721 0072 7B89 ldrh r3, [r7, #10] @ movhi + 11722 0074 BB81 strh r3, [r7, #12] @ movhi +5783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->AddrEventCount++; + 11723 .loc 1 5783 13 + 11724 0076 7B68 ldr r3, [r7, #4] + 11725 0078 9B6C ldr r3, [r3, #72] + 11726 .loc 1 5783 29 + 11727 007a 5A1C adds r2, r3, #1 + 11728 007c 7B68 ldr r3, [r7, #4] + 11729 007e 9A64 str r2, [r3, #72] +5784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->AddrEventCount == 2U) + 11730 .loc 1 5784 17 + 11731 0080 7B68 ldr r3, [r7, #4] + 11732 0082 9B6C ldr r3, [r3, #72] + 11733 .loc 1 5784 12 + 11734 0084 022B cmp r3, #2 + 11735 0086 3BD1 bne .L575 +5785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Reset Address Event counter */ +5787:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->AddrEventCount = 0U; + 11736 .loc 1 5787 32 + 11737 0088 7B68 ldr r3, [r7, #4] + 11738 008a 0022 movs r2, #0 + 11739 008c 9A64 str r2, [r3, #72] +5788:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear ADDR flag */ +5790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + 11740 .loc 1 5790 11 + 11741 008e 7B68 ldr r3, [r7, #4] + 11742 0090 1B68 ldr r3, [r3] + 11743 0092 0822 movs r2, #8 + 11744 0094 DA61 str r2, [r3, #28] +5791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +5793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 11745 .loc 1 5793 11 + 11746 0096 7B68 ldr r3, [r7, #4] + 11747 0098 0022 movs r2, #0 + 11748 009a 83F84020 strb r2, [r3, #64] +5794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/cc5G5cqz.s page 310 + + +5795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call Slave Addr callback */ +5796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +5798:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #else +5799:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); + 11749 .loc 1 5799 11 + 11750 009e BA89 ldrh r2, [r7, #12] + 11751 00a0 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 11752 00a2 1946 mov r1, r3 + 11753 00a4 7868 ldr r0, [r7, #4] + 11754 00a6 FFF7FEFF bl HAL_I2C_AddrCallback +5800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5803:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5804:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** slaveaddrcode = ownadd2code; +5806:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5807:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable ADDR Interrupts */ +5808:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); +5809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +5811:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call Slave Addr callback */ +5814:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +5816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #else +5817:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +5818:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5820:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5821:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* else 7 bits addressing mode is selected */ +5822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable ADDR Interrupts */ +5825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); +5826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5827:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +5828:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5829:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5830:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call Slave Addr callback */ +5831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5832:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +5833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #else +5834:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +5835:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5836:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Else clear address flag only */ +5839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5840:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear ADDR flag */ +5842:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); +5843:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5844:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +5845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + ARM GAS /tmp/cc5G5cqz.s page 311 + + +5846:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11755 .loc 1 5847 1 + 11756 00aa 29E0 b .L575 + 11757 .L573: +5805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11758 .loc 1 5805 23 + 11759 00ac 3B89 ldrh r3, [r7, #8] @ movhi + 11760 00ae BB81 strh r3, [r7, #12] @ movhi +5808:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11761 .loc 1 5808 9 + 11762 00b0 4FF40041 mov r1, #32768 + 11763 00b4 7868 ldr r0, [r7, #4] + 11764 00b6 FFF7FEFF bl I2C_Disable_IRQ +5811:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11765 .loc 1 5811 9 + 11766 00ba 7B68 ldr r3, [r7, #4] + 11767 00bc 0022 movs r2, #0 + 11768 00be 83F84020 strb r2, [r3, #64] +5817:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 11769 .loc 1 5817 9 + 11770 00c2 BA89 ldrh r2, [r7, #12] + 11771 00c4 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 11772 00c6 1946 mov r1, r3 + 11773 00c8 7868 ldr r0, [r7, #4] + 11774 00ca FFF7FEFF bl HAL_I2C_AddrCallback + 11775 .loc 1 5847 1 + 11776 00ce 17E0 b .L575 + 11777 .L572: +5825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11778 .loc 1 5825 7 + 11779 00d0 4FF40041 mov r1, #32768 + 11780 00d4 7868 ldr r0, [r7, #4] + 11781 00d6 FFF7FEFF bl I2C_Disable_IRQ +5828:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11782 .loc 1 5828 7 + 11783 00da 7B68 ldr r3, [r7, #4] + 11784 00dc 0022 movs r2, #0 + 11785 00de 83F84020 strb r2, [r3, #64] +5834:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 11786 .loc 1 5834 7 + 11787 00e2 BA89 ldrh r2, [r7, #12] + 11788 00e4 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 11789 00e6 1946 mov r1, r3 + 11790 00e8 7868 ldr r0, [r7, #4] + 11791 00ea FFF7FEFF bl HAL_I2C_AddrCallback + 11792 .loc 1 5847 1 + 11793 00ee 07E0 b .L575 + 11794 .L571: +5842:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11795 .loc 1 5842 5 + 11796 00f0 7B68 ldr r3, [r7, #4] + 11797 00f2 1B68 ldr r3, [r3] + 11798 00f4 0822 movs r2, #8 + 11799 00f6 DA61 str r2, [r3, #28] +5845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11800 .loc 1 5845 5 + ARM GAS /tmp/cc5G5cqz.s page 312 + + + 11801 00f8 7B68 ldr r3, [r7, #4] + 11802 00fa 0022 movs r2, #0 + 11803 00fc 83F84020 strb r2, [r3, #64] + 11804 .L575: + 11805 .loc 1 5847 1 + 11806 0100 00BF nop + 11807 0102 1037 adds r7, r7, #16 + 11808 .cfi_def_cfa_offset 8 + 11809 0104 BD46 mov sp, r7 + 11810 .cfi_def_cfa_register 13 + 11811 @ sp needed + 11812 0106 80BD pop {r7, pc} + 11813 .cfi_endproc + 11814 .LFE187: + 11816 .section .text.I2C_ITMasterSeqCplt,"ax",%progbits + 11817 .align 1 + 11818 .syntax unified + 11819 .thumb + 11820 .thumb_func + 11822 I2C_ITMasterSeqCplt: + 11823 .LFB188: +5848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +5850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief I2C Master sequential complete process. +5851:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c I2C handle. +5852:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +5853:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +5854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c) +5855:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11824 .loc 1 5855 1 + 11825 .cfi_startproc + 11826 @ args = 0, pretend = 0, frame = 8 + 11827 @ frame_needed = 1, uses_anonymous_args = 0 + 11828 0000 80B5 push {r7, lr} + 11829 .cfi_def_cfa_offset 8 + 11830 .cfi_offset 7, -8 + 11831 .cfi_offset 14, -4 + 11832 0002 82B0 sub sp, sp, #8 + 11833 .cfi_def_cfa_offset 16 + 11834 0004 00AF add r7, sp, #0 + 11835 .cfi_def_cfa_register 7 + 11836 0006 7860 str r0, [r7, #4] +5856:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Reset I2C handle mode */ +5857:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 11837 .loc 1 5857 14 + 11838 0008 7B68 ldr r3, [r7, #4] + 11839 000a 0022 movs r2, #0 + 11840 000c 83F84220 strb r2, [r3, #66] +5858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5859:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* No Generate Stop, to permit restart mode */ +5860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */ +5861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + 11841 .loc 1 5861 11 + 11842 0010 7B68 ldr r3, [r7, #4] + 11843 0012 93F84130 ldrb r3, [r3, #65] + 11844 0016 DBB2 uxtb r3, r3 + 11845 .loc 1 5861 6 + ARM GAS /tmp/cc5G5cqz.s page 313 + + + 11846 0018 212B cmp r3, #33 + 11847 001a 15D1 bne .L577 +5862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 11848 .loc 1 5863 25 + 11849 001c 7B68 ldr r3, [r7, #4] + 11850 001e 2022 movs r2, #32 + 11851 0020 83F84120 strb r2, [r3, #65] +5864:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + 11852 .loc 1 5864 25 + 11853 0024 7B68 ldr r3, [r7, #4] + 11854 0026 1122 movs r2, #17 + 11855 0028 1A63 str r2, [r3, #48] +5865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = NULL; + 11856 .loc 1 5865 25 + 11857 002a 7B68 ldr r3, [r7, #4] + 11858 002c 0022 movs r2, #0 + 11859 002e 5A63 str r2, [r3, #52] +5866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Interrupts */ +5868:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + 11860 .loc 1 5868 5 + 11861 0030 0121 movs r1, #1 + 11862 0032 7868 ldr r0, [r7, #4] + 11863 0034 FFF7FEFF bl I2C_Disable_IRQ +5869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5870:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +5871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 11864 .loc 1 5871 5 + 11865 0038 7B68 ldr r3, [r7, #4] + 11866 003a 0022 movs r2, #0 + 11867 003c 83F84020 strb r2, [r3, #64] +5872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5873:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5875:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MasterTxCpltCallback(hi2c); +5876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #else +5877:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_MasterTxCpltCallback(hi2c); + 11868 .loc 1 5877 5 + 11869 0040 7868 ldr r0, [r7, #4] + 11870 0042 FFF7FEFF bl HAL_I2C_MasterTxCpltCallback +5878:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5879:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ +5881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +5884:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; +5885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = NULL; +5886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5887:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Interrupts */ +5888:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); +5889:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5890:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +5891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5892:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ + ARM GAS /tmp/cc5G5cqz.s page 314 + + +5894:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5895:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MasterRxCpltCallback(hi2c); +5896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #else +5897:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_MasterRxCpltCallback(hi2c); +5898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5899:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5900:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 11871 .loc 1 5900 1 + 11872 0046 14E0 b .L579 + 11873 .L577: +5883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + 11874 .loc 1 5883 25 + 11875 0048 7B68 ldr r3, [r7, #4] + 11876 004a 2022 movs r2, #32 + 11877 004c 83F84120 strb r2, [r3, #65] +5884:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = NULL; + 11878 .loc 1 5884 25 + 11879 0050 7B68 ldr r3, [r7, #4] + 11880 0052 1222 movs r2, #18 + 11881 0054 1A63 str r2, [r3, #48] +5885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11882 .loc 1 5885 25 + 11883 0056 7B68 ldr r3, [r7, #4] + 11884 0058 0022 movs r2, #0 + 11885 005a 5A63 str r2, [r3, #52] +5888:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11886 .loc 1 5888 5 + 11887 005c 0221 movs r1, #2 + 11888 005e 7868 ldr r0, [r7, #4] + 11889 0060 FFF7FEFF bl I2C_Disable_IRQ +5891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 11890 .loc 1 5891 5 + 11891 0064 7B68 ldr r3, [r7, #4] + 11892 0066 0022 movs r2, #0 + 11893 0068 83F84020 strb r2, [r3, #64] +5897:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 11894 .loc 1 5897 5 + 11895 006c 7868 ldr r0, [r7, #4] + 11896 006e FFF7FEFF bl HAL_I2C_MasterRxCpltCallback + 11897 .L579: + 11898 .loc 1 5900 1 + 11899 0072 00BF nop + 11900 0074 0837 adds r7, r7, #8 + 11901 .cfi_def_cfa_offset 8 + 11902 0076 BD46 mov sp, r7 + 11903 .cfi_def_cfa_register 13 + 11904 @ sp needed + 11905 0078 80BD pop {r7, pc} + 11906 .cfi_endproc + 11907 .LFE188: + 11909 .section .text.I2C_ITSlaveSeqCplt,"ax",%progbits + 11910 .align 1 + 11911 .syntax unified + 11912 .thumb + 11913 .thumb_func + 11915 I2C_ITSlaveSeqCplt: + 11916 .LFB189: + ARM GAS /tmp/cc5G5cqz.s page 315 + + +5901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5902:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +5903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief I2C Slave sequential complete process. +5904:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c I2C handle. +5905:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +5906:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +5907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c) +5908:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 11917 .loc 1 5908 1 + 11918 .cfi_startproc + 11919 @ args = 0, pretend = 0, frame = 16 + 11920 @ frame_needed = 1, uses_anonymous_args = 0 + 11921 0000 80B5 push {r7, lr} + 11922 .cfi_def_cfa_offset 8 + 11923 .cfi_offset 7, -8 + 11924 .cfi_offset 14, -4 + 11925 0002 84B0 sub sp, sp, #16 + 11926 .cfi_def_cfa_offset 24 + 11927 0004 00AF add r7, sp, #0 + 11928 .cfi_def_cfa_register 7 + 11929 0006 7860 str r0, [r7, #4] +5909:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + 11930 .loc 1 5909 26 + 11931 0008 7B68 ldr r3, [r7, #4] + 11932 000a 1B68 ldr r3, [r3] + 11933 .loc 1 5909 12 + 11934 000c 1B68 ldr r3, [r3] + 11935 000e FB60 str r3, [r7, #12] +5910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5911:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Reset I2C handle mode */ +5912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 11936 .loc 1 5912 14 + 11937 0010 7B68 ldr r3, [r7, #4] + 11938 0012 0022 movs r2, #0 + 11939 0014 83F84220 strb r2, [r3, #66] +5913:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5914:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* If a DMA is ongoing, Update handle size context */ +5915:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) + 11940 .loc 1 5915 7 + 11941 0018 FB68 ldr r3, [r7, #12] + 11942 001a 9B0B lsrs r3, r3, #14 + 11943 001c 03F00103 and r3, r3, #1 + 11944 .loc 1 5915 6 + 11945 0020 002B cmp r3, #0 + 11946 0022 08D0 beq .L581 +5916:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5917:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable DMA Request */ +5918:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + 11947 .loc 1 5918 9 + 11948 0024 7B68 ldr r3, [r7, #4] + 11949 0026 1B68 ldr r3, [r3] + 11950 .loc 1 5918 19 + 11951 0028 1A68 ldr r2, [r3] + 11952 .loc 1 5918 9 + 11953 002a 7B68 ldr r3, [r7, #4] + 11954 002c 1B68 ldr r3, [r3] + 11955 .loc 1 5918 25 + ARM GAS /tmp/cc5G5cqz.s page 316 + + + 11956 002e 22F48042 bic r2, r2, #16384 + 11957 0032 1A60 str r2, [r3] + 11958 0034 0DE0 b .L582 + 11959 .L581: +5919:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5920:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) + 11960 .loc 1 5920 12 + 11961 0036 FB68 ldr r3, [r7, #12] + 11962 0038 DB0B lsrs r3, r3, #15 + 11963 003a 03F00103 and r3, r3, #1 + 11964 .loc 1 5920 11 + 11965 003e 002B cmp r3, #0 + 11966 0040 07D0 beq .L582 +5921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5922:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable DMA Request */ +5923:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + 11967 .loc 1 5923 9 + 11968 0042 7B68 ldr r3, [r7, #4] + 11969 0044 1B68 ldr r3, [r3] + 11970 .loc 1 5923 19 + 11971 0046 1A68 ldr r2, [r3] + 11972 .loc 1 5923 9 + 11973 0048 7B68 ldr r3, [r7, #4] + 11974 004a 1B68 ldr r3, [r3] + 11975 .loc 1 5923 25 + 11976 004c 22F40042 bic r2, r2, #32768 + 11977 0050 1A60 str r2, [r3] + 11978 .L582: +5924:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5925:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5926:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Do nothing */ +5928:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5929:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5930:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + 11979 .loc 1 5930 11 + 11980 0052 7B68 ldr r3, [r7, #4] + 11981 0054 93F84130 ldrb r3, [r3, #65] + 11982 0058 DBB2 uxtb r3, r3 + 11983 .loc 1 5930 6 + 11984 005a 292B cmp r3, #41 + 11985 005c 12D1 bne .L583 +5931:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5932:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ +5933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; + 11986 .loc 1 5933 25 + 11987 005e 7B68 ldr r3, [r7, #4] + 11988 0060 2822 movs r2, #40 + 11989 0062 83F84120 strb r2, [r3, #65] +5934:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + 11990 .loc 1 5934 25 + 11991 0066 7B68 ldr r3, [r7, #4] + 11992 0068 2122 movs r2, #33 + 11993 006a 1A63 str r2, [r3, #48] +5935:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5936:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Interrupts */ +5937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + ARM GAS /tmp/cc5G5cqz.s page 317 + + + 11994 .loc 1 5937 5 + 11995 006c 0121 movs r1, #1 + 11996 006e 7868 ldr r0, [r7, #4] + 11997 0070 FFF7FEFF bl I2C_Disable_IRQ +5938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5939:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +5940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 11998 .loc 1 5940 5 + 11999 0074 7B68 ldr r3, [r7, #4] + 12000 0076 0022 movs r2, #0 + 12001 0078 83F84020 strb r2, [r3, #64] +5941:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5943:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5944:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->SlaveTxCpltCallback(hi2c); +5945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #else +5946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_SlaveTxCpltCallback(hi2c); + 12002 .loc 1 5946 5 + 12003 007c 7868 ldr r0, [r7, #4] + 12004 007e FFF7FEFF bl HAL_I2C_SlaveTxCpltCallback +5947:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5948:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5950:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) +5951:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */ +5953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; +5954:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; +5955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5956:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Interrupts */ +5957:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); +5958:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +5960:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +5961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +5963:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +5964:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->SlaveRxCpltCallback(hi2c); +5965:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #else +5966:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_SlaveRxCpltCallback(hi2c); +5967:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +5968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5969:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +5970:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5971:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Nothing to do */ +5972:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5973:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12005 .loc 1 5973 1 + 12006 0082 17E0 b .L585 + 12007 .L583: +5950:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12008 .loc 1 5950 16 + 12009 0084 7B68 ldr r3, [r7, #4] + 12010 0086 93F84130 ldrb r3, [r3, #65] + 12011 008a DBB2 uxtb r3, r3 +5950:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12012 .loc 1 5950 11 + ARM GAS /tmp/cc5G5cqz.s page 318 + + + 12013 008c 2A2B cmp r3, #42 + 12014 008e 11D1 bne .L585 +5953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + 12015 .loc 1 5953 25 + 12016 0090 7B68 ldr r3, [r7, #4] + 12017 0092 2822 movs r2, #40 + 12018 0094 83F84120 strb r2, [r3, #65] +5954:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12019 .loc 1 5954 25 + 12020 0098 7B68 ldr r3, [r7, #4] + 12021 009a 2222 movs r2, #34 + 12022 009c 1A63 str r2, [r3, #48] +5957:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12023 .loc 1 5957 5 + 12024 009e 0221 movs r1, #2 + 12025 00a0 7868 ldr r0, [r7, #4] + 12026 00a2 FFF7FEFF bl I2C_Disable_IRQ +5960:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12027 .loc 1 5960 5 + 12028 00a6 7B68 ldr r3, [r7, #4] + 12029 00a8 0022 movs r2, #0 + 12030 00aa 83F84020 strb r2, [r3, #64] +5966:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 12031 .loc 1 5966 5 + 12032 00ae 7868 ldr r0, [r7, #4] + 12033 00b0 FFF7FEFF bl HAL_I2C_SlaveRxCpltCallback + 12034 .L585: + 12035 .loc 1 5973 1 + 12036 00b4 00BF nop + 12037 00b6 1037 adds r7, r7, #16 + 12038 .cfi_def_cfa_offset 8 + 12039 00b8 BD46 mov sp, r7 + 12040 .cfi_def_cfa_register 13 + 12041 @ sp needed + 12042 00ba 80BD pop {r7, pc} + 12043 .cfi_endproc + 12044 .LFE189: + 12046 .section .text.I2C_ITMasterCplt,"ax",%progbits + 12047 .align 1 + 12048 .syntax unified + 12049 .thumb + 12050 .thumb_func + 12052 I2C_ITMasterCplt: + 12053 .LFB190: +5974:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5975:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +5976:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief I2C Master complete process. +5977:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c I2C handle. +5978:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. +5979:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +5980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +5981:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +5982:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12054 .loc 1 5982 1 + 12055 .cfi_startproc + 12056 @ args = 0, pretend = 0, frame = 24 + 12057 @ frame_needed = 1, uses_anonymous_args = 0 + ARM GAS /tmp/cc5G5cqz.s page 319 + + + 12058 0000 80B5 push {r7, lr} + 12059 .cfi_def_cfa_offset 8 + 12060 .cfi_offset 7, -8 + 12061 .cfi_offset 14, -4 + 12062 0002 86B0 sub sp, sp, #24 + 12063 .cfi_def_cfa_offset 32 + 12064 0004 00AF add r7, sp, #0 + 12065 .cfi_def_cfa_register 7 + 12066 0006 7860 str r0, [r7, #4] + 12067 0008 3960 str r1, [r7] +5983:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmperror; +5984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; + 12068 .loc 1 5984 12 + 12069 000a 3B68 ldr r3, [r7] + 12070 000c 7B61 str r3, [r7, #20] +5985:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __IO uint32_t tmpreg; +5986:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5987:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear STOP Flag */ +5988:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + 12071 .loc 1 5988 3 + 12072 000e 7B68 ldr r3, [r7, #4] + 12073 0010 1B68 ldr r3, [r3] + 12074 0012 2022 movs r2, #32 + 12075 0014 DA61 str r2, [r3, #28] +5989:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +5990:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Interrupts and Store Previous state */ +5991:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + 12076 .loc 1 5991 11 + 12077 0016 7B68 ldr r3, [r7, #4] + 12078 0018 93F84130 ldrb r3, [r3, #65] + 12079 001c DBB2 uxtb r3, r3 + 12080 .loc 1 5991 6 + 12081 001e 212B cmp r3, #33 + 12082 0020 07D1 bne .L587 +5992:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +5993:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + 12083 .loc 1 5993 5 + 12084 0022 0121 movs r1, #1 + 12085 0024 7868 ldr r0, [r7, #4] + 12086 0026 FFF7FEFF bl I2C_Disable_IRQ +5994:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + 12087 .loc 1 5994 25 + 12088 002a 7B68 ldr r3, [r7, #4] + 12089 002c 1122 movs r2, #17 + 12090 002e 1A63 str r2, [r3, #48] + 12091 0030 0CE0 b .L588 + 12092 .L587: +5995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +5996:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + 12093 .loc 1 5996 16 + 12094 0032 7B68 ldr r3, [r7, #4] + 12095 0034 93F84130 ldrb r3, [r3, #65] + 12096 0038 DBB2 uxtb r3, r3 + 12097 .loc 1 5996 11 + 12098 003a 222B cmp r3, #34 + 12099 003c 06D1 bne .L588 +5997:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + ARM GAS /tmp/cc5G5cqz.s page 320 + + +5998:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + 12100 .loc 1 5998 5 + 12101 003e 0221 movs r1, #2 + 12102 0040 7868 ldr r0, [r7, #4] + 12103 0042 FFF7FEFF bl I2C_Disable_IRQ +5999:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + 12104 .loc 1 5999 25 + 12105 0046 7B68 ldr r3, [r7, #4] + 12106 0048 1222 movs r2, #18 + 12107 004a 1A63 str r2, [r3, #48] + 12108 .L588: +6000:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6001:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +6002:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6003:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Do nothing */ +6004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6005:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6006:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear Configuration Register 2 */ +6007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_RESET_CR2(hi2c); + 12109 .loc 1 6007 3 + 12110 004c 7B68 ldr r3, [r7, #4] + 12111 004e 1B68 ldr r3, [r3] + 12112 0050 5968 ldr r1, [r3, #4] + 12113 0052 7B68 ldr r3, [r7, #4] + 12114 0054 1A68 ldr r2, [r3] + 12115 0056 4D4B ldr r3, .L598 + 12116 0058 0B40 ands r3, r3, r1 + 12117 005a 5360 str r3, [r2, #4] +6008:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Reset handle parameters */ +6010:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = NULL; + 12118 .loc 1 6010 23 + 12119 005c 7B68 ldr r3, [r7, #4] + 12120 005e 0022 movs r2, #0 + 12121 0060 5A63 str r2, [r3, #52] +6011:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 12122 .loc 1 6011 23 + 12123 0062 7B68 ldr r3, [r7, #4] + 12124 0064 4A4A ldr r2, .L598+4 + 12125 0066 DA62 str r2, [r3, #44] +6012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6013:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) + 12126 .loc 1 6013 7 + 12127 0068 7B69 ldr r3, [r7, #20] + 12128 006a 1B09 lsrs r3, r3, #4 + 12129 006c 03F00103 and r3, r3, #1 + 12130 .loc 1 6013 6 + 12131 0070 002B cmp r3, #0 + 12132 0072 09D0 beq .L589 +6014:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6015:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear NACK Flag */ +6016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + 12133 .loc 1 6016 5 + 12134 0074 7B68 ldr r3, [r7, #4] + 12135 0076 1B68 ldr r3, [r3] + 12136 0078 1022 movs r2, #16 + 12137 007a DA61 str r2, [r3, #28] + ARM GAS /tmp/cc5G5cqz.s page 321 + + +6017:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6018:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set acknowledge error code */ +6019:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + 12138 .loc 1 6019 9 + 12139 007c 7B68 ldr r3, [r7, #4] + 12140 007e 5B6C ldr r3, [r3, #68] + 12141 .loc 1 6019 21 + 12142 0080 43F00402 orr r2, r3, #4 + 12143 0084 7B68 ldr r3, [r7, #4] + 12144 0086 5A64 str r2, [r3, #68] + 12145 .L589: +6020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6021:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Fetch Last receive data if any */ +6023:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)) + 12146 .loc 1 6023 12 + 12147 0088 7B68 ldr r3, [r7, #4] + 12148 008a 93F84130 ldrb r3, [r3, #65] + 12149 008e DBB2 uxtb r3, r3 + 12150 .loc 1 6023 6 + 12151 0090 602B cmp r3, #96 + 12152 0092 0BD1 bne .L590 + 12153 .loc 1 6023 48 discriminator 1 + 12154 0094 7B69 ldr r3, [r7, #20] + 12155 0096 9B08 lsrs r3, r3, #2 + 12156 0098 03F00103 and r3, r3, #1 + 12157 .loc 1 6023 44 discriminator 1 + 12158 009c 002B cmp r3, #0 + 12159 009e 05D0 beq .L590 +6024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6025:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Read data from RXDR */ +6026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmpreg = (uint8_t)hi2c->Instance->RXDR; + 12160 .loc 1 6026 27 + 12161 00a0 7B68 ldr r3, [r7, #4] + 12162 00a2 1B68 ldr r3, [r3] + 12163 .loc 1 6026 37 + 12164 00a4 5B6A ldr r3, [r3, #36] + 12165 .loc 1 6026 14 + 12166 00a6 DBB2 uxtb r3, r3 + 12167 .loc 1 6026 12 + 12168 00a8 FB60 str r3, [r7, #12] +6027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** UNUSED(tmpreg); + 12169 .loc 1 6027 5 + 12170 00aa FB68 ldr r3, [r7, #12] + 12171 .L590: +6028:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6030:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Flush TX register */ +6031:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); + 12172 .loc 1 6031 3 + 12173 00ac 7868 ldr r0, [r7, #4] + 12174 00ae FFF7FEFF bl I2C_Flush_TXDR +6032:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6033:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Store current volatile hi2c->ErrorCode, misra rule */ +6034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmperror = hi2c->ErrorCode; + 12175 .loc 1 6034 12 + 12176 00b2 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/cc5G5cqz.s page 322 + + + 12177 00b4 5B6C ldr r3, [r3, #68] + 12178 00b6 3B61 str r3, [r7, #16] +6035:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6036:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +6037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE)) + 12179 .loc 1 6037 12 + 12180 00b8 7B68 ldr r3, [r7, #4] + 12181 00ba 93F84130 ldrb r3, [r3, #65] + 12182 00be DBB2 uxtb r3, r3 + 12183 .loc 1 6037 6 + 12184 00c0 602B cmp r3, #96 + 12185 00c2 02D0 beq .L591 + 12186 .loc 1 6037 44 discriminator 1 + 12187 00c4 3B69 ldr r3, [r7, #16] + 12188 00c6 002B cmp r3, #0 + 12189 00c8 06D0 beq .L592 + 12190 .L591: +6038:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6039:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +6040:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITError(hi2c, hi2c->ErrorCode); + 12191 .loc 1 6040 27 + 12192 00ca 7B68 ldr r3, [r7, #4] + 12193 00cc 5B6C ldr r3, [r3, #68] + 12194 .loc 1 6040 5 + 12195 00ce 1946 mov r1, r3 + 12196 00d0 7868 ldr r0, [r7, #4] + 12197 00d2 FFF7FEFF bl I2C_ITError +6041:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* hi2c->State == HAL_I2C_STATE_BUSY_TX */ +6043:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) +6044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6045:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +6046:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; +6047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->Mode == HAL_I2C_MODE_MEM) +6049:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6050:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +6051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6052:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +6053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6055:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +6056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +6057:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MemTxCpltCallback(hi2c); +6058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #else +6059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_MemTxCpltCallback(hi2c); +6060:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +6061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6062:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +6063:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6064:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +6065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6066:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +6067:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6069:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +6070:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + ARM GAS /tmp/cc5G5cqz.s page 323 + + +6071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MasterTxCpltCallback(hi2c); +6072:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #else +6073:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_MasterTxCpltCallback(hi2c); +6074:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +6075:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6076:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6077:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ +6078:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) +6079:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +6081:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; +6082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->Mode == HAL_I2C_MODE_MEM) +6084:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +6086:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6087:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +6088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6089:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6090:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +6091:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +6092:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MemRxCpltCallback(hi2c); +6093:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #else +6094:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_MemRxCpltCallback(hi2c); +6095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +6096:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6097:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +6098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6099:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; +6100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +6102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +6105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +6106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->MasterRxCpltCallback(hi2c); +6107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #else +6108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_MasterRxCpltCallback(hi2c); +6109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +6110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +6113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Nothing to do */ +6115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12198 .loc 1 6116 1 + 12199 00d6 54E0 b .L597 + 12200 .L592: +6043:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12201 .loc 1 6043 16 + 12202 00d8 7B68 ldr r3, [r7, #4] + 12203 00da 93F84130 ldrb r3, [r3, #65] + 12204 00de DBB2 uxtb r3, r3 +6043:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12205 .loc 1 6043 11 + 12206 00e0 212B cmp r3, #33 + ARM GAS /tmp/cc5G5cqz.s page 324 + + + 12207 00e2 24D1 bne .L594 +6045:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 12208 .loc 1 6045 17 + 12209 00e4 7B68 ldr r3, [r7, #4] + 12210 00e6 2022 movs r2, #32 + 12211 00e8 83F84120 strb r2, [r3, #65] +6046:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12212 .loc 1 6046 25 + 12213 00ec 7B68 ldr r3, [r7, #4] + 12214 00ee 0022 movs r2, #0 + 12215 00f0 1A63 str r2, [r3, #48] +6048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12216 .loc 1 6048 13 + 12217 00f2 7B68 ldr r3, [r7, #4] + 12218 00f4 93F84230 ldrb r3, [r3, #66] + 12219 00f8 DBB2 uxtb r3, r3 +6048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12220 .loc 1 6048 8 + 12221 00fa 402B cmp r3, #64 + 12222 00fc 0BD1 bne .L595 +6050:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12223 .loc 1 6050 18 + 12224 00fe 7B68 ldr r3, [r7, #4] + 12225 0100 0022 movs r2, #0 + 12226 0102 83F84220 strb r2, [r3, #66] +6053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12227 .loc 1 6053 7 + 12228 0106 7B68 ldr r3, [r7, #4] + 12229 0108 0022 movs r2, #0 + 12230 010a 83F84020 strb r2, [r3, #64] +6059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 12231 .loc 1 6059 7 + 12232 010e 7868 ldr r0, [r7, #4] + 12233 0110 FFF7FEFF bl HAL_I2C_MemTxCpltCallback + 12234 .loc 1 6116 1 + 12235 0114 35E0 b .L597 + 12236 .L595: +6064:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12237 .loc 1 6064 18 + 12238 0116 7B68 ldr r3, [r7, #4] + 12239 0118 0022 movs r2, #0 + 12240 011a 83F84220 strb r2, [r3, #66] +6067:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12241 .loc 1 6067 7 + 12242 011e 7B68 ldr r3, [r7, #4] + 12243 0120 0022 movs r2, #0 + 12244 0122 83F84020 strb r2, [r3, #64] +6073:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 12245 .loc 1 6073 7 + 12246 0126 7868 ldr r0, [r7, #4] + 12247 0128 FFF7FEFF bl HAL_I2C_MasterTxCpltCallback + 12248 .loc 1 6116 1 + 12249 012c 29E0 b .L597 + 12250 .L594: +6078:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12251 .loc 1 6078 16 + 12252 012e 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/cc5G5cqz.s page 325 + + + 12253 0130 93F84130 ldrb r3, [r3, #65] + 12254 0134 DBB2 uxtb r3, r3 +6078:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12255 .loc 1 6078 11 + 12256 0136 222B cmp r3, #34 + 12257 0138 23D1 bne .L597 +6080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 12258 .loc 1 6080 17 + 12259 013a 7B68 ldr r3, [r7, #4] + 12260 013c 2022 movs r2, #32 + 12261 013e 83F84120 strb r2, [r3, #65] +6081:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12262 .loc 1 6081 25 + 12263 0142 7B68 ldr r3, [r7, #4] + 12264 0144 0022 movs r2, #0 + 12265 0146 1A63 str r2, [r3, #48] +6083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12266 .loc 1 6083 13 + 12267 0148 7B68 ldr r3, [r7, #4] + 12268 014a 93F84230 ldrb r3, [r3, #66] + 12269 014e DBB2 uxtb r3, r3 +6083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12270 .loc 1 6083 8 + 12271 0150 402B cmp r3, #64 + 12272 0152 0BD1 bne .L596 +6085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12273 .loc 1 6085 18 + 12274 0154 7B68 ldr r3, [r7, #4] + 12275 0156 0022 movs r2, #0 + 12276 0158 83F84220 strb r2, [r3, #66] +6088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12277 .loc 1 6088 7 + 12278 015c 7B68 ldr r3, [r7, #4] + 12279 015e 0022 movs r2, #0 + 12280 0160 83F84020 strb r2, [r3, #64] +6094:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 12281 .loc 1 6094 7 + 12282 0164 7868 ldr r0, [r7, #4] + 12283 0166 FFF7FEFF bl HAL_I2C_MemRxCpltCallback + 12284 .loc 1 6116 1 + 12285 016a 0AE0 b .L597 + 12286 .L596: +6099:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12287 .loc 1 6099 18 + 12288 016c 7B68 ldr r3, [r7, #4] + 12289 016e 0022 movs r2, #0 + 12290 0170 83F84220 strb r2, [r3, #66] +6102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12291 .loc 1 6102 7 + 12292 0174 7B68 ldr r3, [r7, #4] + 12293 0176 0022 movs r2, #0 + 12294 0178 83F84020 strb r2, [r3, #64] +6108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 12295 .loc 1 6108 7 + 12296 017c 7868 ldr r0, [r7, #4] + 12297 017e FFF7FEFF bl HAL_I2C_MasterRxCpltCallback + 12298 .L597: + ARM GAS /tmp/cc5G5cqz.s page 326 + + + 12299 .loc 1 6116 1 + 12300 0182 00BF nop + 12301 0184 1837 adds r7, r7, #24 + 12302 .cfi_def_cfa_offset 8 + 12303 0186 BD46 mov sp, r7 + 12304 .cfi_def_cfa_register 13 + 12305 @ sp needed + 12306 0188 80BD pop {r7, pc} + 12307 .L599: + 12308 018a 00BF .align 2 + 12309 .L598: + 12310 018c 00E800FE .word -33495040 + 12311 0190 0000FFFF .word -65536 + 12312 .cfi_endproc + 12313 .LFE190: + 12315 .section .text.I2C_ITSlaveCplt,"ax",%progbits + 12316 .align 1 + 12317 .syntax unified + 12318 .thumb + 12319 .thumb_func + 12321 I2C_ITSlaveCplt: + 12322 .LFB191: +6117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +6119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief I2C Slave complete process. +6120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c I2C handle. +6121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. +6122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +6123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +6124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +6125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12323 .loc 1 6125 1 + 12324 .cfi_startproc + 12325 @ args = 0, pretend = 0, frame = 24 + 12326 @ frame_needed = 1, uses_anonymous_args = 0 + 12327 0000 80B5 push {r7, lr} + 12328 .cfi_def_cfa_offset 8 + 12329 .cfi_offset 7, -8 + 12330 .cfi_offset 14, -4 + 12331 0002 86B0 sub sp, sp, #24 + 12332 .cfi_def_cfa_offset 32 + 12333 0004 00AF add r7, sp, #0 + 12334 .cfi_def_cfa_register 7 + 12335 0006 7860 str r0, [r7, #4] + 12336 0008 3960 str r1, [r7] +6126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + 12337 .loc 1 6126 26 + 12338 000a 7B68 ldr r3, [r7, #4] + 12339 000c 1B68 ldr r3, [r3] + 12340 .loc 1 6126 12 + 12341 000e 1B68 ldr r3, [r3] + 12342 0010 3B61 str r3, [r7, #16] +6127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmpITFlags = ITFlags; + 12343 .loc 1 6127 12 + 12344 0012 3B68 ldr r3, [r7] + 12345 0014 7B61 str r3, [r7, #20] +6128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_StateTypeDef tmpstate = hi2c->State; + ARM GAS /tmp/cc5G5cqz.s page 327 + + + 12346 .loc 1 6128 24 + 12347 0016 7B68 ldr r3, [r7, #4] + 12348 0018 93F84130 ldrb r3, [r3, #65] + 12349 001c FB73 strb r3, [r7, #15] +6129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear STOP Flag */ +6131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + 12350 .loc 1 6131 3 + 12351 001e 7B68 ldr r3, [r7, #4] + 12352 0020 1B68 ldr r3, [r3] + 12353 0022 2022 movs r2, #32 + 12354 0024 DA61 str r2, [r3, #28] +6132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Interrupts and Store Previous state */ +6134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) + 12355 .loc 1 6134 6 + 12356 0026 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 12357 0028 212B cmp r3, #33 + 12358 002a 02D0 beq .L601 + 12359 .loc 1 6134 43 discriminator 1 + 12360 002c FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 12361 002e 292B cmp r3, #41 + 12362 0030 08D1 bne .L602 + 12363 .L601: +6135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + 12364 .loc 1 6136 5 + 12365 0032 48F20101 movw r1, #32769 + 12366 0036 7868 ldr r0, [r7, #4] + 12367 0038 FFF7FEFF bl I2C_Disable_IRQ +6137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + 12368 .loc 1 6137 25 + 12369 003c 7B68 ldr r3, [r7, #4] + 12370 003e 2122 movs r2, #33 + 12371 0040 1A63 str r2, [r3, #48] + 12372 0042 0DE0 b .L603 + 12373 .L602: +6138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + 12374 .loc 1 6139 11 + 12375 0044 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 12376 0046 222B cmp r3, #34 + 12377 0048 02D0 beq .L604 + 12378 .loc 1 6139 48 discriminator 1 + 12379 004a FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 12380 004c 2A2B cmp r3, #42 + 12381 004e 07D1 bne .L603 + 12382 .L604: +6140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + 12383 .loc 1 6141 5 + 12384 0050 48F20201 movw r1, #32770 + 12385 0054 7868 ldr r0, [r7, #4] + 12386 0056 FFF7FEFF bl I2C_Disable_IRQ +6142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + 12387 .loc 1 6142 25 + 12388 005a 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/cc5G5cqz.s page 328 + + + 12389 005c 2222 movs r2, #34 + 12390 005e 1A63 str r2, [r3, #48] + 12391 .L603: +6143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +6145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Do nothing */ +6147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Address Acknowledge */ +6150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; + 12392 .loc 1 6150 7 + 12393 0060 7B68 ldr r3, [r7, #4] + 12394 0062 1B68 ldr r3, [r3] + 12395 .loc 1 6150 17 + 12396 0064 5A68 ldr r2, [r3, #4] + 12397 .loc 1 6150 7 + 12398 0066 7B68 ldr r3, [r7, #4] + 12399 0068 1B68 ldr r3, [r3] + 12400 .loc 1 6150 23 + 12401 006a 42F40042 orr r2, r2, #32768 + 12402 006e 5A60 str r2, [r3, #4] +6151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear Configuration Register 2 */ +6153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_RESET_CR2(hi2c); + 12403 .loc 1 6153 3 + 12404 0070 7B68 ldr r3, [r7, #4] + 12405 0072 1B68 ldr r3, [r3] + 12406 0074 5968 ldr r1, [r3, #4] + 12407 0076 7B68 ldr r3, [r7, #4] + 12408 0078 1A68 ldr r2, [r3] + 12409 007a 644B ldr r3, .L614 + 12410 007c 0B40 ands r3, r3, r1 + 12411 007e 5360 str r3, [r2, #4] +6154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Flush TX register */ +6156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); + 12412 .loc 1 6156 3 + 12413 0080 7868 ldr r0, [r7, #4] + 12414 0082 FFF7FEFF bl I2C_Flush_TXDR +6157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* If a DMA is ongoing, Update handle size context */ +6159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) + 12415 .loc 1 6159 7 + 12416 0086 3B69 ldr r3, [r7, #16] + 12417 0088 9B0B lsrs r3, r3, #14 + 12418 008a 03F00103 and r3, r3, #1 + 12419 .loc 1 6159 6 + 12420 008e 002B cmp r3, #0 + 12421 0090 13D0 beq .L605 +6160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable DMA Request */ +6162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + 12422 .loc 1 6162 9 + 12423 0092 7B68 ldr r3, [r7, #4] + 12424 0094 1B68 ldr r3, [r3] + 12425 .loc 1 6162 19 + ARM GAS /tmp/cc5G5cqz.s page 329 + + + 12426 0096 1A68 ldr r2, [r3] + 12427 .loc 1 6162 9 + 12428 0098 7B68 ldr r3, [r7, #4] + 12429 009a 1B68 ldr r3, [r3] + 12430 .loc 1 6162 25 + 12431 009c 22F48042 bic r2, r2, #16384 + 12432 00a0 1A60 str r2, [r3] +6163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) + 12433 .loc 1 6164 13 + 12434 00a2 7B68 ldr r3, [r7, #4] + 12435 00a4 9B6B ldr r3, [r3, #56] + 12436 .loc 1 6164 8 + 12437 00a6 002B cmp r3, #0 + 12438 00a8 20D0 beq .L606 +6165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx); + 12439 .loc 1 6166 35 + 12440 00aa 7B68 ldr r3, [r7, #4] + 12441 00ac 9B6B ldr r3, [r3, #56] + 12442 00ae 1B68 ldr r3, [r3] + 12443 00b0 5B68 ldr r3, [r3, #4] + 12444 .loc 1 6166 25 + 12445 00b2 9AB2 uxth r2, r3 + 12446 .loc 1 6166 23 + 12447 00b4 7B68 ldr r3, [r7, #4] + 12448 00b6 5A85 strh r2, [r3, #42] @ movhi + 12449 00b8 18E0 b .L606 + 12450 .L605: +6167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) + 12451 .loc 1 6169 12 + 12452 00ba 3B69 ldr r3, [r7, #16] + 12453 00bc DB0B lsrs r3, r3, #15 + 12454 00be 03F00103 and r3, r3, #1 + 12455 .loc 1 6169 11 + 12456 00c2 002B cmp r3, #0 + 12457 00c4 12D0 beq .L606 +6170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable DMA Request */ +6172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + 12458 .loc 1 6172 9 + 12459 00c6 7B68 ldr r3, [r7, #4] + 12460 00c8 1B68 ldr r3, [r3] + 12461 .loc 1 6172 19 + 12462 00ca 1A68 ldr r2, [r3] + 12463 .loc 1 6172 9 + 12464 00cc 7B68 ldr r3, [r7, #4] + 12465 00ce 1B68 ldr r3, [r3] + 12466 .loc 1 6172 25 + 12467 00d0 22F40042 bic r2, r2, #32768 + 12468 00d4 1A60 str r2, [r3] +6173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) + 12469 .loc 1 6174 13 + 12470 00d6 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/cc5G5cqz.s page 330 + + + 12471 00d8 DB6B ldr r3, [r3, #60] + 12472 .loc 1 6174 8 + 12473 00da 002B cmp r3, #0 + 12474 00dc 06D0 beq .L606 +6175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx); + 12475 .loc 1 6176 35 + 12476 00de 7B68 ldr r3, [r7, #4] + 12477 00e0 DB6B ldr r3, [r3, #60] + 12478 00e2 1B68 ldr r3, [r3] + 12479 00e4 5B68 ldr r3, [r3, #4] + 12480 .loc 1 6176 25 + 12481 00e6 9AB2 uxth r2, r3 + 12482 .loc 1 6176 23 + 12483 00e8 7B68 ldr r3, [r7, #4] + 12484 00ea 5A85 strh r2, [r3, #42] @ movhi + 12485 .L606: +6177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +6180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Do nothing */ +6182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Store Last receive data if any */ +6185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) + 12486 .loc 1 6185 7 + 12487 00ec 7B69 ldr r3, [r7, #20] + 12488 00ee 9B08 lsrs r3, r3, #2 + 12489 00f0 03F00103 and r3, r3, #1 + 12490 .loc 1 6185 6 + 12491 00f4 002B cmp r3, #0 + 12492 00f6 20D0 beq .L607 +6186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Remove RXNE flag on temporary variable as read done */ +6188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmpITFlags &= ~I2C_FLAG_RXNE; + 12493 .loc 1 6188 16 + 12494 00f8 7B69 ldr r3, [r7, #20] + 12495 00fa 23F00403 bic r3, r3, #4 + 12496 00fe 7B61 str r3, [r7, #20] +6189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Read data from RXDR */ +6191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + 12497 .loc 1 6191 36 + 12498 0100 7B68 ldr r3, [r7, #4] + 12499 0102 1B68 ldr r3, [r3] + 12500 .loc 1 6191 46 + 12501 0104 5A6A ldr r2, [r3, #36] + 12502 .loc 1 6191 10 + 12503 0106 7B68 ldr r3, [r7, #4] + 12504 0108 5B6A ldr r3, [r3, #36] + 12505 .loc 1 6191 23 + 12506 010a D2B2 uxtb r2, r2 + 12507 .loc 1 6191 21 + 12508 010c 1A70 strb r2, [r3] +6192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Increment Buffer pointer */ + ARM GAS /tmp/cc5G5cqz.s page 331 + + +6194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr++; + 12509 .loc 1 6194 9 + 12510 010e 7B68 ldr r3, [r7, #4] + 12511 0110 5B6A ldr r3, [r3, #36] + 12512 .loc 1 6194 19 + 12513 0112 5A1C adds r2, r3, #1 + 12514 0114 7B68 ldr r3, [r7, #4] + 12515 0116 5A62 str r2, [r3, #36] +6195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->XferSize > 0U)) + 12516 .loc 1 6196 14 + 12517 0118 7B68 ldr r3, [r7, #4] + 12518 011a 1B8D ldrh r3, [r3, #40] + 12519 .loc 1 6196 8 + 12520 011c 002B cmp r3, #0 + 12521 011e 0CD0 beq .L607 +6197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize--; + 12522 .loc 1 6198 11 + 12523 0120 7B68 ldr r3, [r7, #4] + 12524 0122 1B8D ldrh r3, [r3, #40] + 12525 .loc 1 6198 21 + 12526 0124 013B subs r3, r3, #1 + 12527 0126 9AB2 uxth r2, r3 + 12528 0128 7B68 ldr r3, [r7, #4] + 12529 012a 1A85 strh r2, [r3, #40] @ movhi +6199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount--; + 12530 .loc 1 6199 11 + 12531 012c 7B68 ldr r3, [r7, #4] + 12532 012e 5B8D ldrh r3, [r3, #42] @ movhi + 12533 0130 9BB2 uxth r3, r3 + 12534 .loc 1 6199 22 + 12535 0132 013B subs r3, r3, #1 + 12536 0134 9AB2 uxth r2, r3 + 12537 0136 7B68 ldr r3, [r7, #4] + 12538 0138 5A85 strh r2, [r3, #42] @ movhi + 12539 .L607: +6200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* All data are not transferred, so set error code accordingly */ +6204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount != 0U) + 12540 .loc 1 6204 11 + 12541 013a 7B68 ldr r3, [r7, #4] + 12542 013c 5B8D ldrh r3, [r3, #42] @ movhi + 12543 013e 9BB2 uxth r3, r3 + 12544 .loc 1 6204 6 + 12545 0140 002B cmp r3, #0 + 12546 0142 05D0 beq .L608 +6205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set ErrorCode corresponding to a Non-Acknowledge */ +6207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + 12547 .loc 1 6207 9 + 12548 0144 7B68 ldr r3, [r7, #4] + 12549 0146 5B6C ldr r3, [r3, #68] + 12550 .loc 1 6207 21 + 12551 0148 43F00402 orr r2, r3, #4 + ARM GAS /tmp/cc5G5cqz.s page 332 + + + 12552 014c 7B68 ldr r3, [r7, #4] + 12553 014e 5A64 str r2, [r3, #68] + 12554 .L608: +6208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 12555 .loc 1 6210 14 + 12556 0150 7B68 ldr r3, [r7, #4] + 12557 0152 0022 movs r2, #0 + 12558 0154 83F84220 strb r2, [r3, #66] +6211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = NULL; + 12559 .loc 1 6211 17 + 12560 0158 7B68 ldr r3, [r7, #4] + 12561 015a 0022 movs r2, #0 + 12562 015c 5A63 str r2, [r3, #52] +6212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + 12563 .loc 1 6213 11 + 12564 015e 7B68 ldr r3, [r7, #4] + 12565 0160 5B6C ldr r3, [r3, #68] + 12566 .loc 1 6213 6 + 12567 0162 002B cmp r3, #0 + 12568 0164 10D0 beq .L609 +6214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +6216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITError(hi2c, hi2c->ErrorCode); + 12569 .loc 1 6216 27 + 12570 0166 7B68 ldr r3, [r7, #4] + 12571 0168 5B6C ldr r3, [r3, #68] + 12572 .loc 1 6216 5 + 12573 016a 1946 mov r1, r3 + 12574 016c 7868 ldr r0, [r7, #4] + 12575 016e FFF7FEFF bl I2C_ITError +6217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +6219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_LISTEN) + 12576 .loc 1 6219 13 + 12577 0172 7B68 ldr r3, [r7, #4] + 12578 0174 93F84130 ldrb r3, [r3, #65] + 12579 0178 DBB2 uxtb r3, r3 + 12580 .loc 1 6219 8 + 12581 017a 282B cmp r3, #40 + 12582 017c 41D1 bne .L613 +6220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call I2C Listen complete process */ +6222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITListenCplt(hi2c, tmpITFlags); + 12583 .loc 1 6222 7 + 12584 017e 7969 ldr r1, [r7, #20] + 12585 0180 7868 ldr r0, [r7, #4] + 12586 0182 FFF7FEFF bl I2C_ITListenCplt +6223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) +6226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */ +6228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITSlaveSeqCplt(hi2c); +6229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/cc5G5cqz.s page 333 + + +6230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; +6231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +6232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; +6233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +6235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +6238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +6239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ListenCpltCallback(hi2c); +6240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #else +6241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_ListenCpltCallback(hi2c); +6242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +6243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +6245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) +6246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +6248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; +6249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +6251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +6254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +6255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->SlaveRxCpltCallback(hi2c); +6256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #else +6257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_SlaveRxCpltCallback(hi2c); +6258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +6259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +6261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; +6263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; +6264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +6266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +6269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +6270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->SlaveTxCpltCallback(hi2c); +6271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #else +6272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_SlaveTxCpltCallback(hi2c); +6273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +6274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12587 .loc 1 6275 1 + 12588 0186 3CE0 b .L613 + 12589 .L609: +6225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12590 .loc 1 6225 16 + 12591 0188 7B68 ldr r3, [r7, #4] + 12592 018a DB6A ldr r3, [r3, #44] +6225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12593 .loc 1 6225 11 + 12594 018c 13F5803F cmn r3, #65536 + 12595 0190 14D0 beq .L611 + ARM GAS /tmp/cc5G5cqz.s page 334 + + +6228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12596 .loc 1 6228 5 + 12597 0192 7868 ldr r0, [r7, #4] + 12598 0194 FFF7FEFF bl I2C_ITSlaveSeqCplt +6230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 12599 .loc 1 6230 23 + 12600 0198 7B68 ldr r3, [r7, #4] + 12601 019a 1D4A ldr r2, .L614+4 + 12602 019c DA62 str r2, [r3, #44] +6231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 12603 .loc 1 6231 17 + 12604 019e 7B68 ldr r3, [r7, #4] + 12605 01a0 2022 movs r2, #32 + 12606 01a2 83F84120 strb r2, [r3, #65] +6232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12607 .loc 1 6232 25 + 12608 01a6 7B68 ldr r3, [r7, #4] + 12609 01a8 0022 movs r2, #0 + 12610 01aa 1A63 str r2, [r3, #48] +6235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12611 .loc 1 6235 5 + 12612 01ac 7B68 ldr r3, [r7, #4] + 12613 01ae 0022 movs r2, #0 + 12614 01b0 83F84020 strb r2, [r3, #64] +6241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 12615 .loc 1 6241 5 + 12616 01b4 7868 ldr r0, [r7, #4] + 12617 01b6 FFF7FEFF bl HAL_I2C_ListenCpltCallback + 12618 .loc 1 6275 1 + 12619 01ba 22E0 b .L613 + 12620 .L611: +6245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12621 .loc 1 6245 16 + 12622 01bc 7B68 ldr r3, [r7, #4] + 12623 01be 93F84130 ldrb r3, [r3, #65] + 12624 01c2 DBB2 uxtb r3, r3 +6245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12625 .loc 1 6245 11 + 12626 01c4 222B cmp r3, #34 + 12627 01c6 0ED1 bne .L612 +6247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 12628 .loc 1 6247 17 + 12629 01c8 7B68 ldr r3, [r7, #4] + 12630 01ca 2022 movs r2, #32 + 12631 01cc 83F84120 strb r2, [r3, #65] +6248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12632 .loc 1 6248 25 + 12633 01d0 7B68 ldr r3, [r7, #4] + 12634 01d2 0022 movs r2, #0 + 12635 01d4 1A63 str r2, [r3, #48] +6251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12636 .loc 1 6251 5 + 12637 01d6 7B68 ldr r3, [r7, #4] + 12638 01d8 0022 movs r2, #0 + 12639 01da 83F84020 strb r2, [r3, #64] +6257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 12640 .loc 1 6257 5 + ARM GAS /tmp/cc5G5cqz.s page 335 + + + 12641 01de 7868 ldr r0, [r7, #4] + 12642 01e0 FFF7FEFF bl HAL_I2C_SlaveRxCpltCallback + 12643 .loc 1 6275 1 + 12644 01e4 0DE0 b .L613 + 12645 .L612: +6262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 12646 .loc 1 6262 17 + 12647 01e6 7B68 ldr r3, [r7, #4] + 12648 01e8 2022 movs r2, #32 + 12649 01ea 83F84120 strb r2, [r3, #65] +6263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12650 .loc 1 6263 25 + 12651 01ee 7B68 ldr r3, [r7, #4] + 12652 01f0 0022 movs r2, #0 + 12653 01f2 1A63 str r2, [r3, #48] +6266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 12654 .loc 1 6266 5 + 12655 01f4 7B68 ldr r3, [r7, #4] + 12656 01f6 0022 movs r2, #0 + 12657 01f8 83F84020 strb r2, [r3, #64] +6272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 12658 .loc 1 6272 5 + 12659 01fc 7868 ldr r0, [r7, #4] + 12660 01fe FFF7FEFF bl HAL_I2C_SlaveTxCpltCallback + 12661 .L613: + 12662 .loc 1 6275 1 + 12663 0202 00BF nop + 12664 0204 1837 adds r7, r7, #24 + 12665 .cfi_def_cfa_offset 8 + 12666 0206 BD46 mov sp, r7 + 12667 .cfi_def_cfa_register 13 + 12668 @ sp needed + 12669 0208 80BD pop {r7, pc} + 12670 .L615: + 12671 020a 00BF .align 2 + 12672 .L614: + 12673 020c 00E800FE .word -33495040 + 12674 0210 0000FFFF .word -65536 + 12675 .cfi_endproc + 12676 .LFE191: + 12678 .section .text.I2C_ITListenCplt,"ax",%progbits + 12679 .align 1 + 12680 .syntax unified + 12681 .thumb + 12682 .thumb_func + 12684 I2C_ITListenCplt: + 12685 .LFB192: +6276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +6278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief I2C Listen complete process. +6279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c I2C handle. +6280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param ITFlags Interrupt flags to handle. +6281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +6282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +6283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +6284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12686 .loc 1 6284 1 + ARM GAS /tmp/cc5G5cqz.s page 336 + + + 12687 .cfi_startproc + 12688 @ args = 0, pretend = 0, frame = 8 + 12689 @ frame_needed = 1, uses_anonymous_args = 0 + 12690 0000 80B5 push {r7, lr} + 12691 .cfi_def_cfa_offset 8 + 12692 .cfi_offset 7, -8 + 12693 .cfi_offset 14, -4 + 12694 0002 82B0 sub sp, sp, #8 + 12695 .cfi_def_cfa_offset 16 + 12696 0004 00AF add r7, sp, #0 + 12697 .cfi_def_cfa_register 7 + 12698 0006 7860 str r0, [r7, #4] + 12699 0008 3960 str r1, [r7] +6285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Reset handle parameters */ +6286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 12700 .loc 1 6286 21 + 12701 000a 7B68 ldr r3, [r7, #4] + 12702 000c 264A ldr r2, .L618 + 12703 000e DA62 str r2, [r3, #44] +6287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 12704 .loc 1 6287 23 + 12705 0010 7B68 ldr r3, [r7, #4] + 12706 0012 0022 movs r2, #0 + 12707 0014 1A63 str r2, [r3, #48] +6288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 12708 .loc 1 6288 15 + 12709 0016 7B68 ldr r3, [r7, #4] + 12710 0018 2022 movs r2, #32 + 12711 001a 83F84120 strb r2, [r3, #65] +6289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 12712 .loc 1 6289 14 + 12713 001e 7B68 ldr r3, [r7, #4] + 12714 0020 0022 movs r2, #0 + 12715 0022 83F84220 strb r2, [r3, #66] +6290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = NULL; + 12716 .loc 1 6290 17 + 12717 0026 7B68 ldr r3, [r7, #4] + 12718 0028 0022 movs r2, #0 + 12719 002a 5A63 str r2, [r3, #52] +6291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Store Last receive data if any */ +6293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET) + 12720 .loc 1 6293 7 + 12721 002c 3B68 ldr r3, [r7] + 12722 002e 9B08 lsrs r3, r3, #2 + 12723 0030 03F00103 and r3, r3, #1 + 12724 .loc 1 6293 6 + 12725 0034 002B cmp r3, #0 + 12726 0036 22D0 beq .L617 +6294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Read data from RXDR */ +6296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + 12727 .loc 1 6296 36 + 12728 0038 7B68 ldr r3, [r7, #4] + 12729 003a 1B68 ldr r3, [r3] + 12730 .loc 1 6296 46 + 12731 003c 5A6A ldr r2, [r3, #36] + ARM GAS /tmp/cc5G5cqz.s page 337 + + + 12732 .loc 1 6296 10 + 12733 003e 7B68 ldr r3, [r7, #4] + 12734 0040 5B6A ldr r3, [r3, #36] + 12735 .loc 1 6296 23 + 12736 0042 D2B2 uxtb r2, r2 + 12737 .loc 1 6296 21 + 12738 0044 1A70 strb r2, [r3] +6297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Increment Buffer pointer */ +6299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr++; + 12739 .loc 1 6299 9 + 12740 0046 7B68 ldr r3, [r7, #4] + 12741 0048 5B6A ldr r3, [r3, #36] + 12742 .loc 1 6299 19 + 12743 004a 5A1C adds r2, r3, #1 + 12744 004c 7B68 ldr r3, [r7, #4] + 12745 004e 5A62 str r2, [r3, #36] +6300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->XferSize > 0U)) + 12746 .loc 1 6301 14 + 12747 0050 7B68 ldr r3, [r7, #4] + 12748 0052 1B8D ldrh r3, [r3, #40] + 12749 .loc 1 6301 8 + 12750 0054 002B cmp r3, #0 + 12751 0056 12D0 beq .L617 +6302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize--; + 12752 .loc 1 6303 11 + 12753 0058 7B68 ldr r3, [r7, #4] + 12754 005a 1B8D ldrh r3, [r3, #40] + 12755 .loc 1 6303 21 + 12756 005c 013B subs r3, r3, #1 + 12757 005e 9AB2 uxth r2, r3 + 12758 0060 7B68 ldr r3, [r7, #4] + 12759 0062 1A85 strh r2, [r3, #40] @ movhi +6304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount--; + 12760 .loc 1 6304 11 + 12761 0064 7B68 ldr r3, [r7, #4] + 12762 0066 5B8D ldrh r3, [r3, #42] @ movhi + 12763 0068 9BB2 uxth r3, r3 + 12764 .loc 1 6304 22 + 12765 006a 013B subs r3, r3, #1 + 12766 006c 9AB2 uxth r2, r3 + 12767 006e 7B68 ldr r3, [r7, #4] + 12768 0070 5A85 strh r2, [r3, #42] @ movhi +6305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set ErrorCode corresponding to a Non-Acknowledge */ +6307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + 12769 .loc 1 6307 11 + 12770 0072 7B68 ldr r3, [r7, #4] + 12771 0074 5B6C ldr r3, [r3, #68] + 12772 .loc 1 6307 23 + 12773 0076 43F00402 orr r2, r3, #4 + 12774 007a 7B68 ldr r3, [r7, #4] + 12775 007c 5A64 str r2, [r3, #68] + 12776 .L617: +6308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/cc5G5cqz.s page 338 + + +6309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable all Interrupts*/ +6312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); + 12777 .loc 1 6312 3 + 12778 007e 48F20301 movw r1, #32771 + 12779 0082 7868 ldr r0, [r7, #4] + 12780 0084 FFF7FEFF bl I2C_Disable_IRQ +6313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear NACK Flag */ +6315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + 12781 .loc 1 6315 3 + 12782 0088 7B68 ldr r3, [r7, #4] + 12783 008a 1B68 ldr r3, [r3] + 12784 008c 1022 movs r2, #16 + 12785 008e DA61 str r2, [r3, #28] +6316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +6318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 12786 .loc 1 6318 3 + 12787 0090 7B68 ldr r3, [r7, #4] + 12788 0092 0022 movs r2, #0 + 12789 0094 83F84020 strb r2, [r3, #64] +6319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +6321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +6322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ListenCpltCallback(hi2c); +6323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #else +6324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_ListenCpltCallback(hi2c); + 12790 .loc 1 6324 3 + 12791 0098 7868 ldr r0, [r7, #4] + 12792 009a FFF7FEFF bl HAL_I2C_ListenCpltCallback +6325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +6326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 12793 .loc 1 6326 1 + 12794 009e 00BF nop + 12795 00a0 0837 adds r7, r7, #8 + 12796 .cfi_def_cfa_offset 8 + 12797 00a2 BD46 mov sp, r7 + 12798 .cfi_def_cfa_register 13 + 12799 @ sp needed + 12800 00a4 80BD pop {r7, pc} + 12801 .L619: + 12802 00a6 00BF .align 2 + 12803 .L618: + 12804 00a8 0000FFFF .word -65536 + 12805 .cfi_endproc + 12806 .LFE192: + 12808 .section .text.I2C_ITError,"ax",%progbits + 12809 .align 1 + 12810 .syntax unified + 12811 .thumb + 12812 .thumb_func + 12814 I2C_ITError: + 12815 .LFB193: +6327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** + ARM GAS /tmp/cc5G5cqz.s page 339 + + +6329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief I2C interrupts error process. +6330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c I2C handle. +6331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param ErrorCode Error code to handle. +6332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +6333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +6334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) +6335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 12816 .loc 1 6335 1 + 12817 .cfi_startproc + 12818 @ args = 0, pretend = 0, frame = 16 + 12819 @ frame_needed = 1, uses_anonymous_args = 0 + 12820 0000 80B5 push {r7, lr} + 12821 .cfi_def_cfa_offset 8 + 12822 .cfi_offset 7, -8 + 12823 .cfi_offset 14, -4 + 12824 0002 84B0 sub sp, sp, #16 + 12825 .cfi_def_cfa_offset 24 + 12826 0004 00AF add r7, sp, #0 + 12827 .cfi_def_cfa_register 7 + 12828 0006 7860 str r0, [r7, #4] + 12829 0008 3960 str r1, [r7] +6336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_StateTypeDef tmpstate = hi2c->State; + 12830 .loc 1 6336 24 + 12831 000a 7B68 ldr r3, [r7, #4] + 12832 000c 93F84130 ldrb r3, [r3, #65] + 12833 0010 FB73 strb r3, [r7, #15] +6337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmppreviousstate; +6339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Reset handle parameters */ +6341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 12834 .loc 1 6341 23 + 12835 0012 7B68 ldr r3, [r7, #4] + 12836 0014 0022 movs r2, #0 + 12837 0016 83F84220 strb r2, [r3, #66] +6342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_NO_OPTION_FRAME; + 12838 .loc 1 6342 23 + 12839 001a 7B68 ldr r3, [r7, #4] + 12840 001c 6D4A ldr r2, .L640 + 12841 001e DA62 str r2, [r3, #44] +6343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferCount = 0U; + 12842 .loc 1 6343 23 + 12843 0020 7B68 ldr r3, [r7, #4] + 12844 0022 0022 movs r2, #0 + 12845 0024 5A85 strh r2, [r3, #42] @ movhi +6344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set new error code */ +6346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= ErrorCode; + 12846 .loc 1 6346 7 + 12847 0026 7B68 ldr r3, [r7, #4] + 12848 0028 5A6C ldr r2, [r3, #68] + 12849 .loc 1 6346 19 + 12850 002a 3B68 ldr r3, [r7] + 12851 002c 1A43 orrs r2, r2, r3 + 12852 002e 7B68 ldr r3, [r7, #4] + 12853 0030 5A64 str r2, [r3, #68] +6347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/cc5G5cqz.s page 340 + + +6348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Interrupts */ +6349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((tmpstate == HAL_I2C_STATE_LISTEN) || + 12854 .loc 1 6349 6 + 12855 0032 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 12856 0034 282B cmp r3, #40 + 12857 0036 05D0 beq .L621 + 12858 .loc 1 6349 50 discriminator 1 + 12859 0038 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 12860 003a 292B cmp r3, #41 + 12861 003c 02D0 beq .L621 +6350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) || + 12862 .loc 1 6350 50 + 12863 003e FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 12864 0040 2A2B cmp r3, #42 + 12865 0042 0BD1 bne .L622 + 12866 .L621: +6351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) +6352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable all interrupts, except interrupts related to LISTEN state */ +6354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT); + 12867 .loc 1 6354 5 + 12868 0044 0321 movs r1, #3 + 12869 0046 7868 ldr r0, [r7, #4] + 12870 0048 FFF7FEFF bl I2C_Disable_IRQ +6355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* keep HAL_I2C_STATE_LISTEN if set */ +6357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_LISTEN; + 12871 .loc 1 6357 25 + 12872 004c 7B68 ldr r3, [r7, #4] + 12873 004e 2822 movs r2, #40 + 12874 0050 83F84120 strb r2, [r3, #65] +6358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = I2C_Slave_ISR_IT; + 12875 .loc 1 6358 25 + 12876 0054 7B68 ldr r3, [r7, #4] + 12877 0056 604A ldr r2, .L640+4 + 12878 0058 5A63 str r2, [r3, #52] + 12879 005a 30E0 b .L623 + 12880 .L622: +6359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +6361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable all interrupts */ +6363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); + 12881 .loc 1 6363 5 + 12882 005c 48F20301 movw r1, #32771 + 12883 0060 7868 ldr r0, [r7, #4] + 12884 0062 FFF7FEFF bl I2C_Disable_IRQ +6364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Flush TX register */ +6366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); + 12885 .loc 1 6366 5 + 12886 0066 7868 ldr r0, [r7, #4] + 12887 0068 FFF7FEFF bl I2C_Flush_TXDR +6367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* If state is an abort treatment on going, don't change state */ +6369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* This change will be do later */ +6370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State != HAL_I2C_STATE_ABORT) + ARM GAS /tmp/cc5G5cqz.s page 341 + + + 12888 .loc 1 6370 13 + 12889 006c 7B68 ldr r3, [r7, #4] + 12890 006e 93F84130 ldrb r3, [r3, #65] + 12891 0072 DBB2 uxtb r3, r3 + 12892 .loc 1 6370 8 + 12893 0074 602B cmp r3, #96 + 12894 0076 1FD0 beq .L624 +6371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set HAL_I2C_STATE_READY */ +6373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 12895 .loc 1 6373 27 + 12896 0078 7B68 ldr r3, [r7, #4] + 12897 007a 2022 movs r2, #32 + 12898 007c 83F84120 strb r2, [r3, #65] +6374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check if a STOPF is detected */ +6376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + 12899 .loc 1 6376 11 + 12900 0080 7B68 ldr r3, [r7, #4] + 12901 0082 1B68 ldr r3, [r3] + 12902 0084 9B69 ldr r3, [r3, #24] + 12903 0086 03F02003 and r3, r3, #32 + 12904 .loc 1 6376 10 + 12905 008a 202B cmp r3, #32 + 12906 008c 14D1 bne .L624 +6377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + 12907 .loc 1 6378 13 + 12908 008e 7B68 ldr r3, [r7, #4] + 12909 0090 1B68 ldr r3, [r3] + 12910 0092 9B69 ldr r3, [r3, #24] + 12911 0094 03F01003 and r3, r3, #16 + 12912 .loc 1 6378 12 + 12913 0098 102B cmp r3, #16 + 12914 009a 09D1 bne .L625 +6379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + 12915 .loc 1 6380 11 + 12916 009c 7B68 ldr r3, [r7, #4] + 12917 009e 1B68 ldr r3, [r3] + 12918 00a0 1022 movs r2, #16 + 12919 00a2 DA61 str r2, [r3, #28] +6381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + 12920 .loc 1 6381 15 + 12921 00a4 7B68 ldr r3, [r7, #4] + 12922 00a6 5B6C ldr r3, [r3, #68] + 12923 .loc 1 6381 27 + 12924 00a8 43F00402 orr r2, r3, #4 + 12925 00ac 7B68 ldr r3, [r7, #4] + 12926 00ae 5A64 str r2, [r3, #68] + 12927 .L625: +6382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear STOP Flag */ +6385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + 12928 .loc 1 6385 9 + 12929 00b0 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/cc5G5cqz.s page 342 + + + 12930 00b2 1B68 ldr r3, [r3] + 12931 00b4 2022 movs r2, #32 + 12932 00b6 DA61 str r2, [r3, #28] + 12933 .L624: +6386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferISR = NULL; + 12934 .loc 1 6389 25 + 12935 00b8 7B68 ldr r3, [r7, #4] + 12936 00ba 0022 movs r2, #0 + 12937 00bc 5A63 str r2, [r3, #52] + 12938 .L623: +6390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Abort DMA TX transfer if any */ +6393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmppreviousstate = hi2c->PreviousState; + 12939 .loc 1 6393 20 + 12940 00be 7B68 ldr r3, [r7, #4] + 12941 00c0 1B6B ldr r3, [r3, #48] + 12942 00c2 BB60 str r3, [r7, #8] +6394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \ + 12943 .loc 1 6395 12 + 12944 00c4 7B68 ldr r3, [r7, #4] + 12945 00c6 9B6B ldr r3, [r3, #56] + 12946 .loc 1 6395 6 + 12947 00c8 002B cmp r3, #0 + 12948 00ca 39D0 beq .L626 + 12949 .loc 1 6395 30 discriminator 1 + 12950 00cc BB68 ldr r3, [r7, #8] + 12951 00ce 112B cmp r3, #17 + 12952 00d0 02D0 beq .L627 + 12953 .loc 1 6395 81 discriminator 2 + 12954 00d2 BB68 ldr r3, [r7, #8] + 12955 00d4 212B cmp r3, #33 + 12956 00d6 33D1 bne .L626 + 12957 .L627: +6396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) +6397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + 12958 .loc 1 6398 14 + 12959 00d8 7B68 ldr r3, [r7, #4] + 12960 00da 1B68 ldr r3, [r3] + 12961 .loc 1 6398 24 + 12962 00dc 1B68 ldr r3, [r3] + 12963 .loc 1 6398 30 + 12964 00de 03F48043 and r3, r3, #16384 + 12965 .loc 1 6398 8 + 12966 00e2 B3F5804F cmp r3, #16384 + 12967 00e6 07D1 bne .L628 +6399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + 12968 .loc 1 6400 11 + 12969 00e8 7B68 ldr r3, [r7, #4] + 12970 00ea 1B68 ldr r3, [r3] + 12971 .loc 1 6400 21 + ARM GAS /tmp/cc5G5cqz.s page 343 + + + 12972 00ec 1A68 ldr r2, [r3] + 12973 .loc 1 6400 11 + 12974 00ee 7B68 ldr r3, [r7, #4] + 12975 00f0 1B68 ldr r3, [r3] + 12976 .loc 1 6400 27 + 12977 00f2 22F48042 bic r2, r2, #16384 + 12978 00f6 1A60 str r2, [r3] + 12979 .L628: +6401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) + 12980 .loc 1 6403 9 + 12981 00f8 7B68 ldr r3, [r7, #4] + 12982 00fa 9B6B ldr r3, [r3, #56] + 12983 00fc 1846 mov r0, r3 + 12984 00fe FFF7FEFF bl HAL_DMA_GetState + 12985 0102 0346 mov r3, r0 + 12986 .loc 1 6403 8 discriminator 1 + 12987 0104 012B cmp r3, #1 + 12988 0106 17D0 beq .L629 +6404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the I2C DMA Abort callback : +6406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ +6407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + 12989 .loc 1 6407 11 + 12990 0108 7B68 ldr r3, [r7, #4] + 12991 010a 9B6B ldr r3, [r3, #56] + 12992 .loc 1 6407 39 + 12993 010c 334A ldr r2, .L640+8 + 12994 010e 5A63 str r2, [r3, #52] +6408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +6410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 12995 .loc 1 6410 7 + 12996 0110 7B68 ldr r3, [r7, #4] + 12997 0112 0022 movs r2, #0 + 12998 0114 83F84020 strb r2, [r3, #64] +6411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Abort DMA TX */ +6413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + 12999 .loc 1 6413 11 + 13000 0118 7B68 ldr r3, [r7, #4] + 13001 011a 9B6B ldr r3, [r3, #56] + 13002 011c 1846 mov r0, r3 + 13003 011e FFF7FEFF bl HAL_DMA_Abort_IT + 13004 0122 0346 mov r3, r0 + 13005 .loc 1 6413 10 discriminator 1 + 13006 0124 002B cmp r3, #0 + 13007 0126 4DD0 beq .L637 +6414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call Directly XferAbortCallback function in case of error */ +6416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + 13008 .loc 1 6416 13 + 13009 0128 7B68 ldr r3, [r7, #4] + 13010 012a 9B6B ldr r3, [r3, #56] + 13011 .loc 1 6416 21 + 13012 012c 5B6B ldr r3, [r3, #52] + ARM GAS /tmp/cc5G5cqz.s page 344 + + + 13013 .loc 1 6416 45 + 13014 012e 7A68 ldr r2, [r7, #4] + 13015 0130 926B ldr r2, [r2, #56] + 13016 .loc 1 6416 9 + 13017 0132 1046 mov r0, r2 + 13018 0134 9847 blx r3 + 13019 .LVL7: +6403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 13020 .loc 1 6403 8 + 13021 0136 45E0 b .L637 + 13022 .L629: +6417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +6420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TreatErrorCallback(hi2c); + 13023 .loc 1 6421 7 + 13024 0138 7868 ldr r0, [r7, #4] + 13025 013a FFF7FEFF bl I2C_TreatErrorCallback +6403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 13026 .loc 1 6403 8 + 13027 013e 41E0 b .L637 + 13028 .L626: +6422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Abort DMA RX transfer if any */ +6425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \ + 13029 .loc 1 6425 17 + 13030 0140 7B68 ldr r3, [r7, #4] + 13031 0142 DB6B ldr r3, [r3, #60] + 13032 .loc 1 6425 11 + 13033 0144 002B cmp r3, #0 + 13034 0146 39D0 beq .L632 + 13035 .loc 1 6425 35 discriminator 1 + 13036 0148 BB68 ldr r3, [r7, #8] + 13037 014a 122B cmp r3, #18 + 13038 014c 02D0 beq .L633 + 13039 .loc 1 6425 86 discriminator 2 + 13040 014e BB68 ldr r3, [r7, #8] + 13041 0150 222B cmp r3, #34 + 13042 0152 33D1 bne .L632 + 13043 .L633: +6426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX))) +6427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + 13044 .loc 1 6428 14 + 13045 0154 7B68 ldr r3, [r7, #4] + 13046 0156 1B68 ldr r3, [r3] + 13047 .loc 1 6428 24 + 13048 0158 1B68 ldr r3, [r3] + 13049 .loc 1 6428 30 + 13050 015a 03F40043 and r3, r3, #32768 + 13051 .loc 1 6428 8 + 13052 015e B3F5004F cmp r3, #32768 + 13053 0162 07D1 bne .L634 +6429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + ARM GAS /tmp/cc5G5cqz.s page 345 + + + 13054 .loc 1 6430 11 + 13055 0164 7B68 ldr r3, [r7, #4] + 13056 0166 1B68 ldr r3, [r3] + 13057 .loc 1 6430 21 + 13058 0168 1A68 ldr r2, [r3] + 13059 .loc 1 6430 11 + 13060 016a 7B68 ldr r3, [r7, #4] + 13061 016c 1B68 ldr r3, [r3] + 13062 .loc 1 6430 27 + 13063 016e 22F40042 bic r2, r2, #32768 + 13064 0172 1A60 str r2, [r3] + 13065 .L634: +6431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) + 13066 .loc 1 6433 9 + 13067 0174 7B68 ldr r3, [r7, #4] + 13068 0176 DB6B ldr r3, [r3, #60] + 13069 0178 1846 mov r0, r3 + 13070 017a FFF7FEFF bl HAL_DMA_GetState + 13071 017e 0346 mov r3, r0 + 13072 .loc 1 6433 8 discriminator 1 + 13073 0180 012B cmp r3, #1 + 13074 0182 17D0 beq .L635 +6434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the I2C DMA Abort callback : +6436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ +6437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + 13075 .loc 1 6437 11 + 13076 0184 7B68 ldr r3, [r7, #4] + 13077 0186 DB6B ldr r3, [r3, #60] + 13078 .loc 1 6437 39 + 13079 0188 144A ldr r2, .L640+8 + 13080 018a 5A63 str r2, [r3, #52] +6438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +6440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 13081 .loc 1 6440 7 + 13082 018c 7B68 ldr r3, [r7, #4] + 13083 018e 0022 movs r2, #0 + 13084 0190 83F84020 strb r2, [r3, #64] +6441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Abort DMA RX */ +6443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + 13085 .loc 1 6443 11 + 13086 0194 7B68 ldr r3, [r7, #4] + 13087 0196 DB6B ldr r3, [r3, #60] + 13088 0198 1846 mov r0, r3 + 13089 019a FFF7FEFF bl HAL_DMA_Abort_IT + 13090 019e 0346 mov r3, r0 + 13091 .loc 1 6443 10 discriminator 1 + 13092 01a0 002B cmp r3, #0 + 13093 01a2 11D0 beq .L638 +6444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ +6446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + 13094 .loc 1 6446 13 + ARM GAS /tmp/cc5G5cqz.s page 346 + + + 13095 01a4 7B68 ldr r3, [r7, #4] + 13096 01a6 DB6B ldr r3, [r3, #60] + 13097 .loc 1 6446 21 + 13098 01a8 5B6B ldr r3, [r3, #52] + 13099 .loc 1 6446 45 + 13100 01aa 7A68 ldr r2, [r7, #4] + 13101 01ac D26B ldr r2, [r2, #60] + 13102 .loc 1 6446 9 + 13103 01ae 1046 mov r0, r2 + 13104 01b0 9847 blx r3 + 13105 .LVL8: +6433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 13106 .loc 1 6433 8 + 13107 01b2 09E0 b .L638 + 13108 .L635: +6447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +6450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TreatErrorCallback(hi2c); + 13109 .loc 1 6451 7 + 13110 01b4 7868 ldr r0, [r7, #4] + 13111 01b6 FFF7FEFF bl I2C_TreatErrorCallback +6433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 13112 .loc 1 6433 8 + 13113 01ba 05E0 b .L638 + 13114 .L632: +6452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +6455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TreatErrorCallback(hi2c); + 13115 .loc 1 6456 5 + 13116 01bc 7868 ldr r0, [r7, #4] + 13117 01be FFF7FEFF bl I2C_TreatErrorCallback +6457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 13118 .loc 1 6458 1 + 13119 01c2 02E0 b .L639 + 13120 .L637: +6403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 13121 .loc 1 6403 8 + 13122 01c4 00BF nop + 13123 01c6 00E0 b .L639 + 13124 .L638: +6433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 13125 .loc 1 6433 8 + 13126 01c8 00BF nop + 13127 .L639: + 13128 .loc 1 6458 1 + 13129 01ca 00BF nop + 13130 01cc 1037 adds r7, r7, #16 + 13131 .cfi_def_cfa_offset 8 + 13132 01ce BD46 mov sp, r7 + 13133 .cfi_def_cfa_register 13 + 13134 @ sp needed + 13135 01d0 80BD pop {r7, pc} + ARM GAS /tmp/cc5G5cqz.s page 347 + + + 13136 .L641: + 13137 01d2 00BF .align 2 + 13138 .L640: + 13139 01d4 0000FFFF .word -65536 + 13140 01d8 00000000 .word I2C_Slave_ISR_IT + 13141 01dc 00000000 .word I2C_DMAAbort + 13142 .cfi_endproc + 13143 .LFE193: + 13145 .section .text.I2C_TreatErrorCallback,"ax",%progbits + 13146 .align 1 + 13147 .syntax unified + 13148 .thumb + 13149 .thumb_func + 13151 I2C_TreatErrorCallback: + 13152 .LFB194: +6459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +6461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief I2C Error callback treatment. +6462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c I2C handle. +6463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +6464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +6465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c) +6466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 13153 .loc 1 6466 1 + 13154 .cfi_startproc + 13155 @ args = 0, pretend = 0, frame = 8 + 13156 @ frame_needed = 1, uses_anonymous_args = 0 + 13157 0000 80B5 push {r7, lr} + 13158 .cfi_def_cfa_offset 8 + 13159 .cfi_offset 7, -8 + 13160 .cfi_offset 14, -4 + 13161 0002 82B0 sub sp, sp, #8 + 13162 .cfi_def_cfa_offset 16 + 13163 0004 00AF add r7, sp, #0 + 13164 .cfi_def_cfa_register 7 + 13165 0006 7860 str r0, [r7, #4] +6467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->State == HAL_I2C_STATE_ABORT) + 13166 .loc 1 6467 11 + 13167 0008 7B68 ldr r3, [r7, #4] + 13168 000a 93F84130 ldrb r3, [r3, #65] + 13169 000e DBB2 uxtb r3, r3 + 13170 .loc 1 6467 6 + 13171 0010 602B cmp r3, #96 + 13172 0012 0ED1 bne .L643 +6468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 13173 .loc 1 6469 17 + 13174 0014 7B68 ldr r3, [r7, #4] + 13175 0016 2022 movs r2, #32 + 13176 0018 83F84120 strb r2, [r3, #65] +6470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; + 13177 .loc 1 6470 25 + 13178 001c 7B68 ldr r3, [r7, #4] + 13179 001e 0022 movs r2, #0 + 13180 0020 1A63 str r2, [r3, #48] +6471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ + ARM GAS /tmp/cc5G5cqz.s page 348 + + +6473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 13181 .loc 1 6473 5 + 13182 0022 7B68 ldr r3, [r7, #4] + 13183 0024 0022 movs r2, #0 + 13184 0026 83F84020 strb r2, [r3, #64] +6474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +6476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +6477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->AbortCpltCallback(hi2c); +6478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #else +6479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_AbortCpltCallback(hi2c); + 13185 .loc 1 6479 5 + 13186 002a 7868 ldr r0, [r7, #4] + 13187 002c FFF7FEFF bl HAL_I2C_AbortCpltCallback +6480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +6481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +6483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->PreviousState = I2C_STATE_NONE; +6485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +6487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); +6488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +6490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +6491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCallback(hi2c); +6492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #else +6493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_ErrorCallback(hi2c); +6494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +6495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 13188 .loc 1 6496 1 + 13189 0030 09E0 b .L645 + 13190 .L643: +6484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 13191 .loc 1 6484 25 + 13192 0032 7B68 ldr r3, [r7, #4] + 13193 0034 0022 movs r2, #0 + 13194 0036 1A63 str r2, [r3, #48] +6487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 13195 .loc 1 6487 5 + 13196 0038 7B68 ldr r3, [r7, #4] + 13197 003a 0022 movs r2, #0 + 13198 003c 83F84020 strb r2, [r3, #64] +6493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + 13199 .loc 1 6493 5 + 13200 0040 7868 ldr r0, [r7, #4] + 13201 0042 FFF7FEFF bl HAL_I2C_ErrorCallback + 13202 .L645: + 13203 .loc 1 6496 1 + 13204 0046 00BF nop + 13205 0048 0837 adds r7, r7, #8 + 13206 .cfi_def_cfa_offset 8 + 13207 004a BD46 mov sp, r7 + 13208 .cfi_def_cfa_register 13 + 13209 @ sp needed + 13210 004c 80BD pop {r7, pc} + ARM GAS /tmp/cc5G5cqz.s page 349 + + + 13211 .cfi_endproc + 13212 .LFE194: + 13214 .section .text.I2C_Flush_TXDR,"ax",%progbits + 13215 .align 1 + 13216 .syntax unified + 13217 .thumb + 13218 .thumb_func + 13220 I2C_Flush_TXDR: + 13221 .LFB195: +6497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +6499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief I2C Tx data register flush process. +6500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c I2C handle. +6501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +6502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +6503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) +6504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 13222 .loc 1 6504 1 + 13223 .cfi_startproc + 13224 @ args = 0, pretend = 0, frame = 8 + 13225 @ frame_needed = 1, uses_anonymous_args = 0 + 13226 @ link register save eliminated. + 13227 0000 80B4 push {r7} + 13228 .cfi_def_cfa_offset 4 + 13229 .cfi_offset 7, -4 + 13230 0002 83B0 sub sp, sp, #12 + 13231 .cfi_def_cfa_offset 16 + 13232 0004 00AF add r7, sp, #0 + 13233 .cfi_def_cfa_register 7 + 13234 0006 7860 str r0, [r7, #4] +6505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* If a pending TXIS flag is set */ +6506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Write a dummy data in TXDR to clear it */ +6507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) + 13235 .loc 1 6507 7 + 13236 0008 7B68 ldr r3, [r7, #4] + 13237 000a 1B68 ldr r3, [r3] + 13238 000c 9B69 ldr r3, [r3, #24] + 13239 000e 03F00203 and r3, r3, #2 + 13240 .loc 1 6507 6 + 13241 0012 022B cmp r3, #2 + 13242 0014 03D1 bne .L647 +6508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->TXDR = 0x00U; + 13243 .loc 1 6509 9 + 13244 0016 7B68 ldr r3, [r7, #4] + 13245 0018 1B68 ldr r3, [r3] + 13246 .loc 1 6509 26 + 13247 001a 0022 movs r2, #0 + 13248 001c 9A62 str r2, [r3, #40] + 13249 .L647: +6510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Flush TX register if not empty */ +6513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) + 13250 .loc 1 6513 7 + 13251 001e 7B68 ldr r3, [r7, #4] + 13252 0020 1B68 ldr r3, [r3] + ARM GAS /tmp/cc5G5cqz.s page 350 + + + 13253 0022 9B69 ldr r3, [r3, #24] + 13254 0024 03F00103 and r3, r3, #1 + 13255 .loc 1 6513 6 + 13256 0028 012B cmp r3, #1 + 13257 002a 07D0 beq .L649 +6514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); + 13258 .loc 1 6515 5 + 13259 002c 7B68 ldr r3, [r7, #4] + 13260 002e 1B68 ldr r3, [r3] + 13261 0030 9A69 ldr r2, [r3, #24] + 13262 0032 7B68 ldr r3, [r7, #4] + 13263 0034 1B68 ldr r3, [r3] + 13264 0036 42F00102 orr r2, r2, #1 + 13265 003a 9A61 str r2, [r3, #24] + 13266 .L649: +6516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 13267 .loc 1 6517 1 + 13268 003c 00BF nop + 13269 003e 0C37 adds r7, r7, #12 + 13270 .cfi_def_cfa_offset 4 + 13271 0040 BD46 mov sp, r7 + 13272 .cfi_def_cfa_register 13 + 13273 @ sp needed + 13274 0042 5DF8047B ldr r7, [sp], #4 + 13275 .cfi_restore 7 + 13276 .cfi_def_cfa_offset 0 + 13277 0046 7047 bx lr + 13278 .cfi_endproc + 13279 .LFE195: + 13281 .section .text.I2C_DMAMasterTransmitCplt,"ax",%progbits + 13282 .align 1 + 13283 .syntax unified + 13284 .thumb + 13285 .thumb_func + 13287 I2C_DMAMasterTransmitCplt: + 13288 .LFB196: +6518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +6520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief DMA I2C master transmit process complete callback. +6521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hdma DMA handle +6522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +6523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +6524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) +6525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 13289 .loc 1 6525 1 + 13290 .cfi_startproc + 13291 @ args = 0, pretend = 0, frame = 16 + 13292 @ frame_needed = 1, uses_anonymous_args = 0 + 13293 0000 80B5 push {r7, lr} + 13294 .cfi_def_cfa_offset 8 + 13295 .cfi_offset 7, -8 + 13296 .cfi_offset 14, -4 + 13297 0002 84B0 sub sp, sp, #16 + 13298 .cfi_def_cfa_offset 24 + 13299 0004 00AF add r7, sp, #0 + ARM GAS /tmp/cc5G5cqz.s page 351 + + + 13300 .cfi_def_cfa_register 7 + 13301 0006 7860 str r0, [r7, #4] +6526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ +6527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + 13302 .loc 1 6527 22 + 13303 0008 7B68 ldr r3, [r7, #4] + 13304 000a 5B6A ldr r3, [r3, #36] + 13305 000c FB60 str r3, [r7, #12] +6528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable DMA Request */ +6530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + 13306 .loc 1 6530 7 + 13307 000e FB68 ldr r3, [r7, #12] + 13308 0010 1B68 ldr r3, [r3] + 13309 .loc 1 6530 17 + 13310 0012 1A68 ldr r2, [r3] + 13311 .loc 1 6530 7 + 13312 0014 FB68 ldr r3, [r7, #12] + 13313 0016 1B68 ldr r3, [r3] + 13314 .loc 1 6530 23 + 13315 0018 22F48042 bic r2, r2, #16384 + 13316 001c 1A60 str r2, [r3] +6531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* If last transfer, enable STOP interrupt */ +6533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount == 0U) + 13317 .loc 1 6533 11 + 13318 001e FB68 ldr r3, [r7, #12] + 13319 0020 5B8D ldrh r3, [r3, #42] @ movhi + 13320 0022 9BB2 uxth r3, r3 + 13321 .loc 1 6533 6 + 13322 0024 002B cmp r3, #0 + 13323 0026 04D1 bne .L651 +6534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable STOP interrupt */ +6536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + 13324 .loc 1 6536 5 + 13325 0028 2021 movs r1, #32 + 13326 002a F868 ldr r0, [r7, #12] + 13327 002c FFF7FEFF bl I2C_Enable_IRQ +6537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* else prepare a new DMA transfer and enable TCReload interrupt */ +6539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +6540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update Buffer pointer */ +6542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr += hi2c->XferSize; +6543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the XferSize to transfer */ +6545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +6546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +6548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +6550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +6552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable the DMA channel */ + ARM GAS /tmp/cc5G5cqz.s page 352 + + +6555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, +6556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) +6557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +6559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); +6560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +6562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable TC interrupts */ +6564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); +6565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 13328 .loc 1 6567 1 + 13329 0030 2DE0 b .L656 + 13330 .L651: +6542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 13331 .loc 1 6542 9 + 13332 0032 FB68 ldr r3, [r7, #12] + 13333 0034 5B6A ldr r3, [r3, #36] +6542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 13334 .loc 1 6542 27 + 13335 0036 FA68 ldr r2, [r7, #12] + 13336 0038 128D ldrh r2, [r2, #40] +6542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 13337 .loc 1 6542 20 + 13338 003a 1A44 add r2, r2, r3 + 13339 003c FB68 ldr r3, [r7, #12] + 13340 003e 5A62 str r2, [r3, #36] +6545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 13341 .loc 1 6545 13 + 13342 0040 FB68 ldr r3, [r7, #12] + 13343 0042 5B8D ldrh r3, [r3, #42] @ movhi + 13344 0044 9BB2 uxth r3, r3 +6545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 13345 .loc 1 6545 8 + 13346 0046 FF2B cmp r3, #255 + 13347 0048 03D9 bls .L653 +6547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 13348 .loc 1 6547 22 + 13349 004a FB68 ldr r3, [r7, #12] + 13350 004c FF22 movs r2, #255 + 13351 004e 1A85 strh r2, [r3, #40] @ movhi + 13352 0050 04E0 b .L654 + 13353 .L653: +6551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 13354 .loc 1 6551 28 + 13355 0052 FB68 ldr r3, [r7, #12] + 13356 0054 5B8D ldrh r3, [r3, #42] @ movhi + 13357 0056 9AB2 uxth r2, r3 +6551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 13358 .loc 1 6551 22 + 13359 0058 FB68 ldr r3, [r7, #12] + 13360 005a 1A85 strh r2, [r3, #40] @ movhi + 13361 .L654: +6555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) + 13362 .loc 1 6555 9 + ARM GAS /tmp/cc5G5cqz.s page 353 + + + 13363 005c FB68 ldr r3, [r7, #12] + 13364 005e 986B ldr r0, [r3, #56] +6555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) + 13365 .loc 1 6555 54 + 13366 0060 FB68 ldr r3, [r7, #12] + 13367 0062 5B6A ldr r3, [r3, #36] +6555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) + 13368 .loc 1 6555 9 + 13369 0064 1946 mov r1, r3 +6555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) + 13370 .loc 1 6555 81 + 13371 0066 FB68 ldr r3, [r7, #12] + 13372 0068 1B68 ldr r3, [r3] +6555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) + 13373 .loc 1 6555 76 + 13374 006a 2833 adds r3, r3, #40 +6555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) + 13375 .loc 1 6555 9 + 13376 006c 1A46 mov r2, r3 +6556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 13377 .loc 1 6556 30 + 13378 006e FB68 ldr r3, [r7, #12] + 13379 0070 1B8D ldrh r3, [r3, #40] +6555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) + 13380 .loc 1 6555 9 + 13381 0072 FFF7FEFF bl HAL_DMA_Start_IT + 13382 0076 0346 mov r3, r0 +6555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) + 13383 .loc 1 6555 8 discriminator 1 + 13384 0078 002B cmp r3, #0 + 13385 007a 04D0 beq .L655 +6559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 13386 .loc 1 6559 7 + 13387 007c 1021 movs r1, #16 + 13388 007e F868 ldr r0, [r7, #12] + 13389 0080 FFF7FEFF bl I2C_ITError + 13390 .loc 1 6567 1 + 13391 0084 03E0 b .L656 + 13392 .L655: +6564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 13393 .loc 1 6564 7 + 13394 0086 4021 movs r1, #64 + 13395 0088 F868 ldr r0, [r7, #12] + 13396 008a FFF7FEFF bl I2C_Enable_IRQ + 13397 .L656: + 13398 .loc 1 6567 1 + 13399 008e 00BF nop + 13400 0090 1037 adds r7, r7, #16 + 13401 .cfi_def_cfa_offset 8 + 13402 0092 BD46 mov sp, r7 + 13403 .cfi_def_cfa_register 13 + 13404 @ sp needed + 13405 0094 80BD pop {r7, pc} + 13406 .cfi_endproc + 13407 .LFE196: + 13409 .section .text.I2C_DMASlaveTransmitCplt,"ax",%progbits + 13410 .align 1 + ARM GAS /tmp/cc5G5cqz.s page 354 + + + 13411 .syntax unified + 13412 .thumb + 13413 .thumb_func + 13415 I2C_DMASlaveTransmitCplt: + 13416 .LFB197: +6568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +6571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief DMA I2C slave transmit process complete callback. +6572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hdma DMA handle +6573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +6574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +6575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) +6576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 13417 .loc 1 6576 1 + 13418 .cfi_startproc + 13419 @ args = 0, pretend = 0, frame = 16 + 13420 @ frame_needed = 1, uses_anonymous_args = 0 + 13421 0000 80B5 push {r7, lr} + 13422 .cfi_def_cfa_offset 8 + 13423 .cfi_offset 7, -8 + 13424 .cfi_offset 14, -4 + 13425 0002 84B0 sub sp, sp, #16 + 13426 .cfi_def_cfa_offset 24 + 13427 0004 00AF add r7, sp, #0 + 13428 .cfi_def_cfa_register 7 + 13429 0006 7860 str r0, [r7, #4] +6577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ +6578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + 13430 .loc 1 6578 22 + 13431 0008 7B68 ldr r3, [r7, #4] + 13432 000a 5B6A ldr r3, [r3, #36] + 13433 000c FB60 str r3, [r7, #12] +6579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; + 13434 .loc 1 6579 12 + 13435 000e FB68 ldr r3, [r7, #12] + 13436 0010 DB6A ldr r3, [r3, #44] + 13437 0012 BB60 str r3, [r7, #8] +6580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) + 13438 .loc 1 6581 6 + 13439 0014 BB68 ldr r3, [r7, #8] + 13440 0016 B3F1807F cmp r3, #16777216 + 13441 001a 02D0 beq .L658 + 13442 .loc 1 6581 38 discriminator 1 + 13443 001c BB68 ldr r3, [r7, #8] + 13444 001e 002B cmp r3, #0 + 13445 0020 0AD1 bne .L660 + 13446 .L658: +6582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable DMA Request */ +6584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + 13447 .loc 1 6584 9 + 13448 0022 FB68 ldr r3, [r7, #12] + 13449 0024 1B68 ldr r3, [r3] + 13450 .loc 1 6584 19 + 13451 0026 1A68 ldr r2, [r3] + ARM GAS /tmp/cc5G5cqz.s page 355 + + + 13452 .loc 1 6584 9 + 13453 0028 FB68 ldr r3, [r7, #12] + 13454 002a 1B68 ldr r3, [r3] + 13455 .loc 1 6584 25 + 13456 002c 22F48042 bic r2, r2, #16384 + 13457 0030 1A60 str r2, [r3] +6585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Last Byte is Transmitted */ +6587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call I2C Slave Sequential complete process */ +6588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITSlaveSeqCplt(hi2c); + 13458 .loc 1 6588 5 + 13459 0032 F868 ldr r0, [r7, #12] + 13460 0034 FFF7FEFF bl I2C_ITSlaveSeqCplt + 13461 .L660: +6589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +6591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* No specific action, Master fully manage the generation of STOP condition */ +6593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Mean that this generation can arrive at any time, at the end or during DMA process */ +6594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* So STOP condition should be manage through Interrupt treatment */ +6595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 13462 .loc 1 6596 1 + 13463 0038 00BF nop + 13464 003a 1037 adds r7, r7, #16 + 13465 .cfi_def_cfa_offset 8 + 13466 003c BD46 mov sp, r7 + 13467 .cfi_def_cfa_register 13 + 13468 @ sp needed + 13469 003e 80BD pop {r7, pc} + 13470 .cfi_endproc + 13471 .LFE197: + 13473 .section .text.I2C_DMAMasterReceiveCplt,"ax",%progbits + 13474 .align 1 + 13475 .syntax unified + 13476 .thumb + 13477 .thumb_func + 13479 I2C_DMAMasterReceiveCplt: + 13480 .LFB198: +6597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +6600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief DMA I2C master receive process complete callback. +6601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hdma DMA handle +6602:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +6603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +6604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) +6605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 13481 .loc 1 6605 1 + 13482 .cfi_startproc + 13483 @ args = 0, pretend = 0, frame = 16 + 13484 @ frame_needed = 1, uses_anonymous_args = 0 + 13485 0000 80B5 push {r7, lr} + 13486 .cfi_def_cfa_offset 8 + 13487 .cfi_offset 7, -8 + 13488 .cfi_offset 14, -4 + 13489 0002 84B0 sub sp, sp, #16 + ARM GAS /tmp/cc5G5cqz.s page 356 + + + 13490 .cfi_def_cfa_offset 24 + 13491 0004 00AF add r7, sp, #0 + 13492 .cfi_def_cfa_register 7 + 13493 0006 7860 str r0, [r7, #4] +6606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ +6607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + 13494 .loc 1 6607 22 + 13495 0008 7B68 ldr r3, [r7, #4] + 13496 000a 5B6A ldr r3, [r3, #36] + 13497 000c FB60 str r3, [r7, #12] +6608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable DMA Request */ +6610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + 13498 .loc 1 6610 7 + 13499 000e FB68 ldr r3, [r7, #12] + 13500 0010 1B68 ldr r3, [r3] + 13501 .loc 1 6610 17 + 13502 0012 1A68 ldr r2, [r3] + 13503 .loc 1 6610 7 + 13504 0014 FB68 ldr r3, [r7, #12] + 13505 0016 1B68 ldr r3, [r3] + 13506 .loc 1 6610 23 + 13507 0018 22F40042 bic r2, r2, #32768 + 13508 001c 1A60 str r2, [r3] +6611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6612:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* If last transfer, enable STOP interrupt */ +6613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount == 0U) + 13509 .loc 1 6613 11 + 13510 001e FB68 ldr r3, [r7, #12] + 13511 0020 5B8D ldrh r3, [r3, #42] @ movhi + 13512 0022 9BB2 uxth r3, r3 + 13513 .loc 1 6613 6 + 13514 0024 002B cmp r3, #0 + 13515 0026 04D1 bne .L662 +6614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable STOP interrupt */ +6616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + 13516 .loc 1 6616 5 + 13517 0028 2021 movs r1, #32 + 13518 002a F868 ldr r0, [r7, #12] + 13519 002c FFF7FEFF bl I2C_Enable_IRQ +6617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* else prepare a new DMA transfer and enable TCReload interrupt */ +6619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +6620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update Buffer pointer */ +6622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->pBuffPtr += hi2c->XferSize; +6623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Set the XferSize to transfer */ +6625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferCount > MAX_NBYTE_SIZE) +6626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = MAX_NBYTE_SIZE; +6628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +6630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize = hi2c->XferCount; +6632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/cc5G5cqz.s page 357 + + +6633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable the DMA channel */ +6635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, +6636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) +6637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +6639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); +6640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +6642:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable TC interrupts */ +6644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); +6645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 13520 .loc 1 6647 1 + 13521 0030 2DE0 b .L667 + 13522 .L662: +6622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 13523 .loc 1 6622 9 + 13524 0032 FB68 ldr r3, [r7, #12] + 13525 0034 5B6A ldr r3, [r3, #36] +6622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 13526 .loc 1 6622 27 + 13527 0036 FA68 ldr r2, [r7, #12] + 13528 0038 128D ldrh r2, [r2, #40] +6622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + 13529 .loc 1 6622 20 + 13530 003a 1A44 add r2, r2, r3 + 13531 003c FB68 ldr r3, [r7, #12] + 13532 003e 5A62 str r2, [r3, #36] +6625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 13533 .loc 1 6625 13 + 13534 0040 FB68 ldr r3, [r7, #12] + 13535 0042 5B8D ldrh r3, [r3, #42] @ movhi + 13536 0044 9BB2 uxth r3, r3 +6625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 13537 .loc 1 6625 8 + 13538 0046 FF2B cmp r3, #255 + 13539 0048 03D9 bls .L664 +6627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 13540 .loc 1 6627 22 + 13541 004a FB68 ldr r3, [r7, #12] + 13542 004c FF22 movs r2, #255 + 13543 004e 1A85 strh r2, [r3, #40] @ movhi + 13544 0050 04E0 b .L665 + 13545 .L664: +6631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 13546 .loc 1 6631 28 + 13547 0052 FB68 ldr r3, [r7, #12] + 13548 0054 5B8D ldrh r3, [r3, #42] @ movhi + 13549 0056 9AB2 uxth r2, r3 +6631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 13550 .loc 1 6631 22 + 13551 0058 FB68 ldr r3, [r7, #12] + 13552 005a 1A85 strh r2, [r3, #40] @ movhi + 13553 .L665: + ARM GAS /tmp/cc5G5cqz.s page 358 + + +6635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) + 13554 .loc 1 6635 9 + 13555 005c FB68 ldr r3, [r7, #12] + 13556 005e D86B ldr r0, [r3, #60] +6635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) + 13557 .loc 1 6635 55 + 13558 0060 FB68 ldr r3, [r7, #12] + 13559 0062 1B68 ldr r3, [r3] +6635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) + 13560 .loc 1 6635 50 + 13561 0064 2433 adds r3, r3, #36 +6635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) + 13562 .loc 1 6635 9 + 13563 0066 1946 mov r1, r3 +6635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) + 13564 .loc 1 6635 87 + 13565 0068 FB68 ldr r3, [r7, #12] + 13566 006a 5B6A ldr r3, [r3, #36] +6635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) + 13567 .loc 1 6635 9 + 13568 006c 1A46 mov r2, r3 +6636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 13569 .loc 1 6636 30 + 13570 006e FB68 ldr r3, [r7, #12] + 13571 0070 1B8D ldrh r3, [r3, #40] +6635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) + 13572 .loc 1 6635 9 + 13573 0072 FFF7FEFF bl HAL_DMA_Start_IT + 13574 0076 0346 mov r3, r0 +6635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferSize) != HAL_OK) + 13575 .loc 1 6635 8 discriminator 1 + 13576 0078 002B cmp r3, #0 + 13577 007a 04D0 beq .L666 +6639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 13578 .loc 1 6639 7 + 13579 007c 1021 movs r1, #16 + 13580 007e F868 ldr r0, [r7, #12] + 13581 0080 FFF7FEFF bl I2C_ITError + 13582 .loc 1 6647 1 + 13583 0084 03E0 b .L667 + 13584 .L666: +6644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 13585 .loc 1 6644 7 + 13586 0086 4021 movs r1, #64 + 13587 0088 F868 ldr r0, [r7, #12] + 13588 008a FFF7FEFF bl I2C_Enable_IRQ + 13589 .L667: + 13590 .loc 1 6647 1 + 13591 008e 00BF nop + 13592 0090 1037 adds r7, r7, #16 + 13593 .cfi_def_cfa_offset 8 + 13594 0092 BD46 mov sp, r7 + 13595 .cfi_def_cfa_register 13 + 13596 @ sp needed + 13597 0094 80BD pop {r7, pc} + 13598 .cfi_endproc + 13599 .LFE198: + ARM GAS /tmp/cc5G5cqz.s page 359 + + + 13601 .section .text.I2C_DMASlaveReceiveCplt,"ax",%progbits + 13602 .align 1 + 13603 .syntax unified + 13604 .thumb + 13605 .thumb_func + 13607 I2C_DMASlaveReceiveCplt: + 13608 .LFB199: +6648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +6651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief DMA I2C slave receive process complete callback. +6652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hdma DMA handle +6653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +6654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +6655:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) +6656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 13609 .loc 1 6656 1 + 13610 .cfi_startproc + 13611 @ args = 0, pretend = 0, frame = 16 + 13612 @ frame_needed = 1, uses_anonymous_args = 0 + 13613 0000 80B5 push {r7, lr} + 13614 .cfi_def_cfa_offset 8 + 13615 .cfi_offset 7, -8 + 13616 .cfi_offset 14, -4 + 13617 0002 84B0 sub sp, sp, #16 + 13618 .cfi_def_cfa_offset 24 + 13619 0004 00AF add r7, sp, #0 + 13620 .cfi_def_cfa_register 7 + 13621 0006 7860 str r0, [r7, #4] +6657:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ +6658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + 13622 .loc 1 6658 22 + 13623 0008 7B68 ldr r3, [r7, #4] + 13624 000a 5B6A ldr r3, [r3, #36] + 13625 000c FB60 str r3, [r7, #12] +6659:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmpoptions = hi2c->XferOptions; + 13626 .loc 1 6659 12 + 13627 000e FB68 ldr r3, [r7, #12] + 13628 0010 DB6A ldr r3, [r3, #44] + 13629 0012 BB60 str r3, [r7, #8] +6660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) && \ + 13630 .loc 1 6661 8 + 13631 0014 FB68 ldr r3, [r7, #12] + 13632 0016 DB6B ldr r3, [r3, #60] + 13633 0018 1B68 ldr r3, [r3] + 13634 001a 5B68 ldr r3, [r3, #4] + 13635 .loc 1 6661 6 + 13636 001c 002B cmp r3, #0 + 13637 001e 0ED1 bne .L670 + 13638 .loc 1 6661 53 discriminator 1 + 13639 0020 BB68 ldr r3, [r7, #8] + 13640 0022 13F5803F cmn r3, #65536 + 13641 0026 0AD0 beq .L670 +6662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (tmpoptions != I2C_NO_OPTION_FRAME)) +6663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6664:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable DMA Request */ + ARM GAS /tmp/cc5G5cqz.s page 360 + + +6665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + 13642 .loc 1 6665 9 + 13643 0028 FB68 ldr r3, [r7, #12] + 13644 002a 1B68 ldr r3, [r3] + 13645 .loc 1 6665 19 + 13646 002c 1A68 ldr r2, [r3] + 13647 .loc 1 6665 9 + 13648 002e FB68 ldr r3, [r7, #12] + 13649 0030 1B68 ldr r3, [r3] + 13650 .loc 1 6665 25 + 13651 0032 22F40042 bic r2, r2, #32768 + 13652 0036 1A60 str r2, [r3] +6666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call I2C Slave Sequential complete process */ +6668:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITSlaveSeqCplt(hi2c); + 13653 .loc 1 6668 5 + 13654 0038 F868 ldr r0, [r7, #12] + 13655 003a FFF7FEFF bl I2C_ITSlaveSeqCplt + 13656 .L670: +6669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +6671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* No specific action, Master fully manage the generation of STOP condition */ +6673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Mean that this generation can arrive at any time, at the end or during DMA process */ +6674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* So STOP condition should be manage through Interrupt treatment */ +6675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 13657 .loc 1 6676 1 + 13658 003e 00BF nop + 13659 0040 1037 adds r7, r7, #16 + 13660 .cfi_def_cfa_offset 8 + 13661 0042 BD46 mov sp, r7 + 13662 .cfi_def_cfa_register 13 + 13663 @ sp needed + 13664 0044 80BD pop {r7, pc} + 13665 .cfi_endproc + 13666 .LFE199: + 13668 .section .text.I2C_DMAError,"ax",%progbits + 13669 .align 1 + 13670 .syntax unified + 13671 .thumb + 13672 .thumb_func + 13674 I2C_DMAError: + 13675 .LFB200: +6677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +6680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief DMA I2C communication error callback. +6681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hdma DMA handle +6682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +6683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +6684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_DMAError(DMA_HandleTypeDef *hdma) +6685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 13676 .loc 1 6685 1 + 13677 .cfi_startproc + 13678 @ args = 0, pretend = 0, frame = 16 + 13679 @ frame_needed = 1, uses_anonymous_args = 0 + ARM GAS /tmp/cc5G5cqz.s page 361 + + + 13680 0000 80B5 push {r7, lr} + 13681 .cfi_def_cfa_offset 8 + 13682 .cfi_offset 7, -8 + 13683 .cfi_offset 14, -4 + 13684 0002 84B0 sub sp, sp, #16 + 13685 .cfi_def_cfa_offset 24 + 13686 0004 00AF add r7, sp, #0 + 13687 .cfi_def_cfa_register 7 + 13688 0006 7860 str r0, [r7, #4] +6686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ +6687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + 13689 .loc 1 6687 22 + 13690 0008 7B68 ldr r3, [r7, #4] + 13691 000a 5B6A ldr r3, [r3, #36] + 13692 000c FB60 str r3, [r7, #12] +6688:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable Acknowledge */ +6690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_NACK; + 13693 .loc 1 6690 7 + 13694 000e FB68 ldr r3, [r7, #12] + 13695 0010 1B68 ldr r3, [r3] + 13696 .loc 1 6690 17 + 13697 0012 5A68 ldr r2, [r3, #4] + 13698 .loc 1 6690 7 + 13699 0014 FB68 ldr r3, [r7, #12] + 13700 0016 1B68 ldr r3, [r3] + 13701 .loc 1 6690 23 + 13702 0018 42F40042 orr r2, r2, #32768 + 13703 001c 5A60 str r2, [r3, #4] +6691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Call the corresponding callback to inform upper layer of End of Transfer */ +6693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); + 13704 .loc 1 6693 3 + 13705 001e 1021 movs r1, #16 + 13706 0020 F868 ldr r0, [r7, #12] + 13707 0022 FFF7FEFF bl I2C_ITError +6694:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 13708 .loc 1 6694 1 + 13709 0026 00BF nop + 13710 0028 1037 adds r7, r7, #16 + 13711 .cfi_def_cfa_offset 8 + 13712 002a BD46 mov sp, r7 + 13713 .cfi_def_cfa_register 13 + 13714 @ sp needed + 13715 002c 80BD pop {r7, pc} + 13716 .cfi_endproc + 13717 .LFE200: + 13719 .section .text.I2C_DMAAbort,"ax",%progbits + 13720 .align 1 + 13721 .syntax unified + 13722 .thumb + 13723 .thumb_func + 13725 I2C_DMAAbort: + 13726 .LFB201: +6695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** + ARM GAS /tmp/cc5G5cqz.s page 362 + + +6698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief DMA I2C communication abort callback +6699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * (To be called at end of DMA Abort procedure). +6700:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hdma DMA handle. +6701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +6702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +6703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) +6704:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 13727 .loc 1 6704 1 + 13728 .cfi_startproc + 13729 @ args = 0, pretend = 0, frame = 16 + 13730 @ frame_needed = 1, uses_anonymous_args = 0 + 13731 0000 80B5 push {r7, lr} + 13732 .cfi_def_cfa_offset 8 + 13733 .cfi_offset 7, -8 + 13734 .cfi_offset 14, -4 + 13735 0002 84B0 sub sp, sp, #16 + 13736 .cfi_def_cfa_offset 24 + 13737 0004 00AF add r7, sp, #0 + 13738 .cfi_def_cfa_register 7 + 13739 0006 7860 str r0, [r7, #4] +6705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Derogation MISRAC2012-Rule-11.5 */ +6706:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + 13740 .loc 1 6706 22 + 13741 0008 7B68 ldr r3, [r7, #4] + 13742 000a 5B6A ldr r3, [r3, #36] + 13743 000c FB60 str r3, [r7, #12] +6707:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6708:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Reset AbortCpltCallback */ +6709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->hdmatx != NULL) + 13744 .loc 1 6709 11 + 13745 000e FB68 ldr r3, [r7, #12] + 13746 0010 9B6B ldr r3, [r3, #56] + 13747 .loc 1 6709 6 + 13748 0012 002B cmp r3, #0 + 13749 0014 03D0 beq .L673 +6710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmatx->XferAbortCallback = NULL; + 13750 .loc 1 6711 9 + 13751 0016 FB68 ldr r3, [r7, #12] + 13752 0018 9B6B ldr r3, [r3, #56] + 13753 .loc 1 6711 37 + 13754 001a 0022 movs r2, #0 + 13755 001c 5A63 str r2, [r3, #52] + 13756 .L673: +6712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6713:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->hdmarx != NULL) + 13757 .loc 1 6713 11 + 13758 001e FB68 ldr r3, [r7, #12] + 13759 0020 DB6B ldr r3, [r3, #60] + 13760 .loc 1 6713 6 + 13761 0022 002B cmp r3, #0 + 13762 0024 03D0 beq .L674 +6714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->hdmarx->XferAbortCallback = NULL; + 13763 .loc 1 6715 9 + 13764 0026 FB68 ldr r3, [r7, #12] + 13765 0028 DB6B ldr r3, [r3, #60] + ARM GAS /tmp/cc5G5cqz.s page 363 + + + 13766 .loc 1 6715 37 + 13767 002a 0022 movs r2, #0 + 13768 002c 5A63 str r2, [r3, #52] + 13769 .L674: +6716:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6718:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_TreatErrorCallback(hi2c); + 13770 .loc 1 6718 3 + 13771 002e F868 ldr r0, [r7, #12] + 13772 0030 FFF7FEFF bl I2C_TreatErrorCallback +6719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 13773 .loc 1 6719 1 + 13774 0034 00BF nop + 13775 0036 1037 adds r7, r7, #16 + 13776 .cfi_def_cfa_offset 8 + 13777 0038 BD46 mov sp, r7 + 13778 .cfi_def_cfa_register 13 + 13779 @ sp needed + 13780 003a 80BD pop {r7, pc} + 13781 .cfi_endproc + 13782 .LFE201: + 13784 .section .text.I2C_WaitOnFlagUntilTimeout,"ax",%progbits + 13785 .align 1 + 13786 .syntax unified + 13787 .thumb + 13788 .thumb_func + 13790 I2C_WaitOnFlagUntilTimeout: + 13791 .LFB202: +6720:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6722:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +6723:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief This function handles I2C Communication Timeout. It waits +6724:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * until a flag is no longer in the specified status. +6725:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +6726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +6727:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Flag Specifies the I2C flag to check. +6728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Status The actual Flag status (SET or RESET). +6729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Timeout Timeout duration +6730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Tickstart Tick start value +6731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +6732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +6733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagSta +6734:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t Timeout, uint32_t Tickstart) +6735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 13792 .loc 1 6735 1 + 13793 .cfi_startproc + 13794 @ args = 4, pretend = 0, frame = 16 + 13795 @ frame_needed = 1, uses_anonymous_args = 0 + 13796 0000 80B5 push {r7, lr} + 13797 .cfi_def_cfa_offset 8 + 13798 .cfi_offset 7, -8 + 13799 .cfi_offset 14, -4 + 13800 0002 84B0 sub sp, sp, #16 + 13801 .cfi_def_cfa_offset 24 + 13802 0004 00AF add r7, sp, #0 + 13803 .cfi_def_cfa_register 7 + 13804 0006 F860 str r0, [r7, #12] + ARM GAS /tmp/cc5G5cqz.s page 364 + + + 13805 0008 B960 str r1, [r7, #8] + 13806 000a 3B60 str r3, [r7] + 13807 000c 1346 mov r3, r2 + 13808 000e FB71 strb r3, [r7, #7] +6736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) + 13809 .loc 1 6736 9 + 13810 0010 31E0 b .L677 + 13811 .L681: +6737:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check for the Timeout */ +6739:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (Timeout != HAL_MAX_DELAY) + 13812 .loc 1 6739 8 + 13813 0012 3B68 ldr r3, [r7] + 13814 0014 B3F1FF3F cmp r3, #-1 + 13815 0018 2DD0 beq .L677 +6740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + 13816 .loc 1 6741 13 + 13817 001a FFF7FEFF bl HAL_GetTick + 13818 001e 0246 mov r2, r0 + 13819 .loc 1 6741 27 discriminator 1 + 13820 0020 BB69 ldr r3, [r7, #24] + 13821 0022 D31A subs r3, r2, r3 + 13822 .loc 1 6741 10 discriminator 1 + 13823 0024 3A68 ldr r2, [r7] + 13824 0026 9A42 cmp r2, r3 + 13825 0028 02D3 bcc .L678 + 13826 .loc 1 6741 51 discriminator 1 + 13827 002a 3B68 ldr r3, [r7] + 13828 002c 002B cmp r3, #0 + 13829 002e 22D1 bne .L677 + 13830 .L678: +6742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6743:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)) + 13831 .loc 1 6743 14 + 13832 0030 FB68 ldr r3, [r7, #12] + 13833 0032 1B68 ldr r3, [r3] + 13834 0034 9A69 ldr r2, [r3, #24] + 13835 0036 BB68 ldr r3, [r7, #8] + 13836 0038 1340 ands r3, r3, r2 + 13837 003a BA68 ldr r2, [r7, #8] + 13838 003c 9A42 cmp r2, r3 + 13839 003e 0CBF ite eq + 13840 0040 0123 moveq r3, #1 + 13841 0042 0023 movne r3, #0 + 13842 0044 DBB2 uxtb r3, r3 + 13843 0046 1A46 mov r2, r3 + 13844 .loc 1 6743 45 + 13845 0048 FB79 ldrb r3, [r7, #7] @ zero_extendqisi2 + 13846 .loc 1 6743 12 + 13847 004a 9A42 cmp r2, r3 + 13848 004c 13D1 bne .L677 +6744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6745:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + 13849 .loc 1 6745 15 + 13850 004e FB68 ldr r3, [r7, #12] + 13851 0050 5B6C ldr r3, [r3, #68] + ARM GAS /tmp/cc5G5cqz.s page 365 + + + 13852 .loc 1 6745 27 + 13853 0052 43F02002 orr r2, r3, #32 + 13854 0056 FB68 ldr r3, [r7, #12] + 13855 0058 5A64 str r2, [r3, #68] +6746:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 13856 .loc 1 6746 23 + 13857 005a FB68 ldr r3, [r7, #12] + 13858 005c 2022 movs r2, #32 + 13859 005e 83F84120 strb r2, [r3, #65] +6747:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 13860 .loc 1 6747 22 + 13861 0062 FB68 ldr r3, [r7, #12] + 13862 0064 0022 movs r2, #0 + 13863 0066 83F84220 strb r2, [r3, #66] +6748:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +6750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 13864 .loc 1 6750 11 + 13865 006a FB68 ldr r3, [r7, #12] + 13866 006c 0022 movs r2, #0 + 13867 006e 83F84020 strb r2, [r3, #64] +6751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 13868 .loc 1 6751 18 + 13869 0072 0123 movs r3, #1 + 13870 0074 0FE0 b .L680 + 13871 .L677: +6736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 13872 .loc 1 6736 10 + 13873 0076 FB68 ldr r3, [r7, #12] + 13874 0078 1B68 ldr r3, [r3] + 13875 007a 9A69 ldr r2, [r3, #24] + 13876 007c BB68 ldr r3, [r7, #8] + 13877 007e 1340 ands r3, r3, r2 + 13878 0080 BA68 ldr r2, [r7, #8] + 13879 0082 9A42 cmp r2, r3 + 13880 0084 0CBF ite eq + 13881 0086 0123 moveq r3, #1 + 13882 0088 0023 movne r3, #0 + 13883 008a DBB2 uxtb r3, r3 + 13884 008c 1A46 mov r2, r3 +6736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 13885 .loc 1 6736 41 + 13886 008e FB79 ldrb r3, [r7, #7] @ zero_extendqisi2 + 13887 0090 9A42 cmp r2, r3 + 13888 0092 BED0 beq .L681 +6752:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6755:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; + 13889 .loc 1 6756 10 + 13890 0094 0023 movs r3, #0 + 13891 .L680: +6757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 13892 .loc 1 6757 1 + 13893 0096 1846 mov r0, r3 + 13894 0098 1037 adds r7, r7, #16 + ARM GAS /tmp/cc5G5cqz.s page 366 + + + 13895 .cfi_def_cfa_offset 8 + 13896 009a BD46 mov sp, r7 + 13897 .cfi_def_cfa_register 13 + 13898 @ sp needed + 13899 009c 80BD pop {r7, pc} + 13900 .cfi_endproc + 13901 .LFE202: + 13903 .section .text.I2C_WaitOnTXISFlagUntilTimeout,"ax",%progbits + 13904 .align 1 + 13905 .syntax unified + 13906 .thumb + 13907 .thumb_func + 13909 I2C_WaitOnTXISFlagUntilTimeout: + 13910 .LFB203: +6758:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +6760:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag. +6761:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +6762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +6763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Timeout Timeout duration +6764:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Tickstart Tick start value +6765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +6766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +6767:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, +6768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t Tickstart) +6769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 13911 .loc 1 6769 1 + 13912 .cfi_startproc + 13913 @ args = 0, pretend = 0, frame = 16 + 13914 @ frame_needed = 1, uses_anonymous_args = 0 + 13915 0000 80B5 push {r7, lr} + 13916 .cfi_def_cfa_offset 8 + 13917 .cfi_offset 7, -8 + 13918 .cfi_offset 14, -4 + 13919 0002 84B0 sub sp, sp, #16 + 13920 .cfi_def_cfa_offset 24 + 13921 0004 00AF add r7, sp, #0 + 13922 .cfi_def_cfa_register 7 + 13923 0006 F860 str r0, [r7, #12] + 13924 0008 B960 str r1, [r7, #8] + 13925 000a 7A60 str r2, [r7, #4] +6770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) + 13926 .loc 1 6770 9 + 13927 000c 33E0 b .L686 + 13928 .L689: +6771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check if an error is detected */ +6773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) + 13929 .loc 1 6773 9 + 13930 000e 7A68 ldr r2, [r7, #4] + 13931 0010 B968 ldr r1, [r7, #8] + 13932 0012 F868 ldr r0, [r7, #12] + 13933 0014 FFF7FEFF bl I2C_IsErrorOccurred + 13934 0018 0346 mov r3, r0 + 13935 .loc 1 6773 8 discriminator 1 + 13936 001a 002B cmp r3, #0 + 13937 001c 01D0 beq .L684 + ARM GAS /tmp/cc5G5cqz.s page 367 + + +6774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 13938 .loc 1 6775 14 + 13939 001e 0123 movs r3, #1 + 13940 0020 31E0 b .L685 + 13941 .L684: +6776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6777:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check for the Timeout */ +6779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (Timeout != HAL_MAX_DELAY) + 13942 .loc 1 6779 8 + 13943 0022 BB68 ldr r3, [r7, #8] + 13944 0024 B3F1FF3F cmp r3, #-1 + 13945 0028 25D0 beq .L686 +6780:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + 13946 .loc 1 6781 13 + 13947 002a FFF7FEFF bl HAL_GetTick + 13948 002e 0246 mov r2, r0 + 13949 .loc 1 6781 27 discriminator 1 + 13950 0030 7B68 ldr r3, [r7, #4] + 13951 0032 D31A subs r3, r2, r3 + 13952 .loc 1 6781 10 discriminator 1 + 13953 0034 BA68 ldr r2, [r7, #8] + 13954 0036 9A42 cmp r2, r3 + 13955 0038 02D3 bcc .L687 + 13956 .loc 1 6781 51 discriminator 1 + 13957 003a BB68 ldr r3, [r7, #8] + 13958 003c 002B cmp r3, #0 + 13959 003e 1AD1 bne .L686 + 13960 .L687: +6782:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)) + 13961 .loc 1 6783 14 + 13962 0040 FB68 ldr r3, [r7, #12] + 13963 0042 1B68 ldr r3, [r3] + 13964 0044 9B69 ldr r3, [r3, #24] + 13965 0046 03F00203 and r3, r3, #2 + 13966 .loc 1 6783 12 + 13967 004a 022B cmp r3, #2 + 13968 004c 13D0 beq .L686 +6784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + 13969 .loc 1 6785 15 + 13970 004e FB68 ldr r3, [r7, #12] + 13971 0050 5B6C ldr r3, [r3, #68] + 13972 .loc 1 6785 27 + 13973 0052 43F02002 orr r2, r3, #32 + 13974 0056 FB68 ldr r3, [r7, #12] + 13975 0058 5A64 str r2, [r3, #68] +6786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 13976 .loc 1 6786 23 + 13977 005a FB68 ldr r3, [r7, #12] + 13978 005c 2022 movs r2, #32 + 13979 005e 83F84120 strb r2, [r3, #65] +6787:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 13980 .loc 1 6787 22 + ARM GAS /tmp/cc5G5cqz.s page 368 + + + 13981 0062 FB68 ldr r3, [r7, #12] + 13982 0064 0022 movs r2, #0 + 13983 0066 83F84220 strb r2, [r3, #66] +6788:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +6790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 13984 .loc 1 6790 11 + 13985 006a FB68 ldr r3, [r7, #12] + 13986 006c 0022 movs r2, #0 + 13987 006e 83F84020 strb r2, [r3, #64] +6791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 13988 .loc 1 6792 18 + 13989 0072 0123 movs r3, #1 + 13990 0074 07E0 b .L685 + 13991 .L686: +6770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 13992 .loc 1 6770 10 + 13993 0076 FB68 ldr r3, [r7, #12] + 13994 0078 1B68 ldr r3, [r3] + 13995 007a 9B69 ldr r3, [r3, #24] + 13996 007c 03F00203 and r3, r3, #2 +6770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 13997 .loc 1 6770 50 + 13998 0080 022B cmp r3, #2 + 13999 0082 C4D1 bne .L689 +6793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; + 14000 .loc 1 6797 10 + 14001 0084 0023 movs r3, #0 + 14002 .L685: +6798:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 14003 .loc 1 6798 1 + 14004 0086 1846 mov r0, r3 + 14005 0088 1037 adds r7, r7, #16 + 14006 .cfi_def_cfa_offset 8 + 14007 008a BD46 mov sp, r7 + 14008 .cfi_def_cfa_register 13 + 14009 @ sp needed + 14010 008c 80BD pop {r7, pc} + 14011 .cfi_endproc + 14012 .LFE203: + 14014 .section .text.I2C_WaitOnSTOPFlagUntilTimeout,"ax",%progbits + 14015 .align 1 + 14016 .syntax unified + 14017 .thumb + 14018 .thumb_func + 14020 I2C_WaitOnSTOPFlagUntilTimeout: + 14021 .LFB204: +6799:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +6801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. +6802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +6803:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. + ARM GAS /tmp/cc5G5cqz.s page 369 + + +6804:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Timeout Timeout duration +6805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Tickstart Tick start value +6806:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +6807:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +6808:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, +6809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t Tickstart) +6810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 14022 .loc 1 6810 1 + 14023 .cfi_startproc + 14024 @ args = 0, pretend = 0, frame = 16 + 14025 @ frame_needed = 1, uses_anonymous_args = 0 + 14026 0000 80B5 push {r7, lr} + 14027 .cfi_def_cfa_offset 8 + 14028 .cfi_offset 7, -8 + 14029 .cfi_offset 14, -4 + 14030 0002 84B0 sub sp, sp, #16 + 14031 .cfi_def_cfa_offset 24 + 14032 0004 00AF add r7, sp, #0 + 14033 .cfi_def_cfa_register 7 + 14034 0006 F860 str r0, [r7, #12] + 14035 0008 B960 str r1, [r7, #8] + 14036 000a 7A60 str r2, [r7, #4] +6811:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + 14037 .loc 1 6811 9 + 14038 000c 2FE0 b .L691 + 14039 .L696: +6812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check if an error is detected */ +6814:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) + 14040 .loc 1 6814 9 + 14041 000e 7A68 ldr r2, [r7, #4] + 14042 0010 B968 ldr r1, [r7, #8] + 14043 0012 F868 ldr r0, [r7, #12] + 14044 0014 FFF7FEFF bl I2C_IsErrorOccurred + 14045 0018 0346 mov r3, r0 + 14046 .loc 1 6814 8 discriminator 1 + 14047 001a 002B cmp r3, #0 + 14048 001c 01D0 beq .L692 +6815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 14049 .loc 1 6816 14 + 14050 001e 0123 movs r3, #1 + 14051 0020 2DE0 b .L693 + 14052 .L692: +6817:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6818:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check for the Timeout */ +6820:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + 14053 .loc 1 6820 11 + 14054 0022 FFF7FEFF bl HAL_GetTick + 14055 0026 0246 mov r2, r0 + 14056 .loc 1 6820 25 discriminator 1 + 14057 0028 7B68 ldr r3, [r7, #4] + 14058 002a D31A subs r3, r2, r3 + 14059 .loc 1 6820 8 discriminator 1 + 14060 002c BA68 ldr r2, [r7, #8] + 14061 002e 9A42 cmp r2, r3 + ARM GAS /tmp/cc5G5cqz.s page 370 + + + 14062 0030 02D3 bcc .L694 + 14063 .loc 1 6820 49 discriminator 1 + 14064 0032 BB68 ldr r3, [r7, #8] + 14065 0034 002B cmp r3, #0 + 14066 0036 1AD1 bne .L691 + 14067 .L694: +6821:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)) + 14068 .loc 1 6822 12 + 14069 0038 FB68 ldr r3, [r7, #12] + 14070 003a 1B68 ldr r3, [r3] + 14071 003c 9B69 ldr r3, [r3, #24] + 14072 003e 03F02003 and r3, r3, #32 + 14073 .loc 1 6822 10 + 14074 0042 202B cmp r3, #32 + 14075 0044 13D0 beq .L691 +6823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + 14076 .loc 1 6824 13 + 14077 0046 FB68 ldr r3, [r7, #12] + 14078 0048 5B6C ldr r3, [r3, #68] + 14079 .loc 1 6824 25 + 14080 004a 43F02002 orr r2, r3, #32 + 14081 004e FB68 ldr r3, [r7, #12] + 14082 0050 5A64 str r2, [r3, #68] +6825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 14083 .loc 1 6825 21 + 14084 0052 FB68 ldr r3, [r7, #12] + 14085 0054 2022 movs r2, #32 + 14086 0056 83F84120 strb r2, [r3, #65] +6826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 14087 .loc 1 6826 20 + 14088 005a FB68 ldr r3, [r7, #12] + 14089 005c 0022 movs r2, #0 + 14090 005e 83F84220 strb r2, [r3, #66] +6827:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6828:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +6829:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 14091 .loc 1 6829 9 + 14092 0062 FB68 ldr r3, [r7, #12] + 14093 0064 0022 movs r2, #0 + 14094 0066 83F84020 strb r2, [r3, #64] +6830:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 14095 .loc 1 6831 16 + 14096 006a 0123 movs r3, #1 + 14097 006c 07E0 b .L693 + 14098 .L691: +6811:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 14099 .loc 1 6811 10 + 14100 006e FB68 ldr r3, [r7, #12] + 14101 0070 1B68 ldr r3, [r3] + 14102 0072 9B69 ldr r3, [r3, #24] + 14103 0074 03F02003 and r3, r3, #32 +6811:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 14104 .loc 1 6811 51 + 14105 0078 202B cmp r3, #32 + ARM GAS /tmp/cc5G5cqz.s page 371 + + + 14106 007a C8D1 bne .L696 +6832:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6834:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6835:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; + 14107 .loc 1 6835 10 + 14108 007c 0023 movs r3, #0 + 14109 .L693: +6836:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 14110 .loc 1 6836 1 + 14111 007e 1846 mov r0, r3 + 14112 0080 1037 adds r7, r7, #16 + 14113 .cfi_def_cfa_offset 8 + 14114 0082 BD46 mov sp, r7 + 14115 .cfi_def_cfa_register 13 + 14116 @ sp needed + 14117 0084 80BD pop {r7, pc} + 14118 .cfi_endproc + 14119 .LFE204: + 14121 .section .text.I2C_WaitOnRXNEFlagUntilTimeout,"ax",%progbits + 14122 .align 1 + 14123 .syntax unified + 14124 .thumb + 14125 .thumb_func + 14127 I2C_WaitOnRXNEFlagUntilTimeout: + 14128 .LFB205: +6837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +6839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. +6840:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +6841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +6842:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Timeout Timeout duration +6843:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Tickstart Tick start value +6844:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +6845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +6846:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, +6847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t Tickstart) +6848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 14129 .loc 1 6848 1 + 14130 .cfi_startproc + 14131 @ args = 0, pretend = 0, frame = 16 + 14132 @ frame_needed = 1, uses_anonymous_args = 0 + 14133 0000 80B5 push {r7, lr} + 14134 .cfi_def_cfa_offset 8 + 14135 .cfi_offset 7, -8 + 14136 .cfi_offset 14, -4 + 14137 0002 84B0 sub sp, sp, #16 + 14138 .cfi_def_cfa_offset 24 + 14139 0004 00AF add r7, sp, #0 + 14140 .cfi_def_cfa_register 7 + 14141 0006 F860 str r0, [r7, #12] + 14142 0008 B960 str r1, [r7, #8] + 14143 000a 7A60 str r2, [r7, #4] +6849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) + 14144 .loc 1 6849 9 + 14145 000c 6BE0 b .L698 + 14146 .L707: + ARM GAS /tmp/cc5G5cqz.s page 372 + + +6850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6851:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check if an error is detected */ +6852:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) + 14147 .loc 1 6852 9 + 14148 000e 7A68 ldr r2, [r7, #4] + 14149 0010 B968 ldr r1, [r7, #8] + 14150 0012 F868 ldr r0, [r7, #12] + 14151 0014 FFF7FEFF bl I2C_IsErrorOccurred + 14152 0018 0346 mov r3, r0 + 14153 .loc 1 6852 8 discriminator 1 + 14154 001a 002B cmp r3, #0 + 14155 001c 01D0 beq .L699 +6853:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 14156 .loc 1 6854 14 + 14157 001e 0123 movs r3, #1 + 14158 0020 69E0 b .L700 + 14159 .L699: +6855:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6856:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6857:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check if a STOPF is detected */ +6858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + 14160 .loc 1 6858 9 + 14161 0022 FB68 ldr r3, [r7, #12] + 14162 0024 1B68 ldr r3, [r3] + 14163 0026 9B69 ldr r3, [r3, #24] + 14164 0028 03F02003 and r3, r3, #32 + 14165 .loc 1 6858 8 + 14166 002c 202B cmp r3, #32 + 14167 002e 38D1 bne .L701 +6859:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check if an RXNE is pending */ +6861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Store Last receive data if any */ +6862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U)) + 14168 .loc 1 6862 12 + 14169 0030 FB68 ldr r3, [r7, #12] + 14170 0032 1B68 ldr r3, [r3] + 14171 0034 9B69 ldr r3, [r3, #24] + 14172 0036 03F00403 and r3, r3, #4 + 14173 .loc 1 6862 10 + 14174 003a 042B cmp r3, #4 + 14175 003c 05D1 bne .L702 + 14176 .loc 1 6862 68 discriminator 1 + 14177 003e FB68 ldr r3, [r7, #12] + 14178 0040 1B8D ldrh r3, [r3, #40] + 14179 .loc 1 6862 60 discriminator 1 + 14180 0042 002B cmp r3, #0 + 14181 0044 01D0 beq .L702 +6863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6864:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Return HAL_OK */ +6865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* The Reading of data from RXDR will be done in caller function */ +6866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; + 14182 .loc 1 6866 16 + 14183 0046 0023 movs r3, #0 + 14184 0048 55E0 b .L700 + 14185 .L702: +6867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/cc5G5cqz.s page 373 + + +6868:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +6869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6870:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + 14186 .loc 1 6870 13 + 14187 004a FB68 ldr r3, [r7, #12] + 14188 004c 1B68 ldr r3, [r3] + 14189 004e 9B69 ldr r3, [r3, #24] + 14190 0050 03F01003 and r3, r3, #16 + 14191 .loc 1 6870 12 + 14192 0054 102B cmp r3, #16 + 14193 0056 07D1 bne .L703 +6871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + 14194 .loc 1 6872 11 + 14195 0058 FB68 ldr r3, [r7, #12] + 14196 005a 1B68 ldr r3, [r3] + 14197 005c 1022 movs r2, #16 + 14198 005e DA61 str r2, [r3, #28] +6873:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_AF; + 14199 .loc 1 6873 27 + 14200 0060 FB68 ldr r3, [r7, #12] + 14201 0062 0422 movs r2, #4 + 14202 0064 5A64 str r2, [r3, #68] + 14203 0066 02E0 b .L704 + 14204 .L703: +6874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6875:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +6876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6877:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + 14205 .loc 1 6877 27 + 14206 0068 FB68 ldr r3, [r7, #12] + 14207 006a 0022 movs r2, #0 + 14208 006c 5A64 str r2, [r3, #68] + 14209 .L704: +6878:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6879:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear STOP Flag */ +6881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + 14210 .loc 1 6881 9 + 14211 006e FB68 ldr r3, [r7, #12] + 14212 0070 1B68 ldr r3, [r3] + 14213 0072 2022 movs r2, #32 + 14214 0074 DA61 str r2, [r3, #28] +6882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear Configuration Register 2 */ +6884:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_RESET_CR2(hi2c); + 14215 .loc 1 6884 9 + 14216 0076 FB68 ldr r3, [r7, #12] + 14217 0078 1B68 ldr r3, [r3] + 14218 007a 5968 ldr r1, [r3, #4] + 14219 007c FB68 ldr r3, [r7, #12] + 14220 007e 1A68 ldr r2, [r3] + 14221 0080 1F4B ldr r3, .L708 + 14222 0082 0B40 ands r3, r3, r1 + 14223 0084 5360 str r3, [r2, #4] +6885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + ARM GAS /tmp/cc5G5cqz.s page 374 + + + 14224 .loc 1 6886 21 + 14225 0086 FB68 ldr r3, [r7, #12] + 14226 0088 2022 movs r2, #32 + 14227 008a 83F84120 strb r2, [r3, #65] +6887:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 14228 .loc 1 6887 20 + 14229 008e FB68 ldr r3, [r7, #12] + 14230 0090 0022 movs r2, #0 + 14231 0092 83F84220 strb r2, [r3, #66] +6888:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6889:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +6890:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 14232 .loc 1 6890 9 + 14233 0096 FB68 ldr r3, [r7, #12] + 14234 0098 0022 movs r2, #0 + 14235 009a 83F84020 strb r2, [r3, #64] +6891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6892:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 14236 .loc 1 6892 16 + 14237 009e 0123 movs r3, #1 + 14238 00a0 29E0 b .L700 + 14239 .L701: +6893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6894:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6895:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check for the Timeout */ +6897:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + 14240 .loc 1 6897 11 + 14241 00a2 FFF7FEFF bl HAL_GetTick + 14242 00a6 0246 mov r2, r0 + 14243 .loc 1 6897 25 discriminator 1 + 14244 00a8 7B68 ldr r3, [r7, #4] + 14245 00aa D31A subs r3, r2, r3 + 14246 .loc 1 6897 8 discriminator 1 + 14247 00ac BA68 ldr r2, [r7, #8] + 14248 00ae 9A42 cmp r2, r3 + 14249 00b0 02D3 bcc .L705 + 14250 .loc 1 6897 49 discriminator 1 + 14251 00b2 BB68 ldr r3, [r7, #8] + 14252 00b4 002B cmp r3, #0 + 14253 00b6 16D1 bne .L698 + 14254 .L705: +6898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6899:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)) + 14255 .loc 1 6899 12 + 14256 00b8 FB68 ldr r3, [r7, #12] + 14257 00ba 1B68 ldr r3, [r3] + 14258 00bc 9B69 ldr r3, [r3, #24] + 14259 00be 03F00403 and r3, r3, #4 + 14260 .loc 1 6899 10 + 14261 00c2 042B cmp r3, #4 + 14262 00c4 0FD0 beq .L698 +6900:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + 14263 .loc 1 6901 13 + 14264 00c6 FB68 ldr r3, [r7, #12] + 14265 00c8 5B6C ldr r3, [r3, #68] + ARM GAS /tmp/cc5G5cqz.s page 375 + + + 14266 .loc 1 6901 25 + 14267 00ca 43F02002 orr r2, r3, #32 + 14268 00ce FB68 ldr r3, [r7, #12] + 14269 00d0 5A64 str r2, [r3, #68] +6902:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 14270 .loc 1 6902 21 + 14271 00d2 FB68 ldr r3, [r7, #12] + 14272 00d4 2022 movs r2, #32 + 14273 00d6 83F84120 strb r2, [r3, #65] +6903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6904:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +6905:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 14274 .loc 1 6905 9 + 14275 00da FB68 ldr r3, [r7, #12] + 14276 00dc 0022 movs r2, #0 + 14277 00de 83F84020 strb r2, [r3, #64] +6906:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_ERROR; + 14278 .loc 1 6907 16 + 14279 00e2 0123 movs r3, #1 + 14280 00e4 07E0 b .L700 + 14281 .L698: +6849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 14282 .loc 1 6849 10 + 14283 00e6 FB68 ldr r3, [r7, #12] + 14284 00e8 1B68 ldr r3, [r3] + 14285 00ea 9B69 ldr r3, [r3, #24] + 14286 00ec 03F00403 and r3, r3, #4 +6849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 14287 .loc 1 6849 50 + 14288 00f0 042B cmp r3, #4 + 14289 00f2 8CD1 bne .L707 +6908:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6909:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6911:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return HAL_OK; + 14290 .loc 1 6911 10 + 14291 00f4 0023 movs r3, #0 + 14292 .L700: +6912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 14293 .loc 1 6912 1 + 14294 00f6 1846 mov r0, r3 + 14295 00f8 1037 adds r7, r7, #16 + 14296 .cfi_def_cfa_offset 8 + 14297 00fa BD46 mov sp, r7 + 14298 .cfi_def_cfa_register 13 + 14299 @ sp needed + 14300 00fc 80BD pop {r7, pc} + 14301 .L709: + 14302 00fe 00BF .align 2 + 14303 .L708: + 14304 0100 00E800FE .word -33495040 + 14305 .cfi_endproc + 14306 .LFE205: + 14308 .section .text.I2C_IsErrorOccurred,"ax",%progbits + 14309 .align 1 + 14310 .syntax unified + ARM GAS /tmp/cc5G5cqz.s page 376 + + + 14311 .thumb + 14312 .thumb_func + 14314 I2C_IsErrorOccurred: + 14315 .LFB206: +6913:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6914:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +6915:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief This function handles errors detection during an I2C Communication. +6916:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +6917:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +6918:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Timeout Timeout duration +6919:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Tickstart Tick start value +6920:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval HAL status +6921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +6922:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Ti +6923:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 14316 .loc 1 6923 1 + 14317 .cfi_startproc + 14318 @ args = 0, pretend = 0, frame = 40 + 14319 @ frame_needed = 1, uses_anonymous_args = 0 + 14320 0000 80B5 push {r7, lr} + 14321 .cfi_def_cfa_offset 8 + 14322 .cfi_offset 7, -8 + 14323 .cfi_offset 14, -4 + 14324 0002 8AB0 sub sp, sp, #40 + 14325 .cfi_def_cfa_offset 48 + 14326 0004 00AF add r7, sp, #0 + 14327 .cfi_def_cfa_register 7 + 14328 0006 F860 str r0, [r7, #12] + 14329 0008 B960 str r1, [r7, #8] + 14330 000a 7A60 str r2, [r7, #4] +6924:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_StatusTypeDef status = HAL_OK; + 14331 .loc 1 6924 21 + 14332 000c 0023 movs r3, #0 + 14333 000e 87F82730 strb r3, [r7, #39] +6925:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t itflag = hi2c->Instance->ISR; + 14334 .loc 1 6925 27 + 14335 0012 FB68 ldr r3, [r7, #12] + 14336 0014 1B68 ldr r3, [r3] + 14337 .loc 1 6925 12 + 14338 0016 9B69 ldr r3, [r3, #24] + 14339 0018 BB61 str r3, [r7, #24] +6926:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t error_code = 0; + 14340 .loc 1 6926 12 + 14341 001a 0023 movs r3, #0 + 14342 001c 3B62 str r3, [r7, #32] +6927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tickstart = Tickstart; + 14343 .loc 1 6927 12 + 14344 001e 7B68 ldr r3, [r7, #4] + 14345 0020 FB61 str r3, [r7, #28] +6928:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmp1; +6929:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** HAL_I2C_ModeTypeDef tmp2; +6930:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6931:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF)) + 14346 .loc 1 6931 7 + 14347 0022 BB69 ldr r3, [r7, #24] + 14348 0024 03F01003 and r3, r3, #16 + 14349 .loc 1 6931 6 + ARM GAS /tmp/cc5G5cqz.s page 377 + + + 14350 0028 002B cmp r3, #0 + 14351 002a 68D0 beq .L711 +6932:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear NACKF Flag */ +6934:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + 14352 .loc 1 6934 5 + 14353 002c FB68 ldr r3, [r7, #12] + 14354 002e 1B68 ldr r3, [r3] + 14355 0030 1022 movs r2, #16 + 14356 0032 DA61 str r2, [r3, #28] +6935:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6936:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Wait until STOP Flag is set or timeout occurred */ +6937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* AutoEnd should be initiate after AF */ +6938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK)) + 14357 .loc 1 6938 11 + 14358 0034 49E0 b .L713 + 14359 .L720: +6939:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check for the Timeout */ +6941:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (Timeout != HAL_MAX_DELAY) + 14360 .loc 1 6941 10 + 14361 0036 BB68 ldr r3, [r7, #8] + 14362 0038 B3F1FF3F cmp r3, #-1 + 14363 003c 45D0 beq .L713 +6942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6943:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + 14364 .loc 1 6943 15 + 14365 003e FFF7FEFF bl HAL_GetTick + 14366 0042 0246 mov r2, r0 + 14367 .loc 1 6943 29 discriminator 1 + 14368 0044 FB69 ldr r3, [r7, #28] + 14369 0046 D31A subs r3, r2, r3 + 14370 .loc 1 6943 12 discriminator 1 + 14371 0048 BA68 ldr r2, [r7, #8] + 14372 004a 9A42 cmp r2, r3 + 14373 004c 02D3 bcc .L714 + 14374 .loc 1 6943 53 discriminator 1 + 14375 004e BB68 ldr r3, [r7, #8] + 14376 0050 002B cmp r3, #0 + 14377 0052 3AD1 bne .L713 + 14378 .L714: +6944:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP); + 14379 .loc 1 6945 33 + 14380 0054 FB68 ldr r3, [r7, #12] + 14381 0056 1B68 ldr r3, [r3] + 14382 .loc 1 6945 43 + 14383 0058 5B68 ldr r3, [r3, #4] + 14384 .loc 1 6945 16 + 14385 005a 03F48043 and r3, r3, #16384 + 14386 005e 7B61 str r3, [r7, #20] +6946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmp2 = hi2c->Mode; + 14387 .loc 1 6946 16 + 14388 0060 FB68 ldr r3, [r7, #12] + 14389 0062 93F84230 ldrb r3, [r3, #66] + 14390 0066 FB74 strb r3, [r7, #19] +6947:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** + ARM GAS /tmp/cc5G5cqz.s page 378 + + +6948:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* In case of I2C still busy, try to regenerate a STOP manually */ +6949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \ + 14391 .loc 1 6949 16 + 14392 0068 FB68 ldr r3, [r7, #12] + 14393 006a 1B68 ldr r3, [r3] + 14394 006c 9B69 ldr r3, [r3, #24] + 14395 006e 03F40043 and r3, r3, #32768 + 14396 .loc 1 6949 14 + 14397 0072 B3F5004F cmp r3, #32768 + 14398 0076 21D1 bne .L717 + 14399 .loc 1 6949 66 discriminator 1 + 14400 0078 7B69 ldr r3, [r7, #20] + 14401 007a B3F5804F cmp r3, #16384 + 14402 007e 1DD0 beq .L717 +6950:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (tmp1 != I2C_CR2_STOP) && \ + 14403 .loc 1 6950 38 + 14404 0080 FB7C ldrb r3, [r7, #19] @ zero_extendqisi2 + 14405 0082 202B cmp r3, #32 + 14406 0084 1AD0 beq .L717 +6951:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (tmp2 != HAL_I2C_MODE_SLAVE)) +6952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Generate Stop */ +6954:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Instance->CR2 |= I2C_CR2_STOP; + 14407 .loc 1 6954 17 + 14408 0086 FB68 ldr r3, [r7, #12] + 14409 0088 1B68 ldr r3, [r3] + 14410 .loc 1 6954 27 + 14411 008a 5A68 ldr r2, [r3, #4] + 14412 .loc 1 6954 17 + 14413 008c FB68 ldr r3, [r7, #12] + 14414 008e 1B68 ldr r3, [r3] + 14415 .loc 1 6954 33 + 14416 0090 42F48042 orr r2, r2, #16384 + 14417 0094 5A60 str r2, [r3, #4] +6955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6956:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Update Tick with new reference */ +6957:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tickstart = HAL_GetTick(); + 14418 .loc 1 6957 25 + 14419 0096 FFF7FEFF bl HAL_GetTick + 14420 009a F861 str r0, [r7, #28] +6958:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6960:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + 14421 .loc 1 6960 17 + 14422 009c 0EE0 b .L717 + 14423 .L718: +6961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check for the Timeout */ +6963:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF) + 14424 .loc 1 6963 18 + 14425 009e FFF7FEFF bl HAL_GetTick + 14426 00a2 0246 mov r2, r0 + 14427 .loc 1 6963 32 discriminator 1 + 14428 00a4 FB69 ldr r3, [r7, #28] + 14429 00a6 D31A subs r3, r2, r3 + 14430 .loc 1 6963 16 discriminator 1 + 14431 00a8 192B cmp r3, #25 + ARM GAS /tmp/cc5G5cqz.s page 379 + + + 14432 00aa 07D9 bls .L717 +6964:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6965:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** error_code |= HAL_I2C_ERROR_TIMEOUT; + 14433 .loc 1 6965 26 + 14434 00ac 3B6A ldr r3, [r7, #32] + 14435 00ae 43F02003 orr r3, r3, #32 + 14436 00b2 3B62 str r3, [r7, #32] +6966:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6967:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** status = HAL_ERROR; + 14437 .loc 1 6967 22 + 14438 00b4 0123 movs r3, #1 + 14439 00b6 87F82730 strb r3, [r7, #39] +6968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6969:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** break; + 14440 .loc 1 6969 15 + 14441 00ba 06E0 b .L713 + 14442 .L717: +6960:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 14443 .loc 1 6960 18 + 14444 00bc FB68 ldr r3, [r7, #12] + 14445 00be 1B68 ldr r3, [r3] + 14446 00c0 9B69 ldr r3, [r3, #24] + 14447 00c2 03F02003 and r3, r3, #32 +6960:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 14448 .loc 1 6960 59 + 14449 00c6 202B cmp r3, #32 + 14450 00c8 E9D1 bne .L718 + 14451 .L713: +6938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 14452 .loc 1 6938 13 + 14453 00ca FB68 ldr r3, [r7, #12] + 14454 00cc 1B68 ldr r3, [r3] + 14455 00ce 9B69 ldr r3, [r3, #24] + 14456 00d0 03F02003 and r3, r3, #32 +6938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 14457 .loc 1 6938 64 + 14458 00d4 202B cmp r3, #32 + 14459 00d6 03D0 beq .L719 +6938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 14460 .loc 1 6938 64 is_stmt 0 discriminator 1 + 14461 00d8 97F82730 ldrb r3, [r7, #39] @ zero_extendqisi2 + 14462 00dc 002B cmp r3, #0 + 14463 00de AAD0 beq .L720 + 14464 .L719: +6970:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6971:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6972:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6973:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6974:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6975:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6976:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* In case STOP Flag is detected, clear it */ +6977:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (status == HAL_OK) + 14465 .loc 1 6977 8 is_stmt 1 + 14466 00e0 97F82730 ldrb r3, [r7, #39] @ zero_extendqisi2 + 14467 00e4 002B cmp r3, #0 + 14468 00e6 03D1 bne .L721 +6978:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + ARM GAS /tmp/cc5G5cqz.s page 380 + + +6979:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear STOP Flag */ +6980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + 14469 .loc 1 6980 7 + 14470 00e8 FB68 ldr r3, [r7, #12] + 14471 00ea 1B68 ldr r3, [r3] + 14472 00ec 2022 movs r2, #32 + 14473 00ee DA61 str r2, [r3, #28] + 14474 .L721: +6981:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6982:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6983:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** error_code |= HAL_I2C_ERROR_AF; + 14475 .loc 1 6983 16 + 14476 00f0 3B6A ldr r3, [r7, #32] + 14477 00f2 43F00403 orr r3, r3, #4 + 14478 00f6 3B62 str r3, [r7, #32] +6984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6985:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** status = HAL_ERROR; + 14479 .loc 1 6985 12 + 14480 00f8 0123 movs r3, #1 + 14481 00fa 87F82730 strb r3, [r7, #39] + 14482 .L711: +6986:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +6987:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6988:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Refresh Content of Status register */ +6989:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** itflag = hi2c->Instance->ISR; + 14483 .loc 1 6989 16 + 14484 00fe FB68 ldr r3, [r7, #12] + 14485 0100 1B68 ldr r3, [r3] + 14486 .loc 1 6989 10 + 14487 0102 9B69 ldr r3, [r3, #24] + 14488 0104 BB61 str r3, [r7, #24] +6990:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6991:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Then verify if an additional errors occurs */ +6992:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check if a Bus error occurred */ +6993:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR)) + 14489 .loc 1 6993 7 + 14490 0106 BB69 ldr r3, [r7, #24] + 14491 0108 03F48073 and r3, r3, #256 + 14492 .loc 1 6993 6 + 14493 010c 002B cmp r3, #0 + 14494 010e 0BD0 beq .L722 +6994:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +6995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** error_code |= HAL_I2C_ERROR_BERR; + 14495 .loc 1 6995 16 + 14496 0110 3B6A ldr r3, [r7, #32] + 14497 0112 43F00103 orr r3, r3, #1 + 14498 0116 3B62 str r3, [r7, #32] +6996:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +6997:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear BERR flag */ +6998:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); + 14499 .loc 1 6998 5 + 14500 0118 FB68 ldr r3, [r7, #12] + 14501 011a 1B68 ldr r3, [r3] + 14502 011c 4FF48072 mov r2, #256 + 14503 0120 DA61 str r2, [r3, #28] +6999:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +7000:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** status = HAL_ERROR; + ARM GAS /tmp/cc5G5cqz.s page 381 + + + 14504 .loc 1 7000 12 + 14505 0122 0123 movs r3, #1 + 14506 0124 87F82730 strb r3, [r7, #39] + 14507 .L722: +7001:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +7002:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +7003:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check if an Over-Run/Under-Run error occurred */ +7004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR)) + 14508 .loc 1 7004 7 + 14509 0128 BB69 ldr r3, [r7, #24] + 14510 012a 03F48063 and r3, r3, #1024 + 14511 .loc 1 7004 6 + 14512 012e 002B cmp r3, #0 + 14513 0130 0BD0 beq .L723 +7005:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +7006:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** error_code |= HAL_I2C_ERROR_OVR; + 14514 .loc 1 7006 16 + 14515 0132 3B6A ldr r3, [r7, #32] + 14516 0134 43F00803 orr r3, r3, #8 + 14517 0138 3B62 str r3, [r7, #32] +7007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +7008:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear OVR flag */ +7009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); + 14518 .loc 1 7009 5 + 14519 013a FB68 ldr r3, [r7, #12] + 14520 013c 1B68 ldr r3, [r3] + 14521 013e 4FF48062 mov r2, #1024 + 14522 0142 DA61 str r2, [r3, #28] +7010:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +7011:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** status = HAL_ERROR; + 14523 .loc 1 7011 12 + 14524 0144 0123 movs r3, #1 + 14525 0146 87F82730 strb r3, [r7, #39] + 14526 .L723: +7012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +7013:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +7014:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check if an Arbitration Loss error occurred */ +7015:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO)) + 14527 .loc 1 7015 7 + 14528 014a BB69 ldr r3, [r7, #24] + 14529 014c 03F40073 and r3, r3, #512 + 14530 .loc 1 7015 6 + 14531 0150 002B cmp r3, #0 + 14532 0152 0BD0 beq .L724 +7016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +7017:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** error_code |= HAL_I2C_ERROR_ARLO; + 14533 .loc 1 7017 16 + 14534 0154 3B6A ldr r3, [r7, #32] + 14535 0156 43F00203 orr r3, r3, #2 + 14536 015a 3B62 str r3, [r7, #32] +7018:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +7019:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear ARLO flag */ +7020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); + 14537 .loc 1 7020 5 + 14538 015c FB68 ldr r3, [r7, #12] + 14539 015e 1B68 ldr r3, [r3] + 14540 0160 4FF40072 mov r2, #512 + ARM GAS /tmp/cc5G5cqz.s page 382 + + + 14541 0164 DA61 str r2, [r3, #28] +7021:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +7022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** status = HAL_ERROR; + 14542 .loc 1 7022 12 + 14543 0166 0123 movs r3, #1 + 14544 0168 87F82730 strb r3, [r7, #39] + 14545 .L724: +7023:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +7024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +7025:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (status != HAL_OK) + 14546 .loc 1 7025 6 + 14547 016c 97F82730 ldrb r3, [r7, #39] @ zero_extendqisi2 + 14548 0170 002B cmp r3, #0 + 14549 0172 1CD0 beq .L725 +7026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +7027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Flush TX register */ +7028:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_Flush_TXDR(hi2c); + 14550 .loc 1 7028 5 + 14551 0174 F868 ldr r0, [r7, #12] + 14552 0176 FFF7FEFF bl I2C_Flush_TXDR +7029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +7030:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Clear Configuration Register 2 */ +7031:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_RESET_CR2(hi2c); + 14553 .loc 1 7031 5 + 14554 017a FB68 ldr r3, [r7, #12] + 14555 017c 1B68 ldr r3, [r3] + 14556 017e 5968 ldr r1, [r3, #4] + 14557 0180 FB68 ldr r3, [r7, #12] + 14558 0182 1A68 ldr r2, [r3] + 14559 0184 0D4B ldr r3, .L727 + 14560 0186 0B40 ands r3, r3, r1 + 14561 0188 5360 str r3, [r2, #4] +7032:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +7033:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->ErrorCode |= error_code; + 14562 .loc 1 7033 9 + 14563 018a FB68 ldr r3, [r7, #12] + 14564 018c 5A6C ldr r2, [r3, #68] + 14565 .loc 1 7033 21 + 14566 018e 3B6A ldr r3, [r7, #32] + 14567 0190 1A43 orrs r2, r2, r3 + 14568 0192 FB68 ldr r3, [r7, #12] + 14569 0194 5A64 str r2, [r3, #68] +7034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->State = HAL_I2C_STATE_READY; + 14570 .loc 1 7034 17 + 14571 0196 FB68 ldr r3, [r7, #12] + 14572 0198 2022 movs r2, #32 + 14573 019a 83F84120 strb r2, [r3, #65] +7035:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->Mode = HAL_I2C_MODE_NONE; + 14574 .loc 1 7035 16 + 14575 019e FB68 ldr r3, [r7, #12] + 14576 01a0 0022 movs r2, #0 + 14577 01a2 83F84220 strb r2, [r3, #66] +7036:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +7037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Process Unlocked */ +7038:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_UNLOCK(hi2c); + 14578 .loc 1 7038 5 + 14579 01a6 FB68 ldr r3, [r7, #12] + ARM GAS /tmp/cc5G5cqz.s page 383 + + + 14580 01a8 0022 movs r2, #0 + 14581 01aa 83F84020 strb r2, [r3, #64] + 14582 .L725: +7039:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +7040:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +7041:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** return status; + 14583 .loc 1 7041 10 + 14584 01ae 97F82730 ldrb r3, [r7, #39] @ zero_extendqisi2 +7042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 14585 .loc 1 7042 1 + 14586 01b2 1846 mov r0, r3 + 14587 01b4 2837 adds r7, r7, #40 + 14588 .cfi_def_cfa_offset 8 + 14589 01b6 BD46 mov sp, r7 + 14590 .cfi_def_cfa_register 13 + 14591 @ sp needed + 14592 01b8 80BD pop {r7, pc} + 14593 .L728: + 14594 01ba 00BF .align 2 + 14595 .L727: + 14596 01bc 00E800FE .word -33495040 + 14597 .cfi_endproc + 14598 .LFE206: + 14600 .section .text.I2C_TransferConfig,"ax",%progbits + 14601 .align 1 + 14602 .syntax unified + 14603 .thumb + 14604 .thumb_func + 14606 I2C_TransferConfig: + 14607 .LFB207: +7043:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +7044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +7045:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag ar +7046:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c I2C handle. +7047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param DevAddress Specifies the slave address to be programmed. +7048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Size Specifies the number of bytes to be programmed. +7049:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * This parameter must be a value between 0 and 255. +7050:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Mode New state of the I2C START condition generation. +7051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * This parameter can be one of the following values: +7052:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref I2C_RELOAD_MODE Enable Reload mode . +7053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode. +7054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref I2C_SOFTEND_MODE Enable Software end mode. +7055:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param Request New state of the I2C START condition generation. +7056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * This parameter can be one of the following values: +7057:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition. +7058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0). +7059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request. +7060:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request. +7061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +7062:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +7063:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t +7064:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t Request) +7065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 14608 .loc 1 7065 1 + 14609 .cfi_startproc + 14610 @ args = 4, pretend = 0, frame = 24 + 14611 @ frame_needed = 1, uses_anonymous_args = 0 + ARM GAS /tmp/cc5G5cqz.s page 384 + + + 14612 @ link register save eliminated. + 14613 0000 80B4 push {r7} + 14614 .cfi_def_cfa_offset 4 + 14615 .cfi_offset 7, -4 + 14616 0002 87B0 sub sp, sp, #28 + 14617 .cfi_def_cfa_offset 32 + 14618 0004 00AF add r7, sp, #0 + 14619 .cfi_def_cfa_register 7 + 14620 0006 F860 str r0, [r7, #12] + 14621 0008 7B60 str r3, [r7, #4] + 14622 000a 0B46 mov r3, r1 @ movhi + 14623 000c 7B81 strh r3, [r7, #10] @ movhi + 14624 000e 1346 mov r3, r2 + 14625 0010 7B72 strb r3, [r7, #9] +7066:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Check the parameters */ +7067:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); +7068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_TRANSFER_MODE(Mode)); +7069:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** assert_param(IS_TRANSFER_REQUEST(Request)); +7070:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +7071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Declaration of tmp to prevent undefined behavior of volatile usage */ +7072:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ + 14626 .loc 1 7072 52 + 14627 0012 7B89 ldrh r3, [r7, #10] + 14628 0014 C3F30902 ubfx r2, r3, #0, #10 +7073:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + 14629 .loc 1 7073 32 + 14630 0018 7B7A ldrb r3, [r7, #9] @ zero_extendqisi2 + 14631 .loc 1 7073 47 + 14632 001a 1B04 lsls r3, r3, #16 + 14633 .loc 1 7073 70 + 14634 001c 03F47F03 and r3, r3, #16711680 +7072:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + 14635 .loc 1 7072 68 + 14636 0020 1A43 orrs r2, r2, r3 + 14637 .loc 1 7073 88 + 14638 0022 7B68 ldr r3, [r7, #4] + 14639 0024 1A43 orrs r2, r2, r3 +7072:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + 14640 .loc 1 7072 19 + 14641 0026 3B6A ldr r3, [r7, #32] + 14642 0028 1343 orrs r3, r3, r2 +7072:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + 14643 .loc 1 7072 12 + 14644 002a 23F00043 bic r3, r3, #-2147483648 + 14645 002e 7B61 str r3, [r7, #20] +7074:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); +7075:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +7076:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* update CR2 register */ +7077:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** MODIFY_REG(hi2c->Instance->CR2, \ + 14646 .loc 1 7077 3 + 14647 0030 FB68 ldr r3, [r7, #12] + 14648 0032 1B68 ldr r3, [r3] + 14649 0034 5A68 ldr r2, [r3, #4] + 14650 0036 3B6A ldr r3, [r7, #32] + 14651 0038 5B0D lsrs r3, r3, #21 + 14652 003a 03F48061 and r1, r3, #1024 + 14653 003e 084B ldr r3, .L730 + ARM GAS /tmp/cc5G5cqz.s page 385 + + + 14654 0040 0B43 orrs r3, r3, r1 + 14655 0042 DB43 mvns r3, r3 + 14656 0044 02EA0301 and r1, r2, r3 + 14657 0048 FB68 ldr r3, [r7, #12] + 14658 004a 1B68 ldr r3, [r3] + 14659 004c 7A69 ldr r2, [r7, #20] + 14660 004e 0A43 orrs r2, r2, r1 + 14661 0050 5A60 str r2, [r3, #4] +7078:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \ +7079:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \ +7080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** I2C_CR2_START | I2C_CR2_STOP)), tmp); +7081:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 14662 .loc 1 7081 1 + 14663 0052 00BF nop + 14664 0054 1C37 adds r7, r7, #28 + 14665 .cfi_def_cfa_offset 4 + 14666 0056 BD46 mov sp, r7 + 14667 .cfi_def_cfa_register 13 + 14668 @ sp needed + 14669 0058 5DF8047B ldr r7, [sp], #4 + 14670 .cfi_restore 7 + 14671 .cfi_def_cfa_offset 0 + 14672 005c 7047 bx lr + 14673 .L731: + 14674 005e 00BF .align 2 + 14675 .L730: + 14676 0060 FF63FF03 .word 67068927 + 14677 .cfi_endproc + 14678 .LFE207: + 14680 .section .text.I2C_Enable_IRQ,"ax",%progbits + 14681 .align 1 + 14682 .syntax unified + 14683 .thumb + 14684 .thumb_func + 14686 I2C_Enable_IRQ: + 14687 .LFB208: +7082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +7083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +7084:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Manage the enabling of Interrupts. +7085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +7086:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +7087:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. +7088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +7089:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +7090:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +7091:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 14688 .loc 1 7091 1 + 14689 .cfi_startproc + 14690 @ args = 0, pretend = 0, frame = 16 + 14691 @ frame_needed = 1, uses_anonymous_args = 0 + 14692 @ link register save eliminated. + 14693 0000 80B4 push {r7} + 14694 .cfi_def_cfa_offset 4 + 14695 .cfi_offset 7, -4 + 14696 0002 85B0 sub sp, sp, #20 + 14697 .cfi_def_cfa_offset 24 + 14698 0004 00AF add r7, sp, #0 + ARM GAS /tmp/cc5G5cqz.s page 386 + + + 14699 .cfi_def_cfa_register 7 + 14700 0006 7860 str r0, [r7, #4] + 14701 0008 0B46 mov r3, r1 + 14702 000a 7B80 strh r3, [r7, #2] @ movhi +7092:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmpisr = 0U; + 14703 .loc 1 7092 12 + 14704 000c 0023 movs r3, #0 + 14705 000e FB60 str r3, [r7, #12] +7093:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +7094:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->XferISR != I2C_Master_ISR_DMA) && \ + 14706 .loc 1 7094 12 + 14707 0010 7B68 ldr r3, [r7, #4] + 14708 0012 5B6B ldr r3, [r3, #52] + 14709 .loc 1 7094 6 + 14710 0014 3B4A ldr r2, .L745 + 14711 0016 9342 cmp r3, r2 + 14712 0018 32D0 beq .L733 +7095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (hi2c->XferISR != I2C_Slave_ISR_DMA) && \ + 14713 .loc 1 7095 12 + 14714 001a 7B68 ldr r3, [r7, #4] + 14715 001c 5B6B ldr r3, [r3, #52] +7094:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (hi2c->XferISR != I2C_Slave_ISR_DMA) && \ + 14716 .loc 1 7094 45 discriminator 1 + 14717 001e 3A4A ldr r2, .L745+4 + 14718 0020 9342 cmp r3, r2 + 14719 0022 2DD0 beq .L733 +7096:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (hi2c->XferISR != I2C_Mem_ISR_DMA)) + 14720 .loc 1 7096 12 + 14721 0024 7B68 ldr r3, [r7, #4] + 14722 0026 5B6B ldr r3, [r3, #52] +7095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** (hi2c->XferISR != I2C_Slave_ISR_DMA) && \ + 14723 .loc 1 7095 44 + 14724 0028 384A ldr r2, .L745+8 + 14725 002a 9342 cmp r3, r2 + 14726 002c 28D0 beq .L733 +7097:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +7098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + 14727 .loc 1 7098 49 + 14728 002e B7F90230 ldrsh r3, [r7, #2] + 14729 .loc 1 7098 8 + 14730 0032 002B cmp r3, #0 + 14731 0034 03DA bge .L734 +7099:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +7100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR, STOP, NACK and ADDR interrupts */ +7101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + 14732 .loc 1 7101 14 + 14733 0036 FB68 ldr r3, [r7, #12] + 14734 0038 43F0B803 orr r3, r3, #184 + 14735 003c FB60 str r3, [r7, #12] + 14736 .L734: +7102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +7103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +7104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + 14737 .loc 1 7104 27 + 14738 003e 7B88 ldrh r3, [r7, #2] + 14739 0040 03F00103 and r3, r3, #1 + 14740 .loc 1 7104 8 + ARM GAS /tmp/cc5G5cqz.s page 387 + + + 14741 0044 002B cmp r3, #0 + 14742 0046 03D0 beq .L735 +7105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +7106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK and RXI interrupts */ +7107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; + 14743 .loc 1 7107 14 + 14744 0048 FB68 ldr r3, [r7, #12] + 14745 004a 43F0F203 orr r3, r3, #242 + 14746 004e FB60 str r3, [r7, #12] + 14747 .L735: +7108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +7109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +7110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + 14748 .loc 1 7110 27 + 14749 0050 7B88 ldrh r3, [r7, #2] + 14750 0052 03F00203 and r3, r3, #2 + 14751 .loc 1 7110 8 + 14752 0056 002B cmp r3, #0 + 14753 0058 03D0 beq .L736 +7111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +7112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK and TXI interrupts */ +7113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; + 14754 .loc 1 7113 14 + 14755 005a FB68 ldr r3, [r7, #12] + 14756 005c 43F0F403 orr r3, r3, #244 + 14757 0060 FB60 str r3, [r7, #12] + 14758 .L736: +7114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +7115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +7116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (InterruptRequest == I2C_XFER_ERROR_IT) + 14759 .loc 1 7116 8 + 14760 0062 7B88 ldrh r3, [r7, #2] + 14761 0064 102B cmp r3, #16 + 14762 0066 03D1 bne .L737 +7117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +7118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR and NACK interrupts */ +7119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + 14763 .loc 1 7119 14 + 14764 0068 FB68 ldr r3, [r7, #12] + 14765 006a 43F09003 orr r3, r3, #144 + 14766 006e FB60 str r3, [r7, #12] + 14767 .L737: +7120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +7121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +7122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (InterruptRequest == I2C_XFER_CPLT_IT) + 14768 .loc 1 7122 8 + 14769 0070 7B88 ldrh r3, [r7, #2] + 14770 0072 202B cmp r3, #32 + 14771 0074 38D1 bne .L739 +7123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +7124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable STOP interrupts */ +7125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmpisr |= I2C_IT_STOPI; + 14772 .loc 1 7125 14 + 14773 0076 FB68 ldr r3, [r7, #12] + 14774 0078 43F02003 orr r3, r3, #32 + 14775 007c FB60 str r3, [r7, #12] +7122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + ARM GAS /tmp/cc5G5cqz.s page 388 + + + 14776 .loc 1 7122 8 + 14777 007e 33E0 b .L739 + 14778 .L733: +7126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +7127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +7128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +7129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +7130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +7131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + 14779 .loc 1 7131 49 + 14780 0080 B7F90230 ldrsh r3, [r7, #2] + 14781 .loc 1 7131 8 + 14782 0084 002B cmp r3, #0 + 14783 0086 03DA bge .L740 +7132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +7133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR, STOP, NACK and ADDR interrupts */ +7134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + 14784 .loc 1 7134 14 + 14785 0088 FB68 ldr r3, [r7, #12] + 14786 008a 43F0B803 orr r3, r3, #184 + 14787 008e FB60 str r3, [r7, #12] + 14788 .L740: +7135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +7136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +7137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + 14789 .loc 1 7137 27 + 14790 0090 7B88 ldrh r3, [r7, #2] + 14791 0092 03F00103 and r3, r3, #1 + 14792 .loc 1 7137 8 + 14793 0096 002B cmp r3, #0 + 14794 0098 03D0 beq .L741 +7138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +7139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK and RXI interrupts */ +7140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; + 14795 .loc 1 7140 14 + 14796 009a FB68 ldr r3, [r7, #12] + 14797 009c 43F0F203 orr r3, r3, #242 + 14798 00a0 FB60 str r3, [r7, #12] + 14799 .L741: +7141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +7142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +7143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + 14800 .loc 1 7143 27 + 14801 00a2 7B88 ldrh r3, [r7, #2] + 14802 00a4 03F00203 and r3, r3, #2 + 14803 .loc 1 7143 8 + 14804 00a8 002B cmp r3, #0 + 14805 00aa 03D0 beq .L742 +7144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +7145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR, TC, STOP, NACK and TXI interrupts */ +7146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; + 14806 .loc 1 7146 14 + 14807 00ac FB68 ldr r3, [r7, #12] + 14808 00ae 43F0F403 orr r3, r3, #244 + 14809 00b2 FB60 str r3, [r7, #12] + 14810 .L742: +7147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/cc5G5cqz.s page 389 + + +7148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +7149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (InterruptRequest == I2C_XFER_ERROR_IT) + 14811 .loc 1 7149 8 + 14812 00b4 7B88 ldrh r3, [r7, #2] + 14813 00b6 102B cmp r3, #16 + 14814 00b8 03D1 bne .L743 +7150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +7151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR and NACK interrupts */ +7152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + 14815 .loc 1 7152 14 + 14816 00ba FB68 ldr r3, [r7, #12] + 14817 00bc 43F09003 orr r3, r3, #144 + 14818 00c0 FB60 str r3, [r7, #12] + 14819 .L743: +7153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +7154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +7155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (InterruptRequest == I2C_XFER_CPLT_IT) + 14820 .loc 1 7155 8 + 14821 00c2 7B88 ldrh r3, [r7, #2] + 14822 00c4 202B cmp r3, #32 + 14823 00c6 03D1 bne .L744 +7156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +7157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable STOP interrupts */ +7158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI); + 14824 .loc 1 7158 14 + 14825 00c8 FB68 ldr r3, [r7, #12] + 14826 00ca 43F06003 orr r3, r3, #96 + 14827 00ce FB60 str r3, [r7, #12] + 14828 .L744: +7159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +7160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +7161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((hi2c->XferISR != I2C_Mem_ISR_DMA) && (InterruptRequest == I2C_XFER_RELOAD_IT)) + 14829 .loc 1 7161 14 + 14830 00d0 7B68 ldr r3, [r7, #4] + 14831 00d2 5B6B ldr r3, [r3, #52] + 14832 .loc 1 7161 8 + 14833 00d4 0D4A ldr r2, .L745+8 + 14834 00d6 9342 cmp r3, r2 + 14835 00d8 06D0 beq .L739 + 14836 .loc 1 7161 44 discriminator 1 + 14837 00da 7B88 ldrh r3, [r7, #2] + 14838 00dc 402B cmp r3, #64 + 14839 00de 03D1 bne .L739 +7162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +7163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable TC interrupts */ +7164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmpisr |= I2C_IT_TCI; + 14840 .loc 1 7164 14 + 14841 00e0 FB68 ldr r3, [r7, #12] + 14842 00e2 43F04003 orr r3, r3, #64 + 14843 00e6 FB60 str r3, [r7, #12] + 14844 .L739: +7165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +7166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +7167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +7168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable interrupts only at the end */ +7169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* to avoid the risk of I2C interrupt handle execution before */ +7170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* all interrupts requested done */ + ARM GAS /tmp/cc5G5cqz.s page 390 + + +7171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_ENABLE_IT(hi2c, tmpisr); + 14845 .loc 1 7171 3 + 14846 00e8 7B68 ldr r3, [r7, #4] + 14847 00ea 1B68 ldr r3, [r3] + 14848 00ec 1968 ldr r1, [r3] + 14849 00ee 7B68 ldr r3, [r7, #4] + 14850 00f0 1B68 ldr r3, [r3] + 14851 00f2 FA68 ldr r2, [r7, #12] + 14852 00f4 0A43 orrs r2, r2, r1 + 14853 00f6 1A60 str r2, [r3] +7172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 14854 .loc 1 7172 1 + 14855 00f8 00BF nop + 14856 00fa 1437 adds r7, r7, #20 + 14857 .cfi_def_cfa_offset 4 + 14858 00fc BD46 mov sp, r7 + 14859 .cfi_def_cfa_register 13 + 14860 @ sp needed + 14861 00fe 5DF8047B ldr r7, [sp], #4 + 14862 .cfi_restore 7 + 14863 .cfi_def_cfa_offset 0 + 14864 0102 7047 bx lr + 14865 .L746: + 14866 .align 2 + 14867 .L745: + 14868 0104 00000000 .word I2C_Master_ISR_DMA + 14869 0108 00000000 .word I2C_Slave_ISR_DMA + 14870 010c 00000000 .word I2C_Mem_ISR_DMA + 14871 .cfi_endproc + 14872 .LFE208: + 14874 .section .text.I2C_Disable_IRQ,"ax",%progbits + 14875 .align 1 + 14876 .syntax unified + 14877 .thumb + 14878 .thumb_func + 14880 I2C_Disable_IRQ: + 14881 .LFB209: +7173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +7174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +7175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Manage the disabling of Interrupts. +7176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains +7177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * the configuration information for the specified I2C. +7178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. +7179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +7180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +7181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +7182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 14882 .loc 1 7182 1 + 14883 .cfi_startproc + 14884 @ args = 0, pretend = 0, frame = 16 + 14885 @ frame_needed = 1, uses_anonymous_args = 0 + 14886 @ link register save eliminated. + 14887 0000 80B4 push {r7} + 14888 .cfi_def_cfa_offset 4 + 14889 .cfi_offset 7, -4 + 14890 0002 85B0 sub sp, sp, #20 + 14891 .cfi_def_cfa_offset 24 + ARM GAS /tmp/cc5G5cqz.s page 391 + + + 14892 0004 00AF add r7, sp, #0 + 14893 .cfi_def_cfa_register 7 + 14894 0006 7860 str r0, [r7, #4] + 14895 0008 0B46 mov r3, r1 + 14896 000a 7B80 strh r3, [r7, #2] @ movhi +7183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** uint32_t tmpisr = 0U; + 14897 .loc 1 7183 12 + 14898 000c 0023 movs r3, #0 + 14899 000e FB60 str r3, [r7, #12] +7184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +7185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + 14900 .loc 1 7185 25 + 14901 0010 7B88 ldrh r3, [r7, #2] + 14902 0012 03F00103 and r3, r3, #1 + 14903 .loc 1 7185 6 + 14904 0016 002B cmp r3, #0 + 14905 0018 0FD0 beq .L748 +7186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +7187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable TC and TXI interrupts */ +7188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmpisr |= I2C_IT_TCI | I2C_IT_TXI; + 14906 .loc 1 7188 12 + 14907 001a FB68 ldr r3, [r7, #12] + 14908 001c 43F04203 orr r3, r3, #66 + 14909 0020 FB60 str r3, [r7, #12] +7189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +7190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) + 14910 .loc 1 7190 24 + 14911 0022 7B68 ldr r3, [r7, #4] + 14912 0024 93F84130 ldrb r3, [r3, #65] + 14913 0028 DBB2 uxtb r3, r3 + 14914 .loc 1 7190 32 + 14915 002a 03F02803 and r3, r3, #40 + 14916 .loc 1 7190 8 + 14917 002e 282B cmp r3, #40 + 14918 0030 03D0 beq .L748 +7191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +7192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable NACK and STOP interrupts */ +7193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + 14919 .loc 1 7193 14 + 14920 0032 FB68 ldr r3, [r7, #12] + 14921 0034 43F0B003 orr r3, r3, #176 + 14922 0038 FB60 str r3, [r7, #12] + 14923 .L748: +7194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +7195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +7196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +7197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + 14924 .loc 1 7197 25 + 14925 003a 7B88 ldrh r3, [r7, #2] + 14926 003c 03F00203 and r3, r3, #2 + 14927 .loc 1 7197 6 + 14928 0040 002B cmp r3, #0 + 14929 0042 0FD0 beq .L749 +7198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +7199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable TC and RXI interrupts */ +7200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmpisr |= I2C_IT_TCI | I2C_IT_RXI; + 14930 .loc 1 7200 12 + ARM GAS /tmp/cc5G5cqz.s page 392 + + + 14931 0044 FB68 ldr r3, [r7, #12] + 14932 0046 43F04403 orr r3, r3, #68 + 14933 004a FB60 str r3, [r7, #12] +7201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +7202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) + 14934 .loc 1 7202 24 + 14935 004c 7B68 ldr r3, [r7, #4] + 14936 004e 93F84130 ldrb r3, [r3, #65] + 14937 0052 DBB2 uxtb r3, r3 + 14938 .loc 1 7202 32 + 14939 0054 03F02803 and r3, r3, #40 + 14940 .loc 1 7202 8 + 14941 0058 282B cmp r3, #40 + 14942 005a 03D0 beq .L749 +7203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +7204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable NACK and STOP interrupts */ +7205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + 14943 .loc 1 7205 14 + 14944 005c FB68 ldr r3, [r7, #12] + 14945 005e 43F0B003 orr r3, r3, #176 + 14946 0062 FB60 str r3, [r7, #12] + 14947 .L749: +7206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +7207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +7208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +7209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + 14948 .loc 1 7209 47 + 14949 0064 B7F90230 ldrsh r3, [r7, #2] + 14950 .loc 1 7209 6 + 14951 0068 002B cmp r3, #0 + 14952 006a 03DA bge .L750 +7210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +7211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable ADDR, NACK and STOP interrupts */ +7212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + 14953 .loc 1 7212 12 + 14954 006c FB68 ldr r3, [r7, #12] + 14955 006e 43F0B803 orr r3, r3, #184 + 14956 0072 FB60 str r3, [r7, #12] + 14957 .L750: +7213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +7214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +7215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (InterruptRequest == I2C_XFER_ERROR_IT) + 14958 .loc 1 7215 6 + 14959 0074 7B88 ldrh r3, [r7, #2] + 14960 0076 102B cmp r3, #16 + 14961 0078 03D1 bne .L751 +7216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +7217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable ERR and NACK interrupts */ +7218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + 14962 .loc 1 7218 12 + 14963 007a FB68 ldr r3, [r7, #12] + 14964 007c 43F09003 orr r3, r3, #144 + 14965 0080 FB60 str r3, [r7, #12] + 14966 .L751: +7219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +7220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +7221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (InterruptRequest == I2C_XFER_CPLT_IT) + ARM GAS /tmp/cc5G5cqz.s page 393 + + + 14967 .loc 1 7221 6 + 14968 0082 7B88 ldrh r3, [r7, #2] + 14969 0084 202B cmp r3, #32 + 14970 0086 03D1 bne .L752 +7222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +7223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable STOP interrupts */ +7224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmpisr |= I2C_IT_STOPI; + 14971 .loc 1 7224 12 + 14972 0088 FB68 ldr r3, [r7, #12] + 14973 008a 43F02003 orr r3, r3, #32 + 14974 008e FB60 str r3, [r7, #12] + 14975 .L752: +7225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +7226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +7227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (InterruptRequest == I2C_XFER_RELOAD_IT) + 14976 .loc 1 7227 6 + 14977 0090 7B88 ldrh r3, [r7, #2] + 14978 0092 402B cmp r3, #64 + 14979 0094 03D1 bne .L753 +7228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +7229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Enable TC interrupts */ +7230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** tmpisr |= I2C_IT_TCI; + 14980 .loc 1 7230 12 + 14981 0096 FB68 ldr r3, [r7, #12] + 14982 0098 43F04003 orr r3, r3, #64 + 14983 009c FB60 str r3, [r7, #12] + 14984 .L753: +7231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +7232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +7233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Disable interrupts only at the end */ +7234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* to avoid a breaking situation like at "t" time */ +7235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* all disable interrupts request are not done */ +7236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** __HAL_I2C_DISABLE_IT(hi2c, tmpisr); + 14985 .loc 1 7236 3 + 14986 009e 7B68 ldr r3, [r7, #4] + 14987 00a0 1B68 ldr r3, [r3] + 14988 00a2 1968 ldr r1, [r3] + 14989 00a4 FB68 ldr r3, [r7, #12] + 14990 00a6 DA43 mvns r2, r3 + 14991 00a8 7B68 ldr r3, [r7, #4] + 14992 00aa 1B68 ldr r3, [r3] + 14993 00ac 0A40 ands r2, r2, r1 + 14994 00ae 1A60 str r2, [r3] +7237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 14995 .loc 1 7237 1 + 14996 00b0 00BF nop + 14997 00b2 1437 adds r7, r7, #20 + 14998 .cfi_def_cfa_offset 4 + 14999 00b4 BD46 mov sp, r7 + 15000 .cfi_def_cfa_register 13 + 15001 @ sp needed + 15002 00b6 5DF8047B ldr r7, [sp], #4 + 15003 .cfi_restore 7 + 15004 .cfi_def_cfa_offset 0 + 15005 00ba 7047 bx lr + 15006 .cfi_endproc + 15007 .LFE209: + ARM GAS /tmp/cc5G5cqz.s page 394 + + + 15009 .section .text.I2C_ConvertOtherXferOptions,"ax",%progbits + 15010 .align 1 + 15011 .syntax unified + 15012 .thumb + 15013 .thumb_func + 15015 I2C_ConvertOtherXferOptions: + 15016 .LFB210: +7238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** +7239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /** +7240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions. +7241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @param hi2c I2C handle. +7242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** * @retval None +7243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** */ +7244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c) +7245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 15017 .loc 1 7245 1 + 15018 .cfi_startproc + 15019 @ args = 0, pretend = 0, frame = 8 + 15020 @ frame_needed = 1, uses_anonymous_args = 0 + 15021 @ link register save eliminated. + 15022 0000 80B4 push {r7} + 15023 .cfi_def_cfa_offset 4 + 15024 .cfi_offset 7, -4 + 15025 0002 83B0 sub sp, sp, #12 + 15026 .cfi_def_cfa_offset 16 + 15027 0004 00AF add r7, sp, #0 + 15028 .cfi_def_cfa_register 7 + 15029 0006 7860 str r0, [r7, #4] +7246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* if user set XferOptions to I2C_OTHER_FRAME */ +7247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* it request implicitly to generate a restart condition */ +7248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* set XferOptions to I2C_FIRST_FRAME */ +7249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** if (hi2c->XferOptions == I2C_OTHER_FRAME) + 15030 .loc 1 7249 11 + 15031 0008 7B68 ldr r3, [r7, #4] + 15032 000a DB6A ldr r3, [r3, #44] + 15033 .loc 1 7249 6 + 15034 000c AA2B cmp r3, #170 + 15035 000e 03D1 bne .L755 +7250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +7251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_FIRST_FRAME; + 15036 .loc 1 7251 23 + 15037 0010 7B68 ldr r3, [r7, #4] + 15038 0012 0022 movs r2, #0 + 15039 0014 DA62 str r2, [r3, #44] +7252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +7253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */ +7254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* it request implicitly to generate a restart condition */ +7255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* then generate a stop condition at the end of transfer */ +7256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */ +7257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME) +7258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +7259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME; +7260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } +7261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** else +7262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { +7263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** /* Nothing to do */ +7264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + ARM GAS /tmp/cc5G5cqz.s page 395 + + +7265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 15040 .loc 1 7265 1 + 15041 0016 08E0 b .L757 + 15042 .L755: +7257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 15043 .loc 1 7257 16 + 15044 0018 7B68 ldr r3, [r7, #4] + 15045 001a DB6A ldr r3, [r3, #44] +7257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** { + 15046 .loc 1 7257 11 + 15047 001c B3F52A4F cmp r3, #43520 + 15048 0020 03D1 bne .L757 +7259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c **** } + 15049 .loc 1 7259 23 + 15050 0022 7B68 ldr r3, [r7, #4] + 15051 0024 4FF00072 mov r2, #33554432 + 15052 0028 DA62 str r2, [r3, #44] + 15053 .L757: + 15054 .loc 1 7265 1 + 15055 002a 00BF nop + 15056 002c 0C37 adds r7, r7, #12 + 15057 .cfi_def_cfa_offset 4 + 15058 002e BD46 mov sp, r7 + 15059 .cfi_def_cfa_register 13 + 15060 @ sp needed + 15061 0030 5DF8047B ldr r7, [sp], #4 + 15062 .cfi_restore 7 + 15063 .cfi_def_cfa_offset 0 + 15064 0034 7047 bx lr + 15065 .cfi_endproc + 15066 .LFE210: + 15068 .text + 15069 .Letext0: + 15070 .file 2 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 15071 .file 3 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 15072 .file 4 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + 15073 .file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h" + 15074 .file 6 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h" + 15075 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h" + 15076 .file 8 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h" + 15077 .file 9 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h" + ARM GAS /tmp/cc5G5cqz.s page 396 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f3xx_hal_i2c.c + /tmp/cc5G5cqz.s:21 .text.HAL_I2C_Init:00000000 $t + /tmp/cc5G5cqz.s:27 .text.HAL_I2C_Init:00000000 HAL_I2C_Init + /tmp/cc5G5cqz.s:320 .text.HAL_I2C_MspInit:00000000 HAL_I2C_MspInit + /tmp/cc5G5cqz.s:235 .text.HAL_I2C_DeInit:00000000 $t + /tmp/cc5G5cqz.s:241 .text.HAL_I2C_DeInit:00000000 HAL_I2C_DeInit + /tmp/cc5G5cqz.s:356 .text.HAL_I2C_MspDeInit:00000000 HAL_I2C_MspDeInit + /tmp/cc5G5cqz.s:314 .text.HAL_I2C_MspInit:00000000 $t + /tmp/cc5G5cqz.s:350 .text.HAL_I2C_MspDeInit:00000000 $t + /tmp/cc5G5cqz.s:386 .text.HAL_I2C_Master_Transmit:00000000 $t + /tmp/cc5G5cqz.s:392 .text.HAL_I2C_Master_Transmit:00000000 HAL_I2C_Master_Transmit + /tmp/cc5G5cqz.s:13790 .text.I2C_WaitOnFlagUntilTimeout:00000000 I2C_WaitOnFlagUntilTimeout + /tmp/cc5G5cqz.s:14606 .text.I2C_TransferConfig:00000000 I2C_TransferConfig + /tmp/cc5G5cqz.s:13909 .text.I2C_WaitOnTXISFlagUntilTimeout:00000000 I2C_WaitOnTXISFlagUntilTimeout + /tmp/cc5G5cqz.s:14020 .text.I2C_WaitOnSTOPFlagUntilTimeout:00000000 I2C_WaitOnSTOPFlagUntilTimeout + /tmp/cc5G5cqz.s:705 .text.HAL_I2C_Master_Transmit:000001e0 $d + /tmp/cc5G5cqz.s:711 .text.HAL_I2C_Master_Receive:00000000 $t + /tmp/cc5G5cqz.s:717 .text.HAL_I2C_Master_Receive:00000000 HAL_I2C_Master_Receive + /tmp/cc5G5cqz.s:14127 .text.I2C_WaitOnRXNEFlagUntilTimeout:00000000 I2C_WaitOnRXNEFlagUntilTimeout + /tmp/cc5G5cqz.s:1032 .text.HAL_I2C_Master_Receive:000001e4 $d + /tmp/cc5G5cqz.s:1038 .text.HAL_I2C_Slave_Transmit:00000000 $t + /tmp/cc5G5cqz.s:1044 .text.HAL_I2C_Slave_Transmit:00000000 HAL_I2C_Slave_Transmit + /tmp/cc5G5cqz.s:13220 .text.I2C_Flush_TXDR:00000000 I2C_Flush_TXDR + /tmp/cc5G5cqz.s:1461 .text.HAL_I2C_Slave_Receive:00000000 $t + /tmp/cc5G5cqz.s:1467 .text.HAL_I2C_Slave_Receive:00000000 HAL_I2C_Slave_Receive + /tmp/cc5G5cqz.s:1839 .text.HAL_I2C_Master_Transmit_IT:00000000 $t + /tmp/cc5G5cqz.s:1845 .text.HAL_I2C_Master_Transmit_IT:00000000 HAL_I2C_Master_Transmit_IT + /tmp/cc5G5cqz.s:14686 .text.I2C_Enable_IRQ:00000000 I2C_Enable_IRQ + /tmp/cc5G5cqz.s:1991 .text.HAL_I2C_Master_Transmit_IT:000000d4 $d + /tmp/cc5G5cqz.s:9171 .text.I2C_Master_ISR_IT:00000000 I2C_Master_ISR_IT + /tmp/cc5G5cqz.s:1998 .text.HAL_I2C_Master_Receive_IT:00000000 $t + /tmp/cc5G5cqz.s:2004 .text.HAL_I2C_Master_Receive_IT:00000000 HAL_I2C_Master_Receive_IT + /tmp/cc5G5cqz.s:2150 .text.HAL_I2C_Master_Receive_IT:000000d4 $d + /tmp/cc5G5cqz.s:2157 .text.HAL_I2C_Slave_Transmit_IT:00000000 $t + /tmp/cc5G5cqz.s:2163 .text.HAL_I2C_Slave_Transmit_IT:00000000 HAL_I2C_Slave_Transmit_IT + /tmp/cc5G5cqz.s:2315 .text.HAL_I2C_Slave_Transmit_IT:000000d4 $d + /tmp/cc5G5cqz.s:9982 .text.I2C_Slave_ISR_IT:00000000 I2C_Slave_ISR_IT + /tmp/cc5G5cqz.s:2321 .text.HAL_I2C_Slave_Receive_IT:00000000 $t + /tmp/cc5G5cqz.s:2327 .text.HAL_I2C_Slave_Receive_IT:00000000 HAL_I2C_Slave_Receive_IT + /tmp/cc5G5cqz.s:2438 .text.HAL_I2C_Slave_Receive_IT:00000098 $d + /tmp/cc5G5cqz.s:2444 .text.HAL_I2C_Master_Transmit_DMA:00000000 $t + /tmp/cc5G5cqz.s:2450 .text.HAL_I2C_Master_Transmit_DMA:00000000 HAL_I2C_Master_Transmit_DMA + /tmp/cc5G5cqz.s:2751 .text.HAL_I2C_Master_Transmit_DMA:000001c8 $d + /tmp/cc5G5cqz.s:10339 .text.I2C_Master_ISR_DMA:00000000 I2C_Master_ISR_DMA + /tmp/cc5G5cqz.s:13287 .text.I2C_DMAMasterTransmitCplt:00000000 I2C_DMAMasterTransmitCplt + /tmp/cc5G5cqz.s:13674 .text.I2C_DMAError:00000000 I2C_DMAError + /tmp/cc5G5cqz.s:2761 .text.HAL_I2C_Master_Receive_DMA:00000000 $t + /tmp/cc5G5cqz.s:2767 .text.HAL_I2C_Master_Receive_DMA:00000000 HAL_I2C_Master_Receive_DMA + /tmp/cc5G5cqz.s:3068 .text.HAL_I2C_Master_Receive_DMA:000001c8 $d + /tmp/cc5G5cqz.s:13479 .text.I2C_DMAMasterReceiveCplt:00000000 I2C_DMAMasterReceiveCplt + /tmp/cc5G5cqz.s:3078 .text.HAL_I2C_Slave_Transmit_DMA:00000000 $t + /tmp/cc5G5cqz.s:3084 .text.HAL_I2C_Slave_Transmit_DMA:00000000 HAL_I2C_Slave_Transmit_DMA + /tmp/cc5G5cqz.s:3397 .text.HAL_I2C_Slave_Transmit_DMA:000001c8 $d + /tmp/cc5G5cqz.s:11069 .text.I2C_Slave_ISR_DMA:00000000 I2C_Slave_ISR_DMA + /tmp/cc5G5cqz.s:13415 .text.I2C_DMASlaveTransmitCplt:00000000 I2C_DMASlaveTransmitCplt + /tmp/cc5G5cqz.s:3405 .text.HAL_I2C_Slave_Receive_DMA:00000000 $t + ARM GAS /tmp/cc5G5cqz.s page 397 + + + /tmp/cc5G5cqz.s:3411 .text.HAL_I2C_Slave_Receive_DMA:00000000 HAL_I2C_Slave_Receive_DMA + /tmp/cc5G5cqz.s:3650 .text.HAL_I2C_Slave_Receive_DMA:0000015c $d + /tmp/cc5G5cqz.s:13607 .text.I2C_DMASlaveReceiveCplt:00000000 I2C_DMASlaveReceiveCplt + /tmp/cc5G5cqz.s:3658 .text.HAL_I2C_Mem_Write:00000000 $t + /tmp/cc5G5cqz.s:3664 .text.HAL_I2C_Mem_Write:00000000 HAL_I2C_Mem_Write + /tmp/cc5G5cqz.s:11380 .text.I2C_RequestMemoryWrite:00000000 I2C_RequestMemoryWrite + /tmp/cc5G5cqz.s:4018 .text.HAL_I2C_Mem_Write:00000224 $d + /tmp/cc5G5cqz.s:4023 .text.HAL_I2C_Mem_Read:00000000 $t + /tmp/cc5G5cqz.s:4029 .text.HAL_I2C_Mem_Read:00000000 HAL_I2C_Mem_Read + /tmp/cc5G5cqz.s:11512 .text.I2C_RequestMemoryRead:00000000 I2C_RequestMemoryRead + /tmp/cc5G5cqz.s:4388 .text.HAL_I2C_Mem_Read:0000022c $d + /tmp/cc5G5cqz.s:4394 .text.HAL_I2C_Mem_Write_IT:00000000 $t + /tmp/cc5G5cqz.s:4400 .text.HAL_I2C_Mem_Write_IT:00000000 HAL_I2C_Mem_Write_IT + /tmp/cc5G5cqz.s:4577 .text.HAL_I2C_Mem_Write_IT:00000100 $d + /tmp/cc5G5cqz.s:9572 .text.I2C_Mem_ISR_IT:00000000 I2C_Mem_ISR_IT + /tmp/cc5G5cqz.s:4584 .text.HAL_I2C_Mem_Read_IT:00000000 $t + /tmp/cc5G5cqz.s:4590 .text.HAL_I2C_Mem_Read_IT:00000000 HAL_I2C_Mem_Read_IT + /tmp/cc5G5cqz.s:4767 .text.HAL_I2C_Mem_Read_IT:00000100 $d + /tmp/cc5G5cqz.s:4774 .text.HAL_I2C_Mem_Write_DMA:00000000 $t + /tmp/cc5G5cqz.s:4780 .text.HAL_I2C_Mem_Write_DMA:00000000 HAL_I2C_Mem_Write_DMA + /tmp/cc5G5cqz.s:5078 .text.HAL_I2C_Mem_Write_DMA:000001b8 $d + /tmp/cc5G5cqz.s:10671 .text.I2C_Mem_ISR_DMA:00000000 I2C_Mem_ISR_DMA + /tmp/cc5G5cqz.s:5087 .text.HAL_I2C_Mem_Read_DMA:00000000 $t + /tmp/cc5G5cqz.s:5093 .text.HAL_I2C_Mem_Read_DMA:00000000 HAL_I2C_Mem_Read_DMA + /tmp/cc5G5cqz.s:5391 .text.HAL_I2C_Mem_Read_DMA:000001b8 $d + /tmp/cc5G5cqz.s:5400 .text.HAL_I2C_IsDeviceReady:00000000 $t + /tmp/cc5G5cqz.s:5406 .text.HAL_I2C_IsDeviceReady:00000000 HAL_I2C_IsDeviceReady + /tmp/cc5G5cqz.s:5744 .text.HAL_I2C_Master_Seq_Transmit_IT:00000000 $t + /tmp/cc5G5cqz.s:5750 .text.HAL_I2C_Master_Seq_Transmit_IT:00000000 HAL_I2C_Master_Seq_Transmit_IT + /tmp/cc5G5cqz.s:15015 .text.I2C_ConvertOtherXferOptions:00000000 I2C_ConvertOtherXferOptions + /tmp/cc5G5cqz.s:5934 .text.HAL_I2C_Master_Seq_Transmit_IT:00000100 $d + /tmp/cc5G5cqz.s:5940 .text.HAL_I2C_Master_Seq_Transmit_DMA:00000000 $t + /tmp/cc5G5cqz.s:5946 .text.HAL_I2C_Master_Seq_Transmit_DMA:00000000 HAL_I2C_Master_Seq_Transmit_DMA + /tmp/cc5G5cqz.s:6285 .text.HAL_I2C_Master_Seq_Transmit_DMA:000001f4 $d + /tmp/cc5G5cqz.s:6294 .text.HAL_I2C_Master_Seq_Receive_IT:00000000 $t + /tmp/cc5G5cqz.s:6300 .text.HAL_I2C_Master_Seq_Receive_IT:00000000 HAL_I2C_Master_Seq_Receive_IT + /tmp/cc5G5cqz.s:6484 .text.HAL_I2C_Master_Seq_Receive_IT:00000100 $d + /tmp/cc5G5cqz.s:6490 .text.HAL_I2C_Master_Seq_Receive_DMA:00000000 $t + /tmp/cc5G5cqz.s:6496 .text.HAL_I2C_Master_Seq_Receive_DMA:00000000 HAL_I2C_Master_Seq_Receive_DMA + /tmp/cc5G5cqz.s:6835 .text.HAL_I2C_Master_Seq_Receive_DMA:000001f4 $d + /tmp/cc5G5cqz.s:6844 .text.HAL_I2C_Slave_Seq_Transmit_IT:00000000 $t + /tmp/cc5G5cqz.s:6850 .text.HAL_I2C_Slave_Seq_Transmit_IT:00000000 HAL_I2C_Slave_Seq_Transmit_IT + /tmp/cc5G5cqz.s:14880 .text.I2C_Disable_IRQ:00000000 I2C_Disable_IRQ + /tmp/cc5G5cqz.s:7084 .text.HAL_I2C_Slave_Seq_Transmit_IT:0000015c $d + /tmp/cc5G5cqz.s:13725 .text.I2C_DMAAbort:00000000 I2C_DMAAbort + /tmp/cc5G5cqz.s:7090 .text.HAL_I2C_Slave_Seq_Transmit_DMA:00000000 $t + /tmp/cc5G5cqz.s:7096 .text.HAL_I2C_Slave_Seq_Transmit_DMA:00000000 HAL_I2C_Slave_Seq_Transmit_DMA + /tmp/cc5G5cqz.s:7522 .text.HAL_I2C_Slave_Seq_Transmit_DMA:0000027c $d + /tmp/cc5G5cqz.s:7530 .text.HAL_I2C_Slave_Seq_Receive_IT:00000000 $t + /tmp/cc5G5cqz.s:7536 .text.HAL_I2C_Slave_Seq_Receive_IT:00000000 HAL_I2C_Slave_Seq_Receive_IT + /tmp/cc5G5cqz.s:7770 .text.HAL_I2C_Slave_Seq_Receive_IT:0000015c $d + /tmp/cc5G5cqz.s:7776 .text.HAL_I2C_Slave_Seq_Receive_DMA:00000000 $t + /tmp/cc5G5cqz.s:7782 .text.HAL_I2C_Slave_Seq_Receive_DMA:00000000 HAL_I2C_Slave_Seq_Receive_DMA + /tmp/cc5G5cqz.s:8208 .text.HAL_I2C_Slave_Seq_Receive_DMA:0000027c $d + /tmp/cc5G5cqz.s:8216 .text.HAL_I2C_EnableListen_IT:00000000 $t + /tmp/cc5G5cqz.s:8222 .text.HAL_I2C_EnableListen_IT:00000000 HAL_I2C_EnableListen_IT + /tmp/cc5G5cqz.s:8274 .text.HAL_I2C_EnableListen_IT:0000003c $d + ARM GAS /tmp/cc5G5cqz.s page 398 + + + /tmp/cc5G5cqz.s:8279 .text.HAL_I2C_DisableListen_IT:00000000 $t + /tmp/cc5G5cqz.s:8285 .text.HAL_I2C_DisableListen_IT:00000000 HAL_I2C_DisableListen_IT + /tmp/cc5G5cqz.s:8361 .text.HAL_I2C_Master_Abort_IT:00000000 $t + /tmp/cc5G5cqz.s:8367 .text.HAL_I2C_Master_Abort_IT:00000000 HAL_I2C_Master_Abort_IT + /tmp/cc5G5cqz.s:8476 .text.HAL_I2C_Master_Abort_IT:0000009c $d + /tmp/cc5G5cqz.s:8481 .text.HAL_I2C_EV_IRQHandler:00000000 $t + /tmp/cc5G5cqz.s:8487 .text.HAL_I2C_EV_IRQHandler:00000000 HAL_I2C_EV_IRQHandler + /tmp/cc5G5cqz.s:8542 .text.HAL_I2C_ER_IRQHandler:00000000 $t + /tmp/cc5G5cqz.s:8548 .text.HAL_I2C_ER_IRQHandler:00000000 HAL_I2C_ER_IRQHandler + /tmp/cc5G5cqz.s:12814 .text.I2C_ITError:00000000 I2C_ITError + /tmp/cc5G5cqz.s:8683 .text.HAL_I2C_MasterTxCpltCallback:00000000 $t + /tmp/cc5G5cqz.s:8689 .text.HAL_I2C_MasterTxCpltCallback:00000000 HAL_I2C_MasterTxCpltCallback + /tmp/cc5G5cqz.s:8719 .text.HAL_I2C_MasterRxCpltCallback:00000000 $t + /tmp/cc5G5cqz.s:8725 .text.HAL_I2C_MasterRxCpltCallback:00000000 HAL_I2C_MasterRxCpltCallback + /tmp/cc5G5cqz.s:8755 .text.HAL_I2C_SlaveTxCpltCallback:00000000 $t + /tmp/cc5G5cqz.s:8761 .text.HAL_I2C_SlaveTxCpltCallback:00000000 HAL_I2C_SlaveTxCpltCallback + /tmp/cc5G5cqz.s:8791 .text.HAL_I2C_SlaveRxCpltCallback:00000000 $t + /tmp/cc5G5cqz.s:8797 .text.HAL_I2C_SlaveRxCpltCallback:00000000 HAL_I2C_SlaveRxCpltCallback + /tmp/cc5G5cqz.s:8827 .text.HAL_I2C_AddrCallback:00000000 $t + /tmp/cc5G5cqz.s:8833 .text.HAL_I2C_AddrCallback:00000000 HAL_I2C_AddrCallback + /tmp/cc5G5cqz.s:8867 .text.HAL_I2C_ListenCpltCallback:00000000 $t + /tmp/cc5G5cqz.s:8873 .text.HAL_I2C_ListenCpltCallback:00000000 HAL_I2C_ListenCpltCallback + /tmp/cc5G5cqz.s:8903 .text.HAL_I2C_MemTxCpltCallback:00000000 $t + /tmp/cc5G5cqz.s:8909 .text.HAL_I2C_MemTxCpltCallback:00000000 HAL_I2C_MemTxCpltCallback + /tmp/cc5G5cqz.s:8939 .text.HAL_I2C_MemRxCpltCallback:00000000 $t + /tmp/cc5G5cqz.s:8945 .text.HAL_I2C_MemRxCpltCallback:00000000 HAL_I2C_MemRxCpltCallback + /tmp/cc5G5cqz.s:8975 .text.HAL_I2C_ErrorCallback:00000000 $t + /tmp/cc5G5cqz.s:8981 .text.HAL_I2C_ErrorCallback:00000000 HAL_I2C_ErrorCallback + /tmp/cc5G5cqz.s:9011 .text.HAL_I2C_AbortCpltCallback:00000000 $t + /tmp/cc5G5cqz.s:9017 .text.HAL_I2C_AbortCpltCallback:00000000 HAL_I2C_AbortCpltCallback + /tmp/cc5G5cqz.s:9047 .text.HAL_I2C_GetState:00000000 $t + /tmp/cc5G5cqz.s:9053 .text.HAL_I2C_GetState:00000000 HAL_I2C_GetState + /tmp/cc5G5cqz.s:9087 .text.HAL_I2C_GetMode:00000000 $t + /tmp/cc5G5cqz.s:9093 .text.HAL_I2C_GetMode:00000000 HAL_I2C_GetMode + /tmp/cc5G5cqz.s:9127 .text.HAL_I2C_GetError:00000000 $t + /tmp/cc5G5cqz.s:9133 .text.HAL_I2C_GetError:00000000 HAL_I2C_GetError + /tmp/cc5G5cqz.s:9166 .text.I2C_Master_ISR_IT:00000000 $t + /tmp/cc5G5cqz.s:11822 .text.I2C_ITMasterSeqCplt:00000000 I2C_ITMasterSeqCplt + /tmp/cc5G5cqz.s:12052 .text.I2C_ITMasterCplt:00000000 I2C_ITMasterCplt + /tmp/cc5G5cqz.s:9567 .text.I2C_Mem_ISR_IT:00000000 $t + /tmp/cc5G5cqz.s:9971 .text.I2C_Mem_ISR_IT:0000024c $d + /tmp/cc5G5cqz.s:9977 .text.I2C_Slave_ISR_IT:00000000 $t + /tmp/cc5G5cqz.s:12321 .text.I2C_ITSlaveCplt:00000000 I2C_ITSlaveCplt + /tmp/cc5G5cqz.s:12684 .text.I2C_ITListenCplt:00000000 I2C_ITListenCplt + /tmp/cc5G5cqz.s:11915 .text.I2C_ITSlaveSeqCplt:00000000 I2C_ITSlaveSeqCplt + /tmp/cc5G5cqz.s:11644 .text.I2C_ITAddrCplt:00000000 I2C_ITAddrCplt + /tmp/cc5G5cqz.s:10334 .text.I2C_Master_ISR_DMA:00000000 $t + /tmp/cc5G5cqz.s:10666 .text.I2C_Mem_ISR_DMA:00000000 $t + /tmp/cc5G5cqz.s:11058 .text.I2C_Mem_ISR_DMA:00000240 $d + /tmp/cc5G5cqz.s:11064 .text.I2C_Slave_ISR_DMA:00000000 $t + /tmp/cc5G5cqz.s:11375 .text.I2C_RequestMemoryWrite:00000000 $t + /tmp/cc5G5cqz.s:11502 .text.I2C_RequestMemoryWrite:000000a4 $d + /tmp/cc5G5cqz.s:11507 .text.I2C_RequestMemoryRead:00000000 $t + /tmp/cc5G5cqz.s:11634 .text.I2C_RequestMemoryRead:000000a4 $d + /tmp/cc5G5cqz.s:11639 .text.I2C_ITAddrCplt:00000000 $t + /tmp/cc5G5cqz.s:11817 .text.I2C_ITMasterSeqCplt:00000000 $t + /tmp/cc5G5cqz.s:11910 .text.I2C_ITSlaveSeqCplt:00000000 $t + ARM GAS /tmp/cc5G5cqz.s page 399 + + + /tmp/cc5G5cqz.s:12047 .text.I2C_ITMasterCplt:00000000 $t + /tmp/cc5G5cqz.s:12310 .text.I2C_ITMasterCplt:0000018c $d + /tmp/cc5G5cqz.s:12316 .text.I2C_ITSlaveCplt:00000000 $t + /tmp/cc5G5cqz.s:12673 .text.I2C_ITSlaveCplt:0000020c $d + /tmp/cc5G5cqz.s:12679 .text.I2C_ITListenCplt:00000000 $t + /tmp/cc5G5cqz.s:12804 .text.I2C_ITListenCplt:000000a8 $d + /tmp/cc5G5cqz.s:12809 .text.I2C_ITError:00000000 $t + /tmp/cc5G5cqz.s:13151 .text.I2C_TreatErrorCallback:00000000 I2C_TreatErrorCallback + /tmp/cc5G5cqz.s:13139 .text.I2C_ITError:000001d4 $d + /tmp/cc5G5cqz.s:13146 .text.I2C_TreatErrorCallback:00000000 $t + /tmp/cc5G5cqz.s:13215 .text.I2C_Flush_TXDR:00000000 $t + /tmp/cc5G5cqz.s:13282 .text.I2C_DMAMasterTransmitCplt:00000000 $t + /tmp/cc5G5cqz.s:13410 .text.I2C_DMASlaveTransmitCplt:00000000 $t + /tmp/cc5G5cqz.s:13474 .text.I2C_DMAMasterReceiveCplt:00000000 $t + /tmp/cc5G5cqz.s:13602 .text.I2C_DMASlaveReceiveCplt:00000000 $t + /tmp/cc5G5cqz.s:13669 .text.I2C_DMAError:00000000 $t + /tmp/cc5G5cqz.s:13720 .text.I2C_DMAAbort:00000000 $t + /tmp/cc5G5cqz.s:13785 .text.I2C_WaitOnFlagUntilTimeout:00000000 $t + /tmp/cc5G5cqz.s:13904 .text.I2C_WaitOnTXISFlagUntilTimeout:00000000 $t + /tmp/cc5G5cqz.s:14314 .text.I2C_IsErrorOccurred:00000000 I2C_IsErrorOccurred + /tmp/cc5G5cqz.s:14015 .text.I2C_WaitOnSTOPFlagUntilTimeout:00000000 $t + /tmp/cc5G5cqz.s:14122 .text.I2C_WaitOnRXNEFlagUntilTimeout:00000000 $t + /tmp/cc5G5cqz.s:14304 .text.I2C_WaitOnRXNEFlagUntilTimeout:00000100 $d + /tmp/cc5G5cqz.s:14309 .text.I2C_IsErrorOccurred:00000000 $t + /tmp/cc5G5cqz.s:14596 .text.I2C_IsErrorOccurred:000001bc $d + /tmp/cc5G5cqz.s:14601 .text.I2C_TransferConfig:00000000 $t + /tmp/cc5G5cqz.s:14676 .text.I2C_TransferConfig:00000060 $d + /tmp/cc5G5cqz.s:14681 .text.I2C_Enable_IRQ:00000000 $t + /tmp/cc5G5cqz.s:14868 .text.I2C_Enable_IRQ:00000104 $d + /tmp/cc5G5cqz.s:14875 .text.I2C_Disable_IRQ:00000000 $t + /tmp/cc5G5cqz.s:15010 .text.I2C_ConvertOtherXferOptions:00000000 $t + +UNDEFINED SYMBOLS +HAL_GetTick +HAL_DMA_Start_IT +HAL_DMA_Abort_IT +HAL_DMA_GetState diff --git a/Software/build/stm32f3xx_hal_i2c.o b/Software/build/stm32f3xx_hal_i2c.o new file mode 100644 index 0000000..1161aa2 Binary files /dev/null and b/Software/build/stm32f3xx_hal_i2c.o differ diff --git a/Software/build/stm32f3xx_hal_i2c_ex.d b/Software/build/stm32f3xx_hal_i2c_ex.d new file mode 100644 index 0000000..729660c --- /dev/null +++ b/Software/build/stm32f3xx_hal_i2c_ex.d @@ -0,0 +1,62 @@ +build/stm32f3xx_hal_i2c_ex.o: \ + Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + Core/Inc/stm32f3xx_hal_conf.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h: diff --git a/Software/build/stm32f3xx_hal_i2c_ex.lst b/Software/build/stm32f3xx_hal_i2c_ex.lst new file mode 100644 index 0000000..af75f81 --- /dev/null +++ b/Software/build/stm32f3xx_hal_i2c_ex.lst @@ -0,0 +1,997 @@ +ARM GAS /tmp/ccn4xs8A.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 6 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "stm32f3xx_hal_i2c_ex.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c" + 20 .section .text.HAL_I2CEx_ConfigAnalogFilter,"ax",%progbits + 21 .align 1 + 22 .global HAL_I2CEx_ConfigAnalogFilter + 23 .syntax unified + 24 .thumb + 25 .thumb_func + 27 HAL_I2CEx_ConfigAnalogFilter: + 28 .LFB130: + 1:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /** + 2:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** ****************************************************************************** + 3:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @file stm32f3xx_hal_i2c_ex.c + 4:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @author MCD Application Team + 5:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @brief I2C Extended HAL module driver. + 6:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * functionalities of I2C Extended peripheral: + 8:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * + Filter Mode Functions + 9:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * + WakeUp Mode Functions + 10:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * + FastModePlus Functions + 11:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * + 12:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** ****************************************************************************** + 13:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @attention + 14:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * + 15:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * Copyright (c) 2016 STMicroelectronics. + 16:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * All rights reserved. + 17:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * + 18:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * This software is licensed under terms that can be found in the LICENSE file + 19:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * in the root directory of this software component. + 20:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 21:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * + 22:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** ****************************************************************************** + 23:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** @verbatim + 24:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** ============================================================================== + 25:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** ##### I2C peripheral Extended features ##### + 26:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** ============================================================================== + 27:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** [..] Comparing to other previous devices, the I2C interface for STM32F3xx + 29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** devices contains the following additional features + 30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + ARM GAS /tmp/ccn4xs8A.s page 2 + + + 31:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** (+) Possibility to disable or enable Analog Noise Filter + 32:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** (+) Use of a configured Digital Noise Filter + 33:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** (+) Disable or enable wakeup from Stop mode(s) + 34:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** (+) Disable or enable Fast Mode Plus + 35:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 36:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** ##### How to use this driver ##### + 37:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** ============================================================================== + 38:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** [..] This driver provides functions to configure Noise Filter and Wake Up Feature + 39:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter() + 40:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter() + 41:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** (#) Configure the enable or disable of I2C Wake Up Mode using the functions : + 42:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** (++) HAL_I2CEx_EnableWakeUp() + 43:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** (++) HAL_I2CEx_DisableWakeUp() + 44:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** (#) Configure the enable or disable of fast mode plus driving capability using the functions : + 45:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** (++) HAL_I2CEx_EnableFastModePlus() + 46:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** (++) HAL_I2CEx_DisableFastModePlus() + 47:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** @endverbatim + 48:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** */ + 49:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 50:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Includes ------------------------------------------------------------------*/ + 51:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** #include "stm32f3xx_hal.h" + 52:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 53:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /** @addtogroup STM32F3xx_HAL_Driver + 54:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @{ + 55:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** */ + 56:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 57:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /** @defgroup I2CEx I2CEx + 58:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @brief I2C Extended HAL module driver + 59:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @{ + 60:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** */ + 61:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 62:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** #ifdef HAL_I2C_MODULE_ENABLED + 63:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 64:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Private typedef -----------------------------------------------------------*/ + 65:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Private define ------------------------------------------------------------*/ + 66:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Private macro -------------------------------------------------------------*/ + 67:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Private variables ---------------------------------------------------------*/ + 68:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Private function prototypes -----------------------------------------------*/ + 69:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Private functions ---------------------------------------------------------*/ + 70:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 71:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions + 72:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @{ + 73:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** */ + 74:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 75:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions + 76:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @brief Filter Mode Functions + 77:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * + 78:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** @verbatim + 79:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** =============================================================================== + 80:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** ##### Filter Mode Functions ##### + 81:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** =============================================================================== + 82:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** [..] This section provides functions allowing to: + 83:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** (+) Configure Noise Filters + 84:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** @endverbatim + 86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @{ + 87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** */ + ARM GAS /tmp/ccn4xs8A.s page 3 + + + 88:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 89:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /** + 90:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @brief Configure I2C Analog noise filter. + 91:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 92:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * the configuration information for the specified I2Cx peripheral. + 93:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @param AnalogFilter New state of the Analog filter. + 94:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @retval HAL status + 95:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** */ + 96:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) + 97:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** { + 29 .loc 1 97 1 + 30 .cfi_startproc + 31 @ args = 0, pretend = 0, frame = 8 + 32 @ frame_needed = 1, uses_anonymous_args = 0 + 33 @ link register save eliminated. + 34 0000 80B4 push {r7} + 35 .cfi_def_cfa_offset 4 + 36 .cfi_offset 7, -4 + 37 0002 83B0 sub sp, sp, #12 + 38 .cfi_def_cfa_offset 16 + 39 0004 00AF add r7, sp, #0 + 40 .cfi_def_cfa_register 7 + 41 0006 7860 str r0, [r7, #4] + 42 0008 3960 str r1, [r7] + 98:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Check the parameters */ + 99:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + 100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); + 101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 43 .loc 1 102 11 + 44 000a 7B68 ldr r3, [r7, #4] + 45 000c 93F84130 ldrb r3, [r3, #65] + 46 0010 DBB2 uxtb r3, r3 + 47 .loc 1 102 6 + 48 0012 202B cmp r3, #32 + 49 0014 38D1 bne .L2 + 103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** { + 104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Process Locked */ + 105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_LOCK(hi2c); + 50 .loc 1 105 5 + 51 0016 7B68 ldr r3, [r7, #4] + 52 0018 93F84030 ldrb r3, [r3, #64] @ zero_extendqisi2 + 53 001c 012B cmp r3, #1 + 54 001e 01D1 bne .L3 + 55 .loc 1 105 5 is_stmt 0 discriminator 1 + 56 0020 0223 movs r3, #2 + 57 .loc 1 105 5 + 58 0022 32E0 b .L4 + 59 .L3: + 60 .loc 1 105 5 discriminator 2 + 61 0024 7B68 ldr r3, [r7, #4] + 62 0026 0122 movs r2, #1 + 63 0028 83F84020 strb r2, [r3, #64] + 106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_BUSY; + 64 .loc 1 107 17 is_stmt 1 + 65 002c 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/ccn4xs8A.s page 4 + + + 66 002e 2422 movs r2, #36 + 67 0030 83F84120 strb r2, [r3, #65] + 108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Disable the selected I2C peripheral */ + 110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_I2C_DISABLE(hi2c); + 68 .loc 1 110 5 + 69 0034 7B68 ldr r3, [r7, #4] + 70 0036 1B68 ldr r3, [r3] + 71 0038 1A68 ldr r2, [r3] + 72 003a 7B68 ldr r3, [r7, #4] + 73 003c 1B68 ldr r3, [r3] + 74 003e 22F00102 bic r2, r2, #1 + 75 0042 1A60 str r2, [r3] + 111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Reset I2Cx ANOFF bit */ + 113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); + 76 .loc 1 113 9 + 77 0044 7B68 ldr r3, [r7, #4] + 78 0046 1B68 ldr r3, [r3] + 79 .loc 1 113 19 + 80 0048 1A68 ldr r2, [r3] + 81 .loc 1 113 9 + 82 004a 7B68 ldr r3, [r7, #4] + 83 004c 1B68 ldr r3, [r3] + 84 .loc 1 113 25 + 85 004e 22F48052 bic r2, r2, #4096 + 86 0052 1A60 str r2, [r3] + 114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Set analog filter bit*/ + 116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** hi2c->Instance->CR1 |= AnalogFilter; + 87 .loc 1 116 9 + 88 0054 7B68 ldr r3, [r7, #4] + 89 0056 1B68 ldr r3, [r3] + 90 .loc 1 116 19 + 91 0058 1968 ldr r1, [r3] + 92 .loc 1 116 9 + 93 005a 7B68 ldr r3, [r7, #4] + 94 005c 1B68 ldr r3, [r3] + 95 .loc 1 116 25 + 96 005e 3A68 ldr r2, [r7] + 97 0060 0A43 orrs r2, r2, r1 + 98 0062 1A60 str r2, [r3] + 117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_I2C_ENABLE(hi2c); + 99 .loc 1 118 5 + 100 0064 7B68 ldr r3, [r7, #4] + 101 0066 1B68 ldr r3, [r3] + 102 0068 1A68 ldr r2, [r3] + 103 006a 7B68 ldr r3, [r7, #4] + 104 006c 1B68 ldr r3, [r3] + 105 006e 42F00102 orr r2, r2, #1 + 106 0072 1A60 str r2, [r3] + 119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_READY; + 107 .loc 1 120 17 + 108 0074 7B68 ldr r3, [r7, #4] + 109 0076 2022 movs r2, #32 + ARM GAS /tmp/ccn4xs8A.s page 5 + + + 110 0078 83F84120 strb r2, [r3, #65] + 121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Process Unlocked */ + 123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_UNLOCK(hi2c); + 111 .loc 1 123 5 + 112 007c 7B68 ldr r3, [r7, #4] + 113 007e 0022 movs r2, #0 + 114 0080 83F84020 strb r2, [r3, #64] + 124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** return HAL_OK; + 115 .loc 1 125 12 + 116 0084 0023 movs r3, #0 + 117 0086 00E0 b .L4 + 118 .L2: + 126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** } + 127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** else + 128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** { + 129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** return HAL_BUSY; + 119 .loc 1 129 12 + 120 0088 0223 movs r3, #2 + 121 .L4: + 130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** } + 131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** } + 122 .loc 1 131 1 + 123 008a 1846 mov r0, r3 + 124 008c 0C37 adds r7, r7, #12 + 125 .cfi_def_cfa_offset 4 + 126 008e BD46 mov sp, r7 + 127 .cfi_def_cfa_register 13 + 128 @ sp needed + 129 0090 5DF8047B ldr r7, [sp], #4 + 130 .cfi_restore 7 + 131 .cfi_def_cfa_offset 0 + 132 0094 7047 bx lr + 133 .cfi_endproc + 134 .LFE130: + 136 .section .text.HAL_I2CEx_ConfigDigitalFilter,"ax",%progbits + 137 .align 1 + 138 .global HAL_I2CEx_ConfigDigitalFilter + 139 .syntax unified + 140 .thumb + 141 .thumb_func + 143 HAL_I2CEx_ConfigDigitalFilter: + 144 .LFB131: + 132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /** + 134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @brief Configure I2C Digital noise filter. + 135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * the configuration information for the specified I2Cx peripheral. + 137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x + 138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @retval HAL status + 139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** */ + 140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) + 141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** { + 145 .loc 1 141 1 + 146 .cfi_startproc + 147 @ args = 0, pretend = 0, frame = 16 + ARM GAS /tmp/ccn4xs8A.s page 6 + + + 148 @ frame_needed = 1, uses_anonymous_args = 0 + 149 @ link register save eliminated. + 150 0000 80B4 push {r7} + 151 .cfi_def_cfa_offset 4 + 152 .cfi_offset 7, -4 + 153 0002 85B0 sub sp, sp, #20 + 154 .cfi_def_cfa_offset 24 + 155 0004 00AF add r7, sp, #0 + 156 .cfi_def_cfa_register 7 + 157 0006 7860 str r0, [r7, #4] + 158 0008 3960 str r1, [r7] + 142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** uint32_t tmpreg; + 143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Check the parameters */ + 145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + 146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); + 147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 159 .loc 1 148 11 + 160 000a 7B68 ldr r3, [r7, #4] + 161 000c 93F84130 ldrb r3, [r3, #65] + 162 0010 DBB2 uxtb r3, r3 + 163 .loc 1 148 6 + 164 0012 202B cmp r3, #32 + 165 0014 39D1 bne .L6 + 149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** { + 150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Process Locked */ + 151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_LOCK(hi2c); + 166 .loc 1 151 5 + 167 0016 7B68 ldr r3, [r7, #4] + 168 0018 93F84030 ldrb r3, [r3, #64] @ zero_extendqisi2 + 169 001c 012B cmp r3, #1 + 170 001e 01D1 bne .L7 + 171 .loc 1 151 5 is_stmt 0 discriminator 1 + 172 0020 0223 movs r3, #2 + 173 .loc 1 151 5 + 174 0022 33E0 b .L8 + 175 .L7: + 176 .loc 1 151 5 discriminator 2 + 177 0024 7B68 ldr r3, [r7, #4] + 178 0026 0122 movs r2, #1 + 179 0028 83F84020 strb r2, [r3, #64] + 152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_BUSY; + 180 .loc 1 153 17 is_stmt 1 + 181 002c 7B68 ldr r3, [r7, #4] + 182 002e 2422 movs r2, #36 + 183 0030 83F84120 strb r2, [r3, #65] + 154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Disable the selected I2C peripheral */ + 156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_I2C_DISABLE(hi2c); + 184 .loc 1 156 5 + 185 0034 7B68 ldr r3, [r7, #4] + 186 0036 1B68 ldr r3, [r3] + 187 0038 1A68 ldr r2, [r3] + 188 003a 7B68 ldr r3, [r7, #4] + 189 003c 1B68 ldr r3, [r3] + ARM GAS /tmp/ccn4xs8A.s page 7 + + + 190 003e 22F00102 bic r2, r2, #1 + 191 0042 1A60 str r2, [r3] + 157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Get the old register value */ + 159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** tmpreg = hi2c->Instance->CR1; + 192 .loc 1 159 18 + 193 0044 7B68 ldr r3, [r7, #4] + 194 0046 1B68 ldr r3, [r3] + 195 .loc 1 159 12 + 196 0048 1B68 ldr r3, [r3] + 197 004a FB60 str r3, [r7, #12] + 160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Reset I2Cx DNF bits [11:8] */ + 162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** tmpreg &= ~(I2C_CR1_DNF); + 198 .loc 1 162 12 + 199 004c FB68 ldr r3, [r7, #12] + 200 004e 23F47063 bic r3, r3, #3840 + 201 0052 FB60 str r3, [r7, #12] + 163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Set I2Cx DNF coefficient */ + 165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** tmpreg |= DigitalFilter << 8U; + 202 .loc 1 165 29 + 203 0054 3B68 ldr r3, [r7] + 204 0056 1B02 lsls r3, r3, #8 + 205 .loc 1 165 12 + 206 0058 FA68 ldr r2, [r7, #12] + 207 005a 1343 orrs r3, r3, r2 + 208 005c FB60 str r3, [r7, #12] + 166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Store the new register value */ + 168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** hi2c->Instance->CR1 = tmpreg; + 209 .loc 1 168 9 + 210 005e 7B68 ldr r3, [r7, #4] + 211 0060 1B68 ldr r3, [r3] + 212 .loc 1 168 25 + 213 0062 FA68 ldr r2, [r7, #12] + 214 0064 1A60 str r2, [r3] + 169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_I2C_ENABLE(hi2c); + 215 .loc 1 170 5 + 216 0066 7B68 ldr r3, [r7, #4] + 217 0068 1B68 ldr r3, [r3] + 218 006a 1A68 ldr r2, [r3] + 219 006c 7B68 ldr r3, [r7, #4] + 220 006e 1B68 ldr r3, [r3] + 221 0070 42F00102 orr r2, r2, #1 + 222 0074 1A60 str r2, [r3] + 171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_READY; + 223 .loc 1 172 17 + 224 0076 7B68 ldr r3, [r7, #4] + 225 0078 2022 movs r2, #32 + 226 007a 83F84120 strb r2, [r3, #65] + 173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Process Unlocked */ + 175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_UNLOCK(hi2c); + 227 .loc 1 175 5 + ARM GAS /tmp/ccn4xs8A.s page 8 + + + 228 007e 7B68 ldr r3, [r7, #4] + 229 0080 0022 movs r2, #0 + 230 0082 83F84020 strb r2, [r3, #64] + 176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** return HAL_OK; + 231 .loc 1 177 12 + 232 0086 0023 movs r3, #0 + 233 0088 00E0 b .L8 + 234 .L6: + 178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** } + 179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** else + 180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** { + 181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** return HAL_BUSY; + 235 .loc 1 181 12 + 236 008a 0223 movs r3, #2 + 237 .L8: + 182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** } + 183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** } + 238 .loc 1 183 1 + 239 008c 1846 mov r0, r3 + 240 008e 1437 adds r7, r7, #20 + 241 .cfi_def_cfa_offset 4 + 242 0090 BD46 mov sp, r7 + 243 .cfi_def_cfa_register 13 + 244 @ sp needed + 245 0092 5DF8047B ldr r7, [sp], #4 + 246 .cfi_restore 7 + 247 .cfi_def_cfa_offset 0 + 248 0096 7047 bx lr + 249 .cfi_endproc + 250 .LFE131: + 252 .section .text.HAL_I2CEx_EnableWakeUp,"ax",%progbits + 253 .align 1 + 254 .global HAL_I2CEx_EnableWakeUp + 255 .syntax unified + 256 .thumb + 257 .thumb_func + 259 HAL_I2CEx_EnableWakeUp: + 260 .LFB132: + 184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /** + 185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @} + 186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** */ + 187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /** @defgroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions + 189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @brief WakeUp Mode Functions + 190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * + 191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** @verbatim + 192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** =============================================================================== + 193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** ##### WakeUp Mode Functions ##### + 194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** =============================================================================== + 195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** [..] This section provides functions allowing to: + 196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** (+) Configure Wake Up Feature + 197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** @endverbatim + 199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @{ + 200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** */ + 201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + ARM GAS /tmp/ccn4xs8A.s page 9 + + + 202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /** + 203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @brief Enable I2C wakeup from Stop mode(s). + 204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * the configuration information for the specified I2Cx peripheral. + 206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @retval HAL status + 207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** */ + 208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c) + 209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** { + 261 .loc 1 209 1 + 262 .cfi_startproc + 263 @ args = 0, pretend = 0, frame = 8 + 264 @ frame_needed = 1, uses_anonymous_args = 0 + 265 @ link register save eliminated. + 266 0000 80B4 push {r7} + 267 .cfi_def_cfa_offset 4 + 268 .cfi_offset 7, -4 + 269 0002 83B0 sub sp, sp, #12 + 270 .cfi_def_cfa_offset 16 + 271 0004 00AF add r7, sp, #0 + 272 .cfi_def_cfa_register 7 + 273 0006 7860 str r0, [r7, #4] + 210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Check the parameters */ + 211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); + 212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 274 .loc 1 213 11 + 275 0008 7B68 ldr r3, [r7, #4] + 276 000a 93F84130 ldrb r3, [r3, #65] + 277 000e DBB2 uxtb r3, r3 + 278 .loc 1 213 6 + 279 0010 202B cmp r3, #32 + 280 0012 30D1 bne .L10 + 214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** { + 215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Process Locked */ + 216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_LOCK(hi2c); + 281 .loc 1 216 5 + 282 0014 7B68 ldr r3, [r7, #4] + 283 0016 93F84030 ldrb r3, [r3, #64] @ zero_extendqisi2 + 284 001a 012B cmp r3, #1 + 285 001c 01D1 bne .L11 + 286 .loc 1 216 5 is_stmt 0 discriminator 1 + 287 001e 0223 movs r3, #2 + 288 .loc 1 216 5 + 289 0020 2AE0 b .L12 + 290 .L11: + 291 .loc 1 216 5 discriminator 2 + 292 0022 7B68 ldr r3, [r7, #4] + 293 0024 0122 movs r2, #1 + 294 0026 83F84020 strb r2, [r3, #64] + 217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_BUSY; + 295 .loc 1 218 17 is_stmt 1 + 296 002a 7B68 ldr r3, [r7, #4] + 297 002c 2422 movs r2, #36 + 298 002e 83F84120 strb r2, [r3, #65] + 219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Disable the selected I2C peripheral */ + ARM GAS /tmp/ccn4xs8A.s page 10 + + + 221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_I2C_DISABLE(hi2c); + 299 .loc 1 221 5 + 300 0032 7B68 ldr r3, [r7, #4] + 301 0034 1B68 ldr r3, [r3] + 302 0036 1A68 ldr r2, [r3] + 303 0038 7B68 ldr r3, [r7, #4] + 304 003a 1B68 ldr r3, [r3] + 305 003c 22F00102 bic r2, r2, #1 + 306 0040 1A60 str r2, [r3] + 222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Enable wakeup from stop mode */ + 224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** hi2c->Instance->CR1 |= I2C_CR1_WUPEN; + 307 .loc 1 224 9 + 308 0042 7B68 ldr r3, [r7, #4] + 309 0044 1B68 ldr r3, [r3] + 310 .loc 1 224 19 + 311 0046 1A68 ldr r2, [r3] + 312 .loc 1 224 9 + 313 0048 7B68 ldr r3, [r7, #4] + 314 004a 1B68 ldr r3, [r3] + 315 .loc 1 224 25 + 316 004c 42F48022 orr r2, r2, #262144 + 317 0050 1A60 str r2, [r3] + 225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_I2C_ENABLE(hi2c); + 318 .loc 1 226 5 + 319 0052 7B68 ldr r3, [r7, #4] + 320 0054 1B68 ldr r3, [r3] + 321 0056 1A68 ldr r2, [r3] + 322 0058 7B68 ldr r3, [r7, #4] + 323 005a 1B68 ldr r3, [r3] + 324 005c 42F00102 orr r2, r2, #1 + 325 0060 1A60 str r2, [r3] + 227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_READY; + 326 .loc 1 228 17 + 327 0062 7B68 ldr r3, [r7, #4] + 328 0064 2022 movs r2, #32 + 329 0066 83F84120 strb r2, [r3, #65] + 229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Process Unlocked */ + 231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_UNLOCK(hi2c); + 330 .loc 1 231 5 + 331 006a 7B68 ldr r3, [r7, #4] + 332 006c 0022 movs r2, #0 + 333 006e 83F84020 strb r2, [r3, #64] + 232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** return HAL_OK; + 334 .loc 1 233 12 + 335 0072 0023 movs r3, #0 + 336 0074 00E0 b .L12 + 337 .L10: + 234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** } + 235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** else + 236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** { + 237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** return HAL_BUSY; + 338 .loc 1 237 12 + ARM GAS /tmp/ccn4xs8A.s page 11 + + + 339 0076 0223 movs r3, #2 + 340 .L12: + 238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** } + 239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** } + 341 .loc 1 239 1 + 342 0078 1846 mov r0, r3 + 343 007a 0C37 adds r7, r7, #12 + 344 .cfi_def_cfa_offset 4 + 345 007c BD46 mov sp, r7 + 346 .cfi_def_cfa_register 13 + 347 @ sp needed + 348 007e 5DF8047B ldr r7, [sp], #4 + 349 .cfi_restore 7 + 350 .cfi_def_cfa_offset 0 + 351 0082 7047 bx lr + 352 .cfi_endproc + 353 .LFE132: + 355 .section .text.HAL_I2CEx_DisableWakeUp,"ax",%progbits + 356 .align 1 + 357 .global HAL_I2CEx_DisableWakeUp + 358 .syntax unified + 359 .thumb + 360 .thumb_func + 362 HAL_I2CEx_DisableWakeUp: + 363 .LFB133: + 240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /** + 242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @brief Disable I2C wakeup from Stop mode(s). + 243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + 244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * the configuration information for the specified I2Cx peripheral. + 245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @retval HAL status + 246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** */ + 247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c) + 248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** { + 364 .loc 1 248 1 + 365 .cfi_startproc + 366 @ args = 0, pretend = 0, frame = 8 + 367 @ frame_needed = 1, uses_anonymous_args = 0 + 368 @ link register save eliminated. + 369 0000 80B4 push {r7} + 370 .cfi_def_cfa_offset 4 + 371 .cfi_offset 7, -4 + 372 0002 83B0 sub sp, sp, #12 + 373 .cfi_def_cfa_offset 16 + 374 0004 00AF add r7, sp, #0 + 375 .cfi_def_cfa_register 7 + 376 0006 7860 str r0, [r7, #4] + 249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Check the parameters */ + 250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); + 251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** if (hi2c->State == HAL_I2C_STATE_READY) + 377 .loc 1 252 11 + 378 0008 7B68 ldr r3, [r7, #4] + 379 000a 93F84130 ldrb r3, [r3, #65] + 380 000e DBB2 uxtb r3, r3 + 381 .loc 1 252 6 + 382 0010 202B cmp r3, #32 + ARM GAS /tmp/ccn4xs8A.s page 12 + + + 383 0012 30D1 bne .L14 + 253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** { + 254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Process Locked */ + 255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_LOCK(hi2c); + 384 .loc 1 255 5 + 385 0014 7B68 ldr r3, [r7, #4] + 386 0016 93F84030 ldrb r3, [r3, #64] @ zero_extendqisi2 + 387 001a 012B cmp r3, #1 + 388 001c 01D1 bne .L15 + 389 .loc 1 255 5 is_stmt 0 discriminator 1 + 390 001e 0223 movs r3, #2 + 391 .loc 1 255 5 + 392 0020 2AE0 b .L16 + 393 .L15: + 394 .loc 1 255 5 discriminator 2 + 395 0022 7B68 ldr r3, [r7, #4] + 396 0024 0122 movs r2, #1 + 397 0026 83F84020 strb r2, [r3, #64] + 256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_BUSY; + 398 .loc 1 257 17 is_stmt 1 + 399 002a 7B68 ldr r3, [r7, #4] + 400 002c 2422 movs r2, #36 + 401 002e 83F84120 strb r2, [r3, #65] + 258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Disable the selected I2C peripheral */ + 260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_I2C_DISABLE(hi2c); + 402 .loc 1 260 5 + 403 0032 7B68 ldr r3, [r7, #4] + 404 0034 1B68 ldr r3, [r3] + 405 0036 1A68 ldr r2, [r3] + 406 0038 7B68 ldr r3, [r7, #4] + 407 003a 1B68 ldr r3, [r3] + 408 003c 22F00102 bic r2, r2, #1 + 409 0040 1A60 str r2, [r3] + 261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Enable wakeup from stop mode */ + 263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN); + 410 .loc 1 263 9 + 411 0042 7B68 ldr r3, [r7, #4] + 412 0044 1B68 ldr r3, [r3] + 413 .loc 1 263 19 + 414 0046 1A68 ldr r2, [r3] + 415 .loc 1 263 9 + 416 0048 7B68 ldr r3, [r7, #4] + 417 004a 1B68 ldr r3, [r3] + 418 .loc 1 263 25 + 419 004c 22F48022 bic r2, r2, #262144 + 420 0050 1A60 str r2, [r3] + 264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_I2C_ENABLE(hi2c); + 421 .loc 1 265 5 + 422 0052 7B68 ldr r3, [r7, #4] + 423 0054 1B68 ldr r3, [r3] + 424 0056 1A68 ldr r2, [r3] + 425 0058 7B68 ldr r3, [r7, #4] + 426 005a 1B68 ldr r3, [r3] + ARM GAS /tmp/ccn4xs8A.s page 13 + + + 427 005c 42F00102 orr r2, r2, #1 + 428 0060 1A60 str r2, [r3] + 266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** hi2c->State = HAL_I2C_STATE_READY; + 429 .loc 1 267 17 + 430 0062 7B68 ldr r3, [r7, #4] + 431 0064 2022 movs r2, #32 + 432 0066 83F84120 strb r2, [r3, #65] + 268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Process Unlocked */ + 270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_UNLOCK(hi2c); + 433 .loc 1 270 5 + 434 006a 7B68 ldr r3, [r7, #4] + 435 006c 0022 movs r2, #0 + 436 006e 83F84020 strb r2, [r3, #64] + 271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** return HAL_OK; + 437 .loc 1 272 12 + 438 0072 0023 movs r3, #0 + 439 0074 00E0 b .L16 + 440 .L14: + 273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** } + 274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** else + 275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** { + 276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** return HAL_BUSY; + 441 .loc 1 276 12 + 442 0076 0223 movs r3, #2 + 443 .L16: + 277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** } + 278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** } + 444 .loc 1 278 1 + 445 0078 1846 mov r0, r3 + 446 007a 0C37 adds r7, r7, #12 + 447 .cfi_def_cfa_offset 4 + 448 007c BD46 mov sp, r7 + 449 .cfi_def_cfa_register 13 + 450 @ sp needed + 451 007e 5DF8047B ldr r7, [sp], #4 + 452 .cfi_restore 7 + 453 .cfi_def_cfa_offset 0 + 454 0082 7047 bx lr + 455 .cfi_endproc + 456 .LFE133: + 458 .section .text.HAL_I2CEx_EnableFastModePlus,"ax",%progbits + 459 .align 1 + 460 .global HAL_I2CEx_EnableFastModePlus + 461 .syntax unified + 462 .thumb + 463 .thumb_func + 465 HAL_I2CEx_EnableFastModePlus: + 466 .LFB134: + 279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /** + 280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @} + 281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** */ + 282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions + 284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @brief Fast Mode Plus Functions + ARM GAS /tmp/ccn4xs8A.s page 14 + + + 285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * + 286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** @verbatim + 287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** =============================================================================== + 288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** ##### Fast Mode Plus Functions ##### + 289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** =============================================================================== + 290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** [..] This section provides functions allowing to: + 291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** (+) Configure Fast Mode Plus + 292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** @endverbatim + 294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @{ + 295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** */ + 296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /** + 298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @brief Enable the I2C fast mode plus driving capability. + 299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @param ConfigFastModePlus Selects the pin. + 300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * This parameter can be one of the @ref I2CEx_FastModePlus values + 301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @note For I2C1, fast mode plus driving capability can be enabled on all selected + 302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently + 303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * on each one of the following pins PB6, PB7, PB8 and PB9. + 304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + 305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter. + 306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @note For all I2C2 pins fast mode plus driving capability can be enabled + 307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * only by using I2C_FASTMODEPLUS_I2C2 parameter. + 308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @note For all I2C3 pins fast mode plus driving capability can be enabled + 309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * only by using I2C_FASTMODEPLUS_I2C3 parameter. + 310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @retval None + 311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** */ + 312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus) + 313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** { + 467 .loc 1 313 1 + 468 .cfi_startproc + 469 @ args = 0, pretend = 0, frame = 16 + 470 @ frame_needed = 1, uses_anonymous_args = 0 + 471 @ link register save eliminated. + 472 0000 80B4 push {r7} + 473 .cfi_def_cfa_offset 4 + 474 .cfi_offset 7, -4 + 475 0002 85B0 sub sp, sp, #20 + 476 .cfi_def_cfa_offset 24 + 477 0004 00AF add r7, sp, #0 + 478 .cfi_def_cfa_register 7 + 479 0006 7860 str r0, [r7, #4] + 480 .LBB2: + 314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Check the parameter */ + 315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); + 316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Enable SYSCFG clock */ + 318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_RCC_SYSCFG_CLK_ENABLE(); + 481 .loc 1 318 3 + 482 0008 0B4B ldr r3, .L18 + 483 000a 9B69 ldr r3, [r3, #24] + 484 000c 0A4A ldr r2, .L18 + 485 000e 43F00103 orr r3, r3, #1 + 486 0012 9361 str r3, [r2, #24] + 487 0014 084B ldr r3, .L18 + 488 0016 9B69 ldr r3, [r3, #24] + 489 0018 03F00103 and r3, r3, #1 + ARM GAS /tmp/ccn4xs8A.s page 15 + + + 490 001c FB60 str r3, [r7, #12] + 491 001e FB68 ldr r3, [r7, #12] + 492 .LBE2: + 319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Enable fast mode plus driving capability for selected pin */ + 321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus); + 493 .loc 1 321 3 + 494 0020 064B ldr r3, .L18+4 + 495 0022 1A68 ldr r2, [r3] + 496 0024 0549 ldr r1, .L18+4 + 497 0026 7B68 ldr r3, [r7, #4] + 498 0028 1343 orrs r3, r3, r2 + 499 002a 0B60 str r3, [r1] + 322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** } + 500 .loc 1 322 1 + 501 002c 00BF nop + 502 002e 1437 adds r7, r7, #20 + 503 .cfi_def_cfa_offset 4 + 504 0030 BD46 mov sp, r7 + 505 .cfi_def_cfa_register 13 + 506 @ sp needed + 507 0032 5DF8047B ldr r7, [sp], #4 + 508 .cfi_restore 7 + 509 .cfi_def_cfa_offset 0 + 510 0036 7047 bx lr + 511 .L19: + 512 .align 2 + 513 .L18: + 514 0038 00100240 .word 1073876992 + 515 003c 00000140 .word 1073807360 + 516 .cfi_endproc + 517 .LFE134: + 519 .section .text.HAL_I2CEx_DisableFastModePlus,"ax",%progbits + 520 .align 1 + 521 .global HAL_I2CEx_DisableFastModePlus + 522 .syntax unified + 523 .thumb + 524 .thumb_func + 526 HAL_I2CEx_DisableFastModePlus: + 527 .LFB135: + 323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /** + 325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @brief Disable the I2C fast mode plus driving capability. + 326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @param ConfigFastModePlus Selects the pin. + 327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * This parameter can be one of the @ref I2CEx_FastModePlus values + 328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @note For I2C1, fast mode plus driving capability can be disabled on all selected + 329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently + 330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * on each one of the following pins PB6, PB7, PB8 and PB9. + 331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + 332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter. + 333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @note For all I2C2 pins fast mode plus driving capability can be disabled + 334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * only by using I2C_FASTMODEPLUS_I2C2 parameter. + 335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @note For all I2C3 pins fast mode plus driving capability can be disabled + 336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * only by using I2C_FASTMODEPLUS_I2C3 parameter. + 337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** * @retval None + 338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** */ + 339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus) + ARM GAS /tmp/ccn4xs8A.s page 16 + + + 340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** { + 528 .loc 1 340 1 + 529 .cfi_startproc + 530 @ args = 0, pretend = 0, frame = 16 + 531 @ frame_needed = 1, uses_anonymous_args = 0 + 532 @ link register save eliminated. + 533 0000 80B4 push {r7} + 534 .cfi_def_cfa_offset 4 + 535 .cfi_offset 7, -4 + 536 0002 85B0 sub sp, sp, #20 + 537 .cfi_def_cfa_offset 24 + 538 0004 00AF add r7, sp, #0 + 539 .cfi_def_cfa_register 7 + 540 0006 7860 str r0, [r7, #4] + 541 .LBB3: + 341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Check the parameter */ + 342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); + 343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Enable SYSCFG clock */ + 345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** __HAL_RCC_SYSCFG_CLK_ENABLE(); + 542 .loc 1 345 3 + 543 0008 0C4B ldr r3, .L21 + 544 000a 9B69 ldr r3, [r3, #24] + 545 000c 0B4A ldr r2, .L21 + 546 000e 43F00103 orr r3, r3, #1 + 547 0012 9361 str r3, [r2, #24] + 548 0014 094B ldr r3, .L21 + 549 0016 9B69 ldr r3, [r3, #24] + 550 0018 03F00103 and r3, r3, #1 + 551 001c FB60 str r3, [r7, #12] + 552 001e FB68 ldr r3, [r7, #12] + 553 .LBE3: + 346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** + 347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** /* Disable fast mode plus driving capability for selected pin */ + 348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus); + 554 .loc 1 348 3 + 555 0020 074B ldr r3, .L21+4 + 556 0022 1A68 ldr r2, [r3] + 557 0024 7B68 ldr r3, [r7, #4] + 558 0026 DB43 mvns r3, r3 + 559 0028 0549 ldr r1, .L21+4 + 560 002a 1340 ands r3, r3, r2 + 561 002c 0B60 str r3, [r1] + 349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c **** } + 562 .loc 1 349 1 + 563 002e 00BF nop + 564 0030 1437 adds r7, r7, #20 + 565 .cfi_def_cfa_offset 4 + 566 0032 BD46 mov sp, r7 + 567 .cfi_def_cfa_register 13 + 568 @ sp needed + 569 0034 5DF8047B ldr r7, [sp], #4 + 570 .cfi_restore 7 + 571 .cfi_def_cfa_offset 0 + 572 0038 7047 bx lr + 573 .L22: + 574 003a 00BF .align 2 + ARM GAS /tmp/ccn4xs8A.s page 17 + + + 575 .L21: + 576 003c 00100240 .word 1073876992 + 577 0040 00000140 .word 1073807360 + 578 .cfi_endproc + 579 .LFE135: + 581 .text + 582 .Letext0: + 583 .file 2 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 584 .file 3 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 585 .file 4 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + 586 .file 5 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h" + 587 .file 6 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h" + 588 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h" + ARM GAS /tmp/ccn4xs8A.s page 18 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f3xx_hal_i2c_ex.c + /tmp/ccn4xs8A.s:21 .text.HAL_I2CEx_ConfigAnalogFilter:00000000 $t + /tmp/ccn4xs8A.s:27 .text.HAL_I2CEx_ConfigAnalogFilter:00000000 HAL_I2CEx_ConfigAnalogFilter + /tmp/ccn4xs8A.s:137 .text.HAL_I2CEx_ConfigDigitalFilter:00000000 $t + /tmp/ccn4xs8A.s:143 .text.HAL_I2CEx_ConfigDigitalFilter:00000000 HAL_I2CEx_ConfigDigitalFilter + /tmp/ccn4xs8A.s:253 .text.HAL_I2CEx_EnableWakeUp:00000000 $t + /tmp/ccn4xs8A.s:259 .text.HAL_I2CEx_EnableWakeUp:00000000 HAL_I2CEx_EnableWakeUp + /tmp/ccn4xs8A.s:356 .text.HAL_I2CEx_DisableWakeUp:00000000 $t + /tmp/ccn4xs8A.s:362 .text.HAL_I2CEx_DisableWakeUp:00000000 HAL_I2CEx_DisableWakeUp + /tmp/ccn4xs8A.s:459 .text.HAL_I2CEx_EnableFastModePlus:00000000 $t + /tmp/ccn4xs8A.s:465 .text.HAL_I2CEx_EnableFastModePlus:00000000 HAL_I2CEx_EnableFastModePlus + /tmp/ccn4xs8A.s:514 .text.HAL_I2CEx_EnableFastModePlus:00000038 $d + /tmp/ccn4xs8A.s:520 .text.HAL_I2CEx_DisableFastModePlus:00000000 $t + /tmp/ccn4xs8A.s:526 .text.HAL_I2CEx_DisableFastModePlus:00000000 HAL_I2CEx_DisableFastModePlus + /tmp/ccn4xs8A.s:576 .text.HAL_I2CEx_DisableFastModePlus:0000003c $d + +NO UNDEFINED SYMBOLS diff --git a/Software/build/stm32f3xx_hal_i2c_ex.o b/Software/build/stm32f3xx_hal_i2c_ex.o new file mode 100644 index 0000000..ec84b95 Binary files /dev/null and b/Software/build/stm32f3xx_hal_i2c_ex.o differ diff --git a/Software/build/stm32f3xx_hal_msp.d b/Software/build/stm32f3xx_hal_msp.d new file mode 100644 index 0000000..cfeacce --- /dev/null +++ b/Software/build/stm32f3xx_hal_msp.d @@ -0,0 +1,62 @@ +build/stm32f3xx_hal_msp.o: Core/Src/stm32f3xx_hal_msp.c Core/Inc/main.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + Core/Inc/stm32f3xx_hal_conf.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h +Core/Inc/main.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h: diff --git a/Software/build/stm32f3xx_hal_msp.lst b/Software/build/stm32f3xx_hal_msp.lst new file mode 100644 index 0000000..427ef1a --- /dev/null +++ b/Software/build/stm32f3xx_hal_msp.lst @@ -0,0 +1,1880 @@ +ARM GAS /tmp/cc61sY4U.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 6 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "stm32f3xx_hal_msp.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Core/Src/stm32f3xx_hal_msp.c" + 20 .section .text.HAL_MspInit,"ax",%progbits + 21 .align 1 + 22 .global HAL_MspInit + 23 .syntax unified + 24 .thumb + 25 .thumb_func + 27 HAL_MspInit: + 28 .LFB130: + 1:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN Header */ + 2:Core/Src/stm32f3xx_hal_msp.c **** /** + 3:Core/Src/stm32f3xx_hal_msp.c **** ****************************************************************************** + 4:Core/Src/stm32f3xx_hal_msp.c **** * @file stm32f3xx_hal_msp.c + 5:Core/Src/stm32f3xx_hal_msp.c **** * @brief This file provides code for the MSP Initialization + 6:Core/Src/stm32f3xx_hal_msp.c **** * and de-Initialization codes. + 7:Core/Src/stm32f3xx_hal_msp.c **** ****************************************************************************** + 8:Core/Src/stm32f3xx_hal_msp.c **** * @attention + 9:Core/Src/stm32f3xx_hal_msp.c **** * + 10:Core/Src/stm32f3xx_hal_msp.c **** * Copyright (c) 2024 STMicroelectronics. + 11:Core/Src/stm32f3xx_hal_msp.c **** * All rights reserved. + 12:Core/Src/stm32f3xx_hal_msp.c **** * + 13:Core/Src/stm32f3xx_hal_msp.c **** * This software is licensed under terms that can be found in the LICENSE file + 14:Core/Src/stm32f3xx_hal_msp.c **** * in the root directory of this software component. + 15:Core/Src/stm32f3xx_hal_msp.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 16:Core/Src/stm32f3xx_hal_msp.c **** * + 17:Core/Src/stm32f3xx_hal_msp.c **** ****************************************************************************** + 18:Core/Src/stm32f3xx_hal_msp.c **** */ + 19:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END Header */ + 20:Core/Src/stm32f3xx_hal_msp.c **** + 21:Core/Src/stm32f3xx_hal_msp.c **** /* Includes ------------------------------------------------------------------*/ + 22:Core/Src/stm32f3xx_hal_msp.c **** #include "main.h" + 23:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN Includes */ + 24:Core/Src/stm32f3xx_hal_msp.c **** + 25:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END Includes */ + 26:Core/Src/stm32f3xx_hal_msp.c **** + 27:Core/Src/stm32f3xx_hal_msp.c **** /* Private typedef -----------------------------------------------------------*/ + 28:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TD */ + 29:Core/Src/stm32f3xx_hal_msp.c **** + 30:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END TD */ + ARM GAS /tmp/cc61sY4U.s page 2 + + + 31:Core/Src/stm32f3xx_hal_msp.c **** + 32:Core/Src/stm32f3xx_hal_msp.c **** /* Private define ------------------------------------------------------------*/ + 33:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN Define */ + 34:Core/Src/stm32f3xx_hal_msp.c **** + 35:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END Define */ + 36:Core/Src/stm32f3xx_hal_msp.c **** + 37:Core/Src/stm32f3xx_hal_msp.c **** /* Private macro -------------------------------------------------------------*/ + 38:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN Macro */ + 39:Core/Src/stm32f3xx_hal_msp.c **** + 40:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END Macro */ + 41:Core/Src/stm32f3xx_hal_msp.c **** + 42:Core/Src/stm32f3xx_hal_msp.c **** /* Private variables ---------------------------------------------------------*/ + 43:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN PV */ + 44:Core/Src/stm32f3xx_hal_msp.c **** + 45:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END PV */ + 46:Core/Src/stm32f3xx_hal_msp.c **** + 47:Core/Src/stm32f3xx_hal_msp.c **** /* Private function prototypes -----------------------------------------------*/ + 48:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN PFP */ + 49:Core/Src/stm32f3xx_hal_msp.c **** + 50:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END PFP */ + 51:Core/Src/stm32f3xx_hal_msp.c **** + 52:Core/Src/stm32f3xx_hal_msp.c **** /* External functions --------------------------------------------------------*/ + 53:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN ExternalFunctions */ + 54:Core/Src/stm32f3xx_hal_msp.c **** + 55:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END ExternalFunctions */ + 56:Core/Src/stm32f3xx_hal_msp.c **** + 57:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN 0 */ + 58:Core/Src/stm32f3xx_hal_msp.c **** + 59:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END 0 */ + 60:Core/Src/stm32f3xx_hal_msp.c **** + 61:Core/Src/stm32f3xx_hal_msp.c **** void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + 62:Core/Src/stm32f3xx_hal_msp.c **** /** + 63:Core/Src/stm32f3xx_hal_msp.c **** * Initializes the Global MSP. + 64:Core/Src/stm32f3xx_hal_msp.c **** */ + 65:Core/Src/stm32f3xx_hal_msp.c **** void HAL_MspInit(void) + 66:Core/Src/stm32f3xx_hal_msp.c **** { + 29 .loc 1 66 1 + 30 .cfi_startproc + 31 @ args = 0, pretend = 0, frame = 8 + 32 @ frame_needed = 1, uses_anonymous_args = 0 + 33 @ link register save eliminated. + 34 0000 80B4 push {r7} + 35 .cfi_def_cfa_offset 4 + 36 .cfi_offset 7, -4 + 37 0002 83B0 sub sp, sp, #12 + 38 .cfi_def_cfa_offset 16 + 39 0004 00AF add r7, sp, #0 + 40 .cfi_def_cfa_register 7 + 41 .LBB2: + 67:Core/Src/stm32f3xx_hal_msp.c **** + 68:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN MspInit 0 */ + 69:Core/Src/stm32f3xx_hal_msp.c **** + 70:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END MspInit 0 */ + 71:Core/Src/stm32f3xx_hal_msp.c **** + 72:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_SYSCFG_CLK_ENABLE(); + 42 .loc 1 72 3 + 43 0006 0F4B ldr r3, .L2 + ARM GAS /tmp/cc61sY4U.s page 3 + + + 44 0008 9B69 ldr r3, [r3, #24] + 45 000a 0E4A ldr r2, .L2 + 46 000c 43F00103 orr r3, r3, #1 + 47 0010 9361 str r3, [r2, #24] + 48 0012 0C4B ldr r3, .L2 + 49 0014 9B69 ldr r3, [r3, #24] + 50 0016 03F00103 and r3, r3, #1 + 51 001a 7B60 str r3, [r7, #4] + 52 001c 7B68 ldr r3, [r7, #4] + 53 .LBE2: + 54 .LBB3: + 73:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_PWR_CLK_ENABLE(); + 55 .loc 1 73 3 + 56 001e 094B ldr r3, .L2 + 57 0020 DB69 ldr r3, [r3, #28] + 58 0022 084A ldr r2, .L2 + 59 0024 43F08053 orr r3, r3, #268435456 + 60 0028 D361 str r3, [r2, #28] + 61 002a 064B ldr r3, .L2 + 62 002c DB69 ldr r3, [r3, #28] + 63 002e 03F08053 and r3, r3, #268435456 + 64 0032 3B60 str r3, [r7] + 65 0034 3B68 ldr r3, [r7] + 66 .LBE3: + 74:Core/Src/stm32f3xx_hal_msp.c **** + 75:Core/Src/stm32f3xx_hal_msp.c **** /* System interrupt init*/ + 76:Core/Src/stm32f3xx_hal_msp.c **** + 77:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN MspInit 1 */ + 78:Core/Src/stm32f3xx_hal_msp.c **** + 79:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END MspInit 1 */ + 80:Core/Src/stm32f3xx_hal_msp.c **** } + 67 .loc 1 80 1 + 68 0036 00BF nop + 69 0038 0C37 adds r7, r7, #12 + 70 .cfi_def_cfa_offset 4 + 71 003a BD46 mov sp, r7 + 72 .cfi_def_cfa_register 13 + 73 @ sp needed + 74 003c 5DF8047B ldr r7, [sp], #4 + 75 .cfi_restore 7 + 76 .cfi_def_cfa_offset 0 + 77 0040 7047 bx lr + 78 .L3: + 79 0042 00BF .align 2 + 80 .L2: + 81 0044 00100240 .word 1073876992 + 82 .cfi_endproc + 83 .LFE130: + 85 .section .text.HAL_CAN_MspInit,"ax",%progbits + 86 .align 1 + 87 .global HAL_CAN_MspInit + 88 .syntax unified + 89 .thumb + 90 .thumb_func + 92 HAL_CAN_MspInit: + 93 .LFB131: + 81:Core/Src/stm32f3xx_hal_msp.c **** + ARM GAS /tmp/cc61sY4U.s page 4 + + + 82:Core/Src/stm32f3xx_hal_msp.c **** /** + 83:Core/Src/stm32f3xx_hal_msp.c **** * @brief CAN MSP Initialization + 84:Core/Src/stm32f3xx_hal_msp.c **** * This function configures the hardware resources used in this example + 85:Core/Src/stm32f3xx_hal_msp.c **** * @param hcan: CAN handle pointer + 86:Core/Src/stm32f3xx_hal_msp.c **** * @retval None + 87:Core/Src/stm32f3xx_hal_msp.c **** */ + 88:Core/Src/stm32f3xx_hal_msp.c **** void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan) + 89:Core/Src/stm32f3xx_hal_msp.c **** { + 94 .loc 1 89 1 + 95 .cfi_startproc + 96 @ args = 0, pretend = 0, frame = 40 + 97 @ frame_needed = 1, uses_anonymous_args = 0 + 98 0000 80B5 push {r7, lr} + 99 .cfi_def_cfa_offset 8 + 100 .cfi_offset 7, -8 + 101 .cfi_offset 14, -4 + 102 0002 8AB0 sub sp, sp, #40 + 103 .cfi_def_cfa_offset 48 + 104 0004 00AF add r7, sp, #0 + 105 .cfi_def_cfa_register 7 + 106 0006 7860 str r0, [r7, #4] + 90:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitTypeDef GPIO_InitStruct = {0}; + 107 .loc 1 90 20 + 108 0008 07F11403 add r3, r7, #20 + 109 000c 0022 movs r2, #0 + 110 000e 1A60 str r2, [r3] + 111 0010 5A60 str r2, [r3, #4] + 112 0012 9A60 str r2, [r3, #8] + 113 0014 DA60 str r2, [r3, #12] + 114 0016 1A61 str r2, [r3, #16] + 91:Core/Src/stm32f3xx_hal_msp.c **** if(hcan->Instance==CAN) + 115 .loc 1 91 10 + 116 0018 7B68 ldr r3, [r7, #4] + 117 001a 1B68 ldr r3, [r3] + 118 .loc 1 91 5 + 119 001c 204A ldr r2, .L7 + 120 001e 9342 cmp r3, r2 + 121 0020 39D1 bne .L6 + 122 .LBB4: + 92:Core/Src/stm32f3xx_hal_msp.c **** { + 93:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN CAN_MspInit 0 */ + 94:Core/Src/stm32f3xx_hal_msp.c **** + 95:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END CAN_MspInit 0 */ + 96:Core/Src/stm32f3xx_hal_msp.c **** /* Peripheral clock enable */ + 97:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_CAN1_CLK_ENABLE(); + 123 .loc 1 97 5 + 124 0022 204B ldr r3, .L7+4 + 125 0024 DB69 ldr r3, [r3, #28] + 126 0026 1F4A ldr r2, .L7+4 + 127 0028 43F00073 orr r3, r3, #33554432 + 128 002c D361 str r3, [r2, #28] + 129 002e 1D4B ldr r3, .L7+4 + 130 0030 DB69 ldr r3, [r3, #28] + 131 0032 03F00073 and r3, r3, #33554432 + 132 0036 3B61 str r3, [r7, #16] + 133 0038 3B69 ldr r3, [r7, #16] + 134 .LBE4: + ARM GAS /tmp/cc61sY4U.s page 5 + + + 135 .LBB5: + 98:Core/Src/stm32f3xx_hal_msp.c **** + 99:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_GPIOA_CLK_ENABLE(); + 136 .loc 1 99 5 + 137 003a 1A4B ldr r3, .L7+4 + 138 003c 5B69 ldr r3, [r3, #20] + 139 003e 194A ldr r2, .L7+4 + 140 0040 43F40033 orr r3, r3, #131072 + 141 0044 5361 str r3, [r2, #20] + 142 0046 174B ldr r3, .L7+4 + 143 0048 5B69 ldr r3, [r3, #20] + 144 004a 03F40033 and r3, r3, #131072 + 145 004e FB60 str r3, [r7, #12] + 146 0050 FB68 ldr r3, [r7, #12] + 147 .LBE5: + 100:Core/Src/stm32f3xx_hal_msp.c **** /**CAN GPIO Configuration + 101:Core/Src/stm32f3xx_hal_msp.c **** PA11 ------> CAN_RX + 102:Core/Src/stm32f3xx_hal_msp.c **** PA12 ------> CAN_TX + 103:Core/Src/stm32f3xx_hal_msp.c **** */ + 104:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12; + 148 .loc 1 104 25 + 149 0052 4FF4C053 mov r3, #6144 + 150 0056 7B61 str r3, [r7, #20] + 105:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 151 .loc 1 105 26 + 152 0058 0223 movs r3, #2 + 153 005a BB61 str r3, [r7, #24] + 106:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 154 .loc 1 106 26 + 155 005c 0023 movs r3, #0 + 156 005e FB61 str r3, [r7, #28] + 107:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + 157 .loc 1 107 27 + 158 0060 0323 movs r3, #3 + 159 0062 3B62 str r3, [r7, #32] + 108:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF9_CAN; + 160 .loc 1 108 31 + 161 0064 0923 movs r3, #9 + 162 0066 7B62 str r3, [r7, #36] + 109:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 163 .loc 1 109 5 + 164 0068 07F11403 add r3, r7, #20 + 165 006c 1946 mov r1, r3 + 166 006e 4FF09040 mov r0, #1207959552 + 167 0072 FFF7FEFF bl HAL_GPIO_Init + 110:Core/Src/stm32f3xx_hal_msp.c **** + 111:Core/Src/stm32f3xx_hal_msp.c **** /* CAN interrupt Init */ + 112:Core/Src/stm32f3xx_hal_msp.c **** HAL_NVIC_SetPriority(USB_LP_CAN_RX0_IRQn, 0, 0); + 168 .loc 1 112 5 + 169 0076 0022 movs r2, #0 + 170 0078 0021 movs r1, #0 + 171 007a 1420 movs r0, #20 + 172 007c FFF7FEFF bl HAL_NVIC_SetPriority + 113:Core/Src/stm32f3xx_hal_msp.c **** HAL_NVIC_EnableIRQ(USB_LP_CAN_RX0_IRQn); + 173 .loc 1 113 5 + 174 0080 1420 movs r0, #20 + 175 0082 FFF7FEFF bl HAL_NVIC_EnableIRQ + ARM GAS /tmp/cc61sY4U.s page 6 + + + 114:Core/Src/stm32f3xx_hal_msp.c **** HAL_NVIC_SetPriority(CAN_RX1_IRQn, 0, 0); + 176 .loc 1 114 5 + 177 0086 0022 movs r2, #0 + 178 0088 0021 movs r1, #0 + 179 008a 1520 movs r0, #21 + 180 008c FFF7FEFF bl HAL_NVIC_SetPriority + 115:Core/Src/stm32f3xx_hal_msp.c **** HAL_NVIC_EnableIRQ(CAN_RX1_IRQn); + 181 .loc 1 115 5 + 182 0090 1520 movs r0, #21 + 183 0092 FFF7FEFF bl HAL_NVIC_EnableIRQ + 184 .L6: + 116:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN CAN_MspInit 1 */ + 117:Core/Src/stm32f3xx_hal_msp.c **** + 118:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END CAN_MspInit 1 */ + 119:Core/Src/stm32f3xx_hal_msp.c **** } + 120:Core/Src/stm32f3xx_hal_msp.c **** + 121:Core/Src/stm32f3xx_hal_msp.c **** } + 185 .loc 1 121 1 + 186 0096 00BF nop + 187 0098 2837 adds r7, r7, #40 + 188 .cfi_def_cfa_offset 8 + 189 009a BD46 mov sp, r7 + 190 .cfi_def_cfa_register 13 + 191 @ sp needed + 192 009c 80BD pop {r7, pc} + 193 .L8: + 194 009e 00BF .align 2 + 195 .L7: + 196 00a0 00640040 .word 1073767424 + 197 00a4 00100240 .word 1073876992 + 198 .cfi_endproc + 199 .LFE131: + 201 .section .text.HAL_CAN_MspDeInit,"ax",%progbits + 202 .align 1 + 203 .global HAL_CAN_MspDeInit + 204 .syntax unified + 205 .thumb + 206 .thumb_func + 208 HAL_CAN_MspDeInit: + 209 .LFB132: + 122:Core/Src/stm32f3xx_hal_msp.c **** + 123:Core/Src/stm32f3xx_hal_msp.c **** /** + 124:Core/Src/stm32f3xx_hal_msp.c **** * @brief CAN MSP De-Initialization + 125:Core/Src/stm32f3xx_hal_msp.c **** * This function freeze the hardware resources used in this example + 126:Core/Src/stm32f3xx_hal_msp.c **** * @param hcan: CAN handle pointer + 127:Core/Src/stm32f3xx_hal_msp.c **** * @retval None + 128:Core/Src/stm32f3xx_hal_msp.c **** */ + 129:Core/Src/stm32f3xx_hal_msp.c **** void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan) + 130:Core/Src/stm32f3xx_hal_msp.c **** { + 210 .loc 1 130 1 + 211 .cfi_startproc + 212 @ args = 0, pretend = 0, frame = 8 + 213 @ frame_needed = 1, uses_anonymous_args = 0 + 214 0000 80B5 push {r7, lr} + 215 .cfi_def_cfa_offset 8 + 216 .cfi_offset 7, -8 + 217 .cfi_offset 14, -4 + ARM GAS /tmp/cc61sY4U.s page 7 + + + 218 0002 82B0 sub sp, sp, #8 + 219 .cfi_def_cfa_offset 16 + 220 0004 00AF add r7, sp, #0 + 221 .cfi_def_cfa_register 7 + 222 0006 7860 str r0, [r7, #4] + 131:Core/Src/stm32f3xx_hal_msp.c **** if(hcan->Instance==CAN) + 223 .loc 1 131 10 + 224 0008 7B68 ldr r3, [r7, #4] + 225 000a 1B68 ldr r3, [r3] + 226 .loc 1 131 5 + 227 000c 0C4A ldr r2, .L12 + 228 000e 9342 cmp r3, r2 + 229 0010 11D1 bne .L11 + 132:Core/Src/stm32f3xx_hal_msp.c **** { + 133:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN CAN_MspDeInit 0 */ + 134:Core/Src/stm32f3xx_hal_msp.c **** + 135:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END CAN_MspDeInit 0 */ + 136:Core/Src/stm32f3xx_hal_msp.c **** /* Peripheral clock disable */ + 137:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_CAN1_CLK_DISABLE(); + 230 .loc 1 137 5 + 231 0012 0C4B ldr r3, .L12+4 + 232 0014 DB69 ldr r3, [r3, #28] + 233 0016 0B4A ldr r2, .L12+4 + 234 0018 23F00073 bic r3, r3, #33554432 + 235 001c D361 str r3, [r2, #28] + 138:Core/Src/stm32f3xx_hal_msp.c **** + 139:Core/Src/stm32f3xx_hal_msp.c **** /**CAN GPIO Configuration + 140:Core/Src/stm32f3xx_hal_msp.c **** PA11 ------> CAN_RX + 141:Core/Src/stm32f3xx_hal_msp.c **** PA12 ------> CAN_TX + 142:Core/Src/stm32f3xx_hal_msp.c **** */ + 143:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11|GPIO_PIN_12); + 236 .loc 1 143 5 + 237 001e 4FF4C051 mov r1, #6144 + 238 0022 4FF09040 mov r0, #1207959552 + 239 0026 FFF7FEFF bl HAL_GPIO_DeInit + 144:Core/Src/stm32f3xx_hal_msp.c **** + 145:Core/Src/stm32f3xx_hal_msp.c **** /* CAN interrupt DeInit */ + 146:Core/Src/stm32f3xx_hal_msp.c **** HAL_NVIC_DisableIRQ(USB_LP_CAN_RX0_IRQn); + 240 .loc 1 146 5 + 241 002a 1420 movs r0, #20 + 242 002c FFF7FEFF bl HAL_NVIC_DisableIRQ + 147:Core/Src/stm32f3xx_hal_msp.c **** HAL_NVIC_DisableIRQ(CAN_RX1_IRQn); + 243 .loc 1 147 5 + 244 0030 1520 movs r0, #21 + 245 0032 FFF7FEFF bl HAL_NVIC_DisableIRQ + 246 .L11: + 148:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN CAN_MspDeInit 1 */ + 149:Core/Src/stm32f3xx_hal_msp.c **** + 150:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END CAN_MspDeInit 1 */ + 151:Core/Src/stm32f3xx_hal_msp.c **** } + 152:Core/Src/stm32f3xx_hal_msp.c **** + 153:Core/Src/stm32f3xx_hal_msp.c **** } + 247 .loc 1 153 1 + 248 0036 00BF nop + 249 0038 0837 adds r7, r7, #8 + 250 .cfi_def_cfa_offset 8 + 251 003a BD46 mov sp, r7 + ARM GAS /tmp/cc61sY4U.s page 8 + + + 252 .cfi_def_cfa_register 13 + 253 @ sp needed + 254 003c 80BD pop {r7, pc} + 255 .L13: + 256 003e 00BF .align 2 + 257 .L12: + 258 0040 00640040 .word 1073767424 + 259 0044 00100240 .word 1073876992 + 260 .cfi_endproc + 261 .LFE132: + 263 .section .text.HAL_I2C_MspInit,"ax",%progbits + 264 .align 1 + 265 .global HAL_I2C_MspInit + 266 .syntax unified + 267 .thumb + 268 .thumb_func + 270 HAL_I2C_MspInit: + 271 .LFB133: + 154:Core/Src/stm32f3xx_hal_msp.c **** + 155:Core/Src/stm32f3xx_hal_msp.c **** /** + 156:Core/Src/stm32f3xx_hal_msp.c **** * @brief I2C MSP Initialization + 157:Core/Src/stm32f3xx_hal_msp.c **** * This function configures the hardware resources used in this example + 158:Core/Src/stm32f3xx_hal_msp.c **** * @param hi2c: I2C handle pointer + 159:Core/Src/stm32f3xx_hal_msp.c **** * @retval None + 160:Core/Src/stm32f3xx_hal_msp.c **** */ + 161:Core/Src/stm32f3xx_hal_msp.c **** void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c) + 162:Core/Src/stm32f3xx_hal_msp.c **** { + 272 .loc 1 162 1 + 273 .cfi_startproc + 274 @ args = 0, pretend = 0, frame = 48 + 275 @ frame_needed = 1, uses_anonymous_args = 0 + 276 0000 80B5 push {r7, lr} + 277 .cfi_def_cfa_offset 8 + 278 .cfi_offset 7, -8 + 279 .cfi_offset 14, -4 + 280 0002 8CB0 sub sp, sp, #48 + 281 .cfi_def_cfa_offset 56 + 282 0004 00AF add r7, sp, #0 + 283 .cfi_def_cfa_register 7 + 284 0006 7860 str r0, [r7, #4] + 163:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitTypeDef GPIO_InitStruct = {0}; + 285 .loc 1 163 20 + 286 0008 07F11C03 add r3, r7, #28 + 287 000c 0022 movs r2, #0 + 288 000e 1A60 str r2, [r3] + 289 0010 5A60 str r2, [r3, #4] + 290 0012 9A60 str r2, [r3, #8] + 291 0014 DA60 str r2, [r3, #12] + 292 0016 1A61 str r2, [r3, #16] + 164:Core/Src/stm32f3xx_hal_msp.c **** if(hi2c->Instance==I2C1) + 293 .loc 1 164 10 + 294 0018 7B68 ldr r3, [r7, #4] + 295 001a 1B68 ldr r3, [r3] + 296 .loc 1 164 5 + 297 001c 3E4A ldr r2, .L18 + 298 001e 9342 cmp r3, r2 + 299 0020 47D1 bne .L15 + ARM GAS /tmp/cc61sY4U.s page 9 + + + 300 .LBB6: + 165:Core/Src/stm32f3xx_hal_msp.c **** { + 166:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN I2C1_MspInit 0 */ + 167:Core/Src/stm32f3xx_hal_msp.c **** + 168:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END I2C1_MspInit 0 */ + 169:Core/Src/stm32f3xx_hal_msp.c **** + 170:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_GPIOA_CLK_ENABLE(); + 301 .loc 1 170 5 + 302 0022 3E4B ldr r3, .L18+4 + 303 0024 5B69 ldr r3, [r3, #20] + 304 0026 3D4A ldr r2, .L18+4 + 305 0028 43F40033 orr r3, r3, #131072 + 306 002c 5361 str r3, [r2, #20] + 307 002e 3B4B ldr r3, .L18+4 + 308 0030 5B69 ldr r3, [r3, #20] + 309 0032 03F40033 and r3, r3, #131072 + 310 0036 BB61 str r3, [r7, #24] + 311 0038 BB69 ldr r3, [r7, #24] + 312 .LBE6: + 313 .LBB7: + 171:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); + 314 .loc 1 171 5 + 315 003a 384B ldr r3, .L18+4 + 316 003c 5B69 ldr r3, [r3, #20] + 317 003e 374A ldr r2, .L18+4 + 318 0040 43F48023 orr r3, r3, #262144 + 319 0044 5361 str r3, [r2, #20] + 320 0046 354B ldr r3, .L18+4 + 321 0048 5B69 ldr r3, [r3, #20] + 322 004a 03F48023 and r3, r3, #262144 + 323 004e 7B61 str r3, [r7, #20] + 324 0050 7B69 ldr r3, [r7, #20] + 325 .LBE7: + 172:Core/Src/stm32f3xx_hal_msp.c **** /**I2C1 GPIO Configuration + 173:Core/Src/stm32f3xx_hal_msp.c **** PA15 ------> I2C1_SCL + 174:Core/Src/stm32f3xx_hal_msp.c **** PB9 ------> I2C1_SDA + 175:Core/Src/stm32f3xx_hal_msp.c **** */ + 176:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pin = TMP_SCL_Pin; + 326 .loc 1 176 25 + 327 0052 4FF40043 mov r3, #32768 + 328 0056 FB61 str r3, [r7, #28] + 177:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + 329 .loc 1 177 26 + 330 0058 1223 movs r3, #18 + 331 005a 3B62 str r3, [r7, #32] + 178:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 332 .loc 1 178 26 + 333 005c 0023 movs r3, #0 + 334 005e 7B62 str r3, [r7, #36] + 179:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + 335 .loc 1 179 27 + 336 0060 0323 movs r3, #3 + 337 0062 BB62 str r3, [r7, #40] + 180:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; + 338 .loc 1 180 31 + 339 0064 0423 movs r3, #4 + 340 0066 FB62 str r3, [r7, #44] + ARM GAS /tmp/cc61sY4U.s page 10 + + + 181:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_Init(TMP_SCL_GPIO_Port, &GPIO_InitStruct); + 341 .loc 1 181 5 + 342 0068 07F11C03 add r3, r7, #28 + 343 006c 1946 mov r1, r3 + 344 006e 4FF09040 mov r0, #1207959552 + 345 0072 FFF7FEFF bl HAL_GPIO_Init + 182:Core/Src/stm32f3xx_hal_msp.c **** + 183:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pin = TMP_SDA_Pin; + 346 .loc 1 183 25 + 347 0076 4FF40073 mov r3, #512 + 348 007a FB61 str r3, [r7, #28] + 184:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + 349 .loc 1 184 26 + 350 007c 1223 movs r3, #18 + 351 007e 3B62 str r3, [r7, #32] + 185:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 352 .loc 1 185 26 + 353 0080 0023 movs r3, #0 + 354 0082 7B62 str r3, [r7, #36] + 186:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + 355 .loc 1 186 27 + 356 0084 0323 movs r3, #3 + 357 0086 BB62 str r3, [r7, #40] + 187:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; + 358 .loc 1 187 31 + 359 0088 0423 movs r3, #4 + 360 008a FB62 str r3, [r7, #44] + 188:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_Init(TMP_SDA_GPIO_Port, &GPIO_InitStruct); + 361 .loc 1 188 5 + 362 008c 07F11C03 add r3, r7, #28 + 363 0090 1946 mov r1, r3 + 364 0092 2348 ldr r0, .L18+8 + 365 0094 FFF7FEFF bl HAL_GPIO_Init + 366 .LBB8: + 189:Core/Src/stm32f3xx_hal_msp.c **** + 190:Core/Src/stm32f3xx_hal_msp.c **** /* Peripheral clock enable */ + 191:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_I2C1_CLK_ENABLE(); + 367 .loc 1 191 5 + 368 0098 204B ldr r3, .L18+4 + 369 009a DB69 ldr r3, [r3, #28] + 370 009c 1F4A ldr r2, .L18+4 + 371 009e 43F40013 orr r3, r3, #2097152 + 372 00a2 D361 str r3, [r2, #28] + 373 00a4 1D4B ldr r3, .L18+4 + 374 00a6 DB69 ldr r3, [r3, #28] + 375 00a8 03F40013 and r3, r3, #2097152 + 376 00ac 3B61 str r3, [r7, #16] + 377 00ae 3B69 ldr r3, [r7, #16] + 378 .LBE8: + 192:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN I2C1_MspInit 1 */ + 193:Core/Src/stm32f3xx_hal_msp.c **** + 194:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END I2C1_MspInit 1 */ + 195:Core/Src/stm32f3xx_hal_msp.c **** } + 196:Core/Src/stm32f3xx_hal_msp.c **** else if(hi2c->Instance==I2C2) + 197:Core/Src/stm32f3xx_hal_msp.c **** { + 198:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN I2C2_MspInit 0 */ + 199:Core/Src/stm32f3xx_hal_msp.c **** + ARM GAS /tmp/cc61sY4U.s page 11 + + + 200:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END I2C2_MspInit 0 */ + 201:Core/Src/stm32f3xx_hal_msp.c **** + 202:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_GPIOA_CLK_ENABLE(); + 203:Core/Src/stm32f3xx_hal_msp.c **** /**I2C2 GPIO Configuration + 204:Core/Src/stm32f3xx_hal_msp.c **** PA9 ------> I2C2_SCL + 205:Core/Src/stm32f3xx_hal_msp.c **** PA10 ------> I2C2_SDA + 206:Core/Src/stm32f3xx_hal_msp.c **** */ + 207:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pin = EEPROM_SCL_Pin|EEPROM_SDA_Pin; + 208:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + 209:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 210:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + 211:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF4_I2C2; + 212:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 213:Core/Src/stm32f3xx_hal_msp.c **** + 214:Core/Src/stm32f3xx_hal_msp.c **** /* Peripheral clock enable */ + 215:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_I2C2_CLK_ENABLE(); + 216:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN I2C2_MspInit 1 */ + 217:Core/Src/stm32f3xx_hal_msp.c **** + 218:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END I2C2_MspInit 1 */ + 219:Core/Src/stm32f3xx_hal_msp.c **** } + 220:Core/Src/stm32f3xx_hal_msp.c **** + 221:Core/Src/stm32f3xx_hal_msp.c **** } + 379 .loc 1 221 1 + 380 00b0 2EE0 b .L17 + 381 .L15: + 196:Core/Src/stm32f3xx_hal_msp.c **** { + 382 .loc 1 196 15 + 383 00b2 7B68 ldr r3, [r7, #4] + 384 00b4 1B68 ldr r3, [r3] + 196:Core/Src/stm32f3xx_hal_msp.c **** { + 385 .loc 1 196 10 + 386 00b6 1B4A ldr r2, .L18+12 + 387 00b8 9342 cmp r3, r2 + 388 00ba 29D1 bne .L17 + 389 .LBB9: + 202:Core/Src/stm32f3xx_hal_msp.c **** /**I2C2 GPIO Configuration + 390 .loc 1 202 5 + 391 00bc 174B ldr r3, .L18+4 + 392 00be 5B69 ldr r3, [r3, #20] + 393 00c0 164A ldr r2, .L18+4 + 394 00c2 43F40033 orr r3, r3, #131072 + 395 00c6 5361 str r3, [r2, #20] + 396 00c8 144B ldr r3, .L18+4 + 397 00ca 5B69 ldr r3, [r3, #20] + 398 00cc 03F40033 and r3, r3, #131072 + 399 00d0 FB60 str r3, [r7, #12] + 400 00d2 FB68 ldr r3, [r7, #12] + 401 .LBE9: + 207:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + 402 .loc 1 207 25 + 403 00d4 4FF4C063 mov r3, #1536 + 404 00d8 FB61 str r3, [r7, #28] + 208:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 405 .loc 1 208 26 + 406 00da 1223 movs r3, #18 + 407 00dc 3B62 str r3, [r7, #32] + 209:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + ARM GAS /tmp/cc61sY4U.s page 12 + + + 408 .loc 1 209 26 + 409 00de 0023 movs r3, #0 + 410 00e0 7B62 str r3, [r7, #36] + 210:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF4_I2C2; + 411 .loc 1 210 27 + 412 00e2 0323 movs r3, #3 + 413 00e4 BB62 str r3, [r7, #40] + 211:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 414 .loc 1 211 31 + 415 00e6 0423 movs r3, #4 + 416 00e8 FB62 str r3, [r7, #44] + 212:Core/Src/stm32f3xx_hal_msp.c **** + 417 .loc 1 212 5 + 418 00ea 07F11C03 add r3, r7, #28 + 419 00ee 1946 mov r1, r3 + 420 00f0 4FF09040 mov r0, #1207959552 + 421 00f4 FFF7FEFF bl HAL_GPIO_Init + 422 .LBB10: + 215:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN I2C2_MspInit 1 */ + 423 .loc 1 215 5 + 424 00f8 084B ldr r3, .L18+4 + 425 00fa DB69 ldr r3, [r3, #28] + 426 00fc 074A ldr r2, .L18+4 + 427 00fe 43F48003 orr r3, r3, #4194304 + 428 0102 D361 str r3, [r2, #28] + 429 0104 054B ldr r3, .L18+4 + 430 0106 DB69 ldr r3, [r3, #28] + 431 0108 03F48003 and r3, r3, #4194304 + 432 010c BB60 str r3, [r7, #8] + 433 010e BB68 ldr r3, [r7, #8] + 434 .L17: + 435 .LBE10: + 436 .loc 1 221 1 + 437 0110 00BF nop + 438 0112 3037 adds r7, r7, #48 + 439 .cfi_def_cfa_offset 8 + 440 0114 BD46 mov sp, r7 + 441 .cfi_def_cfa_register 13 + 442 @ sp needed + 443 0116 80BD pop {r7, pc} + 444 .L19: + 445 .align 2 + 446 .L18: + 447 0118 00540040 .word 1073763328 + 448 011c 00100240 .word 1073876992 + 449 0120 00040048 .word 1207960576 + 450 0124 00580040 .word 1073764352 + 451 .cfi_endproc + 452 .LFE133: + 454 .section .text.HAL_I2C_MspDeInit,"ax",%progbits + 455 .align 1 + 456 .global HAL_I2C_MspDeInit + 457 .syntax unified + 458 .thumb + 459 .thumb_func + 461 HAL_I2C_MspDeInit: + 462 .LFB134: + ARM GAS /tmp/cc61sY4U.s page 13 + + + 222:Core/Src/stm32f3xx_hal_msp.c **** + 223:Core/Src/stm32f3xx_hal_msp.c **** /** + 224:Core/Src/stm32f3xx_hal_msp.c **** * @brief I2C MSP De-Initialization + 225:Core/Src/stm32f3xx_hal_msp.c **** * This function freeze the hardware resources used in this example + 226:Core/Src/stm32f3xx_hal_msp.c **** * @param hi2c: I2C handle pointer + 227:Core/Src/stm32f3xx_hal_msp.c **** * @retval None + 228:Core/Src/stm32f3xx_hal_msp.c **** */ + 229:Core/Src/stm32f3xx_hal_msp.c **** void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c) + 230:Core/Src/stm32f3xx_hal_msp.c **** { + 463 .loc 1 230 1 + 464 .cfi_startproc + 465 @ args = 0, pretend = 0, frame = 8 + 466 @ frame_needed = 1, uses_anonymous_args = 0 + 467 0000 80B5 push {r7, lr} + 468 .cfi_def_cfa_offset 8 + 469 .cfi_offset 7, -8 + 470 .cfi_offset 14, -4 + 471 0002 82B0 sub sp, sp, #8 + 472 .cfi_def_cfa_offset 16 + 473 0004 00AF add r7, sp, #0 + 474 .cfi_def_cfa_register 7 + 475 0006 7860 str r0, [r7, #4] + 231:Core/Src/stm32f3xx_hal_msp.c **** if(hi2c->Instance==I2C1) + 476 .loc 1 231 10 + 477 0008 7B68 ldr r3, [r7, #4] + 478 000a 1B68 ldr r3, [r3] + 479 .loc 1 231 5 + 480 000c 174A ldr r2, .L24 + 481 000e 9342 cmp r3, r2 + 482 0010 11D1 bne .L21 + 232:Core/Src/stm32f3xx_hal_msp.c **** { + 233:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN I2C1_MspDeInit 0 */ + 234:Core/Src/stm32f3xx_hal_msp.c **** + 235:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END I2C1_MspDeInit 0 */ + 236:Core/Src/stm32f3xx_hal_msp.c **** /* Peripheral clock disable */ + 237:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_I2C1_CLK_DISABLE(); + 483 .loc 1 237 5 + 484 0012 174B ldr r3, .L24+4 + 485 0014 DB69 ldr r3, [r3, #28] + 486 0016 164A ldr r2, .L24+4 + 487 0018 23F40013 bic r3, r3, #2097152 + 488 001c D361 str r3, [r2, #28] + 238:Core/Src/stm32f3xx_hal_msp.c **** + 239:Core/Src/stm32f3xx_hal_msp.c **** /**I2C1 GPIO Configuration + 240:Core/Src/stm32f3xx_hal_msp.c **** PA15 ------> I2C1_SCL + 241:Core/Src/stm32f3xx_hal_msp.c **** PB9 ------> I2C1_SDA + 242:Core/Src/stm32f3xx_hal_msp.c **** */ + 243:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_DeInit(TMP_SCL_GPIO_Port, TMP_SCL_Pin); + 489 .loc 1 243 5 + 490 001e 4FF40041 mov r1, #32768 + 491 0022 4FF09040 mov r0, #1207959552 + 492 0026 FFF7FEFF bl HAL_GPIO_DeInit + 244:Core/Src/stm32f3xx_hal_msp.c **** + 245:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_DeInit(TMP_SDA_GPIO_Port, TMP_SDA_Pin); + 493 .loc 1 245 5 + 494 002a 4FF40071 mov r1, #512 + 495 002e 1148 ldr r0, .L24+8 + ARM GAS /tmp/cc61sY4U.s page 14 + + + 496 0030 FFF7FEFF bl HAL_GPIO_DeInit + 246:Core/Src/stm32f3xx_hal_msp.c **** + 247:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN I2C1_MspDeInit 1 */ + 248:Core/Src/stm32f3xx_hal_msp.c **** + 249:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END I2C1_MspDeInit 1 */ + 250:Core/Src/stm32f3xx_hal_msp.c **** } + 251:Core/Src/stm32f3xx_hal_msp.c **** else if(hi2c->Instance==I2C2) + 252:Core/Src/stm32f3xx_hal_msp.c **** { + 253:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN I2C2_MspDeInit 0 */ + 254:Core/Src/stm32f3xx_hal_msp.c **** + 255:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END I2C2_MspDeInit 0 */ + 256:Core/Src/stm32f3xx_hal_msp.c **** /* Peripheral clock disable */ + 257:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_I2C2_CLK_DISABLE(); + 258:Core/Src/stm32f3xx_hal_msp.c **** + 259:Core/Src/stm32f3xx_hal_msp.c **** /**I2C2 GPIO Configuration + 260:Core/Src/stm32f3xx_hal_msp.c **** PA9 ------> I2C2_SCL + 261:Core/Src/stm32f3xx_hal_msp.c **** PA10 ------> I2C2_SDA + 262:Core/Src/stm32f3xx_hal_msp.c **** */ + 263:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_DeInit(EEPROM_SCL_GPIO_Port, EEPROM_SCL_Pin); + 264:Core/Src/stm32f3xx_hal_msp.c **** + 265:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_DeInit(EEPROM_SDA_GPIO_Port, EEPROM_SDA_Pin); + 266:Core/Src/stm32f3xx_hal_msp.c **** + 267:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN I2C2_MspDeInit 1 */ + 268:Core/Src/stm32f3xx_hal_msp.c **** + 269:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END I2C2_MspDeInit 1 */ + 270:Core/Src/stm32f3xx_hal_msp.c **** } + 271:Core/Src/stm32f3xx_hal_msp.c **** + 272:Core/Src/stm32f3xx_hal_msp.c **** } + 497 .loc 1 272 1 + 498 0034 16E0 b .L23 + 499 .L21: + 251:Core/Src/stm32f3xx_hal_msp.c **** { + 500 .loc 1 251 15 + 501 0036 7B68 ldr r3, [r7, #4] + 502 0038 1B68 ldr r3, [r3] + 251:Core/Src/stm32f3xx_hal_msp.c **** { + 503 .loc 1 251 10 + 504 003a 0F4A ldr r2, .L24+12 + 505 003c 9342 cmp r3, r2 + 506 003e 11D1 bne .L23 + 257:Core/Src/stm32f3xx_hal_msp.c **** + 507 .loc 1 257 5 + 508 0040 0B4B ldr r3, .L24+4 + 509 0042 DB69 ldr r3, [r3, #28] + 510 0044 0A4A ldr r2, .L24+4 + 511 0046 23F48003 bic r3, r3, #4194304 + 512 004a D361 str r3, [r2, #28] + 263:Core/Src/stm32f3xx_hal_msp.c **** + 513 .loc 1 263 5 + 514 004c 4FF40071 mov r1, #512 + 515 0050 4FF09040 mov r0, #1207959552 + 516 0054 FFF7FEFF bl HAL_GPIO_DeInit + 265:Core/Src/stm32f3xx_hal_msp.c **** + 517 .loc 1 265 5 + 518 0058 4FF48061 mov r1, #1024 + 519 005c 4FF09040 mov r0, #1207959552 + 520 0060 FFF7FEFF bl HAL_GPIO_DeInit + ARM GAS /tmp/cc61sY4U.s page 15 + + + 521 .L23: + 522 .loc 1 272 1 + 523 0064 00BF nop + 524 0066 0837 adds r7, r7, #8 + 525 .cfi_def_cfa_offset 8 + 526 0068 BD46 mov sp, r7 + 527 .cfi_def_cfa_register 13 + 528 @ sp needed + 529 006a 80BD pop {r7, pc} + 530 .L25: + 531 .align 2 + 532 .L24: + 533 006c 00540040 .word 1073763328 + 534 0070 00100240 .word 1073876992 + 535 0074 00040048 .word 1207960576 + 536 0078 00580040 .word 1073764352 + 537 .cfi_endproc + 538 .LFE134: + 540 .section .text.HAL_SPI_MspInit,"ax",%progbits + 541 .align 1 + 542 .global HAL_SPI_MspInit + 543 .syntax unified + 544 .thumb + 545 .thumb_func + 547 HAL_SPI_MspInit: + 548 .LFB135: + 273:Core/Src/stm32f3xx_hal_msp.c **** + 274:Core/Src/stm32f3xx_hal_msp.c **** /** + 275:Core/Src/stm32f3xx_hal_msp.c **** * @brief SPI MSP Initialization + 276:Core/Src/stm32f3xx_hal_msp.c **** * This function configures the hardware resources used in this example + 277:Core/Src/stm32f3xx_hal_msp.c **** * @param hspi: SPI handle pointer + 278:Core/Src/stm32f3xx_hal_msp.c **** * @retval None + 279:Core/Src/stm32f3xx_hal_msp.c **** */ + 280:Core/Src/stm32f3xx_hal_msp.c **** void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) + 281:Core/Src/stm32f3xx_hal_msp.c **** { + 549 .loc 1 281 1 + 550 .cfi_startproc + 551 @ args = 0, pretend = 0, frame = 40 + 552 @ frame_needed = 1, uses_anonymous_args = 0 + 553 0000 80B5 push {r7, lr} + 554 .cfi_def_cfa_offset 8 + 555 .cfi_offset 7, -8 + 556 .cfi_offset 14, -4 + 557 0002 8AB0 sub sp, sp, #40 + 558 .cfi_def_cfa_offset 48 + 559 0004 00AF add r7, sp, #0 + 560 .cfi_def_cfa_register 7 + 561 0006 7860 str r0, [r7, #4] + 282:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitTypeDef GPIO_InitStruct = {0}; + 562 .loc 1 282 20 + 563 0008 07F11403 add r3, r7, #20 + 564 000c 0022 movs r2, #0 + 565 000e 1A60 str r2, [r3] + 566 0010 5A60 str r2, [r3, #4] + 567 0012 9A60 str r2, [r3, #8] + 568 0014 DA60 str r2, [r3, #12] + 569 0016 1A61 str r2, [r3, #16] + ARM GAS /tmp/cc61sY4U.s page 16 + + + 283:Core/Src/stm32f3xx_hal_msp.c **** if(hspi->Instance==SPI1) + 570 .loc 1 283 10 + 571 0018 7B68 ldr r3, [r7, #4] + 572 001a 1B68 ldr r3, [r3] + 573 .loc 1 283 5 + 574 001c 174A ldr r2, .L29 + 575 001e 9342 cmp r3, r2 + 576 0020 28D1 bne .L28 + 577 .LBB11: + 284:Core/Src/stm32f3xx_hal_msp.c **** { + 285:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN SPI1_MspInit 0 */ + 286:Core/Src/stm32f3xx_hal_msp.c **** + 287:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END SPI1_MspInit 0 */ + 288:Core/Src/stm32f3xx_hal_msp.c **** /* Peripheral clock enable */ + 289:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_SPI1_CLK_ENABLE(); + 578 .loc 1 289 5 + 579 0022 174B ldr r3, .L29+4 + 580 0024 9B69 ldr r3, [r3, #24] + 581 0026 164A ldr r2, .L29+4 + 582 0028 43F48053 orr r3, r3, #4096 + 583 002c 9361 str r3, [r2, #24] + 584 002e 144B ldr r3, .L29+4 + 585 0030 9B69 ldr r3, [r3, #24] + 586 0032 03F48053 and r3, r3, #4096 + 587 0036 3B61 str r3, [r7, #16] + 588 0038 3B69 ldr r3, [r7, #16] + 589 .LBE11: + 590 .LBB12: + 290:Core/Src/stm32f3xx_hal_msp.c **** + 291:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_GPIOA_CLK_ENABLE(); + 591 .loc 1 291 5 + 592 003a 114B ldr r3, .L29+4 + 593 003c 5B69 ldr r3, [r3, #20] + 594 003e 104A ldr r2, .L29+4 + 595 0040 43F40033 orr r3, r3, #131072 + 596 0044 5361 str r3, [r2, #20] + 597 0046 0E4B ldr r3, .L29+4 + 598 0048 5B69 ldr r3, [r3, #20] + 599 004a 03F40033 and r3, r3, #131072 + 600 004e FB60 str r3, [r7, #12] + 601 0050 FB68 ldr r3, [r7, #12] + 602 .LBE12: + 292:Core/Src/stm32f3xx_hal_msp.c **** /**SPI1 GPIO Configuration + 293:Core/Src/stm32f3xx_hal_msp.c **** PA5 ------> SPI1_SCK + 294:Core/Src/stm32f3xx_hal_msp.c **** PA6 ------> SPI1_MISO + 295:Core/Src/stm32f3xx_hal_msp.c **** PA7 ------> SPI1_MOSI + 296:Core/Src/stm32f3xx_hal_msp.c **** */ + 297:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; + 603 .loc 1 297 25 + 604 0052 E023 movs r3, #224 + 605 0054 7B61 str r3, [r7, #20] + 298:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 606 .loc 1 298 26 + 607 0056 0223 movs r3, #2 + 608 0058 BB61 str r3, [r7, #24] + 299:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 609 .loc 1 299 26 + ARM GAS /tmp/cc61sY4U.s page 17 + + + 610 005a 0023 movs r3, #0 + 611 005c FB61 str r3, [r7, #28] + 300:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + 612 .loc 1 300 27 + 613 005e 0323 movs r3, #3 + 614 0060 3B62 str r3, [r7, #32] + 301:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF5_SPI1; + 615 .loc 1 301 31 + 616 0062 0523 movs r3, #5 + 617 0064 7B62 str r3, [r7, #36] + 302:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 618 .loc 1 302 5 + 619 0066 07F11403 add r3, r7, #20 + 620 006a 1946 mov r1, r3 + 621 006c 4FF09040 mov r0, #1207959552 + 622 0070 FFF7FEFF bl HAL_GPIO_Init + 623 .L28: + 303:Core/Src/stm32f3xx_hal_msp.c **** + 304:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN SPI1_MspInit 1 */ + 305:Core/Src/stm32f3xx_hal_msp.c **** + 306:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END SPI1_MspInit 1 */ + 307:Core/Src/stm32f3xx_hal_msp.c **** } + 308:Core/Src/stm32f3xx_hal_msp.c **** + 309:Core/Src/stm32f3xx_hal_msp.c **** } + 624 .loc 1 309 1 + 625 0074 00BF nop + 626 0076 2837 adds r7, r7, #40 + 627 .cfi_def_cfa_offset 8 + 628 0078 BD46 mov sp, r7 + 629 .cfi_def_cfa_register 13 + 630 @ sp needed + 631 007a 80BD pop {r7, pc} + 632 .L30: + 633 .align 2 + 634 .L29: + 635 007c 00300140 .word 1073819648 + 636 0080 00100240 .word 1073876992 + 637 .cfi_endproc + 638 .LFE135: + 640 .section .text.HAL_SPI_MspDeInit,"ax",%progbits + 641 .align 1 + 642 .global HAL_SPI_MspDeInit + 643 .syntax unified + 644 .thumb + 645 .thumb_func + 647 HAL_SPI_MspDeInit: + 648 .LFB136: + 310:Core/Src/stm32f3xx_hal_msp.c **** + 311:Core/Src/stm32f3xx_hal_msp.c **** /** + 312:Core/Src/stm32f3xx_hal_msp.c **** * @brief SPI MSP De-Initialization + 313:Core/Src/stm32f3xx_hal_msp.c **** * This function freeze the hardware resources used in this example + 314:Core/Src/stm32f3xx_hal_msp.c **** * @param hspi: SPI handle pointer + 315:Core/Src/stm32f3xx_hal_msp.c **** * @retval None + 316:Core/Src/stm32f3xx_hal_msp.c **** */ + 317:Core/Src/stm32f3xx_hal_msp.c **** void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) + 318:Core/Src/stm32f3xx_hal_msp.c **** { + 649 .loc 1 318 1 + ARM GAS /tmp/cc61sY4U.s page 18 + + + 650 .cfi_startproc + 651 @ args = 0, pretend = 0, frame = 8 + 652 @ frame_needed = 1, uses_anonymous_args = 0 + 653 0000 80B5 push {r7, lr} + 654 .cfi_def_cfa_offset 8 + 655 .cfi_offset 7, -8 + 656 .cfi_offset 14, -4 + 657 0002 82B0 sub sp, sp, #8 + 658 .cfi_def_cfa_offset 16 + 659 0004 00AF add r7, sp, #0 + 660 .cfi_def_cfa_register 7 + 661 0006 7860 str r0, [r7, #4] + 319:Core/Src/stm32f3xx_hal_msp.c **** if(hspi->Instance==SPI1) + 662 .loc 1 319 10 + 663 0008 7B68 ldr r3, [r7, #4] + 664 000a 1B68 ldr r3, [r3] + 665 .loc 1 319 5 + 666 000c 084A ldr r2, .L34 + 667 000e 9342 cmp r3, r2 + 668 0010 0AD1 bne .L33 + 320:Core/Src/stm32f3xx_hal_msp.c **** { + 321:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN SPI1_MspDeInit 0 */ + 322:Core/Src/stm32f3xx_hal_msp.c **** + 323:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END SPI1_MspDeInit 0 */ + 324:Core/Src/stm32f3xx_hal_msp.c **** /* Peripheral clock disable */ + 325:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_SPI1_CLK_DISABLE(); + 669 .loc 1 325 5 + 670 0012 084B ldr r3, .L34+4 + 671 0014 9B69 ldr r3, [r3, #24] + 672 0016 074A ldr r2, .L34+4 + 673 0018 23F48053 bic r3, r3, #4096 + 674 001c 9361 str r3, [r2, #24] + 326:Core/Src/stm32f3xx_hal_msp.c **** + 327:Core/Src/stm32f3xx_hal_msp.c **** /**SPI1 GPIO Configuration + 328:Core/Src/stm32f3xx_hal_msp.c **** PA5 ------> SPI1_SCK + 329:Core/Src/stm32f3xx_hal_msp.c **** PA6 ------> SPI1_MISO + 330:Core/Src/stm32f3xx_hal_msp.c **** PA7 ------> SPI1_MOSI + 331:Core/Src/stm32f3xx_hal_msp.c **** */ + 332:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7); + 675 .loc 1 332 5 + 676 001e E021 movs r1, #224 + 677 0020 4FF09040 mov r0, #1207959552 + 678 0024 FFF7FEFF bl HAL_GPIO_DeInit + 679 .L33: + 333:Core/Src/stm32f3xx_hal_msp.c **** + 334:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN SPI1_MspDeInit 1 */ + 335:Core/Src/stm32f3xx_hal_msp.c **** + 336:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END SPI1_MspDeInit 1 */ + 337:Core/Src/stm32f3xx_hal_msp.c **** } + 338:Core/Src/stm32f3xx_hal_msp.c **** + 339:Core/Src/stm32f3xx_hal_msp.c **** } + 680 .loc 1 339 1 + 681 0028 00BF nop + 682 002a 0837 adds r7, r7, #8 + 683 .cfi_def_cfa_offset 8 + 684 002c BD46 mov sp, r7 + 685 .cfi_def_cfa_register 13 + ARM GAS /tmp/cc61sY4U.s page 19 + + + 686 @ sp needed + 687 002e 80BD pop {r7, pc} + 688 .L35: + 689 .align 2 + 690 .L34: + 691 0030 00300140 .word 1073819648 + 692 0034 00100240 .word 1073876992 + 693 .cfi_endproc + 694 .LFE136: + 696 .section .text.HAL_TIM_PWM_MspInit,"ax",%progbits + 697 .align 1 + 698 .global HAL_TIM_PWM_MspInit + 699 .syntax unified + 700 .thumb + 701 .thumb_func + 703 HAL_TIM_PWM_MspInit: + 704 .LFB137: + 340:Core/Src/stm32f3xx_hal_msp.c **** + 341:Core/Src/stm32f3xx_hal_msp.c **** /** + 342:Core/Src/stm32f3xx_hal_msp.c **** * @brief TIM_PWM MSP Initialization + 343:Core/Src/stm32f3xx_hal_msp.c **** * This function configures the hardware resources used in this example + 344:Core/Src/stm32f3xx_hal_msp.c **** * @param htim_pwm: TIM_PWM handle pointer + 345:Core/Src/stm32f3xx_hal_msp.c **** * @retval None + 346:Core/Src/stm32f3xx_hal_msp.c **** */ + 347:Core/Src/stm32f3xx_hal_msp.c **** void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* htim_pwm) + 348:Core/Src/stm32f3xx_hal_msp.c **** { + 705 .loc 1 348 1 + 706 .cfi_startproc + 707 @ args = 0, pretend = 0, frame = 24 + 708 @ frame_needed = 1, uses_anonymous_args = 0 + 709 @ link register save eliminated. + 710 0000 80B4 push {r7} + 711 .cfi_def_cfa_offset 4 + 712 .cfi_offset 7, -4 + 713 0002 87B0 sub sp, sp, #28 + 714 .cfi_def_cfa_offset 32 + 715 0004 00AF add r7, sp, #0 + 716 .cfi_def_cfa_register 7 + 717 0006 7860 str r0, [r7, #4] + 349:Core/Src/stm32f3xx_hal_msp.c **** if(htim_pwm->Instance==TIM2) + 718 .loc 1 349 14 + 719 0008 7B68 ldr r3, [r7, #4] + 720 000a 1B68 ldr r3, [r3] + 721 .loc 1 349 5 + 722 000c B3F1804F cmp r3, #1073741824 + 723 0010 0CD1 bne .L37 + 724 .LBB13: + 350:Core/Src/stm32f3xx_hal_msp.c **** { + 351:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM2_MspInit 0 */ + 352:Core/Src/stm32f3xx_hal_msp.c **** + 353:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END TIM2_MspInit 0 */ + 354:Core/Src/stm32f3xx_hal_msp.c **** /* Peripheral clock enable */ + 355:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_TIM2_CLK_ENABLE(); + 725 .loc 1 355 5 + 726 0012 244B ldr r3, .L42 + 727 0014 DB69 ldr r3, [r3, #28] + 728 0016 234A ldr r2, .L42 + ARM GAS /tmp/cc61sY4U.s page 20 + + + 729 0018 43F00103 orr r3, r3, #1 + 730 001c D361 str r3, [r2, #28] + 731 001e 214B ldr r3, .L42 + 732 0020 DB69 ldr r3, [r3, #28] + 733 0022 03F00103 and r3, r3, #1 + 734 0026 7B61 str r3, [r7, #20] + 735 0028 7B69 ldr r3, [r7, #20] + 736 .LBE13: + 356:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM2_MspInit 1 */ + 357:Core/Src/stm32f3xx_hal_msp.c **** + 358:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END TIM2_MspInit 1 */ + 359:Core/Src/stm32f3xx_hal_msp.c **** } + 360:Core/Src/stm32f3xx_hal_msp.c **** else if(htim_pwm->Instance==TIM3) + 361:Core/Src/stm32f3xx_hal_msp.c **** { + 362:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM3_MspInit 0 */ + 363:Core/Src/stm32f3xx_hal_msp.c **** + 364:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END TIM3_MspInit 0 */ + 365:Core/Src/stm32f3xx_hal_msp.c **** /* Peripheral clock enable */ + 366:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_TIM3_CLK_ENABLE(); + 367:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM3_MspInit 1 */ + 368:Core/Src/stm32f3xx_hal_msp.c **** + 369:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END TIM3_MspInit 1 */ + 370:Core/Src/stm32f3xx_hal_msp.c **** } + 371:Core/Src/stm32f3xx_hal_msp.c **** else if(htim_pwm->Instance==TIM4) + 372:Core/Src/stm32f3xx_hal_msp.c **** { + 373:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM4_MspInit 0 */ + 374:Core/Src/stm32f3xx_hal_msp.c **** + 375:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END TIM4_MspInit 0 */ + 376:Core/Src/stm32f3xx_hal_msp.c **** /* Peripheral clock enable */ + 377:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_TIM4_CLK_ENABLE(); + 378:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM4_MspInit 1 */ + 379:Core/Src/stm32f3xx_hal_msp.c **** + 380:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END TIM4_MspInit 1 */ + 381:Core/Src/stm32f3xx_hal_msp.c **** } + 382:Core/Src/stm32f3xx_hal_msp.c **** else if(htim_pwm->Instance==TIM15) + 383:Core/Src/stm32f3xx_hal_msp.c **** { + 384:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM15_MspInit 0 */ + 385:Core/Src/stm32f3xx_hal_msp.c **** + 386:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END TIM15_MspInit 0 */ + 387:Core/Src/stm32f3xx_hal_msp.c **** /* Peripheral clock enable */ + 388:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_TIM15_CLK_ENABLE(); + 389:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM15_MspInit 1 */ + 390:Core/Src/stm32f3xx_hal_msp.c **** + 391:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END TIM15_MspInit 1 */ + 392:Core/Src/stm32f3xx_hal_msp.c **** } + 393:Core/Src/stm32f3xx_hal_msp.c **** + 394:Core/Src/stm32f3xx_hal_msp.c **** } + 737 .loc 1 394 1 + 738 002a 34E0 b .L41 + 739 .L37: + 360:Core/Src/stm32f3xx_hal_msp.c **** { + 740 .loc 1 360 19 + 741 002c 7B68 ldr r3, [r7, #4] + 742 002e 1B68 ldr r3, [r3] + 360:Core/Src/stm32f3xx_hal_msp.c **** { + 743 .loc 1 360 10 + 744 0030 1D4A ldr r2, .L42+4 + ARM GAS /tmp/cc61sY4U.s page 21 + + + 745 0032 9342 cmp r3, r2 + 746 0034 0CD1 bne .L39 + 747 .LBB14: + 366:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM3_MspInit 1 */ + 748 .loc 1 366 5 + 749 0036 1B4B ldr r3, .L42 + 750 0038 DB69 ldr r3, [r3, #28] + 751 003a 1A4A ldr r2, .L42 + 752 003c 43F00203 orr r3, r3, #2 + 753 0040 D361 str r3, [r2, #28] + 754 0042 184B ldr r3, .L42 + 755 0044 DB69 ldr r3, [r3, #28] + 756 0046 03F00203 and r3, r3, #2 + 757 004a 3B61 str r3, [r7, #16] + 758 004c 3B69 ldr r3, [r7, #16] + 759 .LBE14: + 760 .loc 1 394 1 + 761 004e 22E0 b .L41 + 762 .L39: + 371:Core/Src/stm32f3xx_hal_msp.c **** { + 763 .loc 1 371 19 + 764 0050 7B68 ldr r3, [r7, #4] + 765 0052 1B68 ldr r3, [r3] + 371:Core/Src/stm32f3xx_hal_msp.c **** { + 766 .loc 1 371 10 + 767 0054 154A ldr r2, .L42+8 + 768 0056 9342 cmp r3, r2 + 769 0058 0CD1 bne .L40 + 770 .LBB15: + 377:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM4_MspInit 1 */ + 771 .loc 1 377 5 + 772 005a 124B ldr r3, .L42 + 773 005c DB69 ldr r3, [r3, #28] + 774 005e 114A ldr r2, .L42 + 775 0060 43F00403 orr r3, r3, #4 + 776 0064 D361 str r3, [r2, #28] + 777 0066 0F4B ldr r3, .L42 + 778 0068 DB69 ldr r3, [r3, #28] + 779 006a 03F00403 and r3, r3, #4 + 780 006e FB60 str r3, [r7, #12] + 781 0070 FB68 ldr r3, [r7, #12] + 782 .LBE15: + 783 .loc 1 394 1 + 784 0072 10E0 b .L41 + 785 .L40: + 382:Core/Src/stm32f3xx_hal_msp.c **** { + 786 .loc 1 382 19 + 787 0074 7B68 ldr r3, [r7, #4] + 788 0076 1B68 ldr r3, [r3] + 382:Core/Src/stm32f3xx_hal_msp.c **** { + 789 .loc 1 382 10 + 790 0078 0D4A ldr r2, .L42+12 + 791 007a 9342 cmp r3, r2 + 792 007c 0BD1 bne .L41 + 793 .LBB16: + 388:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM15_MspInit 1 */ + 794 .loc 1 388 5 + ARM GAS /tmp/cc61sY4U.s page 22 + + + 795 007e 094B ldr r3, .L42 + 796 0080 9B69 ldr r3, [r3, #24] + 797 0082 084A ldr r2, .L42 + 798 0084 43F48033 orr r3, r3, #65536 + 799 0088 9361 str r3, [r2, #24] + 800 008a 064B ldr r3, .L42 + 801 008c 9B69 ldr r3, [r3, #24] + 802 008e 03F48033 and r3, r3, #65536 + 803 0092 BB60 str r3, [r7, #8] + 804 0094 BB68 ldr r3, [r7, #8] + 805 .L41: + 806 .LBE16: + 807 .loc 1 394 1 + 808 0096 00BF nop + 809 0098 1C37 adds r7, r7, #28 + 810 .cfi_def_cfa_offset 4 + 811 009a BD46 mov sp, r7 + 812 .cfi_def_cfa_register 13 + 813 @ sp needed + 814 009c 5DF8047B ldr r7, [sp], #4 + 815 .cfi_restore 7 + 816 .cfi_def_cfa_offset 0 + 817 00a0 7047 bx lr + 818 .L43: + 819 00a2 00BF .align 2 + 820 .L42: + 821 00a4 00100240 .word 1073876992 + 822 00a8 00040040 .word 1073742848 + 823 00ac 00080040 .word 1073743872 + 824 00b0 00400140 .word 1073823744 + 825 .cfi_endproc + 826 .LFE137: + 828 .section .text.HAL_TIM_MspPostInit,"ax",%progbits + 829 .align 1 + 830 .global HAL_TIM_MspPostInit + 831 .syntax unified + 832 .thumb + 833 .thumb_func + 835 HAL_TIM_MspPostInit: + 836 .LFB138: + 395:Core/Src/stm32f3xx_hal_msp.c **** + 396:Core/Src/stm32f3xx_hal_msp.c **** void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) + 397:Core/Src/stm32f3xx_hal_msp.c **** { + 837 .loc 1 397 1 + 838 .cfi_startproc + 839 @ args = 0, pretend = 0, frame = 48 + 840 @ frame_needed = 1, uses_anonymous_args = 0 + 841 0000 80B5 push {r7, lr} + 842 .cfi_def_cfa_offset 8 + 843 .cfi_offset 7, -8 + 844 .cfi_offset 14, -4 + 845 0002 8CB0 sub sp, sp, #48 + 846 .cfi_def_cfa_offset 56 + 847 0004 00AF add r7, sp, #0 + 848 .cfi_def_cfa_register 7 + 849 0006 7860 str r0, [r7, #4] + 398:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitTypeDef GPIO_InitStruct = {0}; + ARM GAS /tmp/cc61sY4U.s page 23 + + + 850 .loc 1 398 20 + 851 0008 07F11C03 add r3, r7, #28 + 852 000c 0022 movs r2, #0 + 853 000e 1A60 str r2, [r3] + 854 0010 5A60 str r2, [r3, #4] + 855 0012 9A60 str r2, [r3, #8] + 856 0014 DA60 str r2, [r3, #12] + 857 0016 1A61 str r2, [r3, #16] + 399:Core/Src/stm32f3xx_hal_msp.c **** if(htim->Instance==TIM2) + 858 .loc 1 399 10 + 859 0018 7B68 ldr r3, [r7, #4] + 860 001a 1B68 ldr r3, [r3] + 861 .loc 1 399 5 + 862 001c B3F1804F cmp r3, #1073741824 + 863 0020 1DD1 bne .L45 + 864 .LBB17: + 400:Core/Src/stm32f3xx_hal_msp.c **** { + 401:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM2_MspPostInit 0 */ + 402:Core/Src/stm32f3xx_hal_msp.c **** + 403:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END TIM2_MspPostInit 0 */ + 404:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); + 865 .loc 1 404 5 + 866 0022 444B ldr r3, .L50 + 867 0024 5B69 ldr r3, [r3, #20] + 868 0026 434A ldr r2, .L50 + 869 0028 43F48023 orr r3, r3, #262144 + 870 002c 5361 str r3, [r2, #20] + 871 002e 414B ldr r3, .L50 + 872 0030 5B69 ldr r3, [r3, #20] + 873 0032 03F48023 and r3, r3, #262144 + 874 0036 BB61 str r3, [r7, #24] + 875 0038 BB69 ldr r3, [r7, #24] + 876 .LBE17: + 405:Core/Src/stm32f3xx_hal_msp.c **** /**TIM2 GPIO Configuration + 406:Core/Src/stm32f3xx_hal_msp.c **** PB10 ------> TIM2_CH3 + 407:Core/Src/stm32f3xx_hal_msp.c **** PB11 ------> TIM2_CH4 + 408:Core/Src/stm32f3xx_hal_msp.c **** */ + 409:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pin = BAT_COOLING_PWM_Pin|BAT_COOLING_ENABLE_Pin; + 877 .loc 1 409 25 + 878 003a 4FF44063 mov r3, #3072 + 879 003e FB61 str r3, [r7, #28] + 410:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 880 .loc 1 410 26 + 881 0040 0223 movs r3, #2 + 882 0042 3B62 str r3, [r7, #32] + 411:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 883 .loc 1 411 26 + 884 0044 0023 movs r3, #0 + 885 0046 7B62 str r3, [r7, #36] + 412:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 886 .loc 1 412 27 + 887 0048 0023 movs r3, #0 + 888 004a BB62 str r3, [r7, #40] + 413:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF1_TIM2; + 889 .loc 1 413 31 + 890 004c 0123 movs r3, #1 + 891 004e FB62 str r3, [r7, #44] + ARM GAS /tmp/cc61sY4U.s page 24 + + + 414:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 892 .loc 1 414 5 + 893 0050 07F11C03 add r3, r7, #28 + 894 0054 1946 mov r1, r3 + 895 0056 3848 ldr r0, .L50+4 + 896 0058 FFF7FEFF bl HAL_GPIO_Init + 415:Core/Src/stm32f3xx_hal_msp.c **** + 416:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM2_MspPostInit 1 */ + 417:Core/Src/stm32f3xx_hal_msp.c **** + 418:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END TIM2_MspPostInit 1 */ + 419:Core/Src/stm32f3xx_hal_msp.c **** } + 420:Core/Src/stm32f3xx_hal_msp.c **** else if(htim->Instance==TIM3) + 421:Core/Src/stm32f3xx_hal_msp.c **** { + 422:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM3_MspPostInit 0 */ + 423:Core/Src/stm32f3xx_hal_msp.c **** + 424:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END TIM3_MspPostInit 0 */ + 425:Core/Src/stm32f3xx_hal_msp.c **** + 426:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); + 427:Core/Src/stm32f3xx_hal_msp.c **** /**TIM3 GPIO Configuration + 428:Core/Src/stm32f3xx_hal_msp.c **** PB0 ------> TIM3_CH3 + 429:Core/Src/stm32f3xx_hal_msp.c **** PB1 ------> TIM3_CH4 + 430:Core/Src/stm32f3xx_hal_msp.c **** */ + 431:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pin = ESC_L_PWM_Pin|ESC_R_PWM_Pin; + 432:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 433:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 434:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 435:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF2_TIM3; + 436:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 437:Core/Src/stm32f3xx_hal_msp.c **** + 438:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM3_MspPostInit 1 */ + 439:Core/Src/stm32f3xx_hal_msp.c **** + 440:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END TIM3_MspPostInit 1 */ + 441:Core/Src/stm32f3xx_hal_msp.c **** } + 442:Core/Src/stm32f3xx_hal_msp.c **** else if(htim->Instance==TIM4) + 443:Core/Src/stm32f3xx_hal_msp.c **** { + 444:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM4_MspPostInit 0 */ + 445:Core/Src/stm32f3xx_hal_msp.c **** + 446:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END TIM4_MspPostInit 0 */ + 447:Core/Src/stm32f3xx_hal_msp.c **** + 448:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); + 449:Core/Src/stm32f3xx_hal_msp.c **** /**TIM4 GPIO Configuration + 450:Core/Src/stm32f3xx_hal_msp.c **** PB6 ------> TIM4_CH1 + 451:Core/Src/stm32f3xx_hal_msp.c **** PB7 ------> TIM4_CH2 + 452:Core/Src/stm32f3xx_hal_msp.c **** PB8 ------> TIM4_CH3 + 453:Core/Src/stm32f3xx_hal_msp.c **** */ + 454:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pin = STATUS_LED_R_Pin|STATUS_LED_G_Pin|STATUS_LED_B_Pin; + 455:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 456:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_PULLDOWN; + 457:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 458:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF2_TIM4; + 459:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 460:Core/Src/stm32f3xx_hal_msp.c **** + 461:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM4_MspPostInit 1 */ + 462:Core/Src/stm32f3xx_hal_msp.c **** + 463:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END TIM4_MspPostInit 1 */ + 464:Core/Src/stm32f3xx_hal_msp.c **** } + 465:Core/Src/stm32f3xx_hal_msp.c **** else if(htim->Instance==TIM15) + ARM GAS /tmp/cc61sY4U.s page 25 + + + 466:Core/Src/stm32f3xx_hal_msp.c **** { + 467:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM15_MspPostInit 0 */ + 468:Core/Src/stm32f3xx_hal_msp.c **** + 469:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END TIM15_MspPostInit 0 */ + 470:Core/Src/stm32f3xx_hal_msp.c **** + 471:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); + 472:Core/Src/stm32f3xx_hal_msp.c **** /**TIM15 GPIO Configuration + 473:Core/Src/stm32f3xx_hal_msp.c **** PB14 ------> TIM15_CH1 + 474:Core/Src/stm32f3xx_hal_msp.c **** PB15 ------> TIM15_CH2 + 475:Core/Src/stm32f3xx_hal_msp.c **** */ + 476:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pin = ESC_COOLING_ENABLE_Pin|ESC_COOLING_PWM_Pin; + 477:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 478:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 479:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 480:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF1_TIM15; + 481:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 482:Core/Src/stm32f3xx_hal_msp.c **** + 483:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM15_MspPostInit 1 */ + 484:Core/Src/stm32f3xx_hal_msp.c **** + 485:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END TIM15_MspPostInit 1 */ + 486:Core/Src/stm32f3xx_hal_msp.c **** } + 487:Core/Src/stm32f3xx_hal_msp.c **** + 488:Core/Src/stm32f3xx_hal_msp.c **** } + 897 .loc 1 488 1 + 898 005c 66E0 b .L49 + 899 .L45: + 420:Core/Src/stm32f3xx_hal_msp.c **** { + 900 .loc 1 420 15 + 901 005e 7B68 ldr r3, [r7, #4] + 902 0060 1B68 ldr r3, [r3] + 420:Core/Src/stm32f3xx_hal_msp.c **** { + 903 .loc 1 420 10 + 904 0062 364A ldr r2, .L50+8 + 905 0064 9342 cmp r3, r2 + 906 0066 1CD1 bne .L47 + 907 .LBB18: + 426:Core/Src/stm32f3xx_hal_msp.c **** /**TIM3 GPIO Configuration + 908 .loc 1 426 5 + 909 0068 324B ldr r3, .L50 + 910 006a 5B69 ldr r3, [r3, #20] + 911 006c 314A ldr r2, .L50 + 912 006e 43F48023 orr r3, r3, #262144 + 913 0072 5361 str r3, [r2, #20] + 914 0074 2F4B ldr r3, .L50 + 915 0076 5B69 ldr r3, [r3, #20] + 916 0078 03F48023 and r3, r3, #262144 + 917 007c 7B61 str r3, [r7, #20] + 918 007e 7B69 ldr r3, [r7, #20] + 919 .LBE18: + 431:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 920 .loc 1 431 25 + 921 0080 0323 movs r3, #3 + 922 0082 FB61 str r3, [r7, #28] + 432:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 923 .loc 1 432 26 + 924 0084 0223 movs r3, #2 + 925 0086 3B62 str r3, [r7, #32] + ARM GAS /tmp/cc61sY4U.s page 26 + + + 433:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 926 .loc 1 433 26 + 927 0088 0023 movs r3, #0 + 928 008a 7B62 str r3, [r7, #36] + 434:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF2_TIM3; + 929 .loc 1 434 27 + 930 008c 0023 movs r3, #0 + 931 008e BB62 str r3, [r7, #40] + 435:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 932 .loc 1 435 31 + 933 0090 0223 movs r3, #2 + 934 0092 FB62 str r3, [r7, #44] + 436:Core/Src/stm32f3xx_hal_msp.c **** + 935 .loc 1 436 5 + 936 0094 07F11C03 add r3, r7, #28 + 937 0098 1946 mov r1, r3 + 938 009a 2748 ldr r0, .L50+4 + 939 009c FFF7FEFF bl HAL_GPIO_Init + 940 .loc 1 488 1 + 941 00a0 44E0 b .L49 + 942 .L47: + 442:Core/Src/stm32f3xx_hal_msp.c **** { + 943 .loc 1 442 15 + 944 00a2 7B68 ldr r3, [r7, #4] + 945 00a4 1B68 ldr r3, [r3] + 442:Core/Src/stm32f3xx_hal_msp.c **** { + 946 .loc 1 442 10 + 947 00a6 264A ldr r2, .L50+12 + 948 00a8 9342 cmp r3, r2 + 949 00aa 1DD1 bne .L48 + 950 .LBB19: + 448:Core/Src/stm32f3xx_hal_msp.c **** /**TIM4 GPIO Configuration + 951 .loc 1 448 5 + 952 00ac 214B ldr r3, .L50 + 953 00ae 5B69 ldr r3, [r3, #20] + 954 00b0 204A ldr r2, .L50 + 955 00b2 43F48023 orr r3, r3, #262144 + 956 00b6 5361 str r3, [r2, #20] + 957 00b8 1E4B ldr r3, .L50 + 958 00ba 5B69 ldr r3, [r3, #20] + 959 00bc 03F48023 and r3, r3, #262144 + 960 00c0 3B61 str r3, [r7, #16] + 961 00c2 3B69 ldr r3, [r7, #16] + 962 .LBE19: + 454:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 963 .loc 1 454 25 + 964 00c4 4FF4E073 mov r3, #448 + 965 00c8 FB61 str r3, [r7, #28] + 455:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_PULLDOWN; + 966 .loc 1 455 26 + 967 00ca 0223 movs r3, #2 + 968 00cc 3B62 str r3, [r7, #32] + 456:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 969 .loc 1 456 26 + 970 00ce 0223 movs r3, #2 + 971 00d0 7B62 str r3, [r7, #36] + 457:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF2_TIM4; + ARM GAS /tmp/cc61sY4U.s page 27 + + + 972 .loc 1 457 27 + 973 00d2 0023 movs r3, #0 + 974 00d4 BB62 str r3, [r7, #40] + 458:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 975 .loc 1 458 31 + 976 00d6 0223 movs r3, #2 + 977 00d8 FB62 str r3, [r7, #44] + 459:Core/Src/stm32f3xx_hal_msp.c **** + 978 .loc 1 459 5 + 979 00da 07F11C03 add r3, r7, #28 + 980 00de 1946 mov r1, r3 + 981 00e0 1548 ldr r0, .L50+4 + 982 00e2 FFF7FEFF bl HAL_GPIO_Init + 983 .loc 1 488 1 + 984 00e6 21E0 b .L49 + 985 .L48: + 465:Core/Src/stm32f3xx_hal_msp.c **** { + 986 .loc 1 465 15 + 987 00e8 7B68 ldr r3, [r7, #4] + 988 00ea 1B68 ldr r3, [r3] + 465:Core/Src/stm32f3xx_hal_msp.c **** { + 989 .loc 1 465 10 + 990 00ec 154A ldr r2, .L50+16 + 991 00ee 9342 cmp r3, r2 + 992 00f0 1CD1 bne .L49 + 993 .LBB20: + 471:Core/Src/stm32f3xx_hal_msp.c **** /**TIM15 GPIO Configuration + 994 .loc 1 471 5 + 995 00f2 104B ldr r3, .L50 + 996 00f4 5B69 ldr r3, [r3, #20] + 997 00f6 0F4A ldr r2, .L50 + 998 00f8 43F48023 orr r3, r3, #262144 + 999 00fc 5361 str r3, [r2, #20] + 1000 00fe 0D4B ldr r3, .L50 + 1001 0100 5B69 ldr r3, [r3, #20] + 1002 0102 03F48023 and r3, r3, #262144 + 1003 0106 FB60 str r3, [r7, #12] + 1004 0108 FB68 ldr r3, [r7, #12] + 1005 .LBE20: + 476:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 1006 .loc 1 476 25 + 1007 010a 4FF44043 mov r3, #49152 + 1008 010e FB61 str r3, [r7, #28] + 477:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; + 1009 .loc 1 477 26 + 1010 0110 0223 movs r3, #2 + 1011 0112 3B62 str r3, [r7, #32] + 478:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 1012 .loc 1 478 26 + 1013 0114 0023 movs r3, #0 + 1014 0116 7B62 str r3, [r7, #36] + 479:Core/Src/stm32f3xx_hal_msp.c **** GPIO_InitStruct.Alternate = GPIO_AF1_TIM15; + 1015 .loc 1 479 27 + 1016 0118 0023 movs r3, #0 + 1017 011a BB62 str r3, [r7, #40] + 480:Core/Src/stm32f3xx_hal_msp.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 1018 .loc 1 480 31 + ARM GAS /tmp/cc61sY4U.s page 28 + + + 1019 011c 0123 movs r3, #1 + 1020 011e FB62 str r3, [r7, #44] + 481:Core/Src/stm32f3xx_hal_msp.c **** + 1021 .loc 1 481 5 + 1022 0120 07F11C03 add r3, r7, #28 + 1023 0124 1946 mov r1, r3 + 1024 0126 0448 ldr r0, .L50+4 + 1025 0128 FFF7FEFF bl HAL_GPIO_Init + 1026 .L49: + 1027 .loc 1 488 1 + 1028 012c 00BF nop + 1029 012e 3037 adds r7, r7, #48 + 1030 .cfi_def_cfa_offset 8 + 1031 0130 BD46 mov sp, r7 + 1032 .cfi_def_cfa_register 13 + 1033 @ sp needed + 1034 0132 80BD pop {r7, pc} + 1035 .L51: + 1036 .align 2 + 1037 .L50: + 1038 0134 00100240 .word 1073876992 + 1039 0138 00040048 .word 1207960576 + 1040 013c 00040040 .word 1073742848 + 1041 0140 00080040 .word 1073743872 + 1042 0144 00400140 .word 1073823744 + 1043 .cfi_endproc + 1044 .LFE138: + 1046 .section .text.HAL_TIM_PWM_MspDeInit,"ax",%progbits + 1047 .align 1 + 1048 .global HAL_TIM_PWM_MspDeInit + 1049 .syntax unified + 1050 .thumb + 1051 .thumb_func + 1053 HAL_TIM_PWM_MspDeInit: + 1054 .LFB139: + 489:Core/Src/stm32f3xx_hal_msp.c **** /** + 490:Core/Src/stm32f3xx_hal_msp.c **** * @brief TIM_PWM MSP De-Initialization + 491:Core/Src/stm32f3xx_hal_msp.c **** * This function freeze the hardware resources used in this example + 492:Core/Src/stm32f3xx_hal_msp.c **** * @param htim_pwm: TIM_PWM handle pointer + 493:Core/Src/stm32f3xx_hal_msp.c **** * @retval None + 494:Core/Src/stm32f3xx_hal_msp.c **** */ + 495:Core/Src/stm32f3xx_hal_msp.c **** void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef* htim_pwm) + 496:Core/Src/stm32f3xx_hal_msp.c **** { + 1055 .loc 1 496 1 + 1056 .cfi_startproc + 1057 @ args = 0, pretend = 0, frame = 8 + 1058 @ frame_needed = 1, uses_anonymous_args = 0 + 1059 @ link register save eliminated. + 1060 0000 80B4 push {r7} + 1061 .cfi_def_cfa_offset 4 + 1062 .cfi_offset 7, -4 + 1063 0002 83B0 sub sp, sp, #12 + 1064 .cfi_def_cfa_offset 16 + 1065 0004 00AF add r7, sp, #0 + 1066 .cfi_def_cfa_register 7 + 1067 0006 7860 str r0, [r7, #4] + 497:Core/Src/stm32f3xx_hal_msp.c **** if(htim_pwm->Instance==TIM2) + ARM GAS /tmp/cc61sY4U.s page 29 + + + 1068 .loc 1 497 14 + 1069 0008 7B68 ldr r3, [r7, #4] + 1070 000a 1B68 ldr r3, [r3] + 1071 .loc 1 497 5 + 1072 000c B3F1804F cmp r3, #1073741824 + 1073 0010 06D1 bne .L53 + 498:Core/Src/stm32f3xx_hal_msp.c **** { + 499:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM2_MspDeInit 0 */ + 500:Core/Src/stm32f3xx_hal_msp.c **** + 501:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END TIM2_MspDeInit 0 */ + 502:Core/Src/stm32f3xx_hal_msp.c **** /* Peripheral clock disable */ + 503:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_TIM2_CLK_DISABLE(); + 1074 .loc 1 503 5 + 1075 0012 184B ldr r3, .L58 + 1076 0014 DB69 ldr r3, [r3, #28] + 1077 0016 174A ldr r2, .L58 + 1078 0018 23F00103 bic r3, r3, #1 + 1079 001c D361 str r3, [r2, #28] + 504:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM2_MspDeInit 1 */ + 505:Core/Src/stm32f3xx_hal_msp.c **** + 506:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END TIM2_MspDeInit 1 */ + 507:Core/Src/stm32f3xx_hal_msp.c **** } + 508:Core/Src/stm32f3xx_hal_msp.c **** else if(htim_pwm->Instance==TIM3) + 509:Core/Src/stm32f3xx_hal_msp.c **** { + 510:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM3_MspDeInit 0 */ + 511:Core/Src/stm32f3xx_hal_msp.c **** + 512:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END TIM3_MspDeInit 0 */ + 513:Core/Src/stm32f3xx_hal_msp.c **** /* Peripheral clock disable */ + 514:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_TIM3_CLK_DISABLE(); + 515:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM3_MspDeInit 1 */ + 516:Core/Src/stm32f3xx_hal_msp.c **** + 517:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END TIM3_MspDeInit 1 */ + 518:Core/Src/stm32f3xx_hal_msp.c **** } + 519:Core/Src/stm32f3xx_hal_msp.c **** else if(htim_pwm->Instance==TIM4) + 520:Core/Src/stm32f3xx_hal_msp.c **** { + 521:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM4_MspDeInit 0 */ + 522:Core/Src/stm32f3xx_hal_msp.c **** + 523:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END TIM4_MspDeInit 0 */ + 524:Core/Src/stm32f3xx_hal_msp.c **** /* Peripheral clock disable */ + 525:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_TIM4_CLK_DISABLE(); + 526:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM4_MspDeInit 1 */ + 527:Core/Src/stm32f3xx_hal_msp.c **** + 528:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END TIM4_MspDeInit 1 */ + 529:Core/Src/stm32f3xx_hal_msp.c **** } + 530:Core/Src/stm32f3xx_hal_msp.c **** else if(htim_pwm->Instance==TIM15) + 531:Core/Src/stm32f3xx_hal_msp.c **** { + 532:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM15_MspDeInit 0 */ + 533:Core/Src/stm32f3xx_hal_msp.c **** + 534:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END TIM15_MspDeInit 0 */ + 535:Core/Src/stm32f3xx_hal_msp.c **** /* Peripheral clock disable */ + 536:Core/Src/stm32f3xx_hal_msp.c **** __HAL_RCC_TIM15_CLK_DISABLE(); + 537:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM15_MspDeInit 1 */ + 538:Core/Src/stm32f3xx_hal_msp.c **** + 539:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE END TIM15_MspDeInit 1 */ + 540:Core/Src/stm32f3xx_hal_msp.c **** } + 541:Core/Src/stm32f3xx_hal_msp.c **** + 542:Core/Src/stm32f3xx_hal_msp.c **** } + ARM GAS /tmp/cc61sY4U.s page 30 + + + 1080 .loc 1 542 1 + 1081 001e 22E0 b .L57 + 1082 .L53: + 508:Core/Src/stm32f3xx_hal_msp.c **** { + 1083 .loc 1 508 19 + 1084 0020 7B68 ldr r3, [r7, #4] + 1085 0022 1B68 ldr r3, [r3] + 508:Core/Src/stm32f3xx_hal_msp.c **** { + 1086 .loc 1 508 10 + 1087 0024 144A ldr r2, .L58+4 + 1088 0026 9342 cmp r3, r2 + 1089 0028 06D1 bne .L55 + 514:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM3_MspDeInit 1 */ + 1090 .loc 1 514 5 + 1091 002a 124B ldr r3, .L58 + 1092 002c DB69 ldr r3, [r3, #28] + 1093 002e 114A ldr r2, .L58 + 1094 0030 23F00203 bic r3, r3, #2 + 1095 0034 D361 str r3, [r2, #28] + 1096 .loc 1 542 1 + 1097 0036 16E0 b .L57 + 1098 .L55: + 519:Core/Src/stm32f3xx_hal_msp.c **** { + 1099 .loc 1 519 19 + 1100 0038 7B68 ldr r3, [r7, #4] + 1101 003a 1B68 ldr r3, [r3] + 519:Core/Src/stm32f3xx_hal_msp.c **** { + 1102 .loc 1 519 10 + 1103 003c 0F4A ldr r2, .L58+8 + 1104 003e 9342 cmp r3, r2 + 1105 0040 06D1 bne .L56 + 525:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM4_MspDeInit 1 */ + 1106 .loc 1 525 5 + 1107 0042 0C4B ldr r3, .L58 + 1108 0044 DB69 ldr r3, [r3, #28] + 1109 0046 0B4A ldr r2, .L58 + 1110 0048 23F00403 bic r3, r3, #4 + 1111 004c D361 str r3, [r2, #28] + 1112 .loc 1 542 1 + 1113 004e 0AE0 b .L57 + 1114 .L56: + 530:Core/Src/stm32f3xx_hal_msp.c **** { + 1115 .loc 1 530 19 + 1116 0050 7B68 ldr r3, [r7, #4] + 1117 0052 1B68 ldr r3, [r3] + 530:Core/Src/stm32f3xx_hal_msp.c **** { + 1118 .loc 1 530 10 + 1119 0054 0A4A ldr r2, .L58+12 + 1120 0056 9342 cmp r3, r2 + 1121 0058 05D1 bne .L57 + 536:Core/Src/stm32f3xx_hal_msp.c **** /* USER CODE BEGIN TIM15_MspDeInit 1 */ + 1122 .loc 1 536 5 + 1123 005a 064B ldr r3, .L58 + 1124 005c 9B69 ldr r3, [r3, #24] + 1125 005e 054A ldr r2, .L58 + 1126 0060 23F48033 bic r3, r3, #65536 + 1127 0064 9361 str r3, [r2, #24] + ARM GAS /tmp/cc61sY4U.s page 31 + + + 1128 .L57: + 1129 .loc 1 542 1 + 1130 0066 00BF nop + 1131 0068 0C37 adds r7, r7, #12 + 1132 .cfi_def_cfa_offset 4 + 1133 006a BD46 mov sp, r7 + 1134 .cfi_def_cfa_register 13 + 1135 @ sp needed + 1136 006c 5DF8047B ldr r7, [sp], #4 + 1137 .cfi_restore 7 + 1138 .cfi_def_cfa_offset 0 + 1139 0070 7047 bx lr + 1140 .L59: + 1141 0072 00BF .align 2 + 1142 .L58: + 1143 0074 00100240 .word 1073876992 + 1144 0078 00040040 .word 1073742848 + 1145 007c 00080040 .word 1073743872 + 1146 0080 00400140 .word 1073823744 + 1147 .cfi_endproc + 1148 .LFE139: + 1150 .text + 1151 .Letext0: + 1152 .file 2 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + 1153 .file 3 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 1154 .file 4 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 1155 .file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h" + 1156 .file 6 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h" + 1157 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h" + 1158 .file 8 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h" + 1159 .file 9 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h" + 1160 .file 10 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h" + 1161 .file 11 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h" + 1162 .file 12 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h" + 1163 .file 13 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h" + ARM GAS /tmp/cc61sY4U.s page 32 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f3xx_hal_msp.c + /tmp/cc61sY4U.s:21 .text.HAL_MspInit:00000000 $t + /tmp/cc61sY4U.s:27 .text.HAL_MspInit:00000000 HAL_MspInit + /tmp/cc61sY4U.s:81 .text.HAL_MspInit:00000044 $d + /tmp/cc61sY4U.s:86 .text.HAL_CAN_MspInit:00000000 $t + /tmp/cc61sY4U.s:92 .text.HAL_CAN_MspInit:00000000 HAL_CAN_MspInit + /tmp/cc61sY4U.s:196 .text.HAL_CAN_MspInit:000000a0 $d + /tmp/cc61sY4U.s:202 .text.HAL_CAN_MspDeInit:00000000 $t + /tmp/cc61sY4U.s:208 .text.HAL_CAN_MspDeInit:00000000 HAL_CAN_MspDeInit + /tmp/cc61sY4U.s:258 .text.HAL_CAN_MspDeInit:00000040 $d + /tmp/cc61sY4U.s:264 .text.HAL_I2C_MspInit:00000000 $t + /tmp/cc61sY4U.s:270 .text.HAL_I2C_MspInit:00000000 HAL_I2C_MspInit + /tmp/cc61sY4U.s:447 .text.HAL_I2C_MspInit:00000118 $d + /tmp/cc61sY4U.s:455 .text.HAL_I2C_MspDeInit:00000000 $t + /tmp/cc61sY4U.s:461 .text.HAL_I2C_MspDeInit:00000000 HAL_I2C_MspDeInit + /tmp/cc61sY4U.s:533 .text.HAL_I2C_MspDeInit:0000006c $d + /tmp/cc61sY4U.s:541 .text.HAL_SPI_MspInit:00000000 $t + /tmp/cc61sY4U.s:547 .text.HAL_SPI_MspInit:00000000 HAL_SPI_MspInit + /tmp/cc61sY4U.s:635 .text.HAL_SPI_MspInit:0000007c $d + /tmp/cc61sY4U.s:641 .text.HAL_SPI_MspDeInit:00000000 $t + /tmp/cc61sY4U.s:647 .text.HAL_SPI_MspDeInit:00000000 HAL_SPI_MspDeInit + /tmp/cc61sY4U.s:691 .text.HAL_SPI_MspDeInit:00000030 $d + /tmp/cc61sY4U.s:697 .text.HAL_TIM_PWM_MspInit:00000000 $t + /tmp/cc61sY4U.s:703 .text.HAL_TIM_PWM_MspInit:00000000 HAL_TIM_PWM_MspInit + /tmp/cc61sY4U.s:821 .text.HAL_TIM_PWM_MspInit:000000a4 $d + /tmp/cc61sY4U.s:829 .text.HAL_TIM_MspPostInit:00000000 $t + /tmp/cc61sY4U.s:835 .text.HAL_TIM_MspPostInit:00000000 HAL_TIM_MspPostInit + /tmp/cc61sY4U.s:1038 .text.HAL_TIM_MspPostInit:00000134 $d + /tmp/cc61sY4U.s:1047 .text.HAL_TIM_PWM_MspDeInit:00000000 $t + /tmp/cc61sY4U.s:1053 .text.HAL_TIM_PWM_MspDeInit:00000000 HAL_TIM_PWM_MspDeInit + /tmp/cc61sY4U.s:1143 .text.HAL_TIM_PWM_MspDeInit:00000074 $d + +UNDEFINED SYMBOLS +HAL_GPIO_Init +HAL_NVIC_SetPriority +HAL_NVIC_EnableIRQ +HAL_GPIO_DeInit +HAL_NVIC_DisableIRQ diff --git a/Software/build/stm32f3xx_hal_msp.o b/Software/build/stm32f3xx_hal_msp.o new file mode 100644 index 0000000..7f44947 Binary files /dev/null and b/Software/build/stm32f3xx_hal_msp.o differ diff --git a/Software/build/stm32f3xx_hal_pwr.d b/Software/build/stm32f3xx_hal_pwr.d new file mode 100644 index 0000000..16b6690 --- /dev/null +++ b/Software/build/stm32f3xx_hal_pwr.d @@ -0,0 +1,62 @@ +build/stm32f3xx_hal_pwr.o: \ + Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + Core/Inc/stm32f3xx_hal_conf.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h: diff --git a/Software/build/stm32f3xx_hal_pwr.lst b/Software/build/stm32f3xx_hal_pwr.lst new file mode 100644 index 0000000..d574b21 --- /dev/null +++ b/Software/build/stm32f3xx_hal_pwr.lst @@ -0,0 +1,1177 @@ +ARM GAS /tmp/ccdoKIzP.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 6 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "stm32f3xx_hal_pwr.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" + 20 .section .text.HAL_PWR_DeInit,"ax",%progbits + 21 .align 1 + 22 .global HAL_PWR_DeInit + 23 .syntax unified + 24 .thumb + 25 .thumb_func + 27 HAL_PWR_DeInit: + 28 .LFB130: + 1:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** + 2:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ****************************************************************************** + 3:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @file stm32f3xx_hal_pwr.c + 4:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @author MCD Application Team + 5:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief PWR HAL module driver. + 6:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * functionalities of the Power Controller (PWR) peripheral: + 8:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * + Initialization/de-initialization functions + 9:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * + Peripheral Control functions + 10:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * + 11:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ****************************************************************************** + 12:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @attention + 13:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * + 14:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * Copyright (c) 2016 STMicroelectronics. + 15:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * All rights reserved. + 16:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * + 17:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This software is licensed under terms that can be found in the LICENSE file + 18:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * in the root directory of this software component. + 19:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 20:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * + 21:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ****************************************************************************** + 22:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */ + 23:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 24:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Includes ------------------------------------------------------------------*/ + 25:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** #include "stm32f3xx_hal.h" + 26:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 27:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** @addtogroup STM32F3xx_HAL_Driver + 28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @{ + 29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */ + 30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + ARM GAS /tmp/ccdoKIzP.s page 2 + + + 31:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** @defgroup PWR PWR + 32:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief PWR HAL module driver + 33:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @{ + 34:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */ + 35:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 36:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** #ifdef HAL_PWR_MODULE_ENABLED + 37:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 38:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Private typedef -----------------------------------------------------------*/ + 39:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Private define ------------------------------------------------------------*/ + 40:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Private macro -------------------------------------------------------------*/ + 41:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Private variables ---------------------------------------------------------*/ + 42:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Private function prototypes -----------------------------------------------*/ + 43:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Private functions ---------------------------------------------------------*/ + 44:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 45:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions PWR Exported Functions + 46:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @{ + 47:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */ + 48:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 49:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + 50:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Initialization and de-initialization functions + 51:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * + 52:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** @verbatim + 53:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** =============================================================================== + 54:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ##### Initialization and de-initialization functions ##### + 55:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** =============================================================================== + 56:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..] + 57:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** After reset, the backup domain (RTC registers, RTC backup data + 58:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** registers and backup SRAM) is protected against possible unwanted + 59:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** write accesses. + 60:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** To enable access to the RTC Domain and RTC registers, proceed as follows: + 61:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Enable the Power Controller (PWR) APB1 interface clock using the + 62:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __HAL_RCC_PWR_CLK_ENABLE() macro. + 63:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. + 64:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 65:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** @endverbatim + 66:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @{ + 67:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */ + 68:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 69:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** + 70:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Deinitializes the PWR peripheral registers to their default reset values. + 71:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None + 72:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */ + 73:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_DeInit(void) + 74:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** { + 29 .loc 1 74 1 + 30 .cfi_startproc + 31 @ args = 0, pretend = 0, frame = 0 + 32 @ frame_needed = 1, uses_anonymous_args = 0 + 33 @ link register save eliminated. + 34 0000 80B4 push {r7} + 35 .cfi_def_cfa_offset 4 + 36 .cfi_offset 7, -4 + 37 0002 00AF add r7, sp, #0 + 38 .cfi_def_cfa_register 7 + 75:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __HAL_RCC_PWR_FORCE_RESET(); + 39 .loc 1 75 3 + 40 0004 084B ldr r3, .L2 + ARM GAS /tmp/ccdoKIzP.s page 3 + + + 41 0006 1B69 ldr r3, [r3, #16] + 42 0008 074A ldr r2, .L2 + 43 000a 43F08053 orr r3, r3, #268435456 + 44 000e 1361 str r3, [r2, #16] + 76:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __HAL_RCC_PWR_RELEASE_RESET(); + 45 .loc 1 76 3 + 46 0010 054B ldr r3, .L2 + 47 0012 1B69 ldr r3, [r3, #16] + 48 0014 044A ldr r2, .L2 + 49 0016 23F08053 bic r3, r3, #268435456 + 50 001a 1361 str r3, [r2, #16] + 77:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** } + 51 .loc 1 77 1 + 52 001c 00BF nop + 53 001e BD46 mov sp, r7 + 54 .cfi_def_cfa_register 13 + 55 @ sp needed + 56 0020 5DF8047B ldr r7, [sp], #4 + 57 .cfi_restore 7 + 58 .cfi_def_cfa_offset 0 + 59 0024 7047 bx lr + 60 .L3: + 61 0026 00BF .align 2 + 62 .L2: + 63 0028 00100240 .word 1073876992 + 64 .cfi_endproc + 65 .LFE130: + 67 .section .text.HAL_PWR_EnableBkUpAccess,"ax",%progbits + 68 .align 1 + 69 .global HAL_PWR_EnableBkUpAccess + 70 .syntax unified + 71 .thumb + 72 .thumb_func + 74 HAL_PWR_EnableBkUpAccess: + 75 .LFB131: + 78:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 79:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** + 80:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Enables access to the backup domain (RTC registers, RTC + 81:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * backup data registers and backup SRAM). + 82:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note If the HSE divided by 32 is used as the RTC clock, the + 83:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * Backup Domain Access should be kept enabled. + 84:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None + 85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */ + 86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnableBkUpAccess(void) + 87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** { + 76 .loc 1 87 1 + 77 .cfi_startproc + 78 @ args = 0, pretend = 0, frame = 0 + 79 @ frame_needed = 1, uses_anonymous_args = 0 + 80 @ link register save eliminated. + 81 0000 80B4 push {r7} + 82 .cfi_def_cfa_offset 4 + 83 .cfi_offset 7, -4 + 84 0002 00AF add r7, sp, #0 + 85 .cfi_def_cfa_register 7 + 88:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SET_BIT(PWR->CR, PWR_CR_DBP); + 86 .loc 1 88 3 + ARM GAS /tmp/ccdoKIzP.s page 4 + + + 87 0004 054B ldr r3, .L5 + 88 0006 1B68 ldr r3, [r3] + 89 0008 044A ldr r2, .L5 + 90 000a 43F48073 orr r3, r3, #256 + 91 000e 1360 str r3, [r2] + 89:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** } + 92 .loc 1 89 1 + 93 0010 00BF nop + 94 0012 BD46 mov sp, r7 + 95 .cfi_def_cfa_register 13 + 96 @ sp needed + 97 0014 5DF8047B ldr r7, [sp], #4 + 98 .cfi_restore 7 + 99 .cfi_def_cfa_offset 0 + 100 0018 7047 bx lr + 101 .L6: + 102 001a 00BF .align 2 + 103 .L5: + 104 001c 00700040 .word 1073770496 + 105 .cfi_endproc + 106 .LFE131: + 108 .section .text.HAL_PWR_DisableBkUpAccess,"ax",%progbits + 109 .align 1 + 110 .global HAL_PWR_DisableBkUpAccess + 111 .syntax unified + 112 .thumb + 113 .thumb_func + 115 HAL_PWR_DisableBkUpAccess: + 116 .LFB132: + 90:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 91:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** + 92:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Disables access to the backup domain (RTC registers, RTC + 93:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * backup data registers and backup SRAM). + 94:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note If the HSE divided by 32 is used as the RTC clock, the + 95:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * Backup Domain Access should be kept enabled. + 96:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None + 97:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */ + 98:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_DisableBkUpAccess(void) + 99:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** { + 117 .loc 1 99 1 + 118 .cfi_startproc + 119 @ args = 0, pretend = 0, frame = 0 + 120 @ frame_needed = 1, uses_anonymous_args = 0 + 121 @ link register save eliminated. + 122 0000 80B4 push {r7} + 123 .cfi_def_cfa_offset 4 + 124 .cfi_offset 7, -4 + 125 0002 00AF add r7, sp, #0 + 126 .cfi_def_cfa_register 7 + 100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** CLEAR_BIT(PWR->CR, PWR_CR_DBP); + 127 .loc 1 100 3 + 128 0004 054B ldr r3, .L8 + 129 0006 1B68 ldr r3, [r3] + 130 0008 044A ldr r2, .L8 + 131 000a 23F48073 bic r3, r3, #256 + 132 000e 1360 str r3, [r2] + 101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** } + ARM GAS /tmp/ccdoKIzP.s page 5 + + + 133 .loc 1 101 1 + 134 0010 00BF nop + 135 0012 BD46 mov sp, r7 + 136 .cfi_def_cfa_register 13 + 137 @ sp needed + 138 0014 5DF8047B ldr r7, [sp], #4 + 139 .cfi_restore 7 + 140 .cfi_def_cfa_offset 0 + 141 0018 7047 bx lr + 142 .L9: + 143 001a 00BF .align 2 + 144 .L8: + 145 001c 00700040 .word 1073770496 + 146 .cfi_endproc + 147 .LFE132: + 149 .section .text.HAL_PWR_EnableWakeUpPin,"ax",%progbits + 150 .align 1 + 151 .global HAL_PWR_EnableWakeUpPin + 152 .syntax unified + 153 .thumb + 154 .thumb_func + 156 HAL_PWR_EnableWakeUpPin: + 157 .LFB133: + 102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** + 104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @} + 105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */ + 106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions + 108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Low Power modes configuration functions + 109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * + 110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** @verbatim + 111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** =============================================================================== + 113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ##### Peripheral Control functions ##### + 114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** =============================================================================== + 115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *** WakeUp pin configuration *** + 117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ================================ + 118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..] + 119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) WakeUp pin is used to wakeup the system from Standby mode. This pin is + 120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** forced in input pull down configuration and is active on rising edges. + 121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) There are up to three WakeUp pins: + 122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++)WakeUp Pin 1 on PA.00. + 123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++)WakeUp Pin 2 on PC.13 (STM32F303xC, STM32F303xE only). + 124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++)WakeUp Pin 3 on PE.06. + 125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *** Main and Backup Regulators configuration *** + 127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ================================================ + 128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..] + 129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) When the backup domain is supplied by VDD (analog switch connected to VDD) + 130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** the backup SRAM is powered from VDD which replaces the VBAT power supply to + 131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** save battery life. + 132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) The backup SRAM is not mass erased by a tamper event. It is read + 134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** protected to prevent confidential data, such as cryptographic private + 135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** key, from being accessed. The backup SRAM can be erased only through + ARM GAS /tmp/ccdoKIzP.s page 6 + + + 136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** the Flash interface when a protection level change from level 1 to + 137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** level 0 is requested. + 138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** -@- Refer to the description of Read protection (RDP) in the Flash + 139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** programming manual. + 140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** Refer to the datasheets for more details. + 142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *** Low Power modes configuration *** + 144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ===================================== + 145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..] + 146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The devices feature 3 low-power modes: + 147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running. + 148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Stop mode: all clocks are stopped, regulator running, regulator + 149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** in low power mode + 150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Standby mode: 1.2V domain powered off (mode not available on STM32F3x8 devices). + 151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *** Sleep mode *** + 153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ================== + 154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..] + 155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Entry: + 156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_S + 157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** functions with + 158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction + 159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + 160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Exit: + 162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) Any peripheral interrupt acknowledged by the nested vectored interrupt + 163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** controller (NVIC) can wake up the device from Sleep mode. + 164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *** Stop mode *** + 166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ================= + 167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..] + 168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** In Stop mode, all clocks in the 1.8V domain are stopped, the PLL, the HSI, + 169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** and the HSE RC oscillators are disabled. Internal SRAM and register contents + 170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** are preserved. + 171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The voltage regulator can be configured either in normal or low-power mode to minimize the co + 172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Entry: + 174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_STOPEN + 175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** function with: + 176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) Main regulator ON or + 177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) Low Power regulator ON. + 178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction or + 179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction + 180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Exit: + 181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode. + 182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) Some specific communication peripherals (CEC, USART, I2C) interrupts, + 183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** when programmed in wakeup mode (the peripheral must be + 184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** programmed in wakeup mode and the corresponding interrupt vector + 185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** must be enabled in the NVIC). + 186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *** Standby mode *** + 188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ==================== + 189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..] + 190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The Standby mode allows to achieve the lowest power consumption. It is based + 191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** on the Cortex-M4 deep sleep mode, with the voltage regulator disabled. + 192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The 1.8V domain is consequently powered off. The PLL, the HSI oscillator and + ARM GAS /tmp/ccdoKIzP.s page 7 + + + 193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** the HSE oscillator are also switched off. SRAM and register contents are lost + 194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** except for the RTC registers, RTC backup registers, backup SRAM and Standby + 195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** circuitry. + 196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The voltage regulator is OFF. + 197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Entry: + 199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. + 200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Exit: + 201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup, + 202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** tamper event, time-stamp event, external reset in NRST pin, IWDG reset. + 203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *** Auto-wakeup (AWU) from low-power mode *** + 205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ============================================= + 206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..] + 207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC + 208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** Wakeup event, a tamper event, a time-stamp event, or a comparator event, + 209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** without depending on an external interrupt (Auto-wakeup mode). + 210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) RTC auto-wakeup (AWU) from the Stop and Standby modes + 212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to + 214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. + 215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it + 217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** is necessary to configure the RTC to detect the tamper or time stamp event using the + 218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** HAL_RTC_SetTimeStamp_IT() or HAL_RTC_SetTamper_IT() functions. + 219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to + 221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** configure the RTC to generate the RTC WakeUp event using the HAL_RTC_SetWakeUpTimer_IT() + 222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Comparator auto-wakeup (AWU) from the Stop mode + 224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) To wake up from the Stop mode with a comparator wakeup event, it is necessary to: + 226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+++) Configure the EXTI Line associated with the comparator (example EXTI Line 22 for c + 227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** to be sensitive to to the selected edges (falling, rising or falling + 228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** and rising) (Interrupt or Event modes) using the EXTI_Init() function. + 229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+++) Configure the comparator to generate the event. + 230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** @endverbatim + 231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @{ + 232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */ + 233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** + 235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Enables the WakeUp PINx functionality. + 236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @param WakeUpPinx Specifies the Power Wake-Up pin to enable. + 237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This parameter can be value of : + 238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @ref PWR_WakeUp_Pins + 239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None + 240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */ + 241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) + 242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** { + 158 .loc 1 242 1 + 159 .cfi_startproc + 160 @ args = 0, pretend = 0, frame = 8 + 161 @ frame_needed = 1, uses_anonymous_args = 0 + 162 @ link register save eliminated. + 163 0000 80B4 push {r7} + 164 .cfi_def_cfa_offset 4 + ARM GAS /tmp/ccdoKIzP.s page 8 + + + 165 .cfi_offset 7, -4 + 166 0002 83B0 sub sp, sp, #12 + 167 .cfi_def_cfa_offset 16 + 168 0004 00AF add r7, sp, #0 + 169 .cfi_def_cfa_register 7 + 170 0006 7860 str r0, [r7, #4] + 243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Check the parameters */ + 244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); + 245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Enable the EWUPx pin */ + 246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SET_BIT(PWR->CSR, WakeUpPinx); + 171 .loc 1 246 3 + 172 0008 054B ldr r3, .L11 + 173 000a 5A68 ldr r2, [r3, #4] + 174 000c 0449 ldr r1, .L11 + 175 000e 7B68 ldr r3, [r7, #4] + 176 0010 1343 orrs r3, r3, r2 + 177 0012 4B60 str r3, [r1, #4] + 247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** } + 178 .loc 1 247 1 + 179 0014 00BF nop + 180 0016 0C37 adds r7, r7, #12 + 181 .cfi_def_cfa_offset 4 + 182 0018 BD46 mov sp, r7 + 183 .cfi_def_cfa_register 13 + 184 @ sp needed + 185 001a 5DF8047B ldr r7, [sp], #4 + 186 .cfi_restore 7 + 187 .cfi_def_cfa_offset 0 + 188 001e 7047 bx lr + 189 .L12: + 190 .align 2 + 191 .L11: + 192 0020 00700040 .word 1073770496 + 193 .cfi_endproc + 194 .LFE133: + 196 .section .text.HAL_PWR_DisableWakeUpPin,"ax",%progbits + 197 .align 1 + 198 .global HAL_PWR_DisableWakeUpPin + 199 .syntax unified + 200 .thumb + 201 .thumb_func + 203 HAL_PWR_DisableWakeUpPin: + 204 .LFB134: + 248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** + 250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Disables the WakeUp PINx functionality. + 251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @param WakeUpPinx Specifies the Power Wake-Up pin to disable. + 252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This parameter can be values of : + 253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @ref PWR_WakeUp_Pins + 254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None + 255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */ + 256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) + 257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** { + 205 .loc 1 257 1 + 206 .cfi_startproc + 207 @ args = 0, pretend = 0, frame = 8 + 208 @ frame_needed = 1, uses_anonymous_args = 0 + ARM GAS /tmp/ccdoKIzP.s page 9 + + + 209 @ link register save eliminated. + 210 0000 80B4 push {r7} + 211 .cfi_def_cfa_offset 4 + 212 .cfi_offset 7, -4 + 213 0002 83B0 sub sp, sp, #12 + 214 .cfi_def_cfa_offset 16 + 215 0004 00AF add r7, sp, #0 + 216 .cfi_def_cfa_register 7 + 217 0006 7860 str r0, [r7, #4] + 258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Check the parameters */ + 259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); + 260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Disable the EWUPx pin */ + 261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** CLEAR_BIT(PWR->CSR, WakeUpPinx); + 218 .loc 1 261 3 + 219 0008 064B ldr r3, .L14 + 220 000a 5A68 ldr r2, [r3, #4] + 221 000c 7B68 ldr r3, [r7, #4] + 222 000e DB43 mvns r3, r3 + 223 0010 0449 ldr r1, .L14 + 224 0012 1340 ands r3, r3, r2 + 225 0014 4B60 str r3, [r1, #4] + 262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** } + 226 .loc 1 262 1 + 227 0016 00BF nop + 228 0018 0C37 adds r7, r7, #12 + 229 .cfi_def_cfa_offset 4 + 230 001a BD46 mov sp, r7 + 231 .cfi_def_cfa_register 13 + 232 @ sp needed + 233 001c 5DF8047B ldr r7, [sp], #4 + 234 .cfi_restore 7 + 235 .cfi_def_cfa_offset 0 + 236 0020 7047 bx lr + 237 .L15: + 238 0022 00BF .align 2 + 239 .L14: + 240 0024 00700040 .word 1073770496 + 241 .cfi_endproc + 242 .LFE134: + 244 .section .text.HAL_PWR_EnterSLEEPMode,"ax",%progbits + 245 .align 1 + 246 .global HAL_PWR_EnterSLEEPMode + 247 .syntax unified + 248 .thumb + 249 .thumb_func + 251 HAL_PWR_EnterSLEEPMode: + 252 .LFB135: + 263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** + 265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Enters Sleep mode. + 266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note In Sleep mode, all I/O pins keep the same state as in Run mode. + 267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @param Regulator Specifies the regulator state in SLEEP mode. + 268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This parameter can be one of the following values: + 269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON + 270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON + 271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note This parameter has no effect in F3 family and is just maintained to + 272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * offer full portability of other STM32 families software. + ARM GAS /tmp/ccdoKIzP.s page 10 + + + 273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @param SLEEPEntry Specifies if SLEEP mode is entered with WFI or WFE instruction. + 274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * When WFI entry is used, tick interrupt have to be disabled if not desired as + 275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * the interrupt wake up source. + 276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This parameter can be one of the following values: + 277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction + 278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + 279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None + 280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */ + 281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) + 282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** { + 253 .loc 1 282 1 + 254 .cfi_startproc + 255 @ args = 0, pretend = 0, frame = 8 + 256 @ frame_needed = 1, uses_anonymous_args = 0 + 257 @ link register save eliminated. + 258 0000 80B4 push {r7} + 259 .cfi_def_cfa_offset 4 + 260 .cfi_offset 7, -4 + 261 0002 83B0 sub sp, sp, #12 + 262 .cfi_def_cfa_offset 16 + 263 0004 00AF add r7, sp, #0 + 264 .cfi_def_cfa_register 7 + 265 0006 7860 str r0, [r7, #4] + 266 0008 0B46 mov r3, r1 + 267 000a FB70 strb r3, [r7, #3] + 283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Check the parameters */ + 284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); + 285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Clear SLEEPDEEP bit of Cortex System Control Register */ + 287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); + 268 .loc 1 287 6 + 269 000c 094B ldr r3, .L20 + 270 000e 1B69 ldr r3, [r3, #16] + 271 0010 084A ldr r2, .L20 + 272 .loc 1 287 12 + 273 0012 23F00403 bic r3, r3, #4 + 274 0016 1361 str r3, [r2, #16] + 288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Select SLEEP mode entry -------------------------------------------------*/ + 290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** if(SLEEPEntry == PWR_SLEEPENTRY_WFI) + 275 .loc 1 290 5 + 276 0018 FB78 ldrb r3, [r7, #3] @ zero_extendqisi2 + 277 001a 012B cmp r3, #1 + 278 001c 01D1 bne .L17 + 291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** { + 292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Request Wait For Interrupt */ + 293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFI(); + 279 .loc 1 293 5 + 280 .syntax unified + 281 @ 293 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1 + 282 001e 30BF wfi + 283 @ 0 "" 2 + 294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** } + 295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** else + 296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** { + 297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Request Wait For Event */ + 298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __SEV(); + ARM GAS /tmp/ccdoKIzP.s page 11 + + + 299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFE(); + 300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFE(); + 301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** } + 302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** } + 284 .loc 1 302 1 + 285 .thumb + 286 .syntax unified + 287 0020 02E0 b .L19 + 288 .L17: + 298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFE(); + 289 .loc 1 298 5 + 290 .syntax unified + 291 @ 298 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1 + 292 0022 40BF sev + 293 @ 0 "" 2 + 299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFE(); + 294 .loc 1 299 5 + 295 @ 299 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1 + 296 0024 20BF wfe + 297 @ 0 "" 2 + 300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** } + 298 .loc 1 300 5 + 299 @ 300 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1 + 300 0026 20BF wfe + 301 @ 0 "" 2 + 302 .thumb + 303 .syntax unified + 304 .L19: + 305 .loc 1 302 1 + 306 0028 00BF nop + 307 002a 0C37 adds r7, r7, #12 + 308 .cfi_def_cfa_offset 4 + 309 002c BD46 mov sp, r7 + 310 .cfi_def_cfa_register 13 + 311 @ sp needed + 312 002e 5DF8047B ldr r7, [sp], #4 + 313 .cfi_restore 7 + 314 .cfi_def_cfa_offset 0 + 315 0032 7047 bx lr + 316 .L21: + 317 .align 2 + 318 .L20: + 319 0034 00ED00E0 .word -536810240 + 320 .cfi_endproc + 321 .LFE135: + 323 .section .text.HAL_PWR_EnterSTOPMode,"ax",%progbits + 324 .align 1 + 325 .global HAL_PWR_EnterSTOPMode + 326 .syntax unified + 327 .thumb + 328 .thumb_func + 330 HAL_PWR_EnterSTOPMode: + 331 .LFB136: + 303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** + 305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Enters STOP mode. + 306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note In Stop mode, all I/O pins keep the same state as in Run mode. + ARM GAS /tmp/ccdoKIzP.s page 12 + + + 307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note When exiting Stop mode by issuing an interrupt or a wakeup event, + 308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * the HSI RC oscillator is selected as system clock. + 309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note When the voltage regulator operates in low power mode, an additional + 310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * startup delay is incurred when waking up from Stop mode. + 311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * By keeping the internal regulator ON during Stop mode, the consumption + 312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * is higher although the startup time is reduced. + 313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @param Regulator Specifies the regulator state in STOP mode. + 314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This parameter can be one of the following values: + 315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_MAINREGULATOR_ON: STOP mode with regulator ON + 316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_LOWPOWERREGULATOR_ON: STOP mode with low power regulator ON + 317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction. + 318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This parameter can be one of the following values: + 319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_STOPENTRY_WFI:Enter STOP mode with WFI instruction + 320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_STOPENTRY_WFE: Enter STOP mode with WFE instruction + 321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None + 322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */ + 323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) + 324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** { + 332 .loc 1 324 1 + 333 .cfi_startproc + 334 @ args = 0, pretend = 0, frame = 16 + 335 @ frame_needed = 1, uses_anonymous_args = 0 + 336 @ link register save eliminated. + 337 0000 80B4 push {r7} + 338 .cfi_def_cfa_offset 4 + 339 .cfi_offset 7, -4 + 340 0002 85B0 sub sp, sp, #20 + 341 .cfi_def_cfa_offset 24 + 342 0004 00AF add r7, sp, #0 + 343 .cfi_def_cfa_register 7 + 344 0006 7860 str r0, [r7, #4] + 345 0008 0B46 mov r3, r1 + 346 000a FB70 strb r3, [r7, #3] + 325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** uint32_t tmpreg = 0U; + 347 .loc 1 325 12 + 348 000c 0023 movs r3, #0 + 349 000e FB60 str r3, [r7, #12] + 326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Check the parameters */ + 328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** assert_param(IS_PWR_REGULATOR(Regulator)); + 329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); + 330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Select the regulator state in STOP mode ---------------------------------*/ + 332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** tmpreg = PWR->CR; + 350 .loc 1 332 15 + 351 0010 134B ldr r3, .L25 + 352 .loc 1 332 10 + 353 0012 1B68 ldr r3, [r3] + 354 0014 FB60 str r3, [r7, #12] + 333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Clear PDDS and LPDS bits */ + 335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** tmpreg &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS); + 355 .loc 1 335 10 + 356 0016 FB68 ldr r3, [r7, #12] + 357 0018 23F00303 bic r3, r3, #3 + 358 001c FB60 str r3, [r7, #12] + 336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + ARM GAS /tmp/ccdoKIzP.s page 13 + + + 337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Set LPDS bit according to Regulator value */ + 338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** tmpreg |= Regulator; + 359 .loc 1 338 10 + 360 001e FA68 ldr r2, [r7, #12] + 361 0020 7B68 ldr r3, [r7, #4] + 362 0022 1343 orrs r3, r3, r2 + 363 0024 FB60 str r3, [r7, #12] + 339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Store the new value */ + 341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** PWR->CR = tmpreg; + 364 .loc 1 341 6 + 365 0026 0E4A ldr r2, .L25 + 366 .loc 1 341 11 + 367 0028 FB68 ldr r3, [r7, #12] + 368 002a 1360 str r3, [r2] + 342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */ + 344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + 369 .loc 1 344 6 + 370 002c 0D4B ldr r3, .L25+4 + 371 002e 1B69 ldr r3, [r3, #16] + 372 0030 0C4A ldr r2, .L25+4 + 373 .loc 1 344 12 + 374 0032 43F00403 orr r3, r3, #4 + 375 0036 1361 str r3, [r2, #16] + 345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Select STOP mode entry --------------------------------------------------*/ + 347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** if(STOPEntry == PWR_STOPENTRY_WFI) + 376 .loc 1 347 5 + 377 0038 FB78 ldrb r3, [r7, #3] @ zero_extendqisi2 + 378 003a 012B cmp r3, #1 + 379 003c 01D1 bne .L23 + 348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** { + 349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Request Wait For Interrupt */ + 350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFI(); + 380 .loc 1 350 5 + 381 .syntax unified + 382 @ 350 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1 + 383 003e 30BF wfi + 384 @ 0 "" 2 + 385 .thumb + 386 .syntax unified + 387 0040 02E0 b .L24 + 388 .L23: + 351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** } + 352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** else + 353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** { + 354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Request Wait For Event */ + 355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __SEV(); + 389 .loc 1 355 5 + 390 .syntax unified + 391 @ 355 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1 + 392 0042 40BF sev + 393 @ 0 "" 2 + 356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFE(); + 394 .loc 1 356 5 + 395 @ 356 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1 + ARM GAS /tmp/ccdoKIzP.s page 14 + + + 396 0044 20BF wfe + 397 @ 0 "" 2 + 357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFE(); + 398 .loc 1 357 5 + 399 @ 357 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1 + 400 0046 20BF wfe + 401 @ 0 "" 2 + 402 .thumb + 403 .syntax unified + 404 .L24: + 358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** } + 359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Reset SLEEPDEEP bit of Cortex System Control Register */ + 361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); + 405 .loc 1 361 6 + 406 0048 064B ldr r3, .L25+4 + 407 004a 1B69 ldr r3, [r3, #16] + 408 004c 054A ldr r2, .L25+4 + 409 .loc 1 361 12 + 410 004e 23F00403 bic r3, r3, #4 + 411 0052 1361 str r3, [r2, #16] + 362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** } + 412 .loc 1 362 1 + 413 0054 00BF nop + 414 0056 1437 adds r7, r7, #20 + 415 .cfi_def_cfa_offset 4 + 416 0058 BD46 mov sp, r7 + 417 .cfi_def_cfa_register 13 + 418 @ sp needed + 419 005a 5DF8047B ldr r7, [sp], #4 + 420 .cfi_restore 7 + 421 .cfi_def_cfa_offset 0 + 422 005e 7047 bx lr + 423 .L26: + 424 .align 2 + 425 .L25: + 426 0060 00700040 .word 1073770496 + 427 0064 00ED00E0 .word -536810240 + 428 .cfi_endproc + 429 .LFE136: + 431 .section .text.HAL_PWR_EnterSTANDBYMode,"ax",%progbits + 432 .align 1 + 433 .global HAL_PWR_EnterSTANDBYMode + 434 .syntax unified + 435 .thumb + 436 .thumb_func + 438 HAL_PWR_EnterSTANDBYMode: + 439 .LFB137: + 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** + 365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Enters STANDBY mode. + 366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note In Standby mode, all I/O pins are high impedance except for: + 367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * - Reset pad (still available), + 368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * - RTC alternate function pins if configured for tamper, time-stamp, RTC + 369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * Alarm out, or RTC clock calibration out, + 370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * - WKUP pins if enabled. + 371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None + ARM GAS /tmp/ccdoKIzP.s page 15 + + + 372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */ + 373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnterSTANDBYMode(void) + 374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** { + 440 .loc 1 374 1 + 441 .cfi_startproc + 442 @ args = 0, pretend = 0, frame = 0 + 443 @ frame_needed = 1, uses_anonymous_args = 0 + 444 @ link register save eliminated. + 445 0000 80B4 push {r7} + 446 .cfi_def_cfa_offset 4 + 447 .cfi_offset 7, -4 + 448 0002 00AF add r7, sp, #0 + 449 .cfi_def_cfa_register 7 + 375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Select STANDBY mode */ + 376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** PWR->CR |= PWR_CR_PDDS; + 450 .loc 1 376 6 + 451 0004 084B ldr r3, .L28 + 452 0006 1B68 ldr r3, [r3] + 453 0008 074A ldr r2, .L28 + 454 .loc 1 376 11 + 455 000a 43F00203 orr r3, r3, #2 + 456 000e 1360 str r3, [r2] + 377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */ + 379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + 457 .loc 1 379 6 + 458 0010 064B ldr r3, .L28+4 + 459 0012 1B69 ldr r3, [r3, #16] + 460 0014 054A ldr r2, .L28+4 + 461 .loc 1 379 12 + 462 0016 43F00403 orr r3, r3, #4 + 463 001a 1361 str r3, [r2, #16] + 380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* This option is used to ensure that store operations are completed */ + 382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** #if defined ( __CC_ARM) + 383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __force_stores(); + 384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** #endif + 385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Request Wait For Interrupt */ + 386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFI(); + 464 .loc 1 386 3 + 465 .syntax unified + 466 @ 386 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1 + 467 001c 30BF wfi + 468 @ 0 "" 2 + 387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** } + 469 .loc 1 387 1 + 470 .thumb + 471 .syntax unified + 472 001e 00BF nop + 473 0020 BD46 mov sp, r7 + 474 .cfi_def_cfa_register 13 + 475 @ sp needed + 476 0022 5DF8047B ldr r7, [sp], #4 + 477 .cfi_restore 7 + 478 .cfi_def_cfa_offset 0 + 479 0026 7047 bx lr + 480 .L29: + ARM GAS /tmp/ccdoKIzP.s page 16 + + + 481 .align 2 + 482 .L28: + 483 0028 00700040 .word 1073770496 + 484 002c 00ED00E0 .word -536810240 + 485 .cfi_endproc + 486 .LFE137: + 488 .section .text.HAL_PWR_EnableSleepOnExit,"ax",%progbits + 489 .align 1 + 490 .global HAL_PWR_EnableSleepOnExit + 491 .syntax unified + 492 .thumb + 493 .thumb_func + 495 HAL_PWR_EnableSleepOnExit: + 496 .LFB138: + 388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** + 390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. + 391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor + 392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * re-enters SLEEP mode when an interruption handling is over. + 393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * Setting this bit is useful when the processor is expected to run only on + 394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * interruptions handling. + 395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None + 396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */ + 397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnableSleepOnExit(void) + 398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** { + 497 .loc 1 398 1 + 498 .cfi_startproc + 499 @ args = 0, pretend = 0, frame = 0 + 500 @ frame_needed = 1, uses_anonymous_args = 0 + 501 @ link register save eliminated. + 502 0000 80B4 push {r7} + 503 .cfi_def_cfa_offset 4 + 504 .cfi_offset 7, -4 + 505 0002 00AF add r7, sp, #0 + 506 .cfi_def_cfa_register 7 + 399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Set SLEEPONEXIT bit of Cortex System Control Register */ + 400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); + 507 .loc 1 400 3 + 508 0004 054B ldr r3, .L31 + 509 0006 1B69 ldr r3, [r3, #16] + 510 0008 044A ldr r2, .L31 + 511 000a 43F00203 orr r3, r3, #2 + 512 000e 1361 str r3, [r2, #16] + 401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** } + 513 .loc 1 401 1 + 514 0010 00BF nop + 515 0012 BD46 mov sp, r7 + 516 .cfi_def_cfa_register 13 + 517 @ sp needed + 518 0014 5DF8047B ldr r7, [sp], #4 + 519 .cfi_restore 7 + 520 .cfi_def_cfa_offset 0 + 521 0018 7047 bx lr + 522 .L32: + 523 001a 00BF .align 2 + 524 .L31: + 525 001c 00ED00E0 .word -536810240 + ARM GAS /tmp/ccdoKIzP.s page 17 + + + 526 .cfi_endproc + 527 .LFE138: + 529 .section .text.HAL_PWR_DisableSleepOnExit,"ax",%progbits + 530 .align 1 + 531 .global HAL_PWR_DisableSleepOnExit + 532 .syntax unified + 533 .thumb + 534 .thumb_func + 536 HAL_PWR_DisableSleepOnExit: + 537 .LFB139: + 402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** + 405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. + 406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor + 407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * re-enters SLEEP mode when an interruption handling is over. + 408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None + 409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */ + 410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_DisableSleepOnExit(void) + 411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** { + 538 .loc 1 411 1 + 539 .cfi_startproc + 540 @ args = 0, pretend = 0, frame = 0 + 541 @ frame_needed = 1, uses_anonymous_args = 0 + 542 @ link register save eliminated. + 543 0000 80B4 push {r7} + 544 .cfi_def_cfa_offset 4 + 545 .cfi_offset 7, -4 + 546 0002 00AF add r7, sp, #0 + 547 .cfi_def_cfa_register 7 + 412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Clear SLEEPONEXIT bit of Cortex System Control Register */ + 413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); + 548 .loc 1 413 3 + 549 0004 054B ldr r3, .L34 + 550 0006 1B69 ldr r3, [r3, #16] + 551 0008 044A ldr r2, .L34 + 552 000a 23F00203 bic r3, r3, #2 + 553 000e 1361 str r3, [r2, #16] + 414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** } + 554 .loc 1 414 1 + 555 0010 00BF nop + 556 0012 BD46 mov sp, r7 + 557 .cfi_def_cfa_register 13 + 558 @ sp needed + 559 0014 5DF8047B ldr r7, [sp], #4 + 560 .cfi_restore 7 + 561 .cfi_def_cfa_offset 0 + 562 0018 7047 bx lr + 563 .L35: + 564 001a 00BF .align 2 + 565 .L34: + 566 001c 00ED00E0 .word -536810240 + 567 .cfi_endproc + 568 .LFE139: + 570 .section .text.HAL_PWR_EnableSEVOnPend,"ax",%progbits + 571 .align 1 + 572 .global HAL_PWR_EnableSEVOnPend + ARM GAS /tmp/ccdoKIzP.s page 18 + + + 573 .syntax unified + 574 .thumb + 575 .thumb_func + 577 HAL_PWR_EnableSEVOnPend: + 578 .LFB140: + 415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** + 419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Enables CORTEX M4 SEVONPEND bit. + 420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes + 421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * WFE to wake up when an interrupt moves from inactive to pended. + 422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None + 423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */ + 424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnableSEVOnPend(void) + 425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** { + 579 .loc 1 425 1 + 580 .cfi_startproc + 581 @ args = 0, pretend = 0, frame = 0 + 582 @ frame_needed = 1, uses_anonymous_args = 0 + 583 @ link register save eliminated. + 584 0000 80B4 push {r7} + 585 .cfi_def_cfa_offset 4 + 586 .cfi_offset 7, -4 + 587 0002 00AF add r7, sp, #0 + 588 .cfi_def_cfa_register 7 + 426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Set SEVONPEND bit of Cortex System Control Register */ + 427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); + 589 .loc 1 427 3 + 590 0004 054B ldr r3, .L37 + 591 0006 1B69 ldr r3, [r3, #16] + 592 0008 044A ldr r2, .L37 + 593 000a 43F01003 orr r3, r3, #16 + 594 000e 1361 str r3, [r2, #16] + 428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** } + 595 .loc 1 428 1 + 596 0010 00BF nop + 597 0012 BD46 mov sp, r7 + 598 .cfi_def_cfa_register 13 + 599 @ sp needed + 600 0014 5DF8047B ldr r7, [sp], #4 + 601 .cfi_restore 7 + 602 .cfi_def_cfa_offset 0 + 603 0018 7047 bx lr + 604 .L38: + 605 001a 00BF .align 2 + 606 .L37: + 607 001c 00ED00E0 .word -536810240 + 608 .cfi_endproc + 609 .LFE140: + 611 .section .text.HAL_PWR_DisableSEVOnPend,"ax",%progbits + 612 .align 1 + 613 .global HAL_PWR_DisableSEVOnPend + 614 .syntax unified + 615 .thumb + 616 .thumb_func + 618 HAL_PWR_DisableSEVOnPend: + ARM GAS /tmp/ccdoKIzP.s page 19 + + + 619 .LFB141: + 429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** + 431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** + 432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Disables CORTEX M4 SEVONPEND bit. + 433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes + 434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * WFE to wake up when an interrupt moves from inactive to pended. + 435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None + 436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */ + 437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_DisableSEVOnPend(void) + 438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** { + 620 .loc 1 438 1 + 621 .cfi_startproc + 622 @ args = 0, pretend = 0, frame = 0 + 623 @ frame_needed = 1, uses_anonymous_args = 0 + 624 @ link register save eliminated. + 625 0000 80B4 push {r7} + 626 .cfi_def_cfa_offset 4 + 627 .cfi_offset 7, -4 + 628 0002 00AF add r7, sp, #0 + 629 .cfi_def_cfa_register 7 + 439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Clear SEVONPEND bit of Cortex System Control Register */ + 440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); + 630 .loc 1 440 3 + 631 0004 054B ldr r3, .L40 + 632 0006 1B69 ldr r3, [r3, #16] + 633 0008 044A ldr r2, .L40 + 634 000a 23F01003 bic r3, r3, #16 + 635 000e 1361 str r3, [r2, #16] + 441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** } + 636 .loc 1 441 1 + 637 0010 00BF nop + 638 0012 BD46 mov sp, r7 + 639 .cfi_def_cfa_register 13 + 640 @ sp needed + 641 0014 5DF8047B ldr r7, [sp], #4 + 642 .cfi_restore 7 + 643 .cfi_def_cfa_offset 0 + 644 0018 7047 bx lr + 645 .L41: + 646 001a 00BF .align 2 + 647 .L40: + 648 001c 00ED00E0 .word -536810240 + 649 .cfi_endproc + 650 .LFE141: + 652 .text + 653 .Letext0: + 654 .file 2 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 655 .file 3 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 656 .file 4 "Drivers/CMSIS/Include/core_cm4.h" + 657 .file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + ARM GAS /tmp/ccdoKIzP.s page 20 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f3xx_hal_pwr.c + /tmp/ccdoKIzP.s:21 .text.HAL_PWR_DeInit:00000000 $t + /tmp/ccdoKIzP.s:27 .text.HAL_PWR_DeInit:00000000 HAL_PWR_DeInit + /tmp/ccdoKIzP.s:63 .text.HAL_PWR_DeInit:00000028 $d + /tmp/ccdoKIzP.s:68 .text.HAL_PWR_EnableBkUpAccess:00000000 $t + /tmp/ccdoKIzP.s:74 .text.HAL_PWR_EnableBkUpAccess:00000000 HAL_PWR_EnableBkUpAccess + /tmp/ccdoKIzP.s:104 .text.HAL_PWR_EnableBkUpAccess:0000001c $d + /tmp/ccdoKIzP.s:109 .text.HAL_PWR_DisableBkUpAccess:00000000 $t + /tmp/ccdoKIzP.s:115 .text.HAL_PWR_DisableBkUpAccess:00000000 HAL_PWR_DisableBkUpAccess + /tmp/ccdoKIzP.s:145 .text.HAL_PWR_DisableBkUpAccess:0000001c $d + /tmp/ccdoKIzP.s:150 .text.HAL_PWR_EnableWakeUpPin:00000000 $t + /tmp/ccdoKIzP.s:156 .text.HAL_PWR_EnableWakeUpPin:00000000 HAL_PWR_EnableWakeUpPin + /tmp/ccdoKIzP.s:192 .text.HAL_PWR_EnableWakeUpPin:00000020 $d + /tmp/ccdoKIzP.s:197 .text.HAL_PWR_DisableWakeUpPin:00000000 $t + /tmp/ccdoKIzP.s:203 .text.HAL_PWR_DisableWakeUpPin:00000000 HAL_PWR_DisableWakeUpPin + /tmp/ccdoKIzP.s:240 .text.HAL_PWR_DisableWakeUpPin:00000024 $d + /tmp/ccdoKIzP.s:245 .text.HAL_PWR_EnterSLEEPMode:00000000 $t + /tmp/ccdoKIzP.s:251 .text.HAL_PWR_EnterSLEEPMode:00000000 HAL_PWR_EnterSLEEPMode + /tmp/ccdoKIzP.s:319 .text.HAL_PWR_EnterSLEEPMode:00000034 $d + /tmp/ccdoKIzP.s:324 .text.HAL_PWR_EnterSTOPMode:00000000 $t + /tmp/ccdoKIzP.s:330 .text.HAL_PWR_EnterSTOPMode:00000000 HAL_PWR_EnterSTOPMode + /tmp/ccdoKIzP.s:426 .text.HAL_PWR_EnterSTOPMode:00000060 $d + /tmp/ccdoKIzP.s:432 .text.HAL_PWR_EnterSTANDBYMode:00000000 $t + /tmp/ccdoKIzP.s:438 .text.HAL_PWR_EnterSTANDBYMode:00000000 HAL_PWR_EnterSTANDBYMode + /tmp/ccdoKIzP.s:483 .text.HAL_PWR_EnterSTANDBYMode:00000028 $d + /tmp/ccdoKIzP.s:489 .text.HAL_PWR_EnableSleepOnExit:00000000 $t + /tmp/ccdoKIzP.s:495 .text.HAL_PWR_EnableSleepOnExit:00000000 HAL_PWR_EnableSleepOnExit + /tmp/ccdoKIzP.s:525 .text.HAL_PWR_EnableSleepOnExit:0000001c $d + /tmp/ccdoKIzP.s:530 .text.HAL_PWR_DisableSleepOnExit:00000000 $t + /tmp/ccdoKIzP.s:536 .text.HAL_PWR_DisableSleepOnExit:00000000 HAL_PWR_DisableSleepOnExit + /tmp/ccdoKIzP.s:566 .text.HAL_PWR_DisableSleepOnExit:0000001c $d + /tmp/ccdoKIzP.s:571 .text.HAL_PWR_EnableSEVOnPend:00000000 $t + /tmp/ccdoKIzP.s:577 .text.HAL_PWR_EnableSEVOnPend:00000000 HAL_PWR_EnableSEVOnPend + /tmp/ccdoKIzP.s:607 .text.HAL_PWR_EnableSEVOnPend:0000001c $d + /tmp/ccdoKIzP.s:612 .text.HAL_PWR_DisableSEVOnPend:00000000 $t + /tmp/ccdoKIzP.s:618 .text.HAL_PWR_DisableSEVOnPend:00000000 HAL_PWR_DisableSEVOnPend + /tmp/ccdoKIzP.s:648 .text.HAL_PWR_DisableSEVOnPend:0000001c $d + +NO UNDEFINED SYMBOLS diff --git a/Software/build/stm32f3xx_hal_pwr.o b/Software/build/stm32f3xx_hal_pwr.o new file mode 100644 index 0000000..f3466e1 Binary files /dev/null and b/Software/build/stm32f3xx_hal_pwr.o differ diff --git a/Software/build/stm32f3xx_hal_pwr_ex.d b/Software/build/stm32f3xx_hal_pwr_ex.d new file mode 100644 index 0000000..74ec6a6 --- /dev/null +++ b/Software/build/stm32f3xx_hal_pwr_ex.d @@ -0,0 +1,62 @@ +build/stm32f3xx_hal_pwr_ex.o: \ + Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + Core/Inc/stm32f3xx_hal_conf.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h: diff --git a/Software/build/stm32f3xx_hal_pwr_ex.lst b/Software/build/stm32f3xx_hal_pwr_ex.lst new file mode 100644 index 0000000..a068adb --- /dev/null +++ b/Software/build/stm32f3xx_hal_pwr_ex.lst @@ -0,0 +1,568 @@ +ARM GAS /tmp/ccb21fMF.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 6 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "stm32f3xx_hal_pwr_ex.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c" + 20 .section .text.HAL_PWR_ConfigPVD,"ax",%progbits + 21 .align 1 + 22 .global HAL_PWR_ConfigPVD + 23 .syntax unified + 24 .thumb + 25 .thumb_func + 27 HAL_PWR_ConfigPVD: + 28 .LFB130: + 1:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /** + 2:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** ****************************************************************************** + 3:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @file stm32f3xx_hal_pwr_ex.c + 4:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @author MCD Application Team + 5:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @brief Extended PWR HAL module driver. + 6:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * functionalities of the Power Controller (PWR) peripheral: + 8:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * + Extended Initialization and de-initialization functions + 9:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * + Extended Peripheral Control functions + 10:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * + 11:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** ****************************************************************************** + 12:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @attention + 13:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * + 14:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * Copyright (c) 2016 STMicroelectronics. + 15:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * All rights reserved. + 16:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * + 17:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * This software is licensed under terms that can be found in the LICENSE file + 18:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * in the root directory of this software component. + 19:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 20:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * + 21:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** ****************************************************************************** + 22:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** */ + 23:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 24:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* Includes ------------------------------------------------------------------*/ + 25:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** #include "stm32f3xx_hal.h" + 26:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 27:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /** @addtogroup STM32F3xx_HAL_Driver + 28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @{ + 29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** */ + 30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + ARM GAS /tmp/ccb21fMF.s page 2 + + + 31:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /** @defgroup PWREx PWREx + 32:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @brief PWREx HAL module driver + 33:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @{ + 34:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** */ + 35:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 36:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** #ifdef HAL_PWR_MODULE_ENABLED + 37:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 38:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* Private typedef -----------------------------------------------------------*/ + 39:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* Private define ------------------------------------------------------------*/ + 40:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /** @defgroup PWREx_Private_Constants PWR Extended Private Constants + 41:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @{ + 42:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** */ + 43:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** #define PVD_MODE_IT (0x00010000U) + 44:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** #define PVD_MODE_EVT (0x00020000U) + 45:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** #define PVD_RISING_EDGE (0x00000001U) + 46:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** #define PVD_FALLING_EDGE (0x00000002U) + 47:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /** + 48:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @} + 49:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** */ + 50:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 51:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* Private macro -------------------------------------------------------------*/ + 52:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* Private variables ---------------------------------------------------------*/ + 53:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* Private function prototypes -----------------------------------------------*/ + 54:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* Exported functions ---------------------------------------------------------*/ + 55:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 56:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions + 57:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @{ + 58:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** */ + 59:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 60:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended Control Functions + 61:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @brief Extended Peripheral Control functions + 62:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * + 63:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** @verbatim + 64:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 65:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** =============================================================================== + 66:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** ##### Peripheral Extended control functions ##### + 67:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** =============================================================================== + 68:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** *** PVD configuration (present on all other devices than STM32F3x8 devices) *** + 69:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** ========================= + 70:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** [..] + 71:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** (+) The PVD is used to monitor the VDD power supply by comparing it to a + 72:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). + 73:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower + 74:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** than the PVD threshold. This event is internally connected to the EXTI + 75:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** line16 and can generate an interrupt if enabled. This is done through + 76:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** __HAL_PWR_PVD_EXTI_ENABLE_IT() macro + 77:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** (+) The PVD is stopped in Standby mode. + 78:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** -@- PVD is not available on STM32F3x8 Product Line + 79:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 80:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 81:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** *** Voltage regulator *** + 82:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** ========================= + 83:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** [..] + 84:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** (+) The voltage regulator is always enabled after Reset. It works in three different + 85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** modes. + 86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** In Run mode, the regulator supplies full power to the 1.8V domain (core, memories + 87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** and digital peripherals). + ARM GAS /tmp/ccb21fMF.s page 3 + + + 88:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** In Stop mode, the regulator supplies low power to the 1.8V domain, preserving + 89:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** contents of registers and SRAM. + 90:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** In Stop mode, the regulator is powered off. The contents of the registers and SRAM + 91:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** are lost except for the Standby circuitry and the Backup Domain. + 92:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** Note: in the STM32F3x8xx devices, the voltage regulator is bypassed and the + 93:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** microcontroller must be powered from a nominal VDD = 1.8V +/-8U% voltage. + 94:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 95:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 96:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower + 97:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** than the PVD threshold. This event is internally connected to the EXTI + 98:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** line16 and can generate an interrupt if enabled. This is done through + 99:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** __HAL_PWR_PVD_EXTI_ENABLE_IT() macro + 100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** (+) The PVD is stopped in Standby mode. + 101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** *** SDADC power configuration *** + 104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** ================================ + 105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** [..] + 106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** (+) On STM32F373xC/STM32F378xx devices, there are up to + 107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** 3 SDADC instances that can be enabled/disabled. + 108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** @endverbatim + 110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @{ + 111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** */ + 112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** #if defined(STM32F302xE) || defined(STM32F303xE) || \ + 114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** defined(STM32F302xC) || defined(STM32F303xC) || \ + 115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** defined(STM32F303x8) || defined(STM32F334x8) || \ + 116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** defined(STM32F301x8) || defined(STM32F302x8) || \ + 117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** defined(STM32F373xC) + 118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /** + 120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). + 121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration + 122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * information for the PVD. + 123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @note Refer to the electrical characteristics of your device datasheet for + 124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * more details about the voltage threshold corresponding to each + 125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * detection level. + 126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @retval None + 127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** */ + 128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) + 129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** { + 29 .loc 1 129 1 + 30 .cfi_startproc + 31 @ args = 0, pretend = 0, frame = 8 + 32 @ frame_needed = 1, uses_anonymous_args = 0 + 33 @ link register save eliminated. + 34 0000 80B4 push {r7} + 35 .cfi_def_cfa_offset 4 + 36 .cfi_offset 7, -4 + 37 0002 83B0 sub sp, sp, #12 + 38 .cfi_def_cfa_offset 16 + 39 0004 00AF add r7, sp, #0 + 40 .cfi_def_cfa_register 7 + 41 0006 7860 str r0, [r7, #4] + 130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* Check the parameters */ + 131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); + ARM GAS /tmp/ccb21fMF.s page 4 + + + 132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); + 133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* Set PLS[7:5] bits according to PVDLevel value */ + 135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel); + 42 .loc 1 135 3 + 43 0008 2B4B ldr r3, .L7 + 44 000a 1B68 ldr r3, [r3] + 45 000c 23F0E002 bic r2, r3, #224 + 46 0010 7B68 ldr r3, [r7, #4] + 47 0012 1B68 ldr r3, [r3] + 48 0014 2849 ldr r1, .L7 + 49 0016 1343 orrs r3, r3, r2 + 50 0018 0B60 str r3, [r1] + 136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* Clear any previous config. Keep it clear if no event or IT mode is selected */ + 138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); + 51 .loc 1 138 3 + 52 001a 284B ldr r3, .L7+4 + 53 001c 5B68 ldr r3, [r3, #4] + 54 001e 274A ldr r2, .L7+4 + 55 0020 23F48033 bic r3, r3, #65536 + 56 0024 5360 str r3, [r2, #4] + 139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** __HAL_PWR_PVD_EXTI_DISABLE_IT(); + 57 .loc 1 139 3 + 58 0026 254B ldr r3, .L7+4 + 59 0028 1B68 ldr r3, [r3] + 60 002a 244A ldr r2, .L7+4 + 61 002c 23F48033 bic r3, r3, #65536 + 62 0030 1360 str r3, [r2] + 140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); + 63 .loc 1 140 3 + 64 0032 224B ldr r3, .L7+4 + 65 0034 9B68 ldr r3, [r3, #8] + 66 0036 214A ldr r2, .L7+4 + 67 0038 23F48033 bic r3, r3, #65536 + 68 003c 9360 str r3, [r2, #8] + 69 .loc 1 140 44 + 70 003e 1F4B ldr r3, .L7+4 + 71 0040 DB68 ldr r3, [r3, #12] + 72 0042 1E4A ldr r2, .L7+4 + 73 0044 23F48033 bic r3, r3, #65536 + 74 0048 D360 str r3, [r2, #12] + 141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* Configure interrupt mode */ + 143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) + 75 .loc 1 143 17 + 76 004a 7B68 ldr r3, [r7, #4] + 77 004c 5B68 ldr r3, [r3, #4] + 78 .loc 1 143 24 + 79 004e 03F48033 and r3, r3, #65536 + 80 .loc 1 143 5 + 81 0052 002B cmp r3, #0 + 82 0054 05D0 beq .L2 + 144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** { + 145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** __HAL_PWR_PVD_EXTI_ENABLE_IT(); + 83 .loc 1 145 5 + 84 0056 194B ldr r3, .L7+4 + ARM GAS /tmp/ccb21fMF.s page 5 + + + 85 0058 1B68 ldr r3, [r3] + 86 005a 184A ldr r2, .L7+4 + 87 005c 43F48033 orr r3, r3, #65536 + 88 0060 1360 str r3, [r2] + 89 .L2: + 146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** } + 147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* Configure event mode */ + 149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) + 90 .loc 1 149 17 + 91 0062 7B68 ldr r3, [r7, #4] + 92 0064 5B68 ldr r3, [r3, #4] + 93 .loc 1 149 24 + 94 0066 03F40033 and r3, r3, #131072 + 95 .loc 1 149 5 + 96 006a 002B cmp r3, #0 + 97 006c 05D0 beq .L3 + 150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** { + 151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); + 98 .loc 1 151 5 + 99 006e 134B ldr r3, .L7+4 + 100 0070 5B68 ldr r3, [r3, #4] + 101 0072 124A ldr r2, .L7+4 + 102 0074 43F48033 orr r3, r3, #65536 + 103 0078 5360 str r3, [r2, #4] + 104 .L3: + 152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** } + 153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* Configure the edge */ + 155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) + 105 .loc 1 155 17 + 106 007a 7B68 ldr r3, [r7, #4] + 107 007c 5B68 ldr r3, [r3, #4] + 108 .loc 1 155 24 + 109 007e 03F00103 and r3, r3, #1 + 110 .loc 1 155 5 + 111 0082 002B cmp r3, #0 + 112 0084 05D0 beq .L4 + 156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** { + 157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); + 113 .loc 1 157 5 + 114 0086 0D4B ldr r3, .L7+4 + 115 0088 9B68 ldr r3, [r3, #8] + 116 008a 0C4A ldr r2, .L7+4 + 117 008c 43F48033 orr r3, r3, #65536 + 118 0090 9360 str r3, [r2, #8] + 119 .L4: + 158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** } + 159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) + 120 .loc 1 160 17 + 121 0092 7B68 ldr r3, [r7, #4] + 122 0094 5B68 ldr r3, [r3, #4] + 123 .loc 1 160 24 + 124 0096 03F00203 and r3, r3, #2 + 125 .loc 1 160 5 + 126 009a 002B cmp r3, #0 + ARM GAS /tmp/ccb21fMF.s page 6 + + + 127 009c 05D0 beq .L6 + 161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** { + 162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); + 128 .loc 1 162 5 + 129 009e 074B ldr r3, .L7+4 + 130 00a0 DB68 ldr r3, [r3, #12] + 131 00a2 064A ldr r2, .L7+4 + 132 00a4 43F48033 orr r3, r3, #65536 + 133 00a8 D360 str r3, [r2, #12] + 134 .L6: + 163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** } + 164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** } + 135 .loc 1 164 1 + 136 00aa 00BF nop + 137 00ac 0C37 adds r7, r7, #12 + 138 .cfi_def_cfa_offset 4 + 139 00ae BD46 mov sp, r7 + 140 .cfi_def_cfa_register 13 + 141 @ sp needed + 142 00b0 5DF8047B ldr r7, [sp], #4 + 143 .cfi_restore 7 + 144 .cfi_def_cfa_offset 0 + 145 00b4 7047 bx lr + 146 .L8: + 147 00b6 00BF .align 2 + 148 .L7: + 149 00b8 00700040 .word 1073770496 + 150 00bc 00040140 .word 1073808384 + 151 .cfi_endproc + 152 .LFE130: + 154 .section .text.HAL_PWR_EnablePVD,"ax",%progbits + 155 .align 1 + 156 .global HAL_PWR_EnablePVD + 157 .syntax unified + 158 .thumb + 159 .thumb_func + 161 HAL_PWR_EnablePVD: + 162 .LFB131: + 165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /** + 167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @brief Enables the Power Voltage Detector(PVD). + 168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @retval None + 169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** */ + 170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** void HAL_PWR_EnablePVD(void) + 171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** { + 163 .loc 1 171 1 + 164 .cfi_startproc + 165 @ args = 0, pretend = 0, frame = 0 + 166 @ frame_needed = 1, uses_anonymous_args = 0 + 167 @ link register save eliminated. + 168 0000 80B4 push {r7} + 169 .cfi_def_cfa_offset 4 + 170 .cfi_offset 7, -4 + 171 0002 00AF add r7, sp, #0 + 172 .cfi_def_cfa_register 7 + 172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** SET_BIT(PWR->CR, PWR_CR_PVDE); + 173 .loc 1 172 3 + ARM GAS /tmp/ccb21fMF.s page 7 + + + 174 0004 054B ldr r3, .L10 + 175 0006 1B68 ldr r3, [r3] + 176 0008 044A ldr r2, .L10 + 177 000a 43F01003 orr r3, r3, #16 + 178 000e 1360 str r3, [r2] + 173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** } + 179 .loc 1 173 1 + 180 0010 00BF nop + 181 0012 BD46 mov sp, r7 + 182 .cfi_def_cfa_register 13 + 183 @ sp needed + 184 0014 5DF8047B ldr r7, [sp], #4 + 185 .cfi_restore 7 + 186 .cfi_def_cfa_offset 0 + 187 0018 7047 bx lr + 188 .L11: + 189 001a 00BF .align 2 + 190 .L10: + 191 001c 00700040 .word 1073770496 + 192 .cfi_endproc + 193 .LFE131: + 195 .section .text.HAL_PWR_DisablePVD,"ax",%progbits + 196 .align 1 + 197 .global HAL_PWR_DisablePVD + 198 .syntax unified + 199 .thumb + 200 .thumb_func + 202 HAL_PWR_DisablePVD: + 203 .LFB132: + 174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /** + 176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @brief Disables the Power Voltage Detector(PVD). + 177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @retval None + 178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** */ + 179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** void HAL_PWR_DisablePVD(void) + 180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** { + 204 .loc 1 180 1 + 205 .cfi_startproc + 206 @ args = 0, pretend = 0, frame = 0 + 207 @ frame_needed = 1, uses_anonymous_args = 0 + 208 @ link register save eliminated. + 209 0000 80B4 push {r7} + 210 .cfi_def_cfa_offset 4 + 211 .cfi_offset 7, -4 + 212 0002 00AF add r7, sp, #0 + 213 .cfi_def_cfa_register 7 + 181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** CLEAR_BIT(PWR->CR, PWR_CR_PVDE); + 214 .loc 1 181 3 + 215 0004 054B ldr r3, .L13 + 216 0006 1B68 ldr r3, [r3] + 217 0008 044A ldr r2, .L13 + 218 000a 23F01003 bic r3, r3, #16 + 219 000e 1360 str r3, [r2] + 182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** } + 220 .loc 1 182 1 + 221 0010 00BF nop + 222 0012 BD46 mov sp, r7 + ARM GAS /tmp/ccb21fMF.s page 8 + + + 223 .cfi_def_cfa_register 13 + 224 @ sp needed + 225 0014 5DF8047B ldr r7, [sp], #4 + 226 .cfi_restore 7 + 227 .cfi_def_cfa_offset 0 + 228 0018 7047 bx lr + 229 .L14: + 230 001a 00BF .align 2 + 231 .L13: + 232 001c 00700040 .word 1073770496 + 233 .cfi_endproc + 234 .LFE132: + 236 .section .text.HAL_PWR_PVD_IRQHandler,"ax",%progbits + 237 .align 1 + 238 .global HAL_PWR_PVD_IRQHandler + 239 .syntax unified + 240 .thumb + 241 .thumb_func + 243 HAL_PWR_PVD_IRQHandler: + 244 .LFB133: + 183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /** + 185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @brief This function handles the PWR PVD interrupt request. + 186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @note This API should be called under the PVD_IRQHandler(). + 187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @retval None + 188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** */ + 189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** void HAL_PWR_PVD_IRQHandler(void) + 190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** { + 245 .loc 1 190 1 + 246 .cfi_startproc + 247 @ args = 0, pretend = 0, frame = 0 + 248 @ frame_needed = 1, uses_anonymous_args = 0 + 249 0000 80B5 push {r7, lr} + 250 .cfi_def_cfa_offset 8 + 251 .cfi_offset 7, -8 + 252 .cfi_offset 14, -4 + 253 0002 00AF add r7, sp, #0 + 254 .cfi_def_cfa_register 7 + 191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* Check PWR exti flag */ + 192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) + 255 .loc 1 192 6 + 256 0004 064B ldr r3, .L18 + 257 0006 5B69 ldr r3, [r3, #20] + 258 0008 03F48033 and r3, r3, #65536 + 259 .loc 1 192 5 + 260 000c 002B cmp r3, #0 + 261 000e 05D0 beq .L17 + 193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** { + 194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* PWR PVD interrupt user callback */ + 195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** HAL_PWR_PVDCallback(); + 262 .loc 1 195 5 + 263 0010 FFF7FEFF bl HAL_PWR_PVDCallback + 196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* Clear PWR Exti pending bit */ + 198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); + 264 .loc 1 198 5 + 265 0014 024B ldr r3, .L18 + ARM GAS /tmp/ccb21fMF.s page 9 + + + 266 0016 4FF48032 mov r2, #65536 + 267 001a 5A61 str r2, [r3, #20] + 268 .L17: + 199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** } + 200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** } + 269 .loc 1 200 1 + 270 001c 00BF nop + 271 001e 80BD pop {r7, pc} + 272 .L19: + 273 .align 2 + 274 .L18: + 275 0020 00040140 .word 1073808384 + 276 .cfi_endproc + 277 .LFE133: + 279 .section .text.HAL_PWR_PVDCallback,"ax",%progbits + 280 .align 1 + 281 .weak HAL_PWR_PVDCallback + 282 .syntax unified + 283 .thumb + 284 .thumb_func + 286 HAL_PWR_PVDCallback: + 287 .LFB134: + 201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** + 202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /** + 203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @brief PWR PVD interrupt callback + 204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** * @retval None + 205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** */ + 206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** __weak void HAL_PWR_PVDCallback(void) + 207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** { + 288 .loc 1 207 1 + 289 .cfi_startproc + 290 @ args = 0, pretend = 0, frame = 0 + 291 @ frame_needed = 1, uses_anonymous_args = 0 + 292 @ link register save eliminated. + 293 0000 80B4 push {r7} + 294 .cfi_def_cfa_offset 4 + 295 .cfi_offset 7, -4 + 296 0002 00AF add r7, sp, #0 + 297 .cfi_def_cfa_register 7 + 208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** /* NOTE : This function Should not be modified, when the callback is needed, + 209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** the HAL_PWR_PVDCallback could be implemented in the user file + 210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** */ + 211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr_ex.c **** } + 298 .loc 1 211 1 + 299 0004 00BF nop + 300 0006 BD46 mov sp, r7 + 301 .cfi_def_cfa_register 13 + 302 @ sp needed + 303 0008 5DF8047B ldr r7, [sp], #4 + 304 .cfi_restore 7 + 305 .cfi_def_cfa_offset 0 + 306 000c 7047 bx lr + 307 .cfi_endproc + 308 .LFE134: + 310 .text + 311 .Letext0: + 312 .file 2 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + ARM GAS /tmp/ccb21fMF.s page 10 + + + 313 .file 3 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 314 .file 4 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + 315 .file 5 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h" + 316 .file 6 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h" + ARM GAS /tmp/ccb21fMF.s page 11 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f3xx_hal_pwr_ex.c + /tmp/ccb21fMF.s:21 .text.HAL_PWR_ConfigPVD:00000000 $t + /tmp/ccb21fMF.s:27 .text.HAL_PWR_ConfigPVD:00000000 HAL_PWR_ConfigPVD + /tmp/ccb21fMF.s:149 .text.HAL_PWR_ConfigPVD:000000b8 $d + /tmp/ccb21fMF.s:155 .text.HAL_PWR_EnablePVD:00000000 $t + /tmp/ccb21fMF.s:161 .text.HAL_PWR_EnablePVD:00000000 HAL_PWR_EnablePVD + /tmp/ccb21fMF.s:191 .text.HAL_PWR_EnablePVD:0000001c $d + /tmp/ccb21fMF.s:196 .text.HAL_PWR_DisablePVD:00000000 $t + /tmp/ccb21fMF.s:202 .text.HAL_PWR_DisablePVD:00000000 HAL_PWR_DisablePVD + /tmp/ccb21fMF.s:232 .text.HAL_PWR_DisablePVD:0000001c $d + /tmp/ccb21fMF.s:237 .text.HAL_PWR_PVD_IRQHandler:00000000 $t + /tmp/ccb21fMF.s:243 .text.HAL_PWR_PVD_IRQHandler:00000000 HAL_PWR_PVD_IRQHandler + /tmp/ccb21fMF.s:286 .text.HAL_PWR_PVDCallback:00000000 HAL_PWR_PVDCallback + /tmp/ccb21fMF.s:275 .text.HAL_PWR_PVD_IRQHandler:00000020 $d + /tmp/ccb21fMF.s:280 .text.HAL_PWR_PVDCallback:00000000 $t + +NO UNDEFINED SYMBOLS diff --git a/Software/build/stm32f3xx_hal_pwr_ex.o b/Software/build/stm32f3xx_hal_pwr_ex.o new file mode 100644 index 0000000..4c49809 Binary files /dev/null and b/Software/build/stm32f3xx_hal_pwr_ex.o differ diff --git a/Software/build/stm32f3xx_hal_rcc.d b/Software/build/stm32f3xx_hal_rcc.d new file mode 100644 index 0000000..57ca011 --- /dev/null +++ b/Software/build/stm32f3xx_hal_rcc.d @@ -0,0 +1,62 @@ +build/stm32f3xx_hal_rcc.o: \ + Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + Core/Inc/stm32f3xx_hal_conf.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h: diff --git a/Software/build/stm32f3xx_hal_rcc.lst b/Software/build/stm32f3xx_hal_rcc.lst new file mode 100644 index 0000000..725762b --- /dev/null +++ b/Software/build/stm32f3xx_hal_rcc.lst @@ -0,0 +1,6923 @@ +ARM GAS /tmp/ccSuWkwR.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 6 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "stm32f3xx_hal_rcc.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c" + 20 .section .rodata.aPLLMULFactorTable,"a" + 21 .align 2 + 24 aPLLMULFactorTable: + 25 0000 02030405 .ascii "\002\003\004\005\006\007\010\011\012\013\014\015\016" + 25 06070809 + 25 0A0B0C0D + 25 0E + 26 000d 0F1010 .ascii "\017\020\020" + 27 .section .rodata.aPredivFactorTable,"a" + 28 .align 2 + 31 aPredivFactorTable: + 32 0000 01020304 .ascii "\001\002\003\004\005\006\007\010\011\012\013\014\015" + 32 05060708 + 32 090A0B0C + 32 0D + 33 000d 0E0F10 .ascii "\016\017\020" + 34 .section .text.HAL_RCC_DeInit,"ax",%progbits + 35 .align 1 + 36 .global HAL_RCC_DeInit + 37 .syntax unified + 38 .thumb + 39 .thumb_func + 41 HAL_RCC_DeInit: + 42 .LFB130: + 1:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** + 2:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** ****************************************************************************** + 3:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @file stm32f3xx_hal_rcc.c + 4:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @author MCD Application Team + 5:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief RCC HAL module driver. + 6:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * functionalities of the Reset and Clock Control (RCC) peripheral: + 8:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * + Initialization and de-initialization functions + 9:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * + Peripheral Control functions + 10:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * + 11:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** @verbatim + 12:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** ============================================================================== + 13:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** ##### RCC specific features ##### + 14:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** ============================================================================== + ARM GAS /tmp/ccSuWkwR.s page 2 + + + 15:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** [..] + 16:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** After reset the device is running from Internal High Speed oscillator + 17:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled, + 18:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** and all peripherals are off except internal SRAM, Flash and JTAG. + 19:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses; + 20:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** all peripherals mapped on these buses are running at HSI speed. + 21:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (+) The clock for all peripherals is switched off, except the SRAM and FLASH. + 22:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (+) All GPIOs are in input floating state, except the JTAG pins which + 23:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** are assigned to be used for debug purpose. + 24:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** [..] Once the device started from reset, the user application has to: + 25:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (+) Configure the clock source to be used to drive the System clock + 26:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (if the application needs higher frequency/performance) + 27:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (+) Configure the System clock frequency and Flash settings + 28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (+) Configure the AHB and APB buses prescalers + 29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (+) Enable the clock for the peripheral(s) to be used + 30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (+) Configure the clock source(s) for peripherals whose clocks are not + 31:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** derived from the System clock (RTC, ADC, I2C, I2S, TIM, USB FS) + 32:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 33:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** ##### RCC Limitations ##### + 34:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** ============================================================================== + 35:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** [..] + 36:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** A delay between an RCC peripheral clock enable and the effective peripheral + 37:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** enabling should be taken into account in order to manage the peripheral read/write + 38:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** from/to registers. + 39:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (+) This delay depends on the peripheral mapping. + 40:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (++) AHB & APB peripherals, 1 dummy read is necessary + 41:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 42:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** [..] + 43:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** Workarounds: + 44:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + 45:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro. + 46:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 47:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** @endverbatim + 48:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** ****************************************************************************** + 49:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @attention + 50:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * + 51:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * Copyright (c) 2016 STMicroelectronics. + 52:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * All rights reserved. + 53:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * + 54:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * This software is licensed under terms that can be found in the LICENSE file in + 55:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * the root directory of this software component. + 56:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 57:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** ****************************************************************************** + 58:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ + 59:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 60:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Includes ------------------------------------------------------------------*/ + 61:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #include "stm32f3xx_hal.h" + 62:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 63:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** @addtogroup STM32F3xx_HAL_Driver + 64:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @{ + 65:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ + 66:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 67:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** @defgroup RCC RCC + 68:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief RCC HAL module driver + 69:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @{ + 70:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ + 71:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + ARM GAS /tmp/ccSuWkwR.s page 3 + + + 72:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #ifdef HAL_RCC_MODULE_ENABLED + 73:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 74:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Private typedef -----------------------------------------------------------*/ + 75:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Private define ------------------------------------------------------------*/ + 76:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** @defgroup RCC_Private_Constants RCC Private Constants + 77:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @{ + 78:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ + 79:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Bits position in in the CFGR register */ + 80:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #define RCC_CFGR_HPRE_BITNUMBER POSITION_VAL(RCC_CFGR_HPRE) + 81:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #define RCC_CFGR_PPRE1_BITNUMBER POSITION_VAL(RCC_CFGR_PPRE1) + 82:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #define RCC_CFGR_PPRE2_BITNUMBER POSITION_VAL(RCC_CFGR_PPRE2) + 83:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** + 84:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @} + 85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ + 86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Private macro -------------------------------------------------------------*/ + 87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** @defgroup RCC_Private_Macros RCC Private Macros + 88:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @{ + 89:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ + 90:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 91:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() + 92:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #define MCO1_GPIO_PORT GPIOA + 93:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #define MCO1_PIN GPIO_PIN_8 + 94:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 95:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** + 96:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @} + 97:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ + 98:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 99:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Private variables ---------------------------------------------------------*/ + 100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** @defgroup RCC_Private_Variables RCC Private Variables + 101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @{ + 102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ + 103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** static const uint8_t aPLLMULFactorTable[16U] = { 2U, 3U, 4U, 5U, 6U, 7U, 8U, 9U, + 104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 10U, 11U, 12U, 13U, 14U, 15U, 16U, 16U}; + 105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** static const uint8_t aPredivFactorTable[16U] = { 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U, + 106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** 9U,10U, 11U, 12U, 13U, 14U, 15U, 16U}; + 107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** + 108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @} + 109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ + 110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Private function prototypes -----------------------------------------------*/ + 112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Exported functions ---------------------------------------------------------*/ + 113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** @defgroup RCC_Exported_Functions RCC Exported Functions + 115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @{ + 116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ + 117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions + 119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief Initialization and Configuration functions + 120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * + 121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** @verbatim + 122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** =============================================================================== + 123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** ##### Initialization and de-initialization functions ##### + 124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** =============================================================================== + 125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** [..] + 126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** This section provides functions allowing to configure the internal/external oscillators + 127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1 + 128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** and APB2). + ARM GAS /tmp/ccSuWkwR.s page 4 + + + 129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** [..] Internal/external clock and PLL configuration + 131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through + 132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** the PLL as System clock source. + 133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** The HSI clock can be used also to clock the USART and I2C peripherals. + 134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (#) LSI (low-speed internal), ~40 KHz low consumption RC used as IWDG and/or RTC + 136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** clock source. + 137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or + 139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** through the PLL as System clock source. Can be used also as RTC clock source. + 140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. + 142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (#) PLL (clocked by HSI or HSE), featuring different output clocks: + 144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (++) The first output is used to generate the high speed system clock (up to 72 MHz) + 145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (++) The second output is used to generate the clock for the USB FS (48 MHz) + 146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (++) The third output may be used to generate the clock for the ADC peripherals (up to 72 M + 147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (++) The fourth output may be used to generate the clock for the TIM peripherals (144 MHz) + 148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE() + 150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** and if a HSE clock failure occurs(HSE used directly or through PLL as System + 151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** clock source), the System clocks automatically switched to HSI and an interrupt + 152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** is generated if enabled. The interrupt is linked to the Cortex-M4 NMI + 153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (Non-Maskable Interrupt) exception vector. + 154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSE, LSI, LSE or PLL + 156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** clock (divided by 2) output on pin (such as PA8 pin). + 157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** [..] System, AHB and APB buses clocks configuration + 159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI, + 160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** HSE and PLL. + 161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** The AHB clock (HCLK) is derived from System clock through configurable + 162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** prescaler and used to clock the CPU, memory and peripherals mapped + 163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived + 164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** from AHB clock through configurable prescalers and used to clock + 165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** the peripherals mapped on these buses. You can use + 166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. + 167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (#) All the peripheral clocks are derived from the System clock (SYSCLK) except: + 169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (++) The FLASH program/erase clock which is always HSI 8MHz clock. + 170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (++) The USB 48 MHz clock which is derived from the PLL VCO clock. + 171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (++) The USART clock which can be derived as well from HSI 8MHz, LSI or LSE. + 172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (++) The I2C clock which can be derived as well from HSI 8MHz clock. + 173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (++) The ADC clock which is derived from PLL output. + 174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (++) The RTC clock which is derived from the LSE, LSI or 1 MHz HSE_RTC + 175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (HSE divided by a programmable prescaler). The System clock (SYSCLK) + 176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** frequency must be higher or equal to the RTC clock frequency. + 177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (++) IWDG clock which is always the LSI clock. + 178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (#) For the STM32F3xx devices, the maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 + 180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** Depending on the SYSCLK frequency, the flash latency should be adapted accordingly. + 181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and + 183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** prefetch is disabled. + 184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** @endverbatim + 185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @{ + ARM GAS /tmp/ccSuWkwR.s page 5 + + + 186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ + 187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* + 189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** Additional consideration on the SYSCLK based on Latency settings: + 190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** +-----------------------------------------------+ + 191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** | Latency | SYSCLK clock frequency (MHz) | + 192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** |---------------|-------------------------------| + 193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** |0WS(1CPU cycle)| 0 < SYSCLK <= 24 | + 194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** |---------------|-------------------------------| + 195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** |1WS(2CPU cycle)| 24 < SYSCLK <= 48 | + 196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** |---------------|-------------------------------| + 197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** |2WS(3CPU cycle)| 48 < SYSCLK <= 72 | + 198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** +-----------------------------------------------+ + 199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ + 200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** + 202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief Resets the RCC clock configuration to the default reset state. + 203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note The default reset state of the clock configuration is given below: + 204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * - HSI ON and used as system clock source + 205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * - HSE and PLL OFF + 206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * - AHB, APB1 and APB2 prescaler set to 1. + 207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * - CSS and MCO1 OFF + 208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * - All interrupts disabled + 209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note This function does not modify the configuration of the + 210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * - Peripheral clocks + 211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * - LSI, LSE and RTC clocks + 212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @retval HAL status + 213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ + 214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** HAL_StatusTypeDef HAL_RCC_DeInit(void) + 215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 43 .loc 1 215 1 + 44 .cfi_startproc + 45 @ args = 0, pretend = 0, frame = 16 + 46 @ frame_needed = 1, uses_anonymous_args = 0 + 47 0000 80B5 push {r7, lr} + 48 .cfi_def_cfa_offset 8 + 49 .cfi_offset 7, -8 + 50 .cfi_offset 14, -4 + 51 0002 84B0 sub sp, sp, #16 + 52 .cfi_def_cfa_offset 24 + 53 0004 00AF add r7, sp, #0 + 54 .cfi_def_cfa_register 7 + 216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** uint32_t tickstart = 0; + 55 .loc 1 216 12 + 56 0006 0023 movs r3, #0 + 57 0008 FB60 str r3, [r7, #12] + 217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Set HSION bit */ + 219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** SET_BIT(RCC->CR, RCC_CR_HSION); + 58 .loc 1 219 3 + 59 000a 494B ldr r3, .L11 + 60 000c 1B68 ldr r3, [r3] + 61 000e 484A ldr r2, .L11 + 62 0010 43F00103 orr r3, r3, #1 + 63 0014 1360 str r3, [r2] + 220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Insure HSIRDY bit is set before writing default HSITRIM value */ + ARM GAS /tmp/ccSuWkwR.s page 6 + + + 222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get start tick */ + 223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 64 .loc 1 223 15 + 65 0016 FFF7FEFF bl HAL_GetTick + 66 001a F860 str r0, [r7, #12] + 224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Wait till HSI is ready */ + 226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) + 67 .loc 1 226 8 + 68 001c 08E0 b .L2 + 69 .L4: + 227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + 70 .loc 1 228 9 + 71 001e FFF7FEFF bl HAL_GetTick + 72 0022 0246 mov r2, r0 + 73 .loc 1 228 23 discriminator 1 + 74 0024 FB68 ldr r3, [r7, #12] + 75 0026 D31A subs r3, r2, r3 + 76 .loc 1 228 7 discriminator 1 + 77 0028 022B cmp r3, #2 + 78 002a 01D9 bls .L2 + 229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_TIMEOUT; + 79 .loc 1 230 14 + 80 002c 0323 movs r3, #3 + 81 002e 7BE0 b .L3 + 82 .L2: + 226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 83 .loc 1 226 9 + 84 0030 3F4B ldr r3, .L11 + 85 0032 1B68 ldr r3, [r3] + 86 0034 03F00203 and r3, r3, #2 + 226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 87 .loc 1 226 42 + 88 0038 002B cmp r3, #0 + 89 003a F0D0 beq .L4 + 231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Set HSITRIM default value */ + 235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, RCC_CR_HSITRIM_4); + 90 .loc 1 235 3 + 91 003c 3C4B ldr r3, .L11 + 92 003e 1B68 ldr r3, [r3] + 93 0040 23F0F803 bic r3, r3, #248 + 94 0044 3A4A ldr r2, .L11 + 95 0046 43F08003 orr r3, r3, #128 + 96 004a 1360 str r3, [r2] + 236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0] and MCOSEL[2:0] bits */ + 238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2 | RCC_CFGR_MCO + 97 .loc 1 238 3 + 98 004c 384B ldr r3, .L11 + 99 004e 5A68 ldr r2, [r3, #4] + 100 0050 3749 ldr r1, .L11 + 101 0052 384B ldr r3, .L11+4 + ARM GAS /tmp/ccSuWkwR.s page 7 + + + 102 0054 1340 ands r3, r3, r2 + 103 0056 4B60 str r3, [r1, #4] + 239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Insure HSI selected as system clock source */ + 241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get start tick */ + 242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 104 .loc 1 242 15 + 105 0058 FFF7FEFF bl HAL_GetTick + 106 005c F860 str r0, [r7, #12] + 243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Wait till system clock source is ready */ + 245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while(READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) + 107 .loc 1 245 8 + 108 005e 0AE0 b .L5 + 109 .L6: + 246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + 110 .loc 1 247 9 + 111 0060 FFF7FEFF bl HAL_GetTick + 112 0064 0246 mov r2, r0 + 113 .loc 1 247 23 discriminator 1 + 114 0066 FB68 ldr r3, [r7, #12] + 115 0068 D31A subs r3, r2, r3 + 116 .loc 1 247 7 discriminator 1 + 117 006a 41F28832 movw r2, #5000 + 118 006e 9342 cmp r3, r2 + 119 0070 01D9 bls .L5 + 248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_TIMEOUT; + 120 .loc 1 249 14 + 121 0072 0323 movs r3, #3 + 122 0074 58E0 b .L3 + 123 .L5: + 245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 124 .loc 1 245 9 + 125 0076 2E4B ldr r3, .L11 + 126 0078 5B68 ldr r3, [r3, #4] + 127 007a 03F00C03 and r3, r3, #12 + 245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 128 .loc 1 245 43 + 129 007e 002B cmp r3, #0 + 130 0080 EED1 bne .L6 + 250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Update the SystemCoreClock global variable for HSI as system clock source */ + 254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** SystemCoreClock = HSI_VALUE; + 131 .loc 1 254 19 + 132 0082 2D4B ldr r3, .L11+8 + 133 0084 2D4A ldr r2, .L11+12 + 134 0086 1A60 str r2, [r3] + 255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Configure the source of time base considering new system clock settings */ + 257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(HAL_InitTick(uwTickPrio) != HAL_OK) + 135 .loc 1 257 6 + 136 0088 2D4B ldr r3, .L11+16 + 137 008a 1B68 ldr r3, [r3] + ARM GAS /tmp/ccSuWkwR.s page 8 + + + 138 008c 1846 mov r0, r3 + 139 008e FFF7FEFF bl HAL_InitTick + 140 0092 0346 mov r3, r0 + 141 .loc 1 257 5 discriminator 1 + 142 0094 002B cmp r3, #0 + 143 0096 01D0 beq .L7 + 258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_ERROR; + 144 .loc 1 259 12 + 145 0098 0123 movs r3, #1 + 146 009a 45E0 b .L3 + 147 .L7: + 260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Reset HSEON, CSSON, PLLON bits */ + 263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** CLEAR_BIT(RCC->CR, RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON); + 148 .loc 1 263 3 + 149 009c 244B ldr r3, .L11 + 150 009e 1B68 ldr r3, [r3] + 151 00a0 234A ldr r2, .L11 + 152 00a2 23F08473 bic r3, r3, #17301504 + 153 00a6 23F48033 bic r3, r3, #65536 + 154 00aa 1360 str r3, [r2] + 264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Reset HSEBYP bit */ + 266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); + 155 .loc 1 266 3 + 156 00ac 204B ldr r3, .L11 + 157 00ae 1B68 ldr r3, [r3] + 158 00b0 1F4A ldr r2, .L11 + 159 00b2 23F48023 bic r3, r3, #262144 + 160 00b6 1360 str r3, [r2] + 267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Insure PLLRDY is reset */ + 269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get start tick */ + 270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 161 .loc 1 270 15 + 162 00b8 FFF7FEFF bl HAL_GetTick + 163 00bc F860 str r0, [r7, #12] + 271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) + 164 .loc 1 271 8 + 165 00be 08E0 b .L8 + 166 .L9: + 272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 167 .loc 1 273 9 + 168 00c0 FFF7FEFF bl HAL_GetTick + 169 00c4 0246 mov r2, r0 + 170 .loc 1 273 23 discriminator 1 + 171 00c6 FB68 ldr r3, [r7, #12] + 172 00c8 D31A subs r3, r2, r3 + 173 .loc 1 273 7 discriminator 1 + 174 00ca 022B cmp r3, #2 + 175 00cc 01D9 bls .L8 + 274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_TIMEOUT; + 176 .loc 1 275 14 + ARM GAS /tmp/ccSuWkwR.s page 9 + + + 177 00ce 0323 movs r3, #3 + 178 00d0 2AE0 b .L3 + 179 .L8: + 271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 180 .loc 1 271 9 + 181 00d2 174B ldr r3, .L11 + 182 00d4 1B68 ldr r3, [r3] + 183 00d6 03F00073 and r3, r3, #33554432 + 271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 184 .loc 1 271 42 + 185 00da 002B cmp r3, #0 + 186 00dc F0D1 bne .L9 + 276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Reset CFGR register */ + 280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** CLEAR_REG(RCC->CFGR); + 187 .loc 1 280 3 + 188 00de 144B ldr r3, .L11 + 189 00e0 0022 movs r2, #0 + 190 00e2 5A60 str r2, [r3, #4] + 281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Reset CFGR2 register */ + 283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** CLEAR_REG(RCC->CFGR2); + 191 .loc 1 283 3 + 192 00e4 124B ldr r3, .L11 + 193 00e6 0022 movs r2, #0 + 194 00e8 DA62 str r2, [r3, #44] + 284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Reset CFGR3 register */ + 286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** CLEAR_REG(RCC->CFGR3); + 195 .loc 1 286 3 + 196 00ea 114B ldr r3, .L11 + 197 00ec 0022 movs r2, #0 + 198 00ee 1A63 str r2, [r3, #48] + 287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Clear all interrupt flags */ + 289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR + 199 .loc 1 289 3 + 200 00f0 0F4B ldr r3, .L11 + 201 00f2 9B68 ldr r3, [r3, #8] + 202 00f4 0E4A ldr r2, .L11 + 203 00f6 43F41F03 orr r3, r3, #10420224 + 204 00fa 9360 str r3, [r2, #8] + 290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Disable all interrupts */ + 292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** CLEAR_REG(RCC->CIR); + 205 .loc 1 292 3 + 206 00fc 0C4B ldr r3, .L11 + 207 00fe 0022 movs r2, #0 + 208 0100 9A60 str r2, [r3, #8] + 209 0102 4FF08073 mov r3, #16777216 + 210 0106 BB60 str r3, [r7, #8] + 211 .LBB168: + 212 .LBB169: + 213 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h" + 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** + ARM GAS /tmp/ccSuWkwR.s page 10 + + + 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h + 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file + 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.0.4 + 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 09. April 2018 + 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ + 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* + 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 + 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may + 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. + 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at + 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 + 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software + 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT + 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and + 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. + 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 24:Drivers/CMSIS/Include/cmsis_gcc.h **** + 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H + 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H + 27:Drivers/CMSIS/Include/cmsis_gcc.h **** + 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ + 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" + 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" + 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" + 33:Drivers/CMSIS/Include/cmsis_gcc.h **** + 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ + 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin + 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) + 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 38:Drivers/CMSIS/Include/cmsis_gcc.h **** + 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ + 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM + 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm + 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE + 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline + 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE + 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline + 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE + 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline + 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN + 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) + 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED + 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) + 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK + ARM GAS /tmp/ccSuWkwR.s page 11 + + + 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) + 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED + 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) + 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT + 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION + 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) + 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ + 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE + 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- + 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ + 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add + 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE + 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- + 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ + 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add + 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED + 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) + 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT + 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict + 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + ARM GAS /tmp/ccSuWkwR.s page 12 + + + 116:Drivers/CMSIS/Include/cmsis_gcc.h **** + 117:Drivers/CMSIS/Include/cmsis_gcc.h **** + 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ + 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface + 120:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + 121:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 122:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 123:Drivers/CMSIS/Include/cmsis_gcc.h **** + 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts + 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + 127:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 128:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) + 130:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); + 132:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 133:Drivers/CMSIS/Include/cmsis_gcc.h **** + 134:Drivers/CMSIS/Include/cmsis_gcc.h **** + 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 136:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts + 137:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. + 138:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 139:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) + 141:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 142:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); + 143:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 144:Drivers/CMSIS/Include/cmsis_gcc.h **** + 145:Drivers/CMSIS/Include/cmsis_gcc.h **** + 146:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 147:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register + 148:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register. + 149:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value + 150:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) + 152:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 153:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 154:Drivers/CMSIS/Include/cmsis_gcc.h **** + 155:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) ); + 156:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 157:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 158:Drivers/CMSIS/Include/cmsis_gcc.h **** + 159:Drivers/CMSIS/Include/cmsis_gcc.h **** + 160:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 161:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 162:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register (non-secure) + 163:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the non-secure Control Register when in secure mode. + 164:Drivers/CMSIS/Include/cmsis_gcc.h **** \return non-secure Control Register value + 165:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 166:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) + 167:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 168:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 169:Drivers/CMSIS/Include/cmsis_gcc.h **** + 170:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + 171:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 172:Drivers/CMSIS/Include/cmsis_gcc.h **** } + ARM GAS /tmp/ccSuWkwR.s page 13 + + + 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 174:Drivers/CMSIS/Include/cmsis_gcc.h **** + 175:Drivers/CMSIS/Include/cmsis_gcc.h **** + 176:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 177:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register + 178:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register. + 179:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 180:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 181:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) + 182:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 183:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + 184:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 185:Drivers/CMSIS/Include/cmsis_gcc.h **** + 186:Drivers/CMSIS/Include/cmsis_gcc.h **** + 187:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 188:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 189:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register (non-secure) + 190:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the non-secure Control Register when in secure state. + 191:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 192:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 193:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) + 194:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 195:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + 196:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 197:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 198:Drivers/CMSIS/Include/cmsis_gcc.h **** + 199:Drivers/CMSIS/Include/cmsis_gcc.h **** + 200:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 201:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register + 202:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register. + 203:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value + 204:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void) + 206:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 207:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 208:Drivers/CMSIS/Include/cmsis_gcc.h **** + 209:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 210:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 211:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 212:Drivers/CMSIS/Include/cmsis_gcc.h **** + 213:Drivers/CMSIS/Include/cmsis_gcc.h **** + 214:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 215:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register + 216:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register. + 217:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value + 218:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 219:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void) + 220:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 221:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 222:Drivers/CMSIS/Include/cmsis_gcc.h **** + 223:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + 224:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 225:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 226:Drivers/CMSIS/Include/cmsis_gcc.h **** + 227:Drivers/CMSIS/Include/cmsis_gcc.h **** + 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 229:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register + ARM GAS /tmp/ccSuWkwR.s page 14 + + + 230:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register. + 231:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value + 232:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void) + 234:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 235:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 236:Drivers/CMSIS/Include/cmsis_gcc.h **** + 237:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + 238:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 239:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 240:Drivers/CMSIS/Include/cmsis_gcc.h **** + 241:Drivers/CMSIS/Include/cmsis_gcc.h **** + 242:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 243:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer + 244:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP). + 245:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 246:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 247:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void) + 248:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 249:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 250:Drivers/CMSIS/Include/cmsis_gcc.h **** + 251:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp" : "=r" (result) ); + 252:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 253:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 254:Drivers/CMSIS/Include/cmsis_gcc.h **** + 255:Drivers/CMSIS/Include/cmsis_gcc.h **** + 256:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 257:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 258:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer (non-secure) + 259:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s + 260:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 261:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) + 263:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 264:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 265:Drivers/CMSIS/Include/cmsis_gcc.h **** + 266:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + 267:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 268:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 269:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 270:Drivers/CMSIS/Include/cmsis_gcc.h **** + 271:Drivers/CMSIS/Include/cmsis_gcc.h **** + 272:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 273:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer + 274:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP). + 275:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 276:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 277:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) + 278:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 279:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); + 280:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 281:Drivers/CMSIS/Include/cmsis_gcc.h **** + 282:Drivers/CMSIS/Include/cmsis_gcc.h **** + 283:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 284:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 285:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + 286:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta + ARM GAS /tmp/ccSuWkwR.s page 15 + + + 287:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 288:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 289:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) + 290:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 291:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); + 292:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 293:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 294:Drivers/CMSIS/Include/cmsis_gcc.h **** + 295:Drivers/CMSIS/Include/cmsis_gcc.h **** + 296:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 297:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer + 298:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP). + 299:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 300:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 301:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void) + 302:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 303:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 304:Drivers/CMSIS/Include/cmsis_gcc.h **** + 305:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp" : "=r" (result) ); + 306:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 307:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 308:Drivers/CMSIS/Include/cmsis_gcc.h **** + 309:Drivers/CMSIS/Include/cmsis_gcc.h **** + 310:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 311:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 312:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer (non-secure) + 313:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat + 314:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 315:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 316:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) + 317:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 318:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 319:Drivers/CMSIS/Include/cmsis_gcc.h **** + 320:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + 321:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 322:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 324:Drivers/CMSIS/Include/cmsis_gcc.h **** + 325:Drivers/CMSIS/Include/cmsis_gcc.h **** + 326:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 327:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer + 328:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP). + 329:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 330:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 331:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) + 332:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 333:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); + 334:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 335:Drivers/CMSIS/Include/cmsis_gcc.h **** + 336:Drivers/CMSIS/Include/cmsis_gcc.h **** + 337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 338:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 339:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer (non-secure) + 340:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + 341:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 342:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 343:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) + ARM GAS /tmp/ccSuWkwR.s page 16 + + + 344:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 345:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); + 346:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 347:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 348:Drivers/CMSIS/Include/cmsis_gcc.h **** + 349:Drivers/CMSIS/Include/cmsis_gcc.h **** + 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 352:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Stack Pointer (non-secure) + 353:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + 354:Drivers/CMSIS/Include/cmsis_gcc.h **** \return SP Register value + 355:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) + 357:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 358:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 359:Drivers/CMSIS/Include/cmsis_gcc.h **** + 360:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + 361:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 362:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 363:Drivers/CMSIS/Include/cmsis_gcc.h **** + 364:Drivers/CMSIS/Include/cmsis_gcc.h **** + 365:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 366:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Stack Pointer (non-secure) + 367:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + 368:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfStack Stack Pointer value to set + 369:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 370:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) + 371:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 372:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); + 373:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 374:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 375:Drivers/CMSIS/Include/cmsis_gcc.h **** + 376:Drivers/CMSIS/Include/cmsis_gcc.h **** + 377:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 378:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask + 379:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register. + 380:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 381:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 382:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) + 383:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 384:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 385:Drivers/CMSIS/Include/cmsis_gcc.h **** + 386:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 387:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 388:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 389:Drivers/CMSIS/Include/cmsis_gcc.h **** + 390:Drivers/CMSIS/Include/cmsis_gcc.h **** + 391:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 392:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 393:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask (non-secure) + 394:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg + 395:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 396:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 397:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) + 398:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 399:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 400:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccSuWkwR.s page 17 + + + 401:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + 402:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 403:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 405:Drivers/CMSIS/Include/cmsis_gcc.h **** + 406:Drivers/CMSIS/Include/cmsis_gcc.h **** + 407:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 408:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask + 409:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register. + 410:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 411:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 412:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) + 413:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 414:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 415:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 416:Drivers/CMSIS/Include/cmsis_gcc.h **** + 417:Drivers/CMSIS/Include/cmsis_gcc.h **** + 418:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 419:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 420:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask (non-secure) + 421:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + 422:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 423:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 424:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) + 425:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 426:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); + 427:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 428:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 429:Drivers/CMSIS/Include/cmsis_gcc.h **** + 430:Drivers/CMSIS/Include/cmsis_gcc.h **** + 431:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 432:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 433:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + 434:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 435:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ + 436:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + 437:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 438:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 439:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void) + 440:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 441:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory"); + 442:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 443:Drivers/CMSIS/Include/cmsis_gcc.h **** + 444:Drivers/CMSIS/Include/cmsis_gcc.h **** + 445:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 446:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ + 447:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR. + 448:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 449:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 450:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void) + 451:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 452:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory"); + 453:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 454:Drivers/CMSIS/Include/cmsis_gcc.h **** + 455:Drivers/CMSIS/Include/cmsis_gcc.h **** + 456:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 457:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority + ARM GAS /tmp/ccSuWkwR.s page 18 + + + 458:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register. + 459:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 460:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 461:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) + 462:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 463:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 464:Drivers/CMSIS/Include/cmsis_gcc.h **** + 465:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + 466:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 467:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 468:Drivers/CMSIS/Include/cmsis_gcc.h **** + 469:Drivers/CMSIS/Include/cmsis_gcc.h **** + 470:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 471:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 472:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority (non-secure) + 473:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Base Priority register when in secure state. + 474:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 475:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) + 477:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 478:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 479:Drivers/CMSIS/Include/cmsis_gcc.h **** + 480:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + 481:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 482:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 483:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 484:Drivers/CMSIS/Include/cmsis_gcc.h **** + 485:Drivers/CMSIS/Include/cmsis_gcc.h **** + 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 487:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority + 488:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register. + 489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 490:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) + 492:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 493:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); + 494:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 495:Drivers/CMSIS/Include/cmsis_gcc.h **** + 496:Drivers/CMSIS/Include/cmsis_gcc.h **** + 497:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 498:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 499:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority (non-secure) + 500:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Base Priority register when in secure state. + 501:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 502:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 503:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) + 504:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 505:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); + 506:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 507:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 508:Drivers/CMSIS/Include/cmsis_gcc.h **** + 509:Drivers/CMSIS/Include/cmsis_gcc.h **** + 510:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 511:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition + 512:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable + 513:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level. + 514:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + ARM GAS /tmp/ccSuWkwR.s page 19 + + + 515:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 516:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) + 517:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 518:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); + 519:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 520:Drivers/CMSIS/Include/cmsis_gcc.h **** + 521:Drivers/CMSIS/Include/cmsis_gcc.h **** + 522:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 523:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask + 524:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register. + 525:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 526:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) + 528:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 529:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 530:Drivers/CMSIS/Include/cmsis_gcc.h **** + 531:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + 532:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 533:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 534:Drivers/CMSIS/Include/cmsis_gcc.h **** + 535:Drivers/CMSIS/Include/cmsis_gcc.h **** + 536:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 537:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 538:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask (non-secure) + 539:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Fault Mask register when in secure state. + 540:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 541:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 542:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) + 543:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 544:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 545:Drivers/CMSIS/Include/cmsis_gcc.h **** + 546:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + 547:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 548:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 549:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 550:Drivers/CMSIS/Include/cmsis_gcc.h **** + 551:Drivers/CMSIS/Include/cmsis_gcc.h **** + 552:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 553:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask + 554:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register. + 555:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 556:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 557:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) + 558:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 559:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); + 560:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 561:Drivers/CMSIS/Include/cmsis_gcc.h **** + 562:Drivers/CMSIS/Include/cmsis_gcc.h **** + 563:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 564:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 565:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask (non-secure) + 566:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Fault Mask register when in secure state. + 567:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 568:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 569:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) + 570:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 571:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); + ARM GAS /tmp/ccSuWkwR.s page 20 + + + 572:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 573:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 574:Drivers/CMSIS/Include/cmsis_gcc.h **** + 575:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 576:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 577:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + 578:Drivers/CMSIS/Include/cmsis_gcc.h **** + 579:Drivers/CMSIS/Include/cmsis_gcc.h **** + 580:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 581:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + 582:Drivers/CMSIS/Include/cmsis_gcc.h **** + 583:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 584:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit + 585:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 586:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 587:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 588:Drivers/CMSIS/Include/cmsis_gcc.h **** + 589:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + 590:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 591:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 592:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) + 593:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 594:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 595:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 596:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 597:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 598:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 599:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 600:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + 601:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 602:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 603:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 604:Drivers/CMSIS/Include/cmsis_gcc.h **** + 605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) + 606:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 607:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit (non-secure) + 608:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 609:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + 610:Drivers/CMSIS/Include/cmsis_gcc.h **** + 611:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in + 612:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 613:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 614:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) + 615:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 617:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 618:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 619:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 620:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 621:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + 622:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 623:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 624:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 625:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 626:Drivers/CMSIS/Include/cmsis_gcc.h **** + 627:Drivers/CMSIS/Include/cmsis_gcc.h **** + 628:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + ARM GAS /tmp/ccSuWkwR.s page 21 + + + 629:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer Limit + 630:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 631:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 632:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 633:Drivers/CMSIS/Include/cmsis_gcc.h **** + 634:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + 635:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 636:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 637:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) + 638:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 639:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 640:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 641:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 642:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 643:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 644:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); + 645:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 646:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 647:Drivers/CMSIS/Include/cmsis_gcc.h **** + 648:Drivers/CMSIS/Include/cmsis_gcc.h **** + 649:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 651:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + 652:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 653:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 654:Drivers/CMSIS/Include/cmsis_gcc.h **** + 655:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s + 656:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 657:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 658:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) + 659:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 661:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 662:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 663:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 664:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); + 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 666:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 667:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 668:Drivers/CMSIS/Include/cmsis_gcc.h **** + 669:Drivers/CMSIS/Include/cmsis_gcc.h **** + 670:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 671:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit + 672:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 673:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 674:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 675:Drivers/CMSIS/Include/cmsis_gcc.h **** + 676:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + 677:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 678:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) + 680:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 681:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 682:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 683:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 684:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 685:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + ARM GAS /tmp/ccSuWkwR.s page 22 + + + 686:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 687:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + 688:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 689:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 690:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 691:Drivers/CMSIS/Include/cmsis_gcc.h **** + 692:Drivers/CMSIS/Include/cmsis_gcc.h **** + 693:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 694:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 695:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit (non-secure) + 696:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 697:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + 698:Drivers/CMSIS/Include/cmsis_gcc.h **** + 699:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec + 700:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 701:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 702:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) + 703:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 704:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 705:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 706:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 707:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 708:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 709:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + 710:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 711:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 712:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 713:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 714:Drivers/CMSIS/Include/cmsis_gcc.h **** + 715:Drivers/CMSIS/Include/cmsis_gcc.h **** + 716:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 717:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit + 718:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 719:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 720:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 721:Drivers/CMSIS/Include/cmsis_gcc.h **** + 722:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + 723:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + 724:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) + 726:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 728:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 729:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 730:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 731:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 732:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); + 733:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 734:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 735:Drivers/CMSIS/Include/cmsis_gcc.h **** + 736:Drivers/CMSIS/Include/cmsis_gcc.h **** + 737:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 738:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 739:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit (non-secure) + 740:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 741:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 742:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccSuWkwR.s page 23 + + + 743:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu + 744:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer value to set + 745:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) + 747:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 749:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 750:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 751:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 752:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); + 753:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 754:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 755:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 756:Drivers/CMSIS/Include/cmsis_gcc.h **** + 757:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 758:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + 759:Drivers/CMSIS/Include/cmsis_gcc.h **** + 760:Drivers/CMSIS/Include/cmsis_gcc.h **** + 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 762:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR + 763:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register. + 764:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value + 765:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 766:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) + 767:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 768:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 769:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 770:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) + 771:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + 772:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 773:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 774:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_arm_get_fpscr(); + 775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 776:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 777:Drivers/CMSIS/Include/cmsis_gcc.h **** + 778:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + 779:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 781:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 782:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0U); + 783:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 784:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 785:Drivers/CMSIS/Include/cmsis_gcc.h **** + 786:Drivers/CMSIS/Include/cmsis_gcc.h **** + 787:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 788:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR + 789:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register. + 790:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set + 791:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) + 793:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 795:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 796:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr) + 797:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + 798:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 799:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + ARM GAS /tmp/ccSuWkwR.s page 24 + + + 800:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_arm_set_fpscr(fpscr); + 801:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 802:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); + 803:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 805:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)fpscr; + 806:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 807:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 808:Drivers/CMSIS/Include/cmsis_gcc.h **** + 809:Drivers/CMSIS/Include/cmsis_gcc.h **** + 810:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */ + 811:Drivers/CMSIS/Include/cmsis_gcc.h **** + 812:Drivers/CMSIS/Include/cmsis_gcc.h **** + 813:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */ + 814:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + 815:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions + 816:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 817:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 818:Drivers/CMSIS/Include/cmsis_gcc.h **** + 819:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2. + 820:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l" + 821:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */ + 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__) + 823:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r) + 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r) + 825:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r) + 826:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 827:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r) + 828:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r) + 829:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r) + 830:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 831:Drivers/CMSIS/Include/cmsis_gcc.h **** + 832:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 833:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation + 834:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes. + 835:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 836:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP() __ASM volatile ("nop") + 837:Drivers/CMSIS/Include/cmsis_gcc.h **** + 838:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 839:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt + 840:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o + 841:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI() __ASM volatile ("wfi") + 843:Drivers/CMSIS/Include/cmsis_gcc.h **** + 844:Drivers/CMSIS/Include/cmsis_gcc.h **** + 845:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 846:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event + 847:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter + 848:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs. + 849:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE() __ASM volatile ("wfe") + 851:Drivers/CMSIS/Include/cmsis_gcc.h **** + 852:Drivers/CMSIS/Include/cmsis_gcc.h **** + 853:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 854:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event + 855:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + 856:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + ARM GAS /tmp/ccSuWkwR.s page 25 + + + 857:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev") + 858:Drivers/CMSIS/Include/cmsis_gcc.h **** + 859:Drivers/CMSIS/Include/cmsis_gcc.h **** + 860:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 861:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier + 862:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor, + 863:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory, + 864:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed. + 865:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 866:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void) + 867:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 868:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory"); + 869:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 870:Drivers/CMSIS/Include/cmsis_gcc.h **** + 871:Drivers/CMSIS/Include/cmsis_gcc.h **** + 872:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 873:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier + 874:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier. + 875:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete. + 876:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 877:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void) + 878:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 879:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory"); + 880:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 881:Drivers/CMSIS/Include/cmsis_gcc.h **** + 882:Drivers/CMSIS/Include/cmsis_gcc.h **** + 883:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 884:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Memory Barrier + 885:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Ensures the apparent order of the explicit memory operations before + 886:Drivers/CMSIS/Include/cmsis_gcc.h **** and after the instruction, without ensuring their completion. + 887:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 888:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void) + 889:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 890:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dmb 0xF":::"memory"); + 891:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 892:Drivers/CMSIS/Include/cmsis_gcc.h **** + 893:Drivers/CMSIS/Include/cmsis_gcc.h **** + 894:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 895:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (32 bit) + 896:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x785 + 897:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 898:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 899:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 900:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV(uint32_t value) + 901:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 902:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + 903:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_bswap32(value); + 904:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 905:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 906:Drivers/CMSIS/Include/cmsis_gcc.h **** + 907:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + 908:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 909:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 910:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 911:Drivers/CMSIS/Include/cmsis_gcc.h **** + 912:Drivers/CMSIS/Include/cmsis_gcc.h **** + 913:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + ARM GAS /tmp/ccSuWkwR.s page 26 + + + 914:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) + 915:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes + 916:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 917:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 918:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 919:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) + 920:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 921:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 922:Drivers/CMSIS/Include/cmsis_gcc.h **** + 923:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + 924:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 925:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 926:Drivers/CMSIS/Include/cmsis_gcc.h **** + 927:Drivers/CMSIS/Include/cmsis_gcc.h **** + 928:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 929:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) + 930:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For exam + 931:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 932:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 933:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 934:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE int16_t __REVSH(int16_t value) + 935:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 936:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + 937:Drivers/CMSIS/Include/cmsis_gcc.h **** return (int16_t)__builtin_bswap16(value); + 938:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 939:Drivers/CMSIS/Include/cmsis_gcc.h **** int16_t result; + 940:Drivers/CMSIS/Include/cmsis_gcc.h **** + 941:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + 942:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 943:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 944:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 945:Drivers/CMSIS/Include/cmsis_gcc.h **** + 946:Drivers/CMSIS/Include/cmsis_gcc.h **** + 947:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 948:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Rotate Right in unsigned value (32 bit) + 949:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v + 950:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op1 Value to rotate + 951:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op2 Number of Bits to rotate + 952:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Rotated value + 953:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 954:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) + 955:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 956:Drivers/CMSIS/Include/cmsis_gcc.h **** op2 %= 32U; + 957:Drivers/CMSIS/Include/cmsis_gcc.h **** if (op2 == 0U) + 958:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 959:Drivers/CMSIS/Include/cmsis_gcc.h **** return op1; + 960:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 961:Drivers/CMSIS/Include/cmsis_gcc.h **** return (op1 >> op2) | (op1 << (32U - op2)); + 962:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 963:Drivers/CMSIS/Include/cmsis_gcc.h **** + 964:Drivers/CMSIS/Include/cmsis_gcc.h **** + 965:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 966:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Breakpoint + 967:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Causes the processor to enter Debug state. + 968:Drivers/CMSIS/Include/cmsis_gcc.h **** Debug tools can use this to investigate system state when the instruction at a particula + 969:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value is ignored by the processor. + 970:Drivers/CMSIS/Include/cmsis_gcc.h **** If required, a debugger can use it to store additional information about the break + ARM GAS /tmp/ccSuWkwR.s page 27 + + + 971:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 972:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __BKPT(value) __ASM volatile ("bkpt "#value) + 973:Drivers/CMSIS/Include/cmsis_gcc.h **** + 974:Drivers/CMSIS/Include/cmsis_gcc.h **** + 975:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 976:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse bit order of value + 977:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the bit order of the given value. + 978:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 979:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 980:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) + 982:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 984:Drivers/CMSIS/Include/cmsis_gcc.h **** + 985:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 986:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 987:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 214 .loc 2 988 4 + 215 0108 BB68 ldr r3, [r7, #8] + 216 .syntax unified + 217 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 218 010a 93FAA3F3 rbit r3, r3 + 219 @ 0 "" 2 + 220 .thumb + 221 .syntax unified + 222 010e 7B60 str r3, [r7, #4] + 989:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 990:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + 991:Drivers/CMSIS/Include/cmsis_gcc.h **** + 992:Drivers/CMSIS/Include/cmsis_gcc.h **** result = value; /* r will be reversed bits of v; first get LSB of v */ + 993:Drivers/CMSIS/Include/cmsis_gcc.h **** for (value >>= 1U; value != 0U; value >>= 1U) + 994:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 995:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= 1U; + 996:Drivers/CMSIS/Include/cmsis_gcc.h **** result |= value & 1U; + 997:Drivers/CMSIS/Include/cmsis_gcc.h **** s--; + 998:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 999:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= s; /* shift when v's highest bits are zero */ +1000:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif +1001:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 223 .loc 2 1001 10 + 224 0110 7B68 ldr r3, [r7, #4] + 225 .LBE169: + 226 .LBE168: + 293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Reset all CSR flags */ + 295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_CLEAR_RESET_FLAGS(); + 227 .loc 1 295 3 discriminator 1 + 228 0112 B3FA83F3 clz r3, r3 + 229 .loc 1 295 3 is_stmt 0 discriminator 2 + 230 0116 DBB2 uxtb r3, r3 + 231 0118 1A46 mov r2, r3 + 232 011a 0A4B ldr r3, .L11+20 + 233 011c 1344 add r3, r3, r2 + 234 011e 9B00 lsls r3, r3, #2 + 235 0120 1A46 mov r2, r3 + 236 0122 0123 movs r3, #1 + ARM GAS /tmp/ccSuWkwR.s page 28 + + + 237 0124 1360 str r3, [r2] + 296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_OK; + 238 .loc 1 297 10 is_stmt 1 + 239 0126 0023 movs r3, #0 + 240 .L3: + 298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 241 .loc 1 298 1 + 242 0128 1846 mov r0, r3 + 243 012a 1037 adds r7, r7, #16 + 244 .cfi_def_cfa_offset 8 + 245 012c BD46 mov sp, r7 + 246 .cfi_def_cfa_register 13 + 247 @ sp needed + 248 012e 80BD pop {r7, pc} + 249 .L12: + 250 .align 2 + 251 .L11: + 252 0130 00100240 .word 1073876992 + 253 0134 0CC0FFF8 .word -117456884 + 254 0138 00000000 .word SystemCoreClock + 255 013c 00127A00 .word 8000000 + 256 0140 00000000 .word uwTickPrio + 257 0144 20819010 .word 277905696 + 258 .cfi_endproc + 259 .LFE130: + 261 .section .text.HAL_RCC_OscConfig,"ax",%progbits + 262 .align 1 + 263 .global HAL_RCC_OscConfig + 264 .syntax unified + 265 .thumb + 266 .thumb_func + 268 HAL_RCC_OscConfig: + 269 .LFB131: + 299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** + 301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief Initializes the RCC Oscillators according to the specified parameters in the + 302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * RCC_OscInitTypeDef. + 303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that + 304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * contains the configuration information for the RCC Oscillators. + 305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note The PLL is not disabled when used as system clock. + 306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not + 307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * supported by this macro. User should request a transition to LSE Off + 308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * first and then LSE On or LSE Bypass. + 309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + 310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * supported by this macro. User should request a transition to HSE Off + 311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * first and then HSE On or HSE Bypass. + 312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @retval HAL status + 313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ + 314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) + 315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 270 .loc 1 315 1 + 271 .cfi_startproc + 272 @ args = 0, pretend = 0, frame = 512 + 273 @ frame_needed = 1, uses_anonymous_args = 0 + 274 0000 80B5 push {r7, lr} + 275 .cfi_def_cfa_offset 8 + ARM GAS /tmp/ccSuWkwR.s page 29 + + + 276 .cfi_offset 7, -8 + 277 .cfi_offset 14, -4 + 278 0002 ADF5007D sub sp, sp, #512 + 279 .cfi_def_cfa_offset 520 + 280 0006 00AF add r7, sp, #0 + 281 .cfi_def_cfa_register 7 + 282 0008 07F50073 add r3, r7, #512 + 283 000c A3F5FE73 sub r3, r3, #508 + 284 0010 1860 str r0, [r3] + 316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** uint32_t tickstart; + 317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** uint32_t pll_config; + 318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) + 319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** uint32_t pll_config2; + 320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */ + 321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check Null pointer */ + 323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(RCC_OscInitStruct == NULL) + 285 .loc 1 323 5 + 286 0012 07F50073 add r3, r7, #512 + 287 0016 A3F5FE73 sub r3, r3, #508 + 288 001a 1B68 ldr r3, [r3] + 289 001c 002B cmp r3, #0 + 290 001e 02D1 bne .L14 + 324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_ERROR; + 291 .loc 1 325 12 + 292 0020 0123 movs r3, #1 + 293 0022 00F0F4BF b .L15 + 294 .L14: + 326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the parameters */ + 329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + 330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /*------------------------------- HSE Configuration ------------------------*/ + 332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + 295 .loc 1 332 25 + 296 0026 07F50073 add r3, r7, #512 + 297 002a A3F5FE73 sub r3, r3, #508 + 298 002e 1B68 ldr r3, [r3] + 299 0030 1B68 ldr r3, [r3] + 300 .loc 1 332 43 + 301 0032 03F00103 and r3, r3, #1 + 302 .loc 1 332 5 + 303 0036 002B cmp r3, #0 + 304 0038 00F06D81 beq .L16 + 333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the parameters */ + 335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + 336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowe + 338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) + 305 .loc 1 338 9 + 306 003c B44B ldr r3, .L154 + 307 003e 5B68 ldr r3, [r3, #4] + 308 0040 03F00C03 and r3, r3, #12 + 309 .loc 1 338 7 + ARM GAS /tmp/ccSuWkwR.s page 30 + + + 310 0044 042B cmp r3, #4 + 311 0046 0CD0 beq .L17 + 339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_ + 312 .loc 1 339 13 + 313 0048 B14B ldr r3, .L154 + 314 004a 5B68 ldr r3, [r3, #4] + 315 004c 03F00C03 and r3, r3, #12 + 316 .loc 1 339 8 + 317 0050 082B cmp r3, #8 + 318 0052 57D1 bne .L18 + 319 .loc 1 339 82 discriminator 1 + 320 0054 AE4B ldr r3, .L154 + 321 0056 5B68 ldr r3, [r3, #4] + 322 0058 03F48033 and r3, r3, #65536 + 323 .loc 1 339 78 discriminator 1 + 324 005c B3F5803F cmp r3, #65536 + 325 0060 50D1 bne .L18 + 326 .L17: + 327 0062 4FF40033 mov r3, #131072 + 328 0066 C7F8F031 str r3, [r7, #496] + 329 .LBB170: + 330 .LBB171: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 331 .loc 2 988 4 + 332 006a D7F8F031 ldr r3, [r7, #496] + 333 .syntax unified + 334 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 335 006e 93FAA3F3 rbit r3, r3 + 336 @ 0 "" 2 + 337 .thumb + 338 .syntax unified + 339 0072 C7F8EC31 str r3, [r7, #492] + 340 .loc 2 1001 10 + 341 0076 D7F8EC31 ldr r3, [r7, #492] + 342 .LBE171: + 343 .LBE170: + 340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_ + 344 .loc 1 341 11 discriminator 1 + 345 007a B3FA83F3 clz r3, r3 + 346 .loc 1 341 11 is_stmt 0 discriminator 2 + 347 007e DBB2 uxtb r3, r3 + 348 0080 3F2B cmp r3, #63 + 349 0082 02D8 bhi .L20 + 350 .loc 1 341 11 discriminator 1 + 351 0084 A24B ldr r3, .L154 + 352 0086 1B68 ldr r3, [r3] + 353 0088 15E0 b .L21 + 354 .L20: + 355 008a 4FF40033 mov r3, #131072 + 356 008e C7F8E831 str r3, [r7, #488] + 357 .LBB172: + 358 .LBB173: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 359 .loc 2 988 4 is_stmt 1 + 360 0092 D7F8E831 ldr r3, [r7, #488] + 361 .syntax unified + ARM GAS /tmp/ccSuWkwR.s page 31 + + + 362 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 363 0096 93FAA3F3 rbit r3, r3 + 364 @ 0 "" 2 + 365 .thumb + 366 .syntax unified + 367 009a C7F8E431 str r3, [r7, #484] + 368 009e 4FF40033 mov r3, #131072 + 369 00a2 C7F8E031 str r3, [r7, #480] + 370 .LBE173: + 371 .LBE172: + 372 .LBB174: + 373 .LBB175: + 374 00a6 D7F8E031 ldr r3, [r7, #480] + 375 .syntax unified + 376 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 377 00aa 93FAA3F3 rbit r3, r3 + 378 @ 0 "" 2 + 379 .thumb + 380 .syntax unified + 381 00ae C7F8DC31 str r3, [r7, #476] + 382 .LBE175: + 383 .LBE174: + 384 .loc 1 341 11 discriminator 8 + 385 00b2 974B ldr r3, .L154 + 386 00b4 5B6A ldr r3, [r3, #36] + 387 .L21: + 388 00b6 4FF40032 mov r2, #131072 + 389 00ba C7F8D821 str r2, [r7, #472] + 390 .LBB176: + 391 .LBB177: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 392 .loc 2 988 4 + 393 00be D7F8D821 ldr r2, [r7, #472] + 394 .syntax unified + 395 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 396 00c2 92FAA2F2 rbit r2, r2 + 397 @ 0 "" 2 + 398 .thumb + 399 .syntax unified + 400 00c6 C7F8D421 str r2, [r7, #468] + 401 .loc 2 1001 10 + 402 00ca D7F8D421 ldr r2, [r7, #468] + 403 .LBE177: + 404 .LBE176: + 405 .loc 1 341 11 discriminator 1 + 406 00ce B2FA82F2 clz r2, r2 + 407 .loc 1 341 11 is_stmt 0 discriminator 2 + 408 00d2 D2B2 uxtb r2, r2 + 409 00d4 42F02002 orr r2, r2, #32 + 410 00d8 D2B2 uxtb r2, r2 + 411 00da 02F01F02 and r2, r2, #31 + 412 00de 0121 movs r1, #1 + 413 00e0 01FA02F2 lsl r2, r1, r2 + 414 00e4 1340 ands r3, r3, r2 + 415 .loc 1 341 9 is_stmt 1 discriminator 2 + 416 00e6 002B cmp r3, #0 + 417 00e8 00F01481 beq .L153 + ARM GAS /tmp/ccSuWkwR.s page 32 + + + 418 .loc 1 341 78 discriminator 13 + 419 00ec 07F50073 add r3, r7, #512 + 420 00f0 A3F5FE73 sub r3, r3, #508 + 421 00f4 1B68 ldr r3, [r3] + 422 00f6 5B68 ldr r3, [r3, #4] + 423 .loc 1 341 57 discriminator 13 + 424 00f8 002B cmp r3, #0 + 425 00fa 40F00B81 bne .L153 + 342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_ERROR; + 426 .loc 1 343 16 + 427 00fe 0123 movs r3, #1 + 428 0100 00F085BF b .L15 + 429 .L18: + 344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else + 347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Set the new HSE configuration ---------------------------------------*/ + 349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + 430 .loc 1 349 7 + 431 0104 07F50073 add r3, r7, #512 + 432 0108 A3F5FE73 sub r3, r3, #508 + 433 010c 1B68 ldr r3, [r3] + 434 010e 5B68 ldr r3, [r3, #4] + 435 0110 B3F5803F cmp r3, #65536 + 436 0114 06D1 bne .L26 + 437 .loc 1 349 7 is_stmt 0 discriminator 1 + 438 0116 7E4B ldr r3, .L154 + 439 0118 1B68 ldr r3, [r3] + 440 011a 7D4A ldr r2, .L154 + 441 011c 43F48033 orr r3, r3, #65536 + 442 0120 1360 str r3, [r2] + 443 0122 36E0 b .L27 + 444 .L26: + 445 .loc 1 349 7 discriminator 2 + 446 0124 07F50073 add r3, r7, #512 + 447 0128 A3F5FE73 sub r3, r3, #508 + 448 012c 1B68 ldr r3, [r3] + 449 012e 5B68 ldr r3, [r3, #4] + 450 0130 002B cmp r3, #0 + 451 0132 0CD1 bne .L28 + 452 .loc 1 349 7 discriminator 3 + 453 0134 764B ldr r3, .L154 + 454 0136 1B68 ldr r3, [r3] + 455 0138 754A ldr r2, .L154 + 456 013a 23F48033 bic r3, r3, #65536 + 457 013e 1360 str r3, [r2] + 458 0140 734B ldr r3, .L154 + 459 0142 1B68 ldr r3, [r3] + 460 0144 724A ldr r2, .L154 + 461 0146 23F48023 bic r3, r3, #262144 + 462 014a 1360 str r3, [r2] + 463 014c 21E0 b .L27 + 464 .L28: + 465 .loc 1 349 7 discriminator 4 + 466 014e 07F50073 add r3, r7, #512 + ARM GAS /tmp/ccSuWkwR.s page 33 + + + 467 0152 A3F5FE73 sub r3, r3, #508 + 468 0156 1B68 ldr r3, [r3] + 469 0158 5B68 ldr r3, [r3, #4] + 470 015a B3F5A02F cmp r3, #327680 + 471 015e 0CD1 bne .L29 + 472 .loc 1 349 7 discriminator 5 + 473 0160 6B4B ldr r3, .L154 + 474 0162 1B68 ldr r3, [r3] + 475 0164 6A4A ldr r2, .L154 + 476 0166 43F48023 orr r3, r3, #262144 + 477 016a 1360 str r3, [r2] + 478 016c 684B ldr r3, .L154 + 479 016e 1B68 ldr r3, [r3] + 480 0170 674A ldr r2, .L154 + 481 0172 43F48033 orr r3, r3, #65536 + 482 0176 1360 str r3, [r2] + 483 0178 0BE0 b .L27 + 484 .L29: + 485 .loc 1 349 7 discriminator 6 + 486 017a 654B ldr r3, .L154 + 487 017c 1B68 ldr r3, [r3] + 488 017e 644A ldr r2, .L154 + 489 0180 23F48033 bic r3, r3, #65536 + 490 0184 1360 str r3, [r2] + 491 0186 624B ldr r3, .L154 + 492 0188 1B68 ldr r3, [r3] + 493 018a 614A ldr r2, .L154 + 494 018c 23F48023 bic r3, r3, #262144 + 495 0190 1360 str r3, [r2] + 496 .L27: + 350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #if defined(RCC_CFGR_PLLSRC_HSI_DIV2) + 352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Configure the HSE predivision factor --------------------------------*/ + 353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue); + 497 .loc 1 353 7 is_stmt 1 + 498 0192 5F4B ldr r3, .L154 + 499 0194 DB6A ldr r3, [r3, #44] + 500 0196 23F00F02 bic r2, r3, #15 + 501 019a 07F50073 add r3, r7, #512 + 502 019e A3F5FE73 sub r3, r3, #508 + 503 01a2 1B68 ldr r3, [r3] + 504 01a4 9B68 ldr r3, [r3, #8] + 505 01a6 5A49 ldr r1, .L154 + 506 01a8 1343 orrs r3, r3, r2 + 507 01aa CB62 str r3, [r1, #44] + 354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */ + 355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the HSE State */ + 357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + 508 .loc 1 357 27 + 509 01ac 07F50073 add r3, r7, #512 + 510 01b0 A3F5FE73 sub r3, r3, #508 + 511 01b4 1B68 ldr r3, [r3] + 512 01b6 5B68 ldr r3, [r3, #4] + 513 .loc 1 357 9 + 514 01b8 002B cmp r3, #0 + 515 01ba 54D0 beq .L30 + ARM GAS /tmp/ccSuWkwR.s page 34 + + + 358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get Start Tick */ + 360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 516 .loc 1 360 21 + 517 01bc FFF7FEFF bl HAL_GetTick + 518 01c0 C7F8F801 str r0, [r7, #504] + 361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Wait till HSE is ready */ + 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + 519 .loc 1 363 14 + 520 01c4 0AE0 b .L31 + 521 .L38: + 364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + 522 .loc 1 365 15 + 523 01c6 FFF7FEFF bl HAL_GetTick + 524 01ca 0246 mov r2, r0 + 525 .loc 1 365 29 discriminator 1 + 526 01cc D7F8F831 ldr r3, [r7, #504] + 527 01d0 D31A subs r3, r2, r3 + 528 .loc 1 365 13 discriminator 1 + 529 01d2 642B cmp r3, #100 + 530 01d4 02D9 bls .L31 + 366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_TIMEOUT; + 531 .loc 1 367 20 + 532 01d6 0323 movs r3, #3 + 533 01d8 00F019BF b .L15 + 534 .L31: + 535 01dc 4FF40033 mov r3, #131072 + 536 01e0 C7F8D031 str r3, [r7, #464] + 537 .LBB178: + 538 .LBB179: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 539 .loc 2 988 4 + 540 01e4 D7F8D031 ldr r3, [r7, #464] + 541 .syntax unified + 542 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 543 01e8 93FAA3F3 rbit r3, r3 + 544 @ 0 "" 2 + 545 .thumb + 546 .syntax unified + 547 01ec C7F8CC31 str r3, [r7, #460] + 548 .loc 2 1001 10 + 549 01f0 D7F8CC31 ldr r3, [r7, #460] + 550 .LBE179: + 551 .LBE178: + 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 552 .loc 1 363 15 discriminator 1 + 553 01f4 B3FA83F3 clz r3, r3 + 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 554 .loc 1 363 15 is_stmt 0 discriminator 2 + 555 01f8 DBB2 uxtb r3, r3 + 556 01fa 3F2B cmp r3, #63 + 557 01fc 02D8 bhi .L33 + 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 558 .loc 1 363 15 discriminator 1 + ARM GAS /tmp/ccSuWkwR.s page 35 + + + 559 01fe 444B ldr r3, .L154 + 560 0200 1B68 ldr r3, [r3] + 561 0202 15E0 b .L34 + 562 .L33: + 563 0204 4FF40033 mov r3, #131072 + 564 0208 C7F8C831 str r3, [r7, #456] + 565 .LBB180: + 566 .LBB181: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 567 .loc 2 988 4 is_stmt 1 + 568 020c D7F8C831 ldr r3, [r7, #456] + 569 .syntax unified + 570 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 571 0210 93FAA3F3 rbit r3, r3 + 572 @ 0 "" 2 + 573 .thumb + 574 .syntax unified + 575 0214 C7F8C431 str r3, [r7, #452] + 576 0218 4FF40033 mov r3, #131072 + 577 021c C7F8C031 str r3, [r7, #448] + 578 .LBE181: + 579 .LBE180: + 580 .LBB182: + 581 .LBB183: + 582 0220 D7F8C031 ldr r3, [r7, #448] + 583 .syntax unified + 584 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 585 0224 93FAA3F3 rbit r3, r3 + 586 @ 0 "" 2 + 587 .thumb + 588 .syntax unified + 589 0228 C7F8BC31 str r3, [r7, #444] + 590 .LBE183: + 591 .LBE182: + 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 592 .loc 1 363 15 discriminator 8 + 593 022c 384B ldr r3, .L154 + 594 022e 5B6A ldr r3, [r3, #36] + 595 .L34: + 596 0230 4FF40032 mov r2, #131072 + 597 0234 C7F8B821 str r2, [r7, #440] + 598 .LBB184: + 599 .LBB185: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 600 .loc 2 988 4 + 601 0238 D7F8B821 ldr r2, [r7, #440] + 602 .syntax unified + 603 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 604 023c 92FAA2F2 rbit r2, r2 + 605 @ 0 "" 2 + 606 .thumb + 607 .syntax unified + 608 0240 C7F8B421 str r2, [r7, #436] + 609 .loc 2 1001 10 + 610 0244 D7F8B421 ldr r2, [r7, #436] + 611 .LBE185: + 612 .LBE184: + ARM GAS /tmp/ccSuWkwR.s page 36 + + + 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 613 .loc 1 363 15 discriminator 1 + 614 0248 B2FA82F2 clz r2, r2 + 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 615 .loc 1 363 15 is_stmt 0 discriminator 2 + 616 024c D2B2 uxtb r2, r2 + 617 024e 42F02002 orr r2, r2, #32 + 618 0252 D2B2 uxtb r2, r2 + 619 0254 02F01F02 and r2, r2, #31 + 620 0258 0121 movs r1, #1 + 621 025a 01FA02F2 lsl r2, r1, r2 + 622 025e 1340 ands r3, r3, r2 + 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 623 .loc 1 363 51 is_stmt 1 discriminator 2 + 624 0260 002B cmp r3, #0 + 625 0262 B0D0 beq .L38 + 626 0264 57E0 b .L16 + 627 .L30: + 368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else + 372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get Start Tick */ + 374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 628 .loc 1 374 21 + 629 0266 FFF7FEFF bl HAL_GetTick + 630 026a C7F8F801 str r0, [r7, #504] + 375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Wait till HSE is disabled */ + 377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + 631 .loc 1 377 14 + 632 026e 0AE0 b .L39 + 633 .L46: + 378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + 634 .loc 1 379 16 + 635 0270 FFF7FEFF bl HAL_GetTick + 636 0274 0246 mov r2, r0 + 637 .loc 1 379 30 discriminator 1 + 638 0276 D7F8F831 ldr r3, [r7, #504] + 639 027a D31A subs r3, r2, r3 + 640 .loc 1 379 14 discriminator 1 + 641 027c 642B cmp r3, #100 + 642 027e 02D9 bls .L39 + 380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_TIMEOUT; + 643 .loc 1 381 20 + 644 0280 0323 movs r3, #3 + 645 0282 00F0C4BE b .L15 + 646 .L39: + 647 0286 4FF40033 mov r3, #131072 + 648 028a C7F8B031 str r3, [r7, #432] + 649 .LBB186: + 650 .LBB187: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 651 .loc 2 988 4 + ARM GAS /tmp/ccSuWkwR.s page 37 + + + 652 028e D7F8B031 ldr r3, [r7, #432] + 653 .syntax unified + 654 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 655 0292 93FAA3F3 rbit r3, r3 + 656 @ 0 "" 2 + 657 .thumb + 658 .syntax unified + 659 0296 C7F8AC31 str r3, [r7, #428] + 660 .loc 2 1001 10 + 661 029a D7F8AC31 ldr r3, [r7, #428] + 662 .LBE187: + 663 .LBE186: + 377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 664 .loc 1 377 15 discriminator 1 + 665 029e B3FA83F3 clz r3, r3 + 377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 666 .loc 1 377 15 is_stmt 0 discriminator 2 + 667 02a2 DBB2 uxtb r3, r3 + 668 02a4 3F2B cmp r3, #63 + 669 02a6 02D8 bhi .L41 + 377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 670 .loc 1 377 15 discriminator 1 + 671 02a8 194B ldr r3, .L154 + 672 02aa 1B68 ldr r3, [r3] + 673 02ac 15E0 b .L42 + 674 .L41: + 675 02ae 4FF40033 mov r3, #131072 + 676 02b2 C7F8A831 str r3, [r7, #424] + 677 .LBB188: + 678 .LBB189: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 679 .loc 2 988 4 is_stmt 1 + 680 02b6 D7F8A831 ldr r3, [r7, #424] + 681 .syntax unified + 682 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 683 02ba 93FAA3F3 rbit r3, r3 + 684 @ 0 "" 2 + 685 .thumb + 686 .syntax unified + 687 02be C7F8A431 str r3, [r7, #420] + 688 02c2 4FF40033 mov r3, #131072 + 689 02c6 C7F8A031 str r3, [r7, #416] + 690 .LBE189: + 691 .LBE188: + 692 .LBB190: + 693 .LBB191: + 694 02ca D7F8A031 ldr r3, [r7, #416] + 695 .syntax unified + 696 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 697 02ce 93FAA3F3 rbit r3, r3 + 698 @ 0 "" 2 + 699 .thumb + 700 .syntax unified + 701 02d2 C7F89C31 str r3, [r7, #412] + 702 .LBE191: + 703 .LBE190: + 377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + ARM GAS /tmp/ccSuWkwR.s page 38 + + + 704 .loc 1 377 15 discriminator 8 + 705 02d6 0E4B ldr r3, .L154 + 706 02d8 5B6A ldr r3, [r3, #36] + 707 .L42: + 708 02da 4FF40032 mov r2, #131072 + 709 02de C7F89821 str r2, [r7, #408] + 710 .LBB192: + 711 .LBB193: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 712 .loc 2 988 4 + 713 02e2 D7F89821 ldr r2, [r7, #408] + 714 .syntax unified + 715 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 716 02e6 92FAA2F2 rbit r2, r2 + 717 @ 0 "" 2 + 718 .thumb + 719 .syntax unified + 720 02ea C7F89421 str r2, [r7, #404] + 721 .loc 2 1001 10 + 722 02ee D7F89421 ldr r2, [r7, #404] + 723 .LBE193: + 724 .LBE192: + 377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 725 .loc 1 377 15 discriminator 1 + 726 02f2 B2FA82F2 clz r2, r2 + 377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 727 .loc 1 377 15 is_stmt 0 discriminator 2 + 728 02f6 D2B2 uxtb r2, r2 + 729 02f8 42F02002 orr r2, r2, #32 + 730 02fc D2B2 uxtb r2, r2 + 731 02fe 02F01F02 and r2, r2, #31 + 732 0302 0121 movs r1, #1 + 733 0304 01FA02F2 lsl r2, r1, r2 + 734 0308 1340 ands r3, r3, r2 + 377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 735 .loc 1 377 51 is_stmt 1 discriminator 2 + 736 030a 002B cmp r3, #0 + 737 030c B0D1 bne .L46 + 738 030e 02E0 b .L16 + 739 .L155: + 740 .align 2 + 741 .L154: + 742 0310 00100240 .word 1073876992 + 743 .L153: + 341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 744 .loc 1 341 9 + 745 0314 00BF nop + 746 .L16: + 382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /*----------------------------- HSI Configuration --------------------------*/ + 388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + 747 .loc 1 388 25 + 748 0316 07F50073 add r3, r7, #512 + ARM GAS /tmp/ccSuWkwR.s page 39 + + + 749 031a A3F5FE73 sub r3, r3, #508 + 750 031e 1B68 ldr r3, [r3] + 751 0320 1B68 ldr r3, [r3] + 752 .loc 1 388 43 + 753 0322 03F00203 and r3, r3, #2 + 754 .loc 1 388 5 + 755 0326 002B cmp r3, #0 + 756 0328 00F06C81 beq .L47 + 389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the parameters */ + 391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + 392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + 393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock * + 395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) + 757 .loc 1 395 9 + 758 032c CC4B ldr r3, .L156 + 759 032e 5B68 ldr r3, [r3, #4] + 760 0330 03F00C03 and r3, r3, #12 + 761 .loc 1 395 7 + 762 0334 002B cmp r3, #0 + 763 0336 0BD0 beq .L48 + 396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_ + 764 .loc 1 396 13 + 765 0338 C94B ldr r3, .L156 + 766 033a 5B68 ldr r3, [r3, #4] + 767 033c 03F00C03 and r3, r3, #12 + 768 .loc 1 396 8 + 769 0340 082B cmp r3, #8 + 770 0342 6DD1 bne .L49 + 771 .loc 1 396 82 discriminator 1 + 772 0344 C64B ldr r3, .L156 + 773 0346 5B68 ldr r3, [r3, #4] + 774 0348 03F48033 and r3, r3, #65536 + 775 .loc 1 396 78 discriminator 1 + 776 034c 002B cmp r3, #0 + 777 034e 67D1 bne .L49 + 778 .L48: + 779 0350 0223 movs r3, #2 + 780 0352 C7F89031 str r3, [r7, #400] + 781 .LBB194: + 782 .LBB195: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 783 .loc 2 988 4 + 784 0356 D7F89031 ldr r3, [r7, #400] + 785 .syntax unified + 786 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 787 035a 93FAA3F3 rbit r3, r3 + 788 @ 0 "" 2 + 789 .thumb + 790 .syntax unified + 791 035e C7F88C31 str r3, [r7, #396] + 792 .loc 2 1001 10 + 793 0362 D7F88C31 ldr r3, [r7, #396] + 794 .LBE195: + 795 .LBE194: + 397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + ARM GAS /tmp/ccSuWkwR.s page 40 + + + 398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* When HSI is used as system clock it will not disabled */ + 399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ + 796 .loc 1 399 11 discriminator 1 + 797 0366 B3FA83F3 clz r3, r3 + 798 .loc 1 399 11 is_stmt 0 discriminator 2 + 799 036a DBB2 uxtb r3, r3 + 800 036c 3F2B cmp r3, #63 + 801 036e 02D8 bhi .L51 + 802 .loc 1 399 11 discriminator 1 + 803 0370 BB4B ldr r3, .L156 + 804 0372 1B68 ldr r3, [r3] + 805 0374 13E0 b .L52 + 806 .L51: + 807 0376 0223 movs r3, #2 + 808 0378 C7F88831 str r3, [r7, #392] + 809 .LBB196: + 810 .LBB197: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 811 .loc 2 988 4 is_stmt 1 + 812 037c D7F88831 ldr r3, [r7, #392] + 813 .syntax unified + 814 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 815 0380 93FAA3F3 rbit r3, r3 + 816 @ 0 "" 2 + 817 .thumb + 818 .syntax unified + 819 0384 C7F88431 str r3, [r7, #388] + 820 0388 0223 movs r3, #2 + 821 038a C7F88031 str r3, [r7, #384] + 822 .LBE197: + 823 .LBE196: + 824 .LBB198: + 825 .LBB199: + 826 038e D7F88031 ldr r3, [r7, #384] + 827 .syntax unified + 828 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 829 0392 93FAA3F3 rbit r3, r3 + 830 @ 0 "" 2 + 831 .thumb + 832 .syntax unified + 833 0396 C7F87C31 str r3, [r7, #380] + 834 .LBE199: + 835 .LBE198: + 836 .loc 1 399 11 discriminator 8 + 837 039a B14B ldr r3, .L156 + 838 039c 5B6A ldr r3, [r3, #36] + 839 .L52: + 840 039e 0222 movs r2, #2 + 841 03a0 C7F87821 str r2, [r7, #376] + 842 .LBB200: + 843 .LBB201: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 844 .loc 2 988 4 + 845 03a4 D7F87821 ldr r2, [r7, #376] + 846 .syntax unified + 847 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 848 03a8 92FAA2F2 rbit r2, r2 + ARM GAS /tmp/ccSuWkwR.s page 41 + + + 849 @ 0 "" 2 + 850 .thumb + 851 .syntax unified + 852 03ac C7F87421 str r2, [r7, #372] + 853 .loc 2 1001 10 + 854 03b0 D7F87421 ldr r2, [r7, #372] + 855 .LBE201: + 856 .LBE200: + 857 .loc 1 399 11 discriminator 1 + 858 03b4 B2FA82F2 clz r2, r2 + 859 .loc 1 399 11 is_stmt 0 discriminator 2 + 860 03b8 D2B2 uxtb r2, r2 + 861 03ba 42F02002 orr r2, r2, #32 + 862 03be D2B2 uxtb r2, r2 + 863 03c0 02F01F02 and r2, r2, #31 + 864 03c4 0121 movs r1, #1 + 865 03c6 01FA02F2 lsl r2, r1, r2 + 866 03ca 1340 ands r3, r3, r2 + 867 .loc 1 399 9 is_stmt 1 discriminator 2 + 868 03cc 002B cmp r3, #0 + 869 03ce 0AD0 beq .L56 + 870 .loc 1 399 78 discriminator 13 + 871 03d0 07F50073 add r3, r7, #512 + 872 03d4 A3F5FE73 sub r3, r3, #508 + 873 03d8 1B68 ldr r3, [r3] + 874 03da 1B69 ldr r3, [r3, #16] + 875 .loc 1 399 57 discriminator 13 + 876 03dc 012B cmp r3, #1 + 877 03de 02D0 beq .L56 + 400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_ERROR; + 878 .loc 1 401 16 + 879 03e0 0123 movs r3, #1 + 880 03e2 00F014BE b .L15 + 881 .L56: + 402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Otherwise, just the calibration is allowed */ + 404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else + 405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + 407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 882 .loc 1 407 9 + 883 03e6 9E4B ldr r3, .L156 + 884 03e8 1B68 ldr r3, [r3] + 885 03ea 23F0F802 bic r2, r3, #248 + 886 03ee 07F50073 add r3, r7, #512 + 887 03f2 A3F5FE73 sub r3, r3, #508 + 888 03f6 1B68 ldr r3, [r3] + 889 03f8 5B69 ldr r3, [r3, #20] + 890 03fa F821 movs r1, #248 + 891 03fc C7F87011 str r1, [r7, #368] + 892 .LBB202: + 893 .LBB203: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 894 .loc 2 988 4 + 895 0400 D7F87011 ldr r1, [r7, #368] + 896 .syntax unified + ARM GAS /tmp/ccSuWkwR.s page 42 + + + 897 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 898 0404 91FAA1F1 rbit r1, r1 + 899 @ 0 "" 2 + 900 .thumb + 901 .syntax unified + 902 0408 C7F86C11 str r1, [r7, #364] + 903 .loc 2 1001 10 + 904 040c D7F86C11 ldr r1, [r7, #364] + 905 .LBE203: + 906 .LBE202: + 907 .loc 1 407 9 discriminator 1 + 908 0410 B1FA81F1 clz r1, r1 + 909 .loc 1 407 9 is_stmt 0 discriminator 2 + 910 0414 C9B2 uxtb r1, r1 + 911 0416 8B40 lsls r3, r3, r1 + 912 0418 9149 ldr r1, .L156 + 913 041a 1343 orrs r3, r3, r2 + 914 041c 0B60 str r3, [r1] + 399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 915 .loc 1 399 9 is_stmt 1 + 916 041e F1E0 b .L47 + 917 .L49: + 408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else + 411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the HSI State */ + 413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) + 918 .loc 1 413 27 + 919 0420 07F50073 add r3, r7, #512 + 920 0424 A3F5FE73 sub r3, r3, #508 + 921 0428 1B68 ldr r3, [r3] + 922 042a 1B69 ldr r3, [r3, #16] + 923 .loc 1 413 9 + 924 042c 002B cmp r3, #0 + 925 042e 00F08380 beq .L58 + 926 0432 0123 movs r3, #1 + 927 0434 C7F86831 str r3, [r7, #360] + 928 .LBB204: + 929 .LBB205: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 930 .loc 2 988 4 + 931 0438 D7F86831 ldr r3, [r7, #360] + 932 .syntax unified + 933 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 934 043c 93FAA3F3 rbit r3, r3 + 935 @ 0 "" 2 + 936 .thumb + 937 .syntax unified + 938 0440 C7F86431 str r3, [r7, #356] + 939 .loc 2 1001 10 + 940 0444 D7F86431 ldr r3, [r7, #356] + 941 .LBE205: + 942 .LBE204: + 414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Enable the Internal High Speed oscillator (HSI). */ + 416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_HSI_ENABLE(); + ARM GAS /tmp/ccSuWkwR.s page 43 + + + 943 .loc 1 416 9 discriminator 1 + 944 0448 B3FA83F3 clz r3, r3 + 945 .loc 1 416 9 is_stmt 0 discriminator 2 + 946 044c DBB2 uxtb r3, r3 + 947 044e 03F18453 add r3, r3, #276824064 + 948 0452 03F58413 add r3, r3, #1081344 + 949 0456 9B00 lsls r3, r3, #2 + 950 0458 1A46 mov r2, r3 + 951 045a 0123 movs r3, #1 + 952 045c 1360 str r3, [r2] + 417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get Start Tick */ + 419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 953 .loc 1 419 21 is_stmt 1 + 954 045e FFF7FEFF bl HAL_GetTick + 955 0462 C7F8F801 str r0, [r7, #504] + 420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Wait till HSI is ready */ + 422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + 956 .loc 1 422 14 + 957 0466 0AE0 b .L60 + 958 .L67: + 423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + 959 .loc 1 424 15 + 960 0468 FFF7FEFF bl HAL_GetTick + 961 046c 0246 mov r2, r0 + 962 .loc 1 424 29 discriminator 1 + 963 046e D7F8F831 ldr r3, [r7, #504] + 964 0472 D31A subs r3, r2, r3 + 965 .loc 1 424 13 discriminator 1 + 966 0474 022B cmp r3, #2 + 967 0476 02D9 bls .L60 + 425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_TIMEOUT; + 968 .loc 1 426 20 + 969 0478 0323 movs r3, #3 + 970 047a 00F0C8BD b .L15 + 971 .L60: + 972 047e 0223 movs r3, #2 + 973 0480 C7F86031 str r3, [r7, #352] + 974 .LBB206: + 975 .LBB207: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 976 .loc 2 988 4 + 977 0484 D7F86031 ldr r3, [r7, #352] + 978 .syntax unified + 979 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 980 0488 93FAA3F3 rbit r3, r3 + 981 @ 0 "" 2 + 982 .thumb + 983 .syntax unified + 984 048c C7F85C31 str r3, [r7, #348] + 985 .loc 2 1001 10 + 986 0490 D7F85C31 ldr r3, [r7, #348] + 987 .LBE207: + 988 .LBE206: + ARM GAS /tmp/ccSuWkwR.s page 44 + + + 422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 989 .loc 1 422 15 discriminator 1 + 990 0494 B3FA83F3 clz r3, r3 + 422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 991 .loc 1 422 15 is_stmt 0 discriminator 2 + 992 0498 DBB2 uxtb r3, r3 + 993 049a 3F2B cmp r3, #63 + 994 049c 02D8 bhi .L62 + 422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 995 .loc 1 422 15 discriminator 1 + 996 049e 704B ldr r3, .L156 + 997 04a0 1B68 ldr r3, [r3] + 998 04a2 13E0 b .L63 + 999 .L62: + 1000 04a4 0223 movs r3, #2 + 1001 04a6 C7F85831 str r3, [r7, #344] + 1002 .LBB208: + 1003 .LBB209: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 1004 .loc 2 988 4 is_stmt 1 + 1005 04aa D7F85831 ldr r3, [r7, #344] + 1006 .syntax unified + 1007 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1008 04ae 93FAA3F3 rbit r3, r3 + 1009 @ 0 "" 2 + 1010 .thumb + 1011 .syntax unified + 1012 04b2 C7F85431 str r3, [r7, #340] + 1013 04b6 0223 movs r3, #2 + 1014 04b8 C7F85031 str r3, [r7, #336] + 1015 .LBE209: + 1016 .LBE208: + 1017 .LBB210: + 1018 .LBB211: + 1019 04bc D7F85031 ldr r3, [r7, #336] + 1020 .syntax unified + 1021 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1022 04c0 93FAA3F3 rbit r3, r3 + 1023 @ 0 "" 2 + 1024 .thumb + 1025 .syntax unified + 1026 04c4 C7F84C31 str r3, [r7, #332] + 1027 .LBE211: + 1028 .LBE210: + 422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1029 .loc 1 422 15 discriminator 8 + 1030 04c8 654B ldr r3, .L156 + 1031 04ca 5B6A ldr r3, [r3, #36] + 1032 .L63: + 1033 04cc 0222 movs r2, #2 + 1034 04ce C7F84821 str r2, [r7, #328] + 1035 .LBB212: + 1036 .LBB213: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 1037 .loc 2 988 4 + 1038 04d2 D7F84821 ldr r2, [r7, #328] + 1039 .syntax unified + ARM GAS /tmp/ccSuWkwR.s page 45 + + + 1040 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1041 04d6 92FAA2F2 rbit r2, r2 + 1042 @ 0 "" 2 + 1043 .thumb + 1044 .syntax unified + 1045 04da C7F84421 str r2, [r7, #324] + 1046 .loc 2 1001 10 + 1047 04de D7F84421 ldr r2, [r7, #324] + 1048 .LBE213: + 1049 .LBE212: + 422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1050 .loc 1 422 15 discriminator 1 + 1051 04e2 B2FA82F2 clz r2, r2 + 422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1052 .loc 1 422 15 is_stmt 0 discriminator 2 + 1053 04e6 D2B2 uxtb r2, r2 + 1054 04e8 42F02002 orr r2, r2, #32 + 1055 04ec D2B2 uxtb r2, r2 + 1056 04ee 02F01F02 and r2, r2, #31 + 1057 04f2 0121 movs r1, #1 + 1058 04f4 01FA02F2 lsl r2, r1, r2 + 1059 04f8 1340 ands r3, r3, r2 + 422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1060 .loc 1 422 51 is_stmt 1 discriminator 2 + 1061 04fa 002B cmp r3, #0 + 1062 04fc B4D0 beq .L67 + 427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + 431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 1063 .loc 1 431 9 + 1064 04fe 584B ldr r3, .L156 + 1065 0500 1B68 ldr r3, [r3] + 1066 0502 23F0F802 bic r2, r3, #248 + 1067 0506 07F50073 add r3, r7, #512 + 1068 050a A3F5FE73 sub r3, r3, #508 + 1069 050e 1B68 ldr r3, [r3] + 1070 0510 5B69 ldr r3, [r3, #20] + 1071 0512 F821 movs r1, #248 + 1072 0514 C7F84011 str r1, [r7, #320] + 1073 .LBB214: + 1074 .LBB215: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 1075 .loc 2 988 4 + 1076 0518 D7F84011 ldr r1, [r7, #320] + 1077 .syntax unified + 1078 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1079 051c 91FAA1F1 rbit r1, r1 + 1080 @ 0 "" 2 + 1081 .thumb + 1082 .syntax unified + 1083 0520 C7F83C11 str r1, [r7, #316] + 1084 .loc 2 1001 10 + 1085 0524 D7F83C11 ldr r1, [r7, #316] + 1086 .LBE215: + 1087 .LBE214: + ARM GAS /tmp/ccSuWkwR.s page 46 + + + 1088 .loc 1 431 9 discriminator 1 + 1089 0528 B1FA81F1 clz r1, r1 + 1090 .loc 1 431 9 is_stmt 0 discriminator 2 + 1091 052c C9B2 uxtb r1, r1 + 1092 052e 8B40 lsls r3, r3, r1 + 1093 0530 4B49 ldr r1, .L156 + 1094 0532 1343 orrs r3, r3, r2 + 1095 0534 0B60 str r3, [r1] + 1096 0536 65E0 b .L47 + 1097 .L58: + 1098 0538 0123 movs r3, #1 + 1099 053a C7F83831 str r3, [r7, #312] + 1100 .LBB216: + 1101 .LBB217: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 1102 .loc 2 988 4 is_stmt 1 + 1103 053e D7F83831 ldr r3, [r7, #312] + 1104 .syntax unified + 1105 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1106 0542 93FAA3F3 rbit r3, r3 + 1107 @ 0 "" 2 + 1108 .thumb + 1109 .syntax unified + 1110 0546 C7F83431 str r3, [r7, #308] + 1111 .loc 2 1001 10 + 1112 054a D7F83431 ldr r3, [r7, #308] + 1113 .LBE217: + 1114 .LBE216: + 432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else + 434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Disable the Internal High Speed oscillator (HSI). */ + 436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_HSI_DISABLE(); + 1115 .loc 1 436 9 discriminator 1 + 1116 054e B3FA83F3 clz r3, r3 + 1117 .loc 1 436 9 is_stmt 0 discriminator 2 + 1118 0552 DBB2 uxtb r3, r3 + 1119 0554 03F18453 add r3, r3, #276824064 + 1120 0558 03F58413 add r3, r3, #1081344 + 1121 055c 9B00 lsls r3, r3, #2 + 1122 055e 1A46 mov r2, r3 + 1123 0560 0023 movs r3, #0 + 1124 0562 1360 str r3, [r2] + 437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get Start Tick */ + 439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 1125 .loc 1 439 21 is_stmt 1 + 1126 0564 FFF7FEFF bl HAL_GetTick + 1127 0568 C7F8F801 str r0, [r7, #504] + 440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Wait till HSI is disabled */ + 442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + 1128 .loc 1 442 14 + 1129 056c 0AE0 b .L70 + 1130 .L77: + 443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + ARM GAS /tmp/ccSuWkwR.s page 47 + + + 1131 .loc 1 444 15 + 1132 056e FFF7FEFF bl HAL_GetTick + 1133 0572 0246 mov r2, r0 + 1134 .loc 1 444 29 discriminator 1 + 1135 0574 D7F8F831 ldr r3, [r7, #504] + 1136 0578 D31A subs r3, r2, r3 + 1137 .loc 1 444 13 discriminator 1 + 1138 057a 022B cmp r3, #2 + 1139 057c 02D9 bls .L70 + 445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_TIMEOUT; + 1140 .loc 1 446 20 + 1141 057e 0323 movs r3, #3 + 1142 0580 00F045BD b .L15 + 1143 .L70: + 1144 0584 0223 movs r3, #2 + 1145 0586 C7F83031 str r3, [r7, #304] + 1146 .LBB218: + 1147 .LBB219: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 1148 .loc 2 988 4 + 1149 058a D7F83031 ldr r3, [r7, #304] + 1150 .syntax unified + 1151 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1152 058e 93FAA3F3 rbit r3, r3 + 1153 @ 0 "" 2 + 1154 .thumb + 1155 .syntax unified + 1156 0592 C7F82C31 str r3, [r7, #300] + 1157 .loc 2 1001 10 + 1158 0596 D7F82C31 ldr r3, [r7, #300] + 1159 .LBE219: + 1160 .LBE218: + 442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1161 .loc 1 442 15 discriminator 1 + 1162 059a B3FA83F3 clz r3, r3 + 442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1163 .loc 1 442 15 is_stmt 0 discriminator 2 + 1164 059e DBB2 uxtb r3, r3 + 1165 05a0 3F2B cmp r3, #63 + 1166 05a2 02D8 bhi .L72 + 442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1167 .loc 1 442 15 discriminator 1 + 1168 05a4 2E4B ldr r3, .L156 + 1169 05a6 1B68 ldr r3, [r3] + 1170 05a8 13E0 b .L73 + 1171 .L72: + 1172 05aa 0223 movs r3, #2 + 1173 05ac C7F82831 str r3, [r7, #296] + 1174 .LBB220: + 1175 .LBB221: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 1176 .loc 2 988 4 is_stmt 1 + 1177 05b0 D7F82831 ldr r3, [r7, #296] + 1178 .syntax unified + 1179 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1180 05b4 93FAA3F3 rbit r3, r3 + ARM GAS /tmp/ccSuWkwR.s page 48 + + + 1181 @ 0 "" 2 + 1182 .thumb + 1183 .syntax unified + 1184 05b8 C7F82431 str r3, [r7, #292] + 1185 05bc 0223 movs r3, #2 + 1186 05be C7F82031 str r3, [r7, #288] + 1187 .LBE221: + 1188 .LBE220: + 1189 .LBB222: + 1190 .LBB223: + 1191 05c2 D7F82031 ldr r3, [r7, #288] + 1192 .syntax unified + 1193 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1194 05c6 93FAA3F3 rbit r3, r3 + 1195 @ 0 "" 2 + 1196 .thumb + 1197 .syntax unified + 1198 05ca C7F81C31 str r3, [r7, #284] + 1199 .LBE223: + 1200 .LBE222: + 442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1201 .loc 1 442 15 discriminator 8 + 1202 05ce 244B ldr r3, .L156 + 1203 05d0 5B6A ldr r3, [r3, #36] + 1204 .L73: + 1205 05d2 0222 movs r2, #2 + 1206 05d4 C7F81821 str r2, [r7, #280] + 1207 .LBB224: + 1208 .LBB225: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 1209 .loc 2 988 4 + 1210 05d8 D7F81821 ldr r2, [r7, #280] + 1211 .syntax unified + 1212 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1213 05dc 92FAA2F2 rbit r2, r2 + 1214 @ 0 "" 2 + 1215 .thumb + 1216 .syntax unified + 1217 05e0 C7F81421 str r2, [r7, #276] + 1218 .loc 2 1001 10 + 1219 05e4 D7F81421 ldr r2, [r7, #276] + 1220 .LBE225: + 1221 .LBE224: + 442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1222 .loc 1 442 15 discriminator 1 + 1223 05e8 B2FA82F2 clz r2, r2 + 442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1224 .loc 1 442 15 is_stmt 0 discriminator 2 + 1225 05ec D2B2 uxtb r2, r2 + 1226 05ee 42F02002 orr r2, r2, #32 + 1227 05f2 D2B2 uxtb r2, r2 + 1228 05f4 02F01F02 and r2, r2, #31 + 1229 05f8 0121 movs r1, #1 + 1230 05fa 01FA02F2 lsl r2, r1, r2 + 1231 05fe 1340 ands r3, r3, r2 + 442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1232 .loc 1 442 51 is_stmt 1 discriminator 2 + ARM GAS /tmp/ccSuWkwR.s page 49 + + + 1233 0600 002B cmp r3, #0 + 1234 0602 B4D1 bne .L77 + 1235 .L47: + 447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /*------------------------------ LSI Configuration -------------------------*/ + 453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + 1236 .loc 1 453 25 + 1237 0604 07F50073 add r3, r7, #512 + 1238 0608 A3F5FE73 sub r3, r3, #508 + 1239 060c 1B68 ldr r3, [r3] + 1240 060e 1B68 ldr r3, [r3] + 1241 .loc 1 453 43 + 1242 0610 03F00803 and r3, r3, #8 + 1243 .loc 1 453 5 + 1244 0614 002B cmp r3, #0 + 1245 0616 00F01581 beq .L78 + 454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the parameters */ + 456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + 457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the LSI State */ + 459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) + 1246 .loc 1 459 25 + 1247 061a 07F50073 add r3, r7, #512 + 1248 061e A3F5FE73 sub r3, r3, #508 + 1249 0622 1B68 ldr r3, [r3] + 1250 0624 9B69 ldr r3, [r3, #24] + 1251 .loc 1 459 7 + 1252 0626 002B cmp r3, #0 + 1253 0628 7ED0 beq .L79 + 1254 062a 0123 movs r3, #1 + 1255 062c C7F81031 str r3, [r7, #272] + 1256 .LBB226: + 1257 .LBB227: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 1258 .loc 2 988 4 + 1259 0630 D7F81031 ldr r3, [r7, #272] + 1260 .syntax unified + 1261 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1262 0634 93FAA3F3 rbit r3, r3 + 1263 @ 0 "" 2 + 1264 .thumb + 1265 .syntax unified + 1266 0638 C7F80C31 str r3, [r7, #268] + 1267 .loc 2 1001 10 + 1268 063c D7F80C31 ldr r3, [r7, #268] + 1269 .LBE227: + 1270 .LBE226: + 460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Enable the Internal Low Speed oscillator (LSI). */ + 462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_LSI_ENABLE(); + 1271 .loc 1 462 7 discriminator 1 + 1272 0640 B3FA83F3 clz r3, r3 + ARM GAS /tmp/ccSuWkwR.s page 50 + + + 1273 .loc 1 462 7 is_stmt 0 discriminator 2 + 1274 0644 DBB2 uxtb r3, r3 + 1275 0646 1A46 mov r2, r3 + 1276 0648 064B ldr r3, .L156+4 + 1277 064a 1344 add r3, r3, r2 + 1278 064c 9B00 lsls r3, r3, #2 + 1279 064e 1A46 mov r2, r3 + 1280 0650 0123 movs r3, #1 + 1281 0652 1360 str r3, [r2] + 463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get Start Tick */ + 465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 1282 .loc 1 465 19 is_stmt 1 + 1283 0654 FFF7FEFF bl HAL_GetTick + 1284 0658 C7F8F801 str r0, [r7, #504] + 466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Wait till LSI is ready */ + 468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + 1285 .loc 1 468 12 + 1286 065c 0FE0 b .L81 + 1287 .L157: + 1288 065e 00BF .align 2 + 1289 .L156: + 1290 0660 00100240 .word 1073876992 + 1291 0664 20819010 .word 277905696 + 1292 .L86: + 469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + 1293 .loc 1 470 13 + 1294 0668 FFF7FEFF bl HAL_GetTick + 1295 066c 0246 mov r2, r0 + 1296 .loc 1 470 27 discriminator 1 + 1297 066e D7F8F831 ldr r3, [r7, #504] + 1298 0672 D31A subs r3, r2, r3 + 1299 .loc 1 470 11 discriminator 1 + 1300 0674 022B cmp r3, #2 + 1301 0676 02D9 bls .L81 + 471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_TIMEOUT; + 1302 .loc 1 472 18 + 1303 0678 0323 movs r3, #3 + 1304 067a 00F0C8BC b .L15 + 1305 .L81: + 1306 067e 0223 movs r3, #2 + 1307 0680 C7F80831 str r3, [r7, #264] + 1308 .LBB228: + 1309 .LBB229: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 1310 .loc 2 988 4 + 1311 0684 D7F80831 ldr r3, [r7, #264] + 1312 .syntax unified + 1313 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1314 0688 93FAA3F3 rbit r3, r3 + 1315 @ 0 "" 2 + 1316 .thumb + 1317 .syntax unified + 1318 068c C7F80431 str r3, [r7, #260] + ARM GAS /tmp/ccSuWkwR.s page 51 + + + 1319 0690 07F50073 add r3, r7, #512 + 1320 0694 A3F58073 sub r3, r3, #256 + 1321 0698 0222 movs r2, #2 + 1322 069a 1A60 str r2, [r3] + 1323 .LBE229: + 1324 .LBE228: + 1325 .LBB230: + 1326 .LBB231: + 1327 069c 07F50073 add r3, r7, #512 + 1328 06a0 A3F58073 sub r3, r3, #256 + 1329 06a4 1B68 ldr r3, [r3] + 1330 .syntax unified + 1331 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1332 06a6 93FAA3F2 rbit r2, r3 + 1333 @ 0 "" 2 + 1334 .thumb + 1335 .syntax unified + 1336 06aa 07F50073 add r3, r7, #512 + 1337 06ae A3F58273 sub r3, r3, #260 + 1338 06b2 1A60 str r2, [r3] + 1339 06b4 07F50073 add r3, r7, #512 + 1340 06b8 A3F58473 sub r3, r3, #264 + 1341 06bc 0222 movs r2, #2 + 1342 06be 1A60 str r2, [r3] + 1343 .LBE231: + 1344 .LBE230: + 1345 .LBB232: + 1346 .LBB233: + 1347 06c0 07F50073 add r3, r7, #512 + 1348 06c4 A3F58473 sub r3, r3, #264 + 1349 06c8 1B68 ldr r3, [r3] + 1350 .syntax unified + 1351 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1352 06ca 93FAA3F2 rbit r2, r3 + 1353 @ 0 "" 2 + 1354 .thumb + 1355 .syntax unified + 1356 06ce 07F50073 add r3, r7, #512 + 1357 06d2 A3F58673 sub r3, r3, #268 + 1358 06d6 1A60 str r2, [r3] + 1359 .LBE233: + 1360 .LBE232: + 468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1361 .loc 1 468 13 discriminator 8 + 1362 06d8 B04B ldr r3, .L158 + 1363 06da 5A6A ldr r2, [r3, #36] + 1364 06dc 07F50073 add r3, r7, #512 + 1365 06e0 A3F58873 sub r3, r3, #272 + 1366 06e4 0221 movs r1, #2 + 1367 06e6 1960 str r1, [r3] + 1368 .LBB234: + 1369 .LBB235: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 1370 .loc 2 988 4 + 1371 06e8 07F50073 add r3, r7, #512 + 1372 06ec A3F58873 sub r3, r3, #272 + 1373 06f0 1B68 ldr r3, [r3] + ARM GAS /tmp/ccSuWkwR.s page 52 + + + 1374 .syntax unified + 1375 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1376 06f2 93FAA3F1 rbit r1, r3 + 1377 @ 0 "" 2 + 1378 .thumb + 1379 .syntax unified + 1380 06f6 07F50073 add r3, r7, #512 + 1381 06fa A3F58A73 sub r3, r3, #276 + 1382 06fe 1960 str r1, [r3] + 1383 .loc 2 1001 10 + 1384 0700 07F50073 add r3, r7, #512 + 1385 0704 A3F58A73 sub r3, r3, #276 + 1386 0708 1B68 ldr r3, [r3] + 1387 .LBE235: + 1388 .LBE234: + 468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1389 .loc 1 468 13 discriminator 1 + 1390 070a B3FA83F3 clz r3, r3 + 468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1391 .loc 1 468 13 is_stmt 0 discriminator 2 + 1392 070e DBB2 uxtb r3, r3 + 1393 0710 43F06003 orr r3, r3, #96 + 1394 0714 DBB2 uxtb r3, r3 + 1395 0716 03F01F03 and r3, r3, #31 + 1396 071a 0121 movs r1, #1 + 1397 071c 01FA03F3 lsl r3, r1, r3 + 1398 0720 1340 ands r3, r3, r2 + 468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1399 .loc 1 468 49 is_stmt 1 discriminator 2 + 1400 0722 002B cmp r3, #0 + 1401 0724 A0D0 beq .L86 + 1402 0726 8DE0 b .L78 + 1403 .L79: + 1404 0728 07F50073 add r3, r7, #512 + 1405 072c A3F58C73 sub r3, r3, #280 + 1406 0730 0122 movs r2, #1 + 1407 0732 1A60 str r2, [r3] + 1408 .LBB236: + 1409 .LBB237: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 1410 .loc 2 988 4 + 1411 0734 07F50073 add r3, r7, #512 + 1412 0738 A3F58C73 sub r3, r3, #280 + 1413 073c 1B68 ldr r3, [r3] + 1414 .syntax unified + 1415 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1416 073e 93FAA3F2 rbit r2, r3 + 1417 @ 0 "" 2 + 1418 .thumb + 1419 .syntax unified + 1420 0742 07F50073 add r3, r7, #512 + 1421 0746 A3F58E73 sub r3, r3, #284 + 1422 074a 1A60 str r2, [r3] + 1423 .loc 2 1001 10 + 1424 074c 07F50073 add r3, r7, #512 + 1425 0750 A3F58E73 sub r3, r3, #284 + 1426 0754 1B68 ldr r3, [r3] + ARM GAS /tmp/ccSuWkwR.s page 53 + + + 1427 .LBE237: + 1428 .LBE236: + 473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else + 477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Disable the Internal Low Speed oscillator (LSI). */ + 479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_LSI_DISABLE(); + 1429 .loc 1 479 7 discriminator 1 + 1430 0756 B3FA83F3 clz r3, r3 + 1431 .loc 1 479 7 is_stmt 0 discriminator 2 + 1432 075a DBB2 uxtb r3, r3 + 1433 075c 1A46 mov r2, r3 + 1434 075e 904B ldr r3, .L158+4 + 1435 0760 1344 add r3, r3, r2 + 1436 0762 9B00 lsls r3, r3, #2 + 1437 0764 1A46 mov r2, r3 + 1438 0766 0023 movs r3, #0 + 1439 0768 1360 str r3, [r2] + 480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get Start Tick */ + 482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 1440 .loc 1 482 19 is_stmt 1 + 1441 076a FFF7FEFF bl HAL_GetTick + 1442 076e C7F8F801 str r0, [r7, #504] + 483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Wait till LSI is disabled */ + 485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + 1443 .loc 1 485 12 + 1444 0772 0AE0 b .L88 + 1445 .L93: + 486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + 1446 .loc 1 487 13 + 1447 0774 FFF7FEFF bl HAL_GetTick + 1448 0778 0246 mov r2, r0 + 1449 .loc 1 487 27 discriminator 1 + 1450 077a D7F8F831 ldr r3, [r7, #504] + 1451 077e D31A subs r3, r2, r3 + 1452 .loc 1 487 11 discriminator 1 + 1453 0780 022B cmp r3, #2 + 1454 0782 02D9 bls .L88 + 488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_TIMEOUT; + 1455 .loc 1 489 18 + 1456 0784 0323 movs r3, #3 + 1457 0786 00F042BC b .L15 + 1458 .L88: + 1459 078a 07F50073 add r3, r7, #512 + 1460 078e A3F59073 sub r3, r3, #288 + 1461 0792 0222 movs r2, #2 + 1462 0794 1A60 str r2, [r3] + 1463 .LBB238: + 1464 .LBB239: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 1465 .loc 2 988 4 + ARM GAS /tmp/ccSuWkwR.s page 54 + + + 1466 0796 07F50073 add r3, r7, #512 + 1467 079a A3F59073 sub r3, r3, #288 + 1468 079e 1B68 ldr r3, [r3] + 1469 .syntax unified + 1470 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1471 07a0 93FAA3F2 rbit r2, r3 + 1472 @ 0 "" 2 + 1473 .thumb + 1474 .syntax unified + 1475 07a4 07F50073 add r3, r7, #512 + 1476 07a8 A3F59273 sub r3, r3, #292 + 1477 07ac 1A60 str r2, [r3] + 1478 07ae 07F50073 add r3, r7, #512 + 1479 07b2 A3F59473 sub r3, r3, #296 + 1480 07b6 0222 movs r2, #2 + 1481 07b8 1A60 str r2, [r3] + 1482 .LBE239: + 1483 .LBE238: + 1484 .LBB240: + 1485 .LBB241: + 1486 07ba 07F50073 add r3, r7, #512 + 1487 07be A3F59473 sub r3, r3, #296 + 1488 07c2 1B68 ldr r3, [r3] + 1489 .syntax unified + 1490 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1491 07c4 93FAA3F2 rbit r2, r3 + 1492 @ 0 "" 2 + 1493 .thumb + 1494 .syntax unified + 1495 07c8 07F50073 add r3, r7, #512 + 1496 07cc A3F59673 sub r3, r3, #300 + 1497 07d0 1A60 str r2, [r3] + 1498 07d2 07F50073 add r3, r7, #512 + 1499 07d6 A3F59873 sub r3, r3, #304 + 1500 07da 0222 movs r2, #2 + 1501 07dc 1A60 str r2, [r3] + 1502 .LBE241: + 1503 .LBE240: + 1504 .LBB242: + 1505 .LBB243: + 1506 07de 07F50073 add r3, r7, #512 + 1507 07e2 A3F59873 sub r3, r3, #304 + 1508 07e6 1B68 ldr r3, [r3] + 1509 .syntax unified + 1510 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1511 07e8 93FAA3F2 rbit r2, r3 + 1512 @ 0 "" 2 + 1513 .thumb + 1514 .syntax unified + 1515 07ec 07F50073 add r3, r7, #512 + 1516 07f0 A3F59A73 sub r3, r3, #308 + 1517 07f4 1A60 str r2, [r3] + 1518 .LBE243: + 1519 .LBE242: + 485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1520 .loc 1 485 13 discriminator 8 + 1521 07f6 694B ldr r3, .L158 + ARM GAS /tmp/ccSuWkwR.s page 55 + + + 1522 07f8 5A6A ldr r2, [r3, #36] + 1523 07fa 07F50073 add r3, r7, #512 + 1524 07fe A3F59C73 sub r3, r3, #312 + 1525 0802 0221 movs r1, #2 + 1526 0804 1960 str r1, [r3] + 1527 .LBB244: + 1528 .LBB245: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 1529 .loc 2 988 4 + 1530 0806 07F50073 add r3, r7, #512 + 1531 080a A3F59C73 sub r3, r3, #312 + 1532 080e 1B68 ldr r3, [r3] + 1533 .syntax unified + 1534 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1535 0810 93FAA3F1 rbit r1, r3 + 1536 @ 0 "" 2 + 1537 .thumb + 1538 .syntax unified + 1539 0814 07F50073 add r3, r7, #512 + 1540 0818 A3F59E73 sub r3, r3, #316 + 1541 081c 1960 str r1, [r3] + 1542 .loc 2 1001 10 + 1543 081e 07F50073 add r3, r7, #512 + 1544 0822 A3F59E73 sub r3, r3, #316 + 1545 0826 1B68 ldr r3, [r3] + 1546 .LBE245: + 1547 .LBE244: + 485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1548 .loc 1 485 13 discriminator 1 + 1549 0828 B3FA83F3 clz r3, r3 + 485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1550 .loc 1 485 13 is_stmt 0 discriminator 2 + 1551 082c DBB2 uxtb r3, r3 + 1552 082e 43F06003 orr r3, r3, #96 + 1553 0832 DBB2 uxtb r3, r3 + 1554 0834 03F01F03 and r3, r3, #31 + 1555 0838 0121 movs r1, #1 + 1556 083a 01FA03F3 lsl r3, r1, r3 + 1557 083e 1340 ands r3, r3, r2 + 485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1558 .loc 1 485 49 is_stmt 1 discriminator 2 + 1559 0840 002B cmp r3, #0 + 1560 0842 97D1 bne .L93 + 1561 .L78: + 490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /*------------------------------ LSE Configuration -------------------------*/ + 495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + 1562 .loc 1 495 25 + 1563 0844 07F50073 add r3, r7, #512 + 1564 0848 A3F5FE73 sub r3, r3, #508 + 1565 084c 1B68 ldr r3, [r3] + 1566 084e 1B68 ldr r3, [r3] + 1567 .loc 1 495 43 + 1568 0850 03F00403 and r3, r3, #4 + ARM GAS /tmp/ccSuWkwR.s page 56 + + + 1569 .loc 1 495 5 + 1570 0854 002B cmp r3, #0 + 1571 0856 00F09E81 beq .L94 + 1572 .LBB246: + 496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** FlagStatus pwrclkchanged = RESET; + 1573 .loc 1 497 22 + 1574 085a 0023 movs r3, #0 + 1575 085c 87F8FF31 strb r3, [r7, #511] + 498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the parameters */ + 500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + 501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Update LSE configuration in Backup Domain control register */ + 503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Requires to enable write access to Backup Domain of necessary */ + 504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + 1576 .loc 1 504 8 + 1577 0860 4E4B ldr r3, .L158 + 1578 0862 DB69 ldr r3, [r3, #28] + 1579 0864 03F08053 and r3, r3, #268435456 + 1580 .loc 1 504 7 + 1581 0868 002B cmp r3, #0 + 1582 086a 16D1 bne .L95 + 1583 .LBB247: + 505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_PWR_CLK_ENABLE(); + 1584 .loc 1 506 7 + 1585 086c 4B4B ldr r3, .L158 + 1586 086e DB69 ldr r3, [r3, #28] + 1587 0870 4A4A ldr r2, .L158 + 1588 0872 43F08053 orr r3, r3, #268435456 + 1589 0876 D361 str r3, [r2, #28] + 1590 0878 484B ldr r3, .L158 + 1591 087a DB69 ldr r3, [r3, #28] + 1592 087c 03F08052 and r2, r3, #268435456 + 1593 0880 07F50073 add r3, r7, #512 + 1594 0884 A3F5FC73 sub r3, r3, #504 + 1595 0888 1A60 str r2, [r3] + 1596 088a 07F50073 add r3, r7, #512 + 1597 088e A3F5FC73 sub r3, r3, #504 + 1598 0892 1B68 ldr r3, [r3] + 1599 .LBE247: + 507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** pwrclkchanged = SET; + 1600 .loc 1 507 21 + 1601 0894 0123 movs r3, #1 + 1602 0896 87F8FF31 strb r3, [r7, #511] + 1603 .L95: + 508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 1604 .loc 1 510 8 + 1605 089a 424B ldr r3, .L158+8 + 1606 089c 1B68 ldr r3, [r3] + 1607 089e 03F48073 and r3, r3, #256 + 1608 .loc 1 510 7 + 1609 08a2 002B cmp r3, #0 + 1610 08a4 1AD1 bne .L96 + ARM GAS /tmp/ccSuWkwR.s page 57 + + + 511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Enable write access to Backup domain */ + 513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** SET_BIT(PWR->CR, PWR_CR_DBP); + 1611 .loc 1 513 7 + 1612 08a6 3F4B ldr r3, .L158+8 + 1613 08a8 1B68 ldr r3, [r3] + 1614 08aa 3E4A ldr r2, .L158+8 + 1615 08ac 43F48073 orr r3, r3, #256 + 1616 08b0 1360 str r3, [r2] + 514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Wait for Backup domain Write protection disable */ + 516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 1617 .loc 1 516 19 + 1618 08b2 FFF7FEFF bl HAL_GetTick + 1619 08b6 C7F8F801 str r0, [r7, #504] + 517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 1620 .loc 1 518 12 + 1621 08ba 09E0 b .L97 + 1622 .L98: + 519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 1623 .loc 1 520 13 + 1624 08bc FFF7FEFF bl HAL_GetTick + 1625 08c0 0246 mov r2, r0 + 1626 .loc 1 520 27 discriminator 1 + 1627 08c2 D7F8F831 ldr r3, [r7, #504] + 1628 08c6 D31A subs r3, r2, r3 + 1629 .loc 1 520 11 discriminator 1 + 1630 08c8 642B cmp r3, #100 + 1631 08ca 01D9 bls .L97 + 521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_TIMEOUT; + 1632 .loc 1 522 18 + 1633 08cc 0323 movs r3, #3 + 1634 08ce 9EE3 b .L15 + 1635 .L97: + 518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1636 .loc 1 518 13 + 1637 08d0 344B ldr r3, .L158+8 + 1638 08d2 1B68 ldr r3, [r3] + 1639 08d4 03F48073 and r3, r3, #256 + 1640 08d8 002B cmp r3, #0 + 1641 08da EFD0 beq .L98 + 1642 .L96: + 523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Set the new LSE configuration -----------------------------------------*/ + 528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + 1643 .loc 1 528 5 + 1644 08dc 07F50073 add r3, r7, #512 + 1645 08e0 A3F5FE73 sub r3, r3, #508 + 1646 08e4 1B68 ldr r3, [r3] + 1647 08e6 DB68 ldr r3, [r3, #12] + 1648 08e8 012B cmp r3, #1 + ARM GAS /tmp/ccSuWkwR.s page 58 + + + 1649 08ea 06D1 bne .L99 + 1650 .loc 1 528 5 is_stmt 0 discriminator 1 + 1651 08ec 2B4B ldr r3, .L158 + 1652 08ee 1B6A ldr r3, [r3, #32] + 1653 08f0 2A4A ldr r2, .L158 + 1654 08f2 43F00103 orr r3, r3, #1 + 1655 08f6 1362 str r3, [r2, #32] + 1656 08f8 35E0 b .L100 + 1657 .L99: + 1658 .loc 1 528 5 discriminator 2 + 1659 08fa 07F50073 add r3, r7, #512 + 1660 08fe A3F5FE73 sub r3, r3, #508 + 1661 0902 1B68 ldr r3, [r3] + 1662 0904 DB68 ldr r3, [r3, #12] + 1663 0906 002B cmp r3, #0 + 1664 0908 0CD1 bne .L101 + 1665 .loc 1 528 5 discriminator 3 + 1666 090a 244B ldr r3, .L158 + 1667 090c 1B6A ldr r3, [r3, #32] + 1668 090e 234A ldr r2, .L158 + 1669 0910 23F00103 bic r3, r3, #1 + 1670 0914 1362 str r3, [r2, #32] + 1671 0916 214B ldr r3, .L158 + 1672 0918 1B6A ldr r3, [r3, #32] + 1673 091a 204A ldr r2, .L158 + 1674 091c 23F00403 bic r3, r3, #4 + 1675 0920 1362 str r3, [r2, #32] + 1676 0922 20E0 b .L100 + 1677 .L101: + 1678 .loc 1 528 5 discriminator 4 + 1679 0924 07F50073 add r3, r7, #512 + 1680 0928 A3F5FE73 sub r3, r3, #508 + 1681 092c 1B68 ldr r3, [r3] + 1682 092e DB68 ldr r3, [r3, #12] + 1683 0930 052B cmp r3, #5 + 1684 0932 0CD1 bne .L102 + 1685 .loc 1 528 5 discriminator 5 + 1686 0934 194B ldr r3, .L158 + 1687 0936 1B6A ldr r3, [r3, #32] + 1688 0938 184A ldr r2, .L158 + 1689 093a 43F00403 orr r3, r3, #4 + 1690 093e 1362 str r3, [r2, #32] + 1691 0940 164B ldr r3, .L158 + 1692 0942 1B6A ldr r3, [r3, #32] + 1693 0944 154A ldr r2, .L158 + 1694 0946 43F00103 orr r3, r3, #1 + 1695 094a 1362 str r3, [r2, #32] + 1696 094c 0BE0 b .L100 + 1697 .L102: + 1698 .loc 1 528 5 discriminator 6 + 1699 094e 134B ldr r3, .L158 + 1700 0950 1B6A ldr r3, [r3, #32] + 1701 0952 124A ldr r2, .L158 + 1702 0954 23F00103 bic r3, r3, #1 + 1703 0958 1362 str r3, [r2, #32] + 1704 095a 104B ldr r3, .L158 + 1705 095c 1B6A ldr r3, [r3, #32] + ARM GAS /tmp/ccSuWkwR.s page 59 + + + 1706 095e 0F4A ldr r2, .L158 + 1707 0960 23F00403 bic r3, r3, #4 + 1708 0964 1362 str r3, [r2, #32] + 1709 .L100: + 529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the LSE State */ + 530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) + 1710 .loc 1 530 25 is_stmt 1 + 1711 0966 07F50073 add r3, r7, #512 + 1712 096a A3F5FE73 sub r3, r3, #508 + 1713 096e 1B68 ldr r3, [r3] + 1714 0970 DB68 ldr r3, [r3, #12] + 1715 .loc 1 530 7 + 1716 0972 002B cmp r3, #0 + 1717 0974 00F08780 beq .L103 + 531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get Start Tick */ + 533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 1718 .loc 1 533 19 + 1719 0978 FFF7FEFF bl HAL_GetTick + 1720 097c C7F8F801 str r0, [r7, #504] + 534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Wait till LSE is ready */ + 536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 1721 .loc 1 536 12 + 1722 0980 12E0 b .L104 + 1723 .L111: + 537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 1724 .loc 1 538 13 + 1725 0982 FFF7FEFF bl HAL_GetTick + 1726 0986 0246 mov r2, r0 + 1727 .loc 1 538 27 discriminator 1 + 1728 0988 D7F8F831 ldr r3, [r7, #504] + 1729 098c D31A subs r3, r2, r3 + 1730 .loc 1 538 11 discriminator 1 + 1731 098e 41F28832 movw r2, #5000 + 1732 0992 9342 cmp r3, r2 + 1733 0994 08D9 bls .L104 + 539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_TIMEOUT; + 1734 .loc 1 540 18 + 1735 0996 0323 movs r3, #3 + 1736 0998 39E3 b .L15 + 1737 .L159: + 1738 099a 00BF .align 2 + 1739 .L158: + 1740 099c 00100240 .word 1073876992 + 1741 09a0 20819010 .word 277905696 + 1742 09a4 00700040 .word 1073770496 + 1743 .L104: + 1744 09a8 07F50073 add r3, r7, #512 + 1745 09ac A3F5A073 sub r3, r3, #320 + 1746 09b0 0222 movs r2, #2 + 1747 09b2 1A60 str r2, [r3] + 1748 .LBB248: + 1749 .LBB249: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + ARM GAS /tmp/ccSuWkwR.s page 60 + + + 1750 .loc 2 988 4 + 1751 09b4 07F50073 add r3, r7, #512 + 1752 09b8 A3F5A073 sub r3, r3, #320 + 1753 09bc 1B68 ldr r3, [r3] + 1754 .syntax unified + 1755 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1756 09be 93FAA3F2 rbit r2, r3 + 1757 @ 0 "" 2 + 1758 .thumb + 1759 .syntax unified + 1760 09c2 07F50073 add r3, r7, #512 + 1761 09c6 A3F5A273 sub r3, r3, #324 + 1762 09ca 1A60 str r2, [r3] + 1763 09cc 07F50073 add r3, r7, #512 + 1764 09d0 A3F5A473 sub r3, r3, #328 + 1765 09d4 0222 movs r2, #2 + 1766 09d6 1A60 str r2, [r3] + 1767 .LBE249: + 1768 .LBE248: + 1769 .LBB250: + 1770 .LBB251: + 1771 09d8 07F50073 add r3, r7, #512 + 1772 09dc A3F5A473 sub r3, r3, #328 + 1773 09e0 1B68 ldr r3, [r3] + 1774 .syntax unified + 1775 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1776 09e2 93FAA3F2 rbit r2, r3 + 1777 @ 0 "" 2 + 1778 .thumb + 1779 .syntax unified + 1780 09e6 07F50073 add r3, r7, #512 + 1781 09ea A3F5A673 sub r3, r3, #332 + 1782 09ee 1A60 str r2, [r3] + 1783 .loc 2 1001 10 + 1784 09f0 07F50073 add r3, r7, #512 + 1785 09f4 A3F5A673 sub r3, r3, #332 + 1786 09f8 1B68 ldr r3, [r3] + 1787 .LBE251: + 1788 .LBE250: + 536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1789 .loc 1 536 13 discriminator 1 + 1790 09fa B3FA83F3 clz r3, r3 + 536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1791 .loc 1 536 13 is_stmt 0 discriminator 2 + 1792 09fe DBB2 uxtb r3, r3 + 1793 0a00 23F05F03 bic r3, r3, #95 + 1794 0a04 DBB2 uxtb r3, r3 + 1795 0a06 002B cmp r3, #0 + 1796 0a08 02D1 bne .L107 + 536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1797 .loc 1 536 13 discriminator 4 + 1798 0a0a 984B ldr r3, .L160 + 1799 0a0c 1B6A ldr r3, [r3, #32] + 1800 0a0e 13E0 b .L108 + 1801 .L107: + 1802 0a10 07F50073 add r3, r7, #512 + 1803 0a14 A3F5A873 sub r3, r3, #336 + ARM GAS /tmp/ccSuWkwR.s page 61 + + + 1804 0a18 0222 movs r2, #2 + 1805 0a1a 1A60 str r2, [r3] + 1806 .LBB252: + 1807 .LBB253: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 1808 .loc 2 988 4 is_stmt 1 + 1809 0a1c 07F50073 add r3, r7, #512 + 1810 0a20 A3F5A873 sub r3, r3, #336 + 1811 0a24 1B68 ldr r3, [r3] + 1812 .syntax unified + 1813 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1814 0a26 93FAA3F2 rbit r2, r3 + 1815 @ 0 "" 2 + 1816 .thumb + 1817 .syntax unified + 1818 0a2a 07F50073 add r3, r7, #512 + 1819 0a2e A3F5AA73 sub r3, r3, #340 + 1820 0a32 1A60 str r2, [r3] + 1821 .LBE253: + 1822 .LBE252: + 536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1823 .loc 1 536 13 discriminator 8 + 1824 0a34 8D4B ldr r3, .L160 + 1825 0a36 5B6A ldr r3, [r3, #36] + 1826 .L108: + 1827 0a38 07F50072 add r2, r7, #512 + 1828 0a3c A2F5AC72 sub r2, r2, #344 + 1829 0a40 0221 movs r1, #2 + 1830 0a42 1160 str r1, [r2] + 1831 .LBB254: + 1832 .LBB255: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 1833 .loc 2 988 4 + 1834 0a44 07F50072 add r2, r7, #512 + 1835 0a48 A2F5AC72 sub r2, r2, #344 + 1836 0a4c 1268 ldr r2, [r2] + 1837 .syntax unified + 1838 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1839 0a4e 92FAA2F1 rbit r1, r2 + 1840 @ 0 "" 2 + 1841 .thumb + 1842 .syntax unified + 1843 0a52 07F50072 add r2, r7, #512 + 1844 0a56 A2F5AE72 sub r2, r2, #348 + 1845 0a5a 1160 str r1, [r2] + 1846 .loc 2 1001 10 + 1847 0a5c 07F50072 add r2, r7, #512 + 1848 0a60 A2F5AE72 sub r2, r2, #348 + 1849 0a64 1268 ldr r2, [r2] + 1850 .LBE255: + 1851 .LBE254: + 536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1852 .loc 1 536 13 discriminator 1 + 1853 0a66 B2FA82F2 clz r2, r2 + 536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1854 .loc 1 536 13 is_stmt 0 discriminator 2 + 1855 0a6a D2B2 uxtb r2, r2 + ARM GAS /tmp/ccSuWkwR.s page 62 + + + 1856 0a6c 42F04002 orr r2, r2, #64 + 1857 0a70 D2B2 uxtb r2, r2 + 1858 0a72 02F01F02 and r2, r2, #31 + 1859 0a76 0121 movs r1, #1 + 1860 0a78 01FA02F2 lsl r2, r1, r2 + 1861 0a7c 1340 ands r3, r3, r2 + 536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1862 .loc 1 536 49 is_stmt 1 discriminator 2 + 1863 0a7e 002B cmp r3, #0 + 1864 0a80 3FF47FAF beq .L111 + 1865 0a84 7DE0 b .L112 + 1866 .L103: + 541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else + 545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get Start Tick */ + 547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 1867 .loc 1 547 19 + 1868 0a86 FFF7FEFF bl HAL_GetTick + 1869 0a8a C7F8F801 str r0, [r7, #504] + 548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Wait till LSE is disabled */ + 550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + 1870 .loc 1 550 12 + 1871 0a8e 0BE0 b .L113 + 1872 .L120: + 551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 1873 .loc 1 552 13 + 1874 0a90 FFF7FEFF bl HAL_GetTick + 1875 0a94 0246 mov r2, r0 + 1876 .loc 1 552 27 discriminator 1 + 1877 0a96 D7F8F831 ldr r3, [r7, #504] + 1878 0a9a D31A subs r3, r2, r3 + 1879 .loc 1 552 11 discriminator 1 + 1880 0a9c 41F28832 movw r2, #5000 + 1881 0aa0 9342 cmp r3, r2 + 1882 0aa2 01D9 bls .L113 + 553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_TIMEOUT; + 1883 .loc 1 554 18 + 1884 0aa4 0323 movs r3, #3 + 1885 0aa6 B2E2 b .L15 + 1886 .L113: + 1887 0aa8 07F50073 add r3, r7, #512 + 1888 0aac A3F5B073 sub r3, r3, #352 + 1889 0ab0 0222 movs r2, #2 + 1890 0ab2 1A60 str r2, [r3] + 1891 .LBB256: + 1892 .LBB257: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 1893 .loc 2 988 4 + 1894 0ab4 07F50073 add r3, r7, #512 + 1895 0ab8 A3F5B073 sub r3, r3, #352 + 1896 0abc 1B68 ldr r3, [r3] + ARM GAS /tmp/ccSuWkwR.s page 63 + + + 1897 .syntax unified + 1898 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1899 0abe 93FAA3F2 rbit r2, r3 + 1900 @ 0 "" 2 + 1901 .thumb + 1902 .syntax unified + 1903 0ac2 07F50073 add r3, r7, #512 + 1904 0ac6 A3F5B273 sub r3, r3, #356 + 1905 0aca 1A60 str r2, [r3] + 1906 0acc 07F50073 add r3, r7, #512 + 1907 0ad0 A3F5B473 sub r3, r3, #360 + 1908 0ad4 0222 movs r2, #2 + 1909 0ad6 1A60 str r2, [r3] + 1910 .LBE257: + 1911 .LBE256: + 1912 .LBB258: + 1913 .LBB259: + 1914 0ad8 07F50073 add r3, r7, #512 + 1915 0adc A3F5B473 sub r3, r3, #360 + 1916 0ae0 1B68 ldr r3, [r3] + 1917 .syntax unified + 1918 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1919 0ae2 93FAA3F2 rbit r2, r3 + 1920 @ 0 "" 2 + 1921 .thumb + 1922 .syntax unified + 1923 0ae6 07F50073 add r3, r7, #512 + 1924 0aea A3F5B673 sub r3, r3, #364 + 1925 0aee 1A60 str r2, [r3] + 1926 .loc 2 1001 10 + 1927 0af0 07F50073 add r3, r7, #512 + 1928 0af4 A3F5B673 sub r3, r3, #364 + 1929 0af8 1B68 ldr r3, [r3] + 1930 .LBE259: + 1931 .LBE258: + 550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1932 .loc 1 550 13 discriminator 1 + 1933 0afa B3FA83F3 clz r3, r3 + 550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1934 .loc 1 550 13 is_stmt 0 discriminator 2 + 1935 0afe DBB2 uxtb r3, r3 + 1936 0b00 23F05F03 bic r3, r3, #95 + 1937 0b04 DBB2 uxtb r3, r3 + 1938 0b06 002B cmp r3, #0 + 1939 0b08 02D1 bne .L116 + 550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1940 .loc 1 550 13 discriminator 4 + 1941 0b0a 584B ldr r3, .L160 + 1942 0b0c 1B6A ldr r3, [r3, #32] + 1943 0b0e 13E0 b .L117 + 1944 .L116: + 1945 0b10 07F50073 add r3, r7, #512 + 1946 0b14 A3F5B873 sub r3, r3, #368 + 1947 0b18 0222 movs r2, #2 + 1948 0b1a 1A60 str r2, [r3] + 1949 .LBB260: + 1950 .LBB261: + ARM GAS /tmp/ccSuWkwR.s page 64 + + + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 1951 .loc 2 988 4 is_stmt 1 + 1952 0b1c 07F50073 add r3, r7, #512 + 1953 0b20 A3F5B873 sub r3, r3, #368 + 1954 0b24 1B68 ldr r3, [r3] + 1955 .syntax unified + 1956 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1957 0b26 93FAA3F2 rbit r2, r3 + 1958 @ 0 "" 2 + 1959 .thumb + 1960 .syntax unified + 1961 0b2a 07F50073 add r3, r7, #512 + 1962 0b2e A3F5BA73 sub r3, r3, #372 + 1963 0b32 1A60 str r2, [r3] + 1964 .LBE261: + 1965 .LBE260: + 550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1966 .loc 1 550 13 discriminator 8 + 1967 0b34 4D4B ldr r3, .L160 + 1968 0b36 5B6A ldr r3, [r3, #36] + 1969 .L117: + 1970 0b38 07F50072 add r2, r7, #512 + 1971 0b3c A2F5BC72 sub r2, r2, #376 + 1972 0b40 0221 movs r1, #2 + 1973 0b42 1160 str r1, [r2] + 1974 .LBB262: + 1975 .LBB263: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 1976 .loc 2 988 4 + 1977 0b44 07F50072 add r2, r7, #512 + 1978 0b48 A2F5BC72 sub r2, r2, #376 + 1979 0b4c 1268 ldr r2, [r2] + 1980 .syntax unified + 1981 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1982 0b4e 92FAA2F1 rbit r1, r2 + 1983 @ 0 "" 2 + 1984 .thumb + 1985 .syntax unified + 1986 0b52 07F50072 add r2, r7, #512 + 1987 0b56 A2F5BE72 sub r2, r2, #380 + 1988 0b5a 1160 str r1, [r2] + 1989 .loc 2 1001 10 + 1990 0b5c 07F50072 add r2, r7, #512 + 1991 0b60 A2F5BE72 sub r2, r2, #380 + 1992 0b64 1268 ldr r2, [r2] + 1993 .LBE263: + 1994 .LBE262: + 550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1995 .loc 1 550 13 discriminator 1 + 1996 0b66 B2FA82F2 clz r2, r2 + 550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 1997 .loc 1 550 13 is_stmt 0 discriminator 2 + 1998 0b6a D2B2 uxtb r2, r2 + 1999 0b6c 42F04002 orr r2, r2, #64 + 2000 0b70 D2B2 uxtb r2, r2 + 2001 0b72 02F01F02 and r2, r2, #31 + 2002 0b76 0121 movs r1, #1 + ARM GAS /tmp/ccSuWkwR.s page 65 + + + 2003 0b78 01FA02F2 lsl r2, r1, r2 + 2004 0b7c 1340 ands r3, r3, r2 + 550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2005 .loc 1 550 49 is_stmt 1 discriminator 2 + 2006 0b7e 002B cmp r3, #0 + 2007 0b80 86D1 bne .L120 + 2008 .L112: + 555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Require to disable power clock if necessary */ + 560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(pwrclkchanged == SET) + 2009 .loc 1 560 7 + 2010 0b82 97F8FF31 ldrb r3, [r7, #511] @ zero_extendqisi2 + 2011 0b86 012B cmp r3, #1 + 2012 0b88 05D1 bne .L94 + 561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_PWR_CLK_DISABLE(); + 2013 .loc 1 562 7 + 2014 0b8a 384B ldr r3, .L160 + 2015 0b8c DB69 ldr r3, [r3, #28] + 2016 0b8e 374A ldr r2, .L160 + 2017 0b90 23F08053 bic r3, r3, #268435456 + 2018 0b94 D361 str r3, [r2, #28] + 2019 .L94: + 2020 .LBE246: + 563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /*-------------------------------- PLL Configuration -----------------------*/ + 567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the parameters */ + 568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + 569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + 2021 .loc 1 569 30 + 2022 0b96 07F50073 add r3, r7, #512 + 2023 0b9a A3F5FE73 sub r3, r3, #508 + 2024 0b9e 1B68 ldr r3, [r3] + 2025 0ba0 DB69 ldr r3, [r3, #28] + 2026 .loc 1 569 6 + 2027 0ba2 002B cmp r3, #0 + 2028 0ba4 00F03282 beq .L121 + 570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check if the PLL is used as system clock or not */ + 572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 2029 .loc 1 572 8 + 2030 0ba8 304B ldr r3, .L160 + 2031 0baa 5B68 ldr r3, [r3, #4] + 2032 0bac 03F00C03 and r3, r3, #12 + 2033 .loc 1 572 7 + 2034 0bb0 082B cmp r3, #8 + 2035 0bb2 00F00182 beq .L122 + 573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + 2036 .loc 1 574 33 + 2037 0bb6 07F50073 add r3, r7, #512 + 2038 0bba A3F5FE73 sub r3, r3, #508 + ARM GAS /tmp/ccSuWkwR.s page 66 + + + 2039 0bbe 1B68 ldr r3, [r3] + 2040 0bc0 DB69 ldr r3, [r3, #28] + 2041 .loc 1 574 9 + 2042 0bc2 022B cmp r3, #2 + 2043 0bc4 40F05781 bne .L123 + 2044 0bc8 07F50073 add r3, r7, #512 + 2045 0bcc A3F5C073 sub r3, r3, #384 + 2046 0bd0 4FF08072 mov r2, #16777216 + 2047 0bd4 1A60 str r2, [r3] + 2048 .LBB264: + 2049 .LBB265: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 2050 .loc 2 988 4 + 2051 0bd6 07F50073 add r3, r7, #512 + 2052 0bda A3F5C073 sub r3, r3, #384 + 2053 0bde 1B68 ldr r3, [r3] + 2054 .syntax unified + 2055 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2056 0be0 93FAA3F2 rbit r2, r3 + 2057 @ 0 "" 2 + 2058 .thumb + 2059 .syntax unified + 2060 0be4 07F50073 add r3, r7, #512 + 2061 0be8 A3F5C273 sub r3, r3, #388 + 2062 0bec 1A60 str r2, [r3] + 2063 .loc 2 1001 10 + 2064 0bee 07F50073 add r3, r7, #512 + 2065 0bf2 A3F5C273 sub r3, r3, #388 + 2066 0bf6 1B68 ldr r3, [r3] + 2067 .LBE265: + 2068 .LBE264: + 575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the parameters */ + 577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + 578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); + 579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) + 580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV)); + 581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #endif + 582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Disable the main PLL. */ + 584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_PLL_DISABLE(); + 2069 .loc 1 584 9 discriminator 1 + 2070 0bf8 B3FA83F3 clz r3, r3 + 2071 .loc 1 584 9 is_stmt 0 discriminator 2 + 2072 0bfc DBB2 uxtb r3, r3 + 2073 0bfe 03F18453 add r3, r3, #276824064 + 2074 0c02 03F58413 add r3, r3, #1081344 + 2075 0c06 9B00 lsls r3, r3, #2 + 2076 0c08 1A46 mov r2, r3 + 2077 0c0a 0023 movs r3, #0 + 2078 0c0c 1360 str r3, [r2] + 585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get Start Tick */ + 587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 2079 .loc 1 587 21 is_stmt 1 + 2080 0c0e FFF7FEFF bl HAL_GetTick + 2081 0c12 C7F8F801 str r0, [r7, #504] + ARM GAS /tmp/ccSuWkwR.s page 67 + + + 588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Wait till PLL is disabled */ + 590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 2082 .loc 1 590 14 + 2083 0c16 09E0 b .L125 + 2084 .L132: + 591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 2085 .loc 1 592 15 + 2086 0c18 FFF7FEFF bl HAL_GetTick + 2087 0c1c 0246 mov r2, r0 + 2088 .loc 1 592 29 discriminator 1 + 2089 0c1e D7F8F831 ldr r3, [r7, #504] + 2090 0c22 D31A subs r3, r2, r3 + 2091 .loc 1 592 13 discriminator 1 + 2092 0c24 022B cmp r3, #2 + 2093 0c26 01D9 bls .L125 + 593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_TIMEOUT; + 2094 .loc 1 594 20 + 2095 0c28 0323 movs r3, #3 + 2096 0c2a F0E1 b .L15 + 2097 .L125: + 2098 0c2c 07F50073 add r3, r7, #512 + 2099 0c30 A3F5C473 sub r3, r3, #392 + 2100 0c34 4FF00072 mov r2, #33554432 + 2101 0c38 1A60 str r2, [r3] + 2102 .LBB266: + 2103 .LBB267: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 2104 .loc 2 988 4 + 2105 0c3a 07F50073 add r3, r7, #512 + 2106 0c3e A3F5C473 sub r3, r3, #392 + 2107 0c42 1B68 ldr r3, [r3] + 2108 .syntax unified + 2109 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2110 0c44 93FAA3F2 rbit r2, r3 + 2111 @ 0 "" 2 + 2112 .thumb + 2113 .syntax unified + 2114 0c48 07F50073 add r3, r7, #512 + 2115 0c4c A3F5C673 sub r3, r3, #396 + 2116 0c50 1A60 str r2, [r3] + 2117 .loc 2 1001 10 + 2118 0c52 07F50073 add r3, r7, #512 + 2119 0c56 A3F5C673 sub r3, r3, #396 + 2120 0c5a 1B68 ldr r3, [r3] + 2121 .LBE267: + 2122 .LBE266: + 590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2123 .loc 1 590 15 discriminator 1 + 2124 0c5c B3FA83F3 clz r3, r3 + 590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2125 .loc 1 590 15 is_stmt 0 discriminator 2 + 2126 0c60 DBB2 uxtb r3, r3 + 2127 0c62 3F2B cmp r3, #63 + 2128 0c64 04D8 bhi .L127 + ARM GAS /tmp/ccSuWkwR.s page 68 + + + 590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2129 .loc 1 590 15 discriminator 1 + 2130 0c66 014B ldr r3, .L160 + 2131 0c68 1B68 ldr r3, [r3] + 2132 0c6a 29E0 b .L128 + 2133 .L161: + 2134 .align 2 + 2135 .L160: + 2136 0c6c 00100240 .word 1073876992 + 2137 .L127: + 2138 0c70 07F50073 add r3, r7, #512 + 2139 0c74 A3F5C873 sub r3, r3, #400 + 2140 0c78 4FF00072 mov r2, #33554432 + 2141 0c7c 1A60 str r2, [r3] + 2142 .LBB268: + 2143 .LBB269: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 2144 .loc 2 988 4 is_stmt 1 + 2145 0c7e 07F50073 add r3, r7, #512 + 2146 0c82 A3F5C873 sub r3, r3, #400 + 2147 0c86 1B68 ldr r3, [r3] + 2148 .syntax unified + 2149 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2150 0c88 93FAA3F2 rbit r2, r3 + 2151 @ 0 "" 2 + 2152 .thumb + 2153 .syntax unified + 2154 0c8c 07F50073 add r3, r7, #512 + 2155 0c90 A3F5CA73 sub r3, r3, #404 + 2156 0c94 1A60 str r2, [r3] + 2157 0c96 07F50073 add r3, r7, #512 + 2158 0c9a A3F5CC73 sub r3, r3, #408 + 2159 0c9e 4FF00072 mov r2, #33554432 + 2160 0ca2 1A60 str r2, [r3] + 2161 .LBE269: + 2162 .LBE268: + 2163 .LBB270: + 2164 .LBB271: + 2165 0ca4 07F50073 add r3, r7, #512 + 2166 0ca8 A3F5CC73 sub r3, r3, #408 + 2167 0cac 1B68 ldr r3, [r3] + 2168 .syntax unified + 2169 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2170 0cae 93FAA3F2 rbit r2, r3 + 2171 @ 0 "" 2 + 2172 .thumb + 2173 .syntax unified + 2174 0cb2 07F50073 add r3, r7, #512 + 2175 0cb6 A3F5CE73 sub r3, r3, #412 + 2176 0cba 1A60 str r2, [r3] + 2177 .LBE271: + 2178 .LBE270: + 590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2179 .loc 1 590 15 discriminator 8 + 2180 0cbc C34B ldr r3, .L162 + 2181 0cbe 5B6A ldr r3, [r3, #36] + 2182 .L128: + ARM GAS /tmp/ccSuWkwR.s page 69 + + + 2183 0cc0 07F50072 add r2, r7, #512 + 2184 0cc4 A2F5D072 sub r2, r2, #416 + 2185 0cc8 4FF00071 mov r1, #33554432 + 2186 0ccc 1160 str r1, [r2] + 2187 .LBB272: + 2188 .LBB273: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 2189 .loc 2 988 4 + 2190 0cce 07F50072 add r2, r7, #512 + 2191 0cd2 A2F5D072 sub r2, r2, #416 + 2192 0cd6 1268 ldr r2, [r2] + 2193 .syntax unified + 2194 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2195 0cd8 92FAA2F1 rbit r1, r2 + 2196 @ 0 "" 2 + 2197 .thumb + 2198 .syntax unified + 2199 0cdc 07F50072 add r2, r7, #512 + 2200 0ce0 A2F5D272 sub r2, r2, #420 + 2201 0ce4 1160 str r1, [r2] + 2202 .loc 2 1001 10 + 2203 0ce6 07F50072 add r2, r7, #512 + 2204 0cea A2F5D272 sub r2, r2, #420 + 2205 0cee 1268 ldr r2, [r2] + 2206 .LBE273: + 2207 .LBE272: + 590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2208 .loc 1 590 15 discriminator 1 + 2209 0cf0 B2FA82F2 clz r2, r2 + 590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2210 .loc 1 590 15 is_stmt 0 discriminator 2 + 2211 0cf4 D2B2 uxtb r2, r2 + 2212 0cf6 42F02002 orr r2, r2, #32 + 2213 0cfa D2B2 uxtb r2, r2 + 2214 0cfc 02F01F02 and r2, r2, #31 + 2215 0d00 0121 movs r1, #1 + 2216 0d02 01FA02F2 lsl r2, r1, r2 + 2217 0d06 1340 ands r3, r3, r2 + 590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2218 .loc 1 590 52 is_stmt 1 discriminator 2 + 2219 0d08 002B cmp r3, #0 + 2220 0d0a 85D1 bne .L132 + 595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) + 599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Configure the main PLL clock source, predivider and multiplication factor. */ + 600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + 601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PREDIV, + 602:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLMUL); + 603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #else + 604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Configure the main PLL clock source and multiplication factor. */ + 605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + 2221 .loc 1 605 7 + 2222 0d0c AF4B ldr r3, .L162 + 2223 0d0e 5B68 ldr r3, [r3, #4] + 2224 0d10 23F47412 bic r2, r3, #3997696 + ARM GAS /tmp/ccSuWkwR.s page 70 + + + 2225 0d14 07F50073 add r3, r7, #512 + 2226 0d18 A3F5FE73 sub r3, r3, #508 + 2227 0d1c 1B68 ldr r3, [r3] + 2228 0d1e 596A ldr r1, [r3, #36] + 2229 0d20 07F50073 add r3, r7, #512 + 2230 0d24 A3F5FE73 sub r3, r3, #508 + 2231 0d28 1B68 ldr r3, [r3] + 2232 0d2a 1B6A ldr r3, [r3, #32] + 2233 0d2c 0B43 orrs r3, r3, r1 + 2234 0d2e A749 ldr r1, .L162 + 2235 0d30 1343 orrs r3, r3, r2 + 2236 0d32 4B60 str r3, [r1, #4] + 2237 0d34 07F50073 add r3, r7, #512 + 2238 0d38 A3F5D473 sub r3, r3, #424 + 2239 0d3c 4FF08072 mov r2, #16777216 + 2240 0d40 1A60 str r2, [r3] + 2241 .LBB274: + 2242 .LBB275: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 2243 .loc 2 988 4 + 2244 0d42 07F50073 add r3, r7, #512 + 2245 0d46 A3F5D473 sub r3, r3, #424 + 2246 0d4a 1B68 ldr r3, [r3] + 2247 .syntax unified + 2248 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2249 0d4c 93FAA3F2 rbit r2, r3 + 2250 @ 0 "" 2 + 2251 .thumb + 2252 .syntax unified + 2253 0d50 07F50073 add r3, r7, #512 + 2254 0d54 A3F5D673 sub r3, r3, #428 + 2255 0d58 1A60 str r2, [r3] + 2256 .loc 2 1001 10 + 2257 0d5a 07F50073 add r3, r7, #512 + 2258 0d5e A3F5D673 sub r3, r3, #428 + 2259 0d62 1B68 ldr r3, [r3] + 2260 .LBE275: + 2261 .LBE274: + 606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLMUL); + 607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */ + 608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Enable the main PLL. */ + 609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_PLL_ENABLE(); + 2262 .loc 1 609 9 discriminator 1 + 2263 0d64 B3FA83F3 clz r3, r3 + 2264 .loc 1 609 9 is_stmt 0 discriminator 2 + 2265 0d68 DBB2 uxtb r3, r3 + 2266 0d6a 03F18453 add r3, r3, #276824064 + 2267 0d6e 03F58413 add r3, r3, #1081344 + 2268 0d72 9B00 lsls r3, r3, #2 + 2269 0d74 1A46 mov r2, r3 + 2270 0d76 0123 movs r3, #1 + 2271 0d78 1360 str r3, [r2] + 610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get Start Tick */ + 612:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 2272 .loc 1 612 21 is_stmt 1 + 2273 0d7a FFF7FEFF bl HAL_GetTick + ARM GAS /tmp/ccSuWkwR.s page 71 + + + 2274 0d7e C7F8F801 str r0, [r7, #504] + 613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Wait till PLL is ready */ + 615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 2275 .loc 1 615 14 + 2276 0d82 09E0 b .L134 + 2277 .L141: + 616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 2278 .loc 1 617 15 + 2279 0d84 FFF7FEFF bl HAL_GetTick + 2280 0d88 0246 mov r2, r0 + 2281 .loc 1 617 29 discriminator 1 + 2282 0d8a D7F8F831 ldr r3, [r7, #504] + 2283 0d8e D31A subs r3, r2, r3 + 2284 .loc 1 617 13 discriminator 1 + 2285 0d90 022B cmp r3, #2 + 2286 0d92 01D9 bls .L134 + 618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_TIMEOUT; + 2287 .loc 1 619 20 + 2288 0d94 0323 movs r3, #3 + 2289 0d96 3AE1 b .L15 + 2290 .L134: + 2291 0d98 07F50073 add r3, r7, #512 + 2292 0d9c A3F5D873 sub r3, r3, #432 + 2293 0da0 4FF00072 mov r2, #33554432 + 2294 0da4 1A60 str r2, [r3] + 2295 .LBB276: + 2296 .LBB277: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 2297 .loc 2 988 4 + 2298 0da6 07F50073 add r3, r7, #512 + 2299 0daa A3F5D873 sub r3, r3, #432 + 2300 0dae 1B68 ldr r3, [r3] + 2301 .syntax unified + 2302 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2303 0db0 93FAA3F2 rbit r2, r3 + 2304 @ 0 "" 2 + 2305 .thumb + 2306 .syntax unified + 2307 0db4 07F50073 add r3, r7, #512 + 2308 0db8 A3F5DA73 sub r3, r3, #436 + 2309 0dbc 1A60 str r2, [r3] + 2310 .loc 2 1001 10 + 2311 0dbe 07F50073 add r3, r7, #512 + 2312 0dc2 A3F5DA73 sub r3, r3, #436 + 2313 0dc6 1B68 ldr r3, [r3] + 2314 .LBE277: + 2315 .LBE276: + 615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2316 .loc 1 615 15 discriminator 1 + 2317 0dc8 B3FA83F3 clz r3, r3 + 615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2318 .loc 1 615 15 is_stmt 0 discriminator 2 + 2319 0dcc DBB2 uxtb r3, r3 + 2320 0dce 3F2B cmp r3, #63 + ARM GAS /tmp/ccSuWkwR.s page 72 + + + 2321 0dd0 02D8 bhi .L136 + 615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2322 .loc 1 615 15 discriminator 1 + 2323 0dd2 7E4B ldr r3, .L162 + 2324 0dd4 1B68 ldr r3, [r3] + 2325 0dd6 27E0 b .L137 + 2326 .L136: + 2327 0dd8 07F50073 add r3, r7, #512 + 2328 0ddc A3F5DC73 sub r3, r3, #440 + 2329 0de0 4FF00072 mov r2, #33554432 + 2330 0de4 1A60 str r2, [r3] + 2331 .LBB278: + 2332 .LBB279: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 2333 .loc 2 988 4 is_stmt 1 + 2334 0de6 07F50073 add r3, r7, #512 + 2335 0dea A3F5DC73 sub r3, r3, #440 + 2336 0dee 1B68 ldr r3, [r3] + 2337 .syntax unified + 2338 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2339 0df0 93FAA3F2 rbit r2, r3 + 2340 @ 0 "" 2 + 2341 .thumb + 2342 .syntax unified + 2343 0df4 07F50073 add r3, r7, #512 + 2344 0df8 A3F5DE73 sub r3, r3, #444 + 2345 0dfc 1A60 str r2, [r3] + 2346 0dfe 07F50073 add r3, r7, #512 + 2347 0e02 A3F5E073 sub r3, r3, #448 + 2348 0e06 4FF00072 mov r2, #33554432 + 2349 0e0a 1A60 str r2, [r3] + 2350 .LBE279: + 2351 .LBE278: + 2352 .LBB280: + 2353 .LBB281: + 2354 0e0c 07F50073 add r3, r7, #512 + 2355 0e10 A3F5E073 sub r3, r3, #448 + 2356 0e14 1B68 ldr r3, [r3] + 2357 .syntax unified + 2358 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2359 0e16 93FAA3F2 rbit r2, r3 + 2360 @ 0 "" 2 + 2361 .thumb + 2362 .syntax unified + 2363 0e1a 07F50073 add r3, r7, #512 + 2364 0e1e A3F5E273 sub r3, r3, #452 + 2365 0e22 1A60 str r2, [r3] + 2366 .LBE281: + 2367 .LBE280: + 615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2368 .loc 1 615 15 discriminator 8 + 2369 0e24 694B ldr r3, .L162 + 2370 0e26 5B6A ldr r3, [r3, #36] + 2371 .L137: + 2372 0e28 07F50072 add r2, r7, #512 + 2373 0e2c A2F5E472 sub r2, r2, #456 + 2374 0e30 4FF00071 mov r1, #33554432 + ARM GAS /tmp/ccSuWkwR.s page 73 + + + 2375 0e34 1160 str r1, [r2] + 2376 .LBB282: + 2377 .LBB283: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 2378 .loc 2 988 4 + 2379 0e36 07F50072 add r2, r7, #512 + 2380 0e3a A2F5E472 sub r2, r2, #456 + 2381 0e3e 1268 ldr r2, [r2] + 2382 .syntax unified + 2383 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2384 0e40 92FAA2F1 rbit r1, r2 + 2385 @ 0 "" 2 + 2386 .thumb + 2387 .syntax unified + 2388 0e44 07F50072 add r2, r7, #512 + 2389 0e48 A2F5E672 sub r2, r2, #460 + 2390 0e4c 1160 str r1, [r2] + 2391 .loc 2 1001 10 + 2392 0e4e 07F50072 add r2, r7, #512 + 2393 0e52 A2F5E672 sub r2, r2, #460 + 2394 0e56 1268 ldr r2, [r2] + 2395 .LBE283: + 2396 .LBE282: + 615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2397 .loc 1 615 15 discriminator 1 + 2398 0e58 B2FA82F2 clz r2, r2 + 615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2399 .loc 1 615 15 is_stmt 0 discriminator 2 + 2400 0e5c D2B2 uxtb r2, r2 + 2401 0e5e 42F02002 orr r2, r2, #32 + 2402 0e62 D2B2 uxtb r2, r2 + 2403 0e64 02F01F02 and r2, r2, #31 + 2404 0e68 0121 movs r1, #1 + 2405 0e6a 01FA02F2 lsl r2, r1, r2 + 2406 0e6e 1340 ands r3, r3, r2 + 615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2407 .loc 1 615 52 is_stmt 1 discriminator 2 + 2408 0e70 002B cmp r3, #0 + 2409 0e72 87D0 beq .L141 + 2410 0e74 CAE0 b .L121 + 2411 .L123: + 2412 0e76 07F50073 add r3, r7, #512 + 2413 0e7a A3F5E873 sub r3, r3, #464 + 2414 0e7e 4FF08072 mov r2, #16777216 + 2415 0e82 1A60 str r2, [r3] + 2416 .LBB284: + 2417 .LBB285: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 2418 .loc 2 988 4 + 2419 0e84 07F50073 add r3, r7, #512 + 2420 0e88 A3F5E873 sub r3, r3, #464 + 2421 0e8c 1B68 ldr r3, [r3] + 2422 .syntax unified + 2423 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2424 0e8e 93FAA3F2 rbit r2, r3 + 2425 @ 0 "" 2 + 2426 .thumb + ARM GAS /tmp/ccSuWkwR.s page 74 + + + 2427 .syntax unified + 2428 0e92 07F50073 add r3, r7, #512 + 2429 0e96 A3F5EA73 sub r3, r3, #468 + 2430 0e9a 1A60 str r2, [r3] + 2431 .loc 2 1001 10 + 2432 0e9c 07F50073 add r3, r7, #512 + 2433 0ea0 A3F5EA73 sub r3, r3, #468 + 2434 0ea4 1B68 ldr r3, [r3] + 2435 .LBE285: + 2436 .LBE284: + 620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else + 624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Disable the main PLL. */ + 626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_PLL_DISABLE(); + 2437 .loc 1 626 9 discriminator 1 + 2438 0ea6 B3FA83F3 clz r3, r3 + 2439 .loc 1 626 9 is_stmt 0 discriminator 2 + 2440 0eaa DBB2 uxtb r3, r3 + 2441 0eac 03F18453 add r3, r3, #276824064 + 2442 0eb0 03F58413 add r3, r3, #1081344 + 2443 0eb4 9B00 lsls r3, r3, #2 + 2444 0eb6 1A46 mov r2, r3 + 2445 0eb8 0023 movs r3, #0 + 2446 0eba 1360 str r3, [r2] + 627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get Start Tick */ + 629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 2447 .loc 1 629 21 is_stmt 1 + 2448 0ebc FFF7FEFF bl HAL_GetTick + 2449 0ec0 C7F8F801 str r0, [r7, #504] + 630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Wait till PLL is disabled */ + 632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 2450 .loc 1 632 14 + 2451 0ec4 09E0 b .L143 + 2452 .L150: + 633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 2453 .loc 1 634 15 + 2454 0ec6 FFF7FEFF bl HAL_GetTick + 2455 0eca 0246 mov r2, r0 + 2456 .loc 1 634 29 discriminator 1 + 2457 0ecc D7F8F831 ldr r3, [r7, #504] + 2458 0ed0 D31A subs r3, r2, r3 + 2459 .loc 1 634 13 discriminator 1 + 2460 0ed2 022B cmp r3, #2 + 2461 0ed4 01D9 bls .L143 + 635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_TIMEOUT; + 2462 .loc 1 636 20 + 2463 0ed6 0323 movs r3, #3 + 2464 0ed8 99E0 b .L15 + 2465 .L143: + 2466 0eda 07F50073 add r3, r7, #512 + ARM GAS /tmp/ccSuWkwR.s page 75 + + + 2467 0ede A3F5EC73 sub r3, r3, #472 + 2468 0ee2 4FF00072 mov r2, #33554432 + 2469 0ee6 1A60 str r2, [r3] + 2470 .LBB286: + 2471 .LBB287: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 2472 .loc 2 988 4 + 2473 0ee8 07F50073 add r3, r7, #512 + 2474 0eec A3F5EC73 sub r3, r3, #472 + 2475 0ef0 1B68 ldr r3, [r3] + 2476 .syntax unified + 2477 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2478 0ef2 93FAA3F2 rbit r2, r3 + 2479 @ 0 "" 2 + 2480 .thumb + 2481 .syntax unified + 2482 0ef6 07F50073 add r3, r7, #512 + 2483 0efa A3F5EE73 sub r3, r3, #476 + 2484 0efe 1A60 str r2, [r3] + 2485 .loc 2 1001 10 + 2486 0f00 07F50073 add r3, r7, #512 + 2487 0f04 A3F5EE73 sub r3, r3, #476 + 2488 0f08 1B68 ldr r3, [r3] + 2489 .LBE287: + 2490 .LBE286: + 632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2491 .loc 1 632 15 discriminator 1 + 2492 0f0a B3FA83F3 clz r3, r3 + 632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2493 .loc 1 632 15 is_stmt 0 discriminator 2 + 2494 0f0e DBB2 uxtb r3, r3 + 2495 0f10 3F2B cmp r3, #63 + 2496 0f12 02D8 bhi .L145 + 632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2497 .loc 1 632 15 discriminator 1 + 2498 0f14 2D4B ldr r3, .L162 + 2499 0f16 1B68 ldr r3, [r3] + 2500 0f18 27E0 b .L146 + 2501 .L145: + 2502 0f1a 07F50073 add r3, r7, #512 + 2503 0f1e A3F5F073 sub r3, r3, #480 + 2504 0f22 4FF00072 mov r2, #33554432 + 2505 0f26 1A60 str r2, [r3] + 2506 .LBB288: + 2507 .LBB289: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 2508 .loc 2 988 4 is_stmt 1 + 2509 0f28 07F50073 add r3, r7, #512 + 2510 0f2c A3F5F073 sub r3, r3, #480 + 2511 0f30 1B68 ldr r3, [r3] + 2512 .syntax unified + 2513 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2514 0f32 93FAA3F2 rbit r2, r3 + 2515 @ 0 "" 2 + 2516 .thumb + 2517 .syntax unified + 2518 0f36 07F50073 add r3, r7, #512 + ARM GAS /tmp/ccSuWkwR.s page 76 + + + 2519 0f3a A3F5F273 sub r3, r3, #484 + 2520 0f3e 1A60 str r2, [r3] + 2521 0f40 07F50073 add r3, r7, #512 + 2522 0f44 A3F5F473 sub r3, r3, #488 + 2523 0f48 4FF00072 mov r2, #33554432 + 2524 0f4c 1A60 str r2, [r3] + 2525 .LBE289: + 2526 .LBE288: + 2527 .LBB290: + 2528 .LBB291: + 2529 0f4e 07F50073 add r3, r7, #512 + 2530 0f52 A3F5F473 sub r3, r3, #488 + 2531 0f56 1B68 ldr r3, [r3] + 2532 .syntax unified + 2533 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2534 0f58 93FAA3F2 rbit r2, r3 + 2535 @ 0 "" 2 + 2536 .thumb + 2537 .syntax unified + 2538 0f5c 07F50073 add r3, r7, #512 + 2539 0f60 A3F5F673 sub r3, r3, #492 + 2540 0f64 1A60 str r2, [r3] + 2541 .LBE291: + 2542 .LBE290: + 632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2543 .loc 1 632 15 discriminator 8 + 2544 0f66 194B ldr r3, .L162 + 2545 0f68 5B6A ldr r3, [r3, #36] + 2546 .L146: + 2547 0f6a 07F50072 add r2, r7, #512 + 2548 0f6e A2F5F872 sub r2, r2, #496 + 2549 0f72 4FF00071 mov r1, #33554432 + 2550 0f76 1160 str r1, [r2] + 2551 .LBB292: + 2552 .LBB293: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 2553 .loc 2 988 4 + 2554 0f78 07F50072 add r2, r7, #512 + 2555 0f7c A2F5F872 sub r2, r2, #496 + 2556 0f80 1268 ldr r2, [r2] + 2557 .syntax unified + 2558 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2559 0f82 92FAA2F1 rbit r1, r2 + 2560 @ 0 "" 2 + 2561 .thumb + 2562 .syntax unified + 2563 0f86 07F50072 add r2, r7, #512 + 2564 0f8a A2F5FA72 sub r2, r2, #500 + 2565 0f8e 1160 str r1, [r2] + 2566 .loc 2 1001 10 + 2567 0f90 07F50072 add r2, r7, #512 + 2568 0f94 A2F5FA72 sub r2, r2, #500 + 2569 0f98 1268 ldr r2, [r2] + 2570 .LBE293: + 2571 .LBE292: + 632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2572 .loc 1 632 15 discriminator 1 + ARM GAS /tmp/ccSuWkwR.s page 77 + + + 2573 0f9a B2FA82F2 clz r2, r2 + 632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2574 .loc 1 632 15 is_stmt 0 discriminator 2 + 2575 0f9e D2B2 uxtb r2, r2 + 2576 0fa0 42F02002 orr r2, r2, #32 + 2577 0fa4 D2B2 uxtb r2, r2 + 2578 0fa6 02F01F02 and r2, r2, #31 + 2579 0faa 0121 movs r1, #1 + 2580 0fac 01FA02F2 lsl r2, r1, r2 + 2581 0fb0 1340 ands r3, r3, r2 + 632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2582 .loc 1 632 52 is_stmt 1 discriminator 2 + 2583 0fb2 002B cmp r3, #0 + 2584 0fb4 87D1 bne .L150 + 2585 0fb6 29E0 b .L121 + 2586 .L122: + 637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else + 642:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check if there is a request to disable the PLL used as System clock source */ + 644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) + 2587 .loc 1 644 33 + 2588 0fb8 07F50073 add r3, r7, #512 + 2589 0fbc A3F5FE73 sub r3, r3, #508 + 2590 0fc0 1B68 ldr r3, [r3] + 2591 0fc2 DB69 ldr r3, [r3, #28] + 2592 .loc 1 644 9 + 2593 0fc4 012B cmp r3, #1 + 2594 0fc6 03D1 bne .L151 + 645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_ERROR; + 2595 .loc 1 646 16 + 2596 0fc8 0123 movs r3, #1 + 2597 0fca 20E0 b .L15 + 2598 .L163: + 2599 .align 2 + 2600 .L162: + 2601 0fcc 00100240 .word 1073876992 + 2602 .L151: + 647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else + 649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Do not return HAL_ERROR if request repeats the current configuration */ + 651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** pll_config = RCC->CFGR; + 2603 .loc 1 651 25 + 2604 0fd0 114B ldr r3, .L164 + 2605 .loc 1 651 20 + 2606 0fd2 5B68 ldr r3, [r3, #4] + 2607 0fd4 C7F8F431 str r3, [r7, #500] + 652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) + 653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** pll_config2 = RCC->CFGR2; + 654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 655:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) || + 656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV)) + ARM GAS /tmp/ccSuWkwR.s page 78 + + + 657:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #else + 658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 2608 .loc 1 658 13 + 2609 0fd8 D7F8F431 ldr r3, [r7, #500] + 2610 0fdc 03F48032 and r2, r3, #65536 + 2611 .loc 1 658 78 + 2612 0fe0 07F50073 add r3, r7, #512 + 2613 0fe4 A3F5FE73 sub r3, r3, #508 + 2614 0fe8 1B68 ldr r3, [r3] + 2615 0fea 1B6A ldr r3, [r3, #32] + 2616 .loc 1 658 11 + 2617 0fec 9A42 cmp r2, r3 + 2618 0fee 0BD1 bne .L152 + 659:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL)) + 2619 .loc 1 659 13 + 2620 0ff0 D7F8F431 ldr r3, [r7, #500] + 2621 0ff4 03F47012 and r2, r3, #3932160 + 2622 .loc 1 659 78 + 2623 0ff8 07F50073 add r3, r7, #512 + 2624 0ffc A3F5FE73 sub r3, r3, #508 + 2625 1000 1B68 ldr r3, [r3] + 2626 1002 5B6A ldr r3, [r3, #36] + 658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL)) + 2627 .loc 1 658 90 discriminator 1 + 2628 1004 9A42 cmp r2, r3 + 2629 1006 01D0 beq .L121 + 2630 .L152: + 660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #endif + 661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_ERROR; + 2631 .loc 1 662 18 + 2632 1008 0123 movs r3, #1 + 2633 100a 00E0 b .L15 + 2634 .L121: + 663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 664:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 668:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_OK; + 2635 .loc 1 668 10 + 2636 100c 0023 movs r3, #0 + 2637 .L15: + 669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 2638 .loc 1 669 1 + 2639 100e 1846 mov r0, r3 + 2640 1010 07F50077 add r7, r7, #512 + 2641 .cfi_def_cfa_offset 8 + 2642 1014 BD46 mov sp, r7 + 2643 .cfi_def_cfa_register 13 + 2644 @ sp needed + 2645 1016 80BD pop {r7, pc} + 2646 .L165: + 2647 .align 2 + 2648 .L164: + 2649 1018 00100240 .word 1073876992 + 2650 .cfi_endproc + ARM GAS /tmp/ccSuWkwR.s page 79 + + + 2651 .LFE131: + 2653 .section .text.HAL_RCC_ClockConfig,"ax",%progbits + 2654 .align 1 + 2655 .global HAL_RCC_ClockConfig + 2656 .syntax unified + 2657 .thumb + 2658 .thumb_func + 2660 HAL_RCC_ClockConfig: + 2661 .LFB132: + 670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** + 672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief Initializes the CPU, AHB and APB buses clocks according to the specified + 673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * parameters in the RCC_ClkInitStruct. + 674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that + 675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * contains the configuration information for the RCC peripheral. + 676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @param FLatency FLASH Latency + 677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * The value of this parameter depend on device used within the same series + 678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + 679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function + 680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * + 681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note The HSI is used (enabled by hardware) as system clock source after + 682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * start-up from Reset, wake-up from STOP and STANDBY mode, or in case + 683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * of failure of the HSE used directly or indirectly as system clock + 684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * (if the Clock Security System CSS is enabled). + 685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * + 686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note A switch from one clock source to another occurs only if the target + 687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * clock source is ready (clock stable after start-up delay or PLL locked). + 688:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * If a clock source which is not yet ready is selected, the switch will + 689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * occur when the clock source will be ready. + 690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is + 691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * currently used as system clock source. + 692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @retval HAL status + 693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ + 694:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) + 695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 2662 .loc 1 695 1 + 2663 .cfi_startproc + 2664 @ args = 0, pretend = 0, frame = 120 + 2665 @ frame_needed = 1, uses_anonymous_args = 0 + 2666 0000 80B5 push {r7, lr} + 2667 .cfi_def_cfa_offset 8 + 2668 .cfi_offset 7, -8 + 2669 .cfi_offset 14, -4 + 2670 0002 9EB0 sub sp, sp, #120 + 2671 .cfi_def_cfa_offset 128 + 2672 0004 00AF add r7, sp, #0 + 2673 .cfi_def_cfa_register 7 + 2674 0006 7860 str r0, [r7, #4] + 2675 0008 3960 str r1, [r7] + 696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** uint32_t tickstart = 0U; + 2676 .loc 1 696 12 + 2677 000a 0023 movs r3, #0 + 2678 000c 7B67 str r3, [r7, #116] + 697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check Null pointer */ + 699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(RCC_ClkInitStruct == NULL) + 2679 .loc 1 699 5 + ARM GAS /tmp/ccSuWkwR.s page 80 + + + 2680 000e 7B68 ldr r3, [r7, #4] + 2681 0010 002B cmp r3, #0 + 2682 0012 01D1 bne .L167 + 700:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_ERROR; + 2683 .loc 1 701 12 + 2684 0014 0123 movs r3, #1 + 2685 0016 54E1 b .L168 + 2686 .L167: + 702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 704:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the parameters */ + 705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); + 706:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_FLASH_LATENCY(FLatency)); + 707:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 708:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + 709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** must be correctly programmed according to the frequency of the CPU clock + 710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** (HCLK) of the device. */ + 711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Increasing the number of wait states because of higher CPU frequency */ + 713:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(FLatency > __HAL_FLASH_GET_LATENCY()) + 2687 .loc 1 713 17 + 2688 0018 894B ldr r3, .L199 + 2689 001a 1B68 ldr r3, [r3] + 2690 001c 03F00703 and r3, r3, #7 + 2691 .loc 1 713 5 + 2692 0020 3A68 ldr r2, [r7] + 2693 0022 9A42 cmp r2, r3 + 2694 0024 10D9 bls .L169 + 714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + 716:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_FLASH_SET_LATENCY(FLatency); + 2695 .loc 1 716 5 + 2696 0026 864B ldr r3, .L199 + 2697 0028 1B68 ldr r3, [r3] + 2698 002a 23F00702 bic r2, r3, #7 + 2699 002e 8449 ldr r1, .L199 + 2700 0030 3B68 ldr r3, [r7] + 2701 0032 1343 orrs r3, r3, r2 + 2702 0034 0B60 str r3, [r1] + 717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 718:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check that the new number of wait states is taken into account to access the Flash + 719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** memory by reading the FLASH_ACR register */ + 720:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(__HAL_FLASH_GET_LATENCY() != FLatency) + 2703 .loc 1 720 8 + 2704 0036 824B ldr r3, .L199 + 2705 0038 1B68 ldr r3, [r3] + 2706 003a 03F00703 and r3, r3, #7 + 2707 .loc 1 720 7 + 2708 003e 3A68 ldr r2, [r7] + 2709 0040 9A42 cmp r2, r3 + 2710 0042 01D0 beq .L169 + 721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 722:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_ERROR; + 2711 .loc 1 722 14 + 2712 0044 0123 movs r3, #1 + 2713 0046 3CE1 b .L168 + ARM GAS /tmp/ccSuWkwR.s page 81 + + + 2714 .L169: + 723:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 724:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 725:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /*-------------------------- HCLK Configuration --------------------------*/ + 727:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + 2715 .loc 1 727 25 + 2716 0048 7B68 ldr r3, [r7, #4] + 2717 004a 1B68 ldr r3, [r3] + 2718 .loc 1 727 38 + 2719 004c 03F00203 and r3, r3, #2 + 2720 .loc 1 727 5 + 2721 0050 002B cmp r3, #0 + 2722 0052 08D0 beq .L170 + 728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + 730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + 2723 .loc 1 730 5 + 2724 0054 7B4B ldr r3, .L199+4 + 2725 0056 5B68 ldr r3, [r3, #4] + 2726 0058 23F0F002 bic r2, r3, #240 + 2727 005c 7B68 ldr r3, [r7, #4] + 2728 005e 9B68 ldr r3, [r3, #8] + 2729 0060 7849 ldr r1, .L199+4 + 2730 0062 1343 orrs r3, r3, r2 + 2731 0064 4B60 str r3, [r1, #4] + 2732 .L170: + 731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /*------------------------- SYSCLK Configuration ---------------------------*/ + 734:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + 2733 .loc 1 734 25 + 2734 0066 7B68 ldr r3, [r7, #4] + 2735 0068 1B68 ldr r3, [r3] + 2736 .loc 1 734 38 + 2737 006a 03F00103 and r3, r3, #1 + 2738 .loc 1 734 5 + 2739 006e 002B cmp r3, #0 + 2740 0070 00F0CD80 beq .L171 + 735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + 737:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* HSE is selected as System Clock Source */ + 739:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + 2741 .loc 1 739 25 + 2742 0074 7B68 ldr r3, [r7, #4] + 2743 0076 5B68 ldr r3, [r3, #4] + 2744 .loc 1 739 7 + 2745 0078 012B cmp r3, #1 + 2746 007a 37D1 bne .L172 + 2747 007c 4FF40033 mov r3, #131072 + 2748 0080 FB66 str r3, [r7, #108] + 2749 .LBB294: + 2750 .LBB295: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 2751 .loc 2 988 4 + 2752 0082 FB6E ldr r3, [r7, #108] + ARM GAS /tmp/ccSuWkwR.s page 82 + + + 2753 .syntax unified + 2754 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2755 0084 93FAA3F3 rbit r3, r3 + 2756 @ 0 "" 2 + 2757 .thumb + 2758 .syntax unified + 2759 0088 3B67 str r3, [r7, #112] + 2760 .loc 2 1001 10 + 2761 008a 3B6F ldr r3, [r7, #112] + 2762 .LBE295: + 2763 .LBE294: + 740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the HSE ready flag */ + 742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + 2764 .loc 1 742 10 discriminator 1 + 2765 008c B3FA83F3 clz r3, r3 + 2766 .loc 1 742 10 is_stmt 0 discriminator 2 + 2767 0090 DBB2 uxtb r3, r3 + 2768 0092 3F2B cmp r3, #63 + 2769 0094 02D8 bhi .L174 + 2770 .loc 1 742 10 discriminator 1 + 2771 0096 6B4B ldr r3, .L199+4 + 2772 0098 1B68 ldr r3, [r3] + 2773 009a 0FE0 b .L175 + 2774 .L174: + 2775 009c 4FF40033 mov r3, #131072 + 2776 00a0 BB66 str r3, [r7, #104] + 2777 .LBB296: + 2778 .LBB297: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 2779 .loc 2 988 4 is_stmt 1 + 2780 00a2 BB6E ldr r3, [r7, #104] + 2781 .syntax unified + 2782 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2783 00a4 93FAA3F3 rbit r3, r3 + 2784 @ 0 "" 2 + 2785 .thumb + 2786 .syntax unified + 2787 00a8 7B66 str r3, [r7, #100] + 2788 00aa 4FF40033 mov r3, #131072 + 2789 00ae 3B66 str r3, [r7, #96] + 2790 .LBE297: + 2791 .LBE296: + 2792 .LBB298: + 2793 .LBB299: + 2794 00b0 3B6E ldr r3, [r7, #96] + 2795 .syntax unified + 2796 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2797 00b2 93FAA3F3 rbit r3, r3 + 2798 @ 0 "" 2 + 2799 .thumb + 2800 .syntax unified + 2801 00b6 FB65 str r3, [r7, #92] + 2802 .LBE299: + 2803 .LBE298: + 2804 .loc 1 742 10 discriminator 8 + 2805 00b8 624B ldr r3, .L199+4 + ARM GAS /tmp/ccSuWkwR.s page 83 + + + 2806 00ba 5B6A ldr r3, [r3, #36] + 2807 .L175: + 2808 00bc 4FF40032 mov r2, #131072 + 2809 00c0 BA65 str r2, [r7, #88] + 2810 .LBB300: + 2811 .LBB301: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 2812 .loc 2 988 4 + 2813 00c2 BA6D ldr r2, [r7, #88] + 2814 .syntax unified + 2815 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2816 00c4 92FAA2F2 rbit r2, r2 + 2817 @ 0 "" 2 + 2818 .thumb + 2819 .syntax unified + 2820 00c8 7A65 str r2, [r7, #84] + 2821 .loc 2 1001 10 + 2822 00ca 7A6D ldr r2, [r7, #84] + 2823 .LBE301: + 2824 .LBE300: + 2825 .loc 1 742 10 discriminator 1 + 2826 00cc B2FA82F2 clz r2, r2 + 2827 .loc 1 742 10 is_stmt 0 discriminator 2 + 2828 00d0 D2B2 uxtb r2, r2 + 2829 00d2 42F02002 orr r2, r2, #32 + 2830 00d6 D2B2 uxtb r2, r2 + 2831 00d8 02F01F02 and r2, r2, #31 + 2832 00dc 0121 movs r1, #1 + 2833 00de 01FA02F2 lsl r2, r1, r2 + 2834 00e2 1340 ands r3, r3, r2 + 2835 .loc 1 742 9 is_stmt 1 discriminator 2 + 2836 00e4 002B cmp r3, #0 + 2837 00e6 71D1 bne .L179 + 743:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_ERROR; + 2838 .loc 1 744 16 + 2839 00e8 0123 movs r3, #1 + 2840 00ea EAE0 b .L168 + 2841 .L172: + 745:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 746:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 747:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* PLL is selected as System Clock Source */ + 748:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + 2842 .loc 1 748 30 + 2843 00ec 7B68 ldr r3, [r7, #4] + 2844 00ee 5B68 ldr r3, [r3, #4] + 2845 .loc 1 748 12 + 2846 00f0 022B cmp r3, #2 + 2847 00f2 37D1 bne .L180 + 2848 00f4 4FF00073 mov r3, #33554432 + 2849 00f8 3B65 str r3, [r7, #80] + 2850 .LBB302: + 2851 .LBB303: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 2852 .loc 2 988 4 + 2853 00fa 3B6D ldr r3, [r7, #80] + 2854 .syntax unified + ARM GAS /tmp/ccSuWkwR.s page 84 + + + 2855 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2856 00fc 93FAA3F3 rbit r3, r3 + 2857 @ 0 "" 2 + 2858 .thumb + 2859 .syntax unified + 2860 0100 FB64 str r3, [r7, #76] + 2861 .loc 2 1001 10 + 2862 0102 FB6C ldr r3, [r7, #76] + 2863 .LBE303: + 2864 .LBE302: + 749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the PLL ready flag */ + 751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 2865 .loc 1 751 10 discriminator 1 + 2866 0104 B3FA83F3 clz r3, r3 + 2867 .loc 1 751 10 is_stmt 0 discriminator 2 + 2868 0108 DBB2 uxtb r3, r3 + 2869 010a 3F2B cmp r3, #63 + 2870 010c 02D8 bhi .L182 + 2871 .loc 1 751 10 discriminator 1 + 2872 010e 4D4B ldr r3, .L199+4 + 2873 0110 1B68 ldr r3, [r3] + 2874 0112 0FE0 b .L183 + 2875 .L182: + 2876 0114 4FF00073 mov r3, #33554432 + 2877 0118 BB64 str r3, [r7, #72] + 2878 .LBB304: + 2879 .LBB305: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 2880 .loc 2 988 4 is_stmt 1 + 2881 011a BB6C ldr r3, [r7, #72] + 2882 .syntax unified + 2883 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2884 011c 93FAA3F3 rbit r3, r3 + 2885 @ 0 "" 2 + 2886 .thumb + 2887 .syntax unified + 2888 0120 7B64 str r3, [r7, #68] + 2889 0122 4FF00073 mov r3, #33554432 + 2890 0126 3B64 str r3, [r7, #64] + 2891 .LBE305: + 2892 .LBE304: + 2893 .LBB306: + 2894 .LBB307: + 2895 0128 3B6C ldr r3, [r7, #64] + 2896 .syntax unified + 2897 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2898 012a 93FAA3F3 rbit r3, r3 + 2899 @ 0 "" 2 + 2900 .thumb + 2901 .syntax unified + 2902 012e FB63 str r3, [r7, #60] + 2903 .LBE307: + 2904 .LBE306: + 2905 .loc 1 751 10 discriminator 8 + 2906 0130 444B ldr r3, .L199+4 + 2907 0132 5B6A ldr r3, [r3, #36] + ARM GAS /tmp/ccSuWkwR.s page 85 + + + 2908 .L183: + 2909 0134 4FF00072 mov r2, #33554432 + 2910 0138 BA63 str r2, [r7, #56] + 2911 .LBB308: + 2912 .LBB309: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 2913 .loc 2 988 4 + 2914 013a BA6B ldr r2, [r7, #56] + 2915 .syntax unified + 2916 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2917 013c 92FAA2F2 rbit r2, r2 + 2918 @ 0 "" 2 + 2919 .thumb + 2920 .syntax unified + 2921 0140 7A63 str r2, [r7, #52] + 2922 .loc 2 1001 10 + 2923 0142 7A6B ldr r2, [r7, #52] + 2924 .LBE309: + 2925 .LBE308: + 2926 .loc 1 751 10 discriminator 1 + 2927 0144 B2FA82F2 clz r2, r2 + 2928 .loc 1 751 10 is_stmt 0 discriminator 2 + 2929 0148 D2B2 uxtb r2, r2 + 2930 014a 42F02002 orr r2, r2, #32 + 2931 014e D2B2 uxtb r2, r2 + 2932 0150 02F01F02 and r2, r2, #31 + 2933 0154 0121 movs r1, #1 + 2934 0156 01FA02F2 lsl r2, r1, r2 + 2935 015a 1340 ands r3, r3, r2 + 2936 .loc 1 751 9 is_stmt 1 discriminator 2 + 2937 015c 002B cmp r3, #0 + 2938 015e 35D1 bne .L179 + 752:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_ERROR; + 2939 .loc 1 753 16 + 2940 0160 0123 movs r3, #1 + 2941 0162 AEE0 b .L168 + 2942 .L180: + 2943 0164 0223 movs r3, #2 + 2944 0166 3B63 str r3, [r7, #48] + 2945 .LBB310: + 2946 .LBB311: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 2947 .loc 2 988 4 + 2948 0168 3B6B ldr r3, [r7, #48] + 2949 .syntax unified + 2950 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2951 016a 93FAA3F3 rbit r3, r3 + 2952 @ 0 "" 2 + 2953 .thumb + 2954 .syntax unified + 2955 016e FB62 str r3, [r7, #44] + 2956 .loc 2 1001 10 + 2957 0170 FB6A ldr r3, [r7, #44] + 2958 .LBE311: + 2959 .LBE310: + 754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + ARM GAS /tmp/ccSuWkwR.s page 86 + + + 755:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* HSI is selected as System Clock Source */ + 757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else + 758:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the HSI ready flag */ + 760:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + 2960 .loc 1 760 10 discriminator 1 + 2961 0172 B3FA83F3 clz r3, r3 + 2962 .loc 1 760 10 is_stmt 0 discriminator 2 + 2963 0176 DBB2 uxtb r3, r3 + 2964 0178 3F2B cmp r3, #63 + 2965 017a 02D8 bhi .L188 + 2966 .loc 1 760 10 discriminator 1 + 2967 017c 314B ldr r3, .L199+4 + 2968 017e 1B68 ldr r3, [r3] + 2969 0180 0DE0 b .L189 + 2970 .L188: + 2971 0182 0223 movs r3, #2 + 2972 0184 BB62 str r3, [r7, #40] + 2973 .LBB312: + 2974 .LBB313: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 2975 .loc 2 988 4 is_stmt 1 + 2976 0186 BB6A ldr r3, [r7, #40] + 2977 .syntax unified + 2978 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2979 0188 93FAA3F3 rbit r3, r3 + 2980 @ 0 "" 2 + 2981 .thumb + 2982 .syntax unified + 2983 018c 7B62 str r3, [r7, #36] + 2984 018e 0223 movs r3, #2 + 2985 0190 3B62 str r3, [r7, #32] + 2986 .LBE313: + 2987 .LBE312: + 2988 .LBB314: + 2989 .LBB315: + 2990 0192 3B6A ldr r3, [r7, #32] + 2991 .syntax unified + 2992 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 2993 0194 93FAA3F3 rbit r3, r3 + 2994 @ 0 "" 2 + 2995 .thumb + 2996 .syntax unified + 2997 0198 FB61 str r3, [r7, #28] + 2998 .LBE315: + 2999 .LBE314: + 3000 .loc 1 760 10 discriminator 8 + 3001 019a 2A4B ldr r3, .L199+4 + 3002 019c 5B6A ldr r3, [r3, #36] + 3003 .L189: + 3004 019e 0222 movs r2, #2 + 3005 01a0 BA61 str r2, [r7, #24] + 3006 .LBB316: + 3007 .LBB317: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 3008 .loc 2 988 4 + ARM GAS /tmp/ccSuWkwR.s page 87 + + + 3009 01a2 BA69 ldr r2, [r7, #24] + 3010 .syntax unified + 3011 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 3012 01a4 92FAA2F2 rbit r2, r2 + 3013 @ 0 "" 2 + 3014 .thumb + 3015 .syntax unified + 3016 01a8 7A61 str r2, [r7, #20] + 3017 .loc 2 1001 10 + 3018 01aa 7A69 ldr r2, [r7, #20] + 3019 .LBE317: + 3020 .LBE316: + 3021 .loc 1 760 10 discriminator 1 + 3022 01ac B2FA82F2 clz r2, r2 + 3023 .loc 1 760 10 is_stmt 0 discriminator 2 + 3024 01b0 D2B2 uxtb r2, r2 + 3025 01b2 42F02002 orr r2, r2, #32 + 3026 01b6 D2B2 uxtb r2, r2 + 3027 01b8 02F01F02 and r2, r2, #31 + 3028 01bc 0121 movs r1, #1 + 3029 01be 01FA02F2 lsl r2, r1, r2 + 3030 01c2 1340 ands r3, r3, r2 + 3031 .loc 1 760 9 is_stmt 1 discriminator 2 + 3032 01c4 002B cmp r3, #0 + 3033 01c6 01D1 bne .L179 + 761:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_ERROR; + 3034 .loc 1 762 16 + 3035 01c8 0123 movs r3, #1 + 3036 01ca 7AE0 b .L168 + 3037 .L179: + 763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 764:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); + 3038 .loc 1 766 5 + 3039 01cc 1D4B ldr r3, .L199+4 + 3040 01ce 5B68 ldr r3, [r3, #4] + 3041 01d0 23F00302 bic r2, r3, #3 + 3042 01d4 7B68 ldr r3, [r7, #4] + 3043 01d6 5B68 ldr r3, [r3, #4] + 3044 01d8 1A49 ldr r1, .L199+4 + 3045 01da 1343 orrs r3, r3, r2 + 3046 01dc 4B60 str r3, [r1, #4] + 767:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get Start Tick */ + 769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tickstart = HAL_GetTick(); + 3047 .loc 1 769 17 + 3048 01de FFF7FEFF bl HAL_GetTick + 3049 01e2 7867 str r0, [r7, #116] + 770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + 3050 .loc 1 771 11 + 3051 01e4 0AE0 b .L193 + 3052 .L194: + 772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + ARM GAS /tmp/ccSuWkwR.s page 88 + + + 3053 .loc 1 773 12 + 3054 01e6 FFF7FEFF bl HAL_GetTick + 3055 01ea 0246 mov r2, r0 + 3056 .loc 1 773 26 discriminator 1 + 3057 01ec 7B6F ldr r3, [r7, #116] + 3058 01ee D31A subs r3, r2, r3 + 3059 .loc 1 773 10 discriminator 1 + 3060 01f0 41F28832 movw r2, #5000 + 3061 01f4 9342 cmp r3, r2 + 3062 01f6 01D9 bls .L193 + 774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_TIMEOUT; + 3063 .loc 1 775 16 + 3064 01f8 0323 movs r3, #3 + 3065 01fa 62E0 b .L168 + 3066 .L193: + 771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 3067 .loc 1 771 12 + 3068 01fc 114B ldr r3, .L199+4 + 3069 01fe 5B68 ldr r3, [r3, #4] + 3070 0200 03F00C02 and r2, r3, #12 + 771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 3071 .loc 1 771 63 + 3072 0204 7B68 ldr r3, [r7, #4] + 3073 0206 5B68 ldr r3, [r3, #4] + 771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 3074 .loc 1 771 78 + 3075 0208 9B00 lsls r3, r3, #2 + 771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 3076 .loc 1 771 42 + 3077 020a 9A42 cmp r2, r3 + 3078 020c EBD1 bne .L194 + 3079 .L171: + 776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 777:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Decreasing the number of wait states because of lower CPU frequency */ + 780:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(FLatency < __HAL_FLASH_GET_LATENCY()) + 3080 .loc 1 780 17 + 3081 020e 0C4B ldr r3, .L199 + 3082 0210 1B68 ldr r3, [r3] + 3083 0212 03F00703 and r3, r3, #7 + 3084 .loc 1 780 5 + 3085 0216 3A68 ldr r2, [r7] + 3086 0218 9A42 cmp r2, r3 + 3087 021a 15D2 bcs .L195 + 781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 782:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + 783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_FLASH_SET_LATENCY(FLatency); + 3088 .loc 1 783 5 + 3089 021c 084B ldr r3, .L199 + 3090 021e 1B68 ldr r3, [r3] + 3091 0220 23F00702 bic r2, r3, #7 + 3092 0224 0649 ldr r1, .L199 + 3093 0226 3B68 ldr r3, [r7] + 3094 0228 1343 orrs r3, r3, r2 + 3095 022a 0B60 str r3, [r1] + ARM GAS /tmp/ccSuWkwR.s page 89 + + + 784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check that the new number of wait states is taken into account to access the Flash + 786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** memory by reading the FLASH_ACR register */ + 787:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(__HAL_FLASH_GET_LATENCY() != FLatency) + 3096 .loc 1 787 8 + 3097 022c 044B ldr r3, .L199 + 3098 022e 1B68 ldr r3, [r3] + 3099 0230 03F00703 and r3, r3, #7 + 3100 .loc 1 787 7 + 3101 0234 3A68 ldr r2, [r7] + 3102 0236 9A42 cmp r2, r3 + 3103 0238 06D0 beq .L195 + 788:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_ERROR; + 3104 .loc 1 789 14 + 3105 023a 0123 movs r3, #1 + 3106 023c 41E0 b .L168 + 3107 .L200: + 3108 023e 00BF .align 2 + 3109 .L199: + 3110 0240 00200240 .word 1073881088 + 3111 0244 00100240 .word 1073876992 + 3112 .L195: + 790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /*-------------------------- PCLK1 Configuration ---------------------------*/ + 794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 3113 .loc 1 794 25 + 3114 0248 7B68 ldr r3, [r7, #4] + 3115 024a 1B68 ldr r3, [r3] + 3116 .loc 1 794 38 + 3117 024c 03F00403 and r3, r3, #4 + 3118 .loc 1 794 5 + 3119 0250 002B cmp r3, #0 + 3120 0252 08D0 beq .L196 + 795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); + 797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); + 3121 .loc 1 797 5 + 3122 0254 1D4B ldr r3, .L201 + 3123 0256 5B68 ldr r3, [r3, #4] + 3124 0258 23F4E062 bic r2, r3, #1792 + 3125 025c 7B68 ldr r3, [r7, #4] + 3126 025e DB68 ldr r3, [r3, #12] + 3127 0260 1A49 ldr r1, .L201 + 3128 0262 1343 orrs r3, r3, r2 + 3129 0264 4B60 str r3, [r1, #4] + 3130 .L196: + 798:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 799:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /*-------------------------- PCLK2 Configuration ---------------------------*/ + 801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + 3131 .loc 1 801 25 + 3132 0266 7B68 ldr r3, [r7, #4] + 3133 0268 1B68 ldr r3, [r3] + 3134 .loc 1 801 38 + ARM GAS /tmp/ccSuWkwR.s page 90 + + + 3135 026a 03F00803 and r3, r3, #8 + 3136 .loc 1 801 5 + 3137 026e 002B cmp r3, #0 + 3138 0270 09D0 beq .L197 + 802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 803:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); + 804:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); + 3139 .loc 1 804 5 + 3140 0272 164B ldr r3, .L201 + 3141 0274 5B68 ldr r3, [r3, #4] + 3142 0276 23F46052 bic r2, r3, #14336 + 3143 027a 7B68 ldr r3, [r7, #4] + 3144 027c 1B69 ldr r3, [r3, #16] + 3145 027e DB00 lsls r3, r3, #3 + 3146 0280 1249 ldr r1, .L201 + 3147 0282 1343 orrs r3, r3, r2 + 3148 0284 4B60 str r3, [r1, #4] + 3149 .L197: + 805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 806:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 807:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Update the SystemCoreClock global variable */ + 808:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CF + 3150 .loc 1 808 21 + 3151 0286 FFF7FEFF bl HAL_RCC_GetSysClockFreq + 3152 028a 0146 mov r1, r0 + 3153 .loc 1 808 68 discriminator 1 + 3154 028c 0F4B ldr r3, .L201 + 3155 028e 5B68 ldr r3, [r3, #4] + 3156 .loc 1 808 75 discriminator 1 + 3157 0290 03F0F003 and r3, r3, #240 + 3158 0294 F022 movs r2, #240 + 3159 0296 3A61 str r2, [r7, #16] + 3160 .LBB318: + 3161 .LBB319: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 3162 .loc 2 988 4 + 3163 0298 3A69 ldr r2, [r7, #16] + 3164 .syntax unified + 3165 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 3166 029a 92FAA2F2 rbit r2, r2 + 3167 @ 0 "" 2 + 3168 .thumb + 3169 .syntax unified + 3170 029e FA60 str r2, [r7, #12] + 3171 .loc 2 1001 10 + 3172 02a0 FA68 ldr r2, [r7, #12] + 3173 .LBE319: + 3174 .LBE318: + 3175 .loc 1 808 94 discriminator 2 + 3176 02a2 B2FA82F2 clz r2, r2 + 3177 .loc 1 808 94 is_stmt 0 discriminator 3 + 3178 02a6 D2B2 uxtb r2, r2 + 3179 .loc 1 808 91 is_stmt 1 discriminator 3 + 3180 02a8 D340 lsrs r3, r3, r2 + 3181 .loc 1 808 63 discriminator 3 + 3182 02aa 094A ldr r2, .L201+4 + 3183 02ac D35C ldrb r3, [r2, r3] @ zero_extendqisi2 + ARM GAS /tmp/ccSuWkwR.s page 91 + + + 3184 .loc 1 808 47 discriminator 3 + 3185 02ae 21FA03F3 lsr r3, r1, r3 + 3186 .loc 1 808 19 discriminator 3 + 3187 02b2 084A ldr r2, .L201+8 + 3188 02b4 1360 str r3, [r2] + 809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Configure the source of time base considering new system clocks settings*/ + 811:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** HAL_InitTick (uwTickPrio); + 3189 .loc 1 811 3 + 3190 02b6 084B ldr r3, .L201+12 + 3191 02b8 1B68 ldr r3, [r3] + 3192 02ba 1846 mov r0, r3 + 3193 02bc FFF7FEFF bl HAL_InitTick + 812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return HAL_OK; + 3194 .loc 1 813 10 + 3195 02c0 0023 movs r3, #0 + 3196 .L168: + 814:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 3197 .loc 1 814 1 + 3198 02c2 1846 mov r0, r3 + 3199 02c4 7837 adds r7, r7, #120 + 3200 .cfi_def_cfa_offset 8 + 3201 02c6 BD46 mov sp, r7 + 3202 .cfi_def_cfa_register 13 + 3203 @ sp needed + 3204 02c8 80BD pop {r7, pc} + 3205 .L202: + 3206 02ca 00BF .align 2 + 3207 .L201: + 3208 02cc 00100240 .word 1073876992 + 3209 02d0 00000000 .word AHBPrescTable + 3210 02d4 00000000 .word SystemCoreClock + 3211 02d8 00000000 .word uwTickPrio + 3212 .cfi_endproc + 3213 .LFE132: + 3215 .section .text.HAL_RCC_MCOConfig,"ax",%progbits + 3216 .align 1 + 3217 .global HAL_RCC_MCOConfig + 3218 .syntax unified + 3219 .thumb + 3220 .thumb_func + 3222 HAL_RCC_MCOConfig: + 3223 .LFB133: + 815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** + 817:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @} + 818:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ + 819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 820:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions + 821:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief RCC clocks control functions + 822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * + 823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** @verbatim + 824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** =============================================================================== + 825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** ##### Peripheral Control functions ##### + 826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** =============================================================================== + 827:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** [..] + ARM GAS /tmp/ccSuWkwR.s page 92 + + + 828:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** This subsection provides a set of functions allowing to control the RCC Clocks + 829:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** frequencies. + 830:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** @endverbatim + 832:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @{ + 833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ + 834:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 835:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #if defined(RCC_CFGR_MCOPRE) + 836:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** + 837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief Selects the clock source to output on MCO pin. + 838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note MCO pin should be configured in alternate function mode. + 839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @param RCC_MCOx specifies the output direction for the clock source. + 840:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * This parameter can be one of the following values: + 841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8). + 842:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @param RCC_MCOSource specifies the clock source to output. + 843:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * This parameter can be one of the following values: + 844:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected + 845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock + 846:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock + 847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock + 848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock + 849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock + 850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock + 851:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock + 852:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @param RCC_MCODiv specifies the MCO DIV. + 853:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * This parameter can be one of the following values: + 854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCODIV_1 no division applied to MCO clock + 855:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCODIV_2 division by 2 applied to MCO clock + 856:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCODIV_4 division by 4 applied to MCO clock + 857:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCODIV_8 division by 8 applied to MCO clock + 858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCODIV_16 division by 16 applied to MCO clock + 859:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCODIV_32 division by 32 applied to MCO clock + 860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCODIV_64 division by 64 applied to MCO clock + 861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCODIV_128 division by 128 applied to MCO clock + 862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @retval None + 863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ + 864:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #else + 865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** + 866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief Selects the clock source to output on MCO pin. + 867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note MCO pin should be configured in alternate function mode. + 868:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @param RCC_MCOx specifies the output direction for the clock source. + 869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * This parameter can be one of the following values: + 870:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8). + 871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @param RCC_MCOSource specifies the clock source to output. + 872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * This parameter can be one of the following values: + 873:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock + 874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO clock + 875:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock + 876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock + 877:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock + 878:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock + 879:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock + 880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @param RCC_MCODiv specifies the MCO DIV. + 881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * This parameter can be one of the following values: + 882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @arg @ref RCC_MCODIV_1 no division applied to MCO clock + 883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @retval None + 884:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ + ARM GAS /tmp/ccSuWkwR.s page 93 + + + 885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #endif + 886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) + 887:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 3224 .loc 1 887 1 + 3225 .cfi_startproc + 3226 @ args = 0, pretend = 0, frame = 40 + 3227 @ frame_needed = 1, uses_anonymous_args = 0 + 3228 0000 80B5 push {r7, lr} + 3229 .cfi_def_cfa_offset 8 + 3230 .cfi_offset 7, -8 + 3231 .cfi_offset 14, -4 + 3232 0002 8AB0 sub sp, sp, #40 + 3233 .cfi_def_cfa_offset 48 + 3234 0004 00AF add r7, sp, #0 + 3235 .cfi_def_cfa_register 7 + 3236 0006 F860 str r0, [r7, #12] + 3237 0008 B960 str r1, [r7, #8] + 3238 000a 7A60 str r2, [r7, #4] + 888:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** GPIO_InitTypeDef gpio; + 889:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 890:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the parameters */ + 891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_MCO(RCC_MCOx)); + 892:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_MCODIV(RCC_MCODiv)); + 893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); + 894:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 895:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Configure the MCO1 pin in alternate function mode */ + 896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** gpio.Mode = GPIO_MODE_AF_PP; + 3239 .loc 1 896 18 + 3240 000c 0223 movs r3, #2 + 3241 000e BB61 str r3, [r7, #24] + 897:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** gpio.Speed = GPIO_SPEED_FREQ_HIGH; + 3242 .loc 1 897 18 + 3243 0010 0323 movs r3, #3 + 3244 0012 3B62 str r3, [r7, #32] + 898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** gpio.Pull = GPIO_NOPULL; + 3245 .loc 1 898 18 + 3246 0014 0023 movs r3, #0 + 3247 0016 FB61 str r3, [r7, #28] + 899:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** gpio.Pin = MCO1_PIN; + 3248 .loc 1 899 18 + 3249 0018 4FF48073 mov r3, #256 + 3250 001c 7B61 str r3, [r7, #20] + 900:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** gpio.Alternate = GPIO_AF0_MCO; + 3251 .loc 1 900 18 + 3252 001e 0023 movs r3, #0 + 3253 0020 7B62 str r3, [r7, #36] + 3254 .LBB320: + 901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 902:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* MCO1 Clock Enable */ + 903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** MCO1_CLK_ENABLE(); + 3255 .loc 1 903 3 + 3256 0022 0F4B ldr r3, .L204 + 3257 0024 5B69 ldr r3, [r3, #20] + 3258 0026 0E4A ldr r2, .L204 + 3259 0028 43F40033 orr r3, r3, #131072 + 3260 002c 5361 str r3, [r2, #20] + 3261 002e 0C4B ldr r3, .L204 + ARM GAS /tmp/ccSuWkwR.s page 94 + + + 3262 0030 5B69 ldr r3, [r3, #20] + 3263 0032 03F40033 and r3, r3, #131072 + 3264 0036 3B61 str r3, [r7, #16] + 3265 0038 3B69 ldr r3, [r7, #16] + 3266 .LBE320: + 904:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 905:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio); + 3267 .loc 1 905 3 + 3268 003a 07F11403 add r3, r7, #20 + 3269 003e 1946 mov r1, r3 + 3270 0040 4FF09040 mov r0, #1207959552 + 3271 0044 FFF7FEFF bl HAL_GPIO_Init + 906:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Configure the MCO clock source */ + 908:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv); + 3272 .loc 1 908 3 + 3273 0048 054B ldr r3, .L204 + 3274 004a 5B68 ldr r3, [r3, #4] + 3275 004c 23F0E062 bic r2, r3, #117440512 + 3276 0050 0349 ldr r1, .L204 + 3277 0052 BB68 ldr r3, [r7, #8] + 3278 0054 1343 orrs r3, r3, r2 + 3279 0056 4B60 str r3, [r1, #4] + 909:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 3280 .loc 1 909 1 + 3281 0058 00BF nop + 3282 005a 2837 adds r7, r7, #40 + 3283 .cfi_def_cfa_offset 8 + 3284 005c BD46 mov sp, r7 + 3285 .cfi_def_cfa_register 13 + 3286 @ sp needed + 3287 005e 80BD pop {r7, pc} + 3288 .L205: + 3289 .align 2 + 3290 .L204: + 3291 0060 00100240 .word 1073876992 + 3292 .cfi_endproc + 3293 .LFE133: + 3295 .section .text.HAL_RCC_EnableCSS,"ax",%progbits + 3296 .align 1 + 3297 .global HAL_RCC_EnableCSS + 3298 .syntax unified + 3299 .thumb + 3300 .thumb_func + 3302 HAL_RCC_EnableCSS: + 3303 .LFB134: + 910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 911:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** + 912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief Enables the Clock Security System. + 913:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note If a failure is detected on the HSE oscillator clock, this oscillator + 914:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * is automatically disabled and an interrupt is generated to inform the + 915:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * software about the failure (Clock Security System Interrupt, CSSI), + 916:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * allowing the MCU to perform rescue operations. The CSSI is linked to + 917:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector. + 918:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @retval None + 919:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ + 920:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** void HAL_RCC_EnableCSS(void) + ARM GAS /tmp/ccSuWkwR.s page 95 + + + 921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 3304 .loc 1 921 1 + 3305 .cfi_startproc + 3306 @ args = 0, pretend = 0, frame = 8 + 3307 @ frame_needed = 1, uses_anonymous_args = 0 + 3308 @ link register save eliminated. + 3309 0000 80B4 push {r7} + 3310 .cfi_def_cfa_offset 4 + 3311 .cfi_offset 7, -4 + 3312 0002 83B0 sub sp, sp, #12 + 3313 .cfi_def_cfa_offset 16 + 3314 0004 00AF add r7, sp, #0 + 3315 .cfi_def_cfa_register 7 + 3316 0006 4FF40023 mov r3, #524288 + 3317 000a 7B60 str r3, [r7, #4] + 3318 .LBB321: + 3319 .LBB322: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 3320 .loc 2 988 4 + 3321 000c 7B68 ldr r3, [r7, #4] + 3322 .syntax unified + 3323 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 3324 000e 93FAA3F3 rbit r3, r3 + 3325 @ 0 "" 2 + 3326 .thumb + 3327 .syntax unified + 3328 0012 3B60 str r3, [r7] + 3329 .loc 2 1001 10 + 3330 0014 3B68 ldr r3, [r7] + 3331 .LBE322: + 3332 .LBE321: + 922:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE; + 3333 .loc 1 922 22 discriminator 1 + 3334 0016 B3FA83F3 clz r3, r3 + 3335 .loc 1 922 22 is_stmt 0 discriminator 2 + 3336 001a DBB2 uxtb r3, r3 + 3337 001c 03F18453 add r3, r3, #276824064 + 3338 0020 03F58413 add r3, r3, #1081344 + 3339 0024 9B00 lsls r3, r3, #2 + 3340 .loc 1 922 4 is_stmt 1 discriminator 2 + 3341 0026 1A46 mov r2, r3 + 3342 .loc 1 922 38 discriminator 2 + 3343 0028 0123 movs r3, #1 + 3344 002a 1360 str r3, [r2] + 923:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 3345 .loc 1 923 1 + 3346 002c 00BF nop + 3347 002e 0C37 adds r7, r7, #12 + 3348 .cfi_def_cfa_offset 4 + 3349 0030 BD46 mov sp, r7 + 3350 .cfi_def_cfa_register 13 + 3351 @ sp needed + 3352 0032 5DF8047B ldr r7, [sp], #4 + 3353 .cfi_restore 7 + 3354 .cfi_def_cfa_offset 0 + 3355 0036 7047 bx lr + 3356 .cfi_endproc + ARM GAS /tmp/ccSuWkwR.s page 96 + + + 3357 .LFE134: + 3359 .section .text.HAL_RCC_DisableCSS,"ax",%progbits + 3360 .align 1 + 3361 .global HAL_RCC_DisableCSS + 3362 .syntax unified + 3363 .thumb + 3364 .thumb_func + 3366 HAL_RCC_DisableCSS: + 3367 .LFB135: + 924:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 925:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** + 926:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief Disables the Clock Security System. + 927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @retval None + 928:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ + 929:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** void HAL_RCC_DisableCSS(void) + 930:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 3368 .loc 1 930 1 + 3369 .cfi_startproc + 3370 @ args = 0, pretend = 0, frame = 8 + 3371 @ frame_needed = 1, uses_anonymous_args = 0 + 3372 @ link register save eliminated. + 3373 0000 80B4 push {r7} + 3374 .cfi_def_cfa_offset 4 + 3375 .cfi_offset 7, -4 + 3376 0002 83B0 sub sp, sp, #12 + 3377 .cfi_def_cfa_offset 16 + 3378 0004 00AF add r7, sp, #0 + 3379 .cfi_def_cfa_register 7 + 3380 0006 4FF40023 mov r3, #524288 + 3381 000a 7B60 str r3, [r7, #4] + 3382 .LBB323: + 3383 .LBB324: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 3384 .loc 2 988 4 + 3385 000c 7B68 ldr r3, [r7, #4] + 3386 .syntax unified + 3387 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 3388 000e 93FAA3F3 rbit r3, r3 + 3389 @ 0 "" 2 + 3390 .thumb + 3391 .syntax unified + 3392 0012 3B60 str r3, [r7] + 3393 .loc 2 1001 10 + 3394 0014 3B68 ldr r3, [r7] + 3395 .LBE324: + 3396 .LBE323: + 931:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE; + 3397 .loc 1 931 22 discriminator 1 + 3398 0016 B3FA83F3 clz r3, r3 + 3399 .loc 1 931 22 is_stmt 0 discriminator 2 + 3400 001a DBB2 uxtb r3, r3 + 3401 001c 03F18453 add r3, r3, #276824064 + 3402 0020 03F58413 add r3, r3, #1081344 + 3403 0024 9B00 lsls r3, r3, #2 + 3404 .loc 1 931 4 is_stmt 1 discriminator 2 + 3405 0026 1A46 mov r2, r3 + 3406 .loc 1 931 38 discriminator 2 + ARM GAS /tmp/ccSuWkwR.s page 97 + + + 3407 0028 0023 movs r3, #0 + 3408 002a 1360 str r3, [r2] + 932:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 3409 .loc 1 932 1 + 3410 002c 00BF nop + 3411 002e 0C37 adds r7, r7, #12 + 3412 .cfi_def_cfa_offset 4 + 3413 0030 BD46 mov sp, r7 + 3414 .cfi_def_cfa_register 13 + 3415 @ sp needed + 3416 0032 5DF8047B ldr r7, [sp], #4 + 3417 .cfi_restore 7 + 3418 .cfi_def_cfa_offset 0 + 3419 0036 7047 bx lr + 3420 .cfi_endproc + 3421 .LFE135: + 3423 .section .text.HAL_RCC_GetSysClockFreq,"ax",%progbits + 3424 .align 1 + 3425 .global HAL_RCC_GetSysClockFreq + 3426 .syntax unified + 3427 .thumb + 3428 .thumb_func + 3430 HAL_RCC_GetSysClockFreq: + 3431 .LFB136: + 933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 934:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** + 935:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief Returns the SYSCLK frequency + 936:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note The system frequency computed by this function is not the real + 937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * frequency in the chip. It is calculated based on the predefined + 938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * constant and the selected clock source: + 939:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) + 940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE + 941:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * divided by PREDIV factor(**) + 942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE + 943:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * divided by PREDIV factor(**) or HSI_VALUE(*) multiplied by the PLL factor. + 944:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note (*) HSI_VALUE is a constant defined in stm32f3xx_hal_conf.h file (default value + 945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * 8 MHz) but the real value may vary depending on the variations + 946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * in voltage and temperature. + 947:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note (**) HSE_VALUE is a constant defined in stm32f3xx_hal_conf.h file (default value + 948:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * 8 MHz), user has to ensure that HSE_VALUE is same as the real + 949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * frequency of the crystal used. Otherwise, this function may + 950:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * have wrong result. + 951:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * + 952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note The result of this function could be not correct when using fractional + 953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * value for HSE crystal. + 954:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * + 955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note This function can be used by the user application to compute the + 956:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * baud-rate for the communication peripherals or configure other parameters. + 957:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * + 958:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note Each time SYSCLK changes, this function must be called to update the + 959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * right SYSCLK value. Otherwise, any configuration based on this function will be incorre + 960:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * + 961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @retval SYSCLK frequency + 962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ + 963:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** uint32_t HAL_RCC_GetSysClockFreq(void) + 964:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 3432 .loc 1 964 1 + ARM GAS /tmp/ccSuWkwR.s page 98 + + + 3433 .cfi_startproc + 3434 @ args = 0, pretend = 0, frame = 40 + 3435 @ frame_needed = 1, uses_anonymous_args = 0 + 3436 @ link register save eliminated. + 3437 0000 80B4 push {r7} + 3438 .cfi_def_cfa_offset 4 + 3439 .cfi_offset 7, -4 + 3440 0002 8BB0 sub sp, sp, #44 + 3441 .cfi_def_cfa_offset 48 + 3442 0004 00AF add r7, sp, #0 + 3443 .cfi_def_cfa_register 7 + 965:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U; + 3444 .loc 1 965 12 + 3445 0006 0023 movs r3, #0 + 3446 0008 FB61 str r3, [r7, #28] + 3447 .loc 1 965 25 + 3448 000a 0023 movs r3, #0 + 3449 000c BB61 str r3, [r7, #24] + 3450 .loc 1 965 38 + 3451 000e 0023 movs r3, #0 + 3452 0010 7B62 str r3, [r7, #36] + 3453 .loc 1 965 51 + 3454 0012 0023 movs r3, #0 + 3455 0014 7B61 str r3, [r7, #20] + 966:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** uint32_t sysclockfreq = 0U; + 3456 .loc 1 966 12 + 3457 0016 0023 movs r3, #0 + 3458 0018 3B62 str r3, [r7, #32] + 967:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** tmpreg = RCC->CFGR; + 3459 .loc 1 968 15 + 3460 001a 294B ldr r3, .L221 + 3461 .loc 1 968 10 + 3462 001c 5B68 ldr r3, [r3, #4] + 3463 001e FB61 str r3, [r7, #28] + 969:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + 970:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get SYSCLK source -------------------------------------------------------*/ + 971:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** switch (tmpreg & RCC_CFGR_SWS) + 3464 .loc 1 971 18 + 3465 0020 FB69 ldr r3, [r7, #28] + 3466 0022 03F00C03 and r3, r3, #12 + 3467 .loc 1 971 3 + 3468 0026 042B cmp r3, #4 + 3469 0028 02D0 beq .L211 + 3470 002a 082B cmp r3, #8 + 3471 002c 03D0 beq .L212 + 3472 002e 3CE0 b .L220 + 3473 .L211: + 972:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 973:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ + 974:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 975:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** sysclockfreq = HSE_VALUE; + 3474 .loc 1 975 20 + 3475 0030 244B ldr r3, .L221+4 + 3476 0032 3B62 str r3, [r7, #32] + 976:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** break; + 3477 .loc 1 976 7 + ARM GAS /tmp/ccSuWkwR.s page 99 + + + 3478 0034 3CE0 b .L214 + 3479 .L212: + 977:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 978:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ + 979:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> POSITION_VAL(RCC_CFGR_PLL + 3480 .loc 1 980 35 + 3481 0036 FB69 ldr r3, [r7, #28] + 3482 0038 03F47013 and r3, r3, #3932160 + 3483 003c 4FF47012 mov r2, #3932160 + 3484 0040 BA60 str r2, [r7, #8] + 3485 .LBB325: + 3486 .LBB326: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 3487 .loc 2 988 4 + 3488 0042 BA68 ldr r2, [r7, #8] + 3489 .syntax unified + 3490 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 3491 0044 92FAA2F2 rbit r2, r2 + 3492 @ 0 "" 2 + 3493 .thumb + 3494 .syntax unified + 3495 0048 7A60 str r2, [r7, #4] + 3496 .loc 2 1001 10 + 3497 004a 7A68 ldr r2, [r7, #4] + 3498 .LBE326: + 3499 .LBE325: + 3500 .loc 1 980 75 discriminator 1 + 3501 004c B2FA82F2 clz r2, r2 + 3502 .loc 1 980 75 is_stmt 0 discriminator 2 + 3503 0050 D2B2 uxtb r2, r2 + 3504 .loc 1 980 72 is_stmt 1 discriminator 2 + 3505 0052 D340 lsrs r3, r3, r2 + 3506 .loc 1 980 34 discriminator 2 + 3507 0054 1C4A ldr r2, .L221+8 + 3508 0056 D35C ldrb r3, [r2, r3] @ zero_extendqisi2 + 3509 .loc 1 980 14 discriminator 2 + 3510 0058 7B61 str r3, [r7, #20] + 981:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> POSITION_VAL(RCC_CFG + 3511 .loc 1 981 49 + 3512 005a 194B ldr r3, .L221 + 3513 005c DB6A ldr r3, [r3, #44] + 3514 .loc 1 981 35 + 3515 005e 03F00F03 and r3, r3, #15 + 3516 0062 0F22 movs r2, #15 + 3517 0064 3A61 str r2, [r7, #16] + 3518 .LBB327: + 3519 .LBB328: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 3520 .loc 2 988 4 + 3521 0066 3A69 ldr r2, [r7, #16] + 3522 .syntax unified + 3523 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 3524 0068 92FAA2F2 rbit r2, r2 + 3525 @ 0 "" 2 + 3526 .thumb + 3527 .syntax unified + ARM GAS /tmp/ccSuWkwR.s page 100 + + + 3528 006c FA60 str r2, [r7, #12] + 3529 .loc 2 1001 10 + 3530 006e FA68 ldr r2, [r7, #12] + 3531 .LBE328: + 3532 .LBE327: + 3533 .loc 1 981 80 discriminator 1 + 3534 0070 B2FA82F2 clz r2, r2 + 3535 .loc 1 981 80 is_stmt 0 discriminator 2 + 3536 0074 D2B2 uxtb r2, r2 + 3537 .loc 1 981 77 is_stmt 1 discriminator 2 + 3538 0076 D340 lsrs r3, r3, r2 + 3539 .loc 1 981 34 discriminator 2 + 3540 0078 144A ldr r2, .L221+12 + 3541 007a D35C ldrb r3, [r2, r3] @ zero_extendqisi2 + 3542 .loc 1 981 14 discriminator 2 + 3543 007c BB61 str r3, [r7, #24] + 982:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #if defined(RCC_CFGR_PLLSRC_HSI_DIV2) + 983:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI) + 3544 .loc 1 983 19 + 3545 007e FB69 ldr r3, [r7, #28] + 3546 0080 03F48033 and r3, r3, #65536 + 3547 .loc 1 983 10 + 3548 0084 002B cmp r3, #0 + 3549 0086 08D0 beq .L217 + 984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 985:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */ + 986:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul); + 3550 .loc 1 986 18 + 3551 0088 0E4A ldr r2, .L221+4 + 3552 008a BB69 ldr r3, [r7, #24] + 3553 008c B2FBF3F2 udiv r2, r2, r3 + 3554 .loc 1 986 16 + 3555 0090 7B69 ldr r3, [r7, #20] + 3556 0092 02FB03F3 mul r3, r2, r3 + 3557 0096 7B62 str r3, [r7, #36] + 3558 0098 04E0 b .L218 + 3559 .L217: + 987:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 988:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else + 989:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 990:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */ + 991:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** pllclk = (uint32_t)((uint64_t) (HSI_VALUE >> 1U) * ((uint64_t) pllmul)); + 3560 .loc 1 991 16 + 3561 009a 7B69 ldr r3, [r7, #20] + 3562 009c 0C4A ldr r2, .L221+16 + 3563 009e 02FB03F3 mul r3, r2, r3 + 3564 00a2 7B62 str r3, [r7, #36] + 3565 .L218: + 992:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 993:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #else + 994:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if ((tmpreg & RCC_CFGR_PLLSRC_HSE_PREDIV) == RCC_CFGR_PLLSRC_HSE_PREDIV) + 995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 996:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */ + 997:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul); + 998:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 999:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else +1000:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + ARM GAS /tmp/ccSuWkwR.s page 101 + + +1001:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */ +1002:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** pllclk = (uint32_t)((uint64_t) HSI_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul); +1003:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } +1004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */ +1005:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** sysclockfreq = pllclk; + 3566 .loc 1 1005 20 + 3567 00a4 7B6A ldr r3, [r7, #36] + 3568 00a6 3B62 str r3, [r7, #32] +1006:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** break; + 3569 .loc 1 1006 7 + 3570 00a8 02E0 b .L214 + 3571 .L220: +1007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } +1008:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ +1009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** default: /* HSI used as system clock */ +1010:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { +1011:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** sysclockfreq = HSI_VALUE; + 3572 .loc 1 1011 20 + 3573 00aa 0A4B ldr r3, .L221+20 + 3574 00ac 3B62 str r3, [r7, #32] +1012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** break; + 3575 .loc 1 1012 7 + 3576 00ae 00BF nop + 3577 .L214: +1013:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } +1014:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } +1015:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return sysclockfreq; + 3578 .loc 1 1015 10 + 3579 00b0 3B6A ldr r3, [r7, #32] +1016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 3580 .loc 1 1016 1 + 3581 00b2 1846 mov r0, r3 + 3582 00b4 2C37 adds r7, r7, #44 + 3583 .cfi_def_cfa_offset 4 + 3584 00b6 BD46 mov sp, r7 + 3585 .cfi_def_cfa_register 13 + 3586 @ sp needed + 3587 00b8 5DF8047B ldr r7, [sp], #4 + 3588 .cfi_restore 7 + 3589 .cfi_def_cfa_offset 0 + 3590 00bc 7047 bx lr + 3591 .L222: + 3592 00be 00BF .align 2 + 3593 .L221: + 3594 00c0 00100240 .word 1073876992 + 3595 00c4 0024F400 .word 16000000 + 3596 00c8 00000000 .word aPLLMULFactorTable + 3597 00cc 00000000 .word aPredivFactorTable + 3598 00d0 00093D00 .word 4000000 + 3599 00d4 00127A00 .word 8000000 + 3600 .cfi_endproc + 3601 .LFE136: + 3603 .section .text.HAL_RCC_GetHCLKFreq,"ax",%progbits + 3604 .align 1 + 3605 .global HAL_RCC_GetHCLKFreq + 3606 .syntax unified + 3607 .thumb + ARM GAS /tmp/ccSuWkwR.s page 102 + + + 3608 .thumb_func + 3610 HAL_RCC_GetHCLKFreq: + 3611 .LFB137: +1017:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** +1018:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** +1019:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief Returns the HCLK frequency +1020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note Each time HCLK changes, this function must be called to update the +1021:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * right HCLK value. Otherwise, any configuration based on this function will be incorrect +1022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * +1023:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency +1024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * and updated within this function +1025:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @retval HCLK frequency +1026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ +1027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** uint32_t HAL_RCC_GetHCLKFreq(void) +1028:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 3612 .loc 1 1028 1 + 3613 .cfi_startproc + 3614 @ args = 0, pretend = 0, frame = 0 + 3615 @ frame_needed = 1, uses_anonymous_args = 0 + 3616 @ link register save eliminated. + 3617 0000 80B4 push {r7} + 3618 .cfi_def_cfa_offset 4 + 3619 .cfi_offset 7, -4 + 3620 0002 00AF add r7, sp, #0 + 3621 .cfi_def_cfa_register 7 +1029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return SystemCoreClock; + 3622 .loc 1 1029 10 + 3623 0004 034B ldr r3, .L225 + 3624 0006 1B68 ldr r3, [r3] +1030:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 3625 .loc 1 1030 1 + 3626 0008 1846 mov r0, r3 + 3627 000a BD46 mov sp, r7 + 3628 .cfi_def_cfa_register 13 + 3629 @ sp needed + 3630 000c 5DF8047B ldr r7, [sp], #4 + 3631 .cfi_restore 7 + 3632 .cfi_def_cfa_offset 0 + 3633 0010 7047 bx lr + 3634 .L226: + 3635 0012 00BF .align 2 + 3636 .L225: + 3637 0014 00000000 .word SystemCoreClock + 3638 .cfi_endproc + 3639 .LFE137: + 3641 .section .text.HAL_RCC_GetPCLK1Freq,"ax",%progbits + 3642 .align 1 + 3643 .global HAL_RCC_GetPCLK1Freq + 3644 .syntax unified + 3645 .thumb + 3646 .thumb_func + 3648 HAL_RCC_GetPCLK1Freq: + 3649 .LFB138: +1031:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** +1032:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** +1033:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief Returns the PCLK1 frequency +1034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note Each time PCLK1 changes, this function must be called to update the + ARM GAS /tmp/ccSuWkwR.s page 103 + + +1035:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * right PCLK1 value. Otherwise, any configuration based on this function will be incorrec +1036:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @retval PCLK1 frequency +1037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ +1038:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** uint32_t HAL_RCC_GetPCLK1Freq(void) +1039:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 3650 .loc 1 1039 1 + 3651 .cfi_startproc + 3652 @ args = 0, pretend = 0, frame = 8 + 3653 @ frame_needed = 1, uses_anonymous_args = 0 + 3654 0000 80B5 push {r7, lr} + 3655 .cfi_def_cfa_offset 8 + 3656 .cfi_offset 7, -8 + 3657 .cfi_offset 14, -4 + 3658 0002 82B0 sub sp, sp, #8 + 3659 .cfi_def_cfa_offset 16 + 3660 0004 00AF add r7, sp, #0 + 3661 .cfi_def_cfa_register 7 +1040:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ +1041:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_BIT + 3662 .loc 1 1041 11 + 3663 0006 FFF7FEFF bl HAL_RCC_GetHCLKFreq + 3664 000a 0146 mov r1, r0 + 3665 .loc 1 1041 54 discriminator 1 + 3666 000c 0B4B ldr r3, .L230 + 3667 000e 5B68 ldr r3, [r3, #4] + 3668 .loc 1 1041 61 discriminator 1 + 3669 0010 03F4E063 and r3, r3, #1792 + 3670 0014 4FF4E062 mov r2, #1792 + 3671 0018 7A60 str r2, [r7, #4] + 3672 .LBB329: + 3673 .LBB330: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 3674 .loc 2 988 4 + 3675 001a 7A68 ldr r2, [r7, #4] + 3676 .syntax unified + 3677 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 3678 001c 92FAA2F2 rbit r2, r2 + 3679 @ 0 "" 2 + 3680 .thumb + 3681 .syntax unified + 3682 0020 3A60 str r2, [r7] + 3683 .loc 2 1001 10 + 3684 0022 3A68 ldr r2, [r7] + 3685 .LBE330: + 3686 .LBE329: + 3687 .loc 1 1041 82 discriminator 2 + 3688 0024 B2FA82F2 clz r2, r2 + 3689 .loc 1 1041 82 is_stmt 0 discriminator 3 + 3690 0028 D2B2 uxtb r2, r2 + 3691 .loc 1 1041 79 is_stmt 1 discriminator 3 + 3692 002a D340 lsrs r3, r3, r2 + 3693 .loc 1 1041 49 discriminator 3 + 3694 002c 044A ldr r2, .L230+4 + 3695 002e D35C ldrb r3, [r2, r3] @ zero_extendqisi2 + 3696 .loc 1 1041 33 discriminator 3 + 3697 0030 21FA03F3 lsr r3, r1, r3 +1042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + ARM GAS /tmp/ccSuWkwR.s page 104 + + + 3698 .loc 1 1042 1 + 3699 0034 1846 mov r0, r3 + 3700 0036 0837 adds r7, r7, #8 + 3701 .cfi_def_cfa_offset 8 + 3702 0038 BD46 mov sp, r7 + 3703 .cfi_def_cfa_register 13 + 3704 @ sp needed + 3705 003a 80BD pop {r7, pc} + 3706 .L231: + 3707 .align 2 + 3708 .L230: + 3709 003c 00100240 .word 1073876992 + 3710 0040 00000000 .word APBPrescTable + 3711 .cfi_endproc + 3712 .LFE138: + 3714 .section .text.HAL_RCC_GetPCLK2Freq,"ax",%progbits + 3715 .align 1 + 3716 .global HAL_RCC_GetPCLK2Freq + 3717 .syntax unified + 3718 .thumb + 3719 .thumb_func + 3721 HAL_RCC_GetPCLK2Freq: + 3722 .LFB139: +1043:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** +1044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** +1045:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief Returns the PCLK2 frequency +1046:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note Each time PCLK2 changes, this function must be called to update the +1047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * right PCLK2 value. Otherwise, any configuration based on this function will be incorrec +1048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @retval PCLK2 frequency +1049:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ +1050:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** uint32_t HAL_RCC_GetPCLK2Freq(void) +1051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 3723 .loc 1 1051 1 + 3724 .cfi_startproc + 3725 @ args = 0, pretend = 0, frame = 8 + 3726 @ frame_needed = 1, uses_anonymous_args = 0 + 3727 0000 80B5 push {r7, lr} + 3728 .cfi_def_cfa_offset 8 + 3729 .cfi_offset 7, -8 + 3730 .cfi_offset 14, -4 + 3731 0002 82B0 sub sp, sp, #8 + 3732 .cfi_def_cfa_offset 16 + 3733 0004 00AF add r7, sp, #0 + 3734 .cfi_def_cfa_register 7 +1052:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ +1053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_BITN + 3735 .loc 1 1053 11 + 3736 0006 FFF7FEFF bl HAL_RCC_GetHCLKFreq + 3737 000a 0146 mov r1, r0 + 3738 .loc 1 1053 53 discriminator 1 + 3739 000c 0B4B ldr r3, .L235 + 3740 000e 5B68 ldr r3, [r3, #4] + 3741 .loc 1 1053 60 discriminator 1 + 3742 0010 03F46053 and r3, r3, #14336 + 3743 0014 4FF46052 mov r2, #14336 + 3744 0018 7A60 str r2, [r7, #4] + 3745 .LBB331: + ARM GAS /tmp/ccSuWkwR.s page 105 + + + 3746 .LBB332: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 3747 .loc 2 988 4 + 3748 001a 7A68 ldr r2, [r7, #4] + 3749 .syntax unified + 3750 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 3751 001c 92FAA2F2 rbit r2, r2 + 3752 @ 0 "" 2 + 3753 .thumb + 3754 .syntax unified + 3755 0020 3A60 str r2, [r7] + 3756 .loc 2 1001 10 + 3757 0022 3A68 ldr r2, [r7] + 3758 .LBE332: + 3759 .LBE331: + 3760 .loc 1 1053 81 discriminator 2 + 3761 0024 B2FA82F2 clz r2, r2 + 3762 .loc 1 1053 81 is_stmt 0 discriminator 3 + 3763 0028 D2B2 uxtb r2, r2 + 3764 .loc 1 1053 78 is_stmt 1 discriminator 3 + 3765 002a D340 lsrs r3, r3, r2 + 3766 .loc 1 1053 48 discriminator 3 + 3767 002c 044A ldr r2, .L235+4 + 3768 002e D35C ldrb r3, [r2, r3] @ zero_extendqisi2 + 3769 .loc 1 1053 32 discriminator 3 + 3770 0030 21FA03F3 lsr r3, r1, r3 +1054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 3771 .loc 1 1054 1 + 3772 0034 1846 mov r0, r3 + 3773 0036 0837 adds r7, r7, #8 + 3774 .cfi_def_cfa_offset 8 + 3775 0038 BD46 mov sp, r7 + 3776 .cfi_def_cfa_register 13 + 3777 @ sp needed + 3778 003a 80BD pop {r7, pc} + 3779 .L236: + 3780 .align 2 + 3781 .L235: + 3782 003c 00100240 .word 1073876992 + 3783 0040 00000000 .word APBPrescTable + 3784 .cfi_endproc + 3785 .LFE139: + 3787 .section .text.HAL_RCC_GetOscConfig,"ax",%progbits + 3788 .align 1 + 3789 .global HAL_RCC_GetOscConfig + 3790 .syntax unified + 3791 .thumb + 3792 .thumb_func + 3794 HAL_RCC_GetOscConfig: + 3795 .LFB140: +1055:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** +1056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** +1057:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief Configures the RCC_OscInitStruct according to the internal +1058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * RCC configuration registers. +1059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that +1060:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * will be configured. +1061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @retval None + ARM GAS /tmp/ccSuWkwR.s page 106 + + +1062:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ +1063:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +1064:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 3796 .loc 1 1064 1 + 3797 .cfi_startproc + 3798 @ args = 0, pretend = 0, frame = 16 + 3799 @ frame_needed = 1, uses_anonymous_args = 0 + 3800 @ link register save eliminated. + 3801 0000 80B4 push {r7} + 3802 .cfi_def_cfa_offset 4 + 3803 .cfi_offset 7, -4 + 3804 0002 85B0 sub sp, sp, #20 + 3805 .cfi_def_cfa_offset 24 + 3806 0004 00AF add r7, sp, #0 + 3807 .cfi_def_cfa_register 7 + 3808 0006 7860 str r0, [r7, #4] +1065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the parameters */ +1066:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(RCC_OscInitStruct != NULL); +1067:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** +1068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Set all possible values for the Oscillator type parameter ---------------*/ +1069:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI \ + 3809 .loc 1 1069 37 + 3810 0008 7B68 ldr r3, [r7, #4] + 3811 000a 0F22 movs r2, #15 + 3812 000c 1A60 str r2, [r3] +1070:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI; +1071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** +1072:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** +1073:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get the HSE configuration -----------------------------------------------*/ +1074:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP) + 3813 .loc 1 1074 10 + 3814 000e 424B ldr r3, .L251 + 3815 0010 1B68 ldr r3, [r3] + 3816 .loc 1 1074 15 + 3817 0012 03F48023 and r3, r3, #262144 + 3818 .loc 1 1074 5 + 3819 0016 B3F5802F cmp r3, #262144 + 3820 001a 04D1 bne .L238 +1075:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { +1076:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; + 3821 .loc 1 1076 33 + 3822 001c 7B68 ldr r3, [r7, #4] + 3823 001e 4FF4A022 mov r2, #327680 + 3824 0022 5A60 str r2, [r3, #4] + 3825 0024 0EE0 b .L239 + 3826 .L238: +1077:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } +1078:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON) + 3827 .loc 1 1078 15 + 3828 0026 3C4B ldr r3, .L251 + 3829 0028 1B68 ldr r3, [r3] + 3830 .loc 1 1078 20 + 3831 002a 03F48033 and r3, r3, #65536 + 3832 .loc 1 1078 10 + 3833 002e B3F5803F cmp r3, #65536 + 3834 0032 04D1 bne .L240 +1079:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + ARM GAS /tmp/ccSuWkwR.s page 107 + + +1080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->HSEState = RCC_HSE_ON; + 3835 .loc 1 1080 33 + 3836 0034 7B68 ldr r3, [r7, #4] + 3837 0036 4FF48032 mov r2, #65536 + 3838 003a 5A60 str r2, [r3, #4] + 3839 003c 02E0 b .L239 + 3840 .L240: +1081:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } +1082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else +1083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { +1084:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->HSEState = RCC_HSE_OFF; + 3841 .loc 1 1084 33 + 3842 003e 7B68 ldr r3, [r7, #4] + 3843 0040 0022 movs r2, #0 + 3844 0042 5A60 str r2, [r3, #4] + 3845 .L239: +1085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } +1086:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #if defined(RCC_CFGR_PLLSRC_HSI_DIV2) +1087:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->HSEPredivValue = __HAL_RCC_HSE_GET_PREDIV(); + 3846 .loc 1 1087 39 + 3847 0044 344B ldr r3, .L251 + 3848 0046 DB6A ldr r3, [r3, #44] + 3849 0048 03F00F02 and r2, r3, #15 + 3850 .loc 1 1087 37 + 3851 004c 7B68 ldr r3, [r7, #4] + 3852 004e 9A60 str r2, [r3, #8] +1088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #endif +1089:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** +1090:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get the HSI configuration -----------------------------------------------*/ +1091:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION) + 3853 .loc 1 1091 10 + 3854 0050 314B ldr r3, .L251 + 3855 0052 1B68 ldr r3, [r3] + 3856 .loc 1 1091 15 + 3857 0054 03F00103 and r3, r3, #1 + 3858 .loc 1 1091 5 + 3859 0058 012B cmp r3, #1 + 3860 005a 03D1 bne .L241 +1092:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { +1093:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->HSIState = RCC_HSI_ON; + 3861 .loc 1 1093 33 + 3862 005c 7B68 ldr r3, [r7, #4] + 3863 005e 0122 movs r2, #1 + 3864 0060 1A61 str r2, [r3, #16] + 3865 0062 02E0 b .L242 + 3866 .L241: +1094:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } +1095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else +1096:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { +1097:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->HSIState = RCC_HSI_OFF; + 3867 .loc 1 1097 33 + 3868 0064 7B68 ldr r3, [r7, #4] + 3869 0066 0022 movs r2, #0 + 3870 0068 1A61 str r2, [r3, #16] + 3871 .L242: +1098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } +1099:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** + ARM GAS /tmp/ccSuWkwR.s page 108 + + +1100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> POSITION_VAL(RC + 3872 .loc 1 1100 59 + 3873 006a 2B4B ldr r3, .L251 + 3874 006c 1B68 ldr r3, [r3] + 3875 .loc 1 1100 64 + 3876 006e 03F0F803 and r3, r3, #248 + 3877 0072 F822 movs r2, #248 + 3878 0074 FA60 str r2, [r7, #12] + 3879 .LBB333: + 3880 .LBB334: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 3881 .loc 2 988 4 + 3882 0076 FA68 ldr r2, [r7, #12] + 3883 .syntax unified + 3884 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 3885 0078 92FAA2F2 rbit r2, r2 + 3886 @ 0 "" 2 + 3887 .thumb + 3888 .syntax unified + 3889 007c BA60 str r2, [r7, #8] + 3890 .loc 2 1001 10 + 3891 007e BA68 ldr r2, [r7, #8] + 3892 .LBE334: + 3893 .LBE333: + 3894 .loc 1 1100 85 discriminator 1 + 3895 0080 B2FA82F2 clz r2, r2 + 3896 .loc 1 1100 85 is_stmt 0 discriminator 2 + 3897 0084 D2B2 uxtb r2, r2 + 3898 .loc 1 1100 44 is_stmt 1 discriminator 2 + 3899 0086 23FA02F2 lsr r2, r3, r2 + 3900 .loc 1 1100 42 discriminator 2 + 3901 008a 7B68 ldr r3, [r7, #4] + 3902 008c 5A61 str r2, [r3, #20] +1101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** +1102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get the LSE configuration -----------------------------------------------*/ +1103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) + 3903 .loc 1 1103 10 + 3904 008e 224B ldr r3, .L251 + 3905 0090 1B6A ldr r3, [r3, #32] + 3906 .loc 1 1103 17 + 3907 0092 03F00403 and r3, r3, #4 + 3908 .loc 1 1103 5 + 3909 0096 042B cmp r3, #4 + 3910 0098 03D1 bne .L244 +1104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { +1105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; + 3911 .loc 1 1105 33 + 3912 009a 7B68 ldr r3, [r7, #4] + 3913 009c 0522 movs r2, #5 + 3914 009e DA60 str r2, [r3, #12] + 3915 00a0 0CE0 b .L245 + 3916 .L244: +1106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } +1107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON) + 3917 .loc 1 1107 15 + 3918 00a2 1D4B ldr r3, .L251 + 3919 00a4 1B6A ldr r3, [r3, #32] + ARM GAS /tmp/ccSuWkwR.s page 109 + + + 3920 .loc 1 1107 22 + 3921 00a6 03F00103 and r3, r3, #1 + 3922 .loc 1 1107 10 + 3923 00aa 012B cmp r3, #1 + 3924 00ac 03D1 bne .L246 +1108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { +1109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->LSEState = RCC_LSE_ON; + 3925 .loc 1 1109 33 + 3926 00ae 7B68 ldr r3, [r7, #4] + 3927 00b0 0122 movs r2, #1 + 3928 00b2 DA60 str r2, [r3, #12] + 3929 00b4 02E0 b .L245 + 3930 .L246: +1110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } +1111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else +1112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { +1113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->LSEState = RCC_LSE_OFF; + 3931 .loc 1 1113 33 + 3932 00b6 7B68 ldr r3, [r7, #4] + 3933 00b8 0022 movs r2, #0 + 3934 00ba DA60 str r2, [r3, #12] + 3935 .L245: +1114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } +1115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** +1116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get the LSI configuration -----------------------------------------------*/ +1117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION) + 3936 .loc 1 1117 10 + 3937 00bc 164B ldr r3, .L251 + 3938 00be 5B6A ldr r3, [r3, #36] + 3939 .loc 1 1117 16 + 3940 00c0 03F00103 and r3, r3, #1 + 3941 .loc 1 1117 5 + 3942 00c4 012B cmp r3, #1 + 3943 00c6 03D1 bne .L247 +1118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { +1119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->LSIState = RCC_LSI_ON; + 3944 .loc 1 1119 33 + 3945 00c8 7B68 ldr r3, [r7, #4] + 3946 00ca 0122 movs r2, #1 + 3947 00cc 9A61 str r2, [r3, #24] + 3948 00ce 02E0 b .L248 + 3949 .L247: +1120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } +1121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else +1122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { +1123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->LSIState = RCC_LSI_OFF; + 3950 .loc 1 1123 33 + 3951 00d0 7B68 ldr r3, [r7, #4] + 3952 00d2 0022 movs r2, #0 + 3953 00d4 9A61 str r2, [r3, #24] + 3954 .L248: +1124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } +1125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** +1126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** +1127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get the PLL configuration -----------------------------------------------*/ +1128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON) + 3955 .loc 1 1128 10 + ARM GAS /tmp/ccSuWkwR.s page 110 + + + 3956 00d6 104B ldr r3, .L251 + 3957 00d8 1B68 ldr r3, [r3] + 3958 .loc 1 1128 15 + 3959 00da 03F08073 and r3, r3, #16777216 + 3960 .loc 1 1128 5 + 3961 00de B3F1807F cmp r3, #16777216 + 3962 00e2 03D1 bne .L249 +1129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { +1130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; + 3963 .loc 1 1130 37 + 3964 00e4 7B68 ldr r3, [r7, #4] + 3965 00e6 0222 movs r2, #2 + 3966 00e8 DA61 str r2, [r3, #28] + 3967 00ea 02E0 b .L250 + 3968 .L249: +1131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } +1132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** else +1133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { +1134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; + 3969 .loc 1 1134 37 + 3970 00ec 7B68 ldr r3, [r7, #4] + 3971 00ee 0122 movs r2, #1 + 3972 00f0 DA61 str r2, [r3, #28] + 3973 .L250: +1135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } +1136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC); + 3974 .loc 1 1136 52 + 3975 00f2 094B ldr r3, .L251 + 3976 00f4 5B68 ldr r3, [r3, #4] + 3977 .loc 1 1136 38 + 3978 00f6 03F48032 and r2, r3, #65536 + 3979 .loc 1 1136 36 + 3980 00fa 7B68 ldr r3, [r7, #4] + 3981 00fc 1A62 str r2, [r3, #32] +1137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMUL); + 3982 .loc 1 1137 49 + 3983 00fe 064B ldr r3, .L251 + 3984 0100 5B68 ldr r3, [r3, #4] + 3985 .loc 1 1137 35 + 3986 0102 03F47012 and r2, r3, #3932160 + 3987 .loc 1 1137 33 + 3988 0106 7B68 ldr r3, [r7, #4] + 3989 0108 5A62 str r2, [r3, #36] +1138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV) +1139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_OscInitStruct->PLL.PREDIV = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV); +1140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** #endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */ +1141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 3990 .loc 1 1141 1 + 3991 010a 00BF nop + 3992 010c 1437 adds r7, r7, #20 + 3993 .cfi_def_cfa_offset 4 + 3994 010e BD46 mov sp, r7 + 3995 .cfi_def_cfa_register 13 + 3996 @ sp needed + 3997 0110 5DF8047B ldr r7, [sp], #4 + 3998 .cfi_restore 7 + 3999 .cfi_def_cfa_offset 0 + ARM GAS /tmp/ccSuWkwR.s page 111 + + + 4000 0114 7047 bx lr + 4001 .L252: + 4002 0116 00BF .align 2 + 4003 .L251: + 4004 0118 00100240 .word 1073876992 + 4005 .cfi_endproc + 4006 .LFE140: + 4008 .section .text.HAL_RCC_GetClockConfig,"ax",%progbits + 4009 .align 1 + 4010 .global HAL_RCC_GetClockConfig + 4011 .syntax unified + 4012 .thumb + 4013 .thumb_func + 4015 HAL_RCC_GetClockConfig: + 4016 .LFB141: +1142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** +1143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** +1144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief Get the RCC_ClkInitStruct according to the internal +1145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * RCC configuration registers. +1146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that +1147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * contains the current clock configuration. +1148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @param pFLatency Pointer on the Flash Latency. +1149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @retval None +1150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ +1151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) +1152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 4017 .loc 1 1152 1 + 4018 .cfi_startproc + 4019 @ args = 0, pretend = 0, frame = 8 + 4020 @ frame_needed = 1, uses_anonymous_args = 0 + 4021 @ link register save eliminated. + 4022 0000 80B4 push {r7} + 4023 .cfi_def_cfa_offset 4 + 4024 .cfi_offset 7, -4 + 4025 0002 83B0 sub sp, sp, #12 + 4026 .cfi_def_cfa_offset 16 + 4027 0004 00AF add r7, sp, #0 + 4028 .cfi_def_cfa_register 7 + 4029 0006 7860 str r0, [r7, #4] + 4030 0008 3960 str r1, [r7] +1153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check the parameters */ +1154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(RCC_ClkInitStruct != NULL); +1155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** assert_param(pFLatency != NULL); +1156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** +1157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Set all possible values for the Clock type parameter --------------------*/ +1158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | + 4031 .loc 1 1158 32 + 4032 000a 7B68 ldr r3, [r7, #4] + 4033 000c 0F22 movs r2, #15 + 4034 000e 1A60 str r2, [r3] +1159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** +1160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get the SYSCLK configuration --------------------------------------------*/ +1161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); + 4035 .loc 1 1161 51 + 4036 0010 124B ldr r3, .L254 + 4037 0012 5B68 ldr r3, [r3, #4] + 4038 .loc 1 1161 37 + ARM GAS /tmp/ccSuWkwR.s page 112 + + + 4039 0014 03F00302 and r2, r3, #3 + 4040 .loc 1 1161 35 + 4041 0018 7B68 ldr r3, [r7, #4] + 4042 001a 5A60 str r2, [r3, #4] +1162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** +1163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get the HCLK configuration ----------------------------------------------*/ +1164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); + 4043 .loc 1 1164 52 + 4044 001c 0F4B ldr r3, .L254 + 4045 001e 5B68 ldr r3, [r3, #4] + 4046 .loc 1 1164 38 + 4047 0020 03F0F002 and r2, r3, #240 + 4048 .loc 1 1164 36 + 4049 0024 7B68 ldr r3, [r7, #4] + 4050 0026 9A60 str r2, [r3, #8] +1165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** +1166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get the APB1 configuration ----------------------------------------------*/ +1167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); + 4051 .loc 1 1167 53 + 4052 0028 0C4B ldr r3, .L254 + 4053 002a 5B68 ldr r3, [r3, #4] + 4054 .loc 1 1167 39 + 4055 002c 03F4E062 and r2, r3, #1792 + 4056 .loc 1 1167 37 + 4057 0030 7B68 ldr r3, [r7, #4] + 4058 0032 DA60 str r2, [r3, #12] +1168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** +1169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get the APB2 configuration ----------------------------------------------*/ +1170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U); + 4059 .loc 1 1170 54 + 4060 0034 094B ldr r3, .L254 + 4061 0036 5B68 ldr r3, [r3, #4] + 4062 .loc 1 1170 39 + 4063 0038 DB08 lsrs r3, r3, #3 + 4064 003a 03F4E062 and r2, r3, #1792 + 4065 .loc 1 1170 37 + 4066 003e 7B68 ldr r3, [r7, #4] + 4067 0040 1A61 str r2, [r3, #16] +1171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** +1172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Get the Flash Wait State (Latency) configuration ------------------------*/ +1173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); + 4068 .loc 1 1173 32 + 4069 0042 074B ldr r3, .L254+4 + 4070 0044 1B68 ldr r3, [r3] + 4071 .loc 1 1173 16 + 4072 0046 03F00702 and r2, r3, #7 + 4073 .loc 1 1173 14 + 4074 004a 3B68 ldr r3, [r7] + 4075 004c 1A60 str r2, [r3] +1174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 4076 .loc 1 1174 1 + 4077 004e 00BF nop + 4078 0050 0C37 adds r7, r7, #12 + 4079 .cfi_def_cfa_offset 4 + 4080 0052 BD46 mov sp, r7 + 4081 .cfi_def_cfa_register 13 + 4082 @ sp needed + ARM GAS /tmp/ccSuWkwR.s page 113 + + + 4083 0054 5DF8047B ldr r7, [sp], #4 + 4084 .cfi_restore 7 + 4085 .cfi_def_cfa_offset 0 + 4086 0058 7047 bx lr + 4087 .L255: + 4088 005a 00BF .align 2 + 4089 .L254: + 4090 005c 00100240 .word 1073876992 + 4091 0060 00200240 .word 1073881088 + 4092 .cfi_endproc + 4093 .LFE141: + 4095 .section .text.HAL_RCC_NMI_IRQHandler,"ax",%progbits + 4096 .align 1 + 4097 .global HAL_RCC_NMI_IRQHandler + 4098 .syntax unified + 4099 .thumb + 4100 .thumb_func + 4102 HAL_RCC_NMI_IRQHandler: + 4103 .LFB142: +1175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** +1176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** +1177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief This function handles the RCC CSS interrupt request. +1178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @note This API should be called under the NMI_Handler(). +1179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @retval None +1180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ +1181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** void HAL_RCC_NMI_IRQHandler(void) +1182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 4104 .loc 1 1182 1 + 4105 .cfi_startproc + 4106 @ args = 0, pretend = 0, frame = 0 + 4107 @ frame_needed = 1, uses_anonymous_args = 0 + 4108 0000 80B5 push {r7, lr} + 4109 .cfi_def_cfa_offset 8 + 4110 .cfi_offset 7, -8 + 4111 .cfi_offset 14, -4 + 4112 0002 00AF add r7, sp, #0 + 4113 .cfi_def_cfa_register 7 +1183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Check RCC CSSF flag */ +1184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** if(__HAL_RCC_GET_IT(RCC_IT_CSS)) + 4114 .loc 1 1184 6 + 4115 0004 064B ldr r3, .L259 + 4116 0006 9B68 ldr r3, [r3, #8] + 4117 0008 03F08003 and r3, r3, #128 + 4118 .loc 1 1184 5 + 4119 000c 802B cmp r3, #128 + 4120 000e 04D1 bne .L258 +1185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { +1186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* RCC Clock Security System interrupt user callback */ +1187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** HAL_RCC_CSSCallback(); + 4121 .loc 1 1187 5 + 4122 0010 FFF7FEFF bl HAL_RCC_CSSCallback +1188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** +1189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* Clear RCC CSS pending bit */ +1190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __HAL_RCC_CLEAR_IT(RCC_IT_CSS); + 4123 .loc 1 1190 5 + 4124 0014 034B ldr r3, .L259+4 + 4125 0016 8022 movs r2, #128 + ARM GAS /tmp/ccSuWkwR.s page 114 + + + 4126 0018 1A70 strb r2, [r3] + 4127 .L258: +1191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } +1192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 4128 .loc 1 1192 1 + 4129 001a 00BF nop + 4130 001c 80BD pop {r7, pc} + 4131 .L260: + 4132 001e 00BF .align 2 + 4133 .L259: + 4134 0020 00100240 .word 1073876992 + 4135 0024 0A100240 .word 1073877002 + 4136 .cfi_endproc + 4137 .LFE142: + 4139 .section .text.HAL_RCC_CSSCallback,"ax",%progbits + 4140 .align 1 + 4141 .weak HAL_RCC_CSSCallback + 4142 .syntax unified + 4143 .thumb + 4144 .thumb_func + 4146 HAL_RCC_CSSCallback: + 4147 .LFB143: +1193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** +1194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /** +1195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @brief RCC Clock Security System interrupt callback +1196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** * @retval none +1197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ +1198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** __weak void HAL_RCC_CSSCallback(void) +1199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** { + 4148 .loc 1 1199 1 + 4149 .cfi_startproc + 4150 @ args = 0, pretend = 0, frame = 0 + 4151 @ frame_needed = 1, uses_anonymous_args = 0 + 4152 @ link register save eliminated. + 4153 0000 80B4 push {r7} + 4154 .cfi_def_cfa_offset 4 + 4155 .cfi_offset 7, -4 + 4156 0002 00AF add r7, sp, #0 + 4157 .cfi_def_cfa_register 7 +1200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** /* NOTE : This function Should not be modified, when the callback is needed, +1201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** the HAL_RCC_CSSCallback could be implemented in the user file +1202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** */ +1203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc.c **** } + 4158 .loc 1 1203 1 + 4159 0004 00BF nop + 4160 0006 BD46 mov sp, r7 + 4161 .cfi_def_cfa_register 13 + 4162 @ sp needed + 4163 0008 5DF8047B ldr r7, [sp], #4 + 4164 .cfi_restore 7 + 4165 .cfi_def_cfa_offset 0 + 4166 000c 7047 bx lr + 4167 .cfi_endproc + 4168 .LFE143: + 4170 .text + 4171 .Letext0: + 4172 .file 3 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + ARM GAS /tmp/ccSuWkwR.s page 115 + + + 4173 .file 4 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 4174 .file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h" + 4175 .file 6 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + 4176 .file 7 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h" + 4177 .file 8 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h" + 4178 .file 9 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h" + 4179 .file 10 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h" + 4180 .file 11 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h" + ARM GAS /tmp/ccSuWkwR.s page 116 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f3xx_hal_rcc.c + /tmp/ccSuWkwR.s:21 .rodata.aPLLMULFactorTable:00000000 $d + /tmp/ccSuWkwR.s:24 .rodata.aPLLMULFactorTable:00000000 aPLLMULFactorTable + /tmp/ccSuWkwR.s:28 .rodata.aPredivFactorTable:00000000 $d + /tmp/ccSuWkwR.s:31 .rodata.aPredivFactorTable:00000000 aPredivFactorTable + /tmp/ccSuWkwR.s:35 .text.HAL_RCC_DeInit:00000000 $t + /tmp/ccSuWkwR.s:41 .text.HAL_RCC_DeInit:00000000 HAL_RCC_DeInit + /tmp/ccSuWkwR.s:252 .text.HAL_RCC_DeInit:00000130 $d + /tmp/ccSuWkwR.s:262 .text.HAL_RCC_OscConfig:00000000 $t + /tmp/ccSuWkwR.s:268 .text.HAL_RCC_OscConfig:00000000 HAL_RCC_OscConfig + /tmp/ccSuWkwR.s:742 .text.HAL_RCC_OscConfig:00000310 $d + /tmp/ccSuWkwR.s:745 .text.HAL_RCC_OscConfig:00000314 $t + /tmp/ccSuWkwR.s:1290 .text.HAL_RCC_OscConfig:00000660 $d + /tmp/ccSuWkwR.s:1294 .text.HAL_RCC_OscConfig:00000668 $t + /tmp/ccSuWkwR.s:1740 .text.HAL_RCC_OscConfig:0000099c $d + /tmp/ccSuWkwR.s:1744 .text.HAL_RCC_OscConfig:000009a8 $t + /tmp/ccSuWkwR.s:2136 .text.HAL_RCC_OscConfig:00000c6c $d + /tmp/ccSuWkwR.s:2138 .text.HAL_RCC_OscConfig:00000c70 $t + /tmp/ccSuWkwR.s:2601 .text.HAL_RCC_OscConfig:00000fcc $d + /tmp/ccSuWkwR.s:2604 .text.HAL_RCC_OscConfig:00000fd0 $t + /tmp/ccSuWkwR.s:2649 .text.HAL_RCC_OscConfig:00001018 $d + /tmp/ccSuWkwR.s:2654 .text.HAL_RCC_ClockConfig:00000000 $t + /tmp/ccSuWkwR.s:2660 .text.HAL_RCC_ClockConfig:00000000 HAL_RCC_ClockConfig + /tmp/ccSuWkwR.s:3110 .text.HAL_RCC_ClockConfig:00000240 $d + /tmp/ccSuWkwR.s:3114 .text.HAL_RCC_ClockConfig:00000248 $t + /tmp/ccSuWkwR.s:3430 .text.HAL_RCC_GetSysClockFreq:00000000 HAL_RCC_GetSysClockFreq + /tmp/ccSuWkwR.s:3208 .text.HAL_RCC_ClockConfig:000002cc $d + /tmp/ccSuWkwR.s:3216 .text.HAL_RCC_MCOConfig:00000000 $t + /tmp/ccSuWkwR.s:3222 .text.HAL_RCC_MCOConfig:00000000 HAL_RCC_MCOConfig + /tmp/ccSuWkwR.s:3291 .text.HAL_RCC_MCOConfig:00000060 $d + /tmp/ccSuWkwR.s:3296 .text.HAL_RCC_EnableCSS:00000000 $t + /tmp/ccSuWkwR.s:3302 .text.HAL_RCC_EnableCSS:00000000 HAL_RCC_EnableCSS + /tmp/ccSuWkwR.s:3360 .text.HAL_RCC_DisableCSS:00000000 $t + /tmp/ccSuWkwR.s:3366 .text.HAL_RCC_DisableCSS:00000000 HAL_RCC_DisableCSS + /tmp/ccSuWkwR.s:3424 .text.HAL_RCC_GetSysClockFreq:00000000 $t + /tmp/ccSuWkwR.s:3594 .text.HAL_RCC_GetSysClockFreq:000000c0 $d + /tmp/ccSuWkwR.s:3604 .text.HAL_RCC_GetHCLKFreq:00000000 $t + /tmp/ccSuWkwR.s:3610 .text.HAL_RCC_GetHCLKFreq:00000000 HAL_RCC_GetHCLKFreq + /tmp/ccSuWkwR.s:3637 .text.HAL_RCC_GetHCLKFreq:00000014 $d + /tmp/ccSuWkwR.s:3642 .text.HAL_RCC_GetPCLK1Freq:00000000 $t + /tmp/ccSuWkwR.s:3648 .text.HAL_RCC_GetPCLK1Freq:00000000 HAL_RCC_GetPCLK1Freq + /tmp/ccSuWkwR.s:3709 .text.HAL_RCC_GetPCLK1Freq:0000003c $d + /tmp/ccSuWkwR.s:3715 .text.HAL_RCC_GetPCLK2Freq:00000000 $t + /tmp/ccSuWkwR.s:3721 .text.HAL_RCC_GetPCLK2Freq:00000000 HAL_RCC_GetPCLK2Freq + /tmp/ccSuWkwR.s:3782 .text.HAL_RCC_GetPCLK2Freq:0000003c $d + /tmp/ccSuWkwR.s:3788 .text.HAL_RCC_GetOscConfig:00000000 $t + /tmp/ccSuWkwR.s:3794 .text.HAL_RCC_GetOscConfig:00000000 HAL_RCC_GetOscConfig + /tmp/ccSuWkwR.s:4004 .text.HAL_RCC_GetOscConfig:00000118 $d + /tmp/ccSuWkwR.s:4009 .text.HAL_RCC_GetClockConfig:00000000 $t + /tmp/ccSuWkwR.s:4015 .text.HAL_RCC_GetClockConfig:00000000 HAL_RCC_GetClockConfig + /tmp/ccSuWkwR.s:4090 .text.HAL_RCC_GetClockConfig:0000005c $d + /tmp/ccSuWkwR.s:4096 .text.HAL_RCC_NMI_IRQHandler:00000000 $t + /tmp/ccSuWkwR.s:4102 .text.HAL_RCC_NMI_IRQHandler:00000000 HAL_RCC_NMI_IRQHandler + /tmp/ccSuWkwR.s:4146 .text.HAL_RCC_CSSCallback:00000000 HAL_RCC_CSSCallback + /tmp/ccSuWkwR.s:4134 .text.HAL_RCC_NMI_IRQHandler:00000020 $d + /tmp/ccSuWkwR.s:4140 .text.HAL_RCC_CSSCallback:00000000 $t + ARM GAS /tmp/ccSuWkwR.s page 117 + + + +UNDEFINED SYMBOLS +HAL_GetTick +HAL_InitTick +SystemCoreClock +uwTickPrio +AHBPrescTable +HAL_GPIO_Init +APBPrescTable diff --git a/Software/build/stm32f3xx_hal_rcc.o b/Software/build/stm32f3xx_hal_rcc.o new file mode 100644 index 0000000..f6f4963 Binary files /dev/null and b/Software/build/stm32f3xx_hal_rcc.o differ diff --git a/Software/build/stm32f3xx_hal_rcc_ex.d b/Software/build/stm32f3xx_hal_rcc_ex.d new file mode 100644 index 0000000..370abcc --- /dev/null +++ b/Software/build/stm32f3xx_hal_rcc_ex.d @@ -0,0 +1,62 @@ +build/stm32f3xx_hal_rcc_ex.o: \ + Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + Core/Inc/stm32f3xx_hal_conf.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h: diff --git a/Software/build/stm32f3xx_hal_rcc_ex.lst b/Software/build/stm32f3xx_hal_rcc_ex.lst new file mode 100644 index 0000000..b17eb98 --- /dev/null +++ b/Software/build/stm32f3xx_hal_rcc_ex.lst @@ -0,0 +1,4665 @@ +ARM GAS /tmp/ccwmaYtI.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 6 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "stm32f3xx_hal_rcc_ex.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c" + 20 .section .text.HAL_RCCEx_PeriphCLKConfig,"ax",%progbits + 21 .align 1 + 22 .global HAL_RCCEx_PeriphCLKConfig + 23 .syntax unified + 24 .thumb + 25 .thumb_func + 27 HAL_RCCEx_PeriphCLKConfig: + 28 .LFB130: + 1:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /** + 2:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** ****************************************************************************** + 3:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @file stm32f3xx_hal_rcc_ex.c + 4:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @author MCD Application Team + 5:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @brief Extended RCC HAL module driver. + 6:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * functionalities RCC extension peripheral: + 8:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * + Extended Peripheral Control functions + 9:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * + 10:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** ****************************************************************************** + 11:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @attention + 12:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * + 13:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * Copyright (c) 2016 STMicroelectronics. + 14:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * All rights reserved. + 15:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * + 16:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * This software is licensed under terms that can be found in the LICENSE file in + 17:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * the root directory of this software component. + 18:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 19:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** ****************************************************************************** + 20:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** */ + 21:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 22:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Includes ------------------------------------------------------------------*/ + 23:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #include "stm32f3xx_hal.h" + 24:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 25:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /** @addtogroup STM32F3xx_HAL_Driver + 26:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @{ + 27:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** */ + 28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #ifdef HAL_RCC_MODULE_ENABLED + 30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + ARM GAS /tmp/ccwmaYtI.s page 2 + + + 31:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /** @defgroup RCCEx RCCEx + 32:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @brief RCC Extension HAL module driver. + 33:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @{ + 34:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** */ + 35:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 36:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Private typedef -----------------------------------------------------------*/ + 37:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Private define ------------------------------------------------------------*/ + 38:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Private macro -------------------------------------------------------------*/ + 39:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /** @defgroup RCCEx_Private_Macros RCCEx Private Macros + 40:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @{ + 41:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** */ + 42:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /** + 43:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @} + 44:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** */ + 45:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 46:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Private variables ---------------------------------------------------------*/ + 47:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Private function prototypes -----------------------------------------------*/ + 48:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Private functions ---------------------------------------------------------*/ + 49:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34) || de + 50:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(RCC_CFGR3_TIM1SW) || defined(RCC_CFGR3_TIM2SW) || defined(RCC_CFGR3_TIM8SW) || defined( + 51:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(RCC_CFGR3_TIM16SW) || defined(RCC_CFGR3_TIM17SW) || defined(RCC_CFGR3_TIM20SW) || defin + 52:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(RCC_CFGR3_HRTIM1SW) + 53:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /** @defgroup RCCEx_Private_Functions RCCEx Private Functions + 54:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @{ + 55:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** */ + 56:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** static uint32_t RCC_GetPLLCLKFreq(void); + 57:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 58:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /** + 59:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @} + 60:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** */ + 61:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRExx || RCC_CFGR3_TIMxSW || RCC_CFGR3_HRTIM1SW || RCC + 62:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 63:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions + 64:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @{ + 65:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** */ + 66:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 67:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions + 68:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @brief Extended Peripheral Control functions + 69:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * + 70:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @verbatim + 71:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** =============================================================================== + 72:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** ##### Extended Peripheral Control functions ##### + 73:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** =============================================================================== + 74:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** [..] + 75:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** This subsection provides a set of functions allowing to control the RCC Clocks + 76:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequencies. + 77:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** [..] + 78:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to + 79:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** select the RTC clock source; in this case the Backup domain will be reset in + 80:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** order to modify the RTC Clock source, as consequence RTC registers (including + 81:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** the backup registers) are set to their reset values. + 82:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 83:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @endverbatim + 84:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @{ + 85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** */ + 86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /** + ARM GAS /tmp/ccwmaYtI.s page 3 + + + 88:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @brief Initializes the RCC extended peripherals clocks according to the specified + 89:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * parameters in the RCC_PeriphCLKInitTypeDef. + 90:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + 91:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * contains the configuration information for the Extended Peripherals clocks + 92:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * (ADC, CEC, I2C, I2S, SDADC, HRTIM, TIM, USART, RTC and USB). + 93:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * + 94:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + 95:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * the RTC clock source; in this case the Backup domain will be reset in + 96:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * order to modify the RTC Clock source, as consequence RTC registers (including + 97:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * the backup registers) and RCC_BDCR register are set to their reset values. + 98:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * + 99:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @note When the TIMx clock source is APB clock, so the TIMx clock is APB clock or + 100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * APB clock x 2 depending on the APB prescaler. + 101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * When the TIMx clock source is PLL clock, so the TIMx clock is PLL clock x 2. + 102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * + 103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @retval HAL status + 104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** */ + 105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) + 106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 29 .loc 1 106 1 + 30 .cfi_startproc + 31 @ args = 0, pretend = 0, frame = 72 + 32 @ frame_needed = 1, uses_anonymous_args = 0 + 33 0000 80B5 push {r7, lr} + 34 .cfi_def_cfa_offset 8 + 35 .cfi_offset 7, -8 + 36 .cfi_offset 14, -4 + 37 0002 92B0 sub sp, sp, #72 + 38 .cfi_def_cfa_offset 80 + 39 0004 00AF add r7, sp, #0 + 40 .cfi_def_cfa_register 7 + 41 0006 7860 str r0, [r7, #4] + 107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** uint32_t tickstart = 0U; + 42 .loc 1 107 12 + 43 0008 0023 movs r3, #0 + 44 000a 3B64 str r3, [r7, #64] + 108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** uint32_t temp_reg = 0U; + 45 .loc 1 108 12 + 46 000c 0023 movs r3, #0 + 47 000e FB63 str r3, [r7, #60] + 109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** FlagStatus pwrclkchanged = RESET; + 48 .loc 1 109 20 + 49 0010 0023 movs r3, #0 + 50 0012 87F84730 strb r3, [r7, #71] + 110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + 113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*---------------------------- RTC configuration -------------------------------*/ + 115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) + 51 .loc 1 115 21 + 52 0016 7B68 ldr r3, [r7, #4] + 53 0018 1B68 ldr r3, [r3] + 54 .loc 1 115 45 + 55 001a 03F48033 and r3, r3, #65536 + 56 .loc 1 115 5 + 57 001e 002B cmp r3, #0 + ARM GAS /tmp/ccwmaYtI.s page 4 + + + 58 0020 00F0D280 beq .L2 + 116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* check for RTC Parameters used to output RTCCLK */ + 118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + 119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* As soon as function is called to change RTC clock source, activation of the + 122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** power domain is done. */ + 123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Requires to enable write access to Backup Domain of necessary */ + 124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + 59 .loc 1 124 8 + 60 0024 4D4B ldr r3, .L30 + 61 0026 DB69 ldr r3, [r3, #28] + 62 0028 03F08053 and r3, r3, #268435456 + 63 .loc 1 124 7 + 64 002c 002B cmp r3, #0 + 65 002e 0ED1 bne .L3 + 66 .LBB17: + 125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_PWR_CLK_ENABLE(); + 67 .loc 1 126 7 + 68 0030 4A4B ldr r3, .L30 + 69 0032 DB69 ldr r3, [r3, #28] + 70 0034 494A ldr r2, .L30 + 71 0036 43F08053 orr r3, r3, #268435456 + 72 003a D361 str r3, [r2, #28] + 73 003c 474B ldr r3, .L30 + 74 003e DB69 ldr r3, [r3, #28] + 75 0040 03F08053 and r3, r3, #268435456 + 76 0044 BB60 str r3, [r7, #8] + 77 0046 BB68 ldr r3, [r7, #8] + 78 .LBE17: + 127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** pwrclkchanged = SET; + 79 .loc 1 127 21 + 80 0048 0123 movs r3, #1 + 81 004a 87F84730 strb r3, [r7, #71] + 82 .L3: + 128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 83 .loc 1 130 8 + 84 004e 444B ldr r3, .L30+4 + 85 0050 1B68 ldr r3, [r3] + 86 0052 03F48073 and r3, r3, #256 + 87 .loc 1 130 7 + 88 0056 002B cmp r3, #0 + 89 0058 18D1 bne .L4 + 131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Enable write access to Backup domain */ + 133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** SET_BIT(PWR->CR, PWR_CR_DBP); + 90 .loc 1 133 7 + 91 005a 414B ldr r3, .L30+4 + 92 005c 1B68 ldr r3, [r3] + 93 005e 404A ldr r2, .L30+4 + 94 0060 43F48073 orr r3, r3, #256 + 95 0064 1360 str r3, [r2] + 134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + ARM GAS /tmp/ccwmaYtI.s page 5 + + + 135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Wait for Backup domain Write protection disable */ + 136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** tickstart = HAL_GetTick(); + 96 .loc 1 136 19 + 97 0066 FFF7FEFF bl HAL_GetTick + 98 006a 3864 str r0, [r7, #64] + 137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 99 .loc 1 138 12 + 100 006c 08E0 b .L5 + 101 .L7: + 139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 102 .loc 1 140 15 + 103 006e FFF7FEFF bl HAL_GetTick + 104 0072 0246 mov r2, r0 + 105 .loc 1 140 29 discriminator 1 + 106 0074 3B6C ldr r3, [r7, #64] + 107 0076 D31A subs r3, r2, r3 + 108 .loc 1 140 13 discriminator 1 + 109 0078 642B cmp r3, #100 + 110 007a 01D9 bls .L5 + 141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** return HAL_TIMEOUT; + 111 .loc 1 142 18 + 112 007c 0323 movs r3, #3 + 113 007e 49E1 b .L6 + 114 .L5: + 138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 115 .loc 1 138 13 + 116 0080 374B ldr r3, .L30+4 + 117 0082 1B68 ldr r3, [r3] + 118 0084 03F48073 and r3, r3, #256 + 119 0088 002B cmp r3, #0 + 120 008a F0D0 beq .L7 + 121 .L4: + 143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value + 148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL); + 122 .loc 1 148 20 + 123 008c 334B ldr r3, .L30 + 124 008e 1B6A ldr r3, [r3, #32] + 125 .loc 1 148 14 + 126 0090 03F44073 and r3, r3, #768 + 127 0094 FB63 str r3, [r7, #60] + 149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSE + 128 .loc 1 149 7 + 129 0096 FB6B ldr r3, [r7, #60] + 130 0098 002B cmp r3, #0 + 131 009a 00F08280 beq .L8 + 132 .loc 1 149 64 discriminator 1 + 133 009e 7B68 ldr r3, [r7, #4] + 134 00a0 5B68 ldr r3, [r3, #4] + 135 .loc 1 149 84 discriminator 1 + 136 00a2 03F44073 and r3, r3, #768 + ARM GAS /tmp/ccwmaYtI.s page 6 + + + 137 .loc 1 149 34 discriminator 1 + 138 00a6 FA6B ldr r2, [r7, #60] + 139 00a8 9A42 cmp r2, r3 + 140 00aa 7AD0 beq .L8 + 150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Store the content of BDCR register before the reset of Backup Domain */ + 152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + 141 .loc 1 152 22 + 142 00ac 2B4B ldr r3, .L30 + 143 00ae 1B6A ldr r3, [r3, #32] + 144 .loc 1 152 16 + 145 00b0 23F44073 bic r3, r3, #768 + 146 00b4 FB63 str r3, [r7, #60] + 147 00b6 4FF48033 mov r3, #65536 + 148 00ba 3B63 str r3, [r7, #48] + 149 .LBB18: + 150 .LBB19: + 151 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h" + 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** + 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h + 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file + 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.0.4 + 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 09. April 2018 + 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ + 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* + 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 + 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may + 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. + 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at + 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 + 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * + 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software + 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT + 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and + 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. + 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 24:Drivers/CMSIS/Include/cmsis_gcc.h **** + 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H + 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H + 27:Drivers/CMSIS/Include/cmsis_gcc.h **** + 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ + 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" + 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" + 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" + 33:Drivers/CMSIS/Include/cmsis_gcc.h **** + 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ + 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin + 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) + 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 38:Drivers/CMSIS/Include/cmsis_gcc.h **** + 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ + ARM GAS /tmp/ccwmaYtI.s page 7 + + + 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM + 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm + 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE + 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline + 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE + 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline + 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE + 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline + 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN + 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) + 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED + 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) + 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK + 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) + 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED + 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) + 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT + 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION + 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) + 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ + 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE + 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- + 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ + 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add + 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE + 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + ARM GAS /tmp/ccwmaYtI.s page 8 + + + 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- + 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ + 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push + 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" + 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" + 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop + 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add + 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED + 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) + 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT + 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict + 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 116:Drivers/CMSIS/Include/cmsis_gcc.h **** + 117:Drivers/CMSIS/Include/cmsis_gcc.h **** + 118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ + 119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface + 120:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + 121:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 122:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 123:Drivers/CMSIS/Include/cmsis_gcc.h **** + 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts + 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + 127:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 128:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) + 130:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); + 132:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 133:Drivers/CMSIS/Include/cmsis_gcc.h **** + 134:Drivers/CMSIS/Include/cmsis_gcc.h **** + 135:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 136:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts + 137:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. + 138:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 139:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) + 141:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 142:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); + 143:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 144:Drivers/CMSIS/Include/cmsis_gcc.h **** + 145:Drivers/CMSIS/Include/cmsis_gcc.h **** + 146:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 147:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register + 148:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the Control Register. + 149:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Control Register value + 150:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 151:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) + 152:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 153:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + ARM GAS /tmp/ccwmaYtI.s page 9 + + + 154:Drivers/CMSIS/Include/cmsis_gcc.h **** + 155:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control" : "=r" (result) ); + 156:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 157:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 158:Drivers/CMSIS/Include/cmsis_gcc.h **** + 159:Drivers/CMSIS/Include/cmsis_gcc.h **** + 160:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 161:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 162:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Control Register (non-secure) + 163:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the non-secure Control Register when in secure mode. + 164:Drivers/CMSIS/Include/cmsis_gcc.h **** \return non-secure Control Register value + 165:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 166:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) + 167:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 168:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 169:Drivers/CMSIS/Include/cmsis_gcc.h **** + 170:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + 171:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 172:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 174:Drivers/CMSIS/Include/cmsis_gcc.h **** + 175:Drivers/CMSIS/Include/cmsis_gcc.h **** + 176:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 177:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register + 178:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the Control Register. + 179:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 180:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 181:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) + 182:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 183:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + 184:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 185:Drivers/CMSIS/Include/cmsis_gcc.h **** + 186:Drivers/CMSIS/Include/cmsis_gcc.h **** + 187:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 188:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 189:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Control Register (non-secure) + 190:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Writes the given value to the non-secure Control Register when in secure state. + 191:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] control Control Register value to set + 192:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 193:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) + 194:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 195:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + 196:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 197:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 198:Drivers/CMSIS/Include/cmsis_gcc.h **** + 199:Drivers/CMSIS/Include/cmsis_gcc.h **** + 200:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 201:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get IPSR Register + 202:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the IPSR Register. + 203:Drivers/CMSIS/Include/cmsis_gcc.h **** \return IPSR Register value + 204:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 205:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void) + 206:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 207:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 208:Drivers/CMSIS/Include/cmsis_gcc.h **** + 209:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 210:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + ARM GAS /tmp/ccwmaYtI.s page 10 + + + 211:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 212:Drivers/CMSIS/Include/cmsis_gcc.h **** + 213:Drivers/CMSIS/Include/cmsis_gcc.h **** + 214:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 215:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get APSR Register + 216:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the APSR Register. + 217:Drivers/CMSIS/Include/cmsis_gcc.h **** \return APSR Register value + 218:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 219:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void) + 220:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 221:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 222:Drivers/CMSIS/Include/cmsis_gcc.h **** + 223:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + 224:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 225:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 226:Drivers/CMSIS/Include/cmsis_gcc.h **** + 227:Drivers/CMSIS/Include/cmsis_gcc.h **** + 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 229:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get xPSR Register + 230:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the content of the xPSR Register. + 231:Drivers/CMSIS/Include/cmsis_gcc.h **** \return xPSR Register value + 232:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void) + 234:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 235:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 236:Drivers/CMSIS/Include/cmsis_gcc.h **** + 237:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + 238:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 239:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 240:Drivers/CMSIS/Include/cmsis_gcc.h **** + 241:Drivers/CMSIS/Include/cmsis_gcc.h **** + 242:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 243:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer + 244:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer (PSP). + 245:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 246:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 247:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void) + 248:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 249:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 250:Drivers/CMSIS/Include/cmsis_gcc.h **** + 251:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp" : "=r" (result) ); + 252:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 253:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 254:Drivers/CMSIS/Include/cmsis_gcc.h **** + 255:Drivers/CMSIS/Include/cmsis_gcc.h **** + 256:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 257:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 258:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer (non-secure) + 259:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s + 260:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSP Register value + 261:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 262:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) + 263:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 264:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 265:Drivers/CMSIS/Include/cmsis_gcc.h **** + 266:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + 267:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + ARM GAS /tmp/ccwmaYtI.s page 11 + + + 268:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 269:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 270:Drivers/CMSIS/Include/cmsis_gcc.h **** + 271:Drivers/CMSIS/Include/cmsis_gcc.h **** + 272:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 273:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer + 274:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer (PSP). + 275:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 276:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 277:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) + 278:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 279:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); + 280:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 281:Drivers/CMSIS/Include/cmsis_gcc.h **** + 282:Drivers/CMSIS/Include/cmsis_gcc.h **** + 283:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 284:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 285:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + 286:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta + 287:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfProcStack Process Stack Pointer value to set + 288:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 289:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) + 290:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 291:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); + 292:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 293:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 294:Drivers/CMSIS/Include/cmsis_gcc.h **** + 295:Drivers/CMSIS/Include/cmsis_gcc.h **** + 296:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 297:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer + 298:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer (MSP). + 299:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 300:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 301:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void) + 302:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 303:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 304:Drivers/CMSIS/Include/cmsis_gcc.h **** + 305:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp" : "=r" (result) ); + 306:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 307:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 308:Drivers/CMSIS/Include/cmsis_gcc.h **** + 309:Drivers/CMSIS/Include/cmsis_gcc.h **** + 310:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 311:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 312:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer (non-secure) + 313:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat + 314:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSP Register value + 315:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 316:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) + 317:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 318:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 319:Drivers/CMSIS/Include/cmsis_gcc.h **** + 320:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + 321:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 322:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 324:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccwmaYtI.s page 12 + + + 325:Drivers/CMSIS/Include/cmsis_gcc.h **** + 326:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 327:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer + 328:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer (MSP). + 329:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 330:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 331:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) + 332:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 333:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); + 334:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 335:Drivers/CMSIS/Include/cmsis_gcc.h **** + 336:Drivers/CMSIS/Include/cmsis_gcc.h **** + 337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 338:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 339:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer (non-secure) + 340:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + 341:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfMainStack Main Stack Pointer value to set + 342:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 343:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) + 344:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 345:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); + 346:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 347:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 348:Drivers/CMSIS/Include/cmsis_gcc.h **** + 349:Drivers/CMSIS/Include/cmsis_gcc.h **** + 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 352:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Stack Pointer (non-secure) + 353:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + 354:Drivers/CMSIS/Include/cmsis_gcc.h **** \return SP Register value + 355:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) + 357:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 358:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 359:Drivers/CMSIS/Include/cmsis_gcc.h **** + 360:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + 361:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 362:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 363:Drivers/CMSIS/Include/cmsis_gcc.h **** + 364:Drivers/CMSIS/Include/cmsis_gcc.h **** + 365:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 366:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Stack Pointer (non-secure) + 367:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + 368:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] topOfStack Stack Pointer value to set + 369:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 370:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) + 371:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 372:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); + 373:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 374:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 375:Drivers/CMSIS/Include/cmsis_gcc.h **** + 376:Drivers/CMSIS/Include/cmsis_gcc.h **** + 377:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 378:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask + 379:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the priority mask bit from the Priority Mask Register. + 380:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 381:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + ARM GAS /tmp/ccwmaYtI.s page 13 + + + 382:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) + 383:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 384:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 385:Drivers/CMSIS/Include/cmsis_gcc.h **** + 386:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 387:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 388:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 389:Drivers/CMSIS/Include/cmsis_gcc.h **** + 390:Drivers/CMSIS/Include/cmsis_gcc.h **** + 391:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 392:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 393:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Priority Mask (non-secure) + 394:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg + 395:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Priority Mask value + 396:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 397:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) + 398:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 399:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 400:Drivers/CMSIS/Include/cmsis_gcc.h **** + 401:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + 402:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 403:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 405:Drivers/CMSIS/Include/cmsis_gcc.h **** + 406:Drivers/CMSIS/Include/cmsis_gcc.h **** + 407:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 408:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask + 409:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Priority Mask Register. + 410:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 411:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 412:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) + 413:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 414:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 415:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 416:Drivers/CMSIS/Include/cmsis_gcc.h **** + 417:Drivers/CMSIS/Include/cmsis_gcc.h **** + 418:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 419:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 420:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Priority Mask (non-secure) + 421:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + 422:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] priMask Priority Mask + 423:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 424:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) + 425:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 426:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); + 427:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 428:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 429:Drivers/CMSIS/Include/cmsis_gcc.h **** + 430:Drivers/CMSIS/Include/cmsis_gcc.h **** + 431:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 432:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 433:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + 434:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 435:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable FIQ + 436:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + 437:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 438:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + ARM GAS /tmp/ccwmaYtI.s page 14 + + + 439:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void) + 440:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 441:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie f" : : : "memory"); + 442:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 443:Drivers/CMSIS/Include/cmsis_gcc.h **** + 444:Drivers/CMSIS/Include/cmsis_gcc.h **** + 445:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 446:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable FIQ + 447:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables FIQ interrupts by setting the F-bit in the CPSR. + 448:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. + 449:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 450:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void) + 451:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 452:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid f" : : : "memory"); + 453:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 454:Drivers/CMSIS/Include/cmsis_gcc.h **** + 455:Drivers/CMSIS/Include/cmsis_gcc.h **** + 456:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 457:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority + 458:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Base Priority register. + 459:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 460:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 461:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) + 462:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 463:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 464:Drivers/CMSIS/Include/cmsis_gcc.h **** + 465:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + 466:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 467:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 468:Drivers/CMSIS/Include/cmsis_gcc.h **** + 469:Drivers/CMSIS/Include/cmsis_gcc.h **** + 470:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 471:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 472:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Base Priority (non-secure) + 473:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Base Priority register when in secure state. + 474:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Base Priority register value + 475:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) + 477:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 478:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 479:Drivers/CMSIS/Include/cmsis_gcc.h **** + 480:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + 481:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 482:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 483:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 484:Drivers/CMSIS/Include/cmsis_gcc.h **** + 485:Drivers/CMSIS/Include/cmsis_gcc.h **** + 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 487:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority + 488:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register. + 489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 490:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) + 492:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 493:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); + 494:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 495:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccwmaYtI.s page 15 + + + 496:Drivers/CMSIS/Include/cmsis_gcc.h **** + 497:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 498:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 499:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority (non-secure) + 500:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Base Priority register when in secure state. + 501:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 502:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 503:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) + 504:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 505:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); + 506:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 507:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 508:Drivers/CMSIS/Include/cmsis_gcc.h **** + 509:Drivers/CMSIS/Include/cmsis_gcc.h **** + 510:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 511:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Base Priority with condition + 512:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable + 513:Drivers/CMSIS/Include/cmsis_gcc.h **** or the new value increases the BASEPRI priority level. + 514:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] basePri Base Priority value to set + 515:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 516:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) + 517:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 518:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); + 519:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 520:Drivers/CMSIS/Include/cmsis_gcc.h **** + 521:Drivers/CMSIS/Include/cmsis_gcc.h **** + 522:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 523:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask + 524:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Fault Mask register. + 525:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 526:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) + 528:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 529:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 530:Drivers/CMSIS/Include/cmsis_gcc.h **** + 531:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + 532:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 533:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 534:Drivers/CMSIS/Include/cmsis_gcc.h **** + 535:Drivers/CMSIS/Include/cmsis_gcc.h **** + 536:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 537:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 538:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Fault Mask (non-secure) + 539:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Fault Mask register when in secure state. + 540:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Fault Mask register value + 541:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 542:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) + 543:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 544:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 545:Drivers/CMSIS/Include/cmsis_gcc.h **** + 546:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + 547:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 548:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 549:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 550:Drivers/CMSIS/Include/cmsis_gcc.h **** + 551:Drivers/CMSIS/Include/cmsis_gcc.h **** + 552:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + ARM GAS /tmp/ccwmaYtI.s page 16 + + + 553:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask + 554:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Fault Mask register. + 555:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 556:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 557:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) + 558:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 559:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); + 560:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 561:Drivers/CMSIS/Include/cmsis_gcc.h **** + 562:Drivers/CMSIS/Include/cmsis_gcc.h **** + 563:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 564:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 565:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Fault Mask (non-secure) + 566:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Fault Mask register when in secure state. + 567:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] faultMask Fault Mask value to set + 568:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 569:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) + 570:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 571:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); + 572:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 573:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 574:Drivers/CMSIS/Include/cmsis_gcc.h **** + 575:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 576:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 577:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + 578:Drivers/CMSIS/Include/cmsis_gcc.h **** + 579:Drivers/CMSIS/Include/cmsis_gcc.h **** + 580:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 581:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + 582:Drivers/CMSIS/Include/cmsis_gcc.h **** + 583:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 584:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit + 585:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 586:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 587:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 588:Drivers/CMSIS/Include/cmsis_gcc.h **** + 589:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + 590:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 591:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 592:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) + 593:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 594:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 595:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 596:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 597:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 598:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 599:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 600:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + 601:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 602:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 603:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 604:Drivers/CMSIS/Include/cmsis_gcc.h **** + 605:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) + 606:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 607:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Process Stack Pointer Limit (non-secure) + 608:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 609:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + ARM GAS /tmp/ccwmaYtI.s page 17 + + + 610:Drivers/CMSIS/Include/cmsis_gcc.h **** + 611:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in + 612:Drivers/CMSIS/Include/cmsis_gcc.h **** \return PSPLIM Register value + 613:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 614:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) + 615:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 617:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 618:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 619:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 620:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 621:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + 622:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 623:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 624:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 625:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 626:Drivers/CMSIS/Include/cmsis_gcc.h **** + 627:Drivers/CMSIS/Include/cmsis_gcc.h **** + 628:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 629:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer Limit + 630:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 631:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 632:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 633:Drivers/CMSIS/Include/cmsis_gcc.h **** + 634:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + 635:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 636:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 637:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) + 638:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 639:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 640:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 641:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 642:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 643:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 644:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); + 645:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 646:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 647:Drivers/CMSIS/Include/cmsis_gcc.h **** + 648:Drivers/CMSIS/Include/cmsis_gcc.h **** + 649:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 651:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Process Stack Pointer (non-secure) + 652:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 653:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 654:Drivers/CMSIS/Include/cmsis_gcc.h **** + 655:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s + 656:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + 657:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 658:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) + 659:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 660:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 661:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure PSPLIM is RAZ/WI + 662:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)ProcStackPtrLimit; + 663:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 664:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); + 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 666:Drivers/CMSIS/Include/cmsis_gcc.h **** } + ARM GAS /tmp/ccwmaYtI.s page 18 + + + 667:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 668:Drivers/CMSIS/Include/cmsis_gcc.h **** + 669:Drivers/CMSIS/Include/cmsis_gcc.h **** + 670:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 671:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit + 672:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 673:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always in non-secure + 674:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 675:Drivers/CMSIS/Include/cmsis_gcc.h **** + 676:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + 677:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 678:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) + 680:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 681:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 682:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 683:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 684:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 685:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 686:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 687:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + 688:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 689:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 690:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 691:Drivers/CMSIS/Include/cmsis_gcc.h **** + 692:Drivers/CMSIS/Include/cmsis_gcc.h **** + 693:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 694:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 695:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get Main Stack Pointer Limit (non-secure) + 696:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 697:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence zero is returned always. + 698:Drivers/CMSIS/Include/cmsis_gcc.h **** + 699:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec + 700:Drivers/CMSIS/Include/cmsis_gcc.h **** \return MSPLIM Register value + 701:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 702:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) + 703:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 704:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 705:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 706:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; + 707:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 708:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 709:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + 710:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 711:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 712:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 713:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 714:Drivers/CMSIS/Include/cmsis_gcc.h **** + 715:Drivers/CMSIS/Include/cmsis_gcc.h **** + 716:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 717:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit + 718:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 719:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored in non-secure + 720:Drivers/CMSIS/Include/cmsis_gcc.h **** mode. + 721:Drivers/CMSIS/Include/cmsis_gcc.h **** + 722:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + 723:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + ARM GAS /tmp/ccwmaYtI.s page 19 + + + 724:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) + 726:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + 728:Drivers/CMSIS/Include/cmsis_gcc.h **** (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + 729:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 730:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 731:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 732:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); + 733:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 734:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 735:Drivers/CMSIS/Include/cmsis_gcc.h **** + 736:Drivers/CMSIS/Include/cmsis_gcc.h **** + 737:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + 738:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 739:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set Main Stack Pointer Limit (non-secure) + 740:Drivers/CMSIS/Include/cmsis_gcc.h **** Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + 741:Drivers/CMSIS/Include/cmsis_gcc.h **** Stack Pointer Limit register hence the write is silently ignored. + 742:Drivers/CMSIS/Include/cmsis_gcc.h **** + 743:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu + 744:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] MainStackPtrLimit Main Stack Pointer value to set + 745:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) + 747:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + 749:Drivers/CMSIS/Include/cmsis_gcc.h **** // without main extensions, the non-secure MSPLIM is RAZ/WI + 750:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)MainStackPtrLimit; + 751:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 752:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); + 753:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 754:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 755:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 756:Drivers/CMSIS/Include/cmsis_gcc.h **** + 757:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + 758:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + 759:Drivers/CMSIS/Include/cmsis_gcc.h **** + 760:Drivers/CMSIS/Include/cmsis_gcc.h **** + 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 762:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Get FPSCR + 763:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Returns the current value of the Floating Point Status/Control register. + 764:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Floating Point Status/Control register value + 765:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 766:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void) + 767:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 768:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 769:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 770:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) + 771:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + 772:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 773:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 774:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_arm_get_fpscr(); + 775:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 776:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 777:Drivers/CMSIS/Include/cmsis_gcc.h **** + 778:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + 779:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); + 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + ARM GAS /tmp/ccwmaYtI.s page 20 + + + 781:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 782:Drivers/CMSIS/Include/cmsis_gcc.h **** return(0U); + 783:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 784:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 785:Drivers/CMSIS/Include/cmsis_gcc.h **** + 786:Drivers/CMSIS/Include/cmsis_gcc.h **** + 787:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 788:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Set FPSCR + 789:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Assigns the given value to the Floating Point Status/Control register. + 790:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] fpscr Floating Point Status/Control value to set + 791:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) + 793:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + 795:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + 796:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr) + 797:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed + 798:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + 799:Drivers/CMSIS/Include/cmsis_gcc.h **** /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + 800:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_arm_set_fpscr(fpscr); + 801:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 802:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); + 803:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 805:Drivers/CMSIS/Include/cmsis_gcc.h **** (void)fpscr; + 806:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 807:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 808:Drivers/CMSIS/Include/cmsis_gcc.h **** + 809:Drivers/CMSIS/Include/cmsis_gcc.h **** + 810:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */ + 811:Drivers/CMSIS/Include/cmsis_gcc.h **** + 812:Drivers/CMSIS/Include/cmsis_gcc.h **** + 813:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */ + 814:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + 815:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions + 816:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ + 817:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 818:Drivers/CMSIS/Include/cmsis_gcc.h **** + 819:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2. + 820:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l" + 821:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */ + 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__) + 823:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r) + 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r) + 825:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r) + 826:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 827:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r) + 828:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r) + 829:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r) + 830:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 831:Drivers/CMSIS/Include/cmsis_gcc.h **** + 832:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 833:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation + 834:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes. + 835:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 836:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP() __ASM volatile ("nop") + 837:Drivers/CMSIS/Include/cmsis_gcc.h **** + ARM GAS /tmp/ccwmaYtI.s page 21 + + + 838:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 839:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt + 840:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o + 841:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI() __ASM volatile ("wfi") + 843:Drivers/CMSIS/Include/cmsis_gcc.h **** + 844:Drivers/CMSIS/Include/cmsis_gcc.h **** + 845:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 846:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event + 847:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter + 848:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs. + 849:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE() __ASM volatile ("wfe") + 851:Drivers/CMSIS/Include/cmsis_gcc.h **** + 852:Drivers/CMSIS/Include/cmsis_gcc.h **** + 853:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 854:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event + 855:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + 856:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 857:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev") + 858:Drivers/CMSIS/Include/cmsis_gcc.h **** + 859:Drivers/CMSIS/Include/cmsis_gcc.h **** + 860:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 861:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier + 862:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor, + 863:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory, + 864:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed. + 865:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 866:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void) + 867:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 868:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory"); + 869:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 870:Drivers/CMSIS/Include/cmsis_gcc.h **** + 871:Drivers/CMSIS/Include/cmsis_gcc.h **** + 872:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 873:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier + 874:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier. + 875:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete. + 876:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 877:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void) + 878:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 879:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory"); + 880:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 881:Drivers/CMSIS/Include/cmsis_gcc.h **** + 882:Drivers/CMSIS/Include/cmsis_gcc.h **** + 883:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 884:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Memory Barrier + 885:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Ensures the apparent order of the explicit memory operations before + 886:Drivers/CMSIS/Include/cmsis_gcc.h **** and after the instruction, without ensuring their completion. + 887:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 888:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void) + 889:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 890:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dmb 0xF":::"memory"); + 891:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 892:Drivers/CMSIS/Include/cmsis_gcc.h **** + 893:Drivers/CMSIS/Include/cmsis_gcc.h **** + 894:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + ARM GAS /tmp/ccwmaYtI.s page 22 + + + 895:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (32 bit) + 896:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x785 + 897:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 898:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 899:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 900:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV(uint32_t value) + 901:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 902:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + 903:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_bswap32(value); + 904:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 905:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 906:Drivers/CMSIS/Include/cmsis_gcc.h **** + 907:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + 908:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 909:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 910:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 911:Drivers/CMSIS/Include/cmsis_gcc.h **** + 912:Drivers/CMSIS/Include/cmsis_gcc.h **** + 913:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 914:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) + 915:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes + 916:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 917:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 918:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 919:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) + 920:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 921:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 922:Drivers/CMSIS/Include/cmsis_gcc.h **** + 923:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + 924:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 925:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 926:Drivers/CMSIS/Include/cmsis_gcc.h **** + 927:Drivers/CMSIS/Include/cmsis_gcc.h **** + 928:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 929:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) + 930:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For exam + 931:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 932:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 933:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 934:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE int16_t __REVSH(int16_t value) + 935:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 936:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + 937:Drivers/CMSIS/Include/cmsis_gcc.h **** return (int16_t)__builtin_bswap16(value); + 938:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 939:Drivers/CMSIS/Include/cmsis_gcc.h **** int16_t result; + 940:Drivers/CMSIS/Include/cmsis_gcc.h **** + 941:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + 942:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 943:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif + 944:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 945:Drivers/CMSIS/Include/cmsis_gcc.h **** + 946:Drivers/CMSIS/Include/cmsis_gcc.h **** + 947:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 948:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Rotate Right in unsigned value (32 bit) + 949:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v + 950:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op1 Value to rotate + 951:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op2 Number of Bits to rotate + ARM GAS /tmp/ccwmaYtI.s page 23 + + + 952:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Rotated value + 953:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 954:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) + 955:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 956:Drivers/CMSIS/Include/cmsis_gcc.h **** op2 %= 32U; + 957:Drivers/CMSIS/Include/cmsis_gcc.h **** if (op2 == 0U) + 958:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 959:Drivers/CMSIS/Include/cmsis_gcc.h **** return op1; + 960:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 961:Drivers/CMSIS/Include/cmsis_gcc.h **** return (op1 >> op2) | (op1 << (32U - op2)); + 962:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 963:Drivers/CMSIS/Include/cmsis_gcc.h **** + 964:Drivers/CMSIS/Include/cmsis_gcc.h **** + 965:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 966:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Breakpoint + 967:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Causes the processor to enter Debug state. + 968:Drivers/CMSIS/Include/cmsis_gcc.h **** Debug tools can use this to investigate system state when the instruction at a particula + 969:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value is ignored by the processor. + 970:Drivers/CMSIS/Include/cmsis_gcc.h **** If required, a debugger can use it to store additional information about the break + 971:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 972:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __BKPT(value) __ASM volatile ("bkpt "#value) + 973:Drivers/CMSIS/Include/cmsis_gcc.h **** + 974:Drivers/CMSIS/Include/cmsis_gcc.h **** + 975:Drivers/CMSIS/Include/cmsis_gcc.h **** /** + 976:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse bit order of value + 977:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the bit order of the given value. + 978:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse + 979:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value + 980:Drivers/CMSIS/Include/cmsis_gcc.h **** */ + 981:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) + 982:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 983:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; + 984:Drivers/CMSIS/Include/cmsis_gcc.h **** + 985:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + 986:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + 987:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + 152 .loc 2 988 4 + 153 00bc 3B6B ldr r3, [r7, #48] + 154 .syntax unified + 155 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 156 00be 93FAA3F3 rbit r3, r3 + 157 @ 0 "" 2 + 158 .thumb + 159 .syntax unified + 160 00c2 FB62 str r3, [r7, #44] + 989:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 990:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + 991:Drivers/CMSIS/Include/cmsis_gcc.h **** + 992:Drivers/CMSIS/Include/cmsis_gcc.h **** result = value; /* r will be reversed bits of v; first get LSB of v */ + 993:Drivers/CMSIS/Include/cmsis_gcc.h **** for (value >>= 1U; value != 0U; value >>= 1U) + 994:Drivers/CMSIS/Include/cmsis_gcc.h **** { + 995:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= 1U; + 996:Drivers/CMSIS/Include/cmsis_gcc.h **** result |= value & 1U; + 997:Drivers/CMSIS/Include/cmsis_gcc.h **** s--; + 998:Drivers/CMSIS/Include/cmsis_gcc.h **** } + 999:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= s; /* shift when v's highest bits are zero */ + ARM GAS /tmp/ccwmaYtI.s page 24 + + +1000:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif +1001:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; + 161 .loc 2 1001 10 + 162 00c4 FB6A ldr r3, [r7, #44] + 163 .LBE19: + 164 .LBE18: + 153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* RTC Clock selection can be changed only if the Backup Domain is reset */ + 154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_BACKUPRESET_FORCE(); + 165 .loc 1 154 7 discriminator 1 + 166 00c6 B3FA83F3 clz r3, r3 + 167 .loc 1 154 7 is_stmt 0 discriminator 2 + 168 00ca DBB2 uxtb r3, r3 + 169 00cc 1A46 mov r2, r3 + 170 00ce 254B ldr r3, .L30+8 + 171 00d0 1344 add r3, r3, r2 + 172 00d2 9B00 lsls r3, r3, #2 + 173 00d4 1A46 mov r2, r3 + 174 00d6 0123 movs r3, #1 + 175 00d8 1360 str r3, [r2] + 176 00da 4FF48033 mov r3, #65536 + 177 00de BB63 str r3, [r7, #56] + 178 .LBB20: + 179 .LBB21: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 180 .loc 2 988 4 is_stmt 1 + 181 00e0 BB6B ldr r3, [r7, #56] + 182 .syntax unified + 183 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 184 00e2 93FAA3F3 rbit r3, r3 + 185 @ 0 "" 2 + 186 .thumb + 187 .syntax unified + 188 00e6 7B63 str r3, [r7, #52] + 189 .loc 2 1001 10 + 190 00e8 7B6B ldr r3, [r7, #52] + 191 .LBE21: + 192 .LBE20: + 155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_BACKUPRESET_RELEASE(); + 193 .loc 1 155 7 discriminator 1 + 194 00ea B3FA83F3 clz r3, r3 + 195 .loc 1 155 7 is_stmt 0 discriminator 2 + 196 00ee DBB2 uxtb r3, r3 + 197 00f0 1A46 mov r2, r3 + 198 00f2 1C4B ldr r3, .L30+8 + 199 00f4 1344 add r3, r3, r2 + 200 00f6 9B00 lsls r3, r3, #2 + 201 00f8 1A46 mov r2, r3 + 202 00fa 0023 movs r3, #0 + 203 00fc 1360 str r3, [r2] + 156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Restore the Content of BDCR register */ + 157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** RCC->BDCR = temp_reg; + 204 .loc 1 157 10 is_stmt 1 + 205 00fe 174A ldr r2, .L30 + 206 .loc 1 157 17 + 207 0100 FB6B ldr r3, [r7, #60] + 208 0102 1362 str r3, [r2, #32] + 158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + ARM GAS /tmp/ccwmaYtI.s page 25 + + + 159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Wait for LSERDY if LSE was enabled */ + 160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON)) + 209 .loc 1 160 11 + 210 0104 FB6B ldr r3, [r7, #60] + 211 0106 03F00103 and r3, r3, #1 + 212 .loc 1 160 10 + 213 010a 002B cmp r3, #0 + 214 010c 49D0 beq .L8 + 161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get Start Tick */ + 163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** tickstart = HAL_GetTick(); + 215 .loc 1 163 21 + 216 010e FFF7FEFF bl HAL_GetTick + 217 0112 3864 str r0, [r7, #64] + 164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Wait till LSE is ready */ + 166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 218 .loc 1 166 14 + 219 0114 0AE0 b .L11 + 220 .L18: + 167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 221 .loc 1 168 17 + 222 0116 FFF7FEFF bl HAL_GetTick + 223 011a 0246 mov r2, r0 + 224 .loc 1 168 31 discriminator 1 + 225 011c 3B6C ldr r3, [r7, #64] + 226 011e D31A subs r3, r2, r3 + 227 .loc 1 168 15 discriminator 1 + 228 0120 41F28832 movw r2, #5000 + 229 0124 9342 cmp r3, r2 + 230 0126 01D9 bls .L11 + 169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** return HAL_TIMEOUT; + 231 .loc 1 170 20 + 232 0128 0323 movs r3, #3 + 233 012a F3E0 b .L6 + 234 .L11: + 235 012c 0223 movs r3, #2 + 236 012e BB62 str r3, [r7, #40] + 237 .LBB22: + 238 .LBB23: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 239 .loc 2 988 4 + 240 0130 BB6A ldr r3, [r7, #40] + 241 .syntax unified + 242 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 243 0132 93FAA3F3 rbit r3, r3 + 244 @ 0 "" 2 + 245 .thumb + 246 .syntax unified + 247 0136 7B62 str r3, [r7, #36] + 248 0138 0223 movs r3, #2 + 249 013a 3B62 str r3, [r7, #32] + 250 .LBE23: + 251 .LBE22: + 252 .LBB24: + ARM GAS /tmp/ccwmaYtI.s page 26 + + + 253 .LBB25: + 254 013c 3B6A ldr r3, [r7, #32] + 255 .syntax unified + 256 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 257 013e 93FAA3F3 rbit r3, r3 + 258 @ 0 "" 2 + 259 .thumb + 260 .syntax unified + 261 0142 FB61 str r3, [r7, #28] + 262 .loc 2 1001 10 + 263 0144 FB69 ldr r3, [r7, #28] + 264 .LBE25: + 265 .LBE24: + 166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 266 .loc 1 166 15 discriminator 1 + 267 0146 B3FA83F3 clz r3, r3 + 166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 268 .loc 1 166 15 is_stmt 0 discriminator 2 + 269 014a DBB2 uxtb r3, r3 + 270 014c 23F05F03 bic r3, r3, #95 + 271 0150 DBB2 uxtb r3, r3 + 272 0152 002B cmp r3, #0 + 273 0154 08D1 bne .L14 + 166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 274 .loc 1 166 15 discriminator 4 + 275 0156 014B ldr r3, .L30 + 276 0158 1B6A ldr r3, [r3, #32] + 277 015a 0DE0 b .L15 + 278 .L31: + 279 .align 2 + 280 .L30: + 281 015c 00100240 .word 1073876992 + 282 0160 00700040 .word 1073770496 + 283 0164 00819010 .word 277905664 + 284 .L14: + 285 0168 0223 movs r3, #2 + 286 016a BB61 str r3, [r7, #24] + 287 .LBB26: + 288 .LBB27: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 289 .loc 2 988 4 is_stmt 1 + 290 016c BB69 ldr r3, [r7, #24] + 291 .syntax unified + 292 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 293 016e 93FAA3F3 rbit r3, r3 + 294 @ 0 "" 2 + 295 .thumb + 296 .syntax unified + 297 0172 7B61 str r3, [r7, #20] + 298 .LBE27: + 299 .LBE26: + 166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 300 .loc 1 166 15 discriminator 8 + 301 0174 694B ldr r3, .L32 + 302 0176 5B6A ldr r3, [r3, #36] + 303 .L15: + 304 0178 0222 movs r2, #2 + ARM GAS /tmp/ccwmaYtI.s page 27 + + + 305 017a 3A61 str r2, [r7, #16] + 306 .LBB28: + 307 .LBB29: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 308 .loc 2 988 4 + 309 017c 3A69 ldr r2, [r7, #16] + 310 .syntax unified + 311 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 312 017e 92FAA2F2 rbit r2, r2 + 313 @ 0 "" 2 + 314 .thumb + 315 .syntax unified + 316 0182 FA60 str r2, [r7, #12] + 317 .loc 2 1001 10 + 318 0184 FA68 ldr r2, [r7, #12] + 319 .LBE29: + 320 .LBE28: + 166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 321 .loc 1 166 15 discriminator 1 + 322 0186 B2FA82F2 clz r2, r2 + 166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 323 .loc 1 166 15 is_stmt 0 discriminator 2 + 324 018a D2B2 uxtb r2, r2 + 325 018c 42F04002 orr r2, r2, #64 + 326 0190 D2B2 uxtb r2, r2 + 327 0192 02F01F02 and r2, r2, #31 + 328 0196 0121 movs r1, #1 + 329 0198 01FA02F2 lsl r2, r1, r2 + 330 019c 1340 ands r3, r3, r2 + 166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 331 .loc 1 166 51 is_stmt 1 discriminator 2 + 332 019e 002B cmp r3, #0 + 333 01a0 B9D0 beq .L18 + 334 .L8: + 171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + 335 .loc 1 175 5 + 336 01a2 5E4B ldr r3, .L32 + 337 01a4 1B6A ldr r3, [r3, #32] + 338 01a6 23F44072 bic r2, r3, #768 + 339 01aa 7B68 ldr r3, [r7, #4] + 340 01ac 5B68 ldr r3, [r3, #4] + 341 01ae 5B49 ldr r1, .L32 + 342 01b0 1343 orrs r3, r3, r2 + 343 01b2 0B62 str r3, [r1, #32] + 176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Require to disable power clock if necessary */ + 178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(pwrclkchanged == SET) + 344 .loc 1 178 7 + 345 01b4 97F84730 ldrb r3, [r7, #71] @ zero_extendqisi2 + 346 01b8 012B cmp r3, #1 + 347 01ba 05D1 bne .L2 + 179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_PWR_CLK_DISABLE(); + ARM GAS /tmp/ccwmaYtI.s page 28 + + + 348 .loc 1 180 7 + 349 01bc 574B ldr r3, .L32 + 350 01be DB69 ldr r3, [r3, #28] + 351 01c0 564A ldr r2, .L32 + 352 01c2 23F08053 bic r3, r3, #268435456 + 353 01c6 D361 str r3, [r2, #28] + 354 .L2: + 181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------- USART1 Configuration ------------------------*/ + 185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) + 355 .loc 1 185 21 + 356 01c8 7B68 ldr r3, [r7, #4] + 357 01ca 1B68 ldr r3, [r3] + 358 .loc 1 185 45 + 359 01cc 03F00103 and r3, r3, #1 + 360 .loc 1 185 5 + 361 01d0 002B cmp r3, #0 + 362 01d2 08D0 beq .L19 + 186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); + 189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the USART1 clock source */ + 191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); + 363 .loc 1 191 5 + 364 01d4 514B ldr r3, .L32 + 365 01d6 1B6B ldr r3, [r3, #48] + 366 01d8 23F00302 bic r2, r3, #3 + 367 01dc 7B68 ldr r3, [r7, #4] + 368 01de 9B68 ldr r3, [r3, #8] + 369 01e0 4E49 ldr r1, .L32 + 370 01e2 1343 orrs r3, r3, r2 + 371 01e4 0B63 str r3, [r1, #48] + 372 .L19: + 192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR3_USART2SW) + 195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*----------------------------- USART2 Configuration --------------------------*/ + 196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) + 373 .loc 1 196 21 + 374 01e6 7B68 ldr r3, [r7, #4] + 375 01e8 1B68 ldr r3, [r3] + 376 .loc 1 196 45 + 377 01ea 03F00203 and r3, r3, #2 + 378 .loc 1 196 5 + 379 01ee 002B cmp r3, #0 + 380 01f0 08D0 beq .L20 + 197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); + 200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the USART2 clock source */ + 202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); + 381 .loc 1 202 5 + 382 01f2 4A4B ldr r3, .L32 + ARM GAS /tmp/ccwmaYtI.s page 29 + + + 383 01f4 1B6B ldr r3, [r3, #48] + 384 01f6 23F44032 bic r2, r3, #196608 + 385 01fa 7B68 ldr r3, [r7, #4] + 386 01fc DB68 ldr r3, [r3, #12] + 387 01fe 4749 ldr r1, .L32 + 388 0200 1343 orrs r3, r3, r2 + 389 0202 0B63 str r3, [r1, #48] + 390 .L20: + 203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR3_USART2SW */ + 205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR3_USART3SW) + 207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ USART3 Configuration ------------------------*/ + 208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) + 391 .loc 1 208 21 + 392 0204 7B68 ldr r3, [r7, #4] + 393 0206 1B68 ldr r3, [r3] + 394 .loc 1 208 45 + 395 0208 03F00403 and r3, r3, #4 + 396 .loc 1 208 5 + 397 020c 002B cmp r3, #0 + 398 020e 08D0 beq .L21 + 209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); + 212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the USART3 clock source */ + 214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); + 399 .loc 1 214 5 + 400 0210 424B ldr r3, .L32 + 401 0212 1B6B ldr r3, [r3, #48] + 402 0214 23F44022 bic r2, r3, #786432 + 403 0218 7B68 ldr r3, [r7, #4] + 404 021a 1B69 ldr r3, [r3, #16] + 405 021c 3F49 ldr r1, .L32 + 406 021e 1343 orrs r3, r3, r2 + 407 0220 0B63 str r3, [r1, #48] + 408 .L21: + 215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR3_USART3SW */ + 217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ I2C1 Configuration ------------------------*/ + 219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) + 409 .loc 1 219 21 + 410 0222 7B68 ldr r3, [r7, #4] + 411 0224 1B68 ldr r3, [r3] + 412 .loc 1 219 45 + 413 0226 03F02003 and r3, r3, #32 + 414 .loc 1 219 5 + 415 022a 002B cmp r3, #0 + 416 022c 08D0 beq .L22 + 220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); + 223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the I2C1 clock source */ + 225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); + ARM GAS /tmp/ccwmaYtI.s page 30 + + + 417 .loc 1 225 5 + 418 022e 3B4B ldr r3, .L32 + 419 0230 1B6B ldr r3, [r3, #48] + 420 0232 23F01002 bic r2, r3, #16 + 421 0236 7B68 ldr r3, [r7, #4] + 422 0238 DB69 ldr r3, [r3, #28] + 423 023a 3849 ldr r1, .L32 + 424 023c 1343 orrs r3, r3, r2 + 425 023e 0B63 str r3, [r1, #48] + 426 .L22: + 226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F302xE) || defined(STM32F303xE)\ + 229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F302xC) || defined(STM32F303xC)\ + 230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F302x8) \ + 231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F373xC) + 232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ USB Configuration ------------------------*/ + 233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) + 427 .loc 1 233 21 + 428 0240 7B68 ldr r3, [r7, #4] + 429 0242 1B68 ldr r3, [r3] + 430 .loc 1 233 45 + 431 0244 03F40033 and r3, r3, #131072 + 432 .loc 1 233 5 + 433 0248 002B cmp r3, #0 + 434 024a 08D0 beq .L23 + 234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->USBClockSelection)); + 237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the USB clock source */ + 239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_USB_CONFIG(PeriphClkInit->USBClockSelection); + 435 .loc 1 239 5 + 436 024c 334B ldr r3, .L32 + 437 024e 5B68 ldr r3, [r3, #4] + 438 0250 23F48002 bic r2, r3, #4194304 + 439 0254 7B68 ldr r3, [r7, #4] + 440 0256 1B6B ldr r3, [r3, #48] + 441 0258 3049 ldr r1, .L32 + 442 025a 1343 orrs r3, r3, r2 + 443 025c 4B60 str r3, [r1, #4] + 444 .L23: + 240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F302xE || STM32F303xE || */ + 243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F302xC || STM32F303xC || */ + 244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F302x8 || */ + 245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F373xC */ + 246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + 248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ + 249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\ + 250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F373xC) || defined(STM32F378xx) + 251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ I2C2 Configuration ------------------------*/ + 253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) + 445 .loc 1 253 21 + ARM GAS /tmp/ccwmaYtI.s page 31 + + + 446 025e 7B68 ldr r3, [r7, #4] + 447 0260 1B68 ldr r3, [r3] + 448 .loc 1 253 45 + 449 0262 03F04003 and r3, r3, #64 + 450 .loc 1 253 5 + 451 0266 002B cmp r3, #0 + 452 0268 08D0 beq .L24 + 254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); + 257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the I2C2 clock source */ + 259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); + 453 .loc 1 259 5 + 454 026a 2C4B ldr r3, .L32 + 455 026c 1B6B ldr r3, [r3, #48] + 456 026e 23F02002 bic r2, r3, #32 + 457 0272 7B68 ldr r3, [r7, #4] + 458 0274 1B6A ldr r3, [r3, #32] + 459 0276 2949 ldr r1, .L32 + 460 0278 1343 orrs r3, r3, r2 + 461 027a 0B63 str r3, [r1, #48] + 462 .L24: + 260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + 263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F302xC || STM32F303xC || STM32F358xx || */ + 264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F301x8 || STM32F302x8 || STM32F318xx || */ + 265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F373xC || STM32F378xx */ + 266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + 268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) + 269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ I2C3 Configuration ------------------------*/ + 271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) + 272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); + 275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the I2C3 clock source */ + 277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); + 278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + 280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F301x8 || STM32F302x8 || STM32F318xx */ + 281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + 283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) + 284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ UART4 Configuration ------------------------*/ + 286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) + 463 .loc 1 286 21 + 464 027c 7B68 ldr r3, [r7, #4] + 465 027e 1B68 ldr r3, [r3] + 466 .loc 1 286 45 + 467 0280 03F00803 and r3, r3, #8 + 468 .loc 1 286 5 + 469 0284 002B cmp r3, #0 + ARM GAS /tmp/ccwmaYtI.s page 32 + + + 470 0286 08D0 beq .L25 + 287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection)); + 290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the UART4 clock source */ + 292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection); + 471 .loc 1 292 5 + 472 0288 244B ldr r3, .L32 + 473 028a 1B6B ldr r3, [r3, #48] + 474 028c 23F44012 bic r2, r3, #3145728 + 475 0290 7B68 ldr r3, [r7, #4] + 476 0292 5B69 ldr r3, [r3, #20] + 477 0294 2149 ldr r1, .L32 + 478 0296 1343 orrs r3, r3, r2 + 479 0298 0B63 str r3, [r1, #48] + 480 .L25: + 293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ UART5 Configuration ------------------------*/ + 296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) + 481 .loc 1 296 21 + 482 029a 7B68 ldr r3, [r7, #4] + 483 029c 1B68 ldr r3, [r3] + 484 .loc 1 296 45 + 485 029e 03F01003 and r3, r3, #16 + 486 .loc 1 296 5 + 487 02a2 002B cmp r3, #0 + 488 02a4 08D0 beq .L26 + 297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection)); + 300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the UART5 clock source */ + 302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection); + 489 .loc 1 302 5 + 490 02a6 1D4B ldr r3, .L32 + 491 02a8 1B6B ldr r3, [r3, #48] + 492 02aa 23F44002 bic r2, r3, #12582912 + 493 02ae 7B68 ldr r3, [r7, #4] + 494 02b0 9B69 ldr r3, [r3, #24] + 495 02b2 1A49 ldr r1, .L32 + 496 02b4 1343 orrs r3, r3, r2 + 497 02b6 0B63 str r3, [r1, #48] + 498 .L26: + 303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + 306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F302xC || STM32F303xC || STM32F358xx */ + 307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + 309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ + 310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) + 311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ I2S Configuration ------------------------*/ + 312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) + 499 .loc 1 312 21 + 500 02b8 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/ccwmaYtI.s page 33 + + + 501 02ba 1B68 ldr r3, [r3] + 502 .loc 1 312 45 + 503 02bc 03F40073 and r3, r3, #512 + 504 .loc 1 312 5 + 505 02c0 002B cmp r3, #0 + 506 02c2 08D0 beq .L27 + 313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection)); + 316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the I2S clock source */ + 318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection); + 507 .loc 1 318 5 + 508 02c4 154B ldr r3, .L32 + 509 02c6 5B68 ldr r3, [r3, #4] + 510 02c8 23F40002 bic r2, r3, #8388608 + 511 02cc 7B68 ldr r3, [r7, #4] + 512 02ce 9B6A ldr r3, [r3, #40] + 513 02d0 1249 ldr r1, .L32 + 514 02d2 1343 orrs r3, r3, r2 + 515 02d4 4B60 str r3, [r1, #4] + 516 .L27: + 319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + 322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F302xC || STM32F303xC || STM32F358xx || */ + 323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F301x8 || STM32F302x8 || STM32F318xx */ + 324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) + 326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ ADC1 clock Configuration ------------------*/ + 328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC1) == RCC_PERIPHCLK_ADC1) + 329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_ADC1PLLCLK_DIV(PeriphClkInit->Adc1ClockSelection)); + 332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the ADC1 clock source */ + 334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_ADC1_CONFIG(PeriphClkInit->Adc1ClockSelection); + 335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ + 338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + 340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ + 341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) + 342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ ADC1 & ADC2 clock Configuration -------------*/ + 344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) + 517 .loc 1 344 21 + 518 02d6 7B68 ldr r3, [r7, #4] + 519 02d8 1B68 ldr r3, [r3] + 520 .loc 1 344 45 + 521 02da 03F08003 and r3, r3, #128 + 522 .loc 1 344 5 + 523 02de 002B cmp r3, #0 + 524 02e0 08D0 beq .L28 + 345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + ARM GAS /tmp/ccwmaYtI.s page 34 + + + 346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_ADC12PLLCLK_DIV(PeriphClkInit->Adc12ClockSelection)); + 348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the ADC12 clock source */ + 350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_ADC12_CONFIG(PeriphClkInit->Adc12ClockSelection); + 525 .loc 1 350 5 + 526 02e2 0E4B ldr r3, .L32 + 527 02e4 DB6A ldr r3, [r3, #44] + 528 02e6 23F4F872 bic r2, r3, #496 + 529 02ea 7B68 ldr r3, [r7, #4] + 530 02ec 5B6A ldr r3, [r3, #36] + 531 02ee 0B49 ldr r1, .L32 + 532 02f0 1343 orrs r3, r3, r2 + 533 02f2 CB62 str r3, [r1, #44] + 534 .L28: + 351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + 354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F302xC || STM32F303xC || STM32F358xx || */ + 355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F303x8 || STM32F334x8 || STM32F328xx */ + 356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F303xE) || defined(STM32F398xx)\ + 358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F303xC) || defined(STM32F358xx) + 359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ ADC3 & ADC4 clock Configuration -------------*/ + 361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC34) == RCC_PERIPHCLK_ADC34) + 362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_ADC34PLLCLK_DIV(PeriphClkInit->Adc34ClockSelection)); + 365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the ADC34 clock source */ + 367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_ADC34_CONFIG(PeriphClkInit->Adc34ClockSelection); + 368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F303xE || STM32F398xx || */ + 371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F303xC || STM32F358xx */ + 372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F373xC) || defined(STM32F378xx) + 374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ ADC1 clock Configuration ------------------*/ + 376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC1) == RCC_PERIPHCLK_ADC1) + 377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_ADC1PCLK2_DIV(PeriphClkInit->Adc1ClockSelection)); + 380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the ADC1 clock source */ + 382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_ADC1_CONFIG(PeriphClkInit->Adc1ClockSelection); + 383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F373xC || STM32F378xx */ + 386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + 388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ + 389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\ + 390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) + 391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ TIM1 clock Configuration ----------------*/ + ARM GAS /tmp/ccwmaYtI.s page 35 + + + 393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1) + 535 .loc 1 393 21 + 536 02f4 7B68 ldr r3, [r7, #4] + 537 02f6 1B68 ldr r3, [r3] + 538 .loc 1 393 45 + 539 02f8 03F48053 and r3, r3, #4096 + 540 .loc 1 393 5 + 541 02fc 002B cmp r3, #0 + 542 02fe 08D0 beq .L29 + 394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_TIM1CLKSOURCE(PeriphClkInit->Tim1ClockSelection)); + 397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the TIM1 clock source */ + 399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_TIM1_CONFIG(PeriphClkInit->Tim1ClockSelection); + 543 .loc 1 399 5 + 544 0300 064B ldr r3, .L32 + 545 0302 1B6B ldr r3, [r3, #48] + 546 0304 23F48072 bic r2, r3, #256 + 547 0308 7B68 ldr r3, [r7, #4] + 548 030a DB6A ldr r3, [r3, #44] + 549 030c 0349 ldr r1, .L32 + 550 030e 1343 orrs r3, r3, r2 + 551 0310 0B63 str r3, [r1, #48] + 552 .L29: + 400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + 403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F302xC || STM32F303xC || STM32F358xx || */ + 404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ + 405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F301x8 || STM32F302x8 || STM32F318xx */ + 406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F303xE) || defined(STM32F398xx)\ + 408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F303xC) || defined(STM32F358xx) + 409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ TIM8 clock Configuration ----------------*/ + 411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM8) == RCC_PERIPHCLK_TIM8) + 412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_TIM8CLKSOURCE(PeriphClkInit->Tim8ClockSelection)); + 415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the TIM8 clock source */ + 417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_TIM8_CONFIG(PeriphClkInit->Tim8ClockSelection); + 418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F303xE || STM32F398xx || */ + 421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F303xC || STM32F358xx */ + 422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) + 424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ TIM15 clock Configuration ----------------*/ + 426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15) + 427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_TIM15CLKSOURCE(PeriphClkInit->Tim15ClockSelection)); + 430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the TIM15 clock source */ + ARM GAS /tmp/ccwmaYtI.s page 36 + + + 432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_TIM15_CONFIG(PeriphClkInit->Tim15ClockSelection); + 433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ TIM16 clock Configuration ----------------*/ + 436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM16) == RCC_PERIPHCLK_TIM16) + 437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_TIM16CLKSOURCE(PeriphClkInit->Tim16ClockSelection)); + 440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the TIM16 clock source */ + 442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_TIM16_CONFIG(PeriphClkInit->Tim16ClockSelection); + 443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ TIM17 clock Configuration ----------------*/ + 446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM17) == RCC_PERIPHCLK_TIM17) + 447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_TIM17CLKSOURCE(PeriphClkInit->Tim17ClockSelection)); + 450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the TIM17 clock source */ + 452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_TIM17_CONFIG(PeriphClkInit->Tim17ClockSelection); + 453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ + 456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F334x8) + 458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ HRTIM1 clock Configuration ----------------*/ + 460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1) + 461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_HRTIM1CLKSOURCE(PeriphClkInit->Hrtim1ClockSelection)); + 464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the HRTIM1 clock source */ + 466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection); + 467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F334x8 */ + 470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F373xC) || defined(STM32F378xx) + 472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ SDADC clock Configuration -------------------*/ + 474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDADC) == RCC_PERIPHCLK_SDADC) + 475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_SDADCSYSCLK_DIV(PeriphClkInit->SdadcClockSelection)); + 478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the SDADC clock prescaler */ + 480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_SDADC_CONFIG(PeriphClkInit->SdadcClockSelection); + 481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ CEC clock Configuration -------------------*/ + 484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) + 485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); + 488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + ARM GAS /tmp/ccwmaYtI.s page 37 + + + 489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the CEC clock source */ + 490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); + 491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F373xC || STM32F378xx */ + 494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) + 496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ TIM2 clock Configuration -------------------*/ + 498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM2) == RCC_PERIPHCLK_TIM2) + 499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_TIM2CLKSOURCE(PeriphClkInit->Tim2ClockSelection)); + 502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the CEC clock source */ + 504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_TIM2_CONFIG(PeriphClkInit->Tim2ClockSelection); + 505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ TIM3 clock Configuration -------------------*/ + 508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM34) == RCC_PERIPHCLK_TIM34) + 509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_TIM3CLKSOURCE(PeriphClkInit->Tim34ClockSelection)); + 512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the CEC clock source */ + 514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_TIM34_CONFIG(PeriphClkInit->Tim34ClockSelection); + 515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ TIM15 clock Configuration ------------------*/ + 518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15) + 519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_TIM15CLKSOURCE(PeriphClkInit->Tim15ClockSelection)); + 522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the CEC clock source */ + 524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_TIM15_CONFIG(PeriphClkInit->Tim15ClockSelection); + 525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ TIM16 clock Configuration ------------------*/ + 528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM16) == RCC_PERIPHCLK_TIM16) + 529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_TIM16CLKSOURCE(PeriphClkInit->Tim16ClockSelection)); + 532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the CEC clock source */ + 534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_TIM16_CONFIG(PeriphClkInit->Tim16ClockSelection); + 535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ TIM17 clock Configuration ------------------*/ + 538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM17) == RCC_PERIPHCLK_TIM17) + 539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_TIM17CLKSOURCE(PeriphClkInit->Tim17ClockSelection)); + 542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the CEC clock source */ + 544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_TIM17_CONFIG(PeriphClkInit->Tim17ClockSelection); + 545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + ARM GAS /tmp/ccwmaYtI.s page 38 + + + 546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ + 548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F303xE) || defined(STM32F398xx) + 550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /*------------------------------ TIM20 clock Configuration ------------------*/ + 551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM20) == RCC_PERIPHCLK_TIM20) + 552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_TIM20CLKSOURCE(PeriphClkInit->Tim20ClockSelection)); + 555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Configure the CEC clock source */ + 557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** __HAL_RCC_TIM20_CONFIG(PeriphClkInit->Tim20ClockSelection); + 558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F303xE || STM32F398xx */ + 560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** return HAL_OK; + 553 .loc 1 562 10 + 554 0312 0023 movs r3, #0 + 555 .L6: + 563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 556 .loc 1 563 1 + 557 0314 1846 mov r0, r3 + 558 0316 4837 adds r7, r7, #72 + 559 .cfi_def_cfa_offset 8 + 560 0318 BD46 mov sp, r7 + 561 .cfi_def_cfa_register 13 + 562 @ sp needed + 563 031a 80BD pop {r7, pc} + 564 .L33: + 565 .align 2 + 566 .L32: + 567 031c 00100240 .word 1073876992 + 568 .cfi_endproc + 569 .LFE130: + 571 .section .text.HAL_RCCEx_GetPeriphCLKConfig,"ax",%progbits + 572 .align 1 + 573 .global HAL_RCCEx_GetPeriphCLKConfig + 574 .syntax unified + 575 .thumb + 576 .thumb_func + 578 HAL_RCCEx_GetPeriphCLKConfig: + 579 .LFB131: + 564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /** + 566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @brief Get the RCC_ClkInitStruct according to the internal + 567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * RCC configuration registers. + 568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + 569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * returns the configuration information for the Extended Peripherals clocks + 570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * (ADC, CEC, I2C, I2S, SDADC, HRTIM, TIM, USART, RTC and USB clocks). + 571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @retval None + 572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** */ + 573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) + 574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 580 .loc 1 574 1 + 581 .cfi_startproc + 582 @ args = 0, pretend = 0, frame = 8 + ARM GAS /tmp/ccwmaYtI.s page 39 + + + 583 @ frame_needed = 1, uses_anonymous_args = 0 + 584 @ link register save eliminated. + 585 0000 80B4 push {r7} + 586 .cfi_def_cfa_offset 4 + 587 .cfi_offset 7, -4 + 588 0002 83B0 sub sp, sp, #12 + 589 .cfi_def_cfa_offset 16 + 590 0004 00AF add r7, sp, #0 + 591 .cfi_def_cfa_register 7 + 592 0006 7860 str r0, [r7, #4] + 575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Set all possible values for the extended clock type parameter------------*/ + 576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Common part first */ + 577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR3_USART2SW) && defined(RCC_CFGR3_USART3SW) + 578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK + 593 .loc 1 578 39 + 594 0008 7B68 ldr r3, [r7, #4] + 595 000a 3A4A ldr r2, .L35 + 596 000c 1A60 str r2, [r3] + 579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC; + 580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #else + 581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | \ + 582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC; + 583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR3_USART2SW && RCC_CFGR3_USART3SW */ + 584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the RTC configuration --------------------------------------------*/ + 586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE(); + 597 .loc 1 586 38 + 598 000e 3A4B ldr r3, .L35+4 + 599 0010 1B6A ldr r3, [r3, #32] + 600 0012 03F44072 and r2, r3, #768 + 601 .loc 1 586 36 + 602 0016 7B68 ldr r3, [r7, #4] + 603 0018 5A60 str r2, [r3, #4] + 587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the USART1 clock configuration --------------------------------------------*/ + 588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); + 604 .loc 1 588 41 + 605 001a 374B ldr r3, .L35+4 + 606 001c 1B6B ldr r3, [r3, #48] + 607 001e 03F00302 and r2, r3, #3 + 608 .loc 1 588 39 + 609 0022 7B68 ldr r3, [r7, #4] + 610 0024 9A60 str r2, [r3, #8] + 589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR3_USART2SW) + 590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the USART2 clock configuration -----------------------------------------*/ + 591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE(); + 611 .loc 1 591 41 + 612 0026 344B ldr r3, .L35+4 + 613 0028 1B6B ldr r3, [r3, #48] + 614 002a 03F44032 and r2, r3, #196608 + 615 .loc 1 591 39 + 616 002e 7B68 ldr r3, [r7, #4] + 617 0030 DA60 str r2, [r3, #12] + 592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR3_USART2SW */ + 593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR3_USART3SW) + 594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the USART3 clock configuration -----------------------------------------*/ + 595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE(); + 618 .loc 1 595 41 + ARM GAS /tmp/ccwmaYtI.s page 40 + + + 619 0032 314B ldr r3, .L35+4 + 620 0034 1B6B ldr r3, [r3, #48] + 621 0036 03F44022 and r2, r3, #786432 + 622 .loc 1 595 39 + 623 003a 7B68 ldr r3, [r7, #4] + 624 003c 1A61 str r2, [r3, #16] + 596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR3_USART3SW */ + 597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the I2C1 clock configuration -----------------------------------------*/ + 598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); + 625 .loc 1 598 39 + 626 003e 2E4B ldr r3, .L35+4 + 627 0040 1B6B ldr r3, [r3, #48] + 628 0042 03F01002 and r2, r3, #16 + 629 .loc 1 598 37 + 630 0046 7B68 ldr r3, [r7, #4] + 631 0048 DA61 str r2, [r3, #28] + 599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F302xE) || defined(STM32F303xE)\ + 601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F302xC) || defined(STM32F303xC)\ + 602:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F302x8) \ + 603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F373xC) + 604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB; + 632 .loc 1 605 16 + 633 004a 7B68 ldr r3, [r7, #4] + 634 004c 1B68 ldr r3, [r3] + 635 .loc 1 605 39 + 636 004e 43F40032 orr r2, r3, #131072 + 637 0052 7B68 ldr r3, [r7, #4] + 638 0054 1A60 str r2, [r3] + 606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the USB clock configuration -----------------------------------------*/ + 607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->USBClockSelection = __HAL_RCC_GET_USB_SOURCE(); + 639 .loc 1 607 38 + 640 0056 284B ldr r3, .L35+4 + 641 0058 5B68 ldr r3, [r3, #4] + 642 005a 03F48002 and r2, r3, #4194304 + 643 .loc 1 607 36 + 644 005e 7B68 ldr r3, [r7, #4] + 645 0060 1A63 str r2, [r3, #48] + 608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F302xE || STM32F303xE || */ + 610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F302xC || STM32F303xC || */ + 611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F302x8 || */ + 612:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F373xC */ + 613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + 615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ + 616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\ + 617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F373xC) || defined(STM32F378xx) + 618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C2; + 646 .loc 1 619 16 + 647 0062 7B68 ldr r3, [r7, #4] + 648 0064 1B68 ldr r3, [r3] + 649 .loc 1 619 39 + 650 0066 43F04002 orr r2, r3, #64 + 651 006a 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/ccwmaYtI.s page 41 + + + 652 006c 1A60 str r2, [r3] + 620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the I2C2 clock configuration -----------------------------------------*/ + 621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE(); + 653 .loc 1 621 39 + 654 006e 224B ldr r3, .L35+4 + 655 0070 1B6B ldr r3, [r3, #48] + 656 0072 03F02002 and r2, r3, #32 + 657 .loc 1 621 37 + 658 0076 7B68 ldr r3, [r7, #4] + 659 0078 1A62 str r2, [r3, #32] + 622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + 624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F302xC || STM32F303xC || STM32F358xx || */ + 625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F301x8 || STM32F302x8 || STM32F318xx || */ + 626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F373xC || STM32F378xx */ + 627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + 629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) + 630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C3; + 632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the I2C3 clock configuration -----------------------------------------*/ + 633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE(); + 634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + 636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F301x8 || STM32F302x8 || STM32F318xx */ + 637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + 639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F302xC) || defined(STM32F303xC) ||defined(STM32F358xx) + 640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= (RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5); + 660 .loc 1 641 16 + 661 007a 7B68 ldr r3, [r7, #4] + 662 007c 1B68 ldr r3, [r3] + 663 .loc 1 641 39 + 664 007e 43F01802 orr r2, r3, #24 + 665 0082 7B68 ldr r3, [r7, #4] + 666 0084 1A60 str r2, [r3] + 642:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the UART4 clock configuration -----------------------------------------*/ + 643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE(); + 667 .loc 1 643 40 + 668 0086 1C4B ldr r3, .L35+4 + 669 0088 1B6B ldr r3, [r3, #48] + 670 008a 03F44012 and r2, r3, #3145728 + 671 .loc 1 643 38 + 672 008e 7B68 ldr r3, [r7, #4] + 673 0090 5A61 str r2, [r3, #20] + 644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the UART5 clock configuration -----------------------------------------*/ + 645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE(); + 674 .loc 1 645 40 + 675 0092 194B ldr r3, .L35+4 + 676 0094 1B6B ldr r3, [r3, #48] + 677 0096 03F44002 and r2, r3, #12582912 + 678 .loc 1 645 38 + 679 009a 7B68 ldr r3, [r7, #4] + 680 009c 9A61 str r2, [r3, #24] + 646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + ARM GAS /tmp/ccwmaYtI.s page 42 + + + 648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F302xC || STM32F303xC || STM32F358xx */ + 649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + 651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ + 652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) + 653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S; + 681 .loc 1 654 16 + 682 009e 7B68 ldr r3, [r7, #4] + 683 00a0 1B68 ldr r3, [r3] + 684 .loc 1 654 39 + 685 00a2 43F40072 orr r2, r3, #512 + 686 00a6 7B68 ldr r3, [r7, #4] + 687 00a8 1A60 str r2, [r3] + 655:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the I2S clock configuration -----------------------------------------*/ + 656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2S_SOURCE(); + 688 .loc 1 656 38 + 689 00aa 134B ldr r3, .L35+4 + 690 00ac 5B68 ldr r3, [r3, #4] + 691 00ae 03F40002 and r2, r3, #8388608 + 692 .loc 1 656 36 + 693 00b2 7B68 ldr r3, [r7, #4] + 694 00b4 9A62 str r2, [r3, #40] + 657:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + 659:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F302xC || STM32F303xC || STM32F358xx || */ + 660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F301x8 || STM32F302x8 || STM32F318xx || */ + 661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\ + 663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F373xC) || defined(STM32F378xx) + 664:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC1; + 666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the ADC1 clock configuration -----------------------------------------*/ + 667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->Adc1ClockSelection = __HAL_RCC_GET_ADC1_SOURCE(); + 668:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */ + 670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F373xC || STM32F378xx */ + 671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + 673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ + 674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) + 675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC12; + 695 .loc 1 676 16 + 696 00b6 7B68 ldr r3, [r7, #4] + 697 00b8 1B68 ldr r3, [r3] + 698 .loc 1 676 39 + 699 00ba 43F08002 orr r2, r3, #128 + 700 00be 7B68 ldr r3, [r7, #4] + 701 00c0 1A60 str r2, [r3] + 677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the ADC1 & ADC2 clock configuration -----------------------------------------*/ + 678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->Adc12ClockSelection = __HAL_RCC_GET_ADC12_SOURCE(); + 702 .loc 1 678 40 + 703 00c2 0D4B ldr r3, .L35+4 + 704 00c4 DB6A ldr r3, [r3, #44] + 705 00c6 03F4F872 and r2, r3, #496 + 706 .loc 1 678 38 + ARM GAS /tmp/ccwmaYtI.s page 43 + + + 707 00ca 7B68 ldr r3, [r7, #4] + 708 00cc 5A62 str r2, [r3, #36] + 679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + 681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F302xC || STM32F303xC || STM32F358xx || */ + 682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F303x8 || STM32F334x8 || STM32F328xx */ + 683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F303xE) || defined(STM32F398xx)\ + 685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F303xC) || defined(STM32F358xx) + 686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC34; + 688:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the ADC3 & ADC4 clock configuration -----------------------------------------*/ + 689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->Adc34ClockSelection = __HAL_RCC_GET_ADC34_SOURCE(); + 690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F303xE || STM32F398xx || */ + 692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F303xC || STM32F358xx */ + 693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 694:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\ + 695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\ + 696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\ + 697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) + 698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM1; + 709 .loc 1 699 16 + 710 00ce 7B68 ldr r3, [r7, #4] + 711 00d0 1B68 ldr r3, [r3] + 712 .loc 1 699 39 + 713 00d2 43F48052 orr r2, r3, #4096 + 714 00d6 7B68 ldr r3, [r7, #4] + 715 00d8 1A60 str r2, [r3] + 700:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the TIM1 clock configuration -----------------------------------------*/ + 701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->Tim1ClockSelection = __HAL_RCC_GET_TIM1_SOURCE(); + 716 .loc 1 701 39 + 717 00da 074B ldr r3, .L35+4 + 718 00dc 1B6B ldr r3, [r3, #48] + 719 00de 03F48072 and r2, r3, #256 + 720 .loc 1 701 37 + 721 00e2 7B68 ldr r3, [r7, #4] + 722 00e4 DA62 str r2, [r3, #44] + 702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */ + 704:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F302xC || STM32F303xC || STM32F358xx || */ + 705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F303x8 || STM32F334x8 || STM32F328xx || */ + 706:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F301x8 || STM32F302x8 || STM32F318xx */ + 707:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 708:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F303xE) || defined(STM32F398xx)\ + 709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(STM32F303xC) || defined(STM32F358xx) + 710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM8; + 712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the TIM8 clock configuration -----------------------------------------*/ + 713:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->Tim8ClockSelection = __HAL_RCC_GET_TIM8_SOURCE(); + 714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F303xE || STM32F398xx || */ + 716:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* STM32F303xC || STM32F358xx */ + 717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 718:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) + 719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + ARM GAS /tmp/ccwmaYtI.s page 44 + + + 720:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= (RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | RCC_PERIPHCLK + 721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the TIM15 clock configuration -----------------------------------------*/ + 722:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->Tim15ClockSelection = __HAL_RCC_GET_TIM15_SOURCE(); + 723:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the TIM16 clock configuration -----------------------------------------*/ + 724:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->Tim16ClockSelection = __HAL_RCC_GET_TIM16_SOURCE(); + 725:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the TIM17 clock configuration -----------------------------------------*/ + 726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->Tim17ClockSelection = __HAL_RCC_GET_TIM17_SOURCE(); + 727:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */ + 729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F334x8) + 731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_HRTIM1; + 733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the HRTIM1 clock configuration -----------------------------------------*/ + 734:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->Hrtim1ClockSelection = __HAL_RCC_GET_HRTIM1_SOURCE(); + 735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F334x8 */ + 737:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F373xC) || defined(STM32F378xx) + 739:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SDADC; + 741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the SDADC clock configuration -----------------------------------------*/ + 742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->SdadcClockSelection = __HAL_RCC_GET_SDADC_SOURCE(); + 743:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_CEC; + 745:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the CEC clock configuration -----------------------------------------*/ + 746:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE(); + 747:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 748:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F373xC || STM32F378xx */ + 749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) + 751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 752:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM2; + 753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the TIM2 clock configuration -----------------------------------------*/ + 754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->Tim2ClockSelection = __HAL_RCC_GET_TIM2_SOURCE(); + 755:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM34; + 757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the TIM3 clock configuration -----------------------------------------*/ + 758:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->Tim34ClockSelection = __HAL_RCC_GET_TIM34_SOURCE(); + 759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 760:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM15; + 761:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the TIM15 clock configuration -----------------------------------------*/ + 762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->Tim15ClockSelection = __HAL_RCC_GET_TIM15_SOURCE(); + 763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 764:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM16; + 765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the TIM16 clock configuration -----------------------------------------*/ + 766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->Tim16ClockSelection = __HAL_RCC_GET_TIM16_SOURCE(); + 767:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM17; + 769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the TIM17 clock configuration -----------------------------------------*/ + 770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->Tim17ClockSelection = __HAL_RCC_GET_TIM17_SOURCE(); + 771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ + 773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined (STM32F303xE) || defined(STM32F398xx) + 775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM20; + 776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the TIM20 clock configuration -----------------------------------------*/ + ARM GAS /tmp/ccwmaYtI.s page 45 + + + 777:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** PeriphClkInit->Tim20ClockSelection = __HAL_RCC_GET_TIM20_SOURCE(); + 778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* STM32F303xE || STM32F398xx */ + 779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 723 .loc 1 779 1 + 724 00e6 00BF nop + 725 00e8 0C37 adds r7, r7, #12 + 726 .cfi_def_cfa_offset 4 + 727 00ea BD46 mov sp, r7 + 728 .cfi_def_cfa_register 13 + 729 @ sp needed + 730 00ec 5DF8047B ldr r7, [sp], #4 + 731 .cfi_restore 7 + 732 .cfi_def_cfa_offset 0 + 733 00f0 7047 bx lr + 734 .L36: + 735 00f2 00BF .align 2 + 736 .L35: + 737 00f4 27000100 .word 65575 + 738 00f8 00100240 .word 1073876992 + 739 .cfi_endproc + 740 .LFE131: + 742 .section .text.HAL_RCCEx_GetPeriphCLKFreq,"ax",%progbits + 743 .align 1 + 744 .global HAL_RCCEx_GetPeriphCLKFreq + 745 .syntax unified + 746 .thumb + 747 .thumb_func + 749 HAL_RCCEx_GetPeriphCLKFreq: + 750 .LFB132: + 780:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /** + 782:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @brief Returns the peripheral clock frequency + 783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @note Returns 0 if peripheral clock is unknown or 0xDEADDEAD if not applicable. + 784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @param PeriphClk Peripheral clock identifier + 785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * This parameter can be one of the following values: + 786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock + 787:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock + 788:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock + 789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @if STM32F301x8 + 790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock + 791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock + 792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock + 793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock + 794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock + 795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock + 796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock + 797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock + 798:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @endif + 799:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @if STM32F302x8 + 800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock + 801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock + 802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock + 803:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock + 804:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock + 805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock + 806:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock + 807:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock + ARM GAS /tmp/ccwmaYtI.s page 46 + + + 808:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock + 809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @endif + 810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @if STM32F302xC + 811:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock + 812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock + 813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock + 814:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock + 815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock + 816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock + 817:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock + 818:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock + 819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock + 820:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @endif + 821:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @if STM32F302xE + 822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock + 823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock + 824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock + 825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock + 826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock + 827:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock + 828:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock + 829:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock + 830:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock + 831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock + 832:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM2 TIM2 peripheral clock + 833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock + 834:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock + 835:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock + 836:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM34 TIM34 peripheral clock + 837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @endif + 838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @if STM32F303x8 + 839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock + 840:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock + 841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @endif + 842:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @if STM32F303xC + 843:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock + 844:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock + 845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock + 846:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock + 847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock + 848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock + 849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock + 850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock + 851:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_ADC34 ADC34 peripheral clock + 852:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock + 853:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM8 TIM8 peripheral clock + 854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @endif + 855:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @if STM32F303xE + 856:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock + 857:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock + 858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock + 859:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock + 860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock + 861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock + 862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock + 863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock + 864:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock + ARM GAS /tmp/ccwmaYtI.s page 47 + + + 865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_ADC34 ADC34 peripheral clock + 866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock + 867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM2 TIM2 peripheral clock + 868:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM8 TIM8 peripheral clock + 869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock + 870:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock + 871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock + 872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM20 TIM20 peripheral clock + 873:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM34 TIM34 peripheral clock + 874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @endif + 875:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @if STM32F318xx + 876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock + 877:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock + 878:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock + 879:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock + 880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock + 881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock + 882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock + 883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock + 884:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @endif + 885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @if STM32F328xx + 886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock + 887:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock + 888:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock + 889:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @endif + 890:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @if STM32F334x8 + 891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock + 892:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock + 893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_HRTIM1 HRTIM1 peripheral clock + 894:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @endif + 895:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @if STM32F358xx + 896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock + 897:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock + 898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock + 899:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock + 900:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock + 901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock + 902:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_ADC34 ADC34 peripheral clock + 903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock + 904:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM8 TIM8 peripheral clock + 905:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @endif + 906:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @if STM32F373xC + 907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock + 908:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock + 909:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock + 910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USB USB peripheral clock + 911:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock + 912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_SDADC SDADC peripheral clock + 913:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock + 914:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @endif + 915:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @if STM32F378xx + 916:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock + 917:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock + 918:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock + 919:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_ADC1 ADC1 peripheral clock + 920:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_SDADC SDADC peripheral clock + 921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_CEC CEC peripheral clock + ARM GAS /tmp/ccwmaYtI.s page 48 + + + 922:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @endif + 923:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @if STM32F398xx + 924:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock + 925:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock + 926:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock + 927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock + 928:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock + 929:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock + 930:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_I2S I2S peripheral clock + 931:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_ADC12 ADC12 peripheral clock + 932:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_ADC34 ADC34 peripheral clock + 933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM1 TIM1 peripheral clock + 934:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM2 TIM2 peripheral clock + 935:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM8 TIM8 peripheral clock + 936:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM15 TIM15 peripheral clock + 937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM16 TIM16 peripheral clock + 938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM17 TIM17 peripheral clock + 939:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM20 TIM20 peripheral clock + 940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @arg @ref RCC_PERIPHCLK_TIM34 TIM34 peripheral clock + 941:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** @endif + 942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @retval Frequency in Hz (0: means that no available frequency for the peripheral) + 943:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** */ + 944:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) + 945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 751 .loc 1 945 1 + 752 .cfi_startproc + 753 @ args = 0, pretend = 0, frame = 24 + 754 @ frame_needed = 1, uses_anonymous_args = 0 + 755 0000 80B5 push {r7, lr} + 756 .cfi_def_cfa_offset 8 + 757 .cfi_offset 7, -8 + 758 .cfi_offset 14, -4 + 759 0002 86B0 sub sp, sp, #24 + 760 .cfi_def_cfa_offset 32 + 761 0004 00AF add r7, sp, #0 + 762 .cfi_def_cfa_register 7 + 763 0006 7860 str r0, [r7, #4] + 946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* frequency == 0 : means that no available frequency for the peripheral */ + 947:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** uint32_t frequency = 0U; + 764 .loc 1 947 12 + 765 0008 0023 movs r3, #0 + 766 000a 7B61 str r3, [r7, #20] + 948:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** uint32_t srcclk = 0U; + 767 .loc 1 949 12 + 768 000c 0023 movs r3, #0 + 769 000e 3B61 str r3, [r7, #16] + 950:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34) + 951:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** static const uint16_t adc_pll_prediv_table[16U] = { 1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64 + 952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */ + 953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR_SDPRE) + 954:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** static const uint8_t sdadc_prescaler_table[16U] = { 2U, 4U, 6U, 8U, 10U, 12U, 14U, 16U, 20U, 24 + 955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR_SDPRE */ + 956:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 957:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check the parameters */ + 958:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); + 959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + ARM GAS /tmp/ccwmaYtI.s page 49 + + + 960:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** switch (PeriphClk) + 770 .loc 1 960 3 + 771 0010 7B68 ldr r3, [r7, #4] + 772 0012 B3F5003F cmp r3, #131072 + 773 0016 00F0ED81 beq .L38 + 774 001a 7B68 ldr r3, [r7, #4] + 775 001c B3F5003F cmp r3, #131072 + 776 0020 00F24E82 bhi .L91 + 777 0024 7B68 ldr r3, [r7, #4] + 778 0026 B3F5803F cmp r3, #65536 + 779 002a 74D0 beq .L40 + 780 002c 7B68 ldr r3, [r7, #4] + 781 002e B3F5803F cmp r3, #65536 + 782 0032 00F24582 bhi .L91 + 783 0036 7B68 ldr r3, [r7, #4] + 784 0038 B3F5805F cmp r3, #4096 + 785 003c 00F02482 beq .L41 + 786 0040 7B68 ldr r3, [r7, #4] + 787 0042 B3F5805F cmp r3, #4096 + 788 0046 00F23B82 bhi .L91 + 789 004a 7B68 ldr r3, [r7, #4] + 790 004c B3F5007F cmp r3, #512 + 791 0050 00F0BD81 beq .L42 + 792 0054 7B68 ldr r3, [r7, #4] + 793 0056 B3F5007F cmp r3, #512 + 794 005a 00F23182 bhi .L91 + 795 005e 7B68 ldr r3, [r7, #4] + 796 0060 802B cmp r3, #128 + 797 0062 00F0E481 beq .L43 + 798 0066 7B68 ldr r3, [r7, #4] + 799 0068 802B cmp r3, #128 + 800 006a 00F22982 bhi .L91 + 801 006e 7B68 ldr r3, [r7, #4] + 802 0070 202B cmp r3, #32 + 803 0072 4BD8 bhi .L44 + 804 0074 7B68 ldr r3, [r7, #4] + 805 0076 002B cmp r3, #0 + 806 0078 00F02282 beq .L91 + 807 007c 7B68 ldr r3, [r7, #4] + 808 007e 013B subs r3, r3, #1 + 809 0080 1F2B cmp r3, #31 + 810 0082 00F21D82 bhi .L91 + 811 0086 01A2 adr r2, .L46 + 812 0088 52F823F0 ldr pc, [r2, r3, lsl #2] + 813 .p2align 2 + 814 .L46: + 815 008c 7B010000 .word .L51+1 + 816 0090 D7010000 .word .L50+1 + 817 0094 C1040000 .word .L91+1 + 818 0098 39020000 .word .L49+1 + 819 009c C1040000 .word .L91+1 + 820 00a0 C1040000 .word .L91+1 + 821 00a4 C1040000 .word .L91+1 + 822 00a8 9B020000 .word .L48+1 + 823 00ac C1040000 .word .L91+1 + 824 00b0 C1040000 .word .L91+1 + 825 00b4 C1040000 .word .L91+1 + ARM GAS /tmp/ccwmaYtI.s page 50 + + + 826 00b8 C1040000 .word .L91+1 + 827 00bc C1040000 .word .L91+1 + 828 00c0 C1040000 .word .L91+1 + 829 00c4 C1040000 .word .L91+1 + 830 00c8 FD020000 .word .L47+1 + 831 00cc C1040000 .word .L91+1 + 832 00d0 C1040000 .word .L91+1 + 833 00d4 C1040000 .word .L91+1 + 834 00d8 C1040000 .word .L91+1 + 835 00dc C1040000 .word .L91+1 + 836 00e0 C1040000 .word .L91+1 + 837 00e4 C1040000 .word .L91+1 + 838 00e8 C1040000 .word .L91+1 + 839 00ec C1040000 .word .L91+1 + 840 00f0 C1040000 .word .L91+1 + 841 00f4 C1040000 .word .L91+1 + 842 00f8 C1040000 .word .L91+1 + 843 00fc C1040000 .word .L91+1 + 844 0100 C1040000 .word .L91+1 + 845 0104 C1040000 .word .L91+1 + 846 0108 5F030000 .word .L45+1 + 847 .p2align 1 + 848 .L44: + 849 010c 7B68 ldr r3, [r7, #4] + 850 010e 402B cmp r3, #64 + 851 0110 00F04481 beq .L52 + 961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_RTC: + 963:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 964:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the current RTC source */ + 965:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_RTC_SOURCE(); + 966:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 967:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if LSE is ready and if RTC clock selection is LSE */ + 968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if ((srcclk == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) + 969:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 970:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = LSE_VALUE; + 971:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 972:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if LSI is ready and if RTC clock selection is LSI */ + 973:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if ((srcclk == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))) + 974:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 975:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = LSI_VALUE; + 976:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 977:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/ + 978:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if ((srcclk == RCC_RTCCLKSOURCE_HSE_DIV32) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))) + 979:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HSE_VALUE / 32U; + 981:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 982:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; + 983:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_USART1: + 985:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 986:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the current USART1 source */ + 987:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_USART1_SOURCE(); + 988:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 989:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if USART1 clock selection is PCLK1 */ + 990:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_USART1CLKSOURCE_PCLK2) + 991:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if (srcclk == RCC_USART1CLKSOURCE_PCLK2) + ARM GAS /tmp/ccwmaYtI.s page 51 + + + 992:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 993:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetPCLK2Freq(); + 994:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #else + 996:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if (srcclk == RCC_USART1CLKSOURCE_PCLK1) + 997:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 998:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetPCLK1Freq(); + 999:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1000:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_USART1CLKSOURCE_PCLK2 */ +1001:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if HSI is ready and if USART1 clock selection is HSI */ +1002:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if ((srcclk == RCC_USART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) +1003:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HSI_VALUE; +1005:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1006:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if USART1 clock selection is SYSCLK */ +1007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK) +1008:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetSysClockFreq(); +1010:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1011:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if LSE is ready and if USART1 clock selection is LSE */ +1012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if ((srcclk == RCC_USART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) +1013:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1014:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = LSE_VALUE; +1015:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; +1017:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1018:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR3_USART2SW) +1019:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_USART2: +1020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1021:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the current USART2 source */ +1022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_USART2_SOURCE(); +1023:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if USART2 clock selection is PCLK1 */ +1025:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if (srcclk == RCC_USART2CLKSOURCE_PCLK1) +1026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetPCLK1Freq(); +1028:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if HSI is ready and if USART2 clock selection is HSI */ +1030:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if ((srcclk == RCC_USART2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) +1031:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1032:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HSI_VALUE; +1033:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if USART2 clock selection is SYSCLK */ +1035:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK) +1036:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetSysClockFreq(); +1038:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1039:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if LSE is ready and if USART2 clock selection is LSE */ +1040:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if ((srcclk == RCC_USART2CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) +1041:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = LSE_VALUE; +1043:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; +1045:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1046:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR3_USART2SW */ +1047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR3_USART3SW) +1048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_USART3: + ARM GAS /tmp/ccwmaYtI.s page 52 + + +1049:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1050:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the current USART3 source */ +1051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_USART3_SOURCE(); +1052:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if USART3 clock selection is PCLK1 */ +1054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if (srcclk == RCC_USART3CLKSOURCE_PCLK1) +1055:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetPCLK1Freq(); +1057:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if HSI is ready and if USART3 clock selection is HSI */ +1059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if ((srcclk == RCC_USART3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) +1060:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HSI_VALUE; +1062:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1063:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if USART3 clock selection is SYSCLK */ +1064:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if (srcclk == RCC_USART3CLKSOURCE_SYSCLK) +1065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1066:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetSysClockFreq(); +1067:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if LSE is ready and if USART3 clock selection is LSE */ +1069:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if ((srcclk == RCC_USART3CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) +1070:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = LSE_VALUE; +1072:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1073:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; +1074:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1075:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR3_USART3SW */ +1076:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR3_UART4SW) +1077:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_UART4: +1078:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1079:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the current UART4 source */ +1080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_UART4_SOURCE(); +1081:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if UART4 clock selection is PCLK1 */ +1083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if (srcclk == RCC_UART4CLKSOURCE_PCLK1) +1084:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetPCLK1Freq(); +1086:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1087:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if HSI is ready and if UART4 clock selection is HSI */ +1088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if ((srcclk == RCC_UART4CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) +1089:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1090:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HSI_VALUE; +1091:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1092:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if UART4 clock selection is SYSCLK */ +1093:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if (srcclk == RCC_UART4CLKSOURCE_SYSCLK) +1094:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetSysClockFreq(); +1096:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1097:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if LSE is ready and if UART4 clock selection is LSE */ +1098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if ((srcclk == RCC_UART4CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) +1099:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = LSE_VALUE; +1101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; +1103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR3_UART4SW */ +1105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR3_UART5SW) + ARM GAS /tmp/ccwmaYtI.s page 53 + + +1106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_UART5: +1107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the current UART5 source */ +1109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_UART5_SOURCE(); +1110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if UART5 clock selection is PCLK1 */ +1112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if (srcclk == RCC_UART5CLKSOURCE_PCLK1) +1113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetPCLK1Freq(); +1115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if HSI is ready and if UART5 clock selection is HSI */ +1117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if ((srcclk == RCC_UART5CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) +1118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HSI_VALUE; +1120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if UART5 clock selection is SYSCLK */ +1122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if (srcclk == RCC_UART5CLKSOURCE_SYSCLK) +1123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetSysClockFreq(); +1125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if LSE is ready and if UART5 clock selection is LSE */ +1127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if ((srcclk == RCC_UART5CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) +1128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = LSE_VALUE; +1130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; +1132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR3_UART5SW */ +1134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_I2C1: +1135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the current I2C1 source */ +1137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_I2C1_SOURCE(); +1138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if HSI is ready and if I2C1 clock selection is HSI */ +1140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if ((srcclk == RCC_I2C1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) +1141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HSI_VALUE; +1143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if I2C1 clock selection is SYSCLK */ +1145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK) +1146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetSysClockFreq(); +1148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; +1150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR3_I2C2SW) +1152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_I2C2: +1153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the current I2C2 source */ +1155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_I2C2_SOURCE(); +1156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if HSI is ready and if I2C2 clock selection is HSI */ +1158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if ((srcclk == RCC_I2C2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) +1159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HSI_VALUE; +1161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if I2C2 clock selection is SYSCLK */ + ARM GAS /tmp/ccwmaYtI.s page 54 + + +1163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if (srcclk == RCC_I2C2CLKSOURCE_SYSCLK) +1164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetSysClockFreq(); +1166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; +1168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR3_I2C2SW */ +1170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR3_I2C3SW) +1171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_I2C3: +1172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the current I2C3 source */ +1174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_I2C3_SOURCE(); +1175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if HSI is ready and if I2C3 clock selection is HSI */ +1177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if ((srcclk == RCC_I2C3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) +1178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HSI_VALUE; +1180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if I2C3 clock selection is SYSCLK */ +1182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if (srcclk == RCC_I2C3CLKSOURCE_SYSCLK) +1183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetSysClockFreq(); +1185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; +1187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR3_I2C3SW */ +1189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR_I2SSRC) +1190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_I2S: +1191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the current I2S source */ +1193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_I2S_SOURCE(); +1194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin */ +1196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if (srcclk == RCC_I2SCLKSOURCE_EXT) +1197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* External clock used. Frequency cannot be returned.*/ +1199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = 0xDEADDEADU; +1200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if I2S clock selection is SYSCLK */ +1202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if (srcclk == RCC_I2SCLKSOURCE_SYSCLK) +1203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetSysClockFreq(); +1205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; +1207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR_I2SSRC */ +1209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR_USBPRE) +1210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_USB: +1211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if PLL is ready */ +1213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)) +1214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the current USB source */ +1216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_USB_SOURCE(); +1217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if USB clock selection is not divided */ +1219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if (srcclk == RCC_USBCLKSOURCE_PLL) + ARM GAS /tmp/ccwmaYtI.s page 55 + + +1220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = RCC_GetPLLCLKFreq(); +1222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if USB clock selection is divided by 1.5 */ +1224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else /* RCC_USBCLKSOURCE_PLL_DIV1_5 */ +1225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = (RCC_GetPLLCLKFreq() * 3U) / 2U; +1227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; +1230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR_USBPRE */ +1232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR_ADCPRE) +1233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_ADC1: +1234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the current ADC1 source */ +1236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_ADC1_SOURCE(); +1237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR2_ADC1PRES) +1238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if ADC1 clock selection is AHB */ +1239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if (srcclk == RCC_ADC1PLLCLK_OFF) +1240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = SystemCoreClock; +1242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* PLL clock has been selected */ +1244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else +1245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if PLL is ready */ +1247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)) +1248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Frequency is the PLL frequency divided by ADC prescaler (1U/2U/4U/6U/8U/10U/12U/16U/32 +1250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> POSITION_VAL(RCC_CFGR2_ +1251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #else /* RCC_CFGR_ADCPRE */ +1254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* ADC1 is set to PLCK2 frequency divided by 2U/4U/6U/8U */ +1255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HAL_RCC_GetPCLK2Freq() / (((srcclk >> POSITION_VAL(RCC_CFGR_ADCPRE)) + 1U) * 2U) +1256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR2_ADC1PRES */ +1257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; +1258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR_ADCPRE */ +1260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR2_ADCPRE12) +1261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_ADC12: +1262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the current ADC12 source */ +1264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_ADC12_SOURCE(); +1265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if ADC12 clock selection is AHB */ +1266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if (srcclk == RCC_ADC12PLLCLK_OFF) +1267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = SystemCoreClock; +1269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* PLL clock has been selected */ +1271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else +1272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if PLL is ready */ +1274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)) +1275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Frequency is the PLL frequency divided by ADC prescaler (1U/2U/4U/6/8U/10U/12U/16U/32U + ARM GAS /tmp/ccwmaYtI.s page 56 + + +1277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> POSITION_VAL(RCC_CFGR2_ +1278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; +1281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR2_ADCPRE12 */ +1283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR2_ADCPRE34) +1284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_ADC34: +1285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the current ADC34 source */ +1287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_ADC34_SOURCE(); +1288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if ADC34 clock selection is AHB */ +1289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if (srcclk == RCC_ADC34PLLCLK_OFF) +1290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = SystemCoreClock; +1292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* PLL clock has been selected */ +1294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else +1295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if PLL is ready */ +1297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)) +1298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Frequency is the PLL frequency divided by ADC prescaler (1U/2U/4U/6U/8U/10U/12U/16U/32 +1300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = RCC_GetPLLCLKFreq() / adc_pll_prediv_table[(srcclk >> POSITION_VAL(RCC_CFGR2_ +1301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; +1304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR2_ADCPRE34 */ +1306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR3_TIM1SW) +1307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_TIM1: +1308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the current TIM1 source */ +1310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_TIM1_SOURCE(); +1311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if PLL is ready and if TIM1 clock selection is PLL */ +1313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if ((srcclk == RCC_TIM1CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))) +1314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = RCC_GetPLLCLKFreq(); +1316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if TIM1 clock selection is SYSCLK */ +1318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if (srcclk == RCC_TIM1CLK_HCLK) +1319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = SystemCoreClock; +1321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; +1323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR3_TIM1SW */ +1325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR3_TIM2SW) +1326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_TIM2: +1327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the current TIM2 source */ +1329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_TIM2_SOURCE(); +1330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if PLL is ready and if TIM2 clock selection is PLL */ +1332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if ((srcclk == RCC_TIM2CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))) +1333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + ARM GAS /tmp/ccwmaYtI.s page 57 + + +1334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = RCC_GetPLLCLKFreq(); +1335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if TIM2 clock selection is SYSCLK */ +1337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if (srcclk == RCC_TIM2CLK_HCLK) +1338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = SystemCoreClock; +1340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; +1342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR3_TIM2SW */ +1344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR3_TIM8SW) +1345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_TIM8: +1346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the current TIM8 source */ +1348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_TIM8_SOURCE(); +1349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if PLL is ready and if TIM8 clock selection is PLL */ +1351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if ((srcclk == RCC_TIM8CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))) +1352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = RCC_GetPLLCLKFreq(); +1354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if TIM8 clock selection is SYSCLK */ +1356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if (srcclk == RCC_TIM8CLK_HCLK) +1357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = SystemCoreClock; +1359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; +1361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR3_TIM8SW */ +1363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR3_TIM15SW) +1364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_TIM15: +1365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the current TIM15 source */ +1367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_TIM15_SOURCE(); +1368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if PLL is ready and if TIM15 clock selection is PLL */ +1370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if ((srcclk == RCC_TIM15CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))) +1371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = RCC_GetPLLCLKFreq(); +1373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if TIM15 clock selection is SYSCLK */ +1375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if (srcclk == RCC_TIM15CLK_HCLK) +1376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = SystemCoreClock; +1378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; +1380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR3_TIM15SW */ +1382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR3_TIM16SW) +1383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_TIM16: +1384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the current TIM16 source */ +1386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_TIM16_SOURCE(); +1387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if PLL is ready and if TIM16 clock selection is PLL */ +1389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if ((srcclk == RCC_TIM16CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))) +1390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + ARM GAS /tmp/ccwmaYtI.s page 58 + + +1391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = RCC_GetPLLCLKFreq(); +1392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if TIM16 clock selection is SYSCLK */ +1394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if (srcclk == RCC_TIM16CLK_HCLK) +1395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = SystemCoreClock; +1397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; +1399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR3_TIM16SW */ +1401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR3_TIM17SW) +1402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_TIM17: +1403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the current TIM17 source */ +1405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_TIM17_SOURCE(); +1406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if PLL is ready and if TIM17 clock selection is PLL */ +1408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if ((srcclk == RCC_TIM17CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))) +1409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = RCC_GetPLLCLKFreq(); +1411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if TIM17 clock selection is SYSCLK */ +1413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if (srcclk == RCC_TIM17CLK_HCLK) +1414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = SystemCoreClock; +1416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; +1418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR3_TIM17SW */ +1420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR3_TIM20SW) +1421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_TIM20: +1422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the current TIM20 source */ +1424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_TIM20_SOURCE(); +1425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if PLL is ready and if TIM20 clock selection is PLL */ +1427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if ((srcclk == RCC_TIM20CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))) +1428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = RCC_GetPLLCLKFreq(); +1430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if TIM20 clock selection is SYSCLK */ +1432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if (srcclk == RCC_TIM20CLK_HCLK) +1433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = SystemCoreClock; +1435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; +1437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR3_TIM20SW */ +1439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR3_TIM34SW) +1440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_TIM34: +1441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the current TIM34 source */ +1443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_TIM34_SOURCE(); +1444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if PLL is ready and if TIM34 clock selection is PLL */ +1446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if ((srcclk == RCC_TIM34CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))) +1447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + ARM GAS /tmp/ccwmaYtI.s page 59 + + +1448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = RCC_GetPLLCLKFreq(); +1449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if TIM34 clock selection is SYSCLK */ +1451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if (srcclk == RCC_TIM34CLK_HCLK) +1452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = SystemCoreClock; +1454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; +1456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR3_TIM34SW */ +1458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR3_HRTIM1SW) +1459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_HRTIM1: +1460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the current HRTIM1 source */ +1462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_HRTIM1_SOURCE(); +1463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if PLL is ready and if HRTIM1 clock selection is PLL */ +1465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if ((srcclk == RCC_HRTIM1CLK_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY))) +1466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = RCC_GetPLLCLKFreq(); +1468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if HRTIM1 clock selection is SYSCLK */ +1470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if (srcclk == RCC_HRTIM1CLK_HCLK) +1471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = SystemCoreClock; +1473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; +1475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR3_HRTIM1SW */ +1477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR_SDPRE) +1478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_SDADC: +1479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the current SDADC source */ +1481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_SDADC_SOURCE(); +1482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Frequency is the system frequency divided by SDADC prescaler (2U/4U/6U/8U/10U/12U/14U/16U/ +1483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = SystemCoreClock / sdadc_prescaler_table[(srcclk >> POSITION_VAL(RCC_CFGR_SDPRE)) +1484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; +1485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR_SDPRE */ +1487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR3_CECSW) +1488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** case RCC_PERIPHCLK_CEC: +1489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Get the current CEC source */ +1491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** srcclk = __HAL_RCC_GET_CEC_SOURCE(); +1492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if HSI is ready and if CEC clock selection is HSI */ +1494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if ((srcclk == RCC_CECCLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))) +1495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = HSI_VALUE; +1497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if LSE is ready and if CEC clock selection is LSE */ +1499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else if ((srcclk == RCC_CECCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY))) +1500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** frequency = LSE_VALUE; +1502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; +1504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + ARM GAS /tmp/ccwmaYtI.s page 60 + + +1505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR3_CECSW */ +1506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** default: +1507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** break; + 852 .loc 1 1508 7 + 853 0114 D4E1 b .L91 + 854 .L40: + 965:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 855 .loc 1 965 16 + 856 0116 9A4B ldr r3, .L105 + 857 0118 1B6A ldr r3, [r3, #32] + 965:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 858 .loc 1 965 14 + 859 011a 03F44073 and r3, r3, #768 + 860 011e 3B61 str r3, [r7, #16] + 968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 861 .loc 1 968 10 + 862 0120 3B69 ldr r3, [r7, #16] + 863 0122 B3F5807F cmp r3, #256 + 864 0126 09D1 bne .L53 + 968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 865 .loc 1 968 48 discriminator 1 + 866 0128 954B ldr r3, .L105 + 867 012a 1B6A ldr r3, [r3, #32] + 868 012c 03F00203 and r3, r3, #2 + 968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 869 .loc 1 968 44 discriminator 1 + 870 0130 022B cmp r3, #2 + 871 0132 03D1 bne .L53 + 970:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 872 .loc 1 970 19 + 873 0134 4FF40043 mov r3, #32768 + 874 0138 7B61 str r3, [r7, #20] + 875 013a 1DE0 b .L54 + 876 .L53: + 973:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 877 .loc 1 973 15 + 878 013c 3B69 ldr r3, [r7, #16] + 879 013e B3F5007F cmp r3, #512 + 880 0142 09D1 bne .L55 + 973:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 881 .loc 1 973 53 discriminator 1 + 882 0144 8E4B ldr r3, .L105 + 883 0146 5B6A ldr r3, [r3, #36] + 884 0148 03F00203 and r3, r3, #2 + 973:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 885 .loc 1 973 49 discriminator 1 + 886 014c 022B cmp r3, #2 + 887 014e 03D1 bne .L55 + 975:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 888 .loc 1 975 19 + 889 0150 49F64043 movw r3, #40000 + 890 0154 7B61 str r3, [r7, #20] + 891 0156 0FE0 b .L54 + 892 .L55: + 978:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 893 .loc 1 978 15 + ARM GAS /tmp/ccwmaYtI.s page 61 + + + 894 0158 3B69 ldr r3, [r7, #16] + 895 015a B3F5407F cmp r3, #768 + 896 015e 40F0B181 bne .L92 + 978:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 897 .loc 1 978 59 discriminator 1 + 898 0162 874B ldr r3, .L105 + 899 0164 1B68 ldr r3, [r3] + 900 0166 03F40033 and r3, r3, #131072 + 978:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 901 .loc 1 978 55 discriminator 1 + 902 016a B3F5003F cmp r3, #131072 + 903 016e 40F0A981 bne .L92 + 980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 904 .loc 1 980 19 + 905 0172 844B ldr r3, .L105+4 + 906 0174 7B61 str r3, [r7, #20] + 982:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 907 .loc 1 982 7 + 908 0176 A5E1 b .L92 + 909 .L54: + 910 0178 A4E1 b .L92 + 911 .L51: + 987:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 912 .loc 1 987 16 + 913 017a 814B ldr r3, .L105 + 914 017c 1B6B ldr r3, [r3, #48] + 987:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 915 .loc 1 987 14 + 916 017e 03F00303 and r3, r3, #3 + 917 0182 3B61 str r3, [r7, #16] + 991:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 918 .loc 1 991 10 + 919 0184 3B69 ldr r3, [r7, #16] + 920 0186 002B cmp r3, #0 + 921 0188 03D1 bne .L57 + 993:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 922 .loc 1 993 21 + 923 018a FFF7FEFF bl HAL_RCC_GetPCLK2Freq + 924 018e 7861 str r0, [r7, #20] +1016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 925 .loc 1 1016 7 + 926 0190 9AE1 b .L93 + 927 .L57: +1002:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 928 .loc 1 1002 15 + 929 0192 3B69 ldr r3, [r7, #16] + 930 0194 032B cmp r3, #3 + 931 0196 08D1 bne .L59 +1002:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 932 .loc 1 1002 56 discriminator 1 + 933 0198 794B ldr r3, .L105 + 934 019a 1B68 ldr r3, [r3] + 935 019c 03F00203 and r3, r3, #2 +1002:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 936 .loc 1 1002 52 discriminator 1 + 937 01a0 022B cmp r3, #2 + 938 01a2 02D1 bne .L59 + ARM GAS /tmp/ccwmaYtI.s page 62 + + +1004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 939 .loc 1 1004 19 + 940 01a4 784B ldr r3, .L105+8 + 941 01a6 7B61 str r3, [r7, #20] +1016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 942 .loc 1 1016 7 + 943 01a8 8EE1 b .L93 + 944 .L59: +1007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 945 .loc 1 1007 15 + 946 01aa 3B69 ldr r3, [r7, #16] + 947 01ac 012B cmp r3, #1 + 948 01ae 03D1 bne .L60 +1009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 949 .loc 1 1009 21 + 950 01b0 FFF7FEFF bl HAL_RCC_GetSysClockFreq + 951 01b4 7861 str r0, [r7, #20] +1016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 952 .loc 1 1016 7 + 953 01b6 87E1 b .L93 + 954 .L60: +1012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 955 .loc 1 1012 15 + 956 01b8 3B69 ldr r3, [r7, #16] + 957 01ba 022B cmp r3, #2 + 958 01bc 40F08481 bne .L93 +1012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 959 .loc 1 1012 56 discriminator 1 + 960 01c0 6F4B ldr r3, .L105 + 961 01c2 1B6A ldr r3, [r3, #32] + 962 01c4 03F00203 and r3, r3, #2 +1012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 963 .loc 1 1012 52 discriminator 1 + 964 01c8 022B cmp r3, #2 + 965 01ca 40F07D81 bne .L93 +1014:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 966 .loc 1 1014 19 + 967 01ce 4FF40043 mov r3, #32768 + 968 01d2 7B61 str r3, [r7, #20] +1016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 969 .loc 1 1016 7 + 970 01d4 78E1 b .L93 + 971 .L50: +1022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 972 .loc 1 1022 16 + 973 01d6 6A4B ldr r3, .L105 + 974 01d8 1B6B ldr r3, [r3, #48] +1022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 975 .loc 1 1022 14 + 976 01da 03F44033 and r3, r3, #196608 + 977 01de 3B61 str r3, [r7, #16] +1025:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 978 .loc 1 1025 10 + 979 01e0 3B69 ldr r3, [r7, #16] + 980 01e2 002B cmp r3, #0 + 981 01e4 03D1 bne .L61 +1027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + ARM GAS /tmp/ccwmaYtI.s page 63 + + + 982 .loc 1 1027 21 + 983 01e6 FFF7FEFF bl HAL_RCC_GetPCLK1Freq + 984 01ea 7861 str r0, [r7, #20] +1044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 985 .loc 1 1044 7 + 986 01ec 6EE1 b .L94 + 987 .L61: +1030:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 988 .loc 1 1030 15 + 989 01ee 3B69 ldr r3, [r7, #16] + 990 01f0 B3F5403F cmp r3, #196608 + 991 01f4 08D1 bne .L63 +1030:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 992 .loc 1 1030 56 discriminator 1 + 993 01f6 624B ldr r3, .L105 + 994 01f8 1B68 ldr r3, [r3] + 995 01fa 03F00203 and r3, r3, #2 +1030:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 996 .loc 1 1030 52 discriminator 1 + 997 01fe 022B cmp r3, #2 + 998 0200 02D1 bne .L63 +1032:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 999 .loc 1 1032 19 + 1000 0202 614B ldr r3, .L105+8 + 1001 0204 7B61 str r3, [r7, #20] +1044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1002 .loc 1 1044 7 + 1003 0206 61E1 b .L94 + 1004 .L63: +1035:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1005 .loc 1 1035 15 + 1006 0208 3B69 ldr r3, [r7, #16] + 1007 020a B3F5803F cmp r3, #65536 + 1008 020e 03D1 bne .L64 +1037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1009 .loc 1 1037 21 + 1010 0210 FFF7FEFF bl HAL_RCC_GetSysClockFreq + 1011 0214 7861 str r0, [r7, #20] +1044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1012 .loc 1 1044 7 + 1013 0216 59E1 b .L94 + 1014 .L64: +1040:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1015 .loc 1 1040 15 + 1016 0218 3B69 ldr r3, [r7, #16] + 1017 021a B3F5003F cmp r3, #131072 + 1018 021e 40F05581 bne .L94 +1040:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1019 .loc 1 1040 56 discriminator 1 + 1020 0222 574B ldr r3, .L105 + 1021 0224 1B6A ldr r3, [r3, #32] + 1022 0226 03F00203 and r3, r3, #2 +1040:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1023 .loc 1 1040 52 discriminator 1 + 1024 022a 022B cmp r3, #2 + 1025 022c 40F04E81 bne .L94 +1042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + ARM GAS /tmp/ccwmaYtI.s page 64 + + + 1026 .loc 1 1042 19 + 1027 0230 4FF40043 mov r3, #32768 + 1028 0234 7B61 str r3, [r7, #20] +1044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1029 .loc 1 1044 7 + 1030 0236 49E1 b .L94 + 1031 .L49: +1051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 1032 .loc 1 1051 16 + 1033 0238 514B ldr r3, .L105 + 1034 023a 1B6B ldr r3, [r3, #48] +1051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 1035 .loc 1 1051 14 + 1036 023c 03F44023 and r3, r3, #786432 + 1037 0240 3B61 str r3, [r7, #16] +1054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1038 .loc 1 1054 10 + 1039 0242 3B69 ldr r3, [r7, #16] + 1040 0244 002B cmp r3, #0 + 1041 0246 03D1 bne .L65 +1056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1042 .loc 1 1056 21 + 1043 0248 FFF7FEFF bl HAL_RCC_GetPCLK1Freq + 1044 024c 7861 str r0, [r7, #20] +1073:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1045 .loc 1 1073 6 + 1046 024e 3FE1 b .L95 + 1047 .L65: +1059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1048 .loc 1 1059 15 + 1049 0250 3B69 ldr r3, [r7, #16] + 1050 0252 B3F5402F cmp r3, #786432 + 1051 0256 08D1 bne .L67 +1059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1052 .loc 1 1059 56 discriminator 1 + 1053 0258 494B ldr r3, .L105 + 1054 025a 1B68 ldr r3, [r3] + 1055 025c 03F00203 and r3, r3, #2 +1059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1056 .loc 1 1059 52 discriminator 1 + 1057 0260 022B cmp r3, #2 + 1058 0262 02D1 bne .L67 +1061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1059 .loc 1 1061 19 + 1060 0264 484B ldr r3, .L105+8 + 1061 0266 7B61 str r3, [r7, #20] +1073:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1062 .loc 1 1073 6 + 1063 0268 32E1 b .L95 + 1064 .L67: +1064:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1065 .loc 1 1064 15 + 1066 026a 3B69 ldr r3, [r7, #16] + 1067 026c B3F5802F cmp r3, #262144 + 1068 0270 03D1 bne .L68 +1066:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1069 .loc 1 1066 21 + ARM GAS /tmp/ccwmaYtI.s page 65 + + + 1070 0272 FFF7FEFF bl HAL_RCC_GetSysClockFreq + 1071 0276 7861 str r0, [r7, #20] +1073:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1072 .loc 1 1073 6 + 1073 0278 2AE1 b .L95 + 1074 .L68: +1069:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1075 .loc 1 1069 15 + 1076 027a 3B69 ldr r3, [r7, #16] + 1077 027c B3F5002F cmp r3, #524288 + 1078 0280 40F02681 bne .L95 +1069:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1079 .loc 1 1069 56 discriminator 1 + 1080 0284 3E4B ldr r3, .L105 + 1081 0286 1B6A ldr r3, [r3, #32] + 1082 0288 03F00203 and r3, r3, #2 +1069:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1083 .loc 1 1069 52 discriminator 1 + 1084 028c 022B cmp r3, #2 + 1085 028e 40F01F81 bne .L95 +1071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1086 .loc 1 1071 19 + 1087 0292 4FF40043 mov r3, #32768 + 1088 0296 7B61 str r3, [r7, #20] +1073:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1089 .loc 1 1073 6 + 1090 0298 1AE1 b .L95 + 1091 .L48: +1080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 1092 .loc 1 1080 16 + 1093 029a 394B ldr r3, .L105 + 1094 029c 1B6B ldr r3, [r3, #48] +1080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 1095 .loc 1 1080 14 + 1096 029e 03F44013 and r3, r3, #3145728 + 1097 02a2 3B61 str r3, [r7, #16] +1083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1098 .loc 1 1083 10 + 1099 02a4 3B69 ldr r3, [r7, #16] + 1100 02a6 002B cmp r3, #0 + 1101 02a8 03D1 bne .L69 +1085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1102 .loc 1 1085 21 + 1103 02aa FFF7FEFF bl HAL_RCC_GetPCLK1Freq + 1104 02ae 7861 str r0, [r7, #20] +1102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1105 .loc 1 1102 7 + 1106 02b0 10E1 b .L96 + 1107 .L69: +1088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1108 .loc 1 1088 15 + 1109 02b2 3B69 ldr r3, [r7, #16] + 1110 02b4 B3F5401F cmp r3, #3145728 + 1111 02b8 08D1 bne .L71 +1088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1112 .loc 1 1088 55 discriminator 1 + 1113 02ba 314B ldr r3, .L105 + ARM GAS /tmp/ccwmaYtI.s page 66 + + + 1114 02bc 1B68 ldr r3, [r3] + 1115 02be 03F00203 and r3, r3, #2 +1088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1116 .loc 1 1088 51 discriminator 1 + 1117 02c2 022B cmp r3, #2 + 1118 02c4 02D1 bne .L71 +1090:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1119 .loc 1 1090 19 + 1120 02c6 304B ldr r3, .L105+8 + 1121 02c8 7B61 str r3, [r7, #20] +1102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1122 .loc 1 1102 7 + 1123 02ca 03E1 b .L96 + 1124 .L71: +1093:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1125 .loc 1 1093 15 + 1126 02cc 3B69 ldr r3, [r7, #16] + 1127 02ce B3F5801F cmp r3, #1048576 + 1128 02d2 03D1 bne .L72 +1095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1129 .loc 1 1095 21 + 1130 02d4 FFF7FEFF bl HAL_RCC_GetSysClockFreq + 1131 02d8 7861 str r0, [r7, #20] +1102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1132 .loc 1 1102 7 + 1133 02da FBE0 b .L96 + 1134 .L72: +1098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1135 .loc 1 1098 15 + 1136 02dc 3B69 ldr r3, [r7, #16] + 1137 02de B3F5001F cmp r3, #2097152 + 1138 02e2 40F0F780 bne .L96 +1098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1139 .loc 1 1098 55 discriminator 1 + 1140 02e6 264B ldr r3, .L105 + 1141 02e8 1B6A ldr r3, [r3, #32] + 1142 02ea 03F00203 and r3, r3, #2 +1098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1143 .loc 1 1098 51 discriminator 1 + 1144 02ee 022B cmp r3, #2 + 1145 02f0 40F0F080 bne .L96 +1100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1146 .loc 1 1100 19 + 1147 02f4 4FF40043 mov r3, #32768 + 1148 02f8 7B61 str r3, [r7, #20] +1102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1149 .loc 1 1102 7 + 1150 02fa EBE0 b .L96 + 1151 .L47: +1109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 1152 .loc 1 1109 16 + 1153 02fc 204B ldr r3, .L105 + 1154 02fe 1B6B ldr r3, [r3, #48] +1109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 1155 .loc 1 1109 14 + 1156 0300 03F44003 and r3, r3, #12582912 + 1157 0304 3B61 str r3, [r7, #16] + ARM GAS /tmp/ccwmaYtI.s page 67 + + +1112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1158 .loc 1 1112 10 + 1159 0306 3B69 ldr r3, [r7, #16] + 1160 0308 002B cmp r3, #0 + 1161 030a 03D1 bne .L73 +1114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1162 .loc 1 1114 21 + 1163 030c FFF7FEFF bl HAL_RCC_GetPCLK1Freq + 1164 0310 7861 str r0, [r7, #20] +1131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1165 .loc 1 1131 7 + 1166 0312 E1E0 b .L97 + 1167 .L73: +1117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1168 .loc 1 1117 15 + 1169 0314 3B69 ldr r3, [r7, #16] + 1170 0316 B3F5400F cmp r3, #12582912 + 1171 031a 08D1 bne .L75 +1117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1172 .loc 1 1117 55 discriminator 1 + 1173 031c 184B ldr r3, .L105 + 1174 031e 1B68 ldr r3, [r3] + 1175 0320 03F00203 and r3, r3, #2 +1117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1176 .loc 1 1117 51 discriminator 1 + 1177 0324 022B cmp r3, #2 + 1178 0326 02D1 bne .L75 +1119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1179 .loc 1 1119 19 + 1180 0328 174B ldr r3, .L105+8 + 1181 032a 7B61 str r3, [r7, #20] +1131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1182 .loc 1 1131 7 + 1183 032c D4E0 b .L97 + 1184 .L75: +1122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1185 .loc 1 1122 15 + 1186 032e 3B69 ldr r3, [r7, #16] + 1187 0330 B3F5800F cmp r3, #4194304 + 1188 0334 03D1 bne .L76 +1124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1189 .loc 1 1124 21 + 1190 0336 FFF7FEFF bl HAL_RCC_GetSysClockFreq + 1191 033a 7861 str r0, [r7, #20] +1131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1192 .loc 1 1131 7 + 1193 033c CCE0 b .L97 + 1194 .L76: +1127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1195 .loc 1 1127 15 + 1196 033e 3B69 ldr r3, [r7, #16] + 1197 0340 B3F5000F cmp r3, #8388608 + 1198 0344 40F0C880 bne .L97 +1127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1199 .loc 1 1127 55 discriminator 1 + 1200 0348 0D4B ldr r3, .L105 + 1201 034a 1B6A ldr r3, [r3, #32] + ARM GAS /tmp/ccwmaYtI.s page 68 + + + 1202 034c 03F00203 and r3, r3, #2 +1127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1203 .loc 1 1127 51 discriminator 1 + 1204 0350 022B cmp r3, #2 + 1205 0352 40F0C180 bne .L97 +1129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1206 .loc 1 1129 19 + 1207 0356 4FF40043 mov r3, #32768 + 1208 035a 7B61 str r3, [r7, #20] +1131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1209 .loc 1 1131 7 + 1210 035c BCE0 b .L97 + 1211 .L45: +1137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 1212 .loc 1 1137 16 + 1213 035e 084B ldr r3, .L105 + 1214 0360 1B6B ldr r3, [r3, #48] +1137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 1215 .loc 1 1137 14 + 1216 0362 03F01003 and r3, r3, #16 + 1217 0366 3B61 str r3, [r7, #16] +1140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1218 .loc 1 1140 10 + 1219 0368 3B69 ldr r3, [r7, #16] + 1220 036a 002B cmp r3, #0 + 1221 036c 0ED1 bne .L77 +1140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1222 .loc 1 1140 49 discriminator 1 + 1223 036e 044B ldr r3, .L105 + 1224 0370 1B68 ldr r3, [r3] + 1225 0372 03F00203 and r3, r3, #2 +1140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1226 .loc 1 1140 45 discriminator 1 + 1227 0376 022B cmp r3, #2 + 1228 0378 08D1 bne .L77 +1142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1229 .loc 1 1142 19 + 1230 037a 034B ldr r3, .L105+8 + 1231 037c 7B61 str r3, [r7, #20] +1149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1232 .loc 1 1149 7 + 1233 037e ADE0 b .L98 + 1234 .L106: + 1235 .align 2 + 1236 .L105: + 1237 0380 00100240 .word 1073876992 + 1238 0384 20A10700 .word 500000 + 1239 0388 00127A00 .word 8000000 + 1240 .L77: +1145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1241 .loc 1 1145 15 + 1242 038c 3B69 ldr r3, [r7, #16] + 1243 038e 102B cmp r3, #16 + 1244 0390 40F0A480 bne .L98 +1147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1245 .loc 1 1147 21 + 1246 0394 FFF7FEFF bl HAL_RCC_GetSysClockFreq + ARM GAS /tmp/ccwmaYtI.s page 69 + + + 1247 0398 7861 str r0, [r7, #20] +1149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1248 .loc 1 1149 7 + 1249 039a 9FE0 b .L98 + 1250 .L52: +1155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 1251 .loc 1 1155 16 + 1252 039c 574B ldr r3, .L107 + 1253 039e 1B6B ldr r3, [r3, #48] +1155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 1254 .loc 1 1155 14 + 1255 03a0 03F02003 and r3, r3, #32 + 1256 03a4 3B61 str r3, [r7, #16] +1158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1257 .loc 1 1158 10 + 1258 03a6 3B69 ldr r3, [r7, #16] + 1259 03a8 002B cmp r3, #0 + 1260 03aa 08D1 bne .L79 +1158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1261 .loc 1 1158 49 discriminator 1 + 1262 03ac 534B ldr r3, .L107 + 1263 03ae 1B68 ldr r3, [r3] + 1264 03b0 03F00203 and r3, r3, #2 +1158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1265 .loc 1 1158 45 discriminator 1 + 1266 03b4 022B cmp r3, #2 + 1267 03b6 02D1 bne .L79 +1160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1268 .loc 1 1160 19 + 1269 03b8 514B ldr r3, .L107+4 + 1270 03ba 7B61 str r3, [r7, #20] +1167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1271 .loc 1 1167 7 + 1272 03bc 90E0 b .L99 + 1273 .L79: +1163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1274 .loc 1 1163 15 + 1275 03be 3B69 ldr r3, [r7, #16] + 1276 03c0 202B cmp r3, #32 + 1277 03c2 40F08D80 bne .L99 +1165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1278 .loc 1 1165 21 + 1279 03c6 FFF7FEFF bl HAL_RCC_GetSysClockFreq + 1280 03ca 7861 str r0, [r7, #20] +1167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1281 .loc 1 1167 7 + 1282 03cc 88E0 b .L99 + 1283 .L42: +1193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 1284 .loc 1 1193 16 + 1285 03ce 4B4B ldr r3, .L107 + 1286 03d0 5B68 ldr r3, [r3, #4] +1193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 1287 .loc 1 1193 14 + 1288 03d2 03F40003 and r3, r3, #8388608 + 1289 03d6 3B61 str r3, [r7, #16] +1196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + ARM GAS /tmp/ccwmaYtI.s page 70 + + + 1290 .loc 1 1196 10 + 1291 03d8 3B69 ldr r3, [r7, #16] + 1292 03da B3F5000F cmp r3, #8388608 + 1293 03de 02D1 bne .L81 +1199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1294 .loc 1 1199 19 + 1295 03e0 484B ldr r3, .L107+8 + 1296 03e2 7B61 str r3, [r7, #20] +1206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1297 .loc 1 1206 7 + 1298 03e4 7EE0 b .L100 + 1299 .L81: +1202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1300 .loc 1 1202 15 + 1301 03e6 3B69 ldr r3, [r7, #16] + 1302 03e8 002B cmp r3, #0 + 1303 03ea 7BD1 bne .L100 +1204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1304 .loc 1 1204 21 + 1305 03ec FFF7FEFF bl HAL_RCC_GetSysClockFreq + 1306 03f0 7861 str r0, [r7, #20] +1206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1307 .loc 1 1206 7 + 1308 03f2 77E0 b .L100 + 1309 .L38: +1213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1310 .loc 1 1213 11 + 1311 03f4 414B ldr r3, .L107 + 1312 03f6 1B68 ldr r3, [r3] + 1313 03f8 03F00073 and r3, r3, #33554432 +1213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1314 .loc 1 1213 10 + 1315 03fc B3F1007F cmp r3, #33554432 + 1316 0400 72D1 bne .L101 +1216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 1317 .loc 1 1216 18 + 1318 0402 3E4B ldr r3, .L107 + 1319 0404 5B68 ldr r3, [r3, #4] +1216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 1320 .loc 1 1216 16 + 1321 0406 03F48003 and r3, r3, #4194304 + 1322 040a 3B61 str r3, [r7, #16] +1219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1323 .loc 1 1219 12 + 1324 040c 3B69 ldr r3, [r7, #16] + 1325 040e B3F5800F cmp r3, #4194304 + 1326 0412 03D1 bne .L84 +1221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1327 .loc 1 1221 23 + 1328 0414 FFF7FEFF bl RCC_GetPLLCLKFreq + 1329 0418 7861 str r0, [r7, #20] +1229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1330 .loc 1 1229 7 + 1331 041a 65E0 b .L101 + 1332 .L84: +1226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1333 .loc 1 1226 24 + ARM GAS /tmp/ccwmaYtI.s page 71 + + + 1334 041c FFF7FEFF bl RCC_GetPLLCLKFreq + 1335 0420 0246 mov r2, r0 +1226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1336 .loc 1 1226 44 discriminator 1 + 1337 0422 1346 mov r3, r2 + 1338 0424 5B00 lsls r3, r3, #1 + 1339 0426 1344 add r3, r3, r2 +1226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1340 .loc 1 1226 21 discriminator 1 + 1341 0428 5B08 lsrs r3, r3, #1 + 1342 042a 7B61 str r3, [r7, #20] +1229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1343 .loc 1 1229 7 + 1344 042c 5CE0 b .L101 + 1345 .L43: +1264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if ADC12 clock selection is AHB */ + 1346 .loc 1 1264 16 + 1347 042e 334B ldr r3, .L107 + 1348 0430 DB6A ldr r3, [r3, #44] +1264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* Check if ADC12 clock selection is AHB */ + 1349 .loc 1 1264 14 + 1350 0432 03F4F873 and r3, r3, #496 + 1351 0436 3B61 str r3, [r7, #16] +1266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1352 .loc 1 1266 10 + 1353 0438 3B69 ldr r3, [r7, #16] + 1354 043a 002B cmp r3, #0 + 1355 043c 03D1 bne .L85 +1268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1356 .loc 1 1268 21 + 1357 043e 324B ldr r3, .L107+12 + 1358 0440 1B68 ldr r3, [r3] + 1359 0442 7B61 str r3, [r7, #20] +1280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1360 .loc 1 1280 7 + 1361 0444 52E0 b .L102 + 1362 .L85: +1274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1363 .loc 1 1274 13 + 1364 0446 2D4B ldr r3, .L107 + 1365 0448 1B68 ldr r3, [r3] + 1366 044a 03F00073 and r3, r3, #33554432 +1274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1367 .loc 1 1274 12 + 1368 044e B3F1007F cmp r3, #33554432 + 1369 0452 4BD1 bne .L102 +1277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1370 .loc 1 1277 23 + 1371 0454 FFF7FEFF bl RCC_GetPLLCLKFreq + 1372 0458 0246 mov r2, r0 + 1373 045a 4FF4F873 mov r3, #496 + 1374 045e FB60 str r3, [r7, #12] + 1375 .LBB30: + 1376 .LBB31: + 988:Drivers/CMSIS/Include/cmsis_gcc.h **** #else + 1377 .loc 2 988 4 + 1378 0460 FB68 ldr r3, [r7, #12] + ARM GAS /tmp/ccwmaYtI.s page 72 + + + 1379 .syntax unified + 1380 @ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 + 1381 0462 93FAA3F3 rbit r3, r3 + 1382 @ 0 "" 2 + 1383 .thumb + 1384 .syntax unified + 1385 0466 BB60 str r3, [r7, #8] + 1386 .loc 2 1001 10 + 1387 0468 BB68 ldr r3, [r7, #8] + 1388 .LBE31: + 1389 .LBE30: +1277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1390 .loc 1 1277 77 discriminator 2 + 1391 046a B3FA83F3 clz r3, r3 +1277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1392 .loc 1 1277 77 is_stmt 0 discriminator 3 + 1393 046e DBB2 uxtb r3, r3 + 1394 0470 1946 mov r1, r3 +1277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1395 .loc 1 1277 74 is_stmt 1 discriminator 3 + 1396 0472 3B69 ldr r3, [r7, #16] + 1397 0474 CB40 lsrs r3, r3, r1 +1277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1398 .loc 1 1277 111 discriminator 3 + 1399 0476 03F00F03 and r3, r3, #15 +1277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1400 .loc 1 1277 65 discriminator 3 + 1401 047a 2449 ldr r1, .L107+16 + 1402 047c 31F81330 ldrh r3, [r1, r3, lsl #1] +1277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1403 .loc 1 1277 21 discriminator 3 + 1404 0480 B2FBF3F3 udiv r3, r2, r3 + 1405 0484 7B61 str r3, [r7, #20] +1280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1406 .loc 1 1280 7 + 1407 0486 31E0 b .L102 + 1408 .L41: +1310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 1409 .loc 1 1310 16 + 1410 0488 1C4B ldr r3, .L107 + 1411 048a 1B6B ldr r3, [r3, #48] +1310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** + 1412 .loc 1 1310 14 + 1413 048c 03F48073 and r3, r3, #256 + 1414 0490 3B61 str r3, [r7, #16] +1313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1415 .loc 1 1313 10 + 1416 0492 3B69 ldr r3, [r7, #16] + 1417 0494 B3F5807F cmp r3, #256 + 1418 0498 0BD1 bne .L88 +1313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1419 .loc 1 1313 46 discriminator 1 + 1420 049a 184B ldr r3, .L107 + 1421 049c 1B68 ldr r3, [r3] + 1422 049e 03F00073 and r3, r3, #33554432 +1313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1423 .loc 1 1313 42 discriminator 1 + ARM GAS /tmp/ccwmaYtI.s page 73 + + + 1424 04a2 B3F1007F cmp r3, #33554432 + 1425 04a6 04D1 bne .L88 +1315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1426 .loc 1 1315 21 + 1427 04a8 FFF7FEFF bl RCC_GetPLLCLKFreq + 1428 04ac 7861 str r0, [r7, #20] +1315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1429 .loc 1 1315 19 + 1430 04ae 00BF nop +1322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1431 .loc 1 1322 7 + 1432 04b0 1EE0 b .L103 + 1433 .L88: +1318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1434 .loc 1 1318 15 + 1435 04b2 3B69 ldr r3, [r7, #16] + 1436 04b4 002B cmp r3, #0 + 1437 04b6 1BD1 bne .L103 +1320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1438 .loc 1 1320 19 + 1439 04b8 134B ldr r3, .L107+12 + 1440 04ba 1B68 ldr r3, [r3] + 1441 04bc 7B61 str r3, [r7, #20] +1322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1442 .loc 1 1322 7 + 1443 04be 17E0 b .L103 + 1444 .L91: + 1445 .loc 1 1508 7 + 1446 04c0 00BF nop + 1447 04c2 16E0 b .L56 + 1448 .L92: + 982:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1449 .loc 1 982 7 + 1450 04c4 00BF nop + 1451 04c6 14E0 b .L56 + 1452 .L93: +1016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1453 .loc 1 1016 7 + 1454 04c8 00BF nop + 1455 04ca 12E0 b .L56 + 1456 .L94: +1044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1457 .loc 1 1044 7 + 1458 04cc 00BF nop + 1459 04ce 10E0 b .L56 + 1460 .L95: +1073:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1461 .loc 1 1073 6 + 1462 04d0 00BF nop + 1463 04d2 0EE0 b .L56 + 1464 .L96: +1102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1465 .loc 1 1102 7 + 1466 04d4 00BF nop + 1467 04d6 0CE0 b .L56 + 1468 .L97: +1131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + ARM GAS /tmp/ccwmaYtI.s page 74 + + + 1469 .loc 1 1131 7 + 1470 04d8 00BF nop + 1471 04da 0AE0 b .L56 + 1472 .L98: +1149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1473 .loc 1 1149 7 + 1474 04dc 00BF nop + 1475 04de 08E0 b .L56 + 1476 .L99: +1167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1477 .loc 1 1167 7 + 1478 04e0 00BF nop + 1479 04e2 06E0 b .L56 + 1480 .L100: +1206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1481 .loc 1 1206 7 + 1482 04e4 00BF nop + 1483 04e6 04E0 b .L56 + 1484 .L101: +1229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1485 .loc 1 1229 7 + 1486 04e8 00BF nop + 1487 04ea 02E0 b .L56 + 1488 .L102: +1280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1489 .loc 1 1280 7 + 1490 04ec 00BF nop + 1491 04ee 00E0 b .L56 + 1492 .L103: +1322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1493 .loc 1 1322 7 + 1494 04f0 00BF nop + 1495 .L56: +1509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** return(frequency); + 1496 .loc 1 1511 9 + 1497 04f2 7B69 ldr r3, [r7, #20] +1512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1498 .loc 1 1512 1 + 1499 04f4 1846 mov r0, r3 + 1500 04f6 1837 adds r7, r7, #24 + 1501 .cfi_def_cfa_offset 8 + 1502 04f8 BD46 mov sp, r7 + 1503 .cfi_def_cfa_register 13 + 1504 @ sp needed + 1505 04fa 80BD pop {r7, pc} + 1506 .L108: + 1507 .align 2 + 1508 .L107: + 1509 04fc 00100240 .word 1073876992 + 1510 0500 00127A00 .word 8000000 + 1511 0504 ADDEADDE .word -559030611 + 1512 0508 00000000 .word SystemCoreClock + 1513 050c 00000000 .word adc_pll_prediv_table.0 + 1514 .cfi_endproc + 1515 .LFE132: + ARM GAS /tmp/ccwmaYtI.s page 75 + + + 1517 .section .text.RCC_GetPLLCLKFreq,"ax",%progbits + 1518 .align 1 + 1519 .syntax unified + 1520 .thumb + 1521 .thumb_func + 1523 RCC_GetPLLCLKFreq: + 1524 .LFB133: +1513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /** +1515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @} +1516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** */ +1517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /** +1519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @} +1520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** */ +1521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34) || de +1524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(RCC_CFGR3_TIM1SW) || defined(RCC_CFGR3_TIM2SW) || defined(RCC_CFGR3_TIM8SW) || defined( +1525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(RCC_CFGR3_TIM16SW) || defined(RCC_CFGR3_TIM17SW) || defined(RCC_CFGR3_TIM20SW) || defin +1526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** || defined(RCC_CFGR3_HRTIM1SW) +1527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /** @addtogroup RCCEx_Private_Functions +1529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** * @{ +1530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** */ +1531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** static uint32_t RCC_GetPLLCLKFreq(void) +1532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { + 1525 .loc 1 1532 1 + 1526 .cfi_startproc + 1527 @ args = 0, pretend = 0, frame = 16 + 1528 @ frame_needed = 1, uses_anonymous_args = 0 + 1529 @ link register save eliminated. + 1530 0000 80B4 push {r7} + 1531 .cfi_def_cfa_offset 4 + 1532 .cfi_offset 7, -4 + 1533 0002 85B0 sub sp, sp, #20 + 1534 .cfi_def_cfa_offset 24 + 1535 0004 00AF add r7, sp, #0 + 1536 .cfi_def_cfa_register 7 +1533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** uint32_t pllmul = 0U, pllsource = 0U, prediv = 0U, pllclk = 0U; + 1537 .loc 1 1533 12 + 1538 0006 0023 movs r3, #0 + 1539 0008 BB60 str r3, [r7, #8] + 1540 .loc 1 1533 25 + 1541 000a 0023 movs r3, #0 + 1542 000c 7B60 str r3, [r7, #4] + 1543 .loc 1 1533 41 + 1544 000e 0023 movs r3, #0 + 1545 0010 3B60 str r3, [r7] + 1546 .loc 1 1533 54 + 1547 0012 0023 movs r3, #0 + 1548 0014 FB60 str r3, [r7, #12] +1534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; + 1549 .loc 1 1535 15 + 1550 0016 164B ldr r3, .L113 + 1551 0018 5B68 ldr r3, [r3, #4] + ARM GAS /tmp/ccwmaYtI.s page 76 + + + 1552 .loc 1 1535 10 + 1553 001a 03F47013 and r3, r3, #3932160 + 1554 001e BB60 str r3, [r7, #8] +1536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** pllmul = ( pllmul >> 18U) + 2U; + 1555 .loc 1 1536 21 + 1556 0020 BB68 ldr r3, [r7, #8] + 1557 0022 9B0C lsrs r3, r3, #18 + 1558 .loc 1 1536 10 + 1559 0024 0233 adds r3, r3, #2 + 1560 0026 BB60 str r3, [r7, #8] +1537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + 1561 .loc 1 1537 18 + 1562 0028 114B ldr r3, .L113 + 1563 002a 5B68 ldr r3, [r3, #4] + 1564 .loc 1 1537 13 + 1565 002c 03F48033 and r3, r3, #65536 + 1566 0030 7B60 str r3, [r7, #4] +1538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #if defined(RCC_CFGR_PLLSRC_HSI_DIV2) +1539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if (pllsource != RCC_PLLSOURCE_HSI) + 1567 .loc 1 1539 6 + 1568 0032 7B68 ldr r3, [r7, #4] + 1569 0034 002B cmp r3, #0 + 1570 0036 0ED0 beq .L110 +1540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** prediv = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1U; + 1571 .loc 1 1541 18 + 1572 0038 0D4B ldr r3, .L113 + 1573 003a DB6A ldr r3, [r3, #44] + 1574 .loc 1 1541 26 + 1575 003c 03F00F03 and r3, r3, #15 + 1576 .loc 1 1541 12 + 1577 0040 0133 adds r3, r3, #1 + 1578 0042 3B60 str r3, [r7] +1542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */ +1543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** pllclk = (HSE_VALUE/prediv) * pllmul; + 1579 .loc 1 1543 24 + 1580 0044 0B4A ldr r2, .L113+4 + 1581 0046 3B68 ldr r3, [r7] + 1582 0048 B2FBF3F2 udiv r2, r2, r3 + 1583 .loc 1 1543 12 + 1584 004c BB68 ldr r3, [r7, #8] + 1585 004e 02FB03F3 mul r3, r2, r3 + 1586 0052 FB60 str r3, [r7, #12] + 1587 0054 04E0 b .L111 + 1588 .L110: +1544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else +1546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* HSI used as PLL clock source : PLLCLK = HSI/2U * PLLMUL */ +1548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** pllclk = (HSI_VALUE >> 1U) * pllmul; + 1589 .loc 1 1548 12 + 1590 0056 BB68 ldr r3, [r7, #8] + 1591 0058 074A ldr r2, .L113+8 + 1592 005a 02FB03F3 mul r3, r2, r3 + 1593 005e FB60 str r3, [r7, #12] + 1594 .L111: +1549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + ARM GAS /tmp/ccwmaYtI.s page 77 + + +1550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #else +1551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** prediv = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1U; +1552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV) +1553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */ +1555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** pllclk = (HSE_VALUE/prediv) * pllmul; +1556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** else +1558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** { +1559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */ +1560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** pllclk = (HSI_VALUE/prediv) * pllmul; +1561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } +1562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */ +1563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** +1564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** return pllclk; + 1595 .loc 1 1564 10 + 1596 0060 FB68 ldr r3, [r7, #12] +1565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_rcc_ex.c **** } + 1597 .loc 1 1565 1 + 1598 0062 1846 mov r0, r3 + 1599 0064 1437 adds r7, r7, #20 + 1600 .cfi_def_cfa_offset 4 + 1601 0066 BD46 mov sp, r7 + 1602 .cfi_def_cfa_register 13 + 1603 @ sp needed + 1604 0068 5DF8047B ldr r7, [sp], #4 + 1605 .cfi_restore 7 + 1606 .cfi_def_cfa_offset 0 + 1607 006c 7047 bx lr + 1608 .L114: + 1609 006e 00BF .align 2 + 1610 .L113: + 1611 0070 00100240 .word 1073876992 + 1612 0074 0024F400 .word 16000000 + 1613 0078 00093D00 .word 4000000 + 1614 .cfi_endproc + 1615 .LFE133: + 1617 .section .rodata.adc_pll_prediv_table.0,"a" + 1618 .align 2 + 1621 adc_pll_prediv_table.0: + 1622 0000 0100 .short 1 + 1623 0002 0200 .short 2 + 1624 0004 0400 .short 4 + 1625 0006 0600 .short 6 + 1626 0008 0800 .short 8 + 1627 000a 0A00 .short 10 + 1628 000c 0C00 .short 12 + 1629 000e 1000 .short 16 + 1630 0010 2000 .short 32 + 1631 0012 4000 .short 64 + 1632 0014 8000 .short 128 + 1633 0016 0001 .short 256 + 1634 0018 0001 .short 256 + 1635 001a 0001 .short 256 + 1636 001c 0001 .short 256 + 1637 001e 0001 .short 256 + 1638 .text + ARM GAS /tmp/ccwmaYtI.s page 78 + + + 1639 .Letext0: + 1640 .file 3 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 1641 .file 4 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 1642 .file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + 1643 .file 6 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h" + 1644 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h" + 1645 .file 8 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h" + 1646 .file 9 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h" + 1647 .file 10 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h" + 1648 .file 11 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h" + ARM GAS /tmp/ccwmaYtI.s page 79 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f3xx_hal_rcc_ex.c + /tmp/ccwmaYtI.s:21 .text.HAL_RCCEx_PeriphCLKConfig:00000000 $t + /tmp/ccwmaYtI.s:27 .text.HAL_RCCEx_PeriphCLKConfig:00000000 HAL_RCCEx_PeriphCLKConfig + /tmp/ccwmaYtI.s:281 .text.HAL_RCCEx_PeriphCLKConfig:0000015c $d + /tmp/ccwmaYtI.s:285 .text.HAL_RCCEx_PeriphCLKConfig:00000168 $t + /tmp/ccwmaYtI.s:567 .text.HAL_RCCEx_PeriphCLKConfig:0000031c $d + /tmp/ccwmaYtI.s:572 .text.HAL_RCCEx_GetPeriphCLKConfig:00000000 $t + /tmp/ccwmaYtI.s:578 .text.HAL_RCCEx_GetPeriphCLKConfig:00000000 HAL_RCCEx_GetPeriphCLKConfig + /tmp/ccwmaYtI.s:737 .text.HAL_RCCEx_GetPeriphCLKConfig:000000f4 $d + /tmp/ccwmaYtI.s:743 .text.HAL_RCCEx_GetPeriphCLKFreq:00000000 $t + /tmp/ccwmaYtI.s:749 .text.HAL_RCCEx_GetPeriphCLKFreq:00000000 HAL_RCCEx_GetPeriphCLKFreq + /tmp/ccwmaYtI.s:815 .text.HAL_RCCEx_GetPeriphCLKFreq:0000008c $d + /tmp/ccwmaYtI.s:847 .text.HAL_RCCEx_GetPeriphCLKFreq:0000010c $t + /tmp/ccwmaYtI.s:1237 .text.HAL_RCCEx_GetPeriphCLKFreq:00000380 $d + /tmp/ccwmaYtI.s:1242 .text.HAL_RCCEx_GetPeriphCLKFreq:0000038c $t + /tmp/ccwmaYtI.s:1523 .text.RCC_GetPLLCLKFreq:00000000 RCC_GetPLLCLKFreq + /tmp/ccwmaYtI.s:1509 .text.HAL_RCCEx_GetPeriphCLKFreq:000004fc $d + /tmp/ccwmaYtI.s:1621 .rodata.adc_pll_prediv_table.0:00000000 adc_pll_prediv_table.0 + /tmp/ccwmaYtI.s:1518 .text.RCC_GetPLLCLKFreq:00000000 $t + /tmp/ccwmaYtI.s:1611 .text.RCC_GetPLLCLKFreq:00000070 $d + /tmp/ccwmaYtI.s:1618 .rodata.adc_pll_prediv_table.0:00000000 $d + +UNDEFINED SYMBOLS +HAL_GetTick +HAL_RCC_GetPCLK2Freq +HAL_RCC_GetSysClockFreq +HAL_RCC_GetPCLK1Freq +SystemCoreClock diff --git a/Software/build/stm32f3xx_hal_rcc_ex.o b/Software/build/stm32f3xx_hal_rcc_ex.o new file mode 100644 index 0000000..e7ae645 Binary files /dev/null and b/Software/build/stm32f3xx_hal_rcc_ex.o differ diff --git a/Software/build/stm32f3xx_hal_spi.d b/Software/build/stm32f3xx_hal_spi.d new file mode 100644 index 0000000..aa12b1d --- /dev/null +++ b/Software/build/stm32f3xx_hal_spi.d @@ -0,0 +1,62 @@ +build/stm32f3xx_hal_spi.o: \ + Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + Core/Inc/stm32f3xx_hal_conf.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h: diff --git a/Software/build/stm32f3xx_hal_spi.lst b/Software/build/stm32f3xx_hal_spi.lst new file mode 100644 index 0000000..ddd9277 --- /dev/null +++ b/Software/build/stm32f3xx_hal_spi.lst @@ -0,0 +1,13797 @@ +ARM GAS /tmp/ccs34gJO.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 6 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "stm32f3xx_hal_spi.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c" + 20 .section .text.HAL_SPI_Init,"ax",%progbits + 21 .align 1 + 22 .global HAL_SPI_Init + 23 .syntax unified + 24 .thumb + 25 .thumb_func + 27 HAL_SPI_Init: + 28 .LFB130: + 1:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** + 2:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** ****************************************************************************** + 3:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @file stm32f3xx_hal_spi.c + 4:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @author MCD Application Team + 5:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief SPI HAL module driver. + 6:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * functionalities of the Serial Peripheral Interface (SPI) peripheral: + 8:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * + Initialization and de-initialization functions + 9:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * + IO operation functions + 10:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * + Peripheral Control functions + 11:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * + Peripheral State functions + 12:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** ****************************************************************************** + 13:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @attention + 14:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * + 15:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * Copyright (c) 2016 STMicroelectronics. + 16:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * All rights reserved. + 17:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * + 18:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * This software is licensed under terms that can be found in the LICENSE file + 19:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * in the root directory of this software component. + 20:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 21:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * + 22:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** ****************************************************************************** + 23:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** @verbatim + 24:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** ============================================================================== + 25:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** ##### How to use this driver ##### + 26:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** ============================================================================== + 27:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** [..] + 28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** The SPI HAL driver can be used as follows: + 29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (#) Declare a SPI_HandleTypeDef handle structure, for example: + ARM GAS /tmp/ccs34gJO.s page 2 + + + 31:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_HandleTypeDef hspi; + 32:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 33:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API: + 34:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (##) Enable the SPIx interface clock + 35:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (##) SPI pins configuration + 36:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (+++) Enable the clock for the SPI GPIOs + 37:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (+++) Configure these SPI pins as alternate function push-pull + 38:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (##) NVIC configuration if you need to use interrupt process + 39:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (+++) Configure the SPIx interrupt priority + 40:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (+++) Enable the NVIC SPI IRQ handle + 41:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (##) DMA Configuration if you need to use DMA process + 42:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream + 43:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (+++) Enable the DMAx clock + 44:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (+++) Configure the DMA handle parameters + 45:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (+++) Configure the DMA Tx or Rx Stream/Channel + 46:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx hand + 47:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (+++) Configure the priority and enable the NVIC for the transfer complete interrupt + 48:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 49:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS + 50:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init str + 51:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 52:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (#) Initialize the SPI registers by calling the HAL_SPI_Init() API: + 53:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) + 54:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** by calling the customized HAL_SPI_MspInit() API. + 55:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** [..] + 56:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** Circular mode restriction: + 57:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (#) The DMA circular mode cannot be used when the SPI is configured in these modes: + 58:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (##) Master 2Lines RxOnly + 59:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (##) Master 1Line Rx + 60:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (#) The CRC feature is not managed when the DMA circular mode is enabled + 61:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs + 62:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks + 63:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** [..] + 64:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** Master Receive mode restriction: + 65:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or + 66:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI + 67:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** does not initiate a new transfer the following procedure has to be respected: + 68:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (##) HAL_SPI_DeInit() + 69:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (##) HAL_SPI_Init() + 70:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** [..] + 71:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** Callback registration: + 72:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 73:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U + 74:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** allows the user to configure dynamically the driver callbacks. + 75:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback. + 76:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 77:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** Function HAL_SPI_RegisterCallback() allows to register following callbacks: + 78:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) TxCpltCallback : SPI Tx Completed callback + 79:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) RxCpltCallback : SPI Rx Completed callback + 80:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) TxRxCpltCallback : SPI TxRx Completed callback + 81:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) TxHalfCpltCallback : SPI Tx Half Completed callback + 82:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) RxHalfCpltCallback : SPI Rx Half Completed callback + 83:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback + 84:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) ErrorCallback : SPI Error callback + 85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) AbortCpltCallback : SPI Abort callback + 86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) MspInitCallback : SPI Msp Init callback + 87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) MspDeInitCallback : SPI Msp DeInit callback + ARM GAS /tmp/ccs34gJO.s page 3 + + + 88:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** This function takes as parameters the HAL peripheral handle, the Callback ID + 89:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** and a pointer to the user callback function. + 90:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 91:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 92:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default + 93:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** weak function. + 94:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle, + 95:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** and the Callback ID. + 96:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** This function allows to reset following callbacks: + 97:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) TxCpltCallback : SPI Tx Completed callback + 98:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) RxCpltCallback : SPI Rx Completed callback + 99:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) TxRxCpltCallback : SPI TxRx Completed callback + 100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) TxHalfCpltCallback : SPI Tx Half Completed callback + 101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) RxHalfCpltCallback : SPI Rx Half Completed callback + 102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback + 103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) ErrorCallback : SPI Error callback + 104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) AbortCpltCallback : SPI Abort callback + 105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) MspInitCallback : SPI Msp Init callback + 106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) MspDeInitCallback : SPI Msp DeInit callback + 107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** [..] + 109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET + 110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** all callbacks are set to the corresponding weak functions: + 111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback(). + 112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** Exception done for MspInit and MspDeInit functions that are + 113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when + 114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** these callbacks are null (not registered beforehand). + 115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit() + 116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state + 117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** [..] + 119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only. + 120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** Exception done MspInit/MspDeInit functions that can be registered/unregistered + 121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state, + 122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + 123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** Then, the user first registers the MspInit/MspDeInit user callbacks + 124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit() + 125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** or HAL_SPI_Init() function. + 126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** [..] + 128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** When the compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or + 129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** not defined, the callback registering feature is not available + 130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** and weak (surcharged) callbacks are used. + 131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** [..] + 133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** Using the HAL it is not possible to reach all supported SPI frequency with the different SPI + 134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** the following table resume the max SPI frequency reached with data size 8bits/16bits, + 135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance. + 136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** @endverbatim + 138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** Additional table : + 140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** DataSize = SPI_DATASIZE_8BIT: + 142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +------------------------------------------------------------------------------------------- + 143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line + 144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | Process | Transfer mode |---------------------|----------------------|------------------- + ARM GAS /tmp/ccs34gJO.s page 4 + + + 145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | | | Master | Slave | Master | Slave | Master | Slave + 146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** |=========================================================================================== + 147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA + 148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | X |----------------|----------|----------|-----------|----------|-----------|------- + 149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA + 150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | R |----------------|----------|----------|-----------|----------|-----------|------- + 151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA + 152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** |=========|================|==========|==========|===========|==========|===========|======= + 153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/ + 154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | |----------------|----------|----------|-----------|----------|-----------|------- + 155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/ + 156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | X |----------------|----------|----------|-----------|----------|-----------|------- + 157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/ + 158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** |=========|================|==========|==========|===========|==========|===========|======= + 159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/ + 160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | |----------------|----------|----------|-----------|----------|-----------|------- + 161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/ + 162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | X |----------------|----------|----------|-----------|----------|-----------|------- + 163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/ + 164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +------------------------------------------------------------------------------------------- + 165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** DataSize = SPI_DATASIZE_16BIT: + 167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +------------------------------------------------------------------------------------------- + 168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line + 169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | Process | Transfer mode |---------------------|----------------------|------------------- + 170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | | | Master | Slave | Master | Slave | Master | Slave + 171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** |=========================================================================================== + 172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA + 173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | X |----------------|----------|----------|-----------|----------|-----------|------- + 174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA + 175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | R |----------------|----------|----------|-----------|----------|-----------|------- + 176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA + 177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** |=========|================|==========|==========|===========|==========|===========|======= + 178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/ + 179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | |----------------|----------|----------|-----------|----------|-----------|------- + 180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/ + 181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | X |----------------|----------|----------|-----------|----------|-----------|------- + 182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/ + 183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** |=========|================|==========|==========|===========|==========|===========|======= + 184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/ + 185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | |----------------|----------|----------|-----------|----------|-----------|------- + 186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/ + 187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | X |----------------|----------|----------|-----------|----------|-----------|------- + 188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/ + 189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +------------------------------------------------------------------------------------------- + 190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bi + 191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, + 192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** @note + 193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL + 194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() + 195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA + 196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ + 198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Includes ------------------------------------------------------------------*/ + 200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #include "stm32f3xx_hal.h" + 201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + ARM GAS /tmp/ccs34gJO.s page 5 + + + 202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** @addtogroup STM32F3xx_HAL_Driver + 203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @{ + 204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ + 205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** @defgroup SPI SPI + 207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief SPI HAL module driver + 208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @{ + 209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ + 210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #ifdef HAL_SPI_MODULE_ENABLED + 211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Private typedef -----------------------------------------------------------*/ + 213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Private defines -----------------------------------------------------------*/ + 214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** @defgroup SPI_Private_Constants SPI Private Constants + 215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @{ + 216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ + 217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #define SPI_DEFAULT_TIMEOUT 100U + 218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** + 219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @} + 220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ + 221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Private macros ------------------------------------------------------------*/ + 223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Private variables ---------------------------------------------------------*/ + 224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Private function prototypes -----------------------------------------------*/ + 225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** @defgroup SPI_Private_Functions SPI Private Functions + 226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @{ + 227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ + 228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma); + 229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma); + 230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma); + 231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma); + 232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma); + 233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma); + 234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_DMAError(DMA_HandleTypeDef *hdma); + 235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma); + 236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma); + 237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma); + 238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, Flag + 239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t Timeout, uint32_t Tickstart); + 240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint + 241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t Timeout, uint32_t Tickstart); + 242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi); + 243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi); + 244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi); + 245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi); + 246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi); + 247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi); + 248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi); + 249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi); + 250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) + 251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi); + 252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi); + 253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi); + 254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi); + 255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ + 256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi); + 257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi); + 258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi); + ARM GAS /tmp/ccs34gJO.s page 6 + + + 259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi); + 260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi); + 261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t T + 262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t + 263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** + 264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @} + 265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ + 266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Exported functions --------------------------------------------------------*/ + 268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** @defgroup SPI_Exported_Functions SPI Exported Functions + 269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @{ + 270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ + 271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions + 273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Initialization and Configuration functions + 274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * + 275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** @verbatim + 276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** =============================================================================== + 277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** ##### Initialization and de-initialization functions ##### + 278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** =============================================================================== + 279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** [..] This subsection provides a set of functions allowing to initialize and + 280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** de-initialize the SPIx peripheral: + 281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (+) User must implement HAL_SPI_MspInit() function in which he configures + 283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + 284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (+) Call the function HAL_SPI_Init() to configure the selected device with + 286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** the selected configuration: + 287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) Mode + 288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) Direction + 289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) Data Size + 290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) Clock Polarity and Phase + 291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) NSS Management + 292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) BaudRate Prescaler + 293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) FirstBit + 294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) TIMode + 295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) CRC Calculation + 296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) CRC Polynomial if CRC enabled + 297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) CRC Length, used only with Data8 and Data16 + 298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) FIFO reception threshold + 299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (+) Call the function HAL_SPI_DeInit() to restore the default configuration + 301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** of the selected SPIx peripheral. + 302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** @endverbatim + 304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @{ + 305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ + 306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** + 308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Initialize the SPI according to the specified parameters + 309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * in the SPI_InitTypeDef and initialize the associated handle. + 310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains + 311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. + 312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval HAL status + 313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ + 314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) + 315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + ARM GAS /tmp/ccs34gJO.s page 7 + + + 29 .loc 1 315 1 + 30 .cfi_startproc + 31 @ args = 0, pretend = 0, frame = 16 + 32 @ frame_needed = 1, uses_anonymous_args = 0 + 33 0000 80B5 push {r7, lr} + 34 .cfi_def_cfa_offset 8 + 35 .cfi_offset 7, -8 + 36 .cfi_offset 14, -4 + 37 0002 84B0 sub sp, sp, #16 + 38 .cfi_def_cfa_offset 24 + 39 0004 00AF add r7, sp, #0 + 40 .cfi_def_cfa_register 7 + 41 0006 7860 str r0, [r7, #4] + 316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t frxth; + 317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check the SPI handle allocation */ + 319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi == NULL) + 42 .loc 1 319 6 + 43 0008 7B68 ldr r3, [r7, #4] + 44 000a 002B cmp r3, #0 + 45 000c 01D1 bne .L2 + 320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return HAL_ERROR; + 46 .loc 1 321 12 + 47 000e 0123 movs r3, #1 + 48 0010 9DE0 b .L3 + 49 .L2: + 322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check the parameters */ + 325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); + 326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_MODE(hspi->Init.Mode)); + 327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_DIRECTION(hspi->Init.Direction)); + 328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize)); + 329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_NSS(hspi->Init.NSS)); + 330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode)); + 331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + 332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); + 333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); + 334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.TIMode == SPI_TIMODE_DISABLE) + 50 .loc 1 334 17 + 51 0012 7B68 ldr r3, [r7, #4] + 52 0014 5B6A ldr r3, [r3, #36] + 53 .loc 1 334 6 + 54 0016 002B cmp r3, #0 + 55 0018 08D1 bne .L4 + 335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); + 337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); + 338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.Mode == SPI_MODE_MASTER) + 56 .loc 1 339 19 + 57 001a 7B68 ldr r3, [r7, #4] + 58 001c 5B68 ldr r3, [r3, #4] + 59 .loc 1 339 8 + 60 001e B3F5827F cmp r3, #260 + 61 0022 09D0 beq .L5 + ARM GAS /tmp/ccs34gJO.s page 8 + + + 340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + 342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else + 344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */ + 346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + 62 .loc 1 346 36 + 63 0024 7B68 ldr r3, [r7, #4] + 64 0026 0022 movs r2, #0 + 65 0028 DA61 str r2, [r3, #28] + 66 002a 05E0 b .L5 + 67 .L4: + 347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else + 350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + 352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Force polarity and phase to TI protocaol requirements */ + 354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->Init.CLKPolarity = SPI_POLARITY_LOW; + 68 .loc 1 354 28 + 69 002c 7B68 ldr r3, [r7, #4] + 70 002e 0022 movs r2, #0 + 71 0030 1A61 str r2, [r3, #16] + 355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->Init.CLKPhase = SPI_PHASE_1EDGE; + 72 .loc 1 355 28 + 73 0032 7B68 ldr r3, [r7, #4] + 74 0034 0022 movs r2, #0 + 75 0036 5A61 str r2, [r3, #20] + 76 .L5: + 356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) + 358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation)); + 359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + 360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); + 362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength)); + 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else + 365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + 77 .loc 1 365 29 + 78 0038 7B68 ldr r3, [r7, #4] + 79 003a 0022 movs r2, #0 + 80 003c 9A62 str r2, [r3, #40] + 366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ + 367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->State == HAL_SPI_STATE_RESET) + 81 .loc 1 368 11 + 82 003e 7B68 ldr r3, [r7, #4] + 83 0040 93F85D30 ldrb r3, [r3, #93] + 84 0044 DBB2 uxtb r3, r3 + 85 .loc 1 368 6 + 86 0046 002B cmp r3, #0 + 87 0048 06D1 bne .L6 + 369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Allocate lock resource and initialize it */ + ARM GAS /tmp/ccs34gJO.s page 9 + + + 371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->Lock = HAL_UNLOCKED; + 88 .loc 1 371 16 + 89 004a 7B68 ldr r3, [r7, #4] + 90 004c 0022 movs r2, #0 + 91 004e 83F85C20 strb r2, [r3, #92] + 372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + 374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Init the SPI Callback settings */ + 375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback + 376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback + 377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback + 378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback + 379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback + 380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback + 381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback + 382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback + 383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->MspInitCallback == NULL) + 385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */ + 387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + 390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->MspInitCallback(hspi); + 391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else + 392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + 393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_MspInit(hspi); + 92 .loc 1 393 5 + 93 0052 7868 ldr r0, [r7, #4] + 94 0054 FFF7FEFF bl HAL_SPI_MspInit + 95 .L6: + 394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + 395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_BUSY; + 96 .loc 1 397 15 + 97 0058 7B68 ldr r3, [r7, #4] + 98 005a 0222 movs r2, #2 + 99 005c 83F85D20 strb r2, [r3, #93] + 398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable the selected SPI peripheral */ + 400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE(hspi); + 100 .loc 1 400 3 + 101 0060 7B68 ldr r3, [r7, #4] + 102 0062 1B68 ldr r3, [r3] + 103 0064 1A68 ldr r2, [r3] + 104 0066 7B68 ldr r3, [r7, #4] + 105 0068 1B68 ldr r3, [r3] + 106 006a 22F04002 bic r2, r2, #64 + 107 006e 1A60 str r2, [r3] + 401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Align by default the rs fifo threshold on the data size */ + 403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + 108 .loc 1 403 17 + 109 0070 7B68 ldr r3, [r7, #4] + 110 0072 DB68 ldr r3, [r3, #12] + 111 .loc 1 403 6 + ARM GAS /tmp/ccs34gJO.s page 10 + + + 112 0074 B3F5E06F cmp r3, #1792 + 113 0078 02D9 bls .L7 + 404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** frxth = SPI_RXFIFO_THRESHOLD_HF; + 114 .loc 1 405 11 + 115 007a 0023 movs r3, #0 + 116 007c FB60 str r3, [r7, #12] + 117 007e 02E0 b .L8 + 118 .L7: + 406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else + 408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** frxth = SPI_RXFIFO_THRESHOLD_QF; + 119 .loc 1 409 11 + 120 0080 4FF48053 mov r3, #4096 + 121 0084 FB60 str r3, [r7, #12] + 122 .L8: + 410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* CRC calculation is valid only for 16Bit and 8 Bit */ + 413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT)) + 123 .loc 1 413 18 + 124 0086 7B68 ldr r3, [r7, #4] + 125 0088 DB68 ldr r3, [r3, #12] + 126 .loc 1 413 6 + 127 008a B3F5706F cmp r3, #3840 + 128 008e 07D0 beq .L9 + 129 .loc 1 413 65 discriminator 1 + 130 0090 7B68 ldr r3, [r7, #4] + 131 0092 DB68 ldr r3, [r3, #12] + 132 .loc 1 413 51 discriminator 1 + 133 0094 B3F5E06F cmp r3, #1792 + 134 0098 02D0 beq .L9 + 414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* CRC must be disabled */ + 416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + 135 .loc 1 416 31 + 136 009a 7B68 ldr r3, [r7, #4] + 137 009c 0022 movs r2, #0 + 138 009e 9A62 str r2, [r3, #40] + 139 .L9: + 417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ + 420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management, + 421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** Communication speed, First bit and CRC calculation state */ + 422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) | + 140 .loc 1 422 3 + 141 00a0 7B68 ldr r3, [r7, #4] + 142 00a2 5B68 ldr r3, [r3, #4] + 143 00a4 03F48272 and r2, r3, #260 + 144 00a8 7B68 ldr r3, [r7, #4] + 145 00aa 9B68 ldr r3, [r3, #8] + 146 00ac 03F40443 and r3, r3, #33792 + 147 00b0 1A43 orrs r2, r2, r3 + 148 00b2 7B68 ldr r3, [r7, #4] + 149 00b4 1B69 ldr r3, [r3, #16] + ARM GAS /tmp/ccs34gJO.s page 11 + + + 150 00b6 03F00203 and r3, r3, #2 + 151 00ba 1A43 orrs r2, r2, r3 + 152 00bc 7B68 ldr r3, [r7, #4] + 153 00be 5B69 ldr r3, [r3, #20] + 154 00c0 03F00103 and r3, r3, #1 + 155 00c4 1A43 orrs r2, r2, r3 + 156 00c6 7B68 ldr r3, [r7, #4] + 157 00c8 9B69 ldr r3, [r3, #24] + 158 00ca 03F40073 and r3, r3, #512 + 159 00ce 1A43 orrs r2, r2, r3 + 160 00d0 7B68 ldr r3, [r7, #4] + 161 00d2 DB69 ldr r3, [r3, #28] + 162 00d4 03F03803 and r3, r3, #56 + 163 00d8 1A43 orrs r2, r2, r3 + 164 00da 7B68 ldr r3, [r7, #4] + 165 00dc 1B6A ldr r3, [r3, #32] + 166 00de 03F08003 and r3, r3, #128 + 167 00e2 42EA0301 orr r1, r2, r3 + 168 00e6 7B68 ldr r3, [r7, #4] + 169 00e8 9B6A ldr r3, [r3, #40] + 170 00ea 03F40052 and r2, r3, #8192 + 171 00ee 7B68 ldr r3, [r7, #4] + 172 00f0 1B68 ldr r3, [r3] + 173 00f2 0A43 orrs r2, r2, r1 + 174 00f4 1A60 str r2, [r3] + 423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (hspi->Init.Direction & (SPI_CR1_RXONLY | SPI_CR1_BIDIMODE)) | + 424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (hspi->Init.CLKPolarity & SPI_CR1_CPOL) | + 425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (hspi->Init.CLKPhase & SPI_CR1_CPHA) | + 426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (hspi->Init.NSS & SPI_CR1_SSM) | + 427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) | + 428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (hspi->Init.FirstBit & SPI_CR1_LSBFIRST) | + 429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (hspi->Init.CRCCalculation & SPI_CR1_CRCEN))); + 430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) + 431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /*---------------------------- SPIx CRCL Configuration -------------------*/ + 432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + 433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Align the CRC Length on the data size */ + 435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE) + 436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* CRC Length aligned on the data size : value set by default */ + 438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + 439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT; + 441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else + 443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT; + 445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Configure : CRC Length */ + 449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) + 450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCL); + 452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ + ARM GAS /tmp/ccs34gJO.s page 12 + + + 455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */ + 457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | + 175 .loc 1 457 3 + 176 00f6 7B68 ldr r3, [r7, #4] + 177 00f8 9B69 ldr r3, [r3, #24] + 178 00fa 1B0C lsrs r3, r3, #16 + 179 00fc 03F00402 and r2, r3, #4 + 180 0100 7B68 ldr r3, [r7, #4] + 181 0102 5B6A ldr r3, [r3, #36] + 182 0104 03F01003 and r3, r3, #16 + 183 0108 1A43 orrs r2, r2, r3 + 184 010a 7B68 ldr r3, [r7, #4] + 185 010c 5B6B ldr r3, [r3, #52] + 186 010e 03F00803 and r3, r3, #8 + 187 0112 1A43 orrs r2, r2, r3 + 188 0114 7B68 ldr r3, [r7, #4] + 189 0116 DB68 ldr r3, [r3, #12] + 190 0118 03F47063 and r3, r3, #3840 + 191 011c 42EA0301 orr r1, r2, r3 + 192 0120 FB68 ldr r3, [r7, #12] + 193 0122 03F48052 and r2, r3, #4096 + 194 0126 7B68 ldr r3, [r7, #4] + 195 0128 1B68 ldr r3, [r3] + 196 012a 0A43 orrs r2, r2, r1 + 197 012c 5A60 str r2, [r3, #4] + 458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (hspi->Init.TIMode & SPI_CR2_FRF) | + 459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (hspi->Init.NSSPMode & SPI_CR2_NSSP) | + 460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (hspi->Init.DataSize & SPI_CR2_DS_Msk) | + 461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (frxth & SPI_CR2_FRXTH))); + 462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) + 464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /*---------------------------- SPIx CRCPOLY Configuration ------------------*/ + 465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Configure : CRC Polynomial */ + 466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + 467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** WRITE_REG(hspi->Instance->CRCPR, (hspi->Init.CRCPolynomial & SPI_CRCPR_CRCPOLY_Msk)); + 469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ + 471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if defined(SPI_I2SCFGR_I2SMOD) + 473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ + 474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); + 198 .loc 1 474 3 + 199 012e 7B68 ldr r3, [r7, #4] + 200 0130 1B68 ldr r3, [r3] + 201 0132 DA69 ldr r2, [r3, #28] + 202 0134 7B68 ldr r3, [r7, #4] + 203 0136 1B68 ldr r3, [r3] + 204 0138 22F40062 bic r2, r2, #2048 + 205 013c DA61 str r2, [r3, #28] + 475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* SPI_I2SCFGR_I2SMOD */ + 476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 206 .loc 1 477 19 + 207 013e 7B68 ldr r3, [r7, #4] + 208 0140 0022 movs r2, #0 + ARM GAS /tmp/ccs34gJO.s page 13 + + + 209 0142 1A66 str r2, [r3, #96] + 478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; + 210 .loc 1 478 19 + 211 0144 7B68 ldr r3, [r7, #4] + 212 0146 0122 movs r2, #1 + 213 0148 83F85D20 strb r2, [r3, #93] + 479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return HAL_OK; + 214 .loc 1 480 10 + 215 014c 0023 movs r3, #0 + 216 .L3: + 481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 217 .loc 1 481 1 + 218 014e 1846 mov r0, r3 + 219 0150 1037 adds r7, r7, #16 + 220 .cfi_def_cfa_offset 8 + 221 0152 BD46 mov sp, r7 + 222 .cfi_def_cfa_register 13 + 223 @ sp needed + 224 0154 80BD pop {r7, pc} + 225 .cfi_endproc + 226 .LFE130: + 228 .section .text.HAL_SPI_DeInit,"ax",%progbits + 229 .align 1 + 230 .global HAL_SPI_DeInit + 231 .syntax unified + 232 .thumb + 233 .thumb_func + 235 HAL_SPI_DeInit: + 236 .LFB131: + 482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** + 484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief De-Initialize the SPI peripheral. + 485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains + 486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. + 487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval HAL status + 488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ + 489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) + 490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 237 .loc 1 490 1 + 238 .cfi_startproc + 239 @ args = 0, pretend = 0, frame = 8 + 240 @ frame_needed = 1, uses_anonymous_args = 0 + 241 0000 80B5 push {r7, lr} + 242 .cfi_def_cfa_offset 8 + 243 .cfi_offset 7, -8 + 244 .cfi_offset 14, -4 + 245 0002 82B0 sub sp, sp, #8 + 246 .cfi_def_cfa_offset 16 + 247 0004 00AF add r7, sp, #0 + 248 .cfi_def_cfa_register 7 + 249 0006 7860 str r0, [r7, #4] + 491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check the SPI handle allocation */ + 492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi == NULL) + 250 .loc 1 492 6 + 251 0008 7B68 ldr r3, [r7, #4] + 252 000a 002B cmp r3, #0 + ARM GAS /tmp/ccs34gJO.s page 14 + + + 253 000c 01D1 bne .L11 + 493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return HAL_ERROR; + 254 .loc 1 494 12 + 255 000e 0123 movs r3, #1 + 256 0010 1AE0 b .L12 + 257 .L11: + 495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check SPI Instance parameter */ + 498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); + 499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_BUSY; + 258 .loc 1 500 15 + 259 0012 7B68 ldr r3, [r7, #4] + 260 0014 0222 movs r2, #2 + 261 0016 83F85D20 strb r2, [r3, #93] + 501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable the SPI Peripheral Clock */ + 503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE(hspi); + 262 .loc 1 503 3 + 263 001a 7B68 ldr r3, [r7, #4] + 264 001c 1B68 ldr r3, [r3] + 265 001e 1A68 ldr r2, [r3] + 266 0020 7B68 ldr r3, [r7, #4] + 267 0022 1B68 ldr r3, [r3] + 268 0024 22F04002 bic r2, r2, #64 + 269 0028 1A60 str r2, [r3] + 504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + 506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->MspDeInitCallback == NULL) + 507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */ + 509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + 512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->MspDeInitCallback(hspi); + 513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else + 514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + 515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_MspDeInit(hspi); + 270 .loc 1 515 3 + 271 002a 7868 ldr r0, [r7, #4] + 272 002c FFF7FEFF bl HAL_SPI_MspDeInit + 516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + 517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 273 .loc 1 518 19 + 274 0030 7B68 ldr r3, [r7, #4] + 275 0032 0022 movs r2, #0 + 276 0034 1A66 str r2, [r3, #96] + 519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_RESET; + 277 .loc 1 519 15 + 278 0036 7B68 ldr r3, [r7, #4] + 279 0038 0022 movs r2, #0 + 280 003a 83F85D20 strb r2, [r3, #93] + 520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Release Lock */ + ARM GAS /tmp/ccs34gJO.s page 15 + + + 522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_UNLOCK(hspi); + 281 .loc 1 522 3 + 282 003e 7B68 ldr r3, [r7, #4] + 283 0040 0022 movs r2, #0 + 284 0042 83F85C20 strb r2, [r3, #92] + 523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return HAL_OK; + 285 .loc 1 524 10 + 286 0046 0023 movs r3, #0 + 287 .L12: + 525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 288 .loc 1 525 1 + 289 0048 1846 mov r0, r3 + 290 004a 0837 adds r7, r7, #8 + 291 .cfi_def_cfa_offset 8 + 292 004c BD46 mov sp, r7 + 293 .cfi_def_cfa_register 13 + 294 @ sp needed + 295 004e 80BD pop {r7, pc} + 296 .cfi_endproc + 297 .LFE131: + 299 .section .text.HAL_SPI_MspInit,"ax",%progbits + 300 .align 1 + 301 .weak HAL_SPI_MspInit + 302 .syntax unified + 303 .thumb + 304 .thumb_func + 306 HAL_SPI_MspInit: + 307 .LFB132: + 526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** + 528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Initialize the SPI MSP. + 529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains + 530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. + 531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None + 532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ + 533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) + 534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 308 .loc 1 534 1 + 309 .cfi_startproc + 310 @ args = 0, pretend = 0, frame = 8 + 311 @ frame_needed = 1, uses_anonymous_args = 0 + 312 @ link register save eliminated. + 313 0000 80B4 push {r7} + 314 .cfi_def_cfa_offset 4 + 315 .cfi_offset 7, -4 + 316 0002 83B0 sub sp, sp, #12 + 317 .cfi_def_cfa_offset 16 + 318 0004 00AF add r7, sp, #0 + 319 .cfi_def_cfa_register 7 + 320 0006 7860 str r0, [r7, #4] + 535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Prevent unused argument(s) compilation warning */ + 536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(hspi); + 537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* NOTE : This function should not be modified, when the callback is needed, + 539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** the HAL_SPI_MspInit should be implemented in the user file + 540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ + ARM GAS /tmp/ccs34gJO.s page 16 + + + 541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 321 .loc 1 541 1 + 322 0008 00BF nop + 323 000a 0C37 adds r7, r7, #12 + 324 .cfi_def_cfa_offset 4 + 325 000c BD46 mov sp, r7 + 326 .cfi_def_cfa_register 13 + 327 @ sp needed + 328 000e 5DF8047B ldr r7, [sp], #4 + 329 .cfi_restore 7 + 330 .cfi_def_cfa_offset 0 + 331 0012 7047 bx lr + 332 .cfi_endproc + 333 .LFE132: + 335 .section .text.HAL_SPI_MspDeInit,"ax",%progbits + 336 .align 1 + 337 .weak HAL_SPI_MspDeInit + 338 .syntax unified + 339 .thumb + 340 .thumb_func + 342 HAL_SPI_MspDeInit: + 343 .LFB133: + 542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** + 544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief De-Initialize the SPI MSP. + 545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains + 546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. + 547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None + 548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ + 549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) + 550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 344 .loc 1 550 1 + 345 .cfi_startproc + 346 @ args = 0, pretend = 0, frame = 8 + 347 @ frame_needed = 1, uses_anonymous_args = 0 + 348 @ link register save eliminated. + 349 0000 80B4 push {r7} + 350 .cfi_def_cfa_offset 4 + 351 .cfi_offset 7, -4 + 352 0002 83B0 sub sp, sp, #12 + 353 .cfi_def_cfa_offset 16 + 354 0004 00AF add r7, sp, #0 + 355 .cfi_def_cfa_register 7 + 356 0006 7860 str r0, [r7, #4] + 551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Prevent unused argument(s) compilation warning */ + 552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(hspi); + 553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* NOTE : This function should not be modified, when the callback is needed, + 555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** the HAL_SPI_MspDeInit should be implemented in the user file + 556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ + 557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 357 .loc 1 557 1 + 358 0008 00BF nop + 359 000a 0C37 adds r7, r7, #12 + 360 .cfi_def_cfa_offset 4 + 361 000c BD46 mov sp, r7 + 362 .cfi_def_cfa_register 13 + ARM GAS /tmp/ccs34gJO.s page 17 + + + 363 @ sp needed + 364 000e 5DF8047B ldr r7, [sp], #4 + 365 .cfi_restore 7 + 366 .cfi_def_cfa_offset 0 + 367 0012 7047 bx lr + 368 .cfi_endproc + 369 .LFE133: + 371 .section .text.HAL_SPI_Transmit,"ax",%progbits + 372 .align 1 + 373 .global HAL_SPI_Transmit + 374 .syntax unified + 375 .thumb + 376 .thumb_func + 378 HAL_SPI_Transmit: + 379 .LFB134: + 558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + 560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** + 561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Register a User SPI Callback + 562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * To be used instead of the weak predefined callback + 563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi Pointer to a SPI_HandleTypeDef structure that contains + 564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for the specified SPI. + 565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param CallbackID ID of the callback to be registered + 566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param pCallback pointer to the Callback function + 567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval HAL status + 568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ + 569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef Callb + 570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** pSPI_CallbackTypeDef pCallback) + 571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef status = HAL_OK; + 573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (pCallback == NULL) + 575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Update the error code */ + 577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK; + 578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return HAL_ERROR; + 580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Process locked */ + 582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_LOCK(hspi); + 583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_SPI_STATE_READY == hspi->State) + 585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** switch (CallbackID) + 587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** case HAL_SPI_TX_COMPLETE_CB_ID : + 589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxCpltCallback = pCallback; + 590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** case HAL_SPI_RX_COMPLETE_CB_ID : + 593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxCpltCallback = pCallback; + 594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** case HAL_SPI_TX_RX_COMPLETE_CB_ID : + 597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxRxCpltCallback = pCallback; + 598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + ARM GAS /tmp/ccs34gJO.s page 18 + + + 600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** case HAL_SPI_TX_HALF_COMPLETE_CB_ID : + 601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxHalfCpltCallback = pCallback; + 602:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** case HAL_SPI_RX_HALF_COMPLETE_CB_ID : + 605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxHalfCpltCallback = pCallback; + 606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID : + 609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxRxHalfCpltCallback = pCallback; + 610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 612:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** case HAL_SPI_ERROR_CB_ID : + 613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCallback = pCallback; + 614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** case HAL_SPI_ABORT_CB_ID : + 617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->AbortCpltCallback = pCallback; + 618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** case HAL_SPI_MSPINIT_CB_ID : + 621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->MspInitCallback = pCallback; + 622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** case HAL_SPI_MSPDEINIT_CB_ID : + 625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->MspDeInitCallback = pCallback; + 626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** default : + 629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Update the error code */ + 630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + 631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Return error status */ + 633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** status = HAL_ERROR; + 634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else if (HAL_SPI_STATE_RESET == hspi->State) + 638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** switch (CallbackID) + 640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** case HAL_SPI_MSPINIT_CB_ID : + 642:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->MspInitCallback = pCallback; + 643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** case HAL_SPI_MSPDEINIT_CB_ID : + 646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->MspDeInitCallback = pCallback; + 647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** default : + 650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Update the error code */ + 651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + 652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Return error status */ + 654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** status = HAL_ERROR; + 655:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + ARM GAS /tmp/ccs34gJO.s page 19 + + + 657:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else + 659:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Update the error code */ + 661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + 662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Return error status */ + 664:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** status = HAL_ERROR; + 665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Release Lock */ + 668:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_UNLOCK(hspi); + 669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return status; + 670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** + 673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Unregister an SPI Callback + 674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * SPI callback is redirected to the weak predefined callback + 675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi Pointer to a SPI_HandleTypeDef structure that contains + 676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for the specified SPI. + 677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param CallbackID ID of the callback to be unregistered + 678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval HAL status + 679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ + 680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef Cal + 681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef status = HAL_OK; + 683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Process locked */ + 685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_LOCK(hspi); + 686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_SPI_STATE_READY == hspi->State) + 688:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** switch (CallbackID) + 690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** case HAL_SPI_TX_COMPLETE_CB_ID : + 692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback + 693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 694:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** case HAL_SPI_RX_COMPLETE_CB_ID : + 696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback + 697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** case HAL_SPI_TX_RX_COMPLETE_CB_ID : + 700:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback + 701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** case HAL_SPI_TX_HALF_COMPLETE_CB_ID : + 704:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallbac + 705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 706:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 707:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** case HAL_SPI_RX_HALF_COMPLETE_CB_ID : + 708:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallbac + 709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID : + 712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallb + 713:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + ARM GAS /tmp/ccs34gJO.s page 20 + + + 714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** case HAL_SPI_ERROR_CB_ID : + 716:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback + 717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 718:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** case HAL_SPI_ABORT_CB_ID : + 720:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback + 721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 722:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 723:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** case HAL_SPI_MSPINIT_CB_ID : + 724:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit + 725:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 727:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** case HAL_SPI_MSPDEINIT_CB_ID : + 728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit + 729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** default : + 732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Update the error code */ + 733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + 734:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Return error status */ + 736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** status = HAL_ERROR; + 737:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 739:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else if (HAL_SPI_STATE_RESET == hspi->State) + 741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** switch (CallbackID) + 743:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** case HAL_SPI_MSPINIT_CB_ID : + 745:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit + 746:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 747:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 748:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** case HAL_SPI_MSPDEINIT_CB_ID : + 749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit + 750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 752:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** default : + 753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Update the error code */ + 754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + 755:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Return error status */ + 757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** status = HAL_ERROR; + 758:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 760:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 761:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else + 762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Update the error code */ + 764:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + 765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Return error status */ + 767:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** status = HAL_ERROR; + 768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Release Lock */ + ARM GAS /tmp/ccs34gJO.s page 21 + + + 771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_UNLOCK(hspi); + 772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return status; + 773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + 775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** + 776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @} + 777:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ + 778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** @defgroup SPI_Exported_Functions_Group2 IO operation functions + 780:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Data transfers functions + 781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * + 782:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** @verbatim + 783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** ============================================================================== + 784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** ##### IO operation functions ##### + 785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** =============================================================================== + 786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** [..] + 787:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** This subsection provides a set of functions allowing to manage the SPI + 788:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** data transfers. + 789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** [..] The SPI supports master and slave mode : + 791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (#) There are two modes of transfer: + 793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) Blocking mode: The communication is performed in polling mode. + 794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** The HAL status of all data processing is returned by the same function + 795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** after finishing transfer. + 796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (++) No-Blocking mode: The communication is performed using Interrupts + 797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** or DMA, These APIs return the HAL status. + 798:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** The end of the data processing will be indicated through the + 799:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when + 800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** using DMA mode. + 801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() u + 802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** will be executed respectively at the end of the transmit or Receive process + 803:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is + 804:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either I + 806:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** exist for 1Line (simplex) and 2Lines (full duplex) modes. + 807:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 808:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** @endverbatim + 809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @{ + 810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ + 811:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** + 813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Transmit an amount of data in blocking mode. + 814:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains + 815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. + 816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param pData pointer to data buffer + 817:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param Size amount of data to be sent + 818:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param Timeout Timeout duration + 819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval HAL status + 820:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ + 821:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t + 822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 380 .loc 1 822 1 + 381 .cfi_startproc + 382 @ args = 0, pretend = 0, frame = 32 + 383 @ frame_needed = 1, uses_anonymous_args = 0 + 384 0000 80B5 push {r7, lr} + ARM GAS /tmp/ccs34gJO.s page 22 + + + 385 .cfi_def_cfa_offset 8 + 386 .cfi_offset 7, -8 + 387 .cfi_offset 14, -4 + 388 0002 88B0 sub sp, sp, #32 + 389 .cfi_def_cfa_offset 40 + 390 0004 00AF add r7, sp, #0 + 391 .cfi_def_cfa_register 7 + 392 0006 F860 str r0, [r7, #12] + 393 0008 B960 str r1, [r7, #8] + 394 000a 3B60 str r3, [r7] + 395 000c 1346 mov r3, r2 @ movhi + 396 000e FB80 strh r3, [r7, #6] @ movhi + 823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t tickstart; + 824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef errorcode = HAL_OK; + 397 .loc 1 824 21 + 398 0010 0023 movs r3, #0 + 399 0012 FB77 strb r3, [r7, #31] + 825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint16_t initial_TxXferCount; + 826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 827:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check Direction parameter */ + 828:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + 829:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 830:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Process Locked */ + 831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_LOCK(hspi); + 400 .loc 1 831 3 + 401 0014 FB68 ldr r3, [r7, #12] + 402 0016 93F85C30 ldrb r3, [r3, #92] @ zero_extendqisi2 + 403 001a 012B cmp r3, #1 + 404 001c 01D1 bne .L16 + 405 .loc 1 831 3 is_stmt 0 discriminator 1 + 406 001e 0223 movs r3, #2 + 407 .loc 1 831 3 + 408 0020 5FE1 b .L17 + 409 .L16: + 410 .loc 1 831 3 discriminator 2 + 411 0022 FB68 ldr r3, [r7, #12] + 412 0024 0122 movs r2, #1 + 413 0026 83F85C20 strb r2, [r3, #92] + 832:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Init tickstart for timeout management*/ + 834:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tickstart = HAL_GetTick(); + 414 .loc 1 834 15 is_stmt 1 + 415 002a FFF7FEFF bl HAL_GetTick + 416 002e B861 str r0, [r7, #24] + 835:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** initial_TxXferCount = Size; + 417 .loc 1 835 23 + 418 0030 FB88 ldrh r3, [r7, #6] @ movhi + 419 0032 FB82 strh r3, [r7, #22] @ movhi + 836:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->State != HAL_SPI_STATE_READY) + 420 .loc 1 837 11 + 421 0034 FB68 ldr r3, [r7, #12] + 422 0036 93F85D30 ldrb r3, [r3, #93] + 423 003a DBB2 uxtb r3, r3 + 424 .loc 1 837 6 + 425 003c 012B cmp r3, #1 + 426 003e 02D0 beq .L18 + ARM GAS /tmp/ccs34gJO.s page 23 + + + 838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_BUSY; + 427 .loc 1 839 15 + 428 0040 0223 movs r3, #2 + 429 0042 FB77 strb r3, [r7, #31] + 840:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 430 .loc 1 840 5 + 431 0044 48E1 b .L19 + 432 .L18: + 841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 842:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 843:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((pData == NULL) || (Size == 0U)) + 433 .loc 1 843 6 + 434 0046 BB68 ldr r3, [r7, #8] + 435 0048 002B cmp r3, #0 + 436 004a 02D0 beq .L20 + 437 .loc 1 843 23 discriminator 1 + 438 004c FB88 ldrh r3, [r7, #6] + 439 004e 002B cmp r3, #0 + 440 0050 02D1 bne .L21 + 441 .L20: + 844:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; + 442 .loc 1 845 15 + 443 0052 0123 movs r3, #1 + 444 0054 FB77 strb r3, [r7, #31] + 846:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 445 .loc 1 846 5 + 446 0056 3FE1 b .L19 + 447 .L21: + 847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the transaction information */ + 850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_BUSY_TX; + 448 .loc 1 850 21 + 449 0058 FB68 ldr r3, [r7, #12] + 450 005a 0322 movs r2, #3 + 451 005c 83F85D20 strb r2, [r3, #93] + 851:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 452 .loc 1 851 21 + 453 0060 FB68 ldr r3, [r7, #12] + 454 0062 0022 movs r2, #0 + 455 0064 1A66 str r2, [r3, #96] + 852:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr = (uint8_t *)pData; + 456 .loc 1 852 21 + 457 0066 FB68 ldr r3, [r7, #12] + 458 0068 BA68 ldr r2, [r7, #8] + 459 006a 9A63 str r2, [r3, #56] + 853:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferSize = Size; + 460 .loc 1 853 21 + 461 006c FB68 ldr r3, [r7, #12] + 462 006e FA88 ldrh r2, [r7, #6] @ movhi + 463 0070 9A87 strh r2, [r3, #60] @ movhi + 854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = Size; + 464 .loc 1 854 21 + 465 0072 FB68 ldr r3, [r7, #12] + 466 0074 FA88 ldrh r2, [r7, #6] @ movhi + ARM GAS /tmp/ccs34gJO.s page 24 + + + 467 0076 DA87 strh r2, [r3, #62] @ movhi + 855:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 856:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /*Init field not used in handle to zero */ + 857:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr = (uint8_t *)NULL; + 468 .loc 1 857 21 + 469 0078 FB68 ldr r3, [r7, #12] + 470 007a 0022 movs r2, #0 + 471 007c 1A64 str r2, [r3, #64] + 858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferSize = 0U; + 472 .loc 1 858 21 + 473 007e FB68 ldr r3, [r7, #12] + 474 0080 0022 movs r2, #0 + 475 0082 A3F84420 strh r2, [r3, #68] @ movhi + 859:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = 0U; + 476 .loc 1 859 21 + 477 0086 FB68 ldr r3, [r7, #12] + 478 0088 0022 movs r2, #0 + 479 008a A3F84620 strh r2, [r3, #70] @ movhi + 860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxISR = NULL; + 480 .loc 1 860 21 + 481 008e FB68 ldr r3, [r7, #12] + 482 0090 0022 movs r2, #0 + 483 0092 1A65 str r2, [r3, #80] + 861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxISR = NULL; + 484 .loc 1 861 21 + 485 0094 FB68 ldr r3, [r7, #12] + 486 0096 0022 movs r2, #0 + 487 0098 DA64 str r2, [r3, #76] + 862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Configure communication direction : 1Line */ + 864:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + 488 .loc 1 864 17 + 489 009a FB68 ldr r3, [r7, #12] + 490 009c 9B68 ldr r3, [r3, #8] + 491 .loc 1 864 6 + 492 009e B3F5004F cmp r3, #32768 + 493 00a2 0FD1 bne .L22 + 865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + 867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE(hspi); + 494 .loc 1 867 5 + 495 00a4 FB68 ldr r3, [r7, #12] + 496 00a6 1B68 ldr r3, [r3] + 497 00a8 1A68 ldr r2, [r3] + 498 00aa FB68 ldr r3, [r7, #12] + 499 00ac 1B68 ldr r3, [r3] + 500 00ae 22F04002 bic r2, r2, #64 + 501 00b2 1A60 str r2, [r3] + 868:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_1LINE_TX(hspi); + 502 .loc 1 868 5 + 503 00b4 FB68 ldr r3, [r7, #12] + 504 00b6 1B68 ldr r3, [r3] + 505 00b8 1A68 ldr r2, [r3] + 506 00ba FB68 ldr r3, [r7, #12] + 507 00bc 1B68 ldr r3, [r3] + 508 00be 42F48042 orr r2, r2, #16384 + 509 00c2 1A60 str r2, [r3] + ARM GAS /tmp/ccs34gJO.s page 25 + + + 510 .L22: + 869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 870:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) + 872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset CRC Calculation */ + 873:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + 874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 875:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_RESET_CRC(hspi); + 876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 877:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ + 878:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 879:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check if the SPI is already enabled */ + 880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + 511 .loc 1 880 12 + 512 00c4 FB68 ldr r3, [r7, #12] + 513 00c6 1B68 ldr r3, [r3] + 514 .loc 1 880 22 + 515 00c8 1B68 ldr r3, [r3] + 516 .loc 1 880 28 + 517 00ca 03F04003 and r3, r3, #64 + 518 .loc 1 880 6 + 519 00ce 402B cmp r3, #64 + 520 00d0 07D0 beq .L23 + 881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable SPI peripheral */ + 883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_ENABLE(hspi); + 521 .loc 1 883 5 + 522 00d2 FB68 ldr r3, [r7, #12] + 523 00d4 1B68 ldr r3, [r3] + 524 00d6 1A68 ldr r2, [r3] + 525 00d8 FB68 ldr r3, [r7, #12] + 526 00da 1B68 ldr r3, [r3] + 527 00dc 42F04002 orr r2, r2, #64 + 528 00e0 1A60 str r2, [r3] + 529 .L23: + 884:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Transmit data in 16 Bit mode */ + 887:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + 530 .loc 1 887 17 + 531 00e2 FB68 ldr r3, [r7, #12] + 532 00e4 DB68 ldr r3, [r3, #12] + 533 .loc 1 887 6 + 534 00e6 B3F5E06F cmp r3, #1792 + 535 00ea 4FD9 bls .L24 + 888:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 889:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + 536 .loc 1 889 20 + 537 00ec FB68 ldr r3, [r7, #12] + 538 00ee 5B68 ldr r3, [r3, #4] + 539 .loc 1 889 8 + 540 00f0 002B cmp r3, #0 + 541 00f2 02D0 beq .L25 + 542 .loc 1 889 45 discriminator 1 + 543 00f4 FB8A ldrh r3, [r7, #22] + 544 00f6 012B cmp r3, #1 + 545 00f8 42D1 bne .L27 + ARM GAS /tmp/ccs34gJO.s page 26 + + + 546 .L25: + 890:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + 547 .loc 1 891 46 + 548 00fa FB68 ldr r3, [r7, #12] + 549 00fc 9B6B ldr r3, [r3, #56] + 550 .loc 1 891 28 + 551 00fe 1A88 ldrh r2, [r3] + 552 .loc 1 891 11 + 553 0100 FB68 ldr r3, [r7, #12] + 554 0102 1B68 ldr r3, [r3] + 555 .loc 1 891 26 + 556 0104 DA60 str r2, [r3, #12] + 892:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 557 .loc 1 892 11 + 558 0106 FB68 ldr r3, [r7, #12] + 559 0108 9B6B ldr r3, [r3, #56] + 560 .loc 1 892 24 + 561 010a 9A1C adds r2, r3, #2 + 562 010c FB68 ldr r3, [r7, #12] + 563 010e 9A63 str r2, [r3, #56] + 893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 564 .loc 1 893 11 + 565 0110 FB68 ldr r3, [r7, #12] + 566 0112 DB8F ldrh r3, [r3, #62] @ movhi + 567 0114 9BB2 uxth r3, r3 + 568 .loc 1 893 24 + 569 0116 013B subs r3, r3, #1 + 570 0118 9AB2 uxth r2, r3 + 571 011a FB68 ldr r3, [r7, #12] + 572 011c DA87 strh r2, [r3, #62] @ movhi + 894:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 895:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Transmit data in 16 Bit mode */ + 896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** while (hspi->TxXferCount > 0U) + 573 .loc 1 896 11 + 574 011e 2FE0 b .L27 + 575 .L32: + 897:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Wait until TXE flag is set to send data */ + 899:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) + 576 .loc 1 899 11 + 577 0120 FB68 ldr r3, [r7, #12] + 578 0122 1B68 ldr r3, [r3] + 579 0124 9B68 ldr r3, [r3, #8] + 580 0126 03F00203 and r3, r3, #2 + 581 .loc 1 899 10 + 582 012a 022B cmp r3, #2 + 583 012c 12D1 bne .L28 + 900:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + 584 .loc 1 901 48 + 585 012e FB68 ldr r3, [r7, #12] + 586 0130 9B6B ldr r3, [r3, #56] + 587 .loc 1 901 30 + 588 0132 1A88 ldrh r2, [r3] + 589 .loc 1 901 13 + 590 0134 FB68 ldr r3, [r7, #12] + ARM GAS /tmp/ccs34gJO.s page 27 + + + 591 0136 1B68 ldr r3, [r3] + 592 .loc 1 901 28 + 593 0138 DA60 str r2, [r3, #12] + 902:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 594 .loc 1 902 13 + 595 013a FB68 ldr r3, [r7, #12] + 596 013c 9B6B ldr r3, [r3, #56] + 597 .loc 1 902 26 + 598 013e 9A1C adds r2, r3, #2 + 599 0140 FB68 ldr r3, [r7, #12] + 600 0142 9A63 str r2, [r3, #56] + 903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 601 .loc 1 903 13 + 602 0144 FB68 ldr r3, [r7, #12] + 603 0146 DB8F ldrh r3, [r3, #62] @ movhi + 604 0148 9BB2 uxth r3, r3 + 605 .loc 1 903 26 + 606 014a 013B subs r3, r3, #1 + 607 014c 9AB2 uxth r2, r3 + 608 014e FB68 ldr r3, [r7, #12] + 609 0150 DA87 strh r2, [r3, #62] @ movhi + 610 0152 15E0 b .L27 + 611 .L28: + 904:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 905:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else + 906:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Timeout management */ + 908:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout = + 612 .loc 1 908 16 + 613 0154 FFF7FEFF bl HAL_GetTick + 614 0158 0246 mov r2, r0 + 615 .loc 1 908 30 discriminator 1 + 616 015a BB69 ldr r3, [r7, #24] + 617 015c D31A subs r3, r2, r3 + 618 .loc 1 908 12 discriminator 1 + 619 015e 3A68 ldr r2, [r7] + 620 0160 9A42 cmp r2, r3 + 621 0162 03D8 bhi .L30 + 622 .loc 1 908 56 discriminator 1 + 623 0164 3B68 ldr r3, [r7] + 624 0166 B3F1FF3F cmp r3, #-1 + 625 016a 02D1 bne .L31 + 626 .L30: + 627 .loc 1 908 87 discriminator 3 + 628 016c 3B68 ldr r3, [r7] + 629 016e 002B cmp r3, #0 + 630 0170 06D1 bne .L27 + 631 .L31: + 909:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_TIMEOUT; + 632 .loc 1 910 21 + 633 0172 0323 movs r3, #3 + 634 0174 FB77 strb r3, [r7, #31] + 911:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; + 635 .loc 1 911 23 + 636 0176 FB68 ldr r3, [r7, #12] + 637 0178 0122 movs r2, #1 + ARM GAS /tmp/ccs34gJO.s page 28 + + + 638 017a 83F85D20 strb r2, [r3, #93] + 912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 639 .loc 1 912 11 + 640 017e ABE0 b .L19 + 641 .L27: + 896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 642 .loc 1 896 16 + 643 0180 FB68 ldr r3, [r7, #12] + 644 0182 DB8F ldrh r3, [r3, #62] @ movhi + 645 0184 9BB2 uxth r3, r3 + 896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 646 .loc 1 896 30 + 647 0186 002B cmp r3, #0 + 648 0188 CAD1 bne .L32 + 649 018a 80E0 b .L33 + 650 .L24: + 913:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 914:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 915:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 916:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 917:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Transmit data in 8 Bit mode */ + 918:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else + 919:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 920:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + 651 .loc 1 920 20 + 652 018c FB68 ldr r3, [r7, #12] + 653 018e 5B68 ldr r3, [r3, #4] + 654 .loc 1 920 8 + 655 0190 002B cmp r3, #0 + 656 0192 02D0 beq .L34 + 657 .loc 1 920 45 discriminator 1 + 658 0194 FB8A ldrh r3, [r7, #22] + 659 0196 012B cmp r3, #1 + 660 0198 74D1 bne .L37 + 661 .L34: + 921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 922:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->TxXferCount > 1U) + 662 .loc 1 922 15 + 663 019a FB68 ldr r3, [r7, #12] + 664 019c DB8F ldrh r3, [r3, #62] @ movhi + 665 019e 9BB2 uxth r3, r3 + 666 .loc 1 922 10 + 667 01a0 012B cmp r3, #1 + 668 01a2 12D9 bls .L36 + 923:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 924:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* write on the data register in packing mode */ + 925:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + 669 .loc 1 925 48 + 670 01a4 FB68 ldr r3, [r7, #12] + 671 01a6 9B6B ldr r3, [r3, #56] + 672 .loc 1 925 30 + 673 01a8 1A88 ldrh r2, [r3] + 674 .loc 1 925 13 + 675 01aa FB68 ldr r3, [r7, #12] + 676 01ac 1B68 ldr r3, [r3] + 677 .loc 1 925 28 + 678 01ae DA60 str r2, [r3, #12] + ARM GAS /tmp/ccs34gJO.s page 29 + + + 926:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 679 .loc 1 926 13 + 680 01b0 FB68 ldr r3, [r7, #12] + 681 01b2 9B6B ldr r3, [r3, #56] + 682 .loc 1 926 26 + 683 01b4 9A1C adds r2, r3, #2 + 684 01b6 FB68 ldr r3, [r7, #12] + 685 01b8 9A63 str r2, [r3, #56] + 927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount -= 2U; + 686 .loc 1 927 13 + 687 01ba FB68 ldr r3, [r7, #12] + 688 01bc DB8F ldrh r3, [r3, #62] @ movhi + 689 01be 9BB2 uxth r3, r3 + 690 .loc 1 927 27 + 691 01c0 023B subs r3, r3, #2 + 692 01c2 9AB2 uxth r2, r3 + 693 01c4 FB68 ldr r3, [r7, #12] + 694 01c6 DA87 strh r2, [r3, #62] @ movhi + 695 01c8 5CE0 b .L37 + 696 .L36: + 928:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 929:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else + 930:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 931:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); + 697 .loc 1 931 56 + 698 01ca FB68 ldr r3, [r7, #12] + 699 01cc 9A6B ldr r2, [r3, #56] + 700 .loc 1 931 32 + 701 01ce FB68 ldr r3, [r7, #12] + 702 01d0 1B68 ldr r3, [r3] + 703 .loc 1 931 27 + 704 01d2 0C33 adds r3, r3, #12 + 705 .loc 1 931 51 + 706 01d4 1278 ldrb r2, [r2] @ zero_extendqisi2 + 707 .loc 1 931 48 + 708 01d6 1A70 strb r2, [r3] + 932:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr ++; + 709 .loc 1 932 13 + 710 01d8 FB68 ldr r3, [r7, #12] + 711 01da 9B6B ldr r3, [r3, #56] + 712 .loc 1 932 26 + 713 01dc 5A1C adds r2, r3, #1 + 714 01de FB68 ldr r3, [r7, #12] + 715 01e0 9A63 str r2, [r3, #56] + 933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 716 .loc 1 933 13 + 717 01e2 FB68 ldr r3, [r7, #12] + 718 01e4 DB8F ldrh r3, [r3, #62] @ movhi + 719 01e6 9BB2 uxth r3, r3 + 720 .loc 1 933 26 + 721 01e8 013B subs r3, r3, #1 + 722 01ea 9AB2 uxth r2, r3 + 723 01ec FB68 ldr r3, [r7, #12] + 724 01ee DA87 strh r2, [r3, #62] @ movhi + 934:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 935:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 936:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** while (hspi->TxXferCount > 0U) + ARM GAS /tmp/ccs34gJO.s page 30 + + + 725 .loc 1 936 11 + 726 01f0 48E0 b .L37 + 727 .L43: + 937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Wait until TXE flag is set to send data */ + 939:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) + 728 .loc 1 939 11 + 729 01f2 FB68 ldr r3, [r7, #12] + 730 01f4 1B68 ldr r3, [r3] + 731 01f6 9B68 ldr r3, [r3, #8] + 732 01f8 03F00203 and r3, r3, #2 + 733 .loc 1 939 10 + 734 01fc 022B cmp r3, #2 + 735 01fe 2BD1 bne .L38 + 940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 941:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->TxXferCount > 1U) + 736 .loc 1 941 17 + 737 0200 FB68 ldr r3, [r7, #12] + 738 0202 DB8F ldrh r3, [r3, #62] @ movhi + 739 0204 9BB2 uxth r3, r3 + 740 .loc 1 941 12 + 741 0206 012B cmp r3, #1 + 742 0208 12D9 bls .L39 + 942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 943:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* write on the data register in packing mode */ + 944:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + 743 .loc 1 944 50 + 744 020a FB68 ldr r3, [r7, #12] + 745 020c 9B6B ldr r3, [r3, #56] + 746 .loc 1 944 32 + 747 020e 1A88 ldrh r2, [r3] + 748 .loc 1 944 15 + 749 0210 FB68 ldr r3, [r7, #12] + 750 0212 1B68 ldr r3, [r3] + 751 .loc 1 944 30 + 752 0214 DA60 str r2, [r3, #12] + 945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 753 .loc 1 945 15 + 754 0216 FB68 ldr r3, [r7, #12] + 755 0218 9B6B ldr r3, [r3, #56] + 756 .loc 1 945 28 + 757 021a 9A1C adds r2, r3, #2 + 758 021c FB68 ldr r3, [r7, #12] + 759 021e 9A63 str r2, [r3, #56] + 946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount -= 2U; + 760 .loc 1 946 15 + 761 0220 FB68 ldr r3, [r7, #12] + 762 0222 DB8F ldrh r3, [r3, #62] @ movhi + 763 0224 9BB2 uxth r3, r3 + 764 .loc 1 946 29 + 765 0226 023B subs r3, r3, #2 + 766 0228 9AB2 uxth r2, r3 + 767 022a FB68 ldr r3, [r7, #12] + 768 022c DA87 strh r2, [r3, #62] @ movhi + 769 022e 29E0 b .L37 + 770 .L39: + 947:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + ARM GAS /tmp/ccs34gJO.s page 31 + + + 948:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else + 949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 950:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); + 771 .loc 1 950 58 + 772 0230 FB68 ldr r3, [r7, #12] + 773 0232 9A6B ldr r2, [r3, #56] + 774 .loc 1 950 34 + 775 0234 FB68 ldr r3, [r7, #12] + 776 0236 1B68 ldr r3, [r3] + 777 .loc 1 950 29 + 778 0238 0C33 adds r3, r3, #12 + 779 .loc 1 950 53 + 780 023a 1278 ldrb r2, [r2] @ zero_extendqisi2 + 781 .loc 1 950 50 + 782 023c 1A70 strb r2, [r3] + 951:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr++; + 783 .loc 1 951 15 + 784 023e FB68 ldr r3, [r7, #12] + 785 0240 9B6B ldr r3, [r3, #56] + 786 .loc 1 951 27 + 787 0242 5A1C adds r2, r3, #1 + 788 0244 FB68 ldr r3, [r7, #12] + 789 0246 9A63 str r2, [r3, #56] + 952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 790 .loc 1 952 15 + 791 0248 FB68 ldr r3, [r7, #12] + 792 024a DB8F ldrh r3, [r3, #62] @ movhi + 793 024c 9BB2 uxth r3, r3 + 794 .loc 1 952 28 + 795 024e 013B subs r3, r3, #1 + 796 0250 9AB2 uxth r2, r3 + 797 0252 FB68 ldr r3, [r7, #12] + 798 0254 DA87 strh r2, [r3, #62] @ movhi + 799 0256 15E0 b .L37 + 800 .L38: + 953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 954:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else + 956:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 957:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Timeout management */ + 958:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout = + 801 .loc 1 958 16 + 802 0258 FFF7FEFF bl HAL_GetTick + 803 025c 0246 mov r2, r0 + 804 .loc 1 958 30 discriminator 1 + 805 025e BB69 ldr r3, [r7, #24] + 806 0260 D31A subs r3, r2, r3 + 807 .loc 1 958 12 discriminator 1 + 808 0262 3A68 ldr r2, [r7] + 809 0264 9A42 cmp r2, r3 + 810 0266 03D8 bhi .L41 + 811 .loc 1 958 56 discriminator 1 + 812 0268 3B68 ldr r3, [r7] + 813 026a B3F1FF3F cmp r3, #-1 + 814 026e 02D1 bne .L42 + 815 .L41: + 816 .loc 1 958 87 discriminator 3 + ARM GAS /tmp/ccs34gJO.s page 32 + + + 817 0270 3B68 ldr r3, [r7] + 818 0272 002B cmp r3, #0 + 819 0274 06D1 bne .L37 + 820 .L42: + 959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 960:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_TIMEOUT; + 821 .loc 1 960 21 + 822 0276 0323 movs r3, #3 + 823 0278 FB77 strb r3, [r7, #31] + 961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; + 824 .loc 1 961 23 + 825 027a FB68 ldr r3, [r7, #12] + 826 027c 0122 movs r2, #1 + 827 027e 83F85D20 strb r2, [r3, #93] + 962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 828 .loc 1 962 11 + 829 0282 29E0 b .L19 + 830 .L37: + 936:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 831 .loc 1 936 16 + 832 0284 FB68 ldr r3, [r7, #12] + 833 0286 DB8F ldrh r3, [r3, #62] @ movhi + 834 0288 9BB2 uxth r3, r3 + 936:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 835 .loc 1 936 30 + 836 028a 002B cmp r3, #0 + 837 028c B1D1 bne .L43 + 838 .L33: + 963:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 964:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 965:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 966:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 967:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) + 968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable CRC Transmission */ + 969:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + 970:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 971:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + 972:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 973:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ + 974:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 975:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check the end of the transaction */ + 976:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) + 839 .loc 1 976 7 + 840 028e BA69 ldr r2, [r7, #24] + 841 0290 3968 ldr r1, [r7] + 842 0292 F868 ldr r0, [r7, #12] + 843 0294 FFF7FEFF bl SPI_EndRxTxTransaction + 844 0298 0346 mov r3, r0 + 845 .loc 1 976 6 discriminator 1 + 846 029a 002B cmp r3, #0 + 847 029c 02D0 beq .L44 + 977:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 978:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + 848 .loc 1 978 21 + 849 029e FB68 ldr r3, [r7, #12] + 850 02a0 2022 movs r2, #32 + 851 02a2 1A66 str r2, [r3, #96] + ARM GAS /tmp/ccs34gJO.s page 33 + + + 852 .L44: + 979:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 981:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Clear overrun flag in 2 Lines communication mode because received is not read */ + 982:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + 853 .loc 1 982 17 + 854 02a4 FB68 ldr r3, [r7, #12] + 855 02a6 9B68 ldr r3, [r3, #8] + 856 .loc 1 982 6 + 857 02a8 002B cmp r3, #0 + 858 02aa 0AD1 bne .L45 + 859 .LBB2: + 983:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_OVRFLAG(hspi); + 860 .loc 1 984 5 + 861 02ac 0023 movs r3, #0 + 862 02ae 3B61 str r3, [r7, #16] + 863 02b0 FB68 ldr r3, [r7, #12] + 864 02b2 1B68 ldr r3, [r3] + 865 02b4 DB68 ldr r3, [r3, #12] + 866 02b6 3B61 str r3, [r7, #16] + 867 02b8 FB68 ldr r3, [r7, #12] + 868 02ba 1B68 ldr r3, [r3] + 869 02bc 9B68 ldr r3, [r3, #8] + 870 02be 3B61 str r3, [r7, #16] + 871 02c0 3B69 ldr r3, [r7, #16] + 872 .L45: + 873 .LBE2: + 985:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 986:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 987:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + 874 .loc 1 987 11 + 875 02c2 FB68 ldr r3, [r7, #12] + 876 02c4 1B6E ldr r3, [r3, #96] + 877 .loc 1 987 6 + 878 02c6 002B cmp r3, #0 + 879 02c8 02D0 beq .L46 + 988:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 989:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; + 880 .loc 1 989 15 + 881 02ca 0123 movs r3, #1 + 882 02cc FB77 strb r3, [r7, #31] + 883 02ce 03E0 b .L19 + 884 .L46: + 990:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 991:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else + 992:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 993:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; + 885 .loc 1 993 17 + 886 02d0 FB68 ldr r3, [r7, #12] + 887 02d2 0122 movs r2, #1 + 888 02d4 83F85D20 strb r2, [r3, #93] + 889 .L19: + 994:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + 996:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** error: + 997:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Process Unlocked */ + ARM GAS /tmp/ccs34gJO.s page 34 + + + 998:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_UNLOCK(hspi); + 890 .loc 1 998 3 + 891 02d8 FB68 ldr r3, [r7, #12] + 892 02da 0022 movs r2, #0 + 893 02dc 83F85C20 strb r2, [r3, #92] + 999:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; + 894 .loc 1 999 10 + 895 02e0 FB7F ldrb r3, [r7, #31] @ zero_extendqisi2 + 896 .L17: +1000:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 897 .loc 1 1000 1 + 898 02e2 1846 mov r0, r3 + 899 02e4 2037 adds r7, r7, #32 + 900 .cfi_def_cfa_offset 8 + 901 02e6 BD46 mov sp, r7 + 902 .cfi_def_cfa_register 13 + 903 @ sp needed + 904 02e8 80BD pop {r7, pc} + 905 .cfi_endproc + 906 .LFE134: + 908 .section .text.HAL_SPI_Receive,"ax",%progbits + 909 .align 1 + 910 .global HAL_SPI_Receive + 911 .syntax unified + 912 .thumb + 913 .thumb_func + 915 HAL_SPI_Receive: + 916 .LFB135: +1001:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1002:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +1003:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Receive an amount of data in blocking mode. +1004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +1005:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +1006:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param pData pointer to data buffer +1007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param Size amount of data to be received +1008:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param Timeout Timeout duration +1009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval HAL status +1010:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +1011:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t +1012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 917 .loc 1 1012 1 + 918 .cfi_startproc + 919 @ args = 0, pretend = 0, frame = 24 + 920 @ frame_needed = 1, uses_anonymous_args = 0 + 921 0000 80B5 push {r7, lr} + 922 .cfi_def_cfa_offset 8 + 923 .cfi_offset 7, -8 + 924 .cfi_offset 14, -4 + 925 0002 88B0 sub sp, sp, #32 + 926 .cfi_def_cfa_offset 40 + 927 0004 02AF add r7, sp, #8 + 928 .cfi_def_cfa 7, 32 + 929 0006 F860 str r0, [r7, #12] + 930 0008 B960 str r1, [r7, #8] + 931 000a 3B60 str r3, [r7] + 932 000c 1346 mov r3, r2 @ movhi + 933 000e FB80 strh r3, [r7, #6] @ movhi + ARM GAS /tmp/ccs34gJO.s page 35 + + +1013:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +1014:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint32_t tmpreg = 0U; +1015:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint8_t *ptmpreg8; +1016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint8_t tmpreg8 = 0; +1017:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +1018:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t tickstart; +1019:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef errorcode = HAL_OK; + 934 .loc 1 1019 21 + 935 0010 0023 movs r3, #0 + 936 0012 FB75 strb r3, [r7, #23] +1020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1021:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->State != HAL_SPI_STATE_READY) + 937 .loc 1 1021 11 + 938 0014 FB68 ldr r3, [r7, #12] + 939 0016 93F85D30 ldrb r3, [r3, #93] + 940 001a DBB2 uxtb r3, r3 + 941 .loc 1 1021 6 + 942 001c 012B cmp r3, #1 + 943 001e 02D0 beq .L48 +1022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1023:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_BUSY; + 944 .loc 1 1023 15 + 945 0020 0223 movs r3, #2 + 946 0022 FB75 strb r3, [r7, #23] +1024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 947 .loc 1 1024 5 + 948 0024 1AE1 b .L49 + 949 .L48: +1025:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) + 950 .loc 1 1027 18 + 951 0026 FB68 ldr r3, [r7, #12] + 952 0028 5B68 ldr r3, [r3, #4] + 953 .loc 1 1027 6 + 954 002a B3F5827F cmp r3, #260 + 955 002e 12D1 bne .L50 + 956 .loc 1 1027 58 discriminator 1 + 957 0030 FB68 ldr r3, [r7, #12] + 958 0032 9B68 ldr r3, [r3, #8] + 959 .loc 1 1027 44 discriminator 1 + 960 0034 002B cmp r3, #0 + 961 0036 0ED1 bne .L50 +1028:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_BUSY_RX; + 962 .loc 1 1029 17 + 963 0038 FB68 ldr r3, [r7, #12] + 964 003a 0422 movs r2, #4 + 965 003c 83F85D20 strb r2, [r3, #93] +1030:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line +1031:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout); + 966 .loc 1 1031 12 + 967 0040 FA88 ldrh r2, [r7, #6] + 968 0042 3B68 ldr r3, [r7] + 969 0044 0093 str r3, [sp] + 970 0046 1346 mov r3, r2 + 971 0048 BA68 ldr r2, [r7, #8] + ARM GAS /tmp/ccs34gJO.s page 36 + + + 972 004a B968 ldr r1, [r7, #8] + 973 004c F868 ldr r0, [r7, #12] + 974 004e FFF7FEFF bl HAL_SPI_TransmitReceive + 975 0052 0346 mov r3, r0 + 976 0054 07E1 b .L51 + 977 .L50: +1032:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1033:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Process Locked */ +1035:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_LOCK(hspi); + 978 .loc 1 1035 3 + 979 0056 FB68 ldr r3, [r7, #12] + 980 0058 93F85C30 ldrb r3, [r3, #92] @ zero_extendqisi2 + 981 005c 012B cmp r3, #1 + 982 005e 01D1 bne .L52 + 983 .loc 1 1035 3 is_stmt 0 discriminator 1 + 984 0060 0223 movs r3, #2 + 985 .loc 1 1035 3 + 986 0062 00E1 b .L51 + 987 .L52: + 988 .loc 1 1035 3 discriminator 2 + 989 0064 FB68 ldr r3, [r7, #12] + 990 0066 0122 movs r2, #1 + 991 0068 83F85C20 strb r2, [r3, #92] +1036:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Init tickstart for timeout management*/ +1038:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tickstart = HAL_GetTick(); + 992 .loc 1 1038 15 is_stmt 1 + 993 006c FFF7FEFF bl HAL_GetTick + 994 0070 3861 str r0, [r7, #16] +1039:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1040:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((pData == NULL) || (Size == 0U)) + 995 .loc 1 1040 6 + 996 0072 BB68 ldr r3, [r7, #8] + 997 0074 002B cmp r3, #0 + 998 0076 02D0 beq .L53 + 999 .loc 1 1040 23 discriminator 1 + 1000 0078 FB88 ldrh r3, [r7, #6] + 1001 007a 002B cmp r3, #0 + 1002 007c 02D1 bne .L54 + 1003 .L53: +1041:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; + 1004 .loc 1 1042 15 + 1005 007e 0123 movs r3, #1 + 1006 0080 FB75 strb r3, [r7, #23] +1043:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 1007 .loc 1 1043 5 + 1008 0082 EBE0 b .L49 + 1009 .L54: +1044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1045:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1046:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the transaction information */ +1047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_BUSY_RX; + 1010 .loc 1 1047 21 + 1011 0084 FB68 ldr r3, [r7, #12] + 1012 0086 0422 movs r2, #4 + ARM GAS /tmp/ccs34gJO.s page 37 + + + 1013 0088 83F85D20 strb r2, [r3, #93] +1048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 1014 .loc 1 1048 21 + 1015 008c FB68 ldr r3, [r7, #12] + 1016 008e 0022 movs r2, #0 + 1017 0090 1A66 str r2, [r3, #96] +1049:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr = (uint8_t *)pData; + 1018 .loc 1 1049 21 + 1019 0092 FB68 ldr r3, [r7, #12] + 1020 0094 BA68 ldr r2, [r7, #8] + 1021 0096 1A64 str r2, [r3, #64] +1050:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferSize = Size; + 1022 .loc 1 1050 21 + 1023 0098 FB68 ldr r3, [r7, #12] + 1024 009a FA88 ldrh r2, [r7, #6] @ movhi + 1025 009c A3F84420 strh r2, [r3, #68] @ movhi +1051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = Size; + 1026 .loc 1 1051 21 + 1027 00a0 FB68 ldr r3, [r7, #12] + 1028 00a2 FA88 ldrh r2, [r7, #6] @ movhi + 1029 00a4 A3F84620 strh r2, [r3, #70] @ movhi +1052:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /*Init field not used in handle to zero */ +1054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr = (uint8_t *)NULL; + 1030 .loc 1 1054 21 + 1031 00a8 FB68 ldr r3, [r7, #12] + 1032 00aa 0022 movs r2, #0 + 1033 00ac 9A63 str r2, [r3, #56] +1055:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferSize = 0U; + 1034 .loc 1 1055 21 + 1035 00ae FB68 ldr r3, [r7, #12] + 1036 00b0 0022 movs r2, #0 + 1037 00b2 9A87 strh r2, [r3, #60] @ movhi +1056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = 0U; + 1038 .loc 1 1056 21 + 1039 00b4 FB68 ldr r3, [r7, #12] + 1040 00b6 0022 movs r2, #0 + 1041 00b8 DA87 strh r2, [r3, #62] @ movhi +1057:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxISR = NULL; + 1042 .loc 1 1057 21 + 1043 00ba FB68 ldr r3, [r7, #12] + 1044 00bc 0022 movs r2, #0 + 1045 00be DA64 str r2, [r3, #76] +1058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxISR = NULL; + 1046 .loc 1 1058 21 + 1047 00c0 FB68 ldr r3, [r7, #12] + 1048 00c2 0022 movs r2, #0 + 1049 00c4 1A65 str r2, [r3, #80] +1059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1060:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +1061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset CRC Calculation */ +1062:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +1063:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1064:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_RESET_CRC(hspi); +1065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* this is done to handle the CRCNEXT before the latest data */ +1066:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount--; +1067:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + ARM GAS /tmp/ccs34gJO.s page 38 + + +1068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +1069:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1070:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the Rx Fifo threshold */ +1071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + 1050 .loc 1 1071 17 + 1051 00c6 FB68 ldr r3, [r7, #12] + 1052 00c8 DB68 ldr r3, [r3, #12] + 1053 .loc 1 1071 6 + 1054 00ca B3F5E06F cmp r3, #1792 + 1055 00ce 08D9 bls .L55 +1072:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1073:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set RX Fifo threshold according the reception data length: 16bit */ +1074:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + 1056 .loc 1 1074 5 + 1057 00d0 FB68 ldr r3, [r7, #12] + 1058 00d2 1B68 ldr r3, [r3] + 1059 00d4 5A68 ldr r2, [r3, #4] + 1060 00d6 FB68 ldr r3, [r7, #12] + 1061 00d8 1B68 ldr r3, [r3] + 1062 00da 22F48052 bic r2, r2, #4096 + 1063 00de 5A60 str r2, [r3, #4] + 1064 00e0 07E0 b .L56 + 1065 .L55: +1075:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1076:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +1077:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1078:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set RX Fifo threshold according the reception data length: 8bit */ +1079:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + 1066 .loc 1 1079 5 + 1067 00e2 FB68 ldr r3, [r7, #12] + 1068 00e4 1B68 ldr r3, [r3] + 1069 00e6 5A68 ldr r2, [r3, #4] + 1070 00e8 FB68 ldr r3, [r7, #12] + 1071 00ea 1B68 ldr r3, [r3] + 1072 00ec 42F48052 orr r2, r2, #4096 + 1073 00f0 5A60 str r2, [r3, #4] + 1074 .L56: +1080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1081:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Configure communication direction: 1Line */ +1083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + 1075 .loc 1 1083 17 + 1076 00f2 FB68 ldr r3, [r7, #12] + 1077 00f4 9B68 ldr r3, [r3, #8] + 1078 .loc 1 1083 6 + 1079 00f6 B3F5004F cmp r3, #32768 + 1080 00fa 0FD1 bne .L57 +1084:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ +1086:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE(hspi); + 1081 .loc 1 1086 5 + 1082 00fc FB68 ldr r3, [r7, #12] + 1083 00fe 1B68 ldr r3, [r3] + 1084 0100 1A68 ldr r2, [r3] + 1085 0102 FB68 ldr r3, [r7, #12] + 1086 0104 1B68 ldr r3, [r3] + 1087 0106 22F04002 bic r2, r2, #64 + ARM GAS /tmp/ccs34gJO.s page 39 + + + 1088 010a 1A60 str r2, [r3] +1087:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_1LINE_RX(hspi); + 1089 .loc 1 1087 5 + 1090 010c FB68 ldr r3, [r7, #12] + 1091 010e 1B68 ldr r3, [r3] + 1092 0110 1A68 ldr r2, [r3] + 1093 0112 FB68 ldr r3, [r7, #12] + 1094 0114 1B68 ldr r3, [r3] + 1095 0116 22F48042 bic r2, r2, #16384 + 1096 011a 1A60 str r2, [r3] + 1097 .L57: +1088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1089:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1090:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check if the SPI is already enabled */ +1091:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + 1098 .loc 1 1091 12 + 1099 011c FB68 ldr r3, [r7, #12] + 1100 011e 1B68 ldr r3, [r3] + 1101 .loc 1 1091 22 + 1102 0120 1B68 ldr r3, [r3] + 1103 .loc 1 1091 28 + 1104 0122 03F04003 and r3, r3, #64 + 1105 .loc 1 1091 6 + 1106 0126 402B cmp r3, #64 + 1107 0128 07D0 beq .L58 +1092:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1093:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable SPI peripheral */ +1094:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_ENABLE(hspi); + 1108 .loc 1 1094 5 + 1109 012a FB68 ldr r3, [r7, #12] + 1110 012c 1B68 ldr r3, [r3] + 1111 012e 1A68 ldr r2, [r3] + 1112 0130 FB68 ldr r3, [r7, #12] + 1113 0132 1B68 ldr r3, [r3] + 1114 0134 42F04002 orr r2, r2, #64 + 1115 0138 1A60 str r2, [r3] + 1116 .L58: +1095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1096:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1097:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Receive data in 8 Bit mode */ +1098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT) + 1117 .loc 1 1098 17 + 1118 013a FB68 ldr r3, [r7, #12] + 1119 013c DB68 ldr r3, [r3, #12] + 1120 .loc 1 1098 6 + 1121 013e B3F5E06F cmp r3, #1792 + 1122 0142 6FD8 bhi .L67 +1099:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Transfer loop */ +1101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** while (hspi->RxXferCount > 0U) + 1123 .loc 1 1101 11 + 1124 0144 34E0 b .L60 + 1125 .L65: +1102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check the RXNE flag */ +1104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) + 1126 .loc 1 1104 11 + ARM GAS /tmp/ccs34gJO.s page 40 + + + 1127 0146 FB68 ldr r3, [r7, #12] + 1128 0148 1B68 ldr r3, [r3] + 1129 014a 9B68 ldr r3, [r3, #8] + 1130 014c 03F00103 and r3, r3, #1 + 1131 .loc 1 1104 10 + 1132 0150 012B cmp r3, #1 + 1133 0152 17D1 bne .L61 +1105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* read the received data */ +1107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR; + 1134 .loc 1 1107 65 + 1135 0154 FB68 ldr r3, [r7, #12] + 1136 0156 1B68 ldr r3, [r3] + 1137 .loc 1 1107 60 + 1138 0158 03F10C02 add r2, r3, #12 + 1139 .loc 1 1107 27 + 1140 015c FB68 ldr r3, [r7, #12] + 1141 015e 1B6C ldr r3, [r3, #64] + 1142 .loc 1 1107 43 + 1143 0160 1278 ldrb r2, [r2] + 1144 0162 D2B2 uxtb r2, r2 + 1145 .loc 1 1107 41 + 1146 0164 1A70 strb r2, [r3] +1108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr += sizeof(uint8_t); + 1147 .loc 1 1108 13 + 1148 0166 FB68 ldr r3, [r7, #12] + 1149 0168 1B6C ldr r3, [r3, #64] + 1150 .loc 1 1108 26 + 1151 016a 5A1C adds r2, r3, #1 + 1152 016c FB68 ldr r3, [r7, #12] + 1153 016e 1A64 str r2, [r3, #64] +1109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount--; + 1154 .loc 1 1109 13 + 1155 0170 FB68 ldr r3, [r7, #12] + 1156 0172 B3F84630 ldrh r3, [r3, #70] @ movhi + 1157 0176 9BB2 uxth r3, r3 + 1158 .loc 1 1109 26 + 1159 0178 013B subs r3, r3, #1 + 1160 017a 9AB2 uxth r2, r3 + 1161 017c FB68 ldr r3, [r7, #12] + 1162 017e A3F84620 strh r2, [r3, #70] @ movhi + 1163 0182 15E0 b .L60 + 1164 .L61: +1110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +1112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Timeout management */ +1114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout = + 1165 .loc 1 1114 16 + 1166 0184 FFF7FEFF bl HAL_GetTick + 1167 0188 0246 mov r2, r0 + 1168 .loc 1 1114 30 discriminator 1 + 1169 018a 3B69 ldr r3, [r7, #16] + 1170 018c D31A subs r3, r2, r3 + 1171 .loc 1 1114 12 discriminator 1 + 1172 018e 3A68 ldr r2, [r7] + 1173 0190 9A42 cmp r2, r3 + ARM GAS /tmp/ccs34gJO.s page 41 + + + 1174 0192 03D8 bhi .L63 + 1175 .loc 1 1114 56 discriminator 1 + 1176 0194 3B68 ldr r3, [r7] + 1177 0196 B3F1FF3F cmp r3, #-1 + 1178 019a 02D1 bne .L64 + 1179 .L63: + 1180 .loc 1 1114 87 discriminator 3 + 1181 019c 3B68 ldr r3, [r7] + 1182 019e 002B cmp r3, #0 + 1183 01a0 06D1 bne .L60 + 1184 .L64: +1115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_TIMEOUT; + 1185 .loc 1 1116 21 + 1186 01a2 0323 movs r3, #3 + 1187 01a4 FB75 strb r3, [r7, #23] +1117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; + 1188 .loc 1 1117 23 + 1189 01a6 FB68 ldr r3, [r7, #12] + 1190 01a8 0122 movs r2, #1 + 1191 01aa 83F85D20 strb r2, [r3, #93] +1118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 1192 .loc 1 1118 11 + 1193 01ae 55E0 b .L49 + 1194 .L60: +1101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1195 .loc 1 1101 16 + 1196 01b0 FB68 ldr r3, [r7, #12] + 1197 01b2 B3F84630 ldrh r3, [r3, #70] @ movhi + 1198 01b6 9BB2 uxth r3, r3 +1101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1199 .loc 1 1101 30 + 1200 01b8 002B cmp r3, #0 + 1201 01ba C4D1 bne .L65 + 1202 01bc 38E0 b .L66 + 1203 .L72: +1119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +1124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Transfer loop */ +1126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** while (hspi->RxXferCount > 0U) +1127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check the RXNE flag */ +1129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) + 1204 .loc 1 1129 11 + 1205 01be FB68 ldr r3, [r7, #12] + 1206 01c0 1B68 ldr r3, [r3] + 1207 01c2 9B68 ldr r3, [r3, #8] + 1208 01c4 03F00103 and r3, r3, #1 + 1209 .loc 1 1129 10 + 1210 01c8 012B cmp r3, #1 + 1211 01ca 15D1 bne .L68 +1130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; + ARM GAS /tmp/ccs34gJO.s page 42 + + + 1212 .loc 1 1131 57 + 1213 01cc FB68 ldr r3, [r7, #12] + 1214 01ce 1B68 ldr r3, [r3] + 1215 .loc 1 1131 67 + 1216 01d0 DA68 ldr r2, [r3, #12] + 1217 .loc 1 1131 27 + 1218 01d2 FB68 ldr r3, [r7, #12] + 1219 01d4 1B6C ldr r3, [r3, #64] + 1220 .loc 1 1131 43 + 1221 01d6 92B2 uxth r2, r2 + 1222 .loc 1 1131 41 + 1223 01d8 1A80 strh r2, [r3] @ movhi +1132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr += sizeof(uint16_t); + 1224 .loc 1 1132 13 + 1225 01da FB68 ldr r3, [r7, #12] + 1226 01dc 1B6C ldr r3, [r3, #64] + 1227 .loc 1 1132 26 + 1228 01de 9A1C adds r2, r3, #2 + 1229 01e0 FB68 ldr r3, [r7, #12] + 1230 01e2 1A64 str r2, [r3, #64] +1133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount--; + 1231 .loc 1 1133 13 + 1232 01e4 FB68 ldr r3, [r7, #12] + 1233 01e6 B3F84630 ldrh r3, [r3, #70] @ movhi + 1234 01ea 9BB2 uxth r3, r3 + 1235 .loc 1 1133 26 + 1236 01ec 013B subs r3, r3, #1 + 1237 01ee 9AB2 uxth r2, r3 + 1238 01f0 FB68 ldr r3, [r7, #12] + 1239 01f2 A3F84620 strh r2, [r3, #70] @ movhi + 1240 01f6 15E0 b .L67 + 1241 .L68: +1134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +1136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Timeout management */ +1138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout = + 1242 .loc 1 1138 16 + 1243 01f8 FFF7FEFF bl HAL_GetTick + 1244 01fc 0246 mov r2, r0 + 1245 .loc 1 1138 30 discriminator 1 + 1246 01fe 3B69 ldr r3, [r7, #16] + 1247 0200 D31A subs r3, r2, r3 + 1248 .loc 1 1138 12 discriminator 1 + 1249 0202 3A68 ldr r2, [r7] + 1250 0204 9A42 cmp r2, r3 + 1251 0206 03D8 bhi .L70 + 1252 .loc 1 1138 56 discriminator 1 + 1253 0208 3B68 ldr r3, [r7] + 1254 020a B3F1FF3F cmp r3, #-1 + 1255 020e 02D1 bne .L71 + 1256 .L70: + 1257 .loc 1 1138 87 discriminator 3 + 1258 0210 3B68 ldr r3, [r7] + 1259 0212 002B cmp r3, #0 + 1260 0214 06D1 bne .L67 + 1261 .L71: + ARM GAS /tmp/ccs34gJO.s page 43 + + +1139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_TIMEOUT; + 1262 .loc 1 1140 21 + 1263 0216 0323 movs r3, #3 + 1264 0218 FB75 strb r3, [r7, #23] +1141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; + 1265 .loc 1 1141 23 + 1266 021a FB68 ldr r3, [r7, #12] + 1267 021c 0122 movs r2, #1 + 1268 021e 83F85D20 strb r2, [r3, #93] +1142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 1269 .loc 1 1142 11 + 1270 0222 1BE0 b .L49 + 1271 .L67: +1126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1272 .loc 1 1126 16 + 1273 0224 FB68 ldr r3, [r7, #12] + 1274 0226 B3F84630 ldrh r3, [r3, #70] @ movhi + 1275 022a 9BB2 uxth r3, r3 +1126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1276 .loc 1 1126 30 + 1277 022c 002B cmp r3, #0 + 1278 022e C6D1 bne .L72 + 1279 .L66: +1143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +1149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Handle the CRC Transmission */ +1150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +1151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* freeze the CRC before the latest data */ +1153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); +1154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Read the latest data */ +1156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) +1157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* the latest data has not been received */ +1159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_TIMEOUT; +1160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; +1161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Receive last data in 16 Bit mode */ +1164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) +1165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; +1167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Receive last data in 8 Bit mode */ +1169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +1170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR; +1172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Wait the CRC data */ +1175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) + ARM GAS /tmp/ccs34gJO.s page 44 + + +1176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); +1178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_TIMEOUT; +1179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; +1180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Read CRC to Flush DR and RXNE flag */ +1183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) +1184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Read 16bit CRC */ +1186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmpreg = READ_REG(hspi->Instance->DR); +1187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* To avoid GCC warning */ +1188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(tmpreg); +1189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +1191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Initialize the 8bit temporary pointer */ +1193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; +1194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Read 8bit CRC */ +1195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmpreg8 = *ptmpreg8; +1196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* To avoid GCC warning */ +1197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(tmpreg8); +1198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16B +1200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) +1202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Error on the CRC reception */ +1204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); +1205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_TIMEOUT; +1206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; +1207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ +1209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmpreg8 = *ptmpreg8; +1210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* To avoid GCC warning */ +1211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(tmpreg8); +1212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +1216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check the end of the transaction */ +1218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK) + 1280 .loc 1 1218 7 + 1281 0230 3A69 ldr r2, [r7, #16] + 1282 0232 3968 ldr r1, [r7] + 1283 0234 F868 ldr r0, [r7, #12] + 1284 0236 FFF7FEFF bl SPI_EndRxTransaction + 1285 023a 0346 mov r3, r0 + 1286 .loc 1 1218 6 discriminator 1 + 1287 023c 002B cmp r3, #0 + 1288 023e 02D0 beq .L73 +1219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + 1289 .loc 1 1220 21 + 1290 0240 FB68 ldr r3, [r7, #12] + 1291 0242 2022 movs r2, #32 + ARM GAS /tmp/ccs34gJO.s page 45 + + + 1292 0244 1A66 str r2, [r3, #96] + 1293 .L73: +1221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +1224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check if CRC error occurred */ +1225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) +1226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); +1228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_CRCERRFLAG(hspi); +1229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +1231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + 1294 .loc 1 1232 11 + 1295 0246 FB68 ldr r3, [r7, #12] + 1296 0248 1B6E ldr r3, [r3, #96] + 1297 .loc 1 1232 6 + 1298 024a 002B cmp r3, #0 + 1299 024c 02D0 beq .L74 +1233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; + 1300 .loc 1 1234 15 + 1301 024e 0123 movs r3, #1 + 1302 0250 FB75 strb r3, [r7, #23] + 1303 0252 03E0 b .L49 + 1304 .L74: +1235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +1237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; + 1305 .loc 1 1238 17 + 1306 0254 FB68 ldr r3, [r7, #12] + 1307 0256 0122 movs r2, #1 + 1308 0258 83F85D20 strb r2, [r3, #93] + 1309 .L49: +1239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** error : +1242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_UNLOCK(hspi); + 1310 .loc 1 1242 3 + 1311 025c FB68 ldr r3, [r7, #12] + 1312 025e 0022 movs r2, #0 + 1313 0260 83F85C20 strb r2, [r3, #92] +1243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; + 1314 .loc 1 1243 10 + 1315 0264 FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 1316 .L51: +1244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 1317 .loc 1 1244 1 + 1318 0266 1846 mov r0, r3 + 1319 0268 1837 adds r7, r7, #24 + 1320 .cfi_def_cfa_offset 8 + 1321 026a BD46 mov sp, r7 + 1322 .cfi_def_cfa_register 13 + 1323 @ sp needed + 1324 026c 80BD pop {r7, pc} + ARM GAS /tmp/ccs34gJO.s page 46 + + + 1325 .cfi_endproc + 1326 .LFE135: + 1328 .section .text.HAL_SPI_TransmitReceive,"ax",%progbits + 1329 .align 1 + 1330 .global HAL_SPI_TransmitReceive + 1331 .syntax unified + 1332 .thumb + 1333 .thumb_func + 1335 HAL_SPI_TransmitReceive: + 1336 .LFB136: +1245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +1247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Transmit and Receive an amount of data in blocking mode. +1248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +1249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +1250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param pTxData pointer to transmission data buffer +1251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param pRxData pointer to reception data buffer +1252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param Size amount of data to be sent and received +1253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param Timeout Timeout duration +1254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval HAL status +1255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +1256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxDa +1257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t Timeout) +1258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1337 .loc 1 1258 1 + 1338 .cfi_startproc + 1339 @ args = 4, pretend = 0, frame = 40 + 1340 @ frame_needed = 1, uses_anonymous_args = 0 + 1341 0000 80B5 push {r7, lr} + 1342 .cfi_def_cfa_offset 8 + 1343 .cfi_offset 7, -8 + 1344 .cfi_offset 14, -4 + 1345 0002 8AB0 sub sp, sp, #40 + 1346 .cfi_def_cfa_offset 48 + 1347 0004 00AF add r7, sp, #0 + 1348 .cfi_def_cfa_register 7 + 1349 0006 F860 str r0, [r7, #12] + 1350 0008 B960 str r1, [r7, #8] + 1351 000a 7A60 str r2, [r7, #4] + 1352 000c 7B80 strh r3, [r7, #2] @ movhi +1259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint16_t initial_TxXferCount; +1260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint16_t initial_RxXferCount; +1261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t tmp_mode; +1262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_StateTypeDef tmp_state; +1263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t tickstart; +1264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +1265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint32_t tmpreg = 0U; +1266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t spi_cr1; +1267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t spi_cr2; +1268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint8_t *ptmpreg8; +1269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint8_t tmpreg8 = 0; +1270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +1271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Variable used to alternate Rx and Tx during transfer */ +1273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t txallowed = 1U; + 1353 .loc 1 1273 24 + 1354 000e 0123 movs r3, #1 + ARM GAS /tmp/ccs34gJO.s page 47 + + + 1355 0010 7B62 str r3, [r7, #36] +1274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef errorcode = HAL_OK; + 1356 .loc 1 1274 24 + 1357 0012 0023 movs r3, #0 + 1358 0014 87F82330 strb r3, [r7, #35] +1275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check Direction parameter */ +1277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); +1278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Process Locked */ +1280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_LOCK(hspi); + 1359 .loc 1 1280 3 + 1360 0018 FB68 ldr r3, [r7, #12] + 1361 001a 93F85C30 ldrb r3, [r3, #92] @ zero_extendqisi2 + 1362 001e 012B cmp r3, #1 + 1363 0020 01D1 bne .L76 + 1364 .loc 1 1280 3 is_stmt 0 discriminator 1 + 1365 0022 0223 movs r3, #2 + 1366 .loc 1 1280 3 + 1367 0024 0AE2 b .L77 + 1368 .L76: + 1369 .loc 1 1280 3 discriminator 2 + 1370 0026 FB68 ldr r3, [r7, #12] + 1371 0028 0122 movs r2, #1 + 1372 002a 83F85C20 strb r2, [r3, #92] +1281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Init tickstart for timeout management*/ +1283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tickstart = HAL_GetTick(); + 1373 .loc 1 1283 15 is_stmt 1 + 1374 002e FFF7FEFF bl HAL_GetTick + 1375 0032 F861 str r0, [r7, #28] +1284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Init temporary variables */ +1286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmp_state = hspi->State; + 1376 .loc 1 1286 23 + 1377 0034 FB68 ldr r3, [r7, #12] + 1378 0036 93F85D30 ldrb r3, [r3, #93] + 1379 003a FB76 strb r3, [r7, #27] +1287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmp_mode = hspi->Init.Mode; + 1380 .loc 1 1287 23 + 1381 003c FB68 ldr r3, [r7, #12] + 1382 003e 5B68 ldr r3, [r3, #4] + 1383 0040 7B61 str r3, [r7, #20] +1288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** initial_TxXferCount = Size; + 1384 .loc 1 1288 23 + 1385 0042 7B88 ldrh r3, [r7, #2] @ movhi + 1386 0044 7B82 strh r3, [r7, #18] @ movhi +1289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** initial_RxXferCount = Size; + 1387 .loc 1 1289 23 + 1388 0046 7B88 ldrh r3, [r7, #2] @ movhi + 1389 0048 3B82 strh r3, [r7, #16] @ movhi +1290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +1291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** spi_cr1 = READ_REG(hspi->Instance->CR1); +1292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** spi_cr2 = READ_REG(hspi->Instance->CR2); +1293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +1294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (!((tmp_state == HAL_SPI_STATE_READY) || \ + ARM GAS /tmp/ccs34gJO.s page 48 + + + 1390 .loc 1 1295 6 + 1391 004a FB7E ldrb r3, [r7, #27] @ zero_extendqisi2 + 1392 004c 012B cmp r3, #1 + 1393 004e 0ED0 beq .L78 + 1394 .loc 1 1295 7 discriminator 1 + 1395 0050 7B69 ldr r3, [r7, #20] + 1396 0052 B3F5827F cmp r3, #260 + 1397 0056 06D1 bne .L79 +1296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_st + 1398 .loc 1 1296 54 + 1399 0058 FB68 ldr r3, [r7, #12] + 1400 005a 9B68 ldr r3, [r3, #8] + 1401 .loc 1 1296 40 + 1402 005c 002B cmp r3, #0 + 1403 005e 02D1 bne .L79 + 1404 .loc 1 1296 90 discriminator 1 + 1405 0060 FB7E ldrb r3, [r7, #27] @ zero_extendqisi2 + 1406 0062 042B cmp r3, #4 + 1407 0064 03D0 beq .L78 + 1408 .L79: +1297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_BUSY; + 1409 .loc 1 1298 15 + 1410 0066 0223 movs r3, #2 + 1411 0068 87F82330 strb r3, [r7, #35] +1299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 1412 .loc 1 1299 5 + 1413 006c E0E1 b .L80 + 1414 .L78: +1300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + 1415 .loc 1 1302 6 + 1416 006e BB68 ldr r3, [r7, #8] + 1417 0070 002B cmp r3, #0 + 1418 0072 05D0 beq .L81 + 1419 .loc 1 1302 25 discriminator 1 + 1420 0074 7B68 ldr r3, [r7, #4] + 1421 0076 002B cmp r3, #0 + 1422 0078 02D0 beq .L81 + 1423 .loc 1 1302 46 discriminator 2 + 1424 007a 7B88 ldrh r3, [r7, #2] + 1425 007c 002B cmp r3, #0 + 1426 007e 03D1 bne .L82 + 1427 .L81: +1303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; + 1428 .loc 1 1304 15 + 1429 0080 0123 movs r3, #1 + 1430 0082 87F82330 strb r3, [r7, #35] +1305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 1431 .loc 1 1305 5 + 1432 0086 D3E1 b .L80 + 1433 .L82: +1306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ + ARM GAS /tmp/ccs34gJO.s page 49 + + +1309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->State != HAL_SPI_STATE_BUSY_RX) + 1434 .loc 1 1309 11 + 1435 0088 FB68 ldr r3, [r7, #12] + 1436 008a 93F85D30 ldrb r3, [r3, #93] + 1437 008e DBB2 uxtb r3, r3 + 1438 .loc 1 1309 6 + 1439 0090 042B cmp r3, #4 + 1440 0092 03D0 beq .L83 +1310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + 1441 .loc 1 1311 17 + 1442 0094 FB68 ldr r3, [r7, #12] + 1443 0096 0522 movs r2, #5 + 1444 0098 83F85D20 strb r2, [r3, #93] + 1445 .L83: +1312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the transaction information */ +1315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 1446 .loc 1 1315 21 + 1447 009c FB68 ldr r3, [r7, #12] + 1448 009e 0022 movs r2, #0 + 1449 00a0 1A66 str r2, [r3, #96] +1316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr = (uint8_t *)pRxData; + 1450 .loc 1 1316 21 + 1451 00a2 FB68 ldr r3, [r7, #12] + 1452 00a4 7A68 ldr r2, [r7, #4] + 1453 00a6 1A64 str r2, [r3, #64] +1317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = Size; + 1454 .loc 1 1317 21 + 1455 00a8 FB68 ldr r3, [r7, #12] + 1456 00aa 7A88 ldrh r2, [r7, #2] @ movhi + 1457 00ac A3F84620 strh r2, [r3, #70] @ movhi +1318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferSize = Size; + 1458 .loc 1 1318 21 + 1459 00b0 FB68 ldr r3, [r7, #12] + 1460 00b2 7A88 ldrh r2, [r7, #2] @ movhi + 1461 00b4 A3F84420 strh r2, [r3, #68] @ movhi +1319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr = (uint8_t *)pTxData; + 1462 .loc 1 1319 21 + 1463 00b8 FB68 ldr r3, [r7, #12] + 1464 00ba BA68 ldr r2, [r7, #8] + 1465 00bc 9A63 str r2, [r3, #56] +1320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = Size; + 1466 .loc 1 1320 21 + 1467 00be FB68 ldr r3, [r7, #12] + 1468 00c0 7A88 ldrh r2, [r7, #2] @ movhi + 1469 00c2 DA87 strh r2, [r3, #62] @ movhi +1321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferSize = Size; + 1470 .loc 1 1321 21 + 1471 00c4 FB68 ldr r3, [r7, #12] + 1472 00c6 7A88 ldrh r2, [r7, #2] @ movhi + 1473 00c8 9A87 strh r2, [r3, #60] @ movhi +1322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /*Init field not used in handle to zero */ +1324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxISR = NULL; + 1474 .loc 1 1324 21 + ARM GAS /tmp/ccs34gJO.s page 50 + + + 1475 00ca FB68 ldr r3, [r7, #12] + 1476 00cc 0022 movs r2, #0 + 1477 00ce DA64 str r2, [r3, #76] +1325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxISR = NULL; + 1478 .loc 1 1325 21 + 1479 00d0 FB68 ldr r3, [r7, #12] + 1480 00d2 0022 movs r2, #0 + 1481 00d4 1A65 str r2, [r3, #80] +1326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +1328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset CRC Calculation */ +1329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +1330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_RESET_CRC(hspi); +1332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +1334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the Rx Fifo threshold */ +1336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (initial_RxXferCount > 1U)) + 1482 .loc 1 1336 18 + 1483 00d6 FB68 ldr r3, [r7, #12] + 1484 00d8 DB68 ldr r3, [r3, #12] + 1485 .loc 1 1336 6 + 1486 00da B3F5E06F cmp r3, #1792 + 1487 00de 02D8 bhi .L84 + 1488 .loc 1 1336 49 discriminator 1 + 1489 00e0 3B8A ldrh r3, [r7, #16] + 1490 00e2 012B cmp r3, #1 + 1491 00e4 08D9 bls .L85 + 1492 .L84: +1337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set fiforxthreshold according the reception data length: 16bit */ +1339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + 1493 .loc 1 1339 5 + 1494 00e6 FB68 ldr r3, [r7, #12] + 1495 00e8 1B68 ldr r3, [r3] + 1496 00ea 5A68 ldr r2, [r3, #4] + 1497 00ec FB68 ldr r3, [r7, #12] + 1498 00ee 1B68 ldr r3, [r3] + 1499 00f0 22F48052 bic r2, r2, #4096 + 1500 00f4 5A60 str r2, [r3, #4] + 1501 00f6 07E0 b .L86 + 1502 .L85: +1340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +1342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set fiforxthreshold according the reception data length: 8bit */ +1344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + 1503 .loc 1 1344 5 + 1504 00f8 FB68 ldr r3, [r7, #12] + 1505 00fa 1B68 ldr r3, [r3] + 1506 00fc 5A68 ldr r2, [r3, #4] + 1507 00fe FB68 ldr r3, [r7, #12] + 1508 0100 1B68 ldr r3, [r3] + 1509 0102 42F48052 orr r2, r2, #4096 + 1510 0106 5A60 str r2, [r3, #4] + 1511 .L86: + ARM GAS /tmp/ccs34gJO.s page 51 + + +1345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check if the SPI is already enabled */ +1348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + 1512 .loc 1 1348 12 + 1513 0108 FB68 ldr r3, [r7, #12] + 1514 010a 1B68 ldr r3, [r3] + 1515 .loc 1 1348 22 + 1516 010c 1B68 ldr r3, [r3] + 1517 .loc 1 1348 28 + 1518 010e 03F04003 and r3, r3, #64 + 1519 .loc 1 1348 6 + 1520 0112 402B cmp r3, #64 + 1521 0114 07D0 beq .L87 +1349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable SPI peripheral */ +1351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_ENABLE(hspi); + 1522 .loc 1 1351 5 + 1523 0116 FB68 ldr r3, [r7, #12] + 1524 0118 1B68 ldr r3, [r3] + 1525 011a 1A68 ldr r2, [r3] + 1526 011c FB68 ldr r3, [r7, #12] + 1527 011e 1B68 ldr r3, [r3] + 1528 0120 42F04002 orr r2, r2, #64 + 1529 0124 1A60 str r2, [r3] + 1530 .L87: +1352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Transmit and Receive data in 16 Bit mode */ +1355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + 1531 .loc 1 1355 17 + 1532 0126 FB68 ldr r3, [r7, #12] + 1533 0128 DB68 ldr r3, [r3, #12] + 1534 .loc 1 1355 6 + 1535 012a B3F5E06F cmp r3, #1792 + 1536 012e 40F28180 bls .L88 +1356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + 1537 .loc 1 1357 20 + 1538 0132 FB68 ldr r3, [r7, #12] + 1539 0134 5B68 ldr r3, [r3, #4] + 1540 .loc 1 1357 8 + 1541 0136 002B cmp r3, #0 + 1542 0138 02D0 beq .L89 + 1543 .loc 1 1357 45 discriminator 1 + 1544 013a 7B8A ldrh r3, [r7, #18] + 1545 013c 012B cmp r3, #1 + 1546 013e 6DD1 bne .L91 + 1547 .L89: +1358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + 1548 .loc 1 1359 46 + 1549 0140 FB68 ldr r3, [r7, #12] + 1550 0142 9B6B ldr r3, [r3, #56] + 1551 .loc 1 1359 28 + 1552 0144 1A88 ldrh r2, [r3] + 1553 .loc 1 1359 11 + ARM GAS /tmp/ccs34gJO.s page 52 + + + 1554 0146 FB68 ldr r3, [r7, #12] + 1555 0148 1B68 ldr r3, [r3] + 1556 .loc 1 1359 26 + 1557 014a DA60 str r2, [r3, #12] +1360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 1558 .loc 1 1360 11 + 1559 014c FB68 ldr r3, [r7, #12] + 1560 014e 9B6B ldr r3, [r3, #56] + 1561 .loc 1 1360 24 + 1562 0150 9A1C adds r2, r3, #2 + 1563 0152 FB68 ldr r3, [r7, #12] + 1564 0154 9A63 str r2, [r3, #56] +1361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 1565 .loc 1 1361 11 + 1566 0156 FB68 ldr r3, [r7, #12] + 1567 0158 DB8F ldrh r3, [r3, #62] @ movhi + 1568 015a 9BB2 uxth r3, r3 + 1569 .loc 1 1361 24 + 1570 015c 013B subs r3, r3, #1 + 1571 015e 9AB2 uxth r2, r3 + 1572 0160 FB68 ldr r3, [r7, #12] + 1573 0162 DA87 strh r2, [r3, #62] @ movhi +1362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) + 1574 .loc 1 1363 11 + 1575 0164 5AE0 b .L91 + 1576 .L95: +1364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check TXE flag */ +1366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U) + 1577 .loc 1 1366 12 + 1578 0166 FB68 ldr r3, [r7, #12] + 1579 0168 1B68 ldr r3, [r3] + 1580 016a 9B68 ldr r3, [r3, #8] + 1581 016c 03F00203 and r3, r3, #2 + 1582 .loc 1 1366 10 + 1583 0170 022B cmp r3, #2 + 1584 0172 1BD1 bne .L92 + 1585 .loc 1 1366 60 discriminator 1 + 1586 0174 FB68 ldr r3, [r7, #12] + 1587 0176 DB8F ldrh r3, [r3, #62] @ movhi + 1588 0178 9BB2 uxth r3, r3 + 1589 .loc 1 1366 52 discriminator 1 + 1590 017a 002B cmp r3, #0 + 1591 017c 16D0 beq .L92 + 1592 .loc 1 1366 80 discriminator 2 + 1593 017e 7B6A ldr r3, [r7, #36] + 1594 0180 012B cmp r3, #1 + 1595 0182 13D1 bne .L92 +1367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + 1596 .loc 1 1368 48 + 1597 0184 FB68 ldr r3, [r7, #12] + 1598 0186 9B6B ldr r3, [r3, #56] + 1599 .loc 1 1368 30 + 1600 0188 1A88 ldrh r2, [r3] + 1601 .loc 1 1368 13 + ARM GAS /tmp/ccs34gJO.s page 53 + + + 1602 018a FB68 ldr r3, [r7, #12] + 1603 018c 1B68 ldr r3, [r3] + 1604 .loc 1 1368 28 + 1605 018e DA60 str r2, [r3, #12] +1369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 1606 .loc 1 1369 13 + 1607 0190 FB68 ldr r3, [r7, #12] + 1608 0192 9B6B ldr r3, [r3, #56] + 1609 .loc 1 1369 26 + 1610 0194 9A1C adds r2, r3, #2 + 1611 0196 FB68 ldr r3, [r7, #12] + 1612 0198 9A63 str r2, [r3, #56] +1370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 1613 .loc 1 1370 13 + 1614 019a FB68 ldr r3, [r7, #12] + 1615 019c DB8F ldrh r3, [r3, #62] @ movhi + 1616 019e 9BB2 uxth r3, r3 + 1617 .loc 1 1370 26 + 1618 01a0 013B subs r3, r3, #1 + 1619 01a2 9AB2 uxth r2, r3 + 1620 01a4 FB68 ldr r3, [r7, #12] + 1621 01a6 DA87 strh r2, [r3, #62] @ movhi +1371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Next Data is a reception (Rx). Tx not allowed */ +1372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** txallowed = 0U; + 1622 .loc 1 1372 19 + 1623 01a8 0023 movs r3, #0 + 1624 01aa 7B62 str r3, [r7, #36] + 1625 .L92: +1373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +1375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable CRC Transmission */ +1376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) +1377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */ +1379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR +1380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM); +1382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); +1384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +1386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check RXNE flag */ +1389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U)) + 1626 .loc 1 1389 12 + 1627 01ac FB68 ldr r3, [r7, #12] + 1628 01ae 1B68 ldr r3, [r3] + 1629 01b0 9B68 ldr r3, [r3, #8] + 1630 01b2 03F00103 and r3, r3, #1 + 1631 .loc 1 1389 10 + 1632 01b6 012B cmp r3, #1 + 1633 01b8 1CD1 bne .L93 + 1634 .loc 1 1389 61 discriminator 1 + 1635 01ba FB68 ldr r3, [r7, #12] + 1636 01bc B3F84630 ldrh r3, [r3, #70] @ movhi + 1637 01c0 9BB2 uxth r3, r3 + ARM GAS /tmp/ccs34gJO.s page 54 + + + 1638 .loc 1 1389 53 discriminator 1 + 1639 01c2 002B cmp r3, #0 + 1640 01c4 16D0 beq .L93 +1390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; + 1641 .loc 1 1391 57 + 1642 01c6 FB68 ldr r3, [r7, #12] + 1643 01c8 1B68 ldr r3, [r3] + 1644 .loc 1 1391 67 + 1645 01ca DA68 ldr r2, [r3, #12] + 1646 .loc 1 1391 27 + 1647 01cc FB68 ldr r3, [r7, #12] + 1648 01ce 1B6C ldr r3, [r3, #64] + 1649 .loc 1 1391 43 + 1650 01d0 92B2 uxth r2, r2 + 1651 .loc 1 1391 41 + 1652 01d2 1A80 strh r2, [r3] @ movhi +1392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr += sizeof(uint16_t); + 1653 .loc 1 1392 13 + 1654 01d4 FB68 ldr r3, [r7, #12] + 1655 01d6 1B6C ldr r3, [r3, #64] + 1656 .loc 1 1392 26 + 1657 01d8 9A1C adds r2, r3, #2 + 1658 01da FB68 ldr r3, [r7, #12] + 1659 01dc 1A64 str r2, [r3, #64] +1393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount--; + 1660 .loc 1 1393 13 + 1661 01de FB68 ldr r3, [r7, #12] + 1662 01e0 B3F84630 ldrh r3, [r3, #70] @ movhi + 1663 01e4 9BB2 uxth r3, r3 + 1664 .loc 1 1393 26 + 1665 01e6 013B subs r3, r3, #1 + 1666 01e8 9AB2 uxth r2, r3 + 1667 01ea FB68 ldr r3, [r7, #12] + 1668 01ec A3F84620 strh r2, [r3, #70] @ movhi +1394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Next Data is a Transmission (Tx). Tx is allowed */ +1395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** txallowed = 1U; + 1669 .loc 1 1395 19 + 1670 01f0 0123 movs r3, #1 + 1671 01f2 7B62 str r3, [r7, #36] + 1672 .L93: +1396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) + 1673 .loc 1 1397 13 + 1674 01f4 FFF7FEFF bl HAL_GetTick + 1675 01f8 0246 mov r2, r0 + 1676 .loc 1 1397 27 discriminator 1 + 1677 01fa FB69 ldr r3, [r7, #28] + 1678 01fc D31A subs r3, r2, r3 + 1679 .loc 1 1397 10 discriminator 1 + 1680 01fe 3A6B ldr r2, [r7, #48] + 1681 0200 9A42 cmp r2, r3 + 1682 0202 0BD8 bhi .L91 + 1683 .loc 1 1397 53 discriminator 1 + 1684 0204 3B6B ldr r3, [r7, #48] + 1685 0206 B3F1FF3F cmp r3, #-1 + 1686 020a 07D0 beq .L91 + ARM GAS /tmp/ccs34gJO.s page 55 + + +1398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_TIMEOUT; + 1687 .loc 1 1399 19 + 1688 020c 0323 movs r3, #3 + 1689 020e 87F82330 strb r3, [r7, #35] +1400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; + 1690 .loc 1 1400 21 + 1691 0212 FB68 ldr r3, [r7, #12] + 1692 0214 0122 movs r2, #1 + 1693 0216 83F85D20 strb r2, [r3, #93] +1401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 1694 .loc 1 1401 9 + 1695 021a 09E1 b .L80 + 1696 .L91: +1363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1697 .loc 1 1363 17 + 1698 021c FB68 ldr r3, [r7, #12] + 1699 021e DB8F ldrh r3, [r3, #62] @ movhi + 1700 0220 9BB2 uxth r3, r3 +1363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1701 .loc 1 1363 37 + 1702 0222 002B cmp r3, #0 + 1703 0224 9FD1 bne .L95 +1363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1704 .loc 1 1363 45 discriminator 1 + 1705 0226 FB68 ldr r3, [r7, #12] + 1706 0228 B3F84630 ldrh r3, [r3, #70] @ movhi + 1707 022c 9BB2 uxth r3, r3 +1363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 1708 .loc 1 1363 37 discriminator 1 + 1709 022e 002B cmp r3, #0 + 1710 0230 99D1 bne .L95 + 1711 0232 E3E0 b .L96 + 1712 .L88: +1402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Transmit and Receive data in 8 Bit mode */ +1406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +1407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + 1713 .loc 1 1408 20 + 1714 0234 FB68 ldr r3, [r7, #12] + 1715 0236 5B68 ldr r3, [r3, #4] + 1716 .loc 1 1408 8 + 1717 0238 002B cmp r3, #0 + 1718 023a 03D0 beq .L97 + 1719 .loc 1 1408 45 discriminator 1 + 1720 023c 7B8A ldrh r3, [r7, #18] + 1721 023e 012B cmp r3, #1 + 1722 0240 40F0CF80 bne .L100 + 1723 .L97: +1409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->TxXferCount > 1U) + 1724 .loc 1 1410 15 + 1725 0244 FB68 ldr r3, [r7, #12] + 1726 0246 DB8F ldrh r3, [r3, #62] @ movhi + ARM GAS /tmp/ccs34gJO.s page 56 + + + 1727 0248 9BB2 uxth r3, r3 + 1728 .loc 1 1410 10 + 1729 024a 012B cmp r3, #1 + 1730 024c 12D9 bls .L99 +1411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + 1731 .loc 1 1412 48 + 1732 024e FB68 ldr r3, [r7, #12] + 1733 0250 9B6B ldr r3, [r3, #56] + 1734 .loc 1 1412 30 + 1735 0252 1A88 ldrh r2, [r3] + 1736 .loc 1 1412 13 + 1737 0254 FB68 ldr r3, [r7, #12] + 1738 0256 1B68 ldr r3, [r3] + 1739 .loc 1 1412 28 + 1740 0258 DA60 str r2, [r3, #12] +1413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 1741 .loc 1 1413 13 + 1742 025a FB68 ldr r3, [r7, #12] + 1743 025c 9B6B ldr r3, [r3, #56] + 1744 .loc 1 1413 26 + 1745 025e 9A1C adds r2, r3, #2 + 1746 0260 FB68 ldr r3, [r7, #12] + 1747 0262 9A63 str r2, [r3, #56] +1414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount -= 2U; + 1748 .loc 1 1414 13 + 1749 0264 FB68 ldr r3, [r7, #12] + 1750 0266 DB8F ldrh r3, [r3, #62] @ movhi + 1751 0268 9BB2 uxth r3, r3 + 1752 .loc 1 1414 27 + 1753 026a 023B subs r3, r3, #2 + 1754 026c 9AB2 uxth r2, r3 + 1755 026e FB68 ldr r3, [r7, #12] + 1756 0270 DA87 strh r2, [r3, #62] @ movhi + 1757 0272 B6E0 b .L100 + 1758 .L99: +1415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +1417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + 1759 .loc 1 1418 54 + 1760 0274 FB68 ldr r3, [r7, #12] + 1761 0276 9A6B ldr r2, [r3, #56] + 1762 .loc 1 1418 31 + 1763 0278 FB68 ldr r3, [r7, #12] + 1764 027a 1B68 ldr r3, [r3] + 1765 .loc 1 1418 26 + 1766 027c 0C33 adds r3, r3, #12 + 1767 .loc 1 1418 49 + 1768 027e 1278 ldrb r2, [r2] @ zero_extendqisi2 + 1769 .loc 1 1418 46 + 1770 0280 1A70 strb r2, [r3] +1419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr++; + 1771 .loc 1 1419 13 + 1772 0282 FB68 ldr r3, [r7, #12] + 1773 0284 9B6B ldr r3, [r3, #56] + 1774 .loc 1 1419 25 + ARM GAS /tmp/ccs34gJO.s page 57 + + + 1775 0286 5A1C adds r2, r3, #1 + 1776 0288 FB68 ldr r3, [r7, #12] + 1777 028a 9A63 str r2, [r3, #56] +1420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 1778 .loc 1 1420 13 + 1779 028c FB68 ldr r3, [r7, #12] + 1780 028e DB8F ldrh r3, [r3, #62] @ movhi + 1781 0290 9BB2 uxth r3, r3 + 1782 .loc 1 1420 26 + 1783 0292 013B subs r3, r3, #1 + 1784 0294 9AB2 uxth r2, r3 + 1785 0296 FB68 ldr r3, [r7, #12] + 1786 0298 DA87 strh r2, [r3, #62] @ movhi +1421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) + 1787 .loc 1 1423 11 + 1788 029a A2E0 b .L100 + 1789 .L109: +1424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check TXE flag */ +1426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U) + 1790 .loc 1 1426 12 + 1791 029c FB68 ldr r3, [r7, #12] + 1792 029e 1B68 ldr r3, [r3] + 1793 02a0 9B68 ldr r3, [r3, #8] + 1794 02a2 03F00203 and r3, r3, #2 + 1795 .loc 1 1426 10 + 1796 02a6 022B cmp r3, #2 + 1797 02a8 34D1 bne .L101 + 1798 .loc 1 1426 60 discriminator 1 + 1799 02aa FB68 ldr r3, [r7, #12] + 1800 02ac DB8F ldrh r3, [r3, #62] @ movhi + 1801 02ae 9BB2 uxth r3, r3 + 1802 .loc 1 1426 52 discriminator 1 + 1803 02b0 002B cmp r3, #0 + 1804 02b2 2FD0 beq .L101 + 1805 .loc 1 1426 80 discriminator 2 + 1806 02b4 7B6A ldr r3, [r7, #36] + 1807 02b6 012B cmp r3, #1 + 1808 02b8 2CD1 bne .L101 +1427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->TxXferCount > 1U) + 1809 .loc 1 1428 17 + 1810 02ba FB68 ldr r3, [r7, #12] + 1811 02bc DB8F ldrh r3, [r3, #62] @ movhi + 1812 02be 9BB2 uxth r3, r3 + 1813 .loc 1 1428 12 + 1814 02c0 012B cmp r3, #1 + 1815 02c2 12D9 bls .L102 +1429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + 1816 .loc 1 1430 50 + 1817 02c4 FB68 ldr r3, [r7, #12] + 1818 02c6 9B6B ldr r3, [r3, #56] + 1819 .loc 1 1430 32 + 1820 02c8 1A88 ldrh r2, [r3] + ARM GAS /tmp/ccs34gJO.s page 58 + + + 1821 .loc 1 1430 15 + 1822 02ca FB68 ldr r3, [r7, #12] + 1823 02cc 1B68 ldr r3, [r3] + 1824 .loc 1 1430 30 + 1825 02ce DA60 str r2, [r3, #12] +1431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 1826 .loc 1 1431 15 + 1827 02d0 FB68 ldr r3, [r7, #12] + 1828 02d2 9B6B ldr r3, [r3, #56] + 1829 .loc 1 1431 28 + 1830 02d4 9A1C adds r2, r3, #2 + 1831 02d6 FB68 ldr r3, [r7, #12] + 1832 02d8 9A63 str r2, [r3, #56] +1432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount -= 2U; + 1833 .loc 1 1432 15 + 1834 02da FB68 ldr r3, [r7, #12] + 1835 02dc DB8F ldrh r3, [r3, #62] @ movhi + 1836 02de 9BB2 uxth r3, r3 + 1837 .loc 1 1432 29 + 1838 02e0 023B subs r3, r3, #2 + 1839 02e2 9AB2 uxth r2, r3 + 1840 02e4 FB68 ldr r3, [r7, #12] + 1841 02e6 DA87 strh r2, [r3, #62] @ movhi + 1842 02e8 12E0 b .L103 + 1843 .L102: +1433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +1435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + 1844 .loc 1 1436 56 + 1845 02ea FB68 ldr r3, [r7, #12] + 1846 02ec 9A6B ldr r2, [r3, #56] + 1847 .loc 1 1436 33 + 1848 02ee FB68 ldr r3, [r7, #12] + 1849 02f0 1B68 ldr r3, [r3] + 1850 .loc 1 1436 28 + 1851 02f2 0C33 adds r3, r3, #12 + 1852 .loc 1 1436 51 + 1853 02f4 1278 ldrb r2, [r2] @ zero_extendqisi2 + 1854 .loc 1 1436 48 + 1855 02f6 1A70 strb r2, [r3] +1437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr++; + 1856 .loc 1 1437 15 + 1857 02f8 FB68 ldr r3, [r7, #12] + 1858 02fa 9B6B ldr r3, [r3, #56] + 1859 .loc 1 1437 27 + 1860 02fc 5A1C adds r2, r3, #1 + 1861 02fe FB68 ldr r3, [r7, #12] + 1862 0300 9A63 str r2, [r3, #56] +1438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 1863 .loc 1 1438 15 + 1864 0302 FB68 ldr r3, [r7, #12] + 1865 0304 DB8F ldrh r3, [r3, #62] @ movhi + 1866 0306 9BB2 uxth r3, r3 + 1867 .loc 1 1438 28 + 1868 0308 013B subs r3, r3, #1 + 1869 030a 9AB2 uxth r2, r3 + ARM GAS /tmp/ccs34gJO.s page 59 + + + 1870 030c FB68 ldr r3, [r7, #12] + 1871 030e DA87 strh r2, [r3, #62] @ movhi + 1872 .L103: +1439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Next Data is a reception (Rx). Tx not allowed */ +1441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** txallowed = 0U; + 1873 .loc 1 1441 19 + 1874 0310 0023 movs r3, #0 + 1875 0312 7B62 str r3, [r7, #36] + 1876 .L101: +1442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +1444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable CRC Transmission */ +1445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) +1446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */ +1448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR +1449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM); +1451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); +1453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +1455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Wait until RXNE flag is reset */ +1458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U)) + 1877 .loc 1 1458 12 + 1878 0314 FB68 ldr r3, [r7, #12] + 1879 0316 1B68 ldr r3, [r3] + 1880 0318 9B68 ldr r3, [r3, #8] + 1881 031a 03F00103 and r3, r3, #1 + 1882 .loc 1 1458 10 + 1883 031e 012B cmp r3, #1 + 1884 0320 48D1 bne .L104 + 1885 .loc 1 1458 61 discriminator 1 + 1886 0322 FB68 ldr r3, [r7, #12] + 1887 0324 B3F84630 ldrh r3, [r3, #70] @ movhi + 1888 0328 9BB2 uxth r3, r3 + 1889 .loc 1 1458 53 discriminator 1 + 1890 032a 002B cmp r3, #0 + 1891 032c 42D0 beq .L104 +1459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->RxXferCount > 1U) + 1892 .loc 1 1460 17 + 1893 032e FB68 ldr r3, [r7, #12] + 1894 0330 B3F84630 ldrh r3, [r3, #70] @ movhi + 1895 0334 9BB2 uxth r3, r3 + 1896 .loc 1 1460 12 + 1897 0336 012B cmp r3, #1 + 1898 0338 23D9 bls .L105 +1461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; + 1899 .loc 1 1462 59 + 1900 033a FB68 ldr r3, [r7, #12] + 1901 033c 1B68 ldr r3, [r3] + 1902 .loc 1 1462 69 + ARM GAS /tmp/ccs34gJO.s page 60 + + + 1903 033e DA68 ldr r2, [r3, #12] + 1904 .loc 1 1462 29 + 1905 0340 FB68 ldr r3, [r7, #12] + 1906 0342 1B6C ldr r3, [r3, #64] + 1907 .loc 1 1462 45 + 1908 0344 92B2 uxth r2, r2 + 1909 .loc 1 1462 43 + 1910 0346 1A80 strh r2, [r3] @ movhi +1463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr += sizeof(uint16_t); + 1911 .loc 1 1463 15 + 1912 0348 FB68 ldr r3, [r7, #12] + 1913 034a 1B6C ldr r3, [r3, #64] + 1914 .loc 1 1463 28 + 1915 034c 9A1C adds r2, r3, #2 + 1916 034e FB68 ldr r3, [r7, #12] + 1917 0350 1A64 str r2, [r3, #64] +1464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount -= 2U; + 1918 .loc 1 1464 15 + 1919 0352 FB68 ldr r3, [r7, #12] + 1920 0354 B3F84630 ldrh r3, [r3, #70] @ movhi + 1921 0358 9BB2 uxth r3, r3 + 1922 .loc 1 1464 29 + 1923 035a 023B subs r3, r3, #2 + 1924 035c 9AB2 uxth r2, r3 + 1925 035e FB68 ldr r3, [r7, #12] + 1926 0360 A3F84620 strh r2, [r3, #70] @ movhi +1465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->RxXferCount <= 1U) + 1927 .loc 1 1465 19 + 1928 0364 FB68 ldr r3, [r7, #12] + 1929 0366 B3F84630 ldrh r3, [r3, #70] @ movhi + 1930 036a 9BB2 uxth r3, r3 + 1931 .loc 1 1465 14 + 1932 036c 012B cmp r3, #1 + 1933 036e 1FD8 bhi .L106 +1466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set RX Fifo threshold before to switch on 8 bit data size */ +1468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + 1934 .loc 1 1468 13 + 1935 0370 FB68 ldr r3, [r7, #12] + 1936 0372 1B68 ldr r3, [r3] + 1937 0374 5A68 ldr r2, [r3, #4] + 1938 0376 FB68 ldr r3, [r7, #12] + 1939 0378 1B68 ldr r3, [r3] + 1940 037a 42F48052 orr r2, r2, #4096 + 1941 037e 5A60 str r2, [r3, #4] + 1942 0380 16E0 b .L106 + 1943 .L105: +1469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +1472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR; + 1944 .loc 1 1473 66 + 1945 0382 FB68 ldr r3, [r7, #12] + 1946 0384 1B68 ldr r3, [r3] + 1947 .loc 1 1473 61 + 1948 0386 03F10C02 add r2, r3, #12 + ARM GAS /tmp/ccs34gJO.s page 61 + + + 1949 .loc 1 1473 28 + 1950 038a FB68 ldr r3, [r7, #12] + 1951 038c 1B6C ldr r3, [r3, #64] + 1952 .loc 1 1473 44 + 1953 038e 1278 ldrb r2, [r2] + 1954 0390 D2B2 uxtb r2, r2 + 1955 .loc 1 1473 42 + 1956 0392 1A70 strb r2, [r3] +1474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr++; + 1957 .loc 1 1474 15 + 1958 0394 FB68 ldr r3, [r7, #12] + 1959 0396 1B6C ldr r3, [r3, #64] + 1960 .loc 1 1474 27 + 1961 0398 5A1C adds r2, r3, #1 + 1962 039a FB68 ldr r3, [r7, #12] + 1963 039c 1A64 str r2, [r3, #64] +1475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount--; + 1964 .loc 1 1475 15 + 1965 039e FB68 ldr r3, [r7, #12] + 1966 03a0 B3F84630 ldrh r3, [r3, #70] @ movhi + 1967 03a4 9BB2 uxth r3, r3 + 1968 .loc 1 1475 28 + 1969 03a6 013B subs r3, r3, #1 + 1970 03a8 9AB2 uxth r2, r3 + 1971 03aa FB68 ldr r3, [r7, #12] + 1972 03ac A3F84620 strh r2, [r3, #70] @ movhi + 1973 .L106: +1476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Next Data is a Transmission (Tx). Tx is allowed */ +1478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** txallowed = 1U; + 1974 .loc 1 1478 19 + 1975 03b0 0123 movs r3, #1 + 1976 03b2 7B62 str r3, [r7, #36] + 1977 .L104: +1479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout = + 1978 .loc 1 1480 14 + 1979 03b4 FFF7FEFF bl HAL_GetTick + 1980 03b8 0246 mov r2, r0 + 1981 .loc 1 1480 28 discriminator 1 + 1982 03ba FB69 ldr r3, [r7, #28] + 1983 03bc D31A subs r3, r2, r3 + 1984 .loc 1 1480 10 discriminator 1 + 1985 03be 3A6B ldr r2, [r7, #48] + 1986 03c0 9A42 cmp r2, r3 + 1987 03c2 03D8 bhi .L107 + 1988 .loc 1 1480 54 discriminator 1 + 1989 03c4 3B6B ldr r3, [r7, #48] + 1990 03c6 B3F1FF3F cmp r3, #-1 + 1991 03ca 02D1 bne .L108 + 1992 .L107: + 1993 .loc 1 1480 87 discriminator 3 + 1994 03cc 3B6B ldr r3, [r7, #48] + 1995 03ce 002B cmp r3, #0 + 1996 03d0 07D1 bne .L100 + 1997 .L108: +1481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + ARM GAS /tmp/ccs34gJO.s page 62 + + +1482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_TIMEOUT; + 1998 .loc 1 1482 19 + 1999 03d2 0323 movs r3, #3 + 2000 03d4 87F82330 strb r3, [r7, #35] +1483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; + 2001 .loc 1 1483 21 + 2002 03d8 FB68 ldr r3, [r7, #12] + 2003 03da 0122 movs r2, #1 + 2004 03dc 83F85D20 strb r2, [r3, #93] +1484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 2005 .loc 1 1484 9 + 2006 03e0 26E0 b .L80 + 2007 .L100: +1423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2008 .loc 1 1423 17 + 2009 03e2 FB68 ldr r3, [r7, #12] + 2010 03e4 DB8F ldrh r3, [r3, #62] @ movhi + 2011 03e6 9BB2 uxth r3, r3 +1423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2012 .loc 1 1423 37 + 2013 03e8 002B cmp r3, #0 + 2014 03ea 7FF457AF bne .L109 +1423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2015 .loc 1 1423 45 discriminator 1 + 2016 03ee FB68 ldr r3, [r7, #12] + 2017 03f0 B3F84630 ldrh r3, [r3, #70] @ movhi + 2018 03f4 9BB2 uxth r3, r3 +1423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2019 .loc 1 1423 37 discriminator 1 + 2020 03f6 002B cmp r3, #0 + 2021 03f8 7FF450AF bne .L109 + 2022 .L96: +1485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +1490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Read CRC from DR to close CRC calculation process */ +1491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +1492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Wait until TXE flag */ +1494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) +1495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Error on the CRC reception */ +1497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); +1498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_TIMEOUT; +1499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; +1500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Read CRC */ +1502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) +1503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Read 16bit CRC */ +1505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmpreg = READ_REG(hspi->Instance->DR); +1506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* To avoid GCC warning */ +1507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(tmpreg); +1508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else + ARM GAS /tmp/ccs34gJO.s page 63 + + +1510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Initialize the 8bit temporary pointer */ +1512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; +1513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Read 8bit CRC */ +1514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmpreg8 = *ptmpreg8; +1515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* To avoid GCC warning */ +1516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(tmpreg8); +1517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) +1519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) +1521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Error on the CRC reception */ +1523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); +1524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_TIMEOUT; +1525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; +1526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ +1528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmpreg8 = *ptmpreg8; +1529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* To avoid GCC warning */ +1530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(tmpreg8); +1531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check if CRC error occurred */ +1536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) +1537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); +1539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Clear CRC Flag */ +1540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_CRCERRFLAG(hspi); +1541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; +1543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +1545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check the end of the transaction */ +1547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) + 2023 .loc 1 1547 7 + 2024 03fc FA69 ldr r2, [r7, #28] + 2025 03fe 396B ldr r1, [r7, #48] + 2026 0400 F868 ldr r0, [r7, #12] + 2027 0402 FFF7FEFF bl SPI_EndRxTxTransaction + 2028 0406 0346 mov r3, r0 + 2029 .loc 1 1547 6 discriminator 1 + 2030 0408 002B cmp r3, #0 + 2031 040a 05D0 beq .L110 +1548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; + 2032 .loc 1 1549 15 + 2033 040c 0123 movs r3, #1 + 2034 040e 87F82330 strb r3, [r7, #35] +1550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + 2035 .loc 1 1550 21 + 2036 0412 FB68 ldr r3, [r7, #12] + 2037 0414 2022 movs r2, #32 + 2038 0416 1A66 str r2, [r3, #96] + ARM GAS /tmp/ccs34gJO.s page 64 + + + 2039 .L110: +1551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + 2040 .loc 1 1553 11 + 2041 0418 FB68 ldr r3, [r7, #12] + 2042 041a 1B6E ldr r3, [r3, #96] + 2043 .loc 1 1553 6 + 2044 041c 002B cmp r3, #0 + 2045 041e 03D0 beq .L111 +1554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; + 2046 .loc 1 1555 15 + 2047 0420 0123 movs r3, #1 + 2048 0422 87F82330 strb r3, [r7, #35] + 2049 0426 03E0 b .L80 + 2050 .L111: +1556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +1558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; + 2051 .loc 1 1559 17 + 2052 0428 FB68 ldr r3, [r7, #12] + 2053 042a 0122 movs r2, #1 + 2054 042c 83F85D20 strb r2, [r3, #93] + 2055 .L80: +1560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** error : +1563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_UNLOCK(hspi); + 2056 .loc 1 1563 3 + 2057 0430 FB68 ldr r3, [r7, #12] + 2058 0432 0022 movs r2, #0 + 2059 0434 83F85C20 strb r2, [r3, #92] +1564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; + 2060 .loc 1 1564 10 + 2061 0438 97F82330 ldrb r3, [r7, #35] @ zero_extendqisi2 + 2062 .L77: +1565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2063 .loc 1 1565 1 + 2064 043c 1846 mov r0, r3 + 2065 043e 2837 adds r7, r7, #40 + 2066 .cfi_def_cfa_offset 8 + 2067 0440 BD46 mov sp, r7 + 2068 .cfi_def_cfa_register 13 + 2069 @ sp needed + 2070 0442 80BD pop {r7, pc} + 2071 .cfi_endproc + 2072 .LFE136: + 2074 .section .text.HAL_SPI_Transmit_IT,"ax",%progbits + 2075 .align 1 + 2076 .global HAL_SPI_Transmit_IT + 2077 .syntax unified + 2078 .thumb + 2079 .thumb_func + 2081 HAL_SPI_Transmit_IT: + 2082 .LFB137: + ARM GAS /tmp/ccs34gJO.s page 65 + + +1566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +1568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Transmit an amount of data in non-blocking mode with Interrupt. +1569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +1570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +1571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param pData pointer to data buffer +1572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param Size amount of data to be sent +1573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval HAL status +1574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +1575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +1576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2083 .loc 1 1576 1 + 2084 .cfi_startproc + 2085 @ args = 0, pretend = 0, frame = 24 + 2086 @ frame_needed = 1, uses_anonymous_args = 0 + 2087 @ link register save eliminated. + 2088 0000 80B4 push {r7} + 2089 .cfi_def_cfa_offset 4 + 2090 .cfi_offset 7, -4 + 2091 0002 87B0 sub sp, sp, #28 + 2092 .cfi_def_cfa_offset 32 + 2093 0004 00AF add r7, sp, #0 + 2094 .cfi_def_cfa_register 7 + 2095 0006 F860 str r0, [r7, #12] + 2096 0008 B960 str r1, [r7, #8] + 2097 000a 1346 mov r3, r2 + 2098 000c FB80 strh r3, [r7, #6] @ movhi +1577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef errorcode = HAL_OK; + 2099 .loc 1 1577 21 + 2100 000e 0023 movs r3, #0 + 2101 0010 FB75 strb r3, [r7, #23] +1578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check Direction parameter */ +1580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); +1581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Process Locked */ +1583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_LOCK(hspi); + 2102 .loc 1 1583 3 + 2103 0012 FB68 ldr r3, [r7, #12] + 2104 0014 93F85C30 ldrb r3, [r3, #92] @ zero_extendqisi2 + 2105 0018 012B cmp r3, #1 + 2106 001a 01D1 bne .L113 + 2107 .loc 1 1583 3 is_stmt 0 discriminator 1 + 2108 001c 0223 movs r3, #2 + 2109 .loc 1 1583 3 + 2110 001e 72E0 b .L114 + 2111 .L113: + 2112 .loc 1 1583 3 discriminator 2 + 2113 0020 FB68 ldr r3, [r7, #12] + 2114 0022 0122 movs r2, #1 + 2115 0024 83F85C20 strb r2, [r3, #92] +1584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((pData == NULL) || (Size == 0U)) + 2116 .loc 1 1585 6 is_stmt 1 + 2117 0028 BB68 ldr r3, [r7, #8] + 2118 002a 002B cmp r3, #0 + 2119 002c 02D0 beq .L115 + ARM GAS /tmp/ccs34gJO.s page 66 + + + 2120 .loc 1 1585 23 discriminator 1 + 2121 002e FB88 ldrh r3, [r7, #6] + 2122 0030 002B cmp r3, #0 + 2123 0032 02D1 bne .L116 + 2124 .L115: +1586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; + 2125 .loc 1 1587 15 + 2126 0034 0123 movs r3, #1 + 2127 0036 FB75 strb r3, [r7, #23] +1588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 2128 .loc 1 1588 5 + 2129 0038 60E0 b .L117 + 2130 .L116: +1589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->State != HAL_SPI_STATE_READY) + 2131 .loc 1 1591 11 + 2132 003a FB68 ldr r3, [r7, #12] + 2133 003c 93F85D30 ldrb r3, [r3, #93] + 2134 0040 DBB2 uxtb r3, r3 + 2135 .loc 1 1591 6 + 2136 0042 012B cmp r3, #1 + 2137 0044 02D0 beq .L118 +1592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_BUSY; + 2138 .loc 1 1593 15 + 2139 0046 0223 movs r3, #2 + 2140 0048 FB75 strb r3, [r7, #23] +1594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 2141 .loc 1 1594 5 + 2142 004a 57E0 b .L117 + 2143 .L118: +1595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the transaction information */ +1598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_BUSY_TX; + 2144 .loc 1 1598 21 + 2145 004c FB68 ldr r3, [r7, #12] + 2146 004e 0322 movs r2, #3 + 2147 0050 83F85D20 strb r2, [r3, #93] +1599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 2148 .loc 1 1599 21 + 2149 0054 FB68 ldr r3, [r7, #12] + 2150 0056 0022 movs r2, #0 + 2151 0058 1A66 str r2, [r3, #96] +1600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr = (uint8_t *)pData; + 2152 .loc 1 1600 21 + 2153 005a FB68 ldr r3, [r7, #12] + 2154 005c BA68 ldr r2, [r7, #8] + 2155 005e 9A63 str r2, [r3, #56] +1601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferSize = Size; + 2156 .loc 1 1601 21 + 2157 0060 FB68 ldr r3, [r7, #12] + 2158 0062 FA88 ldrh r2, [r7, #6] @ movhi + 2159 0064 9A87 strh r2, [r3, #60] @ movhi +1602:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = Size; + ARM GAS /tmp/ccs34gJO.s page 67 + + + 2160 .loc 1 1602 21 + 2161 0066 FB68 ldr r3, [r7, #12] + 2162 0068 FA88 ldrh r2, [r7, #6] @ movhi + 2163 006a DA87 strh r2, [r3, #62] @ movhi +1603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Init field not used in handle to zero */ +1605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr = (uint8_t *)NULL; + 2164 .loc 1 1605 21 + 2165 006c FB68 ldr r3, [r7, #12] + 2166 006e 0022 movs r2, #0 + 2167 0070 1A64 str r2, [r3, #64] +1606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferSize = 0U; + 2168 .loc 1 1606 21 + 2169 0072 FB68 ldr r3, [r7, #12] + 2170 0074 0022 movs r2, #0 + 2171 0076 A3F84420 strh r2, [r3, #68] @ movhi +1607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = 0U; + 2172 .loc 1 1607 21 + 2173 007a FB68 ldr r3, [r7, #12] + 2174 007c 0022 movs r2, #0 + 2175 007e A3F84620 strh r2, [r3, #70] @ movhi +1608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxISR = NULL; + 2176 .loc 1 1608 21 + 2177 0082 FB68 ldr r3, [r7, #12] + 2178 0084 0022 movs r2, #0 + 2179 0086 DA64 str r2, [r3, #76] +1609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the function for IT treatment */ +1611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + 2180 .loc 1 1611 17 + 2181 0088 FB68 ldr r3, [r7, #12] + 2182 008a DB68 ldr r3, [r3, #12] + 2183 .loc 1 1611 6 + 2184 008c B3F5E06F cmp r3, #1792 + 2185 0090 03D9 bls .L119 +1612:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxISR = SPI_TxISR_16BIT; + 2186 .loc 1 1613 17 + 2187 0092 FB68 ldr r3, [r7, #12] + 2188 0094 1F4A ldr r2, .L123 + 2189 0096 1A65 str r2, [r3, #80] + 2190 0098 02E0 b .L120 + 2191 .L119: +1614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +1616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxISR = SPI_TxISR_8BIT; + 2192 .loc 1 1617 17 + 2193 009a FB68 ldr r3, [r7, #12] + 2194 009c 1E4A ldr r2, .L123+4 + 2195 009e 1A65 str r2, [r3, #80] + 2196 .L120: +1618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Configure communication direction : 1Line */ +1621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + 2197 .loc 1 1621 17 + ARM GAS /tmp/ccs34gJO.s page 68 + + + 2198 00a0 FB68 ldr r3, [r7, #12] + 2199 00a2 9B68 ldr r3, [r3, #8] + 2200 .loc 1 1621 6 + 2201 00a4 B3F5004F cmp r3, #32768 + 2202 00a8 0FD1 bne .L121 +1622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ +1624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE(hspi); + 2203 .loc 1 1624 5 + 2204 00aa FB68 ldr r3, [r7, #12] + 2205 00ac 1B68 ldr r3, [r3] + 2206 00ae 1A68 ldr r2, [r3] + 2207 00b0 FB68 ldr r3, [r7, #12] + 2208 00b2 1B68 ldr r3, [r3] + 2209 00b4 22F04002 bic r2, r2, #64 + 2210 00b8 1A60 str r2, [r3] +1625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_1LINE_TX(hspi); + 2211 .loc 1 1625 5 + 2212 00ba FB68 ldr r3, [r7, #12] + 2213 00bc 1B68 ldr r3, [r3] + 2214 00be 1A68 ldr r2, [r3] + 2215 00c0 FB68 ldr r3, [r7, #12] + 2216 00c2 1B68 ldr r3, [r3] + 2217 00c4 42F48042 orr r2, r2, #16384 + 2218 00c8 1A60 str r2, [r3] + 2219 .L121: +1626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +1629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset CRC Calculation */ +1630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +1631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_RESET_CRC(hspi); +1633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +1635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable TXE and ERR interrupt */ +1637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); + 2220 .loc 1 1637 3 + 2221 00ca FB68 ldr r3, [r7, #12] + 2222 00cc 1B68 ldr r3, [r3] + 2223 00ce 5A68 ldr r2, [r3, #4] + 2224 00d0 FB68 ldr r3, [r7, #12] + 2225 00d2 1B68 ldr r3, [r3] + 2226 00d4 42F0A002 orr r2, r2, #160 + 2227 00d8 5A60 str r2, [r3, #4] +1638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check if the SPI is already enabled */ +1641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + 2228 .loc 1 1641 12 + 2229 00da FB68 ldr r3, [r7, #12] + 2230 00dc 1B68 ldr r3, [r3] + 2231 .loc 1 1641 22 + 2232 00de 1B68 ldr r3, [r3] + 2233 .loc 1 1641 28 + 2234 00e0 03F04003 and r3, r3, #64 + ARM GAS /tmp/ccs34gJO.s page 69 + + + 2235 .loc 1 1641 6 + 2236 00e4 402B cmp r3, #64 + 2237 00e6 08D0 beq .L122 +1642:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable SPI peripheral */ +1644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_ENABLE(hspi); + 2238 .loc 1 1644 5 + 2239 00e8 FB68 ldr r3, [r7, #12] + 2240 00ea 1B68 ldr r3, [r3] + 2241 00ec 1A68 ldr r2, [r3] + 2242 00ee FB68 ldr r3, [r7, #12] + 2243 00f0 1B68 ldr r3, [r3] + 2244 00f2 42F04002 orr r2, r2, #64 + 2245 00f6 1A60 str r2, [r3] + 2246 00f8 00E0 b .L117 + 2247 .L122: +1645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** error : + 2248 .loc 1 1647 1 + 2249 00fa 00BF nop + 2250 .L117: +1648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_UNLOCK(hspi); + 2251 .loc 1 1648 3 + 2252 00fc FB68 ldr r3, [r7, #12] + 2253 00fe 0022 movs r2, #0 + 2254 0100 83F85C20 strb r2, [r3, #92] +1649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; + 2255 .loc 1 1649 10 + 2256 0104 FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 2257 .L114: +1650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2258 .loc 1 1650 1 + 2259 0106 1846 mov r0, r3 + 2260 0108 1C37 adds r7, r7, #28 + 2261 .cfi_def_cfa_offset 4 + 2262 010a BD46 mov sp, r7 + 2263 .cfi_def_cfa_register 13 + 2264 @ sp needed + 2265 010c 5DF8047B ldr r7, [sp], #4 + 2266 .cfi_restore 7 + 2267 .cfi_def_cfa_offset 0 + 2268 0110 7047 bx lr + 2269 .L124: + 2270 0112 00BF .align 2 + 2271 .L123: + 2272 0114 00000000 .word SPI_TxISR_16BIT + 2273 0118 00000000 .word SPI_TxISR_8BIT + 2274 .cfi_endproc + 2275 .LFE137: + 2277 .section .text.HAL_SPI_Receive_IT,"ax",%progbits + 2278 .align 1 + 2279 .global HAL_SPI_Receive_IT + 2280 .syntax unified + 2281 .thumb + 2282 .thumb_func + 2284 HAL_SPI_Receive_IT: + ARM GAS /tmp/ccs34gJO.s page 70 + + + 2285 .LFB138: +1651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +1653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Receive an amount of data in non-blocking mode with Interrupt. +1654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +1655:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +1656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param pData pointer to data buffer +1657:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param Size amount of data to be sent +1658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval HAL status +1659:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +1660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +1661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2286 .loc 1 1661 1 + 2287 .cfi_startproc + 2288 @ args = 0, pretend = 0, frame = 24 + 2289 @ frame_needed = 1, uses_anonymous_args = 0 + 2290 0000 80B5 push {r7, lr} + 2291 .cfi_def_cfa_offset 8 + 2292 .cfi_offset 7, -8 + 2293 .cfi_offset 14, -4 + 2294 0002 86B0 sub sp, sp, #24 + 2295 .cfi_def_cfa_offset 32 + 2296 0004 00AF add r7, sp, #0 + 2297 .cfi_def_cfa_register 7 + 2298 0006 F860 str r0, [r7, #12] + 2299 0008 B960 str r1, [r7, #8] + 2300 000a 1346 mov r3, r2 + 2301 000c FB80 strh r3, [r7, #6] @ movhi +1662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef errorcode = HAL_OK; + 2302 .loc 1 1662 21 + 2303 000e 0023 movs r3, #0 + 2304 0010 FB75 strb r3, [r7, #23] +1663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1664:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->State != HAL_SPI_STATE_READY) + 2305 .loc 1 1665 11 + 2306 0012 FB68 ldr r3, [r7, #12] + 2307 0014 93F85D30 ldrb r3, [r3, #93] + 2308 0018 DBB2 uxtb r3, r3 + 2309 .loc 1 1665 6 + 2310 001a 012B cmp r3, #1 + 2311 001c 02D0 beq .L126 +1666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_BUSY; + 2312 .loc 1 1667 15 + 2313 001e 0223 movs r3, #2 + 2314 0020 FB75 strb r3, [r7, #23] +1668:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 2315 .loc 1 1668 5 + 2316 0022 90E0 b .L127 + 2317 .L126: +1669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) + 2318 .loc 1 1671 18 + 2319 0024 FB68 ldr r3, [r7, #12] + 2320 0026 9B68 ldr r3, [r3, #8] + ARM GAS /tmp/ccs34gJO.s page 71 + + + 2321 .loc 1 1671 6 + 2322 0028 002B cmp r3, #0 + 2323 002a 10D1 bne .L128 + 2324 .loc 1 1671 68 discriminator 1 + 2325 002c FB68 ldr r3, [r7, #12] + 2326 002e 5B68 ldr r3, [r3, #4] + 2327 .loc 1 1671 54 discriminator 1 + 2328 0030 B3F5827F cmp r3, #260 + 2329 0034 0BD1 bne .L128 +1672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_BUSY_RX; + 2330 .loc 1 1673 17 + 2331 0036 FB68 ldr r3, [r7, #12] + 2332 0038 0422 movs r2, #4 + 2333 003a 83F85D20 strb r2, [r3, #93] +1674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line +1675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size); + 2334 .loc 1 1675 12 + 2335 003e FB88 ldrh r3, [r7, #6] + 2336 0040 BA68 ldr r2, [r7, #8] + 2337 0042 B968 ldr r1, [r7, #8] + 2338 0044 F868 ldr r0, [r7, #12] + 2339 0046 FFF7FEFF bl HAL_SPI_TransmitReceive_IT + 2340 004a 0346 mov r3, r0 + 2341 004c 80E0 b .L129 + 2342 .L128: +1676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Process Locked */ +1679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_LOCK(hspi); + 2343 .loc 1 1679 3 + 2344 004e FB68 ldr r3, [r7, #12] + 2345 0050 93F85C30 ldrb r3, [r3, #92] @ zero_extendqisi2 + 2346 0054 012B cmp r3, #1 + 2347 0056 01D1 bne .L130 + 2348 .loc 1 1679 3 is_stmt 0 discriminator 1 + 2349 0058 0223 movs r3, #2 + 2350 .loc 1 1679 3 + 2351 005a 79E0 b .L129 + 2352 .L130: + 2353 .loc 1 1679 3 discriminator 2 + 2354 005c FB68 ldr r3, [r7, #12] + 2355 005e 0122 movs r2, #1 + 2356 0060 83F85C20 strb r2, [r3, #92] +1680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((pData == NULL) || (Size == 0U)) + 2357 .loc 1 1681 6 is_stmt 1 + 2358 0064 BB68 ldr r3, [r7, #8] + 2359 0066 002B cmp r3, #0 + 2360 0068 02D0 beq .L131 + 2361 .loc 1 1681 23 discriminator 1 + 2362 006a FB88 ldrh r3, [r7, #6] + 2363 006c 002B cmp r3, #0 + 2364 006e 02D1 bne .L132 + 2365 .L131: +1682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; + ARM GAS /tmp/ccs34gJO.s page 72 + + + 2366 .loc 1 1683 15 + 2367 0070 0123 movs r3, #1 + 2368 0072 FB75 strb r3, [r7, #23] +1684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 2369 .loc 1 1684 5 + 2370 0074 67E0 b .L127 + 2371 .L132: +1685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the transaction information */ +1688:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_BUSY_RX; + 2372 .loc 1 1688 21 + 2373 0076 FB68 ldr r3, [r7, #12] + 2374 0078 0422 movs r2, #4 + 2375 007a 83F85D20 strb r2, [r3, #93] +1689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 2376 .loc 1 1689 21 + 2377 007e FB68 ldr r3, [r7, #12] + 2378 0080 0022 movs r2, #0 + 2379 0082 1A66 str r2, [r3, #96] +1690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr = (uint8_t *)pData; + 2380 .loc 1 1690 21 + 2381 0084 FB68 ldr r3, [r7, #12] + 2382 0086 BA68 ldr r2, [r7, #8] + 2383 0088 1A64 str r2, [r3, #64] +1691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferSize = Size; + 2384 .loc 1 1691 21 + 2385 008a FB68 ldr r3, [r7, #12] + 2386 008c FA88 ldrh r2, [r7, #6] @ movhi + 2387 008e A3F84420 strh r2, [r3, #68] @ movhi +1692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = Size; + 2388 .loc 1 1692 21 + 2389 0092 FB68 ldr r3, [r7, #12] + 2390 0094 FA88 ldrh r2, [r7, #6] @ movhi + 2391 0096 A3F84620 strh r2, [r3, #70] @ movhi +1693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1694:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Init field not used in handle to zero */ +1695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr = (uint8_t *)NULL; + 2392 .loc 1 1695 21 + 2393 009a FB68 ldr r3, [r7, #12] + 2394 009c 0022 movs r2, #0 + 2395 009e 9A63 str r2, [r3, #56] +1696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferSize = 0U; + 2396 .loc 1 1696 21 + 2397 00a0 FB68 ldr r3, [r7, #12] + 2398 00a2 0022 movs r2, #0 + 2399 00a4 9A87 strh r2, [r3, #60] @ movhi +1697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = 0U; + 2400 .loc 1 1697 21 + 2401 00a6 FB68 ldr r3, [r7, #12] + 2402 00a8 0022 movs r2, #0 + 2403 00aa DA87 strh r2, [r3, #62] @ movhi +1698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxISR = NULL; + 2404 .loc 1 1698 21 + 2405 00ac FB68 ldr r3, [r7, #12] + 2406 00ae 0022 movs r2, #0 + 2407 00b0 1A65 str r2, [r3, #80] + ARM GAS /tmp/ccs34gJO.s page 73 + + +1699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1700:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check the data size to adapt Rx threshold and the set the function for IT treatment */ +1701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + 2408 .loc 1 1701 17 + 2409 00b2 FB68 ldr r3, [r7, #12] + 2410 00b4 DB68 ldr r3, [r3, #12] + 2411 .loc 1 1701 6 + 2412 00b6 B3F5E06F cmp r3, #1792 + 2413 00ba 0BD9 bls .L133 +1702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set RX Fifo threshold according the reception data length: 16 bit */ +1704:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + 2414 .loc 1 1704 5 + 2415 00bc FB68 ldr r3, [r7, #12] + 2416 00be 1B68 ldr r3, [r3] + 2417 00c0 5A68 ldr r2, [r3, #4] + 2418 00c2 FB68 ldr r3, [r7, #12] + 2419 00c4 1B68 ldr r3, [r3] + 2420 00c6 22F48052 bic r2, r2, #4096 + 2421 00ca 5A60 str r2, [r3, #4] +1705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxISR = SPI_RxISR_16BIT; + 2422 .loc 1 1705 17 + 2423 00cc FB68 ldr r3, [r7, #12] + 2424 00ce 224A ldr r2, .L137 + 2425 00d0 DA64 str r2, [r3, #76] + 2426 00d2 0AE0 b .L134 + 2427 .L133: +1706:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1707:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +1708:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set RX Fifo threshold according the reception data length: 8 bit */ +1710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + 2428 .loc 1 1710 5 + 2429 00d4 FB68 ldr r3, [r7, #12] + 2430 00d6 1B68 ldr r3, [r3] + 2431 00d8 5A68 ldr r2, [r3, #4] + 2432 00da FB68 ldr r3, [r7, #12] + 2433 00dc 1B68 ldr r3, [r3] + 2434 00de 42F48052 orr r2, r2, #4096 + 2435 00e2 5A60 str r2, [r3, #4] +1711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxISR = SPI_RxISR_8BIT; + 2436 .loc 1 1711 17 + 2437 00e4 FB68 ldr r3, [r7, #12] + 2438 00e6 1D4A ldr r2, .L137+4 + 2439 00e8 DA64 str r2, [r3, #76] + 2440 .L134: +1712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1713:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Configure communication direction : 1Line */ +1715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + 2441 .loc 1 1715 17 + 2442 00ea FB68 ldr r3, [r7, #12] + 2443 00ec 9B68 ldr r3, [r3, #8] + 2444 .loc 1 1715 6 + 2445 00ee B3F5004F cmp r3, #32768 + 2446 00f2 0FD1 bne .L135 +1716:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + ARM GAS /tmp/ccs34gJO.s page 74 + + +1717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ +1718:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE(hspi); + 2447 .loc 1 1718 5 + 2448 00f4 FB68 ldr r3, [r7, #12] + 2449 00f6 1B68 ldr r3, [r3] + 2450 00f8 1A68 ldr r2, [r3] + 2451 00fa FB68 ldr r3, [r7, #12] + 2452 00fc 1B68 ldr r3, [r3] + 2453 00fe 22F04002 bic r2, r2, #64 + 2454 0102 1A60 str r2, [r3] +1719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_1LINE_RX(hspi); + 2455 .loc 1 1719 5 + 2456 0104 FB68 ldr r3, [r7, #12] + 2457 0106 1B68 ldr r3, [r3] + 2458 0108 1A68 ldr r2, [r3] + 2459 010a FB68 ldr r3, [r7, #12] + 2460 010c 1B68 ldr r3, [r3] + 2461 010e 22F48042 bic r2, r2, #16384 + 2462 0112 1A60 str r2, [r3] + 2463 .L135: +1720:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1722:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +1723:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset CRC Calculation */ +1724:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +1725:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->CRCSize = 1U; +1727:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT +1728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->CRCSize = 2U; +1730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_RESET_CRC(hspi); +1732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +1734:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->CRCSize = 0U; +1736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1737:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +1738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1739:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable TXE and ERR interrupt */ +1740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + 2464 .loc 1 1740 3 + 2465 0114 FB68 ldr r3, [r7, #12] + 2466 0116 1B68 ldr r3, [r3] + 2467 0118 5A68 ldr r2, [r3, #4] + 2468 011a FB68 ldr r3, [r7, #12] + 2469 011c 1B68 ldr r3, [r3] + 2470 011e 42F06002 orr r2, r2, #96 + 2471 0122 5A60 str r2, [r3, #4] +1741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Note : The SPI must be enabled after unlocking current process +1743:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** to avoid the risk of SPI interrupt handle execution before current +1744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** process unlock */ +1745:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1746:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check if the SPI is already enabled */ +1747:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + 2472 .loc 1 1747 12 + ARM GAS /tmp/ccs34gJO.s page 75 + + + 2473 0124 FB68 ldr r3, [r7, #12] + 2474 0126 1B68 ldr r3, [r3] + 2475 .loc 1 1747 22 + 2476 0128 1B68 ldr r3, [r3] + 2477 .loc 1 1747 28 + 2478 012a 03F04003 and r3, r3, #64 + 2479 .loc 1 1747 6 + 2480 012e 402B cmp r3, #64 + 2481 0130 08D0 beq .L136 +1748:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable SPI peripheral */ +1750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_ENABLE(hspi); + 2482 .loc 1 1750 5 + 2483 0132 FB68 ldr r3, [r7, #12] + 2484 0134 1B68 ldr r3, [r3] + 2485 0136 1A68 ldr r2, [r3] + 2486 0138 FB68 ldr r3, [r7, #12] + 2487 013a 1B68 ldr r3, [r3] + 2488 013c 42F04002 orr r2, r2, #64 + 2489 0140 1A60 str r2, [r3] + 2490 0142 00E0 b .L127 + 2491 .L136: +1751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1752:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** error : + 2492 .loc 1 1753 1 + 2493 0144 00BF nop + 2494 .L127: +1754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Process Unlocked */ +1755:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_UNLOCK(hspi); + 2495 .loc 1 1755 3 + 2496 0146 FB68 ldr r3, [r7, #12] + 2497 0148 0022 movs r2, #0 + 2498 014a 83F85C20 strb r2, [r3, #92] +1756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; + 2499 .loc 1 1756 10 + 2500 014e FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 2501 .L129: +1757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2502 .loc 1 1757 1 + 2503 0150 1846 mov r0, r3 + 2504 0152 1837 adds r7, r7, #24 + 2505 .cfi_def_cfa_offset 8 + 2506 0154 BD46 mov sp, r7 + 2507 .cfi_def_cfa_register 13 + 2508 @ sp needed + 2509 0156 80BD pop {r7, pc} + 2510 .L138: + 2511 .align 2 + 2512 .L137: + 2513 0158 00000000 .word SPI_RxISR_16BIT + 2514 015c 00000000 .word SPI_RxISR_8BIT + 2515 .cfi_endproc + 2516 .LFE138: + 2518 .section .text.HAL_SPI_TransmitReceive_IT,"ax",%progbits + 2519 .align 1 + 2520 .global HAL_SPI_TransmitReceive_IT + ARM GAS /tmp/ccs34gJO.s page 76 + + + 2521 .syntax unified + 2522 .thumb + 2523 .thumb_func + 2525 HAL_SPI_TransmitReceive_IT: + 2526 .LFB139: +1758:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +1760:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt. +1761:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +1762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +1763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param pTxData pointer to transmission data buffer +1764:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param pRxData pointer to reception data buffer +1765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param Size amount of data to be sent and received +1766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval HAL status +1767:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +1768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pR +1769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2527 .loc 1 1769 1 + 2528 .cfi_startproc + 2529 @ args = 0, pretend = 0, frame = 24 + 2530 @ frame_needed = 1, uses_anonymous_args = 0 + 2531 @ link register save eliminated. + 2532 0000 80B4 push {r7} + 2533 .cfi_def_cfa_offset 4 + 2534 .cfi_offset 7, -4 + 2535 0002 87B0 sub sp, sp, #28 + 2536 .cfi_def_cfa_offset 32 + 2537 0004 00AF add r7, sp, #0 + 2538 .cfi_def_cfa_register 7 + 2539 0006 F860 str r0, [r7, #12] + 2540 0008 B960 str r1, [r7, #8] + 2541 000a 7A60 str r2, [r7, #4] + 2542 000c 7B80 strh r3, [r7, #2] @ movhi +1770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t tmp_mode; +1771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_StateTypeDef tmp_state; +1772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef errorcode = HAL_OK; + 2543 .loc 1 1772 24 + 2544 000e 0023 movs r3, #0 + 2545 0010 FB75 strb r3, [r7, #23] +1773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check Direction parameter */ +1775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); +1776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1777:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Process locked */ +1778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_LOCK(hspi); + 2546 .loc 1 1778 3 + 2547 0012 FB68 ldr r3, [r7, #12] + 2548 0014 93F85C30 ldrb r3, [r3, #92] @ zero_extendqisi2 + 2549 0018 012B cmp r3, #1 + 2550 001a 01D1 bne .L140 + 2551 .loc 1 1778 3 is_stmt 0 discriminator 1 + 2552 001c 0223 movs r3, #2 + 2553 .loc 1 1778 3 + 2554 001e 91E0 b .L141 + 2555 .L140: + 2556 .loc 1 1778 3 discriminator 2 + 2557 0020 FB68 ldr r3, [r7, #12] + ARM GAS /tmp/ccs34gJO.s page 77 + + + 2558 0022 0122 movs r2, #1 + 2559 0024 83F85C20 strb r2, [r3, #92] +1779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1780:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Init temporary variables */ +1781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmp_state = hspi->State; + 2560 .loc 1 1781 23 is_stmt 1 + 2561 0028 FB68 ldr r3, [r7, #12] + 2562 002a 93F85D30 ldrb r3, [r3, #93] + 2563 002e BB75 strb r3, [r7, #22] +1782:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmp_mode = hspi->Init.Mode; + 2564 .loc 1 1782 23 + 2565 0030 FB68 ldr r3, [r7, #12] + 2566 0032 5B68 ldr r3, [r3, #4] + 2567 0034 3B61 str r3, [r7, #16] +1783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (!((tmp_state == HAL_SPI_STATE_READY) || \ + 2568 .loc 1 1784 6 + 2569 0036 BB7D ldrb r3, [r7, #22] @ zero_extendqisi2 + 2570 0038 012B cmp r3, #1 + 2571 003a 0DD0 beq .L142 + 2572 .loc 1 1784 7 discriminator 1 + 2573 003c 3B69 ldr r3, [r7, #16] + 2574 003e B3F5827F cmp r3, #260 + 2575 0042 06D1 bne .L143 +1785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_st + 2576 .loc 1 1785 54 + 2577 0044 FB68 ldr r3, [r7, #12] + 2578 0046 9B68 ldr r3, [r3, #8] + 2579 .loc 1 1785 40 + 2580 0048 002B cmp r3, #0 + 2581 004a 02D1 bne .L143 + 2582 .loc 1 1785 90 discriminator 1 + 2583 004c BB7D ldrb r3, [r7, #22] @ zero_extendqisi2 + 2584 004e 042B cmp r3, #4 + 2585 0050 02D0 beq .L142 + 2586 .L143: +1786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1787:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_BUSY; + 2587 .loc 1 1787 15 + 2588 0052 0223 movs r3, #2 + 2589 0054 FB75 strb r3, [r7, #23] +1788:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 2590 .loc 1 1788 5 + 2591 0056 70E0 b .L144 + 2592 .L142: +1789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + 2593 .loc 1 1791 6 + 2594 0058 BB68 ldr r3, [r7, #8] + 2595 005a 002B cmp r3, #0 + 2596 005c 05D0 beq .L145 + 2597 .loc 1 1791 25 discriminator 1 + 2598 005e 7B68 ldr r3, [r7, #4] + 2599 0060 002B cmp r3, #0 + 2600 0062 02D0 beq .L145 + 2601 .loc 1 1791 46 discriminator 2 + ARM GAS /tmp/ccs34gJO.s page 78 + + + 2602 0064 7B88 ldrh r3, [r7, #2] + 2603 0066 002B cmp r3, #0 + 2604 0068 02D1 bne .L146 + 2605 .L145: +1792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; + 2606 .loc 1 1793 15 + 2607 006a 0123 movs r3, #1 + 2608 006c FB75 strb r3, [r7, #23] +1794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 2609 .loc 1 1794 5 + 2610 006e 64E0 b .L144 + 2611 .L146: +1795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ +1798:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->State != HAL_SPI_STATE_BUSY_RX) + 2612 .loc 1 1798 11 + 2613 0070 FB68 ldr r3, [r7, #12] + 2614 0072 93F85D30 ldrb r3, [r3, #93] + 2615 0076 DBB2 uxtb r3, r3 + 2616 .loc 1 1798 6 + 2617 0078 042B cmp r3, #4 + 2618 007a 03D0 beq .L147 +1799:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + 2619 .loc 1 1800 17 + 2620 007c FB68 ldr r3, [r7, #12] + 2621 007e 0522 movs r2, #5 + 2622 0080 83F85D20 strb r2, [r3, #93] + 2623 .L147: +1801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1803:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the transaction information */ +1804:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 2624 .loc 1 1804 21 + 2625 0084 FB68 ldr r3, [r7, #12] + 2626 0086 0022 movs r2, #0 + 2627 0088 1A66 str r2, [r3, #96] +1805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr = (uint8_t *)pTxData; + 2628 .loc 1 1805 21 + 2629 008a FB68 ldr r3, [r7, #12] + 2630 008c BA68 ldr r2, [r7, #8] + 2631 008e 9A63 str r2, [r3, #56] +1806:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferSize = Size; + 2632 .loc 1 1806 21 + 2633 0090 FB68 ldr r3, [r7, #12] + 2634 0092 7A88 ldrh r2, [r7, #2] @ movhi + 2635 0094 9A87 strh r2, [r3, #60] @ movhi +1807:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = Size; + 2636 .loc 1 1807 21 + 2637 0096 FB68 ldr r3, [r7, #12] + 2638 0098 7A88 ldrh r2, [r7, #2] @ movhi + 2639 009a DA87 strh r2, [r3, #62] @ movhi +1808:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr = (uint8_t *)pRxData; + 2640 .loc 1 1808 21 + 2641 009c FB68 ldr r3, [r7, #12] + ARM GAS /tmp/ccs34gJO.s page 79 + + + 2642 009e 7A68 ldr r2, [r7, #4] + 2643 00a0 1A64 str r2, [r3, #64] +1809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferSize = Size; + 2644 .loc 1 1809 21 + 2645 00a2 FB68 ldr r3, [r7, #12] + 2646 00a4 7A88 ldrh r2, [r7, #2] @ movhi + 2647 00a6 A3F84420 strh r2, [r3, #68] @ movhi +1810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = Size; + 2648 .loc 1 1810 21 + 2649 00aa FB68 ldr r3, [r7, #12] + 2650 00ac 7A88 ldrh r2, [r7, #2] @ movhi + 2651 00ae A3F84620 strh r2, [r3, #70] @ movhi +1811:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the function for IT treatment */ +1813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + 2652 .loc 1 1813 17 + 2653 00b2 FB68 ldr r3, [r7, #12] + 2654 00b4 DB68 ldr r3, [r3, #12] + 2655 .loc 1 1813 6 + 2656 00b6 B3F5E06F cmp r3, #1792 + 2657 00ba 06D9 bls .L148 +1814:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxISR = SPI_2linesRxISR_16BIT; + 2658 .loc 1 1815 21 + 2659 00bc FB68 ldr r3, [r7, #12] + 2660 00be 244A ldr r2, .L154 + 2661 00c0 DA64 str r2, [r3, #76] +1816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxISR = SPI_2linesTxISR_16BIT; + 2662 .loc 1 1816 21 + 2663 00c2 FB68 ldr r3, [r7, #12] + 2664 00c4 234A ldr r2, .L154+4 + 2665 00c6 1A65 str r2, [r3, #80] + 2666 00c8 05E0 b .L149 + 2667 .L148: +1817:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1818:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +1819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1820:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxISR = SPI_2linesRxISR_8BIT; + 2668 .loc 1 1820 21 + 2669 00ca FB68 ldr r3, [r7, #12] + 2670 00cc 224A ldr r2, .L154+8 + 2671 00ce DA64 str r2, [r3, #76] +1821:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxISR = SPI_2linesTxISR_8BIT; + 2672 .loc 1 1821 21 + 2673 00d0 FB68 ldr r3, [r7, #12] + 2674 00d2 224A ldr r2, .L154+12 + 2675 00d4 1A65 str r2, [r3, #80] + 2676 .L149: +1822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +1825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset CRC Calculation */ +1826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +1827:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1828:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->CRCSize = 1U; +1829:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT +1830:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + ARM GAS /tmp/ccs34gJO.s page 80 + + +1831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->CRCSize = 2U; +1832:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_RESET_CRC(hspi); +1834:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1835:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +1836:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->CRCSize = 0U; +1838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +1840:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check if packing mode is enabled and if there is more than 2 data to receive */ +1842:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size >= 2U)) + 2677 .loc 1 1842 18 + 2678 00d6 FB68 ldr r3, [r7, #12] + 2679 00d8 DB68 ldr r3, [r3, #12] + 2680 .loc 1 1842 6 + 2681 00da B3F5E06F cmp r3, #1792 + 2682 00de 02D8 bhi .L150 + 2683 .loc 1 1842 49 discriminator 1 + 2684 00e0 7B88 ldrh r3, [r7, #2] + 2685 00e2 012B cmp r3, #1 + 2686 00e4 08D9 bls .L151 + 2687 .L150: +1843:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1844:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set RX Fifo threshold according the reception data length: 16 bit */ +1845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + 2688 .loc 1 1845 5 + 2689 00e6 FB68 ldr r3, [r7, #12] + 2690 00e8 1B68 ldr r3, [r3] + 2691 00ea 5A68 ldr r2, [r3, #4] + 2692 00ec FB68 ldr r3, [r7, #12] + 2693 00ee 1B68 ldr r3, [r3] + 2694 00f0 22F48052 bic r2, r2, #4096 + 2695 00f4 5A60 str r2, [r3, #4] + 2696 00f6 07E0 b .L152 + 2697 .L151: +1846:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +1848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set RX Fifo threshold according the reception data length: 8 bit */ +1850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + 2698 .loc 1 1850 5 + 2699 00f8 FB68 ldr r3, [r7, #12] + 2700 00fa 1B68 ldr r3, [r3] + 2701 00fc 5A68 ldr r2, [r3, #4] + 2702 00fe FB68 ldr r3, [r7, #12] + 2703 0100 1B68 ldr r3, [r3] + 2704 0102 42F48052 orr r2, r2, #4096 + 2705 0106 5A60 str r2, [r3, #4] + 2706 .L152: +1851:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1852:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1853:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable TXE, RXNE and ERR interrupt */ +1854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + 2707 .loc 1 1854 3 + 2708 0108 FB68 ldr r3, [r7, #12] + 2709 010a 1B68 ldr r3, [r3] + ARM GAS /tmp/ccs34gJO.s page 81 + + + 2710 010c 5A68 ldr r2, [r3, #4] + 2711 010e FB68 ldr r3, [r7, #12] + 2712 0110 1B68 ldr r3, [r3] + 2713 0112 42F0E002 orr r2, r2, #224 + 2714 0116 5A60 str r2, [r3, #4] +1855:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1856:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check if the SPI is already enabled */ +1857:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + 2715 .loc 1 1857 12 + 2716 0118 FB68 ldr r3, [r7, #12] + 2717 011a 1B68 ldr r3, [r3] + 2718 .loc 1 1857 22 + 2719 011c 1B68 ldr r3, [r3] + 2720 .loc 1 1857 28 + 2721 011e 03F04003 and r3, r3, #64 + 2722 .loc 1 1857 6 + 2723 0122 402B cmp r3, #64 + 2724 0124 08D0 beq .L153 +1858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1859:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable SPI peripheral */ +1860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_ENABLE(hspi); + 2725 .loc 1 1860 5 + 2726 0126 FB68 ldr r3, [r7, #12] + 2727 0128 1B68 ldr r3, [r3] + 2728 012a 1A68 ldr r2, [r3] + 2729 012c FB68 ldr r3, [r7, #12] + 2730 012e 1B68 ldr r3, [r3] + 2731 0130 42F04002 orr r2, r2, #64 + 2732 0134 1A60 str r2, [r3] + 2733 0136 00E0 b .L144 + 2734 .L153: +1861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** error : + 2735 .loc 1 1863 1 + 2736 0138 00BF nop + 2737 .L144: +1864:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Process Unlocked */ +1865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_UNLOCK(hspi); + 2738 .loc 1 1865 3 + 2739 013a FB68 ldr r3, [r7, #12] + 2740 013c 0022 movs r2, #0 + 2741 013e 83F85C20 strb r2, [r3, #92] +1866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; + 2742 .loc 1 1866 10 + 2743 0142 FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 2744 .L141: +1867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 2745 .loc 1 1867 1 + 2746 0144 1846 mov r0, r3 + 2747 0146 1C37 adds r7, r7, #28 + 2748 .cfi_def_cfa_offset 4 + 2749 0148 BD46 mov sp, r7 + 2750 .cfi_def_cfa_register 13 + 2751 @ sp needed + 2752 014a 5DF8047B ldr r7, [sp], #4 + 2753 .cfi_restore 7 + ARM GAS /tmp/ccs34gJO.s page 82 + + + 2754 .cfi_def_cfa_offset 0 + 2755 014e 7047 bx lr + 2756 .L155: + 2757 .align 2 + 2758 .L154: + 2759 0150 00000000 .word SPI_2linesRxISR_16BIT + 2760 0154 00000000 .word SPI_2linesTxISR_16BIT + 2761 0158 00000000 .word SPI_2linesRxISR_8BIT + 2762 015c 00000000 .word SPI_2linesTxISR_8BIT + 2763 .cfi_endproc + 2764 .LFE139: + 2766 .section .text.HAL_SPI_Transmit_DMA,"ax",%progbits + 2767 .align 1 + 2768 .global HAL_SPI_Transmit_DMA + 2769 .syntax unified + 2770 .thumb + 2771 .thumb_func + 2773 HAL_SPI_Transmit_DMA: + 2774 .LFB140: +1868:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +1870:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Transmit an amount of data in non-blocking mode with DMA. +1871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +1872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +1873:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param pData pointer to data buffer +1874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param Size amount of data to be sent +1875:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval HAL status +1876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +1877:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +1878:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 2775 .loc 1 1878 1 + 2776 .cfi_startproc + 2777 @ args = 0, pretend = 0, frame = 24 + 2778 @ frame_needed = 1, uses_anonymous_args = 0 + 2779 0000 80B5 push {r7, lr} + 2780 .cfi_def_cfa_offset 8 + 2781 .cfi_offset 7, -8 + 2782 .cfi_offset 14, -4 + 2783 0002 86B0 sub sp, sp, #24 + 2784 .cfi_def_cfa_offset 32 + 2785 0004 00AF add r7, sp, #0 + 2786 .cfi_def_cfa_register 7 + 2787 0006 F860 str r0, [r7, #12] + 2788 0008 B960 str r1, [r7, #8] + 2789 000a 1346 mov r3, r2 + 2790 000c FB80 strh r3, [r7, #6] @ movhi +1879:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef errorcode = HAL_OK; + 2791 .loc 1 1879 21 + 2792 000e 0023 movs r3, #0 + 2793 0010 FB75 strb r3, [r7, #23] +1880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check tx dma handle */ +1882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); +1883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1884:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check Direction parameter */ +1885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); +1886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + ARM GAS /tmp/ccs34gJO.s page 83 + + +1887:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Process Locked */ +1888:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_LOCK(hspi); + 2794 .loc 1 1888 3 + 2795 0012 FB68 ldr r3, [r7, #12] + 2796 0014 93F85C30 ldrb r3, [r3, #92] @ zero_extendqisi2 + 2797 0018 012B cmp r3, #1 + 2798 001a 01D1 bne .L157 + 2799 .loc 1 1888 3 is_stmt 0 discriminator 1 + 2800 001c 0223 movs r3, #2 + 2801 .loc 1 1888 3 + 2802 001e D4E0 b .L158 + 2803 .L157: + 2804 .loc 1 1888 3 discriminator 2 + 2805 0020 FB68 ldr r3, [r7, #12] + 2806 0022 0122 movs r2, #1 + 2807 0024 83F85C20 strb r2, [r3, #92] +1889:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1890:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->State != HAL_SPI_STATE_READY) + 2808 .loc 1 1890 11 is_stmt 1 + 2809 0028 FB68 ldr r3, [r7, #12] + 2810 002a 93F85D30 ldrb r3, [r3, #93] + 2811 002e DBB2 uxtb r3, r3 + 2812 .loc 1 1890 6 + 2813 0030 012B cmp r3, #1 + 2814 0032 02D0 beq .L159 +1891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1892:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_BUSY; + 2815 .loc 1 1892 15 + 2816 0034 0223 movs r3, #2 + 2817 0036 FB75 strb r3, [r7, #23] +1893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 2818 .loc 1 1893 5 + 2819 0038 C2E0 b .L160 + 2820 .L159: +1894:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1895:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((pData == NULL) || (Size == 0U)) + 2821 .loc 1 1896 6 + 2822 003a BB68 ldr r3, [r7, #8] + 2823 003c 002B cmp r3, #0 + 2824 003e 02D0 beq .L161 + 2825 .loc 1 1896 23 discriminator 1 + 2826 0040 FB88 ldrh r3, [r7, #6] + 2827 0042 002B cmp r3, #0 + 2828 0044 02D1 bne .L162 + 2829 .L161: +1897:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; + 2830 .loc 1 1898 15 + 2831 0046 0123 movs r3, #1 + 2832 0048 FB75 strb r3, [r7, #23] +1899:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 2833 .loc 1 1899 5 + 2834 004a B9E0 b .L160 + 2835 .L162: +1900:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + ARM GAS /tmp/ccs34gJO.s page 84 + + +1902:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the transaction information */ +1903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_BUSY_TX; + 2836 .loc 1 1903 21 + 2837 004c FB68 ldr r3, [r7, #12] + 2838 004e 0322 movs r2, #3 + 2839 0050 83F85D20 strb r2, [r3, #93] +1904:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 2840 .loc 1 1904 21 + 2841 0054 FB68 ldr r3, [r7, #12] + 2842 0056 0022 movs r2, #0 + 2843 0058 1A66 str r2, [r3, #96] +1905:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr = (uint8_t *)pData; + 2844 .loc 1 1905 21 + 2845 005a FB68 ldr r3, [r7, #12] + 2846 005c BA68 ldr r2, [r7, #8] + 2847 005e 9A63 str r2, [r3, #56] +1906:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferSize = Size; + 2848 .loc 1 1906 21 + 2849 0060 FB68 ldr r3, [r7, #12] + 2850 0062 FA88 ldrh r2, [r7, #6] @ movhi + 2851 0064 9A87 strh r2, [r3, #60] @ movhi +1907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = Size; + 2852 .loc 1 1907 21 + 2853 0066 FB68 ldr r3, [r7, #12] + 2854 0068 FA88 ldrh r2, [r7, #6] @ movhi + 2855 006a DA87 strh r2, [r3, #62] @ movhi +1908:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1909:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Init field not used in handle to zero */ +1910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr = (uint8_t *)NULL; + 2856 .loc 1 1910 21 + 2857 006c FB68 ldr r3, [r7, #12] + 2858 006e 0022 movs r2, #0 + 2859 0070 1A64 str r2, [r3, #64] +1911:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxISR = NULL; + 2860 .loc 1 1911 21 + 2861 0072 FB68 ldr r3, [r7, #12] + 2862 0074 0022 movs r2, #0 + 2863 0076 1A65 str r2, [r3, #80] +1912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxISR = NULL; + 2864 .loc 1 1912 21 + 2865 0078 FB68 ldr r3, [r7, #12] + 2866 007a 0022 movs r2, #0 + 2867 007c DA64 str r2, [r3, #76] +1913:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferSize = 0U; + 2868 .loc 1 1913 21 + 2869 007e FB68 ldr r3, [r7, #12] + 2870 0080 0022 movs r2, #0 + 2871 0082 A3F84420 strh r2, [r3, #68] @ movhi +1914:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = 0U; + 2872 .loc 1 1914 21 + 2873 0086 FB68 ldr r3, [r7, #12] + 2874 0088 0022 movs r2, #0 + 2875 008a A3F84620 strh r2, [r3, #70] @ movhi +1915:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1916:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Configure communication direction : 1Line */ +1917:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + 2876 .loc 1 1917 17 + ARM GAS /tmp/ccs34gJO.s page 85 + + + 2877 008e FB68 ldr r3, [r7, #12] + 2878 0090 9B68 ldr r3, [r3, #8] + 2879 .loc 1 1917 6 + 2880 0092 B3F5004F cmp r3, #32768 + 2881 0096 0FD1 bne .L163 +1918:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1919:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ +1920:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE(hspi); + 2882 .loc 1 1920 5 + 2883 0098 FB68 ldr r3, [r7, #12] + 2884 009a 1B68 ldr r3, [r3] + 2885 009c 1A68 ldr r2, [r3] + 2886 009e FB68 ldr r3, [r7, #12] + 2887 00a0 1B68 ldr r3, [r3] + 2888 00a2 22F04002 bic r2, r2, #64 + 2889 00a6 1A60 str r2, [r3] +1921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_1LINE_TX(hspi); + 2890 .loc 1 1921 5 + 2891 00a8 FB68 ldr r3, [r7, #12] + 2892 00aa 1B68 ldr r3, [r3] + 2893 00ac 1A68 ldr r2, [r3] + 2894 00ae FB68 ldr r3, [r7, #12] + 2895 00b0 1B68 ldr r3, [r3] + 2896 00b2 42F48042 orr r2, r2, #16384 + 2897 00b6 1A60 str r2, [r3] + 2898 .L163: +1922:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1923:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1924:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +1925:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset CRC Calculation */ +1926:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +1927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1928:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_RESET_CRC(hspi); +1929:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1930:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +1931:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1932:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the SPI TxDMA Half transfer complete callback */ +1933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt; + 2899 .loc 1 1933 7 + 2900 00b8 FB68 ldr r3, [r7, #12] + 2901 00ba 5B6D ldr r3, [r3, #84] + 2902 .loc 1 1933 38 + 2903 00bc 454A ldr r2, .L168 + 2904 00be DA62 str r2, [r3, #44] +1934:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1935:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the SPI TxDMA transfer complete callback */ +1936:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt; + 2905 .loc 1 1936 7 + 2906 00c0 FB68 ldr r3, [r7, #12] + 2907 00c2 5B6D ldr r3, [r3, #84] + 2908 .loc 1 1936 34 + 2909 00c4 444A ldr r2, .L168+4 + 2910 00c6 9A62 str r2, [r3, #40] +1937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the DMA error callback */ +1939:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmatx->XferErrorCallback = SPI_DMAError; + 2911 .loc 1 1939 7 + ARM GAS /tmp/ccs34gJO.s page 86 + + + 2912 00c8 FB68 ldr r3, [r7, #12] + 2913 00ca 5B6D ldr r3, [r3, #84] + 2914 .loc 1 1939 35 + 2915 00cc 434A ldr r2, .L168+8 + 2916 00ce 1A63 str r2, [r3, #48] +1940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1941:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the DMA AbortCpltCallback */ +1942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmatx->XferAbortCallback = NULL; + 2917 .loc 1 1942 7 + 2918 00d0 FB68 ldr r3, [r7, #12] + 2919 00d2 5B6D ldr r3, [r3, #84] + 2920 .loc 1 1942 35 + 2921 00d4 0022 movs r2, #0 + 2922 00d6 5A63 str r2, [r3, #52] +1943:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1944:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); + 2923 .loc 1 1944 3 + 2924 00d8 FB68 ldr r3, [r7, #12] + 2925 00da 1B68 ldr r3, [r3] + 2926 00dc 5A68 ldr r2, [r3, #4] + 2927 00de FB68 ldr r3, [r7, #12] + 2928 00e0 1B68 ldr r3, [r3] + 2929 00e2 22F48042 bic r2, r2, #16384 + 2930 00e6 5A60 str r2, [r3, #4] +1945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Packing mode is enabled only if the DMA setting is HALWORD */ +1946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDA + 2931 .loc 1 1946 18 + 2932 00e8 FB68 ldr r3, [r7, #12] + 2933 00ea DB68 ldr r3, [r3, #12] + 2934 .loc 1 1946 6 + 2935 00ec B3F5E06F cmp r3, #1792 + 2936 00f0 2DD8 bhi .L164 + 2937 .loc 1 1946 58 discriminator 1 + 2938 00f2 FB68 ldr r3, [r7, #12] + 2939 00f4 5B6D ldr r3, [r3, #84] + 2940 .loc 1 1946 72 discriminator 1 + 2941 00f6 5B69 ldr r3, [r3, #20] + 2942 .loc 1 1946 50 discriminator 1 + 2943 00f8 B3F5806F cmp r3, #1024 + 2944 00fc 27D1 bne .L164 +1947:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1948:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check the even/odd of the data size + crc if enabled */ +1949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->TxXferCount & 0x1U) == 0U) + 2945 .loc 1 1949 14 + 2946 00fe FB68 ldr r3, [r7, #12] + 2947 0100 DB8F ldrh r3, [r3, #62] @ movhi + 2948 0102 9BB2 uxth r3, r3 + 2949 .loc 1 1949 28 + 2950 0104 03F00103 and r3, r3, #1 + 2951 .loc 1 1949 8 + 2952 0108 002B cmp r3, #0 + 2953 010a 0FD1 bne .L165 +1950:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1951:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); + 2954 .loc 1 1951 7 + 2955 010c FB68 ldr r3, [r7, #12] + 2956 010e 1B68 ldr r3, [r3] + ARM GAS /tmp/ccs34gJO.s page 87 + + + 2957 0110 5A68 ldr r2, [r3, #4] + 2958 0112 FB68 ldr r3, [r7, #12] + 2959 0114 1B68 ldr r3, [r3] + 2960 0116 22F48042 bic r2, r2, #16384 + 2961 011a 5A60 str r2, [r3, #4] +1952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = (hspi->TxXferCount >> 1U); + 2962 .loc 1 1952 32 + 2963 011c FB68 ldr r3, [r7, #12] + 2964 011e DB8F ldrh r3, [r3, #62] @ movhi + 2965 0120 9BB2 uxth r3, r3 + 2966 .loc 1 1952 25 + 2967 0122 5B08 lsrs r3, r3, #1 + 2968 0124 9AB2 uxth r2, r3 + 2969 0126 FB68 ldr r3, [r7, #12] + 2970 0128 DA87 strh r2, [r3, #62] @ movhi + 2971 012a 10E0 b .L164 + 2972 .L165: +1953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1954:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +1955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1956:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); + 2973 .loc 1 1956 7 + 2974 012c FB68 ldr r3, [r7, #12] + 2975 012e 1B68 ldr r3, [r3] + 2976 0130 5A68 ldr r2, [r3, #4] + 2977 0132 FB68 ldr r3, [r7, #12] + 2978 0134 1B68 ldr r3, [r3] + 2979 0136 42F48042 orr r2, r2, #16384 + 2980 013a 5A60 str r2, [r3, #4] +1957:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U; + 2981 .loc 1 1957 32 + 2982 013c FB68 ldr r3, [r7, #12] + 2983 013e DB8F ldrh r3, [r3, #62] @ movhi + 2984 0140 9BB2 uxth r3, r3 + 2985 .loc 1 1957 53 + 2986 0142 5B08 lsrs r3, r3, #1 + 2987 0144 9BB2 uxth r3, r3 + 2988 0146 0133 adds r3, r3, #1 + 2989 0148 9AB2 uxth r2, r3 + 2990 .loc 1 1957 25 + 2991 014a FB68 ldr r3, [r7, #12] + 2992 014c DA87 strh r2, [r3, #62] @ movhi + 2993 .L164: +1958:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1960:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable the Tx DMA Stream/Channel */ +1962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instanc + 2994 .loc 1 1962 17 + 2995 014e FB68 ldr r3, [r7, #12] + 2996 0150 586D ldr r0, [r3, #84] + 2997 .loc 1 1962 62 + 2998 0152 FB68 ldr r3, [r7, #12] + 2999 0154 9B6B ldr r3, [r3, #56] + 3000 .loc 1 1962 17 + 3001 0156 1946 mov r1, r3 + 3002 .loc 1 1962 91 + ARM GAS /tmp/ccs34gJO.s page 88 + + + 3003 0158 FB68 ldr r3, [r7, #12] + 3004 015a 1B68 ldr r3, [r3] + 3005 .loc 1 1962 86 + 3006 015c 0C33 adds r3, r3, #12 + 3007 .loc 1 1962 17 + 3008 015e 1A46 mov r2, r3 +1963:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount)) + 3009 .loc 1 1963 38 + 3010 0160 FB68 ldr r3, [r7, #12] + 3011 0162 DB8F ldrh r3, [r3, #62] @ movhi + 3012 0164 9BB2 uxth r3, r3 +1962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount)) + 3013 .loc 1 1962 17 + 3014 0166 FFF7FEFF bl HAL_DMA_Start_IT + 3015 016a 0346 mov r3, r0 +1962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount)) + 3016 .loc 1 1962 6 discriminator 1 + 3017 016c 002B cmp r3, #0 + 3018 016e 08D0 beq .L166 +1964:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1965:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Update SPI error code */ +1966:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + 3019 .loc 1 1966 5 + 3020 0170 FB68 ldr r3, [r7, #12] + 3021 0172 1B6E ldr r3, [r3, #96] + 3022 0174 43F01002 orr r2, r3, #16 + 3023 0178 FB68 ldr r3, [r7, #12] + 3024 017a 1A66 str r2, [r3, #96] +1967:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; + 3025 .loc 1 1967 15 + 3026 017c 0123 movs r3, #1 + 3027 017e FB75 strb r3, [r7, #23] +1968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1969:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 3028 .loc 1 1969 5 + 3029 0180 1EE0 b .L160 + 3030 .L166: +1970:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1971:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1972:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check if the SPI is already enabled */ +1973:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + 3031 .loc 1 1973 12 + 3032 0182 FB68 ldr r3, [r7, #12] + 3033 0184 1B68 ldr r3, [r3] + 3034 .loc 1 1973 22 + 3035 0186 1B68 ldr r3, [r3] + 3036 .loc 1 1973 28 + 3037 0188 03F04003 and r3, r3, #64 + 3038 .loc 1 1973 6 + 3039 018c 402B cmp r3, #64 + 3040 018e 07D0 beq .L167 +1974:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +1975:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable SPI peripheral */ +1976:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_ENABLE(hspi); + 3041 .loc 1 1976 5 + 3042 0190 FB68 ldr r3, [r7, #12] + 3043 0192 1B68 ldr r3, [r3] + ARM GAS /tmp/ccs34gJO.s page 89 + + + 3044 0194 1A68 ldr r2, [r3] + 3045 0196 FB68 ldr r3, [r7, #12] + 3046 0198 1B68 ldr r3, [r3] + 3047 019a 42F04002 orr r2, r2, #64 + 3048 019e 1A60 str r2, [r3] + 3049 .L167: +1977:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +1978:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1979:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable the SPI Error Interrupt Bit */ +1980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); + 3050 .loc 1 1980 3 + 3051 01a0 FB68 ldr r3, [r7, #12] + 3052 01a2 1B68 ldr r3, [r3] + 3053 01a4 5A68 ldr r2, [r3, #4] + 3054 01a6 FB68 ldr r3, [r7, #12] + 3055 01a8 1B68 ldr r3, [r3] + 3056 01aa 42F02002 orr r2, r2, #32 + 3057 01ae 5A60 str r2, [r3, #4] +1981:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1982:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable Tx DMA Request */ +1983:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + 3058 .loc 1 1983 3 + 3059 01b0 FB68 ldr r3, [r7, #12] + 3060 01b2 1B68 ldr r3, [r3] + 3061 01b4 5A68 ldr r2, [r3, #4] + 3062 01b6 FB68 ldr r3, [r7, #12] + 3063 01b8 1B68 ldr r3, [r3] + 3064 01ba 42F00202 orr r2, r2, #2 + 3065 01be 5A60 str r2, [r3, #4] + 3066 .L160: +1984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1985:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** error : +1986:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Process Unlocked */ +1987:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_UNLOCK(hspi); + 3067 .loc 1 1987 3 + 3068 01c0 FB68 ldr r3, [r7, #12] + 3069 01c2 0022 movs r2, #0 + 3070 01c4 83F85C20 strb r2, [r3, #92] +1988:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; + 3071 .loc 1 1988 10 + 3072 01c8 FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 3073 .L158: +1989:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 3074 .loc 1 1989 1 + 3075 01ca 1846 mov r0, r3 + 3076 01cc 1837 adds r7, r7, #24 + 3077 .cfi_def_cfa_offset 8 + 3078 01ce BD46 mov sp, r7 + 3079 .cfi_def_cfa_register 13 + 3080 @ sp needed + 3081 01d0 80BD pop {r7, pc} + 3082 .L169: + 3083 01d2 00BF .align 2 + 3084 .L168: + 3085 01d4 00000000 .word SPI_DMAHalfTransmitCplt + 3086 01d8 00000000 .word SPI_DMATransmitCplt + 3087 01dc 00000000 .word SPI_DMAError + ARM GAS /tmp/ccs34gJO.s page 90 + + + 3088 .cfi_endproc + 3089 .LFE140: + 3091 .section .text.HAL_SPI_Receive_DMA,"ax",%progbits + 3092 .align 1 + 3093 .global HAL_SPI_Receive_DMA + 3094 .syntax unified + 3095 .thumb + 3096 .thumb_func + 3098 HAL_SPI_Receive_DMA: + 3099 .LFB141: +1990:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +1991:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +1992:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Receive an amount of data in non-blocking mode with DMA. +1993:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined. +1994:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +1995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +1996:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param pData pointer to data buffer +1997:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @note When the CRC feature is enabled the pData Length must be Size + 1. +1998:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param Size amount of data to be sent +1999:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval HAL status +2000:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2001:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +2002:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3100 .loc 1 2002 1 + 3101 .cfi_startproc + 3102 @ args = 0, pretend = 0, frame = 24 + 3103 @ frame_needed = 1, uses_anonymous_args = 0 + 3104 0000 80B5 push {r7, lr} + 3105 .cfi_def_cfa_offset 8 + 3106 .cfi_offset 7, -8 + 3107 .cfi_offset 14, -4 + 3108 0002 86B0 sub sp, sp, #24 + 3109 .cfi_def_cfa_offset 32 + 3110 0004 00AF add r7, sp, #0 + 3111 .cfi_def_cfa_register 7 + 3112 0006 F860 str r0, [r7, #12] + 3113 0008 B960 str r1, [r7, #8] + 3114 000a 1346 mov r3, r2 + 3115 000c FB80 strh r3, [r7, #6] @ movhi +2003:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef errorcode = HAL_OK; + 3116 .loc 1 2003 21 + 3117 000e 0023 movs r3, #0 + 3118 0010 FB75 strb r3, [r7, #23] +2004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2005:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check rx dma handle */ +2006:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); +2007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2008:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->State != HAL_SPI_STATE_READY) + 3119 .loc 1 2008 11 + 3120 0012 FB68 ldr r3, [r7, #12] + 3121 0014 93F85D30 ldrb r3, [r3, #93] + 3122 0018 DBB2 uxtb r3, r3 + 3123 .loc 1 2008 6 + 3124 001a 012B cmp r3, #1 + 3125 001c 02D0 beq .L171 +2009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2010:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_BUSY; + ARM GAS /tmp/ccs34gJO.s page 91 + + + 3126 .loc 1 2010 15 + 3127 001e 0223 movs r3, #2 + 3128 0020 FB75 strb r3, [r7, #23] +2011:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 3129 .loc 1 2011 5 + 3130 0022 0CE1 b .L172 + 3131 .L171: +2012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2013:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2014:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) + 3132 .loc 1 2014 18 + 3133 0024 FB68 ldr r3, [r7, #12] + 3134 0026 9B68 ldr r3, [r3, #8] + 3135 .loc 1 2014 6 + 3136 0028 002B cmp r3, #0 + 3137 002a 10D1 bne .L173 + 3138 .loc 1 2014 68 discriminator 1 + 3139 002c FB68 ldr r3, [r7, #12] + 3140 002e 5B68 ldr r3, [r3, #4] + 3141 .loc 1 2014 54 discriminator 1 + 3142 0030 B3F5827F cmp r3, #260 + 3143 0034 0BD1 bne .L173 +2015:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_BUSY_RX; + 3144 .loc 1 2016 17 + 3145 0036 FB68 ldr r3, [r7, #12] + 3146 0038 0422 movs r2, #4 + 3147 003a 83F85D20 strb r2, [r3, #93] +2017:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2018:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check tx dma handle */ +2019:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); +2020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2021:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line +2022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size); + 3148 .loc 1 2022 12 + 3149 003e FB88 ldrh r3, [r7, #6] + 3150 0040 BA68 ldr r2, [r7, #8] + 3151 0042 B968 ldr r1, [r7, #8] + 3152 0044 F868 ldr r0, [r7, #12] + 3153 0046 FFF7FEFF bl HAL_SPI_TransmitReceive_DMA + 3154 004a 0346 mov r3, r0 + 3155 004c FCE0 b .L174 + 3156 .L173: +2023:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2025:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Process Locked */ +2026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_LOCK(hspi); + 3157 .loc 1 2026 3 + 3158 004e FB68 ldr r3, [r7, #12] + 3159 0050 93F85C30 ldrb r3, [r3, #92] @ zero_extendqisi2 + 3160 0054 012B cmp r3, #1 + 3161 0056 01D1 bne .L175 + 3162 .loc 1 2026 3 is_stmt 0 discriminator 1 + 3163 0058 0223 movs r3, #2 + 3164 .loc 1 2026 3 + 3165 005a F5E0 b .L174 + 3166 .L175: + ARM GAS /tmp/ccs34gJO.s page 92 + + + 3167 .loc 1 2026 3 discriminator 2 + 3168 005c FB68 ldr r3, [r7, #12] + 3169 005e 0122 movs r2, #1 + 3170 0060 83F85C20 strb r2, [r3, #92] +2027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2028:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((pData == NULL) || (Size == 0U)) + 3171 .loc 1 2028 6 is_stmt 1 + 3172 0064 BB68 ldr r3, [r7, #8] + 3173 0066 002B cmp r3, #0 + 3174 0068 02D0 beq .L176 + 3175 .loc 1 2028 23 discriminator 1 + 3176 006a FB88 ldrh r3, [r7, #6] + 3177 006c 002B cmp r3, #0 + 3178 006e 02D1 bne .L177 + 3179 .L176: +2029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2030:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; + 3180 .loc 1 2030 15 + 3181 0070 0123 movs r3, #1 + 3182 0072 FB75 strb r3, [r7, #23] +2031:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 3183 .loc 1 2031 5 + 3184 0074 E3E0 b .L172 + 3185 .L177: +2032:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2033:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the transaction information */ +2035:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_BUSY_RX; + 3186 .loc 1 2035 21 + 3187 0076 FB68 ldr r3, [r7, #12] + 3188 0078 0422 movs r2, #4 + 3189 007a 83F85D20 strb r2, [r3, #93] +2036:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 3190 .loc 1 2036 21 + 3191 007e FB68 ldr r3, [r7, #12] + 3192 0080 0022 movs r2, #0 + 3193 0082 1A66 str r2, [r3, #96] +2037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr = (uint8_t *)pData; + 3194 .loc 1 2037 21 + 3195 0084 FB68 ldr r3, [r7, #12] + 3196 0086 BA68 ldr r2, [r7, #8] + 3197 0088 1A64 str r2, [r3, #64] +2038:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferSize = Size; + 3198 .loc 1 2038 21 + 3199 008a FB68 ldr r3, [r7, #12] + 3200 008c FA88 ldrh r2, [r7, #6] @ movhi + 3201 008e A3F84420 strh r2, [r3, #68] @ movhi +2039:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = Size; + 3202 .loc 1 2039 21 + 3203 0092 FB68 ldr r3, [r7, #12] + 3204 0094 FA88 ldrh r2, [r7, #6] @ movhi + 3205 0096 A3F84620 strh r2, [r3, #70] @ movhi +2040:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2041:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /*Init field not used in handle to zero */ +2042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxISR = NULL; + 3206 .loc 1 2042 21 + 3207 009a FB68 ldr r3, [r7, #12] + ARM GAS /tmp/ccs34gJO.s page 93 + + + 3208 009c 0022 movs r2, #0 + 3209 009e DA64 str r2, [r3, #76] +2043:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxISR = NULL; + 3210 .loc 1 2043 21 + 3211 00a0 FB68 ldr r3, [r7, #12] + 3212 00a2 0022 movs r2, #0 + 3213 00a4 1A65 str r2, [r3, #80] +2044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferSize = 0U; + 3214 .loc 1 2044 21 + 3215 00a6 FB68 ldr r3, [r7, #12] + 3216 00a8 0022 movs r2, #0 + 3217 00aa 9A87 strh r2, [r3, #60] @ movhi +2045:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = 0U; + 3218 .loc 1 2045 21 + 3219 00ac FB68 ldr r3, [r7, #12] + 3220 00ae 0022 movs r2, #0 + 3221 00b0 DA87 strh r2, [r3, #62] @ movhi +2046:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Configure communication direction : 1Line */ +2048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + 3222 .loc 1 2048 17 + 3223 00b2 FB68 ldr r3, [r7, #12] + 3224 00b4 9B68 ldr r3, [r3, #8] + 3225 .loc 1 2048 6 + 3226 00b6 B3F5004F cmp r3, #32768 + 3227 00ba 0FD1 bne .L178 +2049:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2050:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ +2051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE(hspi); + 3228 .loc 1 2051 5 + 3229 00bc FB68 ldr r3, [r7, #12] + 3230 00be 1B68 ldr r3, [r3] + 3231 00c0 1A68 ldr r2, [r3] + 3232 00c2 FB68 ldr r3, [r7, #12] + 3233 00c4 1B68 ldr r3, [r3] + 3234 00c6 22F04002 bic r2, r2, #64 + 3235 00ca 1A60 str r2, [r3] +2052:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_1LINE_RX(hspi); + 3236 .loc 1 2052 5 + 3237 00cc FB68 ldr r3, [r7, #12] + 3238 00ce 1B68 ldr r3, [r3] + 3239 00d0 1A68 ldr r2, [r3] + 3240 00d2 FB68 ldr r3, [r7, #12] + 3241 00d4 1B68 ldr r3, [r3] + 3242 00d6 22F48042 bic r2, r2, #16384 + 3243 00da 1A60 str r2, [r3] + 3244 .L178: +2053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2055:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +2056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset CRC Calculation */ +2057:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +2058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_RESET_CRC(hspi); +2060:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +2062:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + ARM GAS /tmp/ccs34gJO.s page 94 + + +2063:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if defined (STM32F302xC) || defined (STM32F303xC) || defined (STM32F373xC) || defined (STM32F358xx +2064:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Packing mode management is enabled by the DMA settings */ +2065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDA + 3245 .loc 1 2065 18 + 3246 00dc FB68 ldr r3, [r7, #12] + 3247 00de DB68 ldr r3, [r3, #12] + 3248 .loc 1 2065 6 + 3249 00e0 B3F5E06F cmp r3, #1792 + 3250 00e4 08D8 bhi .L179 + 3251 .loc 1 2065 58 discriminator 1 + 3252 00e6 FB68 ldr r3, [r7, #12] + 3253 00e8 9B6D ldr r3, [r3, #88] + 3254 .loc 1 2065 72 discriminator 1 + 3255 00ea 5B69 ldr r3, [r3, #20] + 3256 .loc 1 2065 50 discriminator 1 + 3257 00ec B3F5806F cmp r3, #1024 + 3258 00f0 02D1 bne .L179 +2066:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2067:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Restriction the DMA data received is not allowed in this mode */ +2068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; + 3259 .loc 1 2068 15 + 3260 00f2 0123 movs r3, #1 + 3261 00f4 FB75 strb r3, [r7, #23] +2069:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 3262 .loc 1 2069 5 + 3263 00f6 A2E0 b .L172 + 3264 .L179: +2070:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* STM32F302xC || STM32F303xC || STM32F373xC || STM32F358xx || STM32F378xx */ +2072:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2073:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); + 3265 .loc 1 2073 3 + 3266 00f8 FB68 ldr r3, [r7, #12] + 3267 00fa 1B68 ldr r3, [r3] + 3268 00fc 5A68 ldr r2, [r3, #4] + 3269 00fe FB68 ldr r3, [r7, #12] + 3270 0100 1B68 ldr r3, [r3] + 3271 0102 22F40052 bic r2, r2, #8192 + 3272 0106 5A60 str r2, [r3, #4] +2074:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + 3273 .loc 1 2074 17 + 3274 0108 FB68 ldr r3, [r7, #12] + 3275 010a DB68 ldr r3, [r3, #12] + 3276 .loc 1 2074 6 + 3277 010c B3F5E06F cmp r3, #1792 + 3278 0110 08D9 bls .L180 +2075:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2076:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set RX Fifo threshold according the reception data length: 16bit */ +2077:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + 3279 .loc 1 2077 5 + 3280 0112 FB68 ldr r3, [r7, #12] + 3281 0114 1B68 ldr r3, [r3] + 3282 0116 5A68 ldr r2, [r3, #4] + 3283 0118 FB68 ldr r3, [r7, #12] + 3284 011a 1B68 ldr r3, [r3] + 3285 011c 22F48052 bic r2, r2, #4096 + 3286 0120 5A60 str r2, [r3, #4] + ARM GAS /tmp/ccs34gJO.s page 95 + + + 3287 0122 42E0 b .L181 + 3288 .L180: +2078:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2079:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +2080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2081:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set RX Fifo threshold according the reception data length: 8bit */ +2082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + 3289 .loc 1 2082 5 + 3290 0124 FB68 ldr r3, [r7, #12] + 3291 0126 1B68 ldr r3, [r3] + 3292 0128 5A68 ldr r2, [r3, #4] + 3293 012a FB68 ldr r3, [r7, #12] + 3294 012c 1B68 ldr r3, [r3] + 3295 012e 42F48052 orr r2, r2, #4096 + 3296 0132 5A60 str r2, [r3, #4] +2083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2084:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) + 3297 .loc 1 2084 13 + 3298 0134 FB68 ldr r3, [r7, #12] + 3299 0136 9B6D ldr r3, [r3, #88] + 3300 .loc 1 2084 27 + 3301 0138 5B69 ldr r3, [r3, #20] + 3302 .loc 1 2084 8 + 3303 013a B3F5806F cmp r3, #1024 + 3304 013e 34D1 bne .L181 +2085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2086:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set RX Fifo threshold according the reception data length: 16bit */ +2087:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + 3305 .loc 1 2087 7 + 3306 0140 FB68 ldr r3, [r7, #12] + 3307 0142 1B68 ldr r3, [r3] + 3308 0144 5A68 ldr r2, [r3, #4] + 3309 0146 FB68 ldr r3, [r7, #12] + 3310 0148 1B68 ldr r3, [r3] + 3311 014a 22F48052 bic r2, r2, #4096 + 3312 014e 5A60 str r2, [r3, #4] +2088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2089:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->RxXferCount & 0x1U) == 0x0U) + 3313 .loc 1 2089 16 + 3314 0150 FB68 ldr r3, [r7, #12] + 3315 0152 B3F84630 ldrh r3, [r3, #70] @ movhi + 3316 0156 9BB2 uxth r3, r3 + 3317 .loc 1 2089 30 + 3318 0158 03F00103 and r3, r3, #1 + 3319 .loc 1 2089 10 + 3320 015c 002B cmp r3, #0 + 3321 015e 11D1 bne .L182 +2090:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2091:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); + 3322 .loc 1 2091 9 + 3323 0160 FB68 ldr r3, [r7, #12] + 3324 0162 1B68 ldr r3, [r3] + 3325 0164 5A68 ldr r2, [r3, #4] + 3326 0166 FB68 ldr r3, [r7, #12] + 3327 0168 1B68 ldr r3, [r3] + 3328 016a 22F40052 bic r2, r2, #8192 + 3329 016e 5A60 str r2, [r3, #4] + ARM GAS /tmp/ccs34gJO.s page 96 + + +2092:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = hspi->RxXferCount >> 1U; + 3330 .loc 1 2092 33 + 3331 0170 FB68 ldr r3, [r7, #12] + 3332 0172 B3F84630 ldrh r3, [r3, #70] @ movhi + 3333 0176 9BB2 uxth r3, r3 + 3334 .loc 1 2092 27 + 3335 0178 5B08 lsrs r3, r3, #1 + 3336 017a 9AB2 uxth r2, r3 + 3337 017c FB68 ldr r3, [r7, #12] + 3338 017e A3F84620 strh r2, [r3, #70] @ movhi + 3339 0182 12E0 b .L181 + 3340 .L182: +2093:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2094:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +2095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2096:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); + 3341 .loc 1 2096 9 + 3342 0184 FB68 ldr r3, [r7, #12] + 3343 0186 1B68 ldr r3, [r3] + 3344 0188 5A68 ldr r2, [r3, #4] + 3345 018a FB68 ldr r3, [r7, #12] + 3346 018c 1B68 ldr r3, [r3] + 3347 018e 42F40052 orr r2, r2, #8192 + 3348 0192 5A60 str r2, [r3, #4] +2097:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U; + 3349 .loc 1 2097 34 + 3350 0194 FB68 ldr r3, [r7, #12] + 3351 0196 B3F84630 ldrh r3, [r3, #70] @ movhi + 3352 019a 9BB2 uxth r3, r3 + 3353 .loc 1 2097 55 + 3354 019c 5B08 lsrs r3, r3, #1 + 3355 019e 9BB2 uxth r3, r3 + 3356 01a0 0133 adds r3, r3, #1 + 3357 01a2 9AB2 uxth r2, r3 + 3358 .loc 1 2097 27 + 3359 01a4 FB68 ldr r3, [r7, #12] + 3360 01a6 A3F84620 strh r2, [r3, #70] @ movhi + 3361 .L181: +2098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2099:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the SPI RxDMA Half transfer complete callback */ +2103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; + 3362 .loc 1 2103 7 + 3363 01aa FB68 ldr r3, [r7, #12] + 3364 01ac 9B6D ldr r3, [r3, #88] + 3365 .loc 1 2103 38 + 3366 01ae 284A ldr r2, .L185 + 3367 01b0 DA62 str r2, [r3, #44] +2104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the SPI Rx DMA transfer complete callback */ +2106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; + 3368 .loc 1 2106 7 + 3369 01b2 FB68 ldr r3, [r7, #12] + 3370 01b4 9B6D ldr r3, [r3, #88] + 3371 .loc 1 2106 34 + ARM GAS /tmp/ccs34gJO.s page 97 + + + 3372 01b6 274A ldr r2, .L185+4 + 3373 01b8 9A62 str r2, [r3, #40] +2107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the DMA error callback */ +2109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmarx->XferErrorCallback = SPI_DMAError; + 3374 .loc 1 2109 7 + 3375 01ba FB68 ldr r3, [r7, #12] + 3376 01bc 9B6D ldr r3, [r3, #88] + 3377 .loc 1 2109 35 + 3378 01be 264A ldr r2, .L185+8 + 3379 01c0 1A63 str r2, [r3, #48] +2110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the DMA AbortCpltCallback */ +2112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmarx->XferAbortCallback = NULL; + 3380 .loc 1 2112 7 + 3381 01c2 FB68 ldr r3, [r7, #12] + 3382 01c4 9B6D ldr r3, [r3, #88] + 3383 .loc 1 2112 35 + 3384 01c6 0022 movs r2, #0 + 3385 01c8 5A63 str r2, [r3, #52] +2113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable the Rx DMA Stream/Channel */ +2115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBu + 3386 .loc 1 2115 17 + 3387 01ca FB68 ldr r3, [r7, #12] + 3388 01cc 986D ldr r0, [r3, #88] + 3389 .loc 1 2115 63 + 3390 01ce FB68 ldr r3, [r7, #12] + 3391 01d0 1B68 ldr r3, [r3] + 3392 .loc 1 2115 58 + 3393 01d2 0C33 adds r3, r3, #12 + 3394 .loc 1 2115 17 + 3395 01d4 1946 mov r1, r3 + 3396 .loc 1 2115 93 + 3397 01d6 FB68 ldr r3, [r7, #12] + 3398 01d8 1B6C ldr r3, [r3, #64] + 3399 .loc 1 2115 17 + 3400 01da 1A46 mov r2, r3 +2116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount)) + 3401 .loc 1 2116 38 + 3402 01dc FB68 ldr r3, [r7, #12] + 3403 01de B3F84630 ldrh r3, [r3, #70] @ movhi + 3404 01e2 9BB2 uxth r3, r3 +2115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount)) + 3405 .loc 1 2115 17 + 3406 01e4 FFF7FEFF bl HAL_DMA_Start_IT + 3407 01e8 0346 mov r3, r0 +2115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount)) + 3408 .loc 1 2115 6 discriminator 1 + 3409 01ea 002B cmp r3, #0 + 3410 01ec 08D0 beq .L183 +2117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Update SPI error code */ +2119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + 3411 .loc 1 2119 5 + 3412 01ee FB68 ldr r3, [r7, #12] + 3413 01f0 1B6E ldr r3, [r3, #96] + ARM GAS /tmp/ccs34gJO.s page 98 + + + 3414 01f2 43F01002 orr r2, r3, #16 + 3415 01f6 FB68 ldr r3, [r7, #12] + 3416 01f8 1A66 str r2, [r3, #96] +2120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; + 3417 .loc 1 2120 15 + 3418 01fa 0123 movs r3, #1 + 3419 01fc FB75 strb r3, [r7, #23] +2121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 3420 .loc 1 2122 5 + 3421 01fe 1EE0 b .L172 + 3422 .L183: +2123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check if the SPI is already enabled */ +2126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + 3423 .loc 1 2126 12 + 3424 0200 FB68 ldr r3, [r7, #12] + 3425 0202 1B68 ldr r3, [r3] + 3426 .loc 1 2126 22 + 3427 0204 1B68 ldr r3, [r3] + 3428 .loc 1 2126 28 + 3429 0206 03F04003 and r3, r3, #64 + 3430 .loc 1 2126 6 + 3431 020a 402B cmp r3, #64 + 3432 020c 07D0 beq .L184 +2127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable SPI peripheral */ +2129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_ENABLE(hspi); + 3433 .loc 1 2129 5 + 3434 020e FB68 ldr r3, [r7, #12] + 3435 0210 1B68 ldr r3, [r3] + 3436 0212 1A68 ldr r2, [r3] + 3437 0214 FB68 ldr r3, [r7, #12] + 3438 0216 1B68 ldr r3, [r3] + 3439 0218 42F04002 orr r2, r2, #64 + 3440 021c 1A60 str r2, [r3] + 3441 .L184: +2130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable the SPI Error Interrupt Bit */ +2133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); + 3442 .loc 1 2133 3 + 3443 021e FB68 ldr r3, [r7, #12] + 3444 0220 1B68 ldr r3, [r3] + 3445 0222 5A68 ldr r2, [r3, #4] + 3446 0224 FB68 ldr r3, [r7, #12] + 3447 0226 1B68 ldr r3, [r3] + 3448 0228 42F02002 orr r2, r2, #32 + 3449 022c 5A60 str r2, [r3, #4] +2134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable Rx DMA Request */ +2136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + 3450 .loc 1 2136 3 + 3451 022e FB68 ldr r3, [r7, #12] + 3452 0230 1B68 ldr r3, [r3] + 3453 0232 5A68 ldr r2, [r3, #4] + ARM GAS /tmp/ccs34gJO.s page 99 + + + 3454 0234 FB68 ldr r3, [r7, #12] + 3455 0236 1B68 ldr r3, [r3] + 3456 0238 42F00102 orr r2, r2, #1 + 3457 023c 5A60 str r2, [r3, #4] + 3458 .L172: +2137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** error: +2139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Process Unlocked */ +2140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_UNLOCK(hspi); + 3459 .loc 1 2140 3 + 3460 023e FB68 ldr r3, [r7, #12] + 3461 0240 0022 movs r2, #0 + 3462 0242 83F85C20 strb r2, [r3, #92] +2141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; + 3463 .loc 1 2141 10 + 3464 0246 FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 3465 .L174: +2142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 3466 .loc 1 2142 1 + 3467 0248 1846 mov r0, r3 + 3468 024a 1837 adds r7, r7, #24 + 3469 .cfi_def_cfa_offset 8 + 3470 024c BD46 mov sp, r7 + 3471 .cfi_def_cfa_register 13 + 3472 @ sp needed + 3473 024e 80BD pop {r7, pc} + 3474 .L186: + 3475 .align 2 + 3476 .L185: + 3477 0250 00000000 .word SPI_DMAHalfReceiveCplt + 3478 0254 00000000 .word SPI_DMAReceiveCplt + 3479 0258 00000000 .word SPI_DMAError + 3480 .cfi_endproc + 3481 .LFE141: + 3483 .section .text.HAL_SPI_TransmitReceive_DMA,"ax",%progbits + 3484 .align 1 + 3485 .global HAL_SPI_TransmitReceive_DMA + 3486 .syntax unified + 3487 .thumb + 3488 .thumb_func + 3490 HAL_SPI_TransmitReceive_DMA: + 3491 .LFB142: +2143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +2145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Transmit and Receive an amount of data in non-blocking mode with DMA. +2146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +2147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +2148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param pTxData pointer to transmission data buffer +2149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param pRxData pointer to reception data buffer +2150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @note When the CRC feature is enabled the pRxData Length must be Size + 1 +2151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param Size amount of data to be sent +2152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval HAL status +2153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *p +2155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint16_t Size) +2156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 3492 .loc 1 2156 1 + ARM GAS /tmp/ccs34gJO.s page 100 + + + 3493 .cfi_startproc + 3494 @ args = 0, pretend = 0, frame = 24 + 3495 @ frame_needed = 1, uses_anonymous_args = 0 + 3496 0000 80B5 push {r7, lr} + 3497 .cfi_def_cfa_offset 8 + 3498 .cfi_offset 7, -8 + 3499 .cfi_offset 14, -4 + 3500 0002 86B0 sub sp, sp, #24 + 3501 .cfi_def_cfa_offset 32 + 3502 0004 00AF add r7, sp, #0 + 3503 .cfi_def_cfa_register 7 + 3504 0006 F860 str r0, [r7, #12] + 3505 0008 B960 str r1, [r7, #8] + 3506 000a 7A60 str r2, [r7, #4] + 3507 000c 7B80 strh r3, [r7, #2] @ movhi +2157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t tmp_mode; +2158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_StateTypeDef tmp_state; +2159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef errorcode = HAL_OK; + 3508 .loc 1 2159 21 + 3509 000e 0023 movs r3, #0 + 3510 0010 FB75 strb r3, [r7, #23] +2160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check rx & tx dma handles */ +2162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); +2163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); +2164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check Direction parameter */ +2166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); +2167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Process locked */ +2169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_LOCK(hspi); + 3511 .loc 1 2169 3 + 3512 0012 FB68 ldr r3, [r7, #12] + 3513 0014 93F85C30 ldrb r3, [r3, #92] @ zero_extendqisi2 + 3514 0018 012B cmp r3, #1 + 3515 001a 01D1 bne .L188 + 3516 .loc 1 2169 3 is_stmt 0 discriminator 1 + 3517 001c 0223 movs r3, #2 + 3518 .loc 1 2169 3 + 3519 001e 72E1 b .L189 + 3520 .L188: + 3521 .loc 1 2169 3 discriminator 2 + 3522 0020 FB68 ldr r3, [r7, #12] + 3523 0022 0122 movs r2, #1 + 3524 0024 83F85C20 strb r2, [r3, #92] +2170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Init temporary variables */ +2172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmp_state = hspi->State; + 3525 .loc 1 2172 23 is_stmt 1 + 3526 0028 FB68 ldr r3, [r7, #12] + 3527 002a 93F85D30 ldrb r3, [r3, #93] + 3528 002e BB75 strb r3, [r7, #22] +2173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmp_mode = hspi->Init.Mode; + 3529 .loc 1 2173 23 + 3530 0030 FB68 ldr r3, [r7, #12] + 3531 0032 5B68 ldr r3, [r3, #4] + 3532 0034 3B61 str r3, [r7, #16] + ARM GAS /tmp/ccs34gJO.s page 101 + + +2174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (!((tmp_state == HAL_SPI_STATE_READY) || + 3533 .loc 1 2175 6 + 3534 0036 BB7D ldrb r3, [r7, #22] @ zero_extendqisi2 + 3535 0038 012B cmp r3, #1 + 3536 003a 0DD0 beq .L190 + 3537 .loc 1 2175 7 discriminator 1 + 3538 003c 3B69 ldr r3, [r7, #16] + 3539 003e B3F5827F cmp r3, #260 + 3540 0042 06D1 bne .L191 +2176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_st + 3541 .loc 1 2176 54 + 3542 0044 FB68 ldr r3, [r7, #12] + 3543 0046 9B68 ldr r3, [r3, #8] + 3544 .loc 1 2176 40 + 3545 0048 002B cmp r3, #0 + 3546 004a 02D1 bne .L191 + 3547 .loc 1 2176 90 discriminator 1 + 3548 004c BB7D ldrb r3, [r7, #22] @ zero_extendqisi2 + 3549 004e 042B cmp r3, #4 + 3550 0050 02D0 beq .L190 + 3551 .L191: +2177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_BUSY; + 3552 .loc 1 2178 15 + 3553 0052 0223 movs r3, #2 + 3554 0054 FB75 strb r3, [r7, #23] +2179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 3555 .loc 1 2179 5 + 3556 0056 51E1 b .L192 + 3557 .L190: +2180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + 3558 .loc 1 2182 6 + 3559 0058 BB68 ldr r3, [r7, #8] + 3560 005a 002B cmp r3, #0 + 3561 005c 05D0 beq .L193 + 3562 .loc 1 2182 25 discriminator 1 + 3563 005e 7B68 ldr r3, [r7, #4] + 3564 0060 002B cmp r3, #0 + 3565 0062 02D0 beq .L193 + 3566 .loc 1 2182 46 discriminator 2 + 3567 0064 7B88 ldrh r3, [r7, #2] + 3568 0066 002B cmp r3, #0 + 3569 0068 02D1 bne .L194 + 3570 .L193: +2183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; + 3571 .loc 1 2184 15 + 3572 006a 0123 movs r3, #1 + 3573 006c FB75 strb r3, [r7, #23] +2185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 3574 .loc 1 2185 5 + 3575 006e 45E1 b .L192 + 3576 .L194: +2186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + ARM GAS /tmp/ccs34gJO.s page 102 + + +2187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ +2189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->State != HAL_SPI_STATE_BUSY_RX) + 3577 .loc 1 2189 11 + 3578 0070 FB68 ldr r3, [r7, #12] + 3579 0072 93F85D30 ldrb r3, [r3, #93] + 3580 0076 DBB2 uxtb r3, r3 + 3581 .loc 1 2189 6 + 3582 0078 042B cmp r3, #4 + 3583 007a 03D0 beq .L195 +2190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + 3584 .loc 1 2191 17 + 3585 007c FB68 ldr r3, [r7, #12] + 3586 007e 0522 movs r2, #5 + 3587 0080 83F85D20 strb r2, [r3, #93] + 3588 .L195: +2192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the transaction information */ +2195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 3589 .loc 1 2195 21 + 3590 0084 FB68 ldr r3, [r7, #12] + 3591 0086 0022 movs r2, #0 + 3592 0088 1A66 str r2, [r3, #96] +2196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr = (uint8_t *)pTxData; + 3593 .loc 1 2196 21 + 3594 008a FB68 ldr r3, [r7, #12] + 3595 008c BA68 ldr r2, [r7, #8] + 3596 008e 9A63 str r2, [r3, #56] +2197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferSize = Size; + 3597 .loc 1 2197 21 + 3598 0090 FB68 ldr r3, [r7, #12] + 3599 0092 7A88 ldrh r2, [r7, #2] @ movhi + 3600 0094 9A87 strh r2, [r3, #60] @ movhi +2198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = Size; + 3601 .loc 1 2198 21 + 3602 0096 FB68 ldr r3, [r7, #12] + 3603 0098 7A88 ldrh r2, [r7, #2] @ movhi + 3604 009a DA87 strh r2, [r3, #62] @ movhi +2199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr = (uint8_t *)pRxData; + 3605 .loc 1 2199 21 + 3606 009c FB68 ldr r3, [r7, #12] + 3607 009e 7A68 ldr r2, [r7, #4] + 3608 00a0 1A64 str r2, [r3, #64] +2200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferSize = Size; + 3609 .loc 1 2200 21 + 3610 00a2 FB68 ldr r3, [r7, #12] + 3611 00a4 7A88 ldrh r2, [r7, #2] @ movhi + 3612 00a6 A3F84420 strh r2, [r3, #68] @ movhi +2201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = Size; + 3613 .loc 1 2201 21 + 3614 00aa FB68 ldr r3, [r7, #12] + 3615 00ac 7A88 ldrh r2, [r7, #2] @ movhi + 3616 00ae A3F84620 strh r2, [r3, #70] @ movhi +2202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Init field not used in handle to zero */ + ARM GAS /tmp/ccs34gJO.s page 103 + + +2204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxISR = NULL; + 3617 .loc 1 2204 21 + 3618 00b2 FB68 ldr r3, [r7, #12] + 3619 00b4 0022 movs r2, #0 + 3620 00b6 DA64 str r2, [r3, #76] +2205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxISR = NULL; + 3621 .loc 1 2205 21 + 3622 00b8 FB68 ldr r3, [r7, #12] + 3623 00ba 0022 movs r2, #0 + 3624 00bc 1A65 str r2, [r3, #80] +2206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +2208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset CRC Calculation */ +2209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +2210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_RESET_CRC(hspi); +2212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +2214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if defined (STM32F302xC) || defined (STM32F303xC) || defined (STM32F373xC) || defined (STM32F358xx +2216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Packing mode management is enabled by the DMA settings */ +2217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDA + 3625 .loc 1 2217 18 + 3626 00be FB68 ldr r3, [r7, #12] + 3627 00c0 DB68 ldr r3, [r3, #12] + 3628 .loc 1 2217 6 + 3629 00c2 B3F5E06F cmp r3, #1792 + 3630 00c6 08D8 bhi .L196 + 3631 .loc 1 2217 58 discriminator 1 + 3632 00c8 FB68 ldr r3, [r7, #12] + 3633 00ca 9B6D ldr r3, [r3, #88] + 3634 .loc 1 2217 72 discriminator 1 + 3635 00cc 5B69 ldr r3, [r3, #20] + 3636 .loc 1 2217 50 discriminator 1 + 3637 00ce B3F5806F cmp r3, #1024 + 3638 00d2 02D1 bne .L196 +2218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Restriction the DMA data received is not allowed in this mode */ +2220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; + 3639 .loc 1 2220 15 + 3640 00d4 0123 movs r3, #1 + 3641 00d6 FB75 strb r3, [r7, #23] +2221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 3642 .loc 1 2221 5 + 3643 00d8 10E1 b .L192 + 3644 .L196: +2222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* STM32F302xC || STM32F303xC || STM32F373xC || STM32F358xx || STM32F378xx */ +2224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset the threshold bit */ +2226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX); + 3645 .loc 1 2226 3 + 3646 00da FB68 ldr r3, [r7, #12] + 3647 00dc 1B68 ldr r3, [r3] + 3648 00de 5A68 ldr r2, [r3, #4] + 3649 00e0 FB68 ldr r3, [r7, #12] + 3650 00e2 1B68 ldr r3, [r3] + ARM GAS /tmp/ccs34gJO.s page 104 + + + 3651 00e4 22F4C042 bic r2, r2, #24576 + 3652 00e8 5A60 str r2, [r3, #4] +2227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* The packing mode management is enabled by the DMA settings according the spi data size */ +2229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + 3653 .loc 1 2229 17 + 3654 00ea FB68 ldr r3, [r7, #12] + 3655 00ec DB68 ldr r3, [r3, #12] + 3656 .loc 1 2229 6 + 3657 00ee B3F5E06F cmp r3, #1792 + 3658 00f2 08D9 bls .L197 +2230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set fiforxthreshold according the reception data length: 16bit */ +2232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + 3659 .loc 1 2232 5 + 3660 00f4 FB68 ldr r3, [r7, #12] + 3661 00f6 1B68 ldr r3, [r3] + 3662 00f8 5A68 ldr r2, [r3, #4] + 3663 00fa FB68 ldr r3, [r7, #12] + 3664 00fc 1B68 ldr r3, [r3] + 3665 00fe 22F48052 bic r2, r2, #4096 + 3666 0102 5A60 str r2, [r3, #4] + 3667 0104 6FE0 b .L198 + 3668 .L197: +2233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +2235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set RX Fifo threshold according the reception data length: 8bit */ +2237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + 3669 .loc 1 2237 5 + 3670 0106 FB68 ldr r3, [r7, #12] + 3671 0108 1B68 ldr r3, [r3] + 3672 010a 5A68 ldr r2, [r3, #4] + 3673 010c FB68 ldr r3, [r7, #12] + 3674 010e 1B68 ldr r3, [r3] + 3675 0110 42F48052 orr r2, r2, #4096 + 3676 0114 5A60 str r2, [r3, #4] +2238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) + 3677 .loc 1 2239 13 + 3678 0116 FB68 ldr r3, [r7, #12] + 3679 0118 5B6D ldr r3, [r3, #84] + 3680 .loc 1 2239 27 + 3681 011a 5B69 ldr r3, [r3, #20] + 3682 .loc 1 2239 8 + 3683 011c B3F5806F cmp r3, #1024 + 3684 0120 26D1 bne .L199 +2240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->TxXferSize & 0x1U) == 0x0U) + 3685 .loc 1 2241 16 + 3686 0122 FB68 ldr r3, [r7, #12] + 3687 0124 9B8F ldrh r3, [r3, #60] + 3688 .loc 1 2241 29 + 3689 0126 03F00103 and r3, r3, #1 + 3690 .loc 1 2241 10 + 3691 012a 002B cmp r3, #0 + 3692 012c 0FD1 bne .L200 + ARM GAS /tmp/ccs34gJO.s page 105 + + +2242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); + 3693 .loc 1 2243 9 + 3694 012e FB68 ldr r3, [r7, #12] + 3695 0130 1B68 ldr r3, [r3] + 3696 0132 5A68 ldr r2, [r3, #4] + 3697 0134 FB68 ldr r3, [r7, #12] + 3698 0136 1B68 ldr r3, [r3] + 3699 0138 22F48042 bic r2, r2, #16384 + 3700 013c 5A60 str r2, [r3, #4] +2244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = hspi->TxXferCount >> 1U; + 3701 .loc 1 2244 33 + 3702 013e FB68 ldr r3, [r7, #12] + 3703 0140 DB8F ldrh r3, [r3, #62] @ movhi + 3704 0142 9BB2 uxth r3, r3 + 3705 .loc 1 2244 27 + 3706 0144 5B08 lsrs r3, r3, #1 + 3707 0146 9AB2 uxth r2, r3 + 3708 0148 FB68 ldr r3, [r7, #12] + 3709 014a DA87 strh r2, [r3, #62] @ movhi + 3710 014c 10E0 b .L199 + 3711 .L200: +2245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +2247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); + 3712 .loc 1 2248 9 + 3713 014e FB68 ldr r3, [r7, #12] + 3714 0150 1B68 ldr r3, [r3] + 3715 0152 5A68 ldr r2, [r3, #4] + 3716 0154 FB68 ldr r3, [r7, #12] + 3717 0156 1B68 ldr r3, [r3] + 3718 0158 42F48042 orr r2, r2, #16384 + 3719 015c 5A60 str r2, [r3, #4] +2249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U; + 3720 .loc 1 2249 34 + 3721 015e FB68 ldr r3, [r7, #12] + 3722 0160 DB8F ldrh r3, [r3, #62] @ movhi + 3723 0162 9BB2 uxth r3, r3 + 3724 .loc 1 2249 55 + 3725 0164 5B08 lsrs r3, r3, #1 + 3726 0166 9BB2 uxth r3, r3 + 3727 0168 0133 adds r3, r3, #1 + 3728 016a 9AB2 uxth r2, r3 + 3729 .loc 1 2249 27 + 3730 016c FB68 ldr r3, [r7, #12] + 3731 016e DA87 strh r2, [r3, #62] @ movhi + 3732 .L199: +2250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) + 3733 .loc 1 2253 13 + 3734 0170 FB68 ldr r3, [r7, #12] + 3735 0172 9B6D ldr r3, [r3, #88] + 3736 .loc 1 2253 27 + 3737 0174 5B69 ldr r3, [r3, #20] + ARM GAS /tmp/ccs34gJO.s page 106 + + + 3738 .loc 1 2253 8 + 3739 0176 B3F5806F cmp r3, #1024 + 3740 017a 34D1 bne .L198 +2254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set RX Fifo threshold according the reception data length: 16bit */ +2256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + 3741 .loc 1 2256 7 + 3742 017c FB68 ldr r3, [r7, #12] + 3743 017e 1B68 ldr r3, [r3] + 3744 0180 5A68 ldr r2, [r3, #4] + 3745 0182 FB68 ldr r3, [r7, #12] + 3746 0184 1B68 ldr r3, [r3] + 3747 0186 22F48052 bic r2, r2, #4096 + 3748 018a 5A60 str r2, [r3, #4] +2257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->RxXferCount & 0x1U) == 0x0U) + 3749 .loc 1 2258 16 + 3750 018c FB68 ldr r3, [r7, #12] + 3751 018e B3F84630 ldrh r3, [r3, #70] @ movhi + 3752 0192 9BB2 uxth r3, r3 + 3753 .loc 1 2258 30 + 3754 0194 03F00103 and r3, r3, #1 + 3755 .loc 1 2258 10 + 3756 0198 002B cmp r3, #0 + 3757 019a 11D1 bne .L201 +2259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); + 3758 .loc 1 2260 9 + 3759 019c FB68 ldr r3, [r7, #12] + 3760 019e 1B68 ldr r3, [r3] + 3761 01a0 5A68 ldr r2, [r3, #4] + 3762 01a2 FB68 ldr r3, [r7, #12] + 3763 01a4 1B68 ldr r3, [r3] + 3764 01a6 22F40052 bic r2, r2, #8192 + 3765 01aa 5A60 str r2, [r3, #4] +2261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = hspi->RxXferCount >> 1U; + 3766 .loc 1 2261 33 + 3767 01ac FB68 ldr r3, [r7, #12] + 3768 01ae B3F84630 ldrh r3, [r3, #70] @ movhi + 3769 01b2 9BB2 uxth r3, r3 + 3770 .loc 1 2261 27 + 3771 01b4 5B08 lsrs r3, r3, #1 + 3772 01b6 9AB2 uxth r2, r3 + 3773 01b8 FB68 ldr r3, [r7, #12] + 3774 01ba A3F84620 strh r2, [r3, #70] @ movhi + 3775 01be 12E0 b .L198 + 3776 .L201: +2262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +2264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); + 3777 .loc 1 2265 9 + 3778 01c0 FB68 ldr r3, [r7, #12] + 3779 01c2 1B68 ldr r3, [r3] + 3780 01c4 5A68 ldr r2, [r3, #4] + 3781 01c6 FB68 ldr r3, [r7, #12] + 3782 01c8 1B68 ldr r3, [r3] + ARM GAS /tmp/ccs34gJO.s page 107 + + + 3783 01ca 42F40052 orr r2, r2, #8192 + 3784 01ce 5A60 str r2, [r3, #4] +2266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U; + 3785 .loc 1 2266 34 + 3786 01d0 FB68 ldr r3, [r7, #12] + 3787 01d2 B3F84630 ldrh r3, [r3, #70] @ movhi + 3788 01d6 9BB2 uxth r3, r3 + 3789 .loc 1 2266 55 + 3790 01d8 5B08 lsrs r3, r3, #1 + 3791 01da 9BB2 uxth r3, r3 + 3792 01dc 0133 adds r3, r3, #1 + 3793 01de 9AB2 uxth r2, r3 + 3794 .loc 1 2266 27 + 3795 01e0 FB68 ldr r3, [r7, #12] + 3796 01e2 A3F84620 strh r2, [r3, #70] @ movhi + 3797 .L198: +2267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback * +2272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->State == HAL_SPI_STATE_BUSY_RX) + 3798 .loc 1 2272 11 + 3799 01e6 FB68 ldr r3, [r7, #12] + 3800 01e8 93F85D30 ldrb r3, [r3, #93] + 3801 01ec DBB2 uxtb r3, r3 + 3802 .loc 1 2272 6 + 3803 01ee 042B cmp r3, #4 + 3804 01f0 08D1 bne .L202 +2273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the SPI Rx DMA Half transfer complete callback */ +2275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; + 3805 .loc 1 2275 9 + 3806 01f2 FB68 ldr r3, [r7, #12] + 3807 01f4 9B6D ldr r3, [r3, #88] + 3808 .loc 1 2275 40 + 3809 01f6 464A ldr r2, .L207 + 3810 01f8 DA62 str r2, [r3, #44] +2276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; + 3811 .loc 1 2276 9 + 3812 01fa FB68 ldr r3, [r7, #12] + 3813 01fc 9B6D ldr r3, [r3, #88] + 3814 .loc 1 2276 40 + 3815 01fe 454A ldr r2, .L207+4 + 3816 0200 9A62 str r2, [r3, #40] + 3817 0202 07E0 b .L203 + 3818 .L202: +2277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +2279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the SPI Tx/Rx DMA Half transfer complete callback */ +2281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt; + 3819 .loc 1 2281 9 + 3820 0204 FB68 ldr r3, [r7, #12] + 3821 0206 9B6D ldr r3, [r3, #88] + 3822 .loc 1 2281 40 + 3823 0208 434A ldr r2, .L207+8 + ARM GAS /tmp/ccs34gJO.s page 108 + + + 3824 020a DA62 str r2, [r3, #44] +2282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt; + 3825 .loc 1 2282 9 + 3826 020c FB68 ldr r3, [r7, #12] + 3827 020e 9B6D ldr r3, [r3, #88] + 3828 .loc 1 2282 40 + 3829 0210 424A ldr r2, .L207+12 + 3830 0212 9A62 str r2, [r3, #40] + 3831 .L203: +2283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the DMA error callback */ +2286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmarx->XferErrorCallback = SPI_DMAError; + 3832 .loc 1 2286 7 + 3833 0214 FB68 ldr r3, [r7, #12] + 3834 0216 9B6D ldr r3, [r3, #88] + 3835 .loc 1 2286 35 + 3836 0218 414A ldr r2, .L207+16 + 3837 021a 1A63 str r2, [r3, #48] +2287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the DMA AbortCpltCallback */ +2289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmarx->XferAbortCallback = NULL; + 3838 .loc 1 2289 7 + 3839 021c FB68 ldr r3, [r7, #12] + 3840 021e 9B6D ldr r3, [r3, #88] + 3841 .loc 1 2289 35 + 3842 0220 0022 movs r2, #0 + 3843 0222 5A63 str r2, [r3, #52] +2290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable the Rx DMA Stream/Channel */ +2292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBu + 3844 .loc 1 2292 17 + 3845 0224 FB68 ldr r3, [r7, #12] + 3846 0226 986D ldr r0, [r3, #88] + 3847 .loc 1 2292 63 + 3848 0228 FB68 ldr r3, [r7, #12] + 3849 022a 1B68 ldr r3, [r3] + 3850 .loc 1 2292 58 + 3851 022c 0C33 adds r3, r3, #12 + 3852 .loc 1 2292 17 + 3853 022e 1946 mov r1, r3 + 3854 .loc 1 2292 93 + 3855 0230 FB68 ldr r3, [r7, #12] + 3856 0232 1B6C ldr r3, [r3, #64] + 3857 .loc 1 2292 17 + 3858 0234 1A46 mov r2, r3 +2293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount)) + 3859 .loc 1 2293 38 + 3860 0236 FB68 ldr r3, [r7, #12] + 3861 0238 B3F84630 ldrh r3, [r3, #70] @ movhi + 3862 023c 9BB2 uxth r3, r3 +2292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount)) + 3863 .loc 1 2292 17 + 3864 023e FFF7FEFF bl HAL_DMA_Start_IT + 3865 0242 0346 mov r3, r0 +2292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount)) + 3866 .loc 1 2292 6 discriminator 1 + ARM GAS /tmp/ccs34gJO.s page 109 + + + 3867 0244 002B cmp r3, #0 + 3868 0246 08D0 beq .L204 +2294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Update SPI error code */ +2296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + 3869 .loc 1 2296 5 + 3870 0248 FB68 ldr r3, [r7, #12] + 3871 024a 1B6E ldr r3, [r3, #96] + 3872 024c 43F01002 orr r2, r3, #16 + 3873 0250 FB68 ldr r3, [r7, #12] + 3874 0252 1A66 str r2, [r3, #96] +2297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; + 3875 .loc 1 2297 15 + 3876 0254 0123 movs r3, #1 + 3877 0256 FB75 strb r3, [r7, #23] +2298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 3878 .loc 1 2299 5 + 3879 0258 50E0 b .L192 + 3880 .L204: +2300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable Rx DMA Request */ +2303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + 3881 .loc 1 2303 3 + 3882 025a FB68 ldr r3, [r7, #12] + 3883 025c 1B68 ldr r3, [r3] + 3884 025e 5A68 ldr r2, [r3, #4] + 3885 0260 FB68 ldr r3, [r7, #12] + 3886 0262 1B68 ldr r3, [r3] + 3887 0264 42F00102 orr r2, r2, #1 + 3888 0268 5A60 str r2, [r3, #4] +2304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing +2306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** is performed in DMA reception complete callback */ +2307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmatx->XferHalfCpltCallback = NULL; + 3889 .loc 1 2307 7 + 3890 026a FB68 ldr r3, [r7, #12] + 3891 026c 5B6D ldr r3, [r3, #84] + 3892 .loc 1 2307 38 + 3893 026e 0022 movs r2, #0 + 3894 0270 DA62 str r2, [r3, #44] +2308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmatx->XferCpltCallback = NULL; + 3895 .loc 1 2308 7 + 3896 0272 FB68 ldr r3, [r7, #12] + 3897 0274 5B6D ldr r3, [r3, #84] + 3898 .loc 1 2308 38 + 3899 0276 0022 movs r2, #0 + 3900 0278 9A62 str r2, [r3, #40] +2309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmatx->XferErrorCallback = NULL; + 3901 .loc 1 2309 7 + 3902 027a FB68 ldr r3, [r7, #12] + 3903 027c 5B6D ldr r3, [r3, #84] + 3904 .loc 1 2309 38 + 3905 027e 0022 movs r2, #0 + 3906 0280 1A63 str r2, [r3, #48] +2310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmatx->XferAbortCallback = NULL; + ARM GAS /tmp/ccs34gJO.s page 110 + + + 3907 .loc 1 2310 7 + 3908 0282 FB68 ldr r3, [r7, #12] + 3909 0284 5B6D ldr r3, [r3, #84] + 3910 .loc 1 2310 38 + 3911 0286 0022 movs r2, #0 + 3912 0288 5A63 str r2, [r3, #52] +2311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable the Tx DMA Stream/Channel */ +2313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instanc + 3913 .loc 1 2313 17 + 3914 028a FB68 ldr r3, [r7, #12] + 3915 028c 586D ldr r0, [r3, #84] + 3916 .loc 1 2313 62 + 3917 028e FB68 ldr r3, [r7, #12] + 3918 0290 9B6B ldr r3, [r3, #56] + 3919 .loc 1 2313 17 + 3920 0292 1946 mov r1, r3 + 3921 .loc 1 2313 91 + 3922 0294 FB68 ldr r3, [r7, #12] + 3923 0296 1B68 ldr r3, [r3] + 3924 .loc 1 2313 86 + 3925 0298 0C33 adds r3, r3, #12 + 3926 .loc 1 2313 17 + 3927 029a 1A46 mov r2, r3 +2314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount)) + 3928 .loc 1 2314 38 + 3929 029c FB68 ldr r3, [r7, #12] + 3930 029e DB8F ldrh r3, [r3, #62] @ movhi + 3931 02a0 9BB2 uxth r3, r3 +2313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount)) + 3932 .loc 1 2313 17 + 3933 02a2 FFF7FEFF bl HAL_DMA_Start_IT + 3934 02a6 0346 mov r3, r0 +2313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount)) + 3935 .loc 1 2313 6 discriminator 1 + 3936 02a8 002B cmp r3, #0 + 3937 02aa 08D0 beq .L205 +2315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Update SPI error code */ +2317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + 3938 .loc 1 2317 5 + 3939 02ac FB68 ldr r3, [r7, #12] + 3940 02ae 1B6E ldr r3, [r3, #96] + 3941 02b0 43F01002 orr r2, r3, #16 + 3942 02b4 FB68 ldr r3, [r7, #12] + 3943 02b6 1A66 str r2, [r3, #96] +2318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; + 3944 .loc 1 2318 15 + 3945 02b8 0123 movs r3, #1 + 3946 02ba FB75 strb r3, [r7, #23] +2319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** goto error; + 3947 .loc 1 2320 5 + 3948 02bc 1EE0 b .L192 + 3949 .L205: +2321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + ARM GAS /tmp/ccs34gJO.s page 111 + + +2323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check if the SPI is already enabled */ +2324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + 3950 .loc 1 2324 12 + 3951 02be FB68 ldr r3, [r7, #12] + 3952 02c0 1B68 ldr r3, [r3] + 3953 .loc 1 2324 22 + 3954 02c2 1B68 ldr r3, [r3] + 3955 .loc 1 2324 28 + 3956 02c4 03F04003 and r3, r3, #64 + 3957 .loc 1 2324 6 + 3958 02c8 402B cmp r3, #64 + 3959 02ca 07D0 beq .L206 +2325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable SPI peripheral */ +2327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_ENABLE(hspi); + 3960 .loc 1 2327 5 + 3961 02cc FB68 ldr r3, [r7, #12] + 3962 02ce 1B68 ldr r3, [r3] + 3963 02d0 1A68 ldr r2, [r3] + 3964 02d2 FB68 ldr r3, [r7, #12] + 3965 02d4 1B68 ldr r3, [r3] + 3966 02d6 42F04002 orr r2, r2, #64 + 3967 02da 1A60 str r2, [r3] + 3968 .L206: +2328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable the SPI Error Interrupt Bit */ +2330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); + 3969 .loc 1 2330 3 + 3970 02dc FB68 ldr r3, [r7, #12] + 3971 02de 1B68 ldr r3, [r3] + 3972 02e0 5A68 ldr r2, [r3, #4] + 3973 02e2 FB68 ldr r3, [r7, #12] + 3974 02e4 1B68 ldr r3, [r3] + 3975 02e6 42F02002 orr r2, r2, #32 + 3976 02ea 5A60 str r2, [r3, #4] +2331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable Tx DMA Request */ +2333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + 3977 .loc 1 2333 3 + 3978 02ec FB68 ldr r3, [r7, #12] + 3979 02ee 1B68 ldr r3, [r3] + 3980 02f0 5A68 ldr r2, [r3, #4] + 3981 02f2 FB68 ldr r3, [r7, #12] + 3982 02f4 1B68 ldr r3, [r3] + 3983 02f6 42F00202 orr r2, r2, #2 + 3984 02fa 5A60 str r2, [r3, #4] + 3985 .L192: +2334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** error : +2336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Process Unlocked */ +2337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_UNLOCK(hspi); + 3986 .loc 1 2337 3 + 3987 02fc FB68 ldr r3, [r7, #12] + 3988 02fe 0022 movs r2, #0 + 3989 0300 83F85C20 strb r2, [r3, #92] +2338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; + 3990 .loc 1 2338 10 + ARM GAS /tmp/ccs34gJO.s page 112 + + + 3991 0304 FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 3992 .L189: +2339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 3993 .loc 1 2339 1 + 3994 0306 1846 mov r0, r3 + 3995 0308 1837 adds r7, r7, #24 + 3996 .cfi_def_cfa_offset 8 + 3997 030a BD46 mov sp, r7 + 3998 .cfi_def_cfa_register 13 + 3999 @ sp needed + 4000 030c 80BD pop {r7, pc} + 4001 .L208: + 4002 030e 00BF .align 2 + 4003 .L207: + 4004 0310 00000000 .word SPI_DMAHalfReceiveCplt + 4005 0314 00000000 .word SPI_DMAReceiveCplt + 4006 0318 00000000 .word SPI_DMAHalfTransmitReceiveCplt + 4007 031c 00000000 .word SPI_DMATransmitReceiveCplt + 4008 0320 00000000 .word SPI_DMAError + 4009 .cfi_endproc + 4010 .LFE142: + 4012 .section .text.HAL_SPI_Abort,"ax",%progbits + 4013 .align 1 + 4014 .global HAL_SPI_Abort + 4015 .syntax unified + 4016 .thumb + 4017 .thumb_func + 4019 HAL_SPI_Abort: + 4020 .LFB143: +2340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +2342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Abort ongoing transfer (blocking mode). +2343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi SPI handle. +2344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx), +2345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * started in Interrupt or DMA mode. +2346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * This procedure performs following operations : +2347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * - Disable SPI Interrupts (depending of transfer direction) +2348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * - Disable the DMA transfer in the peripheral register (if enabled) +2349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) +2350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * - Set handle State to READY +2351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @note This procedure is executed in blocking mode : when exiting function, Abort is considere +2352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval HAL status +2353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) +2355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4021 .loc 1 2355 1 + 4022 .cfi_startproc + 4023 @ args = 0, pretend = 0, frame = 32 + 4024 @ frame_needed = 1, uses_anonymous_args = 0 + 4025 0000 80B5 push {r7, lr} + 4026 .cfi_def_cfa_offset 8 + 4027 .cfi_offset 7, -8 + 4028 .cfi_offset 14, -4 + 4029 0002 8AB0 sub sp, sp, #40 + 4030 .cfi_def_cfa_offset 48 + 4031 0004 02AF add r7, sp, #8 + 4032 .cfi_def_cfa 7, 40 + ARM GAS /tmp/ccs34gJO.s page 113 + + + 4033 0006 7860 str r0, [r7, #4] +2356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef errorcode; +2357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint32_t count; +2358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint32_t resetcount; +2359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Initialized local variable */ +2361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_OK; + 4034 .loc 1 2361 13 + 4035 0008 0023 movs r3, #0 + 4036 000a FB77 strb r3, [r7, #31] +2362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + 4037 .loc 1 2362 61 + 4038 000c 884B ldr r3, .L228 + 4039 000e 1B68 ldr r3, [r3] + 4040 0010 884A ldr r2, .L228+4 + 4041 0012 A2FB0323 umull r2, r3, r2, r3 + 4042 0016 5B0A lsrs r3, r3, #9 + 4043 .loc 1 2362 36 + 4044 0018 6422 movs r2, #100 + 4045 001a 02FB03F3 mul r3, r2, r3 + 4046 .loc 1 2362 14 + 4047 001e 7B61 str r3, [r7, #20] +2363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** count = resetcount; + 4048 .loc 1 2363 9 + 4049 0020 7B69 ldr r3, [r7, #20] + 4050 0022 BB61 str r3, [r7, #24] +2364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */ +2366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE); + 4051 .loc 1 2366 3 + 4052 0024 7B68 ldr r3, [r7, #4] + 4053 0026 1B68 ldr r3, [r3] + 4054 0028 5A68 ldr r2, [r3, #4] + 4055 002a 7B68 ldr r3, [r7, #4] + 4056 002c 1B68 ldr r3, [r3] + 4057 002e 22F02002 bic r2, r2, #32 + 4058 0032 5A60 str r2, [r3, #4] +2367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */ +2369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)) + 4059 .loc 1 2369 7 + 4060 0034 7B68 ldr r3, [r7, #4] + 4061 0036 1B68 ldr r3, [r3] + 4062 0038 5B68 ldr r3, [r3, #4] + 4063 003a 03F08003 and r3, r3, #128 + 4064 .loc 1 2369 6 + 4065 003e 802B cmp r3, #128 + 4066 0040 17D1 bne .L210 +2370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxISR = SPI_AbortTx_ISR; + 4067 .loc 1 2371 17 + 4068 0042 7B68 ldr r3, [r7, #4] + 4069 0044 7C4A ldr r2, .L228+8 + 4070 0046 1A65 str r2, [r3, #80] + 4071 .L213: +2372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Wait HAL_SPI_STATE_ABORT state */ +2373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** do + ARM GAS /tmp/ccs34gJO.s page 114 + + +2374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (count == 0U) + 4072 .loc 1 2375 17 + 4073 0048 BB69 ldr r3, [r7, #24] + 4074 .loc 1 2375 10 + 4075 004a 002B cmp r3, #0 + 4076 004c 06D1 bne .L211 +2376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + 4077 .loc 1 2377 9 + 4078 004e 7B68 ldr r3, [r7, #4] + 4079 0050 1B6E ldr r3, [r3, #96] + 4080 0052 43F04002 orr r2, r3, #64 + 4081 0056 7B68 ldr r3, [r7, #4] + 4082 0058 1A66 str r2, [r3, #96] +2378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 4083 .loc 1 2378 9 + 4084 005a 08E0 b .L212 + 4085 .L211: +2379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** count--; + 4086 .loc 1 2380 12 + 4087 005c BB69 ldr r3, [r7, #24] + 4088 005e 013B subs r3, r3, #1 + 4089 0060 BB61 str r3, [r7, #24] +2381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } while (hspi->State != HAL_SPI_STATE_ABORT); + 4090 .loc 1 2381 18 + 4091 0062 7B68 ldr r3, [r7, #4] + 4092 0064 93F85D30 ldrb r3, [r3, #93] + 4093 0068 DBB2 uxtb r3, r3 + 4094 .loc 1 2381 26 + 4095 006a 072B cmp r3, #7 + 4096 006c ECD1 bne .L213 + 4097 .L212: +2382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset Timeout Counter */ +2383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** count = resetcount; + 4098 .loc 1 2383 11 + 4099 006e 7B69 ldr r3, [r7, #20] + 4100 0070 BB61 str r3, [r7, #24] + 4101 .L210: +2384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) + 4102 .loc 1 2386 7 + 4103 0072 7B68 ldr r3, [r7, #4] + 4104 0074 1B68 ldr r3, [r3] + 4105 0076 5B68 ldr r3, [r3, #4] + 4106 0078 03F04003 and r3, r3, #64 + 4107 .loc 1 2386 6 + 4108 007c 402B cmp r3, #64 + 4109 007e 17D1 bne .L214 +2387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxISR = SPI_AbortRx_ISR; + 4110 .loc 1 2388 17 + 4111 0080 7B68 ldr r3, [r7, #4] + 4112 0082 6E4A ldr r2, .L228+12 + 4113 0084 DA64 str r2, [r3, #76] + ARM GAS /tmp/ccs34gJO.s page 115 + + + 4114 .L217: +2389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Wait HAL_SPI_STATE_ABORT state */ +2390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** do +2391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (count == 0U) + 4115 .loc 1 2392 17 + 4116 0086 BB69 ldr r3, [r7, #24] + 4117 .loc 1 2392 10 + 4118 0088 002B cmp r3, #0 + 4119 008a 06D1 bne .L215 +2393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + 4120 .loc 1 2394 9 + 4121 008c 7B68 ldr r3, [r7, #4] + 4122 008e 1B6E ldr r3, [r3, #96] + 4123 0090 43F04002 orr r2, r3, #64 + 4124 0094 7B68 ldr r3, [r7, #4] + 4125 0096 1A66 str r2, [r3, #96] +2395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 4126 .loc 1 2395 9 + 4127 0098 08E0 b .L216 + 4128 .L215: +2396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** count--; + 4129 .loc 1 2397 12 + 4130 009a BB69 ldr r3, [r7, #24] + 4131 009c 013B subs r3, r3, #1 + 4132 009e BB61 str r3, [r7, #24] +2398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } while (hspi->State != HAL_SPI_STATE_ABORT); + 4133 .loc 1 2398 18 + 4134 00a0 7B68 ldr r3, [r7, #4] + 4135 00a2 93F85D30 ldrb r3, [r3, #93] + 4136 00a6 DBB2 uxtb r3, r3 + 4137 .loc 1 2398 26 + 4138 00a8 072B cmp r3, #7 + 4139 00aa ECD1 bne .L217 + 4140 .L216: +2399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset Timeout Counter */ +2400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** count = resetcount; + 4141 .loc 1 2400 11 + 4142 00ac 7B69 ldr r3, [r7, #20] + 4143 00ae BB61 str r3, [r7, #24] + 4144 .L214: +2401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable the SPI DMA Tx request if enabled */ +2404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) + 4145 .loc 1 2404 7 + 4146 00b0 7B68 ldr r3, [r7, #4] + 4147 00b2 1B68 ldr r3, [r3] + 4148 00b4 5B68 ldr r3, [r3, #4] + 4149 00b6 03F00203 and r3, r3, #2 + 4150 .loc 1 2404 6 + 4151 00ba 022B cmp r3, #2 + 4152 00bc 41D1 bne .L218 +2405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */ + ARM GAS /tmp/ccs34gJO.s page 116 + + +2407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->hdmatx != NULL) + 4153 .loc 1 2407 13 + 4154 00be 7B68 ldr r3, [r7, #4] + 4155 00c0 5B6D ldr r3, [r3, #84] + 4156 .loc 1 2407 8 + 4157 00c2 002B cmp r3, #0 + 4158 00c4 3DD0 beq .L218 +2408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the SPI DMA Abort callback : +2410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */ +2411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmatx->XferAbortCallback = NULL; + 4159 .loc 1 2411 11 + 4160 00c6 7B68 ldr r3, [r7, #4] + 4161 00c8 5B6D ldr r3, [r3, #84] + 4162 .loc 1 2411 39 + 4163 00ca 0022 movs r2, #0 + 4164 00cc 5A63 str r2, [r3, #52] +2412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Abort DMA Tx Handle linked to SPI Peripheral */ +2414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK) + 4165 .loc 1 2414 11 + 4166 00ce 7B68 ldr r3, [r7, #4] + 4167 00d0 5B6D ldr r3, [r3, #84] + 4168 00d2 1846 mov r0, r3 + 4169 00d4 FFF7FEFF bl HAL_DMA_Abort + 4170 00d8 0346 mov r3, r0 + 4171 .loc 1 2414 10 discriminator 1 + 4172 00da 002B cmp r3, #0 + 4173 00dc 02D0 beq .L219 +2415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + 4174 .loc 1 2416 25 + 4175 00de 7B68 ldr r3, [r7, #4] + 4176 00e0 4022 movs r2, #64 + 4177 00e2 1A66 str r2, [r3, #96] + 4178 .L219: +2417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable Tx DMA Request */ +2420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN)); + 4179 .loc 1 2420 7 + 4180 00e4 7B68 ldr r3, [r7, #4] + 4181 00e6 1B68 ldr r3, [r3] + 4182 00e8 5A68 ldr r2, [r3, #4] + 4183 00ea 7B68 ldr r3, [r7, #4] + 4184 00ec 1B68 ldr r3, [r3] + 4185 00ee 22F00202 bic r2, r2, #2 + 4186 00f2 5A60 str r2, [r3, #4] +2421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + 4187 .loc 1 2422 11 + 4188 00f4 FFF7FEFF bl HAL_GetTick + 4189 00f8 0346 mov r3, r0 + 4190 .loc 1 2422 11 is_stmt 0 discriminator 1 + 4191 00fa 1A46 mov r2, r3 + 4192 00fc 6421 movs r1, #100 + 4193 00fe 7868 ldr r0, [r7, #4] + ARM GAS /tmp/ccs34gJO.s page 117 + + + 4194 0100 FFF7FEFF bl SPI_EndRxTxTransaction + 4195 0104 0346 mov r3, r0 + 4196 .loc 1 2422 10 is_stmt 1 discriminator 2 + 4197 0106 002B cmp r3, #0 + 4198 0108 02D0 beq .L220 +2423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + 4199 .loc 1 2424 25 + 4200 010a 7B68 ldr r3, [r7, #4] + 4201 010c 4022 movs r2, #64 + 4202 010e 1A66 str r2, [r3, #96] + 4203 .L220: +2425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable SPI Peripheral */ +2428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE(hspi); + 4204 .loc 1 2428 7 + 4205 0110 7B68 ldr r3, [r7, #4] + 4206 0112 1B68 ldr r3, [r3] + 4207 0114 1A68 ldr r2, [r3] + 4208 0116 7B68 ldr r3, [r7, #4] + 4209 0118 1B68 ldr r3, [r3] + 4210 011a 22F04002 bic r2, r2, #64 + 4211 011e 1A60 str r2, [r3] +2429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Empty the FRLVL fifo */ +2431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + 4212 .loc 1 2431 11 + 4213 0120 FFF7FEFF bl HAL_GetTick + 4214 0124 0346 mov r3, r0 + 4215 .loc 1 2431 11 is_stmt 0 discriminator 1 + 4216 0126 0093 str r3, [sp] + 4217 0128 6423 movs r3, #100 + 4218 012a 0022 movs r2, #0 + 4219 012c 4FF4C061 mov r1, #1536 + 4220 0130 7868 ldr r0, [r7, #4] + 4221 0132 FFF7FEFF bl SPI_WaitFifoStateUntilTimeout + 4222 0136 0346 mov r3, r0 + 4223 .loc 1 2431 10 is_stmt 1 discriminator 2 + 4224 0138 002B cmp r3, #0 + 4225 013a 02D0 beq .L218 +2432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + 4226 .loc 1 2433 25 + 4227 013c 7B68 ldr r3, [r7, #4] + 4228 013e 4022 movs r2, #64 + 4229 0140 1A66 str r2, [r3, #96] + 4230 .L218: +2434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable the SPI DMA Rx request if enabled */ +2439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)) + 4231 .loc 1 2439 7 + 4232 0142 7B68 ldr r3, [r7, #4] + 4233 0144 1B68 ldr r3, [r3] + ARM GAS /tmp/ccs34gJO.s page 118 + + + 4234 0146 5B68 ldr r3, [r3, #4] + 4235 0148 03F00103 and r3, r3, #1 + 4236 .loc 1 2439 6 + 4237 014c 012B cmp r3, #1 + 4238 014e 43D1 bne .L221 +2440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */ +2442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->hdmarx != NULL) + 4239 .loc 1 2442 13 + 4240 0150 7B68 ldr r3, [r7, #4] + 4241 0152 9B6D ldr r3, [r3, #88] + 4242 .loc 1 2442 8 + 4243 0154 002B cmp r3, #0 + 4244 0156 3FD0 beq .L221 +2443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the SPI DMA Abort callback : +2445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */ +2446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmarx->XferAbortCallback = NULL; + 4245 .loc 1 2446 11 + 4246 0158 7B68 ldr r3, [r7, #4] + 4247 015a 9B6D ldr r3, [r3, #88] + 4248 .loc 1 2446 39 + 4249 015c 0022 movs r2, #0 + 4250 015e 5A63 str r2, [r3, #52] +2447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Abort DMA Rx Handle linked to SPI Peripheral */ +2449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK) + 4251 .loc 1 2449 11 + 4252 0160 7B68 ldr r3, [r7, #4] + 4253 0162 9B6D ldr r3, [r3, #88] + 4254 0164 1846 mov r0, r3 + 4255 0166 FFF7FEFF bl HAL_DMA_Abort + 4256 016a 0346 mov r3, r0 + 4257 .loc 1 2449 10 discriminator 1 + 4258 016c 002B cmp r3, #0 + 4259 016e 02D0 beq .L222 +2450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + 4260 .loc 1 2451 25 + 4261 0170 7B68 ldr r3, [r7, #4] + 4262 0172 4022 movs r2, #64 + 4263 0174 1A66 str r2, [r3, #96] + 4264 .L222: +2452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable peripheral */ +2455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE(hspi); + 4265 .loc 1 2455 7 + 4266 0176 7B68 ldr r3, [r7, #4] + 4267 0178 1B68 ldr r3, [r3] + 4268 017a 1A68 ldr r2, [r3] + 4269 017c 7B68 ldr r3, [r7, #4] + 4270 017e 1B68 ldr r3, [r3] + 4271 0180 22F04002 bic r2, r2, #64 + 4272 0184 1A60 str r2, [r3] +2456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Control the BSY flag */ + ARM GAS /tmp/ccs34gJO.s page 119 + + +2458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick + 4273 .loc 1 2458 11 + 4274 0186 FFF7FEFF bl HAL_GetTick + 4275 018a 0346 mov r3, r0 + 4276 .loc 1 2458 11 is_stmt 0 discriminator 1 + 4277 018c 0093 str r3, [sp] + 4278 018e 6423 movs r3, #100 + 4279 0190 0022 movs r2, #0 + 4280 0192 8021 movs r1, #128 + 4281 0194 7868 ldr r0, [r7, #4] + 4282 0196 FFF7FEFF bl SPI_WaitFlagStateUntilTimeout + 4283 019a 0346 mov r3, r0 + 4284 .loc 1 2458 10 is_stmt 1 discriminator 2 + 4285 019c 002B cmp r3, #0 + 4286 019e 02D0 beq .L223 +2459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + 4287 .loc 1 2460 25 + 4288 01a0 7B68 ldr r3, [r7, #4] + 4289 01a2 4022 movs r2, #64 + 4290 01a4 1A66 str r2, [r3, #96] + 4291 .L223: +2461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Empty the FRLVL fifo */ +2464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + 4292 .loc 1 2464 11 + 4293 01a6 FFF7FEFF bl HAL_GetTick + 4294 01aa 0346 mov r3, r0 + 4295 .loc 1 2464 11 is_stmt 0 discriminator 1 + 4296 01ac 0093 str r3, [sp] + 4297 01ae 6423 movs r3, #100 + 4298 01b0 0022 movs r2, #0 + 4299 01b2 4FF4C061 mov r1, #1536 + 4300 01b6 7868 ldr r0, [r7, #4] + 4301 01b8 FFF7FEFF bl SPI_WaitFifoStateUntilTimeout + 4302 01bc 0346 mov r3, r0 + 4303 .loc 1 2464 10 is_stmt 1 discriminator 2 + 4304 01be 002B cmp r3, #0 + 4305 01c0 02D0 beq .L224 +2465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + 4306 .loc 1 2466 25 + 4307 01c2 7B68 ldr r3, [r7, #4] + 4308 01c4 4022 movs r2, #64 + 4309 01c6 1A66 str r2, [r3, #96] + 4310 .L224: +2467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable Rx DMA Request */ +2470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN)); + 4311 .loc 1 2470 7 + 4312 01c8 7B68 ldr r3, [r7, #4] + 4313 01ca 1B68 ldr r3, [r3] + 4314 01cc 5A68 ldr r2, [r3, #4] + 4315 01ce 7B68 ldr r3, [r7, #4] + 4316 01d0 1B68 ldr r3, [r3] + ARM GAS /tmp/ccs34gJO.s page 120 + + + 4317 01d2 22F00102 bic r2, r2, #1 + 4318 01d6 5A60 str r2, [r3, #4] + 4319 .L221: +2471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset Tx and Rx transfer counters */ +2474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = 0U; + 4320 .loc 1 2474 21 + 4321 01d8 7B68 ldr r3, [r7, #4] + 4322 01da 0022 movs r2, #0 + 4323 01dc A3F84620 strh r2, [r3, #70] @ movhi +2475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = 0U; + 4324 .loc 1 2475 21 + 4325 01e0 7B68 ldr r3, [r7, #4] + 4326 01e2 0022 movs r2, #0 + 4327 01e4 DA87 strh r2, [r3, #62] @ movhi +2476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check error during Abort procedure */ +2478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT) + 4328 .loc 1 2478 11 + 4329 01e6 7B68 ldr r3, [r7, #4] + 4330 01e8 1B6E ldr r3, [r3, #96] + 4331 .loc 1 2478 6 + 4332 01ea 402B cmp r3, #64 + 4333 01ec 02D1 bne .L225 +2479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* return HAL_Error in case of error during Abort procedure */ +2481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; + 4334 .loc 1 2481 15 + 4335 01ee 0123 movs r3, #1 + 4336 01f0 FB77 strb r3, [r7, #31] + 4337 01f2 02E0 b .L226 + 4338 .L225: +2482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +2484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset errorCode */ +2486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 4339 .loc 1 2486 21 + 4340 01f4 7B68 ldr r3, [r7, #4] + 4341 01f6 0022 movs r2, #0 + 4342 01f8 1A66 str r2, [r3, #96] + 4343 .L226: + 4344 .LBB3: +2487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Clear the Error flags in the SR register */ +2490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_OVRFLAG(hspi); + 4345 .loc 1 2490 3 + 4346 01fa 0023 movs r3, #0 + 4347 01fc 3B61 str r3, [r7, #16] + 4348 01fe 7B68 ldr r3, [r7, #4] + 4349 0200 1B68 ldr r3, [r3] + 4350 0202 DB68 ldr r3, [r3, #12] + 4351 0204 3B61 str r3, [r7, #16] + 4352 0206 7B68 ldr r3, [r7, #4] + 4353 0208 1B68 ldr r3, [r3] + ARM GAS /tmp/ccs34gJO.s page 121 + + + 4354 020a 9B68 ldr r3, [r3, #8] + 4355 020c 3B61 str r3, [r7, #16] + 4356 020e 3B69 ldr r3, [r7, #16] + 4357 .LBE3: + 4358 .LBB4: +2491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_FREFLAG(hspi); + 4359 .loc 1 2491 3 + 4360 0210 0023 movs r3, #0 + 4361 0212 FB60 str r3, [r7, #12] + 4362 0214 7B68 ldr r3, [r7, #4] + 4363 0216 1B68 ldr r3, [r3] + 4364 0218 9B68 ldr r3, [r3, #8] + 4365 021a FB60 str r3, [r7, #12] + 4366 021c FB68 ldr r3, [r7, #12] + 4367 .LBE4: +2492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Restore hspi->state to ready */ +2494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; + 4368 .loc 1 2494 15 + 4369 021e 7B68 ldr r3, [r7, #4] + 4370 0220 0122 movs r2, #1 + 4371 0222 83F85D20 strb r2, [r3, #93] +2495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; + 4372 .loc 1 2496 10 + 4373 0226 FB7F ldrb r3, [r7, #31] @ zero_extendqisi2 +2497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4374 .loc 1 2497 1 + 4375 0228 1846 mov r0, r3 + 4376 022a 2037 adds r7, r7, #32 + 4377 .cfi_def_cfa_offset 8 + 4378 022c BD46 mov sp, r7 + 4379 .cfi_def_cfa_register 13 + 4380 @ sp needed + 4381 022e 80BD pop {r7, pc} + 4382 .L229: + 4383 .align 2 + 4384 .L228: + 4385 0230 00000000 .word SystemCoreClock + 4386 0234 F1197605 .word 91625969 + 4387 0238 00000000 .word SPI_AbortTx_ISR + 4388 023c 00000000 .word SPI_AbortRx_ISR + 4389 .cfi_endproc + 4390 .LFE143: + 4392 .section .text.HAL_SPI_Abort_IT,"ax",%progbits + 4393 .align 1 + 4394 .global HAL_SPI_Abort_IT + 4395 .syntax unified + 4396 .thumb + 4397 .thumb_func + 4399 HAL_SPI_Abort_IT: + 4400 .LFB144: +2498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +2500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Abort ongoing transfer (Interrupt mode). +2501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi SPI handle. +2502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx), + ARM GAS /tmp/ccs34gJO.s page 122 + + +2503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * started in Interrupt or DMA mode. +2504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * This procedure performs following operations : +2505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * - Disable SPI Interrupts (depending of transfer direction) +2506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * - Disable the DMA transfer in the peripheral register (if enabled) +2507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) +2508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * - Set handle State to READY +2509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * - At abort completion, call user abort complete callback +2510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be +2511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * considered as completed only when user abort complete callback is executed (not when ex +2512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval HAL status +2513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) +2515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4401 .loc 1 2515 1 + 4402 .cfi_startproc + 4403 @ args = 0, pretend = 0, frame = 32 + 4404 @ frame_needed = 1, uses_anonymous_args = 0 + 4405 0000 80B5 push {r7, lr} + 4406 .cfi_def_cfa_offset 8 + 4407 .cfi_offset 7, -8 + 4408 .cfi_offset 14, -4 + 4409 0002 88B0 sub sp, sp, #32 + 4410 .cfi_def_cfa_offset 40 + 4411 0004 00AF add r7, sp, #0 + 4412 .cfi_def_cfa_register 7 + 4413 0006 7860 str r0, [r7, #4] +2516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef errorcode; +2517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t abortcplt ; +2518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint32_t count; +2519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint32_t resetcount; +2520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Initialized local variable */ +2522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_OK; + 4414 .loc 1 2522 13 + 4415 0008 0023 movs r3, #0 + 4416 000a FB77 strb r3, [r7, #31] +2523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** abortcplt = 1U; + 4417 .loc 1 2523 13 + 4418 000c 0123 movs r3, #1 + 4419 000e BB61 str r3, [r7, #24] +2524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + 4420 .loc 1 2524 61 + 4421 0010 724B ldr r3, .L251 + 4422 0012 1B68 ldr r3, [r3] + 4423 0014 724A ldr r2, .L251+4 + 4424 0016 A2FB0323 umull r2, r3, r2, r3 + 4425 001a 5B0A lsrs r3, r3, #9 + 4426 .loc 1 2524 36 + 4427 001c 6422 movs r2, #100 + 4428 001e 02FB03F3 mul r3, r2, r3 + 4429 .loc 1 2524 14 + 4430 0022 3B61 str r3, [r7, #16] +2525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** count = resetcount; + 4431 .loc 1 2525 9 + 4432 0024 3B69 ldr r3, [r7, #16] + 4433 0026 7B61 str r3, [r7, #20] +2526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + ARM GAS /tmp/ccs34gJO.s page 123 + + +2527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */ +2528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE); + 4434 .loc 1 2528 3 + 4435 0028 7B68 ldr r3, [r7, #4] + 4436 002a 1B68 ldr r3, [r3] + 4437 002c 5A68 ldr r2, [r3, #4] + 4438 002e 7B68 ldr r3, [r7, #4] + 4439 0030 1B68 ldr r3, [r3] + 4440 0032 22F02002 bic r2, r2, #32 + 4441 0036 5A60 str r2, [r3, #4] +2529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */ +2531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)) + 4442 .loc 1 2531 7 + 4443 0038 7B68 ldr r3, [r7, #4] + 4444 003a 1B68 ldr r3, [r3] + 4445 003c 5B68 ldr r3, [r3, #4] + 4446 003e 03F08003 and r3, r3, #128 + 4447 .loc 1 2531 6 + 4448 0042 802B cmp r3, #128 + 4449 0044 17D1 bne .L231 +2532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxISR = SPI_AbortTx_ISR; + 4450 .loc 1 2533 17 + 4451 0046 7B68 ldr r3, [r7, #4] + 4452 0048 664A ldr r2, .L251+8 + 4453 004a 1A65 str r2, [r3, #80] + 4454 .L234: +2534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Wait HAL_SPI_STATE_ABORT state */ +2535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** do +2536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (count == 0U) + 4455 .loc 1 2537 17 + 4456 004c 7B69 ldr r3, [r7, #20] + 4457 .loc 1 2537 10 + 4458 004e 002B cmp r3, #0 + 4459 0050 06D1 bne .L232 +2538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + 4460 .loc 1 2539 9 + 4461 0052 7B68 ldr r3, [r7, #4] + 4462 0054 1B6E ldr r3, [r3, #96] + 4463 0056 43F04002 orr r2, r3, #64 + 4464 005a 7B68 ldr r3, [r7, #4] + 4465 005c 1A66 str r2, [r3, #96] +2540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 4466 .loc 1 2540 9 + 4467 005e 08E0 b .L233 + 4468 .L232: +2541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** count--; + 4469 .loc 1 2542 12 + 4470 0060 7B69 ldr r3, [r7, #20] + 4471 0062 013B subs r3, r3, #1 + 4472 0064 7B61 str r3, [r7, #20] +2543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } while (hspi->State != HAL_SPI_STATE_ABORT); + 4473 .loc 1 2543 18 + ARM GAS /tmp/ccs34gJO.s page 124 + + + 4474 0066 7B68 ldr r3, [r7, #4] + 4475 0068 93F85D30 ldrb r3, [r3, #93] + 4476 006c DBB2 uxtb r3, r3 + 4477 .loc 1 2543 26 + 4478 006e 072B cmp r3, #7 + 4479 0070 ECD1 bne .L234 + 4480 .L233: +2544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset Timeout Counter */ +2545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** count = resetcount; + 4481 .loc 1 2545 11 + 4482 0072 3B69 ldr r3, [r7, #16] + 4483 0074 7B61 str r3, [r7, #20] + 4484 .L231: +2546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) + 4485 .loc 1 2548 7 + 4486 0076 7B68 ldr r3, [r7, #4] + 4487 0078 1B68 ldr r3, [r3] + 4488 007a 5B68 ldr r3, [r3, #4] + 4489 007c 03F04003 and r3, r3, #64 + 4490 .loc 1 2548 6 + 4491 0080 402B cmp r3, #64 + 4492 0082 17D1 bne .L235 +2549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxISR = SPI_AbortRx_ISR; + 4493 .loc 1 2550 17 + 4494 0084 7B68 ldr r3, [r7, #4] + 4495 0086 584A ldr r2, .L251+12 + 4496 0088 DA64 str r2, [r3, #76] + 4497 .L238: +2551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Wait HAL_SPI_STATE_ABORT state */ +2552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** do +2553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (count == 0U) + 4498 .loc 1 2554 17 + 4499 008a 7B69 ldr r3, [r7, #20] + 4500 .loc 1 2554 10 + 4501 008c 002B cmp r3, #0 + 4502 008e 06D1 bne .L236 +2555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + 4503 .loc 1 2556 9 + 4504 0090 7B68 ldr r3, [r7, #4] + 4505 0092 1B6E ldr r3, [r3, #96] + 4506 0094 43F04002 orr r2, r3, #64 + 4507 0098 7B68 ldr r3, [r7, #4] + 4508 009a 1A66 str r2, [r3, #96] +2557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 4509 .loc 1 2557 9 + 4510 009c 08E0 b .L237 + 4511 .L236: +2558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** count--; + 4512 .loc 1 2559 12 + 4513 009e 7B69 ldr r3, [r7, #20] + 4514 00a0 013B subs r3, r3, #1 + ARM GAS /tmp/ccs34gJO.s page 125 + + + 4515 00a2 7B61 str r3, [r7, #20] +2560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } while (hspi->State != HAL_SPI_STATE_ABORT); + 4516 .loc 1 2560 18 + 4517 00a4 7B68 ldr r3, [r7, #4] + 4518 00a6 93F85D30 ldrb r3, [r3, #93] + 4519 00aa DBB2 uxtb r3, r3 + 4520 .loc 1 2560 26 + 4521 00ac 072B cmp r3, #7 + 4522 00ae ECD1 bne .L238 + 4523 .L237: +2561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset Timeout Counter */ +2562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** count = resetcount; + 4524 .loc 1 2562 11 + 4525 00b0 3B69 ldr r3, [r7, #16] + 4526 00b2 7B61 str r3, [r7, #20] + 4527 .L235: +2563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks sho +2566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** before any call to DMA Abort functions */ +2567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* DMA Tx Handle is valid */ +2568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->hdmatx != NULL) + 4528 .loc 1 2568 11 + 4529 00b4 7B68 ldr r3, [r7, #4] + 4530 00b6 5B6D ldr r3, [r3, #84] + 4531 .loc 1 2568 6 + 4532 00b8 002B cmp r3, #0 + 4533 00ba 0FD0 beq .L239 +2569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. +2571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** Otherwise, set it to NULL */ +2572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) + 4534 .loc 1 2572 9 + 4535 00bc 7B68 ldr r3, [r7, #4] + 4536 00be 1B68 ldr r3, [r3] + 4537 00c0 5B68 ldr r3, [r3, #4] + 4538 00c2 03F00203 and r3, r3, #2 + 4539 .loc 1 2572 8 + 4540 00c6 022B cmp r3, #2 + 4541 00c8 04D1 bne .L240 +2573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback; + 4542 .loc 1 2574 11 + 4543 00ca 7B68 ldr r3, [r7, #4] + 4544 00cc 5B6D ldr r3, [r3, #84] + 4545 .loc 1 2574 39 + 4546 00ce 474A ldr r2, .L251+16 + 4547 00d0 5A63 str r2, [r3, #52] + 4548 00d2 03E0 b .L239 + 4549 .L240: +2575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +2577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmatx->XferAbortCallback = NULL; + 4550 .loc 1 2578 11 + 4551 00d4 7B68 ldr r3, [r7, #4] + 4552 00d6 5B6D ldr r3, [r3, #84] + ARM GAS /tmp/ccs34gJO.s page 126 + + + 4553 .loc 1 2578 39 + 4554 00d8 0022 movs r2, #0 + 4555 00da 5A63 str r2, [r3, #52] + 4556 .L239: +2579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* DMA Rx Handle is valid */ +2582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->hdmarx != NULL) + 4557 .loc 1 2582 11 + 4558 00dc 7B68 ldr r3, [r7, #4] + 4559 00de 9B6D ldr r3, [r3, #88] + 4560 .loc 1 2582 6 + 4561 00e0 002B cmp r3, #0 + 4562 00e2 0FD0 beq .L241 +2583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. +2585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** Otherwise, set it to NULL */ +2586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)) + 4563 .loc 1 2586 9 + 4564 00e4 7B68 ldr r3, [r7, #4] + 4565 00e6 1B68 ldr r3, [r3] + 4566 00e8 5B68 ldr r3, [r3, #4] + 4567 00ea 03F00103 and r3, r3, #1 + 4568 .loc 1 2586 8 + 4569 00ee 012B cmp r3, #1 + 4570 00f0 04D1 bne .L242 +2587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback; + 4571 .loc 1 2588 11 + 4572 00f2 7B68 ldr r3, [r7, #4] + 4573 00f4 9B6D ldr r3, [r3, #88] + 4574 .loc 1 2588 39 + 4575 00f6 3E4A ldr r2, .L251+20 + 4576 00f8 5A63 str r2, [r3, #52] + 4577 00fa 03E0 b .L241 + 4578 .L242: +2589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +2591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmarx->XferAbortCallback = NULL; + 4579 .loc 1 2592 11 + 4580 00fc 7B68 ldr r3, [r7, #4] + 4581 00fe 9B6D ldr r3, [r3, #88] + 4582 .loc 1 2592 39 + 4583 0100 0022 movs r2, #0 + 4584 0102 5A63 str r2, [r3, #52] + 4585 .L241: +2593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable the SPI DMA Tx request if enabled */ +2597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) + 4586 .loc 1 2597 7 + 4587 0104 7B68 ldr r3, [r7, #4] + 4588 0106 1B68 ldr r3, [r3] + 4589 0108 5B68 ldr r3, [r3, #4] + 4590 010a 03F00203 and r3, r3, #2 + ARM GAS /tmp/ccs34gJO.s page 127 + + + 4591 .loc 1 2597 6 + 4592 010e 022B cmp r3, #2 + 4593 0110 15D1 bne .L243 +2598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Abort the SPI DMA Tx Stream/Channel */ +2600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->hdmatx != NULL) + 4594 .loc 1 2600 13 + 4595 0112 7B68 ldr r3, [r7, #4] + 4596 0114 5B6D ldr r3, [r3, #84] + 4597 .loc 1 2600 8 + 4598 0116 002B cmp r3, #0 + 4599 0118 11D0 beq .L243 +2601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2602:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Abort DMA Tx Handle linked to SPI Peripheral */ +2603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK) + 4600 .loc 1 2603 11 + 4601 011a 7B68 ldr r3, [r7, #4] + 4602 011c 5B6D ldr r3, [r3, #84] + 4603 011e 1846 mov r0, r3 + 4604 0120 FFF7FEFF bl HAL_DMA_Abort_IT + 4605 0124 0346 mov r3, r0 + 4606 .loc 1 2603 10 discriminator 1 + 4607 0126 002B cmp r3, #0 + 4608 0128 07D0 beq .L244 +2604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmatx->XferAbortCallback = NULL; + 4609 .loc 1 2605 13 + 4610 012a 7B68 ldr r3, [r7, #4] + 4611 012c 5B6D ldr r3, [r3, #84] + 4612 .loc 1 2605 41 + 4613 012e 0022 movs r2, #0 + 4614 0130 5A63 str r2, [r3, #52] +2606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + 4615 .loc 1 2606 25 + 4616 0132 7B68 ldr r3, [r7, #4] + 4617 0134 4022 movs r2, #64 + 4618 0136 1A66 str r2, [r3, #96] + 4619 0138 01E0 b .L243 + 4620 .L244: +2607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +2609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** abortcplt = 0U; + 4621 .loc 1 2610 19 + 4622 013a 0023 movs r3, #0 + 4623 013c BB61 str r3, [r7, #24] + 4624 .L243: +2611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2612:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable the SPI DMA Rx request if enabled */ +2615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)) + 4625 .loc 1 2615 7 + 4626 013e 7B68 ldr r3, [r7, #4] + 4627 0140 1B68 ldr r3, [r3] + 4628 0142 5B68 ldr r3, [r3, #4] + 4629 0144 03F00103 and r3, r3, #1 + ARM GAS /tmp/ccs34gJO.s page 128 + + + 4630 .loc 1 2615 6 + 4631 0148 012B cmp r3, #1 + 4632 014a 15D1 bne .L245 +2616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Abort the SPI DMA Rx Stream/Channel */ +2618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->hdmarx != NULL) + 4633 .loc 1 2618 13 + 4634 014c 7B68 ldr r3, [r7, #4] + 4635 014e 9B6D ldr r3, [r3, #88] + 4636 .loc 1 2618 8 + 4637 0150 002B cmp r3, #0 + 4638 0152 11D0 beq .L245 +2619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Abort DMA Rx Handle linked to SPI Peripheral */ +2621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK) + 4639 .loc 1 2621 11 + 4640 0154 7B68 ldr r3, [r7, #4] + 4641 0156 9B6D ldr r3, [r3, #88] + 4642 0158 1846 mov r0, r3 + 4643 015a FFF7FEFF bl HAL_DMA_Abort_IT + 4644 015e 0346 mov r3, r0 + 4645 .loc 1 2621 10 discriminator 1 + 4646 0160 002B cmp r3, #0 + 4647 0162 07D0 beq .L246 +2622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmarx->XferAbortCallback = NULL; + 4648 .loc 1 2623 13 + 4649 0164 7B68 ldr r3, [r7, #4] + 4650 0166 9B6D ldr r3, [r3, #88] + 4651 .loc 1 2623 41 + 4652 0168 0022 movs r2, #0 + 4653 016a 5A63 str r2, [r3, #52] +2624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + 4654 .loc 1 2624 25 + 4655 016c 7B68 ldr r3, [r7, #4] + 4656 016e 4022 movs r2, #64 + 4657 0170 1A66 str r2, [r3, #96] + 4658 0172 01E0 b .L245 + 4659 .L246: +2625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +2627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** abortcplt = 0U; + 4660 .loc 1 2628 19 + 4661 0174 0023 movs r3, #0 + 4662 0176 BB61 str r3, [r7, #24] + 4663 .L245: +2629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (abortcplt == 1U) + 4664 .loc 1 2633 6 + 4665 0178 BB69 ldr r3, [r7, #24] + 4666 017a 012B cmp r3, #1 + 4667 017c 29D1 bne .L247 +2634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + ARM GAS /tmp/ccs34gJO.s page 129 + + +2635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset Tx and Rx transfer counters */ +2636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = 0U; + 4668 .loc 1 2636 23 + 4669 017e 7B68 ldr r3, [r7, #4] + 4670 0180 0022 movs r2, #0 + 4671 0182 A3F84620 strh r2, [r3, #70] @ movhi +2637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = 0U; + 4672 .loc 1 2637 23 + 4673 0186 7B68 ldr r3, [r7, #4] + 4674 0188 0022 movs r2, #0 + 4675 018a DA87 strh r2, [r3, #62] @ movhi +2638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check error during Abort procedure */ +2640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT) + 4676 .loc 1 2640 13 + 4677 018c 7B68 ldr r3, [r7, #4] + 4678 018e 1B6E ldr r3, [r3, #96] + 4679 .loc 1 2640 8 + 4680 0190 402B cmp r3, #64 + 4681 0192 02D1 bne .L248 +2641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2642:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* return HAL_Error in case of error during Abort procedure */ +2643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; + 4682 .loc 1 2643 17 + 4683 0194 0123 movs r3, #1 + 4684 0196 FB77 strb r3, [r7, #31] + 4685 0198 02E0 b .L249 + 4686 .L248: +2644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +2646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset errorCode */ +2648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 4687 .loc 1 2648 23 + 4688 019a 7B68 ldr r3, [r7, #4] + 4689 019c 0022 movs r2, #0 + 4690 019e 1A66 str r2, [r3, #96] + 4691 .L249: + 4692 .LBB5: +2649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Clear the Error flags in the SR register */ +2652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_OVRFLAG(hspi); + 4693 .loc 1 2652 5 + 4694 01a0 0023 movs r3, #0 + 4695 01a2 FB60 str r3, [r7, #12] + 4696 01a4 7B68 ldr r3, [r7, #4] + 4697 01a6 1B68 ldr r3, [r3] + 4698 01a8 DB68 ldr r3, [r3, #12] + 4699 01aa FB60 str r3, [r7, #12] + 4700 01ac 7B68 ldr r3, [r7, #4] + 4701 01ae 1B68 ldr r3, [r3] + 4702 01b0 9B68 ldr r3, [r3, #8] + 4703 01b2 FB60 str r3, [r7, #12] + 4704 01b4 FB68 ldr r3, [r7, #12] + 4705 .LBE5: + 4706 .LBB6: + ARM GAS /tmp/ccs34gJO.s page 130 + + +2653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_FREFLAG(hspi); + 4707 .loc 1 2653 5 + 4708 01b6 0023 movs r3, #0 + 4709 01b8 BB60 str r3, [r7, #8] + 4710 01ba 7B68 ldr r3, [r7, #4] + 4711 01bc 1B68 ldr r3, [r3] + 4712 01be 9B68 ldr r3, [r3, #8] + 4713 01c0 BB60 str r3, [r7, #8] + 4714 01c2 BB68 ldr r3, [r7, #8] + 4715 .LBE6: +2654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2655:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Restore hspi->State to Ready */ +2656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; + 4716 .loc 1 2656 17 + 4717 01c4 7B68 ldr r3, [r7, #4] + 4718 01c6 0122 movs r2, #1 + 4719 01c8 83F85D20 strb r2, [r3, #93] +2657:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* As no DMA to be aborted, call directly user Abort complete callback */ +2659:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +2660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->AbortCpltCallback(hspi); +2661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else +2662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_AbortCpltCallback(hspi); + 4720 .loc 1 2662 5 + 4721 01cc 7868 ldr r0, [r7, #4] + 4722 01ce FFF7FEFF bl HAL_SPI_AbortCpltCallback + 4723 .L247: +2663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +2664:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; + 4724 .loc 1 2666 10 + 4725 01d2 FB7F ldrb r3, [r7, #31] @ zero_extendqisi2 +2667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4726 .loc 1 2667 1 + 4727 01d4 1846 mov r0, r3 + 4728 01d6 2037 adds r7, r7, #32 + 4729 .cfi_def_cfa_offset 8 + 4730 01d8 BD46 mov sp, r7 + 4731 .cfi_def_cfa_register 13 + 4732 @ sp needed + 4733 01da 80BD pop {r7, pc} + 4734 .L252: + 4735 .align 2 + 4736 .L251: + 4737 01dc 00000000 .word SystemCoreClock + 4738 01e0 F1197605 .word 91625969 + 4739 01e4 00000000 .word SPI_AbortTx_ISR + 4740 01e8 00000000 .word SPI_AbortRx_ISR + 4741 01ec 00000000 .word SPI_DMATxAbortCallback + 4742 01f0 00000000 .word SPI_DMARxAbortCallback + 4743 .cfi_endproc + 4744 .LFE144: + 4746 .section .text.HAL_SPI_DMAPause,"ax",%progbits + 4747 .align 1 + 4748 .global HAL_SPI_DMAPause + 4749 .syntax unified + ARM GAS /tmp/ccs34gJO.s page 131 + + + 4750 .thumb + 4751 .thumb_func + 4753 HAL_SPI_DMAPause: + 4754 .LFB145: +2668:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +2670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Pause the DMA Transfer. +2671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +2672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for the specified SPI module. +2673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval HAL status +2674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi) +2676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4755 .loc 1 2676 1 + 4756 .cfi_startproc + 4757 @ args = 0, pretend = 0, frame = 8 + 4758 @ frame_needed = 1, uses_anonymous_args = 0 + 4759 @ link register save eliminated. + 4760 0000 80B4 push {r7} + 4761 .cfi_def_cfa_offset 4 + 4762 .cfi_offset 7, -4 + 4763 0002 83B0 sub sp, sp, #12 + 4764 .cfi_def_cfa_offset 16 + 4765 0004 00AF add r7, sp, #0 + 4766 .cfi_def_cfa_register 7 + 4767 0006 7860 str r0, [r7, #4] +2677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Process Locked */ +2678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_LOCK(hspi); + 4768 .loc 1 2678 3 + 4769 0008 7B68 ldr r3, [r7, #4] + 4770 000a 93F85C30 ldrb r3, [r3, #92] @ zero_extendqisi2 + 4771 000e 012B cmp r3, #1 + 4772 0010 01D1 bne .L254 + 4773 .loc 1 2678 3 is_stmt 0 discriminator 1 + 4774 0012 0223 movs r3, #2 + 4775 .loc 1 2678 3 + 4776 0014 10E0 b .L255 + 4777 .L254: + 4778 .loc 1 2678 3 discriminator 2 + 4779 0016 7B68 ldr r3, [r7, #4] + 4780 0018 0122 movs r2, #1 + 4781 001a 83F85C20 strb r2, [r3, #92] +2679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable the SPI DMA Tx & Rx requests */ +2681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + 4782 .loc 1 2681 3 is_stmt 1 + 4783 001e 7B68 ldr r3, [r7, #4] + 4784 0020 1B68 ldr r3, [r3] + 4785 0022 5A68 ldr r2, [r3, #4] + 4786 0024 7B68 ldr r3, [r7, #4] + 4787 0026 1B68 ldr r3, [r3] + 4788 0028 22F00302 bic r2, r2, #3 + 4789 002c 5A60 str r2, [r3, #4] +2682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Process Unlocked */ +2684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_UNLOCK(hspi); + 4790 .loc 1 2684 3 + ARM GAS /tmp/ccs34gJO.s page 132 + + + 4791 002e 7B68 ldr r3, [r7, #4] + 4792 0030 0022 movs r2, #0 + 4793 0032 83F85C20 strb r2, [r3, #92] +2685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return HAL_OK; + 4794 .loc 1 2686 10 + 4795 0036 0023 movs r3, #0 + 4796 .L255: +2687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4797 .loc 1 2687 1 + 4798 0038 1846 mov r0, r3 + 4799 003a 0C37 adds r7, r7, #12 + 4800 .cfi_def_cfa_offset 4 + 4801 003c BD46 mov sp, r7 + 4802 .cfi_def_cfa_register 13 + 4803 @ sp needed + 4804 003e 5DF8047B ldr r7, [sp], #4 + 4805 .cfi_restore 7 + 4806 .cfi_def_cfa_offset 0 + 4807 0042 7047 bx lr + 4808 .cfi_endproc + 4809 .LFE145: + 4811 .section .text.HAL_SPI_DMAResume,"ax",%progbits + 4812 .align 1 + 4813 .global HAL_SPI_DMAResume + 4814 .syntax unified + 4815 .thumb + 4816 .thumb_func + 4818 HAL_SPI_DMAResume: + 4819 .LFB146: +2688:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +2690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Resume the DMA Transfer. +2691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +2692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for the specified SPI module. +2693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval HAL status +2694:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi) +2696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4820 .loc 1 2696 1 + 4821 .cfi_startproc + 4822 @ args = 0, pretend = 0, frame = 8 + 4823 @ frame_needed = 1, uses_anonymous_args = 0 + 4824 @ link register save eliminated. + 4825 0000 80B4 push {r7} + 4826 .cfi_def_cfa_offset 4 + 4827 .cfi_offset 7, -4 + 4828 0002 83B0 sub sp, sp, #12 + 4829 .cfi_def_cfa_offset 16 + 4830 0004 00AF add r7, sp, #0 + 4831 .cfi_def_cfa_register 7 + 4832 0006 7860 str r0, [r7, #4] +2697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Process Locked */ +2698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_LOCK(hspi); + 4833 .loc 1 2698 3 + 4834 0008 7B68 ldr r3, [r7, #4] + 4835 000a 93F85C30 ldrb r3, [r3, #92] @ zero_extendqisi2 + ARM GAS /tmp/ccs34gJO.s page 133 + + + 4836 000e 012B cmp r3, #1 + 4837 0010 01D1 bne .L257 + 4838 .loc 1 2698 3 is_stmt 0 discriminator 1 + 4839 0012 0223 movs r3, #2 + 4840 .loc 1 2698 3 + 4841 0014 10E0 b .L258 + 4842 .L257: + 4843 .loc 1 2698 3 discriminator 2 + 4844 0016 7B68 ldr r3, [r7, #4] + 4845 0018 0122 movs r2, #1 + 4846 001a 83F85C20 strb r2, [r3, #92] +2699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2700:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable the SPI DMA Tx & Rx requests */ +2701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + 4847 .loc 1 2701 3 is_stmt 1 + 4848 001e 7B68 ldr r3, [r7, #4] + 4849 0020 1B68 ldr r3, [r3] + 4850 0022 5A68 ldr r2, [r3, #4] + 4851 0024 7B68 ldr r3, [r7, #4] + 4852 0026 1B68 ldr r3, [r3] + 4853 0028 42F00302 orr r2, r2, #3 + 4854 002c 5A60 str r2, [r3, #4] +2702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Process Unlocked */ +2704:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_UNLOCK(hspi); + 4855 .loc 1 2704 3 + 4856 002e 7B68 ldr r3, [r7, #4] + 4857 0030 0022 movs r2, #0 + 4858 0032 83F85C20 strb r2, [r3, #92] +2705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2706:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return HAL_OK; + 4859 .loc 1 2706 10 + 4860 0036 0023 movs r3, #0 + 4861 .L258: +2707:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4862 .loc 1 2707 1 + 4863 0038 1846 mov r0, r3 + 4864 003a 0C37 adds r7, r7, #12 + 4865 .cfi_def_cfa_offset 4 + 4866 003c BD46 mov sp, r7 + 4867 .cfi_def_cfa_register 13 + 4868 @ sp needed + 4869 003e 5DF8047B ldr r7, [sp], #4 + 4870 .cfi_restore 7 + 4871 .cfi_def_cfa_offset 0 + 4872 0042 7047 bx lr + 4873 .cfi_endproc + 4874 .LFE146: + 4876 .section .text.HAL_SPI_DMAStop,"ax",%progbits + 4877 .align 1 + 4878 .global HAL_SPI_DMAStop + 4879 .syntax unified + 4880 .thumb + 4881 .thumb_func + 4883 HAL_SPI_DMAStop: + 4884 .LFB147: +2708:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + ARM GAS /tmp/ccs34gJO.s page 134 + + +2709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +2710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Stop the DMA Transfer. +2711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +2712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for the specified SPI module. +2713:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval HAL status +2714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) +2716:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4885 .loc 1 2716 1 + 4886 .cfi_startproc + 4887 @ args = 0, pretend = 0, frame = 16 + 4888 @ frame_needed = 1, uses_anonymous_args = 0 + 4889 0000 80B5 push {r7, lr} + 4890 .cfi_def_cfa_offset 8 + 4891 .cfi_offset 7, -8 + 4892 .cfi_offset 14, -4 + 4893 0002 84B0 sub sp, sp, #16 + 4894 .cfi_def_cfa_offset 24 + 4895 0004 00AF add r7, sp, #0 + 4896 .cfi_def_cfa_register 7 + 4897 0006 7860 str r0, [r7, #4] +2717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_StatusTypeDef errorcode = HAL_OK; + 4898 .loc 1 2717 21 + 4899 0008 0023 movs r3, #0 + 4900 000a FB73 strb r3, [r7, #15] +2718:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* The Lock is not implemented on this API to allow the user application +2719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() o +2720:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated +2721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() +2722:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2723:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2724:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Abort the SPI DMA tx Stream/Channel */ +2725:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->hdmatx != NULL) + 4901 .loc 1 2725 11 + 4902 000c 7B68 ldr r3, [r7, #4] + 4903 000e 5B6D ldr r3, [r3, #84] + 4904 .loc 1 2725 6 + 4905 0010 002B cmp r3, #0 + 4906 0012 0FD0 beq .L260 +2726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2727:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx)) + 4907 .loc 1 2727 19 + 4908 0014 7B68 ldr r3, [r7, #4] + 4909 0016 5B6D ldr r3, [r3, #84] + 4910 0018 1846 mov r0, r3 + 4911 001a FFF7FEFF bl HAL_DMA_Abort + 4912 001e 0346 mov r3, r0 + 4913 .loc 1 2727 8 discriminator 1 + 4914 0020 002B cmp r3, #0 + 4915 0022 07D0 beq .L260 +2728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + 4916 .loc 1 2729 7 + 4917 0024 7B68 ldr r3, [r7, #4] + 4918 0026 1B6E ldr r3, [r3, #96] + 4919 0028 43F01002 orr r2, r3, #16 + 4920 002c 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/ccs34gJO.s page 135 + + + 4921 002e 1A66 str r2, [r3, #96] +2730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; + 4922 .loc 1 2730 17 + 4923 0030 0123 movs r3, #1 + 4924 0032 FB73 strb r3, [r7, #15] + 4925 .L260: +2731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Abort the SPI DMA rx Stream/Channel */ +2734:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->hdmarx != NULL) + 4926 .loc 1 2734 11 + 4927 0034 7B68 ldr r3, [r7, #4] + 4928 0036 9B6D ldr r3, [r3, #88] + 4929 .loc 1 2734 6 + 4930 0038 002B cmp r3, #0 + 4931 003a 0FD0 beq .L261 +2735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx)) + 4932 .loc 1 2736 19 + 4933 003c 7B68 ldr r3, [r7, #4] + 4934 003e 9B6D ldr r3, [r3, #88] + 4935 0040 1846 mov r0, r3 + 4936 0042 FFF7FEFF bl HAL_DMA_Abort + 4937 0046 0346 mov r3, r0 + 4938 .loc 1 2736 8 discriminator 1 + 4939 0048 002B cmp r3, #0 + 4940 004a 07D0 beq .L261 +2737:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + 4941 .loc 1 2738 7 + 4942 004c 7B68 ldr r3, [r7, #4] + 4943 004e 1B6E ldr r3, [r3, #96] + 4944 0050 43F01002 orr r2, r3, #16 + 4945 0054 7B68 ldr r3, [r7, #4] + 4946 0056 1A66 str r2, [r3, #96] +2739:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** errorcode = HAL_ERROR; + 4947 .loc 1 2739 17 + 4948 0058 0123 movs r3, #1 + 4949 005a FB73 strb r3, [r7, #15] + 4950 .L261: +2740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2743:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable the SPI DMA Tx & Rx requests */ +2744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + 4951 .loc 1 2744 3 + 4952 005c 7B68 ldr r3, [r7, #4] + 4953 005e 1B68 ldr r3, [r3] + 4954 0060 5A68 ldr r2, [r3, #4] + 4955 0062 7B68 ldr r3, [r7, #4] + 4956 0064 1B68 ldr r3, [r3] + 4957 0066 22F00302 bic r2, r2, #3 + 4958 006a 5A60 str r2, [r3, #4] +2745:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; + 4959 .loc 1 2745 15 + 4960 006c 7B68 ldr r3, [r7, #4] + 4961 006e 0122 movs r2, #1 + ARM GAS /tmp/ccs34gJO.s page 136 + + + 4962 0070 83F85D20 strb r2, [r3, #93] +2746:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return errorcode; + 4963 .loc 1 2746 10 + 4964 0074 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 +2747:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 4965 .loc 1 2747 1 + 4966 0076 1846 mov r0, r3 + 4967 0078 1037 adds r7, r7, #16 + 4968 .cfi_def_cfa_offset 8 + 4969 007a BD46 mov sp, r7 + 4970 .cfi_def_cfa_register 13 + 4971 @ sp needed + 4972 007c 80BD pop {r7, pc} + 4973 .cfi_endproc + 4974 .LFE147: + 4976 .section .text.HAL_SPI_IRQHandler,"ax",%progbits + 4977 .align 1 + 4978 .global HAL_SPI_IRQHandler + 4979 .syntax unified + 4980 .thumb + 4981 .thumb_func + 4983 HAL_SPI_IRQHandler: + 4984 .LFB148: +2748:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +2750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Handle SPI interrupt request. +2751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +2752:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for the specified SPI module. +2753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +2754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2755:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) +2756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 4985 .loc 1 2756 1 + 4986 .cfi_startproc + 4987 @ args = 0, pretend = 0, frame = 32 + 4988 @ frame_needed = 1, uses_anonymous_args = 0 + 4989 0000 80B5 push {r7, lr} + 4990 .cfi_def_cfa_offset 8 + 4991 .cfi_offset 7, -8 + 4992 .cfi_offset 14, -4 + 4993 0002 88B0 sub sp, sp, #32 + 4994 .cfi_def_cfa_offset 40 + 4995 0004 00AF add r7, sp, #0 + 4996 .cfi_def_cfa_register 7 + 4997 0006 7860 str r0, [r7, #4] +2757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t itsource = hspi->Instance->CR2; + 4998 .loc 1 2757 27 + 4999 0008 7B68 ldr r3, [r7, #4] + 5000 000a 1B68 ldr r3, [r3] + 5001 .loc 1 2757 12 + 5002 000c 5B68 ldr r3, [r3, #4] + 5003 000e FB61 str r3, [r7, #28] +2758:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t itflag = hspi->Instance->SR; + 5004 .loc 1 2758 27 + 5005 0010 7B68 ldr r3, [r7, #4] + 5006 0012 1B68 ldr r3, [r3] + 5007 .loc 1 2758 12 + ARM GAS /tmp/ccs34gJO.s page 137 + + + 5008 0014 9B68 ldr r3, [r3, #8] + 5009 0016 BB61 str r3, [r7, #24] +2759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2760:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* SPI in mode Receiver ----------------------------------------------------*/ +2761:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) && + 5010 .loc 1 2761 8 + 5011 0018 BB69 ldr r3, [r7, #24] + 5012 001a 9B09 lsrs r3, r3, #6 + 5013 001c 03F00103 and r3, r3, #1 + 5014 .loc 1 2761 6 + 5015 0020 002B cmp r3, #0 + 5016 0022 0FD1 bne .L264 +2762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXN + 5017 .loc 1 2762 8 + 5018 0024 BB69 ldr r3, [r7, #24] + 5019 0026 03F00103 and r3, r3, #1 +2761:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXN + 5020 .loc 1 2761 55 discriminator 1 + 5021 002a 002B cmp r3, #0 + 5022 002c 0AD0 beq .L264 + 5023 .loc 1 2762 60 + 5024 002e FB69 ldr r3, [r7, #28] + 5025 0030 9B09 lsrs r3, r3, #6 + 5026 0032 03F00103 and r3, r3, #1 + 5027 .loc 1 2762 56 + 5028 0036 002B cmp r3, #0 + 5029 0038 04D0 beq .L264 +2763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2764:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxISR(hspi); + 5030 .loc 1 2764 9 + 5031 003a 7B68 ldr r3, [r7, #4] + 5032 003c DB6C ldr r3, [r3, #76] + 5033 .loc 1 2764 5 + 5034 003e 7868 ldr r0, [r7, #4] + 5035 0040 9847 blx r3 + 5036 .LVL0: +2765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return; + 5037 .loc 1 2765 5 + 5038 0042 D7E0 b .L263 + 5039 .L264: +2766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2767:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* SPI in mode Transmitter -------------------------------------------------*/ +2769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) + 5040 .loc 1 2769 8 + 5041 0044 BB69 ldr r3, [r7, #24] + 5042 0046 5B08 lsrs r3, r3, #1 + 5043 0048 03F00103 and r3, r3, #1 + 5044 .loc 1 2769 6 + 5045 004c 002B cmp r3, #0 + 5046 004e 0AD0 beq .L266 + 5047 .loc 1 2769 59 discriminator 1 + 5048 0050 FB69 ldr r3, [r7, #28] + 5049 0052 DB09 lsrs r3, r3, #7 + 5050 0054 03F00103 and r3, r3, #1 + 5051 .loc 1 2769 55 discriminator 1 + 5052 0058 002B cmp r3, #0 + ARM GAS /tmp/ccs34gJO.s page 138 + + + 5053 005a 04D0 beq .L266 +2770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxISR(hspi); + 5054 .loc 1 2771 9 + 5055 005c 7B68 ldr r3, [r7, #4] + 5056 005e 1B6D ldr r3, [r3, #80] + 5057 .loc 1 2771 5 + 5058 0060 7868 ldr r0, [r7, #4] + 5059 0062 9847 blx r3 + 5060 .LVL1: +2772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return; + 5061 .loc 1 2772 5 + 5062 0064 C6E0 b .L263 + 5063 .L266: +2773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* SPI in Error Treatment --------------------------------------------------*/ +2776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != + 5064 .loc 1 2776 9 + 5065 0066 BB69 ldr r3, [r7, #24] + 5066 0068 5B09 lsrs r3, r3, #5 + 5067 006a 03F00103 and r3, r3, #1 + 5068 .loc 1 2776 6 + 5069 006e 002B cmp r3, #0 + 5070 0070 0CD1 bne .L267 + 5071 .loc 1 2776 61 discriminator 1 + 5072 0072 BB69 ldr r3, [r7, #24] + 5073 0074 9B09 lsrs r3, r3, #6 + 5074 0076 03F00103 and r3, r3, #1 + 5075 .loc 1 2776 57 discriminator 1 + 5076 007a 002B cmp r3, #0 + 5077 007c 06D1 bne .L267 +2777:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT + 5078 .loc 1 2777 12 + 5079 007e BB69 ldr r3, [r7, #24] + 5080 0080 1B0A lsrs r3, r3, #8 + 5081 0082 03F00103 and r3, r3, #1 + 5082 .loc 1 2777 8 + 5083 0086 002B cmp r3, #0 + 5084 0088 00F0B480 beq .L263 + 5085 .L267: + 5086 .loc 1 2777 64 discriminator 1 + 5087 008c FB69 ldr r3, [r7, #28] + 5088 008e 5B09 lsrs r3, r3, #5 + 5089 0090 03F00103 and r3, r3, #1 + 5090 .loc 1 2777 60 discriminator 1 + 5091 0094 002B cmp r3, #0 + 5092 0096 00F0AD80 beq .L263 +2778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* SPI Overrun error interrupt occurred ----------------------------------*/ +2780:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET) + 5093 .loc 1 2780 9 + 5094 009a BB69 ldr r3, [r7, #24] + 5095 009c 9B09 lsrs r3, r3, #6 + 5096 009e 03F00103 and r3, r3, #1 + 5097 .loc 1 2780 8 + 5098 00a2 002B cmp r3, #0 + ARM GAS /tmp/ccs34gJO.s page 139 + + + 5099 00a4 23D0 beq .L268 +2781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2782:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->State != HAL_SPI_STATE_BUSY_TX) + 5100 .loc 1 2782 15 + 5101 00a6 7B68 ldr r3, [r7, #4] + 5102 00a8 93F85D30 ldrb r3, [r3, #93] + 5103 00ac DBB2 uxtb r3, r3 + 5104 .loc 1 2782 10 + 5105 00ae 032B cmp r3, #3 + 5106 00b0 11D0 beq .L269 +2783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR); + 5107 .loc 1 2784 9 + 5108 00b2 7B68 ldr r3, [r7, #4] + 5109 00b4 1B6E ldr r3, [r3, #96] + 5110 00b6 43F00402 orr r2, r3, #4 + 5111 00ba 7B68 ldr r3, [r7, #4] + 5112 00bc 1A66 str r2, [r3, #96] + 5113 .LBB7: +2785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_OVRFLAG(hspi); + 5114 .loc 1 2785 9 + 5115 00be 0023 movs r3, #0 + 5116 00c0 7B61 str r3, [r7, #20] + 5117 00c2 7B68 ldr r3, [r7, #4] + 5118 00c4 1B68 ldr r3, [r3] + 5119 00c6 DB68 ldr r3, [r3, #12] + 5120 00c8 7B61 str r3, [r7, #20] + 5121 00ca 7B68 ldr r3, [r7, #4] + 5122 00cc 1B68 ldr r3, [r3] + 5123 00ce 9B68 ldr r3, [r3, #8] + 5124 00d0 7B61 str r3, [r7, #20] + 5125 00d2 7B69 ldr r3, [r7, #20] + 5126 .LBE7: + 5127 00d4 0BE0 b .L268 + 5128 .L269: + 5129 .LBB8: +2786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2787:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +2788:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_OVRFLAG(hspi); + 5130 .loc 1 2789 9 + 5131 00d6 0023 movs r3, #0 + 5132 00d8 3B61 str r3, [r7, #16] + 5133 00da 7B68 ldr r3, [r7, #4] + 5134 00dc 1B68 ldr r3, [r3] + 5135 00de DB68 ldr r3, [r3, #12] + 5136 00e0 3B61 str r3, [r7, #16] + 5137 00e2 7B68 ldr r3, [r7, #4] + 5138 00e4 1B68 ldr r3, [r3] + 5139 00e6 9B68 ldr r3, [r3, #8] + 5140 00e8 3B61 str r3, [r7, #16] + 5141 00ea 3B69 ldr r3, [r7, #16] + 5142 .LBE8: +2790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return; + 5143 .loc 1 2790 9 + 5144 00ec 82E0 b .L263 + 5145 .L268: + ARM GAS /tmp/ccs34gJO.s page 140 + + +2791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* SPI Mode Fault error interrupt occurred -------------------------------*/ +2795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) + 5146 .loc 1 2795 9 + 5147 00ee BB69 ldr r3, [r7, #24] + 5148 00f0 5B09 lsrs r3, r3, #5 + 5149 00f2 03F00103 and r3, r3, #1 + 5150 .loc 1 2795 8 + 5151 00f6 002B cmp r3, #0 + 5152 00f8 14D0 beq .L270 +2796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF); + 5153 .loc 1 2797 7 + 5154 00fa 7B68 ldr r3, [r7, #4] + 5155 00fc 1B6E ldr r3, [r3, #96] + 5156 00fe 43F00102 orr r2, r3, #1 + 5157 0102 7B68 ldr r3, [r7, #4] + 5158 0104 1A66 str r2, [r3, #96] + 5159 .LBB9: +2798:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_MODFFLAG(hspi); + 5160 .loc 1 2798 7 + 5161 0106 0023 movs r3, #0 + 5162 0108 FB60 str r3, [r7, #12] + 5163 010a 7B68 ldr r3, [r7, #4] + 5164 010c 1B68 ldr r3, [r3] + 5165 010e 9B68 ldr r3, [r3, #8] + 5166 0110 FB60 str r3, [r7, #12] + 5167 0112 7B68 ldr r3, [r7, #4] + 5168 0114 1B68 ldr r3, [r3] + 5169 0116 1A68 ldr r2, [r3] + 5170 0118 7B68 ldr r3, [r7, #4] + 5171 011a 1B68 ldr r3, [r3] + 5172 011c 22F04002 bic r2, r2, #64 + 5173 0120 1A60 str r2, [r3] + 5174 0122 FB68 ldr r3, [r7, #12] + 5175 .L270: + 5176 .LBE9: +2799:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* SPI Frame error interrupt occurred ------------------------------------*/ +2802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET) + 5177 .loc 1 2802 9 + 5178 0124 BB69 ldr r3, [r7, #24] + 5179 0126 1B0A lsrs r3, r3, #8 + 5180 0128 03F00103 and r3, r3, #1 + 5181 .loc 1 2802 8 + 5182 012c 002B cmp r3, #0 + 5183 012e 0CD0 beq .L271 +2803:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2804:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE); + 5184 .loc 1 2804 7 + 5185 0130 7B68 ldr r3, [r7, #4] + 5186 0132 1B6E ldr r3, [r3, #96] + 5187 0134 43F00802 orr r2, r3, #8 + 5188 0138 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/ccs34gJO.s page 141 + + + 5189 013a 1A66 str r2, [r3, #96] + 5190 .LBB10: +2805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_FREFLAG(hspi); + 5191 .loc 1 2805 7 + 5192 013c 0023 movs r3, #0 + 5193 013e BB60 str r3, [r7, #8] + 5194 0140 7B68 ldr r3, [r7, #4] + 5195 0142 1B68 ldr r3, [r3] + 5196 0144 9B68 ldr r3, [r3, #8] + 5197 0146 BB60 str r3, [r7, #8] + 5198 0148 BB68 ldr r3, [r7, #8] + 5199 .L271: + 5200 .LBE10: +2806:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2807:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2808:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + 5201 .loc 1 2808 13 + 5202 014a 7B68 ldr r3, [r7, #4] + 5203 014c 1B6E ldr r3, [r3, #96] + 5204 .loc 1 2808 8 + 5205 014e 002B cmp r3, #0 + 5206 0150 4FD0 beq .L277 +2809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable all interrupts */ +2811:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR); + 5207 .loc 1 2811 7 + 5208 0152 7B68 ldr r3, [r7, #4] + 5209 0154 1B68 ldr r3, [r3] + 5210 0156 5A68 ldr r2, [r3, #4] + 5211 0158 7B68 ldr r3, [r7, #4] + 5212 015a 1B68 ldr r3, [r3] + 5213 015c 22F0E002 bic r2, r2, #224 + 5214 0160 5A60 str r2, [r3, #4] +2812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; + 5215 .loc 1 2813 19 + 5216 0162 7B68 ldr r3, [r7, #4] + 5217 0164 0122 movs r2, #1 + 5218 0166 83F85D20 strb r2, [r3, #93] +2814:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable the SPI DMA requests if enabled */ +2815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN) + 5219 .loc 1 2815 12 + 5220 016a FB69 ldr r3, [r7, #28] + 5221 016c 03F00203 and r3, r3, #2 + 5222 .loc 1 2815 10 + 5223 0170 002B cmp r3, #0 + 5224 0172 04D1 bne .L273 + 5225 .loc 1 2815 59 discriminator 1 + 5226 0174 FB69 ldr r3, [r7, #28] + 5227 0176 03F00103 and r3, r3, #1 + 5228 .loc 1 2815 55 discriminator 1 + 5229 017a 002B cmp r3, #0 + 5230 017c 34D0 beq .L274 + 5231 .L273: +2816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2817:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN)); + 5232 .loc 1 2817 9 + ARM GAS /tmp/ccs34gJO.s page 142 + + + 5233 017e 7B68 ldr r3, [r7, #4] + 5234 0180 1B68 ldr r3, [r3] + 5235 0182 5A68 ldr r2, [r3, #4] + 5236 0184 7B68 ldr r3, [r7, #4] + 5237 0186 1B68 ldr r3, [r3] + 5238 0188 22F00302 bic r2, r2, #3 + 5239 018c 5A60 str r2, [r3, #4] +2818:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Abort the SPI DMA Rx channel */ +2820:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->hdmarx != NULL) + 5240 .loc 1 2820 17 + 5241 018e 7B68 ldr r3, [r7, #4] + 5242 0190 9B6D ldr r3, [r3, #88] + 5243 .loc 1 2820 12 + 5244 0192 002B cmp r3, #0 + 5245 0194 11D0 beq .L275 +2821:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the SPI DMA Abort callback : +2823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ +2824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError; + 5246 .loc 1 2824 15 + 5247 0196 7B68 ldr r3, [r7, #4] + 5248 0198 9B6D ldr r3, [r3, #88] + 5249 .loc 1 2824 43 + 5250 019a 184A ldr r2, .L279 + 5251 019c 5A63 str r2, [r3, #52] +2825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx)) + 5252 .loc 1 2825 25 + 5253 019e 7B68 ldr r3, [r7, #4] + 5254 01a0 9B6D ldr r3, [r3, #88] + 5255 01a2 1846 mov r0, r3 + 5256 01a4 FFF7FEFF bl HAL_DMA_Abort_IT + 5257 01a8 0346 mov r3, r0 + 5258 .loc 1 2825 14 discriminator 1 + 5259 01aa 002B cmp r3, #0 + 5260 01ac 05D0 beq .L275 +2826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2827:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + 5261 .loc 1 2827 13 + 5262 01ae 7B68 ldr r3, [r7, #4] + 5263 01b0 1B6E ldr r3, [r3, #96] + 5264 01b2 43F04002 orr r2, r3, #64 + 5265 01b6 7B68 ldr r3, [r7, #4] + 5266 01b8 1A66 str r2, [r3, #96] + 5267 .L275: +2828:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2829:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2830:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Abort the SPI DMA Tx channel */ +2831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->hdmatx != NULL) + 5268 .loc 1 2831 17 + 5269 01ba 7B68 ldr r3, [r7, #4] + 5270 01bc 5B6D ldr r3, [r3, #84] + 5271 .loc 1 2831 12 + 5272 01be 002B cmp r3, #0 + 5273 01c0 16D0 beq .L278 +2832:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set the SPI DMA Abort callback : + ARM GAS /tmp/ccs34gJO.s page 143 + + +2834:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ +2835:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError; + 5274 .loc 1 2835 15 + 5275 01c2 7B68 ldr r3, [r7, #4] + 5276 01c4 5B6D ldr r3, [r3, #84] + 5277 .loc 1 2835 43 + 5278 01c6 0D4A ldr r2, .L279 + 5279 01c8 5A63 str r2, [r3, #52] +2836:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx)) + 5280 .loc 1 2836 25 + 5281 01ca 7B68 ldr r3, [r7, #4] + 5282 01cc 5B6D ldr r3, [r3, #84] + 5283 01ce 1846 mov r0, r3 + 5284 01d0 FFF7FEFF bl HAL_DMA_Abort_IT + 5285 01d4 0346 mov r3, r0 + 5286 .loc 1 2836 14 discriminator 1 + 5287 01d6 002B cmp r3, #0 + 5288 01d8 0AD0 beq .L278 +2837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + 5289 .loc 1 2838 13 + 5290 01da 7B68 ldr r3, [r7, #4] + 5291 01dc 1B6E ldr r3, [r3, #96] + 5292 01de 43F04002 orr r2, r3, #64 + 5293 01e2 7B68 ldr r3, [r7, #4] + 5294 01e4 1A66 str r2, [r3, #96] +2831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5295 .loc 1 2831 12 + 5296 01e6 03E0 b .L278 + 5297 .L274: +2839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2840:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2842:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +2843:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +2844:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user error callback */ +2845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +2846:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCallback(hspi); +2847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else +2848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_ErrorCallback(hspi); + 5298 .loc 1 2848 9 + 5299 01e8 7868 ldr r0, [r7, #4] + 5300 01ea FFF7FEFF bl HAL_SPI_ErrorCallback +2849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +2850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2851:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2852:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return; + 5301 .loc 1 2852 5 + 5302 01ee 00E0 b .L277 + 5303 .L278: +2831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5304 .loc 1 2831 12 + 5305 01f0 00BF nop + 5306 .L277: + 5307 .loc 1 2852 5 + 5308 01f2 00BF nop + 5309 .L263: + ARM GAS /tmp/ccs34gJO.s page 144 + + +2853:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +2854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 5310 .loc 1 2854 1 + 5311 01f4 2037 adds r7, r7, #32 + 5312 .cfi_def_cfa_offset 8 + 5313 01f6 BD46 mov sp, r7 + 5314 .cfi_def_cfa_register 13 + 5315 @ sp needed + 5316 01f8 80BD pop {r7, pc} + 5317 .L280: + 5318 01fa 00BF .align 2 + 5319 .L279: + 5320 01fc 00000000 .word SPI_DMAAbortOnError + 5321 .cfi_endproc + 5322 .LFE148: + 5324 .section .text.HAL_SPI_TxCpltCallback,"ax",%progbits + 5325 .align 1 + 5326 .weak HAL_SPI_TxCpltCallback + 5327 .syntax unified + 5328 .thumb + 5329 .thumb_func + 5331 HAL_SPI_TxCpltCallback: + 5332 .LFB149: +2855:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2856:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +2857:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Tx Transfer completed callback. +2858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +2859:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +2860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +2861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) +2863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5333 .loc 1 2863 1 + 5334 .cfi_startproc + 5335 @ args = 0, pretend = 0, frame = 8 + 5336 @ frame_needed = 1, uses_anonymous_args = 0 + 5337 @ link register save eliminated. + 5338 0000 80B4 push {r7} + 5339 .cfi_def_cfa_offset 4 + 5340 .cfi_offset 7, -4 + 5341 0002 83B0 sub sp, sp, #12 + 5342 .cfi_def_cfa_offset 16 + 5343 0004 00AF add r7, sp, #0 + 5344 .cfi_def_cfa_register 7 + 5345 0006 7860 str r0, [r7, #4] +2864:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Prevent unused argument(s) compilation warning */ +2865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(hspi); +2866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* NOTE : This function should not be modified, when the callback is needed, +2868:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** the HAL_SPI_TxCpltCallback should be implemented in the user file +2869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2870:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 5346 .loc 1 2870 1 + 5347 0008 00BF nop + 5348 000a 0C37 adds r7, r7, #12 + 5349 .cfi_def_cfa_offset 4 + 5350 000c BD46 mov sp, r7 + ARM GAS /tmp/ccs34gJO.s page 145 + + + 5351 .cfi_def_cfa_register 13 + 5352 @ sp needed + 5353 000e 5DF8047B ldr r7, [sp], #4 + 5354 .cfi_restore 7 + 5355 .cfi_def_cfa_offset 0 + 5356 0012 7047 bx lr + 5357 .cfi_endproc + 5358 .LFE149: + 5360 .section .text.HAL_SPI_RxCpltCallback,"ax",%progbits + 5361 .align 1 + 5362 .weak HAL_SPI_RxCpltCallback + 5363 .syntax unified + 5364 .thumb + 5365 .thumb_func + 5367 HAL_SPI_RxCpltCallback: + 5368 .LFB150: +2871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +2873:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Rx Transfer completed callback. +2874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +2875:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +2876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +2877:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2878:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) +2879:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5369 .loc 1 2879 1 + 5370 .cfi_startproc + 5371 @ args = 0, pretend = 0, frame = 8 + 5372 @ frame_needed = 1, uses_anonymous_args = 0 + 5373 @ link register save eliminated. + 5374 0000 80B4 push {r7} + 5375 .cfi_def_cfa_offset 4 + 5376 .cfi_offset 7, -4 + 5377 0002 83B0 sub sp, sp, #12 + 5378 .cfi_def_cfa_offset 16 + 5379 0004 00AF add r7, sp, #0 + 5380 .cfi_def_cfa_register 7 + 5381 0006 7860 str r0, [r7, #4] +2880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Prevent unused argument(s) compilation warning */ +2881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(hspi); +2882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* NOTE : This function should not be modified, when the callback is needed, +2884:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** the HAL_SPI_RxCpltCallback should be implemented in the user file +2885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 5382 .loc 1 2886 1 + 5383 0008 00BF nop + 5384 000a 0C37 adds r7, r7, #12 + 5385 .cfi_def_cfa_offset 4 + 5386 000c BD46 mov sp, r7 + 5387 .cfi_def_cfa_register 13 + 5388 @ sp needed + 5389 000e 5DF8047B ldr r7, [sp], #4 + 5390 .cfi_restore 7 + 5391 .cfi_def_cfa_offset 0 + 5392 0012 7047 bx lr + 5393 .cfi_endproc + ARM GAS /tmp/ccs34gJO.s page 146 + + + 5394 .LFE150: + 5396 .section .text.HAL_SPI_TxRxCpltCallback,"ax",%progbits + 5397 .align 1 + 5398 .weak HAL_SPI_TxRxCpltCallback + 5399 .syntax unified + 5400 .thumb + 5401 .thumb_func + 5403 HAL_SPI_TxRxCpltCallback: + 5404 .LFB151: +2887:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2888:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +2889:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Tx and Rx Transfer completed callback. +2890:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +2891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +2892:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +2893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2894:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) +2895:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5405 .loc 1 2895 1 + 5406 .cfi_startproc + 5407 @ args = 0, pretend = 0, frame = 8 + 5408 @ frame_needed = 1, uses_anonymous_args = 0 + 5409 @ link register save eliminated. + 5410 0000 80B4 push {r7} + 5411 .cfi_def_cfa_offset 4 + 5412 .cfi_offset 7, -4 + 5413 0002 83B0 sub sp, sp, #12 + 5414 .cfi_def_cfa_offset 16 + 5415 0004 00AF add r7, sp, #0 + 5416 .cfi_def_cfa_register 7 + 5417 0006 7860 str r0, [r7, #4] +2896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Prevent unused argument(s) compilation warning */ +2897:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(hspi); +2898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2899:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* NOTE : This function should not be modified, when the callback is needed, +2900:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** the HAL_SPI_TxRxCpltCallback should be implemented in the user file +2901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2902:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 5418 .loc 1 2902 1 + 5419 0008 00BF nop + 5420 000a 0C37 adds r7, r7, #12 + 5421 .cfi_def_cfa_offset 4 + 5422 000c BD46 mov sp, r7 + 5423 .cfi_def_cfa_register 13 + 5424 @ sp needed + 5425 000e 5DF8047B ldr r7, [sp], #4 + 5426 .cfi_restore 7 + 5427 .cfi_def_cfa_offset 0 + 5428 0012 7047 bx lr + 5429 .cfi_endproc + 5430 .LFE151: + 5432 .section .text.HAL_SPI_TxHalfCpltCallback,"ax",%progbits + 5433 .align 1 + 5434 .weak HAL_SPI_TxHalfCpltCallback + 5435 .syntax unified + 5436 .thumb + 5437 .thumb_func + ARM GAS /tmp/ccs34gJO.s page 147 + + + 5439 HAL_SPI_TxHalfCpltCallback: + 5440 .LFB152: +2903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2904:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +2905:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Tx Half Transfer completed callback. +2906:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +2907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +2908:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +2909:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) +2911:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5441 .loc 1 2911 1 + 5442 .cfi_startproc + 5443 @ args = 0, pretend = 0, frame = 8 + 5444 @ frame_needed = 1, uses_anonymous_args = 0 + 5445 @ link register save eliminated. + 5446 0000 80B4 push {r7} + 5447 .cfi_def_cfa_offset 4 + 5448 .cfi_offset 7, -4 + 5449 0002 83B0 sub sp, sp, #12 + 5450 .cfi_def_cfa_offset 16 + 5451 0004 00AF add r7, sp, #0 + 5452 .cfi_def_cfa_register 7 + 5453 0006 7860 str r0, [r7, #4] +2912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Prevent unused argument(s) compilation warning */ +2913:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(hspi); +2914:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2915:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* NOTE : This function should not be modified, when the callback is needed, +2916:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** the HAL_SPI_TxHalfCpltCallback should be implemented in the user file +2917:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2918:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 5454 .loc 1 2918 1 + 5455 0008 00BF nop + 5456 000a 0C37 adds r7, r7, #12 + 5457 .cfi_def_cfa_offset 4 + 5458 000c BD46 mov sp, r7 + 5459 .cfi_def_cfa_register 13 + 5460 @ sp needed + 5461 000e 5DF8047B ldr r7, [sp], #4 + 5462 .cfi_restore 7 + 5463 .cfi_def_cfa_offset 0 + 5464 0012 7047 bx lr + 5465 .cfi_endproc + 5466 .LFE152: + 5468 .section .text.HAL_SPI_RxHalfCpltCallback,"ax",%progbits + 5469 .align 1 + 5470 .weak HAL_SPI_RxHalfCpltCallback + 5471 .syntax unified + 5472 .thumb + 5473 .thumb_func + 5475 HAL_SPI_RxHalfCpltCallback: + 5476 .LFB153: +2919:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2920:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +2921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Rx Half Transfer completed callback. +2922:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +2923:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. + ARM GAS /tmp/ccs34gJO.s page 148 + + +2924:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +2925:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2926:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) +2927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5477 .loc 1 2927 1 + 5478 .cfi_startproc + 5479 @ args = 0, pretend = 0, frame = 8 + 5480 @ frame_needed = 1, uses_anonymous_args = 0 + 5481 @ link register save eliminated. + 5482 0000 80B4 push {r7} + 5483 .cfi_def_cfa_offset 4 + 5484 .cfi_offset 7, -4 + 5485 0002 83B0 sub sp, sp, #12 + 5486 .cfi_def_cfa_offset 16 + 5487 0004 00AF add r7, sp, #0 + 5488 .cfi_def_cfa_register 7 + 5489 0006 7860 str r0, [r7, #4] +2928:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Prevent unused argument(s) compilation warning */ +2929:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(hspi); +2930:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2931:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* NOTE : This function should not be modified, when the callback is needed, +2932:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file +2933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2934:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 5490 .loc 1 2934 1 + 5491 0008 00BF nop + 5492 000a 0C37 adds r7, r7, #12 + 5493 .cfi_def_cfa_offset 4 + 5494 000c BD46 mov sp, r7 + 5495 .cfi_def_cfa_register 13 + 5496 @ sp needed + 5497 000e 5DF8047B ldr r7, [sp], #4 + 5498 .cfi_restore 7 + 5499 .cfi_def_cfa_offset 0 + 5500 0012 7047 bx lr + 5501 .cfi_endproc + 5502 .LFE153: + 5504 .section .text.HAL_SPI_TxRxHalfCpltCallback,"ax",%progbits + 5505 .align 1 + 5506 .weak HAL_SPI_TxRxHalfCpltCallback + 5507 .syntax unified + 5508 .thumb + 5509 .thumb_func + 5511 HAL_SPI_TxRxHalfCpltCallback: + 5512 .LFB154: +2935:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2936:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +2937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Tx and Rx Half Transfer callback. +2938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +2939:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +2940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +2941:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) +2943:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5513 .loc 1 2943 1 + 5514 .cfi_startproc + 5515 @ args = 0, pretend = 0, frame = 8 + ARM GAS /tmp/ccs34gJO.s page 149 + + + 5516 @ frame_needed = 1, uses_anonymous_args = 0 + 5517 @ link register save eliminated. + 5518 0000 80B4 push {r7} + 5519 .cfi_def_cfa_offset 4 + 5520 .cfi_offset 7, -4 + 5521 0002 83B0 sub sp, sp, #12 + 5522 .cfi_def_cfa_offset 16 + 5523 0004 00AF add r7, sp, #0 + 5524 .cfi_def_cfa_register 7 + 5525 0006 7860 str r0, [r7, #4] +2944:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Prevent unused argument(s) compilation warning */ +2945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(hspi); +2946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2947:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* NOTE : This function should not be modified, when the callback is needed, +2948:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file +2949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2950:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 5526 .loc 1 2950 1 + 5527 0008 00BF nop + 5528 000a 0C37 adds r7, r7, #12 + 5529 .cfi_def_cfa_offset 4 + 5530 000c BD46 mov sp, r7 + 5531 .cfi_def_cfa_register 13 + 5532 @ sp needed + 5533 000e 5DF8047B ldr r7, [sp], #4 + 5534 .cfi_restore 7 + 5535 .cfi_def_cfa_offset 0 + 5536 0012 7047 bx lr + 5537 .cfi_endproc + 5538 .LFE154: + 5540 .section .text.HAL_SPI_ErrorCallback,"ax",%progbits + 5541 .align 1 + 5542 .weak HAL_SPI_ErrorCallback + 5543 .syntax unified + 5544 .thumb + 5545 .thumb_func + 5547 HAL_SPI_ErrorCallback: + 5548 .LFB155: +2951:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +2953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief SPI error callback. +2954:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +2955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +2956:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +2957:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2958:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) +2959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5549 .loc 1 2959 1 + 5550 .cfi_startproc + 5551 @ args = 0, pretend = 0, frame = 8 + 5552 @ frame_needed = 1, uses_anonymous_args = 0 + 5553 @ link register save eliminated. + 5554 0000 80B4 push {r7} + 5555 .cfi_def_cfa_offset 4 + 5556 .cfi_offset 7, -4 + 5557 0002 83B0 sub sp, sp, #12 + 5558 .cfi_def_cfa_offset 16 + ARM GAS /tmp/ccs34gJO.s page 150 + + + 5559 0004 00AF add r7, sp, #0 + 5560 .cfi_def_cfa_register 7 + 5561 0006 7860 str r0, [r7, #4] +2960:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Prevent unused argument(s) compilation warning */ +2961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(hspi); +2962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2963:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* NOTE : This function should not be modified, when the callback is needed, +2964:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** the HAL_SPI_ErrorCallback should be implemented in the user file +2965:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2966:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes +2967:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** and user can use HAL_SPI_GetError() API to check the latest error occurred +2968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2969:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 5562 .loc 1 2969 1 + 5563 0008 00BF nop + 5564 000a 0C37 adds r7, r7, #12 + 5565 .cfi_def_cfa_offset 4 + 5566 000c BD46 mov sp, r7 + 5567 .cfi_def_cfa_register 13 + 5568 @ sp needed + 5569 000e 5DF8047B ldr r7, [sp], #4 + 5570 .cfi_restore 7 + 5571 .cfi_def_cfa_offset 0 + 5572 0012 7047 bx lr + 5573 .cfi_endproc + 5574 .LFE155: + 5576 .section .text.HAL_SPI_AbortCpltCallback,"ax",%progbits + 5577 .align 1 + 5578 .weak HAL_SPI_AbortCpltCallback + 5579 .syntax unified + 5580 .thumb + 5581 .thumb_func + 5583 HAL_SPI_AbortCpltCallback: + 5584 .LFB156: +2970:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2971:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +2972:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief SPI Abort Complete callback. +2973:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi SPI handle. +2974:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +2975:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2976:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) +2977:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5585 .loc 1 2977 1 + 5586 .cfi_startproc + 5587 @ args = 0, pretend = 0, frame = 8 + 5588 @ frame_needed = 1, uses_anonymous_args = 0 + 5589 @ link register save eliminated. + 5590 0000 80B4 push {r7} + 5591 .cfi_def_cfa_offset 4 + 5592 .cfi_offset 7, -4 + 5593 0002 83B0 sub sp, sp, #12 + 5594 .cfi_def_cfa_offset 16 + 5595 0004 00AF add r7, sp, #0 + 5596 .cfi_def_cfa_register 7 + 5597 0006 7860 str r0, [r7, #4] +2978:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Prevent unused argument(s) compilation warning */ +2979:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(hspi); + ARM GAS /tmp/ccs34gJO.s page 151 + + +2980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2981:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* NOTE : This function should not be modified, when the callback is needed, +2982:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** the HAL_SPI_AbortCpltCallback can be implemented in the user file. +2983:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 5598 .loc 1 2984 1 + 5599 0008 00BF nop + 5600 000a 0C37 adds r7, r7, #12 + 5601 .cfi_def_cfa_offset 4 + 5602 000c BD46 mov sp, r7 + 5603 .cfi_def_cfa_register 13 + 5604 @ sp needed + 5605 000e 5DF8047B ldr r7, [sp], #4 + 5606 .cfi_restore 7 + 5607 .cfi_def_cfa_offset 0 + 5608 0012 7047 bx lr + 5609 .cfi_endproc + 5610 .LFE156: + 5612 .section .text.HAL_SPI_GetState,"ax",%progbits + 5613 .align 1 + 5614 .global HAL_SPI_GetState + 5615 .syntax unified + 5616 .thumb + 5617 .thumb_func + 5619 HAL_SPI_GetState: + 5620 .LFB157: +2985:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2986:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +2987:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @} +2988:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +2989:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +2990:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions +2991:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief SPI control functions +2992:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * +2993:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** @verbatim +2994:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** =============================================================================== +2995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** ##### Peripheral State and Errors functions ##### +2996:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** =============================================================================== +2997:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** [..] +2998:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** This subsection provides a set of functions allowing to control the SPI. +2999:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral +3000:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** (+) HAL_SPI_GetError() check in run-time Errors occurring during communication +3001:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** @endverbatim +3002:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @{ +3003:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3005:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3006:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Return the SPI handle state. +3007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +3008:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +3009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval SPI state +3010:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3011:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) +3012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5621 .loc 1 3012 1 + 5622 .cfi_startproc + 5623 @ args = 0, pretend = 0, frame = 8 + ARM GAS /tmp/ccs34gJO.s page 152 + + + 5624 @ frame_needed = 1, uses_anonymous_args = 0 + 5625 @ link register save eliminated. + 5626 0000 80B4 push {r7} + 5627 .cfi_def_cfa_offset 4 + 5628 .cfi_offset 7, -4 + 5629 0002 83B0 sub sp, sp, #12 + 5630 .cfi_def_cfa_offset 16 + 5631 0004 00AF add r7, sp, #0 + 5632 .cfi_def_cfa_register 7 + 5633 0006 7860 str r0, [r7, #4] +3013:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Return SPI handle state */ +3014:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return hspi->State; + 5634 .loc 1 3014 14 + 5635 0008 7B68 ldr r3, [r7, #4] + 5636 000a 93F85D30 ldrb r3, [r3, #93] + 5637 000e DBB2 uxtb r3, r3 +3015:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 5638 .loc 1 3015 1 + 5639 0010 1846 mov r0, r3 + 5640 0012 0C37 adds r7, r7, #12 + 5641 .cfi_def_cfa_offset 4 + 5642 0014 BD46 mov sp, r7 + 5643 .cfi_def_cfa_register 13 + 5644 @ sp needed + 5645 0016 5DF8047B ldr r7, [sp], #4 + 5646 .cfi_restore 7 + 5647 .cfi_def_cfa_offset 0 + 5648 001a 7047 bx lr + 5649 .cfi_endproc + 5650 .LFE157: + 5652 .section .text.HAL_SPI_GetError,"ax",%progbits + 5653 .align 1 + 5654 .global HAL_SPI_GetError + 5655 .syntax unified + 5656 .thumb + 5657 .thumb_func + 5659 HAL_SPI_GetError: + 5660 .LFB158: +3016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3017:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3018:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Return the SPI error code. +3019:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +3020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +3021:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval SPI error code in bitmap format +3022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3023:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) +3024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5661 .loc 1 3024 1 + 5662 .cfi_startproc + 5663 @ args = 0, pretend = 0, frame = 8 + 5664 @ frame_needed = 1, uses_anonymous_args = 0 + 5665 @ link register save eliminated. + 5666 0000 80B4 push {r7} + 5667 .cfi_def_cfa_offset 4 + 5668 .cfi_offset 7, -4 + 5669 0002 83B0 sub sp, sp, #12 + 5670 .cfi_def_cfa_offset 16 + ARM GAS /tmp/ccs34gJO.s page 153 + + + 5671 0004 00AF add r7, sp, #0 + 5672 .cfi_def_cfa_register 7 + 5673 0006 7860 str r0, [r7, #4] +3025:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Return SPI ErrorCode */ +3026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return hspi->ErrorCode; + 5674 .loc 1 3026 14 + 5675 0008 7B68 ldr r3, [r7, #4] + 5676 000a 1B6E ldr r3, [r3, #96] +3027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 5677 .loc 1 3027 1 + 5678 000c 1846 mov r0, r3 + 5679 000e 0C37 adds r7, r7, #12 + 5680 .cfi_def_cfa_offset 4 + 5681 0010 BD46 mov sp, r7 + 5682 .cfi_def_cfa_register 13 + 5683 @ sp needed + 5684 0012 5DF8047B ldr r7, [sp], #4 + 5685 .cfi_restore 7 + 5686 .cfi_def_cfa_offset 0 + 5687 0016 7047 bx lr + 5688 .cfi_endproc + 5689 .LFE158: + 5691 .section .text.SPI_DMATransmitCplt,"ax",%progbits + 5692 .align 1 + 5693 .syntax unified + 5694 .thumb + 5695 .thumb_func + 5697 SPI_DMATransmitCplt: + 5698 .LFB159: +3028:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3030:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @} +3031:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3032:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3033:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @} +3035:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3036:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** @addtogroup SPI_Private_Functions +3038:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Private functions +3039:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @{ +3040:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3041:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3043:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief DMA SPI transmit process complete callback. +3044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains +3045:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for the specified DMA module. +3046:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +3047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) +3049:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5699 .loc 1 3049 1 + 5700 .cfi_startproc + 5701 @ args = 0, pretend = 0, frame = 24 + 5702 @ frame_needed = 1, uses_anonymous_args = 0 + 5703 0000 80B5 push {r7, lr} + 5704 .cfi_def_cfa_offset 8 + ARM GAS /tmp/ccs34gJO.s page 154 + + + 5705 .cfi_offset 7, -8 + 5706 .cfi_offset 14, -4 + 5707 0002 86B0 sub sp, sp, #24 + 5708 .cfi_def_cfa_offset 32 + 5709 0004 00AF add r7, sp, #0 + 5710 .cfi_def_cfa_register 7 + 5711 0006 7860 str r0, [r7, #4] +3050:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati + 5712 .loc 1 3050 22 + 5713 0008 7B68 ldr r3, [r7, #4] + 5714 000a 5B6A ldr r3, [r3, #36] + 5715 000c 7B61 str r3, [r7, #20] +3051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t tickstart; +3052:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Init tickstart for timeout management*/ +3054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tickstart = HAL_GetTick(); + 5716 .loc 1 3054 15 + 5717 000e FFF7FEFF bl HAL_GetTick + 5718 0012 3861 str r0, [r7, #16] +3055:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* DMA Normal Mode */ +3057:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC) + 5719 .loc 1 3057 12 + 5720 0014 7B68 ldr r3, [r7, #4] + 5721 0016 1B68 ldr r3, [r3] + 5722 .loc 1 3057 22 + 5723 0018 1B68 ldr r3, [r3] + 5724 .loc 1 3057 28 + 5725 001a 03F02003 and r3, r3, #32 + 5726 .loc 1 3057 6 + 5727 001e 202B cmp r3, #32 + 5728 0020 3BD0 beq .L294 +3058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable ERR interrupt */ +3060:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); + 5729 .loc 1 3060 5 + 5730 0022 7B69 ldr r3, [r7, #20] + 5731 0024 1B68 ldr r3, [r3] + 5732 0026 5A68 ldr r2, [r3, #4] + 5733 0028 7B69 ldr r3, [r7, #20] + 5734 002a 1B68 ldr r3, [r3] + 5735 002c 22F02002 bic r2, r2, #32 + 5736 0030 5A60 str r2, [r3, #4] +3061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3062:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable Tx DMA Request */ +3063:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + 5737 .loc 1 3063 5 + 5738 0032 7B69 ldr r3, [r7, #20] + 5739 0034 1B68 ldr r3, [r3] + 5740 0036 5A68 ldr r2, [r3, #4] + 5741 0038 7B69 ldr r3, [r7, #20] + 5742 003a 1B68 ldr r3, [r3] + 5743 003c 22F00202 bic r2, r2, #2 + 5744 0040 5A60 str r2, [r3, #4] +3064:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check the end of the transaction */ +3066:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + ARM GAS /tmp/ccs34gJO.s page 155 + + + 5745 .loc 1 3066 9 + 5746 0042 3A69 ldr r2, [r7, #16] + 5747 0044 6421 movs r1, #100 + 5748 0046 7869 ldr r0, [r7, #20] + 5749 0048 FFF7FEFF bl SPI_EndRxTxTransaction + 5750 004c 0346 mov r3, r0 + 5751 .loc 1 3066 8 discriminator 1 + 5752 004e 002B cmp r3, #0 + 5753 0050 05D0 beq .L295 +3067:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + 5754 .loc 1 3068 7 + 5755 0052 7B69 ldr r3, [r7, #20] + 5756 0054 1B6E ldr r3, [r3, #96] + 5757 0056 43F02002 orr r2, r3, #32 + 5758 005a 7B69 ldr r3, [r7, #20] + 5759 005c 1A66 str r2, [r3, #96] + 5760 .L295: +3069:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3070:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Clear overrun flag in 2 Lines communication mode because received data is not read */ +3072:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + 5761 .loc 1 3072 19 + 5762 005e 7B69 ldr r3, [r7, #20] + 5763 0060 9B68 ldr r3, [r3, #8] + 5764 .loc 1 3072 8 + 5765 0062 002B cmp r3, #0 + 5766 0064 0AD1 bne .L296 + 5767 .LBB11: +3073:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3074:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_OVRFLAG(hspi); + 5768 .loc 1 3074 7 + 5769 0066 0023 movs r3, #0 + 5770 0068 FB60 str r3, [r7, #12] + 5771 006a 7B69 ldr r3, [r7, #20] + 5772 006c 1B68 ldr r3, [r3] + 5773 006e DB68 ldr r3, [r3, #12] + 5774 0070 FB60 str r3, [r7, #12] + 5775 0072 7B69 ldr r3, [r7, #20] + 5776 0074 1B68 ldr r3, [r3] + 5777 0076 9B68 ldr r3, [r3, #8] + 5778 0078 FB60 str r3, [r7, #12] + 5779 007a FB68 ldr r3, [r7, #12] + 5780 .L296: + 5781 .LBE11: +3075:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3076:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3077:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = 0U; + 5782 .loc 1 3077 23 + 5783 007c 7B69 ldr r3, [r7, #20] + 5784 007e 0022 movs r2, #0 + 5785 0080 DA87 strh r2, [r3, #62] @ movhi +3078:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; + 5786 .loc 1 3078 17 + 5787 0082 7B69 ldr r3, [r7, #20] + 5788 0084 0122 movs r2, #1 + 5789 0086 83F85D20 strb r2, [r3, #93] + ARM GAS /tmp/ccs34gJO.s page 156 + + +3079:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + 5790 .loc 1 3080 13 + 5791 008a 7B69 ldr r3, [r7, #20] + 5792 008c 1B6E ldr r3, [r3, #96] + 5793 .loc 1 3080 8 + 5794 008e 002B cmp r3, #0 + 5795 0090 03D0 beq .L294 +3081:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user error callback */ +3083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +3084:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCallback(hspi); +3085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else +3086:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_ErrorCallback(hspi); + 5796 .loc 1 3086 7 + 5797 0092 7869 ldr r0, [r7, #20] + 5798 0094 FFF7FEFF bl HAL_SPI_ErrorCallback +3087:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +3088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return; + 5799 .loc 1 3088 7 + 5800 0098 02E0 b .L293 + 5801 .L294: +3089:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3090:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3091:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user Tx complete callback */ +3092:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +3093:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxCpltCallback(hspi); +3094:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else +3095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_TxCpltCallback(hspi); + 5802 .loc 1 3095 3 + 5803 009a 7869 ldr r0, [r7, #20] + 5804 009c FFF7FEFF bl HAL_SPI_TxCpltCallback + 5805 .L293: +3096:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +3097:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 5806 .loc 1 3097 1 + 5807 00a0 1837 adds r7, r7, #24 + 5808 .cfi_def_cfa_offset 8 + 5809 00a2 BD46 mov sp, r7 + 5810 .cfi_def_cfa_register 13 + 5811 @ sp needed + 5812 00a4 80BD pop {r7, pc} + 5813 .cfi_endproc + 5814 .LFE159: + 5816 .section .text.SPI_DMAReceiveCplt,"ax",%progbits + 5817 .align 1 + 5818 .syntax unified + 5819 .thumb + 5820 .thumb_func + 5822 SPI_DMAReceiveCplt: + 5823 .LFB160: +3098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3099:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief DMA SPI receive process complete callback. +3101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains +3102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for the specified DMA module. +3103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None + ARM GAS /tmp/ccs34gJO.s page 157 + + +3104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +3106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5824 .loc 1 3106 1 + 5825 .cfi_startproc + 5826 @ args = 0, pretend = 0, frame = 16 + 5827 @ frame_needed = 1, uses_anonymous_args = 0 + 5828 0000 80B5 push {r7, lr} + 5829 .cfi_def_cfa_offset 8 + 5830 .cfi_offset 7, -8 + 5831 .cfi_offset 14, -4 + 5832 0002 84B0 sub sp, sp, #16 + 5833 .cfi_def_cfa_offset 24 + 5834 0004 00AF add r7, sp, #0 + 5835 .cfi_def_cfa_register 7 + 5836 0006 7860 str r0, [r7, #4] +3107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati + 5837 .loc 1 3107 22 + 5838 0008 7B68 ldr r3, [r7, #4] + 5839 000a 5B6A ldr r3, [r3, #36] + 5840 000c FB60 str r3, [r7, #12] +3108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t tickstart; +3109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +3110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint32_t tmpreg = 0U; +3111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint8_t *ptmpreg8; +3112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint8_t tmpreg8 = 0; +3113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +3114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Init tickstart for timeout management*/ +3116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tickstart = HAL_GetTick(); + 5841 .loc 1 3116 15 + 5842 000e FFF7FEFF bl HAL_GetTick + 5843 0012 B860 str r0, [r7, #8] +3117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* DMA Normal Mode */ +3119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC) + 5844 .loc 1 3119 12 + 5845 0014 7B68 ldr r3, [r7, #4] + 5846 0016 1B68 ldr r3, [r3] + 5847 .loc 1 3119 22 + 5848 0018 1B68 ldr r3, [r3] + 5849 .loc 1 3119 28 + 5850 001a 03F02003 and r3, r3, #32 + 5851 .loc 1 3119 6 + 5852 001e 202B cmp r3, #32 + 5853 0020 3CD0 beq .L299 +3120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable ERR interrupt */ +3122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); + 5854 .loc 1 3122 5 + 5855 0022 FB68 ldr r3, [r7, #12] + 5856 0024 1B68 ldr r3, [r3] + 5857 0026 5A68 ldr r2, [r3, #4] + 5858 0028 FB68 ldr r3, [r7, #12] + 5859 002a 1B68 ldr r3, [r3] + 5860 002c 22F02002 bic r2, r2, #32 + 5861 0030 5A60 str r2, [r3, #4] + ARM GAS /tmp/ccs34gJO.s page 158 + + +3123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +3125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* CRC handling */ +3126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +3127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Wait until RXNE flag */ +3129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) ! +3130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Error on the CRC reception */ +3132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); +3133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Read CRC */ +3135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) +3136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Read 16bit CRC */ +3138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmpreg = READ_REG(hspi->Instance->DR); +3139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* To avoid GCC warning */ +3140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(tmpreg); +3141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +3143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Initialize the 8bit temporary pointer */ +3145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; +3146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Read 8bit CRC */ +3147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmpreg8 = *ptmpreg8; +3148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* To avoid GCC warning */ +3149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(tmpreg8); +3150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) +3152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstar +3154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Error on the CRC reception */ +3156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); +3157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ +3159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmpreg8 = *ptmpreg8; +3160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* To avoid GCC warning */ +3161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(tmpreg8); +3162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +3166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check if we are in Master RX 2 line mode */ +3168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) + 5862 .loc 1 3168 20 + 5863 0032 FB68 ldr r3, [r7, #12] + 5864 0034 9B68 ldr r3, [r3, #8] + 5865 .loc 1 3168 8 + 5866 0036 002B cmp r3, #0 + 5867 0038 0DD1 bne .L300 + 5868 .loc 1 3168 70 discriminator 1 + 5869 003a FB68 ldr r3, [r7, #12] + 5870 003c 5B68 ldr r3, [r3, #4] + 5871 .loc 1 3168 56 discriminator 1 + 5872 003e B3F5827F cmp r3, #260 + ARM GAS /tmp/ccs34gJO.s page 159 + + + 5873 0042 08D1 bne .L300 +3169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) +3171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + 5874 .loc 1 3171 7 + 5875 0044 FB68 ldr r3, [r7, #12] + 5876 0046 1B68 ldr r3, [r3] + 5877 0048 5A68 ldr r2, [r3, #4] + 5878 004a FB68 ldr r3, [r7, #12] + 5879 004c 1B68 ldr r3, [r3] + 5880 004e 22F00302 bic r2, r2, #3 + 5881 0052 5A60 str r2, [r3, #4] + 5882 0054 07E0 b .L301 + 5883 .L300: +3172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +3174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Normal case */ +3176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + 5884 .loc 1 3176 7 + 5885 0056 FB68 ldr r3, [r7, #12] + 5886 0058 1B68 ldr r3, [r3] + 5887 005a 5A68 ldr r2, [r3, #4] + 5888 005c FB68 ldr r3, [r7, #12] + 5889 005e 1B68 ldr r3, [r3] + 5890 0060 22F00102 bic r2, r2, #1 + 5891 0064 5A60 str r2, [r3, #4] + 5892 .L301: +3177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check the end of the transaction */ +3180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + 5893 .loc 1 3180 9 + 5894 0066 BA68 ldr r2, [r7, #8] + 5895 0068 6421 movs r1, #100 + 5896 006a F868 ldr r0, [r7, #12] + 5897 006c FFF7FEFF bl SPI_EndRxTransaction + 5898 0070 0346 mov r3, r0 + 5899 .loc 1 3180 8 discriminator 1 + 5900 0072 002B cmp r3, #0 + 5901 0074 02D0 beq .L302 +3181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + 5902 .loc 1 3182 23 + 5903 0076 FB68 ldr r3, [r7, #12] + 5904 0078 2022 movs r2, #32 + 5905 007a 1A66 str r2, [r3, #96] + 5906 .L302: +3183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = 0U; + 5907 .loc 1 3185 23 + 5908 007c FB68 ldr r3, [r7, #12] + 5909 007e 0022 movs r2, #0 + 5910 0080 A3F84620 strh r2, [r3, #70] @ movhi +3186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; + 5911 .loc 1 3186 17 + ARM GAS /tmp/ccs34gJO.s page 160 + + + 5912 0084 FB68 ldr r3, [r7, #12] + 5913 0086 0122 movs r2, #1 + 5914 0088 83F85D20 strb r2, [r3, #93] +3187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +3189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check if CRC error occurred */ +3190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) +3191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); +3193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_CRCERRFLAG(hspi); +3194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +3196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + 5915 .loc 1 3197 13 + 5916 008c FB68 ldr r3, [r7, #12] + 5917 008e 1B6E ldr r3, [r3, #96] + 5918 .loc 1 3197 8 + 5919 0090 002B cmp r3, #0 + 5920 0092 03D0 beq .L299 +3198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user error callback */ +3200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +3201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCallback(hspi); +3202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else +3203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_ErrorCallback(hspi); + 5921 .loc 1 3203 7 + 5922 0094 F868 ldr r0, [r7, #12] + 5923 0096 FFF7FEFF bl HAL_SPI_ErrorCallback +3204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +3205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return; + 5924 .loc 1 3205 7 + 5925 009a 02E0 b .L298 + 5926 .L299: +3206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user Rx complete callback */ +3209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +3210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxCpltCallback(hspi); +3211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else +3212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_RxCpltCallback(hspi); + 5927 .loc 1 3212 3 + 5928 009c F868 ldr r0, [r7, #12] + 5929 009e FFF7FEFF bl HAL_SPI_RxCpltCallback + 5930 .L298: +3213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +3214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 5931 .loc 1 3214 1 + 5932 00a2 1037 adds r7, r7, #16 + 5933 .cfi_def_cfa_offset 8 + 5934 00a4 BD46 mov sp, r7 + 5935 .cfi_def_cfa_register 13 + 5936 @ sp needed + 5937 00a6 80BD pop {r7, pc} + 5938 .cfi_endproc + 5939 .LFE160: + 5941 .section .text.SPI_DMATransmitReceiveCplt,"ax",%progbits + ARM GAS /tmp/ccs34gJO.s page 161 + + + 5942 .align 1 + 5943 .syntax unified + 5944 .thumb + 5945 .thumb_func + 5947 SPI_DMATransmitReceiveCplt: + 5948 .LFB161: +3215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief DMA SPI transmit receive process complete callback. +3218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains +3219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for the specified DMA module. +3220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +3221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) +3223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 5949 .loc 1 3223 1 + 5950 .cfi_startproc + 5951 @ args = 0, pretend = 0, frame = 16 + 5952 @ frame_needed = 1, uses_anonymous_args = 0 + 5953 0000 80B5 push {r7, lr} + 5954 .cfi_def_cfa_offset 8 + 5955 .cfi_offset 7, -8 + 5956 .cfi_offset 14, -4 + 5957 0002 84B0 sub sp, sp, #16 + 5958 .cfi_def_cfa_offset 24 + 5959 0004 00AF add r7, sp, #0 + 5960 .cfi_def_cfa_register 7 + 5961 0006 7860 str r0, [r7, #4] +3224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati + 5962 .loc 1 3224 22 + 5963 0008 7B68 ldr r3, [r7, #4] + 5964 000a 5B6A ldr r3, [r3, #36] + 5965 000c FB60 str r3, [r7, #12] +3225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t tickstart; +3226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +3227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint32_t tmpreg = 0U; +3228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint8_t *ptmpreg8; +3229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint8_t tmpreg8 = 0; +3230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +3231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Init tickstart for timeout management*/ +3233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tickstart = HAL_GetTick(); + 5966 .loc 1 3233 15 + 5967 000e FFF7FEFF bl HAL_GetTick + 5968 0012 B860 str r0, [r7, #8] +3234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* DMA Normal Mode */ +3236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC) + 5969 .loc 1 3236 12 + 5970 0014 7B68 ldr r3, [r7, #4] + 5971 0016 1B68 ldr r3, [r3] + 5972 .loc 1 3236 22 + 5973 0018 1B68 ldr r3, [r3] + 5974 .loc 1 3236 28 + 5975 001a 03F02003 and r3, r3, #32 + 5976 .loc 1 3236 6 + 5977 001e 202B cmp r3, #32 + ARM GAS /tmp/ccs34gJO.s page 162 + + + 5978 0020 30D0 beq .L305 +3237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable ERR interrupt */ +3239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); + 5979 .loc 1 3239 5 + 5980 0022 FB68 ldr r3, [r7, #12] + 5981 0024 1B68 ldr r3, [r3] + 5982 0026 5A68 ldr r2, [r3, #4] + 5983 0028 FB68 ldr r3, [r7, #12] + 5984 002a 1B68 ldr r3, [r3] + 5985 002c 22F02002 bic r2, r2, #32 + 5986 0030 5A60 str r2, [r3, #4] +3240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +3242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* CRC handling */ +3243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +3244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BI +3246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT +3248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tickstart) != HAL_OK) +3249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Error on the CRC reception */ +3251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); +3252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Initialize the 8bit temporary pointer */ +3254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; +3255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Read 8bit CRC */ +3256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmpreg8 = *ptmpreg8; +3257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* To avoid GCC warning */ +3258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(tmpreg8); +3259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +3261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TI +3263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Error on the CRC reception */ +3265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); +3266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Read CRC to Flush DR and RXNE flag */ +3268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmpreg = READ_REG(hspi->Instance->DR); +3269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* To avoid GCC warning */ +3270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(tmpreg); +3271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +3274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check the end of the transaction */ +3276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + 5987 .loc 1 3276 9 + 5988 0032 BA68 ldr r2, [r7, #8] + 5989 0034 6421 movs r1, #100 + 5990 0036 F868 ldr r0, [r7, #12] + 5991 0038 FFF7FEFF bl SPI_EndRxTxTransaction + 5992 003c 0346 mov r3, r0 + 5993 .loc 1 3276 8 discriminator 1 + 5994 003e 002B cmp r3, #0 + ARM GAS /tmp/ccs34gJO.s page 163 + + + 5995 0040 05D0 beq .L306 +3277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + 5996 .loc 1 3278 7 + 5997 0042 FB68 ldr r3, [r7, #12] + 5998 0044 1B6E ldr r3, [r3, #96] + 5999 0046 43F02002 orr r2, r3, #32 + 6000 004a FB68 ldr r3, [r7, #12] + 6001 004c 1A66 str r2, [r3, #96] + 6002 .L306: +3279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable Rx/Tx DMA Request */ +3282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + 6003 .loc 1 3282 5 + 6004 004e FB68 ldr r3, [r7, #12] + 6005 0050 1B68 ldr r3, [r3] + 6006 0052 5A68 ldr r2, [r3, #4] + 6007 0054 FB68 ldr r3, [r7, #12] + 6008 0056 1B68 ldr r3, [r3] + 6009 0058 22F00302 bic r2, r2, #3 + 6010 005c 5A60 str r2, [r3, #4] +3283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = 0U; + 6011 .loc 1 3284 23 + 6012 005e FB68 ldr r3, [r7, #12] + 6013 0060 0022 movs r2, #0 + 6014 0062 DA87 strh r2, [r3, #62] @ movhi +3285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = 0U; + 6015 .loc 1 3285 23 + 6016 0064 FB68 ldr r3, [r7, #12] + 6017 0066 0022 movs r2, #0 + 6018 0068 A3F84620 strh r2, [r3, #70] @ movhi +3286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; + 6019 .loc 1 3286 17 + 6020 006c FB68 ldr r3, [r7, #12] + 6021 006e 0122 movs r2, #1 + 6022 0070 83F85D20 strb r2, [r3, #93] +3287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +3289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check if CRC error occurred */ +3290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) +3291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); +3293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_CRCERRFLAG(hspi); +3294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +3296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + 6023 .loc 1 3297 13 + 6024 0074 FB68 ldr r3, [r7, #12] + 6025 0076 1B6E ldr r3, [r3, #96] + 6026 .loc 1 3297 8 + 6027 0078 002B cmp r3, #0 + 6028 007a 03D0 beq .L305 +3298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user error callback */ + ARM GAS /tmp/ccs34gJO.s page 164 + + +3300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +3301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCallback(hspi); +3302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else +3303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_ErrorCallback(hspi); + 6029 .loc 1 3303 7 + 6030 007c F868 ldr r0, [r7, #12] + 6031 007e FFF7FEFF bl HAL_SPI_ErrorCallback +3304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +3305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return; + 6032 .loc 1 3305 7 + 6033 0082 02E0 b .L304 + 6034 .L305: +3306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user TxRx complete callback */ +3309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +3310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxRxCpltCallback(hspi); +3311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else +3312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_TxRxCpltCallback(hspi); + 6035 .loc 1 3312 3 + 6036 0084 F868 ldr r0, [r7, #12] + 6037 0086 FFF7FEFF bl HAL_SPI_TxRxCpltCallback + 6038 .L304: +3313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +3314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6039 .loc 1 3314 1 + 6040 008a 1037 adds r7, r7, #16 + 6041 .cfi_def_cfa_offset 8 + 6042 008c BD46 mov sp, r7 + 6043 .cfi_def_cfa_register 13 + 6044 @ sp needed + 6045 008e 80BD pop {r7, pc} + 6046 .cfi_endproc + 6047 .LFE161: + 6049 .section .text.SPI_DMAHalfTransmitCplt,"ax",%progbits + 6050 .align 1 + 6051 .syntax unified + 6052 .thumb + 6053 .thumb_func + 6055 SPI_DMAHalfTransmitCplt: + 6056 .LFB162: +3315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief DMA SPI half transmit process complete callback. +3318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains +3319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for the specified DMA module. +3320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +3321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) +3323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6057 .loc 1 3323 1 + 6058 .cfi_startproc + 6059 @ args = 0, pretend = 0, frame = 16 + 6060 @ frame_needed = 1, uses_anonymous_args = 0 + 6061 0000 80B5 push {r7, lr} + 6062 .cfi_def_cfa_offset 8 + 6063 .cfi_offset 7, -8 + ARM GAS /tmp/ccs34gJO.s page 165 + + + 6064 .cfi_offset 14, -4 + 6065 0002 84B0 sub sp, sp, #16 + 6066 .cfi_def_cfa_offset 24 + 6067 0004 00AF add r7, sp, #0 + 6068 .cfi_def_cfa_register 7 + 6069 0006 7860 str r0, [r7, #4] +3324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati + 6070 .loc 1 3324 22 + 6071 0008 7B68 ldr r3, [r7, #4] + 6072 000a 5B6A ldr r3, [r3, #36] + 6073 000c FB60 str r3, [r7, #12] +3325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user Tx half complete callback */ +3327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +3328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxHalfCpltCallback(hspi); +3329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else +3330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_TxHalfCpltCallback(hspi); + 6074 .loc 1 3330 3 + 6075 000e F868 ldr r0, [r7, #12] + 6076 0010 FFF7FEFF bl HAL_SPI_TxHalfCpltCallback +3331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +3332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6077 .loc 1 3332 1 + 6078 0014 00BF nop + 6079 0016 1037 adds r7, r7, #16 + 6080 .cfi_def_cfa_offset 8 + 6081 0018 BD46 mov sp, r7 + 6082 .cfi_def_cfa_register 13 + 6083 @ sp needed + 6084 001a 80BD pop {r7, pc} + 6085 .cfi_endproc + 6086 .LFE162: + 6088 .section .text.SPI_DMAHalfReceiveCplt,"ax",%progbits + 6089 .align 1 + 6090 .syntax unified + 6091 .thumb + 6092 .thumb_func + 6094 SPI_DMAHalfReceiveCplt: + 6095 .LFB163: +3333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief DMA SPI half receive process complete callback +3336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains +3337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for the specified DMA module. +3338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +3339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) +3341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6096 .loc 1 3341 1 + 6097 .cfi_startproc + 6098 @ args = 0, pretend = 0, frame = 16 + 6099 @ frame_needed = 1, uses_anonymous_args = 0 + 6100 0000 80B5 push {r7, lr} + 6101 .cfi_def_cfa_offset 8 + 6102 .cfi_offset 7, -8 + 6103 .cfi_offset 14, -4 + 6104 0002 84B0 sub sp, sp, #16 + ARM GAS /tmp/ccs34gJO.s page 166 + + + 6105 .cfi_def_cfa_offset 24 + 6106 0004 00AF add r7, sp, #0 + 6107 .cfi_def_cfa_register 7 + 6108 0006 7860 str r0, [r7, #4] +3342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati + 6109 .loc 1 3342 22 + 6110 0008 7B68 ldr r3, [r7, #4] + 6111 000a 5B6A ldr r3, [r3, #36] + 6112 000c FB60 str r3, [r7, #12] +3343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user Rx half complete callback */ +3345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +3346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxHalfCpltCallback(hspi); +3347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else +3348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_RxHalfCpltCallback(hspi); + 6113 .loc 1 3348 3 + 6114 000e F868 ldr r0, [r7, #12] + 6115 0010 FFF7FEFF bl HAL_SPI_RxHalfCpltCallback +3349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +3350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6116 .loc 1 3350 1 + 6117 0014 00BF nop + 6118 0016 1037 adds r7, r7, #16 + 6119 .cfi_def_cfa_offset 8 + 6120 0018 BD46 mov sp, r7 + 6121 .cfi_def_cfa_register 13 + 6122 @ sp needed + 6123 001a 80BD pop {r7, pc} + 6124 .cfi_endproc + 6125 .LFE163: + 6127 .section .text.SPI_DMAHalfTransmitReceiveCplt,"ax",%progbits + 6128 .align 1 + 6129 .syntax unified + 6130 .thumb + 6131 .thumb_func + 6133 SPI_DMAHalfTransmitReceiveCplt: + 6134 .LFB164: +3351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief DMA SPI half transmit receive process complete callback. +3354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains +3355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for the specified DMA module. +3356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +3357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) +3359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6135 .loc 1 3359 1 + 6136 .cfi_startproc + 6137 @ args = 0, pretend = 0, frame = 16 + 6138 @ frame_needed = 1, uses_anonymous_args = 0 + 6139 0000 80B5 push {r7, lr} + 6140 .cfi_def_cfa_offset 8 + 6141 .cfi_offset 7, -8 + 6142 .cfi_offset 14, -4 + 6143 0002 84B0 sub sp, sp, #16 + 6144 .cfi_def_cfa_offset 24 + 6145 0004 00AF add r7, sp, #0 + ARM GAS /tmp/ccs34gJO.s page 167 + + + 6146 .cfi_def_cfa_register 7 + 6147 0006 7860 str r0, [r7, #4] +3360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati + 6148 .loc 1 3360 22 + 6149 0008 7B68 ldr r3, [r7, #4] + 6150 000a 5B6A ldr r3, [r3, #36] + 6151 000c FB60 str r3, [r7, #12] +3361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user TxRx half complete callback */ +3363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +3364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxRxHalfCpltCallback(hspi); +3365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else +3366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_TxRxHalfCpltCallback(hspi); + 6152 .loc 1 3366 3 + 6153 000e F868 ldr r0, [r7, #12] + 6154 0010 FFF7FEFF bl HAL_SPI_TxRxHalfCpltCallback +3367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +3368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6155 .loc 1 3368 1 + 6156 0014 00BF nop + 6157 0016 1037 adds r7, r7, #16 + 6158 .cfi_def_cfa_offset 8 + 6159 0018 BD46 mov sp, r7 + 6160 .cfi_def_cfa_register 13 + 6161 @ sp needed + 6162 001a 80BD pop {r7, pc} + 6163 .cfi_endproc + 6164 .LFE164: + 6166 .section .text.SPI_DMAError,"ax",%progbits + 6167 .align 1 + 6168 .syntax unified + 6169 .thumb + 6170 .thumb_func + 6172 SPI_DMAError: + 6173 .LFB165: +3369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief DMA SPI communication error callback. +3372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hdma pointer to a DMA_HandleTypeDef structure that contains +3373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for the specified DMA module. +3374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +3375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_DMAError(DMA_HandleTypeDef *hdma) +3377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6174 .loc 1 3377 1 + 6175 .cfi_startproc + 6176 @ args = 0, pretend = 0, frame = 16 + 6177 @ frame_needed = 1, uses_anonymous_args = 0 + 6178 0000 80B5 push {r7, lr} + 6179 .cfi_def_cfa_offset 8 + 6180 .cfi_offset 7, -8 + 6181 .cfi_offset 14, -4 + 6182 0002 84B0 sub sp, sp, #16 + 6183 .cfi_def_cfa_offset 24 + 6184 0004 00AF add r7, sp, #0 + 6185 .cfi_def_cfa_register 7 + 6186 0006 7860 str r0, [r7, #4] + ARM GAS /tmp/ccs34gJO.s page 168 + + +3378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati + 6187 .loc 1 3378 22 + 6188 0008 7B68 ldr r3, [r7, #4] + 6189 000a 5B6A ldr r3, [r3, #36] + 6190 000c FB60 str r3, [r7, #12] +3379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Stop the disable DMA transfer on SPI side */ +3381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + 6191 .loc 1 3381 3 + 6192 000e FB68 ldr r3, [r7, #12] + 6193 0010 1B68 ldr r3, [r3] + 6194 0012 5A68 ldr r2, [r3, #4] + 6195 0014 FB68 ldr r3, [r7, #12] + 6196 0016 1B68 ldr r3, [r3] + 6197 0018 22F00302 bic r2, r2, #3 + 6198 001c 5A60 str r2, [r3, #4] +3382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + 6199 .loc 1 3383 3 + 6200 001e FB68 ldr r3, [r7, #12] + 6201 0020 1B6E ldr r3, [r3, #96] + 6202 0022 43F01002 orr r2, r3, #16 + 6203 0026 FB68 ldr r3, [r7, #12] + 6204 0028 1A66 str r2, [r3, #96] +3384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; + 6205 .loc 1 3384 15 + 6206 002a FB68 ldr r3, [r7, #12] + 6207 002c 0122 movs r2, #1 + 6208 002e 83F85D20 strb r2, [r3, #93] +3385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user error callback */ +3386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +3387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCallback(hspi); +3388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else +3389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_ErrorCallback(hspi); + 6209 .loc 1 3389 3 + 6210 0032 F868 ldr r0, [r7, #12] + 6211 0034 FFF7FEFF bl HAL_SPI_ErrorCallback +3390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +3391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6212 .loc 1 3391 1 + 6213 0038 00BF nop + 6214 003a 1037 adds r7, r7, #16 + 6215 .cfi_def_cfa_offset 8 + 6216 003c BD46 mov sp, r7 + 6217 .cfi_def_cfa_register 13 + 6218 @ sp needed + 6219 003e 80BD pop {r7, pc} + 6220 .cfi_endproc + 6221 .LFE165: + 6223 .section .text.SPI_DMAAbortOnError,"ax",%progbits + 6224 .align 1 + 6225 .syntax unified + 6226 .thumb + 6227 .thumb_func + 6229 SPI_DMAAbortOnError: + 6230 .LFB166: +3392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + ARM GAS /tmp/ccs34gJO.s page 169 + + +3393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief DMA SPI communication abort callback, when initiated by HAL services on Error +3395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * (To be called at end of DMA Abort procedure following error occurrence). +3396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hdma DMA handle. +3397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +3398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) +3400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6231 .loc 1 3400 1 + 6232 .cfi_startproc + 6233 @ args = 0, pretend = 0, frame = 16 + 6234 @ frame_needed = 1, uses_anonymous_args = 0 + 6235 0000 80B5 push {r7, lr} + 6236 .cfi_def_cfa_offset 8 + 6237 .cfi_offset 7, -8 + 6238 .cfi_offset 14, -4 + 6239 0002 84B0 sub sp, sp, #16 + 6240 .cfi_def_cfa_offset 24 + 6241 0004 00AF add r7, sp, #0 + 6242 .cfi_def_cfa_register 7 + 6243 0006 7860 str r0, [r7, #4] +3401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati + 6244 .loc 1 3401 22 + 6245 0008 7B68 ldr r3, [r7, #4] + 6246 000a 5B6A ldr r3, [r3, #36] + 6247 000c FB60 str r3, [r7, #12] +3402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = 0U; + 6248 .loc 1 3402 21 + 6249 000e FB68 ldr r3, [r7, #12] + 6250 0010 0022 movs r2, #0 + 6251 0012 A3F84620 strh r2, [r3, #70] @ movhi +3403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = 0U; + 6252 .loc 1 3403 21 + 6253 0016 FB68 ldr r3, [r7, #12] + 6254 0018 0022 movs r2, #0 + 6255 001a DA87 strh r2, [r3, #62] @ movhi +3404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user error callback */ +3406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +3407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCallback(hspi); +3408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else +3409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_ErrorCallback(hspi); + 6256 .loc 1 3409 3 + 6257 001c F868 ldr r0, [r7, #12] + 6258 001e FFF7FEFF bl HAL_SPI_ErrorCallback +3410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +3411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6259 .loc 1 3411 1 + 6260 0022 00BF nop + 6261 0024 1037 adds r7, r7, #16 + 6262 .cfi_def_cfa_offset 8 + 6263 0026 BD46 mov sp, r7 + 6264 .cfi_def_cfa_register 13 + 6265 @ sp needed + 6266 0028 80BD pop {r7, pc} + 6267 .cfi_endproc + 6268 .LFE166: + ARM GAS /tmp/ccs34gJO.s page 170 + + + 6270 .section .text.SPI_DMATxAbortCallback,"ax",%progbits + 6271 .align 1 + 6272 .syntax unified + 6273 .thumb + 6274 .thumb_func + 6276 SPI_DMATxAbortCallback: + 6277 .LFB167: +3412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief DMA SPI Tx communication abort callback, when initiated by user +3415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * (To be called at end of DMA Tx Abort procedure following user abort request). +3416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @note When this callback is executed, User Abort complete call back is called only if no +3417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * Abort still ongoing for Rx DMA Handle. +3418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hdma DMA handle. +3419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +3420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +3422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6278 .loc 1 3422 1 + 6279 .cfi_startproc + 6280 @ args = 0, pretend = 0, frame = 24 + 6281 @ frame_needed = 1, uses_anonymous_args = 0 + 6282 0000 80B5 push {r7, lr} + 6283 .cfi_def_cfa_offset 8 + 6284 .cfi_offset 7, -8 + 6285 .cfi_offset 14, -4 + 6286 0002 88B0 sub sp, sp, #32 + 6287 .cfi_def_cfa_offset 40 + 6288 0004 02AF add r7, sp, #8 + 6289 .cfi_def_cfa 7, 32 + 6290 0006 7860 str r0, [r7, #4] +3423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati + 6291 .loc 1 3423 22 + 6292 0008 7B68 ldr r3, [r7, #4] + 6293 000a 5B6A ldr r3, [r3, #36] + 6294 000c 7B61 str r3, [r7, #20] +3424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmatx->XferAbortCallback = NULL; + 6295 .loc 1 3425 7 + 6296 000e 7B69 ldr r3, [r7, #20] + 6297 0010 5B6D ldr r3, [r3, #84] + 6298 .loc 1 3425 35 + 6299 0012 0022 movs r2, #0 + 6300 0014 5A63 str r2, [r3, #52] +3426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable Tx DMA Request */ +3428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + 6301 .loc 1 3428 3 + 6302 0016 7B69 ldr r3, [r7, #20] + 6303 0018 1B68 ldr r3, [r3] + 6304 001a 5A68 ldr r2, [r3, #4] + 6305 001c 7B69 ldr r3, [r7, #20] + 6306 001e 1B68 ldr r3, [r3] + 6307 0020 22F00202 bic r2, r2, #2 + 6308 0024 5A60 str r2, [r3, #4] +3429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + ARM GAS /tmp/ccs34gJO.s page 171 + + + 6309 .loc 1 3430 7 + 6310 0026 FFF7FEFF bl HAL_GetTick + 6311 002a 0346 mov r3, r0 + 6312 .loc 1 3430 7 is_stmt 0 discriminator 1 + 6313 002c 1A46 mov r2, r3 + 6314 002e 6421 movs r1, #100 + 6315 0030 7869 ldr r0, [r7, #20] + 6316 0032 FFF7FEFF bl SPI_EndRxTxTransaction + 6317 0036 0346 mov r3, r0 + 6318 .loc 1 3430 6 is_stmt 1 discriminator 2 + 6319 0038 002B cmp r3, #0 + 6320 003a 02D0 beq .L314 +3431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + 6321 .loc 1 3432 21 + 6322 003c 7B69 ldr r3, [r7, #20] + 6323 003e 4022 movs r2, #64 + 6324 0040 1A66 str r2, [r3, #96] + 6325 .L314: +3433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable SPI Peripheral */ +3436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE(hspi); + 6326 .loc 1 3436 3 + 6327 0042 7B69 ldr r3, [r7, #20] + 6328 0044 1B68 ldr r3, [r3] + 6329 0046 1A68 ldr r2, [r3] + 6330 0048 7B69 ldr r3, [r7, #20] + 6331 004a 1B68 ldr r3, [r3] + 6332 004c 22F04002 bic r2, r2, #64 + 6333 0050 1A60 str r2, [r3] +3437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Empty the FRLVL fifo */ +3439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL + 6334 .loc 1 3439 7 + 6335 0052 FFF7FEFF bl HAL_GetTick + 6336 0056 0346 mov r3, r0 + 6337 .loc 1 3439 7 is_stmt 0 discriminator 1 + 6338 0058 0093 str r3, [sp] + 6339 005a 6423 movs r3, #100 + 6340 005c 0022 movs r2, #0 + 6341 005e 4FF4C061 mov r1, #1536 + 6342 0062 7869 ldr r0, [r7, #20] + 6343 0064 FFF7FEFF bl SPI_WaitFifoStateUntilTimeout + 6344 0068 0346 mov r3, r0 + 6345 .loc 1 3439 6 is_stmt 1 discriminator 2 + 6346 006a 002B cmp r3, #0 + 6347 006c 02D0 beq .L315 +3440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + 6348 .loc 1 3441 21 + 6349 006e 7B69 ldr r3, [r7, #20] + 6350 0070 4022 movs r2, #64 + 6351 0072 1A66 str r2, [r3, #96] + 6352 .L315: +3442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + ARM GAS /tmp/ccs34gJO.s page 172 + + +3444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check if an Abort process is still ongoing */ +3445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->hdmarx != NULL) + 6353 .loc 1 3445 11 + 6354 0074 7B69 ldr r3, [r7, #20] + 6355 0076 9B6D ldr r3, [r3, #88] + 6356 .loc 1 3445 6 + 6357 0078 002B cmp r3, #0 + 6358 007a 04D0 beq .L316 +3446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->hdmarx->XferAbortCallback != NULL) + 6359 .loc 1 3447 13 + 6360 007c 7B69 ldr r3, [r7, #20] + 6361 007e 9B6D ldr r3, [r3, #88] + 6362 .loc 1 3447 21 + 6363 0080 5B6B ldr r3, [r3, #52] + 6364 .loc 1 3447 8 + 6365 0082 002B cmp r3, #0 + 6366 0084 27D1 bne .L319 + 6367 .L316: +3448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return; +3450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete +3454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = 0U; + 6368 .loc 1 3454 21 + 6369 0086 7B69 ldr r3, [r7, #20] + 6370 0088 0022 movs r2, #0 + 6371 008a A3F84620 strh r2, [r3, #70] @ movhi +3455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = 0U; + 6372 .loc 1 3455 21 + 6373 008e 7B69 ldr r3, [r7, #20] + 6374 0090 0022 movs r2, #0 + 6375 0092 DA87 strh r2, [r3, #62] @ movhi +3456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check no error during Abort procedure */ +3458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT) + 6376 .loc 1 3458 11 + 6377 0094 7B69 ldr r3, [r7, #20] + 6378 0096 1B6E ldr r3, [r3, #96] + 6379 .loc 1 3458 6 + 6380 0098 402B cmp r3, #64 + 6381 009a 02D0 beq .L318 +3459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset errorCode */ +3461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 6382 .loc 1 3461 21 + 6383 009c 7B69 ldr r3, [r7, #20] + 6384 009e 0022 movs r2, #0 + 6385 00a0 1A66 str r2, [r3, #96] + 6386 .L318: + 6387 .LBB12: +3462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Clear the Error flags in the SR register */ +3465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_OVRFLAG(hspi); + ARM GAS /tmp/ccs34gJO.s page 173 + + + 6388 .loc 1 3465 3 + 6389 00a2 0023 movs r3, #0 + 6390 00a4 3B61 str r3, [r7, #16] + 6391 00a6 7B69 ldr r3, [r7, #20] + 6392 00a8 1B68 ldr r3, [r3] + 6393 00aa DB68 ldr r3, [r3, #12] + 6394 00ac 3B61 str r3, [r7, #16] + 6395 00ae 7B69 ldr r3, [r7, #20] + 6396 00b0 1B68 ldr r3, [r3] + 6397 00b2 9B68 ldr r3, [r3, #8] + 6398 00b4 3B61 str r3, [r7, #16] + 6399 00b6 3B69 ldr r3, [r7, #16] + 6400 .LBE12: + 6401 .LBB13: +3466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_FREFLAG(hspi); + 6402 .loc 1 3466 3 + 6403 00b8 0023 movs r3, #0 + 6404 00ba FB60 str r3, [r7, #12] + 6405 00bc 7B69 ldr r3, [r7, #20] + 6406 00be 1B68 ldr r3, [r3] + 6407 00c0 9B68 ldr r3, [r3, #8] + 6408 00c2 FB60 str r3, [r7, #12] + 6409 00c4 FB68 ldr r3, [r7, #12] + 6410 .LBE13: +3467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Restore hspi->State to Ready */ +3469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; + 6411 .loc 1 3469 16 + 6412 00c6 7B69 ldr r3, [r7, #20] + 6413 00c8 0122 movs r2, #1 + 6414 00ca 83F85D20 strb r2, [r3, #93] +3470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user Abort complete callback */ +3472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +3473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->AbortCpltCallback(hspi); +3474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else +3475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_AbortCpltCallback(hspi); + 6415 .loc 1 3475 3 + 6416 00ce 7869 ldr r0, [r7, #20] + 6417 00d0 FFF7FEFF bl HAL_SPI_AbortCpltCallback + 6418 00d4 00E0 b .L313 + 6419 .L319: +3449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6420 .loc 1 3449 7 + 6421 00d6 00BF nop + 6422 .L313: +3476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +3477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6423 .loc 1 3477 1 + 6424 00d8 1837 adds r7, r7, #24 + 6425 .cfi_def_cfa_offset 8 + 6426 00da BD46 mov sp, r7 + 6427 .cfi_def_cfa_register 13 + 6428 @ sp needed + 6429 00dc 80BD pop {r7, pc} + 6430 .cfi_endproc + 6431 .LFE167: + ARM GAS /tmp/ccs34gJO.s page 174 + + + 6433 .section .text.SPI_DMARxAbortCallback,"ax",%progbits + 6434 .align 1 + 6435 .syntax unified + 6436 .thumb + 6437 .thumb_func + 6439 SPI_DMARxAbortCallback: + 6440 .LFB168: +3478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief DMA SPI Rx communication abort callback, when initiated by user +3481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * (To be called at end of DMA Rx Abort procedure following user abort request). +3482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @note When this callback is executed, User Abort complete call back is called only if no +3483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * Abort still ongoing for Tx DMA Handle. +3484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hdma DMA handle. +3485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +3486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +3488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6441 .loc 1 3488 1 + 6442 .cfi_startproc + 6443 @ args = 0, pretend = 0, frame = 24 + 6444 @ frame_needed = 1, uses_anonymous_args = 0 + 6445 0000 80B5 push {r7, lr} + 6446 .cfi_def_cfa_offset 8 + 6447 .cfi_offset 7, -8 + 6448 .cfi_offset 14, -4 + 6449 0002 88B0 sub sp, sp, #32 + 6450 .cfi_def_cfa_offset 40 + 6451 0004 02AF add r7, sp, #8 + 6452 .cfi_def_cfa 7, 32 + 6453 0006 7860 str r0, [r7, #4] +3489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogati + 6454 .loc 1 3489 22 + 6455 0008 7B68 ldr r3, [r7, #4] + 6456 000a 5B6A ldr r3, [r3, #36] + 6457 000c 7B61 str r3, [r7, #20] +3490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable SPI Peripheral */ +3492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE(hspi); + 6458 .loc 1 3492 3 + 6459 000e 7B69 ldr r3, [r7, #20] + 6460 0010 1B68 ldr r3, [r3] + 6461 0012 1A68 ldr r2, [r3] + 6462 0014 7B69 ldr r3, [r7, #20] + 6463 0016 1B68 ldr r3, [r3] + 6464 0018 22F04002 bic r2, r2, #64 + 6465 001c 1A60 str r2, [r3] +3493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->hdmarx->XferAbortCallback = NULL; + 6466 .loc 1 3494 7 + 6467 001e 7B69 ldr r3, [r7, #20] + 6468 0020 9B6D ldr r3, [r3, #88] + 6469 .loc 1 3494 35 + 6470 0022 0022 movs r2, #0 + 6471 0024 5A63 str r2, [r3, #52] +3495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable Rx DMA Request */ + ARM GAS /tmp/ccs34gJO.s page 175 + + +3497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + 6472 .loc 1 3497 3 + 6473 0026 7B69 ldr r3, [r7, #20] + 6474 0028 1B68 ldr r3, [r3] + 6475 002a 5A68 ldr r2, [r3, #4] + 6476 002c 7B69 ldr r3, [r7, #20] + 6477 002e 1B68 ldr r3, [r3] + 6478 0030 22F00102 bic r2, r2, #1 + 6479 0034 5A60 str r2, [r3, #4] +3498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Control the BSY flag */ +3500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) + 6480 .loc 1 3500 7 + 6481 0036 FFF7FEFF bl HAL_GetTick + 6482 003a 0346 mov r3, r0 + 6483 .loc 1 3500 7 is_stmt 0 discriminator 1 + 6484 003c 0093 str r3, [sp] + 6485 003e 6423 movs r3, #100 + 6486 0040 0022 movs r2, #0 + 6487 0042 8021 movs r1, #128 + 6488 0044 7869 ldr r0, [r7, #20] + 6489 0046 FFF7FEFF bl SPI_WaitFlagStateUntilTimeout + 6490 004a 0346 mov r3, r0 + 6491 .loc 1 3500 6 is_stmt 1 discriminator 2 + 6492 004c 002B cmp r3, #0 + 6493 004e 02D0 beq .L321 +3501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + 6494 .loc 1 3502 21 + 6495 0050 7B69 ldr r3, [r7, #20] + 6496 0052 4022 movs r2, #64 + 6497 0054 1A66 str r2, [r3, #96] + 6498 .L321: +3503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Empty the FRLVL fifo */ +3506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL + 6499 .loc 1 3506 7 + 6500 0056 FFF7FEFF bl HAL_GetTick + 6501 005a 0346 mov r3, r0 + 6502 .loc 1 3506 7 is_stmt 0 discriminator 1 + 6503 005c 0093 str r3, [sp] + 6504 005e 6423 movs r3, #100 + 6505 0060 0022 movs r2, #0 + 6506 0062 4FF4C061 mov r1, #1536 + 6507 0066 7869 ldr r0, [r7, #20] + 6508 0068 FFF7FEFF bl SPI_WaitFifoStateUntilTimeout + 6509 006c 0346 mov r3, r0 + 6510 .loc 1 3506 6 is_stmt 1 discriminator 2 + 6511 006e 002B cmp r3, #0 + 6512 0070 02D0 beq .L322 +3507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + 6513 .loc 1 3508 21 + 6514 0072 7B69 ldr r3, [r7, #20] + 6515 0074 4022 movs r2, #64 + 6516 0076 1A66 str r2, [r3, #96] + ARM GAS /tmp/ccs34gJO.s page 176 + + + 6517 .L322: +3509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check if an Abort process is still ongoing */ +3512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->hdmatx != NULL) + 6518 .loc 1 3512 11 + 6519 0078 7B69 ldr r3, [r7, #20] + 6520 007a 5B6D ldr r3, [r3, #84] + 6521 .loc 1 3512 6 + 6522 007c 002B cmp r3, #0 + 6523 007e 04D0 beq .L323 +3513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->hdmatx->XferAbortCallback != NULL) + 6524 .loc 1 3514 13 + 6525 0080 7B69 ldr r3, [r7, #20] + 6526 0082 5B6D ldr r3, [r3, #84] + 6527 .loc 1 3514 21 + 6528 0084 5B6B ldr r3, [r3, #52] + 6529 .loc 1 3514 8 + 6530 0086 002B cmp r3, #0 + 6531 0088 27D1 bne .L326 + 6532 .L323: +3515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return; +3517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete +3521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount = 0U; + 6533 .loc 1 3521 21 + 6534 008a 7B69 ldr r3, [r7, #20] + 6535 008c 0022 movs r2, #0 + 6536 008e A3F84620 strh r2, [r3, #70] @ movhi +3522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount = 0U; + 6537 .loc 1 3522 21 + 6538 0092 7B69 ldr r3, [r7, #20] + 6539 0094 0022 movs r2, #0 + 6540 0096 DA87 strh r2, [r3, #62] @ movhi +3523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check no error during Abort procedure */ +3525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT) + 6541 .loc 1 3525 11 + 6542 0098 7B69 ldr r3, [r7, #20] + 6543 009a 1B6E ldr r3, [r3, #96] + 6544 .loc 1 3525 6 + 6545 009c 402B cmp r3, #64 + 6546 009e 02D0 beq .L325 +3526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset errorCode */ +3528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_NONE; + 6547 .loc 1 3528 21 + 6548 00a0 7B69 ldr r3, [r7, #20] + 6549 00a2 0022 movs r2, #0 + 6550 00a4 1A66 str r2, [r3, #96] + 6551 .L325: + 6552 .LBB14: +3529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + ARM GAS /tmp/ccs34gJO.s page 177 + + +3530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Clear the Error flags in the SR register */ +3532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_OVRFLAG(hspi); + 6553 .loc 1 3532 3 + 6554 00a6 0023 movs r3, #0 + 6555 00a8 3B61 str r3, [r7, #16] + 6556 00aa 7B69 ldr r3, [r7, #20] + 6557 00ac 1B68 ldr r3, [r3] + 6558 00ae DB68 ldr r3, [r3, #12] + 6559 00b0 3B61 str r3, [r7, #16] + 6560 00b2 7B69 ldr r3, [r7, #20] + 6561 00b4 1B68 ldr r3, [r3] + 6562 00b6 9B68 ldr r3, [r3, #8] + 6563 00b8 3B61 str r3, [r7, #16] + 6564 00ba 3B69 ldr r3, [r7, #16] + 6565 .LBE14: + 6566 .LBB15: +3533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_FREFLAG(hspi); + 6567 .loc 1 3533 3 + 6568 00bc 0023 movs r3, #0 + 6569 00be FB60 str r3, [r7, #12] + 6570 00c0 7B69 ldr r3, [r7, #20] + 6571 00c2 1B68 ldr r3, [r3] + 6572 00c4 9B68 ldr r3, [r3, #8] + 6573 00c6 FB60 str r3, [r7, #12] + 6574 00c8 FB68 ldr r3, [r7, #12] + 6575 .LBE15: +3534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Restore hspi->State to Ready */ +3536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; + 6576 .loc 1 3536 16 + 6577 00ca 7B69 ldr r3, [r7, #20] + 6578 00cc 0122 movs r2, #1 + 6579 00ce 83F85D20 strb r2, [r3, #93] +3537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user Abort complete callback */ +3539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +3540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->AbortCpltCallback(hspi); +3541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else +3542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_AbortCpltCallback(hspi); + 6580 .loc 1 3542 3 + 6581 00d2 7869 ldr r0, [r7, #20] + 6582 00d4 FFF7FEFF bl HAL_SPI_AbortCpltCallback + 6583 00d8 00E0 b .L320 + 6584 .L326: +3516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6585 .loc 1 3516 7 + 6586 00da 00BF nop + 6587 .L320: +3543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +3544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6588 .loc 1 3544 1 + 6589 00dc 1837 adds r7, r7, #24 + 6590 .cfi_def_cfa_offset 8 + 6591 00de BD46 mov sp, r7 + 6592 .cfi_def_cfa_register 13 + 6593 @ sp needed + ARM GAS /tmp/ccs34gJO.s page 178 + + + 6594 00e0 80BD pop {r7, pc} + 6595 .cfi_endproc + 6596 .LFE168: + 6598 .section .text.SPI_2linesRxISR_8BIT,"ax",%progbits + 6599 .align 1 + 6600 .syntax unified + 6601 .thumb + 6602 .thumb_func + 6604 SPI_2linesRxISR_8BIT: + 6605 .LFB169: +3545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. +3548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +3549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +3550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +3551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) +3553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6606 .loc 1 3553 1 + 6607 .cfi_startproc + 6608 @ args = 0, pretend = 0, frame = 8 + 6609 @ frame_needed = 1, uses_anonymous_args = 0 + 6610 0000 80B5 push {r7, lr} + 6611 .cfi_def_cfa_offset 8 + 6612 .cfi_offset 7, -8 + 6613 .cfi_offset 14, -4 + 6614 0002 82B0 sub sp, sp, #8 + 6615 .cfi_def_cfa_offset 16 + 6616 0004 00AF add r7, sp, #0 + 6617 .cfi_def_cfa_register 7 + 6618 0006 7860 str r0, [r7, #4] +3554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Receive data in packing mode */ +3555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->RxXferCount > 1U) + 6619 .loc 1 3555 11 + 6620 0008 7B68 ldr r3, [r7, #4] + 6621 000a B3F84630 ldrh r3, [r3, #70] @ movhi + 6622 000e 9BB2 uxth r3, r3 + 6623 .loc 1 3555 6 + 6624 0010 012B cmp r3, #1 + 6625 0012 23D9 bls .L328 +3556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR); + 6626 .loc 1 3557 54 + 6627 0014 7B68 ldr r3, [r7, #4] + 6628 0016 1B68 ldr r3, [r3] + 6629 .loc 1 3557 64 + 6630 0018 DA68 ldr r2, [r3, #12] + 6631 .loc 1 3557 23 + 6632 001a 7B68 ldr r3, [r7, #4] + 6633 001c 1B6C ldr r3, [r3, #64] + 6634 .loc 1 3557 39 + 6635 001e 92B2 uxth r2, r2 + 6636 .loc 1 3557 37 + 6637 0020 1A80 strh r2, [r3] @ movhi +3558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr += sizeof(uint16_t); + 6638 .loc 1 3558 9 + ARM GAS /tmp/ccs34gJO.s page 179 + + + 6639 0022 7B68 ldr r3, [r7, #4] + 6640 0024 1B6C ldr r3, [r3, #64] + 6641 .loc 1 3558 22 + 6642 0026 9A1C adds r2, r3, #2 + 6643 0028 7B68 ldr r3, [r7, #4] + 6644 002a 1A64 str r2, [r3, #64] +3559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount -= 2U; + 6645 .loc 1 3559 9 + 6646 002c 7B68 ldr r3, [r7, #4] + 6647 002e B3F84630 ldrh r3, [r3, #70] @ movhi + 6648 0032 9BB2 uxth r3, r3 + 6649 .loc 1 3559 23 + 6650 0034 023B subs r3, r3, #2 + 6651 0036 9AB2 uxth r2, r3 + 6652 0038 7B68 ldr r3, [r7, #4] + 6653 003a A3F84620 strh r2, [r3, #70] @ movhi +3560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->RxXferCount == 1U) + 6654 .loc 1 3560 13 + 6655 003e 7B68 ldr r3, [r7, #4] + 6656 0040 B3F84630 ldrh r3, [r3, #70] @ movhi + 6657 0044 9BB2 uxth r3, r3 + 6658 .loc 1 3560 8 + 6659 0046 012B cmp r3, #1 + 6660 0048 1FD1 bne .L329 +3561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set RX Fifo threshold according the reception data length: 8bit */ +3563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + 6661 .loc 1 3563 7 + 6662 004a 7B68 ldr r3, [r7, #4] + 6663 004c 1B68 ldr r3, [r3] + 6664 004e 5A68 ldr r2, [r3, #4] + 6665 0050 7B68 ldr r3, [r7, #4] + 6666 0052 1B68 ldr r3, [r3] + 6667 0054 42F48052 orr r2, r2, #4096 + 6668 0058 5A60 str r2, [r3, #4] + 6669 005a 16E0 b .L329 + 6670 .L328: +3564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Receive data in 8 Bit mode */ +3567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +3568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR); + 6671 .loc 1 3569 48 + 6672 005c 7B68 ldr r3, [r7, #4] + 6673 005e 1B68 ldr r3, [r3] + 6674 .loc 1 3569 43 + 6675 0060 03F10C02 add r2, r3, #12 + 6676 .loc 1 3569 10 + 6677 0064 7B68 ldr r3, [r7, #4] + 6678 0066 1B6C ldr r3, [r3, #64] + 6679 .loc 1 3569 25 + 6680 0068 1278 ldrb r2, [r2] + 6681 006a D2B2 uxtb r2, r2 + 6682 .loc 1 3569 23 + 6683 006c 1A70 strb r2, [r3] +3570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr++; + ARM GAS /tmp/ccs34gJO.s page 180 + + + 6684 .loc 1 3570 9 + 6685 006e 7B68 ldr r3, [r7, #4] + 6686 0070 1B6C ldr r3, [r3, #64] + 6687 .loc 1 3570 21 + 6688 0072 5A1C adds r2, r3, #1 + 6689 0074 7B68 ldr r3, [r7, #4] + 6690 0076 1A64 str r2, [r3, #64] +3571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount--; + 6691 .loc 1 3571 9 + 6692 0078 7B68 ldr r3, [r7, #4] + 6693 007a B3F84630 ldrh r3, [r3, #70] @ movhi + 6694 007e 9BB2 uxth r3, r3 + 6695 .loc 1 3571 22 + 6696 0080 013B subs r3, r3, #1 + 6697 0082 9AB2 uxth r2, r3 + 6698 0084 7B68 ldr r3, [r7, #4] + 6699 0086 A3F84620 strh r2, [r3, #70] @ movhi + 6700 .L329: +3572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check end of the reception */ +3575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->RxXferCount == 0U) + 6701 .loc 1 3575 11 + 6702 008a 7B68 ldr r3, [r7, #4] + 6703 008c B3F84630 ldrh r3, [r3, #70] @ movhi + 6704 0090 9BB2 uxth r3, r3 + 6705 .loc 1 3575 6 + 6706 0092 002B cmp r3, #0 + 6707 0094 0FD1 bne .L331 +3576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +3578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +3579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); +3581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxISR = SPI_2linesRxISR_8BITCRC; +3582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return; +3583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +3585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable RXNE and ERR interrupt */ +3587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + 6708 .loc 1 3587 5 + 6709 0096 7B68 ldr r3, [r7, #4] + 6710 0098 1B68 ldr r3, [r3] + 6711 009a 5A68 ldr r2, [r3, #4] + 6712 009c 7B68 ldr r3, [r7, #4] + 6713 009e 1B68 ldr r3, [r3] + 6714 00a0 22F06002 bic r2, r2, #96 + 6715 00a4 5A60 str r2, [r3, #4] +3588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->TxXferCount == 0U) + 6716 .loc 1 3589 13 + 6717 00a6 7B68 ldr r3, [r7, #4] + 6718 00a8 DB8F ldrh r3, [r3, #62] @ movhi + 6719 00aa 9BB2 uxth r3, r3 + 6720 .loc 1 3589 8 + 6721 00ac 002B cmp r3, #0 + ARM GAS /tmp/ccs34gJO.s page 181 + + + 6722 00ae 02D1 bne .L331 +3590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_CloseRxTx_ISR(hspi); + 6723 .loc 1 3591 7 + 6724 00b0 7868 ldr r0, [r7, #4] + 6725 00b2 FFF7FEFF bl SPI_CloseRxTx_ISR + 6726 .L331: +3592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6727 .loc 1 3594 1 + 6728 00b6 00BF nop + 6729 00b8 0837 adds r7, r7, #8 + 6730 .cfi_def_cfa_offset 8 + 6731 00ba BD46 mov sp, r7 + 6732 .cfi_def_cfa_register 13 + 6733 @ sp needed + 6734 00bc 80BD pop {r7, pc} + 6735 .cfi_endproc + 6736 .LFE169: + 6738 .section .text.SPI_2linesTxISR_8BIT,"ax",%progbits + 6739 .align 1 + 6740 .syntax unified + 6741 .thumb + 6742 .thumb_func + 6744 SPI_2linesTxISR_8BIT: + 6745 .LFB170: +3595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +3597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. +3599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +3600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +3601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +3602:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) +3604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint8_t *ptmpreg8; +3606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint8_t tmpreg8 = 0; +3607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Initialize the 8bit temporary pointer */ +3609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; +3610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Read 8bit CRC to flush Data Register */ +3611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmpreg8 = *ptmpreg8; +3612:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* To avoid GCC warning */ +3613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(tmpreg8); +3614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->CRCSize--; +3616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check end of the reception */ +3618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->CRCSize == 0U) +3619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable RXNE and ERR interrupt */ +3621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); +3622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->TxXferCount == 0U) +3624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + ARM GAS /tmp/ccs34gJO.s page 182 + + +3625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_CloseRxTx_ISR(hspi); +3626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +3630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode. +3633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +3634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +3635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +3636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) +3638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6746 .loc 1 3638 1 + 6747 .cfi_startproc + 6748 @ args = 0, pretend = 0, frame = 8 + 6749 @ frame_needed = 1, uses_anonymous_args = 0 + 6750 0000 80B5 push {r7, lr} + 6751 .cfi_def_cfa_offset 8 + 6752 .cfi_offset 7, -8 + 6753 .cfi_offset 14, -4 + 6754 0002 82B0 sub sp, sp, #8 + 6755 .cfi_def_cfa_offset 16 + 6756 0004 00AF add r7, sp, #0 + 6757 .cfi_def_cfa_register 7 + 6758 0006 7860 str r0, [r7, #4] +3639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Transmit data in packing Bit mode */ +3640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->TxXferCount >= 2U) + 6759 .loc 1 3640 11 + 6760 0008 7B68 ldr r3, [r7, #4] + 6761 000a DB8F ldrh r3, [r3, #62] @ movhi + 6762 000c 9BB2 uxth r3, r3 + 6763 .loc 1 3640 6 + 6764 000e 012B cmp r3, #1 + 6765 0010 12D9 bls .L333 +3641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3642:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + 6766 .loc 1 3642 44 + 6767 0012 7B68 ldr r3, [r7, #4] + 6768 0014 9B6B ldr r3, [r3, #56] + 6769 .loc 1 3642 26 + 6770 0016 1A88 ldrh r2, [r3] + 6771 .loc 1 3642 9 + 6772 0018 7B68 ldr r3, [r7, #4] + 6773 001a 1B68 ldr r3, [r3] + 6774 .loc 1 3642 24 + 6775 001c DA60 str r2, [r3, #12] +3643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 6776 .loc 1 3643 9 + 6777 001e 7B68 ldr r3, [r7, #4] + 6778 0020 9B6B ldr r3, [r3, #56] + 6779 .loc 1 3643 22 + 6780 0022 9A1C adds r2, r3, #2 + 6781 0024 7B68 ldr r3, [r7, #4] + 6782 0026 9A63 str r2, [r3, #56] +3644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount -= 2U; + ARM GAS /tmp/ccs34gJO.s page 183 + + + 6783 .loc 1 3644 9 + 6784 0028 7B68 ldr r3, [r7, #4] + 6785 002a DB8F ldrh r3, [r3, #62] @ movhi + 6786 002c 9BB2 uxth r3, r3 + 6787 .loc 1 3644 23 + 6788 002e 023B subs r3, r3, #2 + 6789 0030 9AB2 uxth r2, r3 + 6790 0032 7B68 ldr r3, [r7, #4] + 6791 0034 DA87 strh r2, [r3, #62] @ movhi + 6792 0036 12E0 b .L334 + 6793 .L333: +3645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Transmit data in 8 Bit mode */ +3647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +3648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + 6794 .loc 1 3649 50 + 6795 0038 7B68 ldr r3, [r7, #4] + 6796 003a 9A6B ldr r2, [r3, #56] + 6797 .loc 1 3649 27 + 6798 003c 7B68 ldr r3, [r7, #4] + 6799 003e 1B68 ldr r3, [r3] + 6800 .loc 1 3649 22 + 6801 0040 0C33 adds r3, r3, #12 + 6802 .loc 1 3649 45 + 6803 0042 1278 ldrb r2, [r2] @ zero_extendqisi2 + 6804 .loc 1 3649 42 + 6805 0044 1A70 strb r2, [r3] +3650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr++; + 6806 .loc 1 3650 9 + 6807 0046 7B68 ldr r3, [r7, #4] + 6808 0048 9B6B ldr r3, [r3, #56] + 6809 .loc 1 3650 21 + 6810 004a 5A1C adds r2, r3, #1 + 6811 004c 7B68 ldr r3, [r7, #4] + 6812 004e 9A63 str r2, [r3, #56] +3651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 6813 .loc 1 3651 9 + 6814 0050 7B68 ldr r3, [r7, #4] + 6815 0052 DB8F ldrh r3, [r3, #62] @ movhi + 6816 0054 9BB2 uxth r3, r3 + 6817 .loc 1 3651 22 + 6818 0056 013B subs r3, r3, #1 + 6819 0058 9AB2 uxth r2, r3 + 6820 005a 7B68 ldr r3, [r7, #4] + 6821 005c DA87 strh r2, [r3, #62] @ movhi + 6822 .L334: +3652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check the end of the transmission */ +3655:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->TxXferCount == 0U) + 6823 .loc 1 3655 11 + 6824 005e 7B68 ldr r3, [r7, #4] + 6825 0060 DB8F ldrh r3, [r3, #62] @ movhi + 6826 0062 9BB2 uxth r3, r3 + 6827 .loc 1 3655 6 + 6828 0064 002B cmp r3, #0 + ARM GAS /tmp/ccs34gJO.s page 184 + + + 6829 0066 10D1 bne .L336 +3656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3657:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +3658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +3659:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set CRC Next Bit to send CRC */ +3661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); +3662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable TXE interrupt */ +3663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); +3664:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return; +3665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +3667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3668:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable TXE interrupt */ +3669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); + 6830 .loc 1 3669 5 + 6831 0068 7B68 ldr r3, [r7, #4] + 6832 006a 1B68 ldr r3, [r3] + 6833 006c 5A68 ldr r2, [r3, #4] + 6834 006e 7B68 ldr r3, [r7, #4] + 6835 0070 1B68 ldr r3, [r3] + 6836 0072 22F08002 bic r2, r2, #128 + 6837 0076 5A60 str r2, [r3, #4] +3670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->RxXferCount == 0U) + 6838 .loc 1 3671 13 + 6839 0078 7B68 ldr r3, [r7, #4] + 6840 007a B3F84630 ldrh r3, [r3, #70] @ movhi + 6841 007e 9BB2 uxth r3, r3 + 6842 .loc 1 3671 8 + 6843 0080 002B cmp r3, #0 + 6844 0082 02D1 bne .L336 +3672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_CloseRxTx_ISR(hspi); + 6845 .loc 1 3673 7 + 6846 0084 7868 ldr r0, [r7, #4] + 6847 0086 FFF7FEFF bl SPI_CloseRxTx_ISR + 6848 .L336: +3674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6849 .loc 1 3676 1 + 6850 008a 00BF nop + 6851 008c 0837 adds r7, r7, #8 + 6852 .cfi_def_cfa_offset 8 + 6853 008e BD46 mov sp, r7 + 6854 .cfi_def_cfa_register 13 + 6855 @ sp needed + 6856 0090 80BD pop {r7, pc} + 6857 .cfi_endproc + 6858 .LFE170: + 6860 .section .text.SPI_2linesRxISR_16BIT,"ax",%progbits + 6861 .align 1 + 6862 .syntax unified + 6863 .thumb + 6864 .thumb_func + 6866 SPI_2linesRxISR_16BIT: + ARM GAS /tmp/ccs34gJO.s page 185 + + + 6867 .LFB171: +3677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode. +3680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +3681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +3682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +3683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) +3685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6868 .loc 1 3685 1 + 6869 .cfi_startproc + 6870 @ args = 0, pretend = 0, frame = 8 + 6871 @ frame_needed = 1, uses_anonymous_args = 0 + 6872 0000 80B5 push {r7, lr} + 6873 .cfi_def_cfa_offset 8 + 6874 .cfi_offset 7, -8 + 6875 .cfi_offset 14, -4 + 6876 0002 82B0 sub sp, sp, #8 + 6877 .cfi_def_cfa_offset 16 + 6878 0004 00AF add r7, sp, #0 + 6879 .cfi_def_cfa_register 7 + 6880 0006 7860 str r0, [r7, #4] +3686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Receive data in 16 Bit mode */ +3687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR); + 6881 .loc 1 3687 52 + 6882 0008 7B68 ldr r3, [r7, #4] + 6883 000a 1B68 ldr r3, [r3] + 6884 .loc 1 3687 62 + 6885 000c DA68 ldr r2, [r3, #12] + 6886 .loc 1 3687 21 + 6887 000e 7B68 ldr r3, [r7, #4] + 6888 0010 1B6C ldr r3, [r3, #64] + 6889 .loc 1 3687 37 + 6890 0012 92B2 uxth r2, r2 + 6891 .loc 1 3687 35 + 6892 0014 1A80 strh r2, [r3] @ movhi +3688:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr += sizeof(uint16_t); + 6893 .loc 1 3688 7 + 6894 0016 7B68 ldr r3, [r7, #4] + 6895 0018 1B6C ldr r3, [r3, #64] + 6896 .loc 1 3688 20 + 6897 001a 9A1C adds r2, r3, #2 + 6898 001c 7B68 ldr r3, [r7, #4] + 6899 001e 1A64 str r2, [r3, #64] +3689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount--; + 6900 .loc 1 3689 7 + 6901 0020 7B68 ldr r3, [r7, #4] + 6902 0022 B3F84630 ldrh r3, [r3, #70] @ movhi + 6903 0026 9BB2 uxth r3, r3 + 6904 .loc 1 3689 20 + 6905 0028 013B subs r3, r3, #1 + 6906 002a 9AB2 uxth r2, r3 + 6907 002c 7B68 ldr r3, [r7, #4] + 6908 002e A3F84620 strh r2, [r3, #70] @ movhi +3690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->RxXferCount == 0U) + ARM GAS /tmp/ccs34gJO.s page 186 + + + 6909 .loc 1 3691 11 + 6910 0032 7B68 ldr r3, [r7, #4] + 6911 0034 B3F84630 ldrh r3, [r3, #70] @ movhi + 6912 0038 9BB2 uxth r3, r3 + 6913 .loc 1 3691 6 + 6914 003a 002B cmp r3, #0 + 6915 003c 0FD1 bne .L339 +3692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +3694:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +3695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxISR = SPI_2linesRxISR_16BITCRC; +3697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return; +3698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +3700:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable RXNE interrupt */ +3702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); + 6916 .loc 1 3702 5 + 6917 003e 7B68 ldr r3, [r7, #4] + 6918 0040 1B68 ldr r3, [r3] + 6919 0042 5A68 ldr r2, [r3, #4] + 6920 0044 7B68 ldr r3, [r7, #4] + 6921 0046 1B68 ldr r3, [r3] + 6922 0048 22F04002 bic r2, r2, #64 + 6923 004c 5A60 str r2, [r3, #4] +3703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3704:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->TxXferCount == 0U) + 6924 .loc 1 3704 13 + 6925 004e 7B68 ldr r3, [r7, #4] + 6926 0050 DB8F ldrh r3, [r3, #62] @ movhi + 6927 0052 9BB2 uxth r3, r3 + 6928 .loc 1 3704 8 + 6929 0054 002B cmp r3, #0 + 6930 0056 02D1 bne .L339 +3705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3706:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_CloseRxTx_ISR(hspi); + 6931 .loc 1 3706 7 + 6932 0058 7868 ldr r0, [r7, #4] + 6933 005a FFF7FEFF bl SPI_CloseRxTx_ISR + 6934 .L339: +3707:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3708:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 6935 .loc 1 3709 1 + 6936 005e 00BF nop + 6937 0060 0837 adds r7, r7, #8 + 6938 .cfi_def_cfa_offset 8 + 6939 0062 BD46 mov sp, r7 + 6940 .cfi_def_cfa_register 13 + 6941 @ sp needed + 6942 0064 80BD pop {r7, pc} + 6943 .cfi_endproc + 6944 .LFE171: + 6946 .section .text.SPI_2linesTxISR_16BIT,"ax",%progbits + 6947 .align 1 + 6948 .syntax unified + ARM GAS /tmp/ccs34gJO.s page 187 + + + 6949 .thumb + 6950 .thumb_func + 6952 SPI_2linesTxISR_16BIT: + 6953 .LFB172: +3710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +3712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3713:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode. +3714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +3715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +3716:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +3717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3718:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) +3719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3720:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint32_t tmpreg = 0U; +3721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3722:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Read 16bit CRC to flush Data Register */ +3723:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmpreg = READ_REG(hspi->Instance->DR); +3724:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* To avoid GCC warning */ +3725:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(tmpreg); +3726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3727:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable RXNE interrupt */ +3728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); +3729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_CloseRxTx_ISR(hspi); +3731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +3733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3734:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode. +3736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +3737:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +3738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +3739:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) +3741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 6954 .loc 1 3741 1 + 6955 .cfi_startproc + 6956 @ args = 0, pretend = 0, frame = 8 + 6957 @ frame_needed = 1, uses_anonymous_args = 0 + 6958 0000 80B5 push {r7, lr} + 6959 .cfi_def_cfa_offset 8 + 6960 .cfi_offset 7, -8 + 6961 .cfi_offset 14, -4 + 6962 0002 82B0 sub sp, sp, #8 + 6963 .cfi_def_cfa_offset 16 + 6964 0004 00AF add r7, sp, #0 + 6965 .cfi_def_cfa_register 7 + 6966 0006 7860 str r0, [r7, #4] +3742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Transmit data in 16 Bit mode */ +3743:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + 6967 .loc 1 3743 42 + 6968 0008 7B68 ldr r3, [r7, #4] + 6969 000a 9B6B ldr r3, [r3, #56] + 6970 .loc 1 3743 24 + 6971 000c 1A88 ldrh r2, [r3] + 6972 .loc 1 3743 7 + ARM GAS /tmp/ccs34gJO.s page 188 + + + 6973 000e 7B68 ldr r3, [r7, #4] + 6974 0010 1B68 ldr r3, [r3] + 6975 .loc 1 3743 22 + 6976 0012 DA60 str r2, [r3, #12] +3744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 6977 .loc 1 3744 7 + 6978 0014 7B68 ldr r3, [r7, #4] + 6979 0016 9B6B ldr r3, [r3, #56] + 6980 .loc 1 3744 20 + 6981 0018 9A1C adds r2, r3, #2 + 6982 001a 7B68 ldr r3, [r7, #4] + 6983 001c 9A63 str r2, [r3, #56] +3745:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 6984 .loc 1 3745 7 + 6985 001e 7B68 ldr r3, [r7, #4] + 6986 0020 DB8F ldrh r3, [r3, #62] @ movhi + 6987 0022 9BB2 uxth r3, r3 + 6988 .loc 1 3745 20 + 6989 0024 013B subs r3, r3, #1 + 6990 0026 9AB2 uxth r2, r3 + 6991 0028 7B68 ldr r3, [r7, #4] + 6992 002a DA87 strh r2, [r3, #62] @ movhi +3746:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3747:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable CRC Transmission */ +3748:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->TxXferCount == 0U) + 6993 .loc 1 3748 11 + 6994 002c 7B68 ldr r3, [r7, #4] + 6995 002e DB8F ldrh r3, [r3, #62] @ movhi + 6996 0030 9BB2 uxth r3, r3 + 6997 .loc 1 3748 6 + 6998 0032 002B cmp r3, #0 + 6999 0034 10D1 bne .L342 +3749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +3751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +3752:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Set CRC Next Bit to send CRC */ +3754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); +3755:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable TXE interrupt */ +3756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); +3757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return; +3758:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +3760:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3761:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable TXE interrupt */ +3762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); + 7000 .loc 1 3762 5 + 7001 0036 7B68 ldr r3, [r7, #4] + 7002 0038 1B68 ldr r3, [r3] + 7003 003a 5A68 ldr r2, [r3, #4] + 7004 003c 7B68 ldr r3, [r7, #4] + 7005 003e 1B68 ldr r3, [r3] + 7006 0040 22F08002 bic r2, r2, #128 + 7007 0044 5A60 str r2, [r3, #4] +3763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3764:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->RxXferCount == 0U) + 7008 .loc 1 3764 13 + ARM GAS /tmp/ccs34gJO.s page 189 + + + 7009 0046 7B68 ldr r3, [r7, #4] + 7010 0048 B3F84630 ldrh r3, [r3, #70] @ movhi + 7011 004c 9BB2 uxth r3, r3 + 7012 .loc 1 3764 8 + 7013 004e 002B cmp r3, #0 + 7014 0050 02D1 bne .L342 +3765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_CloseRxTx_ISR(hspi); + 7015 .loc 1 3766 7 + 7016 0052 7868 ldr r0, [r7, #4] + 7017 0054 FFF7FEFF bl SPI_CloseRxTx_ISR + 7018 .L342: +3767:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 7019 .loc 1 3769 1 + 7020 0058 00BF nop + 7021 005a 0837 adds r7, r7, #8 + 7022 .cfi_def_cfa_offset 8 + 7023 005c BD46 mov sp, r7 + 7024 .cfi_def_cfa_register 13 + 7025 @ sp needed + 7026 005e 80BD pop {r7, pc} + 7027 .cfi_endproc + 7028 .LFE172: + 7030 .section .text.SPI_RxISR_8BIT,"ax",%progbits + 7031 .align 1 + 7032 .syntax unified + 7033 .thumb + 7034 .thumb_func + 7036 SPI_RxISR_8BIT: + 7037 .LFB173: +3770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +3772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Manage the CRC 8-bit receive in Interrupt context. +3774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +3775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +3776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +3777:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) +3779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3780:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint8_t *ptmpreg8; +3781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint8_t tmpreg8 = 0; +3782:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Initialize the 8bit temporary pointer */ +3784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; +3785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Read 8bit CRC to flush Data Register */ +3786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmpreg8 = *ptmpreg8; +3787:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* To avoid GCC warning */ +3788:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(tmpreg8); +3789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->CRCSize--; +3791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->CRCSize == 0U) +3793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_CloseRx_ISR(hspi); + ARM GAS /tmp/ccs34gJO.s page 190 + + +3795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +3798:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3799:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Manage the receive 8-bit in Interrupt context. +3801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +3802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +3803:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +3804:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi) +3806:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7038 .loc 1 3806 1 + 7039 .cfi_startproc + 7040 @ args = 0, pretend = 0, frame = 8 + 7041 @ frame_needed = 1, uses_anonymous_args = 0 + 7042 0000 80B5 push {r7, lr} + 7043 .cfi_def_cfa_offset 8 + 7044 .cfi_offset 7, -8 + 7045 .cfi_offset 14, -4 + 7046 0002 82B0 sub sp, sp, #8 + 7047 .cfi_def_cfa_offset 16 + 7048 0004 00AF add r7, sp, #0 + 7049 .cfi_def_cfa_register 7 + 7050 0006 7860 str r0, [r7, #4] +3807:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR); + 7051 .loc 1 3807 46 + 7052 0008 7B68 ldr r3, [r7, #4] + 7053 000a 1B68 ldr r3, [r3] + 7054 .loc 1 3807 41 + 7055 000c 03F10C02 add r2, r3, #12 + 7056 .loc 1 3807 8 + 7057 0010 7B68 ldr r3, [r7, #4] + 7058 0012 1B6C ldr r3, [r3, #64] + 7059 .loc 1 3807 24 + 7060 0014 1278 ldrb r2, [r2] + 7061 0016 D2B2 uxtb r2, r2 + 7062 .loc 1 3807 21 + 7063 0018 1A70 strb r2, [r3] +3808:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr++; + 7064 .loc 1 3808 7 + 7065 001a 7B68 ldr r3, [r7, #4] + 7066 001c 1B6C ldr r3, [r3, #64] + 7067 .loc 1 3808 19 + 7068 001e 5A1C adds r2, r3, #1 + 7069 0020 7B68 ldr r3, [r7, #4] + 7070 0022 1A64 str r2, [r3, #64] +3809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount--; + 7071 .loc 1 3809 7 + 7072 0024 7B68 ldr r3, [r7, #4] + 7073 0026 B3F84630 ldrh r3, [r3, #70] @ movhi + 7074 002a 9BB2 uxth r3, r3 + 7075 .loc 1 3809 20 + 7076 002c 013B subs r3, r3, #1 + 7077 002e 9AB2 uxth r2, r3 + 7078 0030 7B68 ldr r3, [r7, #4] + 7079 0032 A3F84620 strh r2, [r3, #70] @ movhi + ARM GAS /tmp/ccs34gJO.s page 191 + + +3810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3811:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +3812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable CRC Transmission */ +3813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) +3814:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); +3816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3817:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +3818:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->RxXferCount == 0U) + 7080 .loc 1 3819 11 + 7081 0036 7B68 ldr r3, [r7, #4] + 7082 0038 B3F84630 ldrh r3, [r3, #70] @ movhi + 7083 003c 9BB2 uxth r3, r3 + 7084 .loc 1 3819 6 + 7085 003e 002B cmp r3, #0 + 7086 0040 02D1 bne .L345 +3820:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3821:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +3822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +3823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxISR = SPI_RxISR_8BITCRC; +3825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return; +3826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3827:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +3828:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_CloseRx_ISR(hspi); + 7087 .loc 1 3828 5 + 7088 0042 7868 ldr r0, [r7, #4] + 7089 0044 FFF7FEFF bl SPI_CloseRx_ISR + 7090 .L345: +3829:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3830:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 7091 .loc 1 3830 1 + 7092 0048 00BF nop + 7093 004a 0837 adds r7, r7, #8 + 7094 .cfi_def_cfa_offset 8 + 7095 004c BD46 mov sp, r7 + 7096 .cfi_def_cfa_register 13 + 7097 @ sp needed + 7098 004e 80BD pop {r7, pc} + 7099 .cfi_endproc + 7100 .LFE173: + 7102 .section .text.SPI_RxISR_16BIT,"ax",%progbits + 7103 .align 1 + 7104 .syntax unified + 7105 .thumb + 7106 .thumb_func + 7108 SPI_RxISR_16BIT: + 7109 .LFB174: +3831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3832:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +3833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3834:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Manage the CRC 16-bit receive in Interrupt context. +3835:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +3836:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +3837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +3838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ + ARM GAS /tmp/ccs34gJO.s page 192 + + +3839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) +3840:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint32_t tmpreg = 0U; +3842:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3843:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Read 16bit CRC to flush Data Register */ +3844:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmpreg = READ_REG(hspi->Instance->DR); +3845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* To avoid GCC warning */ +3846:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(tmpreg); +3847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable RXNE and ERR interrupt */ +3849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); +3850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3851:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_CloseRx_ISR(hspi); +3852:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3853:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +3854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3855:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3856:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Manage the 16-bit receive in Interrupt context. +3857:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +3858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +3859:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +3860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi) +3862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7110 .loc 1 3862 1 + 7111 .cfi_startproc + 7112 @ args = 0, pretend = 0, frame = 8 + 7113 @ frame_needed = 1, uses_anonymous_args = 0 + 7114 0000 80B5 push {r7, lr} + 7115 .cfi_def_cfa_offset 8 + 7116 .cfi_offset 7, -8 + 7117 .cfi_offset 14, -4 + 7118 0002 82B0 sub sp, sp, #8 + 7119 .cfi_def_cfa_offset 16 + 7120 0004 00AF add r7, sp, #0 + 7121 .cfi_def_cfa_register 7 + 7122 0006 7860 str r0, [r7, #4] +3863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR); + 7123 .loc 1 3863 52 + 7124 0008 7B68 ldr r3, [r7, #4] + 7125 000a 1B68 ldr r3, [r3] + 7126 .loc 1 3863 62 + 7127 000c DA68 ldr r2, [r3, #12] + 7128 .loc 1 3863 21 + 7129 000e 7B68 ldr r3, [r7, #4] + 7130 0010 1B6C ldr r3, [r3, #64] + 7131 .loc 1 3863 37 + 7132 0012 92B2 uxth r2, r2 + 7133 .loc 1 3863 35 + 7134 0014 1A80 strh r2, [r3] @ movhi +3864:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pRxBuffPtr += sizeof(uint16_t); + 7135 .loc 1 3864 7 + 7136 0016 7B68 ldr r3, [r7, #4] + 7137 0018 1B6C ldr r3, [r3, #64] + 7138 .loc 1 3864 20 + 7139 001a 9A1C adds r2, r3, #2 + 7140 001c 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/ccs34gJO.s page 193 + + + 7141 001e 1A64 str r2, [r3, #64] +3865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxXferCount--; + 7142 .loc 1 3865 7 + 7143 0020 7B68 ldr r3, [r7, #4] + 7144 0022 B3F84630 ldrh r3, [r3, #70] @ movhi + 7145 0026 9BB2 uxth r3, r3 + 7146 .loc 1 3865 20 + 7147 0028 013B subs r3, r3, #1 + 7148 002a 9AB2 uxth r2, r3 + 7149 002c 7B68 ldr r3, [r7, #4] + 7150 002e A3F84620 strh r2, [r3, #70] @ movhi +3866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +3868:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable CRC Transmission */ +3869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) +3870:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); +3872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3873:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +3874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3875:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->RxXferCount == 0U) + 7151 .loc 1 3875 11 + 7152 0032 7B68 ldr r3, [r7, #4] + 7153 0034 B3F84630 ldrh r3, [r3, #70] @ movhi + 7154 0038 9BB2 uxth r3, r3 + 7155 .loc 1 3875 6 + 7156 003a 002B cmp r3, #0 + 7157 003c 02D1 bne .L348 +3876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3877:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +3878:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +3879:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxISR = SPI_RxISR_16BITCRC; +3881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return; +3882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +3884:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_CloseRx_ISR(hspi); + 7158 .loc 1 3884 5 + 7159 003e 7868 ldr r0, [r7, #4] + 7160 0040 FFF7FEFF bl SPI_CloseRx_ISR + 7161 .L348: +3885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 7162 .loc 1 3886 1 + 7163 0044 00BF nop + 7164 0046 0837 adds r7, r7, #8 + 7165 .cfi_def_cfa_offset 8 + 7166 0048 BD46 mov sp, r7 + 7167 .cfi_def_cfa_register 13 + 7168 @ sp needed + 7169 004a 80BD pop {r7, pc} + 7170 .cfi_endproc + 7171 .LFE174: + 7173 .section .text.SPI_TxISR_8BIT,"ax",%progbits + 7174 .align 1 + 7175 .syntax unified + 7176 .thumb + ARM GAS /tmp/ccs34gJO.s page 194 + + + 7177 .thumb_func + 7179 SPI_TxISR_8BIT: + 7180 .LFB175: +3887:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3888:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3889:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Handle the data 8-bit transmit in Interrupt mode. +3890:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +3891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +3892:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +3893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3894:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) +3895:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7181 .loc 1 3895 1 + 7182 .cfi_startproc + 7183 @ args = 0, pretend = 0, frame = 8 + 7184 @ frame_needed = 1, uses_anonymous_args = 0 + 7185 0000 80B5 push {r7, lr} + 7186 .cfi_def_cfa_offset 8 + 7187 .cfi_offset 7, -8 + 7188 .cfi_offset 14, -4 + 7189 0002 82B0 sub sp, sp, #8 + 7190 .cfi_def_cfa_offset 16 + 7191 0004 00AF add r7, sp, #0 + 7192 .cfi_def_cfa_register 7 + 7193 0006 7860 str r0, [r7, #4] +3896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + 7194 .loc 1 3896 48 + 7195 0008 7B68 ldr r3, [r7, #4] + 7196 000a 9A6B ldr r2, [r3, #56] + 7197 .loc 1 3896 25 + 7198 000c 7B68 ldr r3, [r7, #4] + 7199 000e 1B68 ldr r3, [r3] + 7200 .loc 1 3896 20 + 7201 0010 0C33 adds r3, r3, #12 + 7202 .loc 1 3896 43 + 7203 0012 1278 ldrb r2, [r2] @ zero_extendqisi2 + 7204 .loc 1 3896 40 + 7205 0014 1A70 strb r2, [r3] +3897:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr++; + 7206 .loc 1 3897 7 + 7207 0016 7B68 ldr r3, [r7, #4] + 7208 0018 9B6B ldr r3, [r3, #56] + 7209 .loc 1 3897 19 + 7210 001a 5A1C adds r2, r3, #1 + 7211 001c 7B68 ldr r3, [r7, #4] + 7212 001e 9A63 str r2, [r3, #56] +3898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 7213 .loc 1 3898 7 + 7214 0020 7B68 ldr r3, [r7, #4] + 7215 0022 DB8F ldrh r3, [r3, #62] @ movhi + 7216 0024 9BB2 uxth r3, r3 + 7217 .loc 1 3898 20 + 7218 0026 013B subs r3, r3, #1 + 7219 0028 9AB2 uxth r2, r3 + 7220 002a 7B68 ldr r3, [r7, #4] + 7221 002c DA87 strh r2, [r3, #62] @ movhi +3899:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** + ARM GAS /tmp/ccs34gJO.s page 195 + + +3900:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->TxXferCount == 0U) + 7222 .loc 1 3900 11 + 7223 002e 7B68 ldr r3, [r7, #4] + 7224 0030 DB8F ldrh r3, [r3, #62] @ movhi + 7225 0032 9BB2 uxth r3, r3 + 7226 .loc 1 3900 6 + 7227 0034 002B cmp r3, #0 + 7228 0036 02D1 bne .L351 +3901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3902:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +3903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +3904:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3905:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable CRC Transmission */ +3906:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); +3907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3908:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +3909:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_CloseTx_ISR(hspi); + 7229 .loc 1 3909 5 + 7230 0038 7868 ldr r0, [r7, #4] + 7231 003a FFF7FEFF bl SPI_CloseTx_ISR + 7232 .L351: +3910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3911:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 7233 .loc 1 3911 1 + 7234 003e 00BF nop + 7235 0040 0837 adds r7, r7, #8 + 7236 .cfi_def_cfa_offset 8 + 7237 0042 BD46 mov sp, r7 + 7238 .cfi_def_cfa_register 13 + 7239 @ sp needed + 7240 0044 80BD pop {r7, pc} + 7241 .cfi_endproc + 7242 .LFE175: + 7244 .section .text.SPI_TxISR_16BIT,"ax",%progbits + 7245 .align 1 + 7246 .syntax unified + 7247 .thumb + 7248 .thumb_func + 7250 SPI_TxISR_16BIT: + 7251 .LFB176: +3912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3913:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3914:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Handle the data 16-bit transmit in Interrupt mode. +3915:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +3916:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +3917:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +3918:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3919:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) +3920:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7252 .loc 1 3920 1 + 7253 .cfi_startproc + 7254 @ args = 0, pretend = 0, frame = 8 + 7255 @ frame_needed = 1, uses_anonymous_args = 0 + 7256 0000 80B5 push {r7, lr} + 7257 .cfi_def_cfa_offset 8 + 7258 .cfi_offset 7, -8 + 7259 .cfi_offset 14, -4 + ARM GAS /tmp/ccs34gJO.s page 196 + + + 7260 0002 82B0 sub sp, sp, #8 + 7261 .cfi_def_cfa_offset 16 + 7262 0004 00AF add r7, sp, #0 + 7263 .cfi_def_cfa_register 7 + 7264 0006 7860 str r0, [r7, #4] +3921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Transmit data in 16 Bit mode */ +3922:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + 7265 .loc 1 3922 42 + 7266 0008 7B68 ldr r3, [r7, #4] + 7267 000a 9B6B ldr r3, [r3, #56] + 7268 .loc 1 3922 24 + 7269 000c 1A88 ldrh r2, [r3] + 7270 .loc 1 3922 7 + 7271 000e 7B68 ldr r3, [r7, #4] + 7272 0010 1B68 ldr r3, [r3] + 7273 .loc 1 3922 22 + 7274 0012 DA60 str r2, [r3, #12] +3923:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->pTxBuffPtr += sizeof(uint16_t); + 7275 .loc 1 3923 7 + 7276 0014 7B68 ldr r3, [r7, #4] + 7277 0016 9B6B ldr r3, [r3, #56] + 7278 .loc 1 3923 20 + 7279 0018 9A1C adds r2, r3, #2 + 7280 001a 7B68 ldr r3, [r7, #4] + 7281 001c 9A63 str r2, [r3, #56] +3924:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxXferCount--; + 7282 .loc 1 3924 7 + 7283 001e 7B68 ldr r3, [r7, #4] + 7284 0020 DB8F ldrh r3, [r3, #62] @ movhi + 7285 0022 9BB2 uxth r3, r3 + 7286 .loc 1 3924 20 + 7287 0024 013B subs r3, r3, #1 + 7288 0026 9AB2 uxth r2, r3 + 7289 0028 7B68 ldr r3, [r7, #4] + 7290 002a DA87 strh r2, [r3, #62] @ movhi +3925:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3926:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->TxXferCount == 0U) + 7291 .loc 1 3926 11 + 7292 002c 7B68 ldr r3, [r7, #4] + 7293 002e DB8F ldrh r3, [r3, #62] @ movhi + 7294 0030 9BB2 uxth r3, r3 + 7295 .loc 1 3926 6 + 7296 0032 002B cmp r3, #0 + 7297 0034 02D1 bne .L354 +3927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3928:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +3929:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) +3930:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3931:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Enable CRC Transmission */ +3932:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); +3933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3934:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +3935:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_CloseTx_ISR(hspi); + 7298 .loc 1 3935 5 + 7299 0036 7868 ldr r0, [r7, #4] + 7300 0038 FFF7FEFF bl SPI_CloseTx_ISR + 7301 .L354: + ARM GAS /tmp/ccs34gJO.s page 197 + + +3936:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 7302 .loc 1 3937 1 + 7303 003c 00BF nop + 7304 003e 0837 adds r7, r7, #8 + 7305 .cfi_def_cfa_offset 8 + 7306 0040 BD46 mov sp, r7 + 7307 .cfi_def_cfa_register 13 + 7308 @ sp needed + 7309 0042 80BD pop {r7, pc} + 7310 .cfi_endproc + 7311 .LFE176: + 7313 .section .text.SPI_WaitFlagStateUntilTimeout,"ax",%progbits + 7314 .align 1 + 7315 .syntax unified + 7316 .thumb + 7317 .thumb_func + 7319 SPI_WaitFlagStateUntilTimeout: + 7320 .LFB177: +3938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3939:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +3940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Handle SPI Communication Timeout. +3941:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +3942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +3943:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param Flag SPI flag to check +3944:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param State flag state to check +3945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param Timeout Timeout duration +3946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param Tickstart tick start value +3947:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval HAL status +3948:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +3949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, Flag +3950:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t Timeout, uint32_t Tickstart) +3951:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7321 .loc 1 3951 1 + 7322 .cfi_startproc + 7323 @ args = 4, pretend = 0, frame = 32 + 7324 @ frame_needed = 1, uses_anonymous_args = 0 + 7325 0000 80B5 push {r7, lr} + 7326 .cfi_def_cfa_offset 8 + 7327 .cfi_offset 7, -8 + 7328 .cfi_offset 14, -4 + 7329 0002 88B0 sub sp, sp, #32 + 7330 .cfi_def_cfa_offset 40 + 7331 0004 00AF add r7, sp, #0 + 7332 .cfi_def_cfa_register 7 + 7333 0006 F860 str r0, [r7, #12] + 7334 0008 B960 str r1, [r7, #8] + 7335 000a 3B60 str r3, [r7] + 7336 000c 1346 mov r3, r2 + 7337 000e FB71 strb r3, [r7, #7] +3952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint32_t count; +3953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t tmp_timeout; +3954:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t tmp_tickstart; +3955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3956:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Adjust Timeout value in case of end of transfer */ +3957:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); + 7338 .loc 1 3957 30 + ARM GAS /tmp/ccs34gJO.s page 198 + + + 7339 0010 FFF7FEFF bl HAL_GetTick + 7340 0014 0246 mov r2, r0 + 7341 .loc 1 3957 44 discriminator 1 + 7342 0016 BB6A ldr r3, [r7, #40] + 7343 0018 9B1A subs r3, r3, r2 + 7344 .loc 1 3957 17 discriminator 1 + 7345 001a 3A68 ldr r2, [r7] + 7346 001c 1344 add r3, r3, r2 + 7347 001e FB61 str r3, [r7, #28] +3958:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmp_tickstart = HAL_GetTick(); + 7348 .loc 1 3958 19 + 7349 0020 FFF7FEFF bl HAL_GetTick + 7350 0024 B861 str r0, [r7, #24] +3959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3960:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ +3961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U); + 7351 .loc 1 3961 43 + 7352 0026 394B ldr r3, .L366 + 7353 0028 1B68 ldr r3, [r3] + 7354 002a 5B01 lsls r3, r3, #5 + 7355 .loc 1 3961 50 + 7356 002c 1B0D lsrs r3, r3, #20 + 7357 .loc 1 3961 23 + 7358 002e FA69 ldr r2, [r7, #28] + 7359 0030 02FB03F3 mul r3, r2, r3 + 7360 .loc 1 3961 9 + 7361 0034 7B61 str r3, [r7, #20] +3962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3963:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) + 7362 .loc 1 3963 9 + 7363 0036 54E0 b .L357 + 7364 .L365: +3964:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3965:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (Timeout != HAL_MAX_DELAY) + 7365 .loc 1 3965 8 + 7366 0038 3B68 ldr r3, [r7] + 7367 003a B3F1FF3F cmp r3, #-1 + 7368 003e 50D0 beq .L357 +3966:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3967:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U)) + 7369 .loc 1 3967 13 + 7370 0040 FFF7FEFF bl HAL_GetTick + 7371 0044 0246 mov r2, r0 + 7372 .loc 1 3967 27 discriminator 1 + 7373 0046 BB69 ldr r3, [r7, #24] + 7374 0048 D31A subs r3, r2, r3 + 7375 .loc 1 3967 10 discriminator 1 + 7376 004a FA69 ldr r2, [r7, #28] + 7377 004c 9A42 cmp r2, r3 + 7378 004e 02D9 bls .L358 + 7379 .loc 1 3967 60 discriminator 1 + 7380 0050 FB69 ldr r3, [r7, #28] + 7381 0052 002B cmp r3, #0 + 7382 0054 3DD1 bne .L359 + 7383 .L358: +3968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3969:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable the SPI and reset the CRC: the CRC value should be cleared + ARM GAS /tmp/ccs34gJO.s page 199 + + +3970:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** on both master and slave sides in order to resynchronize the master +3971:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** and slave for their respective CRC calculation */ +3972:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3973:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ +3974:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + 7384 .loc 1 3974 9 + 7385 0056 FB68 ldr r3, [r7, #12] + 7386 0058 1B68 ldr r3, [r3] + 7387 005a 5A68 ldr r2, [r3, #4] + 7388 005c FB68 ldr r3, [r7, #12] + 7389 005e 1B68 ldr r3, [r3] + 7390 0060 22F0E002 bic r2, r2, #224 + 7391 0064 5A60 str r2, [r3, #4] +3975:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3976:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + 7392 .loc 1 3976 24 + 7393 0066 FB68 ldr r3, [r7, #12] + 7394 0068 5B68 ldr r3, [r3, #4] + 7395 .loc 1 3976 12 + 7396 006a B3F5827F cmp r3, #260 + 7397 006e 11D1 bne .L360 + 7398 .loc 1 3976 65 discriminator 1 + 7399 0070 FB68 ldr r3, [r7, #12] + 7400 0072 9B68 ldr r3, [r3, #8] + 7401 .loc 1 3976 50 discriminator 1 + 7402 0074 B3F5004F cmp r3, #32768 + 7403 0078 04D0 beq .L361 +3977:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** || (hspi->Init.Direction == SPI_DIRECTION_2LIN + 7404 .loc 1 3977 68 + 7405 007a FB68 ldr r3, [r7, #12] + 7406 007c 9B68 ldr r3, [r3, #8] + 7407 .loc 1 3977 54 + 7408 007e B3F5806F cmp r3, #1024 + 7409 0082 07D1 bne .L360 + 7410 .L361: +3978:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3979:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable SPI peripheral */ +3980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE(hspi); + 7411 .loc 1 3980 11 + 7412 0084 FB68 ldr r3, [r7, #12] + 7413 0086 1B68 ldr r3, [r3] + 7414 0088 1A68 ldr r2, [r3] + 7415 008a FB68 ldr r3, [r7, #12] + 7416 008c 1B68 ldr r3, [r3] + 7417 008e 22F04002 bic r2, r2, #64 + 7418 0092 1A60 str r2, [r3] + 7419 .L360: +3981:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3982:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3983:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset CRC Calculation */ +3984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + 7420 .loc 1 3984 23 + 7421 0094 FB68 ldr r3, [r7, #12] + 7422 0096 9B6A ldr r3, [r3, #40] + 7423 .loc 1 3984 12 + 7424 0098 B3F5005F cmp r3, #8192 + 7425 009c 0FD1 bne .L362 + ARM GAS /tmp/ccs34gJO.s page 200 + + +3985:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3986:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_RESET_CRC(hspi); + 7426 .loc 1 3986 11 + 7427 009e FB68 ldr r3, [r7, #12] + 7428 00a0 1B68 ldr r3, [r3] + 7429 00a2 1A68 ldr r2, [r3] + 7430 00a4 FB68 ldr r3, [r7, #12] + 7431 00a6 1B68 ldr r3, [r3] + 7432 00a8 22F40052 bic r2, r2, #8192 + 7433 00ac 1A60 str r2, [r3] + 7434 00ae FB68 ldr r3, [r7, #12] + 7435 00b0 1B68 ldr r3, [r3] + 7436 00b2 1A68 ldr r2, [r3] + 7437 00b4 FB68 ldr r3, [r7, #12] + 7438 00b6 1B68 ldr r3, [r3] + 7439 00b8 42F40052 orr r2, r2, #8192 + 7440 00bc 1A60 str r2, [r3] + 7441 .L362: +3987:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3988:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3989:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; + 7442 .loc 1 3989 21 + 7443 00be FB68 ldr r3, [r7, #12] + 7444 00c0 0122 movs r2, #1 + 7445 00c2 83F85D20 strb r2, [r3, #93] +3990:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3991:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Process Unlocked */ +3992:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_UNLOCK(hspi); + 7446 .loc 1 3992 9 + 7447 00c6 FB68 ldr r3, [r7, #12] + 7448 00c8 0022 movs r2, #0 + 7449 00ca 83F85C20 strb r2, [r3, #92] +3993:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +3994:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return HAL_TIMEOUT; + 7450 .loc 1 3994 16 + 7451 00ce 0323 movs r3, #3 + 7452 00d0 17E0 b .L363 + 7453 .L359: +3995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +3996:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop proced +3997:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (count == 0U) + 7454 .loc 1 3997 17 + 7455 00d2 7B69 ldr r3, [r7, #20] + 7456 .loc 1 3997 10 + 7457 00d4 002B cmp r3, #0 + 7458 00d6 01D1 bne .L364 +3998:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +3999:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmp_timeout = 0U; + 7459 .loc 1 3999 21 + 7460 00d8 0023 movs r3, #0 + 7461 00da FB61 str r3, [r7, #28] + 7462 .L364: +4000:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4001:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** count--; + 7463 .loc 1 4001 12 + 7464 00dc 7B69 ldr r3, [r7, #20] + 7465 00de 013B subs r3, r3, #1 + ARM GAS /tmp/ccs34gJO.s page 201 + + + 7466 00e0 7B61 str r3, [r7, #20] + 7467 .L357: +3963:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7468 .loc 1 3963 11 + 7469 00e2 FB68 ldr r3, [r7, #12] + 7470 00e4 1B68 ldr r3, [r3] + 7471 00e6 9A68 ldr r2, [r3, #8] + 7472 00e8 BB68 ldr r3, [r7, #8] + 7473 00ea 1340 ands r3, r3, r2 +3963:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7474 .loc 1 3963 48 + 7475 00ec BA68 ldr r2, [r7, #8] + 7476 00ee 9A42 cmp r2, r3 + 7477 00f0 0CBF ite eq + 7478 00f2 0123 moveq r3, #1 + 7479 00f4 0023 movne r3, #0 + 7480 00f6 DBB2 uxtb r3, r3 + 7481 00f8 1A46 mov r2, r3 +3963:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7482 .loc 1 3963 57 + 7483 00fa FB79 ldrb r3, [r7, #7] @ zero_extendqisi2 + 7484 00fc 9A42 cmp r2, r3 + 7485 00fe 9BD1 bne .L365 +4002:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4003:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4005:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return HAL_OK; + 7486 .loc 1 4005 10 + 7487 0100 0023 movs r3, #0 + 7488 .L363: +4006:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 7489 .loc 1 4006 1 + 7490 0102 1846 mov r0, r3 + 7491 0104 2037 adds r7, r7, #32 + 7492 .cfi_def_cfa_offset 8 + 7493 0106 BD46 mov sp, r7 + 7494 .cfi_def_cfa_register 13 + 7495 @ sp needed + 7496 0108 80BD pop {r7, pc} + 7497 .L367: + 7498 010a 00BF .align 2 + 7499 .L366: + 7500 010c 00000000 .word SystemCoreClock + 7501 .cfi_endproc + 7502 .LFE177: + 7504 .section .text.SPI_WaitFifoStateUntilTimeout,"ax",%progbits + 7505 .align 1 + 7506 .syntax unified + 7507 .thumb + 7508 .thumb_func + 7510 SPI_WaitFifoStateUntilTimeout: + 7511 .LFB178: +4007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4008:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +4009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Handle SPI FIFO Communication Timeout. +4010:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +4011:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. + ARM GAS /tmp/ccs34gJO.s page 202 + + +4012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param Fifo Fifo to check +4013:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param State Fifo state to check +4014:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param Timeout Timeout duration +4015:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param Tickstart tick start value +4016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval HAL status +4017:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +4018:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint +4019:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t Timeout, uint32_t Tickstart) +4020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7512 .loc 1 4020 1 + 7513 .cfi_startproc + 7514 @ args = 4, pretend = 0, frame = 40 + 7515 @ frame_needed = 1, uses_anonymous_args = 0 + 7516 0000 80B5 push {r7, lr} + 7517 .cfi_def_cfa_offset 8 + 7518 .cfi_offset 7, -8 + 7519 .cfi_offset 14, -4 + 7520 0002 8AB0 sub sp, sp, #40 + 7521 .cfi_def_cfa_offset 48 + 7522 0004 00AF add r7, sp, #0 + 7523 .cfi_def_cfa_register 7 + 7524 0006 F860 str r0, [r7, #12] + 7525 0008 B960 str r1, [r7, #8] + 7526 000a 7A60 str r2, [r7, #4] + 7527 000c 3B60 str r3, [r7] +4021:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint32_t count; +4022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t tmp_timeout; +4023:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t tmp_tickstart; +4024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint8_t *ptmpreg8; +4025:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint8_t tmpreg8 = 0; + 7528 .loc 1 4025 17 + 7529 000e 0023 movs r3, #0 + 7530 0010 FB75 strb r3, [r7, #23] +4026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Adjust Timeout value in case of end of transfer */ +4028:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); + 7531 .loc 1 4028 28 + 7532 0012 FFF7FEFF bl HAL_GetTick + 7533 0016 0246 mov r2, r0 + 7534 .loc 1 4028 42 discriminator 1 + 7535 0018 3B6B ldr r3, [r7, #48] + 7536 001a 9B1A subs r3, r3, r2 + 7537 .loc 1 4028 15 discriminator 1 + 7538 001c 3A68 ldr r2, [r7] + 7539 001e 1344 add r3, r3, r2 + 7540 0020 7B62 str r3, [r7, #36] +4029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmp_tickstart = HAL_GetTick(); + 7541 .loc 1 4029 19 + 7542 0022 FFF7FEFF bl HAL_GetTick + 7543 0026 3862 str r0, [r7, #32] +4030:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4031:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Initialize the 8bit temporary pointer */ +4032:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; + 7544 .loc 1 4032 35 + 7545 0028 FB68 ldr r3, [r7, #12] + 7546 002a 1B68 ldr r3, [r3] + 7547 .loc 1 4032 12 + ARM GAS /tmp/ccs34gJO.s page 203 + + + 7548 002c 0C33 adds r3, r3, #12 + 7549 002e FB61 str r3, [r7, #28] +4033:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ +4035:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** count = tmp_timeout * ((SystemCoreClock * 35U) >> 20U); + 7550 .loc 1 4035 43 + 7551 0030 3D4B ldr r3, .L380 + 7552 0032 1A68 ldr r2, [r3] + 7553 0034 1346 mov r3, r2 + 7554 0036 9B00 lsls r3, r3, #2 + 7555 0038 1344 add r3, r3, r2 + 7556 003a DA00 lsls r2, r3, #3 + 7557 003c D31A subs r3, r2, r3 + 7558 .loc 1 4035 50 + 7559 003e 1B0D lsrs r3, r3, #20 + 7560 .loc 1 4035 23 + 7561 0040 7A6A ldr r2, [r7, #36] + 7562 0042 02FB03F3 mul r3, r2, r3 + 7563 .loc 1 4035 9 + 7564 0046 BB61 str r3, [r7, #24] +4036:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** while ((hspi->Instance->SR & Fifo) != State) + 7565 .loc 1 4037 9 + 7566 0048 60E0 b .L371 + 7567 .L379: +4038:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4039:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY)) + 7568 .loc 1 4039 8 + 7569 004a BB68 ldr r3, [r7, #8] + 7570 004c B3F5C06F cmp r3, #1536 + 7571 0050 07D1 bne .L370 + 7572 .loc 1 4039 32 discriminator 1 + 7573 0052 7B68 ldr r3, [r7, #4] + 7574 0054 002B cmp r3, #0 + 7575 0056 04D1 bne .L370 +4040:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4041:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Flush Data Register by a blank read */ +4042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmpreg8 = *ptmpreg8; + 7576 .loc 1 4042 17 + 7577 0058 FB69 ldr r3, [r7, #28] + 7578 005a 1B78 ldrb r3, [r3] + 7579 005c DBB2 uxtb r3, r3 + 7580 .loc 1 4042 15 + 7581 005e FB75 strb r3, [r7, #23] +4043:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* To avoid GCC warning */ +4044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** UNUSED(tmpreg8); + 7582 .loc 1 4044 7 + 7583 0060 FB7D ldrb r3, [r7, #23] + 7584 .L370: +4045:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4046:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (Timeout != HAL_MAX_DELAY) + 7585 .loc 1 4047 8 + 7586 0062 3B68 ldr r3, [r7] + 7587 0064 B3F1FF3F cmp r3, #-1 + 7588 0068 50D0 beq .L371 +4048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + ARM GAS /tmp/ccs34gJO.s page 204 + + +4049:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U)) + 7589 .loc 1 4049 13 + 7590 006a FFF7FEFF bl HAL_GetTick + 7591 006e 0246 mov r2, r0 + 7592 .loc 1 4049 27 discriminator 1 + 7593 0070 3B6A ldr r3, [r7, #32] + 7594 0072 D31A subs r3, r2, r3 + 7595 .loc 1 4049 10 discriminator 1 + 7596 0074 7A6A ldr r2, [r7, #36] + 7597 0076 9A42 cmp r2, r3 + 7598 0078 02D9 bls .L372 + 7599 .loc 1 4049 60 discriminator 1 + 7600 007a 7B6A ldr r3, [r7, #36] + 7601 007c 002B cmp r3, #0 + 7602 007e 3DD1 bne .L373 + 7603 .L372: +4050:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable the SPI and reset the CRC: the CRC value should be cleared +4052:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** on both master and slave sides in order to resynchronize the master +4053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** and slave for their respective CRC calculation */ +4054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4055:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ +4056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + 7604 .loc 1 4056 9 + 7605 0080 FB68 ldr r3, [r7, #12] + 7606 0082 1B68 ldr r3, [r3] + 7607 0084 5A68 ldr r2, [r3, #4] + 7608 0086 FB68 ldr r3, [r7, #12] + 7609 0088 1B68 ldr r3, [r3] + 7610 008a 22F0E002 bic r2, r2, #224 + 7611 008e 5A60 str r2, [r3, #4] +4057:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + 7612 .loc 1 4058 24 + 7613 0090 FB68 ldr r3, [r7, #12] + 7614 0092 5B68 ldr r3, [r3, #4] + 7615 .loc 1 4058 12 + 7616 0094 B3F5827F cmp r3, #260 + 7617 0098 11D1 bne .L374 + 7618 .loc 1 4058 65 discriminator 1 + 7619 009a FB68 ldr r3, [r7, #12] + 7620 009c 9B68 ldr r3, [r3, #8] + 7621 .loc 1 4058 50 discriminator 1 + 7622 009e B3F5004F cmp r3, #32768 + 7623 00a2 04D0 beq .L375 +4059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** || (hspi->Init.Direction == SPI_DIRECTION_2LIN + 7624 .loc 1 4059 68 + 7625 00a4 FB68 ldr r3, [r7, #12] + 7626 00a6 9B68 ldr r3, [r3, #8] + 7627 .loc 1 4059 54 + 7628 00a8 B3F5806F cmp r3, #1024 + 7629 00ac 07D1 bne .L374 + 7630 .L375: +4060:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable SPI peripheral */ +4062:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE(hspi); + 7631 .loc 1 4062 11 + ARM GAS /tmp/ccs34gJO.s page 205 + + + 7632 00ae FB68 ldr r3, [r7, #12] + 7633 00b0 1B68 ldr r3, [r3] + 7634 00b2 1A68 ldr r2, [r3] + 7635 00b4 FB68 ldr r3, [r7, #12] + 7636 00b6 1B68 ldr r3, [r3] + 7637 00b8 22F04002 bic r2, r2, #64 + 7638 00bc 1A60 str r2, [r3] + 7639 .L374: +4063:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4064:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Reset CRC Calculation */ +4066:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + 7640 .loc 1 4066 23 + 7641 00be FB68 ldr r3, [r7, #12] + 7642 00c0 9B6A ldr r3, [r3, #40] + 7643 .loc 1 4066 12 + 7644 00c2 B3F5005F cmp r3, #8192 + 7645 00c6 0FD1 bne .L376 +4067:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SPI_RESET_CRC(hspi); + 7646 .loc 1 4068 11 + 7647 00c8 FB68 ldr r3, [r7, #12] + 7648 00ca 1B68 ldr r3, [r3] + 7649 00cc 1A68 ldr r2, [r3] + 7650 00ce FB68 ldr r3, [r7, #12] + 7651 00d0 1B68 ldr r3, [r3] + 7652 00d2 22F40052 bic r2, r2, #8192 + 7653 00d6 1A60 str r2, [r3] + 7654 00d8 FB68 ldr r3, [r7, #12] + 7655 00da 1B68 ldr r3, [r3] + 7656 00dc 1A68 ldr r2, [r3] + 7657 00de FB68 ldr r3, [r7, #12] + 7658 00e0 1B68 ldr r3, [r3] + 7659 00e2 42F40052 orr r2, r2, #8192 + 7660 00e6 1A60 str r2, [r3] + 7661 .L376: +4069:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4070:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; + 7662 .loc 1 4071 21 + 7663 00e8 FB68 ldr r3, [r7, #12] + 7664 00ea 0122 movs r2, #1 + 7665 00ec 83F85D20 strb r2, [r3, #93] +4072:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4073:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Process Unlocked */ +4074:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_UNLOCK(hspi); + 7666 .loc 1 4074 9 + 7667 00f0 FB68 ldr r3, [r7, #12] + 7668 00f2 0022 movs r2, #0 + 7669 00f4 83F85C20 strb r2, [r3, #92] +4075:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4076:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return HAL_TIMEOUT; + 7670 .loc 1 4076 16 + 7671 00f8 0323 movs r3, #3 + 7672 00fa 10E0 b .L377 + 7673 .L373: +4077:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + ARM GAS /tmp/ccs34gJO.s page 206 + + +4078:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop proced +4079:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (count == 0U) + 7674 .loc 1 4079 17 + 7675 00fc BB69 ldr r3, [r7, #24] + 7676 .loc 1 4079 10 + 7677 00fe 002B cmp r3, #0 + 7678 0100 01D1 bne .L378 +4080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4081:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tmp_timeout = 0U; + 7679 .loc 1 4081 21 + 7680 0102 0023 movs r3, #0 + 7681 0104 7B62 str r3, [r7, #36] + 7682 .L378: +4082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** count--; + 7683 .loc 1 4083 12 + 7684 0106 BB69 ldr r3, [r7, #24] + 7685 0108 013B subs r3, r3, #1 + 7686 010a BB61 str r3, [r7, #24] + 7687 .L371: +4037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7688 .loc 1 4037 15 + 7689 010c FB68 ldr r3, [r7, #12] + 7690 010e 1B68 ldr r3, [r3] +4037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7691 .loc 1 4037 25 + 7692 0110 9A68 ldr r2, [r3, #8] +4037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7693 .loc 1 4037 30 + 7694 0112 BB68 ldr r3, [r7, #8] + 7695 0114 1340 ands r3, r3, r2 +4037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7696 .loc 1 4037 38 + 7697 0116 7A68 ldr r2, [r7, #4] + 7698 0118 9A42 cmp r2, r3 + 7699 011a 96D1 bne .L379 +4084:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4086:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4087:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return HAL_OK; + 7700 .loc 1 4087 10 + 7701 011c 0023 movs r3, #0 + 7702 .L377: +4088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 7703 .loc 1 4088 1 + 7704 011e 1846 mov r0, r3 + 7705 0120 2837 adds r7, r7, #40 + 7706 .cfi_def_cfa_offset 8 + 7707 0122 BD46 mov sp, r7 + 7708 .cfi_def_cfa_register 13 + 7709 @ sp needed + 7710 0124 80BD pop {r7, pc} + 7711 .L381: + 7712 0126 00BF .align 2 + 7713 .L380: + 7714 0128 00000000 .word SystemCoreClock + 7715 .cfi_endproc + ARM GAS /tmp/ccs34gJO.s page 207 + + + 7716 .LFE178: + 7718 .section .text.SPI_EndRxTransaction,"ax",%progbits + 7719 .align 1 + 7720 .syntax unified + 7721 .thumb + 7722 .thumb_func + 7724 SPI_EndRxTransaction: + 7725 .LFB179: +4089:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4090:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +4091:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Handle the check of the RX transaction complete. +4092:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +4093:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +4094:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param Timeout Timeout duration +4095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param Tickstart tick start value +4096:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval HAL status +4097:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +4098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t +4099:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7726 .loc 1 4099 1 + 7727 .cfi_startproc + 7728 @ args = 0, pretend = 0, frame = 16 + 7729 @ frame_needed = 1, uses_anonymous_args = 0 + 7730 0000 80B5 push {r7, lr} + 7731 .cfi_def_cfa_offset 8 + 7732 .cfi_offset 7, -8 + 7733 .cfi_offset 14, -4 + 7734 0002 86B0 sub sp, sp, #24 + 7735 .cfi_def_cfa_offset 32 + 7736 0004 02AF add r7, sp, #8 + 7737 .cfi_def_cfa 7, 24 + 7738 0006 F860 str r0, [r7, #12] + 7739 0008 B960 str r1, [r7, #8] + 7740 000a 7A60 str r2, [r7, #4] +4100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + 7741 .loc 1 4100 18 + 7742 000c FB68 ldr r3, [r7, #12] + 7743 000e 5B68 ldr r3, [r3, #4] + 7744 .loc 1 4100 6 + 7745 0010 B3F5827F cmp r3, #260 + 7746 0014 11D1 bne .L383 + 7747 .loc 1 4100 59 discriminator 1 + 7748 0016 FB68 ldr r3, [r7, #12] + 7749 0018 9B68 ldr r3, [r3, #8] + 7750 .loc 1 4100 44 discriminator 1 + 7751 001a B3F5004F cmp r3, #32768 + 7752 001e 04D0 beq .L384 +4101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXO + 7753 .loc 1 4101 62 + 7754 0020 FB68 ldr r3, [r7, #12] + 7755 0022 9B68 ldr r3, [r3, #8] + 7756 .loc 1 4101 48 + 7757 0024 B3F5806F cmp r3, #1024 + 7758 0028 07D1 bne .L383 + 7759 .L384: +4102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable SPI peripheral */ + ARM GAS /tmp/ccs34gJO.s page 208 + + +4104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE(hspi); + 7760 .loc 1 4104 5 + 7761 002a FB68 ldr r3, [r7, #12] + 7762 002c 1B68 ldr r3, [r3] + 7763 002e 1A68 ldr r2, [r3] + 7764 0030 FB68 ldr r3, [r7, #12] + 7765 0032 1B68 ldr r3, [r3] + 7766 0034 22F04002 bic r2, r2, #64 + 7767 0038 1A60 str r2, [r3] + 7768 .L383: +4105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Control the BSY flag */ +4108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) + 7769 .loc 1 4108 7 + 7770 003a 7B68 ldr r3, [r7, #4] + 7771 003c 0093 str r3, [sp] + 7772 003e BB68 ldr r3, [r7, #8] + 7773 0040 0022 movs r2, #0 + 7774 0042 8021 movs r1, #128 + 7775 0044 F868 ldr r0, [r7, #12] + 7776 0046 FFF7FEFF bl SPI_WaitFlagStateUntilTimeout + 7777 004a 0346 mov r3, r0 + 7778 .loc 1 4108 6 discriminator 1 + 7779 004c 002B cmp r3, #0 + 7780 004e 07D0 beq .L385 +4109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + 7781 .loc 1 4110 5 + 7782 0050 FB68 ldr r3, [r7, #12] + 7783 0052 1B6E ldr r3, [r3, #96] + 7784 0054 43F02002 orr r2, r3, #32 + 7785 0058 FB68 ldr r3, [r7, #12] + 7786 005a 1A66 str r2, [r3, #96] +4111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return HAL_TIMEOUT; + 7787 .loc 1 4111 12 + 7788 005c 0323 movs r3, #3 + 7789 005e 23E0 b .L386 + 7790 .L385: +4112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + 7791 .loc 1 4114 18 + 7792 0060 FB68 ldr r3, [r7, #12] + 7793 0062 5B68 ldr r3, [r3, #4] + 7794 .loc 1 4114 6 + 7795 0064 B3F5827F cmp r3, #260 + 7796 0068 1DD1 bne .L387 + 7797 .loc 1 4114 59 discriminator 1 + 7798 006a FB68 ldr r3, [r7, #12] + 7799 006c 9B68 ldr r3, [r3, #8] + 7800 .loc 1 4114 44 discriminator 1 + 7801 006e B3F5004F cmp r3, #32768 + 7802 0072 04D0 beq .L388 +4115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXO + 7803 .loc 1 4115 62 + 7804 0074 FB68 ldr r3, [r7, #12] + ARM GAS /tmp/ccs34gJO.s page 209 + + + 7805 0076 9B68 ldr r3, [r3, #8] + 7806 .loc 1 4115 48 + 7807 0078 B3F5806F cmp r3, #1024 + 7808 007c 13D1 bne .L387 + 7809 .L388: +4116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Empty the FRLVL fifo */ +4118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != + 7810 .loc 1 4118 9 + 7811 007e 7B68 ldr r3, [r7, #4] + 7812 0080 0093 str r3, [sp] + 7813 0082 BB68 ldr r3, [r7, #8] + 7814 0084 0022 movs r2, #0 + 7815 0086 4FF4C061 mov r1, #1536 + 7816 008a F868 ldr r0, [r7, #12] + 7817 008c FFF7FEFF bl SPI_WaitFifoStateUntilTimeout + 7818 0090 0346 mov r3, r0 + 7819 .loc 1 4118 8 discriminator 1 + 7820 0092 002B cmp r3, #0 + 7821 0094 07D0 beq .L387 +4119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + 7822 .loc 1 4120 7 + 7823 0096 FB68 ldr r3, [r7, #12] + 7824 0098 1B6E ldr r3, [r3, #96] + 7825 009a 43F02002 orr r2, r3, #32 + 7826 009e FB68 ldr r3, [r7, #12] + 7827 00a0 1A66 str r2, [r3, #96] +4121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return HAL_TIMEOUT; + 7828 .loc 1 4121 14 + 7829 00a2 0323 movs r3, #3 + 7830 00a4 00E0 b .L386 + 7831 .L387: +4122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return HAL_OK; + 7832 .loc 1 4124 10 + 7833 00a6 0023 movs r3, #0 + 7834 .L386: +4125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 7835 .loc 1 4125 1 + 7836 00a8 1846 mov r0, r3 + 7837 00aa 1037 adds r7, r7, #16 + 7838 .cfi_def_cfa_offset 8 + 7839 00ac BD46 mov sp, r7 + 7840 .cfi_def_cfa_register 13 + 7841 @ sp needed + 7842 00ae 80BD pop {r7, pc} + 7843 .cfi_endproc + 7844 .LFE179: + 7846 .section .text.SPI_EndRxTxTransaction,"ax",%progbits + 7847 .align 1 + 7848 .syntax unified + 7849 .thumb + 7850 .thumb_func + 7852 SPI_EndRxTxTransaction: + 7853 .LFB180: + ARM GAS /tmp/ccs34gJO.s page 210 + + +4126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +4128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Handle the check of the RXTX or TX transaction complete. +4129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi SPI handle +4130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param Timeout Timeout duration +4131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param Tickstart tick start value +4132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval HAL status +4133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +4134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t +4135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7854 .loc 1 4135 1 + 7855 .cfi_startproc + 7856 @ args = 0, pretend = 0, frame = 16 + 7857 @ frame_needed = 1, uses_anonymous_args = 0 + 7858 0000 80B5 push {r7, lr} + 7859 .cfi_def_cfa_offset 8 + 7860 .cfi_offset 7, -8 + 7861 .cfi_offset 14, -4 + 7862 0002 86B0 sub sp, sp, #24 + 7863 .cfi_def_cfa_offset 32 + 7864 0004 02AF add r7, sp, #8 + 7865 .cfi_def_cfa 7, 24 + 7866 0006 F860 str r0, [r7, #12] + 7867 0008 B960 str r1, [r7, #8] + 7868 000a 7A60 str r2, [r7, #4] +4136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Control if the TX fifo is empty */ +4137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != H + 7869 .loc 1 4137 7 + 7870 000c 7B68 ldr r3, [r7, #4] + 7871 000e 0093 str r3, [sp] + 7872 0010 BB68 ldr r3, [r7, #8] + 7873 0012 0022 movs r2, #0 + 7874 0014 4FF4C051 mov r1, #6144 + 7875 0018 F868 ldr r0, [r7, #12] + 7876 001a FFF7FEFF bl SPI_WaitFifoStateUntilTimeout + 7877 001e 0346 mov r3, r0 + 7878 .loc 1 4137 6 discriminator 1 + 7879 0020 002B cmp r3, #0 + 7880 0022 07D0 beq .L390 +4138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + 7881 .loc 1 4139 5 + 7882 0024 FB68 ldr r3, [r7, #12] + 7883 0026 1B6E ldr r3, [r3, #96] + 7884 0028 43F02002 orr r2, r3, #32 + 7885 002c FB68 ldr r3, [r7, #12] + 7886 002e 1A66 str r2, [r3, #96] +4140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return HAL_TIMEOUT; + 7887 .loc 1 4140 12 + 7888 0030 0323 movs r3, #3 + 7889 0032 27E0 b .L391 + 7890 .L390: +4141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Control the BSY flag */ +4144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) + 7891 .loc 1 4144 7 + ARM GAS /tmp/ccs34gJO.s page 211 + + + 7892 0034 7B68 ldr r3, [r7, #4] + 7893 0036 0093 str r3, [sp] + 7894 0038 BB68 ldr r3, [r7, #8] + 7895 003a 0022 movs r2, #0 + 7896 003c 8021 movs r1, #128 + 7897 003e F868 ldr r0, [r7, #12] + 7898 0040 FFF7FEFF bl SPI_WaitFlagStateUntilTimeout + 7899 0044 0346 mov r3, r0 + 7900 .loc 1 4144 6 discriminator 1 + 7901 0046 002B cmp r3, #0 + 7902 0048 07D0 beq .L392 +4145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + 7903 .loc 1 4146 5 + 7904 004a FB68 ldr r3, [r7, #12] + 7905 004c 1B6E ldr r3, [r3, #96] + 7906 004e 43F02002 orr r2, r3, #32 + 7907 0052 FB68 ldr r3, [r7, #12] + 7908 0054 1A66 str r2, [r3, #96] +4147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return HAL_TIMEOUT; + 7909 .loc 1 4147 12 + 7910 0056 0323 movs r3, #3 + 7911 0058 14E0 b .L391 + 7912 .L392: +4148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Control if the RX fifo is empty */ +4151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != H + 7913 .loc 1 4151 7 + 7914 005a 7B68 ldr r3, [r7, #4] + 7915 005c 0093 str r3, [sp] + 7916 005e BB68 ldr r3, [r7, #8] + 7917 0060 0022 movs r2, #0 + 7918 0062 4FF4C061 mov r1, #1536 + 7919 0066 F868 ldr r0, [r7, #12] + 7920 0068 FFF7FEFF bl SPI_WaitFifoStateUntilTimeout + 7921 006c 0346 mov r3, r0 + 7922 .loc 1 4151 6 discriminator 1 + 7923 006e 002B cmp r3, #0 + 7924 0070 07D0 beq .L393 +4152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + 7925 .loc 1 4153 5 + 7926 0072 FB68 ldr r3, [r7, #12] + 7927 0074 1B6E ldr r3, [r3, #96] + 7928 0076 43F02002 orr r2, r3, #32 + 7929 007a FB68 ldr r3, [r7, #12] + 7930 007c 1A66 str r2, [r3, #96] +4154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return HAL_TIMEOUT; + 7931 .loc 1 4154 12 + 7932 007e 0323 movs r3, #3 + 7933 0080 00E0 b .L391 + 7934 .L393: +4155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** return HAL_OK; + 7935 .loc 1 4157 10 + ARM GAS /tmp/ccs34gJO.s page 212 + + + 7936 0082 0023 movs r3, #0 + 7937 .L391: +4158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 7938 .loc 1 4158 1 + 7939 0084 1846 mov r0, r3 + 7940 0086 1037 adds r7, r7, #16 + 7941 .cfi_def_cfa_offset 8 + 7942 0088 BD46 mov sp, r7 + 7943 .cfi_def_cfa_register 13 + 7944 @ sp needed + 7945 008a 80BD pop {r7, pc} + 7946 .cfi_endproc + 7947 .LFE180: + 7949 .section .text.SPI_CloseRxTx_ISR,"ax",%progbits + 7950 .align 1 + 7951 .syntax unified + 7952 .thumb + 7953 .thumb_func + 7955 SPI_CloseRxTx_ISR: + 7956 .LFB181: +4159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +4161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Handle the end of the RXTX transaction. +4162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +4163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +4164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +4165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +4166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) +4167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 7957 .loc 1 4167 1 + 7958 .cfi_startproc + 7959 @ args = 0, pretend = 0, frame = 16 + 7960 @ frame_needed = 1, uses_anonymous_args = 0 + 7961 0000 80B5 push {r7, lr} + 7962 .cfi_def_cfa_offset 8 + 7963 .cfi_offset 7, -8 + 7964 .cfi_offset 14, -4 + 7965 0002 84B0 sub sp, sp, #16 + 7966 .cfi_def_cfa_offset 24 + 7967 0004 00AF add r7, sp, #0 + 7968 .cfi_def_cfa_register 7 + 7969 0006 7860 str r0, [r7, #4] +4168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t tickstart; +4169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Init tickstart for timeout management */ +4171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tickstart = HAL_GetTick(); + 7970 .loc 1 4171 15 + 7971 0008 FFF7FEFF bl HAL_GetTick + 7972 000c F860 str r0, [r7, #12] +4172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable ERR interrupt */ +4174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); + 7973 .loc 1 4174 3 + 7974 000e 7B68 ldr r3, [r7, #4] + 7975 0010 1B68 ldr r3, [r3] + 7976 0012 5A68 ldr r2, [r3, #4] + 7977 0014 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/ccs34gJO.s page 213 + + + 7978 0016 1B68 ldr r3, [r3] + 7979 0018 22F02002 bic r2, r2, #32 + 7980 001c 5A60 str r2, [r3, #4] +4175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check the end of the transaction */ +4177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + 7981 .loc 1 4177 7 + 7982 001e FA68 ldr r2, [r7, #12] + 7983 0020 6421 movs r1, #100 + 7984 0022 7868 ldr r0, [r7, #4] + 7985 0024 FFF7FEFF bl SPI_EndRxTxTransaction + 7986 0028 0346 mov r3, r0 + 7987 .loc 1 4177 6 discriminator 1 + 7988 002a 002B cmp r3, #0 + 7989 002c 05D0 beq .L395 +4178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + 7990 .loc 1 4179 5 + 7991 002e 7B68 ldr r3, [r7, #4] + 7992 0030 1B6E ldr r3, [r3, #96] + 7993 0032 43F02002 orr r2, r3, #32 + 7994 0036 7B68 ldr r3, [r7, #4] + 7995 0038 1A66 str r2, [r3, #96] + 7996 .L395: +4180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +4183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check if CRC error occurred */ +4184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) +4185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; +4187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); +4188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_CRCERRFLAG(hspi); +4189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user error callback */ +4190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +4191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCallback(hspi); +4192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else +4193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_ErrorCallback(hspi); +4194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +4195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +4197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +4199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->ErrorCode == HAL_SPI_ERROR_NONE) + 7997 .loc 1 4199 13 + 7998 003a 7B68 ldr r3, [r7, #4] + 7999 003c 1B6E ldr r3, [r3, #96] + 8000 .loc 1 4199 8 + 8001 003e 002B cmp r3, #0 + 8002 0040 15D1 bne .L396 +4200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->State == HAL_SPI_STATE_BUSY_RX) + 8003 .loc 1 4201 15 + 8004 0042 7B68 ldr r3, [r7, #4] + 8005 0044 93F85D30 ldrb r3, [r3, #93] + 8006 0048 DBB2 uxtb r3, r3 + 8007 .loc 1 4201 10 + ARM GAS /tmp/ccs34gJO.s page 214 + + + 8008 004a 042B cmp r3, #4 + 8009 004c 07D1 bne .L397 +4202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; + 8010 .loc 1 4203 21 + 8011 004e 7B68 ldr r3, [r7, #4] + 8012 0050 0122 movs r2, #1 + 8013 0052 83F85D20 strb r2, [r3, #93] +4204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user Rx complete callback */ +4205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +4206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxCpltCallback(hspi); +4207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else +4208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_RxCpltCallback(hspi); + 8014 .loc 1 4208 9 + 8015 0056 7868 ldr r0, [r7, #4] + 8016 0058 FFF7FEFF bl HAL_SPI_RxCpltCallback +4209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +4210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +4212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; +4214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user TxRx complete callback */ +4215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +4216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxRxCpltCallback(hspi); +4217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else +4218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_TxRxCpltCallback(hspi); +4219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +4220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +4223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; +4225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user error callback */ +4226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +4227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCallback(hspi); +4228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else +4229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_ErrorCallback(hspi); +4230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +4231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +4233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +4235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 8017 .loc 1 4235 1 + 8018 005c 0EE0 b .L399 + 8019 .L397: +4213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user TxRx complete callback */ + 8020 .loc 1 4213 21 + 8021 005e 7B68 ldr r3, [r7, #4] + 8022 0060 0122 movs r2, #1 + 8023 0062 83F85D20 strb r2, [r3, #93] +4218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + 8024 .loc 1 4218 9 + 8025 0066 7868 ldr r0, [r7, #4] + 8026 0068 FFF7FEFF bl HAL_SPI_TxRxCpltCallback + 8027 .loc 1 4235 1 + 8028 006c 06E0 b .L399 + ARM GAS /tmp/ccs34gJO.s page 215 + + + 8029 .L396: +4224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user error callback */ + 8030 .loc 1 4224 19 + 8031 006e 7B68 ldr r3, [r7, #4] + 8032 0070 0122 movs r2, #1 + 8033 0072 83F85D20 strb r2, [r3, #93] +4229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + 8034 .loc 1 4229 7 + 8035 0076 7868 ldr r0, [r7, #4] + 8036 0078 FFF7FEFF bl HAL_SPI_ErrorCallback + 8037 .L399: + 8038 .loc 1 4235 1 + 8039 007c 00BF nop + 8040 007e 1037 adds r7, r7, #16 + 8041 .cfi_def_cfa_offset 8 + 8042 0080 BD46 mov sp, r7 + 8043 .cfi_def_cfa_register 13 + 8044 @ sp needed + 8045 0082 80BD pop {r7, pc} + 8046 .cfi_endproc + 8047 .LFE181: + 8049 .section .text.SPI_CloseRx_ISR,"ax",%progbits + 8050 .align 1 + 8051 .syntax unified + 8052 .thumb + 8053 .thumb_func + 8055 SPI_CloseRx_ISR: + 8056 .LFB182: +4236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +4238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Handle the end of the RX transaction. +4239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +4240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +4241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +4242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +4243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi) +4244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 8057 .loc 1 4244 1 + 8058 .cfi_startproc + 8059 @ args = 0, pretend = 0, frame = 8 + 8060 @ frame_needed = 1, uses_anonymous_args = 0 + 8061 0000 80B5 push {r7, lr} + 8062 .cfi_def_cfa_offset 8 + 8063 .cfi_offset 7, -8 + 8064 .cfi_offset 14, -4 + 8065 0002 82B0 sub sp, sp, #8 + 8066 .cfi_def_cfa_offset 16 + 8067 0004 00AF add r7, sp, #0 + 8068 .cfi_def_cfa_register 7 + 8069 0006 7860 str r0, [r7, #4] +4245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable RXNE and ERR interrupt */ +4246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + 8070 .loc 1 4246 3 + 8071 0008 7B68 ldr r3, [r7, #4] + 8072 000a 1B68 ldr r3, [r3] + 8073 000c 5A68 ldr r2, [r3, #4] + 8074 000e 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/ccs34gJO.s page 216 + + + 8075 0010 1B68 ldr r3, [r3] + 8076 0012 22F06002 bic r2, r2, #96 + 8077 0016 5A60 str r2, [r3, #4] +4247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check the end of the transaction */ +4249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + 8078 .loc 1 4249 7 + 8079 0018 FFF7FEFF bl HAL_GetTick + 8080 001c 0346 mov r3, r0 + 8081 .loc 1 4249 7 is_stmt 0 discriminator 1 + 8082 001e 1A46 mov r2, r3 + 8083 0020 6421 movs r1, #100 + 8084 0022 7868 ldr r0, [r7, #4] + 8085 0024 FFF7FEFF bl SPI_EndRxTransaction + 8086 0028 0346 mov r3, r0 + 8087 .loc 1 4249 6 is_stmt 1 discriminator 2 + 8088 002a 002B cmp r3, #0 + 8089 002c 05D0 beq .L401 +4250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + 8090 .loc 1 4251 5 + 8091 002e 7B68 ldr r3, [r7, #4] + 8092 0030 1B6E ldr r3, [r3, #96] + 8093 0032 43F02002 orr r2, r3, #32 + 8094 0036 7B68 ldr r3, [r7, #4] + 8095 0038 1A66 str r2, [r3, #96] + 8096 .L401: +4252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; + 8097 .loc 1 4253 15 + 8098 003a 7B68 ldr r3, [r7, #4] + 8099 003c 0122 movs r2, #1 + 8100 003e 83F85D20 strb r2, [r3, #93] +4254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +4256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check if CRC error occurred */ +4257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) +4258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); +4260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_CRCERRFLAG(hspi); +4261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user error callback */ +4262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +4263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCallback(hspi); +4264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else +4265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_ErrorCallback(hspi); +4266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +4267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +4269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +4271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->ErrorCode == HAL_SPI_ERROR_NONE) + 8101 .loc 1 4271 13 + 8102 0042 7B68 ldr r3, [r7, #4] + 8103 0044 1B6E ldr r3, [r3, #96] + 8104 .loc 1 4271 8 + 8105 0046 002B cmp r3, #0 + 8106 0048 03D1 bne .L402 + ARM GAS /tmp/ccs34gJO.s page 217 + + +4272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user Rx complete callback */ +4274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +4275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->RxCpltCallback(hspi); +4276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else +4277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_RxCpltCallback(hspi); + 8107 .loc 1 4277 7 + 8108 004a 7868 ldr r0, [r7, #4] + 8109 004c FFF7FEFF bl HAL_SPI_RxCpltCallback +4278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +4279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +4281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user error callback */ +4283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +4284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCallback(hspi); +4285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else +4286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_ErrorCallback(hspi); +4287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +4288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_SPI_CRC != 0U) +4290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_SPI_CRC */ +4292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 8110 .loc 1 4292 1 + 8111 0050 02E0 b .L404 + 8112 .L402: +4286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + 8113 .loc 1 4286 7 + 8114 0052 7868 ldr r0, [r7, #4] + 8115 0054 FFF7FEFF bl HAL_SPI_ErrorCallback + 8116 .L404: + 8117 .loc 1 4292 1 + 8118 0058 00BF nop + 8119 005a 0837 adds r7, r7, #8 + 8120 .cfi_def_cfa_offset 8 + 8121 005c BD46 mov sp, r7 + 8122 .cfi_def_cfa_register 13 + 8123 @ sp needed + 8124 005e 80BD pop {r7, pc} + 8125 .cfi_endproc + 8126 .LFE182: + 8128 .section .text.SPI_CloseTx_ISR,"ax",%progbits + 8129 .align 1 + 8130 .syntax unified + 8131 .thumb + 8132 .thumb_func + 8134 SPI_CloseTx_ISR: + 8135 .LFB183: +4293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +4295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Handle the end of the TX transaction. +4296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +4297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +4298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +4299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +4300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi) + ARM GAS /tmp/ccs34gJO.s page 218 + + +4301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 8136 .loc 1 4301 1 + 8137 .cfi_startproc + 8138 @ args = 0, pretend = 0, frame = 16 + 8139 @ frame_needed = 1, uses_anonymous_args = 0 + 8140 0000 80B5 push {r7, lr} + 8141 .cfi_def_cfa_offset 8 + 8142 .cfi_offset 7, -8 + 8143 .cfi_offset 14, -4 + 8144 0002 84B0 sub sp, sp, #16 + 8145 .cfi_def_cfa_offset 24 + 8146 0004 00AF add r7, sp, #0 + 8147 .cfi_def_cfa_register 7 + 8148 0006 7860 str r0, [r7, #4] +4302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** uint32_t tickstart; +4303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Init tickstart for timeout management*/ +4305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** tickstart = HAL_GetTick(); + 8149 .loc 1 4305 15 + 8150 0008 FFF7FEFF bl HAL_GetTick + 8151 000c F860 str r0, [r7, #12] +4306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable TXE and ERR interrupt */ +4308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); + 8152 .loc 1 4308 3 + 8153 000e 7B68 ldr r3, [r7, #4] + 8154 0010 1B68 ldr r3, [r3] + 8155 0012 5A68 ldr r2, [r3, #4] + 8156 0014 7B68 ldr r3, [r7, #4] + 8157 0016 1B68 ldr r3, [r3] + 8158 0018 22F0A002 bic r2, r2, #160 + 8159 001c 5A60 str r2, [r3, #4] +4309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check the end of the transaction */ +4311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + 8160 .loc 1 4311 7 + 8161 001e FA68 ldr r2, [r7, #12] + 8162 0020 6421 movs r1, #100 + 8163 0022 7868 ldr r0, [r7, #4] + 8164 0024 FFF7FEFF bl SPI_EndRxTxTransaction + 8165 0028 0346 mov r3, r0 + 8166 .loc 1 4311 6 discriminator 1 + 8167 002a 002B cmp r3, #0 + 8168 002c 05D0 beq .L406 +4312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + 8169 .loc 1 4313 5 + 8170 002e 7B68 ldr r3, [r7, #4] + 8171 0030 1B6E ldr r3, [r3, #96] + 8172 0032 43F02002 orr r2, r3, #32 + 8173 0036 7B68 ldr r3, [r7, #4] + 8174 0038 1A66 str r2, [r3, #96] + 8175 .L406: +4314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Clear overrun flag in 2 Lines communication mode because received is not read */ +4317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + ARM GAS /tmp/ccs34gJO.s page 219 + + + 8176 .loc 1 4317 17 + 8177 003a 7B68 ldr r3, [r7, #4] + 8178 003c 9B68 ldr r3, [r3, #8] + 8179 .loc 1 4317 6 + 8180 003e 002B cmp r3, #0 + 8181 0040 0AD1 bne .L407 + 8182 .LBB16: +4318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_CLEAR_OVRFLAG(hspi); + 8183 .loc 1 4319 5 + 8184 0042 0023 movs r3, #0 + 8185 0044 BB60 str r3, [r7, #8] + 8186 0046 7B68 ldr r3, [r7, #4] + 8187 0048 1B68 ldr r3, [r3] + 8188 004a DB68 ldr r3, [r3, #12] + 8189 004c BB60 str r3, [r7, #8] + 8190 004e 7B68 ldr r3, [r7, #4] + 8191 0050 1B68 ldr r3, [r3] + 8192 0052 9B68 ldr r3, [r3, #8] + 8193 0054 BB60 str r3, [r7, #8] + 8194 0056 BB68 ldr r3, [r7, #8] + 8195 .L407: + 8196 .LBE16: +4320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_READY; + 8197 .loc 1 4322 15 + 8198 0058 7B68 ldr r3, [r7, #4] + 8199 005a 0122 movs r2, #1 + 8200 005c 83F85D20 strb r2, [r3, #93] +4323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + 8201 .loc 1 4323 11 + 8202 0060 7B68 ldr r3, [r7, #4] + 8203 0062 1B6E ldr r3, [r3, #96] + 8204 .loc 1 4323 6 + 8205 0064 002B cmp r3, #0 + 8206 0066 03D0 beq .L408 +4324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user error callback */ +4326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +4327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCallback(hspi); +4328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else +4329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_ErrorCallback(hspi); + 8207 .loc 1 4329 5 + 8208 0068 7868 ldr r0, [r7, #4] + 8209 006a FFF7FEFF bl HAL_SPI_ErrorCallback +4330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +4331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** else +4333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Call user Rx complete callback */ +4335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +4336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->TxCpltCallback(hspi); +4337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #else +4338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** HAL_SPI_TxCpltCallback(hspi); +4339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +4340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + ARM GAS /tmp/ccs34gJO.s page 220 + + +4341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 8210 .loc 1 4341 1 + 8211 006e 02E0 b .L410 + 8212 .L408: +4338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + 8213 .loc 1 4338 5 + 8214 0070 7868 ldr r0, [r7, #4] + 8215 0072 FFF7FEFF bl HAL_SPI_TxCpltCallback + 8216 .L410: + 8217 .loc 1 4341 1 + 8218 0076 00BF nop + 8219 0078 1037 adds r7, r7, #16 + 8220 .cfi_def_cfa_offset 8 + 8221 007a BD46 mov sp, r7 + 8222 .cfi_def_cfa_register 13 + 8223 @ sp needed + 8224 007c 80BD pop {r7, pc} + 8225 .cfi_endproc + 8226 .LFE183: + 8228 .section .text.SPI_AbortRx_ISR,"ax",%progbits + 8229 .align 1 + 8230 .syntax unified + 8231 .thumb + 8232 .thumb_func + 8234 SPI_AbortRx_ISR: + 8235 .LFB184: +4342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +4344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Handle abort a Rx transaction. +4345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +4346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +4347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +4348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +4349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi) +4350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 8236 .loc 1 4350 1 + 8237 .cfi_startproc + 8238 @ args = 0, pretend = 0, frame = 16 + 8239 @ frame_needed = 1, uses_anonymous_args = 0 + 8240 0000 80B5 push {r7, lr} + 8241 .cfi_def_cfa_offset 8 + 8242 .cfi_offset 7, -8 + 8243 .cfi_offset 14, -4 + 8244 0002 86B0 sub sp, sp, #24 + 8245 .cfi_def_cfa_offset 32 + 8246 0004 02AF add r7, sp, #8 + 8247 .cfi_def_cfa 7, 24 + 8248 0006 7860 str r0, [r7, #4] +4351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint32_t count; +4352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable SPI Peripheral */ +4354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE(hspi); + 8249 .loc 1 4354 3 + 8250 0008 7B68 ldr r3, [r7, #4] + 8251 000a 1B68 ldr r3, [r3] + 8252 000c 1A68 ldr r2, [r3] + 8253 000e 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/ccs34gJO.s page 221 + + + 8254 0010 1B68 ldr r3, [r3] + 8255 0012 22F04002 bic r2, r2, #64 + 8256 0016 1A60 str r2, [r3] +4355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + 8257 .loc 1 4356 56 + 8258 0018 274B ldr r3, .L417 + 8259 001a 1B68 ldr r3, [r3] + 8260 001c 274A ldr r2, .L417+4 + 8261 001e A2FB0323 umull r2, r3, r2, r3 + 8262 0022 5B0A lsrs r3, r3, #9 + 8263 .loc 1 4356 31 + 8264 0024 6422 movs r2, #100 + 8265 0026 02FB03F3 mul r3, r2, r3 + 8266 .loc 1 4356 9 + 8267 002a FB60 str r3, [r7, #12] +4357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable RXNEIE interrupt */ +4359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE)); + 8268 .loc 1 4359 3 + 8269 002c 7B68 ldr r3, [r7, #4] + 8270 002e 1B68 ldr r3, [r3] + 8271 0030 5A68 ldr r2, [r3, #4] + 8272 0032 7B68 ldr r3, [r7, #4] + 8273 0034 1B68 ldr r3, [r3] + 8274 0036 22F04002 bic r2, r2, #64 + 8275 003a 5A60 str r2, [r3, #4] + 8276 .L414: +4360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check RXNEIE is disabled */ +4362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** do +4363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (count == 0U) + 8277 .loc 1 4364 15 + 8278 003c FB68 ldr r3, [r7, #12] + 8279 .loc 1 4364 8 + 8280 003e 002B cmp r3, #0 + 8281 0040 06D1 bne .L412 +4365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + 8282 .loc 1 4366 7 + 8283 0042 7B68 ldr r3, [r7, #4] + 8284 0044 1B6E ldr r3, [r3, #96] + 8285 0046 43F04002 orr r2, r3, #64 + 8286 004a 7B68 ldr r3, [r7, #4] + 8287 004c 1A66 str r2, [r3, #96] +4367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 8288 .loc 1 4367 7 + 8289 004e 09E0 b .L413 + 8290 .L412: +4368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** count--; + 8291 .loc 1 4369 10 + 8292 0050 FB68 ldr r3, [r7, #12] + 8293 0052 013B subs r3, r3, #1 + 8294 0054 FB60 str r3, [r7, #12] +4370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)); + ARM GAS /tmp/ccs34gJO.s page 222 + + + 8295 .loc 1 4370 12 + 8296 0056 7B68 ldr r3, [r7, #4] + 8297 0058 1B68 ldr r3, [r3] + 8298 005a 5B68 ldr r3, [r3, #4] + 8299 005c 03F04003 and r3, r3, #64 + 8300 0060 402B cmp r3, #64 + 8301 0062 EBD0 beq .L414 + 8302 .L413: +4371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Control the BSY flag */ +4373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) + 8303 .loc 1 4373 7 + 8304 0064 FFF7FEFF bl HAL_GetTick + 8305 0068 0346 mov r3, r0 + 8306 .loc 1 4373 7 is_stmt 0 discriminator 1 + 8307 006a 0093 str r3, [sp] + 8308 006c 6423 movs r3, #100 + 8309 006e 0022 movs r2, #0 + 8310 0070 8021 movs r1, #128 + 8311 0072 7868 ldr r0, [r7, #4] + 8312 0074 FFF7FEFF bl SPI_WaitFlagStateUntilTimeout + 8313 0078 0346 mov r3, r0 + 8314 .loc 1 4373 6 is_stmt 1 discriminator 2 + 8315 007a 002B cmp r3, #0 + 8316 007c 02D0 beq .L415 +4374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + 8317 .loc 1 4375 21 + 8318 007e 7B68 ldr r3, [r7, #4] + 8319 0080 4022 movs r2, #64 + 8320 0082 1A66 str r2, [r3, #96] + 8321 .L415: +4376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Empty the FRLVL fifo */ +4379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL + 8322 .loc 1 4379 7 + 8323 0084 FFF7FEFF bl HAL_GetTick + 8324 0088 0346 mov r3, r0 + 8325 .loc 1 4379 7 is_stmt 0 discriminator 1 + 8326 008a 0093 str r3, [sp] + 8327 008c 6423 movs r3, #100 + 8328 008e 0022 movs r2, #0 + 8329 0090 4FF4C061 mov r1, #1536 + 8330 0094 7868 ldr r0, [r7, #4] + 8331 0096 FFF7FEFF bl SPI_WaitFifoStateUntilTimeout + 8332 009a 0346 mov r3, r0 + 8333 .loc 1 4379 6 is_stmt 1 discriminator 2 + 8334 009c 002B cmp r3, #0 + 8335 009e 02D0 beq .L416 +4380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + 8336 .loc 1 4381 21 + 8337 00a0 7B68 ldr r3, [r7, #4] + 8338 00a2 4022 movs r2, #64 + 8339 00a4 1A66 str r2, [r3, #96] + 8340 .L416: + ARM GAS /tmp/ccs34gJO.s page 223 + + +4382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_ABORT; + 8341 .loc 1 4384 15 + 8342 00a6 7B68 ldr r3, [r7, #4] + 8343 00a8 0722 movs r2, #7 + 8344 00aa 83F85D20 strb r2, [r3, #93] +4385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 8345 .loc 1 4385 1 + 8346 00ae 00BF nop + 8347 00b0 1037 adds r7, r7, #16 + 8348 .cfi_def_cfa_offset 8 + 8349 00b2 BD46 mov sp, r7 + 8350 .cfi_def_cfa_register 13 + 8351 @ sp needed + 8352 00b4 80BD pop {r7, pc} + 8353 .L418: + 8354 00b6 00BF .align 2 + 8355 .L417: + 8356 00b8 00000000 .word SystemCoreClock + 8357 00bc F1197605 .word 91625969 + 8358 .cfi_endproc + 8359 .LFE184: + 8361 .section .text.SPI_AbortTx_ISR,"ax",%progbits + 8362 .align 1 + 8363 .syntax unified + 8364 .thumb + 8365 .thumb_func + 8367 SPI_AbortTx_ISR: + 8368 .LFB185: +4386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /** +4388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @brief Handle abort a Tx or Rx/Tx transaction. +4389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains +4390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * the configuration information for SPI module. +4391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** * @retval None +4392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** */ +4393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) +4394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { + 8369 .loc 1 4394 1 + 8370 .cfi_startproc + 8371 @ args = 0, pretend = 0, frame = 16 + 8372 @ frame_needed = 1, uses_anonymous_args = 0 + 8373 0000 80B5 push {r7, lr} + 8374 .cfi_def_cfa_offset 8 + 8375 .cfi_offset 7, -8 + 8376 .cfi_offset 14, -4 + 8377 0002 86B0 sub sp, sp, #24 + 8378 .cfi_def_cfa_offset 32 + 8379 0004 02AF add r7, sp, #8 + 8380 .cfi_def_cfa 7, 24 + 8381 0006 7860 str r0, [r7, #4] +4395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __IO uint32_t count; +4396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + 8382 .loc 1 4397 56 + 8383 0008 4C4B ldr r3, .L430 + ARM GAS /tmp/ccs34gJO.s page 224 + + + 8384 000a 1B68 ldr r3, [r3] + 8385 000c 4C4A ldr r2, .L430+4 + 8386 000e A2FB0323 umull r2, r3, r2, r3 + 8387 0012 5B0A lsrs r3, r3, #9 + 8388 .loc 1 4397 31 + 8389 0014 6422 movs r2, #100 + 8390 0016 02FB03F3 mul r3, r2, r3 + 8391 .loc 1 4397 9 + 8392 001a FB60 str r3, [r7, #12] +4398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable TXEIE interrupt */ +4400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE)); + 8393 .loc 1 4400 3 + 8394 001c 7B68 ldr r3, [r7, #4] + 8395 001e 1B68 ldr r3, [r3] + 8396 0020 5A68 ldr r2, [r3, #4] + 8397 0022 7B68 ldr r3, [r7, #4] + 8398 0024 1B68 ldr r3, [r3] + 8399 0026 22F08002 bic r2, r2, #128 + 8400 002a 5A60 str r2, [r3, #4] + 8401 .L422: +4401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check TXEIE is disabled */ +4403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** do +4404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (count == 0U) + 8402 .loc 1 4405 15 + 8403 002c FB68 ldr r3, [r7, #12] + 8404 .loc 1 4405 8 + 8405 002e 002B cmp r3, #0 + 8406 0030 06D1 bne .L420 +4406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + 8407 .loc 1 4407 7 + 8408 0032 7B68 ldr r3, [r7, #4] + 8409 0034 1B6E ldr r3, [r3, #96] + 8410 0036 43F04002 orr r2, r3, #64 + 8411 003a 7B68 ldr r3, [r7, #4] + 8412 003c 1A66 str r2, [r3, #96] +4408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 8413 .loc 1 4408 7 + 8414 003e 09E0 b .L421 + 8415 .L420: +4409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** count--; + 8416 .loc 1 4410 10 + 8417 0040 FB68 ldr r3, [r7, #12] + 8418 0042 013B subs r3, r3, #1 + 8419 0044 FB60 str r3, [r7, #12] +4411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)); + 8420 .loc 1 4411 12 + 8421 0046 7B68 ldr r3, [r7, #4] + 8422 0048 1B68 ldr r3, [r3] + 8423 004a 5B68 ldr r3, [r3, #4] + 8424 004c 03F08003 and r3, r3, #128 + 8425 0050 802B cmp r3, #128 + 8426 0052 EBD0 beq .L422 + ARM GAS /tmp/ccs34gJO.s page 225 + + + 8427 .L421: +4412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + 8428 .loc 1 4413 7 + 8429 0054 FFF7FEFF bl HAL_GetTick + 8430 0058 0346 mov r3, r0 + 8431 .loc 1 4413 7 is_stmt 0 discriminator 1 + 8432 005a 1A46 mov r2, r3 + 8433 005c 6421 movs r1, #100 + 8434 005e 7868 ldr r0, [r7, #4] + 8435 0060 FFF7FEFF bl SPI_EndRxTxTransaction + 8436 0064 0346 mov r3, r0 + 8437 .loc 1 4413 6 is_stmt 1 discriminator 2 + 8438 0066 002B cmp r3, #0 + 8439 0068 02D0 beq .L423 +4414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + 8440 .loc 1 4415 21 + 8441 006a 7B68 ldr r3, [r7, #4] + 8442 006c 4022 movs r2, #64 + 8443 006e 1A66 str r2, [r3, #96] + 8444 .L423: +4416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable SPI Peripheral */ +4419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** __HAL_SPI_DISABLE(hspi); + 8445 .loc 1 4419 3 + 8446 0070 7B68 ldr r3, [r7, #4] + 8447 0072 1B68 ldr r3, [r3] + 8448 0074 1A68 ldr r2, [r3] + 8449 0076 7B68 ldr r3, [r7, #4] + 8450 0078 1B68 ldr r3, [r3] + 8451 007a 22F04002 bic r2, r2, #64 + 8452 007e 1A60 str r2, [r3] +4420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Empty the FRLVL fifo */ +4422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL + 8453 .loc 1 4422 7 + 8454 0080 FFF7FEFF bl HAL_GetTick + 8455 0084 0346 mov r3, r0 + 8456 .loc 1 4422 7 is_stmt 0 discriminator 1 + 8457 0086 0093 str r3, [sp] + 8458 0088 6423 movs r3, #100 + 8459 008a 0022 movs r2, #0 + 8460 008c 4FF4C061 mov r1, #1536 + 8461 0090 7868 ldr r0, [r7, #4] + 8462 0092 FFF7FEFF bl SPI_WaitFifoStateUntilTimeout + 8463 0096 0346 mov r3, r0 + 8464 .loc 1 4422 6 is_stmt 1 discriminator 2 + 8465 0098 002B cmp r3, #0 + 8466 009a 02D0 beq .L424 +4423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + 8467 .loc 1 4424 21 + 8468 009c 7B68 ldr r3, [r7, #4] + 8469 009e 4022 movs r2, #64 + 8470 00a0 1A66 str r2, [r3, #96] + ARM GAS /tmp/ccs34gJO.s page 226 + + + 8471 .L424: +4425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check case of Full-Duplex Mode and disable directly RXNEIE interrupt */ +4428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) + 8472 .loc 1 4428 7 + 8473 00a2 7B68 ldr r3, [r7, #4] + 8474 00a4 1B68 ldr r3, [r3] + 8475 00a6 5B68 ldr r3, [r3, #4] + 8476 00a8 03F04003 and r3, r3, #64 + 8477 .loc 1 4428 6 + 8478 00ac 402B cmp r3, #64 + 8479 00ae 3CD1 bne .L425 +4429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Disable RXNEIE interrupt */ +4431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE)); + 8480 .loc 1 4431 5 + 8481 00b0 7B68 ldr r3, [r7, #4] + 8482 00b2 1B68 ldr r3, [r3] + 8483 00b4 5A68 ldr r2, [r3, #4] + 8484 00b6 7B68 ldr r3, [r7, #4] + 8485 00b8 1B68 ldr r3, [r3] + 8486 00ba 22F04002 bic r2, r2, #64 + 8487 00be 5A60 str r2, [r3, #4] + 8488 .L428: +4432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Check RXNEIE is disabled */ +4434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** do +4435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (count == 0U) + 8489 .loc 1 4436 17 + 8490 00c0 FB68 ldr r3, [r7, #12] + 8491 .loc 1 4436 10 + 8492 00c2 002B cmp r3, #0 + 8493 00c4 06D1 bne .L426 +4437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + 8494 .loc 1 4438 9 + 8495 00c6 7B68 ldr r3, [r7, #4] + 8496 00c8 1B6E ldr r3, [r3, #96] + 8497 00ca 43F04002 orr r2, r3, #64 + 8498 00ce 7B68 ldr r3, [r7, #4] + 8499 00d0 1A66 str r2, [r3, #96] +4439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** break; + 8500 .loc 1 4439 9 + 8501 00d2 09E0 b .L427 + 8502 .L426: +4440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** count--; + 8503 .loc 1 4441 12 + 8504 00d4 FB68 ldr r3, [r7, #12] + 8505 00d6 013B subs r3, r3, #1 + 8506 00d8 FB60 str r3, [r7, #12] +4442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)); + 8507 .loc 1 4442 14 + 8508 00da 7B68 ldr r3, [r7, #4] + 8509 00dc 1B68 ldr r3, [r3] + ARM GAS /tmp/ccs34gJO.s page 227 + + + 8510 00de 5B68 ldr r3, [r3, #4] + 8511 00e0 03F04003 and r3, r3, #64 + 8512 00e4 402B cmp r3, #64 + 8513 00e6 EBD0 beq .L428 + 8514 .L427: +4443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Control the BSY flag */ +4445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick() + 8515 .loc 1 4445 9 + 8516 00e8 FFF7FEFF bl HAL_GetTick + 8517 00ec 0346 mov r3, r0 + 8518 .loc 1 4445 9 is_stmt 0 discriminator 1 + 8519 00ee 0093 str r3, [sp] + 8520 00f0 6423 movs r3, #100 + 8521 00f2 0022 movs r2, #0 + 8522 00f4 8021 movs r1, #128 + 8523 00f6 7868 ldr r0, [r7, #4] + 8524 00f8 FFF7FEFF bl SPI_WaitFlagStateUntilTimeout + 8525 00fc 0346 mov r3, r0 + 8526 .loc 1 4445 8 is_stmt 1 discriminator 2 + 8527 00fe 002B cmp r3, #0 + 8528 0100 02D0 beq .L429 +4446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + 8529 .loc 1 4447 23 + 8530 0102 7B68 ldr r3, [r7, #4] + 8531 0104 4022 movs r2, #64 + 8532 0106 1A66 str r2, [r3, #96] + 8533 .L429: +4448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** +4450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** /* Empty the FRLVL fifo */ +4451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, H + 8534 .loc 1 4451 9 + 8535 0108 FFF7FEFF bl HAL_GetTick + 8536 010c 0346 mov r3, r0 + 8537 .loc 1 4451 9 is_stmt 0 discriminator 1 + 8538 010e 0093 str r3, [sp] + 8539 0110 6423 movs r3, #100 + 8540 0112 0022 movs r2, #0 + 8541 0114 4FF4C061 mov r1, #1536 + 8542 0118 7868 ldr r0, [r7, #4] + 8543 011a FFF7FEFF bl SPI_WaitFifoStateUntilTimeout + 8544 011e 0346 mov r3, r0 + 8545 .loc 1 4451 8 is_stmt 1 discriminator 2 + 8546 0120 002B cmp r3, #0 + 8547 0122 02D0 beq .L425 +4452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** { +4453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + 8548 .loc 1 4453 23 + 8549 0124 7B68 ldr r3, [r7, #4] + 8550 0126 4022 movs r2, #64 + 8551 0128 1A66 str r2, [r3, #96] + 8552 .L425: +4454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } +4456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** hspi->State = HAL_SPI_STATE_ABORT; + ARM GAS /tmp/ccs34gJO.s page 228 + + + 8553 .loc 1 4456 15 + 8554 012a 7B68 ldr r3, [r7, #4] + 8555 012c 0722 movs r2, #7 + 8556 012e 83F85D20 strb r2, [r3, #93] +4457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c **** } + 8557 .loc 1 4457 1 + 8558 0132 00BF nop + 8559 0134 1037 adds r7, r7, #16 + 8560 .cfi_def_cfa_offset 8 + 8561 0136 BD46 mov sp, r7 + 8562 .cfi_def_cfa_register 13 + 8563 @ sp needed + 8564 0138 80BD pop {r7, pc} + 8565 .L431: + 8566 013a 00BF .align 2 + 8567 .L430: + 8568 013c 00000000 .word SystemCoreClock + 8569 0140 F1197605 .word 91625969 + 8570 .cfi_endproc + 8571 .LFE185: + 8573 .text + 8574 .Letext0: + 8575 .file 2 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 8576 .file 3 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 8577 .file 4 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + 8578 .file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h" + 8579 .file 6 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h" + 8580 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h" + 8581 .file 8 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h" + 8582 .file 9 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h" + 8583 .file 10 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h" + ARM GAS /tmp/ccs34gJO.s page 229 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f3xx_hal_spi.c + /tmp/ccs34gJO.s:21 .text.HAL_SPI_Init:00000000 $t + /tmp/ccs34gJO.s:27 .text.HAL_SPI_Init:00000000 HAL_SPI_Init + /tmp/ccs34gJO.s:306 .text.HAL_SPI_MspInit:00000000 HAL_SPI_MspInit + /tmp/ccs34gJO.s:229 .text.HAL_SPI_DeInit:00000000 $t + /tmp/ccs34gJO.s:235 .text.HAL_SPI_DeInit:00000000 HAL_SPI_DeInit + /tmp/ccs34gJO.s:342 .text.HAL_SPI_MspDeInit:00000000 HAL_SPI_MspDeInit + /tmp/ccs34gJO.s:300 .text.HAL_SPI_MspInit:00000000 $t + /tmp/ccs34gJO.s:336 .text.HAL_SPI_MspDeInit:00000000 $t + /tmp/ccs34gJO.s:372 .text.HAL_SPI_Transmit:00000000 $t + /tmp/ccs34gJO.s:378 .text.HAL_SPI_Transmit:00000000 HAL_SPI_Transmit + /tmp/ccs34gJO.s:7852 .text.SPI_EndRxTxTransaction:00000000 SPI_EndRxTxTransaction + /tmp/ccs34gJO.s:909 .text.HAL_SPI_Receive:00000000 $t + /tmp/ccs34gJO.s:915 .text.HAL_SPI_Receive:00000000 HAL_SPI_Receive + /tmp/ccs34gJO.s:1335 .text.HAL_SPI_TransmitReceive:00000000 HAL_SPI_TransmitReceive + /tmp/ccs34gJO.s:7724 .text.SPI_EndRxTransaction:00000000 SPI_EndRxTransaction + /tmp/ccs34gJO.s:1329 .text.HAL_SPI_TransmitReceive:00000000 $t + /tmp/ccs34gJO.s:2075 .text.HAL_SPI_Transmit_IT:00000000 $t + /tmp/ccs34gJO.s:2081 .text.HAL_SPI_Transmit_IT:00000000 HAL_SPI_Transmit_IT + /tmp/ccs34gJO.s:2272 .text.HAL_SPI_Transmit_IT:00000114 $d + /tmp/ccs34gJO.s:7250 .text.SPI_TxISR_16BIT:00000000 SPI_TxISR_16BIT + /tmp/ccs34gJO.s:7179 .text.SPI_TxISR_8BIT:00000000 SPI_TxISR_8BIT + /tmp/ccs34gJO.s:2278 .text.HAL_SPI_Receive_IT:00000000 $t + /tmp/ccs34gJO.s:2284 .text.HAL_SPI_Receive_IT:00000000 HAL_SPI_Receive_IT + /tmp/ccs34gJO.s:2525 .text.HAL_SPI_TransmitReceive_IT:00000000 HAL_SPI_TransmitReceive_IT + /tmp/ccs34gJO.s:2513 .text.HAL_SPI_Receive_IT:00000158 $d + /tmp/ccs34gJO.s:7108 .text.SPI_RxISR_16BIT:00000000 SPI_RxISR_16BIT + /tmp/ccs34gJO.s:7036 .text.SPI_RxISR_8BIT:00000000 SPI_RxISR_8BIT + /tmp/ccs34gJO.s:2519 .text.HAL_SPI_TransmitReceive_IT:00000000 $t + /tmp/ccs34gJO.s:2759 .text.HAL_SPI_TransmitReceive_IT:00000150 $d + /tmp/ccs34gJO.s:6866 .text.SPI_2linesRxISR_16BIT:00000000 SPI_2linesRxISR_16BIT + /tmp/ccs34gJO.s:6952 .text.SPI_2linesTxISR_16BIT:00000000 SPI_2linesTxISR_16BIT + /tmp/ccs34gJO.s:6604 .text.SPI_2linesRxISR_8BIT:00000000 SPI_2linesRxISR_8BIT + /tmp/ccs34gJO.s:6744 .text.SPI_2linesTxISR_8BIT:00000000 SPI_2linesTxISR_8BIT + /tmp/ccs34gJO.s:2767 .text.HAL_SPI_Transmit_DMA:00000000 $t + /tmp/ccs34gJO.s:2773 .text.HAL_SPI_Transmit_DMA:00000000 HAL_SPI_Transmit_DMA + /tmp/ccs34gJO.s:3085 .text.HAL_SPI_Transmit_DMA:000001d4 $d + /tmp/ccs34gJO.s:6055 .text.SPI_DMAHalfTransmitCplt:00000000 SPI_DMAHalfTransmitCplt + /tmp/ccs34gJO.s:5697 .text.SPI_DMATransmitCplt:00000000 SPI_DMATransmitCplt + /tmp/ccs34gJO.s:6172 .text.SPI_DMAError:00000000 SPI_DMAError + /tmp/ccs34gJO.s:3092 .text.HAL_SPI_Receive_DMA:00000000 $t + /tmp/ccs34gJO.s:3098 .text.HAL_SPI_Receive_DMA:00000000 HAL_SPI_Receive_DMA + /tmp/ccs34gJO.s:3490 .text.HAL_SPI_TransmitReceive_DMA:00000000 HAL_SPI_TransmitReceive_DMA + /tmp/ccs34gJO.s:3477 .text.HAL_SPI_Receive_DMA:00000250 $d + /tmp/ccs34gJO.s:6094 .text.SPI_DMAHalfReceiveCplt:00000000 SPI_DMAHalfReceiveCplt + /tmp/ccs34gJO.s:5822 .text.SPI_DMAReceiveCplt:00000000 SPI_DMAReceiveCplt + /tmp/ccs34gJO.s:3484 .text.HAL_SPI_TransmitReceive_DMA:00000000 $t + /tmp/ccs34gJO.s:4004 .text.HAL_SPI_TransmitReceive_DMA:00000310 $d + /tmp/ccs34gJO.s:6133 .text.SPI_DMAHalfTransmitReceiveCplt:00000000 SPI_DMAHalfTransmitReceiveCplt + /tmp/ccs34gJO.s:5947 .text.SPI_DMATransmitReceiveCplt:00000000 SPI_DMATransmitReceiveCplt + /tmp/ccs34gJO.s:4013 .text.HAL_SPI_Abort:00000000 $t + /tmp/ccs34gJO.s:4019 .text.HAL_SPI_Abort:00000000 HAL_SPI_Abort + /tmp/ccs34gJO.s:7510 .text.SPI_WaitFifoStateUntilTimeout:00000000 SPI_WaitFifoStateUntilTimeout + /tmp/ccs34gJO.s:7319 .text.SPI_WaitFlagStateUntilTimeout:00000000 SPI_WaitFlagStateUntilTimeout + /tmp/ccs34gJO.s:4385 .text.HAL_SPI_Abort:00000230 $d + /tmp/ccs34gJO.s:8367 .text.SPI_AbortTx_ISR:00000000 SPI_AbortTx_ISR + ARM GAS /tmp/ccs34gJO.s page 230 + + + /tmp/ccs34gJO.s:8234 .text.SPI_AbortRx_ISR:00000000 SPI_AbortRx_ISR + /tmp/ccs34gJO.s:4393 .text.HAL_SPI_Abort_IT:00000000 $t + /tmp/ccs34gJO.s:4399 .text.HAL_SPI_Abort_IT:00000000 HAL_SPI_Abort_IT + /tmp/ccs34gJO.s:5583 .text.HAL_SPI_AbortCpltCallback:00000000 HAL_SPI_AbortCpltCallback + /tmp/ccs34gJO.s:4737 .text.HAL_SPI_Abort_IT:000001dc $d + /tmp/ccs34gJO.s:6276 .text.SPI_DMATxAbortCallback:00000000 SPI_DMATxAbortCallback + /tmp/ccs34gJO.s:6439 .text.SPI_DMARxAbortCallback:00000000 SPI_DMARxAbortCallback + /tmp/ccs34gJO.s:4747 .text.HAL_SPI_DMAPause:00000000 $t + /tmp/ccs34gJO.s:4753 .text.HAL_SPI_DMAPause:00000000 HAL_SPI_DMAPause + /tmp/ccs34gJO.s:4812 .text.HAL_SPI_DMAResume:00000000 $t + /tmp/ccs34gJO.s:4818 .text.HAL_SPI_DMAResume:00000000 HAL_SPI_DMAResume + /tmp/ccs34gJO.s:4877 .text.HAL_SPI_DMAStop:00000000 $t + /tmp/ccs34gJO.s:4883 .text.HAL_SPI_DMAStop:00000000 HAL_SPI_DMAStop + /tmp/ccs34gJO.s:4977 .text.HAL_SPI_IRQHandler:00000000 $t + /tmp/ccs34gJO.s:4983 .text.HAL_SPI_IRQHandler:00000000 HAL_SPI_IRQHandler + /tmp/ccs34gJO.s:5547 .text.HAL_SPI_ErrorCallback:00000000 HAL_SPI_ErrorCallback + /tmp/ccs34gJO.s:5320 .text.HAL_SPI_IRQHandler:000001fc $d + /tmp/ccs34gJO.s:6229 .text.SPI_DMAAbortOnError:00000000 SPI_DMAAbortOnError + /tmp/ccs34gJO.s:5325 .text.HAL_SPI_TxCpltCallback:00000000 $t + /tmp/ccs34gJO.s:5331 .text.HAL_SPI_TxCpltCallback:00000000 HAL_SPI_TxCpltCallback + /tmp/ccs34gJO.s:5361 .text.HAL_SPI_RxCpltCallback:00000000 $t + /tmp/ccs34gJO.s:5367 .text.HAL_SPI_RxCpltCallback:00000000 HAL_SPI_RxCpltCallback + /tmp/ccs34gJO.s:5397 .text.HAL_SPI_TxRxCpltCallback:00000000 $t + /tmp/ccs34gJO.s:5403 .text.HAL_SPI_TxRxCpltCallback:00000000 HAL_SPI_TxRxCpltCallback + /tmp/ccs34gJO.s:5433 .text.HAL_SPI_TxHalfCpltCallback:00000000 $t + /tmp/ccs34gJO.s:5439 .text.HAL_SPI_TxHalfCpltCallback:00000000 HAL_SPI_TxHalfCpltCallback + /tmp/ccs34gJO.s:5469 .text.HAL_SPI_RxHalfCpltCallback:00000000 $t + /tmp/ccs34gJO.s:5475 .text.HAL_SPI_RxHalfCpltCallback:00000000 HAL_SPI_RxHalfCpltCallback + /tmp/ccs34gJO.s:5505 .text.HAL_SPI_TxRxHalfCpltCallback:00000000 $t + /tmp/ccs34gJO.s:5511 .text.HAL_SPI_TxRxHalfCpltCallback:00000000 HAL_SPI_TxRxHalfCpltCallback + /tmp/ccs34gJO.s:5541 .text.HAL_SPI_ErrorCallback:00000000 $t + /tmp/ccs34gJO.s:5577 .text.HAL_SPI_AbortCpltCallback:00000000 $t + /tmp/ccs34gJO.s:5613 .text.HAL_SPI_GetState:00000000 $t + /tmp/ccs34gJO.s:5619 .text.HAL_SPI_GetState:00000000 HAL_SPI_GetState + /tmp/ccs34gJO.s:5653 .text.HAL_SPI_GetError:00000000 $t + /tmp/ccs34gJO.s:5659 .text.HAL_SPI_GetError:00000000 HAL_SPI_GetError + /tmp/ccs34gJO.s:5692 .text.SPI_DMATransmitCplt:00000000 $t + /tmp/ccs34gJO.s:5817 .text.SPI_DMAReceiveCplt:00000000 $t + /tmp/ccs34gJO.s:5942 .text.SPI_DMATransmitReceiveCplt:00000000 $t + /tmp/ccs34gJO.s:6050 .text.SPI_DMAHalfTransmitCplt:00000000 $t + /tmp/ccs34gJO.s:6089 .text.SPI_DMAHalfReceiveCplt:00000000 $t + /tmp/ccs34gJO.s:6128 .text.SPI_DMAHalfTransmitReceiveCplt:00000000 $t + /tmp/ccs34gJO.s:6167 .text.SPI_DMAError:00000000 $t + /tmp/ccs34gJO.s:6224 .text.SPI_DMAAbortOnError:00000000 $t + /tmp/ccs34gJO.s:6271 .text.SPI_DMATxAbortCallback:00000000 $t + /tmp/ccs34gJO.s:6434 .text.SPI_DMARxAbortCallback:00000000 $t + /tmp/ccs34gJO.s:6599 .text.SPI_2linesRxISR_8BIT:00000000 $t + /tmp/ccs34gJO.s:7955 .text.SPI_CloseRxTx_ISR:00000000 SPI_CloseRxTx_ISR + /tmp/ccs34gJO.s:6739 .text.SPI_2linesTxISR_8BIT:00000000 $t + /tmp/ccs34gJO.s:6861 .text.SPI_2linesRxISR_16BIT:00000000 $t + /tmp/ccs34gJO.s:6947 .text.SPI_2linesTxISR_16BIT:00000000 $t + /tmp/ccs34gJO.s:7031 .text.SPI_RxISR_8BIT:00000000 $t + /tmp/ccs34gJO.s:8055 .text.SPI_CloseRx_ISR:00000000 SPI_CloseRx_ISR + /tmp/ccs34gJO.s:7103 .text.SPI_RxISR_16BIT:00000000 $t + /tmp/ccs34gJO.s:7174 .text.SPI_TxISR_8BIT:00000000 $t + /tmp/ccs34gJO.s:8134 .text.SPI_CloseTx_ISR:00000000 SPI_CloseTx_ISR + /tmp/ccs34gJO.s:7245 .text.SPI_TxISR_16BIT:00000000 $t + ARM GAS /tmp/ccs34gJO.s page 231 + + + /tmp/ccs34gJO.s:7314 .text.SPI_WaitFlagStateUntilTimeout:00000000 $t + /tmp/ccs34gJO.s:7500 .text.SPI_WaitFlagStateUntilTimeout:0000010c $d + /tmp/ccs34gJO.s:7505 .text.SPI_WaitFifoStateUntilTimeout:00000000 $t + /tmp/ccs34gJO.s:7714 .text.SPI_WaitFifoStateUntilTimeout:00000128 $d + /tmp/ccs34gJO.s:7719 .text.SPI_EndRxTransaction:00000000 $t + /tmp/ccs34gJO.s:7847 .text.SPI_EndRxTxTransaction:00000000 $t + /tmp/ccs34gJO.s:7950 .text.SPI_CloseRxTx_ISR:00000000 $t + /tmp/ccs34gJO.s:8050 .text.SPI_CloseRx_ISR:00000000 $t + /tmp/ccs34gJO.s:8129 .text.SPI_CloseTx_ISR:00000000 $t + /tmp/ccs34gJO.s:8229 .text.SPI_AbortRx_ISR:00000000 $t + /tmp/ccs34gJO.s:8356 .text.SPI_AbortRx_ISR:000000b8 $d + /tmp/ccs34gJO.s:8362 .text.SPI_AbortTx_ISR:00000000 $t + /tmp/ccs34gJO.s:8568 .text.SPI_AbortTx_ISR:0000013c $d + +UNDEFINED SYMBOLS +HAL_GetTick +HAL_DMA_Start_IT +HAL_DMA_Abort +SystemCoreClock +HAL_DMA_Abort_IT diff --git a/Software/build/stm32f3xx_hal_spi.o b/Software/build/stm32f3xx_hal_spi.o new file mode 100644 index 0000000..b714971 Binary files /dev/null and b/Software/build/stm32f3xx_hal_spi.o differ diff --git a/Software/build/stm32f3xx_hal_spi_ex.d b/Software/build/stm32f3xx_hal_spi_ex.d new file mode 100644 index 0000000..79dcc10 --- /dev/null +++ b/Software/build/stm32f3xx_hal_spi_ex.d @@ -0,0 +1,62 @@ +build/stm32f3xx_hal_spi_ex.o: \ + Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + Core/Inc/stm32f3xx_hal_conf.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h: diff --git a/Software/build/stm32f3xx_hal_spi_ex.lst b/Software/build/stm32f3xx_hal_spi_ex.lst new file mode 100644 index 0000000..1459582 --- /dev/null +++ b/Software/build/stm32f3xx_hal_spi_ex.lst @@ -0,0 +1,220 @@ +ARM GAS /tmp/cc65SCa1.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 6 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "stm32f3xx_hal_spi_ex.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c" + 20 .section .text.HAL_SPIEx_FlushRxFifo,"ax",%progbits + 21 .align 1 + 22 .global HAL_SPIEx_FlushRxFifo + 23 .syntax unified + 24 .thumb + 25 .thumb_func + 27 HAL_SPIEx_FlushRxFifo: + 28 .LFB130: + 1:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** /** + 2:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** ****************************************************************************** + 3:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * @file stm32f3xx_hal_spi_ex.c + 4:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * @author MCD Application Team + 5:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * @brief Extended SPI HAL module driver. + 6:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * SPI peripheral extended functionalities : + 8:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * + IO operation functions + 9:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * + 10:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** ****************************************************************************** + 11:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * @attention + 12:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * + 13:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * Copyright (c) 2016 STMicroelectronics. + 14:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * All rights reserved. + 15:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * + 16:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * This software is licensed under terms that can be found in the LICENSE file + 17:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * in the root directory of this software component. + 18:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 19:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * + 20:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** ****************************************************************************** + 21:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** */ + 22:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** + 23:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** /* Includes ------------------------------------------------------------------*/ + 24:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** #include "stm32f3xx_hal.h" + 25:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** + 26:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** /** @addtogroup STM32F3xx_HAL_Driver + 27:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * @{ + 28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** */ + 29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** + 30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** /** @defgroup SPIEx SPIEx + ARM GAS /tmp/cc65SCa1.s page 2 + + + 31:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * @brief SPI Extended HAL module driver + 32:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * @{ + 33:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** */ + 34:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** #ifdef HAL_SPI_MODULE_ENABLED + 35:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** + 36:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** /* Private typedef -----------------------------------------------------------*/ + 37:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** /* Private defines -----------------------------------------------------------*/ + 38:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** /** @defgroup SPIEx_Private_Constants SPIEx Private Constants + 39:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * @{ + 40:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** */ + 41:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** #define SPI_FIFO_SIZE 4UL + 42:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** /** + 43:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * @} + 44:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** */ + 45:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** + 46:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** /* Private macros ------------------------------------------------------------*/ + 47:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** /* Private variables ---------------------------------------------------------*/ + 48:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** /* Private function prototypes -----------------------------------------------*/ + 49:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** /* Exported functions --------------------------------------------------------*/ + 50:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** + 51:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** /** @defgroup SPIEx_Exported_Functions SPIEx Exported Functions + 52:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * @{ + 53:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** */ + 54:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** + 55:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** /** @defgroup SPIEx_Exported_Functions_Group1 IO operation functions + 56:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * @brief Data transfers functions + 57:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * + 58:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** @verbatim + 59:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** ============================================================================== + 60:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** ##### IO operation functions ##### + 61:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** =============================================================================== + 62:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** [..] + 63:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** This subsection provides a set of extended functions to manage the SPI + 64:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** data transfers. + 65:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** + 66:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** (#) Rx data flush function: + 67:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** (++) HAL_SPIEx_FlushRxFifo() + 68:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** + 69:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** @endverbatim + 70:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * @{ + 71:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** */ + 72:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** + 73:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** /** + 74:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * @brief Flush the RX fifo. + 75:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * @param hspi pointer to a SPI_HandleTypeDef structure that contains + 76:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * the configuration information for the specified SPI module. + 77:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** * @retval HAL status + 78:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** */ + 79:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi) + 80:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** { + 29 .loc 1 80 1 + 30 .cfi_startproc + 31 @ args = 0, pretend = 0, frame = 16 + 32 @ frame_needed = 1, uses_anonymous_args = 0 + 33 @ link register save eliminated. + 34 0000 80B4 push {r7} + 35 .cfi_def_cfa_offset 4 + ARM GAS /tmp/cc65SCa1.s page 3 + + + 36 .cfi_offset 7, -4 + 37 0002 85B0 sub sp, sp, #20 + 38 .cfi_def_cfa_offset 24 + 39 0004 00AF add r7, sp, #0 + 40 .cfi_def_cfa_register 7 + 41 0006 7860 str r0, [r7, #4] + 81:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** __IO uint32_t tmpreg; + 82:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** uint8_t count = 0U; + 42 .loc 1 82 12 + 43 0008 0023 movs r3, #0 + 44 000a FB73 strb r3, [r7, #15] + 83:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** while ((hspi->Instance->SR & SPI_FLAG_FRLVL) != SPI_FRLVL_EMPTY) + 45 .loc 1 83 9 + 46 000c 0CE0 b .L2 + 47 .L4: + 84:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** { + 85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** count++; + 48 .loc 1 85 10 + 49 000e FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 50 0010 0133 adds r3, r3, #1 + 51 0012 FB73 strb r3, [r7, #15] + 86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** tmpreg = hspi->Instance->DR; + 52 .loc 1 86 18 + 53 0014 7B68 ldr r3, [r7, #4] + 54 0016 1B68 ldr r3, [r3] + 55 .loc 1 86 28 + 56 0018 DB68 ldr r3, [r3, #12] + 57 .loc 1 86 12 + 58 001a BB60 str r3, [r7, #8] + 87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** UNUSED(tmpreg); /* To avoid GCC warning */ + 59 .loc 1 87 5 + 60 001c BB68 ldr r3, [r7, #8] + 88:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** if (count == SPI_FIFO_SIZE) + 61 .loc 1 88 8 + 62 001e FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 63 0020 042B cmp r3, #4 + 64 0022 01D1 bne .L2 + 89:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** { + 90:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** return HAL_TIMEOUT; + 65 .loc 1 90 14 + 66 0024 0323 movs r3, #3 + 67 0026 07E0 b .L3 + 68 .L2: + 83:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** { + 69 .loc 1 83 15 + 70 0028 7B68 ldr r3, [r7, #4] + 71 002a 1B68 ldr r3, [r3] + 83:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** { + 72 .loc 1 83 25 + 73 002c 9B68 ldr r3, [r3, #8] + 83:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** { + 74 .loc 1 83 30 + 75 002e 03F4C063 and r3, r3, #1536 + 83:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** { + 76 .loc 1 83 48 + 77 0032 002B cmp r3, #0 + 78 0034 EBD1 bne .L4 + ARM GAS /tmp/cc65SCa1.s page 4 + + + 91:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** } + 92:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** } + 93:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** return HAL_OK; + 79 .loc 1 93 10 + 80 0036 0023 movs r3, #0 + 81 .L3: + 94:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c **** } + 82 .loc 1 94 1 + 83 0038 1846 mov r0, r3 + 84 003a 1437 adds r7, r7, #20 + 85 .cfi_def_cfa_offset 4 + 86 003c BD46 mov sp, r7 + 87 .cfi_def_cfa_register 13 + 88 @ sp needed + 89 003e 5DF8047B ldr r7, [sp], #4 + 90 .cfi_restore 7 + 91 .cfi_def_cfa_offset 0 + 92 0042 7047 bx lr + 93 .cfi_endproc + 94 .LFE130: + 96 .text + 97 .Letext0: + 98 .file 2 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 99 .file 3 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 100 .file 4 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + 101 .file 5 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h" + 102 .file 6 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h" + 103 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h" + ARM GAS /tmp/cc65SCa1.s page 5 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f3xx_hal_spi_ex.c + /tmp/cc65SCa1.s:21 .text.HAL_SPIEx_FlushRxFifo:00000000 $t + /tmp/cc65SCa1.s:27 .text.HAL_SPIEx_FlushRxFifo:00000000 HAL_SPIEx_FlushRxFifo + +NO UNDEFINED SYMBOLS diff --git a/Software/build/stm32f3xx_hal_spi_ex.o b/Software/build/stm32f3xx_hal_spi_ex.o new file mode 100644 index 0000000..1f7d378 Binary files /dev/null and b/Software/build/stm32f3xx_hal_spi_ex.o differ diff --git a/Software/build/stm32f3xx_hal_tim.d b/Software/build/stm32f3xx_hal_tim.d new file mode 100644 index 0000000..62ea12e --- /dev/null +++ b/Software/build/stm32f3xx_hal_tim.d @@ -0,0 +1,62 @@ +build/stm32f3xx_hal_tim.o: \ + Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + Core/Inc/stm32f3xx_hal_conf.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h: diff --git a/Software/build/stm32f3xx_hal_tim.lst b/Software/build/stm32f3xx_hal_tim.lst new file mode 100644 index 0000000..7d32476 --- /dev/null +++ b/Software/build/stm32f3xx_hal_tim.lst @@ -0,0 +1,28276 @@ +ARM GAS /tmp/ccl4b9YO.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 6 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "stm32f3xx_hal_tim.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c" + 20 .section .text.HAL_TIM_Base_Init,"ax",%progbits + 21 .align 1 + 22 .global HAL_TIM_Base_Init + 23 .syntax unified + 24 .thumb + 25 .thumb_func + 27 HAL_TIM_Base_Init: + 28 .LFB130: + 1:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** + 2:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** ****************************************************************************** + 3:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @file stm32f3xx_hal_tim.c + 4:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @author MCD Application Team + 5:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief TIM HAL module driver. + 6:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * functionalities of the Timer (TIM) peripheral: + 8:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * + TIM Time Base Initialization + 9:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * + TIM Time Base Start + 10:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * + TIM Time Base Start Interruption + 11:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * + TIM Time Base Start DMA + 12:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * + TIM Output Compare/PWM Initialization + 13:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * + TIM Output Compare/PWM Channel Configuration + 14:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * + TIM Output Compare/PWM Start + 15:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * + TIM Output Compare/PWM Start Interruption + 16:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * + TIM Output Compare/PWM Start DMA + 17:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * + TIM Input Capture Initialization + 18:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * + TIM Input Capture Channel Configuration + 19:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * + TIM Input Capture Start + 20:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * + TIM Input Capture Start Interruption + 21:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * + TIM Input Capture Start DMA + 22:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * + TIM One Pulse Initialization + 23:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * + TIM One Pulse Channel Configuration + 24:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * + TIM One Pulse Start + 25:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * + TIM Encoder Interface Initialization + 26:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * + TIM Encoder Interface Start + 27:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * + TIM Encoder Interface Start Interruption + 28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * + TIM Encoder Interface Start DMA + 29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * + Commutation Event configuration with Interruption and DMA + 30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * + TIM OCRef clear configuration + ARM GAS /tmp/ccl4b9YO.s page 2 + + + 31:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * + TIM External Clock configuration + 32:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** ****************************************************************************** + 33:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @attention + 34:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * + 35:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * Copyright (c) 2016 STMicroelectronics. + 36:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * All rights reserved. + 37:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * + 38:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This software is licensed under terms that can be found in the LICENSE file + 39:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * in the root directory of this software component. + 40:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 41:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * + 42:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** ****************************************************************************** + 43:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** @verbatim + 44:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** ============================================================================== + 45:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** ##### TIMER Generic features ##### + 46:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** ============================================================================== + 47:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** [..] The Timer features include: + 48:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (#) 16-bit up, down, up/down auto-reload counter. + 49:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (#) 16-bit programmable prescaler allowing dividing (also on the fly) the + 50:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** counter clock frequency either by any factor between 1 and 65536. + 51:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (#) Up to 4 independent channels for: + 52:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (++) Input Capture + 53:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (++) Output Compare + 54:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (++) PWM generation (Edge and Center-aligned Mode) + 55:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (++) One-pulse mode output + 56:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (#) Synchronization circuit to control the timer with external signals and to interconnect + 57:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** several timers together. + 58:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (#) Supports incremental encoder for positioning purposes + 59:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 60:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** ##### How to use this driver ##### + 61:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** ============================================================================== + 62:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** [..] + 63:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (#) Initialize the TIM low level resources by implementing the following functions + 64:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** depending on the selected feature: + 65:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (++) Time Base : HAL_TIM_Base_MspInit() + 66:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (++) Input Capture : HAL_TIM_IC_MspInit() + 67:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (++) Output Compare : HAL_TIM_OC_MspInit() + 68:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (++) PWM generation : HAL_TIM_PWM_MspInit() + 69:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit() + 70:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (++) Encoder mode output : HAL_TIM_Encoder_MspInit() + 71:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 72:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (#) Initialize the TIM low level resources : + 73:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); + 74:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (##) TIM pins configuration + 75:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+++) Enable the clock for the TIM GPIOs using the following function: + 76:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_RCC_GPIOx_CLK_ENABLE(); + 77:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + 78:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 79:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (#) The external Clock can be configured, if needed (the default clock is the + 80:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** internal clock from the APBx), using the following function: + 81:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_ConfigClockSource, the clock configuration should be done before + 82:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** any start function. + 83:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 84:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (#) Configure the TIM in the desired functioning mode using one of the + 85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** Initialization function of this driver: + 86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base + 87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an + ARM GAS /tmp/ccl4b9YO.s page 3 + + + 88:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** Output Compare signal. + 89:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a + 90:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** PWM signal. + 91:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an + 92:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** external signal. + 93:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer + 94:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** in One Pulse Mode. + 95:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. + 96:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 97:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (#) Activate the TIM peripheral using one of the start functions depending from the feature us + 98:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT() + 99:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT() + 100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT() + 101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT + 102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT() + 103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM + 104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (#) The DMA Burst is managed with the two following functions: + 106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_DMABurst_WriteStart() + 107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_DMABurst_ReadStart() + 108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** *** Callback registration *** + 110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** ============================================= + 111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** [..] + 113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1 + 114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** allows the user to configure dynamically the driver callbacks. + 115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** [..] + 117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** Use Function HAL_TIM_RegisterCallback() to register a callback. + 118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle, + 119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** the Callback ID and a pointer to the user callback function. + 120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** [..] + 122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default + 123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** weak function. + 124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle, + 125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** and the Callback ID. + 126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** [..] + 128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** These functions allow to register/unregister following callbacks: + 129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Base_MspInitCallback : TIM Base Msp Init Callback. + 130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback. + 131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) IC_MspInitCallback : TIM IC Msp Init Callback. + 132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback. + 133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) OC_MspInitCallback : TIM OC Msp Init Callback. + 134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback. + 135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) PWM_MspInitCallback : TIM PWM Msp Init Callback. + 136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback. + 137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback. + 138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback. + 139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback. + 140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback. + 141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback. + 142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback. + 143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) PeriodElapsedCallback : TIM Period Elapsed Callback. + 144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback. + ARM GAS /tmp/ccl4b9YO.s page 4 + + + 145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) TriggerCallback : TIM Trigger Callback. + 146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback. + 147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) IC_CaptureCallback : TIM Input Capture Callback. + 148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback. + 149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback. + 150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback. + 151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback. + 152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) ErrorCallback : TIM Error Callback. + 153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) CommutationCallback : TIM Commutation Callback. + 154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback. + 155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) BreakCallback : TIM Break Callback. + 156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Break2Callback : TIM Break2 Callback (when supported). + 157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** [..] + 159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** By default, after the Init and when the state is HAL_TIM_STATE_RESET + 160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** all interrupt callbacks are set to the corresponding weak functions: + 161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback(). + 162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** [..] + 164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** Exception done for MspInit and MspDeInit functions that are reset to the legacy weak + 165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** functionalities in the Init / DeInit only when these callbacks are null + 166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit + 167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** keep and use the user MspInit / MspDeInit callbacks(registered beforehand) + 168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** [..] + 170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only. + 171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** Exception done MspInit / MspDeInit that can be registered / unregistered + 172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state, + 173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit. + 174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** In that case first register the MspInit/MspDeInit user callbacks + 175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** using HAL_TIM_RegisterCallback() before calling DeInit or Init function. + 176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** [..] + 178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or + 179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** not defined, the callback registration feature is not available and all callbacks + 180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** are set to the corresponding weak functions. + 181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** @endverbatim + 183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** ****************************************************************************** + 184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ + 185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Includes ------------------------------------------------------------------*/ + 187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #include "stm32f3xx_hal.h" + 188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** @addtogroup STM32F3xx_HAL_Driver + 190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @{ + 191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ + 192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** @defgroup TIM TIM + 194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief TIM HAL module driver + 195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @{ + 196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ + 197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #ifdef HAL_TIM_MODULE_ENABLED + 199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Private typedef -----------------------------------------------------------*/ + 201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Private define ------------------------------------------------------------*/ + ARM GAS /tmp/ccl4b9YO.s page 5 + + + 202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Private macros ------------------------------------------------------------*/ + 203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Private variables ---------------------------------------------------------*/ + 204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Private function prototypes -----------------------------------------------*/ + 205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** @addtogroup TIM_Private_Functions + 206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @{ + 207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ + 208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); + 209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); + 210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); + 211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if defined(TIM_CCER_CC5E) + 212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); + 213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* TIM_CCER_CC5E */ + 214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if defined(TIM_CCER_CC6E) + 215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); + 216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* TIM_CCER_CC6E */ + 217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFil + 218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + 219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t TIM_ICFilter); + 220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFil + 221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + 222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t TIM_ICFilter); + 223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + 224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t TIM_ICFilter); + 225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource); + 226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); + 227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma); + 228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); + 229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); + 230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma); + 231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, + 232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** const TIM_SlaveConfigTypeDef *sSlaveConfig); + 233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** + 234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @} + 235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ + 236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Exported functions --------------------------------------------------------*/ + 237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** @defgroup TIM_Exported_Functions TIM Exported Functions + 239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @{ + 240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ + 241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions + 243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Time Base functions + 244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * + 245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** @verbatim + 246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** ============================================================================== + 247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** ##### Time Base functions ##### + 248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** ============================================================================== + 249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** [..] + 250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** This section provides functions allowing to: + 251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Initialize and configure the TIM base. + 252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) De-initialize the TIM base. + 253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Start the Time Base. + 254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Stop the Time Base. + 255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Start the Time Base and enable interrupt. + 256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Stop the Time Base and disable interrupt. + 257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Start the Time Base and enable DMA transfer. + 258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Stop the Time Base and disable DMA transfer. + ARM GAS /tmp/ccl4b9YO.s page 6 + + + 259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** @endverbatim + 261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @{ + 262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ + 263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** + 264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Initializes the TIM Time base Unit according to the specified + 265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * parameters in the TIM_HandleTypeDef and initialize the associated handle. + 266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + 267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * requires a timer reset to avoid unexpected direction + 268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * due to DIR bit readonly in center aligned mode. + 269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() + 270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM Base handle + 271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status + 272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ + 273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) + 274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 29 .loc 1 274 1 + 30 .cfi_startproc + 31 @ args = 0, pretend = 0, frame = 8 + 32 @ frame_needed = 1, uses_anonymous_args = 0 + 33 0000 80B5 push {r7, lr} + 34 .cfi_def_cfa_offset 8 + 35 .cfi_offset 7, -8 + 36 .cfi_offset 14, -4 + 37 0002 82B0 sub sp, sp, #8 + 38 .cfi_def_cfa_offset 16 + 39 0004 00AF add r7, sp, #0 + 40 .cfi_def_cfa_register 7 + 41 0006 7860 str r0, [r7, #4] + 275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the TIM handle allocation */ + 276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (htim == NULL) + 42 .loc 1 276 6 + 43 0008 7B68 ldr r3, [r7, #4] + 44 000a 002B cmp r3, #0 + 45 000c 01D1 bne .L2 + 277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 46 .loc 1 278 12 + 47 000e 0123 movs r3, #1 + 48 0010 49E0 b .L3 + 49 .L2: + 279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ + 282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_INSTANCE(htim->Instance)); + 283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + 284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + 285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + 286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + 287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (htim->State == HAL_TIM_STATE_RESET) + 50 .loc 1 288 11 + 51 0012 7B68 ldr r3, [r7, #4] + 52 0014 93F83D30 ldrb r3, [r3, #61] + 53 0018 DBB2 uxtb r3, r3 + 54 .loc 1 288 6 + 55 001a 002B cmp r3, #0 + ARM GAS /tmp/ccl4b9YO.s page 7 + + + 56 001c 06D1 bne .L4 + 289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Allocate lock resource and initialize it */ + 291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Lock = HAL_UNLOCKED; + 57 .loc 1 291 16 + 58 001e 7B68 ldr r3, [r7, #4] + 59 0020 0022 movs r2, #0 + 60 0022 83F83C20 strb r2, [r3, #60] + 292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + 294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Reset interrupt callbacks to legacy weak callbacks */ + 295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_ResetCallback(htim); + 296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (htim->Base_MspInitCallback == NULL) + 298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; + 300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Init the low level hardware : GPIO, CLOCK, NVIC */ + 302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Base_MspInitCallback(htim); + 303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #else + 304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Init the low level hardware : GPIO, CLOCK, NVIC */ + 305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_Base_MspInit(htim); + 61 .loc 1 305 5 + 62 0026 7868 ldr r0, [r7, #4] + 63 0028 FFF7FEFF bl HAL_TIM_Base_MspInit + 64 .L4: + 306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the TIM state */ + 310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; + 65 .loc 1 310 15 + 66 002c 7B68 ldr r3, [r7, #4] + 67 002e 0222 movs r2, #2 + 68 0030 83F83D20 strb r2, [r3, #61] + 311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the Time Base configuration */ + 313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_Base_SetConfig(htim->Instance, &htim->Init); + 69 .loc 1 313 3 + 70 0034 7B68 ldr r3, [r7, #4] + 71 0036 1A68 ldr r2, [r3] + 72 .loc 1 313 38 + 73 0038 7B68 ldr r3, [r7, #4] + 74 003a 0433 adds r3, r3, #4 + 75 .loc 1 313 3 + 76 003c 1946 mov r1, r3 + 77 003e 1046 mov r0, r2 + 78 0040 FFF7FEFF bl TIM_Base_SetConfig + 314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Initialize the DMA burst operation state */ + 316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + 79 .loc 1 316 23 + 80 0044 7B68 ldr r3, [r7, #4] + 81 0046 0122 movs r2, #1 + 82 0048 83F84820 strb r2, [r3, #72] + 317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Initialize the TIM channels state */ + ARM GAS /tmp/ccl4b9YO.s page 8 + + + 319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 83 .loc 1 319 3 + 84 004c 7B68 ldr r3, [r7, #4] + 85 004e 0122 movs r2, #1 + 86 0050 83F83E20 strb r2, [r3, #62] + 87 0054 7B68 ldr r3, [r7, #4] + 88 0056 0122 movs r2, #1 + 89 0058 83F83F20 strb r2, [r3, #63] + 90 005c 7B68 ldr r3, [r7, #4] + 91 005e 0122 movs r2, #1 + 92 0060 83F84020 strb r2, [r3, #64] + 93 0064 7B68 ldr r3, [r7, #4] + 94 0066 0122 movs r2, #1 + 95 0068 83F84120 strb r2, [r3, #65] + 96 006c 7B68 ldr r3, [r7, #4] + 97 006e 0122 movs r2, #1 + 98 0070 83F84220 strb r2, [r3, #66] + 99 0074 7B68 ldr r3, [r7, #4] + 100 0076 0122 movs r2, #1 + 101 0078 83F84320 strb r2, [r3, #67] + 320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 102 .loc 1 320 3 + 103 007c 7B68 ldr r3, [r7, #4] + 104 007e 0122 movs r2, #1 + 105 0080 83F84420 strb r2, [r3, #68] + 106 0084 7B68 ldr r3, [r7, #4] + 107 0086 0122 movs r2, #1 + 108 0088 83F84520 strb r2, [r3, #69] + 109 008c 7B68 ldr r3, [r7, #4] + 110 008e 0122 movs r2, #1 + 111 0090 83F84620 strb r2, [r3, #70] + 112 0094 7B68 ldr r3, [r7, #4] + 113 0096 0122 movs r2, #1 + 114 0098 83F84720 strb r2, [r3, #71] + 321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Initialize the TIM state*/ + 323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; + 115 .loc 1 323 15 + 116 009c 7B68 ldr r3, [r7, #4] + 117 009e 0122 movs r2, #1 + 118 00a0 83F83D20 strb r2, [r3, #61] + 324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_OK; + 119 .loc 1 325 10 + 120 00a4 0023 movs r3, #0 + 121 .L3: + 326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 122 .loc 1 326 1 + 123 00a6 1846 mov r0, r3 + 124 00a8 0837 adds r7, r7, #8 + 125 .cfi_def_cfa_offset 8 + 126 00aa BD46 mov sp, r7 + 127 .cfi_def_cfa_register 13 + 128 @ sp needed + 129 00ac 80BD pop {r7, pc} + 130 .cfi_endproc + 131 .LFE130: + ARM GAS /tmp/ccl4b9YO.s page 9 + + + 133 .section .text.HAL_TIM_Base_DeInit,"ax",%progbits + 134 .align 1 + 135 .global HAL_TIM_Base_DeInit + 136 .syntax unified + 137 .thumb + 138 .thumb_func + 140 HAL_TIM_Base_DeInit: + 141 .LFB131: + 327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** + 329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief DeInitializes the TIM Base peripheral + 330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM Base handle + 331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status + 332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ + 333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) + 334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 142 .loc 1 334 1 + 143 .cfi_startproc + 144 @ args = 0, pretend = 0, frame = 8 + 145 @ frame_needed = 1, uses_anonymous_args = 0 + 146 0000 80B5 push {r7, lr} + 147 .cfi_def_cfa_offset 8 + 148 .cfi_offset 7, -8 + 149 .cfi_offset 14, -4 + 150 0002 82B0 sub sp, sp, #8 + 151 .cfi_def_cfa_offset 16 + 152 0004 00AF add r7, sp, #0 + 153 .cfi_def_cfa_register 7 + 154 0006 7860 str r0, [r7, #4] + 335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ + 336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_INSTANCE(htim->Instance)); + 337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; + 155 .loc 1 338 15 + 156 0008 7B68 ldr r3, [r7, #4] + 157 000a 0222 movs r2, #2 + 158 000c 83F83D20 strb r2, [r3, #61] + 339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the TIM Peripheral Clock */ + 341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); + 159 .loc 1 341 3 + 160 0010 7B68 ldr r3, [r7, #4] + 161 0012 1B68 ldr r3, [r3] + 162 0014 1A6A ldr r2, [r3, #32] + 163 0016 41F21113 movw r3, #4369 + 164 001a 1340 ands r3, r3, r2 + 165 001c 002B cmp r3, #0 + 166 001e 0FD1 bne .L6 + 167 .loc 1 341 3 is_stmt 0 discriminator 1 + 168 0020 7B68 ldr r3, [r7, #4] + 169 0022 1B68 ldr r3, [r3] + 170 0024 1A6A ldr r2, [r3, #32] + 171 0026 40F24443 movw r3, #1092 + 172 002a 1340 ands r3, r3, r2 + 173 002c 002B cmp r3, #0 + 174 002e 07D1 bne .L6 + 175 .loc 1 341 3 discriminator 2 + ARM GAS /tmp/ccl4b9YO.s page 10 + + + 176 0030 7B68 ldr r3, [r7, #4] + 177 0032 1B68 ldr r3, [r3] + 178 0034 1A68 ldr r2, [r3] + 179 0036 7B68 ldr r3, [r7, #4] + 180 0038 1B68 ldr r3, [r3] + 181 003a 22F00102 bic r2, r2, #1 + 182 003e 1A60 str r2, [r3] + 183 .L6: + 342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + 344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (htim->Base_MspDeInitCallback == NULL) + 345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; + 347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* DeInit the low level hardware */ + 349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Base_MspDeInitCallback(htim); + 350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #else + 351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + 352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_Base_MspDeInit(htim); + 184 .loc 1 352 3 is_stmt 1 + 185 0040 7868 ldr r0, [r7, #4] + 186 0042 FFF7FEFF bl HAL_TIM_Base_MspDeInit + 353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Change the DMA burst operation state */ + 356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + 187 .loc 1 356 23 + 188 0046 7B68 ldr r3, [r7, #4] + 189 0048 0022 movs r2, #0 + 190 004a 83F84820 strb r2, [r3, #72] + 357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Change the TIM channels state */ + 359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + 191 .loc 1 359 3 + 192 004e 7B68 ldr r3, [r7, #4] + 193 0050 0022 movs r2, #0 + 194 0052 83F83E20 strb r2, [r3, #62] + 195 0056 7B68 ldr r3, [r7, #4] + 196 0058 0022 movs r2, #0 + 197 005a 83F83F20 strb r2, [r3, #63] + 198 005e 7B68 ldr r3, [r7, #4] + 199 0060 0022 movs r2, #0 + 200 0062 83F84020 strb r2, [r3, #64] + 201 0066 7B68 ldr r3, [r7, #4] + 202 0068 0022 movs r2, #0 + 203 006a 83F84120 strb r2, [r3, #65] + 204 006e 7B68 ldr r3, [r7, #4] + 205 0070 0022 movs r2, #0 + 206 0072 83F84220 strb r2, [r3, #66] + 207 0076 7B68 ldr r3, [r7, #4] + 208 0078 0022 movs r2, #0 + 209 007a 83F84320 strb r2, [r3, #67] + 360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + 210 .loc 1 360 3 + 211 007e 7B68 ldr r3, [r7, #4] + 212 0080 0022 movs r2, #0 + 213 0082 83F84420 strb r2, [r3, #68] + ARM GAS /tmp/ccl4b9YO.s page 11 + + + 214 0086 7B68 ldr r3, [r7, #4] + 215 0088 0022 movs r2, #0 + 216 008a 83F84520 strb r2, [r3, #69] + 217 008e 7B68 ldr r3, [r7, #4] + 218 0090 0022 movs r2, #0 + 219 0092 83F84620 strb r2, [r3, #70] + 220 0096 7B68 ldr r3, [r7, #4] + 221 0098 0022 movs r2, #0 + 222 009a 83F84720 strb r2, [r3, #71] + 361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Change TIM state */ + 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->State = HAL_TIM_STATE_RESET; + 223 .loc 1 363 15 + 224 009e 7B68 ldr r3, [r7, #4] + 225 00a0 0022 movs r2, #0 + 226 00a2 83F83D20 strb r2, [r3, #61] + 364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Release Lock */ + 366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_UNLOCK(htim); + 227 .loc 1 366 3 + 228 00a6 7B68 ldr r3, [r7, #4] + 229 00a8 0022 movs r2, #0 + 230 00aa 83F83C20 strb r2, [r3, #60] + 367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_OK; + 231 .loc 1 368 10 + 232 00ae 0023 movs r3, #0 + 369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 233 .loc 1 369 1 + 234 00b0 1846 mov r0, r3 + 235 00b2 0837 adds r7, r7, #8 + 236 .cfi_def_cfa_offset 8 + 237 00b4 BD46 mov sp, r7 + 238 .cfi_def_cfa_register 13 + 239 @ sp needed + 240 00b6 80BD pop {r7, pc} + 241 .cfi_endproc + 242 .LFE131: + 244 .section .text.HAL_TIM_Base_MspInit,"ax",%progbits + 245 .align 1 + 246 .weak HAL_TIM_Base_MspInit + 247 .syntax unified + 248 .thumb + 249 .thumb_func + 251 HAL_TIM_Base_MspInit: + 252 .LFB132: + 370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** + 372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Initializes the TIM Base MSP. + 373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM Base handle + 374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval None + 375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ + 376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) + 377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 253 .loc 1 377 1 + 254 .cfi_startproc + 255 @ args = 0, pretend = 0, frame = 8 + ARM GAS /tmp/ccl4b9YO.s page 12 + + + 256 @ frame_needed = 1, uses_anonymous_args = 0 + 257 @ link register save eliminated. + 258 0000 80B4 push {r7} + 259 .cfi_def_cfa_offset 4 + 260 .cfi_offset 7, -4 + 261 0002 83B0 sub sp, sp, #12 + 262 .cfi_def_cfa_offset 16 + 263 0004 00AF add r7, sp, #0 + 264 .cfi_def_cfa_register 7 + 265 0006 7860 str r0, [r7, #4] + 378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** UNUSED(htim); + 380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* NOTE : This function should not be modified, when the callback is needed, + 382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** the HAL_TIM_Base_MspInit could be implemented in the user file + 383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ + 384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 266 .loc 1 384 1 + 267 0008 00BF nop + 268 000a 0C37 adds r7, r7, #12 + 269 .cfi_def_cfa_offset 4 + 270 000c BD46 mov sp, r7 + 271 .cfi_def_cfa_register 13 + 272 @ sp needed + 273 000e 5DF8047B ldr r7, [sp], #4 + 274 .cfi_restore 7 + 275 .cfi_def_cfa_offset 0 + 276 0012 7047 bx lr + 277 .cfi_endproc + 278 .LFE132: + 280 .section .text.HAL_TIM_Base_MspDeInit,"ax",%progbits + 281 .align 1 + 282 .weak HAL_TIM_Base_MspDeInit + 283 .syntax unified + 284 .thumb + 285 .thumb_func + 287 HAL_TIM_Base_MspDeInit: + 288 .LFB133: + 385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** + 387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief DeInitializes TIM Base MSP. + 388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM Base handle + 389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval None + 390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ + 391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) + 392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 289 .loc 1 392 1 + 290 .cfi_startproc + 291 @ args = 0, pretend = 0, frame = 8 + 292 @ frame_needed = 1, uses_anonymous_args = 0 + 293 @ link register save eliminated. + 294 0000 80B4 push {r7} + 295 .cfi_def_cfa_offset 4 + 296 .cfi_offset 7, -4 + 297 0002 83B0 sub sp, sp, #12 + 298 .cfi_def_cfa_offset 16 + 299 0004 00AF add r7, sp, #0 + ARM GAS /tmp/ccl4b9YO.s page 13 + + + 300 .cfi_def_cfa_register 7 + 301 0006 7860 str r0, [r7, #4] + 393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** UNUSED(htim); + 395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* NOTE : This function should not be modified, when the callback is needed, + 397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** the HAL_TIM_Base_MspDeInit could be implemented in the user file + 398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ + 399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 302 .loc 1 399 1 + 303 0008 00BF nop + 304 000a 0C37 adds r7, r7, #12 + 305 .cfi_def_cfa_offset 4 + 306 000c BD46 mov sp, r7 + 307 .cfi_def_cfa_register 13 + 308 @ sp needed + 309 000e 5DF8047B ldr r7, [sp], #4 + 310 .cfi_restore 7 + 311 .cfi_def_cfa_offset 0 + 312 0012 7047 bx lr + 313 .cfi_endproc + 314 .LFE133: + 316 .section .text.HAL_TIM_Base_Start,"ax",%progbits + 317 .align 1 + 318 .global HAL_TIM_Base_Start + 319 .syntax unified + 320 .thumb + 321 .thumb_func + 323 HAL_TIM_Base_Start: + 324 .LFB134: + 400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** + 403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Starts the TIM Base generation. + 404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM Base handle + 405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status + 406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ + 407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) + 408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 325 .loc 1 408 1 + 326 .cfi_startproc + 327 @ args = 0, pretend = 0, frame = 16 + 328 @ frame_needed = 1, uses_anonymous_args = 0 + 329 @ link register save eliminated. + 330 0000 80B4 push {r7} + 331 .cfi_def_cfa_offset 4 + 332 .cfi_offset 7, -4 + 333 0002 85B0 sub sp, sp, #20 + 334 .cfi_def_cfa_offset 24 + 335 0004 00AF add r7, sp, #0 + 336 .cfi_def_cfa_register 7 + 337 0006 7860 str r0, [r7, #4] + 409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpsmcr; + 410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ + 412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_INSTANCE(htim->Instance)); + 413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + ARM GAS /tmp/ccl4b9YO.s page 14 + + + 414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the TIM state */ + 415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (htim->State != HAL_TIM_STATE_READY) + 338 .loc 1 415 11 + 339 0008 7B68 ldr r3, [r7, #4] + 340 000a 93F83D30 ldrb r3, [r3, #61] + 341 000e DBB2 uxtb r3, r3 + 342 .loc 1 415 6 + 343 0010 012B cmp r3, #1 + 344 0012 01D0 beq .L11 + 416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 345 .loc 1 417 12 + 346 0014 0123 movs r3, #1 + 347 0016 3DE0 b .L12 + 348 .L11: + 418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the TIM state */ + 421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; + 349 .loc 1 421 15 + 350 0018 7B68 ldr r3, [r7, #4] + 351 001a 0222 movs r2, #2 + 352 001c 83F83D20 strb r2, [r3, #61] + 422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger + 424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 353 .loc 1 424 7 + 354 0020 7B68 ldr r3, [r7, #4] + 355 0022 1B68 ldr r3, [r3] + 356 .loc 1 424 6 + 357 0024 1E4A ldr r2, .L18 + 358 0026 9342 cmp r3, r2 + 359 0028 13D0 beq .L13 + 360 .loc 1 424 7 discriminator 1 + 361 002a 7B68 ldr r3, [r7, #4] + 362 002c 1B68 ldr r3, [r3] + 363 002e B3F1804F cmp r3, #1073741824 + 364 0032 0ED0 beq .L13 + 365 .loc 1 424 7 is_stmt 0 discriminator 2 + 366 0034 7B68 ldr r3, [r7, #4] + 367 0036 1B68 ldr r3, [r3] + 368 0038 1A4A ldr r2, .L18+4 + 369 003a 9342 cmp r3, r2 + 370 003c 09D0 beq .L13 + 371 .loc 1 424 7 discriminator 3 + 372 003e 7B68 ldr r3, [r7, #4] + 373 0040 1B68 ldr r3, [r3] + 374 0042 194A ldr r2, .L18+8 + 375 0044 9342 cmp r3, r2 + 376 0046 04D0 beq .L13 + 377 .loc 1 424 7 discriminator 4 + 378 0048 7B68 ldr r3, [r7, #4] + 379 004a 1B68 ldr r3, [r3] + 380 004c 174A ldr r2, .L18+12 + 381 004e 9342 cmp r3, r2 + 382 0050 15D1 bne .L14 + 383 .L13: + ARM GAS /tmp/ccl4b9YO.s page 15 + + + 425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + 384 .loc 1 426 19 is_stmt 1 + 385 0052 7B68 ldr r3, [r7, #4] + 386 0054 1B68 ldr r3, [r3] + 387 .loc 1 426 29 + 388 0056 9A68 ldr r2, [r3, #8] + 389 .loc 1 426 13 + 390 0058 154B ldr r3, .L18+16 + 391 005a 1340 ands r3, r3, r2 + 392 005c FB60 str r3, [r7, #12] + 427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 393 .loc 1 427 8 + 394 005e FB68 ldr r3, [r7, #12] + 395 0060 062B cmp r3, #6 + 396 0062 15D0 beq .L17 + 397 .loc 1 427 9 discriminator 1 + 398 0064 FB68 ldr r3, [r7, #12] + 399 0066 B3F5803F cmp r3, #65536 + 400 006a 11D0 beq .L17 + 428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); + 401 .loc 1 429 7 + 402 006c 7B68 ldr r3, [r7, #4] + 403 006e 1B68 ldr r3, [r3] + 404 0070 1A68 ldr r2, [r3] + 405 0072 7B68 ldr r3, [r7, #4] + 406 0074 1B68 ldr r3, [r3] + 407 0076 42F00102 orr r2, r2, #1 + 408 007a 1A60 str r2, [r3] + 427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 409 .loc 1 427 8 + 410 007c 08E0 b .L17 + 411 .L14: + 430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else + 433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); + 412 .loc 1 434 5 + 413 007e 7B68 ldr r3, [r7, #4] + 414 0080 1B68 ldr r3, [r3] + 415 0082 1A68 ldr r2, [r3] + 416 0084 7B68 ldr r3, [r7, #4] + 417 0086 1B68 ldr r3, [r3] + 418 0088 42F00102 orr r2, r2, #1 + 419 008c 1A60 str r2, [r3] + 420 008e 00E0 b .L16 + 421 .L17: + 427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 422 .loc 1 427 8 + 423 0090 00BF nop + 424 .L16: + 435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return function status */ + 438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_OK; + ARM GAS /tmp/ccl4b9YO.s page 16 + + + 425 .loc 1 438 10 + 426 0092 0023 movs r3, #0 + 427 .L12: + 439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 428 .loc 1 439 1 + 429 0094 1846 mov r0, r3 + 430 0096 1437 adds r7, r7, #20 + 431 .cfi_def_cfa_offset 4 + 432 0098 BD46 mov sp, r7 + 433 .cfi_def_cfa_register 13 + 434 @ sp needed + 435 009a 5DF8047B ldr r7, [sp], #4 + 436 .cfi_restore 7 + 437 .cfi_def_cfa_offset 0 + 438 009e 7047 bx lr + 439 .L19: + 440 .align 2 + 441 .L18: + 442 00a0 002C0140 .word 1073818624 + 443 00a4 00040040 .word 1073742848 + 444 00a8 00080040 .word 1073743872 + 445 00ac 00400140 .word 1073823744 + 446 00b0 07000100 .word 65543 + 447 .cfi_endproc + 448 .LFE134: + 450 .section .text.HAL_TIM_Base_Stop,"ax",%progbits + 451 .align 1 + 452 .global HAL_TIM_Base_Stop + 453 .syntax unified + 454 .thumb + 455 .thumb_func + 457 HAL_TIM_Base_Stop: + 458 .LFB135: + 440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** + 442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Stops the TIM Base generation. + 443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM Base handle + 444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status + 445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ + 446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) + 447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 459 .loc 1 447 1 + 460 .cfi_startproc + 461 @ args = 0, pretend = 0, frame = 8 + 462 @ frame_needed = 1, uses_anonymous_args = 0 + 463 @ link register save eliminated. + 464 0000 80B4 push {r7} + 465 .cfi_def_cfa_offset 4 + 466 .cfi_offset 7, -4 + 467 0002 83B0 sub sp, sp, #12 + 468 .cfi_def_cfa_offset 16 + 469 0004 00AF add r7, sp, #0 + 470 .cfi_def_cfa_register 7 + 471 0006 7860 str r0, [r7, #4] + 448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ + 449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_INSTANCE(htim->Instance)); + 450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + ARM GAS /tmp/ccl4b9YO.s page 17 + + + 451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the Peripheral */ + 452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); + 472 .loc 1 452 3 + 473 0008 7B68 ldr r3, [r7, #4] + 474 000a 1B68 ldr r3, [r3] + 475 000c 1A6A ldr r2, [r3, #32] + 476 000e 41F21113 movw r3, #4369 + 477 0012 1340 ands r3, r3, r2 + 478 0014 002B cmp r3, #0 + 479 0016 0FD1 bne .L21 + 480 .loc 1 452 3 is_stmt 0 discriminator 1 + 481 0018 7B68 ldr r3, [r7, #4] + 482 001a 1B68 ldr r3, [r3] + 483 001c 1A6A ldr r2, [r3, #32] + 484 001e 40F24443 movw r3, #1092 + 485 0022 1340 ands r3, r3, r2 + 486 0024 002B cmp r3, #0 + 487 0026 07D1 bne .L21 + 488 .loc 1 452 3 discriminator 2 + 489 0028 7B68 ldr r3, [r7, #4] + 490 002a 1B68 ldr r3, [r3] + 491 002c 1A68 ldr r2, [r3] + 492 002e 7B68 ldr r3, [r7, #4] + 493 0030 1B68 ldr r3, [r3] + 494 0032 22F00102 bic r2, r2, #1 + 495 0036 1A60 str r2, [r3] + 496 .L21: + 453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the TIM state */ + 455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; + 497 .loc 1 455 15 is_stmt 1 + 498 0038 7B68 ldr r3, [r7, #4] + 499 003a 0122 movs r2, #1 + 500 003c 83F83D20 strb r2, [r3, #61] + 456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return function status */ + 458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_OK; + 501 .loc 1 458 10 + 502 0040 0023 movs r3, #0 + 459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 503 .loc 1 459 1 + 504 0042 1846 mov r0, r3 + 505 0044 0C37 adds r7, r7, #12 + 506 .cfi_def_cfa_offset 4 + 507 0046 BD46 mov sp, r7 + 508 .cfi_def_cfa_register 13 + 509 @ sp needed + 510 0048 5DF8047B ldr r7, [sp], #4 + 511 .cfi_restore 7 + 512 .cfi_def_cfa_offset 0 + 513 004c 7047 bx lr + 514 .cfi_endproc + 515 .LFE135: + 517 .section .text.HAL_TIM_Base_Start_IT,"ax",%progbits + 518 .align 1 + 519 .global HAL_TIM_Base_Start_IT + 520 .syntax unified + ARM GAS /tmp/ccl4b9YO.s page 18 + + + 521 .thumb + 522 .thumb_func + 524 HAL_TIM_Base_Start_IT: + 525 .LFB136: + 460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** + 462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Starts the TIM Base generation in interrupt mode. + 463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM Base handle + 464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status + 465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ + 466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) + 467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 526 .loc 1 467 1 + 527 .cfi_startproc + 528 @ args = 0, pretend = 0, frame = 16 + 529 @ frame_needed = 1, uses_anonymous_args = 0 + 530 @ link register save eliminated. + 531 0000 80B4 push {r7} + 532 .cfi_def_cfa_offset 4 + 533 .cfi_offset 7, -4 + 534 0002 85B0 sub sp, sp, #20 + 535 .cfi_def_cfa_offset 24 + 536 0004 00AF add r7, sp, #0 + 537 .cfi_def_cfa_register 7 + 538 0006 7860 str r0, [r7, #4] + 468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpsmcr; + 469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ + 471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_INSTANCE(htim->Instance)); + 472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the TIM state */ + 474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (htim->State != HAL_TIM_STATE_READY) + 539 .loc 1 474 11 + 540 0008 7B68 ldr r3, [r7, #4] + 541 000a 93F83D30 ldrb r3, [r3, #61] + 542 000e DBB2 uxtb r3, r3 + 543 .loc 1 474 6 + 544 0010 012B cmp r3, #1 + 545 0012 01D0 beq .L24 + 475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 546 .loc 1 476 12 + 547 0014 0123 movs r3, #1 + 548 0016 45E0 b .L25 + 549 .L24: + 477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the TIM state */ + 480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; + 550 .loc 1 480 15 + 551 0018 7B68 ldr r3, [r7, #4] + 552 001a 0222 movs r2, #2 + 553 001c 83F83D20 strb r2, [r3, #61] + 481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the TIM Update interrupt */ + 483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); + 554 .loc 1 483 3 + ARM GAS /tmp/ccl4b9YO.s page 19 + + + 555 0020 7B68 ldr r3, [r7, #4] + 556 0022 1B68 ldr r3, [r3] + 557 0024 DA68 ldr r2, [r3, #12] + 558 0026 7B68 ldr r3, [r7, #4] + 559 0028 1B68 ldr r3, [r3] + 560 002a 42F00102 orr r2, r2, #1 + 561 002e DA60 str r2, [r3, #12] + 484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger + 486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 562 .loc 1 486 7 + 563 0030 7B68 ldr r3, [r7, #4] + 564 0032 1B68 ldr r3, [r3] + 565 .loc 1 486 6 + 566 0034 1E4A ldr r2, .L31 + 567 0036 9342 cmp r3, r2 + 568 0038 13D0 beq .L26 + 569 .loc 1 486 7 discriminator 1 + 570 003a 7B68 ldr r3, [r7, #4] + 571 003c 1B68 ldr r3, [r3] + 572 003e B3F1804F cmp r3, #1073741824 + 573 0042 0ED0 beq .L26 + 574 .loc 1 486 7 is_stmt 0 discriminator 2 + 575 0044 7B68 ldr r3, [r7, #4] + 576 0046 1B68 ldr r3, [r3] + 577 0048 1A4A ldr r2, .L31+4 + 578 004a 9342 cmp r3, r2 + 579 004c 09D0 beq .L26 + 580 .loc 1 486 7 discriminator 3 + 581 004e 7B68 ldr r3, [r7, #4] + 582 0050 1B68 ldr r3, [r3] + 583 0052 194A ldr r2, .L31+8 + 584 0054 9342 cmp r3, r2 + 585 0056 04D0 beq .L26 + 586 .loc 1 486 7 discriminator 4 + 587 0058 7B68 ldr r3, [r7, #4] + 588 005a 1B68 ldr r3, [r3] + 589 005c 174A ldr r2, .L31+12 + 590 005e 9342 cmp r3, r2 + 591 0060 15D1 bne .L27 + 592 .L26: + 487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + 593 .loc 1 488 19 is_stmt 1 + 594 0062 7B68 ldr r3, [r7, #4] + 595 0064 1B68 ldr r3, [r3] + 596 .loc 1 488 29 + 597 0066 9A68 ldr r2, [r3, #8] + 598 .loc 1 488 13 + 599 0068 154B ldr r3, .L31+16 + 600 006a 1340 ands r3, r3, r2 + 601 006c FB60 str r3, [r7, #12] + 489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 602 .loc 1 489 8 + 603 006e FB68 ldr r3, [r7, #12] + 604 0070 062B cmp r3, #6 + 605 0072 15D0 beq .L30 + ARM GAS /tmp/ccl4b9YO.s page 20 + + + 606 .loc 1 489 9 discriminator 1 + 607 0074 FB68 ldr r3, [r7, #12] + 608 0076 B3F5803F cmp r3, #65536 + 609 007a 11D0 beq .L30 + 490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); + 610 .loc 1 491 7 + 611 007c 7B68 ldr r3, [r7, #4] + 612 007e 1B68 ldr r3, [r3] + 613 0080 1A68 ldr r2, [r3] + 614 0082 7B68 ldr r3, [r7, #4] + 615 0084 1B68 ldr r3, [r3] + 616 0086 42F00102 orr r2, r2, #1 + 617 008a 1A60 str r2, [r3] + 489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 618 .loc 1 489 8 + 619 008c 08E0 b .L30 + 620 .L27: + 492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else + 495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); + 621 .loc 1 496 5 + 622 008e 7B68 ldr r3, [r7, #4] + 623 0090 1B68 ldr r3, [r3] + 624 0092 1A68 ldr r2, [r3] + 625 0094 7B68 ldr r3, [r7, #4] + 626 0096 1B68 ldr r3, [r3] + 627 0098 42F00102 orr r2, r2, #1 + 628 009c 1A60 str r2, [r3] + 629 009e 00E0 b .L29 + 630 .L30: + 489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 631 .loc 1 489 8 + 632 00a0 00BF nop + 633 .L29: + 497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return function status */ + 500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_OK; + 634 .loc 1 500 10 + 635 00a2 0023 movs r3, #0 + 636 .L25: + 501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 637 .loc 1 501 1 + 638 00a4 1846 mov r0, r3 + 639 00a6 1437 adds r7, r7, #20 + 640 .cfi_def_cfa_offset 4 + 641 00a8 BD46 mov sp, r7 + 642 .cfi_def_cfa_register 13 + 643 @ sp needed + 644 00aa 5DF8047B ldr r7, [sp], #4 + 645 .cfi_restore 7 + 646 .cfi_def_cfa_offset 0 + 647 00ae 7047 bx lr + 648 .L32: + ARM GAS /tmp/ccl4b9YO.s page 21 + + + 649 .align 2 + 650 .L31: + 651 00b0 002C0140 .word 1073818624 + 652 00b4 00040040 .word 1073742848 + 653 00b8 00080040 .word 1073743872 + 654 00bc 00400140 .word 1073823744 + 655 00c0 07000100 .word 65543 + 656 .cfi_endproc + 657 .LFE136: + 659 .section .text.HAL_TIM_Base_Stop_IT,"ax",%progbits + 660 .align 1 + 661 .global HAL_TIM_Base_Stop_IT + 662 .syntax unified + 663 .thumb + 664 .thumb_func + 666 HAL_TIM_Base_Stop_IT: + 667 .LFB137: + 502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** + 504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Stops the TIM Base generation in interrupt mode. + 505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM Base handle + 506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status + 507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ + 508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) + 509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 668 .loc 1 509 1 + 669 .cfi_startproc + 670 @ args = 0, pretend = 0, frame = 8 + 671 @ frame_needed = 1, uses_anonymous_args = 0 + 672 @ link register save eliminated. + 673 0000 80B4 push {r7} + 674 .cfi_def_cfa_offset 4 + 675 .cfi_offset 7, -4 + 676 0002 83B0 sub sp, sp, #12 + 677 .cfi_def_cfa_offset 16 + 678 0004 00AF add r7, sp, #0 + 679 .cfi_def_cfa_register 7 + 680 0006 7860 str r0, [r7, #4] + 510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ + 511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_INSTANCE(htim->Instance)); + 512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the TIM Update interrupt */ + 514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); + 681 .loc 1 514 3 + 682 0008 7B68 ldr r3, [r7, #4] + 683 000a 1B68 ldr r3, [r3] + 684 000c DA68 ldr r2, [r3, #12] + 685 000e 7B68 ldr r3, [r7, #4] + 686 0010 1B68 ldr r3, [r3] + 687 0012 22F00102 bic r2, r2, #1 + 688 0016 DA60 str r2, [r3, #12] + 515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the Peripheral */ + 517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); + 689 .loc 1 517 3 + 690 0018 7B68 ldr r3, [r7, #4] + 691 001a 1B68 ldr r3, [r3] + ARM GAS /tmp/ccl4b9YO.s page 22 + + + 692 001c 1A6A ldr r2, [r3, #32] + 693 001e 41F21113 movw r3, #4369 + 694 0022 1340 ands r3, r3, r2 + 695 0024 002B cmp r3, #0 + 696 0026 0FD1 bne .L34 + 697 .loc 1 517 3 is_stmt 0 discriminator 1 + 698 0028 7B68 ldr r3, [r7, #4] + 699 002a 1B68 ldr r3, [r3] + 700 002c 1A6A ldr r2, [r3, #32] + 701 002e 40F24443 movw r3, #1092 + 702 0032 1340 ands r3, r3, r2 + 703 0034 002B cmp r3, #0 + 704 0036 07D1 bne .L34 + 705 .loc 1 517 3 discriminator 2 + 706 0038 7B68 ldr r3, [r7, #4] + 707 003a 1B68 ldr r3, [r3] + 708 003c 1A68 ldr r2, [r3] + 709 003e 7B68 ldr r3, [r7, #4] + 710 0040 1B68 ldr r3, [r3] + 711 0042 22F00102 bic r2, r2, #1 + 712 0046 1A60 str r2, [r3] + 713 .L34: + 518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the TIM state */ + 520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; + 714 .loc 1 520 15 is_stmt 1 + 715 0048 7B68 ldr r3, [r7, #4] + 716 004a 0122 movs r2, #1 + 717 004c 83F83D20 strb r2, [r3, #61] + 521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return function status */ + 523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_OK; + 718 .loc 1 523 10 + 719 0050 0023 movs r3, #0 + 524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 720 .loc 1 524 1 + 721 0052 1846 mov r0, r3 + 722 0054 0C37 adds r7, r7, #12 + 723 .cfi_def_cfa_offset 4 + 724 0056 BD46 mov sp, r7 + 725 .cfi_def_cfa_register 13 + 726 @ sp needed + 727 0058 5DF8047B ldr r7, [sp], #4 + 728 .cfi_restore 7 + 729 .cfi_def_cfa_offset 0 + 730 005c 7047 bx lr + 731 .cfi_endproc + 732 .LFE137: + 734 .section .text.HAL_TIM_Base_Start_DMA,"ax",%progbits + 735 .align 1 + 736 .global HAL_TIM_Base_Start_DMA + 737 .syntax unified + 738 .thumb + 739 .thumb_func + 741 HAL_TIM_Base_Start_DMA: + 742 .LFB138: + 525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + ARM GAS /tmp/ccl4b9YO.s page 23 + + + 526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** + 527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Starts the TIM Base generation in DMA mode. + 528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM Base handle + 529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param pData The source Buffer address. + 530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param Length The length of data to be transferred from memory to peripheral. + 531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status + 532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ + 533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t L + 534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 743 .loc 1 534 1 + 744 .cfi_startproc + 745 @ args = 0, pretend = 0, frame = 24 + 746 @ frame_needed = 1, uses_anonymous_args = 0 + 747 0000 80B5 push {r7, lr} + 748 .cfi_def_cfa_offset 8 + 749 .cfi_offset 7, -8 + 750 .cfi_offset 14, -4 + 751 0002 86B0 sub sp, sp, #24 + 752 .cfi_def_cfa_offset 32 + 753 0004 00AF add r7, sp, #0 + 754 .cfi_def_cfa_register 7 + 755 0006 F860 str r0, [r7, #12] + 756 0008 B960 str r1, [r7, #8] + 757 000a 1346 mov r3, r2 + 758 000c FB80 strh r3, [r7, #6] @ movhi + 535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpsmcr; + 536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ + 538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + 539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the TIM state */ + 541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (htim->State == HAL_TIM_STATE_BUSY) + 759 .loc 1 541 11 + 760 000e FB68 ldr r3, [r7, #12] + 761 0010 93F83D30 ldrb r3, [r3, #61] + 762 0014 DBB2 uxtb r3, r3 + 763 .loc 1 541 6 + 764 0016 022B cmp r3, #2 + 765 0018 01D1 bne .L37 + 542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_BUSY; + 766 .loc 1 543 12 + 767 001a 0223 movs r3, #2 + 768 001c 71E0 b .L38 + 769 .L37: + 544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else if (htim->State == HAL_TIM_STATE_READY) + 770 .loc 1 545 16 + 771 001e FB68 ldr r3, [r7, #12] + 772 0020 93F83D30 ldrb r3, [r3, #61] + 773 0024 DBB2 uxtb r3, r3 + 774 .loc 1 545 11 + 775 0026 012B cmp r3, #1 + 776 0028 25D1 bne .L39 + 546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if ((pData == NULL) || (Length == 0U)) + 777 .loc 1 547 8 + ARM GAS /tmp/ccl4b9YO.s page 24 + + + 778 002a BB68 ldr r3, [r7, #8] + 779 002c 002B cmp r3, #0 + 780 002e 02D0 beq .L40 + 781 .loc 1 547 25 discriminator 1 + 782 0030 FB88 ldrh r3, [r7, #6] + 783 0032 002B cmp r3, #0 + 784 0034 01D1 bne .L41 + 785 .L40: + 548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 786 .loc 1 549 14 + 787 0036 0123 movs r3, #1 + 788 0038 63E0 b .L38 + 789 .L41: + 550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else + 552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; + 790 .loc 1 553 19 + 791 003a FB68 ldr r3, [r7, #12] + 792 003c 0222 movs r2, #2 + 793 003e 83F83D20 strb r2, [r3, #61] + 554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else + 557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA Period elapsed callbacks */ + 562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + 794 .loc 1 562 13 + 795 0042 FB68 ldr r3, [r7, #12] + 796 0044 1B6A ldr r3, [r3, #32] + 797 .loc 1 562 51 + 798 0046 314A ldr r2, .L50 + 799 0048 9A62 str r2, [r3, #40] + 563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + 800 .loc 1 563 13 + 801 004a FB68 ldr r3, [r7, #12] + 802 004c 1B6A ldr r3, [r3, #32] + 803 .loc 1 563 55 + 804 004e 304A ldr r2, .L50+4 + 805 0050 DA62 str r2, [r3, #44] + 564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA error callback */ + 566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + 806 .loc 1 566 13 + 807 0052 FB68 ldr r3, [r7, #12] + 808 0054 1B6A ldr r3, [r3, #32] + 809 .loc 1 566 52 + 810 0056 2F4A ldr r2, .L50+8 + 811 0058 1A63 str r2, [r3, #48] + 567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the DMA channel */ + 569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->A + 812 .loc 1 569 7 + ARM GAS /tmp/ccl4b9YO.s page 25 + + + 813 005a FB68 ldr r3, [r7, #12] + 814 005c 186A ldr r0, [r3, #32] + 815 005e B968 ldr r1, [r7, #8] + 816 .loc 1 569 87 + 817 0060 FB68 ldr r3, [r7, #12] + 818 0062 1B68 ldr r3, [r3] + 819 .loc 1 569 82 + 820 0064 2C33 adds r3, r3, #44 + 821 .loc 1 569 7 + 822 0066 1A46 mov r2, r3 + 823 0068 FB88 ldrh r3, [r7, #6] + 824 006a FFF7FEFF bl HAL_DMA_Start_IT + 825 006e 0346 mov r3, r0 + 826 .loc 1 569 6 discriminator 1 + 827 0070 002B cmp r3, #0 + 828 0072 04D0 beq .L43 + 829 0074 01E0 b .L48 + 830 .L39: + 558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 831 .loc 1 558 12 + 832 0076 0123 movs r3, #1 + 833 0078 43E0 b .L38 + 834 .L48: + 570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** Length) != HAL_OK) + 571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return error status */ + 573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 835 .loc 1 573 12 + 836 007a 0123 movs r3, #1 + 837 007c 41E0 b .L38 + 838 .L43: + 574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the TIM Update DMA request */ + 577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); + 839 .loc 1 577 3 + 840 007e FB68 ldr r3, [r7, #12] + 841 0080 1B68 ldr r3, [r3] + 842 0082 DA68 ldr r2, [r3, #12] + 843 0084 FB68 ldr r3, [r7, #12] + 844 0086 1B68 ldr r3, [r3] + 845 0088 42F48072 orr r2, r2, #256 + 846 008c DA60 str r2, [r3, #12] + 578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger + 580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 847 .loc 1 580 7 + 848 008e FB68 ldr r3, [r7, #12] + 849 0090 1B68 ldr r3, [r3] + 850 .loc 1 580 6 + 851 0092 214A ldr r2, .L50+12 + 852 0094 9342 cmp r3, r2 + 853 0096 13D0 beq .L44 + 854 .loc 1 580 7 discriminator 1 + 855 0098 FB68 ldr r3, [r7, #12] + 856 009a 1B68 ldr r3, [r3] + 857 009c B3F1804F cmp r3, #1073741824 + ARM GAS /tmp/ccl4b9YO.s page 26 + + + 858 00a0 0ED0 beq .L44 + 859 .loc 1 580 7 is_stmt 0 discriminator 2 + 860 00a2 FB68 ldr r3, [r7, #12] + 861 00a4 1B68 ldr r3, [r3] + 862 00a6 1D4A ldr r2, .L50+16 + 863 00a8 9342 cmp r3, r2 + 864 00aa 09D0 beq .L44 + 865 .loc 1 580 7 discriminator 3 + 866 00ac FB68 ldr r3, [r7, #12] + 867 00ae 1B68 ldr r3, [r3] + 868 00b0 1B4A ldr r2, .L50+20 + 869 00b2 9342 cmp r3, r2 + 870 00b4 04D0 beq .L44 + 871 .loc 1 580 7 discriminator 4 + 872 00b6 FB68 ldr r3, [r7, #12] + 873 00b8 1B68 ldr r3, [r3] + 874 00ba 1A4A ldr r2, .L50+24 + 875 00bc 9342 cmp r3, r2 + 876 00be 15D1 bne .L45 + 877 .L44: + 581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + 878 .loc 1 582 19 is_stmt 1 + 879 00c0 FB68 ldr r3, [r7, #12] + 880 00c2 1B68 ldr r3, [r3] + 881 .loc 1 582 29 + 882 00c4 9A68 ldr r2, [r3, #8] + 883 .loc 1 582 13 + 884 00c6 184B ldr r3, .L50+28 + 885 00c8 1340 ands r3, r3, r2 + 886 00ca 7B61 str r3, [r7, #20] + 583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 887 .loc 1 583 8 + 888 00cc 7B69 ldr r3, [r7, #20] + 889 00ce 062B cmp r3, #6 + 890 00d0 15D0 beq .L49 + 891 .loc 1 583 9 discriminator 1 + 892 00d2 7B69 ldr r3, [r7, #20] + 893 00d4 B3F5803F cmp r3, #65536 + 894 00d8 11D0 beq .L49 + 584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); + 895 .loc 1 585 7 + 896 00da FB68 ldr r3, [r7, #12] + 897 00dc 1B68 ldr r3, [r3] + 898 00de 1A68 ldr r2, [r3] + 899 00e0 FB68 ldr r3, [r7, #12] + 900 00e2 1B68 ldr r3, [r3] + 901 00e4 42F00102 orr r2, r2, #1 + 902 00e8 1A60 str r2, [r3] + 583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 903 .loc 1 583 8 + 904 00ea 08E0 b .L49 + 905 .L45: + 586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else + ARM GAS /tmp/ccl4b9YO.s page 27 + + + 589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); + 906 .loc 1 590 5 + 907 00ec FB68 ldr r3, [r7, #12] + 908 00ee 1B68 ldr r3, [r3] + 909 00f0 1A68 ldr r2, [r3] + 910 00f2 FB68 ldr r3, [r7, #12] + 911 00f4 1B68 ldr r3, [r3] + 912 00f6 42F00102 orr r2, r2, #1 + 913 00fa 1A60 str r2, [r3] + 914 00fc 00E0 b .L47 + 915 .L49: + 583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 916 .loc 1 583 8 + 917 00fe 00BF nop + 918 .L47: + 591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return function status */ + 594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_OK; + 919 .loc 1 594 10 + 920 0100 0023 movs r3, #0 + 921 .L38: + 595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 922 .loc 1 595 1 + 923 0102 1846 mov r0, r3 + 924 0104 1837 adds r7, r7, #24 + 925 .cfi_def_cfa_offset 8 + 926 0106 BD46 mov sp, r7 + 927 .cfi_def_cfa_register 13 + 928 @ sp needed + 929 0108 80BD pop {r7, pc} + 930 .L51: + 931 010a 00BF .align 2 + 932 .L50: + 933 010c 00000000 .word TIM_DMAPeriodElapsedCplt + 934 0110 00000000 .word TIM_DMAPeriodElapsedHalfCplt + 935 0114 00000000 .word TIM_DMAError + 936 0118 002C0140 .word 1073818624 + 937 011c 00040040 .word 1073742848 + 938 0120 00080040 .word 1073743872 + 939 0124 00400140 .word 1073823744 + 940 0128 07000100 .word 65543 + 941 .cfi_endproc + 942 .LFE138: + 944 .section .text.HAL_TIM_Base_Stop_DMA,"ax",%progbits + 945 .align 1 + 946 .global HAL_TIM_Base_Stop_DMA + 947 .syntax unified + 948 .thumb + 949 .thumb_func + 951 HAL_TIM_Base_Stop_DMA: + 952 .LFB139: + 596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** + 598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Stops the TIM Base generation in DMA mode. + 599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM Base handle + ARM GAS /tmp/ccl4b9YO.s page 28 + + + 600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status + 601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ + 602:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) + 603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 953 .loc 1 603 1 + 954 .cfi_startproc + 955 @ args = 0, pretend = 0, frame = 8 + 956 @ frame_needed = 1, uses_anonymous_args = 0 + 957 0000 80B5 push {r7, lr} + 958 .cfi_def_cfa_offset 8 + 959 .cfi_offset 7, -8 + 960 .cfi_offset 14, -4 + 961 0002 82B0 sub sp, sp, #8 + 962 .cfi_def_cfa_offset 16 + 963 0004 00AF add r7, sp, #0 + 964 .cfi_def_cfa_register 7 + 965 0006 7860 str r0, [r7, #4] + 604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ + 605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + 606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the TIM Update DMA request */ + 608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); + 966 .loc 1 608 3 + 967 0008 7B68 ldr r3, [r7, #4] + 968 000a 1B68 ldr r3, [r3] + 969 000c DA68 ldr r2, [r3, #12] + 970 000e 7B68 ldr r3, [r7, #4] + 971 0010 1B68 ldr r3, [r3] + 972 0012 22F48072 bic r2, r2, #256 + 973 0016 DA60 str r2, [r3, #12] + 609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + 974 .loc 1 610 9 + 975 0018 7B68 ldr r3, [r7, #4] + 976 001a 1B6A ldr r3, [r3, #32] + 977 001c 1846 mov r0, r3 + 978 001e FFF7FEFF bl HAL_DMA_Abort_IT + 611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 612:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the Peripheral */ + 613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); + 979 .loc 1 613 3 + 980 0022 7B68 ldr r3, [r7, #4] + 981 0024 1B68 ldr r3, [r3] + 982 0026 1A6A ldr r2, [r3, #32] + 983 0028 41F21113 movw r3, #4369 + 984 002c 1340 ands r3, r3, r2 + 985 002e 002B cmp r3, #0 + 986 0030 0FD1 bne .L53 + 987 .loc 1 613 3 is_stmt 0 discriminator 1 + 988 0032 7B68 ldr r3, [r7, #4] + 989 0034 1B68 ldr r3, [r3] + 990 0036 1A6A ldr r2, [r3, #32] + 991 0038 40F24443 movw r3, #1092 + 992 003c 1340 ands r3, r3, r2 + 993 003e 002B cmp r3, #0 + 994 0040 07D1 bne .L53 + 995 .loc 1 613 3 discriminator 2 + ARM GAS /tmp/ccl4b9YO.s page 29 + + + 996 0042 7B68 ldr r3, [r7, #4] + 997 0044 1B68 ldr r3, [r3] + 998 0046 1A68 ldr r2, [r3] + 999 0048 7B68 ldr r3, [r7, #4] + 1000 004a 1B68 ldr r3, [r3] + 1001 004c 22F00102 bic r2, r2, #1 + 1002 0050 1A60 str r2, [r3] + 1003 .L53: + 614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the TIM state */ + 616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; + 1004 .loc 1 616 15 is_stmt 1 + 1005 0052 7B68 ldr r3, [r7, #4] + 1006 0054 0122 movs r2, #1 + 1007 0056 83F83D20 strb r2, [r3, #61] + 617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return function status */ + 619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_OK; + 1008 .loc 1 619 10 + 1009 005a 0023 movs r3, #0 + 620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 1010 .loc 1 620 1 + 1011 005c 1846 mov r0, r3 + 1012 005e 0837 adds r7, r7, #8 + 1013 .cfi_def_cfa_offset 8 + 1014 0060 BD46 mov sp, r7 + 1015 .cfi_def_cfa_register 13 + 1016 @ sp needed + 1017 0062 80BD pop {r7, pc} + 1018 .cfi_endproc + 1019 .LFE139: + 1021 .section .text.HAL_TIM_OC_Init,"ax",%progbits + 1022 .align 1 + 1023 .global HAL_TIM_OC_Init + 1024 .syntax unified + 1025 .thumb + 1026 .thumb_func + 1028 HAL_TIM_OC_Init: + 1029 .LFB140: + 621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** + 623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @} + 624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ + 625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions + 627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief TIM Output Compare functions + 628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * + 629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** @verbatim + 630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** ============================================================================== + 631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** ##### TIM Output Compare functions ##### + 632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** ============================================================================== + 633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** [..] + 634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** This section provides functions allowing to: + 635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Initialize and configure the TIM Output Compare. + 636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) De-initialize the TIM Output Compare. + 637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Start the TIM Output Compare. + 638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Stop the TIM Output Compare. + ARM GAS /tmp/ccl4b9YO.s page 30 + + + 639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Start the TIM Output Compare and enable interrupt. + 640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Stop the TIM Output Compare and disable interrupt. + 641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Start the TIM Output Compare and enable DMA transfer. + 642:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Stop the TIM Output Compare and disable DMA transfer. + 643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** @endverbatim + 645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @{ + 646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ + 647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** + 648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Initializes the TIM Output Compare according to the specified + 649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * parameters in the TIM_HandleTypeDef and initializes the associated handle. + 650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + 651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * requires a timer reset to avoid unexpected direction + 652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * due to DIR bit readonly in center aligned mode. + 653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() + 654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM Output Compare handle + 655:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status + 656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ + 657:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) + 658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 1030 .loc 1 658 1 + 1031 .cfi_startproc + 1032 @ args = 0, pretend = 0, frame = 8 + 1033 @ frame_needed = 1, uses_anonymous_args = 0 + 1034 0000 80B5 push {r7, lr} + 1035 .cfi_def_cfa_offset 8 + 1036 .cfi_offset 7, -8 + 1037 .cfi_offset 14, -4 + 1038 0002 82B0 sub sp, sp, #8 + 1039 .cfi_def_cfa_offset 16 + 1040 0004 00AF add r7, sp, #0 + 1041 .cfi_def_cfa_register 7 + 1042 0006 7860 str r0, [r7, #4] + 659:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the TIM handle allocation */ + 660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (htim == NULL) + 1043 .loc 1 660 6 + 1044 0008 7B68 ldr r3, [r7, #4] + 1045 000a 002B cmp r3, #0 + 1046 000c 01D1 bne .L56 + 661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 1047 .loc 1 662 12 + 1048 000e 0123 movs r3, #1 + 1049 0010 49E0 b .L57 + 1050 .L56: + 663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 664:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ + 666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_INSTANCE(htim->Instance)); + 667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + 668:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + 669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + 670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + 671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (htim->State == HAL_TIM_STATE_RESET) + 1051 .loc 1 672 11 + 1052 0012 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/ccl4b9YO.s page 31 + + + 1053 0014 93F83D30 ldrb r3, [r3, #61] + 1054 0018 DBB2 uxtb r3, r3 + 1055 .loc 1 672 6 + 1056 001a 002B cmp r3, #0 + 1057 001c 06D1 bne .L58 + 673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Allocate lock resource and initialize it */ + 675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Lock = HAL_UNLOCKED; + 1058 .loc 1 675 16 + 1059 001e 7B68 ldr r3, [r7, #4] + 1060 0020 0022 movs r2, #0 + 1061 0022 83F83C20 strb r2, [r3, #60] + 676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + 678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Reset interrupt callbacks to legacy weak callbacks */ + 679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_ResetCallback(htim); + 680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (htim->OC_MspInitCallback == NULL) + 682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; + 684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Init the low level hardware : GPIO, CLOCK, NVIC */ + 686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->OC_MspInitCallback(htim); + 687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #else + 688:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + 689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_OC_MspInit(htim); + 1062 .loc 1 689 5 + 1063 0026 7868 ldr r0, [r7, #4] + 1064 0028 FFF7FEFF bl HAL_TIM_OC_MspInit + 1065 .L58: + 690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the TIM state */ + 694:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; + 1066 .loc 1 694 15 + 1067 002c 7B68 ldr r3, [r7, #4] + 1068 002e 0222 movs r2, #2 + 1069 0030 83F83D20 strb r2, [r3, #61] + 695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Init the base time for the Output Compare */ + 697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_Base_SetConfig(htim->Instance, &htim->Init); + 1070 .loc 1 697 3 + 1071 0034 7B68 ldr r3, [r7, #4] + 1072 0036 1A68 ldr r2, [r3] + 1073 .loc 1 697 39 + 1074 0038 7B68 ldr r3, [r7, #4] + 1075 003a 0433 adds r3, r3, #4 + 1076 .loc 1 697 3 + 1077 003c 1946 mov r1, r3 + 1078 003e 1046 mov r0, r2 + 1079 0040 FFF7FEFF bl TIM_Base_SetConfig + 698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Initialize the DMA burst operation state */ + 700:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + 1080 .loc 1 700 23 + 1081 0044 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/ccl4b9YO.s page 32 + + + 1082 0046 0122 movs r2, #1 + 1083 0048 83F84820 strb r2, [r3, #72] + 701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Initialize the TIM channels state */ + 703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 1084 .loc 1 703 3 + 1085 004c 7B68 ldr r3, [r7, #4] + 1086 004e 0122 movs r2, #1 + 1087 0050 83F83E20 strb r2, [r3, #62] + 1088 0054 7B68 ldr r3, [r7, #4] + 1089 0056 0122 movs r2, #1 + 1090 0058 83F83F20 strb r2, [r3, #63] + 1091 005c 7B68 ldr r3, [r7, #4] + 1092 005e 0122 movs r2, #1 + 1093 0060 83F84020 strb r2, [r3, #64] + 1094 0064 7B68 ldr r3, [r7, #4] + 1095 0066 0122 movs r2, #1 + 1096 0068 83F84120 strb r2, [r3, #65] + 1097 006c 7B68 ldr r3, [r7, #4] + 1098 006e 0122 movs r2, #1 + 1099 0070 83F84220 strb r2, [r3, #66] + 1100 0074 7B68 ldr r3, [r7, #4] + 1101 0076 0122 movs r2, #1 + 1102 0078 83F84320 strb r2, [r3, #67] + 704:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 1103 .loc 1 704 3 + 1104 007c 7B68 ldr r3, [r7, #4] + 1105 007e 0122 movs r2, #1 + 1106 0080 83F84420 strb r2, [r3, #68] + 1107 0084 7B68 ldr r3, [r7, #4] + 1108 0086 0122 movs r2, #1 + 1109 0088 83F84520 strb r2, [r3, #69] + 1110 008c 7B68 ldr r3, [r7, #4] + 1111 008e 0122 movs r2, #1 + 1112 0090 83F84620 strb r2, [r3, #70] + 1113 0094 7B68 ldr r3, [r7, #4] + 1114 0096 0122 movs r2, #1 + 1115 0098 83F84720 strb r2, [r3, #71] + 705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 706:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Initialize the TIM state*/ + 707:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; + 1116 .loc 1 707 15 + 1117 009c 7B68 ldr r3, [r7, #4] + 1118 009e 0122 movs r2, #1 + 1119 00a0 83F83D20 strb r2, [r3, #61] + 708:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_OK; + 1120 .loc 1 709 10 + 1121 00a4 0023 movs r3, #0 + 1122 .L57: + 710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 1123 .loc 1 710 1 + 1124 00a6 1846 mov r0, r3 + 1125 00a8 0837 adds r7, r7, #8 + 1126 .cfi_def_cfa_offset 8 + 1127 00aa BD46 mov sp, r7 + 1128 .cfi_def_cfa_register 13 + ARM GAS /tmp/ccl4b9YO.s page 33 + + + 1129 @ sp needed + 1130 00ac 80BD pop {r7, pc} + 1131 .cfi_endproc + 1132 .LFE140: + 1134 .section .text.HAL_TIM_OC_DeInit,"ax",%progbits + 1135 .align 1 + 1136 .global HAL_TIM_OC_DeInit + 1137 .syntax unified + 1138 .thumb + 1139 .thumb_func + 1141 HAL_TIM_OC_DeInit: + 1142 .LFB141: + 711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** + 713:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief DeInitializes the TIM peripheral + 714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM Output Compare handle + 715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status + 716:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ + 717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) + 718:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 1143 .loc 1 718 1 + 1144 .cfi_startproc + 1145 @ args = 0, pretend = 0, frame = 8 + 1146 @ frame_needed = 1, uses_anonymous_args = 0 + 1147 0000 80B5 push {r7, lr} + 1148 .cfi_def_cfa_offset 8 + 1149 .cfi_offset 7, -8 + 1150 .cfi_offset 14, -4 + 1151 0002 82B0 sub sp, sp, #8 + 1152 .cfi_def_cfa_offset 16 + 1153 0004 00AF add r7, sp, #0 + 1154 .cfi_def_cfa_register 7 + 1155 0006 7860 str r0, [r7, #4] + 719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ + 720:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_INSTANCE(htim->Instance)); + 721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 722:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; + 1156 .loc 1 722 15 + 1157 0008 7B68 ldr r3, [r7, #4] + 1158 000a 0222 movs r2, #2 + 1159 000c 83F83D20 strb r2, [r3, #61] + 723:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 724:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the TIM Peripheral Clock */ + 725:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); + 1160 .loc 1 725 3 + 1161 0010 7B68 ldr r3, [r7, #4] + 1162 0012 1B68 ldr r3, [r3] + 1163 0014 1A6A ldr r2, [r3, #32] + 1164 0016 41F21113 movw r3, #4369 + 1165 001a 1340 ands r3, r3, r2 + 1166 001c 002B cmp r3, #0 + 1167 001e 0FD1 bne .L60 + 1168 .loc 1 725 3 is_stmt 0 discriminator 1 + 1169 0020 7B68 ldr r3, [r7, #4] + 1170 0022 1B68 ldr r3, [r3] + 1171 0024 1A6A ldr r2, [r3, #32] + 1172 0026 40F24443 movw r3, #1092 + ARM GAS /tmp/ccl4b9YO.s page 34 + + + 1173 002a 1340 ands r3, r3, r2 + 1174 002c 002B cmp r3, #0 + 1175 002e 07D1 bne .L60 + 1176 .loc 1 725 3 discriminator 2 + 1177 0030 7B68 ldr r3, [r7, #4] + 1178 0032 1B68 ldr r3, [r3] + 1179 0034 1A68 ldr r2, [r3] + 1180 0036 7B68 ldr r3, [r7, #4] + 1181 0038 1B68 ldr r3, [r3] + 1182 003a 22F00102 bic r2, r2, #1 + 1183 003e 1A60 str r2, [r3] + 1184 .L60: + 726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 727:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + 728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (htim->OC_MspDeInitCallback == NULL) + 729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; + 731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* DeInit the low level hardware */ + 733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->OC_MspDeInitCallback(htim); + 734:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #else + 735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + 736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_OC_MspDeInit(htim); + 1185 .loc 1 736 3 is_stmt 1 + 1186 0040 7868 ldr r0, [r7, #4] + 1187 0042 FFF7FEFF bl HAL_TIM_OC_MspDeInit + 737:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 739:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Change the DMA burst operation state */ + 740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + 1188 .loc 1 740 23 + 1189 0046 7B68 ldr r3, [r7, #4] + 1190 0048 0022 movs r2, #0 + 1191 004a 83F84820 strb r2, [r3, #72] + 741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Change the TIM channels state */ + 743:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + 1192 .loc 1 743 3 + 1193 004e 7B68 ldr r3, [r7, #4] + 1194 0050 0022 movs r2, #0 + 1195 0052 83F83E20 strb r2, [r3, #62] + 1196 0056 7B68 ldr r3, [r7, #4] + 1197 0058 0022 movs r2, #0 + 1198 005a 83F83F20 strb r2, [r3, #63] + 1199 005e 7B68 ldr r3, [r7, #4] + 1200 0060 0022 movs r2, #0 + 1201 0062 83F84020 strb r2, [r3, #64] + 1202 0066 7B68 ldr r3, [r7, #4] + 1203 0068 0022 movs r2, #0 + 1204 006a 83F84120 strb r2, [r3, #65] + 1205 006e 7B68 ldr r3, [r7, #4] + 1206 0070 0022 movs r2, #0 + 1207 0072 83F84220 strb r2, [r3, #66] + 1208 0076 7B68 ldr r3, [r7, #4] + 1209 0078 0022 movs r2, #0 + 1210 007a 83F84320 strb r2, [r3, #67] + 744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + ARM GAS /tmp/ccl4b9YO.s page 35 + + + 1211 .loc 1 744 3 + 1212 007e 7B68 ldr r3, [r7, #4] + 1213 0080 0022 movs r2, #0 + 1214 0082 83F84420 strb r2, [r3, #68] + 1215 0086 7B68 ldr r3, [r7, #4] + 1216 0088 0022 movs r2, #0 + 1217 008a 83F84520 strb r2, [r3, #69] + 1218 008e 7B68 ldr r3, [r7, #4] + 1219 0090 0022 movs r2, #0 + 1220 0092 83F84620 strb r2, [r3, #70] + 1221 0096 7B68 ldr r3, [r7, #4] + 1222 0098 0022 movs r2, #0 + 1223 009a 83F84720 strb r2, [r3, #71] + 745:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 746:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Change TIM state */ + 747:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->State = HAL_TIM_STATE_RESET; + 1224 .loc 1 747 15 + 1225 009e 7B68 ldr r3, [r7, #4] + 1226 00a0 0022 movs r2, #0 + 1227 00a2 83F83D20 strb r2, [r3, #61] + 748:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Release Lock */ + 750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_UNLOCK(htim); + 1228 .loc 1 750 3 + 1229 00a6 7B68 ldr r3, [r7, #4] + 1230 00a8 0022 movs r2, #0 + 1231 00aa 83F83C20 strb r2, [r3, #60] + 751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 752:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_OK; + 1232 .loc 1 752 10 + 1233 00ae 0023 movs r3, #0 + 753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 1234 .loc 1 753 1 + 1235 00b0 1846 mov r0, r3 + 1236 00b2 0837 adds r7, r7, #8 + 1237 .cfi_def_cfa_offset 8 + 1238 00b4 BD46 mov sp, r7 + 1239 .cfi_def_cfa_register 13 + 1240 @ sp needed + 1241 00b6 80BD pop {r7, pc} + 1242 .cfi_endproc + 1243 .LFE141: + 1245 .section .text.HAL_TIM_OC_MspInit,"ax",%progbits + 1246 .align 1 + 1247 .weak HAL_TIM_OC_MspInit + 1248 .syntax unified + 1249 .thumb + 1250 .thumb_func + 1252 HAL_TIM_OC_MspInit: + 1253 .LFB142: + 754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 755:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** + 756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Initializes the TIM Output Compare MSP. + 757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM Output Compare handle + 758:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval None + 759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ + 760:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) + ARM GAS /tmp/ccl4b9YO.s page 36 + + + 761:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 1254 .loc 1 761 1 + 1255 .cfi_startproc + 1256 @ args = 0, pretend = 0, frame = 8 + 1257 @ frame_needed = 1, uses_anonymous_args = 0 + 1258 @ link register save eliminated. + 1259 0000 80B4 push {r7} + 1260 .cfi_def_cfa_offset 4 + 1261 .cfi_offset 7, -4 + 1262 0002 83B0 sub sp, sp, #12 + 1263 .cfi_def_cfa_offset 16 + 1264 0004 00AF add r7, sp, #0 + 1265 .cfi_def_cfa_register 7 + 1266 0006 7860 str r0, [r7, #4] + 762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** UNUSED(htim); + 764:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* NOTE : This function should not be modified, when the callback is needed, + 766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** the HAL_TIM_OC_MspInit could be implemented in the user file + 767:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ + 768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 1267 .loc 1 768 1 + 1268 0008 00BF nop + 1269 000a 0C37 adds r7, r7, #12 + 1270 .cfi_def_cfa_offset 4 + 1271 000c BD46 mov sp, r7 + 1272 .cfi_def_cfa_register 13 + 1273 @ sp needed + 1274 000e 5DF8047B ldr r7, [sp], #4 + 1275 .cfi_restore 7 + 1276 .cfi_def_cfa_offset 0 + 1277 0012 7047 bx lr + 1278 .cfi_endproc + 1279 .LFE142: + 1281 .section .text.HAL_TIM_OC_MspDeInit,"ax",%progbits + 1282 .align 1 + 1283 .weak HAL_TIM_OC_MspDeInit + 1284 .syntax unified + 1285 .thumb + 1286 .thumb_func + 1288 HAL_TIM_OC_MspDeInit: + 1289 .LFB143: + 769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** + 771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief DeInitializes TIM Output Compare MSP. + 772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM Output Compare handle + 773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval None + 774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ + 775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) + 776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 1290 .loc 1 776 1 + 1291 .cfi_startproc + 1292 @ args = 0, pretend = 0, frame = 8 + 1293 @ frame_needed = 1, uses_anonymous_args = 0 + 1294 @ link register save eliminated. + 1295 0000 80B4 push {r7} + 1296 .cfi_def_cfa_offset 4 + ARM GAS /tmp/ccl4b9YO.s page 37 + + + 1297 .cfi_offset 7, -4 + 1298 0002 83B0 sub sp, sp, #12 + 1299 .cfi_def_cfa_offset 16 + 1300 0004 00AF add r7, sp, #0 + 1301 .cfi_def_cfa_register 7 + 1302 0006 7860 str r0, [r7, #4] + 777:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ + 778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** UNUSED(htim); + 779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 780:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* NOTE : This function should not be modified, when the callback is needed, + 781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** the HAL_TIM_OC_MspDeInit could be implemented in the user file + 782:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ + 783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 1303 .loc 1 783 1 + 1304 0008 00BF nop + 1305 000a 0C37 adds r7, r7, #12 + 1306 .cfi_def_cfa_offset 4 + 1307 000c BD46 mov sp, r7 + 1308 .cfi_def_cfa_register 13 + 1309 @ sp needed + 1310 000e 5DF8047B ldr r7, [sp], #4 + 1311 .cfi_restore 7 + 1312 .cfi_def_cfa_offset 0 + 1313 0012 7047 bx lr + 1314 .cfi_endproc + 1315 .LFE143: + 1317 .section .text.HAL_TIM_OC_Start,"ax",%progbits + 1318 .align 1 + 1319 .global HAL_TIM_OC_Start + 1320 .syntax unified + 1321 .thumb + 1322 .thumb_func + 1324 HAL_TIM_OC_Start: + 1325 .LFB144: + 784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** + 786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Starts the TIM Output Compare signal generation. + 787:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM Output Compare handle + 788:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param Channel TIM Channel to be enabled + 789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: + 790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected + 791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected + 792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected + 793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected + 794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) + 795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) + 796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * (*) Value not defined for all devices + 797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status + 798:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ + 799:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) + 800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 1326 .loc 1 800 1 + 1327 .cfi_startproc + 1328 @ args = 0, pretend = 0, frame = 16 + 1329 @ frame_needed = 1, uses_anonymous_args = 0 + 1330 0000 80B5 push {r7, lr} + 1331 .cfi_def_cfa_offset 8 + ARM GAS /tmp/ccl4b9YO.s page 38 + + + 1332 .cfi_offset 7, -8 + 1333 .cfi_offset 14, -4 + 1334 0002 84B0 sub sp, sp, #16 + 1335 .cfi_def_cfa_offset 24 + 1336 0004 00AF add r7, sp, #0 + 1337 .cfi_def_cfa_register 7 + 1338 0006 7860 str r0, [r7, #4] + 1339 0008 3960 str r1, [r7] + 801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpsmcr; + 802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 803:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ + 804:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + 805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 806:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the TIM channel state */ + 807:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + 1340 .loc 1 807 44 + 1341 000a 3B68 ldr r3, [r7] + 1342 000c 002B cmp r3, #0 + 1343 000e 09D1 bne .L65 + 1344 .loc 1 807 7 discriminator 1 + 1345 0010 7B68 ldr r3, [r7, #4] + 1346 0012 93F83E30 ldrb r3, [r3, #62] + 1347 0016 DBB2 uxtb r3, r3 + 1348 .loc 1 807 44 discriminator 1 + 1349 0018 012B cmp r3, #1 + 1350 001a 14BF ite ne + 1351 001c 0123 movne r3, #1 + 1352 001e 0023 moveq r3, #0 + 1353 0020 DBB2 uxtb r3, r3 + 1354 0022 3CE0 b .L66 + 1355 .L65: + 1356 .loc 1 807 44 is_stmt 0 discriminator 2 + 1357 0024 3B68 ldr r3, [r7] + 1358 0026 042B cmp r3, #4 + 1359 0028 09D1 bne .L67 + 1360 .loc 1 807 7 is_stmt 1 discriminator 4 + 1361 002a 7B68 ldr r3, [r7, #4] + 1362 002c 93F83F30 ldrb r3, [r3, #63] + 1363 0030 DBB2 uxtb r3, r3 + 1364 .loc 1 807 44 discriminator 4 + 1365 0032 012B cmp r3, #1 + 1366 0034 14BF ite ne + 1367 0036 0123 movne r3, #1 + 1368 0038 0023 moveq r3, #0 + 1369 003a DBB2 uxtb r3, r3 + 1370 003c 2FE0 b .L66 + 1371 .L67: + 1372 .loc 1 807 44 is_stmt 0 discriminator 5 + 1373 003e 3B68 ldr r3, [r7] + 1374 0040 082B cmp r3, #8 + 1375 0042 09D1 bne .L69 + 1376 .loc 1 807 7 is_stmt 1 discriminator 7 + 1377 0044 7B68 ldr r3, [r7, #4] + 1378 0046 93F84030 ldrb r3, [r3, #64] + 1379 004a DBB2 uxtb r3, r3 + 1380 .loc 1 807 44 discriminator 7 + 1381 004c 012B cmp r3, #1 + ARM GAS /tmp/ccl4b9YO.s page 39 + + + 1382 004e 14BF ite ne + 1383 0050 0123 movne r3, #1 + 1384 0052 0023 moveq r3, #0 + 1385 0054 DBB2 uxtb r3, r3 + 1386 0056 22E0 b .L66 + 1387 .L69: + 1388 .loc 1 807 44 is_stmt 0 discriminator 8 + 1389 0058 3B68 ldr r3, [r7] + 1390 005a 0C2B cmp r3, #12 + 1391 005c 09D1 bne .L71 + 1392 .loc 1 807 7 is_stmt 1 discriminator 10 + 1393 005e 7B68 ldr r3, [r7, #4] + 1394 0060 93F84130 ldrb r3, [r3, #65] + 1395 0064 DBB2 uxtb r3, r3 + 1396 .loc 1 807 44 discriminator 10 + 1397 0066 012B cmp r3, #1 + 1398 0068 14BF ite ne + 1399 006a 0123 movne r3, #1 + 1400 006c 0023 moveq r3, #0 + 1401 006e DBB2 uxtb r3, r3 + 1402 0070 15E0 b .L66 + 1403 .L71: + 1404 .loc 1 807 44 is_stmt 0 discriminator 11 + 1405 0072 3B68 ldr r3, [r7] + 1406 0074 102B cmp r3, #16 + 1407 0076 09D1 bne .L73 + 1408 .loc 1 807 7 is_stmt 1 discriminator 13 + 1409 0078 7B68 ldr r3, [r7, #4] + 1410 007a 93F84230 ldrb r3, [r3, #66] + 1411 007e DBB2 uxtb r3, r3 + 1412 .loc 1 807 44 discriminator 13 + 1413 0080 012B cmp r3, #1 + 1414 0082 14BF ite ne + 1415 0084 0123 movne r3, #1 + 1416 0086 0023 moveq r3, #0 + 1417 0088 DBB2 uxtb r3, r3 + 1418 008a 08E0 b .L66 + 1419 .L73: + 1420 .loc 1 807 7 discriminator 14 + 1421 008c 7B68 ldr r3, [r7, #4] + 1422 008e 93F84330 ldrb r3, [r3, #67] + 1423 0092 DBB2 uxtb r3, r3 + 1424 .loc 1 807 44 discriminator 14 + 1425 0094 012B cmp r3, #1 + 1426 0096 14BF ite ne + 1427 0098 0123 movne r3, #1 + 1428 009a 0023 moveq r3, #0 + 1429 009c DBB2 uxtb r3, r3 + 1430 .L66: + 1431 .loc 1 807 6 discriminator 20 + 1432 009e 002B cmp r3, #0 + 1433 00a0 01D0 beq .L75 + 808:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 1434 .loc 1 809 12 + 1435 00a2 0123 movs r3, #1 + 1436 00a4 8DE0 b .L76 + ARM GAS /tmp/ccl4b9YO.s page 40 + + + 1437 .L75: + 810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 811:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the TIM channel state */ + 813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + 1438 .loc 1 813 3 + 1439 00a6 3B68 ldr r3, [r7] + 1440 00a8 002B cmp r3, #0 + 1441 00aa 04D1 bne .L77 + 1442 .loc 1 813 3 is_stmt 0 discriminator 1 + 1443 00ac 7B68 ldr r3, [r7, #4] + 1444 00ae 0222 movs r2, #2 + 1445 00b0 83F83E20 strb r2, [r3, #62] + 1446 00b4 23E0 b .L78 + 1447 .L77: + 1448 .loc 1 813 3 discriminator 2 + 1449 00b6 3B68 ldr r3, [r7] + 1450 00b8 042B cmp r3, #4 + 1451 00ba 04D1 bne .L79 + 1452 .loc 1 813 3 discriminator 3 + 1453 00bc 7B68 ldr r3, [r7, #4] + 1454 00be 0222 movs r2, #2 + 1455 00c0 83F83F20 strb r2, [r3, #63] + 1456 00c4 1BE0 b .L78 + 1457 .L79: + 1458 .loc 1 813 3 discriminator 4 + 1459 00c6 3B68 ldr r3, [r7] + 1460 00c8 082B cmp r3, #8 + 1461 00ca 04D1 bne .L81 + 1462 .loc 1 813 3 discriminator 6 + 1463 00cc 7B68 ldr r3, [r7, #4] + 1464 00ce 0222 movs r2, #2 + 1465 00d0 83F84020 strb r2, [r3, #64] + 1466 00d4 13E0 b .L78 + 1467 .L81: + 1468 .loc 1 813 3 discriminator 7 + 1469 00d6 3B68 ldr r3, [r7] + 1470 00d8 0C2B cmp r3, #12 + 1471 00da 04D1 bne .L83 + 1472 .loc 1 813 3 discriminator 9 + 1473 00dc 7B68 ldr r3, [r7, #4] + 1474 00de 0222 movs r2, #2 + 1475 00e0 83F84120 strb r2, [r3, #65] + 1476 00e4 0BE0 b .L78 + 1477 .L83: + 1478 .loc 1 813 3 discriminator 10 + 1479 00e6 3B68 ldr r3, [r7] + 1480 00e8 102B cmp r3, #16 + 1481 00ea 04D1 bne .L85 + 1482 .loc 1 813 3 discriminator 12 + 1483 00ec 7B68 ldr r3, [r7, #4] + 1484 00ee 0222 movs r2, #2 + 1485 00f0 83F84220 strb r2, [r3, #66] + 1486 00f4 03E0 b .L78 + 1487 .L85: + 1488 .loc 1 813 3 discriminator 13 + 1489 00f6 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/ccl4b9YO.s page 41 + + + 1490 00f8 0222 movs r2, #2 + 1491 00fa 83F84320 strb r2, [r3, #67] + 1492 .L78: + 814:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the Output compare channel */ + 816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + 1493 .loc 1 816 3 is_stmt 1 + 1494 00fe 7B68 ldr r3, [r7, #4] + 1495 0100 1B68 ldr r3, [r3] + 1496 0102 0122 movs r2, #1 + 1497 0104 3968 ldr r1, [r7] + 1498 0106 1846 mov r0, r3 + 1499 0108 FFF7FEFF bl TIM_CCxChannelCmd + 817:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 818:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + 1500 .loc 1 818 7 + 1501 010c 7B68 ldr r3, [r7, #4] + 1502 010e 1B68 ldr r3, [r3] + 1503 0110 2E4A ldr r2, .L96 + 1504 0112 9342 cmp r3, r2 + 1505 0114 0ED0 beq .L87 + 1506 .loc 1 818 7 is_stmt 0 discriminator 2 + 1507 0116 7B68 ldr r3, [r7, #4] + 1508 0118 1B68 ldr r3, [r3] + 1509 011a 2D4A ldr r2, .L96+4 + 1510 011c 9342 cmp r3, r2 + 1511 011e 09D0 beq .L87 + 1512 .loc 1 818 7 discriminator 4 + 1513 0120 7B68 ldr r3, [r7, #4] + 1514 0122 1B68 ldr r3, [r3] + 1515 0124 2B4A ldr r2, .L96+8 + 1516 0126 9342 cmp r3, r2 + 1517 0128 04D0 beq .L87 + 1518 .loc 1 818 7 discriminator 6 + 1519 012a 7B68 ldr r3, [r7, #4] + 1520 012c 1B68 ldr r3, [r3] + 1521 012e 2A4A ldr r2, .L96+12 + 1522 0130 9342 cmp r3, r2 + 1523 0132 01D1 bne .L88 + 1524 .L87: + 1525 .loc 1 818 7 discriminator 7 + 1526 0134 0123 movs r3, #1 + 1527 .loc 1 818 7 + 1528 0136 00E0 b .L89 + 1529 .L88: + 1530 .loc 1 818 7 discriminator 8 + 1531 0138 0023 movs r3, #0 + 1532 .L89: + 1533 .loc 1 818 6 is_stmt 1 discriminator 10 + 1534 013a 002B cmp r3, #0 + 1535 013c 07D0 beq .L90 + 819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 820:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the main output */ + 821:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_MOE_ENABLE(htim); + 1536 .loc 1 821 5 + 1537 013e 7B68 ldr r3, [r7, #4] + 1538 0140 1B68 ldr r3, [r3] + ARM GAS /tmp/ccl4b9YO.s page 42 + + + 1539 0142 5A6C ldr r2, [r3, #68] + 1540 0144 7B68 ldr r3, [r7, #4] + 1541 0146 1B68 ldr r3, [r3] + 1542 0148 42F40042 orr r2, r2, #32768 + 1543 014c 5A64 str r2, [r3, #68] + 1544 .L90: + 822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger + 825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 1545 .loc 1 825 7 + 1546 014e 7B68 ldr r3, [r7, #4] + 1547 0150 1B68 ldr r3, [r3] + 1548 .loc 1 825 6 + 1549 0152 1E4A ldr r2, .L96 + 1550 0154 9342 cmp r3, r2 + 1551 0156 13D0 beq .L91 + 1552 .loc 1 825 7 discriminator 1 + 1553 0158 7B68 ldr r3, [r7, #4] + 1554 015a 1B68 ldr r3, [r3] + 1555 015c B3F1804F cmp r3, #1073741824 + 1556 0160 0ED0 beq .L91 + 1557 .loc 1 825 7 is_stmt 0 discriminator 2 + 1558 0162 7B68 ldr r3, [r7, #4] + 1559 0164 1B68 ldr r3, [r3] + 1560 0166 1D4A ldr r2, .L96+16 + 1561 0168 9342 cmp r3, r2 + 1562 016a 09D0 beq .L91 + 1563 .loc 1 825 7 discriminator 3 + 1564 016c 7B68 ldr r3, [r7, #4] + 1565 016e 1B68 ldr r3, [r3] + 1566 0170 1B4A ldr r2, .L96+20 + 1567 0172 9342 cmp r3, r2 + 1568 0174 04D0 beq .L91 + 1569 .loc 1 825 7 discriminator 4 + 1570 0176 7B68 ldr r3, [r7, #4] + 1571 0178 1B68 ldr r3, [r3] + 1572 017a 154A ldr r2, .L96+4 + 1573 017c 9342 cmp r3, r2 + 1574 017e 15D1 bne .L92 + 1575 .L91: + 826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 827:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + 1576 .loc 1 827 19 is_stmt 1 + 1577 0180 7B68 ldr r3, [r7, #4] + 1578 0182 1B68 ldr r3, [r3] + 1579 .loc 1 827 29 + 1580 0184 9A68 ldr r2, [r3, #8] + 1581 .loc 1 827 13 + 1582 0186 174B ldr r3, .L96+24 + 1583 0188 1340 ands r3, r3, r2 + 1584 018a FB60 str r3, [r7, #12] + 828:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 1585 .loc 1 828 8 + 1586 018c FB68 ldr r3, [r7, #12] + 1587 018e 062B cmp r3, #6 + 1588 0190 15D0 beq .L95 + ARM GAS /tmp/ccl4b9YO.s page 43 + + + 1589 .loc 1 828 9 discriminator 1 + 1590 0192 FB68 ldr r3, [r7, #12] + 1591 0194 B3F5803F cmp r3, #65536 + 1592 0198 11D0 beq .L95 + 829:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 830:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); + 1593 .loc 1 830 7 + 1594 019a 7B68 ldr r3, [r7, #4] + 1595 019c 1B68 ldr r3, [r3] + 1596 019e 1A68 ldr r2, [r3] + 1597 01a0 7B68 ldr r3, [r7, #4] + 1598 01a2 1B68 ldr r3, [r3] + 1599 01a4 42F00102 orr r2, r2, #1 + 1600 01a8 1A60 str r2, [r3] + 828:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 1601 .loc 1 828 8 + 1602 01aa 08E0 b .L95 + 1603 .L92: + 831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 832:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else + 834:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 835:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); + 1604 .loc 1 835 5 + 1605 01ac 7B68 ldr r3, [r7, #4] + 1606 01ae 1B68 ldr r3, [r3] + 1607 01b0 1A68 ldr r2, [r3] + 1608 01b2 7B68 ldr r3, [r7, #4] + 1609 01b4 1B68 ldr r3, [r3] + 1610 01b6 42F00102 orr r2, r2, #1 + 1611 01ba 1A60 str r2, [r3] + 1612 01bc 00E0 b .L94 + 1613 .L95: + 828:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 1614 .loc 1 828 8 + 1615 01be 00BF nop + 1616 .L94: + 836:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return function status */ + 839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_OK; + 1617 .loc 1 839 10 + 1618 01c0 0023 movs r3, #0 + 1619 .L76: + 840:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 1620 .loc 1 840 1 + 1621 01c2 1846 mov r0, r3 + 1622 01c4 1037 adds r7, r7, #16 + 1623 .cfi_def_cfa_offset 8 + 1624 01c6 BD46 mov sp, r7 + 1625 .cfi_def_cfa_register 13 + 1626 @ sp needed + 1627 01c8 80BD pop {r7, pc} + 1628 .L97: + 1629 01ca 00BF .align 2 + 1630 .L96: + 1631 01cc 002C0140 .word 1073818624 + ARM GAS /tmp/ccl4b9YO.s page 44 + + + 1632 01d0 00400140 .word 1073823744 + 1633 01d4 00440140 .word 1073824768 + 1634 01d8 00480140 .word 1073825792 + 1635 01dc 00040040 .word 1073742848 + 1636 01e0 00080040 .word 1073743872 + 1637 01e4 07000100 .word 65543 + 1638 .cfi_endproc + 1639 .LFE144: + 1641 .section .text.HAL_TIM_OC_Stop,"ax",%progbits + 1642 .align 1 + 1643 .global HAL_TIM_OC_Stop + 1644 .syntax unified + 1645 .thumb + 1646 .thumb_func + 1648 HAL_TIM_OC_Stop: + 1649 .LFB145: + 841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 842:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** + 843:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Stops the TIM Output Compare signal generation. + 844:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM Output Compare handle + 845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param Channel TIM Channel to be disabled + 846:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: + 847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected + 848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected + 849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected + 850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected + 851:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) + 852:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) + 853:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * (*) Value not defined for all devices + 854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status + 855:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ + 856:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) + 857:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 1650 .loc 1 857 1 + 1651 .cfi_startproc + 1652 @ args = 0, pretend = 0, frame = 8 + 1653 @ frame_needed = 1, uses_anonymous_args = 0 + 1654 0000 80B5 push {r7, lr} + 1655 .cfi_def_cfa_offset 8 + 1656 .cfi_offset 7, -8 + 1657 .cfi_offset 14, -4 + 1658 0002 82B0 sub sp, sp, #8 + 1659 .cfi_def_cfa_offset 16 + 1660 0004 00AF add r7, sp, #0 + 1661 .cfi_def_cfa_register 7 + 1662 0006 7860 str r0, [r7, #4] + 1663 0008 3960 str r1, [r7] + 858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ + 859:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + 860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the Output compare channel */ + 862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + 1664 .loc 1 862 3 + 1665 000a 7B68 ldr r3, [r7, #4] + 1666 000c 1B68 ldr r3, [r3] + 1667 000e 0022 movs r2, #0 + 1668 0010 3968 ldr r1, [r7] + ARM GAS /tmp/ccl4b9YO.s page 45 + + + 1669 0012 1846 mov r0, r3 + 1670 0014 FFF7FEFF bl TIM_CCxChannelCmd + 863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 864:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + 1671 .loc 1 864 7 + 1672 0018 7B68 ldr r3, [r7, #4] + 1673 001a 1B68 ldr r3, [r3] + 1674 001c 3B4A ldr r2, .L115 + 1675 001e 9342 cmp r3, r2 + 1676 0020 0ED0 beq .L99 + 1677 .loc 1 864 7 is_stmt 0 discriminator 2 + 1678 0022 7B68 ldr r3, [r7, #4] + 1679 0024 1B68 ldr r3, [r3] + 1680 0026 3A4A ldr r2, .L115+4 + 1681 0028 9342 cmp r3, r2 + 1682 002a 09D0 beq .L99 + 1683 .loc 1 864 7 discriminator 4 + 1684 002c 7B68 ldr r3, [r7, #4] + 1685 002e 1B68 ldr r3, [r3] + 1686 0030 384A ldr r2, .L115+8 + 1687 0032 9342 cmp r3, r2 + 1688 0034 04D0 beq .L99 + 1689 .loc 1 864 7 discriminator 6 + 1690 0036 7B68 ldr r3, [r7, #4] + 1691 0038 1B68 ldr r3, [r3] + 1692 003a 374A ldr r2, .L115+12 + 1693 003c 9342 cmp r3, r2 + 1694 003e 01D1 bne .L100 + 1695 .L99: + 1696 .loc 1 864 7 discriminator 7 + 1697 0040 0123 movs r3, #1 + 1698 .loc 1 864 7 + 1699 0042 00E0 b .L101 + 1700 .L100: + 1701 .loc 1 864 7 discriminator 8 + 1702 0044 0023 movs r3, #0 + 1703 .L101: + 1704 .loc 1 864 6 is_stmt 1 discriminator 10 + 1705 0046 002B cmp r3, #0 + 1706 0048 17D0 beq .L102 + 865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the Main Output */ + 867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_MOE_DISABLE(htim); + 1707 .loc 1 867 5 + 1708 004a 7B68 ldr r3, [r7, #4] + 1709 004c 1B68 ldr r3, [r3] + 1710 004e 1A6A ldr r2, [r3, #32] + 1711 0050 41F21113 movw r3, #4369 + 1712 0054 1340 ands r3, r3, r2 + 1713 0056 002B cmp r3, #0 + 1714 0058 0FD1 bne .L102 + 1715 .loc 1 867 5 is_stmt 0 discriminator 1 + 1716 005a 7B68 ldr r3, [r7, #4] + 1717 005c 1B68 ldr r3, [r3] + 1718 005e 1A6A ldr r2, [r3, #32] + 1719 0060 40F24443 movw r3, #1092 + 1720 0064 1340 ands r3, r3, r2 + ARM GAS /tmp/ccl4b9YO.s page 46 + + + 1721 0066 002B cmp r3, #0 + 1722 0068 07D1 bne .L102 + 1723 .loc 1 867 5 discriminator 2 + 1724 006a 7B68 ldr r3, [r7, #4] + 1725 006c 1B68 ldr r3, [r3] + 1726 006e 5A6C ldr r2, [r3, #68] + 1727 0070 7B68 ldr r3, [r7, #4] + 1728 0072 1B68 ldr r3, [r3] + 1729 0074 22F40042 bic r2, r2, #32768 + 1730 0078 5A64 str r2, [r3, #68] + 1731 .L102: + 868:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 870:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the Peripheral */ + 871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); + 1732 .loc 1 871 3 is_stmt 1 + 1733 007a 7B68 ldr r3, [r7, #4] + 1734 007c 1B68 ldr r3, [r3] + 1735 007e 1A6A ldr r2, [r3, #32] + 1736 0080 41F21113 movw r3, #4369 + 1737 0084 1340 ands r3, r3, r2 + 1738 0086 002B cmp r3, #0 + 1739 0088 0FD1 bne .L103 + 1740 .loc 1 871 3 is_stmt 0 discriminator 1 + 1741 008a 7B68 ldr r3, [r7, #4] + 1742 008c 1B68 ldr r3, [r3] + 1743 008e 1A6A ldr r2, [r3, #32] + 1744 0090 40F24443 movw r3, #1092 + 1745 0094 1340 ands r3, r3, r2 + 1746 0096 002B cmp r3, #0 + 1747 0098 07D1 bne .L103 + 1748 .loc 1 871 3 discriminator 2 + 1749 009a 7B68 ldr r3, [r7, #4] + 1750 009c 1B68 ldr r3, [r3] + 1751 009e 1A68 ldr r2, [r3] + 1752 00a0 7B68 ldr r3, [r7, #4] + 1753 00a2 1B68 ldr r3, [r3] + 1754 00a4 22F00102 bic r2, r2, #1 + 1755 00a8 1A60 str r2, [r3] + 1756 .L103: + 872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 873:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the TIM channel state */ + 874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 1757 .loc 1 874 3 is_stmt 1 + 1758 00aa 3B68 ldr r3, [r7] + 1759 00ac 002B cmp r3, #0 + 1760 00ae 04D1 bne .L104 + 1761 .loc 1 874 3 is_stmt 0 discriminator 1 + 1762 00b0 7B68 ldr r3, [r7, #4] + 1763 00b2 0122 movs r2, #1 + 1764 00b4 83F83E20 strb r2, [r3, #62] + 1765 00b8 23E0 b .L105 + 1766 .L104: + 1767 .loc 1 874 3 discriminator 2 + 1768 00ba 3B68 ldr r3, [r7] + 1769 00bc 042B cmp r3, #4 + 1770 00be 04D1 bne .L106 + ARM GAS /tmp/ccl4b9YO.s page 47 + + + 1771 .loc 1 874 3 discriminator 3 + 1772 00c0 7B68 ldr r3, [r7, #4] + 1773 00c2 0122 movs r2, #1 + 1774 00c4 83F83F20 strb r2, [r3, #63] + 1775 00c8 1BE0 b .L105 + 1776 .L106: + 1777 .loc 1 874 3 discriminator 4 + 1778 00ca 3B68 ldr r3, [r7] + 1779 00cc 082B cmp r3, #8 + 1780 00ce 04D1 bne .L108 + 1781 .loc 1 874 3 discriminator 6 + 1782 00d0 7B68 ldr r3, [r7, #4] + 1783 00d2 0122 movs r2, #1 + 1784 00d4 83F84020 strb r2, [r3, #64] + 1785 00d8 13E0 b .L105 + 1786 .L108: + 1787 .loc 1 874 3 discriminator 7 + 1788 00da 3B68 ldr r3, [r7] + 1789 00dc 0C2B cmp r3, #12 + 1790 00de 04D1 bne .L110 + 1791 .loc 1 874 3 discriminator 9 + 1792 00e0 7B68 ldr r3, [r7, #4] + 1793 00e2 0122 movs r2, #1 + 1794 00e4 83F84120 strb r2, [r3, #65] + 1795 00e8 0BE0 b .L105 + 1796 .L110: + 1797 .loc 1 874 3 discriminator 10 + 1798 00ea 3B68 ldr r3, [r7] + 1799 00ec 102B cmp r3, #16 + 1800 00ee 04D1 bne .L112 + 1801 .loc 1 874 3 discriminator 12 + 1802 00f0 7B68 ldr r3, [r7, #4] + 1803 00f2 0122 movs r2, #1 + 1804 00f4 83F84220 strb r2, [r3, #66] + 1805 00f8 03E0 b .L105 + 1806 .L112: + 1807 .loc 1 874 3 discriminator 13 + 1808 00fa 7B68 ldr r3, [r7, #4] + 1809 00fc 0122 movs r2, #1 + 1810 00fe 83F84320 strb r2, [r3, #67] + 1811 .L105: + 875:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return function status */ + 877:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_OK; + 1812 .loc 1 877 10 is_stmt 1 + 1813 0102 0023 movs r3, #0 + 878:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 1814 .loc 1 878 1 + 1815 0104 1846 mov r0, r3 + 1816 0106 0837 adds r7, r7, #8 + 1817 .cfi_def_cfa_offset 8 + 1818 0108 BD46 mov sp, r7 + 1819 .cfi_def_cfa_register 13 + 1820 @ sp needed + 1821 010a 80BD pop {r7, pc} + 1822 .L116: + 1823 .align 2 + ARM GAS /tmp/ccl4b9YO.s page 48 + + + 1824 .L115: + 1825 010c 002C0140 .word 1073818624 + 1826 0110 00400140 .word 1073823744 + 1827 0114 00440140 .word 1073824768 + 1828 0118 00480140 .word 1073825792 + 1829 .cfi_endproc + 1830 .LFE145: + 1832 .section .text.HAL_TIM_OC_Start_IT,"ax",%progbits + 1833 .align 1 + 1834 .global HAL_TIM_OC_Start_IT + 1835 .syntax unified + 1836 .thumb + 1837 .thumb_func + 1839 HAL_TIM_OC_Start_IT: + 1840 .LFB146: + 879:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** + 881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Starts the TIM Output Compare signal generation in interrupt mode. + 882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM Output Compare handle + 883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param Channel TIM Channel to be enabled + 884:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: + 885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected + 886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected + 887:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected + 888:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected + 889:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status + 890:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ + 891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) + 892:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 1841 .loc 1 892 1 + 1842 .cfi_startproc + 1843 @ args = 0, pretend = 0, frame = 16 + 1844 @ frame_needed = 1, uses_anonymous_args = 0 + 1845 0000 80B5 push {r7, lr} + 1846 .cfi_def_cfa_offset 8 + 1847 .cfi_offset 7, -8 + 1848 .cfi_offset 14, -4 + 1849 0002 84B0 sub sp, sp, #16 + 1850 .cfi_def_cfa_offset 24 + 1851 0004 00AF add r7, sp, #0 + 1852 .cfi_def_cfa_register 7 + 1853 0006 7860 str r0, [r7, #4] + 1854 0008 3960 str r1, [r7] + 893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 1855 .loc 1 893 21 + 1856 000a 0023 movs r3, #0 + 1857 000c FB73 strb r3, [r7, #15] + 894:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpsmcr; + 895:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ + 897:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + 898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 899:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the TIM channel state */ + 900:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + 1858 .loc 1 900 44 + 1859 000e 3B68 ldr r3, [r7] + 1860 0010 002B cmp r3, #0 + ARM GAS /tmp/ccl4b9YO.s page 49 + + + 1861 0012 09D1 bne .L118 + 1862 .loc 1 900 7 discriminator 1 + 1863 0014 7B68 ldr r3, [r7, #4] + 1864 0016 93F83E30 ldrb r3, [r3, #62] + 1865 001a DBB2 uxtb r3, r3 + 1866 .loc 1 900 44 discriminator 1 + 1867 001c 012B cmp r3, #1 + 1868 001e 14BF ite ne + 1869 0020 0123 movne r3, #1 + 1870 0022 0023 moveq r3, #0 + 1871 0024 DBB2 uxtb r3, r3 + 1872 0026 3CE0 b .L119 + 1873 .L118: + 1874 .loc 1 900 44 is_stmt 0 discriminator 2 + 1875 0028 3B68 ldr r3, [r7] + 1876 002a 042B cmp r3, #4 + 1877 002c 09D1 bne .L120 + 1878 .loc 1 900 7 is_stmt 1 discriminator 4 + 1879 002e 7B68 ldr r3, [r7, #4] + 1880 0030 93F83F30 ldrb r3, [r3, #63] + 1881 0034 DBB2 uxtb r3, r3 + 1882 .loc 1 900 44 discriminator 4 + 1883 0036 012B cmp r3, #1 + 1884 0038 14BF ite ne + 1885 003a 0123 movne r3, #1 + 1886 003c 0023 moveq r3, #0 + 1887 003e DBB2 uxtb r3, r3 + 1888 0040 2FE0 b .L119 + 1889 .L120: + 1890 .loc 1 900 44 is_stmt 0 discriminator 5 + 1891 0042 3B68 ldr r3, [r7] + 1892 0044 082B cmp r3, #8 + 1893 0046 09D1 bne .L122 + 1894 .loc 1 900 7 is_stmt 1 discriminator 7 + 1895 0048 7B68 ldr r3, [r7, #4] + 1896 004a 93F84030 ldrb r3, [r3, #64] + 1897 004e DBB2 uxtb r3, r3 + 1898 .loc 1 900 44 discriminator 7 + 1899 0050 012B cmp r3, #1 + 1900 0052 14BF ite ne + 1901 0054 0123 movne r3, #1 + 1902 0056 0023 moveq r3, #0 + 1903 0058 DBB2 uxtb r3, r3 + 1904 005a 22E0 b .L119 + 1905 .L122: + 1906 .loc 1 900 44 is_stmt 0 discriminator 8 + 1907 005c 3B68 ldr r3, [r7] + 1908 005e 0C2B cmp r3, #12 + 1909 0060 09D1 bne .L124 + 1910 .loc 1 900 7 is_stmt 1 discriminator 10 + 1911 0062 7B68 ldr r3, [r7, #4] + 1912 0064 93F84130 ldrb r3, [r3, #65] + 1913 0068 DBB2 uxtb r3, r3 + 1914 .loc 1 900 44 discriminator 10 + 1915 006a 012B cmp r3, #1 + 1916 006c 14BF ite ne + 1917 006e 0123 movne r3, #1 + ARM GAS /tmp/ccl4b9YO.s page 50 + + + 1918 0070 0023 moveq r3, #0 + 1919 0072 DBB2 uxtb r3, r3 + 1920 0074 15E0 b .L119 + 1921 .L124: + 1922 .loc 1 900 44 is_stmt 0 discriminator 11 + 1923 0076 3B68 ldr r3, [r7] + 1924 0078 102B cmp r3, #16 + 1925 007a 09D1 bne .L126 + 1926 .loc 1 900 7 is_stmt 1 discriminator 13 + 1927 007c 7B68 ldr r3, [r7, #4] + 1928 007e 93F84230 ldrb r3, [r3, #66] + 1929 0082 DBB2 uxtb r3, r3 + 1930 .loc 1 900 44 discriminator 13 + 1931 0084 012B cmp r3, #1 + 1932 0086 14BF ite ne + 1933 0088 0123 movne r3, #1 + 1934 008a 0023 moveq r3, #0 + 1935 008c DBB2 uxtb r3, r3 + 1936 008e 08E0 b .L119 + 1937 .L126: + 1938 .loc 1 900 7 discriminator 14 + 1939 0090 7B68 ldr r3, [r7, #4] + 1940 0092 93F84330 ldrb r3, [r3, #67] + 1941 0096 DBB2 uxtb r3, r3 + 1942 .loc 1 900 44 discriminator 14 + 1943 0098 012B cmp r3, #1 + 1944 009a 14BF ite ne + 1945 009c 0123 movne r3, #1 + 1946 009e 0023 moveq r3, #0 + 1947 00a0 DBB2 uxtb r3, r3 + 1948 .L119: + 1949 .loc 1 900 6 discriminator 20 + 1950 00a2 002B cmp r3, #0 + 1951 00a4 01D0 beq .L128 + 901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 902:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 1952 .loc 1 902 12 + 1953 00a6 0123 movs r3, #1 + 1954 00a8 D8E0 b .L129 + 1955 .L128: + 903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 904:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 905:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the TIM channel state */ + 906:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + 1956 .loc 1 906 3 + 1957 00aa 3B68 ldr r3, [r7] + 1958 00ac 002B cmp r3, #0 + 1959 00ae 04D1 bne .L130 + 1960 .loc 1 906 3 is_stmt 0 discriminator 1 + 1961 00b0 7B68 ldr r3, [r7, #4] + 1962 00b2 0222 movs r2, #2 + 1963 00b4 83F83E20 strb r2, [r3, #62] + 1964 00b8 23E0 b .L131 + 1965 .L130: + 1966 .loc 1 906 3 discriminator 2 + 1967 00ba 3B68 ldr r3, [r7] + 1968 00bc 042B cmp r3, #4 + ARM GAS /tmp/ccl4b9YO.s page 51 + + + 1969 00be 04D1 bne .L132 + 1970 .loc 1 906 3 discriminator 3 + 1971 00c0 7B68 ldr r3, [r7, #4] + 1972 00c2 0222 movs r2, #2 + 1973 00c4 83F83F20 strb r2, [r3, #63] + 1974 00c8 1BE0 b .L131 + 1975 .L132: + 1976 .loc 1 906 3 discriminator 4 + 1977 00ca 3B68 ldr r3, [r7] + 1978 00cc 082B cmp r3, #8 + 1979 00ce 04D1 bne .L134 + 1980 .loc 1 906 3 discriminator 6 + 1981 00d0 7B68 ldr r3, [r7, #4] + 1982 00d2 0222 movs r2, #2 + 1983 00d4 83F84020 strb r2, [r3, #64] + 1984 00d8 13E0 b .L131 + 1985 .L134: + 1986 .loc 1 906 3 discriminator 7 + 1987 00da 3B68 ldr r3, [r7] + 1988 00dc 0C2B cmp r3, #12 + 1989 00de 04D1 bne .L136 + 1990 .loc 1 906 3 discriminator 9 + 1991 00e0 7B68 ldr r3, [r7, #4] + 1992 00e2 0222 movs r2, #2 + 1993 00e4 83F84120 strb r2, [r3, #65] + 1994 00e8 0BE0 b .L131 + 1995 .L136: + 1996 .loc 1 906 3 discriminator 10 + 1997 00ea 3B68 ldr r3, [r7] + 1998 00ec 102B cmp r3, #16 + 1999 00ee 04D1 bne .L138 + 2000 .loc 1 906 3 discriminator 12 + 2001 00f0 7B68 ldr r3, [r7, #4] + 2002 00f2 0222 movs r2, #2 + 2003 00f4 83F84220 strb r2, [r3, #66] + 2004 00f8 03E0 b .L131 + 2005 .L138: + 2006 .loc 1 906 3 discriminator 13 + 2007 00fa 7B68 ldr r3, [r7, #4] + 2008 00fc 0222 movs r2, #2 + 2009 00fe 83F84320 strb r2, [r3, #67] + 2010 .L131: + 907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 908:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** switch (Channel) + 2011 .loc 1 908 3 is_stmt 1 + 2012 0102 3B68 ldr r3, [r7] + 2013 0104 0C2B cmp r3, #12 + 2014 0106 41D8 bhi .L140 + 2015 0108 01A2 adr r2, .L142 + 2016 010a 52F823F0 ldr pc, [r2, r3, lsl #2] + 2017 010e 00BF .p2align 2 + 2018 .L142: + 2019 0110 45010000 .word .L145+1 + 2020 0114 8D010000 .word .L140+1 + 2021 0118 8D010000 .word .L140+1 + 2022 011c 8D010000 .word .L140+1 + 2023 0120 57010000 .word .L144+1 + ARM GAS /tmp/ccl4b9YO.s page 52 + + + 2024 0124 8D010000 .word .L140+1 + 2025 0128 8D010000 .word .L140+1 + 2026 012c 8D010000 .word .L140+1 + 2027 0130 69010000 .word .L143+1 + 2028 0134 8D010000 .word .L140+1 + 2029 0138 8D010000 .word .L140+1 + 2030 013c 8D010000 .word .L140+1 + 2031 0140 7B010000 .word .L141+1 + 2032 .p2align 1 + 2033 .L145: + 909:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_1: + 911:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the TIM Capture/Compare 1 interrupt */ + 913:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + 2034 .loc 1 913 7 + 2035 0144 7B68 ldr r3, [r7, #4] + 2036 0146 1B68 ldr r3, [r3] + 2037 0148 DA68 ldr r2, [r3, #12] + 2038 014a 7B68 ldr r3, [r7, #4] + 2039 014c 1B68 ldr r3, [r3] + 2040 014e 42F00202 orr r2, r2, #2 + 2041 0152 DA60 str r2, [r3, #12] + 914:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 2042 .loc 1 914 7 + 2043 0154 1DE0 b .L146 + 2044 .L144: + 915:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 916:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 917:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_2: + 918:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 919:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the TIM Capture/Compare 2 interrupt */ + 920:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + 2045 .loc 1 920 7 + 2046 0156 7B68 ldr r3, [r7, #4] + 2047 0158 1B68 ldr r3, [r3] + 2048 015a DA68 ldr r2, [r3, #12] + 2049 015c 7B68 ldr r3, [r7, #4] + 2050 015e 1B68 ldr r3, [r3] + 2051 0160 42F00402 orr r2, r2, #4 + 2052 0164 DA60 str r2, [r3, #12] + 921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 2053 .loc 1 921 7 + 2054 0166 14E0 b .L146 + 2055 .L143: + 922:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 923:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 924:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_3: + 925:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 926:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the TIM Capture/Compare 3 interrupt */ + 927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + 2056 .loc 1 927 7 + 2057 0168 7B68 ldr r3, [r7, #4] + 2058 016a 1B68 ldr r3, [r3] + 2059 016c DA68 ldr r2, [r3, #12] + 2060 016e 7B68 ldr r3, [r7, #4] + 2061 0170 1B68 ldr r3, [r3] + ARM GAS /tmp/ccl4b9YO.s page 53 + + + 2062 0172 42F00802 orr r2, r2, #8 + 2063 0176 DA60 str r2, [r3, #12] + 928:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 2064 .loc 1 928 7 + 2065 0178 0BE0 b .L146 + 2066 .L141: + 929:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 930:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 931:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_4: + 932:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the TIM Capture/Compare 4 interrupt */ + 934:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + 2067 .loc 1 934 7 + 2068 017a 7B68 ldr r3, [r7, #4] + 2069 017c 1B68 ldr r3, [r3] + 2070 017e DA68 ldr r2, [r3, #12] + 2071 0180 7B68 ldr r3, [r7, #4] + 2072 0182 1B68 ldr r3, [r3] + 2073 0184 42F01002 orr r2, r2, #16 + 2074 0188 DA60 str r2, [r3, #12] + 935:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 2075 .loc 1 935 7 + 2076 018a 02E0 b .L146 + 2077 .L140: + 936:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** default: + 939:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** status = HAL_ERROR; + 2078 .loc 1 939 14 + 2079 018c 0123 movs r3, #1 + 2080 018e FB73 strb r3, [r7, #15] + 940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 2081 .loc 1 940 7 + 2082 0190 00BF nop + 2083 .L146: + 941:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 943:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (status == HAL_OK) + 2084 .loc 1 943 6 + 2085 0192 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 2086 0194 002B cmp r3, #0 + 2087 0196 60D1 bne .L147 + 944:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the Output compare channel */ + 946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + 2088 .loc 1 946 5 + 2089 0198 7B68 ldr r3, [r7, #4] + 2090 019a 1B68 ldr r3, [r3] + 2091 019c 0122 movs r2, #1 + 2092 019e 3968 ldr r1, [r7] + 2093 01a0 1846 mov r0, r3 + 2094 01a2 FFF7FEFF bl TIM_CCxChannelCmd + 947:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 948:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + 2095 .loc 1 948 9 + 2096 01a6 7B68 ldr r3, [r7, #4] + 2097 01a8 1B68 ldr r3, [r3] + ARM GAS /tmp/ccl4b9YO.s page 54 + + + 2098 01aa 2E4A ldr r2, .L156 + 2099 01ac 9342 cmp r3, r2 + 2100 01ae 0ED0 beq .L148 + 2101 .loc 1 948 9 is_stmt 0 discriminator 2 + 2102 01b0 7B68 ldr r3, [r7, #4] + 2103 01b2 1B68 ldr r3, [r3] + 2104 01b4 2C4A ldr r2, .L156+4 + 2105 01b6 9342 cmp r3, r2 + 2106 01b8 09D0 beq .L148 + 2107 .loc 1 948 9 discriminator 4 + 2108 01ba 7B68 ldr r3, [r7, #4] + 2109 01bc 1B68 ldr r3, [r3] + 2110 01be 2B4A ldr r2, .L156+8 + 2111 01c0 9342 cmp r3, r2 + 2112 01c2 04D0 beq .L148 + 2113 .loc 1 948 9 discriminator 6 + 2114 01c4 7B68 ldr r3, [r7, #4] + 2115 01c6 1B68 ldr r3, [r3] + 2116 01c8 294A ldr r2, .L156+12 + 2117 01ca 9342 cmp r3, r2 + 2118 01cc 01D1 bne .L149 + 2119 .L148: + 2120 .loc 1 948 9 discriminator 7 + 2121 01ce 0123 movs r3, #1 + 2122 .loc 1 948 9 + 2123 01d0 00E0 b .L150 + 2124 .L149: + 2125 .loc 1 948 9 discriminator 8 + 2126 01d2 0023 movs r3, #0 + 2127 .L150: + 2128 .loc 1 948 8 is_stmt 1 discriminator 10 + 2129 01d4 002B cmp r3, #0 + 2130 01d6 07D0 beq .L151 + 949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 950:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the main output */ + 951:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_MOE_ENABLE(htim); + 2131 .loc 1 951 7 + 2132 01d8 7B68 ldr r3, [r7, #4] + 2133 01da 1B68 ldr r3, [r3] + 2134 01dc 5A6C ldr r2, [r3, #68] + 2135 01de 7B68 ldr r3, [r7, #4] + 2136 01e0 1B68 ldr r3, [r3] + 2137 01e2 42F40042 orr r2, r2, #32768 + 2138 01e6 5A64 str r2, [r3, #68] + 2139 .L151: + 952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 954:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigge + 955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 2140 .loc 1 955 9 + 2141 01e8 7B68 ldr r3, [r7, #4] + 2142 01ea 1B68 ldr r3, [r3] + 2143 .loc 1 955 8 + 2144 01ec 1D4A ldr r2, .L156 + 2145 01ee 9342 cmp r3, r2 + 2146 01f0 13D0 beq .L152 + 2147 .loc 1 955 9 discriminator 1 + ARM GAS /tmp/ccl4b9YO.s page 55 + + + 2148 01f2 7B68 ldr r3, [r7, #4] + 2149 01f4 1B68 ldr r3, [r3] + 2150 01f6 B3F1804F cmp r3, #1073741824 + 2151 01fa 0ED0 beq .L152 + 2152 .loc 1 955 9 is_stmt 0 discriminator 2 + 2153 01fc 7B68 ldr r3, [r7, #4] + 2154 01fe 1B68 ldr r3, [r3] + 2155 0200 1C4A ldr r2, .L156+16 + 2156 0202 9342 cmp r3, r2 + 2157 0204 09D0 beq .L152 + 2158 .loc 1 955 9 discriminator 3 + 2159 0206 7B68 ldr r3, [r7, #4] + 2160 0208 1B68 ldr r3, [r3] + 2161 020a 1B4A ldr r2, .L156+20 + 2162 020c 9342 cmp r3, r2 + 2163 020e 04D0 beq .L152 + 2164 .loc 1 955 9 discriminator 4 + 2165 0210 7B68 ldr r3, [r7, #4] + 2166 0212 1B68 ldr r3, [r3] + 2167 0214 144A ldr r2, .L156+4 + 2168 0216 9342 cmp r3, r2 + 2169 0218 15D1 bne .L153 + 2170 .L152: + 956:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 957:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + 2171 .loc 1 957 21 is_stmt 1 + 2172 021a 7B68 ldr r3, [r7, #4] + 2173 021c 1B68 ldr r3, [r3] + 2174 .loc 1 957 31 + 2175 021e 9A68 ldr r2, [r3, #8] + 2176 .loc 1 957 15 + 2177 0220 164B ldr r3, .L156+24 + 2178 0222 1340 ands r3, r3, r2 + 2179 0224 BB60 str r3, [r7, #8] + 958:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 2180 .loc 1 958 10 + 2181 0226 BB68 ldr r3, [r7, #8] + 2182 0228 062B cmp r3, #6 + 2183 022a 15D0 beq .L155 + 2184 .loc 1 958 11 discriminator 1 + 2185 022c BB68 ldr r3, [r7, #8] + 2186 022e B3F5803F cmp r3, #65536 + 2187 0232 11D0 beq .L155 + 959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 960:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); + 2188 .loc 1 960 9 + 2189 0234 7B68 ldr r3, [r7, #4] + 2190 0236 1B68 ldr r3, [r3] + 2191 0238 1A68 ldr r2, [r3] + 2192 023a 7B68 ldr r3, [r7, #4] + 2193 023c 1B68 ldr r3, [r3] + 2194 023e 42F00102 orr r2, r2, #1 + 2195 0242 1A60 str r2, [r3] + 958:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 2196 .loc 1 958 10 + 2197 0244 08E0 b .L155 + 2198 .L153: + ARM GAS /tmp/ccl4b9YO.s page 56 + + + 961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 963:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else + 964:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 965:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); + 2199 .loc 1 965 7 + 2200 0246 7B68 ldr r3, [r7, #4] + 2201 0248 1B68 ldr r3, [r3] + 2202 024a 1A68 ldr r2, [r3] + 2203 024c 7B68 ldr r3, [r7, #4] + 2204 024e 1B68 ldr r3, [r3] + 2205 0250 42F00102 orr r2, r2, #1 + 2206 0254 1A60 str r2, [r3] + 2207 0256 00E0 b .L147 + 2208 .L155: + 958:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 2209 .loc 1 958 10 + 2210 0258 00BF nop + 2211 .L147: + 966:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 967:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 969:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return function status */ + 970:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return status; + 2212 .loc 1 970 10 + 2213 025a FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 2214 .L129: + 971:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 2215 .loc 1 971 1 + 2216 025c 1846 mov r0, r3 + 2217 025e 1037 adds r7, r7, #16 + 2218 .cfi_def_cfa_offset 8 + 2219 0260 BD46 mov sp, r7 + 2220 .cfi_def_cfa_register 13 + 2221 @ sp needed + 2222 0262 80BD pop {r7, pc} + 2223 .L157: + 2224 .align 2 + 2225 .L156: + 2226 0264 002C0140 .word 1073818624 + 2227 0268 00400140 .word 1073823744 + 2228 026c 00440140 .word 1073824768 + 2229 0270 00480140 .word 1073825792 + 2230 0274 00040040 .word 1073742848 + 2231 0278 00080040 .word 1073743872 + 2232 027c 07000100 .word 65543 + 2233 .cfi_endproc + 2234 .LFE146: + 2236 .section .text.HAL_TIM_OC_Stop_IT,"ax",%progbits + 2237 .align 1 + 2238 .global HAL_TIM_OC_Stop_IT + 2239 .syntax unified + 2240 .thumb + 2241 .thumb_func + 2243 HAL_TIM_OC_Stop_IT: + 2244 .LFB147: + 972:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + ARM GAS /tmp/ccl4b9YO.s page 57 + + + 973:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** + 974:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Stops the TIM Output Compare signal generation in interrupt mode. + 975:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM Output Compare handle + 976:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param Channel TIM Channel to be disabled + 977:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: + 978:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected + 979:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected + 980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected + 981:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected + 982:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status + 983:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ + 984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) + 985:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 2245 .loc 1 985 1 + 2246 .cfi_startproc + 2247 @ args = 0, pretend = 0, frame = 16 + 2248 @ frame_needed = 1, uses_anonymous_args = 0 + 2249 0000 80B5 push {r7, lr} + 2250 .cfi_def_cfa_offset 8 + 2251 .cfi_offset 7, -8 + 2252 .cfi_offset 14, -4 + 2253 0002 84B0 sub sp, sp, #16 + 2254 .cfi_def_cfa_offset 24 + 2255 0004 00AF add r7, sp, #0 + 2256 .cfi_def_cfa_register 7 + 2257 0006 7860 str r0, [r7, #4] + 2258 0008 3960 str r1, [r7] + 986:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 2259 .loc 1 986 21 + 2260 000a 0023 movs r3, #0 + 2261 000c FB73 strb r3, [r7, #15] + 987:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 988:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ + 989:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + 990:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + 991:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** switch (Channel) + 2262 .loc 1 991 3 + 2263 000e 3B68 ldr r3, [r7] + 2264 0010 0C2B cmp r3, #12 + 2265 0012 41D8 bhi .L159 + 2266 0014 01A2 adr r2, .L161 + 2267 0016 52F823F0 ldr pc, [r2, r3, lsl #2] + 2268 001a 00BF .p2align 2 + 2269 .L161: + 2270 001c 51000000 .word .L164+1 + 2271 0020 99000000 .word .L159+1 + 2272 0024 99000000 .word .L159+1 + 2273 0028 99000000 .word .L159+1 + 2274 002c 63000000 .word .L163+1 + 2275 0030 99000000 .word .L159+1 + 2276 0034 99000000 .word .L159+1 + 2277 0038 99000000 .word .L159+1 + 2278 003c 75000000 .word .L162+1 + 2279 0040 99000000 .word .L159+1 + 2280 0044 99000000 .word .L159+1 + 2281 0048 99000000 .word .L159+1 + 2282 004c 87000000 .word .L160+1 + ARM GAS /tmp/ccl4b9YO.s page 58 + + + 2283 .p2align 1 + 2284 .L164: + 992:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 993:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_1: + 994:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the TIM Capture/Compare 1 interrupt */ + 996:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + 2285 .loc 1 996 7 + 2286 0050 7B68 ldr r3, [r7, #4] + 2287 0052 1B68 ldr r3, [r3] + 2288 0054 DA68 ldr r2, [r3, #12] + 2289 0056 7B68 ldr r3, [r7, #4] + 2290 0058 1B68 ldr r3, [r3] + 2291 005a 22F00202 bic r2, r2, #2 + 2292 005e DA60 str r2, [r3, #12] + 997:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 2293 .loc 1 997 7 + 2294 0060 1DE0 b .L165 + 2295 .L163: + 998:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 999:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1000:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_2: +1001:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1002:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the TIM Capture/Compare 2 interrupt */ +1003:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + 2296 .loc 1 1003 7 + 2297 0062 7B68 ldr r3, [r7, #4] + 2298 0064 1B68 ldr r3, [r3] + 2299 0066 DA68 ldr r2, [r3, #12] + 2300 0068 7B68 ldr r3, [r7, #4] + 2301 006a 1B68 ldr r3, [r3] + 2302 006c 22F00402 bic r2, r2, #4 + 2303 0070 DA60 str r2, [r3, #12] +1004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 2304 .loc 1 1004 7 + 2305 0072 14E0 b .L165 + 2306 .L162: +1005:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1006:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_3: +1008:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the TIM Capture/Compare 3 interrupt */ +1010:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + 2307 .loc 1 1010 7 + 2308 0074 7B68 ldr r3, [r7, #4] + 2309 0076 1B68 ldr r3, [r3] + 2310 0078 DA68 ldr r2, [r3, #12] + 2311 007a 7B68 ldr r3, [r7, #4] + 2312 007c 1B68 ldr r3, [r3] + 2313 007e 22F00802 bic r2, r2, #8 + 2314 0082 DA60 str r2, [r3, #12] +1011:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 2315 .loc 1 1011 7 + 2316 0084 0BE0 b .L165 + 2317 .L160: +1012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1013:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + ARM GAS /tmp/ccl4b9YO.s page 59 + + +1014:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_4: +1015:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the TIM Capture/Compare 4 interrupt */ +1017:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + 2318 .loc 1 1017 7 + 2319 0086 7B68 ldr r3, [r7, #4] + 2320 0088 1B68 ldr r3, [r3] + 2321 008a DA68 ldr r2, [r3, #12] + 2322 008c 7B68 ldr r3, [r7, #4] + 2323 008e 1B68 ldr r3, [r3] + 2324 0090 22F01002 bic r2, r2, #16 + 2325 0094 DA60 str r2, [r3, #12] +1018:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 2326 .loc 1 1018 7 + 2327 0096 02E0 b .L165 + 2328 .L159: +1019:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1021:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** default: +1022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** status = HAL_ERROR; + 2329 .loc 1 1022 14 + 2330 0098 0123 movs r3, #1 + 2331 009a FB73 strb r3, [r7, #15] +1023:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 2332 .loc 1 1023 7 + 2333 009c 00BF nop + 2334 .L165: +1024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1025:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (status == HAL_OK) + 2335 .loc 1 1026 6 + 2336 009e FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 2337 00a0 002B cmp r3, #0 + 2338 00a2 7BD1 bne .L166 +1027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1028:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the Output compare channel */ +1029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + 2339 .loc 1 1029 5 + 2340 00a4 7B68 ldr r3, [r7, #4] + 2341 00a6 1B68 ldr r3, [r3] + 2342 00a8 0022 movs r2, #0 + 2343 00aa 3968 ldr r1, [r7] + 2344 00ac 1846 mov r0, r3 + 2345 00ae FFF7FEFF bl TIM_CCxChannelCmd +1030:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1031:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + 2346 .loc 1 1031 9 + 2347 00b2 7B68 ldr r3, [r7, #4] + 2348 00b4 1B68 ldr r3, [r3] + 2349 00b6 3C4A ldr r2, .L182 + 2350 00b8 9342 cmp r3, r2 + 2351 00ba 0ED0 beq .L167 + 2352 .loc 1 1031 9 is_stmt 0 discriminator 2 + 2353 00bc 7B68 ldr r3, [r7, #4] + 2354 00be 1B68 ldr r3, [r3] + 2355 00c0 3A4A ldr r2, .L182+4 + 2356 00c2 9342 cmp r3, r2 + ARM GAS /tmp/ccl4b9YO.s page 60 + + + 2357 00c4 09D0 beq .L167 + 2358 .loc 1 1031 9 discriminator 4 + 2359 00c6 7B68 ldr r3, [r7, #4] + 2360 00c8 1B68 ldr r3, [r3] + 2361 00ca 394A ldr r2, .L182+8 + 2362 00cc 9342 cmp r3, r2 + 2363 00ce 04D0 beq .L167 + 2364 .loc 1 1031 9 discriminator 6 + 2365 00d0 7B68 ldr r3, [r7, #4] + 2366 00d2 1B68 ldr r3, [r3] + 2367 00d4 374A ldr r2, .L182+12 + 2368 00d6 9342 cmp r3, r2 + 2369 00d8 01D1 bne .L168 + 2370 .L167: + 2371 .loc 1 1031 9 discriminator 7 + 2372 00da 0123 movs r3, #1 + 2373 .loc 1 1031 9 + 2374 00dc 00E0 b .L169 + 2375 .L168: + 2376 .loc 1 1031 9 discriminator 8 + 2377 00de 0023 movs r3, #0 + 2378 .L169: + 2379 .loc 1 1031 8 is_stmt 1 discriminator 10 + 2380 00e0 002B cmp r3, #0 + 2381 00e2 17D0 beq .L170 +1032:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1033:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the Main Output */ +1034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_MOE_DISABLE(htim); + 2382 .loc 1 1034 7 + 2383 00e4 7B68 ldr r3, [r7, #4] + 2384 00e6 1B68 ldr r3, [r3] + 2385 00e8 1A6A ldr r2, [r3, #32] + 2386 00ea 41F21113 movw r3, #4369 + 2387 00ee 1340 ands r3, r3, r2 + 2388 00f0 002B cmp r3, #0 + 2389 00f2 0FD1 bne .L170 + 2390 .loc 1 1034 7 is_stmt 0 discriminator 1 + 2391 00f4 7B68 ldr r3, [r7, #4] + 2392 00f6 1B68 ldr r3, [r3] + 2393 00f8 1A6A ldr r2, [r3, #32] + 2394 00fa 40F24443 movw r3, #1092 + 2395 00fe 1340 ands r3, r3, r2 + 2396 0100 002B cmp r3, #0 + 2397 0102 07D1 bne .L170 + 2398 .loc 1 1034 7 discriminator 2 + 2399 0104 7B68 ldr r3, [r7, #4] + 2400 0106 1B68 ldr r3, [r3] + 2401 0108 5A6C ldr r2, [r3, #68] + 2402 010a 7B68 ldr r3, [r7, #4] + 2403 010c 1B68 ldr r3, [r3] + 2404 010e 22F40042 bic r2, r2, #32768 + 2405 0112 5A64 str r2, [r3, #68] + 2406 .L170: +1035:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1036:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the Peripheral */ +1038:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); + ARM GAS /tmp/ccl4b9YO.s page 61 + + + 2407 .loc 1 1038 5 is_stmt 1 + 2408 0114 7B68 ldr r3, [r7, #4] + 2409 0116 1B68 ldr r3, [r3] + 2410 0118 1A6A ldr r2, [r3, #32] + 2411 011a 41F21113 movw r3, #4369 + 2412 011e 1340 ands r3, r3, r2 + 2413 0120 002B cmp r3, #0 + 2414 0122 0FD1 bne .L171 + 2415 .loc 1 1038 5 is_stmt 0 discriminator 1 + 2416 0124 7B68 ldr r3, [r7, #4] + 2417 0126 1B68 ldr r3, [r3] + 2418 0128 1A6A ldr r2, [r3, #32] + 2419 012a 40F24443 movw r3, #1092 + 2420 012e 1340 ands r3, r3, r2 + 2421 0130 002B cmp r3, #0 + 2422 0132 07D1 bne .L171 + 2423 .loc 1 1038 5 discriminator 2 + 2424 0134 7B68 ldr r3, [r7, #4] + 2425 0136 1B68 ldr r3, [r3] + 2426 0138 1A68 ldr r2, [r3] + 2427 013a 7B68 ldr r3, [r7, #4] + 2428 013c 1B68 ldr r3, [r3] + 2429 013e 22F00102 bic r2, r2, #1 + 2430 0142 1A60 str r2, [r3] + 2431 .L171: +1039:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1040:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the TIM channel state */ +1041:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 2432 .loc 1 1041 5 is_stmt 1 + 2433 0144 3B68 ldr r3, [r7] + 2434 0146 002B cmp r3, #0 + 2435 0148 04D1 bne .L172 + 2436 .loc 1 1041 5 is_stmt 0 discriminator 1 + 2437 014a 7B68 ldr r3, [r7, #4] + 2438 014c 0122 movs r2, #1 + 2439 014e 83F83E20 strb r2, [r3, #62] + 2440 0152 23E0 b .L166 + 2441 .L172: + 2442 .loc 1 1041 5 discriminator 2 + 2443 0154 3B68 ldr r3, [r7] + 2444 0156 042B cmp r3, #4 + 2445 0158 04D1 bne .L173 + 2446 .loc 1 1041 5 discriminator 3 + 2447 015a 7B68 ldr r3, [r7, #4] + 2448 015c 0122 movs r2, #1 + 2449 015e 83F83F20 strb r2, [r3, #63] + 2450 0162 1BE0 b .L166 + 2451 .L173: + 2452 .loc 1 1041 5 discriminator 4 + 2453 0164 3B68 ldr r3, [r7] + 2454 0166 082B cmp r3, #8 + 2455 0168 04D1 bne .L175 + 2456 .loc 1 1041 5 discriminator 6 + 2457 016a 7B68 ldr r3, [r7, #4] + 2458 016c 0122 movs r2, #1 + 2459 016e 83F84020 strb r2, [r3, #64] + 2460 0172 13E0 b .L166 + ARM GAS /tmp/ccl4b9YO.s page 62 + + + 2461 .L175: + 2462 .loc 1 1041 5 discriminator 7 + 2463 0174 3B68 ldr r3, [r7] + 2464 0176 0C2B cmp r3, #12 + 2465 0178 04D1 bne .L177 + 2466 .loc 1 1041 5 discriminator 9 + 2467 017a 7B68 ldr r3, [r7, #4] + 2468 017c 0122 movs r2, #1 + 2469 017e 83F84120 strb r2, [r3, #65] + 2470 0182 0BE0 b .L166 + 2471 .L177: + 2472 .loc 1 1041 5 discriminator 10 + 2473 0184 3B68 ldr r3, [r7] + 2474 0186 102B cmp r3, #16 + 2475 0188 04D1 bne .L179 + 2476 .loc 1 1041 5 discriminator 12 + 2477 018a 7B68 ldr r3, [r7, #4] + 2478 018c 0122 movs r2, #1 + 2479 018e 83F84220 strb r2, [r3, #66] + 2480 0192 03E0 b .L166 + 2481 .L179: + 2482 .loc 1 1041 5 discriminator 13 + 2483 0194 7B68 ldr r3, [r7, #4] + 2484 0196 0122 movs r2, #1 + 2485 0198 83F84320 strb r2, [r3, #67] + 2486 .L166: +1042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1043:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return function status */ +1045:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return status; + 2487 .loc 1 1045 10 is_stmt 1 + 2488 019c FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 +1046:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 2489 .loc 1 1046 1 + 2490 019e 1846 mov r0, r3 + 2491 01a0 1037 adds r7, r7, #16 + 2492 .cfi_def_cfa_offset 8 + 2493 01a2 BD46 mov sp, r7 + 2494 .cfi_def_cfa_register 13 + 2495 @ sp needed + 2496 01a4 80BD pop {r7, pc} + 2497 .L183: + 2498 01a6 00BF .align 2 + 2499 .L182: + 2500 01a8 002C0140 .word 1073818624 + 2501 01ac 00400140 .word 1073823744 + 2502 01b0 00440140 .word 1073824768 + 2503 01b4 00480140 .word 1073825792 + 2504 .cfi_endproc + 2505 .LFE147: + 2507 .section .text.HAL_TIM_OC_Start_DMA,"ax",%progbits + 2508 .align 1 + 2509 .global HAL_TIM_OC_Start_DMA + 2510 .syntax unified + 2511 .thumb + 2512 .thumb_func + 2514 HAL_TIM_OC_Start_DMA: + ARM GAS /tmp/ccl4b9YO.s page 63 + + + 2515 .LFB148: +1047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +1049:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Starts the TIM Output Compare signal generation in DMA mode. +1050:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM Output Compare handle +1051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param Channel TIM Channel to be enabled +1052:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +1053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +1054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +1055:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +1056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +1057:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param pData The source Buffer address. +1058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param Length The length of data to be transferred from memory to TIM peripheral +1059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status +1060:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +1061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *p +1062:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint16_t Length) +1063:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 2516 .loc 1 1063 1 + 2517 .cfi_startproc + 2518 @ args = 0, pretend = 0, frame = 24 + 2519 @ frame_needed = 1, uses_anonymous_args = 0 + 2520 0000 80B5 push {r7, lr} + 2521 .cfi_def_cfa_offset 8 + 2522 .cfi_offset 7, -8 + 2523 .cfi_offset 14, -4 + 2524 0002 86B0 sub sp, sp, #24 + 2525 .cfi_def_cfa_offset 32 + 2526 0004 00AF add r7, sp, #0 + 2527 .cfi_def_cfa_register 7 + 2528 0006 F860 str r0, [r7, #12] + 2529 0008 B960 str r1, [r7, #8] + 2530 000a 7A60 str r2, [r7, #4] + 2531 000c 7B80 strh r3, [r7, #2] @ movhi +1064:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 2532 .loc 1 1064 21 + 2533 000e 0023 movs r3, #0 + 2534 0010 FB75 strb r3, [r7, #23] +1065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpsmcr; +1066:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1067:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +1068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); +1069:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1070:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the TIM channel state */ +1071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + 2535 .loc 1 1071 44 + 2536 0012 BB68 ldr r3, [r7, #8] + 2537 0014 002B cmp r3, #0 + 2538 0016 09D1 bne .L185 + 2539 .loc 1 1071 7 discriminator 1 + 2540 0018 FB68 ldr r3, [r7, #12] + 2541 001a 93F83E30 ldrb r3, [r3, #62] + 2542 001e DBB2 uxtb r3, r3 + 2543 .loc 1 1071 44 discriminator 1 + 2544 0020 022B cmp r3, #2 + 2545 0022 0CBF ite eq + 2546 0024 0123 moveq r3, #1 + ARM GAS /tmp/ccl4b9YO.s page 64 + + + 2547 0026 0023 movne r3, #0 + 2548 0028 DBB2 uxtb r3, r3 + 2549 002a 3CE0 b .L186 + 2550 .L185: + 2551 .loc 1 1071 44 is_stmt 0 discriminator 2 + 2552 002c BB68 ldr r3, [r7, #8] + 2553 002e 042B cmp r3, #4 + 2554 0030 09D1 bne .L187 + 2555 .loc 1 1071 7 is_stmt 1 discriminator 4 + 2556 0032 FB68 ldr r3, [r7, #12] + 2557 0034 93F83F30 ldrb r3, [r3, #63] + 2558 0038 DBB2 uxtb r3, r3 + 2559 .loc 1 1071 44 discriminator 4 + 2560 003a 022B cmp r3, #2 + 2561 003c 0CBF ite eq + 2562 003e 0123 moveq r3, #1 + 2563 0040 0023 movne r3, #0 + 2564 0042 DBB2 uxtb r3, r3 + 2565 0044 2FE0 b .L186 + 2566 .L187: + 2567 .loc 1 1071 44 is_stmt 0 discriminator 5 + 2568 0046 BB68 ldr r3, [r7, #8] + 2569 0048 082B cmp r3, #8 + 2570 004a 09D1 bne .L189 + 2571 .loc 1 1071 7 is_stmt 1 discriminator 7 + 2572 004c FB68 ldr r3, [r7, #12] + 2573 004e 93F84030 ldrb r3, [r3, #64] + 2574 0052 DBB2 uxtb r3, r3 + 2575 .loc 1 1071 44 discriminator 7 + 2576 0054 022B cmp r3, #2 + 2577 0056 0CBF ite eq + 2578 0058 0123 moveq r3, #1 + 2579 005a 0023 movne r3, #0 + 2580 005c DBB2 uxtb r3, r3 + 2581 005e 22E0 b .L186 + 2582 .L189: + 2583 .loc 1 1071 44 is_stmt 0 discriminator 8 + 2584 0060 BB68 ldr r3, [r7, #8] + 2585 0062 0C2B cmp r3, #12 + 2586 0064 09D1 bne .L191 + 2587 .loc 1 1071 7 is_stmt 1 discriminator 10 + 2588 0066 FB68 ldr r3, [r7, #12] + 2589 0068 93F84130 ldrb r3, [r3, #65] + 2590 006c DBB2 uxtb r3, r3 + 2591 .loc 1 1071 44 discriminator 10 + 2592 006e 022B cmp r3, #2 + 2593 0070 0CBF ite eq + 2594 0072 0123 moveq r3, #1 + 2595 0074 0023 movne r3, #0 + 2596 0076 DBB2 uxtb r3, r3 + 2597 0078 15E0 b .L186 + 2598 .L191: + 2599 .loc 1 1071 44 is_stmt 0 discriminator 11 + 2600 007a BB68 ldr r3, [r7, #8] + 2601 007c 102B cmp r3, #16 + 2602 007e 09D1 bne .L193 + 2603 .loc 1 1071 7 is_stmt 1 discriminator 13 + ARM GAS /tmp/ccl4b9YO.s page 65 + + + 2604 0080 FB68 ldr r3, [r7, #12] + 2605 0082 93F84230 ldrb r3, [r3, #66] + 2606 0086 DBB2 uxtb r3, r3 + 2607 .loc 1 1071 44 discriminator 13 + 2608 0088 022B cmp r3, #2 + 2609 008a 0CBF ite eq + 2610 008c 0123 moveq r3, #1 + 2611 008e 0023 movne r3, #0 + 2612 0090 DBB2 uxtb r3, r3 + 2613 0092 08E0 b .L186 + 2614 .L193: + 2615 .loc 1 1071 7 discriminator 14 + 2616 0094 FB68 ldr r3, [r7, #12] + 2617 0096 93F84330 ldrb r3, [r3, #67] + 2618 009a DBB2 uxtb r3, r3 + 2619 .loc 1 1071 44 discriminator 14 + 2620 009c 022B cmp r3, #2 + 2621 009e 0CBF ite eq + 2622 00a0 0123 moveq r3, #1 + 2623 00a2 0023 movne r3, #0 + 2624 00a4 DBB2 uxtb r3, r3 + 2625 .L186: + 2626 .loc 1 1071 6 discriminator 20 + 2627 00a6 002B cmp r3, #0 + 2628 00a8 01D0 beq .L195 +1072:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1073:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_BUSY; + 2629 .loc 1 1073 12 + 2630 00aa 0223 movs r3, #2 + 2631 00ac 9CE1 b .L196 + 2632 .L195: +1074:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1075:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + 2633 .loc 1 1075 49 + 2634 00ae BB68 ldr r3, [r7, #8] + 2635 00b0 002B cmp r3, #0 + 2636 00b2 09D1 bne .L197 + 2637 .loc 1 1075 12 discriminator 1 + 2638 00b4 FB68 ldr r3, [r7, #12] + 2639 00b6 93F83E30 ldrb r3, [r3, #62] + 2640 00ba DBB2 uxtb r3, r3 + 2641 .loc 1 1075 49 discriminator 1 + 2642 00bc 012B cmp r3, #1 + 2643 00be 0CBF ite eq + 2644 00c0 0123 moveq r3, #1 + 2645 00c2 0023 movne r3, #0 + 2646 00c4 DBB2 uxtb r3, r3 + 2647 00c6 3CE0 b .L198 + 2648 .L197: + 2649 .loc 1 1075 49 is_stmt 0 discriminator 2 + 2650 00c8 BB68 ldr r3, [r7, #8] + 2651 00ca 042B cmp r3, #4 + 2652 00cc 09D1 bne .L199 + 2653 .loc 1 1075 12 is_stmt 1 discriminator 4 + 2654 00ce FB68 ldr r3, [r7, #12] + 2655 00d0 93F83F30 ldrb r3, [r3, #63] + 2656 00d4 DBB2 uxtb r3, r3 + ARM GAS /tmp/ccl4b9YO.s page 66 + + + 2657 .loc 1 1075 49 discriminator 4 + 2658 00d6 012B cmp r3, #1 + 2659 00d8 0CBF ite eq + 2660 00da 0123 moveq r3, #1 + 2661 00dc 0023 movne r3, #0 + 2662 00de DBB2 uxtb r3, r3 + 2663 00e0 2FE0 b .L198 + 2664 .L199: + 2665 .loc 1 1075 49 is_stmt 0 discriminator 5 + 2666 00e2 BB68 ldr r3, [r7, #8] + 2667 00e4 082B cmp r3, #8 + 2668 00e6 09D1 bne .L201 + 2669 .loc 1 1075 12 is_stmt 1 discriminator 7 + 2670 00e8 FB68 ldr r3, [r7, #12] + 2671 00ea 93F84030 ldrb r3, [r3, #64] + 2672 00ee DBB2 uxtb r3, r3 + 2673 .loc 1 1075 49 discriminator 7 + 2674 00f0 012B cmp r3, #1 + 2675 00f2 0CBF ite eq + 2676 00f4 0123 moveq r3, #1 + 2677 00f6 0023 movne r3, #0 + 2678 00f8 DBB2 uxtb r3, r3 + 2679 00fa 22E0 b .L198 + 2680 .L201: + 2681 .loc 1 1075 49 is_stmt 0 discriminator 8 + 2682 00fc BB68 ldr r3, [r7, #8] + 2683 00fe 0C2B cmp r3, #12 + 2684 0100 09D1 bne .L203 + 2685 .loc 1 1075 12 is_stmt 1 discriminator 10 + 2686 0102 FB68 ldr r3, [r7, #12] + 2687 0104 93F84130 ldrb r3, [r3, #65] + 2688 0108 DBB2 uxtb r3, r3 + 2689 .loc 1 1075 49 discriminator 10 + 2690 010a 012B cmp r3, #1 + 2691 010c 0CBF ite eq + 2692 010e 0123 moveq r3, #1 + 2693 0110 0023 movne r3, #0 + 2694 0112 DBB2 uxtb r3, r3 + 2695 0114 15E0 b .L198 + 2696 .L203: + 2697 .loc 1 1075 49 is_stmt 0 discriminator 11 + 2698 0116 BB68 ldr r3, [r7, #8] + 2699 0118 102B cmp r3, #16 + 2700 011a 09D1 bne .L205 + 2701 .loc 1 1075 12 is_stmt 1 discriminator 13 + 2702 011c FB68 ldr r3, [r7, #12] + 2703 011e 93F84230 ldrb r3, [r3, #66] + 2704 0122 DBB2 uxtb r3, r3 + 2705 .loc 1 1075 49 discriminator 13 + 2706 0124 012B cmp r3, #1 + 2707 0126 0CBF ite eq + 2708 0128 0123 moveq r3, #1 + 2709 012a 0023 movne r3, #0 + 2710 012c DBB2 uxtb r3, r3 + 2711 012e 08E0 b .L198 + 2712 .L205: + 2713 .loc 1 1075 12 discriminator 14 + ARM GAS /tmp/ccl4b9YO.s page 67 + + + 2714 0130 FB68 ldr r3, [r7, #12] + 2715 0132 93F84330 ldrb r3, [r3, #67] + 2716 0136 DBB2 uxtb r3, r3 + 2717 .loc 1 1075 49 discriminator 14 + 2718 0138 012B cmp r3, #1 + 2719 013a 0CBF ite eq + 2720 013c 0123 moveq r3, #1 + 2721 013e 0023 movne r3, #0 + 2722 0140 DBB2 uxtb r3, r3 + 2723 .L198: + 2724 .loc 1 1075 11 discriminator 20 + 2725 0142 002B cmp r3, #0 + 2726 0144 34D0 beq .L207 +1076:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1077:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if ((pData == NULL) || (Length == 0U)) + 2727 .loc 1 1077 8 + 2728 0146 7B68 ldr r3, [r7, #4] + 2729 0148 002B cmp r3, #0 + 2730 014a 02D0 beq .L208 + 2731 .loc 1 1077 25 discriminator 1 + 2732 014c 7B88 ldrh r3, [r7, #2] + 2733 014e 002B cmp r3, #0 + 2734 0150 01D1 bne .L209 + 2735 .L208: +1078:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1079:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 2736 .loc 1 1079 14 + 2737 0152 0123 movs r3, #1 + 2738 0154 48E1 b .L196 + 2739 .L209: +1080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1081:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +1082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + 2740 .loc 1 1083 7 + 2741 0156 BB68 ldr r3, [r7, #8] + 2742 0158 002B cmp r3, #0 + 2743 015a 04D1 bne .L210 + 2744 .loc 1 1083 7 is_stmt 0 discriminator 1 + 2745 015c FB68 ldr r3, [r7, #12] + 2746 015e 0222 movs r2, #2 + 2747 0160 83F83E20 strb r2, [r3, #62] + 2748 0164 26E0 b .L211 + 2749 .L210: + 2750 .loc 1 1083 7 discriminator 2 + 2751 0166 BB68 ldr r3, [r7, #8] + 2752 0168 042B cmp r3, #4 + 2753 016a 04D1 bne .L212 + 2754 .loc 1 1083 7 discriminator 3 + 2755 016c FB68 ldr r3, [r7, #12] + 2756 016e 0222 movs r2, #2 + 2757 0170 83F83F20 strb r2, [r3, #63] + 2758 .loc 1 1083 7 discriminator 18 + 2759 0174 1EE0 b .L211 + 2760 .L212: + 2761 .loc 1 1083 7 discriminator 4 + 2762 0176 BB68 ldr r3, [r7, #8] + ARM GAS /tmp/ccl4b9YO.s page 68 + + + 2763 0178 082B cmp r3, #8 + 2764 017a 04D1 bne .L214 + 2765 .loc 1 1083 7 discriminator 6 + 2766 017c FB68 ldr r3, [r7, #12] + 2767 017e 0222 movs r2, #2 + 2768 0180 83F84020 strb r2, [r3, #64] + 2769 .loc 1 1083 7 discriminator 18 + 2770 0184 16E0 b .L211 + 2771 .L214: + 2772 .loc 1 1083 7 discriminator 7 + 2773 0186 BB68 ldr r3, [r7, #8] + 2774 0188 0C2B cmp r3, #12 + 2775 018a 04D1 bne .L216 + 2776 .loc 1 1083 7 discriminator 9 + 2777 018c FB68 ldr r3, [r7, #12] + 2778 018e 0222 movs r2, #2 + 2779 0190 83F84120 strb r2, [r3, #65] + 2780 .loc 1 1083 7 discriminator 18 + 2781 0194 0EE0 b .L211 + 2782 .L216: + 2783 .loc 1 1083 7 discriminator 10 + 2784 0196 BB68 ldr r3, [r7, #8] + 2785 0198 102B cmp r3, #16 + 2786 019a 04D1 bne .L218 + 2787 .loc 1 1083 7 discriminator 12 + 2788 019c FB68 ldr r3, [r7, #12] + 2789 019e 0222 movs r2, #2 + 2790 01a0 83F84220 strb r2, [r3, #66] + 2791 .loc 1 1083 7 discriminator 18 + 2792 01a4 06E0 b .L211 + 2793 .L218: + 2794 .loc 1 1083 7 discriminator 13 + 2795 01a6 FB68 ldr r3, [r7, #12] + 2796 01a8 0222 movs r2, #2 + 2797 01aa 83F84320 strb r2, [r3, #67] + 2798 01ae 01E0 b .L211 + 2799 .L207: +1084:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1086:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +1087:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 2800 .loc 1 1088 12 is_stmt 1 + 2801 01b0 0123 movs r3, #1 + 2802 01b2 19E1 b .L196 + 2803 .L211: +1089:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1090:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1091:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** switch (Channel) + 2804 .loc 1 1091 3 + 2805 01b4 BB68 ldr r3, [r7, #8] + 2806 01b6 0C2B cmp r3, #12 + 2807 01b8 00F2AE80 bhi .L220 + 2808 01bc 01A2 adr r2, .L222 + 2809 01be 52F823F0 ldr pc, [r2, r3, lsl #2] + 2810 01c2 00BF .p2align 2 + 2811 .L222: + ARM GAS /tmp/ccl4b9YO.s page 69 + + + 2812 01c4 F9010000 .word .L225+1 + 2813 01c8 19030000 .word .L220+1 + 2814 01cc 19030000 .word .L220+1 + 2815 01d0 19030000 .word .L220+1 + 2816 01d4 41020000 .word .L224+1 + 2817 01d8 19030000 .word .L220+1 + 2818 01dc 19030000 .word .L220+1 + 2819 01e0 19030000 .word .L220+1 + 2820 01e4 89020000 .word .L223+1 + 2821 01e8 19030000 .word .L220+1 + 2822 01ec 19030000 .word .L220+1 + 2823 01f0 19030000 .word .L220+1 + 2824 01f4 D1020000 .word .L221+1 + 2825 .p2align 1 + 2826 .L225: +1092:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1093:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_1: +1094:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA compare callbacks */ +1096:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + 2827 .loc 1 1096 17 + 2828 01f8 FB68 ldr r3, [r7, #12] + 2829 01fa 5B6A ldr r3, [r3, #36] + 2830 .loc 1 1096 52 + 2831 01fc 7C4A ldr r2, .L240 + 2832 01fe 9A62 str r2, [r3, #40] +1097:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 2833 .loc 1 1097 17 + 2834 0200 FB68 ldr r3, [r7, #12] + 2835 0202 5B6A ldr r3, [r3, #36] + 2836 .loc 1 1097 56 + 2837 0204 7B4A ldr r2, .L240+4 + 2838 0206 DA62 str r2, [r3, #44] +1098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1099:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA error callback */ +1100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + 2839 .loc 1 1100 17 + 2840 0208 FB68 ldr r3, [r7, #12] + 2841 020a 5B6A ldr r3, [r3, #36] + 2842 .loc 1 1100 53 + 2843 020c 7A4A ldr r2, .L240+8 + 2844 020e 1A63 str r2, [r3, #48] +1101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the DMA channel */ +1103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance-> + 2845 .loc 1 1103 11 + 2846 0210 FB68 ldr r3, [r7, #12] + 2847 0212 586A ldr r0, [r3, #36] + 2848 0214 7968 ldr r1, [r7, #4] + 2849 .loc 1 1103 88 + 2850 0216 FB68 ldr r3, [r7, #12] + 2851 0218 1B68 ldr r3, [r3] + 2852 .loc 1 1103 83 + 2853 021a 3433 adds r3, r3, #52 + 2854 .loc 1 1103 11 + 2855 021c 1A46 mov r2, r3 + 2856 021e 7B88 ldrh r3, [r7, #2] + ARM GAS /tmp/ccl4b9YO.s page 70 + + + 2857 0220 FFF7FEFF bl HAL_DMA_Start_IT + 2858 0224 0346 mov r3, r0 + 2859 .loc 1 1103 10 discriminator 1 + 2860 0226 002B cmp r3, #0 + 2861 0228 01D0 beq .L226 +1104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** Length) != HAL_OK) +1105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return error status */ +1107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 2862 .loc 1 1107 16 + 2863 022a 0123 movs r3, #1 + 2864 022c DCE0 b .L196 + 2865 .L226: +1108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the TIM Capture/Compare 1 DMA request */ +1111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + 2866 .loc 1 1111 7 + 2867 022e FB68 ldr r3, [r7, #12] + 2868 0230 1B68 ldr r3, [r3] + 2869 0232 DA68 ldr r2, [r3, #12] + 2870 0234 FB68 ldr r3, [r7, #12] + 2871 0236 1B68 ldr r3, [r3] + 2872 0238 42F40072 orr r2, r2, #512 + 2873 023c DA60 str r2, [r3, #12] +1112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 2874 .loc 1 1112 7 + 2875 023e 6EE0 b .L227 + 2876 .L224: +1113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_2: +1116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA compare callbacks */ +1118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + 2877 .loc 1 1118 17 + 2878 0240 FB68 ldr r3, [r7, #12] + 2879 0242 9B6A ldr r3, [r3, #40] + 2880 .loc 1 1118 52 + 2881 0244 6A4A ldr r2, .L240 + 2882 0246 9A62 str r2, [r3, #40] +1119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 2883 .loc 1 1119 17 + 2884 0248 FB68 ldr r3, [r7, #12] + 2885 024a 9B6A ldr r3, [r3, #40] + 2886 .loc 1 1119 56 + 2887 024c 694A ldr r2, .L240+4 + 2888 024e DA62 str r2, [r3, #44] +1120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA error callback */ +1122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + 2889 .loc 1 1122 17 + 2890 0250 FB68 ldr r3, [r7, #12] + 2891 0252 9B6A ldr r3, [r3, #40] + 2892 .loc 1 1122 53 + 2893 0254 684A ldr r2, .L240+8 + 2894 0256 1A63 str r2, [r3, #48] + ARM GAS /tmp/ccl4b9YO.s page 71 + + +1123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the DMA channel */ +1125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance-> + 2895 .loc 1 1125 11 + 2896 0258 FB68 ldr r3, [r7, #12] + 2897 025a 986A ldr r0, [r3, #40] + 2898 025c 7968 ldr r1, [r7, #4] + 2899 .loc 1 1125 88 + 2900 025e FB68 ldr r3, [r7, #12] + 2901 0260 1B68 ldr r3, [r3] + 2902 .loc 1 1125 83 + 2903 0262 3833 adds r3, r3, #56 + 2904 .loc 1 1125 11 + 2905 0264 1A46 mov r2, r3 + 2906 0266 7B88 ldrh r3, [r7, #2] + 2907 0268 FFF7FEFF bl HAL_DMA_Start_IT + 2908 026c 0346 mov r3, r0 + 2909 .loc 1 1125 10 discriminator 1 + 2910 026e 002B cmp r3, #0 + 2911 0270 01D0 beq .L228 +1126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** Length) != HAL_OK) +1127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return error status */ +1129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 2912 .loc 1 1129 16 + 2913 0272 0123 movs r3, #1 + 2914 0274 B8E0 b .L196 + 2915 .L228: +1130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the TIM Capture/Compare 2 DMA request */ +1133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + 2916 .loc 1 1133 7 + 2917 0276 FB68 ldr r3, [r7, #12] + 2918 0278 1B68 ldr r3, [r3] + 2919 027a DA68 ldr r2, [r3, #12] + 2920 027c FB68 ldr r3, [r7, #12] + 2921 027e 1B68 ldr r3, [r3] + 2922 0280 42F48062 orr r2, r2, #1024 + 2923 0284 DA60 str r2, [r3, #12] +1134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 2924 .loc 1 1134 7 + 2925 0286 4AE0 b .L227 + 2926 .L223: +1135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_3: +1138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA compare callbacks */ +1140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + 2927 .loc 1 1140 17 + 2928 0288 FB68 ldr r3, [r7, #12] + 2929 028a DB6A ldr r3, [r3, #44] + 2930 .loc 1 1140 52 + 2931 028c 584A ldr r2, .L240 + 2932 028e 9A62 str r2, [r3, #40] +1141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + ARM GAS /tmp/ccl4b9YO.s page 72 + + + 2933 .loc 1 1141 17 + 2934 0290 FB68 ldr r3, [r7, #12] + 2935 0292 DB6A ldr r3, [r3, #44] + 2936 .loc 1 1141 56 + 2937 0294 574A ldr r2, .L240+4 + 2938 0296 DA62 str r2, [r3, #44] +1142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA error callback */ +1144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + 2939 .loc 1 1144 17 + 2940 0298 FB68 ldr r3, [r7, #12] + 2941 029a DB6A ldr r3, [r3, #44] + 2942 .loc 1 1144 53 + 2943 029c 564A ldr r2, .L240+8 + 2944 029e 1A63 str r2, [r3, #48] +1145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the DMA channel */ +1147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance-> + 2945 .loc 1 1147 11 + 2946 02a0 FB68 ldr r3, [r7, #12] + 2947 02a2 D86A ldr r0, [r3, #44] + 2948 02a4 7968 ldr r1, [r7, #4] + 2949 .loc 1 1147 88 + 2950 02a6 FB68 ldr r3, [r7, #12] + 2951 02a8 1B68 ldr r3, [r3] + 2952 .loc 1 1147 83 + 2953 02aa 3C33 adds r3, r3, #60 + 2954 .loc 1 1147 11 + 2955 02ac 1A46 mov r2, r3 + 2956 02ae 7B88 ldrh r3, [r7, #2] + 2957 02b0 FFF7FEFF bl HAL_DMA_Start_IT + 2958 02b4 0346 mov r3, r0 + 2959 .loc 1 1147 10 discriminator 1 + 2960 02b6 002B cmp r3, #0 + 2961 02b8 01D0 beq .L229 +1148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** Length) != HAL_OK) +1149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return error status */ +1151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 2962 .loc 1 1151 16 + 2963 02ba 0123 movs r3, #1 + 2964 02bc 94E0 b .L196 + 2965 .L229: +1152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the TIM Capture/Compare 3 DMA request */ +1154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + 2966 .loc 1 1154 7 + 2967 02be FB68 ldr r3, [r7, #12] + 2968 02c0 1B68 ldr r3, [r3] + 2969 02c2 DA68 ldr r2, [r3, #12] + 2970 02c4 FB68 ldr r3, [r7, #12] + 2971 02c6 1B68 ldr r3, [r3] + 2972 02c8 42F40062 orr r2, r2, #2048 + 2973 02cc DA60 str r2, [r3, #12] +1155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 2974 .loc 1 1155 7 + 2975 02ce 26E0 b .L227 + ARM GAS /tmp/ccl4b9YO.s page 73 + + + 2976 .L221: +1156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_4: +1159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA compare callbacks */ +1161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + 2977 .loc 1 1161 17 + 2978 02d0 FB68 ldr r3, [r7, #12] + 2979 02d2 1B6B ldr r3, [r3, #48] + 2980 .loc 1 1161 52 + 2981 02d4 464A ldr r2, .L240 + 2982 02d6 9A62 str r2, [r3, #40] +1162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 2983 .loc 1 1162 17 + 2984 02d8 FB68 ldr r3, [r7, #12] + 2985 02da 1B6B ldr r3, [r3, #48] + 2986 .loc 1 1162 56 + 2987 02dc 454A ldr r2, .L240+4 + 2988 02de DA62 str r2, [r3, #44] +1163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA error callback */ +1165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + 2989 .loc 1 1165 17 + 2990 02e0 FB68 ldr r3, [r7, #12] + 2991 02e2 1B6B ldr r3, [r3, #48] + 2992 .loc 1 1165 53 + 2993 02e4 444A ldr r2, .L240+8 + 2994 02e6 1A63 str r2, [r3, #48] +1166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the DMA channel */ +1168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance-> + 2995 .loc 1 1168 11 + 2996 02e8 FB68 ldr r3, [r7, #12] + 2997 02ea 186B ldr r0, [r3, #48] + 2998 02ec 7968 ldr r1, [r7, #4] + 2999 .loc 1 1168 88 + 3000 02ee FB68 ldr r3, [r7, #12] + 3001 02f0 1B68 ldr r3, [r3] + 3002 .loc 1 1168 83 + 3003 02f2 4033 adds r3, r3, #64 + 3004 .loc 1 1168 11 + 3005 02f4 1A46 mov r2, r3 + 3006 02f6 7B88 ldrh r3, [r7, #2] + 3007 02f8 FFF7FEFF bl HAL_DMA_Start_IT + 3008 02fc 0346 mov r3, r0 + 3009 .loc 1 1168 10 discriminator 1 + 3010 02fe 002B cmp r3, #0 + 3011 0300 01D0 beq .L230 +1169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** Length) != HAL_OK) +1170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return error status */ +1172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 3012 .loc 1 1172 16 + 3013 0302 0123 movs r3, #1 + 3014 0304 70E0 b .L196 + 3015 .L230: + ARM GAS /tmp/ccl4b9YO.s page 74 + + +1173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the TIM Capture/Compare 4 DMA request */ +1175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + 3016 .loc 1 1175 7 + 3017 0306 FB68 ldr r3, [r7, #12] + 3018 0308 1B68 ldr r3, [r3] + 3019 030a DA68 ldr r2, [r3, #12] + 3020 030c FB68 ldr r3, [r7, #12] + 3021 030e 1B68 ldr r3, [r3] + 3022 0310 42F48052 orr r2, r2, #4096 + 3023 0314 DA60 str r2, [r3, #12] +1176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 3024 .loc 1 1176 7 + 3025 0316 02E0 b .L227 + 3026 .L220: +1177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** default: +1180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** status = HAL_ERROR; + 3027 .loc 1 1180 14 + 3028 0318 0123 movs r3, #1 + 3029 031a FB75 strb r3, [r7, #23] +1181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 3030 .loc 1 1181 7 + 3031 031c 00BF nop + 3032 .L227: +1182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (status == HAL_OK) + 3033 .loc 1 1184 6 + 3034 031e FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 3035 0320 002B cmp r3, #0 + 3036 0322 60D1 bne .L231 +1185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the Output compare channel */ +1187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + 3037 .loc 1 1187 5 + 3038 0324 FB68 ldr r3, [r7, #12] + 3039 0326 1B68 ldr r3, [r3] + 3040 0328 0122 movs r2, #1 + 3041 032a B968 ldr r1, [r7, #8] + 3042 032c 1846 mov r0, r3 + 3043 032e FFF7FEFF bl TIM_CCxChannelCmd +1188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + 3044 .loc 1 1189 9 + 3045 0332 FB68 ldr r3, [r7, #12] + 3046 0334 1B68 ldr r3, [r3] + 3047 0336 314A ldr r2, .L240+12 + 3048 0338 9342 cmp r3, r2 + 3049 033a 0ED0 beq .L232 + 3050 .loc 1 1189 9 is_stmt 0 discriminator 2 + 3051 033c FB68 ldr r3, [r7, #12] + 3052 033e 1B68 ldr r3, [r3] + 3053 0340 2F4A ldr r2, .L240+16 + 3054 0342 9342 cmp r3, r2 + 3055 0344 09D0 beq .L232 + ARM GAS /tmp/ccl4b9YO.s page 75 + + + 3056 .loc 1 1189 9 discriminator 4 + 3057 0346 FB68 ldr r3, [r7, #12] + 3058 0348 1B68 ldr r3, [r3] + 3059 034a 2E4A ldr r2, .L240+20 + 3060 034c 9342 cmp r3, r2 + 3061 034e 04D0 beq .L232 + 3062 .loc 1 1189 9 discriminator 6 + 3063 0350 FB68 ldr r3, [r7, #12] + 3064 0352 1B68 ldr r3, [r3] + 3065 0354 2C4A ldr r2, .L240+24 + 3066 0356 9342 cmp r3, r2 + 3067 0358 01D1 bne .L233 + 3068 .L232: + 3069 .loc 1 1189 9 discriminator 7 + 3070 035a 0123 movs r3, #1 + 3071 .loc 1 1189 9 + 3072 035c 00E0 b .L234 + 3073 .L233: + 3074 .loc 1 1189 9 discriminator 8 + 3075 035e 0023 movs r3, #0 + 3076 .L234: + 3077 .loc 1 1189 8 is_stmt 1 discriminator 10 + 3078 0360 002B cmp r3, #0 + 3079 0362 07D0 beq .L235 +1190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the main output */ +1192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_MOE_ENABLE(htim); + 3080 .loc 1 1192 7 + 3081 0364 FB68 ldr r3, [r7, #12] + 3082 0366 1B68 ldr r3, [r3] + 3083 0368 5A6C ldr r2, [r3, #68] + 3084 036a FB68 ldr r3, [r7, #12] + 3085 036c 1B68 ldr r3, [r3] + 3086 036e 42F40042 orr r2, r2, #32768 + 3087 0372 5A64 str r2, [r3, #68] + 3088 .L235: +1193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigge +1196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 3089 .loc 1 1196 9 + 3090 0374 FB68 ldr r3, [r7, #12] + 3091 0376 1B68 ldr r3, [r3] + 3092 .loc 1 1196 8 + 3093 0378 204A ldr r2, .L240+12 + 3094 037a 9342 cmp r3, r2 + 3095 037c 13D0 beq .L236 + 3096 .loc 1 1196 9 discriminator 1 + 3097 037e FB68 ldr r3, [r7, #12] + 3098 0380 1B68 ldr r3, [r3] + 3099 0382 B3F1804F cmp r3, #1073741824 + 3100 0386 0ED0 beq .L236 + 3101 .loc 1 1196 9 is_stmt 0 discriminator 2 + 3102 0388 FB68 ldr r3, [r7, #12] + 3103 038a 1B68 ldr r3, [r3] + 3104 038c 1F4A ldr r2, .L240+28 + 3105 038e 9342 cmp r3, r2 + ARM GAS /tmp/ccl4b9YO.s page 76 + + + 3106 0390 09D0 beq .L236 + 3107 .loc 1 1196 9 discriminator 3 + 3108 0392 FB68 ldr r3, [r7, #12] + 3109 0394 1B68 ldr r3, [r3] + 3110 0396 1E4A ldr r2, .L240+32 + 3111 0398 9342 cmp r3, r2 + 3112 039a 04D0 beq .L236 + 3113 .loc 1 1196 9 discriminator 4 + 3114 039c FB68 ldr r3, [r7, #12] + 3115 039e 1B68 ldr r3, [r3] + 3116 03a0 174A ldr r2, .L240+16 + 3117 03a2 9342 cmp r3, r2 + 3118 03a4 15D1 bne .L237 + 3119 .L236: +1197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + 3120 .loc 1 1198 21 is_stmt 1 + 3121 03a6 FB68 ldr r3, [r7, #12] + 3122 03a8 1B68 ldr r3, [r3] + 3123 .loc 1 1198 31 + 3124 03aa 9A68 ldr r2, [r3, #8] + 3125 .loc 1 1198 15 + 3126 03ac 194B ldr r3, .L240+36 + 3127 03ae 1340 ands r3, r3, r2 + 3128 03b0 3B61 str r3, [r7, #16] +1199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 3129 .loc 1 1199 10 + 3130 03b2 3B69 ldr r3, [r7, #16] + 3131 03b4 062B cmp r3, #6 + 3132 03b6 15D0 beq .L239 + 3133 .loc 1 1199 11 discriminator 1 + 3134 03b8 3B69 ldr r3, [r7, #16] + 3135 03ba B3F5803F cmp r3, #65536 + 3136 03be 11D0 beq .L239 +1200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); + 3137 .loc 1 1201 9 + 3138 03c0 FB68 ldr r3, [r7, #12] + 3139 03c2 1B68 ldr r3, [r3] + 3140 03c4 1A68 ldr r2, [r3] + 3141 03c6 FB68 ldr r3, [r7, #12] + 3142 03c8 1B68 ldr r3, [r3] + 3143 03ca 42F00102 orr r2, r2, #1 + 3144 03ce 1A60 str r2, [r3] +1199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 3145 .loc 1 1199 10 + 3146 03d0 08E0 b .L239 + 3147 .L237: +1202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +1205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); + 3148 .loc 1 1206 7 + 3149 03d2 FB68 ldr r3, [r7, #12] + 3150 03d4 1B68 ldr r3, [r3] + 3151 03d6 1A68 ldr r2, [r3] + ARM GAS /tmp/ccl4b9YO.s page 77 + + + 3152 03d8 FB68 ldr r3, [r7, #12] + 3153 03da 1B68 ldr r3, [r3] + 3154 03dc 42F00102 orr r2, r2, #1 + 3155 03e0 1A60 str r2, [r3] + 3156 03e2 00E0 b .L231 + 3157 .L239: +1199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 3158 .loc 1 1199 10 + 3159 03e4 00BF nop + 3160 .L231: +1207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return function status */ +1211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return status; + 3161 .loc 1 1211 10 + 3162 03e6 FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 3163 .L196: +1212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 3164 .loc 1 1212 1 + 3165 03e8 1846 mov r0, r3 + 3166 03ea 1837 adds r7, r7, #24 + 3167 .cfi_def_cfa_offset 8 + 3168 03ec BD46 mov sp, r7 + 3169 .cfi_def_cfa_register 13 + 3170 @ sp needed + 3171 03ee 80BD pop {r7, pc} + 3172 .L241: + 3173 .align 2 + 3174 .L240: + 3175 03f0 00000000 .word TIM_DMADelayPulseCplt + 3176 03f4 00000000 .word TIM_DMADelayPulseHalfCplt + 3177 03f8 00000000 .word TIM_DMAError + 3178 03fc 002C0140 .word 1073818624 + 3179 0400 00400140 .word 1073823744 + 3180 0404 00440140 .word 1073824768 + 3181 0408 00480140 .word 1073825792 + 3182 040c 00040040 .word 1073742848 + 3183 0410 00080040 .word 1073743872 + 3184 0414 07000100 .word 65543 + 3185 .cfi_endproc + 3186 .LFE148: + 3188 .section .text.HAL_TIM_OC_Stop_DMA,"ax",%progbits + 3189 .align 1 + 3190 .global HAL_TIM_OC_Stop_DMA + 3191 .syntax unified + 3192 .thumb + 3193 .thumb_func + 3195 HAL_TIM_OC_Stop_DMA: + 3196 .LFB149: +1213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +1215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Stops the TIM Output Compare signal generation in DMA mode. +1216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM Output Compare handle +1217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param Channel TIM Channel to be disabled +1218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +1219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected + ARM GAS /tmp/ccl4b9YO.s page 78 + + +1220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +1221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +1222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +1223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status +1224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +1225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +1226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 3197 .loc 1 1226 1 + 3198 .cfi_startproc + 3199 @ args = 0, pretend = 0, frame = 16 + 3200 @ frame_needed = 1, uses_anonymous_args = 0 + 3201 0000 80B5 push {r7, lr} + 3202 .cfi_def_cfa_offset 8 + 3203 .cfi_offset 7, -8 + 3204 .cfi_offset 14, -4 + 3205 0002 84B0 sub sp, sp, #16 + 3206 .cfi_def_cfa_offset 24 + 3207 0004 00AF add r7, sp, #0 + 3208 .cfi_def_cfa_register 7 + 3209 0006 7860 str r0, [r7, #4] + 3210 0008 3960 str r1, [r7] +1227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 3211 .loc 1 1227 21 + 3212 000a 0023 movs r3, #0 + 3213 000c FB73 strb r3, [r7, #15] +1228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +1230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); +1231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** switch (Channel) + 3214 .loc 1 1232 3 + 3215 000e 3B68 ldr r3, [r7] + 3216 0010 0C2B cmp r3, #12 + 3217 0012 55D8 bhi .L243 + 3218 0014 01A2 adr r2, .L245 + 3219 0016 52F823F0 ldr pc, [r2, r3, lsl #2] + 3220 001a 00BF .p2align 2 + 3221 .L245: + 3222 001c 51000000 .word .L248+1 + 3223 0020 C1000000 .word .L243+1 + 3224 0024 C1000000 .word .L243+1 + 3225 0028 C1000000 .word .L243+1 + 3226 002c 6D000000 .word .L247+1 + 3227 0030 C1000000 .word .L243+1 + 3228 0034 C1000000 .word .L243+1 + 3229 0038 C1000000 .word .L243+1 + 3230 003c 89000000 .word .L246+1 + 3231 0040 C1000000 .word .L243+1 + 3232 0044 C1000000 .word .L243+1 + 3233 0048 C1000000 .word .L243+1 + 3234 004c A5000000 .word .L244+1 + 3235 .p2align 1 + 3236 .L248: +1233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_1: +1235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the TIM Capture/Compare 1 DMA request */ + ARM GAS /tmp/ccl4b9YO.s page 79 + + +1237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + 3237 .loc 1 1237 7 + 3238 0050 7B68 ldr r3, [r7, #4] + 3239 0052 1B68 ldr r3, [r3] + 3240 0054 DA68 ldr r2, [r3, #12] + 3241 0056 7B68 ldr r3, [r7, #4] + 3242 0058 1B68 ldr r3, [r3] + 3243 005a 22F40072 bic r2, r2, #512 + 3244 005e DA60 str r2, [r3, #12] +1238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + 3245 .loc 1 1238 13 + 3246 0060 7B68 ldr r3, [r7, #4] + 3247 0062 5B6A ldr r3, [r3, #36] + 3248 0064 1846 mov r0, r3 + 3249 0066 FFF7FEFF bl HAL_DMA_Abort_IT +1239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 3250 .loc 1 1239 7 + 3251 006a 2CE0 b .L249 + 3252 .L247: +1240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_2: +1243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the TIM Capture/Compare 2 DMA request */ +1245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + 3253 .loc 1 1245 7 + 3254 006c 7B68 ldr r3, [r7, #4] + 3255 006e 1B68 ldr r3, [r3] + 3256 0070 DA68 ldr r2, [r3, #12] + 3257 0072 7B68 ldr r3, [r7, #4] + 3258 0074 1B68 ldr r3, [r3] + 3259 0076 22F48062 bic r2, r2, #1024 + 3260 007a DA60 str r2, [r3, #12] +1246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + 3261 .loc 1 1246 13 + 3262 007c 7B68 ldr r3, [r7, #4] + 3263 007e 9B6A ldr r3, [r3, #40] + 3264 0080 1846 mov r0, r3 + 3265 0082 FFF7FEFF bl HAL_DMA_Abort_IT +1247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 3266 .loc 1 1247 7 + 3267 0086 1EE0 b .L249 + 3268 .L246: +1248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_3: +1251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the TIM Capture/Compare 3 DMA request */ +1253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + 3269 .loc 1 1253 7 + 3270 0088 7B68 ldr r3, [r7, #4] + 3271 008a 1B68 ldr r3, [r3] + 3272 008c DA68 ldr r2, [r3, #12] + 3273 008e 7B68 ldr r3, [r7, #4] + 3274 0090 1B68 ldr r3, [r3] + 3275 0092 22F40062 bic r2, r2, #2048 + 3276 0096 DA60 str r2, [r3, #12] + ARM GAS /tmp/ccl4b9YO.s page 80 + + +1254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + 3277 .loc 1 1254 13 + 3278 0098 7B68 ldr r3, [r7, #4] + 3279 009a DB6A ldr r3, [r3, #44] + 3280 009c 1846 mov r0, r3 + 3281 009e FFF7FEFF bl HAL_DMA_Abort_IT +1255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 3282 .loc 1 1255 7 + 3283 00a2 10E0 b .L249 + 3284 .L244: +1256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_4: +1259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the TIM Capture/Compare 4 interrupt */ +1261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + 3285 .loc 1 1261 7 + 3286 00a4 7B68 ldr r3, [r7, #4] + 3287 00a6 1B68 ldr r3, [r3] + 3288 00a8 DA68 ldr r2, [r3, #12] + 3289 00aa 7B68 ldr r3, [r7, #4] + 3290 00ac 1B68 ldr r3, [r3] + 3291 00ae 22F48052 bic r2, r2, #4096 + 3292 00b2 DA60 str r2, [r3, #12] +1262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + 3293 .loc 1 1262 13 + 3294 00b4 7B68 ldr r3, [r7, #4] + 3295 00b6 1B6B ldr r3, [r3, #48] + 3296 00b8 1846 mov r0, r3 + 3297 00ba FFF7FEFF bl HAL_DMA_Abort_IT +1263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 3298 .loc 1 1263 7 + 3299 00be 02E0 b .L249 + 3300 .L243: +1264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** default: +1267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** status = HAL_ERROR; + 3301 .loc 1 1267 14 + 3302 00c0 0123 movs r3, #1 + 3303 00c2 FB73 strb r3, [r7, #15] +1268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 3304 .loc 1 1268 7 + 3305 00c4 00BF nop + 3306 .L249: +1269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (status == HAL_OK) + 3307 .loc 1 1271 6 + 3308 00c6 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 3309 00c8 002B cmp r3, #0 + 3310 00ca 7BD1 bne .L250 +1272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the Output compare channel */ +1274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + 3311 .loc 1 1274 5 + 3312 00cc 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/ccl4b9YO.s page 81 + + + 3313 00ce 1B68 ldr r3, [r3] + 3314 00d0 0022 movs r2, #0 + 3315 00d2 3968 ldr r1, [r7] + 3316 00d4 1846 mov r0, r3 + 3317 00d6 FFF7FEFF bl TIM_CCxChannelCmd +1275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + 3318 .loc 1 1276 9 + 3319 00da 7B68 ldr r3, [r7, #4] + 3320 00dc 1B68 ldr r3, [r3] + 3321 00de 3C4A ldr r2, .L266 + 3322 00e0 9342 cmp r3, r2 + 3323 00e2 0ED0 beq .L251 + 3324 .loc 1 1276 9 is_stmt 0 discriminator 2 + 3325 00e4 7B68 ldr r3, [r7, #4] + 3326 00e6 1B68 ldr r3, [r3] + 3327 00e8 3A4A ldr r2, .L266+4 + 3328 00ea 9342 cmp r3, r2 + 3329 00ec 09D0 beq .L251 + 3330 .loc 1 1276 9 discriminator 4 + 3331 00ee 7B68 ldr r3, [r7, #4] + 3332 00f0 1B68 ldr r3, [r3] + 3333 00f2 394A ldr r2, .L266+8 + 3334 00f4 9342 cmp r3, r2 + 3335 00f6 04D0 beq .L251 + 3336 .loc 1 1276 9 discriminator 6 + 3337 00f8 7B68 ldr r3, [r7, #4] + 3338 00fa 1B68 ldr r3, [r3] + 3339 00fc 374A ldr r2, .L266+12 + 3340 00fe 9342 cmp r3, r2 + 3341 0100 01D1 bne .L252 + 3342 .L251: + 3343 .loc 1 1276 9 discriminator 7 + 3344 0102 0123 movs r3, #1 + 3345 .loc 1 1276 9 + 3346 0104 00E0 b .L253 + 3347 .L252: + 3348 .loc 1 1276 9 discriminator 8 + 3349 0106 0023 movs r3, #0 + 3350 .L253: + 3351 .loc 1 1276 8 is_stmt 1 discriminator 10 + 3352 0108 002B cmp r3, #0 + 3353 010a 17D0 beq .L254 +1277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the Main Output */ +1279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_MOE_DISABLE(htim); + 3354 .loc 1 1279 7 + 3355 010c 7B68 ldr r3, [r7, #4] + 3356 010e 1B68 ldr r3, [r3] + 3357 0110 1A6A ldr r2, [r3, #32] + 3358 0112 41F21113 movw r3, #4369 + 3359 0116 1340 ands r3, r3, r2 + 3360 0118 002B cmp r3, #0 + 3361 011a 0FD1 bne .L254 + 3362 .loc 1 1279 7 is_stmt 0 discriminator 1 + 3363 011c 7B68 ldr r3, [r7, #4] + 3364 011e 1B68 ldr r3, [r3] + ARM GAS /tmp/ccl4b9YO.s page 82 + + + 3365 0120 1A6A ldr r2, [r3, #32] + 3366 0122 40F24443 movw r3, #1092 + 3367 0126 1340 ands r3, r3, r2 + 3368 0128 002B cmp r3, #0 + 3369 012a 07D1 bne .L254 + 3370 .loc 1 1279 7 discriminator 2 + 3371 012c 7B68 ldr r3, [r7, #4] + 3372 012e 1B68 ldr r3, [r3] + 3373 0130 5A6C ldr r2, [r3, #68] + 3374 0132 7B68 ldr r3, [r7, #4] + 3375 0134 1B68 ldr r3, [r3] + 3376 0136 22F40042 bic r2, r2, #32768 + 3377 013a 5A64 str r2, [r3, #68] + 3378 .L254: +1280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the Peripheral */ +1283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); + 3379 .loc 1 1283 5 is_stmt 1 + 3380 013c 7B68 ldr r3, [r7, #4] + 3381 013e 1B68 ldr r3, [r3] + 3382 0140 1A6A ldr r2, [r3, #32] + 3383 0142 41F21113 movw r3, #4369 + 3384 0146 1340 ands r3, r3, r2 + 3385 0148 002B cmp r3, #0 + 3386 014a 0FD1 bne .L255 + 3387 .loc 1 1283 5 is_stmt 0 discriminator 1 + 3388 014c 7B68 ldr r3, [r7, #4] + 3389 014e 1B68 ldr r3, [r3] + 3390 0150 1A6A ldr r2, [r3, #32] + 3391 0152 40F24443 movw r3, #1092 + 3392 0156 1340 ands r3, r3, r2 + 3393 0158 002B cmp r3, #0 + 3394 015a 07D1 bne .L255 + 3395 .loc 1 1283 5 discriminator 2 + 3396 015c 7B68 ldr r3, [r7, #4] + 3397 015e 1B68 ldr r3, [r3] + 3398 0160 1A68 ldr r2, [r3] + 3399 0162 7B68 ldr r3, [r7, #4] + 3400 0164 1B68 ldr r3, [r3] + 3401 0166 22F00102 bic r2, r2, #1 + 3402 016a 1A60 str r2, [r3] + 3403 .L255: +1284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the TIM channel state */ +1286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 3404 .loc 1 1286 5 is_stmt 1 + 3405 016c 3B68 ldr r3, [r7] + 3406 016e 002B cmp r3, #0 + 3407 0170 04D1 bne .L256 + 3408 .loc 1 1286 5 is_stmt 0 discriminator 1 + 3409 0172 7B68 ldr r3, [r7, #4] + 3410 0174 0122 movs r2, #1 + 3411 0176 83F83E20 strb r2, [r3, #62] + 3412 017a 23E0 b .L250 + 3413 .L256: + 3414 .loc 1 1286 5 discriminator 2 + ARM GAS /tmp/ccl4b9YO.s page 83 + + + 3415 017c 3B68 ldr r3, [r7] + 3416 017e 042B cmp r3, #4 + 3417 0180 04D1 bne .L257 + 3418 .loc 1 1286 5 discriminator 3 + 3419 0182 7B68 ldr r3, [r7, #4] + 3420 0184 0122 movs r2, #1 + 3421 0186 83F83F20 strb r2, [r3, #63] + 3422 018a 1BE0 b .L250 + 3423 .L257: + 3424 .loc 1 1286 5 discriminator 4 + 3425 018c 3B68 ldr r3, [r7] + 3426 018e 082B cmp r3, #8 + 3427 0190 04D1 bne .L259 + 3428 .loc 1 1286 5 discriminator 6 + 3429 0192 7B68 ldr r3, [r7, #4] + 3430 0194 0122 movs r2, #1 + 3431 0196 83F84020 strb r2, [r3, #64] + 3432 019a 13E0 b .L250 + 3433 .L259: + 3434 .loc 1 1286 5 discriminator 7 + 3435 019c 3B68 ldr r3, [r7] + 3436 019e 0C2B cmp r3, #12 + 3437 01a0 04D1 bne .L261 + 3438 .loc 1 1286 5 discriminator 9 + 3439 01a2 7B68 ldr r3, [r7, #4] + 3440 01a4 0122 movs r2, #1 + 3441 01a6 83F84120 strb r2, [r3, #65] + 3442 01aa 0BE0 b .L250 + 3443 .L261: + 3444 .loc 1 1286 5 discriminator 10 + 3445 01ac 3B68 ldr r3, [r7] + 3446 01ae 102B cmp r3, #16 + 3447 01b0 04D1 bne .L263 + 3448 .loc 1 1286 5 discriminator 12 + 3449 01b2 7B68 ldr r3, [r7, #4] + 3450 01b4 0122 movs r2, #1 + 3451 01b6 83F84220 strb r2, [r3, #66] + 3452 01ba 03E0 b .L250 + 3453 .L263: + 3454 .loc 1 1286 5 discriminator 13 + 3455 01bc 7B68 ldr r3, [r7, #4] + 3456 01be 0122 movs r2, #1 + 3457 01c0 83F84320 strb r2, [r3, #67] + 3458 .L250: +1287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return function status */ +1290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return status; + 3459 .loc 1 1290 10 is_stmt 1 + 3460 01c4 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 +1291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 3461 .loc 1 1291 1 + 3462 01c6 1846 mov r0, r3 + 3463 01c8 1037 adds r7, r7, #16 + 3464 .cfi_def_cfa_offset 8 + 3465 01ca BD46 mov sp, r7 + 3466 .cfi_def_cfa_register 13 + ARM GAS /tmp/ccl4b9YO.s page 84 + + + 3467 @ sp needed + 3468 01cc 80BD pop {r7, pc} + 3469 .L267: + 3470 01ce 00BF .align 2 + 3471 .L266: + 3472 01d0 002C0140 .word 1073818624 + 3473 01d4 00400140 .word 1073823744 + 3474 01d8 00440140 .word 1073824768 + 3475 01dc 00480140 .word 1073825792 + 3476 .cfi_endproc + 3477 .LFE149: + 3479 .section .text.HAL_TIM_PWM_Init,"ax",%progbits + 3480 .align 1 + 3481 .global HAL_TIM_PWM_Init + 3482 .syntax unified + 3483 .thumb + 3484 .thumb_func + 3486 HAL_TIM_PWM_Init: + 3487 .LFB150: +1292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +1294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @} +1295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +1296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions +1298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief TIM PWM functions +1299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * +1300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** @verbatim +1301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** ============================================================================== +1302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** ##### TIM PWM functions ##### +1303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** ============================================================================== +1304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** [..] +1305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** This section provides functions allowing to: +1306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Initialize and configure the TIM PWM. +1307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) De-initialize the TIM PWM. +1308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Start the TIM PWM. +1309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Stop the TIM PWM. +1310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Start the TIM PWM and enable interrupt. +1311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Stop the TIM PWM and disable interrupt. +1312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Start the TIM PWM and enable DMA transfer. +1313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Stop the TIM PWM and disable DMA transfer. +1314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** @endverbatim +1316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @{ +1317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +1318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +1319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Initializes the TIM PWM Time Base according to the specified +1320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * parameters in the TIM_HandleTypeDef and initializes the associated handle. +1321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) +1322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * requires a timer reset to avoid unexpected direction +1323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * due to DIR bit readonly in center aligned mode. +1324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() +1325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM PWM handle +1326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status +1327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +1328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) +1329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + ARM GAS /tmp/ccl4b9YO.s page 85 + + + 3488 .loc 1 1329 1 + 3489 .cfi_startproc + 3490 @ args = 0, pretend = 0, frame = 8 + 3491 @ frame_needed = 1, uses_anonymous_args = 0 + 3492 0000 80B5 push {r7, lr} + 3493 .cfi_def_cfa_offset 8 + 3494 .cfi_offset 7, -8 + 3495 .cfi_offset 14, -4 + 3496 0002 82B0 sub sp, sp, #8 + 3497 .cfi_def_cfa_offset 16 + 3498 0004 00AF add r7, sp, #0 + 3499 .cfi_def_cfa_register 7 + 3500 0006 7860 str r0, [r7, #4] +1330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the TIM handle allocation */ +1331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (htim == NULL) + 3501 .loc 1 1331 6 + 3502 0008 7B68 ldr r3, [r7, #4] + 3503 000a 002B cmp r3, #0 + 3504 000c 01D1 bne .L269 +1332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 3505 .loc 1 1333 12 + 3506 000e 0123 movs r3, #1 + 3507 0010 49E0 b .L270 + 3508 .L269: +1334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +1337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_INSTANCE(htim->Instance)); +1338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); +1339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); +1340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); +1341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); +1342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (htim->State == HAL_TIM_STATE_RESET) + 3509 .loc 1 1343 11 + 3510 0012 7B68 ldr r3, [r7, #4] + 3511 0014 93F83D30 ldrb r3, [r3, #61] + 3512 0018 DBB2 uxtb r3, r3 + 3513 .loc 1 1343 6 + 3514 001a 002B cmp r3, #0 + 3515 001c 06D1 bne .L271 +1344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Allocate lock resource and initialize it */ +1346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Lock = HAL_UNLOCKED; + 3516 .loc 1 1346 16 + 3517 001e 7B68 ldr r3, [r7, #4] + 3518 0020 0022 movs r2, #0 + 3519 0022 83F83C20 strb r2, [r3, #60] +1347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +1349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Reset interrupt callbacks to legacy weak callbacks */ +1350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_ResetCallback(htim); +1351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (htim->PWM_MspInitCallback == NULL) +1353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; + ARM GAS /tmp/ccl4b9YO.s page 86 + + +1355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Init the low level hardware : GPIO, CLOCK, NVIC */ +1357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->PWM_MspInitCallback(htim); +1358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #else +1359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ +1360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_PWM_MspInit(htim); + 3520 .loc 1 1360 5 + 3521 0026 7868 ldr r0, [r7, #4] + 3522 0028 FFF7FEFF bl HAL_TIM_PWM_MspInit + 3523 .L271: +1361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +1362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the TIM state */ +1365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; + 3524 .loc 1 1365 15 + 3525 002c 7B68 ldr r3, [r7, #4] + 3526 002e 0222 movs r2, #2 + 3527 0030 83F83D20 strb r2, [r3, #61] +1366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Init the base time for the PWM */ +1368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_Base_SetConfig(htim->Instance, &htim->Init); + 3528 .loc 1 1368 3 + 3529 0034 7B68 ldr r3, [r7, #4] + 3530 0036 1A68 ldr r2, [r3] + 3531 .loc 1 1368 38 + 3532 0038 7B68 ldr r3, [r7, #4] + 3533 003a 0433 adds r3, r3, #4 + 3534 .loc 1 1368 3 + 3535 003c 1946 mov r1, r3 + 3536 003e 1046 mov r0, r2 + 3537 0040 FFF7FEFF bl TIM_Base_SetConfig +1369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Initialize the DMA burst operation state */ +1371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + 3538 .loc 1 1371 23 + 3539 0044 7B68 ldr r3, [r7, #4] + 3540 0046 0122 movs r2, #1 + 3541 0048 83F84820 strb r2, [r3, #72] +1372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Initialize the TIM channels state */ +1374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 3542 .loc 1 1374 3 + 3543 004c 7B68 ldr r3, [r7, #4] + 3544 004e 0122 movs r2, #1 + 3545 0050 83F83E20 strb r2, [r3, #62] + 3546 0054 7B68 ldr r3, [r7, #4] + 3547 0056 0122 movs r2, #1 + 3548 0058 83F83F20 strb r2, [r3, #63] + 3549 005c 7B68 ldr r3, [r7, #4] + 3550 005e 0122 movs r2, #1 + 3551 0060 83F84020 strb r2, [r3, #64] + 3552 0064 7B68 ldr r3, [r7, #4] + 3553 0066 0122 movs r2, #1 + 3554 0068 83F84120 strb r2, [r3, #65] + 3555 006c 7B68 ldr r3, [r7, #4] + 3556 006e 0122 movs r2, #1 + ARM GAS /tmp/ccl4b9YO.s page 87 + + + 3557 0070 83F84220 strb r2, [r3, #66] + 3558 0074 7B68 ldr r3, [r7, #4] + 3559 0076 0122 movs r2, #1 + 3560 0078 83F84320 strb r2, [r3, #67] +1375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 3561 .loc 1 1375 3 + 3562 007c 7B68 ldr r3, [r7, #4] + 3563 007e 0122 movs r2, #1 + 3564 0080 83F84420 strb r2, [r3, #68] + 3565 0084 7B68 ldr r3, [r7, #4] + 3566 0086 0122 movs r2, #1 + 3567 0088 83F84520 strb r2, [r3, #69] + 3568 008c 7B68 ldr r3, [r7, #4] + 3569 008e 0122 movs r2, #1 + 3570 0090 83F84620 strb r2, [r3, #70] + 3571 0094 7B68 ldr r3, [r7, #4] + 3572 0096 0122 movs r2, #1 + 3573 0098 83F84720 strb r2, [r3, #71] +1376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Initialize the TIM state*/ +1378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; + 3574 .loc 1 1378 15 + 3575 009c 7B68 ldr r3, [r7, #4] + 3576 009e 0122 movs r2, #1 + 3577 00a0 83F83D20 strb r2, [r3, #61] +1379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_OK; + 3578 .loc 1 1380 10 + 3579 00a4 0023 movs r3, #0 + 3580 .L270: +1381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 3581 .loc 1 1381 1 + 3582 00a6 1846 mov r0, r3 + 3583 00a8 0837 adds r7, r7, #8 + 3584 .cfi_def_cfa_offset 8 + 3585 00aa BD46 mov sp, r7 + 3586 .cfi_def_cfa_register 13 + 3587 @ sp needed + 3588 00ac 80BD pop {r7, pc} + 3589 .cfi_endproc + 3590 .LFE150: + 3592 .section .text.HAL_TIM_PWM_DeInit,"ax",%progbits + 3593 .align 1 + 3594 .global HAL_TIM_PWM_DeInit + 3595 .syntax unified + 3596 .thumb + 3597 .thumb_func + 3599 HAL_TIM_PWM_DeInit: + 3600 .LFB151: +1382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +1384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief DeInitializes the TIM peripheral +1385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM PWM handle +1386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status +1387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +1388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) +1389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + ARM GAS /tmp/ccl4b9YO.s page 88 + + + 3601 .loc 1 1389 1 + 3602 .cfi_startproc + 3603 @ args = 0, pretend = 0, frame = 8 + 3604 @ frame_needed = 1, uses_anonymous_args = 0 + 3605 0000 80B5 push {r7, lr} + 3606 .cfi_def_cfa_offset 8 + 3607 .cfi_offset 7, -8 + 3608 .cfi_offset 14, -4 + 3609 0002 82B0 sub sp, sp, #8 + 3610 .cfi_def_cfa_offset 16 + 3611 0004 00AF add r7, sp, #0 + 3612 .cfi_def_cfa_register 7 + 3613 0006 7860 str r0, [r7, #4] +1390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +1391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_INSTANCE(htim->Instance)); +1392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; + 3614 .loc 1 1393 15 + 3615 0008 7B68 ldr r3, [r7, #4] + 3616 000a 0222 movs r2, #2 + 3617 000c 83F83D20 strb r2, [r3, #61] +1394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the TIM Peripheral Clock */ +1396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); + 3618 .loc 1 1396 3 + 3619 0010 7B68 ldr r3, [r7, #4] + 3620 0012 1B68 ldr r3, [r3] + 3621 0014 1A6A ldr r2, [r3, #32] + 3622 0016 41F21113 movw r3, #4369 + 3623 001a 1340 ands r3, r3, r2 + 3624 001c 002B cmp r3, #0 + 3625 001e 0FD1 bne .L273 + 3626 .loc 1 1396 3 is_stmt 0 discriminator 1 + 3627 0020 7B68 ldr r3, [r7, #4] + 3628 0022 1B68 ldr r3, [r3] + 3629 0024 1A6A ldr r2, [r3, #32] + 3630 0026 40F24443 movw r3, #1092 + 3631 002a 1340 ands r3, r3, r2 + 3632 002c 002B cmp r3, #0 + 3633 002e 07D1 bne .L273 + 3634 .loc 1 1396 3 discriminator 2 + 3635 0030 7B68 ldr r3, [r7, #4] + 3636 0032 1B68 ldr r3, [r3] + 3637 0034 1A68 ldr r2, [r3] + 3638 0036 7B68 ldr r3, [r7, #4] + 3639 0038 1B68 ldr r3, [r3] + 3640 003a 22F00102 bic r2, r2, #1 + 3641 003e 1A60 str r2, [r3] + 3642 .L273: +1397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +1399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (htim->PWM_MspDeInitCallback == NULL) +1400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; +1402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* DeInit the low level hardware */ +1404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->PWM_MspDeInitCallback(htim); + ARM GAS /tmp/ccl4b9YO.s page 89 + + +1405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #else +1406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ +1407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_PWM_MspDeInit(htim); + 3643 .loc 1 1407 3 is_stmt 1 + 3644 0040 7868 ldr r0, [r7, #4] + 3645 0042 FFF7FEFF bl HAL_TIM_PWM_MspDeInit +1408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +1409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Change the DMA burst operation state */ +1411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + 3646 .loc 1 1411 23 + 3647 0046 7B68 ldr r3, [r7, #4] + 3648 0048 0022 movs r2, #0 + 3649 004a 83F84820 strb r2, [r3, #72] +1412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Change the TIM channels state */ +1414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + 3650 .loc 1 1414 3 + 3651 004e 7B68 ldr r3, [r7, #4] + 3652 0050 0022 movs r2, #0 + 3653 0052 83F83E20 strb r2, [r3, #62] + 3654 0056 7B68 ldr r3, [r7, #4] + 3655 0058 0022 movs r2, #0 + 3656 005a 83F83F20 strb r2, [r3, #63] + 3657 005e 7B68 ldr r3, [r7, #4] + 3658 0060 0022 movs r2, #0 + 3659 0062 83F84020 strb r2, [r3, #64] + 3660 0066 7B68 ldr r3, [r7, #4] + 3661 0068 0022 movs r2, #0 + 3662 006a 83F84120 strb r2, [r3, #65] + 3663 006e 7B68 ldr r3, [r7, #4] + 3664 0070 0022 movs r2, #0 + 3665 0072 83F84220 strb r2, [r3, #66] + 3666 0076 7B68 ldr r3, [r7, #4] + 3667 0078 0022 movs r2, #0 + 3668 007a 83F84320 strb r2, [r3, #67] +1415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + 3669 .loc 1 1415 3 + 3670 007e 7B68 ldr r3, [r7, #4] + 3671 0080 0022 movs r2, #0 + 3672 0082 83F84420 strb r2, [r3, #68] + 3673 0086 7B68 ldr r3, [r7, #4] + 3674 0088 0022 movs r2, #0 + 3675 008a 83F84520 strb r2, [r3, #69] + 3676 008e 7B68 ldr r3, [r7, #4] + 3677 0090 0022 movs r2, #0 + 3678 0092 83F84620 strb r2, [r3, #70] + 3679 0096 7B68 ldr r3, [r7, #4] + 3680 0098 0022 movs r2, #0 + 3681 009a 83F84720 strb r2, [r3, #71] +1416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Change TIM state */ +1418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->State = HAL_TIM_STATE_RESET; + 3682 .loc 1 1418 15 + 3683 009e 7B68 ldr r3, [r7, #4] + 3684 00a0 0022 movs r2, #0 + 3685 00a2 83F83D20 strb r2, [r3, #61] + ARM GAS /tmp/ccl4b9YO.s page 90 + + +1419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Release Lock */ +1421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_UNLOCK(htim); + 3686 .loc 1 1421 3 + 3687 00a6 7B68 ldr r3, [r7, #4] + 3688 00a8 0022 movs r2, #0 + 3689 00aa 83F83C20 strb r2, [r3, #60] +1422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_OK; + 3690 .loc 1 1423 10 + 3691 00ae 0023 movs r3, #0 +1424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 3692 .loc 1 1424 1 + 3693 00b0 1846 mov r0, r3 + 3694 00b2 0837 adds r7, r7, #8 + 3695 .cfi_def_cfa_offset 8 + 3696 00b4 BD46 mov sp, r7 + 3697 .cfi_def_cfa_register 13 + 3698 @ sp needed + 3699 00b6 80BD pop {r7, pc} + 3700 .cfi_endproc + 3701 .LFE151: + 3703 .section .text.HAL_TIM_PWM_MspInit,"ax",%progbits + 3704 .align 1 + 3705 .weak HAL_TIM_PWM_MspInit + 3706 .syntax unified + 3707 .thumb + 3708 .thumb_func + 3710 HAL_TIM_PWM_MspInit: + 3711 .LFB152: +1425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +1427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Initializes the TIM PWM MSP. +1428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM PWM handle +1429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval None +1430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +1431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) +1432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 3712 .loc 1 1432 1 + 3713 .cfi_startproc + 3714 @ args = 0, pretend = 0, frame = 8 + 3715 @ frame_needed = 1, uses_anonymous_args = 0 + 3716 @ link register save eliminated. + 3717 0000 80B4 push {r7} + 3718 .cfi_def_cfa_offset 4 + 3719 .cfi_offset 7, -4 + 3720 0002 83B0 sub sp, sp, #12 + 3721 .cfi_def_cfa_offset 16 + 3722 0004 00AF add r7, sp, #0 + 3723 .cfi_def_cfa_register 7 + 3724 0006 7860 str r0, [r7, #4] +1433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +1434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** UNUSED(htim); +1435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* NOTE : This function should not be modified, when the callback is needed, +1437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** the HAL_TIM_PWM_MspInit could be implemented in the user file +1438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ + ARM GAS /tmp/ccl4b9YO.s page 91 + + +1439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 3725 .loc 1 1439 1 + 3726 0008 00BF nop + 3727 000a 0C37 adds r7, r7, #12 + 3728 .cfi_def_cfa_offset 4 + 3729 000c BD46 mov sp, r7 + 3730 .cfi_def_cfa_register 13 + 3731 @ sp needed + 3732 000e 5DF8047B ldr r7, [sp], #4 + 3733 .cfi_restore 7 + 3734 .cfi_def_cfa_offset 0 + 3735 0012 7047 bx lr + 3736 .cfi_endproc + 3737 .LFE152: + 3739 .section .text.HAL_TIM_PWM_MspDeInit,"ax",%progbits + 3740 .align 1 + 3741 .weak HAL_TIM_PWM_MspDeInit + 3742 .syntax unified + 3743 .thumb + 3744 .thumb_func + 3746 HAL_TIM_PWM_MspDeInit: + 3747 .LFB153: +1440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +1442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief DeInitializes TIM PWM MSP. +1443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM PWM handle +1444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval None +1445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +1446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) +1447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 3748 .loc 1 1447 1 + 3749 .cfi_startproc + 3750 @ args = 0, pretend = 0, frame = 8 + 3751 @ frame_needed = 1, uses_anonymous_args = 0 + 3752 @ link register save eliminated. + 3753 0000 80B4 push {r7} + 3754 .cfi_def_cfa_offset 4 + 3755 .cfi_offset 7, -4 + 3756 0002 83B0 sub sp, sp, #12 + 3757 .cfi_def_cfa_offset 16 + 3758 0004 00AF add r7, sp, #0 + 3759 .cfi_def_cfa_register 7 + 3760 0006 7860 str r0, [r7, #4] +1448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +1449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** UNUSED(htim); +1450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* NOTE : This function should not be modified, when the callback is needed, +1452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** the HAL_TIM_PWM_MspDeInit could be implemented in the user file +1453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +1454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 3761 .loc 1 1454 1 + 3762 0008 00BF nop + 3763 000a 0C37 adds r7, r7, #12 + 3764 .cfi_def_cfa_offset 4 + 3765 000c BD46 mov sp, r7 + 3766 .cfi_def_cfa_register 13 + 3767 @ sp needed + ARM GAS /tmp/ccl4b9YO.s page 92 + + + 3768 000e 5DF8047B ldr r7, [sp], #4 + 3769 .cfi_restore 7 + 3770 .cfi_def_cfa_offset 0 + 3771 0012 7047 bx lr + 3772 .cfi_endproc + 3773 .LFE153: + 3775 .section .text.HAL_TIM_PWM_Start,"ax",%progbits + 3776 .align 1 + 3777 .global HAL_TIM_PWM_Start + 3778 .syntax unified + 3779 .thumb + 3780 .thumb_func + 3782 HAL_TIM_PWM_Start: + 3783 .LFB154: +1455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +1457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Starts the PWM signal generation. +1458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM handle +1459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param Channel TIM Channels to be enabled +1460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +1461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +1462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +1463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +1464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +1465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) +1466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) +1467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * (*) Value not defined for all devices +1468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status +1469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +1470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +1471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 3784 .loc 1 1471 1 + 3785 .cfi_startproc + 3786 @ args = 0, pretend = 0, frame = 16 + 3787 @ frame_needed = 1, uses_anonymous_args = 0 + 3788 0000 80B5 push {r7, lr} + 3789 .cfi_def_cfa_offset 8 + 3790 .cfi_offset 7, -8 + 3791 .cfi_offset 14, -4 + 3792 0002 84B0 sub sp, sp, #16 + 3793 .cfi_def_cfa_offset 24 + 3794 0004 00AF add r7, sp, #0 + 3795 .cfi_def_cfa_register 7 + 3796 0006 7860 str r0, [r7, #4] + 3797 0008 3960 str r1, [r7] +1472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpsmcr; +1473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +1475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); +1476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the TIM channel state */ +1478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + 3798 .loc 1 1478 44 + 3799 000a 3B68 ldr r3, [r7] + 3800 000c 002B cmp r3, #0 + 3801 000e 09D1 bne .L278 + 3802 .loc 1 1478 7 discriminator 1 + ARM GAS /tmp/ccl4b9YO.s page 93 + + + 3803 0010 7B68 ldr r3, [r7, #4] + 3804 0012 93F83E30 ldrb r3, [r3, #62] + 3805 0016 DBB2 uxtb r3, r3 + 3806 .loc 1 1478 44 discriminator 1 + 3807 0018 012B cmp r3, #1 + 3808 001a 14BF ite ne + 3809 001c 0123 movne r3, #1 + 3810 001e 0023 moveq r3, #0 + 3811 0020 DBB2 uxtb r3, r3 + 3812 0022 3CE0 b .L279 + 3813 .L278: + 3814 .loc 1 1478 44 is_stmt 0 discriminator 2 + 3815 0024 3B68 ldr r3, [r7] + 3816 0026 042B cmp r3, #4 + 3817 0028 09D1 bne .L280 + 3818 .loc 1 1478 7 is_stmt 1 discriminator 4 + 3819 002a 7B68 ldr r3, [r7, #4] + 3820 002c 93F83F30 ldrb r3, [r3, #63] + 3821 0030 DBB2 uxtb r3, r3 + 3822 .loc 1 1478 44 discriminator 4 + 3823 0032 012B cmp r3, #1 + 3824 0034 14BF ite ne + 3825 0036 0123 movne r3, #1 + 3826 0038 0023 moveq r3, #0 + 3827 003a DBB2 uxtb r3, r3 + 3828 003c 2FE0 b .L279 + 3829 .L280: + 3830 .loc 1 1478 44 is_stmt 0 discriminator 5 + 3831 003e 3B68 ldr r3, [r7] + 3832 0040 082B cmp r3, #8 + 3833 0042 09D1 bne .L282 + 3834 .loc 1 1478 7 is_stmt 1 discriminator 7 + 3835 0044 7B68 ldr r3, [r7, #4] + 3836 0046 93F84030 ldrb r3, [r3, #64] + 3837 004a DBB2 uxtb r3, r3 + 3838 .loc 1 1478 44 discriminator 7 + 3839 004c 012B cmp r3, #1 + 3840 004e 14BF ite ne + 3841 0050 0123 movne r3, #1 + 3842 0052 0023 moveq r3, #0 + 3843 0054 DBB2 uxtb r3, r3 + 3844 0056 22E0 b .L279 + 3845 .L282: + 3846 .loc 1 1478 44 is_stmt 0 discriminator 8 + 3847 0058 3B68 ldr r3, [r7] + 3848 005a 0C2B cmp r3, #12 + 3849 005c 09D1 bne .L284 + 3850 .loc 1 1478 7 is_stmt 1 discriminator 10 + 3851 005e 7B68 ldr r3, [r7, #4] + 3852 0060 93F84130 ldrb r3, [r3, #65] + 3853 0064 DBB2 uxtb r3, r3 + 3854 .loc 1 1478 44 discriminator 10 + 3855 0066 012B cmp r3, #1 + 3856 0068 14BF ite ne + 3857 006a 0123 movne r3, #1 + 3858 006c 0023 moveq r3, #0 + 3859 006e DBB2 uxtb r3, r3 + ARM GAS /tmp/ccl4b9YO.s page 94 + + + 3860 0070 15E0 b .L279 + 3861 .L284: + 3862 .loc 1 1478 44 is_stmt 0 discriminator 11 + 3863 0072 3B68 ldr r3, [r7] + 3864 0074 102B cmp r3, #16 + 3865 0076 09D1 bne .L286 + 3866 .loc 1 1478 7 is_stmt 1 discriminator 13 + 3867 0078 7B68 ldr r3, [r7, #4] + 3868 007a 93F84230 ldrb r3, [r3, #66] + 3869 007e DBB2 uxtb r3, r3 + 3870 .loc 1 1478 44 discriminator 13 + 3871 0080 012B cmp r3, #1 + 3872 0082 14BF ite ne + 3873 0084 0123 movne r3, #1 + 3874 0086 0023 moveq r3, #0 + 3875 0088 DBB2 uxtb r3, r3 + 3876 008a 08E0 b .L279 + 3877 .L286: + 3878 .loc 1 1478 7 discriminator 14 + 3879 008c 7B68 ldr r3, [r7, #4] + 3880 008e 93F84330 ldrb r3, [r3, #67] + 3881 0092 DBB2 uxtb r3, r3 + 3882 .loc 1 1478 44 discriminator 14 + 3883 0094 012B cmp r3, #1 + 3884 0096 14BF ite ne + 3885 0098 0123 movne r3, #1 + 3886 009a 0023 moveq r3, #0 + 3887 009c DBB2 uxtb r3, r3 + 3888 .L279: + 3889 .loc 1 1478 6 discriminator 20 + 3890 009e 002B cmp r3, #0 + 3891 00a0 01D0 beq .L288 +1479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 3892 .loc 1 1480 12 + 3893 00a2 0123 movs r3, #1 + 3894 00a4 8DE0 b .L289 + 3895 .L288: +1481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the TIM channel state */ +1484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + 3896 .loc 1 1484 3 + 3897 00a6 3B68 ldr r3, [r7] + 3898 00a8 002B cmp r3, #0 + 3899 00aa 04D1 bne .L290 + 3900 .loc 1 1484 3 is_stmt 0 discriminator 1 + 3901 00ac 7B68 ldr r3, [r7, #4] + 3902 00ae 0222 movs r2, #2 + 3903 00b0 83F83E20 strb r2, [r3, #62] + 3904 00b4 23E0 b .L291 + 3905 .L290: + 3906 .loc 1 1484 3 discriminator 2 + 3907 00b6 3B68 ldr r3, [r7] + 3908 00b8 042B cmp r3, #4 + 3909 00ba 04D1 bne .L292 + 3910 .loc 1 1484 3 discriminator 3 + ARM GAS /tmp/ccl4b9YO.s page 95 + + + 3911 00bc 7B68 ldr r3, [r7, #4] + 3912 00be 0222 movs r2, #2 + 3913 00c0 83F83F20 strb r2, [r3, #63] + 3914 00c4 1BE0 b .L291 + 3915 .L292: + 3916 .loc 1 1484 3 discriminator 4 + 3917 00c6 3B68 ldr r3, [r7] + 3918 00c8 082B cmp r3, #8 + 3919 00ca 04D1 bne .L294 + 3920 .loc 1 1484 3 discriminator 6 + 3921 00cc 7B68 ldr r3, [r7, #4] + 3922 00ce 0222 movs r2, #2 + 3923 00d0 83F84020 strb r2, [r3, #64] + 3924 00d4 13E0 b .L291 + 3925 .L294: + 3926 .loc 1 1484 3 discriminator 7 + 3927 00d6 3B68 ldr r3, [r7] + 3928 00d8 0C2B cmp r3, #12 + 3929 00da 04D1 bne .L296 + 3930 .loc 1 1484 3 discriminator 9 + 3931 00dc 7B68 ldr r3, [r7, #4] + 3932 00de 0222 movs r2, #2 + 3933 00e0 83F84120 strb r2, [r3, #65] + 3934 00e4 0BE0 b .L291 + 3935 .L296: + 3936 .loc 1 1484 3 discriminator 10 + 3937 00e6 3B68 ldr r3, [r7] + 3938 00e8 102B cmp r3, #16 + 3939 00ea 04D1 bne .L298 + 3940 .loc 1 1484 3 discriminator 12 + 3941 00ec 7B68 ldr r3, [r7, #4] + 3942 00ee 0222 movs r2, #2 + 3943 00f0 83F84220 strb r2, [r3, #66] + 3944 00f4 03E0 b .L291 + 3945 .L298: + 3946 .loc 1 1484 3 discriminator 13 + 3947 00f6 7B68 ldr r3, [r7, #4] + 3948 00f8 0222 movs r2, #2 + 3949 00fa 83F84320 strb r2, [r3, #67] + 3950 .L291: +1485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the Capture compare channel */ +1487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + 3951 .loc 1 1487 3 is_stmt 1 + 3952 00fe 7B68 ldr r3, [r7, #4] + 3953 0100 1B68 ldr r3, [r3] + 3954 0102 0122 movs r2, #1 + 3955 0104 3968 ldr r1, [r7] + 3956 0106 1846 mov r0, r3 + 3957 0108 FFF7FEFF bl TIM_CCxChannelCmd +1488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + 3958 .loc 1 1489 7 + 3959 010c 7B68 ldr r3, [r7, #4] + 3960 010e 1B68 ldr r3, [r3] + 3961 0110 2E4A ldr r2, .L309 + 3962 0112 9342 cmp r3, r2 + ARM GAS /tmp/ccl4b9YO.s page 96 + + + 3963 0114 0ED0 beq .L300 + 3964 .loc 1 1489 7 is_stmt 0 discriminator 2 + 3965 0116 7B68 ldr r3, [r7, #4] + 3966 0118 1B68 ldr r3, [r3] + 3967 011a 2D4A ldr r2, .L309+4 + 3968 011c 9342 cmp r3, r2 + 3969 011e 09D0 beq .L300 + 3970 .loc 1 1489 7 discriminator 4 + 3971 0120 7B68 ldr r3, [r7, #4] + 3972 0122 1B68 ldr r3, [r3] + 3973 0124 2B4A ldr r2, .L309+8 + 3974 0126 9342 cmp r3, r2 + 3975 0128 04D0 beq .L300 + 3976 .loc 1 1489 7 discriminator 6 + 3977 012a 7B68 ldr r3, [r7, #4] + 3978 012c 1B68 ldr r3, [r3] + 3979 012e 2A4A ldr r2, .L309+12 + 3980 0130 9342 cmp r3, r2 + 3981 0132 01D1 bne .L301 + 3982 .L300: + 3983 .loc 1 1489 7 discriminator 7 + 3984 0134 0123 movs r3, #1 + 3985 .loc 1 1489 7 + 3986 0136 00E0 b .L302 + 3987 .L301: + 3988 .loc 1 1489 7 discriminator 8 + 3989 0138 0023 movs r3, #0 + 3990 .L302: + 3991 .loc 1 1489 6 is_stmt 1 discriminator 10 + 3992 013a 002B cmp r3, #0 + 3993 013c 07D0 beq .L303 +1490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the main output */ +1492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_MOE_ENABLE(htim); + 3994 .loc 1 1492 5 + 3995 013e 7B68 ldr r3, [r7, #4] + 3996 0140 1B68 ldr r3, [r3] + 3997 0142 5A6C ldr r2, [r3, #68] + 3998 0144 7B68 ldr r3, [r7, #4] + 3999 0146 1B68 ldr r3, [r3] + 4000 0148 42F40042 orr r2, r2, #32768 + 4001 014c 5A64 str r2, [r3, #68] + 4002 .L303: +1493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger +1496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 4003 .loc 1 1496 7 + 4004 014e 7B68 ldr r3, [r7, #4] + 4005 0150 1B68 ldr r3, [r3] + 4006 .loc 1 1496 6 + 4007 0152 1E4A ldr r2, .L309 + 4008 0154 9342 cmp r3, r2 + 4009 0156 13D0 beq .L304 + 4010 .loc 1 1496 7 discriminator 1 + 4011 0158 7B68 ldr r3, [r7, #4] + 4012 015a 1B68 ldr r3, [r3] + ARM GAS /tmp/ccl4b9YO.s page 97 + + + 4013 015c B3F1804F cmp r3, #1073741824 + 4014 0160 0ED0 beq .L304 + 4015 .loc 1 1496 7 is_stmt 0 discriminator 2 + 4016 0162 7B68 ldr r3, [r7, #4] + 4017 0164 1B68 ldr r3, [r3] + 4018 0166 1D4A ldr r2, .L309+16 + 4019 0168 9342 cmp r3, r2 + 4020 016a 09D0 beq .L304 + 4021 .loc 1 1496 7 discriminator 3 + 4022 016c 7B68 ldr r3, [r7, #4] + 4023 016e 1B68 ldr r3, [r3] + 4024 0170 1B4A ldr r2, .L309+20 + 4025 0172 9342 cmp r3, r2 + 4026 0174 04D0 beq .L304 + 4027 .loc 1 1496 7 discriminator 4 + 4028 0176 7B68 ldr r3, [r7, #4] + 4029 0178 1B68 ldr r3, [r3] + 4030 017a 154A ldr r2, .L309+4 + 4031 017c 9342 cmp r3, r2 + 4032 017e 15D1 bne .L305 + 4033 .L304: +1497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + 4034 .loc 1 1498 19 is_stmt 1 + 4035 0180 7B68 ldr r3, [r7, #4] + 4036 0182 1B68 ldr r3, [r3] + 4037 .loc 1 1498 29 + 4038 0184 9A68 ldr r2, [r3, #8] + 4039 .loc 1 1498 13 + 4040 0186 174B ldr r3, .L309+24 + 4041 0188 1340 ands r3, r3, r2 + 4042 018a FB60 str r3, [r7, #12] +1499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 4043 .loc 1 1499 8 + 4044 018c FB68 ldr r3, [r7, #12] + 4045 018e 062B cmp r3, #6 + 4046 0190 15D0 beq .L308 + 4047 .loc 1 1499 9 discriminator 1 + 4048 0192 FB68 ldr r3, [r7, #12] + 4049 0194 B3F5803F cmp r3, #65536 + 4050 0198 11D0 beq .L308 +1500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); + 4051 .loc 1 1501 7 + 4052 019a 7B68 ldr r3, [r7, #4] + 4053 019c 1B68 ldr r3, [r3] + 4054 019e 1A68 ldr r2, [r3] + 4055 01a0 7B68 ldr r3, [r7, #4] + 4056 01a2 1B68 ldr r3, [r3] + 4057 01a4 42F00102 orr r2, r2, #1 + 4058 01a8 1A60 str r2, [r3] +1499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 4059 .loc 1 1499 8 + 4060 01aa 08E0 b .L308 + 4061 .L305: +1502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + ARM GAS /tmp/ccl4b9YO.s page 98 + + +1504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +1505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); + 4062 .loc 1 1506 5 + 4063 01ac 7B68 ldr r3, [r7, #4] + 4064 01ae 1B68 ldr r3, [r3] + 4065 01b0 1A68 ldr r2, [r3] + 4066 01b2 7B68 ldr r3, [r7, #4] + 4067 01b4 1B68 ldr r3, [r3] + 4068 01b6 42F00102 orr r2, r2, #1 + 4069 01ba 1A60 str r2, [r3] + 4070 01bc 00E0 b .L307 + 4071 .L308: +1499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 4072 .loc 1 1499 8 + 4073 01be 00BF nop + 4074 .L307: +1507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return function status */ +1510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_OK; + 4075 .loc 1 1510 10 + 4076 01c0 0023 movs r3, #0 + 4077 .L289: +1511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 4078 .loc 1 1511 1 + 4079 01c2 1846 mov r0, r3 + 4080 01c4 1037 adds r7, r7, #16 + 4081 .cfi_def_cfa_offset 8 + 4082 01c6 BD46 mov sp, r7 + 4083 .cfi_def_cfa_register 13 + 4084 @ sp needed + 4085 01c8 80BD pop {r7, pc} + 4086 .L310: + 4087 01ca 00BF .align 2 + 4088 .L309: + 4089 01cc 002C0140 .word 1073818624 + 4090 01d0 00400140 .word 1073823744 + 4091 01d4 00440140 .word 1073824768 + 4092 01d8 00480140 .word 1073825792 + 4093 01dc 00040040 .word 1073742848 + 4094 01e0 00080040 .word 1073743872 + 4095 01e4 07000100 .word 65543 + 4096 .cfi_endproc + 4097 .LFE154: + 4099 .section .text.HAL_TIM_PWM_Stop,"ax",%progbits + 4100 .align 1 + 4101 .global HAL_TIM_PWM_Stop + 4102 .syntax unified + 4103 .thumb + 4104 .thumb_func + 4106 HAL_TIM_PWM_Stop: + 4107 .LFB155: +1512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +1514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Stops the PWM signal generation. +1515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM PWM handle + ARM GAS /tmp/ccl4b9YO.s page 99 + + +1516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param Channel TIM Channels to be disabled +1517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +1518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +1519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +1520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +1521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +1522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) +1523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) +1524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * (*) Value not defined for all devices +1525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status +1526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +1527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +1528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 4108 .loc 1 1528 1 + 4109 .cfi_startproc + 4110 @ args = 0, pretend = 0, frame = 8 + 4111 @ frame_needed = 1, uses_anonymous_args = 0 + 4112 0000 80B5 push {r7, lr} + 4113 .cfi_def_cfa_offset 8 + 4114 .cfi_offset 7, -8 + 4115 .cfi_offset 14, -4 + 4116 0002 82B0 sub sp, sp, #8 + 4117 .cfi_def_cfa_offset 16 + 4118 0004 00AF add r7, sp, #0 + 4119 .cfi_def_cfa_register 7 + 4120 0006 7860 str r0, [r7, #4] + 4121 0008 3960 str r1, [r7] +1529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +1530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); +1531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the Capture compare channel */ +1533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + 4122 .loc 1 1533 3 + 4123 000a 7B68 ldr r3, [r7, #4] + 4124 000c 1B68 ldr r3, [r3] + 4125 000e 0022 movs r2, #0 + 4126 0010 3968 ldr r1, [r7] + 4127 0012 1846 mov r0, r3 + 4128 0014 FFF7FEFF bl TIM_CCxChannelCmd +1534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + 4129 .loc 1 1535 7 + 4130 0018 7B68 ldr r3, [r7, #4] + 4131 001a 1B68 ldr r3, [r3] + 4132 001c 3B4A ldr r2, .L328 + 4133 001e 9342 cmp r3, r2 + 4134 0020 0ED0 beq .L312 + 4135 .loc 1 1535 7 is_stmt 0 discriminator 2 + 4136 0022 7B68 ldr r3, [r7, #4] + 4137 0024 1B68 ldr r3, [r3] + 4138 0026 3A4A ldr r2, .L328+4 + 4139 0028 9342 cmp r3, r2 + 4140 002a 09D0 beq .L312 + 4141 .loc 1 1535 7 discriminator 4 + 4142 002c 7B68 ldr r3, [r7, #4] + 4143 002e 1B68 ldr r3, [r3] + 4144 0030 384A ldr r2, .L328+8 + ARM GAS /tmp/ccl4b9YO.s page 100 + + + 4145 0032 9342 cmp r3, r2 + 4146 0034 04D0 beq .L312 + 4147 .loc 1 1535 7 discriminator 6 + 4148 0036 7B68 ldr r3, [r7, #4] + 4149 0038 1B68 ldr r3, [r3] + 4150 003a 374A ldr r2, .L328+12 + 4151 003c 9342 cmp r3, r2 + 4152 003e 01D1 bne .L313 + 4153 .L312: + 4154 .loc 1 1535 7 discriminator 7 + 4155 0040 0123 movs r3, #1 + 4156 .loc 1 1535 7 + 4157 0042 00E0 b .L314 + 4158 .L313: + 4159 .loc 1 1535 7 discriminator 8 + 4160 0044 0023 movs r3, #0 + 4161 .L314: + 4162 .loc 1 1535 6 is_stmt 1 discriminator 10 + 4163 0046 002B cmp r3, #0 + 4164 0048 17D0 beq .L315 +1536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the Main Output */ +1538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_MOE_DISABLE(htim); + 4165 .loc 1 1538 5 + 4166 004a 7B68 ldr r3, [r7, #4] + 4167 004c 1B68 ldr r3, [r3] + 4168 004e 1A6A ldr r2, [r3, #32] + 4169 0050 41F21113 movw r3, #4369 + 4170 0054 1340 ands r3, r3, r2 + 4171 0056 002B cmp r3, #0 + 4172 0058 0FD1 bne .L315 + 4173 .loc 1 1538 5 is_stmt 0 discriminator 1 + 4174 005a 7B68 ldr r3, [r7, #4] + 4175 005c 1B68 ldr r3, [r3] + 4176 005e 1A6A ldr r2, [r3, #32] + 4177 0060 40F24443 movw r3, #1092 + 4178 0064 1340 ands r3, r3, r2 + 4179 0066 002B cmp r3, #0 + 4180 0068 07D1 bne .L315 + 4181 .loc 1 1538 5 discriminator 2 + 4182 006a 7B68 ldr r3, [r7, #4] + 4183 006c 1B68 ldr r3, [r3] + 4184 006e 5A6C ldr r2, [r3, #68] + 4185 0070 7B68 ldr r3, [r7, #4] + 4186 0072 1B68 ldr r3, [r3] + 4187 0074 22F40042 bic r2, r2, #32768 + 4188 0078 5A64 str r2, [r3, #68] + 4189 .L315: +1539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the Peripheral */ +1542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); + 4190 .loc 1 1542 3 is_stmt 1 + 4191 007a 7B68 ldr r3, [r7, #4] + 4192 007c 1B68 ldr r3, [r3] + 4193 007e 1A6A ldr r2, [r3, #32] + 4194 0080 41F21113 movw r3, #4369 + ARM GAS /tmp/ccl4b9YO.s page 101 + + + 4195 0084 1340 ands r3, r3, r2 + 4196 0086 002B cmp r3, #0 + 4197 0088 0FD1 bne .L316 + 4198 .loc 1 1542 3 is_stmt 0 discriminator 1 + 4199 008a 7B68 ldr r3, [r7, #4] + 4200 008c 1B68 ldr r3, [r3] + 4201 008e 1A6A ldr r2, [r3, #32] + 4202 0090 40F24443 movw r3, #1092 + 4203 0094 1340 ands r3, r3, r2 + 4204 0096 002B cmp r3, #0 + 4205 0098 07D1 bne .L316 + 4206 .loc 1 1542 3 discriminator 2 + 4207 009a 7B68 ldr r3, [r7, #4] + 4208 009c 1B68 ldr r3, [r3] + 4209 009e 1A68 ldr r2, [r3] + 4210 00a0 7B68 ldr r3, [r7, #4] + 4211 00a2 1B68 ldr r3, [r3] + 4212 00a4 22F00102 bic r2, r2, #1 + 4213 00a8 1A60 str r2, [r3] + 4214 .L316: +1543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the TIM channel state */ +1545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 4215 .loc 1 1545 3 is_stmt 1 + 4216 00aa 3B68 ldr r3, [r7] + 4217 00ac 002B cmp r3, #0 + 4218 00ae 04D1 bne .L317 + 4219 .loc 1 1545 3 is_stmt 0 discriminator 1 + 4220 00b0 7B68 ldr r3, [r7, #4] + 4221 00b2 0122 movs r2, #1 + 4222 00b4 83F83E20 strb r2, [r3, #62] + 4223 00b8 23E0 b .L318 + 4224 .L317: + 4225 .loc 1 1545 3 discriminator 2 + 4226 00ba 3B68 ldr r3, [r7] + 4227 00bc 042B cmp r3, #4 + 4228 00be 04D1 bne .L319 + 4229 .loc 1 1545 3 discriminator 3 + 4230 00c0 7B68 ldr r3, [r7, #4] + 4231 00c2 0122 movs r2, #1 + 4232 00c4 83F83F20 strb r2, [r3, #63] + 4233 00c8 1BE0 b .L318 + 4234 .L319: + 4235 .loc 1 1545 3 discriminator 4 + 4236 00ca 3B68 ldr r3, [r7] + 4237 00cc 082B cmp r3, #8 + 4238 00ce 04D1 bne .L321 + 4239 .loc 1 1545 3 discriminator 6 + 4240 00d0 7B68 ldr r3, [r7, #4] + 4241 00d2 0122 movs r2, #1 + 4242 00d4 83F84020 strb r2, [r3, #64] + 4243 00d8 13E0 b .L318 + 4244 .L321: + 4245 .loc 1 1545 3 discriminator 7 + 4246 00da 3B68 ldr r3, [r7] + 4247 00dc 0C2B cmp r3, #12 + 4248 00de 04D1 bne .L323 + ARM GAS /tmp/ccl4b9YO.s page 102 + + + 4249 .loc 1 1545 3 discriminator 9 + 4250 00e0 7B68 ldr r3, [r7, #4] + 4251 00e2 0122 movs r2, #1 + 4252 00e4 83F84120 strb r2, [r3, #65] + 4253 00e8 0BE0 b .L318 + 4254 .L323: + 4255 .loc 1 1545 3 discriminator 10 + 4256 00ea 3B68 ldr r3, [r7] + 4257 00ec 102B cmp r3, #16 + 4258 00ee 04D1 bne .L325 + 4259 .loc 1 1545 3 discriminator 12 + 4260 00f0 7B68 ldr r3, [r7, #4] + 4261 00f2 0122 movs r2, #1 + 4262 00f4 83F84220 strb r2, [r3, #66] + 4263 00f8 03E0 b .L318 + 4264 .L325: + 4265 .loc 1 1545 3 discriminator 13 + 4266 00fa 7B68 ldr r3, [r7, #4] + 4267 00fc 0122 movs r2, #1 + 4268 00fe 83F84320 strb r2, [r3, #67] + 4269 .L318: +1546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return function status */ +1548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_OK; + 4270 .loc 1 1548 10 is_stmt 1 + 4271 0102 0023 movs r3, #0 +1549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 4272 .loc 1 1549 1 + 4273 0104 1846 mov r0, r3 + 4274 0106 0837 adds r7, r7, #8 + 4275 .cfi_def_cfa_offset 8 + 4276 0108 BD46 mov sp, r7 + 4277 .cfi_def_cfa_register 13 + 4278 @ sp needed + 4279 010a 80BD pop {r7, pc} + 4280 .L329: + 4281 .align 2 + 4282 .L328: + 4283 010c 002C0140 .word 1073818624 + 4284 0110 00400140 .word 1073823744 + 4285 0114 00440140 .word 1073824768 + 4286 0118 00480140 .word 1073825792 + 4287 .cfi_endproc + 4288 .LFE155: + 4290 .section .text.HAL_TIM_PWM_Start_IT,"ax",%progbits + 4291 .align 1 + 4292 .global HAL_TIM_PWM_Start_IT + 4293 .syntax unified + 4294 .thumb + 4295 .thumb_func + 4297 HAL_TIM_PWM_Start_IT: + 4298 .LFB156: +1550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +1552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Starts the PWM signal generation in interrupt mode. +1553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM PWM handle +1554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param Channel TIM Channel to be enabled + ARM GAS /tmp/ccl4b9YO.s page 103 + + +1555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +1556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +1557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +1558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +1559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +1560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status +1561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +1562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +1563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 4299 .loc 1 1563 1 + 4300 .cfi_startproc + 4301 @ args = 0, pretend = 0, frame = 16 + 4302 @ frame_needed = 1, uses_anonymous_args = 0 + 4303 0000 80B5 push {r7, lr} + 4304 .cfi_def_cfa_offset 8 + 4305 .cfi_offset 7, -8 + 4306 .cfi_offset 14, -4 + 4307 0002 84B0 sub sp, sp, #16 + 4308 .cfi_def_cfa_offset 24 + 4309 0004 00AF add r7, sp, #0 + 4310 .cfi_def_cfa_register 7 + 4311 0006 7860 str r0, [r7, #4] + 4312 0008 3960 str r1, [r7] +1564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 4313 .loc 1 1564 21 + 4314 000a 0023 movs r3, #0 + 4315 000c FB73 strb r3, [r7, #15] +1565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpsmcr; +1566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +1568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); +1569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the TIM channel state */ +1571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + 4316 .loc 1 1571 44 + 4317 000e 3B68 ldr r3, [r7] + 4318 0010 002B cmp r3, #0 + 4319 0012 09D1 bne .L331 + 4320 .loc 1 1571 7 discriminator 1 + 4321 0014 7B68 ldr r3, [r7, #4] + 4322 0016 93F83E30 ldrb r3, [r3, #62] + 4323 001a DBB2 uxtb r3, r3 + 4324 .loc 1 1571 44 discriminator 1 + 4325 001c 012B cmp r3, #1 + 4326 001e 14BF ite ne + 4327 0020 0123 movne r3, #1 + 4328 0022 0023 moveq r3, #0 + 4329 0024 DBB2 uxtb r3, r3 + 4330 0026 3CE0 b .L332 + 4331 .L331: + 4332 .loc 1 1571 44 is_stmt 0 discriminator 2 + 4333 0028 3B68 ldr r3, [r7] + 4334 002a 042B cmp r3, #4 + 4335 002c 09D1 bne .L333 + 4336 .loc 1 1571 7 is_stmt 1 discriminator 4 + 4337 002e 7B68 ldr r3, [r7, #4] + 4338 0030 93F83F30 ldrb r3, [r3, #63] + ARM GAS /tmp/ccl4b9YO.s page 104 + + + 4339 0034 DBB2 uxtb r3, r3 + 4340 .loc 1 1571 44 discriminator 4 + 4341 0036 012B cmp r3, #1 + 4342 0038 14BF ite ne + 4343 003a 0123 movne r3, #1 + 4344 003c 0023 moveq r3, #0 + 4345 003e DBB2 uxtb r3, r3 + 4346 0040 2FE0 b .L332 + 4347 .L333: + 4348 .loc 1 1571 44 is_stmt 0 discriminator 5 + 4349 0042 3B68 ldr r3, [r7] + 4350 0044 082B cmp r3, #8 + 4351 0046 09D1 bne .L335 + 4352 .loc 1 1571 7 is_stmt 1 discriminator 7 + 4353 0048 7B68 ldr r3, [r7, #4] + 4354 004a 93F84030 ldrb r3, [r3, #64] + 4355 004e DBB2 uxtb r3, r3 + 4356 .loc 1 1571 44 discriminator 7 + 4357 0050 012B cmp r3, #1 + 4358 0052 14BF ite ne + 4359 0054 0123 movne r3, #1 + 4360 0056 0023 moveq r3, #0 + 4361 0058 DBB2 uxtb r3, r3 + 4362 005a 22E0 b .L332 + 4363 .L335: + 4364 .loc 1 1571 44 is_stmt 0 discriminator 8 + 4365 005c 3B68 ldr r3, [r7] + 4366 005e 0C2B cmp r3, #12 + 4367 0060 09D1 bne .L337 + 4368 .loc 1 1571 7 is_stmt 1 discriminator 10 + 4369 0062 7B68 ldr r3, [r7, #4] + 4370 0064 93F84130 ldrb r3, [r3, #65] + 4371 0068 DBB2 uxtb r3, r3 + 4372 .loc 1 1571 44 discriminator 10 + 4373 006a 012B cmp r3, #1 + 4374 006c 14BF ite ne + 4375 006e 0123 movne r3, #1 + 4376 0070 0023 moveq r3, #0 + 4377 0072 DBB2 uxtb r3, r3 + 4378 0074 15E0 b .L332 + 4379 .L337: + 4380 .loc 1 1571 44 is_stmt 0 discriminator 11 + 4381 0076 3B68 ldr r3, [r7] + 4382 0078 102B cmp r3, #16 + 4383 007a 09D1 bne .L339 + 4384 .loc 1 1571 7 is_stmt 1 discriminator 13 + 4385 007c 7B68 ldr r3, [r7, #4] + 4386 007e 93F84230 ldrb r3, [r3, #66] + 4387 0082 DBB2 uxtb r3, r3 + 4388 .loc 1 1571 44 discriminator 13 + 4389 0084 012B cmp r3, #1 + 4390 0086 14BF ite ne + 4391 0088 0123 movne r3, #1 + 4392 008a 0023 moveq r3, #0 + 4393 008c DBB2 uxtb r3, r3 + 4394 008e 08E0 b .L332 + 4395 .L339: + ARM GAS /tmp/ccl4b9YO.s page 105 + + + 4396 .loc 1 1571 7 discriminator 14 + 4397 0090 7B68 ldr r3, [r7, #4] + 4398 0092 93F84330 ldrb r3, [r3, #67] + 4399 0096 DBB2 uxtb r3, r3 + 4400 .loc 1 1571 44 discriminator 14 + 4401 0098 012B cmp r3, #1 + 4402 009a 14BF ite ne + 4403 009c 0123 movne r3, #1 + 4404 009e 0023 moveq r3, #0 + 4405 00a0 DBB2 uxtb r3, r3 + 4406 .L332: + 4407 .loc 1 1571 6 discriminator 20 + 4408 00a2 002B cmp r3, #0 + 4409 00a4 01D0 beq .L341 +1572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 4410 .loc 1 1573 12 + 4411 00a6 0123 movs r3, #1 + 4412 00a8 D8E0 b .L342 + 4413 .L341: +1574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the TIM channel state */ +1577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + 4414 .loc 1 1577 3 + 4415 00aa 3B68 ldr r3, [r7] + 4416 00ac 002B cmp r3, #0 + 4417 00ae 04D1 bne .L343 + 4418 .loc 1 1577 3 is_stmt 0 discriminator 1 + 4419 00b0 7B68 ldr r3, [r7, #4] + 4420 00b2 0222 movs r2, #2 + 4421 00b4 83F83E20 strb r2, [r3, #62] + 4422 00b8 23E0 b .L344 + 4423 .L343: + 4424 .loc 1 1577 3 discriminator 2 + 4425 00ba 3B68 ldr r3, [r7] + 4426 00bc 042B cmp r3, #4 + 4427 00be 04D1 bne .L345 + 4428 .loc 1 1577 3 discriminator 3 + 4429 00c0 7B68 ldr r3, [r7, #4] + 4430 00c2 0222 movs r2, #2 + 4431 00c4 83F83F20 strb r2, [r3, #63] + 4432 00c8 1BE0 b .L344 + 4433 .L345: + 4434 .loc 1 1577 3 discriminator 4 + 4435 00ca 3B68 ldr r3, [r7] + 4436 00cc 082B cmp r3, #8 + 4437 00ce 04D1 bne .L347 + 4438 .loc 1 1577 3 discriminator 6 + 4439 00d0 7B68 ldr r3, [r7, #4] + 4440 00d2 0222 movs r2, #2 + 4441 00d4 83F84020 strb r2, [r3, #64] + 4442 00d8 13E0 b .L344 + 4443 .L347: + 4444 .loc 1 1577 3 discriminator 7 + 4445 00da 3B68 ldr r3, [r7] + 4446 00dc 0C2B cmp r3, #12 + ARM GAS /tmp/ccl4b9YO.s page 106 + + + 4447 00de 04D1 bne .L349 + 4448 .loc 1 1577 3 discriminator 9 + 4449 00e0 7B68 ldr r3, [r7, #4] + 4450 00e2 0222 movs r2, #2 + 4451 00e4 83F84120 strb r2, [r3, #65] + 4452 00e8 0BE0 b .L344 + 4453 .L349: + 4454 .loc 1 1577 3 discriminator 10 + 4455 00ea 3B68 ldr r3, [r7] + 4456 00ec 102B cmp r3, #16 + 4457 00ee 04D1 bne .L351 + 4458 .loc 1 1577 3 discriminator 12 + 4459 00f0 7B68 ldr r3, [r7, #4] + 4460 00f2 0222 movs r2, #2 + 4461 00f4 83F84220 strb r2, [r3, #66] + 4462 00f8 03E0 b .L344 + 4463 .L351: + 4464 .loc 1 1577 3 discriminator 13 + 4465 00fa 7B68 ldr r3, [r7, #4] + 4466 00fc 0222 movs r2, #2 + 4467 00fe 83F84320 strb r2, [r3, #67] + 4468 .L344: +1578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** switch (Channel) + 4469 .loc 1 1579 3 is_stmt 1 + 4470 0102 3B68 ldr r3, [r7] + 4471 0104 0C2B cmp r3, #12 + 4472 0106 41D8 bhi .L353 + 4473 0108 01A2 adr r2, .L355 + 4474 010a 52F823F0 ldr pc, [r2, r3, lsl #2] + 4475 010e 00BF .p2align 2 + 4476 .L355: + 4477 0110 45010000 .word .L358+1 + 4478 0114 8D010000 .word .L353+1 + 4479 0118 8D010000 .word .L353+1 + 4480 011c 8D010000 .word .L353+1 + 4481 0120 57010000 .word .L357+1 + 4482 0124 8D010000 .word .L353+1 + 4483 0128 8D010000 .word .L353+1 + 4484 012c 8D010000 .word .L353+1 + 4485 0130 69010000 .word .L356+1 + 4486 0134 8D010000 .word .L353+1 + 4487 0138 8D010000 .word .L353+1 + 4488 013c 8D010000 .word .L353+1 + 4489 0140 7B010000 .word .L354+1 + 4490 .p2align 1 + 4491 .L358: +1580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_1: +1582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the TIM Capture/Compare 1 interrupt */ +1584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + 4492 .loc 1 1584 7 + 4493 0144 7B68 ldr r3, [r7, #4] + 4494 0146 1B68 ldr r3, [r3] + 4495 0148 DA68 ldr r2, [r3, #12] + 4496 014a 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/ccl4b9YO.s page 107 + + + 4497 014c 1B68 ldr r3, [r3] + 4498 014e 42F00202 orr r2, r2, #2 + 4499 0152 DA60 str r2, [r3, #12] +1585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 4500 .loc 1 1585 7 + 4501 0154 1DE0 b .L359 + 4502 .L357: +1586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_2: +1589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the TIM Capture/Compare 2 interrupt */ +1591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + 4503 .loc 1 1591 7 + 4504 0156 7B68 ldr r3, [r7, #4] + 4505 0158 1B68 ldr r3, [r3] + 4506 015a DA68 ldr r2, [r3, #12] + 4507 015c 7B68 ldr r3, [r7, #4] + 4508 015e 1B68 ldr r3, [r3] + 4509 0160 42F00402 orr r2, r2, #4 + 4510 0164 DA60 str r2, [r3, #12] +1592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 4511 .loc 1 1592 7 + 4512 0166 14E0 b .L359 + 4513 .L356: +1593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_3: +1596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the TIM Capture/Compare 3 interrupt */ +1598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + 4514 .loc 1 1598 7 + 4515 0168 7B68 ldr r3, [r7, #4] + 4516 016a 1B68 ldr r3, [r3] + 4517 016c DA68 ldr r2, [r3, #12] + 4518 016e 7B68 ldr r3, [r7, #4] + 4519 0170 1B68 ldr r3, [r3] + 4520 0172 42F00802 orr r2, r2, #8 + 4521 0176 DA60 str r2, [r3, #12] +1599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 4522 .loc 1 1599 7 + 4523 0178 0BE0 b .L359 + 4524 .L354: +1600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1602:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_4: +1603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the TIM Capture/Compare 4 interrupt */ +1605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + 4525 .loc 1 1605 7 + 4526 017a 7B68 ldr r3, [r7, #4] + 4527 017c 1B68 ldr r3, [r3] + 4528 017e DA68 ldr r2, [r3, #12] + 4529 0180 7B68 ldr r3, [r7, #4] + 4530 0182 1B68 ldr r3, [r3] + 4531 0184 42F01002 orr r2, r2, #16 + 4532 0188 DA60 str r2, [r3, #12] + ARM GAS /tmp/ccl4b9YO.s page 108 + + +1606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 4533 .loc 1 1606 7 + 4534 018a 02E0 b .L359 + 4535 .L353: +1607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** default: +1610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** status = HAL_ERROR; + 4536 .loc 1 1610 14 + 4537 018c 0123 movs r3, #1 + 4538 018e FB73 strb r3, [r7, #15] +1611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 4539 .loc 1 1611 7 + 4540 0190 00BF nop + 4541 .L359: +1612:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (status == HAL_OK) + 4542 .loc 1 1614 6 + 4543 0192 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 4544 0194 002B cmp r3, #0 + 4545 0196 60D1 bne .L360 +1615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the Capture compare channel */ +1617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + 4546 .loc 1 1617 5 + 4547 0198 7B68 ldr r3, [r7, #4] + 4548 019a 1B68 ldr r3, [r3] + 4549 019c 0122 movs r2, #1 + 4550 019e 3968 ldr r1, [r7] + 4551 01a0 1846 mov r0, r3 + 4552 01a2 FFF7FEFF bl TIM_CCxChannelCmd +1618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + 4553 .loc 1 1619 9 + 4554 01a6 7B68 ldr r3, [r7, #4] + 4555 01a8 1B68 ldr r3, [r3] + 4556 01aa 2E4A ldr r2, .L369 + 4557 01ac 9342 cmp r3, r2 + 4558 01ae 0ED0 beq .L361 + 4559 .loc 1 1619 9 is_stmt 0 discriminator 2 + 4560 01b0 7B68 ldr r3, [r7, #4] + 4561 01b2 1B68 ldr r3, [r3] + 4562 01b4 2C4A ldr r2, .L369+4 + 4563 01b6 9342 cmp r3, r2 + 4564 01b8 09D0 beq .L361 + 4565 .loc 1 1619 9 discriminator 4 + 4566 01ba 7B68 ldr r3, [r7, #4] + 4567 01bc 1B68 ldr r3, [r3] + 4568 01be 2B4A ldr r2, .L369+8 + 4569 01c0 9342 cmp r3, r2 + 4570 01c2 04D0 beq .L361 + 4571 .loc 1 1619 9 discriminator 6 + 4572 01c4 7B68 ldr r3, [r7, #4] + 4573 01c6 1B68 ldr r3, [r3] + 4574 01c8 294A ldr r2, .L369+12 + 4575 01ca 9342 cmp r3, r2 + ARM GAS /tmp/ccl4b9YO.s page 109 + + + 4576 01cc 01D1 bne .L362 + 4577 .L361: + 4578 .loc 1 1619 9 discriminator 7 + 4579 01ce 0123 movs r3, #1 + 4580 .loc 1 1619 9 + 4581 01d0 00E0 b .L363 + 4582 .L362: + 4583 .loc 1 1619 9 discriminator 8 + 4584 01d2 0023 movs r3, #0 + 4585 .L363: + 4586 .loc 1 1619 8 is_stmt 1 discriminator 10 + 4587 01d4 002B cmp r3, #0 + 4588 01d6 07D0 beq .L364 +1620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the main output */ +1622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_MOE_ENABLE(htim); + 4589 .loc 1 1622 7 + 4590 01d8 7B68 ldr r3, [r7, #4] + 4591 01da 1B68 ldr r3, [r3] + 4592 01dc 5A6C ldr r2, [r3, #68] + 4593 01de 7B68 ldr r3, [r7, #4] + 4594 01e0 1B68 ldr r3, [r3] + 4595 01e2 42F40042 orr r2, r2, #32768 + 4596 01e6 5A64 str r2, [r3, #68] + 4597 .L364: +1623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigge +1626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 4598 .loc 1 1626 9 + 4599 01e8 7B68 ldr r3, [r7, #4] + 4600 01ea 1B68 ldr r3, [r3] + 4601 .loc 1 1626 8 + 4602 01ec 1D4A ldr r2, .L369 + 4603 01ee 9342 cmp r3, r2 + 4604 01f0 13D0 beq .L365 + 4605 .loc 1 1626 9 discriminator 1 + 4606 01f2 7B68 ldr r3, [r7, #4] + 4607 01f4 1B68 ldr r3, [r3] + 4608 01f6 B3F1804F cmp r3, #1073741824 + 4609 01fa 0ED0 beq .L365 + 4610 .loc 1 1626 9 is_stmt 0 discriminator 2 + 4611 01fc 7B68 ldr r3, [r7, #4] + 4612 01fe 1B68 ldr r3, [r3] + 4613 0200 1C4A ldr r2, .L369+16 + 4614 0202 9342 cmp r3, r2 + 4615 0204 09D0 beq .L365 + 4616 .loc 1 1626 9 discriminator 3 + 4617 0206 7B68 ldr r3, [r7, #4] + 4618 0208 1B68 ldr r3, [r3] + 4619 020a 1B4A ldr r2, .L369+20 + 4620 020c 9342 cmp r3, r2 + 4621 020e 04D0 beq .L365 + 4622 .loc 1 1626 9 discriminator 4 + 4623 0210 7B68 ldr r3, [r7, #4] + 4624 0212 1B68 ldr r3, [r3] + 4625 0214 144A ldr r2, .L369+4 + ARM GAS /tmp/ccl4b9YO.s page 110 + + + 4626 0216 9342 cmp r3, r2 + 4627 0218 15D1 bne .L366 + 4628 .L365: +1627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + 4629 .loc 1 1628 21 is_stmt 1 + 4630 021a 7B68 ldr r3, [r7, #4] + 4631 021c 1B68 ldr r3, [r3] + 4632 .loc 1 1628 31 + 4633 021e 9A68 ldr r2, [r3, #8] + 4634 .loc 1 1628 15 + 4635 0220 164B ldr r3, .L369+24 + 4636 0222 1340 ands r3, r3, r2 + 4637 0224 BB60 str r3, [r7, #8] +1629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 4638 .loc 1 1629 10 + 4639 0226 BB68 ldr r3, [r7, #8] + 4640 0228 062B cmp r3, #6 + 4641 022a 15D0 beq .L368 + 4642 .loc 1 1629 11 discriminator 1 + 4643 022c BB68 ldr r3, [r7, #8] + 4644 022e B3F5803F cmp r3, #65536 + 4645 0232 11D0 beq .L368 +1630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); + 4646 .loc 1 1631 9 + 4647 0234 7B68 ldr r3, [r7, #4] + 4648 0236 1B68 ldr r3, [r3] + 4649 0238 1A68 ldr r2, [r3] + 4650 023a 7B68 ldr r3, [r7, #4] + 4651 023c 1B68 ldr r3, [r3] + 4652 023e 42F00102 orr r2, r2, #1 + 4653 0242 1A60 str r2, [r3] +1629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 4654 .loc 1 1629 10 + 4655 0244 08E0 b .L368 + 4656 .L366: +1632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +1635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); + 4657 .loc 1 1636 7 + 4658 0246 7B68 ldr r3, [r7, #4] + 4659 0248 1B68 ldr r3, [r3] + 4660 024a 1A68 ldr r2, [r3] + 4661 024c 7B68 ldr r3, [r7, #4] + 4662 024e 1B68 ldr r3, [r3] + 4663 0250 42F00102 orr r2, r2, #1 + 4664 0254 1A60 str r2, [r3] + 4665 0256 00E0 b .L360 + 4666 .L368: +1629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 4667 .loc 1 1629 10 + 4668 0258 00BF nop + 4669 .L360: +1637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + ARM GAS /tmp/ccl4b9YO.s page 111 + + +1638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return function status */ +1641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return status; + 4670 .loc 1 1641 10 + 4671 025a FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 4672 .L342: +1642:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 4673 .loc 1 1642 1 + 4674 025c 1846 mov r0, r3 + 4675 025e 1037 adds r7, r7, #16 + 4676 .cfi_def_cfa_offset 8 + 4677 0260 BD46 mov sp, r7 + 4678 .cfi_def_cfa_register 13 + 4679 @ sp needed + 4680 0262 80BD pop {r7, pc} + 4681 .L370: + 4682 .align 2 + 4683 .L369: + 4684 0264 002C0140 .word 1073818624 + 4685 0268 00400140 .word 1073823744 + 4686 026c 00440140 .word 1073824768 + 4687 0270 00480140 .word 1073825792 + 4688 0274 00040040 .word 1073742848 + 4689 0278 00080040 .word 1073743872 + 4690 027c 07000100 .word 65543 + 4691 .cfi_endproc + 4692 .LFE156: + 4694 .section .text.HAL_TIM_PWM_Stop_IT,"ax",%progbits + 4695 .align 1 + 4696 .global HAL_TIM_PWM_Stop_IT + 4697 .syntax unified + 4698 .thumb + 4699 .thumb_func + 4701 HAL_TIM_PWM_Stop_IT: + 4702 .LFB157: +1643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +1645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Stops the PWM signal generation in interrupt mode. +1646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM PWM handle +1647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param Channel TIM Channels to be disabled +1648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +1649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +1650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +1651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +1652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +1653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status +1654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +1655:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +1656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 4703 .loc 1 1656 1 + 4704 .cfi_startproc + 4705 @ args = 0, pretend = 0, frame = 16 + 4706 @ frame_needed = 1, uses_anonymous_args = 0 + 4707 0000 80B5 push {r7, lr} + 4708 .cfi_def_cfa_offset 8 + 4709 .cfi_offset 7, -8 + ARM GAS /tmp/ccl4b9YO.s page 112 + + + 4710 .cfi_offset 14, -4 + 4711 0002 84B0 sub sp, sp, #16 + 4712 .cfi_def_cfa_offset 24 + 4713 0004 00AF add r7, sp, #0 + 4714 .cfi_def_cfa_register 7 + 4715 0006 7860 str r0, [r7, #4] + 4716 0008 3960 str r1, [r7] +1657:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 4717 .loc 1 1657 21 + 4718 000a 0023 movs r3, #0 + 4719 000c FB73 strb r3, [r7, #15] +1658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1659:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +1660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); +1661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** switch (Channel) + 4720 .loc 1 1662 3 + 4721 000e 3B68 ldr r3, [r7] + 4722 0010 0C2B cmp r3, #12 + 4723 0012 41D8 bhi .L372 + 4724 0014 01A2 adr r2, .L374 + 4725 0016 52F823F0 ldr pc, [r2, r3, lsl #2] + 4726 001a 00BF .p2align 2 + 4727 .L374: + 4728 001c 51000000 .word .L377+1 + 4729 0020 99000000 .word .L372+1 + 4730 0024 99000000 .word .L372+1 + 4731 0028 99000000 .word .L372+1 + 4732 002c 63000000 .word .L376+1 + 4733 0030 99000000 .word .L372+1 + 4734 0034 99000000 .word .L372+1 + 4735 0038 99000000 .word .L372+1 + 4736 003c 75000000 .word .L375+1 + 4737 0040 99000000 .word .L372+1 + 4738 0044 99000000 .word .L372+1 + 4739 0048 99000000 .word .L372+1 + 4740 004c 87000000 .word .L373+1 + 4741 .p2align 1 + 4742 .L377: +1663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1664:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_1: +1665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the TIM Capture/Compare 1 interrupt */ +1667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + 4743 .loc 1 1667 7 + 4744 0050 7B68 ldr r3, [r7, #4] + 4745 0052 1B68 ldr r3, [r3] + 4746 0054 DA68 ldr r2, [r3, #12] + 4747 0056 7B68 ldr r3, [r7, #4] + 4748 0058 1B68 ldr r3, [r3] + 4749 005a 22F00202 bic r2, r2, #2 + 4750 005e DA60 str r2, [r3, #12] +1668:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 4751 .loc 1 1668 7 + 4752 0060 1DE0 b .L378 + 4753 .L376: +1669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + ARM GAS /tmp/ccl4b9YO.s page 113 + + +1670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_2: +1672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the TIM Capture/Compare 2 interrupt */ +1674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + 4754 .loc 1 1674 7 + 4755 0062 7B68 ldr r3, [r7, #4] + 4756 0064 1B68 ldr r3, [r3] + 4757 0066 DA68 ldr r2, [r3, #12] + 4758 0068 7B68 ldr r3, [r7, #4] + 4759 006a 1B68 ldr r3, [r3] + 4760 006c 22F00402 bic r2, r2, #4 + 4761 0070 DA60 str r2, [r3, #12] +1675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 4762 .loc 1 1675 7 + 4763 0072 14E0 b .L378 + 4764 .L375: +1676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_3: +1679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the TIM Capture/Compare 3 interrupt */ +1681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + 4765 .loc 1 1681 7 + 4766 0074 7B68 ldr r3, [r7, #4] + 4767 0076 1B68 ldr r3, [r3] + 4768 0078 DA68 ldr r2, [r3, #12] + 4769 007a 7B68 ldr r3, [r7, #4] + 4770 007c 1B68 ldr r3, [r3] + 4771 007e 22F00802 bic r2, r2, #8 + 4772 0082 DA60 str r2, [r3, #12] +1682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 4773 .loc 1 1682 7 + 4774 0084 0BE0 b .L378 + 4775 .L373: +1683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_4: +1686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the TIM Capture/Compare 4 interrupt */ +1688:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + 4776 .loc 1 1688 7 + 4777 0086 7B68 ldr r3, [r7, #4] + 4778 0088 1B68 ldr r3, [r3] + 4779 008a DA68 ldr r2, [r3, #12] + 4780 008c 7B68 ldr r3, [r7, #4] + 4781 008e 1B68 ldr r3, [r3] + 4782 0090 22F01002 bic r2, r2, #16 + 4783 0094 DA60 str r2, [r3, #12] +1689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 4784 .loc 1 1689 7 + 4785 0096 02E0 b .L378 + 4786 .L372: +1690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** default: +1693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** status = HAL_ERROR; + ARM GAS /tmp/ccl4b9YO.s page 114 + + + 4787 .loc 1 1693 14 + 4788 0098 0123 movs r3, #1 + 4789 009a FB73 strb r3, [r7, #15] +1694:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 4790 .loc 1 1694 7 + 4791 009c 00BF nop + 4792 .L378: +1695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (status == HAL_OK) + 4793 .loc 1 1697 6 + 4794 009e FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 4795 00a0 002B cmp r3, #0 + 4796 00a2 7BD1 bne .L379 +1698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the Capture compare channel */ +1700:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + 4797 .loc 1 1700 5 + 4798 00a4 7B68 ldr r3, [r7, #4] + 4799 00a6 1B68 ldr r3, [r3] + 4800 00a8 0022 movs r2, #0 + 4801 00aa 3968 ldr r1, [r7] + 4802 00ac 1846 mov r0, r3 + 4803 00ae FFF7FEFF bl TIM_CCxChannelCmd +1701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + 4804 .loc 1 1702 9 + 4805 00b2 7B68 ldr r3, [r7, #4] + 4806 00b4 1B68 ldr r3, [r3] + 4807 00b6 3C4A ldr r2, .L395 + 4808 00b8 9342 cmp r3, r2 + 4809 00ba 0ED0 beq .L380 + 4810 .loc 1 1702 9 is_stmt 0 discriminator 2 + 4811 00bc 7B68 ldr r3, [r7, #4] + 4812 00be 1B68 ldr r3, [r3] + 4813 00c0 3A4A ldr r2, .L395+4 + 4814 00c2 9342 cmp r3, r2 + 4815 00c4 09D0 beq .L380 + 4816 .loc 1 1702 9 discriminator 4 + 4817 00c6 7B68 ldr r3, [r7, #4] + 4818 00c8 1B68 ldr r3, [r3] + 4819 00ca 394A ldr r2, .L395+8 + 4820 00cc 9342 cmp r3, r2 + 4821 00ce 04D0 beq .L380 + 4822 .loc 1 1702 9 discriminator 6 + 4823 00d0 7B68 ldr r3, [r7, #4] + 4824 00d2 1B68 ldr r3, [r3] + 4825 00d4 374A ldr r2, .L395+12 + 4826 00d6 9342 cmp r3, r2 + 4827 00d8 01D1 bne .L381 + 4828 .L380: + 4829 .loc 1 1702 9 discriminator 7 + 4830 00da 0123 movs r3, #1 + 4831 .loc 1 1702 9 + 4832 00dc 00E0 b .L382 + 4833 .L381: + 4834 .loc 1 1702 9 discriminator 8 + ARM GAS /tmp/ccl4b9YO.s page 115 + + + 4835 00de 0023 movs r3, #0 + 4836 .L382: + 4837 .loc 1 1702 8 is_stmt 1 discriminator 10 + 4838 00e0 002B cmp r3, #0 + 4839 00e2 17D0 beq .L383 +1703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1704:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the Main Output */ +1705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_MOE_DISABLE(htim); + 4840 .loc 1 1705 7 + 4841 00e4 7B68 ldr r3, [r7, #4] + 4842 00e6 1B68 ldr r3, [r3] + 4843 00e8 1A6A ldr r2, [r3, #32] + 4844 00ea 41F21113 movw r3, #4369 + 4845 00ee 1340 ands r3, r3, r2 + 4846 00f0 002B cmp r3, #0 + 4847 00f2 0FD1 bne .L383 + 4848 .loc 1 1705 7 is_stmt 0 discriminator 1 + 4849 00f4 7B68 ldr r3, [r7, #4] + 4850 00f6 1B68 ldr r3, [r3] + 4851 00f8 1A6A ldr r2, [r3, #32] + 4852 00fa 40F24443 movw r3, #1092 + 4853 00fe 1340 ands r3, r3, r2 + 4854 0100 002B cmp r3, #0 + 4855 0102 07D1 bne .L383 + 4856 .loc 1 1705 7 discriminator 2 + 4857 0104 7B68 ldr r3, [r7, #4] + 4858 0106 1B68 ldr r3, [r3] + 4859 0108 5A6C ldr r2, [r3, #68] + 4860 010a 7B68 ldr r3, [r7, #4] + 4861 010c 1B68 ldr r3, [r3] + 4862 010e 22F40042 bic r2, r2, #32768 + 4863 0112 5A64 str r2, [r3, #68] + 4864 .L383: +1706:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1707:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1708:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the Peripheral */ +1709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); + 4865 .loc 1 1709 5 is_stmt 1 + 4866 0114 7B68 ldr r3, [r7, #4] + 4867 0116 1B68 ldr r3, [r3] + 4868 0118 1A6A ldr r2, [r3, #32] + 4869 011a 41F21113 movw r3, #4369 + 4870 011e 1340 ands r3, r3, r2 + 4871 0120 002B cmp r3, #0 + 4872 0122 0FD1 bne .L384 + 4873 .loc 1 1709 5 is_stmt 0 discriminator 1 + 4874 0124 7B68 ldr r3, [r7, #4] + 4875 0126 1B68 ldr r3, [r3] + 4876 0128 1A6A ldr r2, [r3, #32] + 4877 012a 40F24443 movw r3, #1092 + 4878 012e 1340 ands r3, r3, r2 + 4879 0130 002B cmp r3, #0 + 4880 0132 07D1 bne .L384 + 4881 .loc 1 1709 5 discriminator 2 + 4882 0134 7B68 ldr r3, [r7, #4] + 4883 0136 1B68 ldr r3, [r3] + 4884 0138 1A68 ldr r2, [r3] + ARM GAS /tmp/ccl4b9YO.s page 116 + + + 4885 013a 7B68 ldr r3, [r7, #4] + 4886 013c 1B68 ldr r3, [r3] + 4887 013e 22F00102 bic r2, r2, #1 + 4888 0142 1A60 str r2, [r3] + 4889 .L384: +1710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the TIM channel state */ +1712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 4890 .loc 1 1712 5 is_stmt 1 + 4891 0144 3B68 ldr r3, [r7] + 4892 0146 002B cmp r3, #0 + 4893 0148 04D1 bne .L385 + 4894 .loc 1 1712 5 is_stmt 0 discriminator 1 + 4895 014a 7B68 ldr r3, [r7, #4] + 4896 014c 0122 movs r2, #1 + 4897 014e 83F83E20 strb r2, [r3, #62] + 4898 0152 23E0 b .L379 + 4899 .L385: + 4900 .loc 1 1712 5 discriminator 2 + 4901 0154 3B68 ldr r3, [r7] + 4902 0156 042B cmp r3, #4 + 4903 0158 04D1 bne .L386 + 4904 .loc 1 1712 5 discriminator 3 + 4905 015a 7B68 ldr r3, [r7, #4] + 4906 015c 0122 movs r2, #1 + 4907 015e 83F83F20 strb r2, [r3, #63] + 4908 0162 1BE0 b .L379 + 4909 .L386: + 4910 .loc 1 1712 5 discriminator 4 + 4911 0164 3B68 ldr r3, [r7] + 4912 0166 082B cmp r3, #8 + 4913 0168 04D1 bne .L388 + 4914 .loc 1 1712 5 discriminator 6 + 4915 016a 7B68 ldr r3, [r7, #4] + 4916 016c 0122 movs r2, #1 + 4917 016e 83F84020 strb r2, [r3, #64] + 4918 0172 13E0 b .L379 + 4919 .L388: + 4920 .loc 1 1712 5 discriminator 7 + 4921 0174 3B68 ldr r3, [r7] + 4922 0176 0C2B cmp r3, #12 + 4923 0178 04D1 bne .L390 + 4924 .loc 1 1712 5 discriminator 9 + 4925 017a 7B68 ldr r3, [r7, #4] + 4926 017c 0122 movs r2, #1 + 4927 017e 83F84120 strb r2, [r3, #65] + 4928 0182 0BE0 b .L379 + 4929 .L390: + 4930 .loc 1 1712 5 discriminator 10 + 4931 0184 3B68 ldr r3, [r7] + 4932 0186 102B cmp r3, #16 + 4933 0188 04D1 bne .L392 + 4934 .loc 1 1712 5 discriminator 12 + 4935 018a 7B68 ldr r3, [r7, #4] + 4936 018c 0122 movs r2, #1 + 4937 018e 83F84220 strb r2, [r3, #66] + 4938 0192 03E0 b .L379 + ARM GAS /tmp/ccl4b9YO.s page 117 + + + 4939 .L392: + 4940 .loc 1 1712 5 discriminator 13 + 4941 0194 7B68 ldr r3, [r7, #4] + 4942 0196 0122 movs r2, #1 + 4943 0198 83F84320 strb r2, [r3, #67] + 4944 .L379: +1713:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return function status */ +1716:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return status; + 4945 .loc 1 1716 10 is_stmt 1 + 4946 019c FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 +1717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 4947 .loc 1 1717 1 + 4948 019e 1846 mov r0, r3 + 4949 01a0 1037 adds r7, r7, #16 + 4950 .cfi_def_cfa_offset 8 + 4951 01a2 BD46 mov sp, r7 + 4952 .cfi_def_cfa_register 13 + 4953 @ sp needed + 4954 01a4 80BD pop {r7, pc} + 4955 .L396: + 4956 01a6 00BF .align 2 + 4957 .L395: + 4958 01a8 002C0140 .word 1073818624 + 4959 01ac 00400140 .word 1073823744 + 4960 01b0 00440140 .word 1073824768 + 4961 01b4 00480140 .word 1073825792 + 4962 .cfi_endproc + 4963 .LFE157: + 4965 .section .text.HAL_TIM_PWM_Start_DMA,"ax",%progbits + 4966 .align 1 + 4967 .global HAL_TIM_PWM_Start_DMA + 4968 .syntax unified + 4969 .thumb + 4970 .thumb_func + 4972 HAL_TIM_PWM_Start_DMA: + 4973 .LFB158: +1718:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +1720:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Starts the TIM PWM signal generation in DMA mode. +1721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM PWM handle +1722:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param Channel TIM Channels to be enabled +1723:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +1724:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +1725:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +1726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +1727:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +1728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param pData The source Buffer address. +1729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param Length The length of data to be transferred from memory to TIM peripheral +1730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status +1731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +1732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t * +1733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint16_t Length) +1734:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 4974 .loc 1 1734 1 + 4975 .cfi_startproc + ARM GAS /tmp/ccl4b9YO.s page 118 + + + 4976 @ args = 0, pretend = 0, frame = 24 + 4977 @ frame_needed = 1, uses_anonymous_args = 0 + 4978 0000 80B5 push {r7, lr} + 4979 .cfi_def_cfa_offset 8 + 4980 .cfi_offset 7, -8 + 4981 .cfi_offset 14, -4 + 4982 0002 86B0 sub sp, sp, #24 + 4983 .cfi_def_cfa_offset 32 + 4984 0004 00AF add r7, sp, #0 + 4985 .cfi_def_cfa_register 7 + 4986 0006 F860 str r0, [r7, #12] + 4987 0008 B960 str r1, [r7, #8] + 4988 000a 7A60 str r2, [r7, #4] + 4989 000c 7B80 strh r3, [r7, #2] @ movhi +1735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 4990 .loc 1 1735 21 + 4991 000e 0023 movs r3, #0 + 4992 0010 FB75 strb r3, [r7, #23] +1736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpsmcr; +1737:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +1739:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); +1740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the TIM channel state */ +1742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + 4993 .loc 1 1742 44 + 4994 0012 BB68 ldr r3, [r7, #8] + 4995 0014 002B cmp r3, #0 + 4996 0016 09D1 bne .L398 + 4997 .loc 1 1742 7 discriminator 1 + 4998 0018 FB68 ldr r3, [r7, #12] + 4999 001a 93F83E30 ldrb r3, [r3, #62] + 5000 001e DBB2 uxtb r3, r3 + 5001 .loc 1 1742 44 discriminator 1 + 5002 0020 022B cmp r3, #2 + 5003 0022 0CBF ite eq + 5004 0024 0123 moveq r3, #1 + 5005 0026 0023 movne r3, #0 + 5006 0028 DBB2 uxtb r3, r3 + 5007 002a 3CE0 b .L399 + 5008 .L398: + 5009 .loc 1 1742 44 is_stmt 0 discriminator 2 + 5010 002c BB68 ldr r3, [r7, #8] + 5011 002e 042B cmp r3, #4 + 5012 0030 09D1 bne .L400 + 5013 .loc 1 1742 7 is_stmt 1 discriminator 4 + 5014 0032 FB68 ldr r3, [r7, #12] + 5015 0034 93F83F30 ldrb r3, [r3, #63] + 5016 0038 DBB2 uxtb r3, r3 + 5017 .loc 1 1742 44 discriminator 4 + 5018 003a 022B cmp r3, #2 + 5019 003c 0CBF ite eq + 5020 003e 0123 moveq r3, #1 + 5021 0040 0023 movne r3, #0 + 5022 0042 DBB2 uxtb r3, r3 + 5023 0044 2FE0 b .L399 + 5024 .L400: + ARM GAS /tmp/ccl4b9YO.s page 119 + + + 5025 .loc 1 1742 44 is_stmt 0 discriminator 5 + 5026 0046 BB68 ldr r3, [r7, #8] + 5027 0048 082B cmp r3, #8 + 5028 004a 09D1 bne .L402 + 5029 .loc 1 1742 7 is_stmt 1 discriminator 7 + 5030 004c FB68 ldr r3, [r7, #12] + 5031 004e 93F84030 ldrb r3, [r3, #64] + 5032 0052 DBB2 uxtb r3, r3 + 5033 .loc 1 1742 44 discriminator 7 + 5034 0054 022B cmp r3, #2 + 5035 0056 0CBF ite eq + 5036 0058 0123 moveq r3, #1 + 5037 005a 0023 movne r3, #0 + 5038 005c DBB2 uxtb r3, r3 + 5039 005e 22E0 b .L399 + 5040 .L402: + 5041 .loc 1 1742 44 is_stmt 0 discriminator 8 + 5042 0060 BB68 ldr r3, [r7, #8] + 5043 0062 0C2B cmp r3, #12 + 5044 0064 09D1 bne .L404 + 5045 .loc 1 1742 7 is_stmt 1 discriminator 10 + 5046 0066 FB68 ldr r3, [r7, #12] + 5047 0068 93F84130 ldrb r3, [r3, #65] + 5048 006c DBB2 uxtb r3, r3 + 5049 .loc 1 1742 44 discriminator 10 + 5050 006e 022B cmp r3, #2 + 5051 0070 0CBF ite eq + 5052 0072 0123 moveq r3, #1 + 5053 0074 0023 movne r3, #0 + 5054 0076 DBB2 uxtb r3, r3 + 5055 0078 15E0 b .L399 + 5056 .L404: + 5057 .loc 1 1742 44 is_stmt 0 discriminator 11 + 5058 007a BB68 ldr r3, [r7, #8] + 5059 007c 102B cmp r3, #16 + 5060 007e 09D1 bne .L406 + 5061 .loc 1 1742 7 is_stmt 1 discriminator 13 + 5062 0080 FB68 ldr r3, [r7, #12] + 5063 0082 93F84230 ldrb r3, [r3, #66] + 5064 0086 DBB2 uxtb r3, r3 + 5065 .loc 1 1742 44 discriminator 13 + 5066 0088 022B cmp r3, #2 + 5067 008a 0CBF ite eq + 5068 008c 0123 moveq r3, #1 + 5069 008e 0023 movne r3, #0 + 5070 0090 DBB2 uxtb r3, r3 + 5071 0092 08E0 b .L399 + 5072 .L406: + 5073 .loc 1 1742 7 discriminator 14 + 5074 0094 FB68 ldr r3, [r7, #12] + 5075 0096 93F84330 ldrb r3, [r3, #67] + 5076 009a DBB2 uxtb r3, r3 + 5077 .loc 1 1742 44 discriminator 14 + 5078 009c 022B cmp r3, #2 + 5079 009e 0CBF ite eq + 5080 00a0 0123 moveq r3, #1 + 5081 00a2 0023 movne r3, #0 + ARM GAS /tmp/ccl4b9YO.s page 120 + + + 5082 00a4 DBB2 uxtb r3, r3 + 5083 .L399: + 5084 .loc 1 1742 6 discriminator 20 + 5085 00a6 002B cmp r3, #0 + 5086 00a8 01D0 beq .L408 +1743:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_BUSY; + 5087 .loc 1 1744 12 + 5088 00aa 0223 movs r3, #2 + 5089 00ac 9CE1 b .L409 + 5090 .L408: +1745:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1746:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + 5091 .loc 1 1746 49 + 5092 00ae BB68 ldr r3, [r7, #8] + 5093 00b0 002B cmp r3, #0 + 5094 00b2 09D1 bne .L410 + 5095 .loc 1 1746 12 discriminator 1 + 5096 00b4 FB68 ldr r3, [r7, #12] + 5097 00b6 93F83E30 ldrb r3, [r3, #62] + 5098 00ba DBB2 uxtb r3, r3 + 5099 .loc 1 1746 49 discriminator 1 + 5100 00bc 012B cmp r3, #1 + 5101 00be 0CBF ite eq + 5102 00c0 0123 moveq r3, #1 + 5103 00c2 0023 movne r3, #0 + 5104 00c4 DBB2 uxtb r3, r3 + 5105 00c6 3CE0 b .L411 + 5106 .L410: + 5107 .loc 1 1746 49 is_stmt 0 discriminator 2 + 5108 00c8 BB68 ldr r3, [r7, #8] + 5109 00ca 042B cmp r3, #4 + 5110 00cc 09D1 bne .L412 + 5111 .loc 1 1746 12 is_stmt 1 discriminator 4 + 5112 00ce FB68 ldr r3, [r7, #12] + 5113 00d0 93F83F30 ldrb r3, [r3, #63] + 5114 00d4 DBB2 uxtb r3, r3 + 5115 .loc 1 1746 49 discriminator 4 + 5116 00d6 012B cmp r3, #1 + 5117 00d8 0CBF ite eq + 5118 00da 0123 moveq r3, #1 + 5119 00dc 0023 movne r3, #0 + 5120 00de DBB2 uxtb r3, r3 + 5121 00e0 2FE0 b .L411 + 5122 .L412: + 5123 .loc 1 1746 49 is_stmt 0 discriminator 5 + 5124 00e2 BB68 ldr r3, [r7, #8] + 5125 00e4 082B cmp r3, #8 + 5126 00e6 09D1 bne .L414 + 5127 .loc 1 1746 12 is_stmt 1 discriminator 7 + 5128 00e8 FB68 ldr r3, [r7, #12] + 5129 00ea 93F84030 ldrb r3, [r3, #64] + 5130 00ee DBB2 uxtb r3, r3 + 5131 .loc 1 1746 49 discriminator 7 + 5132 00f0 012B cmp r3, #1 + 5133 00f2 0CBF ite eq + 5134 00f4 0123 moveq r3, #1 + ARM GAS /tmp/ccl4b9YO.s page 121 + + + 5135 00f6 0023 movne r3, #0 + 5136 00f8 DBB2 uxtb r3, r3 + 5137 00fa 22E0 b .L411 + 5138 .L414: + 5139 .loc 1 1746 49 is_stmt 0 discriminator 8 + 5140 00fc BB68 ldr r3, [r7, #8] + 5141 00fe 0C2B cmp r3, #12 + 5142 0100 09D1 bne .L416 + 5143 .loc 1 1746 12 is_stmt 1 discriminator 10 + 5144 0102 FB68 ldr r3, [r7, #12] + 5145 0104 93F84130 ldrb r3, [r3, #65] + 5146 0108 DBB2 uxtb r3, r3 + 5147 .loc 1 1746 49 discriminator 10 + 5148 010a 012B cmp r3, #1 + 5149 010c 0CBF ite eq + 5150 010e 0123 moveq r3, #1 + 5151 0110 0023 movne r3, #0 + 5152 0112 DBB2 uxtb r3, r3 + 5153 0114 15E0 b .L411 + 5154 .L416: + 5155 .loc 1 1746 49 is_stmt 0 discriminator 11 + 5156 0116 BB68 ldr r3, [r7, #8] + 5157 0118 102B cmp r3, #16 + 5158 011a 09D1 bne .L418 + 5159 .loc 1 1746 12 is_stmt 1 discriminator 13 + 5160 011c FB68 ldr r3, [r7, #12] + 5161 011e 93F84230 ldrb r3, [r3, #66] + 5162 0122 DBB2 uxtb r3, r3 + 5163 .loc 1 1746 49 discriminator 13 + 5164 0124 012B cmp r3, #1 + 5165 0126 0CBF ite eq + 5166 0128 0123 moveq r3, #1 + 5167 012a 0023 movne r3, #0 + 5168 012c DBB2 uxtb r3, r3 + 5169 012e 08E0 b .L411 + 5170 .L418: + 5171 .loc 1 1746 12 discriminator 14 + 5172 0130 FB68 ldr r3, [r7, #12] + 5173 0132 93F84330 ldrb r3, [r3, #67] + 5174 0136 DBB2 uxtb r3, r3 + 5175 .loc 1 1746 49 discriminator 14 + 5176 0138 012B cmp r3, #1 + 5177 013a 0CBF ite eq + 5178 013c 0123 moveq r3, #1 + 5179 013e 0023 movne r3, #0 + 5180 0140 DBB2 uxtb r3, r3 + 5181 .L411: + 5182 .loc 1 1746 11 discriminator 20 + 5183 0142 002B cmp r3, #0 + 5184 0144 34D0 beq .L420 +1747:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1748:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if ((pData == NULL) || (Length == 0U)) + 5185 .loc 1 1748 8 + 5186 0146 7B68 ldr r3, [r7, #4] + 5187 0148 002B cmp r3, #0 + 5188 014a 02D0 beq .L421 + 5189 .loc 1 1748 25 discriminator 1 + ARM GAS /tmp/ccl4b9YO.s page 122 + + + 5190 014c 7B88 ldrh r3, [r7, #2] + 5191 014e 002B cmp r3, #0 + 5192 0150 01D1 bne .L422 + 5193 .L421: +1749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 5194 .loc 1 1750 14 + 5195 0152 0123 movs r3, #1 + 5196 0154 48E1 b .L409 + 5197 .L422: +1751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1752:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +1753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + 5198 .loc 1 1754 7 + 5199 0156 BB68 ldr r3, [r7, #8] + 5200 0158 002B cmp r3, #0 + 5201 015a 04D1 bne .L423 + 5202 .loc 1 1754 7 is_stmt 0 discriminator 1 + 5203 015c FB68 ldr r3, [r7, #12] + 5204 015e 0222 movs r2, #2 + 5205 0160 83F83E20 strb r2, [r3, #62] + 5206 0164 26E0 b .L424 + 5207 .L423: + 5208 .loc 1 1754 7 discriminator 2 + 5209 0166 BB68 ldr r3, [r7, #8] + 5210 0168 042B cmp r3, #4 + 5211 016a 04D1 bne .L425 + 5212 .loc 1 1754 7 discriminator 3 + 5213 016c FB68 ldr r3, [r7, #12] + 5214 016e 0222 movs r2, #2 + 5215 0170 83F83F20 strb r2, [r3, #63] + 5216 .loc 1 1754 7 discriminator 18 + 5217 0174 1EE0 b .L424 + 5218 .L425: + 5219 .loc 1 1754 7 discriminator 4 + 5220 0176 BB68 ldr r3, [r7, #8] + 5221 0178 082B cmp r3, #8 + 5222 017a 04D1 bne .L427 + 5223 .loc 1 1754 7 discriminator 6 + 5224 017c FB68 ldr r3, [r7, #12] + 5225 017e 0222 movs r2, #2 + 5226 0180 83F84020 strb r2, [r3, #64] + 5227 .loc 1 1754 7 discriminator 18 + 5228 0184 16E0 b .L424 + 5229 .L427: + 5230 .loc 1 1754 7 discriminator 7 + 5231 0186 BB68 ldr r3, [r7, #8] + 5232 0188 0C2B cmp r3, #12 + 5233 018a 04D1 bne .L429 + 5234 .loc 1 1754 7 discriminator 9 + 5235 018c FB68 ldr r3, [r7, #12] + 5236 018e 0222 movs r2, #2 + 5237 0190 83F84120 strb r2, [r3, #65] + 5238 .loc 1 1754 7 discriminator 18 + 5239 0194 0EE0 b .L424 + 5240 .L429: + ARM GAS /tmp/ccl4b9YO.s page 123 + + + 5241 .loc 1 1754 7 discriminator 10 + 5242 0196 BB68 ldr r3, [r7, #8] + 5243 0198 102B cmp r3, #16 + 5244 019a 04D1 bne .L431 + 5245 .loc 1 1754 7 discriminator 12 + 5246 019c FB68 ldr r3, [r7, #12] + 5247 019e 0222 movs r2, #2 + 5248 01a0 83F84220 strb r2, [r3, #66] + 5249 .loc 1 1754 7 discriminator 18 + 5250 01a4 06E0 b .L424 + 5251 .L431: + 5252 .loc 1 1754 7 discriminator 13 + 5253 01a6 FB68 ldr r3, [r7, #12] + 5254 01a8 0222 movs r2, #2 + 5255 01aa 83F84320 strb r2, [r3, #67] + 5256 01ae 01E0 b .L424 + 5257 .L420: +1755:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +1758:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 5258 .loc 1 1759 12 is_stmt 1 + 5259 01b0 0123 movs r3, #1 + 5260 01b2 19E1 b .L409 + 5261 .L424: +1760:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1761:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** switch (Channel) + 5262 .loc 1 1762 3 + 5263 01b4 BB68 ldr r3, [r7, #8] + 5264 01b6 0C2B cmp r3, #12 + 5265 01b8 00F2AE80 bhi .L433 + 5266 01bc 01A2 adr r2, .L435 + 5267 01be 52F823F0 ldr pc, [r2, r3, lsl #2] + 5268 01c2 00BF .p2align 2 + 5269 .L435: + 5270 01c4 F9010000 .word .L438+1 + 5271 01c8 19030000 .word .L433+1 + 5272 01cc 19030000 .word .L433+1 + 5273 01d0 19030000 .word .L433+1 + 5274 01d4 41020000 .word .L437+1 + 5275 01d8 19030000 .word .L433+1 + 5276 01dc 19030000 .word .L433+1 + 5277 01e0 19030000 .word .L433+1 + 5278 01e4 89020000 .word .L436+1 + 5279 01e8 19030000 .word .L433+1 + 5280 01ec 19030000 .word .L433+1 + 5281 01f0 19030000 .word .L433+1 + 5282 01f4 D1020000 .word .L434+1 + 5283 .p2align 1 + 5284 .L438: +1763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1764:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_1: +1765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA compare callbacks */ +1767:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + ARM GAS /tmp/ccl4b9YO.s page 124 + + + 5285 .loc 1 1767 17 + 5286 01f8 FB68 ldr r3, [r7, #12] + 5287 01fa 5B6A ldr r3, [r3, #36] + 5288 .loc 1 1767 52 + 5289 01fc 7C4A ldr r2, .L453 + 5290 01fe 9A62 str r2, [r3, #40] +1768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 5291 .loc 1 1768 17 + 5292 0200 FB68 ldr r3, [r7, #12] + 5293 0202 5B6A ldr r3, [r3, #36] + 5294 .loc 1 1768 56 + 5295 0204 7B4A ldr r2, .L453+4 + 5296 0206 DA62 str r2, [r3, #44] +1769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA error callback */ +1771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + 5297 .loc 1 1771 17 + 5298 0208 FB68 ldr r3, [r7, #12] + 5299 020a 5B6A ldr r3, [r3, #36] + 5300 .loc 1 1771 53 + 5301 020c 7A4A ldr r2, .L453+8 + 5302 020e 1A63 str r2, [r3, #48] +1772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the DMA channel */ +1774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance-> + 5303 .loc 1 1774 11 + 5304 0210 FB68 ldr r3, [r7, #12] + 5305 0212 586A ldr r0, [r3, #36] + 5306 0214 7968 ldr r1, [r7, #4] + 5307 .loc 1 1774 88 + 5308 0216 FB68 ldr r3, [r7, #12] + 5309 0218 1B68 ldr r3, [r3] + 5310 .loc 1 1774 83 + 5311 021a 3433 adds r3, r3, #52 + 5312 .loc 1 1774 11 + 5313 021c 1A46 mov r2, r3 + 5314 021e 7B88 ldrh r3, [r7, #2] + 5315 0220 FFF7FEFF bl HAL_DMA_Start_IT + 5316 0224 0346 mov r3, r0 + 5317 .loc 1 1774 10 discriminator 1 + 5318 0226 002B cmp r3, #0 + 5319 0228 01D0 beq .L439 +1775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** Length) != HAL_OK) +1776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1777:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return error status */ +1778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 5320 .loc 1 1778 16 + 5321 022a 0123 movs r3, #1 + 5322 022c DCE0 b .L409 + 5323 .L439: +1779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1780:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the TIM Capture/Compare 1 DMA request */ +1782:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + 5324 .loc 1 1782 7 + 5325 022e FB68 ldr r3, [r7, #12] + 5326 0230 1B68 ldr r3, [r3] + ARM GAS /tmp/ccl4b9YO.s page 125 + + + 5327 0232 DA68 ldr r2, [r3, #12] + 5328 0234 FB68 ldr r3, [r7, #12] + 5329 0236 1B68 ldr r3, [r3] + 5330 0238 42F40072 orr r2, r2, #512 + 5331 023c DA60 str r2, [r3, #12] +1783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 5332 .loc 1 1783 7 + 5333 023e 6EE0 b .L440 + 5334 .L437: +1784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_2: +1787:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1788:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA compare callbacks */ +1789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + 5335 .loc 1 1789 17 + 5336 0240 FB68 ldr r3, [r7, #12] + 5337 0242 9B6A ldr r3, [r3, #40] + 5338 .loc 1 1789 52 + 5339 0244 6A4A ldr r2, .L453 + 5340 0246 9A62 str r2, [r3, #40] +1790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 5341 .loc 1 1790 17 + 5342 0248 FB68 ldr r3, [r7, #12] + 5343 024a 9B6A ldr r3, [r3, #40] + 5344 .loc 1 1790 56 + 5345 024c 694A ldr r2, .L453+4 + 5346 024e DA62 str r2, [r3, #44] +1791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA error callback */ +1793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + 5347 .loc 1 1793 17 + 5348 0250 FB68 ldr r3, [r7, #12] + 5349 0252 9B6A ldr r3, [r3, #40] + 5350 .loc 1 1793 53 + 5351 0254 684A ldr r2, .L453+8 + 5352 0256 1A63 str r2, [r3, #48] +1794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the DMA channel */ +1796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance-> + 5353 .loc 1 1796 11 + 5354 0258 FB68 ldr r3, [r7, #12] + 5355 025a 986A ldr r0, [r3, #40] + 5356 025c 7968 ldr r1, [r7, #4] + 5357 .loc 1 1796 88 + 5358 025e FB68 ldr r3, [r7, #12] + 5359 0260 1B68 ldr r3, [r3] + 5360 .loc 1 1796 83 + 5361 0262 3833 adds r3, r3, #56 + 5362 .loc 1 1796 11 + 5363 0264 1A46 mov r2, r3 + 5364 0266 7B88 ldrh r3, [r7, #2] + 5365 0268 FFF7FEFF bl HAL_DMA_Start_IT + 5366 026c 0346 mov r3, r0 + 5367 .loc 1 1796 10 discriminator 1 + 5368 026e 002B cmp r3, #0 + 5369 0270 01D0 beq .L441 + ARM GAS /tmp/ccl4b9YO.s page 126 + + +1797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** Length) != HAL_OK) +1798:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1799:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return error status */ +1800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 5370 .loc 1 1800 16 + 5371 0272 0123 movs r3, #1 + 5372 0274 B8E0 b .L409 + 5373 .L441: +1801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the TIM Capture/Compare 2 DMA request */ +1803:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + 5374 .loc 1 1803 7 + 5375 0276 FB68 ldr r3, [r7, #12] + 5376 0278 1B68 ldr r3, [r3] + 5377 027a DA68 ldr r2, [r3, #12] + 5378 027c FB68 ldr r3, [r7, #12] + 5379 027e 1B68 ldr r3, [r3] + 5380 0280 42F48062 orr r2, r2, #1024 + 5381 0284 DA60 str r2, [r3, #12] +1804:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 5382 .loc 1 1804 7 + 5383 0286 4AE0 b .L440 + 5384 .L436: +1805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1806:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1807:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_3: +1808:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA compare callbacks */ +1810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + 5385 .loc 1 1810 17 + 5386 0288 FB68 ldr r3, [r7, #12] + 5387 028a DB6A ldr r3, [r3, #44] + 5388 .loc 1 1810 52 + 5389 028c 584A ldr r2, .L453 + 5390 028e 9A62 str r2, [r3, #40] +1811:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 5391 .loc 1 1811 17 + 5392 0290 FB68 ldr r3, [r7, #12] + 5393 0292 DB6A ldr r3, [r3, #44] + 5394 .loc 1 1811 56 + 5395 0294 574A ldr r2, .L453+4 + 5396 0296 DA62 str r2, [r3, #44] +1812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA error callback */ +1814:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + 5397 .loc 1 1814 17 + 5398 0298 FB68 ldr r3, [r7, #12] + 5399 029a DB6A ldr r3, [r3, #44] + 5400 .loc 1 1814 53 + 5401 029c 564A ldr r2, .L453+8 + 5402 029e 1A63 str r2, [r3, #48] +1815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the DMA channel */ +1817:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance-> + 5403 .loc 1 1817 11 + 5404 02a0 FB68 ldr r3, [r7, #12] + 5405 02a2 D86A ldr r0, [r3, #44] + ARM GAS /tmp/ccl4b9YO.s page 127 + + + 5406 02a4 7968 ldr r1, [r7, #4] + 5407 .loc 1 1817 88 + 5408 02a6 FB68 ldr r3, [r7, #12] + 5409 02a8 1B68 ldr r3, [r3] + 5410 .loc 1 1817 83 + 5411 02aa 3C33 adds r3, r3, #60 + 5412 .loc 1 1817 11 + 5413 02ac 1A46 mov r2, r3 + 5414 02ae 7B88 ldrh r3, [r7, #2] + 5415 02b0 FFF7FEFF bl HAL_DMA_Start_IT + 5416 02b4 0346 mov r3, r0 + 5417 .loc 1 1817 10 discriminator 1 + 5418 02b6 002B cmp r3, #0 + 5419 02b8 01D0 beq .L442 +1818:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** Length) != HAL_OK) +1819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1820:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return error status */ +1821:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 5420 .loc 1 1821 16 + 5421 02ba 0123 movs r3, #1 + 5422 02bc 94E0 b .L409 + 5423 .L442: +1822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the TIM Output Capture/Compare 3 request */ +1824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + 5424 .loc 1 1824 7 + 5425 02be FB68 ldr r3, [r7, #12] + 5426 02c0 1B68 ldr r3, [r3] + 5427 02c2 DA68 ldr r2, [r3, #12] + 5428 02c4 FB68 ldr r3, [r7, #12] + 5429 02c6 1B68 ldr r3, [r3] + 5430 02c8 42F40062 orr r2, r2, #2048 + 5431 02cc DA60 str r2, [r3, #12] +1825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 5432 .loc 1 1825 7 + 5433 02ce 26E0 b .L440 + 5434 .L434: +1826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1827:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1828:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_4: +1829:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1830:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA compare callbacks */ +1831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + 5435 .loc 1 1831 17 + 5436 02d0 FB68 ldr r3, [r7, #12] + 5437 02d2 1B6B ldr r3, [r3, #48] + 5438 .loc 1 1831 52 + 5439 02d4 464A ldr r2, .L453 + 5440 02d6 9A62 str r2, [r3, #40] +1832:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 5441 .loc 1 1832 17 + 5442 02d8 FB68 ldr r3, [r7, #12] + 5443 02da 1B6B ldr r3, [r3, #48] + 5444 .loc 1 1832 56 + 5445 02dc 454A ldr r2, .L453+4 + 5446 02de DA62 str r2, [r3, #44] +1833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + ARM GAS /tmp/ccl4b9YO.s page 128 + + +1834:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA error callback */ +1835:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + 5447 .loc 1 1835 17 + 5448 02e0 FB68 ldr r3, [r7, #12] + 5449 02e2 1B6B ldr r3, [r3, #48] + 5450 .loc 1 1835 53 + 5451 02e4 444A ldr r2, .L453+8 + 5452 02e6 1A63 str r2, [r3, #48] +1836:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the DMA channel */ +1838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance-> + 5453 .loc 1 1838 11 + 5454 02e8 FB68 ldr r3, [r7, #12] + 5455 02ea 186B ldr r0, [r3, #48] + 5456 02ec 7968 ldr r1, [r7, #4] + 5457 .loc 1 1838 88 + 5458 02ee FB68 ldr r3, [r7, #12] + 5459 02f0 1B68 ldr r3, [r3] + 5460 .loc 1 1838 83 + 5461 02f2 4033 adds r3, r3, #64 + 5462 .loc 1 1838 11 + 5463 02f4 1A46 mov r2, r3 + 5464 02f6 7B88 ldrh r3, [r7, #2] + 5465 02f8 FFF7FEFF bl HAL_DMA_Start_IT + 5466 02fc 0346 mov r3, r0 + 5467 .loc 1 1838 10 discriminator 1 + 5468 02fe 002B cmp r3, #0 + 5469 0300 01D0 beq .L443 +1839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** Length) != HAL_OK) +1840:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return error status */ +1842:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 5470 .loc 1 1842 16 + 5471 0302 0123 movs r3, #1 + 5472 0304 70E0 b .L409 + 5473 .L443: +1843:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1844:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the TIM Capture/Compare 4 DMA request */ +1845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + 5474 .loc 1 1845 7 + 5475 0306 FB68 ldr r3, [r7, #12] + 5476 0308 1B68 ldr r3, [r3] + 5477 030a DA68 ldr r2, [r3, #12] + 5478 030c FB68 ldr r3, [r7, #12] + 5479 030e 1B68 ldr r3, [r3] + 5480 0310 42F48052 orr r2, r2, #4096 + 5481 0314 DA60 str r2, [r3, #12] +1846:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 5482 .loc 1 1846 7 + 5483 0316 02E0 b .L440 + 5484 .L433: +1847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** default: +1850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** status = HAL_ERROR; + 5485 .loc 1 1850 14 + 5486 0318 0123 movs r3, #1 + ARM GAS /tmp/ccl4b9YO.s page 129 + + + 5487 031a FB75 strb r3, [r7, #23] +1851:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 5488 .loc 1 1851 7 + 5489 031c 00BF nop + 5490 .L440: +1852:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1853:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (status == HAL_OK) + 5491 .loc 1 1854 6 + 5492 031e FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 5493 0320 002B cmp r3, #0 + 5494 0322 60D1 bne .L444 +1855:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1856:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the Capture compare channel */ +1857:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + 5495 .loc 1 1857 5 + 5496 0324 FB68 ldr r3, [r7, #12] + 5497 0326 1B68 ldr r3, [r3] + 5498 0328 0122 movs r2, #1 + 5499 032a B968 ldr r1, [r7, #8] + 5500 032c 1846 mov r0, r3 + 5501 032e FFF7FEFF bl TIM_CCxChannelCmd +1858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1859:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + 5502 .loc 1 1859 9 + 5503 0332 FB68 ldr r3, [r7, #12] + 5504 0334 1B68 ldr r3, [r3] + 5505 0336 314A ldr r2, .L453+12 + 5506 0338 9342 cmp r3, r2 + 5507 033a 0ED0 beq .L445 + 5508 .loc 1 1859 9 is_stmt 0 discriminator 2 + 5509 033c FB68 ldr r3, [r7, #12] + 5510 033e 1B68 ldr r3, [r3] + 5511 0340 2F4A ldr r2, .L453+16 + 5512 0342 9342 cmp r3, r2 + 5513 0344 09D0 beq .L445 + 5514 .loc 1 1859 9 discriminator 4 + 5515 0346 FB68 ldr r3, [r7, #12] + 5516 0348 1B68 ldr r3, [r3] + 5517 034a 2E4A ldr r2, .L453+20 + 5518 034c 9342 cmp r3, r2 + 5519 034e 04D0 beq .L445 + 5520 .loc 1 1859 9 discriminator 6 + 5521 0350 FB68 ldr r3, [r7, #12] + 5522 0352 1B68 ldr r3, [r3] + 5523 0354 2C4A ldr r2, .L453+24 + 5524 0356 9342 cmp r3, r2 + 5525 0358 01D1 bne .L446 + 5526 .L445: + 5527 .loc 1 1859 9 discriminator 7 + 5528 035a 0123 movs r3, #1 + 5529 .loc 1 1859 9 + 5530 035c 00E0 b .L447 + 5531 .L446: + 5532 .loc 1 1859 9 discriminator 8 + 5533 035e 0023 movs r3, #0 + 5534 .L447: + ARM GAS /tmp/ccl4b9YO.s page 130 + + + 5535 .loc 1 1859 8 is_stmt 1 discriminator 10 + 5536 0360 002B cmp r3, #0 + 5537 0362 07D0 beq .L448 +1860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the main output */ +1862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_MOE_ENABLE(htim); + 5538 .loc 1 1862 7 + 5539 0364 FB68 ldr r3, [r7, #12] + 5540 0366 1B68 ldr r3, [r3] + 5541 0368 5A6C ldr r2, [r3, #68] + 5542 036a FB68 ldr r3, [r7, #12] + 5543 036c 1B68 ldr r3, [r3] + 5544 036e 42F40042 orr r2, r2, #32768 + 5545 0372 5A64 str r2, [r3, #68] + 5546 .L448: +1863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1864:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigge +1866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 5547 .loc 1 1866 9 + 5548 0374 FB68 ldr r3, [r7, #12] + 5549 0376 1B68 ldr r3, [r3] + 5550 .loc 1 1866 8 + 5551 0378 204A ldr r2, .L453+12 + 5552 037a 9342 cmp r3, r2 + 5553 037c 13D0 beq .L449 + 5554 .loc 1 1866 9 discriminator 1 + 5555 037e FB68 ldr r3, [r7, #12] + 5556 0380 1B68 ldr r3, [r3] + 5557 0382 B3F1804F cmp r3, #1073741824 + 5558 0386 0ED0 beq .L449 + 5559 .loc 1 1866 9 is_stmt 0 discriminator 2 + 5560 0388 FB68 ldr r3, [r7, #12] + 5561 038a 1B68 ldr r3, [r3] + 5562 038c 1F4A ldr r2, .L453+28 + 5563 038e 9342 cmp r3, r2 + 5564 0390 09D0 beq .L449 + 5565 .loc 1 1866 9 discriminator 3 + 5566 0392 FB68 ldr r3, [r7, #12] + 5567 0394 1B68 ldr r3, [r3] + 5568 0396 1E4A ldr r2, .L453+32 + 5569 0398 9342 cmp r3, r2 + 5570 039a 04D0 beq .L449 + 5571 .loc 1 1866 9 discriminator 4 + 5572 039c FB68 ldr r3, [r7, #12] + 5573 039e 1B68 ldr r3, [r3] + 5574 03a0 174A ldr r2, .L453+16 + 5575 03a2 9342 cmp r3, r2 + 5576 03a4 15D1 bne .L450 + 5577 .L449: +1867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1868:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + 5578 .loc 1 1868 21 is_stmt 1 + 5579 03a6 FB68 ldr r3, [r7, #12] + 5580 03a8 1B68 ldr r3, [r3] + 5581 .loc 1 1868 31 + 5582 03aa 9A68 ldr r2, [r3, #8] + ARM GAS /tmp/ccl4b9YO.s page 131 + + + 5583 .loc 1 1868 15 + 5584 03ac 194B ldr r3, .L453+36 + 5585 03ae 1340 ands r3, r3, r2 + 5586 03b0 3B61 str r3, [r7, #16] +1869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 5587 .loc 1 1869 10 + 5588 03b2 3B69 ldr r3, [r7, #16] + 5589 03b4 062B cmp r3, #6 + 5590 03b6 15D0 beq .L452 + 5591 .loc 1 1869 11 discriminator 1 + 5592 03b8 3B69 ldr r3, [r7, #16] + 5593 03ba B3F5803F cmp r3, #65536 + 5594 03be 11D0 beq .L452 +1870:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); + 5595 .loc 1 1871 9 + 5596 03c0 FB68 ldr r3, [r7, #12] + 5597 03c2 1B68 ldr r3, [r3] + 5598 03c4 1A68 ldr r2, [r3] + 5599 03c6 FB68 ldr r3, [r7, #12] + 5600 03c8 1B68 ldr r3, [r3] + 5601 03ca 42F00102 orr r2, r2, #1 + 5602 03ce 1A60 str r2, [r3] +1869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 5603 .loc 1 1869 10 + 5604 03d0 08E0 b .L452 + 5605 .L450: +1872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1873:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +1875:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); + 5606 .loc 1 1876 7 + 5607 03d2 FB68 ldr r3, [r7, #12] + 5608 03d4 1B68 ldr r3, [r3] + 5609 03d6 1A68 ldr r2, [r3] + 5610 03d8 FB68 ldr r3, [r7, #12] + 5611 03da 1B68 ldr r3, [r3] + 5612 03dc 42F00102 orr r2, r2, #1 + 5613 03e0 1A60 str r2, [r3] + 5614 03e2 00E0 b .L444 + 5615 .L452: +1869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 5616 .loc 1 1869 10 + 5617 03e4 00BF nop + 5618 .L444: +1877:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1878:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1879:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return function status */ +1881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return status; + 5619 .loc 1 1881 10 + 5620 03e6 FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 5621 .L409: +1882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 5622 .loc 1 1882 1 + 5623 03e8 1846 mov r0, r3 + ARM GAS /tmp/ccl4b9YO.s page 132 + + + 5624 03ea 1837 adds r7, r7, #24 + 5625 .cfi_def_cfa_offset 8 + 5626 03ec BD46 mov sp, r7 + 5627 .cfi_def_cfa_register 13 + 5628 @ sp needed + 5629 03ee 80BD pop {r7, pc} + 5630 .L454: + 5631 .align 2 + 5632 .L453: + 5633 03f0 00000000 .word TIM_DMADelayPulseCplt + 5634 03f4 00000000 .word TIM_DMADelayPulseHalfCplt + 5635 03f8 00000000 .word TIM_DMAError + 5636 03fc 002C0140 .word 1073818624 + 5637 0400 00400140 .word 1073823744 + 5638 0404 00440140 .word 1073824768 + 5639 0408 00480140 .word 1073825792 + 5640 040c 00040040 .word 1073742848 + 5641 0410 00080040 .word 1073743872 + 5642 0414 07000100 .word 65543 + 5643 .cfi_endproc + 5644 .LFE158: + 5646 .section .text.HAL_TIM_PWM_Stop_DMA,"ax",%progbits + 5647 .align 1 + 5648 .global HAL_TIM_PWM_Stop_DMA + 5649 .syntax unified + 5650 .thumb + 5651 .thumb_func + 5653 HAL_TIM_PWM_Stop_DMA: + 5654 .LFB159: +1883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1884:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +1885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Stops the TIM PWM signal generation in DMA mode. +1886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM PWM handle +1887:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param Channel TIM Channels to be disabled +1888:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +1889:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +1890:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +1891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +1892:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +1893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status +1894:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +1895:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +1896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 5655 .loc 1 1896 1 + 5656 .cfi_startproc + 5657 @ args = 0, pretend = 0, frame = 16 + 5658 @ frame_needed = 1, uses_anonymous_args = 0 + 5659 0000 80B5 push {r7, lr} + 5660 .cfi_def_cfa_offset 8 + 5661 .cfi_offset 7, -8 + 5662 .cfi_offset 14, -4 + 5663 0002 84B0 sub sp, sp, #16 + 5664 .cfi_def_cfa_offset 24 + 5665 0004 00AF add r7, sp, #0 + 5666 .cfi_def_cfa_register 7 + 5667 0006 7860 str r0, [r7, #4] + 5668 0008 3960 str r1, [r7] + ARM GAS /tmp/ccl4b9YO.s page 133 + + +1897:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 5669 .loc 1 1897 21 + 5670 000a 0023 movs r3, #0 + 5671 000c FB73 strb r3, [r7, #15] +1898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1899:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +1900:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); +1901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1902:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** switch (Channel) + 5672 .loc 1 1902 3 + 5673 000e 3B68 ldr r3, [r7] + 5674 0010 0C2B cmp r3, #12 + 5675 0012 55D8 bhi .L456 + 5676 0014 01A2 adr r2, .L458 + 5677 0016 52F823F0 ldr pc, [r2, r3, lsl #2] + 5678 001a 00BF .p2align 2 + 5679 .L458: + 5680 001c 51000000 .word .L461+1 + 5681 0020 C1000000 .word .L456+1 + 5682 0024 C1000000 .word .L456+1 + 5683 0028 C1000000 .word .L456+1 + 5684 002c 6D000000 .word .L460+1 + 5685 0030 C1000000 .word .L456+1 + 5686 0034 C1000000 .word .L456+1 + 5687 0038 C1000000 .word .L456+1 + 5688 003c 89000000 .word .L459+1 + 5689 0040 C1000000 .word .L456+1 + 5690 0044 C1000000 .word .L456+1 + 5691 0048 C1000000 .word .L456+1 + 5692 004c A5000000 .word .L457+1 + 5693 .p2align 1 + 5694 .L461: +1903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1904:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_1: +1905:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1906:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the TIM Capture/Compare 1 DMA request */ +1907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + 5695 .loc 1 1907 7 + 5696 0050 7B68 ldr r3, [r7, #4] + 5697 0052 1B68 ldr r3, [r3] + 5698 0054 DA68 ldr r2, [r3, #12] + 5699 0056 7B68 ldr r3, [r7, #4] + 5700 0058 1B68 ldr r3, [r3] + 5701 005a 22F40072 bic r2, r2, #512 + 5702 005e DA60 str r2, [r3, #12] +1908:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + 5703 .loc 1 1908 13 + 5704 0060 7B68 ldr r3, [r7, #4] + 5705 0062 5B6A ldr r3, [r3, #36] + 5706 0064 1846 mov r0, r3 + 5707 0066 FFF7FEFF bl HAL_DMA_Abort_IT +1909:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 5708 .loc 1 1909 7 + 5709 006a 2CE0 b .L462 + 5710 .L460: +1910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1911:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + ARM GAS /tmp/ccl4b9YO.s page 134 + + +1912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_2: +1913:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1914:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the TIM Capture/Compare 2 DMA request */ +1915:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + 5711 .loc 1 1915 7 + 5712 006c 7B68 ldr r3, [r7, #4] + 5713 006e 1B68 ldr r3, [r3] + 5714 0070 DA68 ldr r2, [r3, #12] + 5715 0072 7B68 ldr r3, [r7, #4] + 5716 0074 1B68 ldr r3, [r3] + 5717 0076 22F48062 bic r2, r2, #1024 + 5718 007a DA60 str r2, [r3, #12] +1916:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + 5719 .loc 1 1916 13 + 5720 007c 7B68 ldr r3, [r7, #4] + 5721 007e 9B6A ldr r3, [r3, #40] + 5722 0080 1846 mov r0, r3 + 5723 0082 FFF7FEFF bl HAL_DMA_Abort_IT +1917:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 5724 .loc 1 1917 7 + 5725 0086 1EE0 b .L462 + 5726 .L459: +1918:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1919:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1920:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_3: +1921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1922:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the TIM Capture/Compare 3 DMA request */ +1923:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + 5727 .loc 1 1923 7 + 5728 0088 7B68 ldr r3, [r7, #4] + 5729 008a 1B68 ldr r3, [r3] + 5730 008c DA68 ldr r2, [r3, #12] + 5731 008e 7B68 ldr r3, [r7, #4] + 5732 0090 1B68 ldr r3, [r3] + 5733 0092 22F40062 bic r2, r2, #2048 + 5734 0096 DA60 str r2, [r3, #12] +1924:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + 5735 .loc 1 1924 13 + 5736 0098 7B68 ldr r3, [r7, #4] + 5737 009a DB6A ldr r3, [r3, #44] + 5738 009c 1846 mov r0, r3 + 5739 009e FFF7FEFF bl HAL_DMA_Abort_IT +1925:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 5740 .loc 1 1925 7 + 5741 00a2 10E0 b .L462 + 5742 .L457: +1926:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1928:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_4: +1929:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1930:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the TIM Capture/Compare 4 interrupt */ +1931:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + 5743 .loc 1 1931 7 + 5744 00a4 7B68 ldr r3, [r7, #4] + 5745 00a6 1B68 ldr r3, [r3] + 5746 00a8 DA68 ldr r2, [r3, #12] + 5747 00aa 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/ccl4b9YO.s page 135 + + + 5748 00ac 1B68 ldr r3, [r3] + 5749 00ae 22F48052 bic r2, r2, #4096 + 5750 00b2 DA60 str r2, [r3, #12] +1932:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + 5751 .loc 1 1932 13 + 5752 00b4 7B68 ldr r3, [r7, #4] + 5753 00b6 1B6B ldr r3, [r3, #48] + 5754 00b8 1846 mov r0, r3 + 5755 00ba FFF7FEFF bl HAL_DMA_Abort_IT +1933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 5756 .loc 1 1933 7 + 5757 00be 02E0 b .L462 + 5758 .L456: +1934:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1935:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1936:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** default: +1937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** status = HAL_ERROR; + 5759 .loc 1 1937 14 + 5760 00c0 0123 movs r3, #1 + 5761 00c2 FB73 strb r3, [r7, #15] +1938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 5762 .loc 1 1938 7 + 5763 00c4 00BF nop + 5764 .L462: +1939:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1941:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (status == HAL_OK) + 5765 .loc 1 1941 6 + 5766 00c6 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 5767 00c8 002B cmp r3, #0 + 5768 00ca 7BD1 bne .L463 +1942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1943:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the Capture compare channel */ +1944:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + 5769 .loc 1 1944 5 + 5770 00cc 7B68 ldr r3, [r7, #4] + 5771 00ce 1B68 ldr r3, [r3] + 5772 00d0 0022 movs r2, #0 + 5773 00d2 3968 ldr r1, [r7] + 5774 00d4 1846 mov r0, r3 + 5775 00d6 FFF7FEFF bl TIM_CCxChannelCmd +1945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + 5776 .loc 1 1946 9 + 5777 00da 7B68 ldr r3, [r7, #4] + 5778 00dc 1B68 ldr r3, [r3] + 5779 00de 3C4A ldr r2, .L479 + 5780 00e0 9342 cmp r3, r2 + 5781 00e2 0ED0 beq .L464 + 5782 .loc 1 1946 9 is_stmt 0 discriminator 2 + 5783 00e4 7B68 ldr r3, [r7, #4] + 5784 00e6 1B68 ldr r3, [r3] + 5785 00e8 3A4A ldr r2, .L479+4 + 5786 00ea 9342 cmp r3, r2 + 5787 00ec 09D0 beq .L464 + 5788 .loc 1 1946 9 discriminator 4 + 5789 00ee 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/ccl4b9YO.s page 136 + + + 5790 00f0 1B68 ldr r3, [r3] + 5791 00f2 394A ldr r2, .L479+8 + 5792 00f4 9342 cmp r3, r2 + 5793 00f6 04D0 beq .L464 + 5794 .loc 1 1946 9 discriminator 6 + 5795 00f8 7B68 ldr r3, [r7, #4] + 5796 00fa 1B68 ldr r3, [r3] + 5797 00fc 374A ldr r2, .L479+12 + 5798 00fe 9342 cmp r3, r2 + 5799 0100 01D1 bne .L465 + 5800 .L464: + 5801 .loc 1 1946 9 discriminator 7 + 5802 0102 0123 movs r3, #1 + 5803 .loc 1 1946 9 + 5804 0104 00E0 b .L466 + 5805 .L465: + 5806 .loc 1 1946 9 discriminator 8 + 5807 0106 0023 movs r3, #0 + 5808 .L466: + 5809 .loc 1 1946 8 is_stmt 1 discriminator 10 + 5810 0108 002B cmp r3, #0 + 5811 010a 17D0 beq .L467 +1947:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +1948:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the Main Output */ +1949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_MOE_DISABLE(htim); + 5812 .loc 1 1949 7 + 5813 010c 7B68 ldr r3, [r7, #4] + 5814 010e 1B68 ldr r3, [r3] + 5815 0110 1A6A ldr r2, [r3, #32] + 5816 0112 41F21113 movw r3, #4369 + 5817 0116 1340 ands r3, r3, r2 + 5818 0118 002B cmp r3, #0 + 5819 011a 0FD1 bne .L467 + 5820 .loc 1 1949 7 is_stmt 0 discriminator 1 + 5821 011c 7B68 ldr r3, [r7, #4] + 5822 011e 1B68 ldr r3, [r3] + 5823 0120 1A6A ldr r2, [r3, #32] + 5824 0122 40F24443 movw r3, #1092 + 5825 0126 1340 ands r3, r3, r2 + 5826 0128 002B cmp r3, #0 + 5827 012a 07D1 bne .L467 + 5828 .loc 1 1949 7 discriminator 2 + 5829 012c 7B68 ldr r3, [r7, #4] + 5830 012e 1B68 ldr r3, [r3] + 5831 0130 5A6C ldr r2, [r3, #68] + 5832 0132 7B68 ldr r3, [r7, #4] + 5833 0134 1B68 ldr r3, [r3] + 5834 0136 22F40042 bic r2, r2, #32768 + 5835 013a 5A64 str r2, [r3, #68] + 5836 .L467: +1950:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1951:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the Peripheral */ +1953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); + 5837 .loc 1 1953 5 is_stmt 1 + 5838 013c 7B68 ldr r3, [r7, #4] + 5839 013e 1B68 ldr r3, [r3] + ARM GAS /tmp/ccl4b9YO.s page 137 + + + 5840 0140 1A6A ldr r2, [r3, #32] + 5841 0142 41F21113 movw r3, #4369 + 5842 0146 1340 ands r3, r3, r2 + 5843 0148 002B cmp r3, #0 + 5844 014a 0FD1 bne .L468 + 5845 .loc 1 1953 5 is_stmt 0 discriminator 1 + 5846 014c 7B68 ldr r3, [r7, #4] + 5847 014e 1B68 ldr r3, [r3] + 5848 0150 1A6A ldr r2, [r3, #32] + 5849 0152 40F24443 movw r3, #1092 + 5850 0156 1340 ands r3, r3, r2 + 5851 0158 002B cmp r3, #0 + 5852 015a 07D1 bne .L468 + 5853 .loc 1 1953 5 discriminator 2 + 5854 015c 7B68 ldr r3, [r7, #4] + 5855 015e 1B68 ldr r3, [r3] + 5856 0160 1A68 ldr r2, [r3] + 5857 0162 7B68 ldr r3, [r7, #4] + 5858 0164 1B68 ldr r3, [r3] + 5859 0166 22F00102 bic r2, r2, #1 + 5860 016a 1A60 str r2, [r3] + 5861 .L468: +1954:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the TIM channel state */ +1956:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 5862 .loc 1 1956 5 is_stmt 1 + 5863 016c 3B68 ldr r3, [r7] + 5864 016e 002B cmp r3, #0 + 5865 0170 04D1 bne .L469 + 5866 .loc 1 1956 5 is_stmt 0 discriminator 1 + 5867 0172 7B68 ldr r3, [r7, #4] + 5868 0174 0122 movs r2, #1 + 5869 0176 83F83E20 strb r2, [r3, #62] + 5870 017a 23E0 b .L463 + 5871 .L469: + 5872 .loc 1 1956 5 discriminator 2 + 5873 017c 3B68 ldr r3, [r7] + 5874 017e 042B cmp r3, #4 + 5875 0180 04D1 bne .L470 + 5876 .loc 1 1956 5 discriminator 3 + 5877 0182 7B68 ldr r3, [r7, #4] + 5878 0184 0122 movs r2, #1 + 5879 0186 83F83F20 strb r2, [r3, #63] + 5880 018a 1BE0 b .L463 + 5881 .L470: + 5882 .loc 1 1956 5 discriminator 4 + 5883 018c 3B68 ldr r3, [r7] + 5884 018e 082B cmp r3, #8 + 5885 0190 04D1 bne .L472 + 5886 .loc 1 1956 5 discriminator 6 + 5887 0192 7B68 ldr r3, [r7, #4] + 5888 0194 0122 movs r2, #1 + 5889 0196 83F84020 strb r2, [r3, #64] + 5890 019a 13E0 b .L463 + 5891 .L472: + 5892 .loc 1 1956 5 discriminator 7 + 5893 019c 3B68 ldr r3, [r7] + ARM GAS /tmp/ccl4b9YO.s page 138 + + + 5894 019e 0C2B cmp r3, #12 + 5895 01a0 04D1 bne .L474 + 5896 .loc 1 1956 5 discriminator 9 + 5897 01a2 7B68 ldr r3, [r7, #4] + 5898 01a4 0122 movs r2, #1 + 5899 01a6 83F84120 strb r2, [r3, #65] + 5900 01aa 0BE0 b .L463 + 5901 .L474: + 5902 .loc 1 1956 5 discriminator 10 + 5903 01ac 3B68 ldr r3, [r7] + 5904 01ae 102B cmp r3, #16 + 5905 01b0 04D1 bne .L476 + 5906 .loc 1 1956 5 discriminator 12 + 5907 01b2 7B68 ldr r3, [r7, #4] + 5908 01b4 0122 movs r2, #1 + 5909 01b6 83F84220 strb r2, [r3, #66] + 5910 01ba 03E0 b .L463 + 5911 .L476: + 5912 .loc 1 1956 5 discriminator 13 + 5913 01bc 7B68 ldr r3, [r7, #4] + 5914 01be 0122 movs r2, #1 + 5915 01c0 83F84320 strb r2, [r3, #67] + 5916 .L463: +1957:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +1958:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return function status */ +1960:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return status; + 5917 .loc 1 1960 10 is_stmt 1 + 5918 01c4 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 +1961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 5919 .loc 1 1961 1 + 5920 01c6 1846 mov r0, r3 + 5921 01c8 1037 adds r7, r7, #16 + 5922 .cfi_def_cfa_offset 8 + 5923 01ca BD46 mov sp, r7 + 5924 .cfi_def_cfa_register 13 + 5925 @ sp needed + 5926 01cc 80BD pop {r7, pc} + 5927 .L480: + 5928 01ce 00BF .align 2 + 5929 .L479: + 5930 01d0 002C0140 .word 1073818624 + 5931 01d4 00400140 .word 1073823744 + 5932 01d8 00440140 .word 1073824768 + 5933 01dc 00480140 .word 1073825792 + 5934 .cfi_endproc + 5935 .LFE159: + 5937 .section .text.HAL_TIM_IC_Init,"ax",%progbits + 5938 .align 1 + 5939 .global HAL_TIM_IC_Init + 5940 .syntax unified + 5941 .thumb + 5942 .thumb_func + 5944 HAL_TIM_IC_Init: + 5945 .LFB160: +1962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1963:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** + ARM GAS /tmp/ccl4b9YO.s page 139 + + +1964:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @} +1965:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +1966:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1967:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions +1968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief TIM Input Capture functions +1969:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * +1970:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** @verbatim +1971:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** ============================================================================== +1972:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** ##### TIM Input Capture functions ##### +1973:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** ============================================================================== +1974:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** [..] +1975:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** This section provides functions allowing to: +1976:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Initialize and configure the TIM Input Capture. +1977:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) De-initialize the TIM Input Capture. +1978:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Start the TIM Input Capture. +1979:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Stop the TIM Input Capture. +1980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Start the TIM Input Capture and enable interrupt. +1981:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Stop the TIM Input Capture and disable interrupt. +1982:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Start the TIM Input Capture and enable DMA transfer. +1983:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Stop the TIM Input Capture and disable DMA transfer. +1984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +1985:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** @endverbatim +1986:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @{ +1987:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +1988:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +1989:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Initializes the TIM Input Capture Time base according to the specified +1990:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * parameters in the TIM_HandleTypeDef and initializes the associated handle. +1991:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) +1992:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * requires a timer reset to avoid unexpected direction +1993:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * due to DIR bit readonly in center aligned mode. +1994:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init() +1995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM Input Capture handle +1996:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status +1997:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +1998:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) +1999:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 5946 .loc 1 1999 1 + 5947 .cfi_startproc + 5948 @ args = 0, pretend = 0, frame = 8 + 5949 @ frame_needed = 1, uses_anonymous_args = 0 + 5950 0000 80B5 push {r7, lr} + 5951 .cfi_def_cfa_offset 8 + 5952 .cfi_offset 7, -8 + 5953 .cfi_offset 14, -4 + 5954 0002 82B0 sub sp, sp, #8 + 5955 .cfi_def_cfa_offset 16 + 5956 0004 00AF add r7, sp, #0 + 5957 .cfi_def_cfa_register 7 + 5958 0006 7860 str r0, [r7, #4] +2000:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the TIM handle allocation */ +2001:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (htim == NULL) + 5959 .loc 1 2001 6 + 5960 0008 7B68 ldr r3, [r7, #4] + 5961 000a 002B cmp r3, #0 + 5962 000c 01D1 bne .L482 +2002:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2003:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + ARM GAS /tmp/ccl4b9YO.s page 140 + + + 5963 .loc 1 2003 12 + 5964 000e 0123 movs r3, #1 + 5965 0010 49E0 b .L483 + 5966 .L482: +2004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2005:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2006:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +2007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_INSTANCE(htim->Instance)); +2008:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); +2009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); +2010:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); +2011:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); +2012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2013:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (htim->State == HAL_TIM_STATE_RESET) + 5967 .loc 1 2013 11 + 5968 0012 7B68 ldr r3, [r7, #4] + 5969 0014 93F83D30 ldrb r3, [r3, #61] + 5970 0018 DBB2 uxtb r3, r3 + 5971 .loc 1 2013 6 + 5972 001a 002B cmp r3, #0 + 5973 001c 06D1 bne .L484 +2014:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2015:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Allocate lock resource and initialize it */ +2016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Lock = HAL_UNLOCKED; + 5974 .loc 1 2016 16 + 5975 001e 7B68 ldr r3, [r7, #4] + 5976 0020 0022 movs r2, #0 + 5977 0022 83F83C20 strb r2, [r3, #60] +2017:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2018:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +2019:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Reset interrupt callbacks to legacy weak callbacks */ +2020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_ResetCallback(htim); +2021:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (htim->IC_MspInitCallback == NULL) +2023:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; +2025:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Init the low level hardware : GPIO, CLOCK, NVIC */ +2027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->IC_MspInitCallback(htim); +2028:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #else +2029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ +2030:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_IC_MspInit(htim); + 5978 .loc 1 2030 5 + 5979 0026 7868 ldr r0, [r7, #4] + 5980 0028 FFF7FEFF bl HAL_TIM_IC_MspInit + 5981 .L484: +2031:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +2032:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2033:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the TIM state */ +2035:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; + 5982 .loc 1 2035 15 + 5983 002c 7B68 ldr r3, [r7, #4] + 5984 002e 0222 movs r2, #2 + 5985 0030 83F83D20 strb r2, [r3, #61] +2036:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Init the base time for the input capture */ + ARM GAS /tmp/ccl4b9YO.s page 141 + + +2038:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_Base_SetConfig(htim->Instance, &htim->Init); + 5986 .loc 1 2038 3 + 5987 0034 7B68 ldr r3, [r7, #4] + 5988 0036 1A68 ldr r2, [r3] + 5989 .loc 1 2038 38 + 5990 0038 7B68 ldr r3, [r7, #4] + 5991 003a 0433 adds r3, r3, #4 + 5992 .loc 1 2038 3 + 5993 003c 1946 mov r1, r3 + 5994 003e 1046 mov r0, r2 + 5995 0040 FFF7FEFF bl TIM_Base_SetConfig +2039:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2040:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Initialize the DMA burst operation state */ +2041:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + 5996 .loc 1 2041 23 + 5997 0044 7B68 ldr r3, [r7, #4] + 5998 0046 0122 movs r2, #1 + 5999 0048 83F84820 strb r2, [r3, #72] +2042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2043:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Initialize the TIM channels state */ +2044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 6000 .loc 1 2044 3 + 6001 004c 7B68 ldr r3, [r7, #4] + 6002 004e 0122 movs r2, #1 + 6003 0050 83F83E20 strb r2, [r3, #62] + 6004 0054 7B68 ldr r3, [r7, #4] + 6005 0056 0122 movs r2, #1 + 6006 0058 83F83F20 strb r2, [r3, #63] + 6007 005c 7B68 ldr r3, [r7, #4] + 6008 005e 0122 movs r2, #1 + 6009 0060 83F84020 strb r2, [r3, #64] + 6010 0064 7B68 ldr r3, [r7, #4] + 6011 0066 0122 movs r2, #1 + 6012 0068 83F84120 strb r2, [r3, #65] + 6013 006c 7B68 ldr r3, [r7, #4] + 6014 006e 0122 movs r2, #1 + 6015 0070 83F84220 strb r2, [r3, #66] + 6016 0074 7B68 ldr r3, [r7, #4] + 6017 0076 0122 movs r2, #1 + 6018 0078 83F84320 strb r2, [r3, #67] +2045:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + 6019 .loc 1 2045 3 + 6020 007c 7B68 ldr r3, [r7, #4] + 6021 007e 0122 movs r2, #1 + 6022 0080 83F84420 strb r2, [r3, #68] + 6023 0084 7B68 ldr r3, [r7, #4] + 6024 0086 0122 movs r2, #1 + 6025 0088 83F84520 strb r2, [r3, #69] + 6026 008c 7B68 ldr r3, [r7, #4] + 6027 008e 0122 movs r2, #1 + 6028 0090 83F84620 strb r2, [r3, #70] + 6029 0094 7B68 ldr r3, [r7, #4] + 6030 0096 0122 movs r2, #1 + 6031 0098 83F84720 strb r2, [r3, #71] +2046:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Initialize the TIM state*/ +2048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; + ARM GAS /tmp/ccl4b9YO.s page 142 + + + 6032 .loc 1 2048 15 + 6033 009c 7B68 ldr r3, [r7, #4] + 6034 009e 0122 movs r2, #1 + 6035 00a0 83F83D20 strb r2, [r3, #61] +2049:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2050:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_OK; + 6036 .loc 1 2050 10 + 6037 00a4 0023 movs r3, #0 + 6038 .L483: +2051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 6039 .loc 1 2051 1 + 6040 00a6 1846 mov r0, r3 + 6041 00a8 0837 adds r7, r7, #8 + 6042 .cfi_def_cfa_offset 8 + 6043 00aa BD46 mov sp, r7 + 6044 .cfi_def_cfa_register 13 + 6045 @ sp needed + 6046 00ac 80BD pop {r7, pc} + 6047 .cfi_endproc + 6048 .LFE160: + 6050 .section .text.HAL_TIM_IC_DeInit,"ax",%progbits + 6051 .align 1 + 6052 .global HAL_TIM_IC_DeInit + 6053 .syntax unified + 6054 .thumb + 6055 .thumb_func + 6057 HAL_TIM_IC_DeInit: + 6058 .LFB161: +2052:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +2054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief DeInitializes the TIM peripheral +2055:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM Input Capture handle +2056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status +2057:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +2058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) +2059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 6059 .loc 1 2059 1 + 6060 .cfi_startproc + 6061 @ args = 0, pretend = 0, frame = 8 + 6062 @ frame_needed = 1, uses_anonymous_args = 0 + 6063 0000 80B5 push {r7, lr} + 6064 .cfi_def_cfa_offset 8 + 6065 .cfi_offset 7, -8 + 6066 .cfi_offset 14, -4 + 6067 0002 82B0 sub sp, sp, #8 + 6068 .cfi_def_cfa_offset 16 + 6069 0004 00AF add r7, sp, #0 + 6070 .cfi_def_cfa_register 7 + 6071 0006 7860 str r0, [r7, #4] +2060:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +2061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_INSTANCE(htim->Instance)); +2062:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2063:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; + 6072 .loc 1 2063 15 + 6073 0008 7B68 ldr r3, [r7, #4] + 6074 000a 0222 movs r2, #2 + 6075 000c 83F83D20 strb r2, [r3, #61] + ARM GAS /tmp/ccl4b9YO.s page 143 + + +2064:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the TIM Peripheral Clock */ +2066:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); + 6076 .loc 1 2066 3 + 6077 0010 7B68 ldr r3, [r7, #4] + 6078 0012 1B68 ldr r3, [r3] + 6079 0014 1A6A ldr r2, [r3, #32] + 6080 0016 41F21113 movw r3, #4369 + 6081 001a 1340 ands r3, r3, r2 + 6082 001c 002B cmp r3, #0 + 6083 001e 0FD1 bne .L486 + 6084 .loc 1 2066 3 is_stmt 0 discriminator 1 + 6085 0020 7B68 ldr r3, [r7, #4] + 6086 0022 1B68 ldr r3, [r3] + 6087 0024 1A6A ldr r2, [r3, #32] + 6088 0026 40F24443 movw r3, #1092 + 6089 002a 1340 ands r3, r3, r2 + 6090 002c 002B cmp r3, #0 + 6091 002e 07D1 bne .L486 + 6092 .loc 1 2066 3 discriminator 2 + 6093 0030 7B68 ldr r3, [r7, #4] + 6094 0032 1B68 ldr r3, [r3] + 6095 0034 1A68 ldr r2, [r3] + 6096 0036 7B68 ldr r3, [r7, #4] + 6097 0038 1B68 ldr r3, [r3] + 6098 003a 22F00102 bic r2, r2, #1 + 6099 003e 1A60 str r2, [r3] + 6100 .L486: +2067:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +2069:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (htim->IC_MspDeInitCallback == NULL) +2070:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; +2072:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2073:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* DeInit the low level hardware */ +2074:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->IC_MspDeInitCallback(htim); +2075:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #else +2076:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ +2077:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_IC_MspDeInit(htim); + 6101 .loc 1 2077 3 is_stmt 1 + 6102 0040 7868 ldr r0, [r7, #4] + 6103 0042 FFF7FEFF bl HAL_TIM_IC_MspDeInit +2078:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +2079:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Change the DMA burst operation state */ +2081:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + 6104 .loc 1 2081 23 + 6105 0046 7B68 ldr r3, [r7, #4] + 6106 0048 0022 movs r2, #0 + 6107 004a 83F84820 strb r2, [r3, #72] +2082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Change the TIM channels state */ +2084:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + 6108 .loc 1 2084 3 + 6109 004e 7B68 ldr r3, [r7, #4] + 6110 0050 0022 movs r2, #0 + 6111 0052 83F83E20 strb r2, [r3, #62] + ARM GAS /tmp/ccl4b9YO.s page 144 + + + 6112 0056 7B68 ldr r3, [r7, #4] + 6113 0058 0022 movs r2, #0 + 6114 005a 83F83F20 strb r2, [r3, #63] + 6115 005e 7B68 ldr r3, [r7, #4] + 6116 0060 0022 movs r2, #0 + 6117 0062 83F84020 strb r2, [r3, #64] + 6118 0066 7B68 ldr r3, [r7, #4] + 6119 0068 0022 movs r2, #0 + 6120 006a 83F84120 strb r2, [r3, #65] + 6121 006e 7B68 ldr r3, [r7, #4] + 6122 0070 0022 movs r2, #0 + 6123 0072 83F84220 strb r2, [r3, #66] + 6124 0076 7B68 ldr r3, [r7, #4] + 6125 0078 0022 movs r2, #0 + 6126 007a 83F84320 strb r2, [r3, #67] +2085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + 6127 .loc 1 2085 3 + 6128 007e 7B68 ldr r3, [r7, #4] + 6129 0080 0022 movs r2, #0 + 6130 0082 83F84420 strb r2, [r3, #68] + 6131 0086 7B68 ldr r3, [r7, #4] + 6132 0088 0022 movs r2, #0 + 6133 008a 83F84520 strb r2, [r3, #69] + 6134 008e 7B68 ldr r3, [r7, #4] + 6135 0090 0022 movs r2, #0 + 6136 0092 83F84620 strb r2, [r3, #70] + 6137 0096 7B68 ldr r3, [r7, #4] + 6138 0098 0022 movs r2, #0 + 6139 009a 83F84720 strb r2, [r3, #71] +2086:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2087:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Change TIM state */ +2088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->State = HAL_TIM_STATE_RESET; + 6140 .loc 1 2088 15 + 6141 009e 7B68 ldr r3, [r7, #4] + 6142 00a0 0022 movs r2, #0 + 6143 00a2 83F83D20 strb r2, [r3, #61] +2089:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2090:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Release Lock */ +2091:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_UNLOCK(htim); + 6144 .loc 1 2091 3 + 6145 00a6 7B68 ldr r3, [r7, #4] + 6146 00a8 0022 movs r2, #0 + 6147 00aa 83F83C20 strb r2, [r3, #60] +2092:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2093:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_OK; + 6148 .loc 1 2093 10 + 6149 00ae 0023 movs r3, #0 +2094:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 6150 .loc 1 2094 1 + 6151 00b0 1846 mov r0, r3 + 6152 00b2 0837 adds r7, r7, #8 + 6153 .cfi_def_cfa_offset 8 + 6154 00b4 BD46 mov sp, r7 + 6155 .cfi_def_cfa_register 13 + 6156 @ sp needed + 6157 00b6 80BD pop {r7, pc} + 6158 .cfi_endproc + ARM GAS /tmp/ccl4b9YO.s page 145 + + + 6159 .LFE161: + 6161 .section .text.HAL_TIM_IC_MspInit,"ax",%progbits + 6162 .align 1 + 6163 .weak HAL_TIM_IC_MspInit + 6164 .syntax unified + 6165 .thumb + 6166 .thumb_func + 6168 HAL_TIM_IC_MspInit: + 6169 .LFB162: +2095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2096:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +2097:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Initializes the TIM Input Capture MSP. +2098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM Input Capture handle +2099:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval None +2100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +2101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) +2102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 6170 .loc 1 2102 1 + 6171 .cfi_startproc + 6172 @ args = 0, pretend = 0, frame = 8 + 6173 @ frame_needed = 1, uses_anonymous_args = 0 + 6174 @ link register save eliminated. + 6175 0000 80B4 push {r7} + 6176 .cfi_def_cfa_offset 4 + 6177 .cfi_offset 7, -4 + 6178 0002 83B0 sub sp, sp, #12 + 6179 .cfi_def_cfa_offset 16 + 6180 0004 00AF add r7, sp, #0 + 6181 .cfi_def_cfa_register 7 + 6182 0006 7860 str r0, [r7, #4] +2103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +2104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** UNUSED(htim); +2105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* NOTE : This function should not be modified, when the callback is needed, +2107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** the HAL_TIM_IC_MspInit could be implemented in the user file +2108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +2109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 6183 .loc 1 2109 1 + 6184 0008 00BF nop + 6185 000a 0C37 adds r7, r7, #12 + 6186 .cfi_def_cfa_offset 4 + 6187 000c BD46 mov sp, r7 + 6188 .cfi_def_cfa_register 13 + 6189 @ sp needed + 6190 000e 5DF8047B ldr r7, [sp], #4 + 6191 .cfi_restore 7 + 6192 .cfi_def_cfa_offset 0 + 6193 0012 7047 bx lr + 6194 .cfi_endproc + 6195 .LFE162: + 6197 .section .text.HAL_TIM_IC_MspDeInit,"ax",%progbits + 6198 .align 1 + 6199 .weak HAL_TIM_IC_MspDeInit + 6200 .syntax unified + 6201 .thumb + 6202 .thumb_func + 6204 HAL_TIM_IC_MspDeInit: + ARM GAS /tmp/ccl4b9YO.s page 146 + + + 6205 .LFB163: +2110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +2112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief DeInitializes TIM Input Capture MSP. +2113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM handle +2114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval None +2115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +2116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) +2117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 6206 .loc 1 2117 1 + 6207 .cfi_startproc + 6208 @ args = 0, pretend = 0, frame = 8 + 6209 @ frame_needed = 1, uses_anonymous_args = 0 + 6210 @ link register save eliminated. + 6211 0000 80B4 push {r7} + 6212 .cfi_def_cfa_offset 4 + 6213 .cfi_offset 7, -4 + 6214 0002 83B0 sub sp, sp, #12 + 6215 .cfi_def_cfa_offset 16 + 6216 0004 00AF add r7, sp, #0 + 6217 .cfi_def_cfa_register 7 + 6218 0006 7860 str r0, [r7, #4] +2118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +2119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** UNUSED(htim); +2120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* NOTE : This function should not be modified, when the callback is needed, +2122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** the HAL_TIM_IC_MspDeInit could be implemented in the user file +2123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +2124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 6219 .loc 1 2124 1 + 6220 0008 00BF nop + 6221 000a 0C37 adds r7, r7, #12 + 6222 .cfi_def_cfa_offset 4 + 6223 000c BD46 mov sp, r7 + 6224 .cfi_def_cfa_register 13 + 6225 @ sp needed + 6226 000e 5DF8047B ldr r7, [sp], #4 + 6227 .cfi_restore 7 + 6228 .cfi_def_cfa_offset 0 + 6229 0012 7047 bx lr + 6230 .cfi_endproc + 6231 .LFE163: + 6233 .section .text.HAL_TIM_IC_Start,"ax",%progbits + 6234 .align 1 + 6235 .global HAL_TIM_IC_Start + 6236 .syntax unified + 6237 .thumb + 6238 .thumb_func + 6240 HAL_TIM_IC_Start: + 6241 .LFB164: +2125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +2127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Starts the TIM Input Capture measurement. +2128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM Input Capture handle +2129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param Channel TIM Channels to be enabled +2130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +2131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected + ARM GAS /tmp/ccl4b9YO.s page 147 + + +2132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +2133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +2134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +2135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status +2136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +2137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +2138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 6242 .loc 1 2138 1 + 6243 .cfi_startproc + 6244 @ args = 0, pretend = 0, frame = 16 + 6245 @ frame_needed = 1, uses_anonymous_args = 0 + 6246 0000 80B5 push {r7, lr} + 6247 .cfi_def_cfa_offset 8 + 6248 .cfi_offset 7, -8 + 6249 .cfi_offset 14, -4 + 6250 0002 84B0 sub sp, sp, #16 + 6251 .cfi_def_cfa_offset 24 + 6252 0004 00AF add r7, sp, #0 + 6253 .cfi_def_cfa_register 7 + 6254 0006 7860 str r0, [r7, #4] + 6255 0008 3960 str r1, [r7] +2139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpsmcr; +2140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + 6256 .loc 1 2140 47 + 6257 000a 3B68 ldr r3, [r7] + 6258 000c 002B cmp r3, #0 + 6259 000e 04D1 bne .L491 + 6260 .loc 1 2140 47 is_stmt 0 discriminator 1 + 6261 0010 7B68 ldr r3, [r7, #4] + 6262 0012 93F83E30 ldrb r3, [r3, #62] + 6263 0016 DBB2 uxtb r3, r3 + 6264 0018 23E0 b .L492 + 6265 .L491: + 6266 .loc 1 2140 47 discriminator 2 + 6267 001a 3B68 ldr r3, [r7] + 6268 001c 042B cmp r3, #4 + 6269 001e 04D1 bne .L493 + 6270 .loc 1 2140 47 discriminator 4 + 6271 0020 7B68 ldr r3, [r7, #4] + 6272 0022 93F83F30 ldrb r3, [r3, #63] + 6273 0026 DBB2 uxtb r3, r3 + 6274 0028 1BE0 b .L492 + 6275 .L493: + 6276 .loc 1 2140 47 discriminator 5 + 6277 002a 3B68 ldr r3, [r7] + 6278 002c 082B cmp r3, #8 + 6279 002e 04D1 bne .L495 + 6280 .loc 1 2140 47 discriminator 7 + 6281 0030 7B68 ldr r3, [r7, #4] + 6282 0032 93F84030 ldrb r3, [r3, #64] + 6283 0036 DBB2 uxtb r3, r3 + 6284 0038 13E0 b .L492 + 6285 .L495: + 6286 .loc 1 2140 47 discriminator 8 + 6287 003a 3B68 ldr r3, [r7] + 6288 003c 0C2B cmp r3, #12 + 6289 003e 04D1 bne .L497 + ARM GAS /tmp/ccl4b9YO.s page 148 + + + 6290 .loc 1 2140 47 discriminator 10 + 6291 0040 7B68 ldr r3, [r7, #4] + 6292 0042 93F84130 ldrb r3, [r3, #65] + 6293 0046 DBB2 uxtb r3, r3 + 6294 0048 0BE0 b .L492 + 6295 .L497: + 6296 .loc 1 2140 47 discriminator 11 + 6297 004a 3B68 ldr r3, [r7] + 6298 004c 102B cmp r3, #16 + 6299 004e 04D1 bne .L499 + 6300 .loc 1 2140 47 discriminator 13 + 6301 0050 7B68 ldr r3, [r7, #4] + 6302 0052 93F84230 ldrb r3, [r3, #66] + 6303 0056 DBB2 uxtb r3, r3 + 6304 0058 03E0 b .L492 + 6305 .L499: + 6306 .loc 1 2140 47 discriminator 14 + 6307 005a 7B68 ldr r3, [r7, #4] + 6308 005c 93F84330 ldrb r3, [r3, #67] + 6309 0060 DBB2 uxtb r3, r3 + 6310 .L492: + 6311 .loc 1 2140 31 is_stmt 1 discriminator 20 + 6312 0062 FB73 strb r3, [r7, #15] +2141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + 6313 .loc 1 2141 61 + 6314 0064 3B68 ldr r3, [r7] + 6315 0066 002B cmp r3, #0 + 6316 0068 04D1 bne .L501 + 6317 .loc 1 2141 61 is_stmt 0 discriminator 1 + 6318 006a 7B68 ldr r3, [r7, #4] + 6319 006c 93F84430 ldrb r3, [r3, #68] + 6320 0070 DBB2 uxtb r3, r3 + 6321 0072 13E0 b .L502 + 6322 .L501: + 6323 .loc 1 2141 61 discriminator 2 + 6324 0074 3B68 ldr r3, [r7] + 6325 0076 042B cmp r3, #4 + 6326 0078 04D1 bne .L503 + 6327 .loc 1 2141 61 discriminator 4 + 6328 007a 7B68 ldr r3, [r7, #4] + 6329 007c 93F84530 ldrb r3, [r3, #69] + 6330 0080 DBB2 uxtb r3, r3 + 6331 0082 0BE0 b .L502 + 6332 .L503: + 6333 .loc 1 2141 61 discriminator 5 + 6334 0084 3B68 ldr r3, [r7] + 6335 0086 082B cmp r3, #8 + 6336 0088 04D1 bne .L505 + 6337 .loc 1 2141 61 discriminator 7 + 6338 008a 7B68 ldr r3, [r7, #4] + 6339 008c 93F84630 ldrb r3, [r3, #70] + 6340 0090 DBB2 uxtb r3, r3 + 6341 0092 03E0 b .L502 + 6342 .L505: + 6343 .loc 1 2141 61 discriminator 8 + 6344 0094 7B68 ldr r3, [r7, #4] + 6345 0096 93F84730 ldrb r3, [r3, #71] + ARM GAS /tmp/ccl4b9YO.s page 149 + + + 6346 009a DBB2 uxtb r3, r3 + 6347 .L502: + 6348 .loc 1 2141 31 is_stmt 1 discriminator 12 + 6349 009c BB73 strb r3, [r7, #14] +2142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +2144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); +2145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the TIM channel state */ +2147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) + 6350 .loc 1 2147 6 + 6351 009e FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 6352 00a0 012B cmp r3, #1 + 6353 00a2 02D1 bne .L507 +2148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + 6354 .loc 1 2148 7 + 6355 00a4 BB7B ldrb r3, [r7, #14] @ zero_extendqisi2 + 6356 00a6 012B cmp r3, #1 + 6357 00a8 01D0 beq .L508 + 6358 .L507: +2149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 6359 .loc 1 2150 12 + 6360 00aa 0123 movs r3, #1 + 6361 00ac 88E0 b .L509 + 6362 .L508: +2151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the TIM channel state */ +2154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + 6363 .loc 1 2154 3 + 6364 00ae 3B68 ldr r3, [r7] + 6365 00b0 002B cmp r3, #0 + 6366 00b2 04D1 bne .L510 + 6367 .loc 1 2154 3 is_stmt 0 discriminator 1 + 6368 00b4 7B68 ldr r3, [r7, #4] + 6369 00b6 0222 movs r2, #2 + 6370 00b8 83F83E20 strb r2, [r3, #62] + 6371 00bc 23E0 b .L511 + 6372 .L510: + 6373 .loc 1 2154 3 discriminator 2 + 6374 00be 3B68 ldr r3, [r7] + 6375 00c0 042B cmp r3, #4 + 6376 00c2 04D1 bne .L512 + 6377 .loc 1 2154 3 discriminator 3 + 6378 00c4 7B68 ldr r3, [r7, #4] + 6379 00c6 0222 movs r2, #2 + 6380 00c8 83F83F20 strb r2, [r3, #63] + 6381 00cc 1BE0 b .L511 + 6382 .L512: + 6383 .loc 1 2154 3 discriminator 4 + 6384 00ce 3B68 ldr r3, [r7] + 6385 00d0 082B cmp r3, #8 + 6386 00d2 04D1 bne .L514 + 6387 .loc 1 2154 3 discriminator 6 + 6388 00d4 7B68 ldr r3, [r7, #4] + 6389 00d6 0222 movs r2, #2 + ARM GAS /tmp/ccl4b9YO.s page 150 + + + 6390 00d8 83F84020 strb r2, [r3, #64] + 6391 00dc 13E0 b .L511 + 6392 .L514: + 6393 .loc 1 2154 3 discriminator 7 + 6394 00de 3B68 ldr r3, [r7] + 6395 00e0 0C2B cmp r3, #12 + 6396 00e2 04D1 bne .L516 + 6397 .loc 1 2154 3 discriminator 9 + 6398 00e4 7B68 ldr r3, [r7, #4] + 6399 00e6 0222 movs r2, #2 + 6400 00e8 83F84120 strb r2, [r3, #65] + 6401 00ec 0BE0 b .L511 + 6402 .L516: + 6403 .loc 1 2154 3 discriminator 10 + 6404 00ee 3B68 ldr r3, [r7] + 6405 00f0 102B cmp r3, #16 + 6406 00f2 04D1 bne .L518 + 6407 .loc 1 2154 3 discriminator 12 + 6408 00f4 7B68 ldr r3, [r7, #4] + 6409 00f6 0222 movs r2, #2 + 6410 00f8 83F84220 strb r2, [r3, #66] + 6411 00fc 03E0 b .L511 + 6412 .L518: + 6413 .loc 1 2154 3 discriminator 13 + 6414 00fe 7B68 ldr r3, [r7, #4] + 6415 0100 0222 movs r2, #2 + 6416 0102 83F84320 strb r2, [r3, #67] + 6417 .L511: +2155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + 6418 .loc 1 2155 3 is_stmt 1 + 6419 0106 3B68 ldr r3, [r7] + 6420 0108 002B cmp r3, #0 + 6421 010a 04D1 bne .L520 + 6422 .loc 1 2155 3 is_stmt 0 discriminator 1 + 6423 010c 7B68 ldr r3, [r7, #4] + 6424 010e 0222 movs r2, #2 + 6425 0110 83F84420 strb r2, [r3, #68] + 6426 0114 13E0 b .L521 + 6427 .L520: + 6428 .loc 1 2155 3 discriminator 2 + 6429 0116 3B68 ldr r3, [r7] + 6430 0118 042B cmp r3, #4 + 6431 011a 04D1 bne .L522 + 6432 .loc 1 2155 3 discriminator 3 + 6433 011c 7B68 ldr r3, [r7, #4] + 6434 011e 0222 movs r2, #2 + 6435 0120 83F84520 strb r2, [r3, #69] + 6436 0124 0BE0 b .L521 + 6437 .L522: + 6438 .loc 1 2155 3 discriminator 4 + 6439 0126 3B68 ldr r3, [r7] + 6440 0128 082B cmp r3, #8 + 6441 012a 04D1 bne .L524 + 6442 .loc 1 2155 3 discriminator 6 + 6443 012c 7B68 ldr r3, [r7, #4] + 6444 012e 0222 movs r2, #2 + 6445 0130 83F84620 strb r2, [r3, #70] + ARM GAS /tmp/ccl4b9YO.s page 151 + + + 6446 0134 03E0 b .L521 + 6447 .L524: + 6448 .loc 1 2155 3 discriminator 7 + 6449 0136 7B68 ldr r3, [r7, #4] + 6450 0138 0222 movs r2, #2 + 6451 013a 83F84720 strb r2, [r3, #71] + 6452 .L521: +2156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the Input Capture channel */ +2158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + 6453 .loc 1 2158 3 is_stmt 1 + 6454 013e 7B68 ldr r3, [r7, #4] + 6455 0140 1B68 ldr r3, [r3] + 6456 0142 0122 movs r2, #1 + 6457 0144 3968 ldr r1, [r7] + 6458 0146 1846 mov r0, r3 + 6459 0148 FFF7FEFF bl TIM_CCxChannelCmd +2159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger +2161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 6460 .loc 1 2161 7 + 6461 014c 7B68 ldr r3, [r7, #4] + 6462 014e 1B68 ldr r3, [r3] + 6463 .loc 1 2161 6 + 6464 0150 1D4A ldr r2, .L531 + 6465 0152 9342 cmp r3, r2 + 6466 0154 13D0 beq .L526 + 6467 .loc 1 2161 7 discriminator 1 + 6468 0156 7B68 ldr r3, [r7, #4] + 6469 0158 1B68 ldr r3, [r3] + 6470 015a B3F1804F cmp r3, #1073741824 + 6471 015e 0ED0 beq .L526 + 6472 .loc 1 2161 7 is_stmt 0 discriminator 2 + 6473 0160 7B68 ldr r3, [r7, #4] + 6474 0162 1B68 ldr r3, [r3] + 6475 0164 194A ldr r2, .L531+4 + 6476 0166 9342 cmp r3, r2 + 6477 0168 09D0 beq .L526 + 6478 .loc 1 2161 7 discriminator 3 + 6479 016a 7B68 ldr r3, [r7, #4] + 6480 016c 1B68 ldr r3, [r3] + 6481 016e 184A ldr r2, .L531+8 + 6482 0170 9342 cmp r3, r2 + 6483 0172 04D0 beq .L526 + 6484 .loc 1 2161 7 discriminator 4 + 6485 0174 7B68 ldr r3, [r7, #4] + 6486 0176 1B68 ldr r3, [r3] + 6487 0178 164A ldr r2, .L531+12 + 6488 017a 9342 cmp r3, r2 + 6489 017c 15D1 bne .L527 + 6490 .L526: +2162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + 6491 .loc 1 2163 19 is_stmt 1 + 6492 017e 7B68 ldr r3, [r7, #4] + 6493 0180 1B68 ldr r3, [r3] + 6494 .loc 1 2163 29 + ARM GAS /tmp/ccl4b9YO.s page 152 + + + 6495 0182 9A68 ldr r2, [r3, #8] + 6496 .loc 1 2163 13 + 6497 0184 144B ldr r3, .L531+16 + 6498 0186 1340 ands r3, r3, r2 + 6499 0188 BB60 str r3, [r7, #8] +2164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 6500 .loc 1 2164 8 + 6501 018a BB68 ldr r3, [r7, #8] + 6502 018c 062B cmp r3, #6 + 6503 018e 15D0 beq .L530 + 6504 .loc 1 2164 9 discriminator 1 + 6505 0190 BB68 ldr r3, [r7, #8] + 6506 0192 B3F5803F cmp r3, #65536 + 6507 0196 11D0 beq .L530 +2165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); + 6508 .loc 1 2166 7 + 6509 0198 7B68 ldr r3, [r7, #4] + 6510 019a 1B68 ldr r3, [r3] + 6511 019c 1A68 ldr r2, [r3] + 6512 019e 7B68 ldr r3, [r7, #4] + 6513 01a0 1B68 ldr r3, [r3] + 6514 01a2 42F00102 orr r2, r2, #1 + 6515 01a6 1A60 str r2, [r3] +2164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 6516 .loc 1 2164 8 + 6517 01a8 08E0 b .L530 + 6518 .L527: +2167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +2170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); + 6519 .loc 1 2171 5 + 6520 01aa 7B68 ldr r3, [r7, #4] + 6521 01ac 1B68 ldr r3, [r3] + 6522 01ae 1A68 ldr r2, [r3] + 6523 01b0 7B68 ldr r3, [r7, #4] + 6524 01b2 1B68 ldr r3, [r3] + 6525 01b4 42F00102 orr r2, r2, #1 + 6526 01b8 1A60 str r2, [r3] + 6527 01ba 00E0 b .L529 + 6528 .L530: +2164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 6529 .loc 1 2164 8 + 6530 01bc 00BF nop + 6531 .L529: +2172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return function status */ +2175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_OK; + 6532 .loc 1 2175 10 + 6533 01be 0023 movs r3, #0 + 6534 .L509: +2176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 6535 .loc 1 2176 1 + 6536 01c0 1846 mov r0, r3 + ARM GAS /tmp/ccl4b9YO.s page 153 + + + 6537 01c2 1037 adds r7, r7, #16 + 6538 .cfi_def_cfa_offset 8 + 6539 01c4 BD46 mov sp, r7 + 6540 .cfi_def_cfa_register 13 + 6541 @ sp needed + 6542 01c6 80BD pop {r7, pc} + 6543 .L532: + 6544 .align 2 + 6545 .L531: + 6546 01c8 002C0140 .word 1073818624 + 6547 01cc 00040040 .word 1073742848 + 6548 01d0 00080040 .word 1073743872 + 6549 01d4 00400140 .word 1073823744 + 6550 01d8 07000100 .word 65543 + 6551 .cfi_endproc + 6552 .LFE164: + 6554 .section .text.HAL_TIM_IC_Stop,"ax",%progbits + 6555 .align 1 + 6556 .global HAL_TIM_IC_Stop + 6557 .syntax unified + 6558 .thumb + 6559 .thumb_func + 6561 HAL_TIM_IC_Stop: + 6562 .LFB165: +2177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +2179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Stops the TIM Input Capture measurement. +2180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM Input Capture handle +2181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param Channel TIM Channels to be disabled +2182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +2183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +2184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +2185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +2186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +2187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status +2188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +2189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +2190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 6563 .loc 1 2190 1 + 6564 .cfi_startproc + 6565 @ args = 0, pretend = 0, frame = 8 + 6566 @ frame_needed = 1, uses_anonymous_args = 0 + 6567 0000 80B5 push {r7, lr} + 6568 .cfi_def_cfa_offset 8 + 6569 .cfi_offset 7, -8 + 6570 .cfi_offset 14, -4 + 6571 0002 82B0 sub sp, sp, #8 + 6572 .cfi_def_cfa_offset 16 + 6573 0004 00AF add r7, sp, #0 + 6574 .cfi_def_cfa_register 7 + 6575 0006 7860 str r0, [r7, #4] + 6576 0008 3960 str r1, [r7] +2191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +2192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); +2193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the Input Capture channel */ +2195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + ARM GAS /tmp/ccl4b9YO.s page 154 + + + 6577 .loc 1 2195 3 + 6578 000a 7B68 ldr r3, [r7, #4] + 6579 000c 1B68 ldr r3, [r3] + 6580 000e 0022 movs r2, #0 + 6581 0010 3968 ldr r1, [r7] + 6582 0012 1846 mov r0, r3 + 6583 0014 FFF7FEFF bl TIM_CCxChannelCmd +2196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the Peripheral */ +2198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); + 6584 .loc 1 2198 3 + 6585 0018 7B68 ldr r3, [r7, #4] + 6586 001a 1B68 ldr r3, [r3] + 6587 001c 1A6A ldr r2, [r3, #32] + 6588 001e 41F21113 movw r3, #4369 + 6589 0022 1340 ands r3, r3, r2 + 6590 0024 002B cmp r3, #0 + 6591 0026 0FD1 bne .L534 + 6592 .loc 1 2198 3 is_stmt 0 discriminator 1 + 6593 0028 7B68 ldr r3, [r7, #4] + 6594 002a 1B68 ldr r3, [r3] + 6595 002c 1A6A ldr r2, [r3, #32] + 6596 002e 40F24443 movw r3, #1092 + 6597 0032 1340 ands r3, r3, r2 + 6598 0034 002B cmp r3, #0 + 6599 0036 07D1 bne .L534 + 6600 .loc 1 2198 3 discriminator 2 + 6601 0038 7B68 ldr r3, [r7, #4] + 6602 003a 1B68 ldr r3, [r3] + 6603 003c 1A68 ldr r2, [r3] + 6604 003e 7B68 ldr r3, [r7, #4] + 6605 0040 1B68 ldr r3, [r3] + 6606 0042 22F00102 bic r2, r2, #1 + 6607 0046 1A60 str r2, [r3] + 6608 .L534: +2199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the TIM channel state */ +2201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 6609 .loc 1 2201 3 is_stmt 1 + 6610 0048 3B68 ldr r3, [r7] + 6611 004a 002B cmp r3, #0 + 6612 004c 04D1 bne .L535 + 6613 .loc 1 2201 3 is_stmt 0 discriminator 1 + 6614 004e 7B68 ldr r3, [r7, #4] + 6615 0050 0122 movs r2, #1 + 6616 0052 83F83E20 strb r2, [r3, #62] + 6617 0056 23E0 b .L536 + 6618 .L535: + 6619 .loc 1 2201 3 discriminator 2 + 6620 0058 3B68 ldr r3, [r7] + 6621 005a 042B cmp r3, #4 + 6622 005c 04D1 bne .L537 + 6623 .loc 1 2201 3 discriminator 3 + 6624 005e 7B68 ldr r3, [r7, #4] + 6625 0060 0122 movs r2, #1 + 6626 0062 83F83F20 strb r2, [r3, #63] + 6627 0066 1BE0 b .L536 + ARM GAS /tmp/ccl4b9YO.s page 155 + + + 6628 .L537: + 6629 .loc 1 2201 3 discriminator 4 + 6630 0068 3B68 ldr r3, [r7] + 6631 006a 082B cmp r3, #8 + 6632 006c 04D1 bne .L539 + 6633 .loc 1 2201 3 discriminator 6 + 6634 006e 7B68 ldr r3, [r7, #4] + 6635 0070 0122 movs r2, #1 + 6636 0072 83F84020 strb r2, [r3, #64] + 6637 0076 13E0 b .L536 + 6638 .L539: + 6639 .loc 1 2201 3 discriminator 7 + 6640 0078 3B68 ldr r3, [r7] + 6641 007a 0C2B cmp r3, #12 + 6642 007c 04D1 bne .L541 + 6643 .loc 1 2201 3 discriminator 9 + 6644 007e 7B68 ldr r3, [r7, #4] + 6645 0080 0122 movs r2, #1 + 6646 0082 83F84120 strb r2, [r3, #65] + 6647 0086 0BE0 b .L536 + 6648 .L541: + 6649 .loc 1 2201 3 discriminator 10 + 6650 0088 3B68 ldr r3, [r7] + 6651 008a 102B cmp r3, #16 + 6652 008c 04D1 bne .L543 + 6653 .loc 1 2201 3 discriminator 12 + 6654 008e 7B68 ldr r3, [r7, #4] + 6655 0090 0122 movs r2, #1 + 6656 0092 83F84220 strb r2, [r3, #66] + 6657 0096 03E0 b .L536 + 6658 .L543: + 6659 .loc 1 2201 3 discriminator 13 + 6660 0098 7B68 ldr r3, [r7, #4] + 6661 009a 0122 movs r2, #1 + 6662 009c 83F84320 strb r2, [r3, #67] + 6663 .L536: +2202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 6664 .loc 1 2202 3 is_stmt 1 + 6665 00a0 3B68 ldr r3, [r7] + 6666 00a2 002B cmp r3, #0 + 6667 00a4 04D1 bne .L545 + 6668 .loc 1 2202 3 is_stmt 0 discriminator 1 + 6669 00a6 7B68 ldr r3, [r7, #4] + 6670 00a8 0122 movs r2, #1 + 6671 00aa 83F84420 strb r2, [r3, #68] + 6672 00ae 13E0 b .L546 + 6673 .L545: + 6674 .loc 1 2202 3 discriminator 2 + 6675 00b0 3B68 ldr r3, [r7] + 6676 00b2 042B cmp r3, #4 + 6677 00b4 04D1 bne .L547 + 6678 .loc 1 2202 3 discriminator 3 + 6679 00b6 7B68 ldr r3, [r7, #4] + 6680 00b8 0122 movs r2, #1 + 6681 00ba 83F84520 strb r2, [r3, #69] + 6682 00be 0BE0 b .L546 + 6683 .L547: + ARM GAS /tmp/ccl4b9YO.s page 156 + + + 6684 .loc 1 2202 3 discriminator 4 + 6685 00c0 3B68 ldr r3, [r7] + 6686 00c2 082B cmp r3, #8 + 6687 00c4 04D1 bne .L549 + 6688 .loc 1 2202 3 discriminator 6 + 6689 00c6 7B68 ldr r3, [r7, #4] + 6690 00c8 0122 movs r2, #1 + 6691 00ca 83F84620 strb r2, [r3, #70] + 6692 00ce 03E0 b .L546 + 6693 .L549: + 6694 .loc 1 2202 3 discriminator 7 + 6695 00d0 7B68 ldr r3, [r7, #4] + 6696 00d2 0122 movs r2, #1 + 6697 00d4 83F84720 strb r2, [r3, #71] + 6698 .L546: +2203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return function status */ +2205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_OK; + 6699 .loc 1 2205 10 is_stmt 1 + 6700 00d8 0023 movs r3, #0 +2206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 6701 .loc 1 2206 1 + 6702 00da 1846 mov r0, r3 + 6703 00dc 0837 adds r7, r7, #8 + 6704 .cfi_def_cfa_offset 8 + 6705 00de BD46 mov sp, r7 + 6706 .cfi_def_cfa_register 13 + 6707 @ sp needed + 6708 00e0 80BD pop {r7, pc} + 6709 .cfi_endproc + 6710 .LFE165: + 6712 .section .text.HAL_TIM_IC_Start_IT,"ax",%progbits + 6713 .align 1 + 6714 .global HAL_TIM_IC_Start_IT + 6715 .syntax unified + 6716 .thumb + 6717 .thumb_func + 6719 HAL_TIM_IC_Start_IT: + 6720 .LFB166: +2207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +2209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Starts the TIM Input Capture measurement in interrupt mode. +2210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM Input Capture handle +2211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param Channel TIM Channels to be enabled +2212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +2213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +2214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +2215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +2216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +2217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status +2218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +2219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +2220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 6721 .loc 1 2220 1 + 6722 .cfi_startproc + 6723 @ args = 0, pretend = 0, frame = 16 + 6724 @ frame_needed = 1, uses_anonymous_args = 0 + ARM GAS /tmp/ccl4b9YO.s page 157 + + + 6725 0000 80B5 push {r7, lr} + 6726 .cfi_def_cfa_offset 8 + 6727 .cfi_offset 7, -8 + 6728 .cfi_offset 14, -4 + 6729 0002 84B0 sub sp, sp, #16 + 6730 .cfi_def_cfa_offset 24 + 6731 0004 00AF add r7, sp, #0 + 6732 .cfi_def_cfa_register 7 + 6733 0006 7860 str r0, [r7, #4] + 6734 0008 3960 str r1, [r7] +2221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 6735 .loc 1 2221 21 + 6736 000a 0023 movs r3, #0 + 6737 000c FB73 strb r3, [r7, #15] +2222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpsmcr; +2223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + 6738 .loc 1 2224 47 + 6739 000e 3B68 ldr r3, [r7] + 6740 0010 002B cmp r3, #0 + 6741 0012 04D1 bne .L553 + 6742 .loc 1 2224 47 is_stmt 0 discriminator 1 + 6743 0014 7B68 ldr r3, [r7, #4] + 6744 0016 93F83E30 ldrb r3, [r3, #62] + 6745 001a DBB2 uxtb r3, r3 + 6746 001c 23E0 b .L554 + 6747 .L553: + 6748 .loc 1 2224 47 discriminator 2 + 6749 001e 3B68 ldr r3, [r7] + 6750 0020 042B cmp r3, #4 + 6751 0022 04D1 bne .L555 + 6752 .loc 1 2224 47 discriminator 4 + 6753 0024 7B68 ldr r3, [r7, #4] + 6754 0026 93F83F30 ldrb r3, [r3, #63] + 6755 002a DBB2 uxtb r3, r3 + 6756 002c 1BE0 b .L554 + 6757 .L555: + 6758 .loc 1 2224 47 discriminator 5 + 6759 002e 3B68 ldr r3, [r7] + 6760 0030 082B cmp r3, #8 + 6761 0032 04D1 bne .L557 + 6762 .loc 1 2224 47 discriminator 7 + 6763 0034 7B68 ldr r3, [r7, #4] + 6764 0036 93F84030 ldrb r3, [r3, #64] + 6765 003a DBB2 uxtb r3, r3 + 6766 003c 13E0 b .L554 + 6767 .L557: + 6768 .loc 1 2224 47 discriminator 8 + 6769 003e 3B68 ldr r3, [r7] + 6770 0040 0C2B cmp r3, #12 + 6771 0042 04D1 bne .L559 + 6772 .loc 1 2224 47 discriminator 10 + 6773 0044 7B68 ldr r3, [r7, #4] + 6774 0046 93F84130 ldrb r3, [r3, #65] + 6775 004a DBB2 uxtb r3, r3 + 6776 004c 0BE0 b .L554 + 6777 .L559: + ARM GAS /tmp/ccl4b9YO.s page 158 + + + 6778 .loc 1 2224 47 discriminator 11 + 6779 004e 3B68 ldr r3, [r7] + 6780 0050 102B cmp r3, #16 + 6781 0052 04D1 bne .L561 + 6782 .loc 1 2224 47 discriminator 13 + 6783 0054 7B68 ldr r3, [r7, #4] + 6784 0056 93F84230 ldrb r3, [r3, #66] + 6785 005a DBB2 uxtb r3, r3 + 6786 005c 03E0 b .L554 + 6787 .L561: + 6788 .loc 1 2224 47 discriminator 14 + 6789 005e 7B68 ldr r3, [r7, #4] + 6790 0060 93F84330 ldrb r3, [r3, #67] + 6791 0064 DBB2 uxtb r3, r3 + 6792 .L554: + 6793 .loc 1 2224 31 is_stmt 1 discriminator 20 + 6794 0066 BB73 strb r3, [r7, #14] +2225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + 6795 .loc 1 2225 61 + 6796 0068 3B68 ldr r3, [r7] + 6797 006a 002B cmp r3, #0 + 6798 006c 04D1 bne .L563 + 6799 .loc 1 2225 61 is_stmt 0 discriminator 1 + 6800 006e 7B68 ldr r3, [r7, #4] + 6801 0070 93F84430 ldrb r3, [r3, #68] + 6802 0074 DBB2 uxtb r3, r3 + 6803 0076 13E0 b .L564 + 6804 .L563: + 6805 .loc 1 2225 61 discriminator 2 + 6806 0078 3B68 ldr r3, [r7] + 6807 007a 042B cmp r3, #4 + 6808 007c 04D1 bne .L565 + 6809 .loc 1 2225 61 discriminator 4 + 6810 007e 7B68 ldr r3, [r7, #4] + 6811 0080 93F84530 ldrb r3, [r3, #69] + 6812 0084 DBB2 uxtb r3, r3 + 6813 0086 0BE0 b .L564 + 6814 .L565: + 6815 .loc 1 2225 61 discriminator 5 + 6816 0088 3B68 ldr r3, [r7] + 6817 008a 082B cmp r3, #8 + 6818 008c 04D1 bne .L567 + 6819 .loc 1 2225 61 discriminator 7 + 6820 008e 7B68 ldr r3, [r7, #4] + 6821 0090 93F84630 ldrb r3, [r3, #70] + 6822 0094 DBB2 uxtb r3, r3 + 6823 0096 03E0 b .L564 + 6824 .L567: + 6825 .loc 1 2225 61 discriminator 8 + 6826 0098 7B68 ldr r3, [r7, #4] + 6827 009a 93F84730 ldrb r3, [r3, #71] + 6828 009e DBB2 uxtb r3, r3 + 6829 .L564: + 6830 .loc 1 2225 31 is_stmt 1 discriminator 12 + 6831 00a0 7B73 strb r3, [r7, #13] +2226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ + ARM GAS /tmp/ccl4b9YO.s page 159 + + +2228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); +2229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the TIM channel state */ +2231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) + 6832 .loc 1 2231 6 + 6833 00a2 BB7B ldrb r3, [r7, #14] @ zero_extendqisi2 + 6834 00a4 012B cmp r3, #1 + 6835 00a6 02D1 bne .L569 +2232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + 6836 .loc 1 2232 7 + 6837 00a8 7B7B ldrb r3, [r7, #13] @ zero_extendqisi2 + 6838 00aa 012B cmp r3, #1 + 6839 00ac 01D0 beq .L570 + 6840 .L569: +2233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 6841 .loc 1 2234 12 + 6842 00ae 0123 movs r3, #1 + 6843 00b0 D3E0 b .L571 + 6844 .L570: +2235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the TIM channel state */ +2238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + 6845 .loc 1 2238 3 + 6846 00b2 3B68 ldr r3, [r7] + 6847 00b4 002B cmp r3, #0 + 6848 00b6 04D1 bne .L572 + 6849 .loc 1 2238 3 is_stmt 0 discriminator 1 + 6850 00b8 7B68 ldr r3, [r7, #4] + 6851 00ba 0222 movs r2, #2 + 6852 00bc 83F83E20 strb r2, [r3, #62] + 6853 00c0 23E0 b .L573 + 6854 .L572: + 6855 .loc 1 2238 3 discriminator 2 + 6856 00c2 3B68 ldr r3, [r7] + 6857 00c4 042B cmp r3, #4 + 6858 00c6 04D1 bne .L574 + 6859 .loc 1 2238 3 discriminator 3 + 6860 00c8 7B68 ldr r3, [r7, #4] + 6861 00ca 0222 movs r2, #2 + 6862 00cc 83F83F20 strb r2, [r3, #63] + 6863 00d0 1BE0 b .L573 + 6864 .L574: + 6865 .loc 1 2238 3 discriminator 4 + 6866 00d2 3B68 ldr r3, [r7] + 6867 00d4 082B cmp r3, #8 + 6868 00d6 04D1 bne .L576 + 6869 .loc 1 2238 3 discriminator 6 + 6870 00d8 7B68 ldr r3, [r7, #4] + 6871 00da 0222 movs r2, #2 + 6872 00dc 83F84020 strb r2, [r3, #64] + 6873 00e0 13E0 b .L573 + 6874 .L576: + 6875 .loc 1 2238 3 discriminator 7 + 6876 00e2 3B68 ldr r3, [r7] + 6877 00e4 0C2B cmp r3, #12 + ARM GAS /tmp/ccl4b9YO.s page 160 + + + 6878 00e6 04D1 bne .L578 + 6879 .loc 1 2238 3 discriminator 9 + 6880 00e8 7B68 ldr r3, [r7, #4] + 6881 00ea 0222 movs r2, #2 + 6882 00ec 83F84120 strb r2, [r3, #65] + 6883 00f0 0BE0 b .L573 + 6884 .L578: + 6885 .loc 1 2238 3 discriminator 10 + 6886 00f2 3B68 ldr r3, [r7] + 6887 00f4 102B cmp r3, #16 + 6888 00f6 04D1 bne .L580 + 6889 .loc 1 2238 3 discriminator 12 + 6890 00f8 7B68 ldr r3, [r7, #4] + 6891 00fa 0222 movs r2, #2 + 6892 00fc 83F84220 strb r2, [r3, #66] + 6893 0100 03E0 b .L573 + 6894 .L580: + 6895 .loc 1 2238 3 discriminator 13 + 6896 0102 7B68 ldr r3, [r7, #4] + 6897 0104 0222 movs r2, #2 + 6898 0106 83F84320 strb r2, [r3, #67] + 6899 .L573: +2239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + 6900 .loc 1 2239 3 is_stmt 1 + 6901 010a 3B68 ldr r3, [r7] + 6902 010c 002B cmp r3, #0 + 6903 010e 04D1 bne .L582 + 6904 .loc 1 2239 3 is_stmt 0 discriminator 1 + 6905 0110 7B68 ldr r3, [r7, #4] + 6906 0112 0222 movs r2, #2 + 6907 0114 83F84420 strb r2, [r3, #68] + 6908 0118 13E0 b .L583 + 6909 .L582: + 6910 .loc 1 2239 3 discriminator 2 + 6911 011a 3B68 ldr r3, [r7] + 6912 011c 042B cmp r3, #4 + 6913 011e 04D1 bne .L584 + 6914 .loc 1 2239 3 discriminator 3 + 6915 0120 7B68 ldr r3, [r7, #4] + 6916 0122 0222 movs r2, #2 + 6917 0124 83F84520 strb r2, [r3, #69] + 6918 0128 0BE0 b .L583 + 6919 .L584: + 6920 .loc 1 2239 3 discriminator 4 + 6921 012a 3B68 ldr r3, [r7] + 6922 012c 082B cmp r3, #8 + 6923 012e 04D1 bne .L586 + 6924 .loc 1 2239 3 discriminator 6 + 6925 0130 7B68 ldr r3, [r7, #4] + 6926 0132 0222 movs r2, #2 + 6927 0134 83F84620 strb r2, [r3, #70] + 6928 0138 03E0 b .L583 + 6929 .L586: + 6930 .loc 1 2239 3 discriminator 7 + 6931 013a 7B68 ldr r3, [r7, #4] + 6932 013c 0222 movs r2, #2 + 6933 013e 83F84720 strb r2, [r3, #71] + ARM GAS /tmp/ccl4b9YO.s page 161 + + + 6934 .L583: +2240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** switch (Channel) + 6935 .loc 1 2241 3 is_stmt 1 + 6936 0142 3B68 ldr r3, [r7] + 6937 0144 0C2B cmp r3, #12 + 6938 0146 41D8 bhi .L588 + 6939 0148 01A2 adr r2, .L590 + 6940 014a 52F823F0 ldr pc, [r2, r3, lsl #2] + 6941 014e 00BF .p2align 2 + 6942 .L590: + 6943 0150 85010000 .word .L593+1 + 6944 0154 CD010000 .word .L588+1 + 6945 0158 CD010000 .word .L588+1 + 6946 015c CD010000 .word .L588+1 + 6947 0160 97010000 .word .L592+1 + 6948 0164 CD010000 .word .L588+1 + 6949 0168 CD010000 .word .L588+1 + 6950 016c CD010000 .word .L588+1 + 6951 0170 A9010000 .word .L591+1 + 6952 0174 CD010000 .word .L588+1 + 6953 0178 CD010000 .word .L588+1 + 6954 017c CD010000 .word .L588+1 + 6955 0180 BB010000 .word .L589+1 + 6956 .p2align 1 + 6957 .L593: +2242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_1: +2244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the TIM Capture/Compare 1 interrupt */ +2246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + 6958 .loc 1 2246 7 + 6959 0184 7B68 ldr r3, [r7, #4] + 6960 0186 1B68 ldr r3, [r3] + 6961 0188 DA68 ldr r2, [r3, #12] + 6962 018a 7B68 ldr r3, [r7, #4] + 6963 018c 1B68 ldr r3, [r3] + 6964 018e 42F00202 orr r2, r2, #2 + 6965 0192 DA60 str r2, [r3, #12] +2247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 6966 .loc 1 2247 7 + 6967 0194 1DE0 b .L594 + 6968 .L592: +2248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_2: +2251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the TIM Capture/Compare 2 interrupt */ +2253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + 6969 .loc 1 2253 7 + 6970 0196 7B68 ldr r3, [r7, #4] + 6971 0198 1B68 ldr r3, [r3] + 6972 019a DA68 ldr r2, [r3, #12] + 6973 019c 7B68 ldr r3, [r7, #4] + 6974 019e 1B68 ldr r3, [r3] + 6975 01a0 42F00402 orr r2, r2, #4 + 6976 01a4 DA60 str r2, [r3, #12] + ARM GAS /tmp/ccl4b9YO.s page 162 + + +2254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 6977 .loc 1 2254 7 + 6978 01a6 14E0 b .L594 + 6979 .L591: +2255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_3: +2258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the TIM Capture/Compare 3 interrupt */ +2260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + 6980 .loc 1 2260 7 + 6981 01a8 7B68 ldr r3, [r7, #4] + 6982 01aa 1B68 ldr r3, [r3] + 6983 01ac DA68 ldr r2, [r3, #12] + 6984 01ae 7B68 ldr r3, [r7, #4] + 6985 01b0 1B68 ldr r3, [r3] + 6986 01b2 42F00802 orr r2, r2, #8 + 6987 01b6 DA60 str r2, [r3, #12] +2261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 6988 .loc 1 2261 7 + 6989 01b8 0BE0 b .L594 + 6990 .L589: +2262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_4: +2265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the TIM Capture/Compare 4 interrupt */ +2267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + 6991 .loc 1 2267 7 + 6992 01ba 7B68 ldr r3, [r7, #4] + 6993 01bc 1B68 ldr r3, [r3] + 6994 01be DA68 ldr r2, [r3, #12] + 6995 01c0 7B68 ldr r3, [r7, #4] + 6996 01c2 1B68 ldr r3, [r3] + 6997 01c4 42F01002 orr r2, r2, #16 + 6998 01c8 DA60 str r2, [r3, #12] +2268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 6999 .loc 1 2268 7 + 7000 01ca 02E0 b .L594 + 7001 .L588: +2269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** default: +2272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** status = HAL_ERROR; + 7002 .loc 1 2272 14 + 7003 01cc 0123 movs r3, #1 + 7004 01ce FB73 strb r3, [r7, #15] +2273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 7005 .loc 1 2273 7 + 7006 01d0 00BF nop + 7007 .L594: +2274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (status == HAL_OK) + 7008 .loc 1 2276 6 + 7009 01d2 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 7010 01d4 002B cmp r3, #0 + ARM GAS /tmp/ccl4b9YO.s page 163 + + + 7011 01d6 3FD1 bne .L595 +2277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the Input Capture channel */ +2279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + 7012 .loc 1 2279 5 + 7013 01d8 7B68 ldr r3, [r7, #4] + 7014 01da 1B68 ldr r3, [r3] + 7015 01dc 0122 movs r2, #1 + 7016 01de 3968 ldr r1, [r7] + 7017 01e0 1846 mov r0, r3 + 7018 01e2 FFF7FEFF bl TIM_CCxChannelCmd +2280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigge +2282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 7019 .loc 1 2282 9 + 7020 01e6 7B68 ldr r3, [r7, #4] + 7021 01e8 1B68 ldr r3, [r3] + 7022 .loc 1 2282 8 + 7023 01ea 1E4A ldr r2, .L600 + 7024 01ec 9342 cmp r3, r2 + 7025 01ee 13D0 beq .L596 + 7026 .loc 1 2282 9 discriminator 1 + 7027 01f0 7B68 ldr r3, [r7, #4] + 7028 01f2 1B68 ldr r3, [r3] + 7029 01f4 B3F1804F cmp r3, #1073741824 + 7030 01f8 0ED0 beq .L596 + 7031 .loc 1 2282 9 is_stmt 0 discriminator 2 + 7032 01fa 7B68 ldr r3, [r7, #4] + 7033 01fc 1B68 ldr r3, [r3] + 7034 01fe 1A4A ldr r2, .L600+4 + 7035 0200 9342 cmp r3, r2 + 7036 0202 09D0 beq .L596 + 7037 .loc 1 2282 9 discriminator 3 + 7038 0204 7B68 ldr r3, [r7, #4] + 7039 0206 1B68 ldr r3, [r3] + 7040 0208 184A ldr r2, .L600+8 + 7041 020a 9342 cmp r3, r2 + 7042 020c 04D0 beq .L596 + 7043 .loc 1 2282 9 discriminator 4 + 7044 020e 7B68 ldr r3, [r7, #4] + 7045 0210 1B68 ldr r3, [r3] + 7046 0212 174A ldr r2, .L600+12 + 7047 0214 9342 cmp r3, r2 + 7048 0216 15D1 bne .L597 + 7049 .L596: +2283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + 7050 .loc 1 2284 21 is_stmt 1 + 7051 0218 7B68 ldr r3, [r7, #4] + 7052 021a 1B68 ldr r3, [r3] + 7053 .loc 1 2284 31 + 7054 021c 9A68 ldr r2, [r3, #8] + 7055 .loc 1 2284 15 + 7056 021e 154B ldr r3, .L600+16 + 7057 0220 1340 ands r3, r3, r2 + 7058 0222 BB60 str r3, [r7, #8] +2285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + ARM GAS /tmp/ccl4b9YO.s page 164 + + + 7059 .loc 1 2285 10 + 7060 0224 BB68 ldr r3, [r7, #8] + 7061 0226 062B cmp r3, #6 + 7062 0228 15D0 beq .L599 + 7063 .loc 1 2285 11 discriminator 1 + 7064 022a BB68 ldr r3, [r7, #8] + 7065 022c B3F5803F cmp r3, #65536 + 7066 0230 11D0 beq .L599 +2286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); + 7067 .loc 1 2287 9 + 7068 0232 7B68 ldr r3, [r7, #4] + 7069 0234 1B68 ldr r3, [r3] + 7070 0236 1A68 ldr r2, [r3] + 7071 0238 7B68 ldr r3, [r7, #4] + 7072 023a 1B68 ldr r3, [r3] + 7073 023c 42F00102 orr r2, r2, #1 + 7074 0240 1A60 str r2, [r3] +2285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 7075 .loc 1 2285 10 + 7076 0242 08E0 b .L599 + 7077 .L597: +2288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +2291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); + 7078 .loc 1 2292 7 + 7079 0244 7B68 ldr r3, [r7, #4] + 7080 0246 1B68 ldr r3, [r3] + 7081 0248 1A68 ldr r2, [r3] + 7082 024a 7B68 ldr r3, [r7, #4] + 7083 024c 1B68 ldr r3, [r3] + 7084 024e 42F00102 orr r2, r2, #1 + 7085 0252 1A60 str r2, [r3] + 7086 0254 00E0 b .L595 + 7087 .L599: +2285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 7088 .loc 1 2285 10 + 7089 0256 00BF nop + 7090 .L595: +2293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return function status */ +2297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return status; + 7091 .loc 1 2297 10 + 7092 0258 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 7093 .L571: +2298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 7094 .loc 1 2298 1 + 7095 025a 1846 mov r0, r3 + 7096 025c 1037 adds r7, r7, #16 + 7097 .cfi_def_cfa_offset 8 + 7098 025e BD46 mov sp, r7 + 7099 .cfi_def_cfa_register 13 + 7100 @ sp needed + ARM GAS /tmp/ccl4b9YO.s page 165 + + + 7101 0260 80BD pop {r7, pc} + 7102 .L601: + 7103 0262 00BF .align 2 + 7104 .L600: + 7105 0264 002C0140 .word 1073818624 + 7106 0268 00040040 .word 1073742848 + 7107 026c 00080040 .word 1073743872 + 7108 0270 00400140 .word 1073823744 + 7109 0274 07000100 .word 65543 + 7110 .cfi_endproc + 7111 .LFE166: + 7113 .section .text.HAL_TIM_IC_Stop_IT,"ax",%progbits + 7114 .align 1 + 7115 .global HAL_TIM_IC_Stop_IT + 7116 .syntax unified + 7117 .thumb + 7118 .thumb_func + 7120 HAL_TIM_IC_Stop_IT: + 7121 .LFB167: +2299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +2301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Stops the TIM Input Capture measurement in interrupt mode. +2302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM Input Capture handle +2303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param Channel TIM Channels to be disabled +2304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +2305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +2306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +2307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +2308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +2309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status +2310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +2311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +2312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 7122 .loc 1 2312 1 + 7123 .cfi_startproc + 7124 @ args = 0, pretend = 0, frame = 16 + 7125 @ frame_needed = 1, uses_anonymous_args = 0 + 7126 0000 80B5 push {r7, lr} + 7127 .cfi_def_cfa_offset 8 + 7128 .cfi_offset 7, -8 + 7129 .cfi_offset 14, -4 + 7130 0002 84B0 sub sp, sp, #16 + 7131 .cfi_def_cfa_offset 24 + 7132 0004 00AF add r7, sp, #0 + 7133 .cfi_def_cfa_register 7 + 7134 0006 7860 str r0, [r7, #4] + 7135 0008 3960 str r1, [r7] +2313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 7136 .loc 1 2313 21 + 7137 000a 0023 movs r3, #0 + 7138 000c FB73 strb r3, [r7, #15] +2314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +2316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); +2317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** switch (Channel) + 7139 .loc 1 2318 3 + ARM GAS /tmp/ccl4b9YO.s page 166 + + + 7140 000e 3B68 ldr r3, [r7] + 7141 0010 0C2B cmp r3, #12 + 7142 0012 41D8 bhi .L603 + 7143 0014 01A2 adr r2, .L605 + 7144 0016 52F823F0 ldr pc, [r2, r3, lsl #2] + 7145 001a 00BF .p2align 2 + 7146 .L605: + 7147 001c 51000000 .word .L608+1 + 7148 0020 99000000 .word .L603+1 + 7149 0024 99000000 .word .L603+1 + 7150 0028 99000000 .word .L603+1 + 7151 002c 63000000 .word .L607+1 + 7152 0030 99000000 .word .L603+1 + 7153 0034 99000000 .word .L603+1 + 7154 0038 99000000 .word .L603+1 + 7155 003c 75000000 .word .L606+1 + 7156 0040 99000000 .word .L603+1 + 7157 0044 99000000 .word .L603+1 + 7158 0048 99000000 .word .L603+1 + 7159 004c 87000000 .word .L604+1 + 7160 .p2align 1 + 7161 .L608: +2319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_1: +2321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the TIM Capture/Compare 1 interrupt */ +2323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + 7162 .loc 1 2323 7 + 7163 0050 7B68 ldr r3, [r7, #4] + 7164 0052 1B68 ldr r3, [r3] + 7165 0054 DA68 ldr r2, [r3, #12] + 7166 0056 7B68 ldr r3, [r7, #4] + 7167 0058 1B68 ldr r3, [r3] + 7168 005a 22F00202 bic r2, r2, #2 + 7169 005e DA60 str r2, [r3, #12] +2324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 7170 .loc 1 2324 7 + 7171 0060 1DE0 b .L609 + 7172 .L607: +2325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_2: +2328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the TIM Capture/Compare 2 interrupt */ +2330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + 7173 .loc 1 2330 7 + 7174 0062 7B68 ldr r3, [r7, #4] + 7175 0064 1B68 ldr r3, [r3] + 7176 0066 DA68 ldr r2, [r3, #12] + 7177 0068 7B68 ldr r3, [r7, #4] + 7178 006a 1B68 ldr r3, [r3] + 7179 006c 22F00402 bic r2, r2, #4 + 7180 0070 DA60 str r2, [r3, #12] +2331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 7181 .loc 1 2331 7 + 7182 0072 14E0 b .L609 + 7183 .L606: + ARM GAS /tmp/ccl4b9YO.s page 167 + + +2332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_3: +2335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the TIM Capture/Compare 3 interrupt */ +2337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + 7184 .loc 1 2337 7 + 7185 0074 7B68 ldr r3, [r7, #4] + 7186 0076 1B68 ldr r3, [r3] + 7187 0078 DA68 ldr r2, [r3, #12] + 7188 007a 7B68 ldr r3, [r7, #4] + 7189 007c 1B68 ldr r3, [r3] + 7190 007e 22F00802 bic r2, r2, #8 + 7191 0082 DA60 str r2, [r3, #12] +2338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 7192 .loc 1 2338 7 + 7193 0084 0BE0 b .L609 + 7194 .L604: +2339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_4: +2342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the TIM Capture/Compare 4 interrupt */ +2344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + 7195 .loc 1 2344 7 + 7196 0086 7B68 ldr r3, [r7, #4] + 7197 0088 1B68 ldr r3, [r3] + 7198 008a DA68 ldr r2, [r3, #12] + 7199 008c 7B68 ldr r3, [r7, #4] + 7200 008e 1B68 ldr r3, [r3] + 7201 0090 22F01002 bic r2, r2, #16 + 7202 0094 DA60 str r2, [r3, #12] +2345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 7203 .loc 1 2345 7 + 7204 0096 02E0 b .L609 + 7205 .L603: +2346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** default: +2349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** status = HAL_ERROR; + 7206 .loc 1 2349 14 + 7207 0098 0123 movs r3, #1 + 7208 009a FB73 strb r3, [r7, #15] +2350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 7209 .loc 1 2350 7 + 7210 009c 00BF nop + 7211 .L609: +2351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (status == HAL_OK) + 7212 .loc 1 2353 6 + 7213 009e FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 7214 00a0 002B cmp r3, #0 + 7215 00a2 66D1 bne .L610 +2354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the Input Capture channel */ +2356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + ARM GAS /tmp/ccl4b9YO.s page 168 + + + 7216 .loc 1 2356 5 + 7217 00a4 7B68 ldr r3, [r7, #4] + 7218 00a6 1B68 ldr r3, [r3] + 7219 00a8 0022 movs r2, #0 + 7220 00aa 3968 ldr r1, [r7] + 7221 00ac 1846 mov r0, r3 + 7222 00ae FFF7FEFF bl TIM_CCxChannelCmd +2357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the Peripheral */ +2359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); + 7223 .loc 1 2359 5 + 7224 00b2 7B68 ldr r3, [r7, #4] + 7225 00b4 1B68 ldr r3, [r3] + 7226 00b6 1A6A ldr r2, [r3, #32] + 7227 00b8 41F21113 movw r3, #4369 + 7228 00bc 1340 ands r3, r3, r2 + 7229 00be 002B cmp r3, #0 + 7230 00c0 0FD1 bne .L611 + 7231 .loc 1 2359 5 is_stmt 0 discriminator 1 + 7232 00c2 7B68 ldr r3, [r7, #4] + 7233 00c4 1B68 ldr r3, [r3] + 7234 00c6 1A6A ldr r2, [r3, #32] + 7235 00c8 40F24443 movw r3, #1092 + 7236 00cc 1340 ands r3, r3, r2 + 7237 00ce 002B cmp r3, #0 + 7238 00d0 07D1 bne .L611 + 7239 .loc 1 2359 5 discriminator 2 + 7240 00d2 7B68 ldr r3, [r7, #4] + 7241 00d4 1B68 ldr r3, [r3] + 7242 00d6 1A68 ldr r2, [r3] + 7243 00d8 7B68 ldr r3, [r7, #4] + 7244 00da 1B68 ldr r3, [r3] + 7245 00dc 22F00102 bic r2, r2, #1 + 7246 00e0 1A60 str r2, [r3] + 7247 .L611: +2360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the TIM channel state */ +2362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 7248 .loc 1 2362 5 is_stmt 1 + 7249 00e2 3B68 ldr r3, [r7] + 7250 00e4 002B cmp r3, #0 + 7251 00e6 04D1 bne .L612 + 7252 .loc 1 2362 5 is_stmt 0 discriminator 1 + 7253 00e8 7B68 ldr r3, [r7, #4] + 7254 00ea 0122 movs r2, #1 + 7255 00ec 83F83E20 strb r2, [r3, #62] + 7256 00f0 23E0 b .L613 + 7257 .L612: + 7258 .loc 1 2362 5 discriminator 2 + 7259 00f2 3B68 ldr r3, [r7] + 7260 00f4 042B cmp r3, #4 + 7261 00f6 04D1 bne .L614 + 7262 .loc 1 2362 5 discriminator 3 + 7263 00f8 7B68 ldr r3, [r7, #4] + 7264 00fa 0122 movs r2, #1 + 7265 00fc 83F83F20 strb r2, [r3, #63] + 7266 0100 1BE0 b .L613 + ARM GAS /tmp/ccl4b9YO.s page 169 + + + 7267 .L614: + 7268 .loc 1 2362 5 discriminator 4 + 7269 0102 3B68 ldr r3, [r7] + 7270 0104 082B cmp r3, #8 + 7271 0106 04D1 bne .L616 + 7272 .loc 1 2362 5 discriminator 6 + 7273 0108 7B68 ldr r3, [r7, #4] + 7274 010a 0122 movs r2, #1 + 7275 010c 83F84020 strb r2, [r3, #64] + 7276 0110 13E0 b .L613 + 7277 .L616: + 7278 .loc 1 2362 5 discriminator 7 + 7279 0112 3B68 ldr r3, [r7] + 7280 0114 0C2B cmp r3, #12 + 7281 0116 04D1 bne .L618 + 7282 .loc 1 2362 5 discriminator 9 + 7283 0118 7B68 ldr r3, [r7, #4] + 7284 011a 0122 movs r2, #1 + 7285 011c 83F84120 strb r2, [r3, #65] + 7286 0120 0BE0 b .L613 + 7287 .L618: + 7288 .loc 1 2362 5 discriminator 10 + 7289 0122 3B68 ldr r3, [r7] + 7290 0124 102B cmp r3, #16 + 7291 0126 04D1 bne .L620 + 7292 .loc 1 2362 5 discriminator 12 + 7293 0128 7B68 ldr r3, [r7, #4] + 7294 012a 0122 movs r2, #1 + 7295 012c 83F84220 strb r2, [r3, #66] + 7296 0130 03E0 b .L613 + 7297 .L620: + 7298 .loc 1 2362 5 discriminator 13 + 7299 0132 7B68 ldr r3, [r7, #4] + 7300 0134 0122 movs r2, #1 + 7301 0136 83F84320 strb r2, [r3, #67] + 7302 .L613: +2363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 7303 .loc 1 2363 5 is_stmt 1 + 7304 013a 3B68 ldr r3, [r7] + 7305 013c 002B cmp r3, #0 + 7306 013e 04D1 bne .L622 + 7307 .loc 1 2363 5 is_stmt 0 discriminator 1 + 7308 0140 7B68 ldr r3, [r7, #4] + 7309 0142 0122 movs r2, #1 + 7310 0144 83F84420 strb r2, [r3, #68] + 7311 0148 13E0 b .L610 + 7312 .L622: + 7313 .loc 1 2363 5 discriminator 2 + 7314 014a 3B68 ldr r3, [r7] + 7315 014c 042B cmp r3, #4 + 7316 014e 04D1 bne .L623 + 7317 .loc 1 2363 5 discriminator 3 + 7318 0150 7B68 ldr r3, [r7, #4] + 7319 0152 0122 movs r2, #1 + 7320 0154 83F84520 strb r2, [r3, #69] + 7321 0158 0BE0 b .L610 + 7322 .L623: + ARM GAS /tmp/ccl4b9YO.s page 170 + + + 7323 .loc 1 2363 5 discriminator 4 + 7324 015a 3B68 ldr r3, [r7] + 7325 015c 082B cmp r3, #8 + 7326 015e 04D1 bne .L625 + 7327 .loc 1 2363 5 discriminator 6 + 7328 0160 7B68 ldr r3, [r7, #4] + 7329 0162 0122 movs r2, #1 + 7330 0164 83F84620 strb r2, [r3, #70] + 7331 0168 03E0 b .L610 + 7332 .L625: + 7333 .loc 1 2363 5 discriminator 7 + 7334 016a 7B68 ldr r3, [r7, #4] + 7335 016c 0122 movs r2, #1 + 7336 016e 83F84720 strb r2, [r3, #71] + 7337 .L610: +2364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return function status */ +2367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return status; + 7338 .loc 1 2367 10 is_stmt 1 + 7339 0172 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 +2368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 7340 .loc 1 2368 1 + 7341 0174 1846 mov r0, r3 + 7342 0176 1037 adds r7, r7, #16 + 7343 .cfi_def_cfa_offset 8 + 7344 0178 BD46 mov sp, r7 + 7345 .cfi_def_cfa_register 13 + 7346 @ sp needed + 7347 017a 80BD pop {r7, pc} + 7348 .cfi_endproc + 7349 .LFE167: + 7351 .section .text.HAL_TIM_IC_Start_DMA,"ax",%progbits + 7352 .align 1 + 7353 .global HAL_TIM_IC_Start_DMA + 7354 .syntax unified + 7355 .thumb + 7356 .thumb_func + 7358 HAL_TIM_IC_Start_DMA: + 7359 .LFB168: +2369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +2371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Starts the TIM Input Capture measurement in DMA mode. +2372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM Input Capture handle +2373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param Channel TIM Channels to be enabled +2374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +2375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +2376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +2377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +2378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +2379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param pData The destination Buffer address. +2380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param Length The length of data to be transferred from TIM peripheral to memory. +2381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status +2382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +2383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, +2384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 7360 .loc 1 2384 1 + ARM GAS /tmp/ccl4b9YO.s page 171 + + + 7361 .cfi_startproc + 7362 @ args = 0, pretend = 0, frame = 24 + 7363 @ frame_needed = 1, uses_anonymous_args = 0 + 7364 0000 80B5 push {r7, lr} + 7365 .cfi_def_cfa_offset 8 + 7366 .cfi_offset 7, -8 + 7367 .cfi_offset 14, -4 + 7368 0002 86B0 sub sp, sp, #24 + 7369 .cfi_def_cfa_offset 32 + 7370 0004 00AF add r7, sp, #0 + 7371 .cfi_def_cfa_register 7 + 7372 0006 F860 str r0, [r7, #12] + 7373 0008 B960 str r1, [r7, #8] + 7374 000a 7A60 str r2, [r7, #4] + 7375 000c 7B80 strh r3, [r7, #2] @ movhi +2385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 7376 .loc 1 2385 21 + 7377 000e 0023 movs r3, #0 + 7378 0010 FB75 strb r3, [r7, #23] +2386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpsmcr; +2387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + 7379 .loc 1 2388 47 + 7380 0012 BB68 ldr r3, [r7, #8] + 7381 0014 002B cmp r3, #0 + 7382 0016 04D1 bne .L629 + 7383 .loc 1 2388 47 is_stmt 0 discriminator 1 + 7384 0018 FB68 ldr r3, [r7, #12] + 7385 001a 93F83E30 ldrb r3, [r3, #62] + 7386 001e DBB2 uxtb r3, r3 + 7387 0020 23E0 b .L630 + 7388 .L629: + 7389 .loc 1 2388 47 discriminator 2 + 7390 0022 BB68 ldr r3, [r7, #8] + 7391 0024 042B cmp r3, #4 + 7392 0026 04D1 bne .L631 + 7393 .loc 1 2388 47 discriminator 4 + 7394 0028 FB68 ldr r3, [r7, #12] + 7395 002a 93F83F30 ldrb r3, [r3, #63] + 7396 002e DBB2 uxtb r3, r3 + 7397 0030 1BE0 b .L630 + 7398 .L631: + 7399 .loc 1 2388 47 discriminator 5 + 7400 0032 BB68 ldr r3, [r7, #8] + 7401 0034 082B cmp r3, #8 + 7402 0036 04D1 bne .L633 + 7403 .loc 1 2388 47 discriminator 7 + 7404 0038 FB68 ldr r3, [r7, #12] + 7405 003a 93F84030 ldrb r3, [r3, #64] + 7406 003e DBB2 uxtb r3, r3 + 7407 0040 13E0 b .L630 + 7408 .L633: + 7409 .loc 1 2388 47 discriminator 8 + 7410 0042 BB68 ldr r3, [r7, #8] + 7411 0044 0C2B cmp r3, #12 + 7412 0046 04D1 bne .L635 + 7413 .loc 1 2388 47 discriminator 10 + ARM GAS /tmp/ccl4b9YO.s page 172 + + + 7414 0048 FB68 ldr r3, [r7, #12] + 7415 004a 93F84130 ldrb r3, [r3, #65] + 7416 004e DBB2 uxtb r3, r3 + 7417 0050 0BE0 b .L630 + 7418 .L635: + 7419 .loc 1 2388 47 discriminator 11 + 7420 0052 BB68 ldr r3, [r7, #8] + 7421 0054 102B cmp r3, #16 + 7422 0056 04D1 bne .L637 + 7423 .loc 1 2388 47 discriminator 13 + 7424 0058 FB68 ldr r3, [r7, #12] + 7425 005a 93F84230 ldrb r3, [r3, #66] + 7426 005e DBB2 uxtb r3, r3 + 7427 0060 03E0 b .L630 + 7428 .L637: + 7429 .loc 1 2388 47 discriminator 14 + 7430 0062 FB68 ldr r3, [r7, #12] + 7431 0064 93F84330 ldrb r3, [r3, #67] + 7432 0068 DBB2 uxtb r3, r3 + 7433 .L630: + 7434 .loc 1 2388 31 is_stmt 1 discriminator 20 + 7435 006a BB75 strb r3, [r7, #22] +2389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + 7436 .loc 1 2389 61 + 7437 006c BB68 ldr r3, [r7, #8] + 7438 006e 002B cmp r3, #0 + 7439 0070 04D1 bne .L639 + 7440 .loc 1 2389 61 is_stmt 0 discriminator 1 + 7441 0072 FB68 ldr r3, [r7, #12] + 7442 0074 93F84430 ldrb r3, [r3, #68] + 7443 0078 DBB2 uxtb r3, r3 + 7444 007a 13E0 b .L640 + 7445 .L639: + 7446 .loc 1 2389 61 discriminator 2 + 7447 007c BB68 ldr r3, [r7, #8] + 7448 007e 042B cmp r3, #4 + 7449 0080 04D1 bne .L641 + 7450 .loc 1 2389 61 discriminator 4 + 7451 0082 FB68 ldr r3, [r7, #12] + 7452 0084 93F84530 ldrb r3, [r3, #69] + 7453 0088 DBB2 uxtb r3, r3 + 7454 008a 0BE0 b .L640 + 7455 .L641: + 7456 .loc 1 2389 61 discriminator 5 + 7457 008c BB68 ldr r3, [r7, #8] + 7458 008e 082B cmp r3, #8 + 7459 0090 04D1 bne .L643 + 7460 .loc 1 2389 61 discriminator 7 + 7461 0092 FB68 ldr r3, [r7, #12] + 7462 0094 93F84630 ldrb r3, [r3, #70] + 7463 0098 DBB2 uxtb r3, r3 + 7464 009a 03E0 b .L640 + 7465 .L643: + 7466 .loc 1 2389 61 discriminator 8 + 7467 009c FB68 ldr r3, [r7, #12] + 7468 009e 93F84730 ldrb r3, [r3, #71] + 7469 00a2 DBB2 uxtb r3, r3 + ARM GAS /tmp/ccl4b9YO.s page 173 + + + 7470 .L640: + 7471 .loc 1 2389 31 is_stmt 1 discriminator 12 + 7472 00a4 7B75 strb r3, [r7, #21] +2390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +2392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); +2393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); +2394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the TIM channel state */ +2396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY) + 7473 .loc 1 2396 6 + 7474 00a6 BB7D ldrb r3, [r7, #22] @ zero_extendqisi2 + 7475 00a8 022B cmp r3, #2 + 7476 00aa 02D0 beq .L645 +2397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY)) + 7477 .loc 1 2397 7 + 7478 00ac 7B7D ldrb r3, [r7, #21] @ zero_extendqisi2 + 7479 00ae 022B cmp r3, #2 + 7480 00b0 01D1 bne .L646 + 7481 .L645: +2398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_BUSY; + 7482 .loc 1 2399 12 + 7483 00b2 0223 movs r3, #2 + 7484 00b4 4DE1 b .L647 + 7485 .L646: +2400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY) + 7486 .loc 1 2401 11 + 7487 00b6 BB7D ldrb r3, [r7, #22] @ zero_extendqisi2 + 7488 00b8 012B cmp r3, #1 + 7489 00ba 53D1 bne .L648 +2402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY)) + 7490 .loc 1 2402 12 + 7491 00bc 7B7D ldrb r3, [r7, #21] @ zero_extendqisi2 + 7492 00be 012B cmp r3, #1 + 7493 00c0 50D1 bne .L648 +2403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if ((pData == NULL) || (Length == 0U)) + 7494 .loc 1 2404 8 + 7495 00c2 7B68 ldr r3, [r7, #4] + 7496 00c4 002B cmp r3, #0 + 7497 00c6 02D0 beq .L649 + 7498 .loc 1 2404 25 discriminator 1 + 7499 00c8 7B88 ldrh r3, [r7, #2] + 7500 00ca 002B cmp r3, #0 + 7501 00cc 01D1 bne .L650 + 7502 .L649: +2405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 7503 .loc 1 2406 14 + 7504 00ce 0123 movs r3, #1 + 7505 00d0 3FE1 b .L647 + 7506 .L650: +2407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +2409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + ARM GAS /tmp/ccl4b9YO.s page 174 + + +2410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + 7507 .loc 1 2410 7 + 7508 00d2 BB68 ldr r3, [r7, #8] + 7509 00d4 002B cmp r3, #0 + 7510 00d6 04D1 bne .L651 + 7511 .loc 1 2410 7 is_stmt 0 discriminator 1 + 7512 00d8 FB68 ldr r3, [r7, #12] + 7513 00da 0222 movs r2, #2 + 7514 00dc 83F83E20 strb r2, [r3, #62] + 7515 00e0 23E0 b .L652 + 7516 .L651: + 7517 .loc 1 2410 7 discriminator 2 + 7518 00e2 BB68 ldr r3, [r7, #8] + 7519 00e4 042B cmp r3, #4 + 7520 00e6 04D1 bne .L653 + 7521 .loc 1 2410 7 discriminator 3 + 7522 00e8 FB68 ldr r3, [r7, #12] + 7523 00ea 0222 movs r2, #2 + 7524 00ec 83F83F20 strb r2, [r3, #63] + 7525 00f0 1BE0 b .L652 + 7526 .L653: + 7527 .loc 1 2410 7 discriminator 4 + 7528 00f2 BB68 ldr r3, [r7, #8] + 7529 00f4 082B cmp r3, #8 + 7530 00f6 04D1 bne .L655 + 7531 .loc 1 2410 7 discriminator 6 + 7532 00f8 FB68 ldr r3, [r7, #12] + 7533 00fa 0222 movs r2, #2 + 7534 00fc 83F84020 strb r2, [r3, #64] + 7535 0100 13E0 b .L652 + 7536 .L655: + 7537 .loc 1 2410 7 discriminator 7 + 7538 0102 BB68 ldr r3, [r7, #8] + 7539 0104 0C2B cmp r3, #12 + 7540 0106 04D1 bne .L657 + 7541 .loc 1 2410 7 discriminator 9 + 7542 0108 FB68 ldr r3, [r7, #12] + 7543 010a 0222 movs r2, #2 + 7544 010c 83F84120 strb r2, [r3, #65] + 7545 0110 0BE0 b .L652 + 7546 .L657: + 7547 .loc 1 2410 7 discriminator 10 + 7548 0112 BB68 ldr r3, [r7, #8] + 7549 0114 102B cmp r3, #16 + 7550 0116 04D1 bne .L659 + 7551 .loc 1 2410 7 discriminator 12 + 7552 0118 FB68 ldr r3, [r7, #12] + 7553 011a 0222 movs r2, #2 + 7554 011c 83F84220 strb r2, [r3, #66] + 7555 0120 03E0 b .L652 + 7556 .L659: + 7557 .loc 1 2410 7 discriminator 13 + 7558 0122 FB68 ldr r3, [r7, #12] + 7559 0124 0222 movs r2, #2 + 7560 0126 83F84320 strb r2, [r3, #67] + 7561 .L652: +2411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + ARM GAS /tmp/ccl4b9YO.s page 175 + + + 7562 .loc 1 2411 7 is_stmt 1 + 7563 012a BB68 ldr r3, [r7, #8] + 7564 012c 002B cmp r3, #0 + 7565 012e 04D1 bne .L661 + 7566 .loc 1 2411 7 is_stmt 0 discriminator 1 + 7567 0130 FB68 ldr r3, [r7, #12] + 7568 0132 0222 movs r2, #2 + 7569 0134 83F84420 strb r2, [r3, #68] +2404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 7570 .loc 1 2404 8 is_stmt 1 + 7571 0138 16E0 b .L667 + 7572 .L661: + 7573 .loc 1 2411 7 discriminator 2 + 7574 013a BB68 ldr r3, [r7, #8] + 7575 013c 042B cmp r3, #4 + 7576 013e 04D1 bne .L663 + 7577 .loc 1 2411 7 is_stmt 0 discriminator 3 + 7578 0140 FB68 ldr r3, [r7, #12] + 7579 0142 0222 movs r2, #2 + 7580 0144 83F84520 strb r2, [r3, #69] +2404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 7581 .loc 1 2404 8 is_stmt 1 + 7582 0148 0EE0 b .L667 + 7583 .L663: + 7584 .loc 1 2411 7 discriminator 4 + 7585 014a BB68 ldr r3, [r7, #8] + 7586 014c 082B cmp r3, #8 + 7587 014e 04D1 bne .L665 + 7588 .loc 1 2411 7 is_stmt 0 discriminator 6 + 7589 0150 FB68 ldr r3, [r7, #12] + 7590 0152 0222 movs r2, #2 + 7591 0154 83F84620 strb r2, [r3, #70] +2404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 7592 .loc 1 2404 8 is_stmt 1 + 7593 0158 06E0 b .L667 + 7594 .L665: + 7595 .loc 1 2411 7 discriminator 7 + 7596 015a FB68 ldr r3, [r7, #12] + 7597 015c 0222 movs r2, #2 + 7598 015e 83F84720 strb r2, [r3, #71] +2404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 7599 .loc 1 2404 8 + 7600 0162 01E0 b .L667 + 7601 .L648: +2412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +2415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 7602 .loc 1 2416 12 + 7603 0164 0123 movs r3, #1 + 7604 0166 F4E0 b .L647 + 7605 .L667: +2417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the Input Capture channel */ +2420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + ARM GAS /tmp/ccl4b9YO.s page 176 + + + 7606 .loc 1 2420 3 + 7607 0168 FB68 ldr r3, [r7, #12] + 7608 016a 1B68 ldr r3, [r3] + 7609 016c 0122 movs r2, #1 + 7610 016e B968 ldr r1, [r7, #8] + 7611 0170 1846 mov r0, r3 + 7612 0172 FFF7FEFF bl TIM_CCxChannelCmd +2421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** switch (Channel) + 7613 .loc 1 2422 3 + 7614 0176 BB68 ldr r3, [r7, #8] + 7615 0178 0C2B cmp r3, #12 + 7616 017a 00F2AD80 bhi .L668 + 7617 017e 01A2 adr r2, .L670 + 7618 0180 52F823F0 ldr pc, [r2, r3, lsl #2] + 7619 .p2align 2 + 7620 .L670: + 7621 0184 B9010000 .word .L673+1 + 7622 0188 D9020000 .word .L668+1 + 7623 018c D9020000 .word .L668+1 + 7624 0190 D9020000 .word .L668+1 + 7625 0194 01020000 .word .L672+1 + 7626 0198 D9020000 .word .L668+1 + 7627 019c D9020000 .word .L668+1 + 7628 01a0 D9020000 .word .L668+1 + 7629 01a4 49020000 .word .L671+1 + 7630 01a8 D9020000 .word .L668+1 + 7631 01ac D9020000 .word .L668+1 + 7632 01b0 D9020000 .word .L668+1 + 7633 01b4 91020000 .word .L669+1 + 7634 .p2align 1 + 7635 .L673: +2423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_1: +2425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA capture callbacks */ +2427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + 7636 .loc 1 2427 17 + 7637 01b8 FB68 ldr r3, [r7, #12] + 7638 01ba 5B6A ldr r3, [r3, #36] + 7639 .loc 1 2427 52 + 7640 01bc 674A ldr r2, .L684 + 7641 01be 9A62 str r2, [r3, #40] +2428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 7642 .loc 1 2428 17 + 7643 01c0 FB68 ldr r3, [r7, #12] + 7644 01c2 5B6A ldr r3, [r3, #36] + 7645 .loc 1 2428 56 + 7646 01c4 664A ldr r2, .L684+4 + 7647 01c6 DA62 str r2, [r3, #44] +2429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA error callback */ +2431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + 7648 .loc 1 2431 17 + 7649 01c8 FB68 ldr r3, [r7, #12] + 7650 01ca 5B6A ldr r3, [r3, #36] + 7651 .loc 1 2431 53 + ARM GAS /tmp/ccl4b9YO.s page 177 + + + 7652 01cc 654A ldr r2, .L684+8 + 7653 01ce 1A63 str r2, [r3, #48] +2432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the DMA channel */ +2434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)p + 7654 .loc 1 2434 11 + 7655 01d0 FB68 ldr r3, [r7, #12] + 7656 01d2 586A ldr r0, [r3, #36] + 7657 .loc 1 2434 71 + 7658 01d4 FB68 ldr r3, [r7, #12] + 7659 01d6 1B68 ldr r3, [r3] + 7660 .loc 1 2434 66 + 7661 01d8 3433 adds r3, r3, #52 + 7662 .loc 1 2434 11 + 7663 01da 1946 mov r1, r3 + 7664 01dc 7A68 ldr r2, [r7, #4] + 7665 01de 7B88 ldrh r3, [r7, #2] + 7666 01e0 FFF7FEFF bl HAL_DMA_Start_IT + 7667 01e4 0346 mov r3, r0 + 7668 .loc 1 2434 10 discriminator 1 + 7669 01e6 002B cmp r3, #0 + 7670 01e8 01D0 beq .L674 +2435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** Length) != HAL_OK) +2436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return error status */ +2438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 7671 .loc 1 2438 16 + 7672 01ea 0123 movs r3, #1 + 7673 01ec B1E0 b .L647 + 7674 .L674: +2439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the TIM Capture/Compare 1 DMA request */ +2441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + 7675 .loc 1 2441 7 + 7676 01ee FB68 ldr r3, [r7, #12] + 7677 01f0 1B68 ldr r3, [r3] + 7678 01f2 DA68 ldr r2, [r3, #12] + 7679 01f4 FB68 ldr r3, [r7, #12] + 7680 01f6 1B68 ldr r3, [r3] + 7681 01f8 42F40072 orr r2, r2, #512 + 7682 01fc DA60 str r2, [r3, #12] +2442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 7683 .loc 1 2442 7 + 7684 01fe 6EE0 b .L675 + 7685 .L672: +2443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_2: +2446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA capture callbacks */ +2448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + 7686 .loc 1 2448 17 + 7687 0200 FB68 ldr r3, [r7, #12] + 7688 0202 9B6A ldr r3, [r3, #40] + 7689 .loc 1 2448 52 + 7690 0204 554A ldr r2, .L684 + 7691 0206 9A62 str r2, [r3, #40] + ARM GAS /tmp/ccl4b9YO.s page 178 + + +2449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 7692 .loc 1 2449 17 + 7693 0208 FB68 ldr r3, [r7, #12] + 7694 020a 9B6A ldr r3, [r3, #40] + 7695 .loc 1 2449 56 + 7696 020c 544A ldr r2, .L684+4 + 7697 020e DA62 str r2, [r3, #44] +2450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA error callback */ +2452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + 7698 .loc 1 2452 17 + 7699 0210 FB68 ldr r3, [r7, #12] + 7700 0212 9B6A ldr r3, [r3, #40] + 7701 .loc 1 2452 53 + 7702 0214 534A ldr r2, .L684+8 + 7703 0216 1A63 str r2, [r3, #48] +2453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the DMA channel */ +2455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)p + 7704 .loc 1 2455 11 + 7705 0218 FB68 ldr r3, [r7, #12] + 7706 021a 986A ldr r0, [r3, #40] + 7707 .loc 1 2455 71 + 7708 021c FB68 ldr r3, [r7, #12] + 7709 021e 1B68 ldr r3, [r3] + 7710 .loc 1 2455 66 + 7711 0220 3833 adds r3, r3, #56 + 7712 .loc 1 2455 11 + 7713 0222 1946 mov r1, r3 + 7714 0224 7A68 ldr r2, [r7, #4] + 7715 0226 7B88 ldrh r3, [r7, #2] + 7716 0228 FFF7FEFF bl HAL_DMA_Start_IT + 7717 022c 0346 mov r3, r0 + 7718 .loc 1 2455 10 discriminator 1 + 7719 022e 002B cmp r3, #0 + 7720 0230 01D0 beq .L676 +2456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** Length) != HAL_OK) +2457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return error status */ +2459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 7721 .loc 1 2459 16 + 7722 0232 0123 movs r3, #1 + 7723 0234 8DE0 b .L647 + 7724 .L676: +2460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the TIM Capture/Compare 2 DMA request */ +2462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + 7725 .loc 1 2462 7 + 7726 0236 FB68 ldr r3, [r7, #12] + 7727 0238 1B68 ldr r3, [r3] + 7728 023a DA68 ldr r2, [r3, #12] + 7729 023c FB68 ldr r3, [r7, #12] + 7730 023e 1B68 ldr r3, [r3] + 7731 0240 42F48062 orr r2, r2, #1024 + 7732 0244 DA60 str r2, [r3, #12] +2463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 7733 .loc 1 2463 7 + ARM GAS /tmp/ccl4b9YO.s page 179 + + + 7734 0246 4AE0 b .L675 + 7735 .L671: +2464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_3: +2467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA capture callbacks */ +2469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + 7736 .loc 1 2469 17 + 7737 0248 FB68 ldr r3, [r7, #12] + 7738 024a DB6A ldr r3, [r3, #44] + 7739 .loc 1 2469 52 + 7740 024c 434A ldr r2, .L684 + 7741 024e 9A62 str r2, [r3, #40] +2470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 7742 .loc 1 2470 17 + 7743 0250 FB68 ldr r3, [r7, #12] + 7744 0252 DB6A ldr r3, [r3, #44] + 7745 .loc 1 2470 56 + 7746 0254 424A ldr r2, .L684+4 + 7747 0256 DA62 str r2, [r3, #44] +2471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA error callback */ +2473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + 7748 .loc 1 2473 17 + 7749 0258 FB68 ldr r3, [r7, #12] + 7750 025a DB6A ldr r3, [r3, #44] + 7751 .loc 1 2473 53 + 7752 025c 414A ldr r2, .L684+8 + 7753 025e 1A63 str r2, [r3, #48] +2474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the DMA channel */ +2476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)p + 7754 .loc 1 2476 11 + 7755 0260 FB68 ldr r3, [r7, #12] + 7756 0262 D86A ldr r0, [r3, #44] + 7757 .loc 1 2476 71 + 7758 0264 FB68 ldr r3, [r7, #12] + 7759 0266 1B68 ldr r3, [r3] + 7760 .loc 1 2476 66 + 7761 0268 3C33 adds r3, r3, #60 + 7762 .loc 1 2476 11 + 7763 026a 1946 mov r1, r3 + 7764 026c 7A68 ldr r2, [r7, #4] + 7765 026e 7B88 ldrh r3, [r7, #2] + 7766 0270 FFF7FEFF bl HAL_DMA_Start_IT + 7767 0274 0346 mov r3, r0 + 7768 .loc 1 2476 10 discriminator 1 + 7769 0276 002B cmp r3, #0 + 7770 0278 01D0 beq .L677 +2477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** Length) != HAL_OK) +2478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return error status */ +2480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 7771 .loc 1 2480 16 + 7772 027a 0123 movs r3, #1 + 7773 027c 69E0 b .L647 + ARM GAS /tmp/ccl4b9YO.s page 180 + + + 7774 .L677: +2481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the TIM Capture/Compare 3 DMA request */ +2483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + 7775 .loc 1 2483 7 + 7776 027e FB68 ldr r3, [r7, #12] + 7777 0280 1B68 ldr r3, [r3] + 7778 0282 DA68 ldr r2, [r3, #12] + 7779 0284 FB68 ldr r3, [r7, #12] + 7780 0286 1B68 ldr r3, [r3] + 7781 0288 42F40062 orr r2, r2, #2048 + 7782 028c DA60 str r2, [r3, #12] +2484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 7783 .loc 1 2484 7 + 7784 028e 26E0 b .L675 + 7785 .L669: +2485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_4: +2488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA capture callbacks */ +2490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + 7786 .loc 1 2490 17 + 7787 0290 FB68 ldr r3, [r7, #12] + 7788 0292 1B6B ldr r3, [r3, #48] + 7789 .loc 1 2490 52 + 7790 0294 314A ldr r2, .L684 + 7791 0296 9A62 str r2, [r3, #40] +2491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 7792 .loc 1 2491 17 + 7793 0298 FB68 ldr r3, [r7, #12] + 7794 029a 1B6B ldr r3, [r3, #48] + 7795 .loc 1 2491 56 + 7796 029c 304A ldr r2, .L684+4 + 7797 029e DA62 str r2, [r3, #44] +2492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA error callback */ +2494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + 7798 .loc 1 2494 17 + 7799 02a0 FB68 ldr r3, [r7, #12] + 7800 02a2 1B6B ldr r3, [r3, #48] + 7801 .loc 1 2494 53 + 7802 02a4 2F4A ldr r2, .L684+8 + 7803 02a6 1A63 str r2, [r3, #48] +2495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the DMA channel */ +2497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)p + 7804 .loc 1 2497 11 + 7805 02a8 FB68 ldr r3, [r7, #12] + 7806 02aa 186B ldr r0, [r3, #48] + 7807 .loc 1 2497 71 + 7808 02ac FB68 ldr r3, [r7, #12] + 7809 02ae 1B68 ldr r3, [r3] + 7810 .loc 1 2497 66 + 7811 02b0 4033 adds r3, r3, #64 + 7812 .loc 1 2497 11 + 7813 02b2 1946 mov r1, r3 + ARM GAS /tmp/ccl4b9YO.s page 181 + + + 7814 02b4 7A68 ldr r2, [r7, #4] + 7815 02b6 7B88 ldrh r3, [r7, #2] + 7816 02b8 FFF7FEFF bl HAL_DMA_Start_IT + 7817 02bc 0346 mov r3, r0 + 7818 .loc 1 2497 10 discriminator 1 + 7819 02be 002B cmp r3, #0 + 7820 02c0 01D0 beq .L678 +2498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** Length) != HAL_OK) +2499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return error status */ +2501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 7821 .loc 1 2501 16 + 7822 02c2 0123 movs r3, #1 + 7823 02c4 45E0 b .L647 + 7824 .L678: +2502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the TIM Capture/Compare 4 DMA request */ +2504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + 7825 .loc 1 2504 7 + 7826 02c6 FB68 ldr r3, [r7, #12] + 7827 02c8 1B68 ldr r3, [r3] + 7828 02ca DA68 ldr r2, [r3, #12] + 7829 02cc FB68 ldr r3, [r7, #12] + 7830 02ce 1B68 ldr r3, [r3] + 7831 02d0 42F48052 orr r2, r2, #4096 + 7832 02d4 DA60 str r2, [r3, #12] +2505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 7833 .loc 1 2505 7 + 7834 02d6 02E0 b .L675 + 7835 .L668: +2506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** default: +2509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** status = HAL_ERROR; + 7836 .loc 1 2509 14 + 7837 02d8 0123 movs r3, #1 + 7838 02da FB75 strb r3, [r7, #23] +2510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 7839 .loc 1 2510 7 + 7840 02dc 00BF nop + 7841 .L675: +2511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger +2514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 7842 .loc 1 2514 7 + 7843 02de FB68 ldr r3, [r7, #12] + 7844 02e0 1B68 ldr r3, [r3] + 7845 .loc 1 2514 6 + 7846 02e2 214A ldr r2, .L684+12 + 7847 02e4 9342 cmp r3, r2 + 7848 02e6 13D0 beq .L679 + 7849 .loc 1 2514 7 discriminator 1 + 7850 02e8 FB68 ldr r3, [r7, #12] + 7851 02ea 1B68 ldr r3, [r3] + 7852 02ec B3F1804F cmp r3, #1073741824 + 7853 02f0 0ED0 beq .L679 + ARM GAS /tmp/ccl4b9YO.s page 182 + + + 7854 .loc 1 2514 7 is_stmt 0 discriminator 2 + 7855 02f2 FB68 ldr r3, [r7, #12] + 7856 02f4 1B68 ldr r3, [r3] + 7857 02f6 1D4A ldr r2, .L684+16 + 7858 02f8 9342 cmp r3, r2 + 7859 02fa 09D0 beq .L679 + 7860 .loc 1 2514 7 discriminator 3 + 7861 02fc FB68 ldr r3, [r7, #12] + 7862 02fe 1B68 ldr r3, [r3] + 7863 0300 1B4A ldr r2, .L684+20 + 7864 0302 9342 cmp r3, r2 + 7865 0304 04D0 beq .L679 + 7866 .loc 1 2514 7 discriminator 4 + 7867 0306 FB68 ldr r3, [r7, #12] + 7868 0308 1B68 ldr r3, [r3] + 7869 030a 1A4A ldr r2, .L684+24 + 7870 030c 9342 cmp r3, r2 + 7871 030e 15D1 bne .L680 + 7872 .L679: +2515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + 7873 .loc 1 2516 19 is_stmt 1 + 7874 0310 FB68 ldr r3, [r7, #12] + 7875 0312 1B68 ldr r3, [r3] + 7876 .loc 1 2516 29 + 7877 0314 9A68 ldr r2, [r3, #8] + 7878 .loc 1 2516 13 + 7879 0316 184B ldr r3, .L684+28 + 7880 0318 1340 ands r3, r3, r2 + 7881 031a 3B61 str r3, [r7, #16] +2517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 7882 .loc 1 2517 8 + 7883 031c 3B69 ldr r3, [r7, #16] + 7884 031e 062B cmp r3, #6 + 7885 0320 15D0 beq .L683 + 7886 .loc 1 2517 9 discriminator 1 + 7887 0322 3B69 ldr r3, [r7, #16] + 7888 0324 B3F5803F cmp r3, #65536 + 7889 0328 11D0 beq .L683 +2518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); + 7890 .loc 1 2519 7 + 7891 032a FB68 ldr r3, [r7, #12] + 7892 032c 1B68 ldr r3, [r3] + 7893 032e 1A68 ldr r2, [r3] + 7894 0330 FB68 ldr r3, [r7, #12] + 7895 0332 1B68 ldr r3, [r3] + 7896 0334 42F00102 orr r2, r2, #1 + 7897 0338 1A60 str r2, [r3] +2517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 7898 .loc 1 2517 8 + 7899 033a 08E0 b .L683 + 7900 .L680: +2520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +2523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + ARM GAS /tmp/ccl4b9YO.s page 183 + + +2524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); + 7901 .loc 1 2524 5 + 7902 033c FB68 ldr r3, [r7, #12] + 7903 033e 1B68 ldr r3, [r3] + 7904 0340 1A68 ldr r2, [r3] + 7905 0342 FB68 ldr r3, [r7, #12] + 7906 0344 1B68 ldr r3, [r3] + 7907 0346 42F00102 orr r2, r2, #1 + 7908 034a 1A60 str r2, [r3] + 7909 034c 00E0 b .L682 + 7910 .L683: +2517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 7911 .loc 1 2517 8 + 7912 034e 00BF nop + 7913 .L682: +2525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return function status */ +2528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return status; + 7914 .loc 1 2528 10 + 7915 0350 FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 7916 .L647: +2529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 7917 .loc 1 2529 1 + 7918 0352 1846 mov r0, r3 + 7919 0354 1837 adds r7, r7, #24 + 7920 .cfi_def_cfa_offset 8 + 7921 0356 BD46 mov sp, r7 + 7922 .cfi_def_cfa_register 13 + 7923 @ sp needed + 7924 0358 80BD pop {r7, pc} + 7925 .L685: + 7926 035a 00BF .align 2 + 7927 .L684: + 7928 035c 00000000 .word TIM_DMACaptureCplt + 7929 0360 00000000 .word TIM_DMACaptureHalfCplt + 7930 0364 00000000 .word TIM_DMAError + 7931 0368 002C0140 .word 1073818624 + 7932 036c 00040040 .word 1073742848 + 7933 0370 00080040 .word 1073743872 + 7934 0374 00400140 .word 1073823744 + 7935 0378 07000100 .word 65543 + 7936 .cfi_endproc + 7937 .LFE168: + 7939 .section .text.HAL_TIM_IC_Stop_DMA,"ax",%progbits + 7940 .align 1 + 7941 .global HAL_TIM_IC_Stop_DMA + 7942 .syntax unified + 7943 .thumb + 7944 .thumb_func + 7946 HAL_TIM_IC_Stop_DMA: + 7947 .LFB169: +2530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +2532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Stops the TIM Input Capture measurement in DMA mode. +2533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM Input Capture handle +2534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param Channel TIM Channels to be disabled + ARM GAS /tmp/ccl4b9YO.s page 184 + + +2535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +2536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +2537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +2538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +2539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +2540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status +2541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +2542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +2543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 7948 .loc 1 2543 1 + 7949 .cfi_startproc + 7950 @ args = 0, pretend = 0, frame = 16 + 7951 @ frame_needed = 1, uses_anonymous_args = 0 + 7952 0000 80B5 push {r7, lr} + 7953 .cfi_def_cfa_offset 8 + 7954 .cfi_offset 7, -8 + 7955 .cfi_offset 14, -4 + 7956 0002 84B0 sub sp, sp, #16 + 7957 .cfi_def_cfa_offset 24 + 7958 0004 00AF add r7, sp, #0 + 7959 .cfi_def_cfa_register 7 + 7960 0006 7860 str r0, [r7, #4] + 7961 0008 3960 str r1, [r7] +2544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 7962 .loc 1 2544 21 + 7963 000a 0023 movs r3, #0 + 7964 000c FB73 strb r3, [r7, #15] +2545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +2547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); +2548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); +2549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the Input Capture channel */ +2551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + 7965 .loc 1 2551 3 + 7966 000e 7B68 ldr r3, [r7, #4] + 7967 0010 1B68 ldr r3, [r3] + 7968 0012 0022 movs r2, #0 + 7969 0014 3968 ldr r1, [r7] + 7970 0016 1846 mov r0, r3 + 7971 0018 FFF7FEFF bl TIM_CCxChannelCmd +2552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** switch (Channel) + 7972 .loc 1 2553 3 + 7973 001c 3B68 ldr r3, [r7] + 7974 001e 0C2B cmp r3, #12 + 7975 0020 54D8 bhi .L687 + 7976 0022 01A2 adr r2, .L689 + 7977 0024 52F823F0 ldr pc, [r2, r3, lsl #2] + 7978 .p2align 2 + 7979 .L689: + 7980 0028 5D000000 .word .L692+1 + 7981 002c CD000000 .word .L687+1 + 7982 0030 CD000000 .word .L687+1 + 7983 0034 CD000000 .word .L687+1 + 7984 0038 79000000 .word .L691+1 + 7985 003c CD000000 .word .L687+1 + ARM GAS /tmp/ccl4b9YO.s page 185 + + + 7986 0040 CD000000 .word .L687+1 + 7987 0044 CD000000 .word .L687+1 + 7988 0048 95000000 .word .L690+1 + 7989 004c CD000000 .word .L687+1 + 7990 0050 CD000000 .word .L687+1 + 7991 0054 CD000000 .word .L687+1 + 7992 0058 B1000000 .word .L688+1 + 7993 .p2align 1 + 7994 .L692: +2554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_1: +2556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the TIM Capture/Compare 1 DMA request */ +2558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + 7995 .loc 1 2558 7 + 7996 005c 7B68 ldr r3, [r7, #4] + 7997 005e 1B68 ldr r3, [r3] + 7998 0060 DA68 ldr r2, [r3, #12] + 7999 0062 7B68 ldr r3, [r7, #4] + 8000 0064 1B68 ldr r3, [r3] + 8001 0066 22F40072 bic r2, r2, #512 + 8002 006a DA60 str r2, [r3, #12] +2559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + 8003 .loc 1 2559 13 + 8004 006c 7B68 ldr r3, [r7, #4] + 8005 006e 5B6A ldr r3, [r3, #36] + 8006 0070 1846 mov r0, r3 + 8007 0072 FFF7FEFF bl HAL_DMA_Abort_IT +2560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 8008 .loc 1 2560 7 + 8009 0076 2CE0 b .L693 + 8010 .L691: +2561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_2: +2564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the TIM Capture/Compare 2 DMA request */ +2566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + 8011 .loc 1 2566 7 + 8012 0078 7B68 ldr r3, [r7, #4] + 8013 007a 1B68 ldr r3, [r3] + 8014 007c DA68 ldr r2, [r3, #12] + 8015 007e 7B68 ldr r3, [r7, #4] + 8016 0080 1B68 ldr r3, [r3] + 8017 0082 22F48062 bic r2, r2, #1024 + 8018 0086 DA60 str r2, [r3, #12] +2567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + 8019 .loc 1 2567 13 + 8020 0088 7B68 ldr r3, [r7, #4] + 8021 008a 9B6A ldr r3, [r3, #40] + 8022 008c 1846 mov r0, r3 + 8023 008e FFF7FEFF bl HAL_DMA_Abort_IT +2568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 8024 .loc 1 2568 7 + 8025 0092 1EE0 b .L693 + 8026 .L690: +2569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + ARM GAS /tmp/ccl4b9YO.s page 186 + + +2570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_3: +2572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the TIM Capture/Compare 3 DMA request */ +2574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + 8027 .loc 1 2574 7 + 8028 0094 7B68 ldr r3, [r7, #4] + 8029 0096 1B68 ldr r3, [r3] + 8030 0098 DA68 ldr r2, [r3, #12] + 8031 009a 7B68 ldr r3, [r7, #4] + 8032 009c 1B68 ldr r3, [r3] + 8033 009e 22F40062 bic r2, r2, #2048 + 8034 00a2 DA60 str r2, [r3, #12] +2575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + 8035 .loc 1 2575 13 + 8036 00a4 7B68 ldr r3, [r7, #4] + 8037 00a6 DB6A ldr r3, [r3, #44] + 8038 00a8 1846 mov r0, r3 + 8039 00aa FFF7FEFF bl HAL_DMA_Abort_IT +2576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 8040 .loc 1 2576 7 + 8041 00ae 10E0 b .L693 + 8042 .L688: +2577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_4: +2580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the TIM Capture/Compare 4 DMA request */ +2582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + 8043 .loc 1 2582 7 + 8044 00b0 7B68 ldr r3, [r7, #4] + 8045 00b2 1B68 ldr r3, [r3] + 8046 00b4 DA68 ldr r2, [r3, #12] + 8047 00b6 7B68 ldr r3, [r7, #4] + 8048 00b8 1B68 ldr r3, [r3] + 8049 00ba 22F48052 bic r2, r2, #4096 + 8050 00be DA60 str r2, [r3, #12] +2583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + 8051 .loc 1 2583 13 + 8052 00c0 7B68 ldr r3, [r7, #4] + 8053 00c2 1B6B ldr r3, [r3, #48] + 8054 00c4 1846 mov r0, r3 + 8055 00c6 FFF7FEFF bl HAL_DMA_Abort_IT +2584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 8056 .loc 1 2584 7 + 8057 00ca 02E0 b .L693 + 8058 .L687: +2585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** default: +2588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** status = HAL_ERROR; + 8059 .loc 1 2588 14 + 8060 00cc 0123 movs r3, #1 + 8061 00ce FB73 strb r3, [r7, #15] +2589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 8062 .loc 1 2589 7 + 8063 00d0 00BF nop + ARM GAS /tmp/ccl4b9YO.s page 187 + + + 8064 .L693: +2590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (status == HAL_OK) + 8065 .loc 1 2592 6 + 8066 00d2 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 8067 00d4 002B cmp r3, #0 + 8068 00d6 5FD1 bne .L694 +2593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the Peripheral */ +2595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); + 8069 .loc 1 2595 5 + 8070 00d8 7B68 ldr r3, [r7, #4] + 8071 00da 1B68 ldr r3, [r3] + 8072 00dc 1A6A ldr r2, [r3, #32] + 8073 00de 41F21113 movw r3, #4369 + 8074 00e2 1340 ands r3, r3, r2 + 8075 00e4 002B cmp r3, #0 + 8076 00e6 0FD1 bne .L695 + 8077 .loc 1 2595 5 is_stmt 0 discriminator 1 + 8078 00e8 7B68 ldr r3, [r7, #4] + 8079 00ea 1B68 ldr r3, [r3] + 8080 00ec 1A6A ldr r2, [r3, #32] + 8081 00ee 40F24443 movw r3, #1092 + 8082 00f2 1340 ands r3, r3, r2 + 8083 00f4 002B cmp r3, #0 + 8084 00f6 07D1 bne .L695 + 8085 .loc 1 2595 5 discriminator 2 + 8086 00f8 7B68 ldr r3, [r7, #4] + 8087 00fa 1B68 ldr r3, [r3] + 8088 00fc 1A68 ldr r2, [r3] + 8089 00fe 7B68 ldr r3, [r7, #4] + 8090 0100 1B68 ldr r3, [r3] + 8091 0102 22F00102 bic r2, r2, #1 + 8092 0106 1A60 str r2, [r3] + 8093 .L695: +2596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the TIM channel state */ +2598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 8094 .loc 1 2598 5 is_stmt 1 + 8095 0108 3B68 ldr r3, [r7] + 8096 010a 002B cmp r3, #0 + 8097 010c 04D1 bne .L696 + 8098 .loc 1 2598 5 is_stmt 0 discriminator 1 + 8099 010e 7B68 ldr r3, [r7, #4] + 8100 0110 0122 movs r2, #1 + 8101 0112 83F83E20 strb r2, [r3, #62] + 8102 0116 23E0 b .L697 + 8103 .L696: + 8104 .loc 1 2598 5 discriminator 2 + 8105 0118 3B68 ldr r3, [r7] + 8106 011a 042B cmp r3, #4 + 8107 011c 04D1 bne .L698 + 8108 .loc 1 2598 5 discriminator 3 + 8109 011e 7B68 ldr r3, [r7, #4] + 8110 0120 0122 movs r2, #1 + 8111 0122 83F83F20 strb r2, [r3, #63] + ARM GAS /tmp/ccl4b9YO.s page 188 + + + 8112 0126 1BE0 b .L697 + 8113 .L698: + 8114 .loc 1 2598 5 discriminator 4 + 8115 0128 3B68 ldr r3, [r7] + 8116 012a 082B cmp r3, #8 + 8117 012c 04D1 bne .L700 + 8118 .loc 1 2598 5 discriminator 6 + 8119 012e 7B68 ldr r3, [r7, #4] + 8120 0130 0122 movs r2, #1 + 8121 0132 83F84020 strb r2, [r3, #64] + 8122 0136 13E0 b .L697 + 8123 .L700: + 8124 .loc 1 2598 5 discriminator 7 + 8125 0138 3B68 ldr r3, [r7] + 8126 013a 0C2B cmp r3, #12 + 8127 013c 04D1 bne .L702 + 8128 .loc 1 2598 5 discriminator 9 + 8129 013e 7B68 ldr r3, [r7, #4] + 8130 0140 0122 movs r2, #1 + 8131 0142 83F84120 strb r2, [r3, #65] + 8132 0146 0BE0 b .L697 + 8133 .L702: + 8134 .loc 1 2598 5 discriminator 10 + 8135 0148 3B68 ldr r3, [r7] + 8136 014a 102B cmp r3, #16 + 8137 014c 04D1 bne .L704 + 8138 .loc 1 2598 5 discriminator 12 + 8139 014e 7B68 ldr r3, [r7, #4] + 8140 0150 0122 movs r2, #1 + 8141 0152 83F84220 strb r2, [r3, #66] + 8142 0156 03E0 b .L697 + 8143 .L704: + 8144 .loc 1 2598 5 discriminator 13 + 8145 0158 7B68 ldr r3, [r7, #4] + 8146 015a 0122 movs r2, #1 + 8147 015c 83F84320 strb r2, [r3, #67] + 8148 .L697: +2599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 8149 .loc 1 2599 5 is_stmt 1 + 8150 0160 3B68 ldr r3, [r7] + 8151 0162 002B cmp r3, #0 + 8152 0164 04D1 bne .L706 + 8153 .loc 1 2599 5 is_stmt 0 discriminator 1 + 8154 0166 7B68 ldr r3, [r7, #4] + 8155 0168 0122 movs r2, #1 + 8156 016a 83F84420 strb r2, [r3, #68] + 8157 016e 13E0 b .L694 + 8158 .L706: + 8159 .loc 1 2599 5 discriminator 2 + 8160 0170 3B68 ldr r3, [r7] + 8161 0172 042B cmp r3, #4 + 8162 0174 04D1 bne .L707 + 8163 .loc 1 2599 5 discriminator 3 + 8164 0176 7B68 ldr r3, [r7, #4] + 8165 0178 0122 movs r2, #1 + 8166 017a 83F84520 strb r2, [r3, #69] + 8167 017e 0BE0 b .L694 + ARM GAS /tmp/ccl4b9YO.s page 189 + + + 8168 .L707: + 8169 .loc 1 2599 5 discriminator 4 + 8170 0180 3B68 ldr r3, [r7] + 8171 0182 082B cmp r3, #8 + 8172 0184 04D1 bne .L709 + 8173 .loc 1 2599 5 discriminator 6 + 8174 0186 7B68 ldr r3, [r7, #4] + 8175 0188 0122 movs r2, #1 + 8176 018a 83F84620 strb r2, [r3, #70] + 8177 018e 03E0 b .L694 + 8178 .L709: + 8179 .loc 1 2599 5 discriminator 7 + 8180 0190 7B68 ldr r3, [r7, #4] + 8181 0192 0122 movs r2, #1 + 8182 0194 83F84720 strb r2, [r3, #71] + 8183 .L694: +2600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2602:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return function status */ +2603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return status; + 8184 .loc 1 2603 10 is_stmt 1 + 8185 0198 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 +2604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 8186 .loc 1 2604 1 + 8187 019a 1846 mov r0, r3 + 8188 019c 1037 adds r7, r7, #16 + 8189 .cfi_def_cfa_offset 8 + 8190 019e BD46 mov sp, r7 + 8191 .cfi_def_cfa_register 13 + 8192 @ sp needed + 8193 01a0 80BD pop {r7, pc} + 8194 .cfi_endproc + 8195 .LFE169: + 8197 01a2 00BF .section .text.HAL_TIM_OnePulse_Init,"ax",%progbits + 8198 .align 1 + 8199 .global HAL_TIM_OnePulse_Init + 8200 .syntax unified + 8201 .thumb + 8202 .thumb_func + 8204 HAL_TIM_OnePulse_Init: + 8205 .LFB170: +2605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +2606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @} +2607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +2608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions +2610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief TIM One Pulse functions +2611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * +2612:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** @verbatim +2613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** ============================================================================== +2614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** ##### TIM One Pulse functions ##### +2615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** ============================================================================== +2616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** [..] +2617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** This section provides functions allowing to: +2618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Initialize and configure the TIM One Pulse. +2619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) De-initialize the TIM One Pulse. +2620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Start the TIM One Pulse. + ARM GAS /tmp/ccl4b9YO.s page 190 + + +2621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Stop the TIM One Pulse. +2622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Start the TIM One Pulse and enable interrupt. +2623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Stop the TIM One Pulse and disable interrupt. +2624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Start the TIM One Pulse and enable DMA transfer. +2625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Stop the TIM One Pulse and disable DMA transfer. +2626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** @endverbatim +2628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @{ +2629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +2630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +2631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Initializes the TIM One Pulse Time Base according to the specified +2632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * parameters in the TIM_HandleTypeDef and initializes the associated handle. +2633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) +2634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * requires a timer reset to avoid unexpected direction +2635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * due to DIR bit readonly in center aligned mode. +2636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init() +2637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @note When the timer instance is initialized in One Pulse mode, timer +2638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * channels 1 and channel 2 are reserved and cannot be used for other +2639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * purpose. +2640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM One Pulse handle +2641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param OnePulseMode Select the One pulse mode. +2642:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +2643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. +2644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated. +2645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status +2646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +2647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) +2648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 8206 .loc 1 2648 1 + 8207 .cfi_startproc + 8208 @ args = 0, pretend = 0, frame = 8 + 8209 @ frame_needed = 1, uses_anonymous_args = 0 + 8210 0000 80B5 push {r7, lr} + 8211 .cfi_def_cfa_offset 8 + 8212 .cfi_offset 7, -8 + 8213 .cfi_offset 14, -4 + 8214 0002 82B0 sub sp, sp, #8 + 8215 .cfi_def_cfa_offset 16 + 8216 0004 00AF add r7, sp, #0 + 8217 .cfi_def_cfa_register 7 + 8218 0006 7860 str r0, [r7, #4] + 8219 0008 3960 str r1, [r7] +2649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the TIM handle allocation */ +2650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (htim == NULL) + 8220 .loc 1 2650 6 + 8221 000a 7B68 ldr r3, [r7, #4] + 8222 000c 002B cmp r3, #0 + 8223 000e 01D1 bne .L713 +2651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 8224 .loc 1 2652 12 + 8225 0010 0123 movs r3, #1 + 8226 0012 41E0 b .L714 + 8227 .L713: +2653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2655:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ + ARM GAS /tmp/ccl4b9YO.s page 191 + + +2656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_INSTANCE(htim->Instance)); +2657:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); +2658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); +2659:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_OPM_MODE(OnePulseMode)); +2660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); +2661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); +2662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (htim->State == HAL_TIM_STATE_RESET) + 8228 .loc 1 2663 11 + 8229 0014 7B68 ldr r3, [r7, #4] + 8230 0016 93F83D30 ldrb r3, [r3, #61] + 8231 001a DBB2 uxtb r3, r3 + 8232 .loc 1 2663 6 + 8233 001c 002B cmp r3, #0 + 8234 001e 06D1 bne .L715 +2664:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Allocate lock resource and initialize it */ +2666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Lock = HAL_UNLOCKED; + 8235 .loc 1 2666 16 + 8236 0020 7B68 ldr r3, [r7, #4] + 8237 0022 0022 movs r2, #0 + 8238 0024 83F83C20 strb r2, [r3, #60] +2667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2668:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +2669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Reset interrupt callbacks to legacy weak callbacks */ +2670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_ResetCallback(htim); +2671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (htim->OnePulse_MspInitCallback == NULL) +2673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; +2675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Init the low level hardware : GPIO, CLOCK, NVIC */ +2677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->OnePulse_MspInitCallback(htim); +2678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #else +2679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ +2680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_OnePulse_MspInit(htim); + 8239 .loc 1 2680 5 + 8240 0028 7868 ldr r0, [r7, #4] + 8241 002a FFF7FEFF bl HAL_TIM_OnePulse_MspInit + 8242 .L715: +2681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +2682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the TIM state */ +2685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; + 8243 .loc 1 2685 15 + 8244 002e 7B68 ldr r3, [r7, #4] + 8245 0030 0222 movs r2, #2 + 8246 0032 83F83D20 strb r2, [r3, #61] +2686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Configure the Time base in the One Pulse Mode */ +2688:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_Base_SetConfig(htim->Instance, &htim->Init); + 8247 .loc 1 2688 3 + 8248 0036 7B68 ldr r3, [r7, #4] + 8249 0038 1A68 ldr r2, [r3] + 8250 .loc 1 2688 38 + 8251 003a 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/ccl4b9YO.s page 192 + + + 8252 003c 0433 adds r3, r3, #4 + 8253 .loc 1 2688 3 + 8254 003e 1946 mov r1, r3 + 8255 0040 1046 mov r0, r2 + 8256 0042 FFF7FEFF bl TIM_Base_SetConfig +2689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Reset the OPM Bit */ +2691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->CR1 &= ~TIM_CR1_OPM; + 8257 .loc 1 2691 7 + 8258 0046 7B68 ldr r3, [r7, #4] + 8259 0048 1B68 ldr r3, [r3] + 8260 .loc 1 2691 17 + 8261 004a 1A68 ldr r2, [r3] + 8262 .loc 1 2691 7 + 8263 004c 7B68 ldr r3, [r7, #4] + 8264 004e 1B68 ldr r3, [r3] + 8265 .loc 1 2691 23 + 8266 0050 22F00802 bic r2, r2, #8 + 8267 0054 1A60 str r2, [r3] +2692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Configure the OPM Mode */ +2694:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->CR1 |= OnePulseMode; + 8268 .loc 1 2694 7 + 8269 0056 7B68 ldr r3, [r7, #4] + 8270 0058 1B68 ldr r3, [r3] + 8271 .loc 1 2694 17 + 8272 005a 1968 ldr r1, [r3] + 8273 .loc 1 2694 7 + 8274 005c 7B68 ldr r3, [r7, #4] + 8275 005e 1B68 ldr r3, [r3] + 8276 .loc 1 2694 23 + 8277 0060 3A68 ldr r2, [r7] + 8278 0062 0A43 orrs r2, r2, r1 + 8279 0064 1A60 str r2, [r3] +2695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Initialize the DMA burst operation state */ +2697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + 8280 .loc 1 2697 23 + 8281 0066 7B68 ldr r3, [r7, #4] + 8282 0068 0122 movs r2, #1 + 8283 006a 83F84820 strb r2, [r3, #72] +2698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Initialize the TIM channels state */ +2700:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 8284 .loc 1 2700 3 + 8285 006e 7B68 ldr r3, [r7, #4] + 8286 0070 0122 movs r2, #1 + 8287 0072 83F83E20 strb r2, [r3, #62] +2701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 8288 .loc 1 2701 3 + 8289 0076 7B68 ldr r3, [r7, #4] + 8290 0078 0122 movs r2, #1 + 8291 007a 83F83F20 strb r2, [r3, #63] +2702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 8292 .loc 1 2702 3 + 8293 007e 7B68 ldr r3, [r7, #4] + 8294 0080 0122 movs r2, #1 + ARM GAS /tmp/ccl4b9YO.s page 193 + + + 8295 0082 83F84420 strb r2, [r3, #68] +2703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 8296 .loc 1 2703 3 + 8297 0086 7B68 ldr r3, [r7, #4] + 8298 0088 0122 movs r2, #1 + 8299 008a 83F84520 strb r2, [r3, #69] +2704:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Initialize the TIM state*/ +2706:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; + 8300 .loc 1 2706 15 + 8301 008e 7B68 ldr r3, [r7, #4] + 8302 0090 0122 movs r2, #1 + 8303 0092 83F83D20 strb r2, [r3, #61] +2707:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2708:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_OK; + 8304 .loc 1 2708 10 + 8305 0096 0023 movs r3, #0 + 8306 .L714: +2709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 8307 .loc 1 2709 1 + 8308 0098 1846 mov r0, r3 + 8309 009a 0837 adds r7, r7, #8 + 8310 .cfi_def_cfa_offset 8 + 8311 009c BD46 mov sp, r7 + 8312 .cfi_def_cfa_register 13 + 8313 @ sp needed + 8314 009e 80BD pop {r7, pc} + 8315 .cfi_endproc + 8316 .LFE170: + 8318 .section .text.HAL_TIM_OnePulse_DeInit,"ax",%progbits + 8319 .align 1 + 8320 .global HAL_TIM_OnePulse_DeInit + 8321 .syntax unified + 8322 .thumb + 8323 .thumb_func + 8325 HAL_TIM_OnePulse_DeInit: + 8326 .LFB171: +2710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +2712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief DeInitializes the TIM One Pulse +2713:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM One Pulse handle +2714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status +2715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +2716:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) +2717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 8327 .loc 1 2717 1 + 8328 .cfi_startproc + 8329 @ args = 0, pretend = 0, frame = 8 + 8330 @ frame_needed = 1, uses_anonymous_args = 0 + 8331 0000 80B5 push {r7, lr} + 8332 .cfi_def_cfa_offset 8 + 8333 .cfi_offset 7, -8 + 8334 .cfi_offset 14, -4 + 8335 0002 82B0 sub sp, sp, #8 + 8336 .cfi_def_cfa_offset 16 + 8337 0004 00AF add r7, sp, #0 + 8338 .cfi_def_cfa_register 7 + ARM GAS /tmp/ccl4b9YO.s page 194 + + + 8339 0006 7860 str r0, [r7, #4] +2718:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +2719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_INSTANCE(htim->Instance)); +2720:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; + 8340 .loc 1 2721 15 + 8341 0008 7B68 ldr r3, [r7, #4] + 8342 000a 0222 movs r2, #2 + 8343 000c 83F83D20 strb r2, [r3, #61] +2722:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2723:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the TIM Peripheral Clock */ +2724:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); + 8344 .loc 1 2724 3 + 8345 0010 7B68 ldr r3, [r7, #4] + 8346 0012 1B68 ldr r3, [r3] + 8347 0014 1A6A ldr r2, [r3, #32] + 8348 0016 41F21113 movw r3, #4369 + 8349 001a 1340 ands r3, r3, r2 + 8350 001c 002B cmp r3, #0 + 8351 001e 0FD1 bne .L717 + 8352 .loc 1 2724 3 is_stmt 0 discriminator 1 + 8353 0020 7B68 ldr r3, [r7, #4] + 8354 0022 1B68 ldr r3, [r3] + 8355 0024 1A6A ldr r2, [r3, #32] + 8356 0026 40F24443 movw r3, #1092 + 8357 002a 1340 ands r3, r3, r2 + 8358 002c 002B cmp r3, #0 + 8359 002e 07D1 bne .L717 + 8360 .loc 1 2724 3 discriminator 2 + 8361 0030 7B68 ldr r3, [r7, #4] + 8362 0032 1B68 ldr r3, [r3] + 8363 0034 1A68 ldr r2, [r3] + 8364 0036 7B68 ldr r3, [r7, #4] + 8365 0038 1B68 ldr r3, [r3] + 8366 003a 22F00102 bic r2, r2, #1 + 8367 003e 1A60 str r2, [r3] + 8368 .L717: +2725:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +2727:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (htim->OnePulse_MspDeInitCallback == NULL) +2728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; +2730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* DeInit the low level hardware */ +2732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->OnePulse_MspDeInitCallback(htim); +2733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #else +2734:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ +2735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_OnePulse_MspDeInit(htim); + 8369 .loc 1 2735 3 is_stmt 1 + 8370 0040 7868 ldr r0, [r7, #4] + 8371 0042 FFF7FEFF bl HAL_TIM_OnePulse_MspDeInit +2736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +2737:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Change the DMA burst operation state */ +2739:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + 8372 .loc 1 2739 23 + 8373 0046 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/ccl4b9YO.s page 195 + + + 8374 0048 0022 movs r2, #0 + 8375 004a 83F84820 strb r2, [r3, #72] +2740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the TIM channel state */ +2742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + 8376 .loc 1 2742 3 + 8377 004e 7B68 ldr r3, [r7, #4] + 8378 0050 0022 movs r2, #0 + 8379 0052 83F83E20 strb r2, [r3, #62] +2743:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + 8380 .loc 1 2743 3 + 8381 0056 7B68 ldr r3, [r7, #4] + 8382 0058 0022 movs r2, #0 + 8383 005a 83F83F20 strb r2, [r3, #63] +2744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + 8384 .loc 1 2744 3 + 8385 005e 7B68 ldr r3, [r7, #4] + 8386 0060 0022 movs r2, #0 + 8387 0062 83F84420 strb r2, [r3, #68] +2745:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + 8388 .loc 1 2745 3 + 8389 0066 7B68 ldr r3, [r7, #4] + 8390 0068 0022 movs r2, #0 + 8391 006a 83F84520 strb r2, [r3, #69] +2746:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2747:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Change TIM state */ +2748:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->State = HAL_TIM_STATE_RESET; + 8392 .loc 1 2748 15 + 8393 006e 7B68 ldr r3, [r7, #4] + 8394 0070 0022 movs r2, #0 + 8395 0072 83F83D20 strb r2, [r3, #61] +2749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Release Lock */ +2751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_UNLOCK(htim); + 8396 .loc 1 2751 3 + 8397 0076 7B68 ldr r3, [r7, #4] + 8398 0078 0022 movs r2, #0 + 8399 007a 83F83C20 strb r2, [r3, #60] +2752:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_OK; + 8400 .loc 1 2753 10 + 8401 007e 0023 movs r3, #0 +2754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 8402 .loc 1 2754 1 + 8403 0080 1846 mov r0, r3 + 8404 0082 0837 adds r7, r7, #8 + 8405 .cfi_def_cfa_offset 8 + 8406 0084 BD46 mov sp, r7 + 8407 .cfi_def_cfa_register 13 + 8408 @ sp needed + 8409 0086 80BD pop {r7, pc} + 8410 .cfi_endproc + 8411 .LFE171: + 8413 .section .text.HAL_TIM_OnePulse_MspInit,"ax",%progbits + 8414 .align 1 + 8415 .weak HAL_TIM_OnePulse_MspInit + 8416 .syntax unified + ARM GAS /tmp/ccl4b9YO.s page 196 + + + 8417 .thumb + 8418 .thumb_func + 8420 HAL_TIM_OnePulse_MspInit: + 8421 .LFB172: +2755:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +2757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Initializes the TIM One Pulse MSP. +2758:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM One Pulse handle +2759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval None +2760:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +2761:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) +2762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 8422 .loc 1 2762 1 + 8423 .cfi_startproc + 8424 @ args = 0, pretend = 0, frame = 8 + 8425 @ frame_needed = 1, uses_anonymous_args = 0 + 8426 @ link register save eliminated. + 8427 0000 80B4 push {r7} + 8428 .cfi_def_cfa_offset 4 + 8429 .cfi_offset 7, -4 + 8430 0002 83B0 sub sp, sp, #12 + 8431 .cfi_def_cfa_offset 16 + 8432 0004 00AF add r7, sp, #0 + 8433 .cfi_def_cfa_register 7 + 8434 0006 7860 str r0, [r7, #4] +2763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +2764:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** UNUSED(htim); +2765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* NOTE : This function should not be modified, when the callback is needed, +2767:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** the HAL_TIM_OnePulse_MspInit could be implemented in the user file +2768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +2769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 8435 .loc 1 2769 1 + 8436 0008 00BF nop + 8437 000a 0C37 adds r7, r7, #12 + 8438 .cfi_def_cfa_offset 4 + 8439 000c BD46 mov sp, r7 + 8440 .cfi_def_cfa_register 13 + 8441 @ sp needed + 8442 000e 5DF8047B ldr r7, [sp], #4 + 8443 .cfi_restore 7 + 8444 .cfi_def_cfa_offset 0 + 8445 0012 7047 bx lr + 8446 .cfi_endproc + 8447 .LFE172: + 8449 .section .text.HAL_TIM_OnePulse_MspDeInit,"ax",%progbits + 8450 .align 1 + 8451 .weak HAL_TIM_OnePulse_MspDeInit + 8452 .syntax unified + 8453 .thumb + 8454 .thumb_func + 8456 HAL_TIM_OnePulse_MspDeInit: + 8457 .LFB173: +2770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +2772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief DeInitializes TIM One Pulse MSP. +2773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM One Pulse handle + ARM GAS /tmp/ccl4b9YO.s page 197 + + +2774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval None +2775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +2776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) +2777:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 8458 .loc 1 2777 1 + 8459 .cfi_startproc + 8460 @ args = 0, pretend = 0, frame = 8 + 8461 @ frame_needed = 1, uses_anonymous_args = 0 + 8462 @ link register save eliminated. + 8463 0000 80B4 push {r7} + 8464 .cfi_def_cfa_offset 4 + 8465 .cfi_offset 7, -4 + 8466 0002 83B0 sub sp, sp, #12 + 8467 .cfi_def_cfa_offset 16 + 8468 0004 00AF add r7, sp, #0 + 8469 .cfi_def_cfa_register 7 + 8470 0006 7860 str r0, [r7, #4] +2778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +2779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** UNUSED(htim); +2780:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* NOTE : This function should not be modified, when the callback is needed, +2782:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file +2783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +2784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 8471 .loc 1 2784 1 + 8472 0008 00BF nop + 8473 000a 0C37 adds r7, r7, #12 + 8474 .cfi_def_cfa_offset 4 + 8475 000c BD46 mov sp, r7 + 8476 .cfi_def_cfa_register 13 + 8477 @ sp needed + 8478 000e 5DF8047B ldr r7, [sp], #4 + 8479 .cfi_restore 7 + 8480 .cfi_def_cfa_offset 0 + 8481 0012 7047 bx lr + 8482 .cfi_endproc + 8483 .LFE173: + 8485 .section .text.HAL_TIM_OnePulse_Start,"ax",%progbits + 8486 .align 1 + 8487 .global HAL_TIM_OnePulse_Start + 8488 .syntax unified + 8489 .thumb + 8490 .thumb_func + 8492 HAL_TIM_OnePulse_Start: + 8493 .LFB174: +2785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +2787:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Starts the TIM One Pulse signal generation. +2788:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @note Though OutputChannel parameter is deprecated and ignored by the function +2789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * it has been kept to avoid HAL_TIM API compatibility break. +2790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @note The pulse output channel is determined when calling +2791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @ref HAL_TIM_OnePulse_ConfigChannel(). +2792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM One Pulse handle +2793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param OutputChannel See note above +2794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status +2795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +2796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) + ARM GAS /tmp/ccl4b9YO.s page 198 + + +2797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 8494 .loc 1 2797 1 + 8495 .cfi_startproc + 8496 @ args = 0, pretend = 0, frame = 16 + 8497 @ frame_needed = 1, uses_anonymous_args = 0 + 8498 0000 80B5 push {r7, lr} + 8499 .cfi_def_cfa_offset 8 + 8500 .cfi_offset 7, -8 + 8501 .cfi_offset 14, -4 + 8502 0002 84B0 sub sp, sp, #16 + 8503 .cfi_def_cfa_offset 24 + 8504 0004 00AF add r7, sp, #0 + 8505 .cfi_def_cfa_register 7 + 8506 0006 7860 str r0, [r7, #4] + 8507 0008 3960 str r1, [r7] +2798:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + 8508 .loc 1 2798 31 + 8509 000a 7B68 ldr r3, [r7, #4] + 8510 000c 93F83E30 ldrb r3, [r3, #62] + 8511 0010 FB73 strb r3, [r7, #15] +2799:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + 8512 .loc 1 2799 31 + 8513 0012 7B68 ldr r3, [r7, #4] + 8514 0014 93F83F30 ldrb r3, [r3, #63] + 8515 0018 BB73 strb r3, [r7, #14] +2800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 8516 .loc 1 2800 31 + 8517 001a 7B68 ldr r3, [r7, #4] + 8518 001c 93F84430 ldrb r3, [r3, #68] + 8519 0020 7B73 strb r3, [r7, #13] +2801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 8520 .loc 1 2801 31 + 8521 0022 7B68 ldr r3, [r7, #4] + 8522 0024 93F84530 ldrb r3, [r3, #69] + 8523 0028 3B73 strb r3, [r7, #12] +2802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2803:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +2804:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** UNUSED(OutputChannel); +2805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2806:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the TIM channels state */ +2807:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + 8524 .loc 1 2807 6 + 8525 002a FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 8526 002c 012B cmp r3, #1 + 8527 002e 08D1 bne .L722 +2808:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + 8528 .loc 1 2808 7 + 8529 0030 BB7B ldrb r3, [r7, #14] @ zero_extendqisi2 + 8530 0032 012B cmp r3, #1 + 8531 0034 05D1 bne .L722 +2809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + 8532 .loc 1 2809 7 + 8533 0036 7B7B ldrb r3, [r7, #13] @ zero_extendqisi2 + 8534 0038 012B cmp r3, #1 + 8535 003a 02D1 bne .L722 +2810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + 8536 .loc 1 2810 7 + ARM GAS /tmp/ccl4b9YO.s page 199 + + + 8537 003c 3B7B ldrb r3, [r7, #12] @ zero_extendqisi2 + 8538 003e 012B cmp r3, #1 + 8539 0040 01D0 beq .L723 + 8540 .L722: +2811:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 8541 .loc 1 2812 12 + 8542 0042 0123 movs r3, #1 + 8543 0044 3FE0 b .L724 + 8544 .L723: +2813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2814:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the TIM channels state */ +2816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + 8545 .loc 1 2816 3 + 8546 0046 7B68 ldr r3, [r7, #4] + 8547 0048 0222 movs r2, #2 + 8548 004a 83F83E20 strb r2, [r3, #62] +2817:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 8549 .loc 1 2817 3 + 8550 004e 7B68 ldr r3, [r7, #4] + 8551 0050 0222 movs r2, #2 + 8552 0052 83F83F20 strb r2, [r3, #63] +2818:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + 8553 .loc 1 2818 3 + 8554 0056 7B68 ldr r3, [r7, #4] + 8555 0058 0222 movs r2, #2 + 8556 005a 83F84420 strb r2, [r3, #68] +2819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 8557 .loc 1 2819 3 + 8558 005e 7B68 ldr r3, [r7, #4] + 8559 0060 0222 movs r2, #2 + 8560 0062 83F84520 strb r2, [r3, #69] +2820:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2821:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the Capture compare and the Input Capture channels +2822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2 +2823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and +2824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output +2825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together +2826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2827:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** No need to enable the counter, it's enabled automatically by hardware +2828:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (the counter starts in response to a stimulus and generate a pulse */ +2829:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2830:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + 8561 .loc 1 2830 3 + 8562 0066 7B68 ldr r3, [r7, #4] + 8563 0068 1B68 ldr r3, [r3] + 8564 006a 0122 movs r2, #1 + 8565 006c 0021 movs r1, #0 + 8566 006e 1846 mov r0, r3 + 8567 0070 FFF7FEFF bl TIM_CCxChannelCmd +2831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + 8568 .loc 1 2831 3 + 8569 0074 7B68 ldr r3, [r7, #4] + 8570 0076 1B68 ldr r3, [r3] + 8571 0078 0122 movs r2, #1 + 8572 007a 0421 movs r1, #4 + ARM GAS /tmp/ccl4b9YO.s page 200 + + + 8573 007c 1846 mov r0, r3 + 8574 007e FFF7FEFF bl TIM_CCxChannelCmd +2832:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + 8575 .loc 1 2833 7 + 8576 0082 7B68 ldr r3, [r7, #4] + 8577 0084 1B68 ldr r3, [r3] + 8578 0086 124A ldr r2, .L729 + 8579 0088 9342 cmp r3, r2 + 8580 008a 0ED0 beq .L725 + 8581 .loc 1 2833 7 is_stmt 0 discriminator 2 + 8582 008c 7B68 ldr r3, [r7, #4] + 8583 008e 1B68 ldr r3, [r3] + 8584 0090 104A ldr r2, .L729+4 + 8585 0092 9342 cmp r3, r2 + 8586 0094 09D0 beq .L725 + 8587 .loc 1 2833 7 discriminator 4 + 8588 0096 7B68 ldr r3, [r7, #4] + 8589 0098 1B68 ldr r3, [r3] + 8590 009a 0F4A ldr r2, .L729+8 + 8591 009c 9342 cmp r3, r2 + 8592 009e 04D0 beq .L725 + 8593 .loc 1 2833 7 discriminator 6 + 8594 00a0 7B68 ldr r3, [r7, #4] + 8595 00a2 1B68 ldr r3, [r3] + 8596 00a4 0D4A ldr r2, .L729+12 + 8597 00a6 9342 cmp r3, r2 + 8598 00a8 01D1 bne .L726 + 8599 .L725: + 8600 .loc 1 2833 7 discriminator 7 + 8601 00aa 0123 movs r3, #1 + 8602 .loc 1 2833 7 + 8603 00ac 00E0 b .L727 + 8604 .L726: + 8605 .loc 1 2833 7 discriminator 8 + 8606 00ae 0023 movs r3, #0 + 8607 .L727: + 8608 .loc 1 2833 6 is_stmt 1 discriminator 10 + 8609 00b0 002B cmp r3, #0 + 8610 00b2 07D0 beq .L728 +2834:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2835:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the main output */ +2836:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_MOE_ENABLE(htim); + 8611 .loc 1 2836 5 + 8612 00b4 7B68 ldr r3, [r7, #4] + 8613 00b6 1B68 ldr r3, [r3] + 8614 00b8 5A6C ldr r2, [r3, #68] + 8615 00ba 7B68 ldr r3, [r7, #4] + 8616 00bc 1B68 ldr r3, [r3] + 8617 00be 42F40042 orr r2, r2, #32768 + 8618 00c2 5A64 str r2, [r3, #68] + 8619 .L728: +2837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return function status */ +2840:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_OK; + 8620 .loc 1 2840 10 + ARM GAS /tmp/ccl4b9YO.s page 201 + + + 8621 00c4 0023 movs r3, #0 + 8622 .L724: +2841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 8623 .loc 1 2841 1 + 8624 00c6 1846 mov r0, r3 + 8625 00c8 1037 adds r7, r7, #16 + 8626 .cfi_def_cfa_offset 8 + 8627 00ca BD46 mov sp, r7 + 8628 .cfi_def_cfa_register 13 + 8629 @ sp needed + 8630 00cc 80BD pop {r7, pc} + 8631 .L730: + 8632 00ce 00BF .align 2 + 8633 .L729: + 8634 00d0 002C0140 .word 1073818624 + 8635 00d4 00400140 .word 1073823744 + 8636 00d8 00440140 .word 1073824768 + 8637 00dc 00480140 .word 1073825792 + 8638 .cfi_endproc + 8639 .LFE174: + 8641 .section .text.HAL_TIM_OnePulse_Stop,"ax",%progbits + 8642 .align 1 + 8643 .global HAL_TIM_OnePulse_Stop + 8644 .syntax unified + 8645 .thumb + 8646 .thumb_func + 8648 HAL_TIM_OnePulse_Stop: + 8649 .LFB175: +2842:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2843:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +2844:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Stops the TIM One Pulse signal generation. +2845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @note Though OutputChannel parameter is deprecated and ignored by the function +2846:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * it has been kept to avoid HAL_TIM API compatibility break. +2847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @note The pulse output channel is determined when calling +2848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @ref HAL_TIM_OnePulse_ConfigChannel(). +2849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM One Pulse handle +2850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param OutputChannel See note above +2851:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status +2852:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +2853:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +2854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 8650 .loc 1 2854 1 + 8651 .cfi_startproc + 8652 @ args = 0, pretend = 0, frame = 8 + 8653 @ frame_needed = 1, uses_anonymous_args = 0 + 8654 0000 80B5 push {r7, lr} + 8655 .cfi_def_cfa_offset 8 + 8656 .cfi_offset 7, -8 + 8657 .cfi_offset 14, -4 + 8658 0002 82B0 sub sp, sp, #8 + 8659 .cfi_def_cfa_offset 16 + 8660 0004 00AF add r7, sp, #0 + 8661 .cfi_def_cfa_register 7 + 8662 0006 7860 str r0, [r7, #4] + 8663 0008 3960 str r1, [r7] +2855:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +2856:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** UNUSED(OutputChannel); + ARM GAS /tmp/ccl4b9YO.s page 202 + + +2857:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the Capture compare and the Input Capture channels +2859:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) +2860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and +2861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output +2862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ +2863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2864:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + 8664 .loc 1 2864 3 + 8665 000a 7B68 ldr r3, [r7, #4] + 8666 000c 1B68 ldr r3, [r3] + 8667 000e 0022 movs r2, #0 + 8668 0010 0021 movs r1, #0 + 8669 0012 1846 mov r0, r3 + 8670 0014 FFF7FEFF bl TIM_CCxChannelCmd +2865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + 8671 .loc 1 2865 3 + 8672 0018 7B68 ldr r3, [r7, #4] + 8673 001a 1B68 ldr r3, [r3] + 8674 001c 0022 movs r2, #0 + 8675 001e 0421 movs r1, #4 + 8676 0020 1846 mov r0, r3 + 8677 0022 FFF7FEFF bl TIM_CCxChannelCmd +2866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + 8678 .loc 1 2867 7 + 8679 0026 7B68 ldr r3, [r7, #4] + 8680 0028 1B68 ldr r3, [r3] + 8681 002a 2E4A ldr r2, .L738 + 8682 002c 9342 cmp r3, r2 + 8683 002e 0ED0 beq .L732 + 8684 .loc 1 2867 7 is_stmt 0 discriminator 2 + 8685 0030 7B68 ldr r3, [r7, #4] + 8686 0032 1B68 ldr r3, [r3] + 8687 0034 2C4A ldr r2, .L738+4 + 8688 0036 9342 cmp r3, r2 + 8689 0038 09D0 beq .L732 + 8690 .loc 1 2867 7 discriminator 4 + 8691 003a 7B68 ldr r3, [r7, #4] + 8692 003c 1B68 ldr r3, [r3] + 8693 003e 2B4A ldr r2, .L738+8 + 8694 0040 9342 cmp r3, r2 + 8695 0042 04D0 beq .L732 + 8696 .loc 1 2867 7 discriminator 6 + 8697 0044 7B68 ldr r3, [r7, #4] + 8698 0046 1B68 ldr r3, [r3] + 8699 0048 294A ldr r2, .L738+12 + 8700 004a 9342 cmp r3, r2 + 8701 004c 01D1 bne .L733 + 8702 .L732: + 8703 .loc 1 2867 7 discriminator 7 + 8704 004e 0123 movs r3, #1 + 8705 .loc 1 2867 7 + 8706 0050 00E0 b .L734 + 8707 .L733: + 8708 .loc 1 2867 7 discriminator 8 + 8709 0052 0023 movs r3, #0 + ARM GAS /tmp/ccl4b9YO.s page 203 + + + 8710 .L734: + 8711 .loc 1 2867 6 is_stmt 1 discriminator 10 + 8712 0054 002B cmp r3, #0 + 8713 0056 17D0 beq .L735 +2868:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the Main Output */ +2870:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_MOE_DISABLE(htim); + 8714 .loc 1 2870 5 + 8715 0058 7B68 ldr r3, [r7, #4] + 8716 005a 1B68 ldr r3, [r3] + 8717 005c 1A6A ldr r2, [r3, #32] + 8718 005e 41F21113 movw r3, #4369 + 8719 0062 1340 ands r3, r3, r2 + 8720 0064 002B cmp r3, #0 + 8721 0066 0FD1 bne .L735 + 8722 .loc 1 2870 5 is_stmt 0 discriminator 1 + 8723 0068 7B68 ldr r3, [r7, #4] + 8724 006a 1B68 ldr r3, [r3] + 8725 006c 1A6A ldr r2, [r3, #32] + 8726 006e 40F24443 movw r3, #1092 + 8727 0072 1340 ands r3, r3, r2 + 8728 0074 002B cmp r3, #0 + 8729 0076 07D1 bne .L735 + 8730 .loc 1 2870 5 discriminator 2 + 8731 0078 7B68 ldr r3, [r7, #4] + 8732 007a 1B68 ldr r3, [r3] + 8733 007c 5A6C ldr r2, [r3, #68] + 8734 007e 7B68 ldr r3, [r7, #4] + 8735 0080 1B68 ldr r3, [r3] + 8736 0082 22F40042 bic r2, r2, #32768 + 8737 0086 5A64 str r2, [r3, #68] + 8738 .L735: +2871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2873:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the Peripheral */ +2874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); + 8739 .loc 1 2874 3 is_stmt 1 + 8740 0088 7B68 ldr r3, [r7, #4] + 8741 008a 1B68 ldr r3, [r3] + 8742 008c 1A6A ldr r2, [r3, #32] + 8743 008e 41F21113 movw r3, #4369 + 8744 0092 1340 ands r3, r3, r2 + 8745 0094 002B cmp r3, #0 + 8746 0096 0FD1 bne .L736 + 8747 .loc 1 2874 3 is_stmt 0 discriminator 1 + 8748 0098 7B68 ldr r3, [r7, #4] + 8749 009a 1B68 ldr r3, [r3] + 8750 009c 1A6A ldr r2, [r3, #32] + 8751 009e 40F24443 movw r3, #1092 + 8752 00a2 1340 ands r3, r3, r2 + 8753 00a4 002B cmp r3, #0 + 8754 00a6 07D1 bne .L736 + 8755 .loc 1 2874 3 discriminator 2 + 8756 00a8 7B68 ldr r3, [r7, #4] + 8757 00aa 1B68 ldr r3, [r3] + 8758 00ac 1A68 ldr r2, [r3] + 8759 00ae 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/ccl4b9YO.s page 204 + + + 8760 00b0 1B68 ldr r3, [r3] + 8761 00b2 22F00102 bic r2, r2, #1 + 8762 00b6 1A60 str r2, [r3] + 8763 .L736: +2875:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the TIM channels state */ +2877:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 8764 .loc 1 2877 3 is_stmt 1 + 8765 00b8 7B68 ldr r3, [r7, #4] + 8766 00ba 0122 movs r2, #1 + 8767 00bc 83F83E20 strb r2, [r3, #62] +2878:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 8768 .loc 1 2878 3 + 8769 00c0 7B68 ldr r3, [r7, #4] + 8770 00c2 0122 movs r2, #1 + 8771 00c4 83F83F20 strb r2, [r3, #63] +2879:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 8772 .loc 1 2879 3 + 8773 00c8 7B68 ldr r3, [r7, #4] + 8774 00ca 0122 movs r2, #1 + 8775 00cc 83F84420 strb r2, [r3, #68] +2880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 8776 .loc 1 2880 3 + 8777 00d0 7B68 ldr r3, [r7, #4] + 8778 00d2 0122 movs r2, #1 + 8779 00d4 83F84520 strb r2, [r3, #69] +2881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return function status */ +2883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_OK; + 8780 .loc 1 2883 10 + 8781 00d8 0023 movs r3, #0 +2884:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 8782 .loc 1 2884 1 + 8783 00da 1846 mov r0, r3 + 8784 00dc 0837 adds r7, r7, #8 + 8785 .cfi_def_cfa_offset 8 + 8786 00de BD46 mov sp, r7 + 8787 .cfi_def_cfa_register 13 + 8788 @ sp needed + 8789 00e0 80BD pop {r7, pc} + 8790 .L739: + 8791 00e2 00BF .align 2 + 8792 .L738: + 8793 00e4 002C0140 .word 1073818624 + 8794 00e8 00400140 .word 1073823744 + 8795 00ec 00440140 .word 1073824768 + 8796 00f0 00480140 .word 1073825792 + 8797 .cfi_endproc + 8798 .LFE175: + 8800 .section .text.HAL_TIM_OnePulse_Start_IT,"ax",%progbits + 8801 .align 1 + 8802 .global HAL_TIM_OnePulse_Start_IT + 8803 .syntax unified + 8804 .thumb + 8805 .thumb_func + 8807 HAL_TIM_OnePulse_Start_IT: + 8808 .LFB176: + ARM GAS /tmp/ccl4b9YO.s page 205 + + +2885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +2887:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Starts the TIM One Pulse signal generation in interrupt mode. +2888:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @note Though OutputChannel parameter is deprecated and ignored by the function +2889:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * it has been kept to avoid HAL_TIM API compatibility break. +2890:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @note The pulse output channel is determined when calling +2891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @ref HAL_TIM_OnePulse_ConfigChannel(). +2892:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM One Pulse handle +2893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param OutputChannel See note above +2894:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status +2895:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +2896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +2897:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 8809 .loc 1 2897 1 + 8810 .cfi_startproc + 8811 @ args = 0, pretend = 0, frame = 16 + 8812 @ frame_needed = 1, uses_anonymous_args = 0 + 8813 0000 80B5 push {r7, lr} + 8814 .cfi_def_cfa_offset 8 + 8815 .cfi_offset 7, -8 + 8816 .cfi_offset 14, -4 + 8817 0002 84B0 sub sp, sp, #16 + 8818 .cfi_def_cfa_offset 24 + 8819 0004 00AF add r7, sp, #0 + 8820 .cfi_def_cfa_register 7 + 8821 0006 7860 str r0, [r7, #4] + 8822 0008 3960 str r1, [r7] +2898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + 8823 .loc 1 2898 31 + 8824 000a 7B68 ldr r3, [r7, #4] + 8825 000c 93F83E30 ldrb r3, [r3, #62] + 8826 0010 FB73 strb r3, [r7, #15] +2899:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + 8827 .loc 1 2899 31 + 8828 0012 7B68 ldr r3, [r7, #4] + 8829 0014 93F83F30 ldrb r3, [r3, #63] + 8830 0018 BB73 strb r3, [r7, #14] +2900:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 8831 .loc 1 2900 31 + 8832 001a 7B68 ldr r3, [r7, #4] + 8833 001c 93F84430 ldrb r3, [r3, #68] + 8834 0020 7B73 strb r3, [r7, #13] +2901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 8835 .loc 1 2901 31 + 8836 0022 7B68 ldr r3, [r7, #4] + 8837 0024 93F84530 ldrb r3, [r3, #69] + 8838 0028 3B73 strb r3, [r7, #12] +2902:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +2904:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** UNUSED(OutputChannel); +2905:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2906:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the TIM channels state */ +2907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + 8839 .loc 1 2907 6 + 8840 002a FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 8841 002c 012B cmp r3, #1 + 8842 002e 08D1 bne .L741 + ARM GAS /tmp/ccl4b9YO.s page 206 + + +2908:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + 8843 .loc 1 2908 7 + 8844 0030 BB7B ldrb r3, [r7, #14] @ zero_extendqisi2 + 8845 0032 012B cmp r3, #1 + 8846 0034 05D1 bne .L741 +2909:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + 8847 .loc 1 2909 7 + 8848 0036 7B7B ldrb r3, [r7, #13] @ zero_extendqisi2 + 8849 0038 012B cmp r3, #1 + 8850 003a 02D1 bne .L741 +2910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + 8851 .loc 1 2910 7 + 8852 003c 3B7B ldrb r3, [r7, #12] @ zero_extendqisi2 + 8853 003e 012B cmp r3, #1 + 8854 0040 01D0 beq .L742 + 8855 .L741: +2911:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 8856 .loc 1 2912 12 + 8857 0042 0123 movs r3, #1 + 8858 0044 4FE0 b .L743 + 8859 .L742: +2913:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2914:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2915:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the TIM channels state */ +2916:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + 8860 .loc 1 2916 3 + 8861 0046 7B68 ldr r3, [r7, #4] + 8862 0048 0222 movs r2, #2 + 8863 004a 83F83E20 strb r2, [r3, #62] +2917:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 8864 .loc 1 2917 3 + 8865 004e 7B68 ldr r3, [r7, #4] + 8866 0050 0222 movs r2, #2 + 8867 0052 83F83F20 strb r2, [r3, #63] +2918:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + 8868 .loc 1 2918 3 + 8869 0056 7B68 ldr r3, [r7, #4] + 8870 0058 0222 movs r2, #2 + 8871 005a 83F84420 strb r2, [r3, #68] +2919:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 8872 .loc 1 2919 3 + 8873 005e 7B68 ldr r3, [r7, #4] + 8874 0060 0222 movs r2, #2 + 8875 0062 83F84520 strb r2, [r3, #69] +2920:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the Capture compare and the Input Capture channels +2922:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2 +2923:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and +2924:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output +2925:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together +2926:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** No need to enable the counter, it's enabled automatically by hardware +2928:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (the counter starts in response to a stimulus and generate a pulse */ +2929:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2930:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the TIM Capture/Compare 1 interrupt */ +2931:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + ARM GAS /tmp/ccl4b9YO.s page 207 + + + 8876 .loc 1 2931 3 + 8877 0066 7B68 ldr r3, [r7, #4] + 8878 0068 1B68 ldr r3, [r3] + 8879 006a DA68 ldr r2, [r3, #12] + 8880 006c 7B68 ldr r3, [r7, #4] + 8881 006e 1B68 ldr r3, [r3] + 8882 0070 42F00202 orr r2, r2, #2 + 8883 0074 DA60 str r2, [r3, #12] +2932:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the TIM Capture/Compare 2 interrupt */ +2934:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + 8884 .loc 1 2934 3 + 8885 0076 7B68 ldr r3, [r7, #4] + 8886 0078 1B68 ldr r3, [r3] + 8887 007a DA68 ldr r2, [r3, #12] + 8888 007c 7B68 ldr r3, [r7, #4] + 8889 007e 1B68 ldr r3, [r3] + 8890 0080 42F00402 orr r2, r2, #4 + 8891 0084 DA60 str r2, [r3, #12] +2935:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2936:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + 8892 .loc 1 2936 3 + 8893 0086 7B68 ldr r3, [r7, #4] + 8894 0088 1B68 ldr r3, [r3] + 8895 008a 0122 movs r2, #1 + 8896 008c 0021 movs r1, #0 + 8897 008e 1846 mov r0, r3 + 8898 0090 FFF7FEFF bl TIM_CCxChannelCmd +2937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + 8899 .loc 1 2937 3 + 8900 0094 7B68 ldr r3, [r7, #4] + 8901 0096 1B68 ldr r3, [r3] + 8902 0098 0122 movs r2, #1 + 8903 009a 0421 movs r1, #4 + 8904 009c 1846 mov r0, r3 + 8905 009e FFF7FEFF bl TIM_CCxChannelCmd +2938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2939:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + 8906 .loc 1 2939 7 + 8907 00a2 7B68 ldr r3, [r7, #4] + 8908 00a4 1B68 ldr r3, [r3] + 8909 00a6 124A ldr r2, .L748 + 8910 00a8 9342 cmp r3, r2 + 8911 00aa 0ED0 beq .L744 + 8912 .loc 1 2939 7 is_stmt 0 discriminator 2 + 8913 00ac 7B68 ldr r3, [r7, #4] + 8914 00ae 1B68 ldr r3, [r3] + 8915 00b0 104A ldr r2, .L748+4 + 8916 00b2 9342 cmp r3, r2 + 8917 00b4 09D0 beq .L744 + 8918 .loc 1 2939 7 discriminator 4 + 8919 00b6 7B68 ldr r3, [r7, #4] + 8920 00b8 1B68 ldr r3, [r3] + 8921 00ba 0F4A ldr r2, .L748+8 + 8922 00bc 9342 cmp r3, r2 + 8923 00be 04D0 beq .L744 + 8924 .loc 1 2939 7 discriminator 6 + ARM GAS /tmp/ccl4b9YO.s page 208 + + + 8925 00c0 7B68 ldr r3, [r7, #4] + 8926 00c2 1B68 ldr r3, [r3] + 8927 00c4 0D4A ldr r2, .L748+12 + 8928 00c6 9342 cmp r3, r2 + 8929 00c8 01D1 bne .L745 + 8930 .L744: + 8931 .loc 1 2939 7 discriminator 7 + 8932 00ca 0123 movs r3, #1 + 8933 .loc 1 2939 7 + 8934 00cc 00E0 b .L746 + 8935 .L745: + 8936 .loc 1 2939 7 discriminator 8 + 8937 00ce 0023 movs r3, #0 + 8938 .L746: + 8939 .loc 1 2939 6 is_stmt 1 discriminator 10 + 8940 00d0 002B cmp r3, #0 + 8941 00d2 07D0 beq .L747 +2940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2941:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the main output */ +2942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_MOE_ENABLE(htim); + 8942 .loc 1 2942 5 + 8943 00d4 7B68 ldr r3, [r7, #4] + 8944 00d6 1B68 ldr r3, [r3] + 8945 00d8 5A6C ldr r2, [r3, #68] + 8946 00da 7B68 ldr r3, [r7, #4] + 8947 00dc 1B68 ldr r3, [r3] + 8948 00de 42F40042 orr r2, r2, #32768 + 8949 00e2 5A64 str r2, [r3, #68] + 8950 .L747: +2943:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2944:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return function status */ +2946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_OK; + 8951 .loc 1 2946 10 + 8952 00e4 0023 movs r3, #0 + 8953 .L743: +2947:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 8954 .loc 1 2947 1 + 8955 00e6 1846 mov r0, r3 + 8956 00e8 1037 adds r7, r7, #16 + 8957 .cfi_def_cfa_offset 8 + 8958 00ea BD46 mov sp, r7 + 8959 .cfi_def_cfa_register 13 + 8960 @ sp needed + 8961 00ec 80BD pop {r7, pc} + 8962 .L749: + 8963 00ee 00BF .align 2 + 8964 .L748: + 8965 00f0 002C0140 .word 1073818624 + 8966 00f4 00400140 .word 1073823744 + 8967 00f8 00440140 .word 1073824768 + 8968 00fc 00480140 .word 1073825792 + 8969 .cfi_endproc + 8970 .LFE176: + 8972 .section .text.HAL_TIM_OnePulse_Stop_IT,"ax",%progbits + 8973 .align 1 + 8974 .global HAL_TIM_OnePulse_Stop_IT + ARM GAS /tmp/ccl4b9YO.s page 209 + + + 8975 .syntax unified + 8976 .thumb + 8977 .thumb_func + 8979 HAL_TIM_OnePulse_Stop_IT: + 8980 .LFB177: +2948:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +2950:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Stops the TIM One Pulse signal generation in interrupt mode. +2951:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @note Though OutputChannel parameter is deprecated and ignored by the function +2952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * it has been kept to avoid HAL_TIM API compatibility break. +2953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @note The pulse output channel is determined when calling +2954:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @ref HAL_TIM_OnePulse_ConfigChannel(). +2955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM One Pulse handle +2956:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param OutputChannel See note above +2957:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status +2958:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +2959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +2960:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 8981 .loc 1 2960 1 + 8982 .cfi_startproc + 8983 @ args = 0, pretend = 0, frame = 8 + 8984 @ frame_needed = 1, uses_anonymous_args = 0 + 8985 0000 80B5 push {r7, lr} + 8986 .cfi_def_cfa_offset 8 + 8987 .cfi_offset 7, -8 + 8988 .cfi_offset 14, -4 + 8989 0002 82B0 sub sp, sp, #8 + 8990 .cfi_def_cfa_offset 16 + 8991 0004 00AF add r7, sp, #0 + 8992 .cfi_def_cfa_register 7 + 8993 0006 7860 str r0, [r7, #4] + 8994 0008 3960 str r1, [r7] +2961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +2962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** UNUSED(OutputChannel); +2963:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2964:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the TIM Capture/Compare 1 interrupt */ +2965:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + 8995 .loc 1 2965 3 + 8996 000a 7B68 ldr r3, [r7, #4] + 8997 000c 1B68 ldr r3, [r3] + 8998 000e DA68 ldr r2, [r3, #12] + 8999 0010 7B68 ldr r3, [r7, #4] + 9000 0012 1B68 ldr r3, [r3] + 9001 0014 22F00202 bic r2, r2, #2 + 9002 0018 DA60 str r2, [r3, #12] +2966:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2967:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the TIM Capture/Compare 2 interrupt */ +2968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + 9003 .loc 1 2968 3 + 9004 001a 7B68 ldr r3, [r7, #4] + 9005 001c 1B68 ldr r3, [r3] + 9006 001e DA68 ldr r2, [r3, #12] + 9007 0020 7B68 ldr r3, [r7, #4] + 9008 0022 1B68 ldr r3, [r3] + 9009 0024 22F00402 bic r2, r2, #4 + 9010 0028 DA60 str r2, [r3, #12] +2969:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + ARM GAS /tmp/ccl4b9YO.s page 210 + + +2970:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the Capture compare and the Input Capture channels +2971:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) +2972:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and +2973:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output +2974:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ +2975:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + 9011 .loc 1 2975 3 + 9012 002a 7B68 ldr r3, [r7, #4] + 9013 002c 1B68 ldr r3, [r3] + 9014 002e 0022 movs r2, #0 + 9015 0030 0021 movs r1, #0 + 9016 0032 1846 mov r0, r3 + 9017 0034 FFF7FEFF bl TIM_CCxChannelCmd +2976:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + 9018 .loc 1 2976 3 + 9019 0038 7B68 ldr r3, [r7, #4] + 9020 003a 1B68 ldr r3, [r3] + 9021 003c 0022 movs r2, #0 + 9022 003e 0421 movs r1, #4 + 9023 0040 1846 mov r0, r3 + 9024 0042 FFF7FEFF bl TIM_CCxChannelCmd +2977:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2978:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + 9025 .loc 1 2978 7 + 9026 0046 7B68 ldr r3, [r7, #4] + 9027 0048 1B68 ldr r3, [r3] + 9028 004a 2E4A ldr r2, .L757 + 9029 004c 9342 cmp r3, r2 + 9030 004e 0ED0 beq .L751 + 9031 .loc 1 2978 7 is_stmt 0 discriminator 2 + 9032 0050 7B68 ldr r3, [r7, #4] + 9033 0052 1B68 ldr r3, [r3] + 9034 0054 2C4A ldr r2, .L757+4 + 9035 0056 9342 cmp r3, r2 + 9036 0058 09D0 beq .L751 + 9037 .loc 1 2978 7 discriminator 4 + 9038 005a 7B68 ldr r3, [r7, #4] + 9039 005c 1B68 ldr r3, [r3] + 9040 005e 2B4A ldr r2, .L757+8 + 9041 0060 9342 cmp r3, r2 + 9042 0062 04D0 beq .L751 + 9043 .loc 1 2978 7 discriminator 6 + 9044 0064 7B68 ldr r3, [r7, #4] + 9045 0066 1B68 ldr r3, [r3] + 9046 0068 294A ldr r2, .L757+12 + 9047 006a 9342 cmp r3, r2 + 9048 006c 01D1 bne .L752 + 9049 .L751: + 9050 .loc 1 2978 7 discriminator 7 + 9051 006e 0123 movs r3, #1 + 9052 .loc 1 2978 7 + 9053 0070 00E0 b .L753 + 9054 .L752: + 9055 .loc 1 2978 7 discriminator 8 + 9056 0072 0023 movs r3, #0 + 9057 .L753: + 9058 .loc 1 2978 6 is_stmt 1 discriminator 10 + ARM GAS /tmp/ccl4b9YO.s page 211 + + + 9059 0074 002B cmp r3, #0 + 9060 0076 17D0 beq .L754 +2979:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +2980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the Main Output */ +2981:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_MOE_DISABLE(htim); + 9061 .loc 1 2981 5 + 9062 0078 7B68 ldr r3, [r7, #4] + 9063 007a 1B68 ldr r3, [r3] + 9064 007c 1A6A ldr r2, [r3, #32] + 9065 007e 41F21113 movw r3, #4369 + 9066 0082 1340 ands r3, r3, r2 + 9067 0084 002B cmp r3, #0 + 9068 0086 0FD1 bne .L754 + 9069 .loc 1 2981 5 is_stmt 0 discriminator 1 + 9070 0088 7B68 ldr r3, [r7, #4] + 9071 008a 1B68 ldr r3, [r3] + 9072 008c 1A6A ldr r2, [r3, #32] + 9073 008e 40F24443 movw r3, #1092 + 9074 0092 1340 ands r3, r3, r2 + 9075 0094 002B cmp r3, #0 + 9076 0096 07D1 bne .L754 + 9077 .loc 1 2981 5 discriminator 2 + 9078 0098 7B68 ldr r3, [r7, #4] + 9079 009a 1B68 ldr r3, [r3] + 9080 009c 5A6C ldr r2, [r3, #68] + 9081 009e 7B68 ldr r3, [r7, #4] + 9082 00a0 1B68 ldr r3, [r3] + 9083 00a2 22F40042 bic r2, r2, #32768 + 9084 00a6 5A64 str r2, [r3, #68] + 9085 .L754: +2982:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +2983:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the Peripheral */ +2985:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); + 9086 .loc 1 2985 3 is_stmt 1 + 9087 00a8 7B68 ldr r3, [r7, #4] + 9088 00aa 1B68 ldr r3, [r3] + 9089 00ac 1A6A ldr r2, [r3, #32] + 9090 00ae 41F21113 movw r3, #4369 + 9091 00b2 1340 ands r3, r3, r2 + 9092 00b4 002B cmp r3, #0 + 9093 00b6 0FD1 bne .L755 + 9094 .loc 1 2985 3 is_stmt 0 discriminator 1 + 9095 00b8 7B68 ldr r3, [r7, #4] + 9096 00ba 1B68 ldr r3, [r3] + 9097 00bc 1A6A ldr r2, [r3, #32] + 9098 00be 40F24443 movw r3, #1092 + 9099 00c2 1340 ands r3, r3, r2 + 9100 00c4 002B cmp r3, #0 + 9101 00c6 07D1 bne .L755 + 9102 .loc 1 2985 3 discriminator 2 + 9103 00c8 7B68 ldr r3, [r7, #4] + 9104 00ca 1B68 ldr r3, [r3] + 9105 00cc 1A68 ldr r2, [r3] + 9106 00ce 7B68 ldr r3, [r7, #4] + 9107 00d0 1B68 ldr r3, [r3] + 9108 00d2 22F00102 bic r2, r2, #1 + ARM GAS /tmp/ccl4b9YO.s page 212 + + + 9109 00d6 1A60 str r2, [r3] + 9110 .L755: +2986:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2987:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the TIM channels state */ +2988:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 9111 .loc 1 2988 3 is_stmt 1 + 9112 00d8 7B68 ldr r3, [r7, #4] + 9113 00da 0122 movs r2, #1 + 9114 00dc 83F83E20 strb r2, [r3, #62] +2989:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 9115 .loc 1 2989 3 + 9116 00e0 7B68 ldr r3, [r7, #4] + 9117 00e2 0122 movs r2, #1 + 9118 00e4 83F83F20 strb r2, [r3, #63] +2990:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 9119 .loc 1 2990 3 + 9120 00e8 7B68 ldr r3, [r7, #4] + 9121 00ea 0122 movs r2, #1 + 9122 00ec 83F84420 strb r2, [r3, #68] +2991:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 9123 .loc 1 2991 3 + 9124 00f0 7B68 ldr r3, [r7, #4] + 9125 00f2 0122 movs r2, #1 + 9126 00f4 83F84520 strb r2, [r3, #69] +2992:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2993:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return function status */ +2994:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_OK; + 9127 .loc 1 2994 10 + 9128 00f8 0023 movs r3, #0 +2995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 9129 .loc 1 2995 1 + 9130 00fa 1846 mov r0, r3 + 9131 00fc 0837 adds r7, r7, #8 + 9132 .cfi_def_cfa_offset 8 + 9133 00fe BD46 mov sp, r7 + 9134 .cfi_def_cfa_register 13 + 9135 @ sp needed + 9136 0100 80BD pop {r7, pc} + 9137 .L758: + 9138 0102 00BF .align 2 + 9139 .L757: + 9140 0104 002C0140 .word 1073818624 + 9141 0108 00400140 .word 1073823744 + 9142 010c 00440140 .word 1073824768 + 9143 0110 00480140 .word 1073825792 + 9144 .cfi_endproc + 9145 .LFE177: + 9147 .section .text.HAL_TIM_Encoder_Init,"ax",%progbits + 9148 .align 1 + 9149 .global HAL_TIM_Encoder_Init + 9150 .syntax unified + 9151 .thumb + 9152 .thumb_func + 9154 HAL_TIM_Encoder_Init: + 9155 .LFB178: +2996:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +2997:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** + ARM GAS /tmp/ccl4b9YO.s page 213 + + +2998:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @} +2999:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +3000:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3001:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions +3002:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief TIM Encoder functions +3003:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * +3004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** @verbatim +3005:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** ============================================================================== +3006:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** ##### TIM Encoder functions ##### +3007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** ============================================================================== +3008:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** [..] +3009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** This section provides functions allowing to: +3010:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Initialize and configure the TIM Encoder. +3011:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) De-initialize the TIM Encoder. +3012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Start the TIM Encoder. +3013:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Stop the TIM Encoder. +3014:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Start the TIM Encoder and enable interrupt. +3015:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Stop the TIM Encoder and disable interrupt. +3016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Start the TIM Encoder and enable DMA transfer. +3017:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Stop the TIM Encoder and disable DMA transfer. +3018:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3019:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** @endverbatim +3020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @{ +3021:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +3022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +3023:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Initializes the TIM Encoder Interface and initialize the associated handle. +3024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) +3025:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * requires a timer reset to avoid unexpected direction +3026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * due to DIR bit readonly in center aligned mode. +3027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init() +3028:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @note Encoder mode and External clock mode 2 are not compatible and must not be selected toge +3029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_Config +3030:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa +3031:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @note When the timer instance is initialized in Encoder mode, timer +3032:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * channels 1 and channel 2 are reserved and cannot be used for other +3033:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * purpose. +3034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM Encoder Interface handle +3035:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param sConfig TIM Encoder Interface configuration structure +3036:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status +3037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +3038:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sCon +3039:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 9156 .loc 1 3039 1 + 9157 .cfi_startproc + 9158 @ args = 0, pretend = 0, frame = 24 + 9159 @ frame_needed = 1, uses_anonymous_args = 0 + 9160 0000 80B5 push {r7, lr} + 9161 .cfi_def_cfa_offset 8 + 9162 .cfi_offset 7, -8 + 9163 .cfi_offset 14, -4 + 9164 0002 86B0 sub sp, sp, #24 + 9165 .cfi_def_cfa_offset 32 + 9166 0004 00AF add r7, sp, #0 + 9167 .cfi_def_cfa_register 7 + 9168 0006 7860 str r0, [r7, #4] + 9169 0008 3960 str r1, [r7] +3040:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpsmcr; + ARM GAS /tmp/ccl4b9YO.s page 214 + + +3041:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpccmr1; +3042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpccer; +3043:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the TIM handle allocation */ +3045:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (htim == NULL) + 9170 .loc 1 3045 6 + 9171 000a 7B68 ldr r3, [r7, #4] + 9172 000c 002B cmp r3, #0 + 9173 000e 01D1 bne .L760 +3046:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 9174 .loc 1 3047 12 + 9175 0010 0123 movs r3, #1 + 9176 0012 97E0 b .L761 + 9177 .L760: +3048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3049:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3050:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +3051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); +3052:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); +3053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); +3054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); +3055:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); +3056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); +3057:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); +3058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity)); +3059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity)); +3060:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); +3061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); +3062:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); +3063:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); +3064:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); +3065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3066:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (htim->State == HAL_TIM_STATE_RESET) + 9178 .loc 1 3066 11 + 9179 0014 7B68 ldr r3, [r7, #4] + 9180 0016 93F83D30 ldrb r3, [r3, #61] + 9181 001a DBB2 uxtb r3, r3 + 9182 .loc 1 3066 6 + 9183 001c 002B cmp r3, #0 + 9184 001e 06D1 bne .L762 +3067:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Allocate lock resource and initialize it */ +3069:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Lock = HAL_UNLOCKED; + 9185 .loc 1 3069 16 + 9186 0020 7B68 ldr r3, [r7, #4] + 9187 0022 0022 movs r2, #0 + 9188 0024 83F83C20 strb r2, [r3, #60] +3070:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +3072:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Reset interrupt callbacks to legacy weak callbacks */ +3073:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_ResetCallback(htim); +3074:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3075:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (htim->Encoder_MspInitCallback == NULL) +3076:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3077:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; +3078:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + ARM GAS /tmp/ccl4b9YO.s page 215 + + +3079:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Init the low level hardware : GPIO, CLOCK, NVIC */ +3080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Encoder_MspInitCallback(htim); +3081:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #else +3082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ +3083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_Encoder_MspInit(htim); + 9189 .loc 1 3083 5 + 9190 0028 7868 ldr r0, [r7, #4] + 9191 002a FFF7FEFF bl HAL_TIM_Encoder_MspInit + 9192 .L762: +3084:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +3085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3086:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3087:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the TIM state */ +3088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; + 9193 .loc 1 3088 15 + 9194 002e 7B68 ldr r3, [r7, #4] + 9195 0030 0222 movs r2, #2 + 9196 0032 83F83D20 strb r2, [r3, #61] +3089:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3090:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Reset the SMS and ECE bits */ +3091:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); + 9197 .loc 1 3091 7 + 9198 0036 7B68 ldr r3, [r7, #4] + 9199 0038 1B68 ldr r3, [r3] + 9200 .loc 1 3091 17 + 9201 003a 9B68 ldr r3, [r3, #8] + 9202 .loc 1 3091 7 + 9203 003c 7A68 ldr r2, [r7, #4] + 9204 003e 1268 ldr r2, [r2] + 9205 .loc 1 3091 24 + 9206 0040 23F4A033 bic r3, r3, #81920 + 9207 0044 23F00703 bic r3, r3, #7 + 9208 0048 9360 str r3, [r2, #8] +3092:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3093:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Configure the Time base in the Encoder Mode */ +3094:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_Base_SetConfig(htim->Instance, &htim->Init); + 9209 .loc 1 3094 3 + 9210 004a 7B68 ldr r3, [r7, #4] + 9211 004c 1A68 ldr r2, [r3] + 9212 .loc 1 3094 38 + 9213 004e 7B68 ldr r3, [r7, #4] + 9214 0050 0433 adds r3, r3, #4 + 9215 .loc 1 3094 3 + 9216 0052 1946 mov r1, r3 + 9217 0054 1046 mov r0, r2 + 9218 0056 FFF7FEFF bl TIM_Base_SetConfig +3095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3096:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Get the TIMx SMCR register value */ +3097:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpsmcr = htim->Instance->SMCR; + 9219 .loc 1 3097 17 + 9220 005a 7B68 ldr r3, [r7, #4] + 9221 005c 1B68 ldr r3, [r3] + 9222 .loc 1 3097 11 + 9223 005e 9B68 ldr r3, [r3, #8] + 9224 0060 7B61 str r3, [r7, #20] +3098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3099:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Get the TIMx CCMR1 register value */ + ARM GAS /tmp/ccl4b9YO.s page 216 + + +3100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmr1 = htim->Instance->CCMR1; + 9225 .loc 1 3100 18 + 9226 0062 7B68 ldr r3, [r7, #4] + 9227 0064 1B68 ldr r3, [r3] + 9228 .loc 1 3100 12 + 9229 0066 9B69 ldr r3, [r3, #24] + 9230 0068 3B61 str r3, [r7, #16] +3101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Get the TIMx CCER register value */ +3103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccer = htim->Instance->CCER; + 9231 .loc 1 3103 17 + 9232 006a 7B68 ldr r3, [r7, #4] + 9233 006c 1B68 ldr r3, [r3] + 9234 .loc 1 3103 11 + 9235 006e 1B6A ldr r3, [r3, #32] + 9236 0070 FB60 str r3, [r7, #12] +3104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the encoder Mode */ +3106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpsmcr |= sConfig->EncoderMode; + 9237 .loc 1 3106 21 + 9238 0072 3B68 ldr r3, [r7] + 9239 0074 1B68 ldr r3, [r3] + 9240 .loc 1 3106 11 + 9241 0076 7A69 ldr r2, [r7, #20] + 9242 0078 1343 orrs r3, r3, r2 + 9243 007a 7B61 str r3, [r7, #20] +3107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Select the Capture Compare 1 and the Capture Compare 2 as input */ +3109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); + 9244 .loc 1 3109 12 + 9245 007c 3B69 ldr r3, [r7, #16] + 9246 007e 23F44073 bic r3, r3, #768 + 9247 0082 23F00303 bic r3, r3, #3 + 9248 0086 3B61 str r3, [r7, #16] +3110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); + 9249 .loc 1 3110 23 + 9250 0088 3B68 ldr r3, [r7] + 9251 008a 9A68 ldr r2, [r3, #8] + 9252 .loc 1 3110 48 + 9253 008c 3B68 ldr r3, [r7] + 9254 008e 9B69 ldr r3, [r3, #24] + 9255 .loc 1 3110 63 + 9256 0090 1B02 lsls r3, r3, #8 + 9257 .loc 1 3110 38 + 9258 0092 1343 orrs r3, r3, r2 + 9259 .loc 1 3110 12 + 9260 0094 3A69 ldr r2, [r7, #16] + 9261 0096 1343 orrs r3, r3, r2 + 9262 0098 3B61 str r3, [r7, #16] +3111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ +3113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); + 9263 .loc 1 3113 12 + 9264 009a 3B69 ldr r3, [r7, #16] + 9265 009c 23F44063 bic r3, r3, #3072 + 9266 00a0 23F00C03 bic r3, r3, #12 + 9267 00a4 3B61 str r3, [r7, #16] + ARM GAS /tmp/ccl4b9YO.s page 217 + + +3114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); + 9268 .loc 1 3114 12 + 9269 00a6 3B69 ldr r3, [r7, #16] + 9270 00a8 23F47043 bic r3, r3, #61440 + 9271 00ac 23F0F003 bic r3, r3, #240 + 9272 00b0 3B61 str r3, [r7, #16] +3115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); + 9273 .loc 1 3115 22 + 9274 00b2 3B68 ldr r3, [r7] + 9275 00b4 DA68 ldr r2, [r3, #12] + 9276 .loc 1 3115 47 + 9277 00b6 3B68 ldr r3, [r7] + 9278 00b8 DB69 ldr r3, [r3, #28] + 9279 .loc 1 3115 62 + 9280 00ba 1B02 lsls r3, r3, #8 + 9281 .loc 1 3115 37 + 9282 00bc 1343 orrs r3, r3, r2 + 9283 .loc 1 3115 12 + 9284 00be 3A69 ldr r2, [r7, #16] + 9285 00c0 1343 orrs r3, r3, r2 + 9286 00c2 3B61 str r3, [r7, #16] +3116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); + 9287 .loc 1 3116 23 + 9288 00c4 3B68 ldr r3, [r7] + 9289 00c6 1B69 ldr r3, [r3, #16] + 9290 .loc 1 3116 35 + 9291 00c8 1A01 lsls r2, r3, #4 + 9292 .loc 1 3116 52 + 9293 00ca 3B68 ldr r3, [r7] + 9294 00cc 1B6A ldr r3, [r3, #32] + 9295 .loc 1 3116 64 + 9296 00ce 1B03 lsls r3, r3, #12 + 9297 .loc 1 3116 42 + 9298 00d0 1343 orrs r3, r3, r2 + 9299 .loc 1 3116 12 + 9300 00d2 3A69 ldr r2, [r7, #16] + 9301 00d4 1343 orrs r3, r3, r2 + 9302 00d6 3B61 str r3, [r7, #16] +3117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the TI1 and the TI2 Polarities */ +3119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); + 9303 .loc 1 3119 11 + 9304 00d8 FB68 ldr r3, [r7, #12] + 9305 00da 23F02203 bic r3, r3, #34 + 9306 00de FB60 str r3, [r7, #12] +3120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); + 9307 .loc 1 3120 11 + 9308 00e0 FB68 ldr r3, [r7, #12] + 9309 00e2 23F08803 bic r3, r3, #136 + 9310 00e6 FB60 str r3, [r7, #12] +3121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); + 9311 .loc 1 3121 21 + 9312 00e8 3B68 ldr r3, [r7] + 9313 00ea 5A68 ldr r2, [r3, #4] + 9314 .loc 1 3121 45 + 9315 00ec 3B68 ldr r3, [r7] + 9316 00ee 5B69 ldr r3, [r3, #20] + ARM GAS /tmp/ccl4b9YO.s page 218 + + + 9317 .loc 1 3121 59 + 9318 00f0 1B01 lsls r3, r3, #4 + 9319 .loc 1 3121 35 + 9320 00f2 1343 orrs r3, r3, r2 + 9321 .loc 1 3121 11 + 9322 00f4 FA68 ldr r2, [r7, #12] + 9323 00f6 1343 orrs r3, r3, r2 + 9324 00f8 FB60 str r3, [r7, #12] +3122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Write to TIMx SMCR */ +3124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->SMCR = tmpsmcr; + 9325 .loc 1 3124 7 + 9326 00fa 7B68 ldr r3, [r7, #4] + 9327 00fc 1B68 ldr r3, [r3] + 9328 .loc 1 3124 24 + 9329 00fe 7A69 ldr r2, [r7, #20] + 9330 0100 9A60 str r2, [r3, #8] +3125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Write to TIMx CCMR1 */ +3127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->CCMR1 = tmpccmr1; + 9331 .loc 1 3127 7 + 9332 0102 7B68 ldr r3, [r7, #4] + 9333 0104 1B68 ldr r3, [r3] + 9334 .loc 1 3127 25 + 9335 0106 3A69 ldr r2, [r7, #16] + 9336 0108 9A61 str r2, [r3, #24] +3128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Write to TIMx CCER */ +3130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->CCER = tmpccer; + 9337 .loc 1 3130 7 + 9338 010a 7B68 ldr r3, [r7, #4] + 9339 010c 1B68 ldr r3, [r3] + 9340 .loc 1 3130 24 + 9341 010e FA68 ldr r2, [r7, #12] + 9342 0110 1A62 str r2, [r3, #32] +3131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Initialize the DMA burst operation state */ +3133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + 9343 .loc 1 3133 23 + 9344 0112 7B68 ldr r3, [r7, #4] + 9345 0114 0122 movs r2, #1 + 9346 0116 83F84820 strb r2, [r3, #72] +3134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the TIM channels state */ +3136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 9347 .loc 1 3136 3 + 9348 011a 7B68 ldr r3, [r7, #4] + 9349 011c 0122 movs r2, #1 + 9350 011e 83F83E20 strb r2, [r3, #62] +3137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 9351 .loc 1 3137 3 + 9352 0122 7B68 ldr r3, [r7, #4] + 9353 0124 0122 movs r2, #1 + 9354 0126 83F83F20 strb r2, [r3, #63] +3138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 9355 .loc 1 3138 3 + 9356 012a 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/ccl4b9YO.s page 219 + + + 9357 012c 0122 movs r2, #1 + 9358 012e 83F84420 strb r2, [r3, #68] +3139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 9359 .loc 1 3139 3 + 9360 0132 7B68 ldr r3, [r7, #4] + 9361 0134 0122 movs r2, #1 + 9362 0136 83F84520 strb r2, [r3, #69] +3140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Initialize the TIM state*/ +3142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; + 9363 .loc 1 3142 15 + 9364 013a 7B68 ldr r3, [r7, #4] + 9365 013c 0122 movs r2, #1 + 9366 013e 83F83D20 strb r2, [r3, #61] +3143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_OK; + 9367 .loc 1 3144 10 + 9368 0142 0023 movs r3, #0 + 9369 .L761: +3145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 9370 .loc 1 3145 1 + 9371 0144 1846 mov r0, r3 + 9372 0146 1837 adds r7, r7, #24 + 9373 .cfi_def_cfa_offset 8 + 9374 0148 BD46 mov sp, r7 + 9375 .cfi_def_cfa_register 13 + 9376 @ sp needed + 9377 014a 80BD pop {r7, pc} + 9378 .cfi_endproc + 9379 .LFE178: + 9381 .section .text.HAL_TIM_Encoder_DeInit,"ax",%progbits + 9382 .align 1 + 9383 .global HAL_TIM_Encoder_DeInit + 9384 .syntax unified + 9385 .thumb + 9386 .thumb_func + 9388 HAL_TIM_Encoder_DeInit: + 9389 .LFB179: +3146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +3149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief DeInitializes the TIM Encoder interface +3150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM Encoder Interface handle +3151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status +3152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +3153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) +3154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 9390 .loc 1 3154 1 + 9391 .cfi_startproc + 9392 @ args = 0, pretend = 0, frame = 8 + 9393 @ frame_needed = 1, uses_anonymous_args = 0 + 9394 0000 80B5 push {r7, lr} + 9395 .cfi_def_cfa_offset 8 + 9396 .cfi_offset 7, -8 + 9397 .cfi_offset 14, -4 + 9398 0002 82B0 sub sp, sp, #8 + 9399 .cfi_def_cfa_offset 16 + ARM GAS /tmp/ccl4b9YO.s page 220 + + + 9400 0004 00AF add r7, sp, #0 + 9401 .cfi_def_cfa_register 7 + 9402 0006 7860 str r0, [r7, #4] +3155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +3156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_INSTANCE(htim->Instance)); +3157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; + 9403 .loc 1 3158 15 + 9404 0008 7B68 ldr r3, [r7, #4] + 9405 000a 0222 movs r2, #2 + 9406 000c 83F83D20 strb r2, [r3, #61] +3159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the TIM Peripheral Clock */ +3161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); + 9407 .loc 1 3161 3 + 9408 0010 7B68 ldr r3, [r7, #4] + 9409 0012 1B68 ldr r3, [r3] + 9410 0014 1A6A ldr r2, [r3, #32] + 9411 0016 41F21113 movw r3, #4369 + 9412 001a 1340 ands r3, r3, r2 + 9413 001c 002B cmp r3, #0 + 9414 001e 0FD1 bne .L764 + 9415 .loc 1 3161 3 is_stmt 0 discriminator 1 + 9416 0020 7B68 ldr r3, [r7, #4] + 9417 0022 1B68 ldr r3, [r3] + 9418 0024 1A6A ldr r2, [r3, #32] + 9419 0026 40F24443 movw r3, #1092 + 9420 002a 1340 ands r3, r3, r2 + 9421 002c 002B cmp r3, #0 + 9422 002e 07D1 bne .L764 + 9423 .loc 1 3161 3 discriminator 2 + 9424 0030 7B68 ldr r3, [r7, #4] + 9425 0032 1B68 ldr r3, [r3] + 9426 0034 1A68 ldr r2, [r3] + 9427 0036 7B68 ldr r3, [r7, #4] + 9428 0038 1B68 ldr r3, [r3] + 9429 003a 22F00102 bic r2, r2, #1 + 9430 003e 1A60 str r2, [r3] + 9431 .L764: +3162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +3164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (htim->Encoder_MspDeInitCallback == NULL) +3165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; +3167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* DeInit the low level hardware */ +3169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Encoder_MspDeInitCallback(htim); +3170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #else +3171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ +3172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_Encoder_MspDeInit(htim); + 9432 .loc 1 3172 3 is_stmt 1 + 9433 0040 7868 ldr r0, [r7, #4] + 9434 0042 FFF7FEFF bl HAL_TIM_Encoder_MspDeInit +3173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +3174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Change the DMA burst operation state */ +3176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + ARM GAS /tmp/ccl4b9YO.s page 221 + + + 9435 .loc 1 3176 23 + 9436 0046 7B68 ldr r3, [r7, #4] + 9437 0048 0022 movs r2, #0 + 9438 004a 83F84820 strb r2, [r3, #72] +3177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the TIM channels state */ +3179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + 9439 .loc 1 3179 3 + 9440 004e 7B68 ldr r3, [r7, #4] + 9441 0050 0022 movs r2, #0 + 9442 0052 83F83E20 strb r2, [r3, #62] +3180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + 9443 .loc 1 3180 3 + 9444 0056 7B68 ldr r3, [r7, #4] + 9445 0058 0022 movs r2, #0 + 9446 005a 83F83F20 strb r2, [r3, #63] +3181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + 9447 .loc 1 3181 3 + 9448 005e 7B68 ldr r3, [r7, #4] + 9449 0060 0022 movs r2, #0 + 9450 0062 83F84420 strb r2, [r3, #68] +3182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + 9451 .loc 1 3182 3 + 9452 0066 7B68 ldr r3, [r7, #4] + 9453 0068 0022 movs r2, #0 + 9454 006a 83F84520 strb r2, [r3, #69] +3183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Change TIM state */ +3185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->State = HAL_TIM_STATE_RESET; + 9455 .loc 1 3185 15 + 9456 006e 7B68 ldr r3, [r7, #4] + 9457 0070 0022 movs r2, #0 + 9458 0072 83F83D20 strb r2, [r3, #61] +3186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Release Lock */ +3188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_UNLOCK(htim); + 9459 .loc 1 3188 3 + 9460 0076 7B68 ldr r3, [r7, #4] + 9461 0078 0022 movs r2, #0 + 9462 007a 83F83C20 strb r2, [r3, #60] +3189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_OK; + 9463 .loc 1 3190 10 + 9464 007e 0023 movs r3, #0 +3191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 9465 .loc 1 3191 1 + 9466 0080 1846 mov r0, r3 + 9467 0082 0837 adds r7, r7, #8 + 9468 .cfi_def_cfa_offset 8 + 9469 0084 BD46 mov sp, r7 + 9470 .cfi_def_cfa_register 13 + 9471 @ sp needed + 9472 0086 80BD pop {r7, pc} + 9473 .cfi_endproc + 9474 .LFE179: + 9476 .section .text.HAL_TIM_Encoder_MspInit,"ax",%progbits + 9477 .align 1 + ARM GAS /tmp/ccl4b9YO.s page 222 + + + 9478 .weak HAL_TIM_Encoder_MspInit + 9479 .syntax unified + 9480 .thumb + 9481 .thumb_func + 9483 HAL_TIM_Encoder_MspInit: + 9484 .LFB180: +3192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +3194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Initializes the TIM Encoder Interface MSP. +3195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM Encoder Interface handle +3196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval None +3197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +3198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) +3199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 9485 .loc 1 3199 1 + 9486 .cfi_startproc + 9487 @ args = 0, pretend = 0, frame = 8 + 9488 @ frame_needed = 1, uses_anonymous_args = 0 + 9489 @ link register save eliminated. + 9490 0000 80B4 push {r7} + 9491 .cfi_def_cfa_offset 4 + 9492 .cfi_offset 7, -4 + 9493 0002 83B0 sub sp, sp, #12 + 9494 .cfi_def_cfa_offset 16 + 9495 0004 00AF add r7, sp, #0 + 9496 .cfi_def_cfa_register 7 + 9497 0006 7860 str r0, [r7, #4] +3200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +3201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** UNUSED(htim); +3202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* NOTE : This function should not be modified, when the callback is needed, +3204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** the HAL_TIM_Encoder_MspInit could be implemented in the user file +3205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +3206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 9498 .loc 1 3206 1 + 9499 0008 00BF nop + 9500 000a 0C37 adds r7, r7, #12 + 9501 .cfi_def_cfa_offset 4 + 9502 000c BD46 mov sp, r7 + 9503 .cfi_def_cfa_register 13 + 9504 @ sp needed + 9505 000e 5DF8047B ldr r7, [sp], #4 + 9506 .cfi_restore 7 + 9507 .cfi_def_cfa_offset 0 + 9508 0012 7047 bx lr + 9509 .cfi_endproc + 9510 .LFE180: + 9512 .section .text.HAL_TIM_Encoder_MspDeInit,"ax",%progbits + 9513 .align 1 + 9514 .weak HAL_TIM_Encoder_MspDeInit + 9515 .syntax unified + 9516 .thumb + 9517 .thumb_func + 9519 HAL_TIM_Encoder_MspDeInit: + 9520 .LFB181: +3207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** + ARM GAS /tmp/ccl4b9YO.s page 223 + + +3209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief DeInitializes TIM Encoder Interface MSP. +3210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM Encoder Interface handle +3211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval None +3212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +3213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) +3214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 9521 .loc 1 3214 1 + 9522 .cfi_startproc + 9523 @ args = 0, pretend = 0, frame = 8 + 9524 @ frame_needed = 1, uses_anonymous_args = 0 + 9525 @ link register save eliminated. + 9526 0000 80B4 push {r7} + 9527 .cfi_def_cfa_offset 4 + 9528 .cfi_offset 7, -4 + 9529 0002 83B0 sub sp, sp, #12 + 9530 .cfi_def_cfa_offset 16 + 9531 0004 00AF add r7, sp, #0 + 9532 .cfi_def_cfa_register 7 + 9533 0006 7860 str r0, [r7, #4] +3215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +3216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** UNUSED(htim); +3217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* NOTE : This function should not be modified, when the callback is needed, +3219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** the HAL_TIM_Encoder_MspDeInit could be implemented in the user file +3220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +3221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 9534 .loc 1 3221 1 + 9535 0008 00BF nop + 9536 000a 0C37 adds r7, r7, #12 + 9537 .cfi_def_cfa_offset 4 + 9538 000c BD46 mov sp, r7 + 9539 .cfi_def_cfa_register 13 + 9540 @ sp needed + 9541 000e 5DF8047B ldr r7, [sp], #4 + 9542 .cfi_restore 7 + 9543 .cfi_def_cfa_offset 0 + 9544 0012 7047 bx lr + 9545 .cfi_endproc + 9546 .LFE181: + 9548 .section .text.HAL_TIM_Encoder_Start,"ax",%progbits + 9549 .align 1 + 9550 .global HAL_TIM_Encoder_Start + 9551 .syntax unified + 9552 .thumb + 9553 .thumb_func + 9555 HAL_TIM_Encoder_Start: + 9556 .LFB182: +3222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +3224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Starts the TIM Encoder Interface. +3225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM Encoder Interface handle +3226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param Channel TIM Channels to be enabled +3227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +3228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +3229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +3230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected +3231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status + ARM GAS /tmp/ccl4b9YO.s page 224 + + +3232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +3233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +3234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 9557 .loc 1 3234 1 + 9558 .cfi_startproc + 9559 @ args = 0, pretend = 0, frame = 16 + 9560 @ frame_needed = 1, uses_anonymous_args = 0 + 9561 0000 80B5 push {r7, lr} + 9562 .cfi_def_cfa_offset 8 + 9563 .cfi_offset 7, -8 + 9564 .cfi_offset 14, -4 + 9565 0002 84B0 sub sp, sp, #16 + 9566 .cfi_def_cfa_offset 24 + 9567 0004 00AF add r7, sp, #0 + 9568 .cfi_def_cfa_register 7 + 9569 0006 7860 str r0, [r7, #4] + 9570 0008 3960 str r1, [r7] +3235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + 9571 .loc 1 3235 31 + 9572 000a 7B68 ldr r3, [r7, #4] + 9573 000c 93F83E30 ldrb r3, [r3, #62] + 9574 0010 FB73 strb r3, [r7, #15] +3236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + 9575 .loc 1 3236 31 + 9576 0012 7B68 ldr r3, [r7, #4] + 9577 0014 93F83F30 ldrb r3, [r3, #63] + 9578 0018 BB73 strb r3, [r7, #14] +3237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 9579 .loc 1 3237 31 + 9580 001a 7B68 ldr r3, [r7, #4] + 9581 001c 93F84430 ldrb r3, [r3, #68] + 9582 0020 7B73 strb r3, [r7, #13] +3238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 9583 .loc 1 3238 31 + 9584 0022 7B68 ldr r3, [r7, #4] + 9585 0024 93F84530 ldrb r3, [r3, #69] + 9586 0028 3B73 strb r3, [r7, #12] +3239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +3241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); +3242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the TIM channel(s) state */ +3244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (Channel == TIM_CHANNEL_1) + 9587 .loc 1 3244 6 + 9588 002a 3B68 ldr r3, [r7] + 9589 002c 002B cmp r3, #0 + 9590 002e 10D1 bne .L769 +3245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + 9591 .loc 1 3246 8 + 9592 0030 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 9593 0032 012B cmp r3, #1 + 9594 0034 02D1 bne .L770 +3247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + 9595 .loc 1 3247 9 + 9596 0036 7B7B ldrb r3, [r7, #13] @ zero_extendqisi2 + 9597 0038 012B cmp r3, #1 + ARM GAS /tmp/ccl4b9YO.s page 225 + + + 9598 003a 01D0 beq .L771 + 9599 .L770: +3248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 9600 .loc 1 3249 14 + 9601 003c 0123 movs r3, #1 + 9602 003e 69E0 b .L772 + 9603 .L771: +3250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +3252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + 9604 .loc 1 3253 7 + 9605 0040 7B68 ldr r3, [r7, #4] + 9606 0042 0222 movs r2, #2 + 9607 0044 83F83E20 strb r2, [r3, #62] +3254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + 9608 .loc 1 3254 7 + 9609 0048 7B68 ldr r3, [r7, #4] + 9610 004a 0222 movs r2, #2 + 9611 004c 83F84420 strb r2, [r3, #68] + 9612 0050 31E0 b .L773 + 9613 .L769: +3255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else if (Channel == TIM_CHANNEL_2) + 9614 .loc 1 3257 11 + 9615 0052 3B68 ldr r3, [r7] + 9616 0054 042B cmp r3, #4 + 9617 0056 10D1 bne .L774 +3258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + 9618 .loc 1 3259 8 + 9619 0058 BB7B ldrb r3, [r7, #14] @ zero_extendqisi2 + 9620 005a 012B cmp r3, #1 + 9621 005c 02D1 bne .L775 +3260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + 9622 .loc 1 3260 9 + 9623 005e 3B7B ldrb r3, [r7, #12] @ zero_extendqisi2 + 9624 0060 012B cmp r3, #1 + 9625 0062 01D0 beq .L776 + 9626 .L775: +3261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 9627 .loc 1 3262 14 + 9628 0064 0123 movs r3, #1 + 9629 0066 55E0 b .L772 + 9630 .L776: +3263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +3265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 9631 .loc 1 3266 7 + 9632 0068 7B68 ldr r3, [r7, #4] + 9633 006a 0222 movs r2, #2 + 9634 006c 83F83F20 strb r2, [r3, #63] +3267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + ARM GAS /tmp/ccl4b9YO.s page 226 + + + 9635 .loc 1 3267 7 + 9636 0070 7B68 ldr r3, [r7, #4] + 9637 0072 0222 movs r2, #2 + 9638 0074 83F84520 strb r2, [r3, #69] + 9639 0078 1DE0 b .L773 + 9640 .L774: +3268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +3271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + 9641 .loc 1 3272 8 + 9642 007a FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 9643 007c 012B cmp r3, #1 + 9644 007e 08D1 bne .L777 +3273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + 9645 .loc 1 3273 9 + 9646 0080 BB7B ldrb r3, [r7, #14] @ zero_extendqisi2 + 9647 0082 012B cmp r3, #1 + 9648 0084 05D1 bne .L777 +3274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + 9649 .loc 1 3274 9 + 9650 0086 7B7B ldrb r3, [r7, #13] @ zero_extendqisi2 + 9651 0088 012B cmp r3, #1 + 9652 008a 02D1 bne .L777 +3275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + 9653 .loc 1 3275 9 + 9654 008c 3B7B ldrb r3, [r7, #12] @ zero_extendqisi2 + 9655 008e 012B cmp r3, #1 + 9656 0090 01D0 beq .L778 + 9657 .L777: +3276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 9658 .loc 1 3277 14 + 9659 0092 0123 movs r3, #1 + 9660 0094 3EE0 b .L772 + 9661 .L778: +3278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +3280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + 9662 .loc 1 3281 7 + 9663 0096 7B68 ldr r3, [r7, #4] + 9664 0098 0222 movs r2, #2 + 9665 009a 83F83E20 strb r2, [r3, #62] +3282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 9666 .loc 1 3282 7 + 9667 009e 7B68 ldr r3, [r7, #4] + 9668 00a0 0222 movs r2, #2 + 9669 00a2 83F83F20 strb r2, [r3, #63] +3283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + 9670 .loc 1 3283 7 + 9671 00a6 7B68 ldr r3, [r7, #4] + 9672 00a8 0222 movs r2, #2 + 9673 00aa 83F84420 strb r2, [r3, #68] +3284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 9674 .loc 1 3284 7 + ARM GAS /tmp/ccl4b9YO.s page 227 + + + 9675 00ae 7B68 ldr r3, [r7, #4] + 9676 00b0 0222 movs r2, #2 + 9677 00b2 83F84520 strb r2, [r3, #69] + 9678 .L773: +3285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the encoder interface channels */ +3289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** switch (Channel) + 9679 .loc 1 3289 3 + 9680 00b6 3B68 ldr r3, [r7] + 9681 00b8 002B cmp r3, #0 + 9682 00ba 03D0 beq .L779 + 9683 00bc 3B68 ldr r3, [r7] + 9684 00be 042B cmp r3, #4 + 9685 00c0 08D0 beq .L780 + 9686 00c2 0FE0 b .L783 + 9687 .L779: +3290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_1: +3292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + 9688 .loc 1 3293 7 + 9689 00c4 7B68 ldr r3, [r7, #4] + 9690 00c6 1B68 ldr r3, [r3] + 9691 00c8 0122 movs r2, #1 + 9692 00ca 0021 movs r1, #0 + 9693 00cc 1846 mov r0, r3 + 9694 00ce FFF7FEFF bl TIM_CCxChannelCmd +3294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 9695 .loc 1 3294 7 + 9696 00d2 16E0 b .L782 + 9697 .L780: +3295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_2: +3298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + 9698 .loc 1 3299 7 + 9699 00d4 7B68 ldr r3, [r7, #4] + 9700 00d6 1B68 ldr r3, [r3] + 9701 00d8 0122 movs r2, #1 + 9702 00da 0421 movs r1, #4 + 9703 00dc 1846 mov r0, r3 + 9704 00de FFF7FEFF bl TIM_CCxChannelCmd +3300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 9705 .loc 1 3300 7 + 9706 00e2 0EE0 b .L782 + 9707 .L783: +3301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** default : +3304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + 9708 .loc 1 3305 7 + 9709 00e4 7B68 ldr r3, [r7, #4] + 9710 00e6 1B68 ldr r3, [r3] + ARM GAS /tmp/ccl4b9YO.s page 228 + + + 9711 00e8 0122 movs r2, #1 + 9712 00ea 0021 movs r1, #0 + 9713 00ec 1846 mov r0, r3 + 9714 00ee FFF7FEFF bl TIM_CCxChannelCmd +3306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + 9715 .loc 1 3306 7 + 9716 00f2 7B68 ldr r3, [r7, #4] + 9717 00f4 1B68 ldr r3, [r3] + 9718 00f6 0122 movs r2, #1 + 9719 00f8 0421 movs r1, #4 + 9720 00fa 1846 mov r0, r3 + 9721 00fc FFF7FEFF bl TIM_CCxChannelCmd +3307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 9722 .loc 1 3307 7 + 9723 0100 00BF nop + 9724 .L782: +3308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the Peripheral */ +3311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); + 9725 .loc 1 3311 3 + 9726 0102 7B68 ldr r3, [r7, #4] + 9727 0104 1B68 ldr r3, [r3] + 9728 0106 1A68 ldr r2, [r3] + 9729 0108 7B68 ldr r3, [r7, #4] + 9730 010a 1B68 ldr r3, [r3] + 9731 010c 42F00102 orr r2, r2, #1 + 9732 0110 1A60 str r2, [r3] +3312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return function status */ +3314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_OK; + 9733 .loc 1 3314 10 + 9734 0112 0023 movs r3, #0 + 9735 .L772: +3315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 9736 .loc 1 3315 1 + 9737 0114 1846 mov r0, r3 + 9738 0116 1037 adds r7, r7, #16 + 9739 .cfi_def_cfa_offset 8 + 9740 0118 BD46 mov sp, r7 + 9741 .cfi_def_cfa_register 13 + 9742 @ sp needed + 9743 011a 80BD pop {r7, pc} + 9744 .cfi_endproc + 9745 .LFE182: + 9747 .section .text.HAL_TIM_Encoder_Stop,"ax",%progbits + 9748 .align 1 + 9749 .global HAL_TIM_Encoder_Stop + 9750 .syntax unified + 9751 .thumb + 9752 .thumb_func + 9754 HAL_TIM_Encoder_Stop: + 9755 .LFB183: +3316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +3318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Stops the TIM Encoder Interface. +3319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM Encoder Interface handle + ARM GAS /tmp/ccl4b9YO.s page 229 + + +3320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param Channel TIM Channels to be disabled +3321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +3322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +3323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +3324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected +3325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status +3326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +3327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +3328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 9756 .loc 1 3328 1 + 9757 .cfi_startproc + 9758 @ args = 0, pretend = 0, frame = 8 + 9759 @ frame_needed = 1, uses_anonymous_args = 0 + 9760 0000 80B5 push {r7, lr} + 9761 .cfi_def_cfa_offset 8 + 9762 .cfi_offset 7, -8 + 9763 .cfi_offset 14, -4 + 9764 0002 82B0 sub sp, sp, #8 + 9765 .cfi_def_cfa_offset 16 + 9766 0004 00AF add r7, sp, #0 + 9767 .cfi_def_cfa_register 7 + 9768 0006 7860 str r0, [r7, #4] + 9769 0008 3960 str r1, [r7] +3329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +3330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); +3331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the Input Capture channels 1 and 2 +3333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_C +3334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** switch (Channel) + 9770 .loc 1 3334 3 + 9771 000a 3B68 ldr r3, [r7] + 9772 000c 002B cmp r3, #0 + 9773 000e 03D0 beq .L785 + 9774 0010 3B68 ldr r3, [r7] + 9775 0012 042B cmp r3, #4 + 9776 0014 08D0 beq .L786 + 9777 0016 0FE0 b .L810 + 9778 .L785: +3335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_1: +3337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + 9779 .loc 1 3338 7 + 9780 0018 7B68 ldr r3, [r7, #4] + 9781 001a 1B68 ldr r3, [r3] + 9782 001c 0022 movs r2, #0 + 9783 001e 0021 movs r1, #0 + 9784 0020 1846 mov r0, r3 + 9785 0022 FFF7FEFF bl TIM_CCxChannelCmd +3339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 9786 .loc 1 3339 7 + 9787 0026 16E0 b .L788 + 9788 .L786: +3340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_2: +3343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + ARM GAS /tmp/ccl4b9YO.s page 230 + + +3344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + 9789 .loc 1 3344 7 + 9790 0028 7B68 ldr r3, [r7, #4] + 9791 002a 1B68 ldr r3, [r3] + 9792 002c 0022 movs r2, #0 + 9793 002e 0421 movs r1, #4 + 9794 0030 1846 mov r0, r3 + 9795 0032 FFF7FEFF bl TIM_CCxChannelCmd +3345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 9796 .loc 1 3345 7 + 9797 0036 0EE0 b .L788 + 9798 .L810: +3346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** default : +3349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + 9799 .loc 1 3350 7 + 9800 0038 7B68 ldr r3, [r7, #4] + 9801 003a 1B68 ldr r3, [r3] + 9802 003c 0022 movs r2, #0 + 9803 003e 0021 movs r1, #0 + 9804 0040 1846 mov r0, r3 + 9805 0042 FFF7FEFF bl TIM_CCxChannelCmd +3351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + 9806 .loc 1 3351 7 + 9807 0046 7B68 ldr r3, [r7, #4] + 9808 0048 1B68 ldr r3, [r3] + 9809 004a 0022 movs r2, #0 + 9810 004c 0421 movs r1, #4 + 9811 004e 1846 mov r0, r3 + 9812 0050 FFF7FEFF bl TIM_CCxChannelCmd +3352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 9813 .loc 1 3352 7 + 9814 0054 00BF nop + 9815 .L788: +3353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the Peripheral */ +3357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); + 9816 .loc 1 3357 3 + 9817 0056 7B68 ldr r3, [r7, #4] + 9818 0058 1B68 ldr r3, [r3] + 9819 005a 1A6A ldr r2, [r3, #32] + 9820 005c 41F21113 movw r3, #4369 + 9821 0060 1340 ands r3, r3, r2 + 9822 0062 002B cmp r3, #0 + 9823 0064 0FD1 bne .L789 + 9824 .loc 1 3357 3 is_stmt 0 discriminator 1 + 9825 0066 7B68 ldr r3, [r7, #4] + 9826 0068 1B68 ldr r3, [r3] + 9827 006a 1A6A ldr r2, [r3, #32] + 9828 006c 40F24443 movw r3, #1092 + 9829 0070 1340 ands r3, r3, r2 + 9830 0072 002B cmp r3, #0 + 9831 0074 07D1 bne .L789 + ARM GAS /tmp/ccl4b9YO.s page 231 + + + 9832 .loc 1 3357 3 discriminator 2 + 9833 0076 7B68 ldr r3, [r7, #4] + 9834 0078 1B68 ldr r3, [r3] + 9835 007a 1A68 ldr r2, [r3] + 9836 007c 7B68 ldr r3, [r7, #4] + 9837 007e 1B68 ldr r3, [r3] + 9838 0080 22F00102 bic r2, r2, #1 + 9839 0084 1A60 str r2, [r3] + 9840 .L789: +3358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the TIM channel(s) state */ +3360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + 9841 .loc 1 3360 6 is_stmt 1 + 9842 0086 3B68 ldr r3, [r7] + 9843 0088 002B cmp r3, #0 + 9844 008a 02D0 beq .L790 + 9845 .loc 1 3360 34 discriminator 1 + 9846 008c 3B68 ldr r3, [r7] + 9847 008e 042B cmp r3, #4 + 9848 0090 48D1 bne .L791 + 9849 .L790: +3361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 9850 .loc 1 3362 5 + 9851 0092 3B68 ldr r3, [r7] + 9852 0094 002B cmp r3, #0 + 9853 0096 04D1 bne .L792 + 9854 .loc 1 3362 5 is_stmt 0 discriminator 1 + 9855 0098 7B68 ldr r3, [r7, #4] + 9856 009a 0122 movs r2, #1 + 9857 009c 83F83E20 strb r2, [r3, #62] + 9858 00a0 23E0 b .L793 + 9859 .L792: + 9860 .loc 1 3362 5 discriminator 2 + 9861 00a2 3B68 ldr r3, [r7] + 9862 00a4 042B cmp r3, #4 + 9863 00a6 04D1 bne .L794 + 9864 .loc 1 3362 5 discriminator 3 + 9865 00a8 7B68 ldr r3, [r7, #4] + 9866 00aa 0122 movs r2, #1 + 9867 00ac 83F83F20 strb r2, [r3, #63] + 9868 00b0 1BE0 b .L793 + 9869 .L794: + 9870 .loc 1 3362 5 discriminator 4 + 9871 00b2 3B68 ldr r3, [r7] + 9872 00b4 082B cmp r3, #8 + 9873 00b6 04D1 bne .L796 + 9874 .loc 1 3362 5 discriminator 6 + 9875 00b8 7B68 ldr r3, [r7, #4] + 9876 00ba 0122 movs r2, #1 + 9877 00bc 83F84020 strb r2, [r3, #64] + 9878 00c0 13E0 b .L793 + 9879 .L796: + 9880 .loc 1 3362 5 discriminator 7 + 9881 00c2 3B68 ldr r3, [r7] + 9882 00c4 0C2B cmp r3, #12 + 9883 00c6 04D1 bne .L798 + ARM GAS /tmp/ccl4b9YO.s page 232 + + + 9884 .loc 1 3362 5 discriminator 9 + 9885 00c8 7B68 ldr r3, [r7, #4] + 9886 00ca 0122 movs r2, #1 + 9887 00cc 83F84120 strb r2, [r3, #65] + 9888 00d0 0BE0 b .L793 + 9889 .L798: + 9890 .loc 1 3362 5 discriminator 10 + 9891 00d2 3B68 ldr r3, [r7] + 9892 00d4 102B cmp r3, #16 + 9893 00d6 04D1 bne .L800 + 9894 .loc 1 3362 5 discriminator 12 + 9895 00d8 7B68 ldr r3, [r7, #4] + 9896 00da 0122 movs r2, #1 + 9897 00dc 83F84220 strb r2, [r3, #66] + 9898 00e0 03E0 b .L793 + 9899 .L800: + 9900 .loc 1 3362 5 discriminator 13 + 9901 00e2 7B68 ldr r3, [r7, #4] + 9902 00e4 0122 movs r2, #1 + 9903 00e6 83F84320 strb r2, [r3, #67] + 9904 .L793: +3363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 9905 .loc 1 3363 5 is_stmt 1 + 9906 00ea 3B68 ldr r3, [r7] + 9907 00ec 002B cmp r3, #0 + 9908 00ee 04D1 bne .L802 + 9909 .loc 1 3363 5 is_stmt 0 discriminator 1 + 9910 00f0 7B68 ldr r3, [r7, #4] + 9911 00f2 0122 movs r2, #1 + 9912 00f4 83F84420 strb r2, [r3, #68] + 9913 .loc 1 3363 5 + 9914 00f8 24E0 b .L808 + 9915 .L802: + 9916 .loc 1 3363 5 discriminator 2 + 9917 00fa 3B68 ldr r3, [r7] + 9918 00fc 042B cmp r3, #4 + 9919 00fe 04D1 bne .L804 + 9920 .loc 1 3363 5 discriminator 3 + 9921 0100 7B68 ldr r3, [r7, #4] + 9922 0102 0122 movs r2, #1 + 9923 0104 83F84520 strb r2, [r3, #69] + 9924 .loc 1 3363 5 + 9925 0108 1CE0 b .L808 + 9926 .L804: + 9927 .loc 1 3363 5 discriminator 4 + 9928 010a 3B68 ldr r3, [r7] + 9929 010c 082B cmp r3, #8 + 9930 010e 04D1 bne .L806 + 9931 .loc 1 3363 5 discriminator 6 + 9932 0110 7B68 ldr r3, [r7, #4] + 9933 0112 0122 movs r2, #1 + 9934 0114 83F84620 strb r2, [r3, #70] + 9935 .loc 1 3363 5 + 9936 0118 14E0 b .L808 + 9937 .L806: + 9938 .loc 1 3363 5 discriminator 7 + 9939 011a 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/ccl4b9YO.s page 233 + + + 9940 011c 0122 movs r2, #1 + 9941 011e 83F84720 strb r2, [r3, #71] + 9942 .loc 1 3363 5 + 9943 0122 0FE0 b .L808 + 9944 .L791: +3364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +3366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 9945 .loc 1 3367 5 is_stmt 1 + 9946 0124 7B68 ldr r3, [r7, #4] + 9947 0126 0122 movs r2, #1 + 9948 0128 83F83E20 strb r2, [r3, #62] +3368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 9949 .loc 1 3368 5 + 9950 012c 7B68 ldr r3, [r7, #4] + 9951 012e 0122 movs r2, #1 + 9952 0130 83F83F20 strb r2, [r3, #63] +3369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 9953 .loc 1 3369 5 + 9954 0134 7B68 ldr r3, [r7, #4] + 9955 0136 0122 movs r2, #1 + 9956 0138 83F84420 strb r2, [r3, #68] +3370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 9957 .loc 1 3370 5 + 9958 013c 7B68 ldr r3, [r7, #4] + 9959 013e 0122 movs r2, #1 + 9960 0140 83F84520 strb r2, [r3, #69] + 9961 .L808: +3371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return function status */ +3374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_OK; + 9962 .loc 1 3374 10 + 9963 0144 0023 movs r3, #0 +3375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 9964 .loc 1 3375 1 + 9965 0146 1846 mov r0, r3 + 9966 0148 0837 adds r7, r7, #8 + 9967 .cfi_def_cfa_offset 8 + 9968 014a BD46 mov sp, r7 + 9969 .cfi_def_cfa_register 13 + 9970 @ sp needed + 9971 014c 80BD pop {r7, pc} + 9972 .cfi_endproc + 9973 .LFE183: + 9975 .section .text.HAL_TIM_Encoder_Start_IT,"ax",%progbits + 9976 .align 1 + 9977 .global HAL_TIM_Encoder_Start_IT + 9978 .syntax unified + 9979 .thumb + 9980 .thumb_func + 9982 HAL_TIM_Encoder_Start_IT: + 9983 .LFB184: +3376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +3378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Starts the TIM Encoder Interface in interrupt mode. + ARM GAS /tmp/ccl4b9YO.s page 234 + + +3379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM Encoder Interface handle +3380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param Channel TIM Channels to be enabled +3381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +3382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +3383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +3384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected +3385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status +3386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +3387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +3388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 9984 .loc 1 3388 1 + 9985 .cfi_startproc + 9986 @ args = 0, pretend = 0, frame = 16 + 9987 @ frame_needed = 1, uses_anonymous_args = 0 + 9988 0000 80B5 push {r7, lr} + 9989 .cfi_def_cfa_offset 8 + 9990 .cfi_offset 7, -8 + 9991 .cfi_offset 14, -4 + 9992 0002 84B0 sub sp, sp, #16 + 9993 .cfi_def_cfa_offset 24 + 9994 0004 00AF add r7, sp, #0 + 9995 .cfi_def_cfa_register 7 + 9996 0006 7860 str r0, [r7, #4] + 9997 0008 3960 str r1, [r7] +3389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + 9998 .loc 1 3389 31 + 9999 000a 7B68 ldr r3, [r7, #4] + 10000 000c 93F83E30 ldrb r3, [r3, #62] + 10001 0010 FB73 strb r3, [r7, #15] +3390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + 10002 .loc 1 3390 31 + 10003 0012 7B68 ldr r3, [r7, #4] + 10004 0014 93F83F30 ldrb r3, [r3, #63] + 10005 0018 BB73 strb r3, [r7, #14] +3391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 10006 .loc 1 3391 31 + 10007 001a 7B68 ldr r3, [r7, #4] + 10008 001c 93F84430 ldrb r3, [r3, #68] + 10009 0020 7B73 strb r3, [r7, #13] +3392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 10010 .loc 1 3392 31 + 10011 0022 7B68 ldr r3, [r7, #4] + 10012 0024 93F84530 ldrb r3, [r3, #69] + 10013 0028 3B73 strb r3, [r7, #12] +3393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +3395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); +3396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the TIM channel(s) state */ +3398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (Channel == TIM_CHANNEL_1) + 10014 .loc 1 3398 6 + 10015 002a 3B68 ldr r3, [r7] + 10016 002c 002B cmp r3, #0 + 10017 002e 10D1 bne .L812 +3399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + 10018 .loc 1 3400 8 + ARM GAS /tmp/ccl4b9YO.s page 235 + + + 10019 0030 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 10020 0032 012B cmp r3, #1 + 10021 0034 02D1 bne .L813 +3401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + 10022 .loc 1 3401 9 + 10023 0036 7B7B ldrb r3, [r7, #13] @ zero_extendqisi2 + 10024 0038 012B cmp r3, #1 + 10025 003a 01D0 beq .L814 + 10026 .L813: +3402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 10027 .loc 1 3403 14 + 10028 003c 0123 movs r3, #1 + 10029 003e 89E0 b .L815 + 10030 .L814: +3404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +3406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + 10031 .loc 1 3407 7 + 10032 0040 7B68 ldr r3, [r7, #4] + 10033 0042 0222 movs r2, #2 + 10034 0044 83F83E20 strb r2, [r3, #62] +3408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + 10035 .loc 1 3408 7 + 10036 0048 7B68 ldr r3, [r7, #4] + 10037 004a 0222 movs r2, #2 + 10038 004c 83F84420 strb r2, [r3, #68] + 10039 0050 31E0 b .L816 + 10040 .L812: +3409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else if (Channel == TIM_CHANNEL_2) + 10041 .loc 1 3411 11 + 10042 0052 3B68 ldr r3, [r7] + 10043 0054 042B cmp r3, #4 + 10044 0056 10D1 bne .L817 +3412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + 10045 .loc 1 3413 8 + 10046 0058 BB7B ldrb r3, [r7, #14] @ zero_extendqisi2 + 10047 005a 012B cmp r3, #1 + 10048 005c 02D1 bne .L818 +3414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + 10049 .loc 1 3414 9 + 10050 005e 3B7B ldrb r3, [r7, #12] @ zero_extendqisi2 + 10051 0060 012B cmp r3, #1 + 10052 0062 01D0 beq .L819 + 10053 .L818: +3415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 10054 .loc 1 3416 14 + 10055 0064 0123 movs r3, #1 + 10056 0066 75E0 b .L815 + 10057 .L819: +3417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else + ARM GAS /tmp/ccl4b9YO.s page 236 + + +3419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 10058 .loc 1 3420 7 + 10059 0068 7B68 ldr r3, [r7, #4] + 10060 006a 0222 movs r2, #2 + 10061 006c 83F83F20 strb r2, [r3, #63] +3421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 10062 .loc 1 3421 7 + 10063 0070 7B68 ldr r3, [r7, #4] + 10064 0072 0222 movs r2, #2 + 10065 0074 83F84520 strb r2, [r3, #69] + 10066 0078 1DE0 b .L816 + 10067 .L817: +3422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +3425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + 10068 .loc 1 3426 8 + 10069 007a FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 10070 007c 012B cmp r3, #1 + 10071 007e 08D1 bne .L820 +3427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + 10072 .loc 1 3427 9 + 10073 0080 BB7B ldrb r3, [r7, #14] @ zero_extendqisi2 + 10074 0082 012B cmp r3, #1 + 10075 0084 05D1 bne .L820 +3428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + 10076 .loc 1 3428 9 + 10077 0086 7B7B ldrb r3, [r7, #13] @ zero_extendqisi2 + 10078 0088 012B cmp r3, #1 + 10079 008a 02D1 bne .L820 +3429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + 10080 .loc 1 3429 9 + 10081 008c 3B7B ldrb r3, [r7, #12] @ zero_extendqisi2 + 10082 008e 012B cmp r3, #1 + 10083 0090 01D0 beq .L821 + 10084 .L820: +3430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 10085 .loc 1 3431 14 + 10086 0092 0123 movs r3, #1 + 10087 0094 5EE0 b .L815 + 10088 .L821: +3432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +3434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + 10089 .loc 1 3435 7 + 10090 0096 7B68 ldr r3, [r7, #4] + 10091 0098 0222 movs r2, #2 + 10092 009a 83F83E20 strb r2, [r3, #62] +3436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 10093 .loc 1 3436 7 + 10094 009e 7B68 ldr r3, [r7, #4] + 10095 00a0 0222 movs r2, #2 + 10096 00a2 83F83F20 strb r2, [r3, #63] + ARM GAS /tmp/ccl4b9YO.s page 237 + + +3437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + 10097 .loc 1 3437 7 + 10098 00a6 7B68 ldr r3, [r7, #4] + 10099 00a8 0222 movs r2, #2 + 10100 00aa 83F84420 strb r2, [r3, #68] +3438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 10101 .loc 1 3438 7 + 10102 00ae 7B68 ldr r3, [r7, #4] + 10103 00b0 0222 movs r2, #2 + 10104 00b2 83F84520 strb r2, [r3, #69] + 10105 .L816: +3439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the encoder interface channels */ +3443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the capture compare Interrupts 1 and/or 2 */ +3444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** switch (Channel) + 10106 .loc 1 3444 3 + 10107 00b6 3B68 ldr r3, [r7] + 10108 00b8 002B cmp r3, #0 + 10109 00ba 03D0 beq .L822 + 10110 00bc 3B68 ldr r3, [r7] + 10111 00be 042B cmp r3, #4 + 10112 00c0 10D0 beq .L823 + 10113 00c2 1FE0 b .L826 + 10114 .L822: +3445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_1: +3447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + 10115 .loc 1 3448 7 + 10116 00c4 7B68 ldr r3, [r7, #4] + 10117 00c6 1B68 ldr r3, [r3] + 10118 00c8 0122 movs r2, #1 + 10119 00ca 0021 movs r1, #0 + 10120 00cc 1846 mov r0, r3 + 10121 00ce FFF7FEFF bl TIM_CCxChannelCmd +3449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + 10122 .loc 1 3449 7 + 10123 00d2 7B68 ldr r3, [r7, #4] + 10124 00d4 1B68 ldr r3, [r3] + 10125 00d6 DA68 ldr r2, [r3, #12] + 10126 00d8 7B68 ldr r3, [r7, #4] + 10127 00da 1B68 ldr r3, [r3] + 10128 00dc 42F00202 orr r2, r2, #2 + 10129 00e0 DA60 str r2, [r3, #12] +3450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 10130 .loc 1 3450 7 + 10131 00e2 2EE0 b .L825 + 10132 .L823: +3451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_2: +3454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + 10133 .loc 1 3455 7 + 10134 00e4 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/ccl4b9YO.s page 238 + + + 10135 00e6 1B68 ldr r3, [r3] + 10136 00e8 0122 movs r2, #1 + 10137 00ea 0421 movs r1, #4 + 10138 00ec 1846 mov r0, r3 + 10139 00ee FFF7FEFF bl TIM_CCxChannelCmd +3456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + 10140 .loc 1 3456 7 + 10141 00f2 7B68 ldr r3, [r7, #4] + 10142 00f4 1B68 ldr r3, [r3] + 10143 00f6 DA68 ldr r2, [r3, #12] + 10144 00f8 7B68 ldr r3, [r7, #4] + 10145 00fa 1B68 ldr r3, [r3] + 10146 00fc 42F00402 orr r2, r2, #4 + 10147 0100 DA60 str r2, [r3, #12] +3457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 10148 .loc 1 3457 7 + 10149 0102 1EE0 b .L825 + 10150 .L826: +3458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** default : +3461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + 10151 .loc 1 3462 7 + 10152 0104 7B68 ldr r3, [r7, #4] + 10153 0106 1B68 ldr r3, [r3] + 10154 0108 0122 movs r2, #1 + 10155 010a 0021 movs r1, #0 + 10156 010c 1846 mov r0, r3 + 10157 010e FFF7FEFF bl TIM_CCxChannelCmd +3463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + 10158 .loc 1 3463 7 + 10159 0112 7B68 ldr r3, [r7, #4] + 10160 0114 1B68 ldr r3, [r3] + 10161 0116 0122 movs r2, #1 + 10162 0118 0421 movs r1, #4 + 10163 011a 1846 mov r0, r3 + 10164 011c FFF7FEFF bl TIM_CCxChannelCmd +3464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + 10165 .loc 1 3464 7 + 10166 0120 7B68 ldr r3, [r7, #4] + 10167 0122 1B68 ldr r3, [r3] + 10168 0124 DA68 ldr r2, [r3, #12] + 10169 0126 7B68 ldr r3, [r7, #4] + 10170 0128 1B68 ldr r3, [r3] + 10171 012a 42F00202 orr r2, r2, #2 + 10172 012e DA60 str r2, [r3, #12] +3465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + 10173 .loc 1 3465 7 + 10174 0130 7B68 ldr r3, [r7, #4] + 10175 0132 1B68 ldr r3, [r3] + 10176 0134 DA68 ldr r2, [r3, #12] + 10177 0136 7B68 ldr r3, [r7, #4] + 10178 0138 1B68 ldr r3, [r3] + 10179 013a 42F00402 orr r2, r2, #4 + 10180 013e DA60 str r2, [r3, #12] +3466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + ARM GAS /tmp/ccl4b9YO.s page 239 + + + 10181 .loc 1 3466 7 + 10182 0140 00BF nop + 10183 .L825: +3467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the Peripheral */ +3471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); + 10184 .loc 1 3471 3 + 10185 0142 7B68 ldr r3, [r7, #4] + 10186 0144 1B68 ldr r3, [r3] + 10187 0146 1A68 ldr r2, [r3] + 10188 0148 7B68 ldr r3, [r7, #4] + 10189 014a 1B68 ldr r3, [r3] + 10190 014c 42F00102 orr r2, r2, #1 + 10191 0150 1A60 str r2, [r3] +3472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return function status */ +3474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_OK; + 10192 .loc 1 3474 10 + 10193 0152 0023 movs r3, #0 + 10194 .L815: +3475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 10195 .loc 1 3475 1 + 10196 0154 1846 mov r0, r3 + 10197 0156 1037 adds r7, r7, #16 + 10198 .cfi_def_cfa_offset 8 + 10199 0158 BD46 mov sp, r7 + 10200 .cfi_def_cfa_register 13 + 10201 @ sp needed + 10202 015a 80BD pop {r7, pc} + 10203 .cfi_endproc + 10204 .LFE184: + 10206 .section .text.HAL_TIM_Encoder_Stop_IT,"ax",%progbits + 10207 .align 1 + 10208 .global HAL_TIM_Encoder_Stop_IT + 10209 .syntax unified + 10210 .thumb + 10211 .thumb_func + 10213 HAL_TIM_Encoder_Stop_IT: + 10214 .LFB185: +3476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +3478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Stops the TIM Encoder Interface in interrupt mode. +3479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM Encoder Interface handle +3480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param Channel TIM Channels to be disabled +3481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +3482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +3483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +3484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected +3485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status +3486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +3487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +3488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 10215 .loc 1 3488 1 + 10216 .cfi_startproc + 10217 @ args = 0, pretend = 0, frame = 8 + ARM GAS /tmp/ccl4b9YO.s page 240 + + + 10218 @ frame_needed = 1, uses_anonymous_args = 0 + 10219 0000 80B5 push {r7, lr} + 10220 .cfi_def_cfa_offset 8 + 10221 .cfi_offset 7, -8 + 10222 .cfi_offset 14, -4 + 10223 0002 82B0 sub sp, sp, #8 + 10224 .cfi_def_cfa_offset 16 + 10225 0004 00AF add r7, sp, #0 + 10226 .cfi_def_cfa_register 7 + 10227 0006 7860 str r0, [r7, #4] + 10228 0008 3960 str r1, [r7] +3489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +3490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); +3491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the Input Capture channels 1 and 2 +3493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_C +3494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (Channel == TIM_CHANNEL_1) + 10229 .loc 1 3494 6 + 10230 000a 3B68 ldr r3, [r7] + 10231 000c 002B cmp r3, #0 + 10232 000e 0FD1 bne .L828 +3495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + 10233 .loc 1 3496 5 + 10234 0010 7B68 ldr r3, [r7, #4] + 10235 0012 1B68 ldr r3, [r3] + 10236 0014 0022 movs r2, #0 + 10237 0016 0021 movs r1, #0 + 10238 0018 1846 mov r0, r3 + 10239 001a FFF7FEFF bl TIM_CCxChannelCmd +3497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the capture compare Interrupts 1 */ +3499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + 10240 .loc 1 3499 5 + 10241 001e 7B68 ldr r3, [r7, #4] + 10242 0020 1B68 ldr r3, [r3] + 10243 0022 DA68 ldr r2, [r3, #12] + 10244 0024 7B68 ldr r3, [r7, #4] + 10245 0026 1B68 ldr r3, [r3] + 10246 0028 22F00202 bic r2, r2, #2 + 10247 002c DA60 str r2, [r3, #12] + 10248 002e 30E0 b .L829 + 10249 .L828: +3500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else if (Channel == TIM_CHANNEL_2) + 10250 .loc 1 3501 11 + 10251 0030 3B68 ldr r3, [r7] + 10252 0032 042B cmp r3, #4 + 10253 0034 0FD1 bne .L830 +3502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + 10254 .loc 1 3503 5 + 10255 0036 7B68 ldr r3, [r7, #4] + 10256 0038 1B68 ldr r3, [r3] + 10257 003a 0022 movs r2, #0 + 10258 003c 0421 movs r1, #4 + 10259 003e 1846 mov r0, r3 + ARM GAS /tmp/ccl4b9YO.s page 241 + + + 10260 0040 FFF7FEFF bl TIM_CCxChannelCmd +3504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the capture compare Interrupts 2 */ +3506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + 10261 .loc 1 3506 5 + 10262 0044 7B68 ldr r3, [r7, #4] + 10263 0046 1B68 ldr r3, [r3] + 10264 0048 DA68 ldr r2, [r3, #12] + 10265 004a 7B68 ldr r3, [r7, #4] + 10266 004c 1B68 ldr r3, [r3] + 10267 004e 22F00402 bic r2, r2, #4 + 10268 0052 DA60 str r2, [r3, #12] + 10269 0054 1DE0 b .L829 + 10270 .L830: +3507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +3509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + 10271 .loc 1 3510 5 + 10272 0056 7B68 ldr r3, [r7, #4] + 10273 0058 1B68 ldr r3, [r3] + 10274 005a 0022 movs r2, #0 + 10275 005c 0021 movs r1, #0 + 10276 005e 1846 mov r0, r3 + 10277 0060 FFF7FEFF bl TIM_CCxChannelCmd +3511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + 10278 .loc 1 3511 5 + 10279 0064 7B68 ldr r3, [r7, #4] + 10280 0066 1B68 ldr r3, [r3] + 10281 0068 0022 movs r2, #0 + 10282 006a 0421 movs r1, #4 + 10283 006c 1846 mov r0, r3 + 10284 006e FFF7FEFF bl TIM_CCxChannelCmd +3512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the capture compare Interrupts 1 and 2 */ +3514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + 10285 .loc 1 3514 5 + 10286 0072 7B68 ldr r3, [r7, #4] + 10287 0074 1B68 ldr r3, [r3] + 10288 0076 DA68 ldr r2, [r3, #12] + 10289 0078 7B68 ldr r3, [r7, #4] + 10290 007a 1B68 ldr r3, [r3] + 10291 007c 22F00202 bic r2, r2, #2 + 10292 0080 DA60 str r2, [r3, #12] +3515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + 10293 .loc 1 3515 5 + 10294 0082 7B68 ldr r3, [r7, #4] + 10295 0084 1B68 ldr r3, [r3] + 10296 0086 DA68 ldr r2, [r3, #12] + 10297 0088 7B68 ldr r3, [r7, #4] + 10298 008a 1B68 ldr r3, [r3] + 10299 008c 22F00402 bic r2, r2, #4 + 10300 0090 DA60 str r2, [r3, #12] + 10301 .L829: +3516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the Peripheral */ + ARM GAS /tmp/ccl4b9YO.s page 242 + + +3519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); + 10302 .loc 1 3519 3 + 10303 0092 7B68 ldr r3, [r7, #4] + 10304 0094 1B68 ldr r3, [r3] + 10305 0096 1A6A ldr r2, [r3, #32] + 10306 0098 41F21113 movw r3, #4369 + 10307 009c 1340 ands r3, r3, r2 + 10308 009e 002B cmp r3, #0 + 10309 00a0 0FD1 bne .L831 + 10310 .loc 1 3519 3 is_stmt 0 discriminator 1 + 10311 00a2 7B68 ldr r3, [r7, #4] + 10312 00a4 1B68 ldr r3, [r3] + 10313 00a6 1A6A ldr r2, [r3, #32] + 10314 00a8 40F24443 movw r3, #1092 + 10315 00ac 1340 ands r3, r3, r2 + 10316 00ae 002B cmp r3, #0 + 10317 00b0 07D1 bne .L831 + 10318 .loc 1 3519 3 discriminator 2 + 10319 00b2 7B68 ldr r3, [r7, #4] + 10320 00b4 1B68 ldr r3, [r3] + 10321 00b6 1A68 ldr r2, [r3] + 10322 00b8 7B68 ldr r3, [r7, #4] + 10323 00ba 1B68 ldr r3, [r3] + 10324 00bc 22F00102 bic r2, r2, #1 + 10325 00c0 1A60 str r2, [r3] + 10326 .L831: +3520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the TIM channel(s) state */ +3522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + 10327 .loc 1 3522 6 is_stmt 1 + 10328 00c2 3B68 ldr r3, [r7] + 10329 00c4 002B cmp r3, #0 + 10330 00c6 02D0 beq .L832 + 10331 .loc 1 3522 34 discriminator 1 + 10332 00c8 3B68 ldr r3, [r7] + 10333 00ca 042B cmp r3, #4 + 10334 00cc 48D1 bne .L833 + 10335 .L832: +3523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 10336 .loc 1 3524 5 + 10337 00ce 3B68 ldr r3, [r7] + 10338 00d0 002B cmp r3, #0 + 10339 00d2 04D1 bne .L834 + 10340 .loc 1 3524 5 is_stmt 0 discriminator 1 + 10341 00d4 7B68 ldr r3, [r7, #4] + 10342 00d6 0122 movs r2, #1 + 10343 00d8 83F83E20 strb r2, [r3, #62] + 10344 00dc 23E0 b .L835 + 10345 .L834: + 10346 .loc 1 3524 5 discriminator 2 + 10347 00de 3B68 ldr r3, [r7] + 10348 00e0 042B cmp r3, #4 + 10349 00e2 04D1 bne .L836 + 10350 .loc 1 3524 5 discriminator 3 + 10351 00e4 7B68 ldr r3, [r7, #4] + 10352 00e6 0122 movs r2, #1 + ARM GAS /tmp/ccl4b9YO.s page 243 + + + 10353 00e8 83F83F20 strb r2, [r3, #63] + 10354 00ec 1BE0 b .L835 + 10355 .L836: + 10356 .loc 1 3524 5 discriminator 4 + 10357 00ee 3B68 ldr r3, [r7] + 10358 00f0 082B cmp r3, #8 + 10359 00f2 04D1 bne .L838 + 10360 .loc 1 3524 5 discriminator 6 + 10361 00f4 7B68 ldr r3, [r7, #4] + 10362 00f6 0122 movs r2, #1 + 10363 00f8 83F84020 strb r2, [r3, #64] + 10364 00fc 13E0 b .L835 + 10365 .L838: + 10366 .loc 1 3524 5 discriminator 7 + 10367 00fe 3B68 ldr r3, [r7] + 10368 0100 0C2B cmp r3, #12 + 10369 0102 04D1 bne .L840 + 10370 .loc 1 3524 5 discriminator 9 + 10371 0104 7B68 ldr r3, [r7, #4] + 10372 0106 0122 movs r2, #1 + 10373 0108 83F84120 strb r2, [r3, #65] + 10374 010c 0BE0 b .L835 + 10375 .L840: + 10376 .loc 1 3524 5 discriminator 10 + 10377 010e 3B68 ldr r3, [r7] + 10378 0110 102B cmp r3, #16 + 10379 0112 04D1 bne .L842 + 10380 .loc 1 3524 5 discriminator 12 + 10381 0114 7B68 ldr r3, [r7, #4] + 10382 0116 0122 movs r2, #1 + 10383 0118 83F84220 strb r2, [r3, #66] + 10384 011c 03E0 b .L835 + 10385 .L842: + 10386 .loc 1 3524 5 discriminator 13 + 10387 011e 7B68 ldr r3, [r7, #4] + 10388 0120 0122 movs r2, #1 + 10389 0122 83F84320 strb r2, [r3, #67] + 10390 .L835: +3525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 10391 .loc 1 3525 5 is_stmt 1 + 10392 0126 3B68 ldr r3, [r7] + 10393 0128 002B cmp r3, #0 + 10394 012a 04D1 bne .L844 + 10395 .loc 1 3525 5 is_stmt 0 discriminator 1 + 10396 012c 7B68 ldr r3, [r7, #4] + 10397 012e 0122 movs r2, #1 + 10398 0130 83F84420 strb r2, [r3, #68] + 10399 .loc 1 3525 5 + 10400 0134 24E0 b .L850 + 10401 .L844: + 10402 .loc 1 3525 5 discriminator 2 + 10403 0136 3B68 ldr r3, [r7] + 10404 0138 042B cmp r3, #4 + 10405 013a 04D1 bne .L846 + 10406 .loc 1 3525 5 discriminator 3 + 10407 013c 7B68 ldr r3, [r7, #4] + 10408 013e 0122 movs r2, #1 + ARM GAS /tmp/ccl4b9YO.s page 244 + + + 10409 0140 83F84520 strb r2, [r3, #69] + 10410 .loc 1 3525 5 + 10411 0144 1CE0 b .L850 + 10412 .L846: + 10413 .loc 1 3525 5 discriminator 4 + 10414 0146 3B68 ldr r3, [r7] + 10415 0148 082B cmp r3, #8 + 10416 014a 04D1 bne .L848 + 10417 .loc 1 3525 5 discriminator 6 + 10418 014c 7B68 ldr r3, [r7, #4] + 10419 014e 0122 movs r2, #1 + 10420 0150 83F84620 strb r2, [r3, #70] + 10421 .loc 1 3525 5 + 10422 0154 14E0 b .L850 + 10423 .L848: + 10424 .loc 1 3525 5 discriminator 7 + 10425 0156 7B68 ldr r3, [r7, #4] + 10426 0158 0122 movs r2, #1 + 10427 015a 83F84720 strb r2, [r3, #71] + 10428 .loc 1 3525 5 + 10429 015e 0FE0 b .L850 + 10430 .L833: +3526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +3528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 10431 .loc 1 3529 5 is_stmt 1 + 10432 0160 7B68 ldr r3, [r7, #4] + 10433 0162 0122 movs r2, #1 + 10434 0164 83F83E20 strb r2, [r3, #62] +3530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 10435 .loc 1 3530 5 + 10436 0168 7B68 ldr r3, [r7, #4] + 10437 016a 0122 movs r2, #1 + 10438 016c 83F83F20 strb r2, [r3, #63] +3531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 10439 .loc 1 3531 5 + 10440 0170 7B68 ldr r3, [r7, #4] + 10441 0172 0122 movs r2, #1 + 10442 0174 83F84420 strb r2, [r3, #68] +3532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 10443 .loc 1 3532 5 + 10444 0178 7B68 ldr r3, [r7, #4] + 10445 017a 0122 movs r2, #1 + 10446 017c 83F84520 strb r2, [r3, #69] + 10447 .L850: +3533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return function status */ +3536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_OK; + 10448 .loc 1 3536 10 + 10449 0180 0023 movs r3, #0 +3537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 10450 .loc 1 3537 1 + 10451 0182 1846 mov r0, r3 + 10452 0184 0837 adds r7, r7, #8 + 10453 .cfi_def_cfa_offset 8 + ARM GAS /tmp/ccl4b9YO.s page 245 + + + 10454 0186 BD46 mov sp, r7 + 10455 .cfi_def_cfa_register 13 + 10456 @ sp needed + 10457 0188 80BD pop {r7, pc} + 10458 .cfi_endproc + 10459 .LFE185: + 10461 .section .text.HAL_TIM_Encoder_Start_DMA,"ax",%progbits + 10462 .align 1 + 10463 .global HAL_TIM_Encoder_Start_DMA + 10464 .syntax unified + 10465 .thumb + 10466 .thumb_func + 10468 HAL_TIM_Encoder_Start_DMA: + 10469 .LFB186: +3538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +3540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Starts the TIM Encoder Interface in DMA mode. +3541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM Encoder Interface handle +3542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param Channel TIM Channels to be enabled +3543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +3544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +3545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +3546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected +3547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param pData1 The destination Buffer address for IC1. +3548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param pData2 The destination Buffer address for IC2. +3549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param Length The length of data to be transferred from TIM peripheral to memory. +3550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status +3551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +3552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pD +3553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t *pData2, uint16_t Length) +3554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 10470 .loc 1 3554 1 + 10471 .cfi_startproc + 10472 @ args = 4, pretend = 0, frame = 24 + 10473 @ frame_needed = 1, uses_anonymous_args = 0 + 10474 0000 80B5 push {r7, lr} + 10475 .cfi_def_cfa_offset 8 + 10476 .cfi_offset 7, -8 + 10477 .cfi_offset 14, -4 + 10478 0002 86B0 sub sp, sp, #24 + 10479 .cfi_def_cfa_offset 32 + 10480 0004 00AF add r7, sp, #0 + 10481 .cfi_def_cfa_register 7 + 10482 0006 F860 str r0, [r7, #12] + 10483 0008 B960 str r1, [r7, #8] + 10484 000a 7A60 str r2, [r7, #4] + 10485 000c 3B60 str r3, [r7] +3555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + 10486 .loc 1 3555 31 + 10487 000e FB68 ldr r3, [r7, #12] + 10488 0010 93F83E30 ldrb r3, [r3, #62] + 10489 0014 FB75 strb r3, [r7, #23] +3556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + 10490 .loc 1 3556 31 + 10491 0016 FB68 ldr r3, [r7, #12] + 10492 0018 93F83F30 ldrb r3, [r3, #63] + 10493 001c BB75 strb r3, [r7, #22] + ARM GAS /tmp/ccl4b9YO.s page 246 + + +3557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 10494 .loc 1 3557 31 + 10495 001e FB68 ldr r3, [r7, #12] + 10496 0020 93F84430 ldrb r3, [r3, #68] + 10497 0024 7B75 strb r3, [r7, #21] +3558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 10498 .loc 1 3558 31 + 10499 0026 FB68 ldr r3, [r7, #12] + 10500 0028 93F84530 ldrb r3, [r3, #69] + 10501 002c 3B75 strb r3, [r7, #20] +3559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +3561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); +3562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the TIM channel(s) state */ +3564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (Channel == TIM_CHANNEL_1) + 10502 .loc 1 3564 6 + 10503 002e BB68 ldr r3, [r7, #8] + 10504 0030 002B cmp r3, #0 + 10505 0032 20D1 bne .L853 +3565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + 10506 .loc 1 3566 8 + 10507 0034 FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 10508 0036 022B cmp r3, #2 + 10509 0038 02D0 beq .L854 +3567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) + 10510 .loc 1 3567 9 + 10511 003a 7B7D ldrb r3, [r7, #21] @ zero_extendqisi2 + 10512 003c 022B cmp r3, #2 + 10513 003e 01D1 bne .L855 + 10514 .L854: +3568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_BUSY; + 10515 .loc 1 3569 14 + 10516 0040 0223 movs r3, #2 + 10517 0042 3FE1 b .L856 + 10518 .L855: +3570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + 10519 .loc 1 3571 13 + 10520 0044 FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 10521 0046 012B cmp r3, #1 + 10522 0048 13D1 bne .L857 +3572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) + 10523 .loc 1 3572 14 + 10524 004a 7B7D ldrb r3, [r7, #21] @ zero_extendqisi2 + 10525 004c 012B cmp r3, #1 + 10526 004e 10D1 bne .L857 +3573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if ((pData1 == NULL) || (Length == 0U)) + 10527 .loc 1 3574 10 + 10528 0050 7B68 ldr r3, [r7, #4] + 10529 0052 002B cmp r3, #0 + 10530 0054 02D0 beq .L858 + 10531 .loc 1 3574 28 discriminator 1 + 10532 0056 3B8C ldrh r3, [r7, #32] + ARM GAS /tmp/ccl4b9YO.s page 247 + + + 10533 0058 002B cmp r3, #0 + 10534 005a 01D1 bne .L859 + 10535 .L858: +3575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 10536 .loc 1 3576 16 + 10537 005c 0123 movs r3, #1 + 10538 005e 31E1 b .L856 + 10539 .L859: +3577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +3579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + 10540 .loc 1 3580 9 + 10541 0060 FB68 ldr r3, [r7, #12] + 10542 0062 0222 movs r2, #2 + 10543 0064 83F83E20 strb r2, [r3, #62] +3581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + 10544 .loc 1 3581 9 + 10545 0068 FB68 ldr r3, [r7, #12] + 10546 006a 0222 movs r2, #2 + 10547 006c 83F84420 strb r2, [r3, #68] +3574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 10548 .loc 1 3574 10 + 10549 0070 5DE0 b .L861 + 10550 .L857: +3582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +3585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 10551 .loc 1 3586 14 + 10552 0072 0123 movs r3, #1 + 10553 0074 26E1 b .L856 + 10554 .L853: +3587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else if (Channel == TIM_CHANNEL_2) + 10555 .loc 1 3589 11 + 10556 0076 BB68 ldr r3, [r7, #8] + 10557 0078 042B cmp r3, #4 + 10558 007a 20D1 bne .L862 +3590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) + 10559 .loc 1 3591 8 + 10560 007c BB7D ldrb r3, [r7, #22] @ zero_extendqisi2 + 10561 007e 022B cmp r3, #2 + 10562 0080 02D0 beq .L863 +3592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) + 10563 .loc 1 3592 9 + 10564 0082 3B7D ldrb r3, [r7, #20] @ zero_extendqisi2 + 10565 0084 022B cmp r3, #2 + 10566 0086 01D1 bne .L864 + 10567 .L863: +3593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_BUSY; + 10568 .loc 1 3594 14 + ARM GAS /tmp/ccl4b9YO.s page 248 + + + 10569 0088 0223 movs r3, #2 + 10570 008a 1BE1 b .L856 + 10571 .L864: +3595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY) + 10572 .loc 1 3596 13 + 10573 008c BB7D ldrb r3, [r7, #22] @ zero_extendqisi2 + 10574 008e 012B cmp r3, #1 + 10575 0090 13D1 bne .L865 +3597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + 10576 .loc 1 3597 14 + 10577 0092 3B7D ldrb r3, [r7, #20] @ zero_extendqisi2 + 10578 0094 012B cmp r3, #1 + 10579 0096 10D1 bne .L865 +3598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if ((pData2 == NULL) || (Length == 0U)) + 10580 .loc 1 3599 10 + 10581 0098 3B68 ldr r3, [r7] + 10582 009a 002B cmp r3, #0 + 10583 009c 02D0 beq .L866 + 10584 .loc 1 3599 28 discriminator 1 + 10585 009e 3B8C ldrh r3, [r7, #32] + 10586 00a0 002B cmp r3, #0 + 10587 00a2 01D1 bne .L867 + 10588 .L866: +3600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 10589 .loc 1 3601 16 + 10590 00a4 0123 movs r3, #1 + 10591 00a6 0DE1 b .L856 + 10592 .L867: +3602:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +3604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 10593 .loc 1 3605 9 + 10594 00a8 FB68 ldr r3, [r7, #12] + 10595 00aa 0222 movs r2, #2 + 10596 00ac 83F83F20 strb r2, [r3, #63] +3606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 10597 .loc 1 3606 9 + 10598 00b0 FB68 ldr r3, [r7, #12] + 10599 00b2 0222 movs r2, #2 + 10600 00b4 83F84520 strb r2, [r3, #69] +3599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 10601 .loc 1 3599 10 + 10602 00b8 39E0 b .L861 + 10603 .L865: +3607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +3610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 10604 .loc 1 3611 14 + 10605 00ba 0123 movs r3, #1 + 10606 00bc 02E1 b .L856 + 10607 .L862: + ARM GAS /tmp/ccl4b9YO.s page 249 + + +3612:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +3615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + 10608 .loc 1 3616 8 + 10609 00be FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 10610 00c0 022B cmp r3, #2 + 10611 00c2 08D0 beq .L869 +3617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) + 10612 .loc 1 3617 9 + 10613 00c4 BB7D ldrb r3, [r7, #22] @ zero_extendqisi2 + 10614 00c6 022B cmp r3, #2 + 10615 00c8 05D0 beq .L869 +3618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + 10616 .loc 1 3618 9 + 10617 00ca 7B7D ldrb r3, [r7, #21] @ zero_extendqisi2 + 10618 00cc 022B cmp r3, #2 + 10619 00ce 02D0 beq .L869 +3619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) + 10620 .loc 1 3619 9 + 10621 00d0 3B7D ldrb r3, [r7, #20] @ zero_extendqisi2 + 10622 00d2 022B cmp r3, #2 + 10623 00d4 01D1 bne .L870 + 10624 .L869: +3620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_BUSY; + 10625 .loc 1 3621 14 + 10626 00d6 0223 movs r3, #2 + 10627 00d8 F4E0 b .L856 + 10628 .L870: +3622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + 10629 .loc 1 3623 13 + 10630 00da FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 10631 00dc 012B cmp r3, #1 + 10632 00de 24D1 bne .L871 +3624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY) + 10633 .loc 1 3624 14 + 10634 00e0 BB7D ldrb r3, [r7, #22] @ zero_extendqisi2 + 10635 00e2 012B cmp r3, #1 + 10636 00e4 21D1 bne .L871 +3625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + 10637 .loc 1 3625 14 + 10638 00e6 7B7D ldrb r3, [r7, #21] @ zero_extendqisi2 + 10639 00e8 012B cmp r3, #1 + 10640 00ea 1ED1 bne .L871 +3626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + 10641 .loc 1 3626 14 + 10642 00ec 3B7D ldrb r3, [r7, #20] @ zero_extendqisi2 + 10643 00ee 012B cmp r3, #1 + 10644 00f0 1BD1 bne .L871 +3627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if ((((pData1 == NULL) || (pData2 == NULL))) || (Length == 0U)) + 10645 .loc 1 3628 10 + 10646 00f2 7B68 ldr r3, [r7, #4] + 10647 00f4 002B cmp r3, #0 + ARM GAS /tmp/ccl4b9YO.s page 250 + + + 10648 00f6 05D0 beq .L872 + 10649 .loc 1 3628 30 discriminator 1 + 10650 00f8 3B68 ldr r3, [r7] + 10651 00fa 002B cmp r3, #0 + 10652 00fc 02D0 beq .L872 + 10653 .loc 1 3628 52 discriminator 2 + 10654 00fe 3B8C ldrh r3, [r7, #32] + 10655 0100 002B cmp r3, #0 + 10656 0102 01D1 bne .L873 + 10657 .L872: +3629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 10658 .loc 1 3630 16 + 10659 0104 0123 movs r3, #1 + 10660 0106 DDE0 b .L856 + 10661 .L873: +3631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +3633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + 10662 .loc 1 3634 9 + 10663 0108 FB68 ldr r3, [r7, #12] + 10664 010a 0222 movs r2, #2 + 10665 010c 83F83E20 strb r2, [r3, #62] +3635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 10666 .loc 1 3635 9 + 10667 0110 FB68 ldr r3, [r7, #12] + 10668 0112 0222 movs r2, #2 + 10669 0114 83F83F20 strb r2, [r3, #63] +3636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + 10670 .loc 1 3636 9 + 10671 0118 FB68 ldr r3, [r7, #12] + 10672 011a 0222 movs r2, #2 + 10673 011c 83F84420 strb r2, [r3, #68] +3637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 10674 .loc 1 3637 9 + 10675 0120 FB68 ldr r3, [r7, #12] + 10676 0122 0222 movs r2, #2 + 10677 0124 83F84520 strb r2, [r3, #69] +3628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 10678 .loc 1 3628 10 + 10679 0128 01E0 b .L861 + 10680 .L871: +3638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +3641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3642:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 10681 .loc 1 3642 14 + 10682 012a 0123 movs r3, #1 + 10683 012c CAE0 b .L856 + 10684 .L861: +3643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** switch (Channel) + 10685 .loc 1 3646 3 + ARM GAS /tmp/ccl4b9YO.s page 251 + + + 10686 012e BB68 ldr r3, [r7, #8] + 10687 0130 002B cmp r3, #0 + 10688 0132 03D0 beq .L874 + 10689 0134 BB68 ldr r3, [r7, #8] + 10690 0136 042B cmp r3, #4 + 10691 0138 33D0 beq .L875 + 10692 013a 65E0 b .L882 + 10693 .L874: +3647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_1: +3649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA capture callbacks */ +3651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + 10694 .loc 1 3651 17 + 10695 013c FB68 ldr r3, [r7, #12] + 10696 013e 5B6A ldr r3, [r3, #36] + 10697 .loc 1 3651 52 + 10698 0140 624A ldr r2, .L883 + 10699 0142 9A62 str r2, [r3, #40] +3652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 10700 .loc 1 3652 17 + 10701 0144 FB68 ldr r3, [r7, #12] + 10702 0146 5B6A ldr r3, [r3, #36] + 10703 .loc 1 3652 56 + 10704 0148 614A ldr r2, .L883+4 + 10705 014a DA62 str r2, [r3, #44] +3653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA error callback */ +3655:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + 10706 .loc 1 3655 17 + 10707 014c FB68 ldr r3, [r7, #12] + 10708 014e 5B6A ldr r3, [r3, #36] + 10709 .loc 1 3655 53 + 10710 0150 604A ldr r2, .L883+8 + 10711 0152 1A63 str r2, [r3, #48] +3656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3657:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the DMA channel */ +3658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)p + 10712 .loc 1 3658 11 + 10713 0154 FB68 ldr r3, [r7, #12] + 10714 0156 586A ldr r0, [r3, #36] + 10715 .loc 1 3658 71 + 10716 0158 FB68 ldr r3, [r7, #12] + 10717 015a 1B68 ldr r3, [r3] + 10718 .loc 1 3658 66 + 10719 015c 3433 adds r3, r3, #52 + 10720 .loc 1 3658 11 + 10721 015e 1946 mov r1, r3 + 10722 0160 7A68 ldr r2, [r7, #4] + 10723 0162 3B8C ldrh r3, [r7, #32] + 10724 0164 FFF7FEFF bl HAL_DMA_Start_IT + 10725 0168 0346 mov r3, r0 + 10726 .loc 1 3658 10 discriminator 1 + 10727 016a 002B cmp r3, #0 + 10728 016c 01D0 beq .L877 +3659:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** Length) != HAL_OK) +3660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + ARM GAS /tmp/ccl4b9YO.s page 252 + + +3661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return error status */ +3662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 10729 .loc 1 3662 16 + 10730 016e 0123 movs r3, #1 + 10731 0170 A8E0 b .L856 + 10732 .L877: +3663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3664:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the TIM Input Capture DMA request */ +3665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + 10733 .loc 1 3665 7 + 10734 0172 FB68 ldr r3, [r7, #12] + 10735 0174 1B68 ldr r3, [r3] + 10736 0176 DA68 ldr r2, [r3, #12] + 10737 0178 FB68 ldr r3, [r7, #12] + 10738 017a 1B68 ldr r3, [r3] + 10739 017c 42F40072 orr r2, r2, #512 + 10740 0180 DA60 str r2, [r3, #12] +3666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the Capture compare channel */ +3668:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + 10741 .loc 1 3668 7 + 10742 0182 FB68 ldr r3, [r7, #12] + 10743 0184 1B68 ldr r3, [r3] + 10744 0186 0122 movs r2, #1 + 10745 0188 0021 movs r1, #0 + 10746 018a 1846 mov r0, r3 + 10747 018c FFF7FEFF bl TIM_CCxChannelCmd +3669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the Peripheral */ +3671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); + 10748 .loc 1 3671 7 + 10749 0190 FB68 ldr r3, [r7, #12] + 10750 0192 1B68 ldr r3, [r3] + 10751 0194 1A68 ldr r2, [r3] + 10752 0196 FB68 ldr r3, [r7, #12] + 10753 0198 1B68 ldr r3, [r3] + 10754 019a 42F00102 orr r2, r2, #1 + 10755 019e 1A60 str r2, [r3] +3672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 10756 .loc 1 3673 7 + 10757 01a0 8FE0 b .L878 + 10758 .L875: +3674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_2: +3677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA capture callbacks */ +3679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + 10759 .loc 1 3679 17 + 10760 01a2 FB68 ldr r3, [r7, #12] + 10761 01a4 9B6A ldr r3, [r3, #40] + 10762 .loc 1 3679 52 + 10763 01a6 494A ldr r2, .L883 + 10764 01a8 9A62 str r2, [r3, #40] +3680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 10765 .loc 1 3680 17 + ARM GAS /tmp/ccl4b9YO.s page 253 + + + 10766 01aa FB68 ldr r3, [r7, #12] + 10767 01ac 9B6A ldr r3, [r3, #40] + 10768 .loc 1 3680 56 + 10769 01ae 484A ldr r2, .L883+4 + 10770 01b0 DA62 str r2, [r3, #44] +3681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA error callback */ +3683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; + 10771 .loc 1 3683 17 + 10772 01b2 FB68 ldr r3, [r7, #12] + 10773 01b4 9B6A ldr r3, [r3, #40] + 10774 .loc 1 3683 53 + 10775 01b6 474A ldr r2, .L883+8 + 10776 01b8 1A63 str r2, [r3, #48] +3684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the DMA channel */ +3685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)p + 10777 .loc 1 3685 11 + 10778 01ba FB68 ldr r3, [r7, #12] + 10779 01bc 986A ldr r0, [r3, #40] + 10780 .loc 1 3685 71 + 10781 01be FB68 ldr r3, [r7, #12] + 10782 01c0 1B68 ldr r3, [r3] + 10783 .loc 1 3685 66 + 10784 01c2 3833 adds r3, r3, #56 + 10785 .loc 1 3685 11 + 10786 01c4 1946 mov r1, r3 + 10787 01c6 3A68 ldr r2, [r7] + 10788 01c8 3B8C ldrh r3, [r7, #32] + 10789 01ca FFF7FEFF bl HAL_DMA_Start_IT + 10790 01ce 0346 mov r3, r0 + 10791 .loc 1 3685 10 discriminator 1 + 10792 01d0 002B cmp r3, #0 + 10793 01d2 01D0 beq .L879 +3686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** Length) != HAL_OK) +3687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3688:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return error status */ +3689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 10794 .loc 1 3689 16 + 10795 01d4 0123 movs r3, #1 + 10796 01d6 75E0 b .L856 + 10797 .L879: +3690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the TIM Input Capture DMA request */ +3692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + 10798 .loc 1 3692 7 + 10799 01d8 FB68 ldr r3, [r7, #12] + 10800 01da 1B68 ldr r3, [r3] + 10801 01dc DA68 ldr r2, [r3, #12] + 10802 01de FB68 ldr r3, [r7, #12] + 10803 01e0 1B68 ldr r3, [r3] + 10804 01e2 42F48062 orr r2, r2, #1024 + 10805 01e6 DA60 str r2, [r3, #12] +3693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3694:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the Capture compare channel */ +3695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + 10806 .loc 1 3695 7 + 10807 01e8 FB68 ldr r3, [r7, #12] + ARM GAS /tmp/ccl4b9YO.s page 254 + + + 10808 01ea 1B68 ldr r3, [r3] + 10809 01ec 0122 movs r2, #1 + 10810 01ee 0421 movs r1, #4 + 10811 01f0 1846 mov r0, r3 + 10812 01f2 FFF7FEFF bl TIM_CCxChannelCmd +3696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the Peripheral */ +3698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); + 10813 .loc 1 3698 7 + 10814 01f6 FB68 ldr r3, [r7, #12] + 10815 01f8 1B68 ldr r3, [r3] + 10816 01fa 1A68 ldr r2, [r3] + 10817 01fc FB68 ldr r3, [r7, #12] + 10818 01fe 1B68 ldr r3, [r3] + 10819 0200 42F00102 orr r2, r2, #1 + 10820 0204 1A60 str r2, [r3] +3699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3700:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 10821 .loc 1 3700 7 + 10822 0206 5CE0 b .L878 + 10823 .L882: +3701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** default: +3704:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA capture callbacks */ +3706:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + 10824 .loc 1 3706 17 + 10825 0208 FB68 ldr r3, [r7, #12] + 10826 020a 5B6A ldr r3, [r3, #36] + 10827 .loc 1 3706 52 + 10828 020c 2F4A ldr r2, .L883 + 10829 020e 9A62 str r2, [r3, #40] +3707:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 10830 .loc 1 3707 17 + 10831 0210 FB68 ldr r3, [r7, #12] + 10832 0212 5B6A ldr r3, [r3, #36] + 10833 .loc 1 3707 56 + 10834 0214 2E4A ldr r2, .L883+4 + 10835 0216 DA62 str r2, [r3, #44] +3708:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA error callback */ +3710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + 10836 .loc 1 3710 17 + 10837 0218 FB68 ldr r3, [r7, #12] + 10838 021a 5B6A ldr r3, [r3, #36] + 10839 .loc 1 3710 53 + 10840 021c 2D4A ldr r2, .L883+8 + 10841 021e 1A63 str r2, [r3, #48] +3711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the DMA channel */ +3713:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)p + 10842 .loc 1 3713 11 + 10843 0220 FB68 ldr r3, [r7, #12] + 10844 0222 586A ldr r0, [r3, #36] + 10845 .loc 1 3713 71 + 10846 0224 FB68 ldr r3, [r7, #12] + ARM GAS /tmp/ccl4b9YO.s page 255 + + + 10847 0226 1B68 ldr r3, [r3] + 10848 .loc 1 3713 66 + 10849 0228 3433 adds r3, r3, #52 + 10850 .loc 1 3713 11 + 10851 022a 1946 mov r1, r3 + 10852 022c 7A68 ldr r2, [r7, #4] + 10853 022e 3B8C ldrh r3, [r7, #32] + 10854 0230 FFF7FEFF bl HAL_DMA_Start_IT + 10855 0234 0346 mov r3, r0 + 10856 .loc 1 3713 10 discriminator 1 + 10857 0236 002B cmp r3, #0 + 10858 0238 01D0 beq .L880 +3714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** Length) != HAL_OK) +3715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3716:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return error status */ +3717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 10859 .loc 1 3717 16 + 10860 023a 0123 movs r3, #1 + 10861 023c 42E0 b .L856 + 10862 .L880: +3718:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3720:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA capture callbacks */ +3721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + 10863 .loc 1 3721 17 + 10864 023e FB68 ldr r3, [r7, #12] + 10865 0240 9B6A ldr r3, [r3, #40] + 10866 .loc 1 3721 52 + 10867 0242 224A ldr r2, .L883 + 10868 0244 9A62 str r2, [r3, #40] +3722:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 10869 .loc 1 3722 17 + 10870 0246 FB68 ldr r3, [r7, #12] + 10871 0248 9B6A ldr r3, [r3, #40] + 10872 .loc 1 3722 56 + 10873 024a 214A ldr r2, .L883+4 + 10874 024c DA62 str r2, [r3, #44] +3723:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3724:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA error callback */ +3725:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + 10875 .loc 1 3725 17 + 10876 024e FB68 ldr r3, [r7, #12] + 10877 0250 9B6A ldr r3, [r3, #40] + 10878 .loc 1 3725 53 + 10879 0252 204A ldr r2, .L883+8 + 10880 0254 1A63 str r2, [r3, #48] +3726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3727:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the DMA channel */ +3728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)p + 10881 .loc 1 3728 11 + 10882 0256 FB68 ldr r3, [r7, #12] + 10883 0258 986A ldr r0, [r3, #40] + 10884 .loc 1 3728 71 + 10885 025a FB68 ldr r3, [r7, #12] + 10886 025c 1B68 ldr r3, [r3] + 10887 .loc 1 3728 66 + 10888 025e 3833 adds r3, r3, #56 + ARM GAS /tmp/ccl4b9YO.s page 256 + + + 10889 .loc 1 3728 11 + 10890 0260 1946 mov r1, r3 + 10891 0262 3A68 ldr r2, [r7] + 10892 0264 3B8C ldrh r3, [r7, #32] + 10893 0266 FFF7FEFF bl HAL_DMA_Start_IT + 10894 026a 0346 mov r3, r0 + 10895 .loc 1 3728 10 discriminator 1 + 10896 026c 002B cmp r3, #0 + 10897 026e 01D0 beq .L881 +3729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** Length) != HAL_OK) +3730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return error status */ +3732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 10898 .loc 1 3732 16 + 10899 0270 0123 movs r3, #1 + 10900 0272 27E0 b .L856 + 10901 .L881: +3733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3734:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the TIM Input Capture DMA request */ +3736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + 10902 .loc 1 3736 7 + 10903 0274 FB68 ldr r3, [r7, #12] + 10904 0276 1B68 ldr r3, [r3] + 10905 0278 DA68 ldr r2, [r3, #12] + 10906 027a FB68 ldr r3, [r7, #12] + 10907 027c 1B68 ldr r3, [r3] + 10908 027e 42F40072 orr r2, r2, #512 + 10909 0282 DA60 str r2, [r3, #12] +3737:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the TIM Input Capture DMA request */ +3738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + 10910 .loc 1 3738 7 + 10911 0284 FB68 ldr r3, [r7, #12] + 10912 0286 1B68 ldr r3, [r3] + 10913 0288 DA68 ldr r2, [r3, #12] + 10914 028a FB68 ldr r3, [r7, #12] + 10915 028c 1B68 ldr r3, [r3] + 10916 028e 42F48062 orr r2, r2, #1024 + 10917 0292 DA60 str r2, [r3, #12] +3739:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the Capture compare channel */ +3741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + 10918 .loc 1 3741 7 + 10919 0294 FB68 ldr r3, [r7, #12] + 10920 0296 1B68 ldr r3, [r3] + 10921 0298 0122 movs r2, #1 + 10922 029a 0021 movs r1, #0 + 10923 029c 1846 mov r0, r3 + 10924 029e FFF7FEFF bl TIM_CCxChannelCmd +3742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + 10925 .loc 1 3742 7 + 10926 02a2 FB68 ldr r3, [r7, #12] + 10927 02a4 1B68 ldr r3, [r3] + 10928 02a6 0122 movs r2, #1 + 10929 02a8 0421 movs r1, #4 + 10930 02aa 1846 mov r0, r3 + 10931 02ac FFF7FEFF bl TIM_CCxChannelCmd + ARM GAS /tmp/ccl4b9YO.s page 257 + + +3743:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the Peripheral */ +3745:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE(htim); + 10932 .loc 1 3745 7 + 10933 02b0 FB68 ldr r3, [r7, #12] + 10934 02b2 1B68 ldr r3, [r3] + 10935 02b4 1A68 ldr r2, [r3] + 10936 02b6 FB68 ldr r3, [r7, #12] + 10937 02b8 1B68 ldr r3, [r3] + 10938 02ba 42F00102 orr r2, r2, #1 + 10939 02be 1A60 str r2, [r3] +3746:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3747:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 10940 .loc 1 3747 7 + 10941 02c0 00BF nop + 10942 .L878: +3748:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return function status */ +3752:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_OK; + 10943 .loc 1 3752 10 + 10944 02c2 0023 movs r3, #0 + 10945 .L856: +3753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 10946 .loc 1 3753 1 + 10947 02c4 1846 mov r0, r3 + 10948 02c6 1837 adds r7, r7, #24 + 10949 .cfi_def_cfa_offset 8 + 10950 02c8 BD46 mov sp, r7 + 10951 .cfi_def_cfa_register 13 + 10952 @ sp needed + 10953 02ca 80BD pop {r7, pc} + 10954 .L884: + 10955 .align 2 + 10956 .L883: + 10957 02cc 00000000 .word TIM_DMACaptureCplt + 10958 02d0 00000000 .word TIM_DMACaptureHalfCplt + 10959 02d4 00000000 .word TIM_DMAError + 10960 .cfi_endproc + 10961 .LFE186: + 10963 .section .text.HAL_TIM_Encoder_Stop_DMA,"ax",%progbits + 10964 .align 1 + 10965 .global HAL_TIM_Encoder_Stop_DMA + 10966 .syntax unified + 10967 .thumb + 10968 .thumb_func + 10970 HAL_TIM_Encoder_Stop_DMA: + 10971 .LFB187: +3754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3755:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +3756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Stops the TIM Encoder Interface in DMA mode. +3757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM Encoder Interface handle +3758:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param Channel TIM Channels to be enabled +3759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +3760:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +3761:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected + ARM GAS /tmp/ccl4b9YO.s page 258 + + +3762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected +3763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status +3764:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +3765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +3766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 10972 .loc 1 3766 1 + 10973 .cfi_startproc + 10974 @ args = 0, pretend = 0, frame = 8 + 10975 @ frame_needed = 1, uses_anonymous_args = 0 + 10976 0000 80B5 push {r7, lr} + 10977 .cfi_def_cfa_offset 8 + 10978 .cfi_offset 7, -8 + 10979 .cfi_offset 14, -4 + 10980 0002 82B0 sub sp, sp, #8 + 10981 .cfi_def_cfa_offset 16 + 10982 0004 00AF add r7, sp, #0 + 10983 .cfi_def_cfa_register 7 + 10984 0006 7860 str r0, [r7, #4] + 10985 0008 3960 str r1, [r7] +3767:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +3768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); +3769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the Input Capture channels 1 and 2 +3771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_C +3772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (Channel == TIM_CHANNEL_1) + 10986 .loc 1 3772 6 + 10987 000a 3B68 ldr r3, [r7] + 10988 000c 002B cmp r3, #0 + 10989 000e 14D1 bne .L886 +3773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + 10990 .loc 1 3774 5 + 10991 0010 7B68 ldr r3, [r7, #4] + 10992 0012 1B68 ldr r3, [r3] + 10993 0014 0022 movs r2, #0 + 10994 0016 0021 movs r1, #0 + 10995 0018 1846 mov r0, r3 + 10996 001a FFF7FEFF bl TIM_CCxChannelCmd +3775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the capture compare DMA Request 1 */ +3777:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + 10997 .loc 1 3777 5 + 10998 001e 7B68 ldr r3, [r7, #4] + 10999 0020 1B68 ldr r3, [r3] + 11000 0022 DA68 ldr r2, [r3, #12] + 11001 0024 7B68 ldr r3, [r7, #4] + 11002 0026 1B68 ldr r3, [r3] + 11003 0028 22F40072 bic r2, r2, #512 + 11004 002c DA60 str r2, [r3, #12] +3778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + 11005 .loc 1 3778 11 + 11006 002e 7B68 ldr r3, [r7, #4] + 11007 0030 5B6A ldr r3, [r3, #36] + 11008 0032 1846 mov r0, r3 + 11009 0034 FFF7FEFF bl HAL_DMA_Abort_IT + 11010 0038 3FE0 b .L887 + 11011 .L886: + ARM GAS /tmp/ccl4b9YO.s page 259 + + +3779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3780:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else if (Channel == TIM_CHANNEL_2) + 11012 .loc 1 3780 11 + 11013 003a 3B68 ldr r3, [r7] + 11014 003c 042B cmp r3, #4 + 11015 003e 14D1 bne .L888 +3781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3782:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + 11016 .loc 1 3782 5 + 11017 0040 7B68 ldr r3, [r7, #4] + 11018 0042 1B68 ldr r3, [r3] + 11019 0044 0022 movs r2, #0 + 11020 0046 0421 movs r1, #4 + 11021 0048 1846 mov r0, r3 + 11022 004a FFF7FEFF bl TIM_CCxChannelCmd +3783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the capture compare DMA Request 2 */ +3785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + 11023 .loc 1 3785 5 + 11024 004e 7B68 ldr r3, [r7, #4] + 11025 0050 1B68 ldr r3, [r3] + 11026 0052 DA68 ldr r2, [r3, #12] + 11027 0054 7B68 ldr r3, [r7, #4] + 11028 0056 1B68 ldr r3, [r3] + 11029 0058 22F48062 bic r2, r2, #1024 + 11030 005c DA60 str r2, [r3, #12] +3786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + 11031 .loc 1 3786 11 + 11032 005e 7B68 ldr r3, [r7, #4] + 11033 0060 9B6A ldr r3, [r3, #40] + 11034 0062 1846 mov r0, r3 + 11035 0064 FFF7FEFF bl HAL_DMA_Abort_IT + 11036 0068 27E0 b .L887 + 11037 .L888: +3787:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3788:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +3789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + 11038 .loc 1 3790 5 + 11039 006a 7B68 ldr r3, [r7, #4] + 11040 006c 1B68 ldr r3, [r3] + 11041 006e 0022 movs r2, #0 + 11042 0070 0021 movs r1, #0 + 11043 0072 1846 mov r0, r3 + 11044 0074 FFF7FEFF bl TIM_CCxChannelCmd +3791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + 11045 .loc 1 3791 5 + 11046 0078 7B68 ldr r3, [r7, #4] + 11047 007a 1B68 ldr r3, [r3] + 11048 007c 0022 movs r2, #0 + 11049 007e 0421 movs r1, #4 + 11050 0080 1846 mov r0, r3 + 11051 0082 FFF7FEFF bl TIM_CCxChannelCmd +3792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the capture compare DMA Request 1 and 2 */ +3794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + 11052 .loc 1 3794 5 + ARM GAS /tmp/ccl4b9YO.s page 260 + + + 11053 0086 7B68 ldr r3, [r7, #4] + 11054 0088 1B68 ldr r3, [r3] + 11055 008a DA68 ldr r2, [r3, #12] + 11056 008c 7B68 ldr r3, [r7, #4] + 11057 008e 1B68 ldr r3, [r3] + 11058 0090 22F40072 bic r2, r2, #512 + 11059 0094 DA60 str r2, [r3, #12] +3795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + 11060 .loc 1 3795 5 + 11061 0096 7B68 ldr r3, [r7, #4] + 11062 0098 1B68 ldr r3, [r3] + 11063 009a DA68 ldr r2, [r3, #12] + 11064 009c 7B68 ldr r3, [r7, #4] + 11065 009e 1B68 ldr r3, [r3] + 11066 00a0 22F48062 bic r2, r2, #1024 + 11067 00a4 DA60 str r2, [r3, #12] +3796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + 11068 .loc 1 3796 11 + 11069 00a6 7B68 ldr r3, [r7, #4] + 11070 00a8 5B6A ldr r3, [r3, #36] + 11071 00aa 1846 mov r0, r3 + 11072 00ac FFF7FEFF bl HAL_DMA_Abort_IT +3797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + 11073 .loc 1 3797 11 + 11074 00b0 7B68 ldr r3, [r7, #4] + 11075 00b2 9B6A ldr r3, [r3, #40] + 11076 00b4 1846 mov r0, r3 + 11077 00b6 FFF7FEFF bl HAL_DMA_Abort_IT + 11078 .L887: +3798:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3799:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the Peripheral */ +3801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE(htim); + 11079 .loc 1 3801 3 + 11080 00ba 7B68 ldr r3, [r7, #4] + 11081 00bc 1B68 ldr r3, [r3] + 11082 00be 1A6A ldr r2, [r3, #32] + 11083 00c0 41F21113 movw r3, #4369 + 11084 00c4 1340 ands r3, r3, r2 + 11085 00c6 002B cmp r3, #0 + 11086 00c8 0FD1 bne .L889 + 11087 .loc 1 3801 3 is_stmt 0 discriminator 1 + 11088 00ca 7B68 ldr r3, [r7, #4] + 11089 00cc 1B68 ldr r3, [r3] + 11090 00ce 1A6A ldr r2, [r3, #32] + 11091 00d0 40F24443 movw r3, #1092 + 11092 00d4 1340 ands r3, r3, r2 + 11093 00d6 002B cmp r3, #0 + 11094 00d8 07D1 bne .L889 + 11095 .loc 1 3801 3 discriminator 2 + 11096 00da 7B68 ldr r3, [r7, #4] + 11097 00dc 1B68 ldr r3, [r3] + 11098 00de 1A68 ldr r2, [r3] + 11099 00e0 7B68 ldr r3, [r7, #4] + 11100 00e2 1B68 ldr r3, [r3] + 11101 00e4 22F00102 bic r2, r2, #1 + 11102 00e8 1A60 str r2, [r3] + ARM GAS /tmp/ccl4b9YO.s page 261 + + + 11103 .L889: +3802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3803:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the TIM channel(s) state */ +3804:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + 11104 .loc 1 3804 6 is_stmt 1 + 11105 00ea 3B68 ldr r3, [r7] + 11106 00ec 002B cmp r3, #0 + 11107 00ee 02D0 beq .L890 + 11108 .loc 1 3804 34 discriminator 1 + 11109 00f0 3B68 ldr r3, [r7] + 11110 00f2 042B cmp r3, #4 + 11111 00f4 48D1 bne .L891 + 11112 .L890: +3805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3806:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 11113 .loc 1 3806 5 + 11114 00f6 3B68 ldr r3, [r7] + 11115 00f8 002B cmp r3, #0 + 11116 00fa 04D1 bne .L892 + 11117 .loc 1 3806 5 is_stmt 0 discriminator 1 + 11118 00fc 7B68 ldr r3, [r7, #4] + 11119 00fe 0122 movs r2, #1 + 11120 0100 83F83E20 strb r2, [r3, #62] + 11121 0104 23E0 b .L893 + 11122 .L892: + 11123 .loc 1 3806 5 discriminator 2 + 11124 0106 3B68 ldr r3, [r7] + 11125 0108 042B cmp r3, #4 + 11126 010a 04D1 bne .L894 + 11127 .loc 1 3806 5 discriminator 3 + 11128 010c 7B68 ldr r3, [r7, #4] + 11129 010e 0122 movs r2, #1 + 11130 0110 83F83F20 strb r2, [r3, #63] + 11131 0114 1BE0 b .L893 + 11132 .L894: + 11133 .loc 1 3806 5 discriminator 4 + 11134 0116 3B68 ldr r3, [r7] + 11135 0118 082B cmp r3, #8 + 11136 011a 04D1 bne .L896 + 11137 .loc 1 3806 5 discriminator 6 + 11138 011c 7B68 ldr r3, [r7, #4] + 11139 011e 0122 movs r2, #1 + 11140 0120 83F84020 strb r2, [r3, #64] + 11141 0124 13E0 b .L893 + 11142 .L896: + 11143 .loc 1 3806 5 discriminator 7 + 11144 0126 3B68 ldr r3, [r7] + 11145 0128 0C2B cmp r3, #12 + 11146 012a 04D1 bne .L898 + 11147 .loc 1 3806 5 discriminator 9 + 11148 012c 7B68 ldr r3, [r7, #4] + 11149 012e 0122 movs r2, #1 + 11150 0130 83F84120 strb r2, [r3, #65] + 11151 0134 0BE0 b .L893 + 11152 .L898: + 11153 .loc 1 3806 5 discriminator 10 + 11154 0136 3B68 ldr r3, [r7] + ARM GAS /tmp/ccl4b9YO.s page 262 + + + 11155 0138 102B cmp r3, #16 + 11156 013a 04D1 bne .L900 + 11157 .loc 1 3806 5 discriminator 12 + 11158 013c 7B68 ldr r3, [r7, #4] + 11159 013e 0122 movs r2, #1 + 11160 0140 83F84220 strb r2, [r3, #66] + 11161 0144 03E0 b .L893 + 11162 .L900: + 11163 .loc 1 3806 5 discriminator 13 + 11164 0146 7B68 ldr r3, [r7, #4] + 11165 0148 0122 movs r2, #1 + 11166 014a 83F84320 strb r2, [r3, #67] + 11167 .L893: +3807:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 11168 .loc 1 3807 5 is_stmt 1 + 11169 014e 3B68 ldr r3, [r7] + 11170 0150 002B cmp r3, #0 + 11171 0152 04D1 bne .L902 + 11172 .loc 1 3807 5 is_stmt 0 discriminator 1 + 11173 0154 7B68 ldr r3, [r7, #4] + 11174 0156 0122 movs r2, #1 + 11175 0158 83F84420 strb r2, [r3, #68] + 11176 .loc 1 3807 5 + 11177 015c 24E0 b .L908 + 11178 .L902: + 11179 .loc 1 3807 5 discriminator 2 + 11180 015e 3B68 ldr r3, [r7] + 11181 0160 042B cmp r3, #4 + 11182 0162 04D1 bne .L904 + 11183 .loc 1 3807 5 discriminator 3 + 11184 0164 7B68 ldr r3, [r7, #4] + 11185 0166 0122 movs r2, #1 + 11186 0168 83F84520 strb r2, [r3, #69] + 11187 .loc 1 3807 5 + 11188 016c 1CE0 b .L908 + 11189 .L904: + 11190 .loc 1 3807 5 discriminator 4 + 11191 016e 3B68 ldr r3, [r7] + 11192 0170 082B cmp r3, #8 + 11193 0172 04D1 bne .L906 + 11194 .loc 1 3807 5 discriminator 6 + 11195 0174 7B68 ldr r3, [r7, #4] + 11196 0176 0122 movs r2, #1 + 11197 0178 83F84620 strb r2, [r3, #70] + 11198 .loc 1 3807 5 + 11199 017c 14E0 b .L908 + 11200 .L906: + 11201 .loc 1 3807 5 discriminator 7 + 11202 017e 7B68 ldr r3, [r7, #4] + 11203 0180 0122 movs r2, #1 + 11204 0182 83F84720 strb r2, [r3, #71] + 11205 .loc 1 3807 5 + 11206 0186 0FE0 b .L908 + 11207 .L891: +3808:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +3810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + ARM GAS /tmp/ccl4b9YO.s page 263 + + +3811:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 11208 .loc 1 3811 5 is_stmt 1 + 11209 0188 7B68 ldr r3, [r7, #4] + 11210 018a 0122 movs r2, #1 + 11211 018c 83F83E20 strb r2, [r3, #62] +3812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 11212 .loc 1 3812 5 + 11213 0190 7B68 ldr r3, [r7, #4] + 11214 0192 0122 movs r2, #1 + 11215 0194 83F83F20 strb r2, [r3, #63] +3813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 11216 .loc 1 3813 5 + 11217 0198 7B68 ldr r3, [r7, #4] + 11218 019a 0122 movs r2, #1 + 11219 019c 83F84420 strb r2, [r3, #68] +3814:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 11220 .loc 1 3814 5 + 11221 01a0 7B68 ldr r3, [r7, #4] + 11222 01a2 0122 movs r2, #1 + 11223 01a4 83F84520 strb r2, [r3, #69] + 11224 .L908: +3815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3817:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return function status */ +3818:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_OK; + 11225 .loc 1 3818 10 + 11226 01a8 0023 movs r3, #0 +3819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 11227 .loc 1 3819 1 + 11228 01aa 1846 mov r0, r3 + 11229 01ac 0837 adds r7, r7, #8 + 11230 .cfi_def_cfa_offset 8 + 11231 01ae BD46 mov sp, r7 + 11232 .cfi_def_cfa_register 13 + 11233 @ sp needed + 11234 01b0 80BD pop {r7, pc} + 11235 .cfi_endproc + 11236 .LFE187: + 11238 .section .text.HAL_TIM_IRQHandler,"ax",%progbits + 11239 .align 1 + 11240 .global HAL_TIM_IRQHandler + 11241 .syntax unified + 11242 .thumb + 11243 .thumb_func + 11245 HAL_TIM_IRQHandler: + 11246 .LFB188: +3820:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3821:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +3822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @} +3823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +3824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management +3825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief TIM IRQ handler management +3826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * +3827:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** @verbatim +3828:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** ============================================================================== +3829:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** ##### IRQ handler management ##### +3830:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** ============================================================================== + ARM GAS /tmp/ccl4b9YO.s page 264 + + +3831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** [..] +3832:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** This section provides Timer IRQ handler function. +3833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3834:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** @endverbatim +3835:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @{ +3836:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +3837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +3838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief This function handles TIM interrupts requests. +3839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM handle +3840:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval None +3841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +3842:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) +3843:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 11247 .loc 1 3843 1 + 11248 .cfi_startproc + 11249 @ args = 0, pretend = 0, frame = 8 + 11250 @ frame_needed = 1, uses_anonymous_args = 0 + 11251 0000 80B5 push {r7, lr} + 11252 .cfi_def_cfa_offset 8 + 11253 .cfi_offset 7, -8 + 11254 .cfi_offset 14, -4 + 11255 0002 82B0 sub sp, sp, #8 + 11256 .cfi_def_cfa_offset 16 + 11257 0004 00AF add r7, sp, #0 + 11258 .cfi_def_cfa_register 7 + 11259 0006 7860 str r0, [r7, #4] +3844:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Capture compare 1 event */ +3845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) + 11260 .loc 1 3845 7 + 11261 0008 7B68 ldr r3, [r7, #4] + 11262 000a 1B68 ldr r3, [r3] + 11263 000c 1B69 ldr r3, [r3, #16] + 11264 000e 03F00203 and r3, r3, #2 + 11265 .loc 1 3845 6 + 11266 0012 022B cmp r3, #2 + 11267 0014 22D1 bne .L911 +3846:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) + 11268 .loc 1 3847 9 + 11269 0016 7B68 ldr r3, [r7, #4] + 11270 0018 1B68 ldr r3, [r3] + 11271 001a DB68 ldr r3, [r3, #12] + 11272 001c 03F00203 and r3, r3, #2 + 11273 .loc 1 3847 8 + 11274 0020 022B cmp r3, #2 + 11275 0022 1BD1 bne .L911 +3848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); + 11276 .loc 1 3850 9 + 11277 0024 7B68 ldr r3, [r7, #4] + 11278 0026 1B68 ldr r3, [r3] + 11279 0028 6FF00202 mvn r2, #2 + 11280 002c 1A61 str r2, [r3, #16] +3851:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + 11281 .loc 1 3851 23 + 11282 002e 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/ccl4b9YO.s page 265 + + + 11283 0030 0122 movs r2, #1 + 11284 0032 1A77 strb r2, [r3, #28] +3852:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +3853:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Input capture event */ +3854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) + 11285 .loc 1 3854 18 + 11286 0034 7B68 ldr r3, [r7, #4] + 11287 0036 1B68 ldr r3, [r3] + 11288 .loc 1 3854 28 + 11289 0038 9B69 ldr r3, [r3, #24] + 11290 .loc 1 3854 36 + 11291 003a 03F00303 and r3, r3, #3 + 11292 .loc 1 3854 12 + 11293 003e 002B cmp r3, #0 + 11294 0040 03D0 beq .L912 +3855:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3856:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +3857:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->IC_CaptureCallback(htim); +3858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #else +3859:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_IC_CaptureCallback(htim); + 11295 .loc 1 3859 11 + 11296 0042 7868 ldr r0, [r7, #4] + 11297 0044 FFF7FEFF bl HAL_TIM_IC_CaptureCallback + 11298 0048 05E0 b .L913 + 11299 .L912: +3860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +3861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Output compare event */ +3863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +3864:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +3866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->OC_DelayElapsedCallback(htim); +3867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->PWM_PulseFinishedCallback(htim); +3868:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #else +3869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_OC_DelayElapsedCallback(htim); + 11300 .loc 1 3869 11 + 11301 004a 7868 ldr r0, [r7, #4] + 11302 004c FFF7FEFF bl HAL_TIM_OC_DelayElapsedCallback +3870:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_PWM_PulseFinishedCallback(htim); + 11303 .loc 1 3870 11 + 11304 0050 7868 ldr r0, [r7, #4] + 11305 0052 FFF7FEFF bl HAL_TIM_PWM_PulseFinishedCallback + 11306 .L913: +3871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +3872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3873:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 11307 .loc 1 3873 23 + 11308 0056 7B68 ldr r3, [r7, #4] + 11309 0058 0022 movs r2, #0 + 11310 005a 1A77 strb r2, [r3, #28] + 11311 .L911: +3874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3875:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3877:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Capture compare 2 event */ +3878:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) + 11312 .loc 1 3878 7 + ARM GAS /tmp/ccl4b9YO.s page 266 + + + 11313 005c 7B68 ldr r3, [r7, #4] + 11314 005e 1B68 ldr r3, [r3] + 11315 0060 1B69 ldr r3, [r3, #16] + 11316 0062 03F00403 and r3, r3, #4 + 11317 .loc 1 3878 6 + 11318 0066 042B cmp r3, #4 + 11319 0068 22D1 bne .L914 +3879:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) + 11320 .loc 1 3880 9 + 11321 006a 7B68 ldr r3, [r7, #4] + 11322 006c 1B68 ldr r3, [r3] + 11323 006e DB68 ldr r3, [r3, #12] + 11324 0070 03F00403 and r3, r3, #4 + 11325 .loc 1 3880 8 + 11326 0074 042B cmp r3, #4 + 11327 0076 1BD1 bne .L914 +3881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); + 11328 .loc 1 3882 7 + 11329 0078 7B68 ldr r3, [r7, #4] + 11330 007a 1B68 ldr r3, [r3] + 11331 007c 6FF00402 mvn r2, #4 + 11332 0080 1A61 str r2, [r3, #16] +3883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + 11333 .loc 1 3883 21 + 11334 0082 7B68 ldr r3, [r7, #4] + 11335 0084 0222 movs r2, #2 + 11336 0086 1A77 strb r2, [r3, #28] +3884:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Input capture event */ +3885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) + 11337 .loc 1 3885 16 + 11338 0088 7B68 ldr r3, [r7, #4] + 11339 008a 1B68 ldr r3, [r3] + 11340 .loc 1 3885 26 + 11341 008c 9B69 ldr r3, [r3, #24] + 11342 .loc 1 3885 34 + 11343 008e 03F44073 and r3, r3, #768 + 11344 .loc 1 3885 10 + 11345 0092 002B cmp r3, #0 + 11346 0094 03D0 beq .L915 +3886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3887:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +3888:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->IC_CaptureCallback(htim); +3889:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #else +3890:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_IC_CaptureCallback(htim); + 11347 .loc 1 3890 9 + 11348 0096 7868 ldr r0, [r7, #4] + 11349 0098 FFF7FEFF bl HAL_TIM_IC_CaptureCallback + 11350 009c 05E0 b .L916 + 11351 .L915: +3891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +3892:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Output compare event */ +3894:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +3895:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + ARM GAS /tmp/ccl4b9YO.s page 267 + + +3897:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->OC_DelayElapsedCallback(htim); +3898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->PWM_PulseFinishedCallback(htim); +3899:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #else +3900:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_OC_DelayElapsedCallback(htim); + 11352 .loc 1 3900 9 + 11353 009e 7868 ldr r0, [r7, #4] + 11354 00a0 FFF7FEFF bl HAL_TIM_OC_DelayElapsedCallback +3901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_PWM_PulseFinishedCallback(htim); + 11355 .loc 1 3901 9 + 11356 00a4 7868 ldr r0, [r7, #4] + 11357 00a6 FFF7FEFF bl HAL_TIM_PWM_PulseFinishedCallback + 11358 .L916: +3902:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +3903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3904:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 11359 .loc 1 3904 21 + 11360 00aa 7B68 ldr r3, [r7, #4] + 11361 00ac 0022 movs r2, #0 + 11362 00ae 1A77 strb r2, [r3, #28] + 11363 .L914: +3905:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3906:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Capture compare 3 event */ +3908:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) + 11364 .loc 1 3908 7 + 11365 00b0 7B68 ldr r3, [r7, #4] + 11366 00b2 1B68 ldr r3, [r3] + 11367 00b4 1B69 ldr r3, [r3, #16] + 11368 00b6 03F00803 and r3, r3, #8 + 11369 .loc 1 3908 6 + 11370 00ba 082B cmp r3, #8 + 11371 00bc 22D1 bne .L917 +3909:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) + 11372 .loc 1 3910 9 + 11373 00be 7B68 ldr r3, [r7, #4] + 11374 00c0 1B68 ldr r3, [r3] + 11375 00c2 DB68 ldr r3, [r3, #12] + 11376 00c4 03F00803 and r3, r3, #8 + 11377 .loc 1 3910 8 + 11378 00c8 082B cmp r3, #8 + 11379 00ca 1BD1 bne .L917 +3911:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); + 11380 .loc 1 3912 7 + 11381 00cc 7B68 ldr r3, [r7, #4] + 11382 00ce 1B68 ldr r3, [r3] + 11383 00d0 6FF00802 mvn r2, #8 + 11384 00d4 1A61 str r2, [r3, #16] +3913:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + 11385 .loc 1 3913 21 + 11386 00d6 7B68 ldr r3, [r7, #4] + 11387 00d8 0422 movs r2, #4 + 11388 00da 1A77 strb r2, [r3, #28] +3914:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Input capture event */ +3915:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) + 11389 .loc 1 3915 16 + ARM GAS /tmp/ccl4b9YO.s page 268 + + + 11390 00dc 7B68 ldr r3, [r7, #4] + 11391 00de 1B68 ldr r3, [r3] + 11392 .loc 1 3915 26 + 11393 00e0 DB69 ldr r3, [r3, #28] + 11394 .loc 1 3915 34 + 11395 00e2 03F00303 and r3, r3, #3 + 11396 .loc 1 3915 10 + 11397 00e6 002B cmp r3, #0 + 11398 00e8 03D0 beq .L918 +3916:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3917:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +3918:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->IC_CaptureCallback(htim); +3919:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #else +3920:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_IC_CaptureCallback(htim); + 11399 .loc 1 3920 9 + 11400 00ea 7868 ldr r0, [r7, #4] + 11401 00ec FFF7FEFF bl HAL_TIM_IC_CaptureCallback + 11402 00f0 05E0 b .L919 + 11403 .L918: +3921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +3922:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3923:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Output compare event */ +3924:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +3925:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3926:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +3927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->OC_DelayElapsedCallback(htim); +3928:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->PWM_PulseFinishedCallback(htim); +3929:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #else +3930:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_OC_DelayElapsedCallback(htim); + 11404 .loc 1 3930 9 + 11405 00f2 7868 ldr r0, [r7, #4] + 11406 00f4 FFF7FEFF bl HAL_TIM_OC_DelayElapsedCallback +3931:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_PWM_PulseFinishedCallback(htim); + 11407 .loc 1 3931 9 + 11408 00f8 7868 ldr r0, [r7, #4] + 11409 00fa FFF7FEFF bl HAL_TIM_PWM_PulseFinishedCallback + 11410 .L919: +3932:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +3933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3934:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 11411 .loc 1 3934 21 + 11412 00fe 7B68 ldr r3, [r7, #4] + 11413 0100 0022 movs r2, #0 + 11414 0102 1A77 strb r2, [r3, #28] + 11415 .L917: +3935:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3936:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Capture compare 4 event */ +3938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) + 11416 .loc 1 3938 7 + 11417 0104 7B68 ldr r3, [r7, #4] + 11418 0106 1B68 ldr r3, [r3] + 11419 0108 1B69 ldr r3, [r3, #16] + 11420 010a 03F01003 and r3, r3, #16 + 11421 .loc 1 3938 6 + 11422 010e 102B cmp r3, #16 + 11423 0110 22D1 bne .L920 + ARM GAS /tmp/ccl4b9YO.s page 269 + + +3939:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) + 11424 .loc 1 3940 9 + 11425 0112 7B68 ldr r3, [r7, #4] + 11426 0114 1B68 ldr r3, [r3] + 11427 0116 DB68 ldr r3, [r3, #12] + 11428 0118 03F01003 and r3, r3, #16 + 11429 .loc 1 3940 8 + 11430 011c 102B cmp r3, #16 + 11431 011e 1BD1 bne .L920 +3941:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); + 11432 .loc 1 3942 7 + 11433 0120 7B68 ldr r3, [r7, #4] + 11434 0122 1B68 ldr r3, [r3] + 11435 0124 6FF01002 mvn r2, #16 + 11436 0128 1A61 str r2, [r3, #16] +3943:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + 11437 .loc 1 3943 21 + 11438 012a 7B68 ldr r3, [r7, #4] + 11439 012c 0822 movs r2, #8 + 11440 012e 1A77 strb r2, [r3, #28] +3944:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Input capture event */ +3945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) + 11441 .loc 1 3945 16 + 11442 0130 7B68 ldr r3, [r7, #4] + 11443 0132 1B68 ldr r3, [r3] + 11444 .loc 1 3945 26 + 11445 0134 DB69 ldr r3, [r3, #28] + 11446 .loc 1 3945 34 + 11447 0136 03F44073 and r3, r3, #768 + 11448 .loc 1 3945 10 + 11449 013a 002B cmp r3, #0 + 11450 013c 03D0 beq .L921 +3946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3947:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +3948:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->IC_CaptureCallback(htim); +3949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #else +3950:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_IC_CaptureCallback(htim); + 11451 .loc 1 3950 9 + 11452 013e 7868 ldr r0, [r7, #4] + 11453 0140 FFF7FEFF bl HAL_TIM_IC_CaptureCallback + 11454 0144 05E0 b .L922 + 11455 .L921: +3951:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +3952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Output compare event */ +3954:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +3955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3956:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +3957:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->OC_DelayElapsedCallback(htim); +3958:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->PWM_PulseFinishedCallback(htim); +3959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #else +3960:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_OC_DelayElapsedCallback(htim); + 11456 .loc 1 3960 9 + 11457 0146 7868 ldr r0, [r7, #4] + 11458 0148 FFF7FEFF bl HAL_TIM_OC_DelayElapsedCallback + ARM GAS /tmp/ccl4b9YO.s page 270 + + +3961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_PWM_PulseFinishedCallback(htim); + 11459 .loc 1 3961 9 + 11460 014c 7868 ldr r0, [r7, #4] + 11461 014e FFF7FEFF bl HAL_TIM_PWM_PulseFinishedCallback + 11462 .L922: +3962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +3963:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3964:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 11463 .loc 1 3964 21 + 11464 0152 7B68 ldr r3, [r7, #4] + 11465 0154 0022 movs r2, #0 + 11466 0156 1A77 strb r2, [r3, #28] + 11467 .L920: +3965:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3966:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3967:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* TIM Update event */ +3968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) + 11468 .loc 1 3968 7 + 11469 0158 7B68 ldr r3, [r7, #4] + 11470 015a 1B68 ldr r3, [r3] + 11471 015c 1B69 ldr r3, [r3, #16] + 11472 015e 03F00103 and r3, r3, #1 + 11473 .loc 1 3968 6 + 11474 0162 012B cmp r3, #1 + 11475 0164 0ED1 bne .L923 +3969:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3970:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) + 11476 .loc 1 3970 9 + 11477 0166 7B68 ldr r3, [r7, #4] + 11478 0168 1B68 ldr r3, [r3] + 11479 016a DB68 ldr r3, [r3, #12] + 11480 016c 03F00103 and r3, r3, #1 + 11481 .loc 1 3970 8 + 11482 0170 012B cmp r3, #1 + 11483 0172 07D1 bne .L923 +3971:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3972:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); + 11484 .loc 1 3972 7 + 11485 0174 7B68 ldr r3, [r7, #4] + 11486 0176 1B68 ldr r3, [r3] + 11487 0178 6FF00102 mvn r2, #1 + 11488 017c 1A61 str r2, [r3, #16] +3973:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +3974:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->PeriodElapsedCallback(htim); +3975:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #else +3976:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_PeriodElapsedCallback(htim); + 11489 .loc 1 3976 7 + 11490 017e 7868 ldr r0, [r7, #4] + 11491 0180 FFF7FEFF bl HAL_TIM_PeriodElapsedCallback + 11492 .L923: +3977:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +3978:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3979:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* TIM Break input event */ +3981:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) + 11493 .loc 1 3981 7 + 11494 0184 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/ccl4b9YO.s page 271 + + + 11495 0186 1B68 ldr r3, [r3] + 11496 0188 1B69 ldr r3, [r3, #16] + 11497 018a 03F08003 and r3, r3, #128 + 11498 .loc 1 3981 6 + 11499 018e 802B cmp r3, #128 + 11500 0190 0ED1 bne .L924 +3982:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3983:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) + 11501 .loc 1 3983 9 + 11502 0192 7B68 ldr r3, [r7, #4] + 11503 0194 1B68 ldr r3, [r3] + 11504 0196 DB68 ldr r3, [r3, #12] + 11505 0198 03F08003 and r3, r3, #128 + 11506 .loc 1 3983 8 + 11507 019c 802B cmp r3, #128 + 11508 019e 07D1 bne .L924 +3984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3985:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); + 11509 .loc 1 3985 7 + 11510 01a0 7B68 ldr r3, [r7, #4] + 11511 01a2 1B68 ldr r3, [r3] + 11512 01a4 6FF08002 mvn r2, #128 + 11513 01a8 1A61 str r2, [r3, #16] +3986:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +3987:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->BreakCallback(htim); +3988:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #else +3989:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIMEx_BreakCallback(htim); + 11514 .loc 1 3989 7 + 11515 01aa 7868 ldr r0, [r7, #4] + 11516 01ac FFF7FEFF bl HAL_TIMEx_BreakCallback + 11517 .L924: +3990:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +3991:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3992:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +3993:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if defined(TIM_BDTR_BK2E) +3994:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* TIM Break2 input event */ +3995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET) + 11518 .loc 1 3995 7 + 11519 01b0 7B68 ldr r3, [r7, #4] + 11520 01b2 1B68 ldr r3, [r3] + 11521 01b4 1B69 ldr r3, [r3, #16] + 11522 01b6 03F48073 and r3, r3, #256 + 11523 .loc 1 3995 6 + 11524 01ba B3F5807F cmp r3, #256 + 11525 01be 0ED1 bne .L925 +3996:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3997:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) + 11526 .loc 1 3997 9 + 11527 01c0 7B68 ldr r3, [r7, #4] + 11528 01c2 1B68 ldr r3, [r3] + 11529 01c4 DB68 ldr r3, [r3, #12] + 11530 01c6 03F08003 and r3, r3, #128 + 11531 .loc 1 3997 8 + 11532 01ca 802B cmp r3, #128 + 11533 01cc 07D1 bne .L925 +3998:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +3999:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); + ARM GAS /tmp/ccl4b9YO.s page 272 + + + 11534 .loc 1 3999 7 + 11535 01ce 7B68 ldr r3, [r7, #4] + 11536 01d0 1B68 ldr r3, [r3] + 11537 01d2 6FF48072 mvn r2, #256 + 11538 01d6 1A61 str r2, [r3, #16] +4000:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +4001:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Break2Callback(htim); +4002:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #else +4003:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIMEx_Break2Callback(htim); + 11539 .loc 1 4003 7 + 11540 01d8 7868 ldr r0, [r7, #4] + 11541 01da FFF7FEFF bl HAL_TIMEx_Break2Callback + 11542 .L925: +4004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +4005:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4006:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* TIM_BDTR_BK2E */ +4008:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* TIM Trigger detection event */ +4009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) + 11543 .loc 1 4009 7 + 11544 01de 7B68 ldr r3, [r7, #4] + 11545 01e0 1B68 ldr r3, [r3] + 11546 01e2 1B69 ldr r3, [r3, #16] + 11547 01e4 03F04003 and r3, r3, #64 + 11548 .loc 1 4009 6 + 11549 01e8 402B cmp r3, #64 + 11550 01ea 0ED1 bne .L926 +4010:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4011:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET) + 11551 .loc 1 4011 9 + 11552 01ec 7B68 ldr r3, [r7, #4] + 11553 01ee 1B68 ldr r3, [r3] + 11554 01f0 DB68 ldr r3, [r3, #12] + 11555 01f2 03F04003 and r3, r3, #64 + 11556 .loc 1 4011 8 + 11557 01f6 402B cmp r3, #64 + 11558 01f8 07D1 bne .L926 +4012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4013:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); + 11559 .loc 1 4013 7 + 11560 01fa 7B68 ldr r3, [r7, #4] + 11561 01fc 1B68 ldr r3, [r3] + 11562 01fe 6FF04002 mvn r2, #64 + 11563 0202 1A61 str r2, [r3, #16] +4014:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +4015:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->TriggerCallback(htim); +4016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #else +4017:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_TriggerCallback(htim); + 11564 .loc 1 4017 7 + 11565 0204 7868 ldr r0, [r7, #4] + 11566 0206 FFF7FEFF bl HAL_TIM_TriggerCallback + 11567 .L926: +4018:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +4019:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4021:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* TIM commutation event */ +4022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) + ARM GAS /tmp/ccl4b9YO.s page 273 + + + 11568 .loc 1 4022 7 + 11569 020a 7B68 ldr r3, [r7, #4] + 11570 020c 1B68 ldr r3, [r3] + 11571 020e 1B69 ldr r3, [r3, #16] + 11572 0210 03F02003 and r3, r3, #32 + 11573 .loc 1 4022 6 + 11574 0214 202B cmp r3, #32 + 11575 0216 0ED1 bne .L928 +4023:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET) + 11576 .loc 1 4024 9 + 11577 0218 7B68 ldr r3, [r7, #4] + 11578 021a 1B68 ldr r3, [r3] + 11579 021c DB68 ldr r3, [r3, #12] + 11580 021e 03F02003 and r3, r3, #32 + 11581 .loc 1 4024 8 + 11582 0222 202B cmp r3, #32 + 11583 0224 07D1 bne .L928 +4025:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); + 11584 .loc 1 4026 7 + 11585 0226 7B68 ldr r3, [r7, #4] + 11586 0228 1B68 ldr r3, [r3] + 11587 022a 6FF02002 mvn r2, #32 + 11588 022e 1A61 str r2, [r3, #16] +4027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +4028:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->CommutationCallback(htim); +4029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #else +4030:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIMEx_CommutCallback(htim); + 11589 .loc 1 4030 7 + 11590 0230 7868 ldr r0, [r7, #4] + 11591 0232 FFF7FEFF bl HAL_TIMEx_CommutCallback + 11592 .L928: +4031:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +4032:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4033:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 11593 .loc 1 4034 1 + 11594 0236 00BF nop + 11595 0238 0837 adds r7, r7, #8 + 11596 .cfi_def_cfa_offset 8 + 11597 023a BD46 mov sp, r7 + 11598 .cfi_def_cfa_register 13 + 11599 @ sp needed + 11600 023c 80BD pop {r7, pc} + 11601 .cfi_endproc + 11602 .LFE188: + 11604 .section .text.HAL_TIM_OC_ConfigChannel,"ax",%progbits + 11605 .align 1 + 11606 .global HAL_TIM_OC_ConfigChannel + 11607 .syntax unified + 11608 .thumb + 11609 .thumb_func + 11611 HAL_TIM_OC_ConfigChannel: + 11612 .LFB189: +4035:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4036:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** + ARM GAS /tmp/ccl4b9YO.s page 274 + + +4037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @} +4038:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +4039:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4040:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions +4041:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief TIM Peripheral Control functions +4042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * +4043:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** @verbatim +4044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** ============================================================================== +4045:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** ##### Peripheral Control functions ##### +4046:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** ============================================================================== +4047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** [..] +4048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** This section provides functions allowing to: +4049:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. +4050:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Configure External Clock source. +4051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Configure Complementary channels, break features and dead time. +4052:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Configure Master and the Slave synchronization. +4053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) Configure the DMA Burst Mode. +4054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4055:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** @endverbatim +4056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @{ +4057:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +4058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +4060:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Initializes the TIM Output Compare Channels according to the specified +4061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * parameters in the TIM_OC_InitTypeDef. +4062:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM Output Compare handle +4063:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param sConfig TIM Output Compare configuration structure +4064:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param Channel TIM Channels to configure +4065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +4066:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +4067:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +4068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +4069:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +4070:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) +4071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) +4072:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * (*) Value not defined for all devices +4073:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status +4074:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +4075:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, +4076:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** const TIM_OC_InitTypeDef *sConfig, +4077:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t Channel) +4078:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 11613 .loc 1 4078 1 + 11614 .cfi_startproc + 11615 @ args = 0, pretend = 0, frame = 24 + 11616 @ frame_needed = 1, uses_anonymous_args = 0 + 11617 0000 80B5 push {r7, lr} + 11618 .cfi_def_cfa_offset 8 + 11619 .cfi_offset 7, -8 + 11620 .cfi_offset 14, -4 + 11621 0002 86B0 sub sp, sp, #24 + 11622 .cfi_def_cfa_offset 32 + 11623 0004 00AF add r7, sp, #0 + 11624 .cfi_def_cfa_register 7 + 11625 0006 F860 str r0, [r7, #12] + 11626 0008 B960 str r1, [r7, #8] + 11627 000a 7A60 str r2, [r7, #4] + ARM GAS /tmp/ccl4b9YO.s page 275 + + +4079:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 11628 .loc 1 4079 21 + 11629 000c 0023 movs r3, #0 + 11630 000e FB75 strb r3, [r7, #23] +4080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4081:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +4082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CHANNELS(Channel)); +4083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); +4084:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); +4085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4086:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Process Locked */ +4087:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_LOCK(htim); + 11631 .loc 1 4087 3 + 11632 0010 FB68 ldr r3, [r7, #12] + 11633 0012 93F83C30 ldrb r3, [r3, #60] @ zero_extendqisi2 + 11634 0016 012B cmp r3, #1 + 11635 0018 01D1 bne .L930 + 11636 .loc 1 4087 3 is_stmt 0 discriminator 1 + 11637 001a 0223 movs r3, #2 + 11638 .loc 1 4087 3 + 11639 001c 66E0 b .L931 + 11640 .L930: + 11641 .loc 1 4087 3 discriminator 2 + 11642 001e FB68 ldr r3, [r7, #12] + 11643 0020 0122 movs r2, #1 + 11644 0022 83F83C20 strb r2, [r3, #60] +4088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4089:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** switch (Channel) + 11645 .loc 1 4089 3 is_stmt 1 + 11646 0026 7B68 ldr r3, [r7, #4] + 11647 0028 142B cmp r3, #20 + 11648 002a 57D8 bhi .L932 + 11649 002c 01A2 adr r2, .L934 + 11650 002e 52F823F0 ldr pc, [r2, r3, lsl #2] + 11651 0032 00BF .p2align 2 + 11652 .L934: + 11653 0034 89000000 .word .L939+1 + 11654 0038 DD000000 .word .L932+1 + 11655 003c DD000000 .word .L932+1 + 11656 0040 DD000000 .word .L932+1 + 11657 0044 97000000 .word .L938+1 + 11658 0048 DD000000 .word .L932+1 + 11659 004c DD000000 .word .L932+1 + 11660 0050 DD000000 .word .L932+1 + 11661 0054 A5000000 .word .L937+1 + 11662 0058 DD000000 .word .L932+1 + 11663 005c DD000000 .word .L932+1 + 11664 0060 DD000000 .word .L932+1 + 11665 0064 B3000000 .word .L936+1 + 11666 0068 DD000000 .word .L932+1 + 11667 006c DD000000 .word .L932+1 + 11668 0070 DD000000 .word .L932+1 + 11669 0074 C1000000 .word .L935+1 + 11670 0078 DD000000 .word .L932+1 + 11671 007c DD000000 .word .L932+1 + 11672 0080 DD000000 .word .L932+1 + 11673 0084 CF000000 .word .L933+1 + ARM GAS /tmp/ccl4b9YO.s page 276 + + + 11674 .p2align 1 + 11675 .L939: +4090:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4091:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_1: +4092:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4093:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +4094:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); +4095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4096:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Configure the TIM Channel 1 in Output Compare */ +4097:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_OC1_SetConfig(htim->Instance, sConfig); + 11676 .loc 1 4097 7 + 11677 0088 FB68 ldr r3, [r7, #12] + 11678 008a 1B68 ldr r3, [r3] + 11679 008c B968 ldr r1, [r7, #8] + 11680 008e 1846 mov r0, r3 + 11681 0090 FFF7FEFF bl TIM_OC1_SetConfig +4098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 11682 .loc 1 4098 7 + 11683 0094 25E0 b .L940 + 11684 .L938: +4099:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_2: +4102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +4104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); +4105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Configure the TIM Channel 2 in Output Compare */ +4107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_OC2_SetConfig(htim->Instance, sConfig); + 11685 .loc 1 4107 7 + 11686 0096 FB68 ldr r3, [r7, #12] + 11687 0098 1B68 ldr r3, [r3] + 11688 009a B968 ldr r1, [r7, #8] + 11689 009c 1846 mov r0, r3 + 11690 009e FFF7FEFF bl TIM_OC2_SetConfig +4108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 11691 .loc 1 4108 7 + 11692 00a2 1EE0 b .L940 + 11693 .L937: +4109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_3: +4112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +4114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); +4115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Configure the TIM Channel 3 in Output Compare */ +4117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_OC3_SetConfig(htim->Instance, sConfig); + 11694 .loc 1 4117 7 + 11695 00a4 FB68 ldr r3, [r7, #12] + 11696 00a6 1B68 ldr r3, [r3] + 11697 00a8 B968 ldr r1, [r7, #8] + 11698 00aa 1846 mov r0, r3 + 11699 00ac FFF7FEFF bl TIM_OC3_SetConfig +4118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 11700 .loc 1 4118 7 + 11701 00b0 17E0 b .L940 + ARM GAS /tmp/ccl4b9YO.s page 277 + + + 11702 .L936: +4119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_4: +4122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +4124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); +4125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Configure the TIM Channel 4 in Output Compare */ +4127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_OC4_SetConfig(htim->Instance, sConfig); + 11703 .loc 1 4127 7 + 11704 00b2 FB68 ldr r3, [r7, #12] + 11705 00b4 1B68 ldr r3, [r3] + 11706 00b6 B968 ldr r1, [r7, #8] + 11707 00b8 1846 mov r0, r3 + 11708 00ba FFF7FEFF bl TIM_OC4_SetConfig +4128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 11709 .loc 1 4128 7 + 11710 00be 10E0 b .L940 + 11711 .L935: +4129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if defined(TIM_CCER_CC5E) +4132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_5: +4133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +4135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); +4136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Configure the TIM Channel 5 in Output Compare */ +4138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_OC5_SetConfig(htim->Instance, sConfig); + 11712 .loc 1 4138 7 + 11713 00c0 FB68 ldr r3, [r7, #12] + 11714 00c2 1B68 ldr r3, [r3] + 11715 00c4 B968 ldr r1, [r7, #8] + 11716 00c6 1846 mov r0, r3 + 11717 00c8 FFF7FEFF bl TIM_OC5_SetConfig +4139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 11718 .loc 1 4139 7 + 11719 00cc 09E0 b .L940 + 11720 .L933: +4140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* TIM_CCER_CC5E */ +4142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if defined(TIM_CCER_CC6E) +4144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_6: +4145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +4147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); +4148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Configure the TIM Channel 6 in Output Compare */ +4150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_OC6_SetConfig(htim->Instance, sConfig); + 11721 .loc 1 4150 7 + 11722 00ce FB68 ldr r3, [r7, #12] + 11723 00d0 1B68 ldr r3, [r3] + 11724 00d2 B968 ldr r1, [r7, #8] + 11725 00d4 1846 mov r0, r3 + 11726 00d6 FFF7FEFF bl TIM_OC6_SetConfig + ARM GAS /tmp/ccl4b9YO.s page 278 + + +4151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 11727 .loc 1 4151 7 + 11728 00da 02E0 b .L940 + 11729 .L932: +4152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* TIM_CCER_CC6E */ +4154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** default: +4156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** status = HAL_ERROR; + 11730 .loc 1 4156 14 + 11731 00dc 0123 movs r3, #1 + 11732 00de FB75 strb r3, [r7, #23] +4157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 11733 .loc 1 4157 7 + 11734 00e0 00BF nop + 11735 .L940: +4158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_UNLOCK(htim); + 11736 .loc 1 4160 3 + 11737 00e2 FB68 ldr r3, [r7, #12] + 11738 00e4 0022 movs r2, #0 + 11739 00e6 83F83C20 strb r2, [r3, #60] +4161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return status; + 11740 .loc 1 4162 10 + 11741 00ea FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 11742 .L931: +4163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 11743 .loc 1 4163 1 + 11744 00ec 1846 mov r0, r3 + 11745 00ee 1837 adds r7, r7, #24 + 11746 .cfi_def_cfa_offset 8 + 11747 00f0 BD46 mov sp, r7 + 11748 .cfi_def_cfa_register 13 + 11749 @ sp needed + 11750 00f2 80BD pop {r7, pc} + 11751 .cfi_endproc + 11752 .LFE189: + 11754 .section .text.HAL_TIM_IC_ConfigChannel,"ax",%progbits + 11755 .align 1 + 11756 .global HAL_TIM_IC_ConfigChannel + 11757 .syntax unified + 11758 .thumb + 11759 .thumb_func + 11761 HAL_TIM_IC_ConfigChannel: + 11762 .LFB190: +4164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +4166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Initializes the TIM Input Capture Channels according to the specified +4167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * parameters in the TIM_IC_InitTypeDef. +4168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM IC handle +4169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param sConfig TIM Input Capture configuration structure +4170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param Channel TIM Channel to configure +4171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +4172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +4173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected + ARM GAS /tmp/ccl4b9YO.s page 279 + + +4174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +4175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +4176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status +4177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +4178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConf +4179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 11763 .loc 1 4179 1 + 11764 .cfi_startproc + 11765 @ args = 0, pretend = 0, frame = 24 + 11766 @ frame_needed = 1, uses_anonymous_args = 0 + 11767 0000 80B5 push {r7, lr} + 11768 .cfi_def_cfa_offset 8 + 11769 .cfi_offset 7, -8 + 11770 .cfi_offset 14, -4 + 11771 0002 86B0 sub sp, sp, #24 + 11772 .cfi_def_cfa_offset 32 + 11773 0004 00AF add r7, sp, #0 + 11774 .cfi_def_cfa_register 7 + 11775 0006 F860 str r0, [r7, #12] + 11776 0008 B960 str r1, [r7, #8] + 11777 000a 7A60 str r2, [r7, #4] +4180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 11778 .loc 1 4180 21 + 11779 000c 0023 movs r3, #0 + 11780 000e FB75 strb r3, [r7, #23] +4181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +4183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); +4184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); +4185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); +4186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); +4187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); +4188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Process Locked */ +4190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_LOCK(htim); + 11781 .loc 1 4190 3 + 11782 0010 FB68 ldr r3, [r7, #12] + 11783 0012 93F83C30 ldrb r3, [r3, #60] @ zero_extendqisi2 + 11784 0016 012B cmp r3, #1 + 11785 0018 01D1 bne .L942 + 11786 .loc 1 4190 3 is_stmt 0 discriminator 1 + 11787 001a 0223 movs r3, #2 + 11788 .loc 1 4190 3 + 11789 001c 88E0 b .L943 + 11790 .L942: + 11791 .loc 1 4190 3 discriminator 2 + 11792 001e FB68 ldr r3, [r7, #12] + 11793 0020 0122 movs r2, #1 + 11794 0022 83F83C20 strb r2, [r3, #60] +4191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (Channel == TIM_CHANNEL_1) + 11795 .loc 1 4192 6 is_stmt 1 + 11796 0026 7B68 ldr r3, [r7, #4] + 11797 0028 002B cmp r3, #0 + 11798 002a 1BD1 bne .L944 +4193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* TI1 Configuration */ + ARM GAS /tmp/ccl4b9YO.s page 280 + + +4195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_TI1_SetConfig(htim->Instance, + 11799 .loc 1 4195 5 + 11800 002c FB68 ldr r3, [r7, #12] + 11801 002e 1868 ldr r0, [r3] +4196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** sConfig->ICPolarity, + 11802 .loc 1 4196 30 + 11803 0030 BB68 ldr r3, [r7, #8] + 11804 0032 1968 ldr r1, [r3] +4197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** sConfig->ICSelection, + 11805 .loc 1 4197 30 + 11806 0034 BB68 ldr r3, [r7, #8] + 11807 0036 5A68 ldr r2, [r3, #4] +4198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** sConfig->ICFilter); + 11808 .loc 1 4198 30 + 11809 0038 BB68 ldr r3, [r7, #8] + 11810 003a DB68 ldr r3, [r3, #12] +4195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** sConfig->ICPolarity, + 11811 .loc 1 4195 5 + 11812 003c FFF7FEFF bl TIM_TI1_SetConfig +4199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Reset the IC1PSC Bits */ +4201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + 11813 .loc 1 4201 9 + 11814 0040 FB68 ldr r3, [r7, #12] + 11815 0042 1B68 ldr r3, [r3] + 11816 .loc 1 4201 19 + 11817 0044 9A69 ldr r2, [r3, #24] + 11818 .loc 1 4201 9 + 11819 0046 FB68 ldr r3, [r7, #12] + 11820 0048 1B68 ldr r3, [r3] + 11821 .loc 1 4201 27 + 11822 004a 22F00C02 bic r2, r2, #12 + 11823 004e 9A61 str r2, [r3, #24] +4202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the IC1PSC value */ +4204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->CCMR1 |= sConfig->ICPrescaler; + 11824 .loc 1 4204 9 + 11825 0050 FB68 ldr r3, [r7, #12] + 11826 0052 1B68 ldr r3, [r3] + 11827 .loc 1 4204 19 + 11828 0054 9969 ldr r1, [r3, #24] + 11829 .loc 1 4204 37 + 11830 0056 BB68 ldr r3, [r7, #8] + 11831 0058 9A68 ldr r2, [r3, #8] + 11832 .loc 1 4204 9 + 11833 005a FB68 ldr r3, [r7, #12] + 11834 005c 1B68 ldr r3, [r3] + 11835 .loc 1 4204 27 + 11836 005e 0A43 orrs r2, r2, r1 + 11837 0060 9A61 str r2, [r3, #24] + 11838 0062 60E0 b .L945 + 11839 .L944: +4205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else if (Channel == TIM_CHANNEL_2) + 11840 .loc 1 4206 11 + 11841 0064 7B68 ldr r3, [r7, #4] + 11842 0066 042B cmp r3, #4 + ARM GAS /tmp/ccl4b9YO.s page 281 + + + 11843 0068 1CD1 bne .L946 +4207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* TI2 Configuration */ +4209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); +4210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_TI2_SetConfig(htim->Instance, + 11844 .loc 1 4211 5 + 11845 006a FB68 ldr r3, [r7, #12] + 11846 006c 1868 ldr r0, [r3] +4212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** sConfig->ICPolarity, + 11847 .loc 1 4212 30 + 11848 006e BB68 ldr r3, [r7, #8] + 11849 0070 1968 ldr r1, [r3] +4213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** sConfig->ICSelection, + 11850 .loc 1 4213 30 + 11851 0072 BB68 ldr r3, [r7, #8] + 11852 0074 5A68 ldr r2, [r3, #4] +4214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** sConfig->ICFilter); + 11853 .loc 1 4214 30 + 11854 0076 BB68 ldr r3, [r7, #8] + 11855 0078 DB68 ldr r3, [r3, #12] +4211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** sConfig->ICPolarity, + 11856 .loc 1 4211 5 + 11857 007a FFF7FEFF bl TIM_TI2_SetConfig +4215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Reset the IC2PSC Bits */ +4217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + 11858 .loc 1 4217 9 + 11859 007e FB68 ldr r3, [r7, #12] + 11860 0080 1B68 ldr r3, [r3] + 11861 .loc 1 4217 19 + 11862 0082 9A69 ldr r2, [r3, #24] + 11863 .loc 1 4217 9 + 11864 0084 FB68 ldr r3, [r7, #12] + 11865 0086 1B68 ldr r3, [r3] + 11866 .loc 1 4217 27 + 11867 0088 22F44062 bic r2, r2, #3072 + 11868 008c 9A61 str r2, [r3, #24] +4218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the IC2PSC value */ +4220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); + 11869 .loc 1 4220 9 + 11870 008e FB68 ldr r3, [r7, #12] + 11871 0090 1B68 ldr r3, [r3] + 11872 .loc 1 4220 19 + 11873 0092 9969 ldr r1, [r3, #24] + 11874 .loc 1 4220 38 + 11875 0094 BB68 ldr r3, [r7, #8] + 11876 0096 9B68 ldr r3, [r3, #8] + 11877 .loc 1 4220 52 + 11878 0098 1A02 lsls r2, r3, #8 + 11879 .loc 1 4220 9 + 11880 009a FB68 ldr r3, [r7, #12] + 11881 009c 1B68 ldr r3, [r3] + 11882 .loc 1 4220 27 + 11883 009e 0A43 orrs r2, r2, r1 + 11884 00a0 9A61 str r2, [r3, #24] + ARM GAS /tmp/ccl4b9YO.s page 282 + + + 11885 00a2 40E0 b .L945 + 11886 .L946: +4221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else if (Channel == TIM_CHANNEL_3) + 11887 .loc 1 4222 11 + 11888 00a4 7B68 ldr r3, [r7, #4] + 11889 00a6 082B cmp r3, #8 + 11890 00a8 1BD1 bne .L947 +4223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* TI3 Configuration */ +4225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); +4226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_TI3_SetConfig(htim->Instance, + 11891 .loc 1 4227 5 + 11892 00aa FB68 ldr r3, [r7, #12] + 11893 00ac 1868 ldr r0, [r3] +4228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** sConfig->ICPolarity, + 11894 .loc 1 4228 30 + 11895 00ae BB68 ldr r3, [r7, #8] + 11896 00b0 1968 ldr r1, [r3] +4229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** sConfig->ICSelection, + 11897 .loc 1 4229 30 + 11898 00b2 BB68 ldr r3, [r7, #8] + 11899 00b4 5A68 ldr r2, [r3, #4] +4230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** sConfig->ICFilter); + 11900 .loc 1 4230 30 + 11901 00b6 BB68 ldr r3, [r7, #8] + 11902 00b8 DB68 ldr r3, [r3, #12] +4227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** sConfig->ICPolarity, + 11903 .loc 1 4227 5 + 11904 00ba FFF7FEFF bl TIM_TI3_SetConfig +4231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Reset the IC3PSC Bits */ +4233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; + 11905 .loc 1 4233 9 + 11906 00be FB68 ldr r3, [r7, #12] + 11907 00c0 1B68 ldr r3, [r3] + 11908 .loc 1 4233 19 + 11909 00c2 DA69 ldr r2, [r3, #28] + 11910 .loc 1 4233 9 + 11911 00c4 FB68 ldr r3, [r7, #12] + 11912 00c6 1B68 ldr r3, [r3] + 11913 .loc 1 4233 27 + 11914 00c8 22F00C02 bic r2, r2, #12 + 11915 00cc DA61 str r2, [r3, #28] +4234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the IC3PSC value */ +4236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->CCMR2 |= sConfig->ICPrescaler; + 11916 .loc 1 4236 9 + 11917 00ce FB68 ldr r3, [r7, #12] + 11918 00d0 1B68 ldr r3, [r3] + 11919 .loc 1 4236 19 + 11920 00d2 D969 ldr r1, [r3, #28] + 11921 .loc 1 4236 37 + 11922 00d4 BB68 ldr r3, [r7, #8] + 11923 00d6 9A68 ldr r2, [r3, #8] + 11924 .loc 1 4236 9 + ARM GAS /tmp/ccl4b9YO.s page 283 + + + 11925 00d8 FB68 ldr r3, [r7, #12] + 11926 00da 1B68 ldr r3, [r3] + 11927 .loc 1 4236 27 + 11928 00dc 0A43 orrs r2, r2, r1 + 11929 00de DA61 str r2, [r3, #28] + 11930 00e0 21E0 b .L945 + 11931 .L947: +4237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else if (Channel == TIM_CHANNEL_4) + 11932 .loc 1 4238 11 + 11933 00e2 7B68 ldr r3, [r7, #4] + 11934 00e4 0C2B cmp r3, #12 + 11935 00e6 1CD1 bne .L948 +4239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* TI4 Configuration */ +4241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); +4242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_TI4_SetConfig(htim->Instance, + 11936 .loc 1 4243 5 + 11937 00e8 FB68 ldr r3, [r7, #12] + 11938 00ea 1868 ldr r0, [r3] +4244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** sConfig->ICPolarity, + 11939 .loc 1 4244 30 + 11940 00ec BB68 ldr r3, [r7, #8] + 11941 00ee 1968 ldr r1, [r3] +4245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** sConfig->ICSelection, + 11942 .loc 1 4245 30 + 11943 00f0 BB68 ldr r3, [r7, #8] + 11944 00f2 5A68 ldr r2, [r3, #4] +4246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** sConfig->ICFilter); + 11945 .loc 1 4246 30 + 11946 00f4 BB68 ldr r3, [r7, #8] + 11947 00f6 DB68 ldr r3, [r3, #12] +4243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** sConfig->ICPolarity, + 11948 .loc 1 4243 5 + 11949 00f8 FFF7FEFF bl TIM_TI4_SetConfig +4247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Reset the IC4PSC Bits */ +4249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; + 11950 .loc 1 4249 9 + 11951 00fc FB68 ldr r3, [r7, #12] + 11952 00fe 1B68 ldr r3, [r3] + 11953 .loc 1 4249 19 + 11954 0100 DA69 ldr r2, [r3, #28] + 11955 .loc 1 4249 9 + 11956 0102 FB68 ldr r3, [r7, #12] + 11957 0104 1B68 ldr r3, [r3] + 11958 .loc 1 4249 27 + 11959 0106 22F44062 bic r2, r2, #3072 + 11960 010a DA61 str r2, [r3, #28] +4250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the IC4PSC value */ +4252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); + 11961 .loc 1 4252 9 + 11962 010c FB68 ldr r3, [r7, #12] + 11963 010e 1B68 ldr r3, [r3] + 11964 .loc 1 4252 19 + ARM GAS /tmp/ccl4b9YO.s page 284 + + + 11965 0110 D969 ldr r1, [r3, #28] + 11966 .loc 1 4252 38 + 11967 0112 BB68 ldr r3, [r7, #8] + 11968 0114 9B68 ldr r3, [r3, #8] + 11969 .loc 1 4252 52 + 11970 0116 1A02 lsls r2, r3, #8 + 11971 .loc 1 4252 9 + 11972 0118 FB68 ldr r3, [r7, #12] + 11973 011a 1B68 ldr r3, [r3] + 11974 .loc 1 4252 27 + 11975 011c 0A43 orrs r2, r2, r1 + 11976 011e DA61 str r2, [r3, #28] + 11977 0120 01E0 b .L945 + 11978 .L948: +4253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +4255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** status = HAL_ERROR; + 11979 .loc 1 4256 12 + 11980 0122 0123 movs r3, #1 + 11981 0124 FB75 strb r3, [r7, #23] + 11982 .L945: +4257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_UNLOCK(htim); + 11983 .loc 1 4259 3 + 11984 0126 FB68 ldr r3, [r7, #12] + 11985 0128 0022 movs r2, #0 + 11986 012a 83F83C20 strb r2, [r3, #60] +4260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return status; + 11987 .loc 1 4261 10 + 11988 012e FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 11989 .L943: +4262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 11990 .loc 1 4262 1 + 11991 0130 1846 mov r0, r3 + 11992 0132 1837 adds r7, r7, #24 + 11993 .cfi_def_cfa_offset 8 + 11994 0134 BD46 mov sp, r7 + 11995 .cfi_def_cfa_register 13 + 11996 @ sp needed + 11997 0136 80BD pop {r7, pc} + 11998 .cfi_endproc + 11999 .LFE190: + 12001 .section .text.HAL_TIM_PWM_ConfigChannel,"ax",%progbits + 12002 .align 1 + 12003 .global HAL_TIM_PWM_ConfigChannel + 12004 .syntax unified + 12005 .thumb + 12006 .thumb_func + 12008 HAL_TIM_PWM_ConfigChannel: + 12009 .LFB191: +4263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +4265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Initializes the TIM PWM channels according to the specified +4266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * parameters in the TIM_OC_InitTypeDef. + ARM GAS /tmp/ccl4b9YO.s page 285 + + +4267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM PWM handle +4268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param sConfig TIM PWM configuration structure +4269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param Channel TIM Channels to be configured +4270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +4271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +4272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +4273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +4274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +4275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_5: TIM Channel 5 selected (*) +4276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_6: TIM Channel 6 selected (*) +4277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * (*) Value not defined for all devices +4278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status +4279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +4280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, +4281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** const TIM_OC_InitTypeDef *sConfig, +4282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t Channel) +4283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 12010 .loc 1 4283 1 + 12011 .cfi_startproc + 12012 @ args = 0, pretend = 0, frame = 24 + 12013 @ frame_needed = 1, uses_anonymous_args = 0 + 12014 0000 80B5 push {r7, lr} + 12015 .cfi_def_cfa_offset 8 + 12016 .cfi_offset 7, -8 + 12017 .cfi_offset 14, -4 + 12018 0002 86B0 sub sp, sp, #24 + 12019 .cfi_def_cfa_offset 32 + 12020 0004 00AF add r7, sp, #0 + 12021 .cfi_def_cfa_register 7 + 12022 0006 F860 str r0, [r7, #12] + 12023 0008 B960 str r1, [r7, #8] + 12024 000a 7A60 str r2, [r7, #4] +4284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 12025 .loc 1 4284 21 + 12026 000c 0023 movs r3, #0 + 12027 000e FB75 strb r3, [r7, #23] +4285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +4287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CHANNELS(Channel)); +4288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); +4289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); +4290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); +4291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Process Locked */ +4293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_LOCK(htim); + 12028 .loc 1 4293 3 + 12029 0010 FB68 ldr r3, [r7, #12] + 12030 0012 93F83C30 ldrb r3, [r3, #60] @ zero_extendqisi2 + 12031 0016 012B cmp r3, #1 + 12032 0018 01D1 bne .L950 + 12033 .loc 1 4293 3 is_stmt 0 discriminator 1 + 12034 001a 0223 movs r3, #2 + 12035 .loc 1 4293 3 + 12036 001c FFE0 b .L951 + 12037 .L950: + 12038 .loc 1 4293 3 discriminator 2 + 12039 001e FB68 ldr r3, [r7, #12] + ARM GAS /tmp/ccl4b9YO.s page 286 + + + 12040 0020 0122 movs r2, #1 + 12041 0022 83F83C20 strb r2, [r3, #60] +4294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** switch (Channel) + 12042 .loc 1 4295 3 is_stmt 1 + 12043 0026 7B68 ldr r3, [r7, #4] + 12044 0028 142B cmp r3, #20 + 12045 002a 00F2F080 bhi .L952 + 12046 002e 01A2 adr r2, .L954 + 12047 0030 52F823F0 ldr pc, [r2, r3, lsl #2] + 12048 .p2align 2 + 12049 .L954: + 12050 0034 89000000 .word .L959+1 + 12051 0038 0F020000 .word .L952+1 + 12052 003c 0F020000 .word .L952+1 + 12053 0040 0F020000 .word .L952+1 + 12054 0044 C9000000 .word .L958+1 + 12055 0048 0F020000 .word .L952+1 + 12056 004c 0F020000 .word .L952+1 + 12057 0050 0F020000 .word .L952+1 + 12058 0054 0B010000 .word .L957+1 + 12059 0058 0F020000 .word .L952+1 + 12060 005c 0F020000 .word .L952+1 + 12061 0060 0F020000 .word .L952+1 + 12062 0064 4B010000 .word .L956+1 + 12063 0068 0F020000 .word .L952+1 + 12064 006c 0F020000 .word .L952+1 + 12065 0070 0F020000 .word .L952+1 + 12066 0074 8D010000 .word .L955+1 + 12067 0078 0F020000 .word .L952+1 + 12068 007c 0F020000 .word .L952+1 + 12069 0080 0F020000 .word .L952+1 + 12070 0084 CD010000 .word .L953+1 + 12071 .p2align 1 + 12072 .L959: +4296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_1: +4298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +4300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); +4301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Configure the Channel 1 in PWM mode */ +4303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_OC1_SetConfig(htim->Instance, sConfig); + 12073 .loc 1 4303 7 + 12074 0088 FB68 ldr r3, [r7, #12] + 12075 008a 1B68 ldr r3, [r3] + 12076 008c B968 ldr r1, [r7, #8] + 12077 008e 1846 mov r0, r3 + 12078 0090 FFF7FEFF bl TIM_OC1_SetConfig +4304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the Preload enable bit for channel1 */ +4306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; + 12079 .loc 1 4306 11 + 12080 0094 FB68 ldr r3, [r7, #12] + 12081 0096 1B68 ldr r3, [r3] + 12082 .loc 1 4306 21 + 12083 0098 9A69 ldr r2, [r3, #24] + ARM GAS /tmp/ccl4b9YO.s page 287 + + + 12084 .loc 1 4306 11 + 12085 009a FB68 ldr r3, [r7, #12] + 12086 009c 1B68 ldr r3, [r3] + 12087 .loc 1 4306 29 + 12088 009e 42F00802 orr r2, r2, #8 + 12089 00a2 9A61 str r2, [r3, #24] +4307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Configure the Output Fast mode */ +4309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; + 12090 .loc 1 4309 11 + 12091 00a4 FB68 ldr r3, [r7, #12] + 12092 00a6 1B68 ldr r3, [r3] + 12093 .loc 1 4309 21 + 12094 00a8 9A69 ldr r2, [r3, #24] + 12095 .loc 1 4309 11 + 12096 00aa FB68 ldr r3, [r7, #12] + 12097 00ac 1B68 ldr r3, [r3] + 12098 .loc 1 4309 29 + 12099 00ae 22F00402 bic r2, r2, #4 + 12100 00b2 9A61 str r2, [r3, #24] +4310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->CCMR1 |= sConfig->OCFastMode; + 12101 .loc 1 4310 11 + 12102 00b4 FB68 ldr r3, [r7, #12] + 12103 00b6 1B68 ldr r3, [r3] + 12104 .loc 1 4310 21 + 12105 00b8 9969 ldr r1, [r3, #24] + 12106 .loc 1 4310 39 + 12107 00ba BB68 ldr r3, [r7, #8] + 12108 00bc 1A69 ldr r2, [r3, #16] + 12109 .loc 1 4310 11 + 12110 00be FB68 ldr r3, [r7, #12] + 12111 00c0 1B68 ldr r3, [r3] + 12112 .loc 1 4310 29 + 12113 00c2 0A43 orrs r2, r2, r1 + 12114 00c4 9A61 str r2, [r3, #24] +4311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 12115 .loc 1 4311 7 + 12116 00c6 A5E0 b .L960 + 12117 .L958: +4312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_2: +4315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +4317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); +4318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Configure the Channel 2 in PWM mode */ +4320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_OC2_SetConfig(htim->Instance, sConfig); + 12118 .loc 1 4320 7 + 12119 00c8 FB68 ldr r3, [r7, #12] + 12120 00ca 1B68 ldr r3, [r3] + 12121 00cc B968 ldr r1, [r7, #8] + 12122 00ce 1846 mov r0, r3 + 12123 00d0 FFF7FEFF bl TIM_OC2_SetConfig +4321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the Preload enable bit for channel2 */ +4323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; + ARM GAS /tmp/ccl4b9YO.s page 288 + + + 12124 .loc 1 4323 11 + 12125 00d4 FB68 ldr r3, [r7, #12] + 12126 00d6 1B68 ldr r3, [r3] + 12127 .loc 1 4323 21 + 12128 00d8 9A69 ldr r2, [r3, #24] + 12129 .loc 1 4323 11 + 12130 00da FB68 ldr r3, [r7, #12] + 12131 00dc 1B68 ldr r3, [r3] + 12132 .loc 1 4323 29 + 12133 00de 42F40062 orr r2, r2, #2048 + 12134 00e2 9A61 str r2, [r3, #24] +4324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Configure the Output Fast mode */ +4326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; + 12135 .loc 1 4326 11 + 12136 00e4 FB68 ldr r3, [r7, #12] + 12137 00e6 1B68 ldr r3, [r3] + 12138 .loc 1 4326 21 + 12139 00e8 9A69 ldr r2, [r3, #24] + 12140 .loc 1 4326 11 + 12141 00ea FB68 ldr r3, [r7, #12] + 12142 00ec 1B68 ldr r3, [r3] + 12143 .loc 1 4326 29 + 12144 00ee 22F48062 bic r2, r2, #1024 + 12145 00f2 9A61 str r2, [r3, #24] +4327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; + 12146 .loc 1 4327 11 + 12147 00f4 FB68 ldr r3, [r7, #12] + 12148 00f6 1B68 ldr r3, [r3] + 12149 .loc 1 4327 21 + 12150 00f8 9969 ldr r1, [r3, #24] + 12151 .loc 1 4327 39 + 12152 00fa BB68 ldr r3, [r7, #8] + 12153 00fc 1B69 ldr r3, [r3, #16] + 12154 .loc 1 4327 52 + 12155 00fe 1A02 lsls r2, r3, #8 + 12156 .loc 1 4327 11 + 12157 0100 FB68 ldr r3, [r7, #12] + 12158 0102 1B68 ldr r3, [r3] + 12159 .loc 1 4327 29 + 12160 0104 0A43 orrs r2, r2, r1 + 12161 0106 9A61 str r2, [r3, #24] +4328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 12162 .loc 1 4328 7 + 12163 0108 84E0 b .L960 + 12164 .L957: +4329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_3: +4332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +4334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); +4335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Configure the Channel 3 in PWM mode */ +4337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_OC3_SetConfig(htim->Instance, sConfig); + 12165 .loc 1 4337 7 + 12166 010a FB68 ldr r3, [r7, #12] + ARM GAS /tmp/ccl4b9YO.s page 289 + + + 12167 010c 1B68 ldr r3, [r3] + 12168 010e B968 ldr r1, [r7, #8] + 12169 0110 1846 mov r0, r3 + 12170 0112 FFF7FEFF bl TIM_OC3_SetConfig +4338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the Preload enable bit for channel3 */ +4340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; + 12171 .loc 1 4340 11 + 12172 0116 FB68 ldr r3, [r7, #12] + 12173 0118 1B68 ldr r3, [r3] + 12174 .loc 1 4340 21 + 12175 011a DA69 ldr r2, [r3, #28] + 12176 .loc 1 4340 11 + 12177 011c FB68 ldr r3, [r7, #12] + 12178 011e 1B68 ldr r3, [r3] + 12179 .loc 1 4340 29 + 12180 0120 42F00802 orr r2, r2, #8 + 12181 0124 DA61 str r2, [r3, #28] +4341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Configure the Output Fast mode */ +4343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; + 12182 .loc 1 4343 11 + 12183 0126 FB68 ldr r3, [r7, #12] + 12184 0128 1B68 ldr r3, [r3] + 12185 .loc 1 4343 21 + 12186 012a DA69 ldr r2, [r3, #28] + 12187 .loc 1 4343 11 + 12188 012c FB68 ldr r3, [r7, #12] + 12189 012e 1B68 ldr r3, [r3] + 12190 .loc 1 4343 29 + 12191 0130 22F00402 bic r2, r2, #4 + 12192 0134 DA61 str r2, [r3, #28] +4344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->CCMR2 |= sConfig->OCFastMode; + 12193 .loc 1 4344 11 + 12194 0136 FB68 ldr r3, [r7, #12] + 12195 0138 1B68 ldr r3, [r3] + 12196 .loc 1 4344 21 + 12197 013a D969 ldr r1, [r3, #28] + 12198 .loc 1 4344 39 + 12199 013c BB68 ldr r3, [r7, #8] + 12200 013e 1A69 ldr r2, [r3, #16] + 12201 .loc 1 4344 11 + 12202 0140 FB68 ldr r3, [r7, #12] + 12203 0142 1B68 ldr r3, [r3] + 12204 .loc 1 4344 29 + 12205 0144 0A43 orrs r2, r2, r1 + 12206 0146 DA61 str r2, [r3, #28] +4345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 12207 .loc 1 4345 7 + 12208 0148 64E0 b .L960 + 12209 .L956: +4346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_4: +4349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +4351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + ARM GAS /tmp/ccl4b9YO.s page 290 + + +4352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Configure the Channel 4 in PWM mode */ +4354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_OC4_SetConfig(htim->Instance, sConfig); + 12210 .loc 1 4354 7 + 12211 014a FB68 ldr r3, [r7, #12] + 12212 014c 1B68 ldr r3, [r3] + 12213 014e B968 ldr r1, [r7, #8] + 12214 0150 1846 mov r0, r3 + 12215 0152 FFF7FEFF bl TIM_OC4_SetConfig +4355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the Preload enable bit for channel4 */ +4357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; + 12216 .loc 1 4357 11 + 12217 0156 FB68 ldr r3, [r7, #12] + 12218 0158 1B68 ldr r3, [r3] + 12219 .loc 1 4357 21 + 12220 015a DA69 ldr r2, [r3, #28] + 12221 .loc 1 4357 11 + 12222 015c FB68 ldr r3, [r7, #12] + 12223 015e 1B68 ldr r3, [r3] + 12224 .loc 1 4357 29 + 12225 0160 42F40062 orr r2, r2, #2048 + 12226 0164 DA61 str r2, [r3, #28] +4358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Configure the Output Fast mode */ +4360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; + 12227 .loc 1 4360 11 + 12228 0166 FB68 ldr r3, [r7, #12] + 12229 0168 1B68 ldr r3, [r3] + 12230 .loc 1 4360 21 + 12231 016a DA69 ldr r2, [r3, #28] + 12232 .loc 1 4360 11 + 12233 016c FB68 ldr r3, [r7, #12] + 12234 016e 1B68 ldr r3, [r3] + 12235 .loc 1 4360 29 + 12236 0170 22F48062 bic r2, r2, #1024 + 12237 0174 DA61 str r2, [r3, #28] +4361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; + 12238 .loc 1 4361 11 + 12239 0176 FB68 ldr r3, [r7, #12] + 12240 0178 1B68 ldr r3, [r3] + 12241 .loc 1 4361 21 + 12242 017a D969 ldr r1, [r3, #28] + 12243 .loc 1 4361 39 + 12244 017c BB68 ldr r3, [r7, #8] + 12245 017e 1B69 ldr r3, [r3, #16] + 12246 .loc 1 4361 52 + 12247 0180 1A02 lsls r2, r3, #8 + 12248 .loc 1 4361 11 + 12249 0182 FB68 ldr r3, [r7, #12] + 12250 0184 1B68 ldr r3, [r3] + 12251 .loc 1 4361 29 + 12252 0186 0A43 orrs r2, r2, r1 + 12253 0188 DA61 str r2, [r3, #28] +4362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 12254 .loc 1 4362 7 + 12255 018a 43E0 b .L960 + ARM GAS /tmp/ccl4b9YO.s page 291 + + + 12256 .L955: +4363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if defined(TIM_CCER_CC5E) +4366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_5: +4367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +4369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); +4370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Configure the Channel 5 in PWM mode */ +4372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_OC5_SetConfig(htim->Instance, sConfig); + 12257 .loc 1 4372 7 + 12258 018c FB68 ldr r3, [r7, #12] + 12259 018e 1B68 ldr r3, [r3] + 12260 0190 B968 ldr r1, [r7, #8] + 12261 0192 1846 mov r0, r3 + 12262 0194 FFF7FEFF bl TIM_OC5_SetConfig +4373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the Preload enable bit for channel5*/ +4375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; + 12263 .loc 1 4375 11 + 12264 0198 FB68 ldr r3, [r7, #12] + 12265 019a 1B68 ldr r3, [r3] + 12266 .loc 1 4375 21 + 12267 019c 5A6D ldr r2, [r3, #84] + 12268 .loc 1 4375 11 + 12269 019e FB68 ldr r3, [r7, #12] + 12270 01a0 1B68 ldr r3, [r3] + 12271 .loc 1 4375 29 + 12272 01a2 42F00802 orr r2, r2, #8 + 12273 01a6 5A65 str r2, [r3, #84] +4376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Configure the Output Fast mode */ +4378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; + 12274 .loc 1 4378 11 + 12275 01a8 FB68 ldr r3, [r7, #12] + 12276 01aa 1B68 ldr r3, [r3] + 12277 .loc 1 4378 21 + 12278 01ac 5A6D ldr r2, [r3, #84] + 12279 .loc 1 4378 11 + 12280 01ae FB68 ldr r3, [r7, #12] + 12281 01b0 1B68 ldr r3, [r3] + 12282 .loc 1 4378 29 + 12283 01b2 22F00402 bic r2, r2, #4 + 12284 01b6 5A65 str r2, [r3, #84] +4379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->CCMR3 |= sConfig->OCFastMode; + 12285 .loc 1 4379 11 + 12286 01b8 FB68 ldr r3, [r7, #12] + 12287 01ba 1B68 ldr r3, [r3] + 12288 .loc 1 4379 21 + 12289 01bc 596D ldr r1, [r3, #84] + 12290 .loc 1 4379 39 + 12291 01be BB68 ldr r3, [r7, #8] + 12292 01c0 1A69 ldr r2, [r3, #16] + 12293 .loc 1 4379 11 + 12294 01c2 FB68 ldr r3, [r7, #12] + 12295 01c4 1B68 ldr r3, [r3] + ARM GAS /tmp/ccl4b9YO.s page 292 + + + 12296 .loc 1 4379 29 + 12297 01c6 0A43 orrs r2, r2, r1 + 12298 01c8 5A65 str r2, [r3, #84] +4380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 12299 .loc 1 4380 7 + 12300 01ca 23E0 b .L960 + 12301 .L953: +4381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* TIM_CCER_CC5E */ +4383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if defined(TIM_CCER_CC6E) +4385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_6: +4386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +4388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); +4389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Configure the Channel 6 in PWM mode */ +4391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_OC6_SetConfig(htim->Instance, sConfig); + 12302 .loc 1 4391 7 + 12303 01cc FB68 ldr r3, [r7, #12] + 12304 01ce 1B68 ldr r3, [r3] + 12305 01d0 B968 ldr r1, [r7, #8] + 12306 01d2 1846 mov r0, r3 + 12307 01d4 FFF7FEFF bl TIM_OC6_SetConfig +4392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the Preload enable bit for channel6 */ +4394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; + 12308 .loc 1 4394 11 + 12309 01d8 FB68 ldr r3, [r7, #12] + 12310 01da 1B68 ldr r3, [r3] + 12311 .loc 1 4394 21 + 12312 01dc 5A6D ldr r2, [r3, #84] + 12313 .loc 1 4394 11 + 12314 01de FB68 ldr r3, [r7, #12] + 12315 01e0 1B68 ldr r3, [r3] + 12316 .loc 1 4394 29 + 12317 01e2 42F40062 orr r2, r2, #2048 + 12318 01e6 5A65 str r2, [r3, #84] +4395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Configure the Output Fast mode */ +4397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; + 12319 .loc 1 4397 11 + 12320 01e8 FB68 ldr r3, [r7, #12] + 12321 01ea 1B68 ldr r3, [r3] + 12322 .loc 1 4397 21 + 12323 01ec 5A6D ldr r2, [r3, #84] + 12324 .loc 1 4397 11 + 12325 01ee FB68 ldr r3, [r7, #12] + 12326 01f0 1B68 ldr r3, [r3] + 12327 .loc 1 4397 29 + 12328 01f2 22F48062 bic r2, r2, #1024 + 12329 01f6 5A65 str r2, [r3, #84] +4398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; + 12330 .loc 1 4398 11 + 12331 01f8 FB68 ldr r3, [r7, #12] + 12332 01fa 1B68 ldr r3, [r3] + 12333 .loc 1 4398 21 + ARM GAS /tmp/ccl4b9YO.s page 293 + + + 12334 01fc 596D ldr r1, [r3, #84] + 12335 .loc 1 4398 39 + 12336 01fe BB68 ldr r3, [r7, #8] + 12337 0200 1B69 ldr r3, [r3, #16] + 12338 .loc 1 4398 52 + 12339 0202 1A02 lsls r2, r3, #8 + 12340 .loc 1 4398 11 + 12341 0204 FB68 ldr r3, [r7, #12] + 12342 0206 1B68 ldr r3, [r3] + 12343 .loc 1 4398 29 + 12344 0208 0A43 orrs r2, r2, r1 + 12345 020a 5A65 str r2, [r3, #84] +4399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 12346 .loc 1 4399 7 + 12347 020c 02E0 b .L960 + 12348 .L952: +4400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* TIM_CCER_CC6E */ +4402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** default: +4404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** status = HAL_ERROR; + 12349 .loc 1 4404 14 + 12350 020e 0123 movs r3, #1 + 12351 0210 FB75 strb r3, [r7, #23] +4405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 12352 .loc 1 4405 7 + 12353 0212 00BF nop + 12354 .L960: +4406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_UNLOCK(htim); + 12355 .loc 1 4408 3 + 12356 0214 FB68 ldr r3, [r7, #12] + 12357 0216 0022 movs r2, #0 + 12358 0218 83F83C20 strb r2, [r3, #60] +4409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return status; + 12359 .loc 1 4410 10 + 12360 021c FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 12361 .L951: +4411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 12362 .loc 1 4411 1 + 12363 021e 1846 mov r0, r3 + 12364 0220 1837 adds r7, r7, #24 + 12365 .cfi_def_cfa_offset 8 + 12366 0222 BD46 mov sp, r7 + 12367 .cfi_def_cfa_register 13 + 12368 @ sp needed + 12369 0224 80BD pop {r7, pc} + 12370 .cfi_endproc + 12371 .LFE191: + 12373 0226 00BF .section .text.HAL_TIM_OnePulse_ConfigChannel,"ax",%progbits + 12374 .align 1 + 12375 .global HAL_TIM_OnePulse_ConfigChannel + 12376 .syntax unified + 12377 .thumb + 12378 .thumb_func + ARM GAS /tmp/ccl4b9YO.s page 294 + + + 12380 HAL_TIM_OnePulse_ConfigChannel: + 12381 .LFB192: +4412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +4414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Initializes the TIM One Pulse Channels according to the specified +4415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * parameters in the TIM_OnePulse_InitTypeDef. +4416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM One Pulse handle +4417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param sConfig TIM One Pulse configuration structure +4418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param OutputChannel TIM output channel to configure +4419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +4420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +4421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +4422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param InputChannel TIM input Channel to configure +4423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +4424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +4425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +4426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @note To output a waveform with a minimum delay user can enable the fast +4427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx +4428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * output is forced in response to the edge detection on TIx input, +4429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * without taking in account the comparison. +4430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status +4431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +4432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef +4433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t OutputChannel, uint32_t InputChannel) +4434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 12382 .loc 1 4434 1 + 12383 .cfi_startproc + 12384 @ args = 0, pretend = 0, frame = 48 + 12385 @ frame_needed = 1, uses_anonymous_args = 0 + 12386 0000 80B5 push {r7, lr} + 12387 .cfi_def_cfa_offset 8 + 12388 .cfi_offset 7, -8 + 12389 .cfi_offset 14, -4 + 12390 0002 8CB0 sub sp, sp, #48 + 12391 .cfi_def_cfa_offset 56 + 12392 0004 00AF add r7, sp, #0 + 12393 .cfi_def_cfa_register 7 + 12394 0006 F860 str r0, [r7, #12] + 12395 0008 B960 str r1, [r7, #8] + 12396 000a 7A60 str r2, [r7, #4] + 12397 000c 3B60 str r3, [r7] +4435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 12398 .loc 1 4435 21 + 12399 000e 0023 movs r3, #0 + 12400 0010 87F82F30 strb r3, [r7, #47] +4436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_OC_InitTypeDef temp1; +4437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +4439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); +4440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); +4441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (OutputChannel != InputChannel) + 12401 .loc 1 4442 6 + 12402 0014 7A68 ldr r2, [r7, #4] + 12403 0016 3B68 ldr r3, [r7] + 12404 0018 9A42 cmp r2, r3 + 12405 001a 00F0C280 beq .L962 + ARM GAS /tmp/ccl4b9YO.s page 295 + + +4443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Process Locked */ +4445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_LOCK(htim); + 12406 .loc 1 4445 5 + 12407 001e FB68 ldr r3, [r7, #12] + 12408 0020 93F83C30 ldrb r3, [r3, #60] @ zero_extendqisi2 + 12409 0024 012B cmp r3, #1 + 12410 0026 01D1 bne .L963 + 12411 .loc 1 4445 5 is_stmt 0 discriminator 1 + 12412 0028 0223 movs r3, #2 + 12413 .loc 1 4445 5 + 12414 002a BBE0 b .L973 + 12415 .L963: + 12416 .loc 1 4445 5 discriminator 2 + 12417 002c FB68 ldr r3, [r7, #12] + 12418 002e 0122 movs r2, #1 + 12419 0030 83F83C20 strb r2, [r3, #60] +4446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; + 12420 .loc 1 4447 17 is_stmt 1 + 12421 0034 FB68 ldr r3, [r7, #12] + 12422 0036 0222 movs r2, #2 + 12423 0038 83F83D20 strb r2, [r3, #61] +4448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Extract the Output compare configuration from sConfig structure */ +4450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** temp1.OCMode = sConfig->OCMode; + 12424 .loc 1 4450 27 + 12425 003c BB68 ldr r3, [r7, #8] + 12426 003e 1B68 ldr r3, [r3] + 12427 .loc 1 4450 18 + 12428 0040 3B61 str r3, [r7, #16] +4451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** temp1.Pulse = sConfig->Pulse; + 12429 .loc 1 4451 26 + 12430 0042 BB68 ldr r3, [r7, #8] + 12431 0044 5B68 ldr r3, [r3, #4] + 12432 .loc 1 4451 17 + 12433 0046 7B61 str r3, [r7, #20] +4452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** temp1.OCPolarity = sConfig->OCPolarity; + 12434 .loc 1 4452 31 + 12435 0048 BB68 ldr r3, [r7, #8] + 12436 004a 9B68 ldr r3, [r3, #8] + 12437 .loc 1 4452 22 + 12438 004c BB61 str r3, [r7, #24] +4453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** temp1.OCNPolarity = sConfig->OCNPolarity; + 12439 .loc 1 4453 32 + 12440 004e BB68 ldr r3, [r7, #8] + 12441 0050 DB68 ldr r3, [r3, #12] + 12442 .loc 1 4453 23 + 12443 0052 FB61 str r3, [r7, #28] +4454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** temp1.OCIdleState = sConfig->OCIdleState; + 12444 .loc 1 4454 32 + 12445 0054 BB68 ldr r3, [r7, #8] + 12446 0056 1B69 ldr r3, [r3, #16] + 12447 .loc 1 4454 23 + 12448 0058 7B62 str r3, [r7, #36] +4455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** temp1.OCNIdleState = sConfig->OCNIdleState; + 12449 .loc 1 4455 33 + ARM GAS /tmp/ccl4b9YO.s page 296 + + + 12450 005a BB68 ldr r3, [r7, #8] + 12451 005c 5B69 ldr r3, [r3, #20] + 12452 .loc 1 4455 24 + 12453 005e BB62 str r3, [r7, #40] +4456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** switch (OutputChannel) + 12454 .loc 1 4457 5 + 12455 0060 7B68 ldr r3, [r7, #4] + 12456 0062 002B cmp r3, #0 + 12457 0064 03D0 beq .L965 + 12458 0066 7B68 ldr r3, [r7, #4] + 12459 0068 042B cmp r3, #4 + 12460 006a 09D0 beq .L966 + 12461 006c 11E0 b .L974 + 12462 .L965: +4458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_1: +4460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); +4462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_OC1_SetConfig(htim->Instance, &temp1); + 12463 .loc 1 4463 9 + 12464 006e FB68 ldr r3, [r7, #12] + 12465 0070 1B68 ldr r3, [r3] + 12466 0072 07F11002 add r2, r7, #16 + 12467 0076 1146 mov r1, r2 + 12468 0078 1846 mov r0, r3 + 12469 007a FFF7FEFF bl TIM_OC1_SetConfig +4464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 12470 .loc 1 4464 9 + 12471 007e 0CE0 b .L968 + 12472 .L966: +4465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_2: +4468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); +4470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_OC2_SetConfig(htim->Instance, &temp1); + 12473 .loc 1 4471 9 + 12474 0080 FB68 ldr r3, [r7, #12] + 12475 0082 1B68 ldr r3, [r3] + 12476 0084 07F11002 add r2, r7, #16 + 12477 0088 1146 mov r1, r2 + 12478 008a 1846 mov r0, r3 + 12479 008c FFF7FEFF bl TIM_OC2_SetConfig +4472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 12480 .loc 1 4472 9 + 12481 0090 03E0 b .L968 + 12482 .L974: +4473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** default: +4476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** status = HAL_ERROR; + 12483 .loc 1 4476 16 + 12484 0092 0123 movs r3, #1 + 12485 0094 87F82F30 strb r3, [r7, #47] + ARM GAS /tmp/ccl4b9YO.s page 297 + + +4477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 12486 .loc 1 4477 9 + 12487 0098 00BF nop + 12488 .L968: +4478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (status == HAL_OK) + 12489 .loc 1 4480 8 + 12490 009a 97F82F30 ldrb r3, [r7, #47] @ zero_extendqisi2 + 12491 009e 002B cmp r3, #0 + 12492 00a0 74D1 bne .L969 +4481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** switch (InputChannel) + 12493 .loc 1 4482 7 + 12494 00a2 3B68 ldr r3, [r7] + 12495 00a4 002B cmp r3, #0 + 12496 00a6 03D0 beq .L970 + 12497 00a8 3B68 ldr r3, [r7] + 12498 00aa 042B cmp r3, #4 + 12499 00ac 35D0 beq .L971 + 12500 00ae 69E0 b .L975 + 12501 .L970: +4483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_1: +4485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); +4487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, + 12502 .loc 1 4488 11 + 12503 00b0 FB68 ldr r3, [r7, #12] + 12504 00b2 1868 ldr r0, [r3] + 12505 00b4 BB68 ldr r3, [r7, #8] + 12506 00b6 9969 ldr r1, [r3, #24] + 12507 00b8 BB68 ldr r3, [r7, #8] + 12508 00ba DA69 ldr r2, [r3, #28] + 12509 00bc BB68 ldr r3, [r7, #8] + 12510 00be 1B6A ldr r3, [r3, #32] + 12511 00c0 FFF7FEFF bl TIM_TI1_SetConfig +4489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** sConfig->ICSelection, sConfig->ICFilter); +4490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Reset the IC1PSC Bits */ +4492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + 12512 .loc 1 4492 15 + 12513 00c4 FB68 ldr r3, [r7, #12] + 12514 00c6 1B68 ldr r3, [r3] + 12515 .loc 1 4492 25 + 12516 00c8 9A69 ldr r2, [r3, #24] + 12517 .loc 1 4492 15 + 12518 00ca FB68 ldr r3, [r7, #12] + 12519 00cc 1B68 ldr r3, [r3] + 12520 .loc 1 4492 33 + 12521 00ce 22F00C02 bic r2, r2, #12 + 12522 00d2 9A61 str r2, [r3, #24] +4493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Select the Trigger source */ +4495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->SMCR &= ~TIM_SMCR_TS; + 12523 .loc 1 4495 15 + ARM GAS /tmp/ccl4b9YO.s page 298 + + + 12524 00d4 FB68 ldr r3, [r7, #12] + 12525 00d6 1B68 ldr r3, [r3] + 12526 .loc 1 4495 25 + 12527 00d8 9A68 ldr r2, [r3, #8] + 12528 .loc 1 4495 15 + 12529 00da FB68 ldr r3, [r7, #12] + 12530 00dc 1B68 ldr r3, [r3] + 12531 .loc 1 4495 32 + 12532 00de 22F07002 bic r2, r2, #112 + 12533 00e2 9A60 str r2, [r3, #8] +4496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->SMCR |= TIM_TS_TI1FP1; + 12534 .loc 1 4496 15 + 12535 00e4 FB68 ldr r3, [r7, #12] + 12536 00e6 1B68 ldr r3, [r3] + 12537 .loc 1 4496 25 + 12538 00e8 9A68 ldr r2, [r3, #8] + 12539 .loc 1 4496 15 + 12540 00ea FB68 ldr r3, [r7, #12] + 12541 00ec 1B68 ldr r3, [r3] + 12542 .loc 1 4496 32 + 12543 00ee 42F05002 orr r2, r2, #80 + 12544 00f2 9A60 str r2, [r3, #8] +4497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Select the Slave Mode */ +4499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->SMCR &= ~TIM_SMCR_SMS; + 12545 .loc 1 4499 15 + 12546 00f4 FB68 ldr r3, [r7, #12] + 12547 00f6 1B68 ldr r3, [r3] + 12548 .loc 1 4499 25 + 12549 00f8 9B68 ldr r3, [r3, #8] + 12550 .loc 1 4499 15 + 12551 00fa FA68 ldr r2, [r7, #12] + 12552 00fc 1268 ldr r2, [r2] + 12553 .loc 1 4499 32 + 12554 00fe 23F48033 bic r3, r3, #65536 + 12555 0102 23F00703 bic r3, r3, #7 + 12556 0106 9360 str r3, [r2, #8] +4500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + 12557 .loc 1 4500 15 + 12558 0108 FB68 ldr r3, [r7, #12] + 12559 010a 1B68 ldr r3, [r3] + 12560 .loc 1 4500 25 + 12561 010c 9A68 ldr r2, [r3, #8] + 12562 .loc 1 4500 15 + 12563 010e FB68 ldr r3, [r7, #12] + 12564 0110 1B68 ldr r3, [r3] + 12565 .loc 1 4500 32 + 12566 0112 42F00602 orr r2, r2, #6 + 12567 0116 9A60 str r2, [r3, #8] +4501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 12568 .loc 1 4501 11 + 12569 0118 38E0 b .L969 + 12570 .L971: +4502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_2: +4505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + ARM GAS /tmp/ccl4b9YO.s page 299 + + +4506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); +4507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, + 12571 .loc 1 4508 11 + 12572 011a FB68 ldr r3, [r7, #12] + 12573 011c 1868 ldr r0, [r3] + 12574 011e BB68 ldr r3, [r7, #8] + 12575 0120 9969 ldr r1, [r3, #24] + 12576 0122 BB68 ldr r3, [r7, #8] + 12577 0124 DA69 ldr r2, [r3, #28] + 12578 0126 BB68 ldr r3, [r7, #8] + 12579 0128 1B6A ldr r3, [r3, #32] + 12580 012a FFF7FEFF bl TIM_TI2_SetConfig +4509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** sConfig->ICSelection, sConfig->ICFilter); +4510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Reset the IC2PSC Bits */ +4512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + 12581 .loc 1 4512 15 + 12582 012e FB68 ldr r3, [r7, #12] + 12583 0130 1B68 ldr r3, [r3] + 12584 .loc 1 4512 25 + 12585 0132 9A69 ldr r2, [r3, #24] + 12586 .loc 1 4512 15 + 12587 0134 FB68 ldr r3, [r7, #12] + 12588 0136 1B68 ldr r3, [r3] + 12589 .loc 1 4512 33 + 12590 0138 22F44062 bic r2, r2, #3072 + 12591 013c 9A61 str r2, [r3, #24] +4513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Select the Trigger source */ +4515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->SMCR &= ~TIM_SMCR_TS; + 12592 .loc 1 4515 15 + 12593 013e FB68 ldr r3, [r7, #12] + 12594 0140 1B68 ldr r3, [r3] + 12595 .loc 1 4515 25 + 12596 0142 9A68 ldr r2, [r3, #8] + 12597 .loc 1 4515 15 + 12598 0144 FB68 ldr r3, [r7, #12] + 12599 0146 1B68 ldr r3, [r3] + 12600 .loc 1 4515 32 + 12601 0148 22F07002 bic r2, r2, #112 + 12602 014c 9A60 str r2, [r3, #8] +4516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->SMCR |= TIM_TS_TI2FP2; + 12603 .loc 1 4516 15 + 12604 014e FB68 ldr r3, [r7, #12] + 12605 0150 1B68 ldr r3, [r3] + 12606 .loc 1 4516 25 + 12607 0152 9A68 ldr r2, [r3, #8] + 12608 .loc 1 4516 15 + 12609 0154 FB68 ldr r3, [r7, #12] + 12610 0156 1B68 ldr r3, [r3] + 12611 .loc 1 4516 32 + 12612 0158 42F06002 orr r2, r2, #96 + 12613 015c 9A60 str r2, [r3, #8] +4517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Select the Slave Mode */ +4519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->SMCR &= ~TIM_SMCR_SMS; + ARM GAS /tmp/ccl4b9YO.s page 300 + + + 12614 .loc 1 4519 15 + 12615 015e FB68 ldr r3, [r7, #12] + 12616 0160 1B68 ldr r3, [r3] + 12617 .loc 1 4519 25 + 12618 0162 9B68 ldr r3, [r3, #8] + 12619 .loc 1 4519 15 + 12620 0164 FA68 ldr r2, [r7, #12] + 12621 0166 1268 ldr r2, [r2] + 12622 .loc 1 4519 32 + 12623 0168 23F48033 bic r3, r3, #65536 + 12624 016c 23F00703 bic r3, r3, #7 + 12625 0170 9360 str r3, [r2, #8] +4520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + 12626 .loc 1 4520 15 + 12627 0172 FB68 ldr r3, [r7, #12] + 12628 0174 1B68 ldr r3, [r3] + 12629 .loc 1 4520 25 + 12630 0176 9A68 ldr r2, [r3, #8] + 12631 .loc 1 4520 15 + 12632 0178 FB68 ldr r3, [r7, #12] + 12633 017a 1B68 ldr r3, [r3] + 12634 .loc 1 4520 32 + 12635 017c 42F00602 orr r2, r2, #6 + 12636 0180 9A60 str r2, [r3, #8] +4521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 12637 .loc 1 4521 11 + 12638 0182 03E0 b .L969 + 12639 .L975: +4522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** default: +4525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** status = HAL_ERROR; + 12640 .loc 1 4525 18 + 12641 0184 0123 movs r3, #1 + 12642 0186 87F82F30 strb r3, [r7, #47] +4526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 12643 .loc 1 4526 11 + 12644 018a 00BF nop + 12645 .L969: +4527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; + 12646 .loc 1 4530 17 + 12647 018c FB68 ldr r3, [r7, #12] + 12648 018e 0122 movs r2, #1 + 12649 0190 83F83D20 strb r2, [r3, #61] +4531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_UNLOCK(htim); + 12650 .loc 1 4532 5 + 12651 0194 FB68 ldr r3, [r7, #12] + 12652 0196 0022 movs r2, #0 + 12653 0198 83F83C20 strb r2, [r3, #60] +4533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return status; + 12654 .loc 1 4534 12 + 12655 019c 97F82F30 ldrb r3, [r7, #47] @ zero_extendqisi2 + ARM GAS /tmp/ccl4b9YO.s page 301 + + + 12656 01a0 00E0 b .L973 + 12657 .L962: +4535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +4537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 12658 .loc 1 4538 12 + 12659 01a2 0123 movs r3, #1 + 12660 .L973: +4539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 12661 .loc 1 4540 1 + 12662 01a4 1846 mov r0, r3 + 12663 01a6 3037 adds r7, r7, #48 + 12664 .cfi_def_cfa_offset 8 + 12665 01a8 BD46 mov sp, r7 + 12666 .cfi_def_cfa_register 13 + 12667 @ sp needed + 12668 01aa 80BD pop {r7, pc} + 12669 .cfi_endproc + 12670 .LFE192: + 12672 .section .text.HAL_TIM_DMABurst_WriteStart,"ax",%progbits + 12673 .align 1 + 12674 .global HAL_TIM_DMABurst_WriteStart + 12675 .syntax unified + 12676 .thumb + 12677 .thumb_func + 12679 HAL_TIM_DMABurst_WriteStart: + 12680 .LFB193: +4541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +4543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral +4544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM handle +4545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write +4546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +4547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CR1 +4548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CR2 +4549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_SMCR +4550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_DIER +4551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_SR +4552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_EGR +4553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CCMR1 +4554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CCMR2 +4555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CCER +4556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CNT +4557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_PSC +4558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_ARR +4559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_RCR +4560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CCR1 +4561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CCR2 +4562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CCR3 +4563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CCR4 +4564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_BDTR +4565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_OR +4566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CCMR3 (*) +4567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CCR5 (*) +4568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CCR6 (*) + ARM GAS /tmp/ccl4b9YO.s page 302 + + +4569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * (*) value not defined in all devices +4570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param BurstRequestSrc TIM DMA Request sources +4571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +4572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMA_UPDATE: TIM update Interrupt source +4573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source +4574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source +4575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source +4576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source +4577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMA_COM: TIM Commutation DMA source +4578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source +4579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param BurstBuffer The Buffer address. +4580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param BurstLength DMA Burst length. This parameter can be one value +4581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. +4582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @note This function should be used only when BurstLength is equal to DMA data transfer length +4583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status +4584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +4585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, +4586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t BurstRequestSrc, const uint32_t *BurstBuffer +4587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 12681 .loc 1 4587 1 + 12682 .cfi_startproc + 12683 @ args = 4, pretend = 0, frame = 24 + 12684 @ frame_needed = 1, uses_anonymous_args = 0 + 12685 0000 80B5 push {r7, lr} + 12686 .cfi_def_cfa_offset 8 + 12687 .cfi_offset 7, -8 + 12688 .cfi_offset 14, -4 + 12689 0002 88B0 sub sp, sp, #32 + 12690 .cfi_def_cfa_offset 40 + 12691 0004 02AF add r7, sp, #8 + 12692 .cfi_def_cfa 7, 32 + 12693 0006 F860 str r0, [r7, #12] + 12694 0008 B960 str r1, [r7, #8] + 12695 000a 7A60 str r2, [r7, #4] + 12696 000c 3B60 str r3, [r7] +4588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef status; +4589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, B +4591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** ((BurstLength) >> 8U) + 1U); + 12697 .loc 1 4591 60 + 12698 000e 3B6A ldr r3, [r7, #32] + 12699 0010 1B0A lsrs r3, r3, #8 +4590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** ((BurstLength) >> 8U) + 1U); + 12700 .loc 1 4590 12 + 12701 0012 0133 adds r3, r3, #1 + 12702 0014 0193 str r3, [sp, #4] + 12703 0016 3B6A ldr r3, [r7, #32] + 12704 0018 0093 str r3, [sp] + 12705 001a 3B68 ldr r3, [r7] + 12706 001c 7A68 ldr r2, [r7, #4] + 12707 001e B968 ldr r1, [r7, #8] + 12708 0020 F868 ldr r0, [r7, #12] + 12709 0022 FFF7FEFF bl HAL_TIM_DMABurst_MultiWriteStart + 12710 0026 0346 mov r3, r0 + 12711 0028 FB75 strb r3, [r7, #23] +4592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + ARM GAS /tmp/ccl4b9YO.s page 303 + + +4594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return status; + 12712 .loc 1 4595 10 + 12713 002a FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 +4596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 12714 .loc 1 4596 1 + 12715 002c 1846 mov r0, r3 + 12716 002e 1837 adds r7, r7, #24 + 12717 .cfi_def_cfa_offset 8 + 12718 0030 BD46 mov sp, r7 + 12719 .cfi_def_cfa_register 13 + 12720 @ sp needed + 12721 0032 80BD pop {r7, pc} + 12722 .cfi_endproc + 12723 .LFE193: + 12725 .section .text.HAL_TIM_DMABurst_MultiWriteStart,"ax",%progbits + 12726 .align 1 + 12727 .global HAL_TIM_DMABurst_MultiWriteStart + 12728 .syntax unified + 12729 .thumb + 12730 .thumb_func + 12732 HAL_TIM_DMABurst_MultiWriteStart: + 12733 .LFB194: +4597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +4599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral +4600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM handle +4601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write +4602:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +4603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CR1 +4604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CR2 +4605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_SMCR +4606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_DIER +4607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_SR +4608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_EGR +4609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CCMR1 +4610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CCMR2 +4611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CCER +4612:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CNT +4613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_PSC +4614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_ARR +4615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_RCR +4616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CCR1 +4617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CCR2 +4618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CCR3 +4619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CCR4 +4620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_BDTR +4621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_OR +4622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CCMR3 (*) +4623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CCR5 (*) +4624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CCR6 (*) +4625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * (*) value not defined in all devices +4626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param BurstRequestSrc TIM DMA Request sources +4627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +4628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMA_UPDATE: TIM update Interrupt source +4629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source +4630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + ARM GAS /tmp/ccl4b9YO.s page 304 + + +4631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source +4632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source +4633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMA_COM: TIM Commutation DMA source +4634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source +4635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param BurstBuffer The Buffer address. +4636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param BurstLength DMA Burst length. This parameter can be one value +4637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. +4638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param DataLength Data length. This parameter can be one value +4639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * between 1 and 0xFFFF. +4640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status +4641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +4642:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddre +4643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t BurstRequestSrc, const uint32_t *BurstB +4644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t BurstLength, uint32_t DataLength) +4645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 12734 .loc 1 4645 1 + 12735 .cfi_startproc + 12736 @ args = 8, pretend = 0, frame = 24 + 12737 @ frame_needed = 1, uses_anonymous_args = 0 + 12738 0000 80B5 push {r7, lr} + 12739 .cfi_def_cfa_offset 8 + 12740 .cfi_offset 7, -8 + 12741 .cfi_offset 14, -4 + 12742 0002 86B0 sub sp, sp, #24 + 12743 .cfi_def_cfa_offset 32 + 12744 0004 00AF add r7, sp, #0 + 12745 .cfi_def_cfa_register 7 + 12746 0006 F860 str r0, [r7, #12] + 12747 0008 B960 str r1, [r7, #8] + 12748 000a 7A60 str r2, [r7, #4] + 12749 000c 3B60 str r3, [r7] +4646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 12750 .loc 1 4646 21 + 12751 000e 0023 movs r3, #0 + 12752 0010 FB75 strb r3, [r7, #23] +4647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +4649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); +4650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); +4651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); +4652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_DMA_LENGTH(BurstLength)); +4653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); +4654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4655:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) + 12753 .loc 1 4655 11 + 12754 0012 FB68 ldr r3, [r7, #12] + 12755 0014 93F84830 ldrb r3, [r3, #72] + 12756 0018 DBB2 uxtb r3, r3 + 12757 .loc 1 4655 6 + 12758 001a 022B cmp r3, #2 + 12759 001c 01D1 bne .L979 +4656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4657:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_BUSY; + 12760 .loc 1 4657 12 + 12761 001e 0223 movs r3, #2 + 12762 0020 2BE1 b .L980 + 12763 .L979: + ARM GAS /tmp/ccl4b9YO.s page 305 + + +4658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4659:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) + 12764 .loc 1 4659 16 + 12765 0022 FB68 ldr r3, [r7, #12] + 12766 0024 93F84830 ldrb r3, [r3, #72] + 12767 0028 DBB2 uxtb r3, r3 + 12768 .loc 1 4659 11 + 12769 002a 012B cmp r3, #1 + 12770 002c 0BD1 bne .L981 +4660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if ((BurstBuffer == NULL) && (BurstLength > 0U)) + 12771 .loc 1 4661 8 + 12772 002e 3B68 ldr r3, [r7] + 12773 0030 002B cmp r3, #0 + 12774 0032 04D1 bne .L982 + 12775 .loc 1 4661 31 discriminator 1 + 12776 0034 3B6A ldr r3, [r7, #32] + 12777 0036 002B cmp r3, #0 + 12778 0038 01D0 beq .L982 +4662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 12779 .loc 1 4663 14 + 12780 003a 0123 movs r3, #1 + 12781 003c 1DE1 b .L980 + 12782 .L982: +4664:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +4666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; + 12783 .loc 1 4667 27 + 12784 003e FB68 ldr r3, [r7, #12] + 12785 0040 0222 movs r2, #2 + 12786 0042 83F84820 strb r2, [r3, #72] + 12787 .L981: +4668:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +4671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* nothing to do */ +4673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** switch (BurstRequestSrc) + 12788 .loc 1 4675 3 + 12789 0046 7B68 ldr r3, [r7, #4] + 12790 0048 B3F5804F cmp r3, #16384 + 12791 004c 00F0D880 beq .L983 + 12792 0050 7B68 ldr r3, [r7, #4] + 12793 0052 B3F5804F cmp r3, #16384 + 12794 0056 00F2EE80 bhi .L984 + 12795 005a 7B68 ldr r3, [r7, #4] + 12796 005c B3F5005F cmp r3, #8192 + 12797 0060 00F0B380 beq .L985 + 12798 0064 7B68 ldr r3, [r7, #4] + 12799 0066 B3F5005F cmp r3, #8192 + 12800 006a 00F2E480 bhi .L984 + 12801 006e 7B68 ldr r3, [r7, #4] + 12802 0070 B3F5805F cmp r3, #4096 + ARM GAS /tmp/ccl4b9YO.s page 306 + + + 12803 0074 00F08E80 beq .L986 + 12804 0078 7B68 ldr r3, [r7, #4] + 12805 007a B3F5805F cmp r3, #4096 + 12806 007e 00F2DA80 bhi .L984 + 12807 0082 7B68 ldr r3, [r7, #4] + 12808 0084 B3F5006F cmp r3, #2048 + 12809 0088 69D0 beq .L987 + 12810 008a 7B68 ldr r3, [r7, #4] + 12811 008c B3F5006F cmp r3, #2048 + 12812 0090 00F2D180 bhi .L984 + 12813 0094 7B68 ldr r3, [r7, #4] + 12814 0096 B3F5806F cmp r3, #1024 + 12815 009a 45D0 beq .L988 + 12816 009c 7B68 ldr r3, [r7, #4] + 12817 009e B3F5806F cmp r3, #1024 + 12818 00a2 00F2C880 bhi .L984 + 12819 00a6 7B68 ldr r3, [r7, #4] + 12820 00a8 B3F5807F cmp r3, #256 + 12821 00ac 04D0 beq .L989 + 12822 00ae 7B68 ldr r3, [r7, #4] + 12823 00b0 B3F5007F cmp r3, #512 + 12824 00b4 1CD0 beq .L990 + 12825 00b6 BEE0 b .L984 + 12826 .L989: +4676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_DMA_UPDATE: +4678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA Period elapsed callbacks */ +4680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + 12827 .loc 1 4680 17 + 12828 00b8 FB68 ldr r3, [r7, #12] + 12829 00ba 1B6A ldr r3, [r3, #32] + 12830 .loc 1 4680 55 + 12831 00bc 714A ldr r2, .L1007 + 12832 00be 9A62 str r2, [r3, #40] +4681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + 12833 .loc 1 4681 17 + 12834 00c0 FB68 ldr r3, [r7, #12] + 12835 00c2 1B6A ldr r3, [r3, #32] + 12836 .loc 1 4681 59 + 12837 00c4 704A ldr r2, .L1007+4 + 12838 00c6 DA62 str r2, [r3, #44] +4682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA error callback */ +4684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + 12839 .loc 1 4684 17 + 12840 00c8 FB68 ldr r3, [r7, #12] + 12841 00ca 1B6A ldr r3, [r3, #32] + 12842 .loc 1 4684 56 + 12843 00cc 6F4A ldr r2, .L1007+8 + 12844 00ce 1A63 str r2, [r3, #48] +4685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the DMA channel */ +4687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, + 12845 .loc 1 4687 11 + 12846 00d0 FB68 ldr r3, [r7, #12] + 12847 00d2 186A ldr r0, [r3, #32] + ARM GAS /tmp/ccl4b9YO.s page 307 + + + 12848 00d4 3968 ldr r1, [r7] +4688:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + 12849 .loc 1 4688 43 + 12850 00d6 FB68 ldr r3, [r7, #12] + 12851 00d8 1B68 ldr r3, [r3] + 12852 .loc 1 4688 38 + 12853 00da 4C33 adds r3, r3, #76 +4687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + 12854 .loc 1 4687 11 + 12855 00dc 1A46 mov r2, r3 + 12856 00de 7B6A ldr r3, [r7, #36] + 12857 00e0 FFF7FEFF bl HAL_DMA_Start_IT + 12858 00e4 0346 mov r3, r0 +4687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + 12859 .loc 1 4687 10 discriminator 1 + 12860 00e6 002B cmp r3, #0 + 12861 00e8 00F0A880 beq .L1000 +4689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return error status */ +4691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 12862 .loc 1 4691 16 + 12863 00ec 0123 movs r3, #1 + 12864 00ee C4E0 b .L980 + 12865 .L990: +4692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +4694:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_DMA_CC1: +4696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA compare callbacks */ +4698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + 12866 .loc 1 4698 17 + 12867 00f0 FB68 ldr r3, [r7, #12] + 12868 00f2 5B6A ldr r3, [r3, #36] + 12869 .loc 1 4698 52 + 12870 00f4 664A ldr r2, .L1007+12 + 12871 00f6 9A62 str r2, [r3, #40] +4699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 12872 .loc 1 4699 17 + 12873 00f8 FB68 ldr r3, [r7, #12] + 12874 00fa 5B6A ldr r3, [r3, #36] + 12875 .loc 1 4699 56 + 12876 00fc 654A ldr r2, .L1007+16 + 12877 00fe DA62 str r2, [r3, #44] +4700:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA error callback */ +4702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + 12878 .loc 1 4702 17 + 12879 0100 FB68 ldr r3, [r7, #12] + 12880 0102 5B6A ldr r3, [r3, #36] + 12881 .loc 1 4702 53 + 12882 0104 614A ldr r2, .L1007+8 + 12883 0106 1A63 str r2, [r3, #48] +4703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4704:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the DMA channel */ +4705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, + 12884 .loc 1 4705 11 + ARM GAS /tmp/ccl4b9YO.s page 308 + + + 12885 0108 FB68 ldr r3, [r7, #12] + 12886 010a 586A ldr r0, [r3, #36] + 12887 010c 3968 ldr r1, [r7] +4706:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + 12888 .loc 1 4706 43 + 12889 010e FB68 ldr r3, [r7, #12] + 12890 0110 1B68 ldr r3, [r3] + 12891 .loc 1 4706 38 + 12892 0112 4C33 adds r3, r3, #76 +4705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + 12893 .loc 1 4705 11 + 12894 0114 1A46 mov r2, r3 + 12895 0116 7B6A ldr r3, [r7, #36] + 12896 0118 FFF7FEFF bl HAL_DMA_Start_IT + 12897 011c 0346 mov r3, r0 +4705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + 12898 .loc 1 4705 10 discriminator 1 + 12899 011e 002B cmp r3, #0 + 12900 0120 00F08E80 beq .L1001 +4707:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4708:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return error status */ +4709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 12901 .loc 1 4709 16 + 12902 0124 0123 movs r3, #1 + 12903 0126 A8E0 b .L980 + 12904 .L988: +4710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +4712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4713:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_DMA_CC2: +4714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA compare callbacks */ +4716:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + 12905 .loc 1 4716 17 + 12906 0128 FB68 ldr r3, [r7, #12] + 12907 012a 9B6A ldr r3, [r3, #40] + 12908 .loc 1 4716 52 + 12909 012c 584A ldr r2, .L1007+12 + 12910 012e 9A62 str r2, [r3, #40] +4717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 12911 .loc 1 4717 17 + 12912 0130 FB68 ldr r3, [r7, #12] + 12913 0132 9B6A ldr r3, [r3, #40] + 12914 .loc 1 4717 56 + 12915 0134 574A ldr r2, .L1007+16 + 12916 0136 DA62 str r2, [r3, #44] +4718:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA error callback */ +4720:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + 12917 .loc 1 4720 17 + 12918 0138 FB68 ldr r3, [r7, #12] + 12919 013a 9B6A ldr r3, [r3, #40] + 12920 .loc 1 4720 53 + 12921 013c 534A ldr r2, .L1007+8 + 12922 013e 1A63 str r2, [r3, #48] +4721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4722:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the DMA channel */ + ARM GAS /tmp/ccl4b9YO.s page 309 + + +4723:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, + 12923 .loc 1 4723 11 + 12924 0140 FB68 ldr r3, [r7, #12] + 12925 0142 986A ldr r0, [r3, #40] + 12926 0144 3968 ldr r1, [r7] +4724:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + 12927 .loc 1 4724 43 + 12928 0146 FB68 ldr r3, [r7, #12] + 12929 0148 1B68 ldr r3, [r3] + 12930 .loc 1 4724 38 + 12931 014a 4C33 adds r3, r3, #76 +4723:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + 12932 .loc 1 4723 11 + 12933 014c 1A46 mov r2, r3 + 12934 014e 7B6A ldr r3, [r7, #36] + 12935 0150 FFF7FEFF bl HAL_DMA_Start_IT + 12936 0154 0346 mov r3, r0 +4723:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + 12937 .loc 1 4723 10 discriminator 1 + 12938 0156 002B cmp r3, #0 + 12939 0158 74D0 beq .L1002 +4725:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return error status */ +4727:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 12940 .loc 1 4727 16 + 12941 015a 0123 movs r3, #1 + 12942 015c 8DE0 b .L980 + 12943 .L987: +4728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +4730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_DMA_CC3: +4732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA compare callbacks */ +4734:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + 12944 .loc 1 4734 17 + 12945 015e FB68 ldr r3, [r7, #12] + 12946 0160 DB6A ldr r3, [r3, #44] + 12947 .loc 1 4734 52 + 12948 0162 4B4A ldr r2, .L1007+12 + 12949 0164 9A62 str r2, [r3, #40] +4735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 12950 .loc 1 4735 17 + 12951 0166 FB68 ldr r3, [r7, #12] + 12952 0168 DB6A ldr r3, [r3, #44] + 12953 .loc 1 4735 56 + 12954 016a 4A4A ldr r2, .L1007+16 + 12955 016c DA62 str r2, [r3, #44] +4736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4737:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA error callback */ +4738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + 12956 .loc 1 4738 17 + 12957 016e FB68 ldr r3, [r7, #12] + 12958 0170 DB6A ldr r3, [r3, #44] + 12959 .loc 1 4738 53 + 12960 0172 464A ldr r2, .L1007+8 + 12961 0174 1A63 str r2, [r3, #48] + ARM GAS /tmp/ccl4b9YO.s page 310 + + +4739:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the DMA channel */ +4741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, + 12962 .loc 1 4741 11 + 12963 0176 FB68 ldr r3, [r7, #12] + 12964 0178 D86A ldr r0, [r3, #44] + 12965 017a 3968 ldr r1, [r7] +4742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + 12966 .loc 1 4742 43 + 12967 017c FB68 ldr r3, [r7, #12] + 12968 017e 1B68 ldr r3, [r3] + 12969 .loc 1 4742 38 + 12970 0180 4C33 adds r3, r3, #76 +4741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + 12971 .loc 1 4741 11 + 12972 0182 1A46 mov r2, r3 + 12973 0184 7B6A ldr r3, [r7, #36] + 12974 0186 FFF7FEFF bl HAL_DMA_Start_IT + 12975 018a 0346 mov r3, r0 +4741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + 12976 .loc 1 4741 10 discriminator 1 + 12977 018c 002B cmp r3, #0 + 12978 018e 5BD0 beq .L1003 +4743:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return error status */ +4745:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 12979 .loc 1 4745 16 + 12980 0190 0123 movs r3, #1 + 12981 0192 72E0 b .L980 + 12982 .L986: +4746:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4747:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +4748:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_DMA_CC4: +4750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA compare callbacks */ +4752:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + 12983 .loc 1 4752 17 + 12984 0194 FB68 ldr r3, [r7, #12] + 12985 0196 1B6B ldr r3, [r3, #48] + 12986 .loc 1 4752 52 + 12987 0198 3D4A ldr r2, .L1007+12 + 12988 019a 9A62 str r2, [r3, #40] +4753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 12989 .loc 1 4753 17 + 12990 019c FB68 ldr r3, [r7, #12] + 12991 019e 1B6B ldr r3, [r3, #48] + 12992 .loc 1 4753 56 + 12993 01a0 3C4A ldr r2, .L1007+16 + 12994 01a2 DA62 str r2, [r3, #44] +4754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4755:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA error callback */ +4756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + 12995 .loc 1 4756 17 + 12996 01a4 FB68 ldr r3, [r7, #12] + 12997 01a6 1B6B ldr r3, [r3, #48] + 12998 .loc 1 4756 53 + ARM GAS /tmp/ccl4b9YO.s page 311 + + + 12999 01a8 384A ldr r2, .L1007+8 + 13000 01aa 1A63 str r2, [r3, #48] +4757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4758:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the DMA channel */ +4759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, + 13001 .loc 1 4759 11 + 13002 01ac FB68 ldr r3, [r7, #12] + 13003 01ae 186B ldr r0, [r3, #48] + 13004 01b0 3968 ldr r1, [r7] +4760:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + 13005 .loc 1 4760 43 + 13006 01b2 FB68 ldr r3, [r7, #12] + 13007 01b4 1B68 ldr r3, [r3] + 13008 .loc 1 4760 38 + 13009 01b6 4C33 adds r3, r3, #76 +4759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + 13010 .loc 1 4759 11 + 13011 01b8 1A46 mov r2, r3 + 13012 01ba 7B6A ldr r3, [r7, #36] + 13013 01bc FFF7FEFF bl HAL_DMA_Start_IT + 13014 01c0 0346 mov r3, r0 +4759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + 13015 .loc 1 4759 10 discriminator 1 + 13016 01c2 002B cmp r3, #0 + 13017 01c4 42D0 beq .L1004 +4761:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return error status */ +4763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 13018 .loc 1 4763 16 + 13019 01c6 0123 movs r3, #1 + 13020 01c8 57E0 b .L980 + 13021 .L985: +4764:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +4766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4767:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_DMA_COM: +4768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA commutation callbacks */ +4770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + 13022 .loc 1 4770 17 + 13023 01ca FB68 ldr r3, [r7, #12] + 13024 01cc 5B6B ldr r3, [r3, #52] + 13025 .loc 1 4770 60 + 13026 01ce 324A ldr r2, .L1007+20 + 13027 01d0 9A62 str r2, [r3, #40] +4771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + 13028 .loc 1 4771 17 + 13029 01d2 FB68 ldr r3, [r7, #12] + 13030 01d4 5B6B ldr r3, [r3, #52] + 13031 .loc 1 4771 64 + 13032 01d6 314A ldr r2, .L1007+24 + 13033 01d8 DA62 str r2, [r3, #44] +4772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA error callback */ +4774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; + 13034 .loc 1 4774 17 + 13035 01da FB68 ldr r3, [r7, #12] + ARM GAS /tmp/ccl4b9YO.s page 312 + + + 13036 01dc 5B6B ldr r3, [r3, #52] + 13037 .loc 1 4774 61 + 13038 01de 2B4A ldr r2, .L1007+8 + 13039 01e0 1A63 str r2, [r3, #48] +4775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the DMA channel */ +4777:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, + 13040 .loc 1 4777 11 + 13041 01e2 FB68 ldr r3, [r7, #12] + 13042 01e4 586B ldr r0, [r3, #52] + 13043 01e6 3968 ldr r1, [r7] +4778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + 13044 .loc 1 4778 43 + 13045 01e8 FB68 ldr r3, [r7, #12] + 13046 01ea 1B68 ldr r3, [r3] + 13047 .loc 1 4778 38 + 13048 01ec 4C33 adds r3, r3, #76 +4777:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + 13049 .loc 1 4777 11 + 13050 01ee 1A46 mov r2, r3 + 13051 01f0 7B6A ldr r3, [r7, #36] + 13052 01f2 FFF7FEFF bl HAL_DMA_Start_IT + 13053 01f6 0346 mov r3, r0 +4777:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + 13054 .loc 1 4777 10 discriminator 1 + 13055 01f8 002B cmp r3, #0 + 13056 01fa 29D0 beq .L1005 +4779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4780:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return error status */ +4781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 13057 .loc 1 4781 16 + 13058 01fc 0123 movs r3, #1 + 13059 01fe 3CE0 b .L980 + 13060 .L983: +4782:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +4784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_DMA_TRIGGER: +4786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4787:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA trigger callbacks */ +4788:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; + 13061 .loc 1 4788 17 + 13062 0200 FB68 ldr r3, [r7, #12] + 13063 0202 9B6B ldr r3, [r3, #56] + 13064 .loc 1 4788 56 + 13065 0204 264A ldr r2, .L1007+28 + 13066 0206 9A62 str r2, [r3, #40] +4789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; + 13067 .loc 1 4789 17 + 13068 0208 FB68 ldr r3, [r7, #12] + 13069 020a 9B6B ldr r3, [r3, #56] + 13070 .loc 1 4789 60 + 13071 020c 254A ldr r2, .L1007+32 + 13072 020e DA62 str r2, [r3, #44] +4790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA error callback */ +4792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; + ARM GAS /tmp/ccl4b9YO.s page 313 + + + 13073 .loc 1 4792 17 + 13074 0210 FB68 ldr r3, [r7, #12] + 13075 0212 9B6B ldr r3, [r3, #56] + 13076 .loc 1 4792 57 + 13077 0214 1D4A ldr r2, .L1007+8 + 13078 0216 1A63 str r2, [r3, #48] +4793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the DMA channel */ +4795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, + 13079 .loc 1 4795 11 + 13080 0218 FB68 ldr r3, [r7, #12] + 13081 021a 986B ldr r0, [r3, #56] + 13082 021c 3968 ldr r1, [r7] +4796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + 13083 .loc 1 4796 43 + 13084 021e FB68 ldr r3, [r7, #12] + 13085 0220 1B68 ldr r3, [r3] + 13086 .loc 1 4796 38 + 13087 0222 4C33 adds r3, r3, #76 +4795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + 13088 .loc 1 4795 11 + 13089 0224 1A46 mov r2, r3 + 13090 0226 7B6A ldr r3, [r7, #36] + 13091 0228 FFF7FEFF bl HAL_DMA_Start_IT + 13092 022c 0346 mov r3, r0 +4795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + 13093 .loc 1 4795 10 discriminator 1 + 13094 022e 002B cmp r3, #0 + 13095 0230 10D0 beq .L1006 +4797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4798:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return error status */ +4799:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 13096 .loc 1 4799 16 + 13097 0232 0123 movs r3, #1 + 13098 0234 21E0 b .L980 + 13099 .L984: +4800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +4802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4803:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** default: +4804:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** status = HAL_ERROR; + 13100 .loc 1 4804 14 + 13101 0236 0123 movs r3, #1 + 13102 0238 FB75 strb r3, [r7, #23] +4805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 13103 .loc 1 4805 7 + 13104 023a 0CE0 b .L992 + 13105 .L1000: +4693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 13106 .loc 1 4693 7 + 13107 023c 00BF nop + 13108 023e 0AE0 b .L992 + 13109 .L1001: +4711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 13110 .loc 1 4711 7 + 13111 0240 00BF nop + 13112 0242 08E0 b .L992 + ARM GAS /tmp/ccl4b9YO.s page 314 + + + 13113 .L1002: +4729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 13114 .loc 1 4729 7 + 13115 0244 00BF nop + 13116 0246 06E0 b .L992 + 13117 .L1003: +4747:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 13118 .loc 1 4747 7 + 13119 0248 00BF nop + 13120 024a 04E0 b .L992 + 13121 .L1004: +4765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 13122 .loc 1 4765 7 + 13123 024c 00BF nop + 13124 024e 02E0 b .L992 + 13125 .L1005: +4783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 13126 .loc 1 4783 7 + 13127 0250 00BF nop + 13128 0252 00E0 b .L992 + 13129 .L1006: +4801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 13130 .loc 1 4801 7 + 13131 0254 00BF nop + 13132 .L992: +4806:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4807:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4808:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (status == HAL_OK) + 13133 .loc 1 4808 6 + 13134 0256 FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 13135 0258 002B cmp r3, #0 + 13136 025a 0DD1 bne .L999 +4809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Configure the DMA Burst Mode */ +4811:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->DCR = (BurstBaseAddress | BurstLength); + 13137 .loc 1 4811 9 + 13138 025c FB68 ldr r3, [r7, #12] + 13139 025e 1B68 ldr r3, [r3] + 13140 .loc 1 4811 45 + 13141 0260 B968 ldr r1, [r7, #8] + 13142 0262 3A6A ldr r2, [r7, #32] + 13143 0264 0A43 orrs r2, r2, r1 + 13144 .loc 1 4811 25 + 13145 0266 9A64 str r2, [r3, #72] +4812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the TIM DMA Request */ +4813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + 13146 .loc 1 4813 5 + 13147 0268 FB68 ldr r3, [r7, #12] + 13148 026a 1B68 ldr r3, [r3] + 13149 026c D968 ldr r1, [r3, #12] + 13150 026e FB68 ldr r3, [r7, #12] + 13151 0270 1B68 ldr r3, [r3] + 13152 0272 7A68 ldr r2, [r7, #4] + 13153 0274 0A43 orrs r2, r2, r1 + 13154 0276 DA60 str r2, [r3, #12] + 13155 .L999: +4814:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + ARM GAS /tmp/ccl4b9YO.s page 315 + + +4815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return function status */ +4817:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return status; + 13156 .loc 1 4817 10 + 13157 0278 FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 13158 .L980: +4818:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 13159 .loc 1 4818 1 + 13160 027a 1846 mov r0, r3 + 13161 027c 1837 adds r7, r7, #24 + 13162 .cfi_def_cfa_offset 8 + 13163 027e BD46 mov sp, r7 + 13164 .cfi_def_cfa_register 13 + 13165 @ sp needed + 13166 0280 80BD pop {r7, pc} + 13167 .L1008: + 13168 0282 00BF .align 2 + 13169 .L1007: + 13170 0284 00000000 .word TIM_DMAPeriodElapsedCplt + 13171 0288 00000000 .word TIM_DMAPeriodElapsedHalfCplt + 13172 028c 00000000 .word TIM_DMAError + 13173 0290 00000000 .word TIM_DMADelayPulseCplt + 13174 0294 00000000 .word TIM_DMADelayPulseHalfCplt + 13175 0298 00000000 .word TIMEx_DMACommutationCplt + 13176 029c 00000000 .word TIMEx_DMACommutationHalfCplt + 13177 02a0 00000000 .word TIM_DMATriggerCplt + 13178 02a4 00000000 .word TIM_DMATriggerHalfCplt + 13179 .cfi_endproc + 13180 .LFE194: + 13182 .section .text.HAL_TIM_DMABurst_WriteStop,"ax",%progbits + 13183 .align 1 + 13184 .global HAL_TIM_DMABurst_WriteStop + 13185 .syntax unified + 13186 .thumb + 13187 .thumb_func + 13189 HAL_TIM_DMABurst_WriteStop: + 13190 .LFB195: +4819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4820:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +4821:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Stops the TIM DMA Burst mode +4822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM handle +4823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param BurstRequestSrc TIM DMA Request sources to disable +4824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status +4825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +4826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) +4827:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 13191 .loc 1 4827 1 + 13192 .cfi_startproc + 13193 @ args = 0, pretend = 0, frame = 16 + 13194 @ frame_needed = 1, uses_anonymous_args = 0 + 13195 0000 80B5 push {r7, lr} + 13196 .cfi_def_cfa_offset 8 + 13197 .cfi_offset 7, -8 + 13198 .cfi_offset 14, -4 + 13199 0002 84B0 sub sp, sp, #16 + 13200 .cfi_def_cfa_offset 24 + 13201 0004 00AF add r7, sp, #0 + ARM GAS /tmp/ccl4b9YO.s page 316 + + + 13202 .cfi_def_cfa_register 7 + 13203 0006 7860 str r0, [r7, #4] + 13204 0008 3960 str r1, [r7] +4828:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 13205 .loc 1 4828 21 + 13206 000a 0023 movs r3, #0 + 13207 000c FB73 strb r3, [r7, #15] +4829:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4830:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +4831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); +4832:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Abort the DMA transfer (at least disable the DMA channel) */ +4834:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** switch (BurstRequestSrc) + 13208 .loc 1 4834 3 + 13209 000e 3B68 ldr r3, [r7] + 13210 0010 B3F5804F cmp r3, #16384 + 13211 0014 50D0 beq .L1010 + 13212 0016 3B68 ldr r3, [r7] + 13213 0018 B3F5804F cmp r3, #16384 + 13214 001c 52D8 bhi .L1011 + 13215 001e 3B68 ldr r3, [r7] + 13216 0020 B3F5005F cmp r3, #8192 + 13217 0024 42D0 beq .L1012 + 13218 0026 3B68 ldr r3, [r7] + 13219 0028 B3F5005F cmp r3, #8192 + 13220 002c 4AD8 bhi .L1011 + 13221 002e 3B68 ldr r3, [r7] + 13222 0030 B3F5805F cmp r3, #4096 + 13223 0034 34D0 beq .L1013 + 13224 0036 3B68 ldr r3, [r7] + 13225 0038 B3F5805F cmp r3, #4096 + 13226 003c 42D8 bhi .L1011 + 13227 003e 3B68 ldr r3, [r7] + 13228 0040 B3F5006F cmp r3, #2048 + 13229 0044 26D0 beq .L1014 + 13230 0046 3B68 ldr r3, [r7] + 13231 0048 B3F5006F cmp r3, #2048 + 13232 004c 3AD8 bhi .L1011 + 13233 004e 3B68 ldr r3, [r7] + 13234 0050 B3F5806F cmp r3, #1024 + 13235 0054 18D0 beq .L1015 + 13236 0056 3B68 ldr r3, [r7] + 13237 0058 B3F5806F cmp r3, #1024 + 13238 005c 32D8 bhi .L1011 + 13239 005e 3B68 ldr r3, [r7] + 13240 0060 B3F5807F cmp r3, #256 + 13241 0064 04D0 beq .L1016 + 13242 0066 3B68 ldr r3, [r7] + 13243 0068 B3F5007F cmp r3, #512 + 13244 006c 06D0 beq .L1017 + 13245 006e 29E0 b .L1011 + 13246 .L1016: +4835:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4836:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_DMA_UPDATE: +4837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + 13247 .loc 1 4838 13 + ARM GAS /tmp/ccl4b9YO.s page 317 + + + 13248 0070 7B68 ldr r3, [r7, #4] + 13249 0072 1B6A ldr r3, [r3, #32] + 13250 0074 1846 mov r0, r3 + 13251 0076 FFF7FEFF bl HAL_DMA_Abort_IT +4839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 13252 .loc 1 4839 7 + 13253 007a 26E0 b .L1018 + 13254 .L1017: +4840:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_DMA_CC1: +4842:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4843:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + 13255 .loc 1 4843 13 + 13256 007c 7B68 ldr r3, [r7, #4] + 13257 007e 5B6A ldr r3, [r3, #36] + 13258 0080 1846 mov r0, r3 + 13259 0082 FFF7FEFF bl HAL_DMA_Abort_IT +4844:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 13260 .loc 1 4844 7 + 13261 0086 20E0 b .L1018 + 13262 .L1015: +4845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4846:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_DMA_CC2: +4847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + 13263 .loc 1 4848 13 + 13264 0088 7B68 ldr r3, [r7, #4] + 13265 008a 9B6A ldr r3, [r3, #40] + 13266 008c 1846 mov r0, r3 + 13267 008e FFF7FEFF bl HAL_DMA_Abort_IT +4849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 13268 .loc 1 4849 7 + 13269 0092 1AE0 b .L1018 + 13270 .L1014: +4850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4851:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_DMA_CC3: +4852:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4853:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + 13271 .loc 1 4853 13 + 13272 0094 7B68 ldr r3, [r7, #4] + 13273 0096 DB6A ldr r3, [r3, #44] + 13274 0098 1846 mov r0, r3 + 13275 009a FFF7FEFF bl HAL_DMA_Abort_IT +4854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 13276 .loc 1 4854 7 + 13277 009e 14E0 b .L1018 + 13278 .L1013: +4855:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4856:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_DMA_CC4: +4857:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + 13279 .loc 1 4858 13 + 13280 00a0 7B68 ldr r3, [r7, #4] + 13281 00a2 1B6B ldr r3, [r3, #48] + 13282 00a4 1846 mov r0, r3 + 13283 00a6 FFF7FEFF bl HAL_DMA_Abort_IT +4859:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + ARM GAS /tmp/ccl4b9YO.s page 318 + + + 13284 .loc 1 4859 7 + 13285 00aa 0EE0 b .L1018 + 13286 .L1012: +4860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_DMA_COM: +4862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + 13287 .loc 1 4863 13 + 13288 00ac 7B68 ldr r3, [r7, #4] + 13289 00ae 5B6B ldr r3, [r3, #52] + 13290 00b0 1846 mov r0, r3 + 13291 00b2 FFF7FEFF bl HAL_DMA_Abort_IT +4864:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 13292 .loc 1 4864 7 + 13293 00b6 08E0 b .L1018 + 13294 .L1010: +4865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_DMA_TRIGGER: +4867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4868:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + 13295 .loc 1 4868 13 + 13296 00b8 7B68 ldr r3, [r7, #4] + 13297 00ba 9B6B ldr r3, [r3, #56] + 13298 00bc 1846 mov r0, r3 + 13299 00be FFF7FEFF bl HAL_DMA_Abort_IT +4869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 13300 .loc 1 4869 7 + 13301 00c2 02E0 b .L1018 + 13302 .L1011: +4870:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** default: +4872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** status = HAL_ERROR; + 13303 .loc 1 4872 14 + 13304 00c4 0123 movs r3, #1 + 13305 00c6 FB73 strb r3, [r7, #15] +4873:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 13306 .loc 1 4873 7 + 13307 00c8 00BF nop + 13308 .L1018: +4874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4875:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (status == HAL_OK) + 13309 .loc 1 4876 6 + 13310 00ca FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 13311 00cc 002B cmp r3, #0 + 13312 00ce 0CD1 bne .L1019 +4877:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +4878:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the TIM Update DMA request */ +4879:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + 13313 .loc 1 4879 5 + 13314 00d0 7B68 ldr r3, [r7, #4] + 13315 00d2 1B68 ldr r3, [r3] + 13316 00d4 D968 ldr r1, [r3, #12] + 13317 00d6 3B68 ldr r3, [r7] + 13318 00d8 DA43 mvns r2, r3 + 13319 00da 7B68 ldr r3, [r7, #4] + 13320 00dc 1B68 ldr r3, [r3] + ARM GAS /tmp/ccl4b9YO.s page 319 + + + 13321 00de 0A40 ands r2, r2, r1 + 13322 00e0 DA60 str r2, [r3, #12] +4880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Change the DMA burst operation state */ +4882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + 13323 .loc 1 4882 25 + 13324 00e2 7B68 ldr r3, [r7, #4] + 13325 00e4 0122 movs r2, #1 + 13326 00e6 83F84820 strb r2, [r3, #72] + 13327 .L1019: +4883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +4884:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return function status */ +4886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return status; + 13328 .loc 1 4886 10 + 13329 00ea FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 +4887:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 13330 .loc 1 4887 1 + 13331 00ec 1846 mov r0, r3 + 13332 00ee 1037 adds r7, r7, #16 + 13333 .cfi_def_cfa_offset 8 + 13334 00f0 BD46 mov sp, r7 + 13335 .cfi_def_cfa_register 13 + 13336 @ sp needed + 13337 00f2 80BD pop {r7, pc} + 13338 .cfi_endproc + 13339 .LFE195: + 13341 .section .text.HAL_TIM_DMABurst_ReadStart,"ax",%progbits + 13342 .align 1 + 13343 .global HAL_TIM_DMABurst_ReadStart + 13344 .syntax unified + 13345 .thumb + 13346 .thumb_func + 13348 HAL_TIM_DMABurst_ReadStart: + 13349 .LFB196: +4888:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4889:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +4890:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory +4891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM handle +4892:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read +4893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +4894:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CR1 +4895:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CR2 +4896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_SMCR +4897:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_DIER +4898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_SR +4899:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_EGR +4900:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CCMR1 +4901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CCMR2 +4902:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CCER +4903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CNT +4904:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_PSC +4905:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_ARR +4906:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_RCR +4907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CCR1 +4908:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CCR2 +4909:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CCR3 + ARM GAS /tmp/ccl4b9YO.s page 320 + + +4910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CCR4 +4911:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_BDTR +4912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_OR +4913:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CCMR3 (*) +4914:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CCR5 (*) +4915:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CCR6 (*) +4916:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * (*) value not defined in all devices +4917:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param BurstRequestSrc TIM DMA Request sources +4918:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +4919:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMA_UPDATE: TIM update Interrupt source +4920:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source +4921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source +4922:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source +4923:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source +4924:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMA_COM: TIM Commutation DMA source +4925:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source +4926:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param BurstBuffer The Buffer address. +4927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param BurstLength DMA Burst length. This parameter can be one value +4928:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. +4929:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @note This function should be used only when BurstLength is equal to DMA data transfer length +4930:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status +4931:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +4932:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, +4933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint +4934:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 13350 .loc 1 4934 1 + 13351 .cfi_startproc + 13352 @ args = 4, pretend = 0, frame = 24 + 13353 @ frame_needed = 1, uses_anonymous_args = 0 + 13354 0000 80B5 push {r7, lr} + 13355 .cfi_def_cfa_offset 8 + 13356 .cfi_offset 7, -8 + 13357 .cfi_offset 14, -4 + 13358 0002 88B0 sub sp, sp, #32 + 13359 .cfi_def_cfa_offset 40 + 13360 0004 02AF add r7, sp, #8 + 13361 .cfi_def_cfa 7, 32 + 13362 0006 F860 str r0, [r7, #12] + 13363 0008 B960 str r1, [r7, #8] + 13364 000a 7A60 str r2, [r7, #4] + 13365 000c 3B60 str r3, [r7] +4935:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef status; +4936:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, Bu +4938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** ((BurstLength) >> 8U) + 1U); + 13366 .loc 1 4938 59 + 13367 000e 3B6A ldr r3, [r7, #32] + 13368 0010 1B0A lsrs r3, r3, #8 +4937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** ((BurstLength) >> 8U) + 1U); + 13369 .loc 1 4937 12 + 13370 0012 0133 adds r3, r3, #1 + 13371 0014 0193 str r3, [sp, #4] + 13372 0016 3B6A ldr r3, [r7, #32] + 13373 0018 0093 str r3, [sp] + 13374 001a 3B68 ldr r3, [r7] + 13375 001c 7A68 ldr r2, [r7, #4] + 13376 001e B968 ldr r1, [r7, #8] + ARM GAS /tmp/ccl4b9YO.s page 321 + + + 13377 0020 F868 ldr r0, [r7, #12] + 13378 0022 FFF7FEFF bl HAL_TIM_DMABurst_MultiReadStart + 13379 0026 0346 mov r3, r0 + 13380 0028 FB75 strb r3, [r7, #23] +4939:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4941:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return status; + 13381 .loc 1 4941 10 + 13382 002a FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 +4942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 13383 .loc 1 4942 1 + 13384 002c 1846 mov r0, r3 + 13385 002e 1837 adds r7, r7, #24 + 13386 .cfi_def_cfa_offset 8 + 13387 0030 BD46 mov sp, r7 + 13388 .cfi_def_cfa_register 13 + 13389 @ sp needed + 13390 0032 80BD pop {r7, pc} + 13391 .cfi_endproc + 13392 .LFE196: + 13394 .section .text.HAL_TIM_DMABurst_MultiReadStart,"ax",%progbits + 13395 .align 1 + 13396 .global HAL_TIM_DMABurst_MultiReadStart + 13397 .syntax unified + 13398 .thumb + 13399 .thumb_func + 13401 HAL_TIM_DMABurst_MultiReadStart: + 13402 .LFB197: +4943:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4944:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +4945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory +4946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM handle +4947:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read +4948:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +4949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CR1 +4950:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CR2 +4951:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_SMCR +4952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_DIER +4953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_SR +4954:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_EGR +4955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CCMR1 +4956:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CCMR2 +4957:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CCER +4958:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CNT +4959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_PSC +4960:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_ARR +4961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_RCR +4962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CCR1 +4963:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CCR2 +4964:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CCR3 +4965:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CCR4 +4966:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_BDTR +4967:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_OR +4968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CCMR3 (*) +4969:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CCR5 (*) +4970:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMABASE_CCR6 (*) +4971:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * (*) value not defined in all devices + ARM GAS /tmp/ccl4b9YO.s page 322 + + +4972:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param BurstRequestSrc TIM DMA Request sources +4973:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +4974:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMA_UPDATE: TIM update Interrupt source +4975:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source +4976:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source +4977:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source +4978:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source +4979:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMA_COM: TIM Commutation DMA source +4980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source +4981:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param BurstBuffer The Buffer address. +4982:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param BurstLength DMA Burst length. This parameter can be one value +4983:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. +4984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param DataLength Data length. This parameter can be one value +4985:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * between 1 and 0xFFFF. +4986:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status +4987:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +4988:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddres +4989:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t BurstRequestSrc, uint32_t *BurstBuffer, +4990:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t BurstLength, uint32_t DataLength) +4991:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 13403 .loc 1 4991 1 + 13404 .cfi_startproc + 13405 @ args = 8, pretend = 0, frame = 24 + 13406 @ frame_needed = 1, uses_anonymous_args = 0 + 13407 0000 80B5 push {r7, lr} + 13408 .cfi_def_cfa_offset 8 + 13409 .cfi_offset 7, -8 + 13410 .cfi_offset 14, -4 + 13411 0002 86B0 sub sp, sp, #24 + 13412 .cfi_def_cfa_offset 32 + 13413 0004 00AF add r7, sp, #0 + 13414 .cfi_def_cfa_register 7 + 13415 0006 F860 str r0, [r7, #12] + 13416 0008 B960 str r1, [r7, #8] + 13417 000a 7A60 str r2, [r7, #4] + 13418 000c 3B60 str r3, [r7] +4992:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 13419 .loc 1 4992 21 + 13420 000e 0023 movs r3, #0 + 13421 0010 FB75 strb r3, [r7, #23] +4993:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +4994:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +4995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); +4996:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); +4997:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); +4998:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_DMA_LENGTH(BurstLength)); +4999:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); +5000:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5001:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) + 13422 .loc 1 5001 11 + 13423 0012 FB68 ldr r3, [r7, #12] + 13424 0014 93F84830 ldrb r3, [r3, #72] + 13425 0018 DBB2 uxtb r3, r3 + 13426 .loc 1 5001 6 + 13427 001a 022B cmp r3, #2 + 13428 001c 01D1 bne .L1024 +5002:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + ARM GAS /tmp/ccl4b9YO.s page 323 + + +5003:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_BUSY; + 13429 .loc 1 5003 12 + 13430 001e 0223 movs r3, #2 + 13431 0020 2BE1 b .L1025 + 13432 .L1024: +5004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5005:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) + 13433 .loc 1 5005 16 + 13434 0022 FB68 ldr r3, [r7, #12] + 13435 0024 93F84830 ldrb r3, [r3, #72] + 13436 0028 DBB2 uxtb r3, r3 + 13437 .loc 1 5005 11 + 13438 002a 012B cmp r3, #1 + 13439 002c 0BD1 bne .L1026 +5006:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if ((BurstBuffer == NULL) && (BurstLength > 0U)) + 13440 .loc 1 5007 8 + 13441 002e 3B68 ldr r3, [r7] + 13442 0030 002B cmp r3, #0 + 13443 0032 04D1 bne .L1027 + 13444 .loc 1 5007 31 discriminator 1 + 13445 0034 3B6A ldr r3, [r7, #32] + 13446 0036 002B cmp r3, #0 + 13447 0038 01D0 beq .L1027 +5008:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 13448 .loc 1 5009 14 + 13449 003a 0123 movs r3, #1 + 13450 003c 1DE1 b .L1025 + 13451 .L1027: +5010:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5011:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +5012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5013:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; + 13452 .loc 1 5013 27 + 13453 003e FB68 ldr r3, [r7, #12] + 13454 0040 0222 movs r2, #2 + 13455 0042 83F84820 strb r2, [r3, #72] + 13456 .L1026: +5014:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5015:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +5017:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5018:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* nothing to do */ +5019:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** switch (BurstRequestSrc) + 13457 .loc 1 5020 3 + 13458 0046 7B68 ldr r3, [r7, #4] + 13459 0048 B3F5804F cmp r3, #16384 + 13460 004c 00F0D880 beq .L1028 + 13461 0050 7B68 ldr r3, [r7, #4] + 13462 0052 B3F5804F cmp r3, #16384 + 13463 0056 00F2EE80 bhi .L1029 + 13464 005a 7B68 ldr r3, [r7, #4] + 13465 005c B3F5005F cmp r3, #8192 + 13466 0060 00F0B380 beq .L1030 + 13467 0064 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/ccl4b9YO.s page 324 + + + 13468 0066 B3F5005F cmp r3, #8192 + 13469 006a 00F2E480 bhi .L1029 + 13470 006e 7B68 ldr r3, [r7, #4] + 13471 0070 B3F5805F cmp r3, #4096 + 13472 0074 00F08E80 beq .L1031 + 13473 0078 7B68 ldr r3, [r7, #4] + 13474 007a B3F5805F cmp r3, #4096 + 13475 007e 00F2DA80 bhi .L1029 + 13476 0082 7B68 ldr r3, [r7, #4] + 13477 0084 B3F5006F cmp r3, #2048 + 13478 0088 69D0 beq .L1032 + 13479 008a 7B68 ldr r3, [r7, #4] + 13480 008c B3F5006F cmp r3, #2048 + 13481 0090 00F2D180 bhi .L1029 + 13482 0094 7B68 ldr r3, [r7, #4] + 13483 0096 B3F5806F cmp r3, #1024 + 13484 009a 45D0 beq .L1033 + 13485 009c 7B68 ldr r3, [r7, #4] + 13486 009e B3F5806F cmp r3, #1024 + 13487 00a2 00F2C880 bhi .L1029 + 13488 00a6 7B68 ldr r3, [r7, #4] + 13489 00a8 B3F5807F cmp r3, #256 + 13490 00ac 04D0 beq .L1034 + 13491 00ae 7B68 ldr r3, [r7, #4] + 13492 00b0 B3F5007F cmp r3, #512 + 13493 00b4 1CD0 beq .L1035 + 13494 00b6 BEE0 b .L1029 + 13495 .L1034: +5021:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_DMA_UPDATE: +5023:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA Period elapsed callbacks */ +5025:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + 13496 .loc 1 5025 17 + 13497 00b8 FB68 ldr r3, [r7, #12] + 13498 00ba 1B6A ldr r3, [r3, #32] + 13499 .loc 1 5025 55 + 13500 00bc 714A ldr r2, .L1052 + 13501 00be 9A62 str r2, [r3, #40] +5026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + 13502 .loc 1 5026 17 + 13503 00c0 FB68 ldr r3, [r7, #12] + 13504 00c2 1B6A ldr r3, [r3, #32] + 13505 .loc 1 5026 59 + 13506 00c4 704A ldr r2, .L1052+4 + 13507 00c6 DA62 str r2, [r3, #44] +5027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5028:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA error callback */ +5029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + 13508 .loc 1 5029 17 + 13509 00c8 FB68 ldr r3, [r7, #12] + 13510 00ca 1B6A ldr r3, [r3, #32] + 13511 .loc 1 5029 56 + 13512 00cc 6F4A ldr r2, .L1052+8 + 13513 00ce 1A63 str r2, [r3, #48] +5030:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5031:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the DMA channel */ + ARM GAS /tmp/ccl4b9YO.s page 325 + + +5032:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_ + 13514 .loc 1 5032 11 + 13515 00d0 FB68 ldr r3, [r7, #12] + 13516 00d2 186A ldr r0, [r3, #32] + 13517 .loc 1 5032 74 + 13518 00d4 FB68 ldr r3, [r7, #12] + 13519 00d6 1B68 ldr r3, [r3] + 13520 .loc 1 5032 69 + 13521 00d8 4C33 adds r3, r3, #76 + 13522 .loc 1 5032 11 + 13523 00da 1946 mov r1, r3 + 13524 00dc 3A68 ldr r2, [r7] + 13525 00de 7B6A ldr r3, [r7, #36] + 13526 00e0 FFF7FEFF bl HAL_DMA_Start_IT + 13527 00e4 0346 mov r3, r0 + 13528 .loc 1 5032 10 discriminator 1 + 13529 00e6 002B cmp r3, #0 + 13530 00e8 00F0A880 beq .L1045 +5033:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** DataLength) != HAL_OK) +5034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5035:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return error status */ +5036:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 13531 .loc 1 5036 16 + 13532 00ec 0123 movs r3, #1 + 13533 00ee C4E0 b .L1025 + 13534 .L1035: +5037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5038:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +5039:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5040:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_DMA_CC1: +5041:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA capture callbacks */ +5043:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + 13535 .loc 1 5043 17 + 13536 00f0 FB68 ldr r3, [r7, #12] + 13537 00f2 5B6A ldr r3, [r3, #36] + 13538 .loc 1 5043 52 + 13539 00f4 664A ldr r2, .L1052+12 + 13540 00f6 9A62 str r2, [r3, #40] +5044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 13541 .loc 1 5044 17 + 13542 00f8 FB68 ldr r3, [r7, #12] + 13543 00fa 5B6A ldr r3, [r3, #36] + 13544 .loc 1 5044 56 + 13545 00fc 654A ldr r2, .L1052+16 + 13546 00fe DA62 str r2, [r3, #44] +5045:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5046:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA error callback */ +5047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + 13547 .loc 1 5047 17 + 13548 0100 FB68 ldr r3, [r7, #12] + 13549 0102 5B6A ldr r3, [r3, #36] + 13550 .loc 1 5047 53 + 13551 0104 614A ldr r2, .L1052+8 + 13552 0106 1A63 str r2, [r3, #48] +5048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5049:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the DMA channel */ + ARM GAS /tmp/ccl4b9YO.s page 326 + + +5050:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)B + 13553 .loc 1 5050 11 + 13554 0108 FB68 ldr r3, [r7, #12] + 13555 010a 586A ldr r0, [r3, #36] + 13556 .loc 1 5050 71 + 13557 010c FB68 ldr r3, [r7, #12] + 13558 010e 1B68 ldr r3, [r3] + 13559 .loc 1 5050 66 + 13560 0110 4C33 adds r3, r3, #76 + 13561 .loc 1 5050 11 + 13562 0112 1946 mov r1, r3 + 13563 0114 3A68 ldr r2, [r7] + 13564 0116 7B6A ldr r3, [r7, #36] + 13565 0118 FFF7FEFF bl HAL_DMA_Start_IT + 13566 011c 0346 mov r3, r0 + 13567 .loc 1 5050 10 discriminator 1 + 13568 011e 002B cmp r3, #0 + 13569 0120 00F08E80 beq .L1046 +5051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** DataLength) != HAL_OK) +5052:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return error status */ +5054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 13570 .loc 1 5054 16 + 13571 0124 0123 movs r3, #1 + 13572 0126 A8E0 b .L1025 + 13573 .L1033: +5055:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +5057:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_DMA_CC2: +5059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5060:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA capture callbacks */ +5061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + 13574 .loc 1 5061 17 + 13575 0128 FB68 ldr r3, [r7, #12] + 13576 012a 9B6A ldr r3, [r3, #40] + 13577 .loc 1 5061 52 + 13578 012c 584A ldr r2, .L1052+12 + 13579 012e 9A62 str r2, [r3, #40] +5062:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 13580 .loc 1 5062 17 + 13581 0130 FB68 ldr r3, [r7, #12] + 13582 0132 9B6A ldr r3, [r3, #40] + 13583 .loc 1 5062 56 + 13584 0134 574A ldr r2, .L1052+16 + 13585 0136 DA62 str r2, [r3, #44] +5063:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5064:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA error callback */ +5065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + 13586 .loc 1 5065 17 + 13587 0138 FB68 ldr r3, [r7, #12] + 13588 013a 9B6A ldr r3, [r3, #40] + 13589 .loc 1 5065 53 + 13590 013c 534A ldr r2, .L1052+8 + 13591 013e 1A63 str r2, [r3, #48] +5066:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5067:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the DMA channel */ + ARM GAS /tmp/ccl4b9YO.s page 327 + + +5068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)B + 13592 .loc 1 5068 11 + 13593 0140 FB68 ldr r3, [r7, #12] + 13594 0142 986A ldr r0, [r3, #40] + 13595 .loc 1 5068 71 + 13596 0144 FB68 ldr r3, [r7, #12] + 13597 0146 1B68 ldr r3, [r3] + 13598 .loc 1 5068 66 + 13599 0148 4C33 adds r3, r3, #76 + 13600 .loc 1 5068 11 + 13601 014a 1946 mov r1, r3 + 13602 014c 3A68 ldr r2, [r7] + 13603 014e 7B6A ldr r3, [r7, #36] + 13604 0150 FFF7FEFF bl HAL_DMA_Start_IT + 13605 0154 0346 mov r3, r0 + 13606 .loc 1 5068 10 discriminator 1 + 13607 0156 002B cmp r3, #0 + 13608 0158 74D0 beq .L1047 +5069:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** DataLength) != HAL_OK) +5070:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return error status */ +5072:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 13609 .loc 1 5072 16 + 13610 015a 0123 movs r3, #1 + 13611 015c 8DE0 b .L1025 + 13612 .L1032: +5073:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5074:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +5075:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5076:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_DMA_CC3: +5077:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5078:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA capture callbacks */ +5079:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + 13613 .loc 1 5079 17 + 13614 015e FB68 ldr r3, [r7, #12] + 13615 0160 DB6A ldr r3, [r3, #44] + 13616 .loc 1 5079 52 + 13617 0162 4B4A ldr r2, .L1052+12 + 13618 0164 9A62 str r2, [r3, #40] +5080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 13619 .loc 1 5080 17 + 13620 0166 FB68 ldr r3, [r7, #12] + 13621 0168 DB6A ldr r3, [r3, #44] + 13622 .loc 1 5080 56 + 13623 016a 4A4A ldr r2, .L1052+16 + 13624 016c DA62 str r2, [r3, #44] +5081:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA error callback */ +5083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + 13625 .loc 1 5083 17 + 13626 016e FB68 ldr r3, [r7, #12] + 13627 0170 DB6A ldr r3, [r3, #44] + 13628 .loc 1 5083 53 + 13629 0172 464A ldr r2, .L1052+8 + 13630 0174 1A63 str r2, [r3, #48] +5084:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the DMA channel */ + ARM GAS /tmp/ccl4b9YO.s page 328 + + +5086:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)B + 13631 .loc 1 5086 11 + 13632 0176 FB68 ldr r3, [r7, #12] + 13633 0178 D86A ldr r0, [r3, #44] + 13634 .loc 1 5086 71 + 13635 017a FB68 ldr r3, [r7, #12] + 13636 017c 1B68 ldr r3, [r3] + 13637 .loc 1 5086 66 + 13638 017e 4C33 adds r3, r3, #76 + 13639 .loc 1 5086 11 + 13640 0180 1946 mov r1, r3 + 13641 0182 3A68 ldr r2, [r7] + 13642 0184 7B6A ldr r3, [r7, #36] + 13643 0186 FFF7FEFF bl HAL_DMA_Start_IT + 13644 018a 0346 mov r3, r0 + 13645 .loc 1 5086 10 discriminator 1 + 13646 018c 002B cmp r3, #0 + 13647 018e 5BD0 beq .L1048 +5087:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** DataLength) != HAL_OK) +5088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5089:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return error status */ +5090:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 13648 .loc 1 5090 16 + 13649 0190 0123 movs r3, #1 + 13650 0192 72E0 b .L1025 + 13651 .L1031: +5091:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5092:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +5093:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5094:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_DMA_CC4: +5095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5096:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA capture callbacks */ +5097:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + 13652 .loc 1 5097 17 + 13653 0194 FB68 ldr r3, [r7, #12] + 13654 0196 1B6B ldr r3, [r3, #48] + 13655 .loc 1 5097 52 + 13656 0198 3D4A ldr r2, .L1052+12 + 13657 019a 9A62 str r2, [r3, #40] +5098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 13658 .loc 1 5098 17 + 13659 019c FB68 ldr r3, [r7, #12] + 13660 019e 1B6B ldr r3, [r3, #48] + 13661 .loc 1 5098 56 + 13662 01a0 3C4A ldr r2, .L1052+16 + 13663 01a2 DA62 str r2, [r3, #44] +5099:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA error callback */ +5101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + 13664 .loc 1 5101 17 + 13665 01a4 FB68 ldr r3, [r7, #12] + 13666 01a6 1B6B ldr r3, [r3, #48] + 13667 .loc 1 5101 53 + 13668 01a8 384A ldr r2, .L1052+8 + 13669 01aa 1A63 str r2, [r3, #48] +5102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the DMA channel */ + ARM GAS /tmp/ccl4b9YO.s page 329 + + +5104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)B + 13670 .loc 1 5104 11 + 13671 01ac FB68 ldr r3, [r7, #12] + 13672 01ae 186B ldr r0, [r3, #48] + 13673 .loc 1 5104 71 + 13674 01b0 FB68 ldr r3, [r7, #12] + 13675 01b2 1B68 ldr r3, [r3] + 13676 .loc 1 5104 66 + 13677 01b4 4C33 adds r3, r3, #76 + 13678 .loc 1 5104 11 + 13679 01b6 1946 mov r1, r3 + 13680 01b8 3A68 ldr r2, [r7] + 13681 01ba 7B6A ldr r3, [r7, #36] + 13682 01bc FFF7FEFF bl HAL_DMA_Start_IT + 13683 01c0 0346 mov r3, r0 + 13684 .loc 1 5104 10 discriminator 1 + 13685 01c2 002B cmp r3, #0 + 13686 01c4 42D0 beq .L1049 +5105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** DataLength) != HAL_OK) +5106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return error status */ +5108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 13687 .loc 1 5108 16 + 13688 01c6 0123 movs r3, #1 + 13689 01c8 57E0 b .L1025 + 13690 .L1030: +5109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +5111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_DMA_COM: +5113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA commutation callbacks */ +5115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + 13691 .loc 1 5115 17 + 13692 01ca FB68 ldr r3, [r7, #12] + 13693 01cc 5B6B ldr r3, [r3, #52] + 13694 .loc 1 5115 60 + 13695 01ce 324A ldr r2, .L1052+20 + 13696 01d0 9A62 str r2, [r3, #40] +5116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + 13697 .loc 1 5116 17 + 13698 01d2 FB68 ldr r3, [r7, #12] + 13699 01d4 5B6B ldr r3, [r3, #52] + 13700 .loc 1 5116 64 + 13701 01d6 314A ldr r2, .L1052+24 + 13702 01d8 DA62 str r2, [r3, #44] +5117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA error callback */ +5119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; + 13703 .loc 1 5119 17 + 13704 01da FB68 ldr r3, [r7, #12] + 13705 01dc 5B6B ldr r3, [r3, #52] + 13706 .loc 1 5119 61 + 13707 01de 2B4A ldr r2, .L1052+8 + 13708 01e0 1A63 str r2, [r3, #48] +5120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the DMA channel */ + ARM GAS /tmp/ccl4b9YO.s page 330 + + +5122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (ui + 13709 .loc 1 5122 11 + 13710 01e2 FB68 ldr r3, [r7, #12] + 13711 01e4 586B ldr r0, [r3, #52] + 13712 .loc 1 5122 79 + 13713 01e6 FB68 ldr r3, [r7, #12] + 13714 01e8 1B68 ldr r3, [r3] + 13715 .loc 1 5122 74 + 13716 01ea 4C33 adds r3, r3, #76 + 13717 .loc 1 5122 11 + 13718 01ec 1946 mov r1, r3 + 13719 01ee 3A68 ldr r2, [r7] + 13720 01f0 7B6A ldr r3, [r7, #36] + 13721 01f2 FFF7FEFF bl HAL_DMA_Start_IT + 13722 01f6 0346 mov r3, r0 + 13723 .loc 1 5122 10 discriminator 1 + 13724 01f8 002B cmp r3, #0 + 13725 01fa 29D0 beq .L1050 +5123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** DataLength) != HAL_OK) +5124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return error status */ +5126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 13726 .loc 1 5126 16 + 13727 01fc 0123 movs r3, #1 + 13728 01fe 3CE0 b .L1025 + 13729 .L1028: +5127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +5129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_DMA_TRIGGER: +5131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA trigger callbacks */ +5133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; + 13730 .loc 1 5133 17 + 13731 0200 FB68 ldr r3, [r7, #12] + 13732 0202 9B6B ldr r3, [r3, #56] + 13733 .loc 1 5133 56 + 13734 0204 264A ldr r2, .L1052+28 + 13735 0206 9A62 str r2, [r3, #40] +5134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; + 13736 .loc 1 5134 17 + 13737 0208 FB68 ldr r3, [r7, #12] + 13738 020a 9B6B ldr r3, [r3, #56] + 13739 .loc 1 5134 60 + 13740 020c 254A ldr r2, .L1052+32 + 13741 020e DA62 str r2, [r3, #44] +5135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the DMA error callback */ +5137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; + 13742 .loc 1 5137 17 + 13743 0210 FB68 ldr r3, [r7, #12] + 13744 0212 9B6B ldr r3, [r3, #56] + 13745 .loc 1 5137 57 + 13746 0214 1D4A ldr r2, .L1052+8 + 13747 0216 1A63 str r2, [r3, #48] +5138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the DMA channel */ + ARM GAS /tmp/ccl4b9YO.s page 331 + + +5140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32 + 13748 .loc 1 5140 11 + 13749 0218 FB68 ldr r3, [r7, #12] + 13750 021a 986B ldr r0, [r3, #56] + 13751 .loc 1 5140 75 + 13752 021c FB68 ldr r3, [r7, #12] + 13753 021e 1B68 ldr r3, [r3] + 13754 .loc 1 5140 70 + 13755 0220 4C33 adds r3, r3, #76 + 13756 .loc 1 5140 11 + 13757 0222 1946 mov r1, r3 + 13758 0224 3A68 ldr r2, [r7] + 13759 0226 7B6A ldr r3, [r7, #36] + 13760 0228 FFF7FEFF bl HAL_DMA_Start_IT + 13761 022c 0346 mov r3, r0 + 13762 .loc 1 5140 10 discriminator 1 + 13763 022e 002B cmp r3, #0 + 13764 0230 10D0 beq .L1051 +5141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** DataLength) != HAL_OK) +5142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return error status */ +5144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 13765 .loc 1 5144 16 + 13766 0232 0123 movs r3, #1 + 13767 0234 21E0 b .L1025 + 13768 .L1029: +5145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +5147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** default: +5149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** status = HAL_ERROR; + 13769 .loc 1 5149 14 + 13770 0236 0123 movs r3, #1 + 13771 0238 FB75 strb r3, [r7, #23] +5150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 13772 .loc 1 5150 7 + 13773 023a 0CE0 b .L1037 + 13774 .L1045: +5038:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 13775 .loc 1 5038 7 + 13776 023c 00BF nop + 13777 023e 0AE0 b .L1037 + 13778 .L1046: +5056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 13779 .loc 1 5056 7 + 13780 0240 00BF nop + 13781 0242 08E0 b .L1037 + 13782 .L1047: +5074:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 13783 .loc 1 5074 7 + 13784 0244 00BF nop + 13785 0246 06E0 b .L1037 + 13786 .L1048: +5092:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 13787 .loc 1 5092 7 + 13788 0248 00BF nop + 13789 024a 04E0 b .L1037 + ARM GAS /tmp/ccl4b9YO.s page 332 + + + 13790 .L1049: +5110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 13791 .loc 1 5110 7 + 13792 024c 00BF nop + 13793 024e 02E0 b .L1037 + 13794 .L1050: +5128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 13795 .loc 1 5128 7 + 13796 0250 00BF nop + 13797 0252 00E0 b .L1037 + 13798 .L1051: +5146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 13799 .loc 1 5146 7 + 13800 0254 00BF nop + 13801 .L1037: +5151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (status == HAL_OK) + 13802 .loc 1 5153 6 + 13803 0256 FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 13804 0258 002B cmp r3, #0 + 13805 025a 0DD1 bne .L1044 +5154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Configure the DMA Burst Mode */ +5156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->DCR = (BurstBaseAddress | BurstLength); + 13806 .loc 1 5156 9 + 13807 025c FB68 ldr r3, [r7, #12] + 13808 025e 1B68 ldr r3, [r3] + 13809 .loc 1 5156 45 + 13810 0260 B968 ldr r1, [r7, #8] + 13811 0262 3A6A ldr r2, [r7, #32] + 13812 0264 0A43 orrs r2, r2, r1 + 13813 .loc 1 5156 25 + 13814 0266 9A64 str r2, [r3, #72] +5157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the TIM DMA Request */ +5159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + 13815 .loc 1 5159 5 + 13816 0268 FB68 ldr r3, [r7, #12] + 13817 026a 1B68 ldr r3, [r3] + 13818 026c D968 ldr r1, [r3, #12] + 13819 026e FB68 ldr r3, [r7, #12] + 13820 0270 1B68 ldr r3, [r3] + 13821 0272 7A68 ldr r2, [r7, #4] + 13822 0274 0A43 orrs r2, r2, r1 + 13823 0276 DA60 str r2, [r3, #12] + 13824 .L1044: +5160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return function status */ +5163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return status; + 13825 .loc 1 5163 10 + 13826 0278 FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 13827 .L1025: +5164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 13828 .loc 1 5164 1 + 13829 027a 1846 mov r0, r3 + ARM GAS /tmp/ccl4b9YO.s page 333 + + + 13830 027c 1837 adds r7, r7, #24 + 13831 .cfi_def_cfa_offset 8 + 13832 027e BD46 mov sp, r7 + 13833 .cfi_def_cfa_register 13 + 13834 @ sp needed + 13835 0280 80BD pop {r7, pc} + 13836 .L1053: + 13837 0282 00BF .align 2 + 13838 .L1052: + 13839 0284 00000000 .word TIM_DMAPeriodElapsedCplt + 13840 0288 00000000 .word TIM_DMAPeriodElapsedHalfCplt + 13841 028c 00000000 .word TIM_DMAError + 13842 0290 00000000 .word TIM_DMACaptureCplt + 13843 0294 00000000 .word TIM_DMACaptureHalfCplt + 13844 0298 00000000 .word TIMEx_DMACommutationCplt + 13845 029c 00000000 .word TIMEx_DMACommutationHalfCplt + 13846 02a0 00000000 .word TIM_DMATriggerCplt + 13847 02a4 00000000 .word TIM_DMATriggerHalfCplt + 13848 .cfi_endproc + 13849 .LFE197: + 13851 .section .text.HAL_TIM_DMABurst_ReadStop,"ax",%progbits + 13852 .align 1 + 13853 .global HAL_TIM_DMABurst_ReadStop + 13854 .syntax unified + 13855 .thumb + 13856 .thumb_func + 13858 HAL_TIM_DMABurst_ReadStop: + 13859 .LFB198: +5165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +5167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Stop the DMA burst reading +5168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM handle +5169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param BurstRequestSrc TIM DMA Request sources to disable. +5170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status +5171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +5172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) +5173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 13860 .loc 1 5173 1 + 13861 .cfi_startproc + 13862 @ args = 0, pretend = 0, frame = 16 + 13863 @ frame_needed = 1, uses_anonymous_args = 0 + 13864 0000 80B5 push {r7, lr} + 13865 .cfi_def_cfa_offset 8 + 13866 .cfi_offset 7, -8 + 13867 .cfi_offset 14, -4 + 13868 0002 84B0 sub sp, sp, #16 + 13869 .cfi_def_cfa_offset 24 + 13870 0004 00AF add r7, sp, #0 + 13871 .cfi_def_cfa_register 7 + 13872 0006 7860 str r0, [r7, #4] + 13873 0008 3960 str r1, [r7] +5174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 13874 .loc 1 5174 21 + 13875 000a 0023 movs r3, #0 + 13876 000c FB73 strb r3, [r7, #15] +5175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ + ARM GAS /tmp/ccl4b9YO.s page 334 + + +5177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); +5178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Abort the DMA transfer (at least disable the DMA channel) */ +5180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** switch (BurstRequestSrc) + 13877 .loc 1 5180 3 + 13878 000e 3B68 ldr r3, [r7] + 13879 0010 B3F5804F cmp r3, #16384 + 13880 0014 50D0 beq .L1055 + 13881 0016 3B68 ldr r3, [r7] + 13882 0018 B3F5804F cmp r3, #16384 + 13883 001c 52D8 bhi .L1056 + 13884 001e 3B68 ldr r3, [r7] + 13885 0020 B3F5005F cmp r3, #8192 + 13886 0024 42D0 beq .L1057 + 13887 0026 3B68 ldr r3, [r7] + 13888 0028 B3F5005F cmp r3, #8192 + 13889 002c 4AD8 bhi .L1056 + 13890 002e 3B68 ldr r3, [r7] + 13891 0030 B3F5805F cmp r3, #4096 + 13892 0034 34D0 beq .L1058 + 13893 0036 3B68 ldr r3, [r7] + 13894 0038 B3F5805F cmp r3, #4096 + 13895 003c 42D8 bhi .L1056 + 13896 003e 3B68 ldr r3, [r7] + 13897 0040 B3F5006F cmp r3, #2048 + 13898 0044 26D0 beq .L1059 + 13899 0046 3B68 ldr r3, [r7] + 13900 0048 B3F5006F cmp r3, #2048 + 13901 004c 3AD8 bhi .L1056 + 13902 004e 3B68 ldr r3, [r7] + 13903 0050 B3F5806F cmp r3, #1024 + 13904 0054 18D0 beq .L1060 + 13905 0056 3B68 ldr r3, [r7] + 13906 0058 B3F5806F cmp r3, #1024 + 13907 005c 32D8 bhi .L1056 + 13908 005e 3B68 ldr r3, [r7] + 13909 0060 B3F5807F cmp r3, #256 + 13910 0064 04D0 beq .L1061 + 13911 0066 3B68 ldr r3, [r7] + 13912 0068 B3F5007F cmp r3, #512 + 13913 006c 06D0 beq .L1062 + 13914 006e 29E0 b .L1056 + 13915 .L1061: +5181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_DMA_UPDATE: +5183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + 13916 .loc 1 5184 13 + 13917 0070 7B68 ldr r3, [r7, #4] + 13918 0072 1B6A ldr r3, [r3, #32] + 13919 0074 1846 mov r0, r3 + 13920 0076 FFF7FEFF bl HAL_DMA_Abort_IT +5185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 13921 .loc 1 5185 7 + 13922 007a 26E0 b .L1063 + 13923 .L1062: +5186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + ARM GAS /tmp/ccl4b9YO.s page 335 + + +5187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_DMA_CC1: +5188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + 13924 .loc 1 5189 13 + 13925 007c 7B68 ldr r3, [r7, #4] + 13926 007e 5B6A ldr r3, [r3, #36] + 13927 0080 1846 mov r0, r3 + 13928 0082 FFF7FEFF bl HAL_DMA_Abort_IT +5190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 13929 .loc 1 5190 7 + 13930 0086 20E0 b .L1063 + 13931 .L1060: +5191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_DMA_CC2: +5193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + 13932 .loc 1 5194 13 + 13933 0088 7B68 ldr r3, [r7, #4] + 13934 008a 9B6A ldr r3, [r3, #40] + 13935 008c 1846 mov r0, r3 + 13936 008e FFF7FEFF bl HAL_DMA_Abort_IT +5195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 13937 .loc 1 5195 7 + 13938 0092 1AE0 b .L1063 + 13939 .L1059: +5196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_DMA_CC3: +5198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + 13940 .loc 1 5199 13 + 13941 0094 7B68 ldr r3, [r7, #4] + 13942 0096 DB6A ldr r3, [r3, #44] + 13943 0098 1846 mov r0, r3 + 13944 009a FFF7FEFF bl HAL_DMA_Abort_IT +5200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 13945 .loc 1 5200 7 + 13946 009e 14E0 b .L1063 + 13947 .L1058: +5201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_DMA_CC4: +5203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + 13948 .loc 1 5204 13 + 13949 00a0 7B68 ldr r3, [r7, #4] + 13950 00a2 1B6B ldr r3, [r3, #48] + 13951 00a4 1846 mov r0, r3 + 13952 00a6 FFF7FEFF bl HAL_DMA_Abort_IT +5205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 13953 .loc 1 5205 7 + 13954 00aa 0EE0 b .L1063 + 13955 .L1057: +5206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_DMA_COM: +5208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + 13956 .loc 1 5209 13 + 13957 00ac 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/ccl4b9YO.s page 336 + + + 13958 00ae 5B6B ldr r3, [r3, #52] + 13959 00b0 1846 mov r0, r3 + 13960 00b2 FFF7FEFF bl HAL_DMA_Abort_IT +5210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 13961 .loc 1 5210 7 + 13962 00b6 08E0 b .L1063 + 13963 .L1055: +5211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_DMA_TRIGGER: +5213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + 13964 .loc 1 5214 13 + 13965 00b8 7B68 ldr r3, [r7, #4] + 13966 00ba 9B6B ldr r3, [r3, #56] + 13967 00bc 1846 mov r0, r3 + 13968 00be FFF7FEFF bl HAL_DMA_Abort_IT +5215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 13969 .loc 1 5215 7 + 13970 00c2 02E0 b .L1063 + 13971 .L1056: +5216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** default: +5218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** status = HAL_ERROR; + 13972 .loc 1 5218 14 + 13973 00c4 0123 movs r3, #1 + 13974 00c6 FB73 strb r3, [r7, #15] +5219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 13975 .loc 1 5219 7 + 13976 00c8 00BF nop + 13977 .L1063: +5220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (status == HAL_OK) + 13978 .loc 1 5222 6 + 13979 00ca FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 13980 00cc 002B cmp r3, #0 + 13981 00ce 0CD1 bne .L1064 +5223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the TIM Update DMA request */ +5225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + 13982 .loc 1 5225 5 + 13983 00d0 7B68 ldr r3, [r7, #4] + 13984 00d2 1B68 ldr r3, [r3] + 13985 00d4 D968 ldr r1, [r3, #12] + 13986 00d6 3B68 ldr r3, [r7] + 13987 00d8 DA43 mvns r2, r3 + 13988 00da 7B68 ldr r3, [r7, #4] + 13989 00dc 1B68 ldr r3, [r3] + 13990 00de 0A40 ands r2, r2, r1 + 13991 00e0 DA60 str r2, [r3, #12] +5226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Change the DMA burst operation state */ +5228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + 13992 .loc 1 5228 25 + 13993 00e2 7B68 ldr r3, [r7, #4] + 13994 00e4 0122 movs r2, #1 + 13995 00e6 83F84820 strb r2, [r3, #72] + ARM GAS /tmp/ccl4b9YO.s page 337 + + + 13996 .L1064: +5229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return function status */ +5232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return status; + 13997 .loc 1 5232 10 + 13998 00ea FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 +5233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 13999 .loc 1 5233 1 + 14000 00ec 1846 mov r0, r3 + 14001 00ee 1037 adds r7, r7, #16 + 14002 .cfi_def_cfa_offset 8 + 14003 00f0 BD46 mov sp, r7 + 14004 .cfi_def_cfa_register 13 + 14005 @ sp needed + 14006 00f2 80BD pop {r7, pc} + 14007 .cfi_endproc + 14008 .LFE198: + 14010 .section .text.HAL_TIM_GenerateEvent,"ax",%progbits + 14011 .align 1 + 14012 .global HAL_TIM_GenerateEvent + 14013 .syntax unified + 14014 .thumb + 14015 .thumb_func + 14017 HAL_TIM_GenerateEvent: + 14018 .LFB199: +5234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +5236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Generate a software event +5237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM handle +5238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param EventSource specifies the event source. +5239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +5240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source +5241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source +5242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source +5243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source +5244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source +5245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_EVENTSOURCE_COM: Timer COM event source +5246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source +5247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source +5248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source +5249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @note Basic timers can only generate an update event. +5250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances. +5251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @note TIM_EVENTSOURCE_BREAK are relevant only for timer instances +5252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * supporting a break input. +5253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status +5254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +5255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) +5257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 14019 .loc 1 5257 1 + 14020 .cfi_startproc + 14021 @ args = 0, pretend = 0, frame = 8 + 14022 @ frame_needed = 1, uses_anonymous_args = 0 + 14023 @ link register save eliminated. + 14024 0000 80B4 push {r7} + 14025 .cfi_def_cfa_offset 4 + ARM GAS /tmp/ccl4b9YO.s page 338 + + + 14026 .cfi_offset 7, -4 + 14027 0002 83B0 sub sp, sp, #12 + 14028 .cfi_def_cfa_offset 16 + 14029 0004 00AF add r7, sp, #0 + 14030 .cfi_def_cfa_register 7 + 14031 0006 7860 str r0, [r7, #4] + 14032 0008 3960 str r1, [r7] +5258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +5259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_INSTANCE(htim->Instance)); +5260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_EVENT_SOURCE(EventSource)); +5261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Process Locked */ +5263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_LOCK(htim); + 14033 .loc 1 5263 3 + 14034 000a 7B68 ldr r3, [r7, #4] + 14035 000c 93F83C30 ldrb r3, [r3, #60] @ zero_extendqisi2 + 14036 0010 012B cmp r3, #1 + 14037 0012 01D1 bne .L1067 + 14038 .loc 1 5263 3 is_stmt 0 discriminator 1 + 14039 0014 0223 movs r3, #2 + 14040 .loc 1 5263 3 + 14041 0016 14E0 b .L1068 + 14042 .L1067: + 14043 .loc 1 5263 3 discriminator 2 + 14044 0018 7B68 ldr r3, [r7, #4] + 14045 001a 0122 movs r2, #1 + 14046 001c 83F83C20 strb r2, [r3, #60] +5264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Change the TIM state */ +5266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; + 14047 .loc 1 5266 15 is_stmt 1 + 14048 0020 7B68 ldr r3, [r7, #4] + 14049 0022 0222 movs r2, #2 + 14050 0024 83F83D20 strb r2, [r3, #61] +5267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the event sources */ +5269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->EGR = EventSource; + 14051 .loc 1 5269 7 + 14052 0028 7B68 ldr r3, [r7, #4] + 14053 002a 1B68 ldr r3, [r3] + 14054 .loc 1 5269 23 + 14055 002c 3A68 ldr r2, [r7] + 14056 002e 5A61 str r2, [r3, #20] +5270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Change the TIM state */ +5272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; + 14057 .loc 1 5272 15 + 14058 0030 7B68 ldr r3, [r7, #4] + 14059 0032 0122 movs r2, #1 + 14060 0034 83F83D20 strb r2, [r3, #61] +5273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_UNLOCK(htim); + 14061 .loc 1 5274 3 + 14062 0038 7B68 ldr r3, [r7, #4] + 14063 003a 0022 movs r2, #0 + 14064 003c 83F83C20 strb r2, [r3, #60] +5275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + ARM GAS /tmp/ccl4b9YO.s page 339 + + +5276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return function status */ +5277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_OK; + 14065 .loc 1 5277 10 + 14066 0040 0023 movs r3, #0 + 14067 .L1068: +5278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 14068 .loc 1 5278 1 + 14069 0042 1846 mov r0, r3 + 14070 0044 0C37 adds r7, r7, #12 + 14071 .cfi_def_cfa_offset 4 + 14072 0046 BD46 mov sp, r7 + 14073 .cfi_def_cfa_register 13 + 14074 @ sp needed + 14075 0048 5DF8047B ldr r7, [sp], #4 + 14076 .cfi_restore 7 + 14077 .cfi_def_cfa_offset 0 + 14078 004c 7047 bx lr + 14079 .cfi_endproc + 14080 .LFE199: + 14082 .section .text.HAL_TIM_ConfigOCrefClear,"ax",%progbits + 14083 .align 1 + 14084 .global HAL_TIM_ConfigOCrefClear + 14085 .syntax unified + 14086 .thumb + 14087 .thumb_func + 14089 HAL_TIM_ConfigOCrefClear: + 14090 .LFB200: +5279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +5281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Configures the OCRef clear feature +5282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM handle +5283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that +5284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * contains the OCREF clear feature and parameters for the TIM peripheral. +5285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param Channel specifies the TIM Channel +5286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +5287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 +5288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 +5289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 +5290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 +5291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_5: TIM Channel 5 (*) +5292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_6: TIM Channel 6 (*) +5293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * (*) Value not defined for all devices +5294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status +5295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +5296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, +5297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** const TIM_ClearInputConfigTypeDef *sClearInputConfig, +5298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t Channel) +5299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 14091 .loc 1 5299 1 + 14092 .cfi_startproc + 14093 @ args = 0, pretend = 0, frame = 24 + 14094 @ frame_needed = 1, uses_anonymous_args = 0 + 14095 0000 80B5 push {r7, lr} + 14096 .cfi_def_cfa_offset 8 + 14097 .cfi_offset 7, -8 + 14098 .cfi_offset 14, -4 + 14099 0002 86B0 sub sp, sp, #24 + ARM GAS /tmp/ccl4b9YO.s page 340 + + + 14100 .cfi_def_cfa_offset 32 + 14101 0004 00AF add r7, sp, #0 + 14102 .cfi_def_cfa_register 7 + 14103 0006 F860 str r0, [r7, #12] + 14104 0008 B960 str r1, [r7, #8] + 14105 000a 7A60 str r2, [r7, #4] +5300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 14106 .loc 1 5300 21 + 14107 000c 0023 movs r3, #0 + 14108 000e FB75 strb r3, [r7, #23] +5301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +5303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); +5304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); +5305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Process Locked */ +5307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_LOCK(htim); + 14109 .loc 1 5307 3 + 14110 0010 FB68 ldr r3, [r7, #12] + 14111 0012 93F83C30 ldrb r3, [r3, #60] @ zero_extendqisi2 + 14112 0016 012B cmp r3, #1 + 14113 0018 01D1 bne .L1070 + 14114 .loc 1 5307 3 is_stmt 0 discriminator 1 + 14115 001a 0223 movs r3, #2 + 14116 .loc 1 5307 3 + 14117 001c 0EE1 b .L1071 + 14118 .L1070: + 14119 .loc 1 5307 3 discriminator 2 + 14120 001e FB68 ldr r3, [r7, #12] + 14121 0020 0122 movs r2, #1 + 14122 0022 83F83C20 strb r2, [r3, #60] +5308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; + 14123 .loc 1 5309 15 is_stmt 1 + 14124 0026 FB68 ldr r3, [r7, #12] + 14125 0028 0222 movs r2, #2 + 14126 002a 83F83D20 strb r2, [r3, #61] +5310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** switch (sClearInputConfig->ClearInputSource) + 14127 .loc 1 5311 28 + 14128 002e BB68 ldr r3, [r7, #8] + 14129 0030 5B68 ldr r3, [r3, #4] + 14130 .loc 1 5311 3 + 14131 0032 022B cmp r3, #2 + 14132 0034 11D0 beq .L1072 + 14133 0036 022B cmp r3, #2 + 14134 0038 39D8 bhi .L1073 + 14135 003a 002B cmp r3, #0 + 14136 003c 02D0 beq .L1074 + 14137 003e 012B cmp r3, #1 + 14138 0040 14D0 beq .L1075 + 14139 0042 34E0 b .L1073 + 14140 .L1074: +5312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CLEARINPUTSOURCE_NONE: +5314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Clear the OCREF clear selection bit and the the ETR Bits */ + ARM GAS /tmp/ccl4b9YO.s page 341 + + +5316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if defined(TIM_SMCR_OCCS) +5317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE + 14141 .loc 1 5317 7 + 14142 0044 FB68 ldr r3, [r7, #12] + 14143 0046 1B68 ldr r3, [r3] + 14144 0048 9B68 ldr r3, [r3, #8] + 14145 004a FA68 ldr r2, [r7, #12] + 14146 004c 1268 ldr r2, [r2] + 14147 004e 23F47F43 bic r3, r3, #65280 + 14148 0052 23F00803 bic r3, r3, #8 + 14149 0056 9360 str r3, [r2, #8] +5318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #else +5319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)) +5320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* TIM_SMCR_OCCS */ +5321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 14150 .loc 1 5321 7 + 14151 0058 2CE0 b .L1076 + 14152 .L1072: +5322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if defined(TIM_SMCR_OCCS) +5324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CLEARINPUTSOURCE_OCREFCLR: +5325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Clear the OCREF clear selection bit */ +5327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); + 14153 .loc 1 5327 7 + 14154 005a FB68 ldr r3, [r7, #12] + 14155 005c 1B68 ldr r3, [r3] + 14156 005e 9A68 ldr r2, [r3, #8] + 14157 0060 FB68 ldr r3, [r7, #12] + 14158 0062 1B68 ldr r3, [r3] + 14159 0064 22F00802 bic r2, r2, #8 + 14160 0068 9A60 str r2, [r3, #8] +5328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 14161 .loc 1 5328 7 + 14162 006a 23E0 b .L1076 + 14163 .L1075: +5329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* TIM_SMCR_OCCS */ +5331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CLEARINPUTSOURCE_ETR: +5333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +5335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); +5336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); +5337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); +5338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */ +5340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1) + 14164 .loc 1 5340 28 + 14165 006c BB68 ldr r3, [r7, #8] + 14166 006e DB68 ldr r3, [r3, #12] + 14167 .loc 1 5340 10 + 14168 0070 002B cmp r3, #0 + 14169 0072 09D0 beq .L1077 +5341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; + 14170 .loc 1 5342 21 + ARM GAS /tmp/ccl4b9YO.s page 342 + + + 14171 0074 FB68 ldr r3, [r7, #12] + 14172 0076 0122 movs r2, #1 + 14173 0078 83F83D20 strb r2, [r3, #61] +5343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_UNLOCK(htim); + 14174 .loc 1 5343 9 + 14175 007c FB68 ldr r3, [r7, #12] + 14176 007e 0022 movs r2, #0 + 14177 0080 83F83C20 strb r2, [r3, #60] +5344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 14178 .loc 1 5344 16 + 14179 0084 0123 movs r3, #1 + 14180 0086 D9E0 b .L1071 + 14181 .L1077: +5345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_ETR_SetConfig(htim->Instance, + 14182 .loc 1 5347 7 + 14183 0088 FB68 ldr r3, [r7, #12] + 14184 008a 1868 ldr r0, [r3] +5348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** sClearInputConfig->ClearInputPrescaler, + 14185 .loc 1 5348 42 + 14186 008c BB68 ldr r3, [r7, #8] + 14187 008e D968 ldr r1, [r3, #12] +5349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** sClearInputConfig->ClearInputPolarity, + 14188 .loc 1 5349 42 + 14189 0090 BB68 ldr r3, [r7, #8] + 14190 0092 9A68 ldr r2, [r3, #8] +5350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** sClearInputConfig->ClearInputFilter); + 14191 .loc 1 5350 42 + 14192 0094 BB68 ldr r3, [r7, #8] + 14193 0096 1B69 ldr r3, [r3, #16] +5347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** sClearInputConfig->ClearInputPrescaler, + 14194 .loc 1 5347 7 + 14195 0098 FFF7FEFF bl TIM_ETR_SetConfig +5351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if defined(TIM_SMCR_OCCS) +5352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the OCREF clear selection bit */ +5354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); + 14196 .loc 1 5354 7 + 14197 009c FB68 ldr r3, [r7, #12] + 14198 009e 1B68 ldr r3, [r3] + 14199 00a0 9A68 ldr r2, [r3, #8] + 14200 00a2 FB68 ldr r3, [r7, #12] + 14201 00a4 1B68 ldr r3, [r3] + 14202 00a6 42F00802 orr r2, r2, #8 + 14203 00aa 9A60 str r2, [r3, #8] +5355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* TIM_SMCR_OCCS */ +5356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 14204 .loc 1 5356 7 + 14205 00ac 02E0 b .L1076 + 14206 .L1073: +5357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** default: +5360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** status = HAL_ERROR; + 14207 .loc 1 5360 14 + 14208 00ae 0123 movs r3, #1 + ARM GAS /tmp/ccl4b9YO.s page 343 + + + 14209 00b0 FB75 strb r3, [r7, #23] +5361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 14210 .loc 1 5361 7 + 14211 00b2 00BF nop + 14212 .L1076: +5362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (status == HAL_OK) + 14213 .loc 1 5364 6 + 14214 00b4 FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 14215 00b6 002B cmp r3, #0 + 14216 00b8 40F0B780 bne .L1078 +5365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** switch (Channel) + 14217 .loc 1 5366 5 + 14218 00bc 7B68 ldr r3, [r7, #4] + 14219 00be 142B cmp r3, #20 + 14220 00c0 00F2B280 bhi .L1099 + 14221 00c4 01A2 adr r2, .L1081 + 14222 00c6 52F823F0 ldr pc, [r2, r3, lsl #2] + 14223 00ca 00BF .p2align 2 + 14224 .L1081: + 14225 00cc 21010000 .word .L1086+1 + 14226 00d0 29020000 .word .L1099+1 + 14227 00d4 29020000 .word .L1099+1 + 14228 00d8 29020000 .word .L1099+1 + 14229 00dc 4D010000 .word .L1085+1 + 14230 00e0 29020000 .word .L1099+1 + 14231 00e4 29020000 .word .L1099+1 + 14232 00e8 29020000 .word .L1099+1 + 14233 00ec 79010000 .word .L1084+1 + 14234 00f0 29020000 .word .L1099+1 + 14235 00f4 29020000 .word .L1099+1 + 14236 00f8 29020000 .word .L1099+1 + 14237 00fc A5010000 .word .L1083+1 + 14238 0100 29020000 .word .L1099+1 + 14239 0104 29020000 .word .L1099+1 + 14240 0108 29020000 .word .L1099+1 + 14241 010c D1010000 .word .L1082+1 + 14242 0110 29020000 .word .L1099+1 + 14243 0114 29020000 .word .L1099+1 + 14244 0118 29020000 .word .L1099+1 + 14245 011c FD010000 .word .L1080+1 + 14246 .p2align 1 + 14247 .L1086: +5367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_1: +5369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + 14248 .loc 1 5370 30 + 14249 0120 BB68 ldr r3, [r7, #8] + 14250 0122 1B68 ldr r3, [r3] + 14251 .loc 1 5370 12 + 14252 0124 002B cmp r3, #0 + 14253 0126 08D0 beq .L1087 +5371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the OCREF clear feature for Channel 1 */ + ARM GAS /tmp/ccl4b9YO.s page 344 + + +5373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + 14254 .loc 1 5373 11 + 14255 0128 FB68 ldr r3, [r7, #12] + 14256 012a 1B68 ldr r3, [r3] + 14257 012c 9A69 ldr r2, [r3, #24] + 14258 012e FB68 ldr r3, [r7, #12] + 14259 0130 1B68 ldr r3, [r3] + 14260 0132 42F08002 orr r2, r2, #128 + 14261 0136 9A61 str r2, [r3, #24] +5374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +5376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the OCREF clear feature for Channel 1 */ +5378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); +5379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 14262 .loc 1 5380 9 + 14263 0138 77E0 b .L1078 + 14264 .L1087: +5378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 14265 .loc 1 5378 11 + 14266 013a FB68 ldr r3, [r7, #12] + 14267 013c 1B68 ldr r3, [r3] + 14268 013e 9A69 ldr r2, [r3, #24] + 14269 0140 FB68 ldr r3, [r7, #12] + 14270 0142 1B68 ldr r3, [r3] + 14271 0144 22F08002 bic r2, r2, #128 + 14272 0148 9A61 str r2, [r3, #24] + 14273 .loc 1 5380 9 + 14274 014a 6EE0 b .L1078 + 14275 .L1085: +5381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_2: +5383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + 14276 .loc 1 5384 30 + 14277 014c BB68 ldr r3, [r7, #8] + 14278 014e 1B68 ldr r3, [r3] + 14279 .loc 1 5384 12 + 14280 0150 002B cmp r3, #0 + 14281 0152 08D0 beq .L1089 +5385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the OCREF clear feature for Channel 2 */ +5387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + 14282 .loc 1 5387 11 + 14283 0154 FB68 ldr r3, [r7, #12] + 14284 0156 1B68 ldr r3, [r3] + 14285 0158 9A69 ldr r2, [r3, #24] + 14286 015a FB68 ldr r3, [r7, #12] + 14287 015c 1B68 ldr r3, [r3] + 14288 015e 42F40042 orr r2, r2, #32768 + 14289 0162 9A61 str r2, [r3, #24] +5388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +5390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the OCREF clear feature for Channel 2 */ +5392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + ARM GAS /tmp/ccl4b9YO.s page 345 + + +5393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 14290 .loc 1 5394 9 + 14291 0164 61E0 b .L1078 + 14292 .L1089: +5392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 14293 .loc 1 5392 11 + 14294 0166 FB68 ldr r3, [r7, #12] + 14295 0168 1B68 ldr r3, [r3] + 14296 016a 9A69 ldr r2, [r3, #24] + 14297 016c FB68 ldr r3, [r7, #12] + 14298 016e 1B68 ldr r3, [r3] + 14299 0170 22F40042 bic r2, r2, #32768 + 14300 0174 9A61 str r2, [r3, #24] + 14301 .loc 1 5394 9 + 14302 0176 58E0 b .L1078 + 14303 .L1084: +5395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_3: +5397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + 14304 .loc 1 5398 30 + 14305 0178 BB68 ldr r3, [r7, #8] + 14306 017a 1B68 ldr r3, [r3] + 14307 .loc 1 5398 12 + 14308 017c 002B cmp r3, #0 + 14309 017e 08D0 beq .L1091 +5399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the OCREF clear feature for Channel 3 */ +5401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + 14310 .loc 1 5401 11 + 14311 0180 FB68 ldr r3, [r7, #12] + 14312 0182 1B68 ldr r3, [r3] + 14313 0184 DA69 ldr r2, [r3, #28] + 14314 0186 FB68 ldr r3, [r7, #12] + 14315 0188 1B68 ldr r3, [r3] + 14316 018a 42F08002 orr r2, r2, #128 + 14317 018e DA61 str r2, [r3, #28] +5402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +5404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the OCREF clear feature for Channel 3 */ +5406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); +5407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 14318 .loc 1 5408 9 + 14319 0190 4BE0 b .L1078 + 14320 .L1091: +5406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 14321 .loc 1 5406 11 + 14322 0192 FB68 ldr r3, [r7, #12] + 14323 0194 1B68 ldr r3, [r3] + 14324 0196 DA69 ldr r2, [r3, #28] + 14325 0198 FB68 ldr r3, [r7, #12] + 14326 019a 1B68 ldr r3, [r3] + 14327 019c 22F08002 bic r2, r2, #128 + 14328 01a0 DA61 str r2, [r3, #28] + ARM GAS /tmp/ccl4b9YO.s page 346 + + + 14329 .loc 1 5408 9 + 14330 01a2 42E0 b .L1078 + 14331 .L1083: +5409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_4: +5411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + 14332 .loc 1 5412 30 + 14333 01a4 BB68 ldr r3, [r7, #8] + 14334 01a6 1B68 ldr r3, [r3] + 14335 .loc 1 5412 12 + 14336 01a8 002B cmp r3, #0 + 14337 01aa 08D0 beq .L1093 +5413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the OCREF clear feature for Channel 4 */ +5415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + 14338 .loc 1 5415 11 + 14339 01ac FB68 ldr r3, [r7, #12] + 14340 01ae 1B68 ldr r3, [r3] + 14341 01b0 DA69 ldr r2, [r3, #28] + 14342 01b2 FB68 ldr r3, [r7, #12] + 14343 01b4 1B68 ldr r3, [r3] + 14344 01b6 42F40042 orr r2, r2, #32768 + 14345 01ba DA61 str r2, [r3, #28] +5416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +5418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the OCREF clear feature for Channel 4 */ +5420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); +5421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 14346 .loc 1 5422 9 + 14347 01bc 35E0 b .L1078 + 14348 .L1093: +5420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 14349 .loc 1 5420 11 + 14350 01be FB68 ldr r3, [r7, #12] + 14351 01c0 1B68 ldr r3, [r3] + 14352 01c2 DA69 ldr r2, [r3, #28] + 14353 01c4 FB68 ldr r3, [r7, #12] + 14354 01c6 1B68 ldr r3, [r3] + 14355 01c8 22F40042 bic r2, r2, #32768 + 14356 01cc DA61 str r2, [r3, #28] + 14357 .loc 1 5422 9 + 14358 01ce 2CE0 b .L1078 + 14359 .L1082: +5423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if defined(TIM_CCER_CC5E) +5425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_5: +5426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + 14360 .loc 1 5427 30 + 14361 01d0 BB68 ldr r3, [r7, #8] + 14362 01d2 1B68 ldr r3, [r3] + 14363 .loc 1 5427 12 + 14364 01d4 002B cmp r3, #0 + 14365 01d6 08D0 beq .L1095 + ARM GAS /tmp/ccl4b9YO.s page 347 + + +5428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the OCREF clear feature for Channel 5 */ +5430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); + 14366 .loc 1 5430 11 + 14367 01d8 FB68 ldr r3, [r7, #12] + 14368 01da 1B68 ldr r3, [r3] + 14369 01dc 5A6D ldr r2, [r3, #84] + 14370 01de FB68 ldr r3, [r7, #12] + 14371 01e0 1B68 ldr r3, [r3] + 14372 01e2 42F08002 orr r2, r2, #128 + 14373 01e6 5A65 str r2, [r3, #84] +5431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +5433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the OCREF clear feature for Channel 5 */ +5435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); +5436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 14374 .loc 1 5437 9 + 14375 01e8 1FE0 b .L1078 + 14376 .L1095: +5435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 14377 .loc 1 5435 11 + 14378 01ea FB68 ldr r3, [r7, #12] + 14379 01ec 1B68 ldr r3, [r3] + 14380 01ee 5A6D ldr r2, [r3, #84] + 14381 01f0 FB68 ldr r3, [r7, #12] + 14382 01f2 1B68 ldr r3, [r3] + 14383 01f4 22F08002 bic r2, r2, #128 + 14384 01f8 5A65 str r2, [r3, #84] + 14385 .loc 1 5437 9 + 14386 01fa 16E0 b .L1078 + 14387 .L1080: +5438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* TIM_CCER_CC5E */ +5440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if defined(TIM_CCER_CC6E) +5441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_6: +5442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + 14388 .loc 1 5443 30 + 14389 01fc BB68 ldr r3, [r7, #8] + 14390 01fe 1B68 ldr r3, [r3] + 14391 .loc 1 5443 12 + 14392 0200 002B cmp r3, #0 + 14393 0202 08D0 beq .L1097 +5444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the OCREF clear feature for Channel 6 */ +5446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); + 14394 .loc 1 5446 11 + 14395 0204 FB68 ldr r3, [r7, #12] + 14396 0206 1B68 ldr r3, [r3] + 14397 0208 5A6D ldr r2, [r3, #84] + 14398 020a FB68 ldr r3, [r7, #12] + 14399 020c 1B68 ldr r3, [r3] + 14400 020e 42F40042 orr r2, r2, #32768 + 14401 0212 5A65 str r2, [r3, #84] +5447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + ARM GAS /tmp/ccl4b9YO.s page 348 + + +5448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +5449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the OCREF clear feature for Channel 6 */ +5451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); +5452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 14402 .loc 1 5453 9 + 14403 0214 09E0 b .L1078 + 14404 .L1097: +5451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 14405 .loc 1 5451 11 + 14406 0216 FB68 ldr r3, [r7, #12] + 14407 0218 1B68 ldr r3, [r3] + 14408 021a 5A6D ldr r2, [r3, #84] + 14409 021c FB68 ldr r3, [r7, #12] + 14410 021e 1B68 ldr r3, [r3] + 14411 0220 22F40042 bic r2, r2, #32768 + 14412 0224 5A65 str r2, [r3, #84] + 14413 .loc 1 5453 9 + 14414 0226 00E0 b .L1078 + 14415 .L1099: +5454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* TIM_CCER_CC6E */ +5456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** default: +5457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 14416 .loc 1 5457 9 + 14417 0228 00BF nop + 14418 .L1078: +5458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; + 14419 .loc 1 5461 15 + 14420 022a FB68 ldr r3, [r7, #12] + 14421 022c 0122 movs r2, #1 + 14422 022e 83F83D20 strb r2, [r3, #61] +5462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_UNLOCK(htim); + 14423 .loc 1 5463 3 + 14424 0232 FB68 ldr r3, [r7, #12] + 14425 0234 0022 movs r2, #0 + 14426 0236 83F83C20 strb r2, [r3, #60] +5464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return status; + 14427 .loc 1 5465 10 + 14428 023a FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 14429 .L1071: +5466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 14430 .loc 1 5466 1 + 14431 023c 1846 mov r0, r3 + 14432 023e 1837 adds r7, r7, #24 + 14433 .cfi_def_cfa_offset 8 + 14434 0240 BD46 mov sp, r7 + 14435 .cfi_def_cfa_register 13 + 14436 @ sp needed + 14437 0242 80BD pop {r7, pc} + 14438 .cfi_endproc + ARM GAS /tmp/ccl4b9YO.s page 349 + + + 14439 .LFE200: + 14441 .section .text.HAL_TIM_ConfigClockSource,"ax",%progbits + 14442 .align 1 + 14443 .global HAL_TIM_ConfigClockSource + 14444 .syntax unified + 14445 .thumb + 14446 .thumb_func + 14448 HAL_TIM_ConfigClockSource: + 14449 .LFB201: +5467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +5469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Configures the clock source to be used +5470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM handle +5471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that +5472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * contains the clock source information for the TIM peripheral. +5473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status +5474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +5475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef * +5476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 14450 .loc 1 5476 1 + 14451 .cfi_startproc + 14452 @ args = 0, pretend = 0, frame = 16 + 14453 @ frame_needed = 1, uses_anonymous_args = 0 + 14454 0000 80B5 push {r7, lr} + 14455 .cfi_def_cfa_offset 8 + 14456 .cfi_offset 7, -8 + 14457 .cfi_offset 14, -4 + 14458 0002 84B0 sub sp, sp, #16 + 14459 .cfi_def_cfa_offset 24 + 14460 0004 00AF add r7, sp, #0 + 14461 .cfi_def_cfa_register 7 + 14462 0006 7860 str r0, [r7, #4] + 14463 0008 3960 str r1, [r7] +5477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 14464 .loc 1 5477 21 + 14465 000a 0023 movs r3, #0 + 14466 000c FB73 strb r3, [r7, #15] +5478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpsmcr; +5479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Process Locked */ +5481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_LOCK(htim); + 14467 .loc 1 5481 3 + 14468 000e 7B68 ldr r3, [r7, #4] + 14469 0010 93F83C30 ldrb r3, [r3, #60] @ zero_extendqisi2 + 14470 0014 012B cmp r3, #1 + 14471 0016 01D1 bne .L1101 + 14472 .loc 1 5481 3 is_stmt 0 discriminator 1 + 14473 0018 0223 movs r3, #2 + 14474 .loc 1 5481 3 + 14475 001a B6E0 b .L1102 + 14476 .L1101: + 14477 .loc 1 5481 3 discriminator 2 + 14478 001c 7B68 ldr r3, [r7, #4] + 14479 001e 0122 movs r2, #1 + 14480 0020 83F83C20 strb r2, [r3, #60] +5482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; + ARM GAS /tmp/ccl4b9YO.s page 350 + + + 14481 .loc 1 5483 15 is_stmt 1 + 14482 0024 7B68 ldr r3, [r7, #4] + 14483 0026 0222 movs r2, #2 + 14484 0028 83F83D20 strb r2, [r3, #61] +5484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +5486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); +5487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ +5489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpsmcr = htim->Instance->SMCR; + 14485 .loc 1 5489 17 + 14486 002c 7B68 ldr r3, [r7, #4] + 14487 002e 1B68 ldr r3, [r3] + 14488 .loc 1 5489 11 + 14489 0030 9B68 ldr r3, [r3, #8] + 14490 0032 BB60 str r3, [r7, #8] +5490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); + 14491 .loc 1 5490 11 + 14492 0034 BB68 ldr r3, [r7, #8] + 14493 0036 23F48033 bic r3, r3, #65536 + 14494 003a 23F07703 bic r3, r3, #119 + 14495 003e BB60 str r3, [r7, #8] +5491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + 14496 .loc 1 5491 11 + 14497 0040 BB68 ldr r3, [r7, #8] + 14498 0042 23F47F43 bic r3, r3, #65280 + 14499 0046 BB60 str r3, [r7, #8] +5492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->SMCR = tmpsmcr; + 14500 .loc 1 5492 7 + 14501 0048 7B68 ldr r3, [r7, #4] + 14502 004a 1B68 ldr r3, [r3] + 14503 .loc 1 5492 24 + 14504 004c BA68 ldr r2, [r7, #8] + 14505 004e 9A60 str r2, [r3, #8] +5493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** switch (sClockSourceConfig->ClockSource) + 14506 .loc 1 5494 29 + 14507 0050 3B68 ldr r3, [r7] + 14508 0052 1B68 ldr r3, [r3] + 14509 .loc 1 5494 3 + 14510 0054 B3F5005F cmp r3, #8192 + 14511 0058 3ED0 beq .L1103 + 14512 005a B3F5005F cmp r3, #8192 + 14513 005e 00F28780 bhi .L1104 + 14514 0062 B3F5805F cmp r3, #4096 + 14515 0066 00F08680 beq .L1112 + 14516 006a B3F5805F cmp r3, #4096 + 14517 006e 7FD8 bhi .L1104 + 14518 0070 702B cmp r3, #112 + 14519 0072 1AD0 beq .L1106 + 14520 0074 702B cmp r3, #112 + 14521 0076 7BD8 bhi .L1104 + 14522 0078 602B cmp r3, #96 + 14523 007a 50D0 beq .L1107 + 14524 007c 602B cmp r3, #96 + 14525 007e 77D8 bhi .L1104 + 14526 0080 502B cmp r3, #80 + ARM GAS /tmp/ccl4b9YO.s page 351 + + + 14527 0082 3CD0 beq .L1108 + 14528 0084 502B cmp r3, #80 + 14529 0086 73D8 bhi .L1104 + 14530 0088 402B cmp r3, #64 + 14531 008a 58D0 beq .L1109 + 14532 008c 402B cmp r3, #64 + 14533 008e 6FD8 bhi .L1104 + 14534 0090 302B cmp r3, #48 + 14535 0092 64D0 beq .L1110 + 14536 0094 302B cmp r3, #48 + 14537 0096 6BD8 bhi .L1104 + 14538 0098 202B cmp r3, #32 + 14539 009a 60D0 beq .L1110 + 14540 009c 202B cmp r3, #32 + 14541 009e 67D8 bhi .L1104 + 14542 00a0 002B cmp r3, #0 + 14543 00a2 5CD0 beq .L1110 + 14544 00a4 102B cmp r3, #16 + 14545 00a6 5AD0 beq .L1110 + 14546 00a8 62E0 b .L1104 + 14547 .L1106: +5495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CLOCKSOURCE_INTERNAL: +5497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_INSTANCE(htim->Instance)); +5499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +5500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CLOCKSOURCE_ETRMODE1: +5503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/ +5505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); +5506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check ETR input conditioning related parameters */ +5508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); +5509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); +5510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); +5511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Configure the ETR Clock source */ +5513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_ETR_SetConfig(htim->Instance, + 14548 .loc 1 5513 7 + 14549 00aa 7B68 ldr r3, [r7, #4] + 14550 00ac 1868 ldr r0, [r3] +5514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** sClockSourceConfig->ClockPrescaler, + 14551 .loc 1 5514 43 + 14552 00ae 3B68 ldr r3, [r7] + 14553 00b0 9968 ldr r1, [r3, #8] +5515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** sClockSourceConfig->ClockPolarity, + 14554 .loc 1 5515 43 + 14555 00b2 3B68 ldr r3, [r7] + 14556 00b4 5A68 ldr r2, [r3, #4] +5516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** sClockSourceConfig->ClockFilter); + 14557 .loc 1 5516 43 + 14558 00b6 3B68 ldr r3, [r7] + 14559 00b8 DB68 ldr r3, [r3, #12] +5513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** sClockSourceConfig->ClockPrescaler, + 14560 .loc 1 5513 7 + ARM GAS /tmp/ccl4b9YO.s page 352 + + + 14561 00ba FFF7FEFF bl TIM_ETR_SetConfig +5517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Select the External clock mode1 and the ETRF trigger */ +5519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpsmcr = htim->Instance->SMCR; + 14562 .loc 1 5519 21 + 14563 00be 7B68 ldr r3, [r7, #4] + 14564 00c0 1B68 ldr r3, [r3] + 14565 .loc 1 5519 15 + 14566 00c2 9B68 ldr r3, [r3, #8] + 14567 00c4 BB60 str r3, [r7, #8] +5520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); + 14568 .loc 1 5520 15 + 14569 00c6 BB68 ldr r3, [r7, #8] + 14570 00c8 43F07703 orr r3, r3, #119 + 14571 00cc BB60 str r3, [r7, #8] +5521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Write to TIMx SMCR */ +5522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->SMCR = tmpsmcr; + 14572 .loc 1 5522 11 + 14573 00ce 7B68 ldr r3, [r7, #4] + 14574 00d0 1B68 ldr r3, [r3] + 14575 .loc 1 5522 28 + 14576 00d2 BA68 ldr r2, [r7, #8] + 14577 00d4 9A60 str r2, [r3, #8] +5523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 14578 .loc 1 5523 7 + 14579 00d6 4FE0 b .L1111 + 14580 .L1103: +5524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CLOCKSOURCE_ETRMODE2: +5527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/ +5529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance)); +5530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check ETR input conditioning related parameters */ +5532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); +5533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); +5534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); +5535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Configure the ETR Clock source */ +5537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_ETR_SetConfig(htim->Instance, + 14581 .loc 1 5537 7 + 14582 00d8 7B68 ldr r3, [r7, #4] + 14583 00da 1868 ldr r0, [r3] +5538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** sClockSourceConfig->ClockPrescaler, + 14584 .loc 1 5538 43 + 14585 00dc 3B68 ldr r3, [r7] + 14586 00de 9968 ldr r1, [r3, #8] +5539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** sClockSourceConfig->ClockPolarity, + 14587 .loc 1 5539 43 + 14588 00e0 3B68 ldr r3, [r7] + 14589 00e2 5A68 ldr r2, [r3, #4] +5540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** sClockSourceConfig->ClockFilter); + 14590 .loc 1 5540 43 + 14591 00e4 3B68 ldr r3, [r7] + 14592 00e6 DB68 ldr r3, [r3, #12] +5537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** sClockSourceConfig->ClockPrescaler, + ARM GAS /tmp/ccl4b9YO.s page 353 + + + 14593 .loc 1 5537 7 + 14594 00e8 FFF7FEFF bl TIM_ETR_SetConfig +5541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable the External clock mode2 */ +5542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->SMCR |= TIM_SMCR_ECE; + 14595 .loc 1 5542 11 + 14596 00ec 7B68 ldr r3, [r7, #4] + 14597 00ee 1B68 ldr r3, [r3] + 14598 .loc 1 5542 21 + 14599 00f0 9A68 ldr r2, [r3, #8] + 14600 .loc 1 5542 11 + 14601 00f2 7B68 ldr r3, [r7, #4] + 14602 00f4 1B68 ldr r3, [r3] + 14603 .loc 1 5542 28 + 14604 00f6 42F48042 orr r2, r2, #16384 + 14605 00fa 9A60 str r2, [r3, #8] +5543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 14606 .loc 1 5543 7 + 14607 00fc 3CE0 b .L1111 + 14608 .L1108: +5544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CLOCKSOURCE_TI1: +5547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check whether or not the timer instance supports external clock mode 1 */ +5549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); +5550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check TI1 input conditioning related parameters */ +5552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); +5553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); +5554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_TI1_ConfigInputStage(htim->Instance, + 14609 .loc 1 5555 7 + 14610 00fe 7B68 ldr r3, [r7, #4] + 14611 0100 1868 ldr r0, [r3] +5556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** sClockSourceConfig->ClockPolarity, + 14612 .loc 1 5556 50 + 14613 0102 3B68 ldr r3, [r7] + 14614 0104 5968 ldr r1, [r3, #4] +5557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** sClockSourceConfig->ClockFilter); + 14615 .loc 1 5557 50 + 14616 0106 3B68 ldr r3, [r7] + 14617 0108 DB68 ldr r3, [r3, #12] +5555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** sClockSourceConfig->ClockPolarity, + 14618 .loc 1 5555 7 + 14619 010a 1A46 mov r2, r3 + 14620 010c FFF7FEFF bl TIM_TI1_ConfigInputStage +5558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); + 14621 .loc 1 5558 7 + 14622 0110 7B68 ldr r3, [r7, #4] + 14623 0112 1B68 ldr r3, [r3] + 14624 0114 5021 movs r1, #80 + 14625 0116 1846 mov r0, r3 + 14626 0118 FFF7FEFF bl TIM_ITRx_SetConfig +5559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 14627 .loc 1 5559 7 + 14628 011c 2CE0 b .L1111 + 14629 .L1107: + ARM GAS /tmp/ccl4b9YO.s page 354 + + +5560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CLOCKSOURCE_TI2: +5563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/ +5565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); +5566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check TI2 input conditioning related parameters */ +5568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); +5569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); +5570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_TI2_ConfigInputStage(htim->Instance, + 14630 .loc 1 5571 7 + 14631 011e 7B68 ldr r3, [r7, #4] + 14632 0120 1868 ldr r0, [r3] +5572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** sClockSourceConfig->ClockPolarity, + 14633 .loc 1 5572 50 + 14634 0122 3B68 ldr r3, [r7] + 14635 0124 5968 ldr r1, [r3, #4] +5573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** sClockSourceConfig->ClockFilter); + 14636 .loc 1 5573 50 + 14637 0126 3B68 ldr r3, [r7] + 14638 0128 DB68 ldr r3, [r3, #12] +5571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** sClockSourceConfig->ClockPolarity, + 14639 .loc 1 5571 7 + 14640 012a 1A46 mov r2, r3 + 14641 012c FFF7FEFF bl TIM_TI2_ConfigInputStage +5574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); + 14642 .loc 1 5574 7 + 14643 0130 7B68 ldr r3, [r7, #4] + 14644 0132 1B68 ldr r3, [r3] + 14645 0134 6021 movs r1, #96 + 14646 0136 1846 mov r0, r3 + 14647 0138 FFF7FEFF bl TIM_ITRx_SetConfig +5575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 14648 .loc 1 5575 7 + 14649 013c 1CE0 b .L1111 + 14650 .L1109: +5576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CLOCKSOURCE_TI1ED: +5579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check whether or not the timer instance supports external clock mode 1 */ +5581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); +5582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check TI1 input conditioning related parameters */ +5584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); +5585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); +5586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_TI1_ConfigInputStage(htim->Instance, + 14651 .loc 1 5587 7 + 14652 013e 7B68 ldr r3, [r7, #4] + 14653 0140 1868 ldr r0, [r3] +5588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** sClockSourceConfig->ClockPolarity, + 14654 .loc 1 5588 50 + 14655 0142 3B68 ldr r3, [r7] + 14656 0144 5968 ldr r1, [r3, #4] + ARM GAS /tmp/ccl4b9YO.s page 355 + + +5589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** sClockSourceConfig->ClockFilter); + 14657 .loc 1 5589 50 + 14658 0146 3B68 ldr r3, [r7] + 14659 0148 DB68 ldr r3, [r3, #12] +5587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** sClockSourceConfig->ClockPolarity, + 14660 .loc 1 5587 7 + 14661 014a 1A46 mov r2, r3 + 14662 014c FFF7FEFF bl TIM_TI1_ConfigInputStage +5590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); + 14663 .loc 1 5590 7 + 14664 0150 7B68 ldr r3, [r7, #4] + 14665 0152 1B68 ldr r3, [r3] + 14666 0154 4021 movs r1, #64 + 14667 0156 1846 mov r0, r3 + 14668 0158 FFF7FEFF bl TIM_ITRx_SetConfig +5591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 14669 .loc 1 5591 7 + 14670 015c 0CE0 b .L1111 + 14671 .L1110: +5592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CLOCKSOURCE_ITR0: +5595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CLOCKSOURCE_ITR1: +5596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CLOCKSOURCE_ITR2: +5597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CLOCKSOURCE_ITR3: +5598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check whether or not the timer instance supports internal trigger input */ +5600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); +5601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5602:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); + 14672 .loc 1 5602 7 + 14673 015e 7B68 ldr r3, [r7, #4] + 14674 0160 1A68 ldr r2, [r3] + 14675 .loc 1 5602 60 + 14676 0162 3B68 ldr r3, [r7] + 14677 0164 1B68 ldr r3, [r3] + 14678 .loc 1 5602 7 + 14679 0166 1946 mov r1, r3 + 14680 0168 1046 mov r0, r2 + 14681 016a FFF7FEFF bl TIM_ITRx_SetConfig +5603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 14682 .loc 1 5603 7 + 14683 016e 03E0 b .L1111 + 14684 .L1104: +5604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** default: +5607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** status = HAL_ERROR; + 14685 .loc 1 5607 14 + 14686 0170 0123 movs r3, #1 + 14687 0172 FB73 strb r3, [r7, #15] +5608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 14688 .loc 1 5608 7 + 14689 0174 00E0 b .L1111 + 14690 .L1112: +5499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 14691 .loc 1 5499 7 + ARM GAS /tmp/ccl4b9YO.s page 356 + + + 14692 0176 00BF nop + 14693 .L1111: +5609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; + 14694 .loc 1 5610 15 + 14695 0178 7B68 ldr r3, [r7, #4] + 14696 017a 0122 movs r2, #1 + 14697 017c 83F83D20 strb r2, [r3, #61] +5611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5612:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_UNLOCK(htim); + 14698 .loc 1 5612 3 + 14699 0180 7B68 ldr r3, [r7, #4] + 14700 0182 0022 movs r2, #0 + 14701 0184 83F83C20 strb r2, [r3, #60] +5613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return status; + 14702 .loc 1 5614 10 + 14703 0188 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 14704 .L1102: +5615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 14705 .loc 1 5615 1 + 14706 018a 1846 mov r0, r3 + 14707 018c 1037 adds r7, r7, #16 + 14708 .cfi_def_cfa_offset 8 + 14709 018e BD46 mov sp, r7 + 14710 .cfi_def_cfa_register 13 + 14711 @ sp needed + 14712 0190 80BD pop {r7, pc} + 14713 .cfi_endproc + 14714 .LFE201: + 14716 .section .text.HAL_TIM_ConfigTI1Input,"ax",%progbits + 14717 .align 1 + 14718 .global HAL_TIM_ConfigTI1Input + 14719 .syntax unified + 14720 .thumb + 14721 .thumb_func + 14723 HAL_TIM_ConfigTI1Input: + 14724 .LFB202: +5616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +5618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Selects the signal connected to the TI1 input: direct from CH1_input +5619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * or a XOR combination between CH1_input, CH2_input & CH3_input +5620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM handle. +5621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param TI1_Selection Indicate whether or not channel 1 is connected to the +5622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * output of a XOR gate. +5623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +5624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input +5625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 +5626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * pins are connected to the TI1 input (XOR combination) +5627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status +5628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +5629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) +5630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 14725 .loc 1 5630 1 + 14726 .cfi_startproc + 14727 @ args = 0, pretend = 0, frame = 16 + 14728 @ frame_needed = 1, uses_anonymous_args = 0 + ARM GAS /tmp/ccl4b9YO.s page 357 + + + 14729 @ link register save eliminated. + 14730 0000 80B4 push {r7} + 14731 .cfi_def_cfa_offset 4 + 14732 .cfi_offset 7, -4 + 14733 0002 85B0 sub sp, sp, #20 + 14734 .cfi_def_cfa_offset 24 + 14735 0004 00AF add r7, sp, #0 + 14736 .cfi_def_cfa_register 7 + 14737 0006 7860 str r0, [r7, #4] + 14738 0008 3960 str r1, [r7] +5631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpcr2; +5632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +5634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); +5635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_TI1SELECTION(TI1_Selection)); +5636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Get the TIMx CR2 register value */ +5638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpcr2 = htim->Instance->CR2; + 14739 .loc 1 5638 16 + 14740 000a 7B68 ldr r3, [r7, #4] + 14741 000c 1B68 ldr r3, [r3] + 14742 .loc 1 5638 10 + 14743 000e 5B68 ldr r3, [r3, #4] + 14744 0010 FB60 str r3, [r7, #12] +5639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Reset the TI1 selection */ +5641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpcr2 &= ~TIM_CR2_TI1S; + 14745 .loc 1 5641 10 + 14746 0012 FB68 ldr r3, [r7, #12] + 14747 0014 23F08003 bic r3, r3, #128 + 14748 0018 FB60 str r3, [r7, #12] +5642:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the TI1 selection */ +5644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpcr2 |= TI1_Selection; + 14749 .loc 1 5644 10 + 14750 001a FA68 ldr r2, [r7, #12] + 14751 001c 3B68 ldr r3, [r7] + 14752 001e 1343 orrs r3, r3, r2 + 14753 0020 FB60 str r3, [r7, #12] +5645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Write to TIMxCR2 */ +5647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->CR2 = tmpcr2; + 14754 .loc 1 5647 7 + 14755 0022 7B68 ldr r3, [r7, #4] + 14756 0024 1B68 ldr r3, [r3] + 14757 .loc 1 5647 23 + 14758 0026 FA68 ldr r2, [r7, #12] + 14759 0028 5A60 str r2, [r3, #4] +5648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_OK; + 14760 .loc 1 5649 10 + 14761 002a 0023 movs r3, #0 +5650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 14762 .loc 1 5650 1 + 14763 002c 1846 mov r0, r3 + 14764 002e 1437 adds r7, r7, #20 + 14765 .cfi_def_cfa_offset 4 + ARM GAS /tmp/ccl4b9YO.s page 358 + + + 14766 0030 BD46 mov sp, r7 + 14767 .cfi_def_cfa_register 13 + 14768 @ sp needed + 14769 0032 5DF8047B ldr r7, [sp], #4 + 14770 .cfi_restore 7 + 14771 .cfi_def_cfa_offset 0 + 14772 0036 7047 bx lr + 14773 .cfi_endproc + 14774 .LFE202: + 14776 .section .text.HAL_TIM_SlaveConfigSynchro,"ax",%progbits + 14777 .align 1 + 14778 .global HAL_TIM_SlaveConfigSynchro + 14779 .syntax unified + 14780 .thumb + 14781 .thumb_func + 14783 HAL_TIM_SlaveConfigSynchro: + 14784 .LFB203: +5651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +5653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Configures the TIM in Slave mode +5654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM handle. +5655:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that +5656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * contains the selected trigger (internal trigger input, filtered +5657:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * timer input or external trigger input) and the Slave mode +5658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * (Disable, Reset, Gated, Trigger, External clock mode 1). +5659:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status +5660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +5661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef +5662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 14785 .loc 1 5662 1 + 14786 .cfi_startproc + 14787 @ args = 0, pretend = 0, frame = 8 + 14788 @ frame_needed = 1, uses_anonymous_args = 0 + 14789 0000 80B5 push {r7, lr} + 14790 .cfi_def_cfa_offset 8 + 14791 .cfi_offset 7, -8 + 14792 .cfi_offset 14, -4 + 14793 0002 82B0 sub sp, sp, #8 + 14794 .cfi_def_cfa_offset 16 + 14795 0004 00AF add r7, sp, #0 + 14796 .cfi_def_cfa_register 7 + 14797 0006 7860 str r0, [r7, #4] + 14798 0008 3960 str r1, [r7] +5663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +5664:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); +5665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); +5666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); +5667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5668:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_LOCK(htim); + 14799 .loc 1 5668 3 + 14800 000a 7B68 ldr r3, [r7, #4] + 14801 000c 93F83C30 ldrb r3, [r3, #60] @ zero_extendqisi2 + 14802 0010 012B cmp r3, #1 + 14803 0012 01D1 bne .L1116 + 14804 .loc 1 5668 3 is_stmt 0 discriminator 1 + 14805 0014 0223 movs r3, #2 + 14806 .loc 1 5668 3 + ARM GAS /tmp/ccl4b9YO.s page 359 + + + 14807 0016 31E0 b .L1117 + 14808 .L1116: + 14809 .loc 1 5668 3 discriminator 2 + 14810 0018 7B68 ldr r3, [r7, #4] + 14811 001a 0122 movs r2, #1 + 14812 001c 83F83C20 strb r2, [r3, #60] +5669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; + 14813 .loc 1 5670 15 is_stmt 1 + 14814 0020 7B68 ldr r3, [r7, #4] + 14815 0022 0222 movs r2, #2 + 14816 0024 83F83D20 strb r2, [r3, #61] +5671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) + 14817 .loc 1 5672 7 + 14818 0028 3968 ldr r1, [r7] + 14819 002a 7868 ldr r0, [r7, #4] + 14820 002c FFF7FEFF bl TIM_SlaveTimer_SetConfig + 14821 0030 0346 mov r3, r0 + 14822 .loc 1 5672 6 discriminator 1 + 14823 0032 002B cmp r3, #0 + 14824 0034 09D0 beq .L1118 +5673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; + 14825 .loc 1 5674 17 + 14826 0036 7B68 ldr r3, [r7, #4] + 14827 0038 0122 movs r2, #1 + 14828 003a 83F83D20 strb r2, [r3, #61] +5675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_UNLOCK(htim); + 14829 .loc 1 5675 5 + 14830 003e 7B68 ldr r3, [r7, #4] + 14831 0040 0022 movs r2, #0 + 14832 0042 83F83C20 strb r2, [r3, #60] +5676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 14833 .loc 1 5676 12 + 14834 0046 0123 movs r3, #1 + 14835 0048 18E0 b .L1117 + 14836 .L1118: +5677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable Trigger Interrupt */ +5680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); + 14837 .loc 1 5680 3 + 14838 004a 7B68 ldr r3, [r7, #4] + 14839 004c 1B68 ldr r3, [r3] + 14840 004e DA68 ldr r2, [r3, #12] + 14841 0050 7B68 ldr r3, [r7, #4] + 14842 0052 1B68 ldr r3, [r3] + 14843 0054 22F04002 bic r2, r2, #64 + 14844 0058 DA60 str r2, [r3, #12] +5681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable Trigger DMA request */ +5683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); + 14845 .loc 1 5683 3 + 14846 005a 7B68 ldr r3, [r7, #4] + 14847 005c 1B68 ldr r3, [r3] + 14848 005e DA68 ldr r2, [r3, #12] + ARM GAS /tmp/ccl4b9YO.s page 360 + + + 14849 0060 7B68 ldr r3, [r7, #4] + 14850 0062 1B68 ldr r3, [r3] + 14851 0064 22F48042 bic r2, r2, #16384 + 14852 0068 DA60 str r2, [r3, #12] +5684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; + 14853 .loc 1 5685 15 + 14854 006a 7B68 ldr r3, [r7, #4] + 14855 006c 0122 movs r2, #1 + 14856 006e 83F83D20 strb r2, [r3, #61] +5686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_UNLOCK(htim); + 14857 .loc 1 5687 3 + 14858 0072 7B68 ldr r3, [r7, #4] + 14859 0074 0022 movs r2, #0 + 14860 0076 83F83C20 strb r2, [r3, #60] +5688:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_OK; + 14861 .loc 1 5689 10 + 14862 007a 0023 movs r3, #0 + 14863 .L1117: +5690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 14864 .loc 1 5690 1 + 14865 007c 1846 mov r0, r3 + 14866 007e 0837 adds r7, r7, #8 + 14867 .cfi_def_cfa_offset 8 + 14868 0080 BD46 mov sp, r7 + 14869 .cfi_def_cfa_register 13 + 14870 @ sp needed + 14871 0082 80BD pop {r7, pc} + 14872 .cfi_endproc + 14873 .LFE203: + 14875 .section .text.HAL_TIM_SlaveConfigSynchro_IT,"ax",%progbits + 14876 .align 1 + 14877 .global HAL_TIM_SlaveConfigSynchro_IT + 14878 .syntax unified + 14879 .thumb + 14880 .thumb_func + 14882 HAL_TIM_SlaveConfigSynchro_IT: + 14883 .LFB204: +5691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +5693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Configures the TIM in Slave mode in interrupt mode +5694:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM handle. +5695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that +5696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * contains the selected trigger (internal trigger input, filtered +5697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * timer input or external trigger input) and the Slave mode +5698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * (Disable, Reset, Gated, Trigger, External clock mode 1). +5699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL status +5700:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +5701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, +5702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** const TIM_SlaveConfigTypeDef *sSlaveConfig) +5703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 14884 .loc 1 5703 1 + 14885 .cfi_startproc + 14886 @ args = 0, pretend = 0, frame = 8 + 14887 @ frame_needed = 1, uses_anonymous_args = 0 + ARM GAS /tmp/ccl4b9YO.s page 361 + + + 14888 0000 80B5 push {r7, lr} + 14889 .cfi_def_cfa_offset 8 + 14890 .cfi_offset 7, -8 + 14891 .cfi_offset 14, -4 + 14892 0002 82B0 sub sp, sp, #8 + 14893 .cfi_def_cfa_offset 16 + 14894 0004 00AF add r7, sp, #0 + 14895 .cfi_def_cfa_register 7 + 14896 0006 7860 str r0, [r7, #4] + 14897 0008 3960 str r1, [r7] +5704:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +5705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); +5706:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); +5707:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); +5708:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_LOCK(htim); + 14898 .loc 1 5709 3 + 14899 000a 7B68 ldr r3, [r7, #4] + 14900 000c 93F83C30 ldrb r3, [r3, #60] @ zero_extendqisi2 + 14901 0010 012B cmp r3, #1 + 14902 0012 01D1 bne .L1120 + 14903 .loc 1 5709 3 is_stmt 0 discriminator 1 + 14904 0014 0223 movs r3, #2 + 14905 .loc 1 5709 3 + 14906 0016 31E0 b .L1121 + 14907 .L1120: + 14908 .loc 1 5709 3 discriminator 2 + 14909 0018 7B68 ldr r3, [r7, #4] + 14910 001a 0122 movs r2, #1 + 14911 001c 83F83C20 strb r2, [r3, #60] +5710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->State = HAL_TIM_STATE_BUSY; + 14912 .loc 1 5711 15 is_stmt 1 + 14913 0020 7B68 ldr r3, [r7, #4] + 14914 0022 0222 movs r2, #2 + 14915 0024 83F83D20 strb r2, [r3, #61] +5712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5713:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) + 14916 .loc 1 5713 7 + 14917 0028 3968 ldr r1, [r7] + 14918 002a 7868 ldr r0, [r7, #4] + 14919 002c FFF7FEFF bl TIM_SlaveTimer_SetConfig + 14920 0030 0346 mov r3, r0 + 14921 .loc 1 5713 6 discriminator 1 + 14922 0032 002B cmp r3, #0 + 14923 0034 09D0 beq .L1122 +5714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; + 14924 .loc 1 5715 17 + 14925 0036 7B68 ldr r3, [r7, #4] + 14926 0038 0122 movs r2, #1 + 14927 003a 83F83D20 strb r2, [r3, #61] +5716:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_UNLOCK(htim); + 14928 .loc 1 5716 5 + 14929 003e 7B68 ldr r3, [r7, #4] + 14930 0040 0022 movs r2, #0 + 14931 0042 83F83C20 strb r2, [r3, #60] + ARM GAS /tmp/ccl4b9YO.s page 362 + + +5717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 14932 .loc 1 5717 12 + 14933 0046 0123 movs r3, #1 + 14934 0048 18E0 b .L1121 + 14935 .L1122: +5718:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5720:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Enable Trigger Interrupt */ +5721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); + 14936 .loc 1 5721 3 + 14937 004a 7B68 ldr r3, [r7, #4] + 14938 004c 1B68 ldr r3, [r3] + 14939 004e DA68 ldr r2, [r3, #12] + 14940 0050 7B68 ldr r3, [r7, #4] + 14941 0052 1B68 ldr r3, [r3] + 14942 0054 42F04002 orr r2, r2, #64 + 14943 0058 DA60 str r2, [r3, #12] +5722:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5723:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable Trigger DMA request */ +5724:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); + 14944 .loc 1 5724 3 + 14945 005a 7B68 ldr r3, [r7, #4] + 14946 005c 1B68 ldr r3, [r3] + 14947 005e DA68 ldr r2, [r3, #12] + 14948 0060 7B68 ldr r3, [r7, #4] + 14949 0062 1B68 ldr r3, [r3] + 14950 0064 22F48042 bic r2, r2, #16384 + 14951 0068 DA60 str r2, [r3, #12] +5725:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; + 14952 .loc 1 5726 15 + 14953 006a 7B68 ldr r3, [r7, #4] + 14954 006c 0122 movs r2, #1 + 14955 006e 83F83D20 strb r2, [r3, #61] +5727:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __HAL_UNLOCK(htim); + 14956 .loc 1 5728 3 + 14957 0072 7B68 ldr r3, [r7, #4] + 14958 0074 0022 movs r2, #0 + 14959 0076 83F83C20 strb r2, [r3, #60] +5729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_OK; + 14960 .loc 1 5730 10 + 14961 007a 0023 movs r3, #0 + 14962 .L1121: +5731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 14963 .loc 1 5731 1 + 14964 007c 1846 mov r0, r3 + 14965 007e 0837 adds r7, r7, #8 + 14966 .cfi_def_cfa_offset 8 + 14967 0080 BD46 mov sp, r7 + 14968 .cfi_def_cfa_register 13 + 14969 @ sp needed + 14970 0082 80BD pop {r7, pc} + 14971 .cfi_endproc + 14972 .LFE204: + 14974 .section .text.HAL_TIM_ReadCapturedValue,"ax",%progbits + ARM GAS /tmp/ccl4b9YO.s page 363 + + + 14975 .align 1 + 14976 .global HAL_TIM_ReadCapturedValue + 14977 .syntax unified + 14978 .thumb + 14979 .thumb_func + 14981 HAL_TIM_ReadCapturedValue: + 14982 .LFB205: +5732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +5734:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Read the captured value from Capture Compare unit +5735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM handle. +5736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param Channel TIM Channels to be enabled +5737:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +5738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +5739:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +5740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +5741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 selected +5742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval Captured value +5743:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +5744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel) +5745:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 14983 .loc 1 5745 1 + 14984 .cfi_startproc + 14985 @ args = 0, pretend = 0, frame = 16 + 14986 @ frame_needed = 1, uses_anonymous_args = 0 + 14987 @ link register save eliminated. + 14988 0000 80B4 push {r7} + 14989 .cfi_def_cfa_offset 4 + 14990 .cfi_offset 7, -4 + 14991 0002 85B0 sub sp, sp, #20 + 14992 .cfi_def_cfa_offset 24 + 14993 0004 00AF add r7, sp, #0 + 14994 .cfi_def_cfa_register 7 + 14995 0006 7860 str r0, [r7, #4] + 14996 0008 3960 str r1, [r7] +5746:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpreg = 0U; + 14997 .loc 1 5746 12 + 14998 000a 0023 movs r3, #0 + 14999 000c FB60 str r3, [r7, #12] +5747:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5748:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** switch (Channel) + 15000 .loc 1 5748 3 + 15001 000e 3B68 ldr r3, [r7] + 15002 0010 0C2B cmp r3, #12 + 15003 0012 31D8 bhi .L1132 + 15004 0014 01A2 adr r2, .L1126 + 15005 0016 52F823F0 ldr pc, [r2, r3, lsl #2] + 15006 001a 00BF .p2align 2 + 15007 .L1126: + 15008 001c 51000000 .word .L1129+1 + 15009 0020 79000000 .word .L1132+1 + 15010 0024 79000000 .word .L1132+1 + 15011 0028 79000000 .word .L1132+1 + 15012 002c 5B000000 .word .L1128+1 + 15013 0030 79000000 .word .L1132+1 + 15014 0034 79000000 .word .L1132+1 + 15015 0038 79000000 .word .L1132+1 + ARM GAS /tmp/ccl4b9YO.s page 364 + + + 15016 003c 65000000 .word .L1127+1 + 15017 0040 79000000 .word .L1132+1 + 15018 0044 79000000 .word .L1132+1 + 15019 0048 79000000 .word .L1132+1 + 15020 004c 6F000000 .word .L1125+1 + 15021 .p2align 1 + 15022 .L1129: +5749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_1: +5751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5752:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +5753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); +5754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5755:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return the capture 1 value */ +5756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpreg = htim->Instance->CCR1; + 15023 .loc 1 5756 21 + 15024 0050 7B68 ldr r3, [r7, #4] + 15025 0052 1B68 ldr r3, [r3] + 15026 .loc 1 5756 14 + 15027 0054 5B6B ldr r3, [r3, #52] + 15028 0056 FB60 str r3, [r7, #12] +5757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5758:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 15029 .loc 1 5758 7 + 15030 0058 0FE0 b .L1130 + 15031 .L1128: +5759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5760:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_2: +5761:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +5763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); +5764:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return the capture 2 value */ +5766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpreg = htim->Instance->CCR2; + 15032 .loc 1 5766 22 + 15033 005a 7B68 ldr r3, [r7, #4] + 15034 005c 1B68 ldr r3, [r3] + 15035 .loc 1 5766 14 + 15036 005e 9B6B ldr r3, [r3, #56] + 15037 0060 FB60 str r3, [r7, #12] +5767:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 15038 .loc 1 5768 7 + 15039 0062 0AE0 b .L1130 + 15040 .L1127: +5769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_3: +5772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +5774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); +5775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return the capture 3 value */ +5777:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpreg = htim->Instance->CCR3; + 15041 .loc 1 5777 22 + 15042 0064 7B68 ldr r3, [r7, #4] + 15043 0066 1B68 ldr r3, [r3] + ARM GAS /tmp/ccl4b9YO.s page 365 + + + 15044 .loc 1 5777 14 + 15045 0068 DB6B ldr r3, [r3, #60] + 15046 006a FB60 str r3, [r7, #12] +5778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 15047 .loc 1 5779 7 + 15048 006c 05E0 b .L1130 + 15049 .L1125: +5780:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5782:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_CHANNEL_4: +5783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +5784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +5785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); +5786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5787:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return the capture 4 value */ +5788:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpreg = htim->Instance->CCR4; + 15050 .loc 1 5788 22 + 15051 006e 7B68 ldr r3, [r7, #4] + 15052 0070 1B68 ldr r3, [r3] + 15053 .loc 1 5788 14 + 15054 0072 1B6C ldr r3, [r3, #64] + 15055 0074 FB60 str r3, [r7, #12] +5789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 15056 .loc 1 5790 7 + 15057 0076 00E0 b .L1130 + 15058 .L1132: +5791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** default: +5794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 15059 .loc 1 5794 7 + 15060 0078 00BF nop + 15061 .L1130: +5795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +5796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return tmpreg; + 15062 .loc 1 5797 10 + 15063 007a FB68 ldr r3, [r7, #12] +5798:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 15064 .loc 1 5798 1 + 15065 007c 1846 mov r0, r3 + 15066 007e 1437 adds r7, r7, #20 + 15067 .cfi_def_cfa_offset 4 + 15068 0080 BD46 mov sp, r7 + 15069 .cfi_def_cfa_register 13 + 15070 @ sp needed + 15071 0082 5DF8047B ldr r7, [sp], #4 + 15072 .cfi_restore 7 + 15073 .cfi_def_cfa_offset 0 + 15074 0086 7047 bx lr + 15075 .cfi_endproc + 15076 .LFE205: + 15078 .section .text.HAL_TIM_PeriodElapsedCallback,"ax",%progbits + 15079 .align 1 + 15080 .weak HAL_TIM_PeriodElapsedCallback + ARM GAS /tmp/ccl4b9YO.s page 366 + + + 15081 .syntax unified + 15082 .thumb + 15083 .thumb_func + 15085 HAL_TIM_PeriodElapsedCallback: + 15086 .LFB206: +5799:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +5801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @} +5802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +5803:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5804:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions +5805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief TIM Callbacks functions +5806:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * +5807:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** @verbatim +5808:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** ============================================================================== +5809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** ##### TIM Callbacks functions ##### +5810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** ============================================================================== +5811:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** [..] +5812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** This section provides TIM callback functions: +5813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) TIM Period elapsed callback +5814:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) TIM Output Compare callback +5815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) TIM Input capture callback +5816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) TIM Trigger callback +5817:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** (+) TIM Error callback +5818:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** @endverbatim +5820:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @{ +5821:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +5822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +5824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Period elapsed callback in non-blocking mode +5825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM handle +5826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval None +5827:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +5828:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +5829:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 15087 .loc 1 5829 1 + 15088 .cfi_startproc + 15089 @ args = 0, pretend = 0, frame = 8 + 15090 @ frame_needed = 1, uses_anonymous_args = 0 + 15091 @ link register save eliminated. + 15092 0000 80B4 push {r7} + 15093 .cfi_def_cfa_offset 4 + 15094 .cfi_offset 7, -4 + 15095 0002 83B0 sub sp, sp, #12 + 15096 .cfi_def_cfa_offset 16 + 15097 0004 00AF add r7, sp, #0 + 15098 .cfi_def_cfa_register 7 + 15099 0006 7860 str r0, [r7, #4] +5830:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +5831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** UNUSED(htim); +5832:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* NOTE : This function should not be modified, when the callback is needed, +5834:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** the HAL_TIM_PeriodElapsedCallback could be implemented in the user file +5835:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +5836:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 15100 .loc 1 5836 1 + ARM GAS /tmp/ccl4b9YO.s page 367 + + + 15101 0008 00BF nop + 15102 000a 0C37 adds r7, r7, #12 + 15103 .cfi_def_cfa_offset 4 + 15104 000c BD46 mov sp, r7 + 15105 .cfi_def_cfa_register 13 + 15106 @ sp needed + 15107 000e 5DF8047B ldr r7, [sp], #4 + 15108 .cfi_restore 7 + 15109 .cfi_def_cfa_offset 0 + 15110 0012 7047 bx lr + 15111 .cfi_endproc + 15112 .LFE206: + 15114 .section .text.HAL_TIM_PeriodElapsedHalfCpltCallback,"ax",%progbits + 15115 .align 1 + 15116 .weak HAL_TIM_PeriodElapsedHalfCpltCallback + 15117 .syntax unified + 15118 .thumb + 15119 .thumb_func + 15121 HAL_TIM_PeriodElapsedHalfCpltCallback: + 15122 .LFB207: +5837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +5839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Period elapsed half complete callback in non-blocking mode +5840:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM handle +5841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval None +5842:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +5843:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim) +5844:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 15123 .loc 1 5844 1 + 15124 .cfi_startproc + 15125 @ args = 0, pretend = 0, frame = 8 + 15126 @ frame_needed = 1, uses_anonymous_args = 0 + 15127 @ link register save eliminated. + 15128 0000 80B4 push {r7} + 15129 .cfi_def_cfa_offset 4 + 15130 .cfi_offset 7, -4 + 15131 0002 83B0 sub sp, sp, #12 + 15132 .cfi_def_cfa_offset 16 + 15133 0004 00AF add r7, sp, #0 + 15134 .cfi_def_cfa_register 7 + 15135 0006 7860 str r0, [r7, #4] +5845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +5846:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** UNUSED(htim); +5847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* NOTE : This function should not be modified, when the callback is needed, +5849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file +5850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +5851:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 15136 .loc 1 5851 1 + 15137 0008 00BF nop + 15138 000a 0C37 adds r7, r7, #12 + 15139 .cfi_def_cfa_offset 4 + 15140 000c BD46 mov sp, r7 + 15141 .cfi_def_cfa_register 13 + 15142 @ sp needed + 15143 000e 5DF8047B ldr r7, [sp], #4 + 15144 .cfi_restore 7 + ARM GAS /tmp/ccl4b9YO.s page 368 + + + 15145 .cfi_def_cfa_offset 0 + 15146 0012 7047 bx lr + 15147 .cfi_endproc + 15148 .LFE207: + 15150 .section .text.HAL_TIM_OC_DelayElapsedCallback,"ax",%progbits + 15151 .align 1 + 15152 .weak HAL_TIM_OC_DelayElapsedCallback + 15153 .syntax unified + 15154 .thumb + 15155 .thumb_func + 15157 HAL_TIM_OC_DelayElapsedCallback: + 15158 .LFB208: +5852:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5853:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +5854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Output Compare callback in non-blocking mode +5855:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM OC handle +5856:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval None +5857:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +5858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) +5859:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 15159 .loc 1 5859 1 + 15160 .cfi_startproc + 15161 @ args = 0, pretend = 0, frame = 8 + 15162 @ frame_needed = 1, uses_anonymous_args = 0 + 15163 @ link register save eliminated. + 15164 0000 80B4 push {r7} + 15165 .cfi_def_cfa_offset 4 + 15166 .cfi_offset 7, -4 + 15167 0002 83B0 sub sp, sp, #12 + 15168 .cfi_def_cfa_offset 16 + 15169 0004 00AF add r7, sp, #0 + 15170 .cfi_def_cfa_register 7 + 15171 0006 7860 str r0, [r7, #4] +5860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +5861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** UNUSED(htim); +5862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* NOTE : This function should not be modified, when the callback is needed, +5864:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file +5865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +5866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 15172 .loc 1 5866 1 + 15173 0008 00BF nop + 15174 000a 0C37 adds r7, r7, #12 + 15175 .cfi_def_cfa_offset 4 + 15176 000c BD46 mov sp, r7 + 15177 .cfi_def_cfa_register 13 + 15178 @ sp needed + 15179 000e 5DF8047B ldr r7, [sp], #4 + 15180 .cfi_restore 7 + 15181 .cfi_def_cfa_offset 0 + 15182 0012 7047 bx lr + 15183 .cfi_endproc + 15184 .LFE208: + 15186 .section .text.HAL_TIM_IC_CaptureCallback,"ax",%progbits + 15187 .align 1 + 15188 .weak HAL_TIM_IC_CaptureCallback + 15189 .syntax unified + ARM GAS /tmp/ccl4b9YO.s page 369 + + + 15190 .thumb + 15191 .thumb_func + 15193 HAL_TIM_IC_CaptureCallback: + 15194 .LFB209: +5867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5868:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +5869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Input Capture callback in non-blocking mode +5870:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM IC handle +5871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval None +5872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +5873:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) +5874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 15195 .loc 1 5874 1 + 15196 .cfi_startproc + 15197 @ args = 0, pretend = 0, frame = 8 + 15198 @ frame_needed = 1, uses_anonymous_args = 0 + 15199 @ link register save eliminated. + 15200 0000 80B4 push {r7} + 15201 .cfi_def_cfa_offset 4 + 15202 .cfi_offset 7, -4 + 15203 0002 83B0 sub sp, sp, #12 + 15204 .cfi_def_cfa_offset 16 + 15205 0004 00AF add r7, sp, #0 + 15206 .cfi_def_cfa_register 7 + 15207 0006 7860 str r0, [r7, #4] +5875:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +5876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** UNUSED(htim); +5877:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5878:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* NOTE : This function should not be modified, when the callback is needed, +5879:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** the HAL_TIM_IC_CaptureCallback could be implemented in the user file +5880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +5881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 15208 .loc 1 5881 1 + 15209 0008 00BF nop + 15210 000a 0C37 adds r7, r7, #12 + 15211 .cfi_def_cfa_offset 4 + 15212 000c BD46 mov sp, r7 + 15213 .cfi_def_cfa_register 13 + 15214 @ sp needed + 15215 000e 5DF8047B ldr r7, [sp], #4 + 15216 .cfi_restore 7 + 15217 .cfi_def_cfa_offset 0 + 15218 0012 7047 bx lr + 15219 .cfi_endproc + 15220 .LFE209: + 15222 .section .text.HAL_TIM_IC_CaptureHalfCpltCallback,"ax",%progbits + 15223 .align 1 + 15224 .weak HAL_TIM_IC_CaptureHalfCpltCallback + 15225 .syntax unified + 15226 .thumb + 15227 .thumb_func + 15229 HAL_TIM_IC_CaptureHalfCpltCallback: + 15230 .LFB210: +5882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +5884:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Input Capture half complete callback in non-blocking mode +5885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM IC handle + ARM GAS /tmp/ccl4b9YO.s page 370 + + +5886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval None +5887:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +5888:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim) +5889:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 15231 .loc 1 5889 1 + 15232 .cfi_startproc + 15233 @ args = 0, pretend = 0, frame = 8 + 15234 @ frame_needed = 1, uses_anonymous_args = 0 + 15235 @ link register save eliminated. + 15236 0000 80B4 push {r7} + 15237 .cfi_def_cfa_offset 4 + 15238 .cfi_offset 7, -4 + 15239 0002 83B0 sub sp, sp, #12 + 15240 .cfi_def_cfa_offset 16 + 15241 0004 00AF add r7, sp, #0 + 15242 .cfi_def_cfa_register 7 + 15243 0006 7860 str r0, [r7, #4] +5890:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +5891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** UNUSED(htim); +5892:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* NOTE : This function should not be modified, when the callback is needed, +5894:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file +5895:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +5896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 15244 .loc 1 5896 1 + 15245 0008 00BF nop + 15246 000a 0C37 adds r7, r7, #12 + 15247 .cfi_def_cfa_offset 4 + 15248 000c BD46 mov sp, r7 + 15249 .cfi_def_cfa_register 13 + 15250 @ sp needed + 15251 000e 5DF8047B ldr r7, [sp], #4 + 15252 .cfi_restore 7 + 15253 .cfi_def_cfa_offset 0 + 15254 0012 7047 bx lr + 15255 .cfi_endproc + 15256 .LFE210: + 15258 .section .text.HAL_TIM_PWM_PulseFinishedCallback,"ax",%progbits + 15259 .align 1 + 15260 .weak HAL_TIM_PWM_PulseFinishedCallback + 15261 .syntax unified + 15262 .thumb + 15263 .thumb_func + 15265 HAL_TIM_PWM_PulseFinishedCallback: + 15266 .LFB211: +5897:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +5899:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief PWM Pulse finished callback in non-blocking mode +5900:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM handle +5901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval None +5902:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +5903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) +5904:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 15267 .loc 1 5904 1 + 15268 .cfi_startproc + 15269 @ args = 0, pretend = 0, frame = 8 + 15270 @ frame_needed = 1, uses_anonymous_args = 0 + ARM GAS /tmp/ccl4b9YO.s page 371 + + + 15271 @ link register save eliminated. + 15272 0000 80B4 push {r7} + 15273 .cfi_def_cfa_offset 4 + 15274 .cfi_offset 7, -4 + 15275 0002 83B0 sub sp, sp, #12 + 15276 .cfi_def_cfa_offset 16 + 15277 0004 00AF add r7, sp, #0 + 15278 .cfi_def_cfa_register 7 + 15279 0006 7860 str r0, [r7, #4] +5905:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +5906:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** UNUSED(htim); +5907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5908:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* NOTE : This function should not be modified, when the callback is needed, +5909:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file +5910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +5911:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 15280 .loc 1 5911 1 + 15281 0008 00BF nop + 15282 000a 0C37 adds r7, r7, #12 + 15283 .cfi_def_cfa_offset 4 + 15284 000c BD46 mov sp, r7 + 15285 .cfi_def_cfa_register 13 + 15286 @ sp needed + 15287 000e 5DF8047B ldr r7, [sp], #4 + 15288 .cfi_restore 7 + 15289 .cfi_def_cfa_offset 0 + 15290 0012 7047 bx lr + 15291 .cfi_endproc + 15292 .LFE211: + 15294 .section .text.HAL_TIM_PWM_PulseFinishedHalfCpltCallback,"ax",%progbits + 15295 .align 1 + 15296 .weak HAL_TIM_PWM_PulseFinishedHalfCpltCallback + 15297 .syntax unified + 15298 .thumb + 15299 .thumb_func + 15301 HAL_TIM_PWM_PulseFinishedHalfCpltCallback: + 15302 .LFB212: +5912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5913:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +5914:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief PWM Pulse finished half complete callback in non-blocking mode +5915:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM handle +5916:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval None +5917:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +5918:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim) +5919:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 15303 .loc 1 5919 1 + 15304 .cfi_startproc + 15305 @ args = 0, pretend = 0, frame = 8 + 15306 @ frame_needed = 1, uses_anonymous_args = 0 + 15307 @ link register save eliminated. + 15308 0000 80B4 push {r7} + 15309 .cfi_def_cfa_offset 4 + 15310 .cfi_offset 7, -4 + 15311 0002 83B0 sub sp, sp, #12 + 15312 .cfi_def_cfa_offset 16 + 15313 0004 00AF add r7, sp, #0 + 15314 .cfi_def_cfa_register 7 + ARM GAS /tmp/ccl4b9YO.s page 372 + + + 15315 0006 7860 str r0, [r7, #4] +5920:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +5921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** UNUSED(htim); +5922:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5923:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* NOTE : This function should not be modified, when the callback is needed, +5924:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file +5925:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +5926:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 15316 .loc 1 5926 1 + 15317 0008 00BF nop + 15318 000a 0C37 adds r7, r7, #12 + 15319 .cfi_def_cfa_offset 4 + 15320 000c BD46 mov sp, r7 + 15321 .cfi_def_cfa_register 13 + 15322 @ sp needed + 15323 000e 5DF8047B ldr r7, [sp], #4 + 15324 .cfi_restore 7 + 15325 .cfi_def_cfa_offset 0 + 15326 0012 7047 bx lr + 15327 .cfi_endproc + 15328 .LFE212: + 15330 .section .text.HAL_TIM_TriggerCallback,"ax",%progbits + 15331 .align 1 + 15332 .weak HAL_TIM_TriggerCallback + 15333 .syntax unified + 15334 .thumb + 15335 .thumb_func + 15337 HAL_TIM_TriggerCallback: + 15338 .LFB213: +5927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5928:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +5929:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Hall Trigger detection callback in non-blocking mode +5930:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM handle +5931:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval None +5932:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +5933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) +5934:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 15339 .loc 1 5934 1 + 15340 .cfi_startproc + 15341 @ args = 0, pretend = 0, frame = 8 + 15342 @ frame_needed = 1, uses_anonymous_args = 0 + 15343 @ link register save eliminated. + 15344 0000 80B4 push {r7} + 15345 .cfi_def_cfa_offset 4 + 15346 .cfi_offset 7, -4 + 15347 0002 83B0 sub sp, sp, #12 + 15348 .cfi_def_cfa_offset 16 + 15349 0004 00AF add r7, sp, #0 + 15350 .cfi_def_cfa_register 7 + 15351 0006 7860 str r0, [r7, #4] +5935:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +5936:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** UNUSED(htim); +5937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* NOTE : This function should not be modified, when the callback is needed, +5939:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** the HAL_TIM_TriggerCallback could be implemented in the user file +5940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +5941:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + ARM GAS /tmp/ccl4b9YO.s page 373 + + + 15352 .loc 1 5941 1 + 15353 0008 00BF nop + 15354 000a 0C37 adds r7, r7, #12 + 15355 .cfi_def_cfa_offset 4 + 15356 000c BD46 mov sp, r7 + 15357 .cfi_def_cfa_register 13 + 15358 @ sp needed + 15359 000e 5DF8047B ldr r7, [sp], #4 + 15360 .cfi_restore 7 + 15361 .cfi_def_cfa_offset 0 + 15362 0012 7047 bx lr + 15363 .cfi_endproc + 15364 .LFE213: + 15366 .section .text.HAL_TIM_TriggerHalfCpltCallback,"ax",%progbits + 15367 .align 1 + 15368 .weak HAL_TIM_TriggerHalfCpltCallback + 15369 .syntax unified + 15370 .thumb + 15371 .thumb_func + 15373 HAL_TIM_TriggerHalfCpltCallback: + 15374 .LFB214: +5942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5943:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +5944:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Hall Trigger detection half complete callback in non-blocking mode +5945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM handle +5946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval None +5947:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +5948:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim) +5949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 15375 .loc 1 5949 1 + 15376 .cfi_startproc + 15377 @ args = 0, pretend = 0, frame = 8 + 15378 @ frame_needed = 1, uses_anonymous_args = 0 + 15379 @ link register save eliminated. + 15380 0000 80B4 push {r7} + 15381 .cfi_def_cfa_offset 4 + 15382 .cfi_offset 7, -4 + 15383 0002 83B0 sub sp, sp, #12 + 15384 .cfi_def_cfa_offset 16 + 15385 0004 00AF add r7, sp, #0 + 15386 .cfi_def_cfa_register 7 + 15387 0006 7860 str r0, [r7, #4] +5950:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +5951:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** UNUSED(htim); +5952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* NOTE : This function should not be modified, when the callback is needed, +5954:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file +5955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +5956:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 15388 .loc 1 5956 1 + 15389 0008 00BF nop + 15390 000a 0C37 adds r7, r7, #12 + 15391 .cfi_def_cfa_offset 4 + 15392 000c BD46 mov sp, r7 + 15393 .cfi_def_cfa_register 13 + 15394 @ sp needed + 15395 000e 5DF8047B ldr r7, [sp], #4 + ARM GAS /tmp/ccl4b9YO.s page 374 + + + 15396 .cfi_restore 7 + 15397 .cfi_def_cfa_offset 0 + 15398 0012 7047 bx lr + 15399 .cfi_endproc + 15400 .LFE214: + 15402 .section .text.HAL_TIM_ErrorCallback,"ax",%progbits + 15403 .align 1 + 15404 .weak HAL_TIM_ErrorCallback + 15405 .syntax unified + 15406 .thumb + 15407 .thumb_func + 15409 HAL_TIM_ErrorCallback: + 15410 .LFB215: +5957:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5958:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +5959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Timer error callback in non-blocking mode +5960:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM handle +5961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval None +5962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +5963:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) +5964:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 15411 .loc 1 5964 1 + 15412 .cfi_startproc + 15413 @ args = 0, pretend = 0, frame = 8 + 15414 @ frame_needed = 1, uses_anonymous_args = 0 + 15415 @ link register save eliminated. + 15416 0000 80B4 push {r7} + 15417 .cfi_def_cfa_offset 4 + 15418 .cfi_offset 7, -4 + 15419 0002 83B0 sub sp, sp, #12 + 15420 .cfi_def_cfa_offset 16 + 15421 0004 00AF add r7, sp, #0 + 15422 .cfi_def_cfa_register 7 + 15423 0006 7860 str r0, [r7, #4] +5965:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Prevent unused argument(s) compilation warning */ +5966:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** UNUSED(htim); +5967:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* NOTE : This function should not be modified, when the callback is needed, +5969:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** the HAL_TIM_ErrorCallback could be implemented in the user file +5970:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +5971:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 15424 .loc 1 5971 1 + 15425 0008 00BF nop + 15426 000a 0C37 adds r7, r7, #12 + 15427 .cfi_def_cfa_offset 4 + 15428 000c BD46 mov sp, r7 + 15429 .cfi_def_cfa_register 13 + 15430 @ sp needed + 15431 000e 5DF8047B ldr r7, [sp], #4 + 15432 .cfi_restore 7 + 15433 .cfi_def_cfa_offset 0 + 15434 0012 7047 bx lr + 15435 .cfi_endproc + 15436 .LFE215: + 15438 .section .text.HAL_TIM_Base_GetState,"ax",%progbits + 15439 .align 1 + 15440 .global HAL_TIM_Base_GetState + ARM GAS /tmp/ccl4b9YO.s page 375 + + + 15441 .syntax unified + 15442 .thumb + 15443 .thumb_func + 15445 HAL_TIM_Base_GetState: + 15446 .LFB216: +5972:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +5973:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +5974:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +5975:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Register a User TIM callback to be used instead of the weak predefined callback +5976:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim tim handle +5977:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param CallbackID ID of the callback to be registered +5978:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +5979:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID +5980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID +5981:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID +5982:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID +5983:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID +5984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID +5985:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID +5986:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID +5987:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID +5988:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID +5989:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID +5990:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID +5991:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID +5992:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID +5993:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID +5994:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID +5995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID +5996:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID +5997:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID +5998:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID +5999:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID +6000:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID +6001:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callb +6002:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID +6003:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID +6004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID +6005:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID +6006:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if defined(TIM_BDTR_BK2E) +6007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID +6008:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif +6009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param pCallback pointer to the callback function +6010:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval status +6011:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +6012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef Callb +6013:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** pTIM_CallbackTypeDef pCallback) +6014:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +6015:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; +6016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6017:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (pCallback == NULL) +6018:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +6019:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; +6020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +6021:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (htim->State == HAL_TIM_STATE_READY) +6023:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + ARM GAS /tmp/ccl4b9YO.s page 376 + + +6024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** switch (CallbackID) +6025:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +6026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_BASE_MSPINIT_CB_ID : +6027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Base_MspInitCallback = pCallback; +6028:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6030:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_BASE_MSPDEINIT_CB_ID : +6031:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Base_MspDeInitCallback = pCallback; +6032:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6033:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_IC_MSPINIT_CB_ID : +6035:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->IC_MspInitCallback = pCallback; +6036:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6038:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_IC_MSPDEINIT_CB_ID : +6039:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->IC_MspDeInitCallback = pCallback; +6040:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6041:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_OC_MSPINIT_CB_ID : +6043:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->OC_MspInitCallback = pCallback; +6044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6045:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6046:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_OC_MSPDEINIT_CB_ID : +6047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->OC_MspDeInitCallback = pCallback; +6048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6049:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6050:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_PWM_MSPINIT_CB_ID : +6051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->PWM_MspInitCallback = pCallback; +6052:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_PWM_MSPDEINIT_CB_ID : +6055:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->PWM_MspDeInitCallback = pCallback; +6056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6057:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : +6059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->OnePulse_MspInitCallback = pCallback; +6060:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6062:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : +6063:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->OnePulse_MspDeInitCallback = pCallback; +6064:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6066:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_ENCODER_MSPINIT_CB_ID : +6067:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Encoder_MspInitCallback = pCallback; +6068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6069:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6070:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : +6071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Encoder_MspDeInitCallback = pCallback; +6072:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6073:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6074:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : +6075:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->HallSensor_MspInitCallback = pCallback; +6076:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6077:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6078:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : +6079:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->HallSensor_MspDeInitCallback = pCallback; +6080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + ARM GAS /tmp/ccl4b9YO.s page 377 + + +6081:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_PERIOD_ELAPSED_CB_ID : +6083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->PeriodElapsedCallback = pCallback; +6084:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6086:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : +6087:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->PeriodElapsedHalfCpltCallback = pCallback; +6088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6089:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6090:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_TRIGGER_CB_ID : +6091:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->TriggerCallback = pCallback; +6092:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6093:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6094:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_TRIGGER_HALF_CB_ID : +6095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->TriggerHalfCpltCallback = pCallback; +6096:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6097:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_IC_CAPTURE_CB_ID : +6099:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->IC_CaptureCallback = pCallback; +6100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_IC_CAPTURE_HALF_CB_ID : +6103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->IC_CaptureHalfCpltCallback = pCallback; +6104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : +6107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->OC_DelayElapsedCallback = pCallback; +6108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : +6111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->PWM_PulseFinishedCallback = pCallback; +6112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : +6115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->PWM_PulseFinishedHalfCpltCallback = pCallback; +6116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_ERROR_CB_ID : +6119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->ErrorCallback = pCallback; +6120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_COMMUTATION_CB_ID : +6123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->CommutationCallback = pCallback; +6124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_COMMUTATION_HALF_CB_ID : +6127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->CommutationHalfCpltCallback = pCallback; +6128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_BREAK_CB_ID : +6131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->BreakCallback = pCallback; +6132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if defined(TIM_BDTR_BK2E) +6134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_BREAK2_CB_ID : +6136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Break2Callback = pCallback; +6137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + ARM GAS /tmp/ccl4b9YO.s page 378 + + +6138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* TIM_BDTR_BK2E */ +6139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** default : +6141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return error status */ +6142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** status = HAL_ERROR; +6143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +6145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +6146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else if (htim->State == HAL_TIM_STATE_RESET) +6147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +6148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** switch (CallbackID) +6149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +6150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_BASE_MSPINIT_CB_ID : +6151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Base_MspInitCallback = pCallback; +6152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_BASE_MSPDEINIT_CB_ID : +6155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Base_MspDeInitCallback = pCallback; +6156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_IC_MSPINIT_CB_ID : +6159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->IC_MspInitCallback = pCallback; +6160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_IC_MSPDEINIT_CB_ID : +6163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->IC_MspDeInitCallback = pCallback; +6164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_OC_MSPINIT_CB_ID : +6167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->OC_MspInitCallback = pCallback; +6168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_OC_MSPDEINIT_CB_ID : +6171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->OC_MspDeInitCallback = pCallback; +6172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_PWM_MSPINIT_CB_ID : +6175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->PWM_MspInitCallback = pCallback; +6176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_PWM_MSPDEINIT_CB_ID : +6179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->PWM_MspDeInitCallback = pCallback; +6180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : +6183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->OnePulse_MspInitCallback = pCallback; +6184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : +6187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->OnePulse_MspDeInitCallback = pCallback; +6188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_ENCODER_MSPINIT_CB_ID : +6191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Encoder_MspInitCallback = pCallback; +6192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + ARM GAS /tmp/ccl4b9YO.s page 379 + + +6195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Encoder_MspDeInitCallback = pCallback; +6196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : +6199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->HallSensor_MspInitCallback = pCallback; +6200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : +6203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->HallSensor_MspDeInitCallback = pCallback; +6204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** default : +6207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return error status */ +6208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** status = HAL_ERROR; +6209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +6211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +6212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +6213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +6214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return error status */ +6215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** status = HAL_ERROR; +6216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +6217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return status; +6219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +6220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +6222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Unregister a TIM callback +6223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * TIM callback is redirected to the weak predefined callback +6224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim tim handle +6225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param CallbackID ID of the callback to be unregistered +6226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +6227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID +6228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID +6229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID +6230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID +6231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID +6232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID +6233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID +6234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID +6235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID +6236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID +6237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID +6238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID +6239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID +6240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID +6241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID +6242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID +6243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID +6244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID +6245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID +6246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID +6247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID +6248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID +6249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callb +6250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID +6251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID + ARM GAS /tmp/ccl4b9YO.s page 380 + + +6252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID +6253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID +6254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if defined(TIM_BDTR_BK2E) +6255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID +6256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif +6257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval status +6258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +6259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef Cal +6260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +6261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; +6262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (htim->State == HAL_TIM_STATE_READY) +6264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +6265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** switch (CallbackID) +6266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +6267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_BASE_MSPINIT_CB_ID : +6268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Legacy weak Base MspInit Callback */ +6269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; +6270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_BASE_MSPDEINIT_CB_ID : +6273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Legacy weak Base Msp DeInit Callback */ +6274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; +6275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_IC_MSPINIT_CB_ID : +6278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Legacy weak IC Msp Init Callback */ +6279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; +6280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_IC_MSPDEINIT_CB_ID : +6283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Legacy weak IC Msp DeInit Callback */ +6284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; +6285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_OC_MSPINIT_CB_ID : +6288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Legacy weak OC Msp Init Callback */ +6289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; +6290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_OC_MSPDEINIT_CB_ID : +6293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Legacy weak OC Msp DeInit Callback */ +6294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; +6295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_PWM_MSPINIT_CB_ID : +6298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Legacy weak PWM Msp Init Callback */ +6299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; +6300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_PWM_MSPDEINIT_CB_ID : +6303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Legacy weak PWM Msp DeInit Callback */ +6304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; +6305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : +6308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Legacy weak One Pulse Msp Init Callback */ + ARM GAS /tmp/ccl4b9YO.s page 381 + + +6309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; +6310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : +6313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Legacy weak One Pulse Msp DeInit Callback */ +6314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; +6315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_ENCODER_MSPINIT_CB_ID : +6318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Legacy weak Encoder Msp Init Callback */ +6319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; +6320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : +6323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Legacy weak Encoder Msp DeInit Callback */ +6324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; +6325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : +6328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Legacy weak Hall Sensor Msp Init Callback */ +6329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; +6330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : +6333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Legacy weak Hall Sensor Msp DeInit Callback */ +6334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; +6335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_PERIOD_ELAPSED_CB_ID : +6338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Legacy weak Period Elapsed Callback */ +6339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; +6340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : +6343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Legacy weak Period Elapsed half complete Callback */ +6344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; +6345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_TRIGGER_CB_ID : +6348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Legacy weak Trigger Callback */ +6349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->TriggerCallback = HAL_TIM_TriggerCallback; +6350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_TRIGGER_HALF_CB_ID : +6353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Legacy weak Trigger half complete Callback */ +6354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; +6355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_IC_CAPTURE_CB_ID : +6358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Legacy weak IC Capture Callback */ +6359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; +6360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_IC_CAPTURE_HALF_CB_ID : +6363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Legacy weak IC Capture half complete Callback */ +6364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; +6365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + ARM GAS /tmp/ccl4b9YO.s page 382 + + +6366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : +6368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Legacy weak OC Delay Elapsed Callback */ +6369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; +6370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : +6373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Legacy weak PWM Pulse Finished Callback */ +6374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; +6375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : +6378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Legacy weak PWM Pulse Finished half complete Callback */ +6379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; +6380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_ERROR_CB_ID : +6383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Legacy weak Error Callback */ +6384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->ErrorCallback = HAL_TIM_ErrorCallback; +6385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_COMMUTATION_CB_ID : +6388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Legacy weak Commutation Callback */ +6389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->CommutationCallback = HAL_TIMEx_CommutCallback; +6390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_COMMUTATION_HALF_CB_ID : +6393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Legacy weak Commutation half complete Callback */ +6394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; +6395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_BREAK_CB_ID : +6398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Legacy weak Break Callback */ +6399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->BreakCallback = HAL_TIMEx_BreakCallback; +6400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if defined(TIM_BDTR_BK2E) +6402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_BREAK2_CB_ID : +6404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Legacy weak Break2 Callback */ +6405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Break2Callback = HAL_TIMEx_Break2Callback; +6406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* TIM_BDTR_BK2E */ +6408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** default : +6410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return error status */ +6411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** status = HAL_ERROR; +6412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +6414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +6415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else if (htim->State == HAL_TIM_STATE_RESET) +6416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +6417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** switch (CallbackID) +6418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +6419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_BASE_MSPINIT_CB_ID : +6420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Legacy weak Base MspInit Callback */ +6421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; +6422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + ARM GAS /tmp/ccl4b9YO.s page 383 + + +6423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_BASE_MSPDEINIT_CB_ID : +6425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Legacy weak Base Msp DeInit Callback */ +6426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; +6427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_IC_MSPINIT_CB_ID : +6430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Legacy weak IC Msp Init Callback */ +6431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; +6432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_IC_MSPDEINIT_CB_ID : +6435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Legacy weak IC Msp DeInit Callback */ +6436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; +6437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_OC_MSPINIT_CB_ID : +6440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Legacy weak OC Msp Init Callback */ +6441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; +6442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_OC_MSPDEINIT_CB_ID : +6445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Legacy weak OC Msp DeInit Callback */ +6446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; +6447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_PWM_MSPINIT_CB_ID : +6450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Legacy weak PWM Msp Init Callback */ +6451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; +6452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_PWM_MSPDEINIT_CB_ID : +6455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Legacy weak PWM Msp DeInit Callback */ +6456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; +6457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : +6460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Legacy weak One Pulse Msp Init Callback */ +6461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; +6462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : +6465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Legacy weak One Pulse Msp DeInit Callback */ +6466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; +6467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_ENCODER_MSPINIT_CB_ID : +6470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Legacy weak Encoder Msp Init Callback */ +6471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; +6472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : +6475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Legacy weak Encoder Msp DeInit Callback */ +6476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; +6477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + ARM GAS /tmp/ccl4b9YO.s page 384 + + +6480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Legacy weak Hall Sensor Msp Init Callback */ +6481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; +6482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : +6485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Legacy weak Hall Sensor Msp DeInit Callback */ +6486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; +6487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** default : +6490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return error status */ +6491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** status = HAL_ERROR; +6492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +6493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +6494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +6495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +6496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +6497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Return error status */ +6498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** status = HAL_ERROR; +6499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +6500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return status; +6502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +6503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +6504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +6506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @} +6507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +6508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions +6510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief TIM Peripheral State functions +6511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * +6512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** @verbatim +6513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** ============================================================================== +6514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** ##### Peripheral State functions ##### +6515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** ============================================================================== +6516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** [..] +6517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** This subsection permits to get in run-time the status of the peripheral +6518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** and the data flow. +6519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** @endverbatim +6521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @{ +6522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +6523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +6525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Return the TIM Base handle state. +6526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM Base handle +6527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL state +6528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +6529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim) +6530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 15447 .loc 1 6530 1 + 15448 .cfi_startproc + 15449 @ args = 0, pretend = 0, frame = 8 + 15450 @ frame_needed = 1, uses_anonymous_args = 0 + 15451 @ link register save eliminated. + 15452 0000 80B4 push {r7} + ARM GAS /tmp/ccl4b9YO.s page 385 + + + 15453 .cfi_def_cfa_offset 4 + 15454 .cfi_offset 7, -4 + 15455 0002 83B0 sub sp, sp, #12 + 15456 .cfi_def_cfa_offset 16 + 15457 0004 00AF add r7, sp, #0 + 15458 .cfi_def_cfa_register 7 + 15459 0006 7860 str r0, [r7, #4] +6531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return htim->State; + 15460 .loc 1 6531 14 + 15461 0008 7B68 ldr r3, [r7, #4] + 15462 000a 93F83D30 ldrb r3, [r3, #61] + 15463 000e DBB2 uxtb r3, r3 +6532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 15464 .loc 1 6532 1 + 15465 0010 1846 mov r0, r3 + 15466 0012 0C37 adds r7, r7, #12 + 15467 .cfi_def_cfa_offset 4 + 15468 0014 BD46 mov sp, r7 + 15469 .cfi_def_cfa_register 13 + 15470 @ sp needed + 15471 0016 5DF8047B ldr r7, [sp], #4 + 15472 .cfi_restore 7 + 15473 .cfi_def_cfa_offset 0 + 15474 001a 7047 bx lr + 15475 .cfi_endproc + 15476 .LFE216: + 15478 .section .text.HAL_TIM_OC_GetState,"ax",%progbits + 15479 .align 1 + 15480 .global HAL_TIM_OC_GetState + 15481 .syntax unified + 15482 .thumb + 15483 .thumb_func + 15485 HAL_TIM_OC_GetState: + 15486 .LFB217: +6533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +6535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Return the TIM OC handle state. +6536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM Output Compare handle +6537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL state +6538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +6539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim) +6540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 15487 .loc 1 6540 1 + 15488 .cfi_startproc + 15489 @ args = 0, pretend = 0, frame = 8 + 15490 @ frame_needed = 1, uses_anonymous_args = 0 + 15491 @ link register save eliminated. + 15492 0000 80B4 push {r7} + 15493 .cfi_def_cfa_offset 4 + 15494 .cfi_offset 7, -4 + 15495 0002 83B0 sub sp, sp, #12 + 15496 .cfi_def_cfa_offset 16 + 15497 0004 00AF add r7, sp, #0 + 15498 .cfi_def_cfa_register 7 + 15499 0006 7860 str r0, [r7, #4] +6541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return htim->State; + 15500 .loc 1 6541 14 + ARM GAS /tmp/ccl4b9YO.s page 386 + + + 15501 0008 7B68 ldr r3, [r7, #4] + 15502 000a 93F83D30 ldrb r3, [r3, #61] + 15503 000e DBB2 uxtb r3, r3 +6542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 15504 .loc 1 6542 1 + 15505 0010 1846 mov r0, r3 + 15506 0012 0C37 adds r7, r7, #12 + 15507 .cfi_def_cfa_offset 4 + 15508 0014 BD46 mov sp, r7 + 15509 .cfi_def_cfa_register 13 + 15510 @ sp needed + 15511 0016 5DF8047B ldr r7, [sp], #4 + 15512 .cfi_restore 7 + 15513 .cfi_def_cfa_offset 0 + 15514 001a 7047 bx lr + 15515 .cfi_endproc + 15516 .LFE217: + 15518 .section .text.HAL_TIM_PWM_GetState,"ax",%progbits + 15519 .align 1 + 15520 .global HAL_TIM_PWM_GetState + 15521 .syntax unified + 15522 .thumb + 15523 .thumb_func + 15525 HAL_TIM_PWM_GetState: + 15526 .LFB218: +6543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +6545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Return the TIM PWM handle state. +6546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM handle +6547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL state +6548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +6549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim) +6550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 15527 .loc 1 6550 1 + 15528 .cfi_startproc + 15529 @ args = 0, pretend = 0, frame = 8 + 15530 @ frame_needed = 1, uses_anonymous_args = 0 + 15531 @ link register save eliminated. + 15532 0000 80B4 push {r7} + 15533 .cfi_def_cfa_offset 4 + 15534 .cfi_offset 7, -4 + 15535 0002 83B0 sub sp, sp, #12 + 15536 .cfi_def_cfa_offset 16 + 15537 0004 00AF add r7, sp, #0 + 15538 .cfi_def_cfa_register 7 + 15539 0006 7860 str r0, [r7, #4] +6551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return htim->State; + 15540 .loc 1 6551 14 + 15541 0008 7B68 ldr r3, [r7, #4] + 15542 000a 93F83D30 ldrb r3, [r3, #61] + 15543 000e DBB2 uxtb r3, r3 +6552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 15544 .loc 1 6552 1 + 15545 0010 1846 mov r0, r3 + 15546 0012 0C37 adds r7, r7, #12 + 15547 .cfi_def_cfa_offset 4 + 15548 0014 BD46 mov sp, r7 + ARM GAS /tmp/ccl4b9YO.s page 387 + + + 15549 .cfi_def_cfa_register 13 + 15550 @ sp needed + 15551 0016 5DF8047B ldr r7, [sp], #4 + 15552 .cfi_restore 7 + 15553 .cfi_def_cfa_offset 0 + 15554 001a 7047 bx lr + 15555 .cfi_endproc + 15556 .LFE218: + 15558 .section .text.HAL_TIM_IC_GetState,"ax",%progbits + 15559 .align 1 + 15560 .global HAL_TIM_IC_GetState + 15561 .syntax unified + 15562 .thumb + 15563 .thumb_func + 15565 HAL_TIM_IC_GetState: + 15566 .LFB219: +6553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +6555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Return the TIM Input Capture handle state. +6556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM IC handle +6557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL state +6558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +6559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim) +6560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 15567 .loc 1 6560 1 + 15568 .cfi_startproc + 15569 @ args = 0, pretend = 0, frame = 8 + 15570 @ frame_needed = 1, uses_anonymous_args = 0 + 15571 @ link register save eliminated. + 15572 0000 80B4 push {r7} + 15573 .cfi_def_cfa_offset 4 + 15574 .cfi_offset 7, -4 + 15575 0002 83B0 sub sp, sp, #12 + 15576 .cfi_def_cfa_offset 16 + 15577 0004 00AF add r7, sp, #0 + 15578 .cfi_def_cfa_register 7 + 15579 0006 7860 str r0, [r7, #4] +6561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return htim->State; + 15580 .loc 1 6561 14 + 15581 0008 7B68 ldr r3, [r7, #4] + 15582 000a 93F83D30 ldrb r3, [r3, #61] + 15583 000e DBB2 uxtb r3, r3 +6562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 15584 .loc 1 6562 1 + 15585 0010 1846 mov r0, r3 + 15586 0012 0C37 adds r7, r7, #12 + 15587 .cfi_def_cfa_offset 4 + 15588 0014 BD46 mov sp, r7 + 15589 .cfi_def_cfa_register 13 + 15590 @ sp needed + 15591 0016 5DF8047B ldr r7, [sp], #4 + 15592 .cfi_restore 7 + 15593 .cfi_def_cfa_offset 0 + 15594 001a 7047 bx lr + 15595 .cfi_endproc + 15596 .LFE219: + 15598 .section .text.HAL_TIM_OnePulse_GetState,"ax",%progbits + ARM GAS /tmp/ccl4b9YO.s page 388 + + + 15599 .align 1 + 15600 .global HAL_TIM_OnePulse_GetState + 15601 .syntax unified + 15602 .thumb + 15603 .thumb_func + 15605 HAL_TIM_OnePulse_GetState: + 15606 .LFB220: +6563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +6565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Return the TIM One Pulse Mode handle state. +6566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM OPM handle +6567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL state +6568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +6569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim) +6570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 15607 .loc 1 6570 1 + 15608 .cfi_startproc + 15609 @ args = 0, pretend = 0, frame = 8 + 15610 @ frame_needed = 1, uses_anonymous_args = 0 + 15611 @ link register save eliminated. + 15612 0000 80B4 push {r7} + 15613 .cfi_def_cfa_offset 4 + 15614 .cfi_offset 7, -4 + 15615 0002 83B0 sub sp, sp, #12 + 15616 .cfi_def_cfa_offset 16 + 15617 0004 00AF add r7, sp, #0 + 15618 .cfi_def_cfa_register 7 + 15619 0006 7860 str r0, [r7, #4] +6571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return htim->State; + 15620 .loc 1 6571 14 + 15621 0008 7B68 ldr r3, [r7, #4] + 15622 000a 93F83D30 ldrb r3, [r3, #61] + 15623 000e DBB2 uxtb r3, r3 +6572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 15624 .loc 1 6572 1 + 15625 0010 1846 mov r0, r3 + 15626 0012 0C37 adds r7, r7, #12 + 15627 .cfi_def_cfa_offset 4 + 15628 0014 BD46 mov sp, r7 + 15629 .cfi_def_cfa_register 13 + 15630 @ sp needed + 15631 0016 5DF8047B ldr r7, [sp], #4 + 15632 .cfi_restore 7 + 15633 .cfi_def_cfa_offset 0 + 15634 001a 7047 bx lr + 15635 .cfi_endproc + 15636 .LFE220: + 15638 .section .text.HAL_TIM_Encoder_GetState,"ax",%progbits + 15639 .align 1 + 15640 .global HAL_TIM_Encoder_GetState + 15641 .syntax unified + 15642 .thumb + 15643 .thumb_func + 15645 HAL_TIM_Encoder_GetState: + 15646 .LFB221: +6573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** + ARM GAS /tmp/ccl4b9YO.s page 389 + + +6575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Return the TIM Encoder Mode handle state. +6576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM Encoder Interface handle +6577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval HAL state +6578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +6579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim) +6580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 15647 .loc 1 6580 1 + 15648 .cfi_startproc + 15649 @ args = 0, pretend = 0, frame = 8 + 15650 @ frame_needed = 1, uses_anonymous_args = 0 + 15651 @ link register save eliminated. + 15652 0000 80B4 push {r7} + 15653 .cfi_def_cfa_offset 4 + 15654 .cfi_offset 7, -4 + 15655 0002 83B0 sub sp, sp, #12 + 15656 .cfi_def_cfa_offset 16 + 15657 0004 00AF add r7, sp, #0 + 15658 .cfi_def_cfa_register 7 + 15659 0006 7860 str r0, [r7, #4] +6581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return htim->State; + 15660 .loc 1 6581 14 + 15661 0008 7B68 ldr r3, [r7, #4] + 15662 000a 93F83D30 ldrb r3, [r3, #61] + 15663 000e DBB2 uxtb r3, r3 +6582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 15664 .loc 1 6582 1 + 15665 0010 1846 mov r0, r3 + 15666 0012 0C37 adds r7, r7, #12 + 15667 .cfi_def_cfa_offset 4 + 15668 0014 BD46 mov sp, r7 + 15669 .cfi_def_cfa_register 13 + 15670 @ sp needed + 15671 0016 5DF8047B ldr r7, [sp], #4 + 15672 .cfi_restore 7 + 15673 .cfi_def_cfa_offset 0 + 15674 001a 7047 bx lr + 15675 .cfi_endproc + 15676 .LFE221: + 15678 .section .text.HAL_TIM_GetActiveChannel,"ax",%progbits + 15679 .align 1 + 15680 .global HAL_TIM_GetActiveChannel + 15681 .syntax unified + 15682 .thumb + 15683 .thumb_func + 15685 HAL_TIM_GetActiveChannel: + 15686 .LFB222: +6583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +6585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Return the TIM Encoder Mode handle state. +6586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM handle +6587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval Active channel +6588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +6589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim) +6590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 15687 .loc 1 6590 1 + 15688 .cfi_startproc + 15689 @ args = 0, pretend = 0, frame = 8 + ARM GAS /tmp/ccl4b9YO.s page 390 + + + 15690 @ frame_needed = 1, uses_anonymous_args = 0 + 15691 @ link register save eliminated. + 15692 0000 80B4 push {r7} + 15693 .cfi_def_cfa_offset 4 + 15694 .cfi_offset 7, -4 + 15695 0002 83B0 sub sp, sp, #12 + 15696 .cfi_def_cfa_offset 16 + 15697 0004 00AF add r7, sp, #0 + 15698 .cfi_def_cfa_register 7 + 15699 0006 7860 str r0, [r7, #4] +6591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return htim->Channel; + 15700 .loc 1 6591 14 + 15701 0008 7B68 ldr r3, [r7, #4] + 15702 000a 1B7F ldrb r3, [r3, #28] @ zero_extendqisi2 +6592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 15703 .loc 1 6592 1 + 15704 000c 1846 mov r0, r3 + 15705 000e 0C37 adds r7, r7, #12 + 15706 .cfi_def_cfa_offset 4 + 15707 0010 BD46 mov sp, r7 + 15708 .cfi_def_cfa_register 13 + 15709 @ sp needed + 15710 0012 5DF8047B ldr r7, [sp], #4 + 15711 .cfi_restore 7 + 15712 .cfi_def_cfa_offset 0 + 15713 0016 7047 bx lr + 15714 .cfi_endproc + 15715 .LFE222: + 15717 .section .text.HAL_TIM_GetChannelState,"ax",%progbits + 15718 .align 1 + 15719 .global HAL_TIM_GetChannelState + 15720 .syntax unified + 15721 .thumb + 15722 .thumb_func + 15724 HAL_TIM_GetChannelState: + 15725 .LFB223: +6593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +6595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Return actual state of the TIM channel. +6596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM handle +6597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param Channel TIM Channel +6598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +6599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 +6600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 +6601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 +6602:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 +6603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_5: TIM Channel 5 +6604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_6: TIM Channel 6 +6605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval TIM Channel state +6606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +6607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channe +6608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 15726 .loc 1 6608 1 + 15727 .cfi_startproc + 15728 @ args = 0, pretend = 0, frame = 16 + 15729 @ frame_needed = 1, uses_anonymous_args = 0 + 15730 @ link register save eliminated. + ARM GAS /tmp/ccl4b9YO.s page 391 + + + 15731 0000 80B4 push {r7} + 15732 .cfi_def_cfa_offset 4 + 15733 .cfi_offset 7, -4 + 15734 0002 85B0 sub sp, sp, #20 + 15735 .cfi_def_cfa_offset 24 + 15736 0004 00AF add r7, sp, #0 + 15737 .cfi_def_cfa_register 7 + 15738 0006 7860 str r0, [r7, #4] + 15739 0008 3960 str r1, [r7] +6609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_ChannelStateTypeDef channel_state; +6610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +6612:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); +6613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + 15740 .loc 1 6614 19 + 15741 000a 3B68 ldr r3, [r7] + 15742 000c 002B cmp r3, #0 + 15743 000e 04D1 bne .L1158 + 15744 .loc 1 6614 19 is_stmt 0 discriminator 1 + 15745 0010 7B68 ldr r3, [r7, #4] + 15746 0012 93F83E30 ldrb r3, [r3, #62] + 15747 0016 DBB2 uxtb r3, r3 + 15748 0018 23E0 b .L1159 + 15749 .L1158: + 15750 .loc 1 6614 19 discriminator 2 + 15751 001a 3B68 ldr r3, [r7] + 15752 001c 042B cmp r3, #4 + 15753 001e 04D1 bne .L1160 + 15754 .loc 1 6614 19 discriminator 4 + 15755 0020 7B68 ldr r3, [r7, #4] + 15756 0022 93F83F30 ldrb r3, [r3, #63] + 15757 0026 DBB2 uxtb r3, r3 + 15758 0028 1BE0 b .L1159 + 15759 .L1160: + 15760 .loc 1 6614 19 discriminator 5 + 15761 002a 3B68 ldr r3, [r7] + 15762 002c 082B cmp r3, #8 + 15763 002e 04D1 bne .L1162 + 15764 .loc 1 6614 19 discriminator 7 + 15765 0030 7B68 ldr r3, [r7, #4] + 15766 0032 93F84030 ldrb r3, [r3, #64] + 15767 0036 DBB2 uxtb r3, r3 + 15768 0038 13E0 b .L1159 + 15769 .L1162: + 15770 .loc 1 6614 19 discriminator 8 + 15771 003a 3B68 ldr r3, [r7] + 15772 003c 0C2B cmp r3, #12 + 15773 003e 04D1 bne .L1164 + 15774 .loc 1 6614 19 discriminator 10 + 15775 0040 7B68 ldr r3, [r7, #4] + 15776 0042 93F84130 ldrb r3, [r3, #65] + 15777 0046 DBB2 uxtb r3, r3 + 15778 0048 0BE0 b .L1159 + 15779 .L1164: + 15780 .loc 1 6614 19 discriminator 11 + 15781 004a 3B68 ldr r3, [r7] + ARM GAS /tmp/ccl4b9YO.s page 392 + + + 15782 004c 102B cmp r3, #16 + 15783 004e 04D1 bne .L1166 + 15784 .loc 1 6614 19 discriminator 13 + 15785 0050 7B68 ldr r3, [r7, #4] + 15786 0052 93F84230 ldrb r3, [r3, #66] + 15787 0056 DBB2 uxtb r3, r3 + 15788 0058 03E0 b .L1159 + 15789 .L1166: + 15790 .loc 1 6614 19 discriminator 14 + 15791 005a 7B68 ldr r3, [r7, #4] + 15792 005c 93F84330 ldrb r3, [r3, #67] + 15793 0060 DBB2 uxtb r3, r3 + 15794 .L1159: + 15795 .loc 1 6614 17 is_stmt 1 discriminator 20 + 15796 0062 FB73 strb r3, [r7, #15] +6615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return channel_state; + 15797 .loc 1 6616 10 + 15798 0064 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 +6617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 15799 .loc 1 6617 1 + 15800 0066 1846 mov r0, r3 + 15801 0068 1437 adds r7, r7, #20 + 15802 .cfi_def_cfa_offset 4 + 15803 006a BD46 mov sp, r7 + 15804 .cfi_def_cfa_register 13 + 15805 @ sp needed + 15806 006c 5DF8047B ldr r7, [sp], #4 + 15807 .cfi_restore 7 + 15808 .cfi_def_cfa_offset 0 + 15809 0070 7047 bx lr + 15810 .cfi_endproc + 15811 .LFE223: + 15813 .section .text.HAL_TIM_DMABurstState,"ax",%progbits + 15814 .align 1 + 15815 .global HAL_TIM_DMABurstState + 15816 .syntax unified + 15817 .thumb + 15818 .thumb_func + 15820 HAL_TIM_DMABurstState: + 15821 .LFB224: +6618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +6620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Return actual state of a DMA burst operation. +6621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM handle +6622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval DMA burst state +6623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +6624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim) +6625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 15822 .loc 1 6625 1 + 15823 .cfi_startproc + 15824 @ args = 0, pretend = 0, frame = 8 + 15825 @ frame_needed = 1, uses_anonymous_args = 0 + 15826 @ link register save eliminated. + 15827 0000 80B4 push {r7} + 15828 .cfi_def_cfa_offset 4 + 15829 .cfi_offset 7, -4 + ARM GAS /tmp/ccl4b9YO.s page 393 + + + 15830 0002 83B0 sub sp, sp, #12 + 15831 .cfi_def_cfa_offset 16 + 15832 0004 00AF add r7, sp, #0 + 15833 .cfi_def_cfa_register 7 + 15834 0006 7860 str r0, [r7, #4] +6626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +6627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); +6628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return htim->DMABurstState; + 15835 .loc 1 6629 14 + 15836 0008 7B68 ldr r3, [r7, #4] + 15837 000a 93F84830 ldrb r3, [r3, #72] + 15838 000e DBB2 uxtb r3, r3 +6630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 15839 .loc 1 6630 1 + 15840 0010 1846 mov r0, r3 + 15841 0012 0C37 adds r7, r7, #12 + 15842 .cfi_def_cfa_offset 4 + 15843 0014 BD46 mov sp, r7 + 15844 .cfi_def_cfa_register 13 + 15845 @ sp needed + 15846 0016 5DF8047B ldr r7, [sp], #4 + 15847 .cfi_restore 7 + 15848 .cfi_def_cfa_offset 0 + 15849 001a 7047 bx lr + 15850 .cfi_endproc + 15851 .LFE224: + 15853 .section .text.TIM_DMAError,"ax",%progbits + 15854 .align 1 + 15855 .global TIM_DMAError + 15856 .syntax unified + 15857 .thumb + 15858 .thumb_func + 15860 TIM_DMAError: + 15861 .LFB225: +6631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +6633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @} +6634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +6635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +6637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @} +6638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +6639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** @defgroup TIM_Private_Functions TIM Private Functions +6641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @{ +6642:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +6643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +6645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief TIM DMA error callback +6646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param hdma pointer to DMA handle. +6647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval None +6648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +6649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** void TIM_DMAError(DMA_HandleTypeDef *hdma) +6650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 15862 .loc 1 6650 1 + 15863 .cfi_startproc + ARM GAS /tmp/ccl4b9YO.s page 394 + + + 15864 @ args = 0, pretend = 0, frame = 16 + 15865 @ frame_needed = 1, uses_anonymous_args = 0 + 15866 0000 80B5 push {r7, lr} + 15867 .cfi_def_cfa_offset 8 + 15868 .cfi_offset 7, -8 + 15869 .cfi_offset 14, -4 + 15870 0002 84B0 sub sp, sp, #16 + 15871 .cfi_def_cfa_offset 24 + 15872 0004 00AF add r7, sp, #0 + 15873 .cfi_def_cfa_register 7 + 15874 0006 7860 str r0, [r7, #4] +6651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + 15875 .loc 1 6651 22 + 15876 0008 7B68 ldr r3, [r7, #4] + 15877 000a 5B6A ldr r3, [r3, #36] + 15878 000c FB60 str r3, [r7, #12] +6652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + 15879 .loc 1 6653 25 + 15880 000e FB68 ldr r3, [r7, #12] + 15881 0010 5B6A ldr r3, [r3, #36] + 15882 .loc 1 6653 6 + 15883 0012 7A68 ldr r2, [r7, #4] + 15884 0014 9A42 cmp r2, r3 + 15885 0016 07D1 bne .L1172 +6654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +6655:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + 15886 .loc 1 6655 19 + 15887 0018 FB68 ldr r3, [r7, #12] + 15888 001a 0122 movs r2, #1 + 15889 001c 1A77 strb r2, [r3, #28] +6656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 15890 .loc 1 6656 5 + 15891 001e FB68 ldr r3, [r7, #12] + 15892 0020 0122 movs r2, #1 + 15893 0022 83F83E20 strb r2, [r3, #62] + 15894 0026 2AE0 b .L1173 + 15895 .L1172: +6657:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +6658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + 15896 .loc 1 6658 30 + 15897 0028 FB68 ldr r3, [r7, #12] + 15898 002a 9B6A ldr r3, [r3, #40] + 15899 .loc 1 6658 11 + 15900 002c 7A68 ldr r2, [r7, #4] + 15901 002e 9A42 cmp r2, r3 + 15902 0030 07D1 bne .L1174 +6659:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +6660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + 15903 .loc 1 6660 19 + 15904 0032 FB68 ldr r3, [r7, #12] + 15905 0034 0222 movs r2, #2 + 15906 0036 1A77 strb r2, [r3, #28] +6661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 15907 .loc 1 6661 5 + 15908 0038 FB68 ldr r3, [r7, #12] + 15909 003a 0122 movs r2, #1 + ARM GAS /tmp/ccl4b9YO.s page 395 + + + 15910 003c 83F83F20 strb r2, [r3, #63] + 15911 0040 1DE0 b .L1173 + 15912 .L1174: +6662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +6663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + 15913 .loc 1 6663 30 + 15914 0042 FB68 ldr r3, [r7, #12] + 15915 0044 DB6A ldr r3, [r3, #44] + 15916 .loc 1 6663 11 + 15917 0046 7A68 ldr r2, [r7, #4] + 15918 0048 9A42 cmp r2, r3 + 15919 004a 07D1 bne .L1175 +6664:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +6665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + 15920 .loc 1 6665 19 + 15921 004c FB68 ldr r3, [r7, #12] + 15922 004e 0422 movs r2, #4 + 15923 0050 1A77 strb r2, [r3, #28] +6666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + 15924 .loc 1 6666 5 + 15925 0052 FB68 ldr r3, [r7, #12] + 15926 0054 0122 movs r2, #1 + 15927 0056 83F84020 strb r2, [r3, #64] + 15928 005a 10E0 b .L1173 + 15929 .L1175: +6667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +6668:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + 15930 .loc 1 6668 30 + 15931 005c FB68 ldr r3, [r7, #12] + 15932 005e 1B6B ldr r3, [r3, #48] + 15933 .loc 1 6668 11 + 15934 0060 7A68 ldr r2, [r7, #4] + 15935 0062 9A42 cmp r2, r3 + 15936 0064 07D1 bne .L1176 +6669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +6670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + 15937 .loc 1 6670 19 + 15938 0066 FB68 ldr r3, [r7, #12] + 15939 0068 0822 movs r2, #8 + 15940 006a 1A77 strb r2, [r3, #28] +6671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + 15941 .loc 1 6671 5 + 15942 006c FB68 ldr r3, [r7, #12] + 15943 006e 0122 movs r2, #1 + 15944 0070 83F84120 strb r2, [r3, #65] + 15945 0074 03E0 b .L1173 + 15946 .L1176: +6672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +6673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +6674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +6675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; + 15947 .loc 1 6675 17 + 15948 0076 FB68 ldr r3, [r7, #12] + 15949 0078 0122 movs r2, #1 + 15950 007a 83F83D20 strb r2, [r3, #61] + 15951 .L1173: +6676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + ARM GAS /tmp/ccl4b9YO.s page 396 + + +6677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +6679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->ErrorCallback(htim); +6680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #else +6681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_ErrorCallback(htim); + 15952 .loc 1 6681 3 + 15953 007e F868 ldr r0, [r7, #12] + 15954 0080 FFF7FEFF bl HAL_TIM_ErrorCallback +6682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +6683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 15955 .loc 1 6684 17 + 15956 0084 FB68 ldr r3, [r7, #12] + 15957 0086 0022 movs r2, #0 + 15958 0088 1A77 strb r2, [r3, #28] +6685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 15959 .loc 1 6685 1 + 15960 008a 00BF nop + 15961 008c 1037 adds r7, r7, #16 + 15962 .cfi_def_cfa_offset 8 + 15963 008e BD46 mov sp, r7 + 15964 .cfi_def_cfa_register 13 + 15965 @ sp needed + 15966 0090 80BD pop {r7, pc} + 15967 .cfi_endproc + 15968 .LFE225: + 15970 .section .text.TIM_DMADelayPulseCplt,"ax",%progbits + 15971 .align 1 + 15972 .syntax unified + 15973 .thumb + 15974 .thumb_func + 15976 TIM_DMADelayPulseCplt: + 15977 .LFB226: +6686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +6688:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief TIM DMA Delay Pulse complete callback. +6689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param hdma pointer to DMA handle. +6690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval None +6691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +6692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) +6693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 15978 .loc 1 6693 1 + 15979 .cfi_startproc + 15980 @ args = 0, pretend = 0, frame = 16 + 15981 @ frame_needed = 1, uses_anonymous_args = 0 + 15982 0000 80B5 push {r7, lr} + 15983 .cfi_def_cfa_offset 8 + 15984 .cfi_offset 7, -8 + 15985 .cfi_offset 14, -4 + 15986 0002 84B0 sub sp, sp, #16 + 15987 .cfi_def_cfa_offset 24 + 15988 0004 00AF add r7, sp, #0 + 15989 .cfi_def_cfa_register 7 + 15990 0006 7860 str r0, [r7, #4] +6694:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + 15991 .loc 1 6694 22 + 15992 0008 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/ccl4b9YO.s page 397 + + + 15993 000a 5B6A ldr r3, [r3, #36] + 15994 000c FB60 str r3, [r7, #12] +6695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + 15995 .loc 1 6696 25 + 15996 000e FB68 ldr r3, [r7, #12] + 15997 0010 5B6A ldr r3, [r3, #36] + 15998 .loc 1 6696 6 + 15999 0012 7A68 ldr r2, [r7, #4] + 16000 0014 9A42 cmp r2, r3 + 16001 0016 0BD1 bne .L1178 +6697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +6698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + 16002 .loc 1 6698 19 + 16003 0018 FB68 ldr r3, [r7, #12] + 16004 001a 0122 movs r2, #1 + 16005 001c 1A77 strb r2, [r3, #28] +6699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6700:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (hdma->Init.Mode == DMA_NORMAL) + 16006 .loc 1 6700 19 + 16007 001e 7B68 ldr r3, [r7, #4] + 16008 0020 9B69 ldr r3, [r3, #24] + 16009 .loc 1 6700 8 + 16010 0022 002B cmp r3, #0 + 16011 0024 36D1 bne .L1179 +6701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +6702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 16012 .loc 1 6702 7 + 16013 0026 FB68 ldr r3, [r7, #12] + 16014 0028 0122 movs r2, #1 + 16015 002a 83F83E20 strb r2, [r3, #62] + 16016 002e 31E0 b .L1179 + 16017 .L1178: +6703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +6704:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +6705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + 16018 .loc 1 6705 30 + 16019 0030 FB68 ldr r3, [r7, #12] + 16020 0032 9B6A ldr r3, [r3, #40] + 16021 .loc 1 6705 11 + 16022 0034 7A68 ldr r2, [r7, #4] + 16023 0036 9A42 cmp r2, r3 + 16024 0038 0BD1 bne .L1180 +6706:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +6707:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + 16025 .loc 1 6707 19 + 16026 003a FB68 ldr r3, [r7, #12] + 16027 003c 0222 movs r2, #2 + 16028 003e 1A77 strb r2, [r3, #28] +6708:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (hdma->Init.Mode == DMA_NORMAL) + 16029 .loc 1 6709 19 + 16030 0040 7B68 ldr r3, [r7, #4] + 16031 0042 9B69 ldr r3, [r3, #24] + 16032 .loc 1 6709 8 + 16033 0044 002B cmp r3, #0 + 16034 0046 25D1 bne .L1179 + ARM GAS /tmp/ccl4b9YO.s page 398 + + +6710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +6711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 16035 .loc 1 6711 7 + 16036 0048 FB68 ldr r3, [r7, #12] + 16037 004a 0122 movs r2, #1 + 16038 004c 83F83F20 strb r2, [r3, #63] + 16039 0050 20E0 b .L1179 + 16040 .L1180: +6712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +6713:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +6714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + 16041 .loc 1 6714 30 + 16042 0052 FB68 ldr r3, [r7, #12] + 16043 0054 DB6A ldr r3, [r3, #44] + 16044 .loc 1 6714 11 + 16045 0056 7A68 ldr r2, [r7, #4] + 16046 0058 9A42 cmp r2, r3 + 16047 005a 0BD1 bne .L1181 +6715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +6716:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + 16048 .loc 1 6716 19 + 16049 005c FB68 ldr r3, [r7, #12] + 16050 005e 0422 movs r2, #4 + 16051 0060 1A77 strb r2, [r3, #28] +6717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6718:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (hdma->Init.Mode == DMA_NORMAL) + 16052 .loc 1 6718 19 + 16053 0062 7B68 ldr r3, [r7, #4] + 16054 0064 9B69 ldr r3, [r3, #24] + 16055 .loc 1 6718 8 + 16056 0066 002B cmp r3, #0 + 16057 0068 14D1 bne .L1179 +6719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +6720:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + 16058 .loc 1 6720 7 + 16059 006a FB68 ldr r3, [r7, #12] + 16060 006c 0122 movs r2, #1 + 16061 006e 83F84020 strb r2, [r3, #64] + 16062 0072 0FE0 b .L1179 + 16063 .L1181: +6721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +6722:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +6723:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + 16064 .loc 1 6723 30 + 16065 0074 FB68 ldr r3, [r7, #12] + 16066 0076 1B6B ldr r3, [r3, #48] + 16067 .loc 1 6723 11 + 16068 0078 7A68 ldr r2, [r7, #4] + 16069 007a 9A42 cmp r2, r3 + 16070 007c 0AD1 bne .L1179 +6724:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +6725:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + 16071 .loc 1 6725 19 + 16072 007e FB68 ldr r3, [r7, #12] + 16073 0080 0822 movs r2, #8 + 16074 0082 1A77 strb r2, [r3, #28] +6726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + ARM GAS /tmp/ccl4b9YO.s page 399 + + +6727:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (hdma->Init.Mode == DMA_NORMAL) + 16075 .loc 1 6727 19 + 16076 0084 7B68 ldr r3, [r7, #4] + 16077 0086 9B69 ldr r3, [r3, #24] + 16078 .loc 1 6727 8 + 16079 0088 002B cmp r3, #0 + 16080 008a 03D1 bne .L1179 +6728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +6729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + 16081 .loc 1 6729 7 + 16082 008c FB68 ldr r3, [r7, #12] + 16083 008e 0122 movs r2, #1 + 16084 0090 83F84120 strb r2, [r3, #65] + 16085 .L1179: +6730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +6731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +6732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +6733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +6734:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* nothing to do */ +6735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +6736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6737:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +6738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->PWM_PulseFinishedCallback(htim); +6739:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #else +6740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_PWM_PulseFinishedCallback(htim); + 16086 .loc 1 6740 3 + 16087 0094 F868 ldr r0, [r7, #12] + 16088 0096 FFF7FEFF bl HAL_TIM_PWM_PulseFinishedCallback +6741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +6742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6743:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 16089 .loc 1 6743 17 + 16090 009a FB68 ldr r3, [r7, #12] + 16091 009c 0022 movs r2, #0 + 16092 009e 1A77 strb r2, [r3, #28] +6744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 16093 .loc 1 6744 1 + 16094 00a0 00BF nop + 16095 00a2 1037 adds r7, r7, #16 + 16096 .cfi_def_cfa_offset 8 + 16097 00a4 BD46 mov sp, r7 + 16098 .cfi_def_cfa_register 13 + 16099 @ sp needed + 16100 00a6 80BD pop {r7, pc} + 16101 .cfi_endproc + 16102 .LFE226: + 16104 .section .text.TIM_DMADelayPulseHalfCplt,"ax",%progbits + 16105 .align 1 + 16106 .global TIM_DMADelayPulseHalfCplt + 16107 .syntax unified + 16108 .thumb + 16109 .thumb_func + 16111 TIM_DMADelayPulseHalfCplt: + 16112 .LFB227: +6745:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6746:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +6747:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief TIM DMA Delay Pulse half complete callback. + ARM GAS /tmp/ccl4b9YO.s page 400 + + +6748:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param hdma pointer to DMA handle. +6749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval None +6750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +6751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma) +6752:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 16113 .loc 1 6752 1 + 16114 .cfi_startproc + 16115 @ args = 0, pretend = 0, frame = 16 + 16116 @ frame_needed = 1, uses_anonymous_args = 0 + 16117 0000 80B5 push {r7, lr} + 16118 .cfi_def_cfa_offset 8 + 16119 .cfi_offset 7, -8 + 16120 .cfi_offset 14, -4 + 16121 0002 84B0 sub sp, sp, #16 + 16122 .cfi_def_cfa_offset 24 + 16123 0004 00AF add r7, sp, #0 + 16124 .cfi_def_cfa_register 7 + 16125 0006 7860 str r0, [r7, #4] +6753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + 16126 .loc 1 6753 22 + 16127 0008 7B68 ldr r3, [r7, #4] + 16128 000a 5B6A ldr r3, [r3, #36] + 16129 000c FB60 str r3, [r7, #12] +6754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6755:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + 16130 .loc 1 6755 25 + 16131 000e FB68 ldr r3, [r7, #12] + 16132 0010 5B6A ldr r3, [r3, #36] + 16133 .loc 1 6755 6 + 16134 0012 7A68 ldr r2, [r7, #4] + 16135 0014 9A42 cmp r2, r3 + 16136 0016 03D1 bne .L1183 +6756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +6757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + 16137 .loc 1 6757 19 + 16138 0018 FB68 ldr r3, [r7, #12] + 16139 001a 0122 movs r2, #1 + 16140 001c 1A77 strb r2, [r3, #28] + 16141 001e 19E0 b .L1184 + 16142 .L1183: +6758:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +6759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + 16143 .loc 1 6759 30 + 16144 0020 FB68 ldr r3, [r7, #12] + 16145 0022 9B6A ldr r3, [r3, #40] + 16146 .loc 1 6759 11 + 16147 0024 7A68 ldr r2, [r7, #4] + 16148 0026 9A42 cmp r2, r3 + 16149 0028 03D1 bne .L1185 +6760:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +6761:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + 16150 .loc 1 6761 19 + 16151 002a FB68 ldr r3, [r7, #12] + 16152 002c 0222 movs r2, #2 + 16153 002e 1A77 strb r2, [r3, #28] + 16154 0030 10E0 b .L1184 + 16155 .L1185: + ARM GAS /tmp/ccl4b9YO.s page 401 + + +6762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +6763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + 16156 .loc 1 6763 30 + 16157 0032 FB68 ldr r3, [r7, #12] + 16158 0034 DB6A ldr r3, [r3, #44] + 16159 .loc 1 6763 11 + 16160 0036 7A68 ldr r2, [r7, #4] + 16161 0038 9A42 cmp r2, r3 + 16162 003a 03D1 bne .L1186 +6764:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +6765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + 16163 .loc 1 6765 19 + 16164 003c FB68 ldr r3, [r7, #12] + 16165 003e 0422 movs r2, #4 + 16166 0040 1A77 strb r2, [r3, #28] + 16167 0042 07E0 b .L1184 + 16168 .L1186: +6766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +6767:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + 16169 .loc 1 6767 30 + 16170 0044 FB68 ldr r3, [r7, #12] + 16171 0046 1B6B ldr r3, [r3, #48] + 16172 .loc 1 6767 11 + 16173 0048 7A68 ldr r2, [r7, #4] + 16174 004a 9A42 cmp r2, r3 + 16175 004c 02D1 bne .L1184 +6768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +6769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + 16176 .loc 1 6769 19 + 16177 004e FB68 ldr r3, [r7, #12] + 16178 0050 0822 movs r2, #8 + 16179 0052 1A77 strb r2, [r3, #28] + 16180 .L1184: +6770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +6771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +6772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +6773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* nothing to do */ +6774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +6775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +6777:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->PWM_PulseFinishedHalfCpltCallback(htim); +6778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #else +6779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim); + 16181 .loc 1 6779 3 + 16182 0054 F868 ldr r0, [r7, #12] + 16183 0056 FFF7FEFF bl HAL_TIM_PWM_PulseFinishedHalfCpltCallback +6780:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +6781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6782:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 16184 .loc 1 6782 17 + 16185 005a FB68 ldr r3, [r7, #12] + 16186 005c 0022 movs r2, #0 + 16187 005e 1A77 strb r2, [r3, #28] +6783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 16188 .loc 1 6783 1 + 16189 0060 00BF nop + 16190 0062 1037 adds r7, r7, #16 + ARM GAS /tmp/ccl4b9YO.s page 402 + + + 16191 .cfi_def_cfa_offset 8 + 16192 0064 BD46 mov sp, r7 + 16193 .cfi_def_cfa_register 13 + 16194 @ sp needed + 16195 0066 80BD pop {r7, pc} + 16196 .cfi_endproc + 16197 .LFE227: + 16199 .section .text.TIM_DMACaptureCplt,"ax",%progbits + 16200 .align 1 + 16201 .global TIM_DMACaptureCplt + 16202 .syntax unified + 16203 .thumb + 16204 .thumb_func + 16206 TIM_DMACaptureCplt: + 16207 .LFB228: +6784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +6786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief TIM DMA Capture complete callback. +6787:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param hdma pointer to DMA handle. +6788:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval None +6789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +6790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) +6791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 16208 .loc 1 6791 1 + 16209 .cfi_startproc + 16210 @ args = 0, pretend = 0, frame = 16 + 16211 @ frame_needed = 1, uses_anonymous_args = 0 + 16212 0000 80B5 push {r7, lr} + 16213 .cfi_def_cfa_offset 8 + 16214 .cfi_offset 7, -8 + 16215 .cfi_offset 14, -4 + 16216 0002 84B0 sub sp, sp, #16 + 16217 .cfi_def_cfa_offset 24 + 16218 0004 00AF add r7, sp, #0 + 16219 .cfi_def_cfa_register 7 + 16220 0006 7860 str r0, [r7, #4] +6792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + 16221 .loc 1 6792 22 + 16222 0008 7B68 ldr r3, [r7, #4] + 16223 000a 5B6A ldr r3, [r3, #36] + 16224 000c FB60 str r3, [r7, #12] +6793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + 16225 .loc 1 6794 25 + 16226 000e FB68 ldr r3, [r7, #12] + 16227 0010 5B6A ldr r3, [r3, #36] + 16228 .loc 1 6794 6 + 16229 0012 7A68 ldr r2, [r7, #4] + 16230 0014 9A42 cmp r2, r3 + 16231 0016 0FD1 bne .L1188 +6795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +6796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + 16232 .loc 1 6796 19 + 16233 0018 FB68 ldr r3, [r7, #12] + 16234 001a 0122 movs r2, #1 + 16235 001c 1A77 strb r2, [r3, #28] +6797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + ARM GAS /tmp/ccl4b9YO.s page 403 + + +6798:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (hdma->Init.Mode == DMA_NORMAL) + 16236 .loc 1 6798 19 + 16237 001e 7B68 ldr r3, [r7, #4] + 16238 0020 9B69 ldr r3, [r3, #24] + 16239 .loc 1 6798 8 + 16240 0022 002B cmp r3, #0 + 16241 0024 46D1 bne .L1189 +6799:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +6800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 16242 .loc 1 6800 7 + 16243 0026 FB68 ldr r3, [r7, #12] + 16244 0028 0122 movs r2, #1 + 16245 002a 83F83E20 strb r2, [r3, #62] +6801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 16246 .loc 1 6801 7 + 16247 002e FB68 ldr r3, [r7, #12] + 16248 0030 0122 movs r2, #1 + 16249 0032 83F84420 strb r2, [r3, #68] + 16250 0036 3DE0 b .L1189 + 16251 .L1188: +6802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +6803:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +6804:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + 16252 .loc 1 6804 30 + 16253 0038 FB68 ldr r3, [r7, #12] + 16254 003a 9B6A ldr r3, [r3, #40] + 16255 .loc 1 6804 11 + 16256 003c 7A68 ldr r2, [r7, #4] + 16257 003e 9A42 cmp r2, r3 + 16258 0040 0FD1 bne .L1190 +6805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +6806:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + 16259 .loc 1 6806 19 + 16260 0042 FB68 ldr r3, [r7, #12] + 16261 0044 0222 movs r2, #2 + 16262 0046 1A77 strb r2, [r3, #28] +6807:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6808:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (hdma->Init.Mode == DMA_NORMAL) + 16263 .loc 1 6808 19 + 16264 0048 7B68 ldr r3, [r7, #4] + 16265 004a 9B69 ldr r3, [r3, #24] + 16266 .loc 1 6808 8 + 16267 004c 002B cmp r3, #0 + 16268 004e 31D1 bne .L1189 +6809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +6810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 16269 .loc 1 6810 7 + 16270 0050 FB68 ldr r3, [r7, #12] + 16271 0052 0122 movs r2, #1 + 16272 0054 83F83F20 strb r2, [r3, #63] +6811:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 16273 .loc 1 6811 7 + 16274 0058 FB68 ldr r3, [r7, #12] + 16275 005a 0122 movs r2, #1 + 16276 005c 83F84520 strb r2, [r3, #69] + 16277 0060 28E0 b .L1189 + 16278 .L1190: + ARM GAS /tmp/ccl4b9YO.s page 404 + + +6812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +6813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +6814:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + 16279 .loc 1 6814 30 + 16280 0062 FB68 ldr r3, [r7, #12] + 16281 0064 DB6A ldr r3, [r3, #44] + 16282 .loc 1 6814 11 + 16283 0066 7A68 ldr r2, [r7, #4] + 16284 0068 9A42 cmp r2, r3 + 16285 006a 0FD1 bne .L1191 +6815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +6816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + 16286 .loc 1 6816 19 + 16287 006c FB68 ldr r3, [r7, #12] + 16288 006e 0422 movs r2, #4 + 16289 0070 1A77 strb r2, [r3, #28] +6817:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6818:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (hdma->Init.Mode == DMA_NORMAL) + 16290 .loc 1 6818 19 + 16291 0072 7B68 ldr r3, [r7, #4] + 16292 0074 9B69 ldr r3, [r3, #24] + 16293 .loc 1 6818 8 + 16294 0076 002B cmp r3, #0 + 16295 0078 1CD1 bne .L1189 +6819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +6820:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + 16296 .loc 1 6820 7 + 16297 007a FB68 ldr r3, [r7, #12] + 16298 007c 0122 movs r2, #1 + 16299 007e 83F84020 strb r2, [r3, #64] +6821:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + 16300 .loc 1 6821 7 + 16301 0082 FB68 ldr r3, [r7, #12] + 16302 0084 0122 movs r2, #1 + 16303 0086 83F84620 strb r2, [r3, #70] + 16304 008a 13E0 b .L1189 + 16305 .L1191: +6822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +6823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +6824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + 16306 .loc 1 6824 30 + 16307 008c FB68 ldr r3, [r7, #12] + 16308 008e 1B6B ldr r3, [r3, #48] + 16309 .loc 1 6824 11 + 16310 0090 7A68 ldr r2, [r7, #4] + 16311 0092 9A42 cmp r2, r3 + 16312 0094 0ED1 bne .L1189 +6825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +6826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + 16313 .loc 1 6826 19 + 16314 0096 FB68 ldr r3, [r7, #12] + 16315 0098 0822 movs r2, #8 + 16316 009a 1A77 strb r2, [r3, #28] +6827:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6828:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (hdma->Init.Mode == DMA_NORMAL) + 16317 .loc 1 6828 19 + 16318 009c 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/ccl4b9YO.s page 405 + + + 16319 009e 9B69 ldr r3, [r3, #24] + 16320 .loc 1 6828 8 + 16321 00a0 002B cmp r3, #0 + 16322 00a2 07D1 bne .L1189 +6829:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +6830:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + 16323 .loc 1 6830 7 + 16324 00a4 FB68 ldr r3, [r7, #12] + 16325 00a6 0122 movs r2, #1 + 16326 00a8 83F84120 strb r2, [r3, #65] +6831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + 16327 .loc 1 6831 7 + 16328 00ac FB68 ldr r3, [r7, #12] + 16329 00ae 0122 movs r2, #1 + 16330 00b0 83F84720 strb r2, [r3, #71] + 16331 .L1189: +6832:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +6833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +6834:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +6835:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +6836:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* nothing to do */ +6837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +6838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +6840:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->IC_CaptureCallback(htim); +6841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #else +6842:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_IC_CaptureCallback(htim); + 16332 .loc 1 6842 3 + 16333 00b4 F868 ldr r0, [r7, #12] + 16334 00b6 FFF7FEFF bl HAL_TIM_IC_CaptureCallback +6843:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +6844:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 16335 .loc 1 6845 17 + 16336 00ba FB68 ldr r3, [r7, #12] + 16337 00bc 0022 movs r2, #0 + 16338 00be 1A77 strb r2, [r3, #28] +6846:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 16339 .loc 1 6846 1 + 16340 00c0 00BF nop + 16341 00c2 1037 adds r7, r7, #16 + 16342 .cfi_def_cfa_offset 8 + 16343 00c4 BD46 mov sp, r7 + 16344 .cfi_def_cfa_register 13 + 16345 @ sp needed + 16346 00c6 80BD pop {r7, pc} + 16347 .cfi_endproc + 16348 .LFE228: + 16350 .section .text.TIM_DMACaptureHalfCplt,"ax",%progbits + 16351 .align 1 + 16352 .global TIM_DMACaptureHalfCplt + 16353 .syntax unified + 16354 .thumb + 16355 .thumb_func + 16357 TIM_DMACaptureHalfCplt: + 16358 .LFB229: +6847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + ARM GAS /tmp/ccl4b9YO.s page 406 + + +6848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +6849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief TIM DMA Capture half complete callback. +6850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param hdma pointer to DMA handle. +6851:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval None +6852:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +6853:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma) +6854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 16359 .loc 1 6854 1 + 16360 .cfi_startproc + 16361 @ args = 0, pretend = 0, frame = 16 + 16362 @ frame_needed = 1, uses_anonymous_args = 0 + 16363 0000 80B5 push {r7, lr} + 16364 .cfi_def_cfa_offset 8 + 16365 .cfi_offset 7, -8 + 16366 .cfi_offset 14, -4 + 16367 0002 84B0 sub sp, sp, #16 + 16368 .cfi_def_cfa_offset 24 + 16369 0004 00AF add r7, sp, #0 + 16370 .cfi_def_cfa_register 7 + 16371 0006 7860 str r0, [r7, #4] +6855:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + 16372 .loc 1 6855 22 + 16373 0008 7B68 ldr r3, [r7, #4] + 16374 000a 5B6A ldr r3, [r3, #36] + 16375 000c FB60 str r3, [r7, #12] +6856:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6857:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + 16376 .loc 1 6857 25 + 16377 000e FB68 ldr r3, [r7, #12] + 16378 0010 5B6A ldr r3, [r3, #36] + 16379 .loc 1 6857 6 + 16380 0012 7A68 ldr r2, [r7, #4] + 16381 0014 9A42 cmp r2, r3 + 16382 0016 03D1 bne .L1193 +6858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +6859:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + 16383 .loc 1 6859 19 + 16384 0018 FB68 ldr r3, [r7, #12] + 16385 001a 0122 movs r2, #1 + 16386 001c 1A77 strb r2, [r3, #28] + 16387 001e 19E0 b .L1194 + 16388 .L1193: +6860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +6861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + 16389 .loc 1 6861 30 + 16390 0020 FB68 ldr r3, [r7, #12] + 16391 0022 9B6A ldr r3, [r3, #40] + 16392 .loc 1 6861 11 + 16393 0024 7A68 ldr r2, [r7, #4] + 16394 0026 9A42 cmp r2, r3 + 16395 0028 03D1 bne .L1195 +6862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +6863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + 16396 .loc 1 6863 19 + 16397 002a FB68 ldr r3, [r7, #12] + 16398 002c 0222 movs r2, #2 + 16399 002e 1A77 strb r2, [r3, #28] + ARM GAS /tmp/ccl4b9YO.s page 407 + + + 16400 0030 10E0 b .L1194 + 16401 .L1195: +6864:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +6865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + 16402 .loc 1 6865 30 + 16403 0032 FB68 ldr r3, [r7, #12] + 16404 0034 DB6A ldr r3, [r3, #44] + 16405 .loc 1 6865 11 + 16406 0036 7A68 ldr r2, [r7, #4] + 16407 0038 9A42 cmp r2, r3 + 16408 003a 03D1 bne .L1196 +6866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +6867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + 16409 .loc 1 6867 19 + 16410 003c FB68 ldr r3, [r7, #12] + 16411 003e 0422 movs r2, #4 + 16412 0040 1A77 strb r2, [r3, #28] + 16413 0042 07E0 b .L1194 + 16414 .L1196: +6868:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +6869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + 16415 .loc 1 6869 30 + 16416 0044 FB68 ldr r3, [r7, #12] + 16417 0046 1B6B ldr r3, [r3, #48] + 16418 .loc 1 6869 11 + 16419 0048 7A68 ldr r2, [r7, #4] + 16420 004a 9A42 cmp r2, r3 + 16421 004c 02D1 bne .L1194 +6870:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +6871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + 16422 .loc 1 6871 19 + 16423 004e FB68 ldr r3, [r7, #12] + 16424 0050 0822 movs r2, #8 + 16425 0052 1A77 strb r2, [r3, #28] + 16426 .L1194: +6872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +6873:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +6874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +6875:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* nothing to do */ +6876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +6877:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6878:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +6879:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->IC_CaptureHalfCpltCallback(htim); +6880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #else +6881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_IC_CaptureHalfCpltCallback(htim); + 16427 .loc 1 6881 3 + 16428 0054 F868 ldr r0, [r7, #12] + 16429 0056 FFF7FEFF bl HAL_TIM_IC_CaptureHalfCpltCallback +6882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +6883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6884:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 16430 .loc 1 6884 17 + 16431 005a FB68 ldr r3, [r7, #12] + 16432 005c 0022 movs r2, #0 + 16433 005e 1A77 strb r2, [r3, #28] +6885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 16434 .loc 1 6885 1 + ARM GAS /tmp/ccl4b9YO.s page 408 + + + 16435 0060 00BF nop + 16436 0062 1037 adds r7, r7, #16 + 16437 .cfi_def_cfa_offset 8 + 16438 0064 BD46 mov sp, r7 + 16439 .cfi_def_cfa_register 13 + 16440 @ sp needed + 16441 0066 80BD pop {r7, pc} + 16442 .cfi_endproc + 16443 .LFE229: + 16445 .section .text.TIM_DMAPeriodElapsedCplt,"ax",%progbits + 16446 .align 1 + 16447 .syntax unified + 16448 .thumb + 16449 .thumb_func + 16451 TIM_DMAPeriodElapsedCplt: + 16452 .LFB230: +6886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6887:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +6888:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief TIM DMA Period Elapse complete callback. +6889:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param hdma pointer to DMA handle. +6890:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval None +6891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +6892:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) +6893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 16453 .loc 1 6893 1 + 16454 .cfi_startproc + 16455 @ args = 0, pretend = 0, frame = 16 + 16456 @ frame_needed = 1, uses_anonymous_args = 0 + 16457 0000 80B5 push {r7, lr} + 16458 .cfi_def_cfa_offset 8 + 16459 .cfi_offset 7, -8 + 16460 .cfi_offset 14, -4 + 16461 0002 84B0 sub sp, sp, #16 + 16462 .cfi_def_cfa_offset 24 + 16463 0004 00AF add r7, sp, #0 + 16464 .cfi_def_cfa_register 7 + 16465 0006 7860 str r0, [r7, #4] +6894:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + 16466 .loc 1 6894 22 + 16467 0008 7B68 ldr r3, [r7, #4] + 16468 000a 5B6A ldr r3, [r3, #36] + 16469 000c FB60 str r3, [r7, #12] +6895:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL) + 16470 .loc 1 6896 17 + 16471 000e FB68 ldr r3, [r7, #12] + 16472 0010 1B6A ldr r3, [r3, #32] + 16473 .loc 1 6896 42 + 16474 0012 9B69 ldr r3, [r3, #24] + 16475 .loc 1 6896 6 + 16476 0014 002B cmp r3, #0 + 16477 0016 03D1 bne .L1198 +6897:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +6898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; + 16478 .loc 1 6898 17 + 16479 0018 FB68 ldr r3, [r7, #12] + 16480 001a 0122 movs r2, #1 + ARM GAS /tmp/ccl4b9YO.s page 409 + + + 16481 001c 83F83D20 strb r2, [r3, #61] + 16482 .L1198: +6899:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +6900:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +6902:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->PeriodElapsedCallback(htim); +6903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #else +6904:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_PeriodElapsedCallback(htim); + 16483 .loc 1 6904 3 + 16484 0020 F868 ldr r0, [r7, #12] + 16485 0022 FFF7FEFF bl HAL_TIM_PeriodElapsedCallback +6905:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +6906:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 16486 .loc 1 6906 1 + 16487 0026 00BF nop + 16488 0028 1037 adds r7, r7, #16 + 16489 .cfi_def_cfa_offset 8 + 16490 002a BD46 mov sp, r7 + 16491 .cfi_def_cfa_register 13 + 16492 @ sp needed + 16493 002c 80BD pop {r7, pc} + 16494 .cfi_endproc + 16495 .LFE230: + 16497 .section .text.TIM_DMAPeriodElapsedHalfCplt,"ax",%progbits + 16498 .align 1 + 16499 .syntax unified + 16500 .thumb + 16501 .thumb_func + 16503 TIM_DMAPeriodElapsedHalfCplt: + 16504 .LFB231: +6907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6908:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +6909:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief TIM DMA Period Elapse half complete callback. +6910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param hdma pointer to DMA handle. +6911:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval None +6912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +6913:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma) +6914:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 16505 .loc 1 6914 1 + 16506 .cfi_startproc + 16507 @ args = 0, pretend = 0, frame = 16 + 16508 @ frame_needed = 1, uses_anonymous_args = 0 + 16509 0000 80B5 push {r7, lr} + 16510 .cfi_def_cfa_offset 8 + 16511 .cfi_offset 7, -8 + 16512 .cfi_offset 14, -4 + 16513 0002 84B0 sub sp, sp, #16 + 16514 .cfi_def_cfa_offset 24 + 16515 0004 00AF add r7, sp, #0 + 16516 .cfi_def_cfa_register 7 + 16517 0006 7860 str r0, [r7, #4] +6915:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + 16518 .loc 1 6915 22 + 16519 0008 7B68 ldr r3, [r7, #4] + 16520 000a 5B6A ldr r3, [r3, #36] + 16521 000c FB60 str r3, [r7, #12] +6916:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + ARM GAS /tmp/ccl4b9YO.s page 410 + + +6917:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +6918:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->PeriodElapsedHalfCpltCallback(htim); +6919:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #else +6920:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_PeriodElapsedHalfCpltCallback(htim); + 16522 .loc 1 6920 3 + 16523 000e F868 ldr r0, [r7, #12] + 16524 0010 FFF7FEFF bl HAL_TIM_PeriodElapsedHalfCpltCallback +6921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +6922:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 16525 .loc 1 6922 1 + 16526 0014 00BF nop + 16527 0016 1037 adds r7, r7, #16 + 16528 .cfi_def_cfa_offset 8 + 16529 0018 BD46 mov sp, r7 + 16530 .cfi_def_cfa_register 13 + 16531 @ sp needed + 16532 001a 80BD pop {r7, pc} + 16533 .cfi_endproc + 16534 .LFE231: + 16536 .section .text.TIM_DMATriggerCplt,"ax",%progbits + 16537 .align 1 + 16538 .syntax unified + 16539 .thumb + 16540 .thumb_func + 16542 TIM_DMATriggerCplt: + 16543 .LFB232: +6923:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6924:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +6925:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief TIM DMA Trigger callback. +6926:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param hdma pointer to DMA handle. +6927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval None +6928:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +6929:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) +6930:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 16544 .loc 1 6930 1 + 16545 .cfi_startproc + 16546 @ args = 0, pretend = 0, frame = 16 + 16547 @ frame_needed = 1, uses_anonymous_args = 0 + 16548 0000 80B5 push {r7, lr} + 16549 .cfi_def_cfa_offset 8 + 16550 .cfi_offset 7, -8 + 16551 .cfi_offset 14, -4 + 16552 0002 84B0 sub sp, sp, #16 + 16553 .cfi_def_cfa_offset 24 + 16554 0004 00AF add r7, sp, #0 + 16555 .cfi_def_cfa_register 7 + 16556 0006 7860 str r0, [r7, #4] +6931:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + 16557 .loc 1 6931 22 + 16558 0008 7B68 ldr r3, [r7, #4] + 16559 000a 5B6A ldr r3, [r3, #36] + 16560 000c FB60 str r3, [r7, #12] +6932:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL) + 16561 .loc 1 6933 17 + 16562 000e FB68 ldr r3, [r7, #12] + 16563 0010 9B6B ldr r3, [r3, #56] + ARM GAS /tmp/ccl4b9YO.s page 411 + + + 16564 .loc 1 6933 43 + 16565 0012 9B69 ldr r3, [r3, #24] + 16566 .loc 1 6933 6 + 16567 0014 002B cmp r3, #0 + 16568 0016 03D1 bne .L1201 +6934:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +6935:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->State = HAL_TIM_STATE_READY; + 16569 .loc 1 6935 17 + 16570 0018 FB68 ldr r3, [r7, #12] + 16571 001a 0122 movs r2, #1 + 16572 001c 83F83D20 strb r2, [r3, #61] + 16573 .L1201: +6936:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +6937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +6939:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->TriggerCallback(htim); +6940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #else +6941:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_TriggerCallback(htim); + 16574 .loc 1 6941 3 + 16575 0020 F868 ldr r0, [r7, #12] + 16576 0022 FFF7FEFF bl HAL_TIM_TriggerCallback +6942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +6943:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 16577 .loc 1 6943 1 + 16578 0026 00BF nop + 16579 0028 1037 adds r7, r7, #16 + 16580 .cfi_def_cfa_offset 8 + 16581 002a BD46 mov sp, r7 + 16582 .cfi_def_cfa_register 13 + 16583 @ sp needed + 16584 002c 80BD pop {r7, pc} + 16585 .cfi_endproc + 16586 .LFE232: + 16588 .section .text.TIM_DMATriggerHalfCplt,"ax",%progbits + 16589 .align 1 + 16590 .syntax unified + 16591 .thumb + 16592 .thumb_func + 16594 TIM_DMATriggerHalfCplt: + 16595 .LFB233: +6944:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +6946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief TIM DMA Trigger half complete callback. +6947:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param hdma pointer to DMA handle. +6948:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval None +6949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +6950:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma) +6951:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 16596 .loc 1 6951 1 + 16597 .cfi_startproc + 16598 @ args = 0, pretend = 0, frame = 16 + 16599 @ frame_needed = 1, uses_anonymous_args = 0 + 16600 0000 80B5 push {r7, lr} + 16601 .cfi_def_cfa_offset 8 + 16602 .cfi_offset 7, -8 + 16603 .cfi_offset 14, -4 + 16604 0002 84B0 sub sp, sp, #16 + ARM GAS /tmp/ccl4b9YO.s page 412 + + + 16605 .cfi_def_cfa_offset 24 + 16606 0004 00AF add r7, sp, #0 + 16607 .cfi_def_cfa_register 7 + 16608 0006 7860 str r0, [r7, #4] +6952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + 16609 .loc 1 6952 22 + 16610 0008 7B68 ldr r3, [r7, #4] + 16611 000a 5B6A ldr r3, [r3, #36] + 16612 000c FB60 str r3, [r7, #12] +6953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6954:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +6955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->TriggerHalfCpltCallback(htim); +6956:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #else +6957:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_TIM_TriggerHalfCpltCallback(htim); + 16613 .loc 1 6957 3 + 16614 000e F868 ldr r0, [r7, #12] + 16615 0010 FFF7FEFF bl HAL_TIM_TriggerHalfCpltCallback +6958:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +6959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 16616 .loc 1 6959 1 + 16617 0014 00BF nop + 16618 0016 1037 adds r7, r7, #16 + 16619 .cfi_def_cfa_offset 8 + 16620 0018 BD46 mov sp, r7 + 16621 .cfi_def_cfa_register 13 + 16622 @ sp needed + 16623 001a 80BD pop {r7, pc} + 16624 .cfi_endproc + 16625 .LFE233: + 16627 .section .text.TIM_Base_SetConfig,"ax",%progbits + 16628 .align 1 + 16629 .global TIM_Base_SetConfig + 16630 .syntax unified + 16631 .thumb + 16632 .thumb_func + 16634 TIM_Base_SetConfig: + 16635 .LFB234: +6960:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +6962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Time Base configuration +6963:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param TIMx TIM peripheral +6964:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param Structure TIM Base configuration structure +6965:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval None +6966:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +6967:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) +6968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 16636 .loc 1 6968 1 + 16637 .cfi_startproc + 16638 @ args = 0, pretend = 0, frame = 16 + 16639 @ frame_needed = 1, uses_anonymous_args = 0 + 16640 @ link register save eliminated. + 16641 0000 80B4 push {r7} + 16642 .cfi_def_cfa_offset 4 + 16643 .cfi_offset 7, -4 + 16644 0002 85B0 sub sp, sp, #20 + 16645 .cfi_def_cfa_offset 24 + 16646 0004 00AF add r7, sp, #0 + ARM GAS /tmp/ccl4b9YO.s page 413 + + + 16647 .cfi_def_cfa_register 7 + 16648 0006 7860 str r0, [r7, #4] + 16649 0008 3960 str r1, [r7] +6969:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpcr1; +6970:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpcr1 = TIMx->CR1; + 16650 .loc 1 6970 10 + 16651 000a 7B68 ldr r3, [r7, #4] + 16652 000c 1B68 ldr r3, [r3] + 16653 000e FB60 str r3, [r7, #12] +6971:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6972:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set TIM Time Base Unit parameters ---------------------------------------*/ +6973:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) + 16654 .loc 1 6973 6 + 16655 0010 7B68 ldr r3, [r7, #4] + 16656 0012 364A ldr r2, .L1210 + 16657 0014 9342 cmp r3, r2 + 16658 0016 0BD0 beq .L1204 + 16659 .loc 1 6973 7 discriminator 1 + 16660 0018 7B68 ldr r3, [r7, #4] + 16661 001a B3F1804F cmp r3, #1073741824 + 16662 001e 07D0 beq .L1204 + 16663 .loc 1 6973 7 is_stmt 0 discriminator 2 + 16664 0020 7B68 ldr r3, [r7, #4] + 16665 0022 334A ldr r2, .L1210+4 + 16666 0024 9342 cmp r3, r2 + 16667 0026 03D0 beq .L1204 + 16668 .loc 1 6973 7 discriminator 3 + 16669 0028 7B68 ldr r3, [r7, #4] + 16670 002a 324A ldr r2, .L1210+8 + 16671 002c 9342 cmp r3, r2 + 16672 002e 08D1 bne .L1205 + 16673 .L1204: +6974:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +6975:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Select the Counter Mode */ +6976:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); + 16674 .loc 1 6976 12 is_stmt 1 + 16675 0030 FB68 ldr r3, [r7, #12] + 16676 0032 23F07003 bic r3, r3, #112 + 16677 0036 FB60 str r3, [r7, #12] +6977:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpcr1 |= Structure->CounterMode; + 16678 .loc 1 6977 24 + 16679 0038 3B68 ldr r3, [r7] + 16680 003a 5B68 ldr r3, [r3, #4] + 16681 .loc 1 6977 12 + 16682 003c FA68 ldr r2, [r7, #12] + 16683 003e 1343 orrs r3, r3, r2 + 16684 0040 FB60 str r3, [r7, #12] + 16685 .L1205: +6978:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +6979:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) + 16686 .loc 1 6980 6 + 16687 0042 7B68 ldr r3, [r7, #4] + 16688 0044 294A ldr r2, .L1210 + 16689 0046 9342 cmp r3, r2 + 16690 0048 17D0 beq .L1206 + 16691 .loc 1 6980 7 discriminator 1 + ARM GAS /tmp/ccl4b9YO.s page 414 + + + 16692 004a 7B68 ldr r3, [r7, #4] + 16693 004c B3F1804F cmp r3, #1073741824 + 16694 0050 13D0 beq .L1206 + 16695 .loc 1 6980 7 is_stmt 0 discriminator 2 + 16696 0052 7B68 ldr r3, [r7, #4] + 16697 0054 264A ldr r2, .L1210+4 + 16698 0056 9342 cmp r3, r2 + 16699 0058 0FD0 beq .L1206 + 16700 .loc 1 6980 7 discriminator 3 + 16701 005a 7B68 ldr r3, [r7, #4] + 16702 005c 254A ldr r2, .L1210+8 + 16703 005e 9342 cmp r3, r2 + 16704 0060 0BD0 beq .L1206 + 16705 .loc 1 6980 7 discriminator 4 + 16706 0062 7B68 ldr r3, [r7, #4] + 16707 0064 244A ldr r2, .L1210+12 + 16708 0066 9342 cmp r3, r2 + 16709 0068 07D0 beq .L1206 + 16710 .loc 1 6980 7 discriminator 5 + 16711 006a 7B68 ldr r3, [r7, #4] + 16712 006c 234A ldr r2, .L1210+16 + 16713 006e 9342 cmp r3, r2 + 16714 0070 03D0 beq .L1206 + 16715 .loc 1 6980 7 discriminator 6 + 16716 0072 7B68 ldr r3, [r7, #4] + 16717 0074 224A ldr r2, .L1210+20 + 16718 0076 9342 cmp r3, r2 + 16719 0078 08D1 bne .L1207 + 16720 .L1206: +6981:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +6982:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the clock division */ +6983:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpcr1 &= ~TIM_CR1_CKD; + 16721 .loc 1 6983 12 is_stmt 1 + 16722 007a FB68 ldr r3, [r7, #12] + 16723 007c 23F44073 bic r3, r3, #768 + 16724 0080 FB60 str r3, [r7, #12] +6984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpcr1 |= (uint32_t)Structure->ClockDivision; + 16725 .loc 1 6984 34 + 16726 0082 3B68 ldr r3, [r7] + 16727 0084 DB68 ldr r3, [r3, #12] + 16728 .loc 1 6984 12 + 16729 0086 FA68 ldr r2, [r7, #12] + 16730 0088 1343 orrs r3, r3, r2 + 16731 008a FB60 str r3, [r7, #12] + 16732 .L1207: +6985:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +6986:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6987:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the auto-reload preload */ +6988:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); + 16733 .loc 1 6988 3 + 16734 008c FB68 ldr r3, [r7, #12] + 16735 008e 23F08002 bic r2, r3, #128 + 16736 0092 3B68 ldr r3, [r7] + 16737 0094 5B69 ldr r3, [r3, #20] + 16738 0096 1343 orrs r3, r3, r2 + 16739 0098 FB60 str r3, [r7, #12] +6989:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + ARM GAS /tmp/ccl4b9YO.s page 415 + + +6990:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->CR1 = tmpcr1; + 16740 .loc 1 6990 13 + 16741 009a 7B68 ldr r3, [r7, #4] + 16742 009c FA68 ldr r2, [r7, #12] + 16743 009e 1A60 str r2, [r3] +6991:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6992:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the Autoreload value */ +6993:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->ARR = (uint32_t)Structure->Period ; + 16744 .loc 1 6993 34 + 16745 00a0 3B68 ldr r3, [r7] + 16746 00a2 9A68 ldr r2, [r3, #8] + 16747 .loc 1 6993 13 + 16748 00a4 7B68 ldr r3, [r7, #4] + 16749 00a6 DA62 str r2, [r3, #44] +6994:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the Prescaler value */ +6996:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->PSC = Structure->Prescaler; + 16750 .loc 1 6996 24 + 16751 00a8 3B68 ldr r3, [r7] + 16752 00aa 1A68 ldr r2, [r3] + 16753 .loc 1 6996 13 + 16754 00ac 7B68 ldr r3, [r7, #4] + 16755 00ae 9A62 str r2, [r3, #40] +6997:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +6998:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) + 16756 .loc 1 6998 6 + 16757 00b0 7B68 ldr r3, [r7, #4] + 16758 00b2 0E4A ldr r2, .L1210 + 16759 00b4 9342 cmp r3, r2 + 16760 00b6 0BD0 beq .L1208 + 16761 .loc 1 6998 7 discriminator 1 + 16762 00b8 7B68 ldr r3, [r7, #4] + 16763 00ba 0F4A ldr r2, .L1210+12 + 16764 00bc 9342 cmp r3, r2 + 16765 00be 07D0 beq .L1208 + 16766 .loc 1 6998 7 is_stmt 0 discriminator 2 + 16767 00c0 7B68 ldr r3, [r7, #4] + 16768 00c2 0E4A ldr r2, .L1210+16 + 16769 00c4 9342 cmp r3, r2 + 16770 00c6 03D0 beq .L1208 + 16771 .loc 1 6998 7 discriminator 3 + 16772 00c8 7B68 ldr r3, [r7, #4] + 16773 00ca 0D4A ldr r2, .L1210+20 + 16774 00cc 9342 cmp r3, r2 + 16775 00ce 03D1 bne .L1209 + 16776 .L1208: +6999:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +7000:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the Repetition Counter value */ +7001:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->RCR = Structure->RepetitionCounter; + 16777 .loc 1 7001 26 is_stmt 1 + 16778 00d0 3B68 ldr r3, [r7] + 16779 00d2 1A69 ldr r2, [r3, #16] + 16780 .loc 1 7001 15 + 16781 00d4 7B68 ldr r3, [r7, #4] + 16782 00d6 1A63 str r2, [r3, #48] + 16783 .L1209: +7002:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + ARM GAS /tmp/ccl4b9YO.s page 416 + + +7003:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Generate an update event to reload the Prescaler +7005:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** and the repetition counter (only for advanced timer) value immediately */ +7006:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->EGR = TIM_EGR_UG; + 16784 .loc 1 7006 13 + 16785 00d8 7B68 ldr r3, [r7, #4] + 16786 00da 0122 movs r2, #1 + 16787 00dc 5A61 str r2, [r3, #20] +7007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 16788 .loc 1 7007 1 + 16789 00de 00BF nop + 16790 00e0 1437 adds r7, r7, #20 + 16791 .cfi_def_cfa_offset 4 + 16792 00e2 BD46 mov sp, r7 + 16793 .cfi_def_cfa_register 13 + 16794 @ sp needed + 16795 00e4 5DF8047B ldr r7, [sp], #4 + 16796 .cfi_restore 7 + 16797 .cfi_def_cfa_offset 0 + 16798 00e8 7047 bx lr + 16799 .L1211: + 16800 00ea 00BF .align 2 + 16801 .L1210: + 16802 00ec 002C0140 .word 1073818624 + 16803 00f0 00040040 .word 1073742848 + 16804 00f4 00080040 .word 1073743872 + 16805 00f8 00400140 .word 1073823744 + 16806 00fc 00440140 .word 1073824768 + 16807 0100 00480140 .word 1073825792 + 16808 .cfi_endproc + 16809 .LFE234: + 16811 .section .text.TIM_OC1_SetConfig,"ax",%progbits + 16812 .align 1 + 16813 .syntax unified + 16814 .thumb + 16815 .thumb_func + 16817 TIM_OC1_SetConfig: + 16818 .LFB235: +7008:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +7010:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Timer Output Compare 1 configuration +7011:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param TIMx to select the TIM peripheral +7012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param OC_Config The output configuration structure +7013:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval None +7014:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +7015:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +7016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 16819 .loc 1 7016 1 + 16820 .cfi_startproc + 16821 @ args = 0, pretend = 0, frame = 24 + 16822 @ frame_needed = 1, uses_anonymous_args = 0 + 16823 @ link register save eliminated. + 16824 0000 80B4 push {r7} + 16825 .cfi_def_cfa_offset 4 + 16826 .cfi_offset 7, -4 + 16827 0002 87B0 sub sp, sp, #28 + 16828 .cfi_def_cfa_offset 32 + ARM GAS /tmp/ccl4b9YO.s page 417 + + + 16829 0004 00AF add r7, sp, #0 + 16830 .cfi_def_cfa_register 7 + 16831 0006 7860 str r0, [r7, #4] + 16832 0008 3960 str r1, [r7] +7017:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpccmrx; +7018:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpccer; +7019:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpcr2; +7020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7021:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the Channel 1: Reset the CC1E Bit */ +7022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->CCER &= ~TIM_CCER_CC1E; + 16833 .loc 1 7022 7 + 16834 000a 7B68 ldr r3, [r7, #4] + 16835 000c 1B6A ldr r3, [r3, #32] + 16836 .loc 1 7022 14 + 16837 000e 23F00102 bic r2, r3, #1 + 16838 0012 7B68 ldr r3, [r7, #4] + 16839 0014 1A62 str r2, [r3, #32] +7023:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Get the TIMx CCER register value */ +7025:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccer = TIMx->CCER; + 16840 .loc 1 7025 11 + 16841 0016 7B68 ldr r3, [r7, #4] + 16842 0018 1B6A ldr r3, [r3, #32] + 16843 001a 7B61 str r3, [r7, #20] +7026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Get the TIMx CR2 register value */ +7027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpcr2 = TIMx->CR2; + 16844 .loc 1 7027 10 + 16845 001c 7B68 ldr r3, [r7, #4] + 16846 001e 5B68 ldr r3, [r3, #4] + 16847 0020 3B61 str r3, [r7, #16] +7028:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Get the TIMx CCMR1 register value */ +7030:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmrx = TIMx->CCMR1; + 16848 .loc 1 7030 12 + 16849 0022 7B68 ldr r3, [r7, #4] + 16850 0024 9B69 ldr r3, [r3, #24] + 16851 0026 FB60 str r3, [r7, #12] +7031:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7032:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Reset the Output Compare Mode Bits */ +7033:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmrx &= ~TIM_CCMR1_OC1M; + 16852 .loc 1 7033 12 + 16853 0028 FB68 ldr r3, [r7, #12] + 16854 002a 23F48033 bic r3, r3, #65536 + 16855 002e 23F07003 bic r3, r3, #112 + 16856 0032 FB60 str r3, [r7, #12] +7034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmrx &= ~TIM_CCMR1_CC1S; + 16857 .loc 1 7034 12 + 16858 0034 FB68 ldr r3, [r7, #12] + 16859 0036 23F00303 bic r3, r3, #3 + 16860 003a FB60 str r3, [r7, #12] +7035:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Select the Output Compare Mode */ +7036:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmrx |= OC_Config->OCMode; + 16861 .loc 1 7036 24 + 16862 003c 3B68 ldr r3, [r7] + 16863 003e 1B68 ldr r3, [r3] + 16864 .loc 1 7036 12 + 16865 0040 FA68 ldr r2, [r7, #12] + ARM GAS /tmp/ccl4b9YO.s page 418 + + + 16866 0042 1343 orrs r3, r3, r2 + 16867 0044 FB60 str r3, [r7, #12] +7037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7038:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Reset the Output Polarity level */ +7039:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccer &= ~TIM_CCER_CC1P; + 16868 .loc 1 7039 11 + 16869 0046 7B69 ldr r3, [r7, #20] + 16870 0048 23F00203 bic r3, r3, #2 + 16871 004c 7B61 str r3, [r7, #20] +7040:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the Output Compare Polarity */ +7041:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccer |= OC_Config->OCPolarity; + 16872 .loc 1 7041 23 + 16873 004e 3B68 ldr r3, [r7] + 16874 0050 9B68 ldr r3, [r3, #8] + 16875 .loc 1 7041 11 + 16876 0052 7A69 ldr r2, [r7, #20] + 16877 0054 1343 orrs r3, r3, r2 + 16878 0056 7B61 str r3, [r7, #20] +7042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7043:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) + 16879 .loc 1 7043 6 + 16880 0058 7B68 ldr r3, [r7, #4] + 16881 005a 284A ldr r2, .L1217 + 16882 005c 9342 cmp r3, r2 + 16883 005e 0BD0 beq .L1213 + 16884 .loc 1 7043 7 discriminator 1 + 16885 0060 7B68 ldr r3, [r7, #4] + 16886 0062 274A ldr r2, .L1217+4 + 16887 0064 9342 cmp r3, r2 + 16888 0066 07D0 beq .L1213 + 16889 .loc 1 7043 7 is_stmt 0 discriminator 2 + 16890 0068 7B68 ldr r3, [r7, #4] + 16891 006a 264A ldr r2, .L1217+8 + 16892 006c 9342 cmp r3, r2 + 16893 006e 03D0 beq .L1213 + 16894 .loc 1 7043 7 discriminator 3 + 16895 0070 7B68 ldr r3, [r7, #4] + 16896 0072 254A ldr r2, .L1217+12 + 16897 0074 9342 cmp r3, r2 + 16898 0076 0CD1 bne .L1214 + 16899 .L1213: +7044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +7045:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check parameters */ +7046:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); +7047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Reset the Output N Polarity level */ +7049:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccer &= ~TIM_CCER_CC1NP; + 16900 .loc 1 7049 13 is_stmt 1 + 16901 0078 7B69 ldr r3, [r7, #20] + 16902 007a 23F00803 bic r3, r3, #8 + 16903 007e 7B61 str r3, [r7, #20] +7050:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the Output N Polarity */ +7051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccer |= OC_Config->OCNPolarity; + 16904 .loc 1 7051 25 + 16905 0080 3B68 ldr r3, [r7] + 16906 0082 DB68 ldr r3, [r3, #12] + 16907 .loc 1 7051 13 + ARM GAS /tmp/ccl4b9YO.s page 419 + + + 16908 0084 7A69 ldr r2, [r7, #20] + 16909 0086 1343 orrs r3, r3, r2 + 16910 0088 7B61 str r3, [r7, #20] +7052:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Reset the Output N State */ +7053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccer &= ~TIM_CCER_CC1NE; + 16911 .loc 1 7053 13 + 16912 008a 7B69 ldr r3, [r7, #20] + 16913 008c 23F00403 bic r3, r3, #4 + 16914 0090 7B61 str r3, [r7, #20] + 16915 .L1214: +7054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +7055:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (IS_TIM_BREAK_INSTANCE(TIMx)) + 16916 .loc 1 7056 6 + 16917 0092 7B68 ldr r3, [r7, #4] + 16918 0094 194A ldr r2, .L1217 + 16919 0096 9342 cmp r3, r2 + 16920 0098 0BD0 beq .L1215 + 16921 .loc 1 7056 7 discriminator 1 + 16922 009a 7B68 ldr r3, [r7, #4] + 16923 009c 184A ldr r2, .L1217+4 + 16924 009e 9342 cmp r3, r2 + 16925 00a0 07D0 beq .L1215 + 16926 .loc 1 7056 7 is_stmt 0 discriminator 2 + 16927 00a2 7B68 ldr r3, [r7, #4] + 16928 00a4 174A ldr r2, .L1217+8 + 16929 00a6 9342 cmp r3, r2 + 16930 00a8 03D0 beq .L1215 + 16931 .loc 1 7056 7 discriminator 3 + 16932 00aa 7B68 ldr r3, [r7, #4] + 16933 00ac 164A ldr r2, .L1217+12 + 16934 00ae 9342 cmp r3, r2 + 16935 00b0 11D1 bne .L1216 + 16936 .L1215: +7057:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +7058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check parameters */ +7059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); +7060:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); +7061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7062:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Reset the Output Compare and Output Compare N IDLE State */ +7063:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpcr2 &= ~TIM_CR2_OIS1; + 16937 .loc 1 7063 12 is_stmt 1 + 16938 00b2 3B69 ldr r3, [r7, #16] + 16939 00b4 23F48073 bic r3, r3, #256 + 16940 00b8 3B61 str r3, [r7, #16] +7064:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpcr2 &= ~TIM_CR2_OIS1N; + 16941 .loc 1 7064 12 + 16942 00ba 3B69 ldr r3, [r7, #16] + 16943 00bc 23F40073 bic r3, r3, #512 + 16944 00c0 3B61 str r3, [r7, #16] +7065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the Output Idle state */ +7066:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpcr2 |= OC_Config->OCIdleState; + 16945 .loc 1 7066 24 + 16946 00c2 3B68 ldr r3, [r7] + 16947 00c4 5B69 ldr r3, [r3, #20] + 16948 .loc 1 7066 12 + 16949 00c6 3A69 ldr r2, [r7, #16] + ARM GAS /tmp/ccl4b9YO.s page 420 + + + 16950 00c8 1343 orrs r3, r3, r2 + 16951 00ca 3B61 str r3, [r7, #16] +7067:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the Output N Idle state */ +7068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpcr2 |= OC_Config->OCNIdleState; + 16952 .loc 1 7068 24 + 16953 00cc 3B68 ldr r3, [r7] + 16954 00ce 9B69 ldr r3, [r3, #24] + 16955 .loc 1 7068 12 + 16956 00d0 3A69 ldr r2, [r7, #16] + 16957 00d2 1343 orrs r3, r3, r2 + 16958 00d4 3B61 str r3, [r7, #16] + 16959 .L1216: +7069:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +7070:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Write to TIMx CR2 */ +7072:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->CR2 = tmpcr2; + 16960 .loc 1 7072 13 + 16961 00d6 7B68 ldr r3, [r7, #4] + 16962 00d8 3A69 ldr r2, [r7, #16] + 16963 00da 5A60 str r2, [r3, #4] +7073:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7074:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Write to TIMx CCMR1 */ +7075:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->CCMR1 = tmpccmrx; + 16964 .loc 1 7075 15 + 16965 00dc 7B68 ldr r3, [r7, #4] + 16966 00de FA68 ldr r2, [r7, #12] + 16967 00e0 9A61 str r2, [r3, #24] +7076:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7077:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the Capture Compare Register value */ +7078:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->CCR1 = OC_Config->Pulse; + 16968 .loc 1 7078 25 + 16969 00e2 3B68 ldr r3, [r7] + 16970 00e4 5A68 ldr r2, [r3, #4] + 16971 .loc 1 7078 14 + 16972 00e6 7B68 ldr r3, [r7, #4] + 16973 00e8 5A63 str r2, [r3, #52] +7079:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Write to TIMx CCER */ +7081:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->CCER = tmpccer; + 16974 .loc 1 7081 14 + 16975 00ea 7B68 ldr r3, [r7, #4] + 16976 00ec 7A69 ldr r2, [r7, #20] + 16977 00ee 1A62 str r2, [r3, #32] +7082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 16978 .loc 1 7082 1 + 16979 00f0 00BF nop + 16980 00f2 1C37 adds r7, r7, #28 + 16981 .cfi_def_cfa_offset 4 + 16982 00f4 BD46 mov sp, r7 + 16983 .cfi_def_cfa_register 13 + 16984 @ sp needed + 16985 00f6 5DF8047B ldr r7, [sp], #4 + 16986 .cfi_restore 7 + 16987 .cfi_def_cfa_offset 0 + 16988 00fa 7047 bx lr + 16989 .L1218: + 16990 .align 2 + ARM GAS /tmp/ccl4b9YO.s page 421 + + + 16991 .L1217: + 16992 00fc 002C0140 .word 1073818624 + 16993 0100 00400140 .word 1073823744 + 16994 0104 00440140 .word 1073824768 + 16995 0108 00480140 .word 1073825792 + 16996 .cfi_endproc + 16997 .LFE235: + 16999 .section .text.TIM_OC2_SetConfig,"ax",%progbits + 17000 .align 1 + 17001 .global TIM_OC2_SetConfig + 17002 .syntax unified + 17003 .thumb + 17004 .thumb_func + 17006 TIM_OC2_SetConfig: + 17007 .LFB236: +7083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7084:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +7085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Timer Output Compare 2 configuration +7086:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param TIMx to select the TIM peripheral +7087:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param OC_Config The output configuration structure +7088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval None +7089:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +7090:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +7091:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 17008 .loc 1 7091 1 + 17009 .cfi_startproc + 17010 @ args = 0, pretend = 0, frame = 24 + 17011 @ frame_needed = 1, uses_anonymous_args = 0 + 17012 @ link register save eliminated. + 17013 0000 80B4 push {r7} + 17014 .cfi_def_cfa_offset 4 + 17015 .cfi_offset 7, -4 + 17016 0002 87B0 sub sp, sp, #28 + 17017 .cfi_def_cfa_offset 32 + 17018 0004 00AF add r7, sp, #0 + 17019 .cfi_def_cfa_register 7 + 17020 0006 7860 str r0, [r7, #4] + 17021 0008 3960 str r1, [r7] +7092:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpccmrx; +7093:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpccer; +7094:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpcr2; +7095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7096:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the Channel 2: Reset the CC2E Bit */ +7097:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->CCER &= ~TIM_CCER_CC2E; + 17022 .loc 1 7097 7 + 17023 000a 7B68 ldr r3, [r7, #4] + 17024 000c 1B6A ldr r3, [r3, #32] + 17025 .loc 1 7097 14 + 17026 000e 23F01002 bic r2, r3, #16 + 17027 0012 7B68 ldr r3, [r7, #4] + 17028 0014 1A62 str r2, [r3, #32] +7098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7099:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Get the TIMx CCER register value */ +7100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccer = TIMx->CCER; + 17029 .loc 1 7100 11 + 17030 0016 7B68 ldr r3, [r7, #4] + 17031 0018 1B6A ldr r3, [r3, #32] + ARM GAS /tmp/ccl4b9YO.s page 422 + + + 17032 001a 7B61 str r3, [r7, #20] +7101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Get the TIMx CR2 register value */ +7102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpcr2 = TIMx->CR2; + 17033 .loc 1 7102 10 + 17034 001c 7B68 ldr r3, [r7, #4] + 17035 001e 5B68 ldr r3, [r3, #4] + 17036 0020 3B61 str r3, [r7, #16] +7103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Get the TIMx CCMR1 register value */ +7105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmrx = TIMx->CCMR1; + 17037 .loc 1 7105 12 + 17038 0022 7B68 ldr r3, [r7, #4] + 17039 0024 9B69 ldr r3, [r3, #24] + 17040 0026 FB60 str r3, [r7, #12] +7106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Reset the Output Compare mode and Capture/Compare selection Bits */ +7108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmrx &= ~TIM_CCMR1_OC2M; + 17041 .loc 1 7108 12 + 17042 0028 FB68 ldr r3, [r7, #12] + 17043 002a 23F08073 bic r3, r3, #16777216 + 17044 002e 23F4E043 bic r3, r3, #28672 + 17045 0032 FB60 str r3, [r7, #12] +7109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmrx &= ~TIM_CCMR1_CC2S; + 17046 .loc 1 7109 12 + 17047 0034 FB68 ldr r3, [r7, #12] + 17048 0036 23F44073 bic r3, r3, #768 + 17049 003a FB60 str r3, [r7, #12] +7110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Select the Output Compare Mode */ +7112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmrx |= (OC_Config->OCMode << 8U); + 17050 .loc 1 7112 25 + 17051 003c 3B68 ldr r3, [r7] + 17052 003e 1B68 ldr r3, [r3] + 17053 .loc 1 7112 34 + 17054 0040 1B02 lsls r3, r3, #8 + 17055 .loc 1 7112 12 + 17056 0042 FA68 ldr r2, [r7, #12] + 17057 0044 1343 orrs r3, r3, r2 + 17058 0046 FB60 str r3, [r7, #12] +7113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Reset the Output Polarity level */ +7115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccer &= ~TIM_CCER_CC2P; + 17059 .loc 1 7115 11 + 17060 0048 7B69 ldr r3, [r7, #20] + 17061 004a 23F02003 bic r3, r3, #32 + 17062 004e 7B61 str r3, [r7, #20] +7116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the Output Compare Polarity */ +7117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccer |= (OC_Config->OCPolarity << 4U); + 17063 .loc 1 7117 24 + 17064 0050 3B68 ldr r3, [r7] + 17065 0052 9B68 ldr r3, [r3, #8] + 17066 .loc 1 7117 37 + 17067 0054 1B01 lsls r3, r3, #4 + 17068 .loc 1 7117 11 + 17069 0056 7A69 ldr r2, [r7, #20] + 17070 0058 1343 orrs r3, r3, r2 + 17071 005a 7B61 str r3, [r7, #20] + ARM GAS /tmp/ccl4b9YO.s page 423 + + +7118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) + 17072 .loc 1 7119 6 + 17073 005c 7B68 ldr r3, [r7, #4] + 17074 005e 244A ldr r2, .L1223 + 17075 0060 9342 cmp r3, r2 + 17076 0062 0DD1 bne .L1220 +7120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +7121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); +7122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Reset the Output N Polarity level */ +7124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccer &= ~TIM_CCER_CC2NP; + 17077 .loc 1 7124 13 + 17078 0064 7B69 ldr r3, [r7, #20] + 17079 0066 23F08003 bic r3, r3, #128 + 17080 006a 7B61 str r3, [r7, #20] +7125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the Output N Polarity */ +7126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccer |= (OC_Config->OCNPolarity << 4U); + 17081 .loc 1 7126 26 + 17082 006c 3B68 ldr r3, [r7] + 17083 006e DB68 ldr r3, [r3, #12] + 17084 .loc 1 7126 40 + 17085 0070 1B01 lsls r3, r3, #4 + 17086 .loc 1 7126 13 + 17087 0072 7A69 ldr r2, [r7, #20] + 17088 0074 1343 orrs r3, r3, r2 + 17089 0076 7B61 str r3, [r7, #20] +7127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Reset the Output N State */ +7128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccer &= ~TIM_CCER_CC2NE; + 17090 .loc 1 7128 13 + 17091 0078 7B69 ldr r3, [r7, #20] + 17092 007a 23F04003 bic r3, r3, #64 + 17093 007e 7B61 str r3, [r7, #20] + 17094 .L1220: +7129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +7131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (IS_TIM_BREAK_INSTANCE(TIMx)) + 17095 .loc 1 7132 6 + 17096 0080 7B68 ldr r3, [r7, #4] + 17097 0082 1B4A ldr r2, .L1223 + 17098 0084 9342 cmp r3, r2 + 17099 0086 0BD0 beq .L1221 + 17100 .loc 1 7132 7 discriminator 1 + 17101 0088 7B68 ldr r3, [r7, #4] + 17102 008a 1A4A ldr r2, .L1223+4 + 17103 008c 9342 cmp r3, r2 + 17104 008e 07D0 beq .L1221 + 17105 .loc 1 7132 7 is_stmt 0 discriminator 2 + 17106 0090 7B68 ldr r3, [r7, #4] + 17107 0092 194A ldr r2, .L1223+8 + 17108 0094 9342 cmp r3, r2 + 17109 0096 03D0 beq .L1221 + 17110 .loc 1 7132 7 discriminator 3 + 17111 0098 7B68 ldr r3, [r7, #4] + 17112 009a 184A ldr r2, .L1223+12 + 17113 009c 9342 cmp r3, r2 + ARM GAS /tmp/ccl4b9YO.s page 424 + + + 17114 009e 13D1 bne .L1222 + 17115 .L1221: +7133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +7134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check parameters */ +7135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); +7136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); +7137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Reset the Output Compare and Output Compare N IDLE State */ +7139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpcr2 &= ~TIM_CR2_OIS2; + 17116 .loc 1 7139 12 is_stmt 1 + 17117 00a0 3B69 ldr r3, [r7, #16] + 17118 00a2 23F48063 bic r3, r3, #1024 + 17119 00a6 3B61 str r3, [r7, #16] +7140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if defined(TIM_CR2_OIS2N) +7141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpcr2 &= ~TIM_CR2_OIS2N; + 17120 .loc 1 7141 12 + 17121 00a8 3B69 ldr r3, [r7, #16] + 17122 00aa 23F40063 bic r3, r3, #2048 + 17123 00ae 3B61 str r3, [r7, #16] +7142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* TIM_CR2_OIS2N */ +7143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the Output Idle state */ +7144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpcr2 |= (OC_Config->OCIdleState << 2U); + 17124 .loc 1 7144 25 + 17125 00b0 3B68 ldr r3, [r7] + 17126 00b2 5B69 ldr r3, [r3, #20] + 17127 .loc 1 7144 39 + 17128 00b4 9B00 lsls r3, r3, #2 + 17129 .loc 1 7144 12 + 17130 00b6 3A69 ldr r2, [r7, #16] + 17131 00b8 1343 orrs r3, r3, r2 + 17132 00ba 3B61 str r3, [r7, #16] +7145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the Output N Idle state */ +7146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpcr2 |= (OC_Config->OCNIdleState << 2U); + 17133 .loc 1 7146 25 + 17134 00bc 3B68 ldr r3, [r7] + 17135 00be 9B69 ldr r3, [r3, #24] + 17136 .loc 1 7146 40 + 17137 00c0 9B00 lsls r3, r3, #2 + 17138 .loc 1 7146 12 + 17139 00c2 3A69 ldr r2, [r7, #16] + 17140 00c4 1343 orrs r3, r3, r2 + 17141 00c6 3B61 str r3, [r7, #16] + 17142 .L1222: +7147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +7148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Write to TIMx CR2 */ +7150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->CR2 = tmpcr2; + 17143 .loc 1 7150 13 + 17144 00c8 7B68 ldr r3, [r7, #4] + 17145 00ca 3A69 ldr r2, [r7, #16] + 17146 00cc 5A60 str r2, [r3, #4] +7151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Write to TIMx CCMR1 */ +7153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->CCMR1 = tmpccmrx; + 17147 .loc 1 7153 15 + 17148 00ce 7B68 ldr r3, [r7, #4] + 17149 00d0 FA68 ldr r2, [r7, #12] + ARM GAS /tmp/ccl4b9YO.s page 425 + + + 17150 00d2 9A61 str r2, [r3, #24] +7154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the Capture Compare Register value */ +7156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->CCR2 = OC_Config->Pulse; + 17151 .loc 1 7156 25 + 17152 00d4 3B68 ldr r3, [r7] + 17153 00d6 5A68 ldr r2, [r3, #4] + 17154 .loc 1 7156 14 + 17155 00d8 7B68 ldr r3, [r7, #4] + 17156 00da 9A63 str r2, [r3, #56] +7157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Write to TIMx CCER */ +7159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->CCER = tmpccer; + 17157 .loc 1 7159 14 + 17158 00dc 7B68 ldr r3, [r7, #4] + 17159 00de 7A69 ldr r2, [r7, #20] + 17160 00e0 1A62 str r2, [r3, #32] +7160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 17161 .loc 1 7160 1 + 17162 00e2 00BF nop + 17163 00e4 1C37 adds r7, r7, #28 + 17164 .cfi_def_cfa_offset 4 + 17165 00e6 BD46 mov sp, r7 + 17166 .cfi_def_cfa_register 13 + 17167 @ sp needed + 17168 00e8 5DF8047B ldr r7, [sp], #4 + 17169 .cfi_restore 7 + 17170 .cfi_def_cfa_offset 0 + 17171 00ec 7047 bx lr + 17172 .L1224: + 17173 00ee 00BF .align 2 + 17174 .L1223: + 17175 00f0 002C0140 .word 1073818624 + 17176 00f4 00400140 .word 1073823744 + 17177 00f8 00440140 .word 1073824768 + 17178 00fc 00480140 .word 1073825792 + 17179 .cfi_endproc + 17180 .LFE236: + 17182 .section .text.TIM_OC3_SetConfig,"ax",%progbits + 17183 .align 1 + 17184 .syntax unified + 17185 .thumb + 17186 .thumb_func + 17188 TIM_OC3_SetConfig: + 17189 .LFB237: +7161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +7163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Timer Output Compare 3 configuration +7164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param TIMx to select the TIM peripheral +7165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param OC_Config The output configuration structure +7166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval None +7167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +7168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +7169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 17190 .loc 1 7169 1 + 17191 .cfi_startproc + 17192 @ args = 0, pretend = 0, frame = 24 + ARM GAS /tmp/ccl4b9YO.s page 426 + + + 17193 @ frame_needed = 1, uses_anonymous_args = 0 + 17194 @ link register save eliminated. + 17195 0000 80B4 push {r7} + 17196 .cfi_def_cfa_offset 4 + 17197 .cfi_offset 7, -4 + 17198 0002 87B0 sub sp, sp, #28 + 17199 .cfi_def_cfa_offset 32 + 17200 0004 00AF add r7, sp, #0 + 17201 .cfi_def_cfa_register 7 + 17202 0006 7860 str r0, [r7, #4] + 17203 0008 3960 str r1, [r7] +7170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpccmrx; +7171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpccer; +7172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpcr2; +7173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the Channel 3: Reset the CC2E Bit */ +7175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->CCER &= ~TIM_CCER_CC3E; + 17204 .loc 1 7175 7 + 17205 000a 7B68 ldr r3, [r7, #4] + 17206 000c 1B6A ldr r3, [r3, #32] + 17207 .loc 1 7175 14 + 17208 000e 23F48072 bic r2, r3, #256 + 17209 0012 7B68 ldr r3, [r7, #4] + 17210 0014 1A62 str r2, [r3, #32] +7176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Get the TIMx CCER register value */ +7178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccer = TIMx->CCER; + 17211 .loc 1 7178 11 + 17212 0016 7B68 ldr r3, [r7, #4] + 17213 0018 1B6A ldr r3, [r3, #32] + 17214 001a 7B61 str r3, [r7, #20] +7179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Get the TIMx CR2 register value */ +7180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpcr2 = TIMx->CR2; + 17215 .loc 1 7180 10 + 17216 001c 7B68 ldr r3, [r7, #4] + 17217 001e 5B68 ldr r3, [r3, #4] + 17218 0020 3B61 str r3, [r7, #16] +7181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Get the TIMx CCMR2 register value */ +7183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmrx = TIMx->CCMR2; + 17219 .loc 1 7183 12 + 17220 0022 7B68 ldr r3, [r7, #4] + 17221 0024 DB69 ldr r3, [r3, #28] + 17222 0026 FB60 str r3, [r7, #12] +7184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Reset the Output Compare mode and Capture/Compare selection Bits */ +7186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmrx &= ~TIM_CCMR2_OC3M; + 17223 .loc 1 7186 12 + 17224 0028 FB68 ldr r3, [r7, #12] + 17225 002a 23F48033 bic r3, r3, #65536 + 17226 002e 23F07003 bic r3, r3, #112 + 17227 0032 FB60 str r3, [r7, #12] +7187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmrx &= ~TIM_CCMR2_CC3S; + 17228 .loc 1 7187 12 + 17229 0034 FB68 ldr r3, [r7, #12] + 17230 0036 23F00303 bic r3, r3, #3 + 17231 003a FB60 str r3, [r7, #12] + ARM GAS /tmp/ccl4b9YO.s page 427 + + +7188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Select the Output Compare Mode */ +7189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmrx |= OC_Config->OCMode; + 17232 .loc 1 7189 24 + 17233 003c 3B68 ldr r3, [r7] + 17234 003e 1B68 ldr r3, [r3] + 17235 .loc 1 7189 12 + 17236 0040 FA68 ldr r2, [r7, #12] + 17237 0042 1343 orrs r3, r3, r2 + 17238 0044 FB60 str r3, [r7, #12] +7190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Reset the Output Polarity level */ +7192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccer &= ~TIM_CCER_CC3P; + 17239 .loc 1 7192 11 + 17240 0046 7B69 ldr r3, [r7, #20] + 17241 0048 23F40073 bic r3, r3, #512 + 17242 004c 7B61 str r3, [r7, #20] +7193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the Output Compare Polarity */ +7194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccer |= (OC_Config->OCPolarity << 8U); + 17243 .loc 1 7194 24 + 17244 004e 3B68 ldr r3, [r7] + 17245 0050 9B68 ldr r3, [r3, #8] + 17246 .loc 1 7194 37 + 17247 0052 1B02 lsls r3, r3, #8 + 17248 .loc 1 7194 11 + 17249 0054 7A69 ldr r2, [r7, #20] + 17250 0056 1343 orrs r3, r3, r2 + 17251 0058 7B61 str r3, [r7, #20] +7195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) + 17252 .loc 1 7196 6 + 17253 005a 7B68 ldr r3, [r7, #4] + 17254 005c 234A ldr r2, .L1229 + 17255 005e 9342 cmp r3, r2 + 17256 0060 0DD1 bne .L1226 +7197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +7198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); +7199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Reset the Output N Polarity level */ +7201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccer &= ~TIM_CCER_CC3NP; + 17257 .loc 1 7201 13 + 17258 0062 7B69 ldr r3, [r7, #20] + 17259 0064 23F40063 bic r3, r3, #2048 + 17260 0068 7B61 str r3, [r7, #20] +7202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the Output N Polarity */ +7203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccer |= (OC_Config->OCNPolarity << 8U); + 17261 .loc 1 7203 26 + 17262 006a 3B68 ldr r3, [r7] + 17263 006c DB68 ldr r3, [r3, #12] + 17264 .loc 1 7203 40 + 17265 006e 1B02 lsls r3, r3, #8 + 17266 .loc 1 7203 13 + 17267 0070 7A69 ldr r2, [r7, #20] + 17268 0072 1343 orrs r3, r3, r2 + 17269 0074 7B61 str r3, [r7, #20] +7204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Reset the Output N State */ +7205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccer &= ~TIM_CCER_CC3NE; + 17270 .loc 1 7205 13 + ARM GAS /tmp/ccl4b9YO.s page 428 + + + 17271 0076 7B69 ldr r3, [r7, #20] + 17272 0078 23F48063 bic r3, r3, #1024 + 17273 007c 7B61 str r3, [r7, #20] + 17274 .L1226: +7206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +7207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if defined(TIM_CR2_OIS3) +7209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (IS_TIM_BREAK_INSTANCE(TIMx)) + 17275 .loc 1 7209 6 + 17276 007e 7B68 ldr r3, [r7, #4] + 17277 0080 1A4A ldr r2, .L1229 + 17278 0082 9342 cmp r3, r2 + 17279 0084 0BD0 beq .L1227 + 17280 .loc 1 7209 7 discriminator 1 + 17281 0086 7B68 ldr r3, [r7, #4] + 17282 0088 194A ldr r2, .L1229+4 + 17283 008a 9342 cmp r3, r2 + 17284 008c 07D0 beq .L1227 + 17285 .loc 1 7209 7 is_stmt 0 discriminator 2 + 17286 008e 7B68 ldr r3, [r7, #4] + 17287 0090 184A ldr r2, .L1229+8 + 17288 0092 9342 cmp r3, r2 + 17289 0094 03D0 beq .L1227 + 17290 .loc 1 7209 7 discriminator 3 + 17291 0096 7B68 ldr r3, [r7, #4] + 17292 0098 174A ldr r2, .L1229+12 + 17293 009a 9342 cmp r3, r2 + 17294 009c 13D1 bne .L1228 + 17295 .L1227: +7210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +7211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check parameters */ +7212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); +7213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); +7214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Reset the Output Compare and Output Compare N IDLE State */ +7216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpcr2 &= ~TIM_CR2_OIS3; + 17296 .loc 1 7216 12 is_stmt 1 + 17297 009e 3B69 ldr r3, [r7, #16] + 17298 00a0 23F48053 bic r3, r3, #4096 + 17299 00a4 3B61 str r3, [r7, #16] +7217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpcr2 &= ~TIM_CR2_OIS3N; + 17300 .loc 1 7217 12 + 17301 00a6 3B69 ldr r3, [r7, #16] + 17302 00a8 23F40053 bic r3, r3, #8192 + 17303 00ac 3B61 str r3, [r7, #16] +7218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the Output Idle state */ +7219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpcr2 |= (OC_Config->OCIdleState << 4U); + 17304 .loc 1 7219 25 + 17305 00ae 3B68 ldr r3, [r7] + 17306 00b0 5B69 ldr r3, [r3, #20] + 17307 .loc 1 7219 39 + 17308 00b2 1B01 lsls r3, r3, #4 + 17309 .loc 1 7219 12 + 17310 00b4 3A69 ldr r2, [r7, #16] + 17311 00b6 1343 orrs r3, r3, r2 + 17312 00b8 3B61 str r3, [r7, #16] +7220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the Output N Idle state */ + ARM GAS /tmp/ccl4b9YO.s page 429 + + +7221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpcr2 |= (OC_Config->OCNIdleState << 4U); + 17313 .loc 1 7221 25 + 17314 00ba 3B68 ldr r3, [r7] + 17315 00bc 9B69 ldr r3, [r3, #24] + 17316 .loc 1 7221 40 + 17317 00be 1B01 lsls r3, r3, #4 + 17318 .loc 1 7221 12 + 17319 00c0 3A69 ldr r2, [r7, #16] + 17320 00c2 1343 orrs r3, r3, r2 + 17321 00c4 3B61 str r3, [r7, #16] + 17322 .L1228: +7222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +7223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* TIM_CR2_OIS3 */ +7224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Write to TIMx CR2 */ +7226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->CR2 = tmpcr2; + 17323 .loc 1 7226 13 + 17324 00c6 7B68 ldr r3, [r7, #4] + 17325 00c8 3A69 ldr r2, [r7, #16] + 17326 00ca 5A60 str r2, [r3, #4] +7227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Write to TIMx CCMR2 */ +7229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->CCMR2 = tmpccmrx; + 17327 .loc 1 7229 15 + 17328 00cc 7B68 ldr r3, [r7, #4] + 17329 00ce FA68 ldr r2, [r7, #12] + 17330 00d0 DA61 str r2, [r3, #28] +7230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the Capture Compare Register value */ +7232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->CCR3 = OC_Config->Pulse; + 17331 .loc 1 7232 25 + 17332 00d2 3B68 ldr r3, [r7] + 17333 00d4 5A68 ldr r2, [r3, #4] + 17334 .loc 1 7232 14 + 17335 00d6 7B68 ldr r3, [r7, #4] + 17336 00d8 DA63 str r2, [r3, #60] +7233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Write to TIMx CCER */ +7235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->CCER = tmpccer; + 17337 .loc 1 7235 14 + 17338 00da 7B68 ldr r3, [r7, #4] + 17339 00dc 7A69 ldr r2, [r7, #20] + 17340 00de 1A62 str r2, [r3, #32] +7236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 17341 .loc 1 7236 1 + 17342 00e0 00BF nop + 17343 00e2 1C37 adds r7, r7, #28 + 17344 .cfi_def_cfa_offset 4 + 17345 00e4 BD46 mov sp, r7 + 17346 .cfi_def_cfa_register 13 + 17347 @ sp needed + 17348 00e6 5DF8047B ldr r7, [sp], #4 + 17349 .cfi_restore 7 + 17350 .cfi_def_cfa_offset 0 + 17351 00ea 7047 bx lr + 17352 .L1230: + 17353 .align 2 + ARM GAS /tmp/ccl4b9YO.s page 430 + + + 17354 .L1229: + 17355 00ec 002C0140 .word 1073818624 + 17356 00f0 00400140 .word 1073823744 + 17357 00f4 00440140 .word 1073824768 + 17358 00f8 00480140 .word 1073825792 + 17359 .cfi_endproc + 17360 .LFE237: + 17362 .section .text.TIM_OC4_SetConfig,"ax",%progbits + 17363 .align 1 + 17364 .syntax unified + 17365 .thumb + 17366 .thumb_func + 17368 TIM_OC4_SetConfig: + 17369 .LFB238: +7237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +7239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Timer Output Compare 4 configuration +7240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param TIMx to select the TIM peripheral +7241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param OC_Config The output configuration structure +7242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval None +7243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +7244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +7245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 17370 .loc 1 7245 1 + 17371 .cfi_startproc + 17372 @ args = 0, pretend = 0, frame = 24 + 17373 @ frame_needed = 1, uses_anonymous_args = 0 + 17374 @ link register save eliminated. + 17375 0000 80B4 push {r7} + 17376 .cfi_def_cfa_offset 4 + 17377 .cfi_offset 7, -4 + 17378 0002 87B0 sub sp, sp, #28 + 17379 .cfi_def_cfa_offset 32 + 17380 0004 00AF add r7, sp, #0 + 17381 .cfi_def_cfa_register 7 + 17382 0006 7860 str r0, [r7, #4] + 17383 0008 3960 str r1, [r7] +7246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpccmrx; +7247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpccer; +7248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpcr2; +7249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the Channel 4: Reset the CC4E Bit */ +7251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->CCER &= ~TIM_CCER_CC4E; + 17384 .loc 1 7251 7 + 17385 000a 7B68 ldr r3, [r7, #4] + 17386 000c 1B6A ldr r3, [r3, #32] + 17387 .loc 1 7251 14 + 17388 000e 23F48052 bic r2, r3, #4096 + 17389 0012 7B68 ldr r3, [r7, #4] + 17390 0014 1A62 str r2, [r3, #32] +7252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Get the TIMx CCER register value */ +7254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccer = TIMx->CCER; + 17391 .loc 1 7254 11 + 17392 0016 7B68 ldr r3, [r7, #4] + 17393 0018 1B6A ldr r3, [r3, #32] + 17394 001a 3B61 str r3, [r7, #16] + ARM GAS /tmp/ccl4b9YO.s page 431 + + +7255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Get the TIMx CR2 register value */ +7256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpcr2 = TIMx->CR2; + 17395 .loc 1 7256 10 + 17396 001c 7B68 ldr r3, [r7, #4] + 17397 001e 5B68 ldr r3, [r3, #4] + 17398 0020 7B61 str r3, [r7, #20] +7257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Get the TIMx CCMR2 register value */ +7259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmrx = TIMx->CCMR2; + 17399 .loc 1 7259 12 + 17400 0022 7B68 ldr r3, [r7, #4] + 17401 0024 DB69 ldr r3, [r3, #28] + 17402 0026 FB60 str r3, [r7, #12] +7260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Reset the Output Compare mode and Capture/Compare selection Bits */ +7262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmrx &= ~TIM_CCMR2_OC4M; + 17403 .loc 1 7262 12 + 17404 0028 FB68 ldr r3, [r7, #12] + 17405 002a 23F08073 bic r3, r3, #16777216 + 17406 002e 23F4E043 bic r3, r3, #28672 + 17407 0032 FB60 str r3, [r7, #12] +7263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmrx &= ~TIM_CCMR2_CC4S; + 17408 .loc 1 7263 12 + 17409 0034 FB68 ldr r3, [r7, #12] + 17410 0036 23F44073 bic r3, r3, #768 + 17411 003a FB60 str r3, [r7, #12] +7264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Select the Output Compare Mode */ +7266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmrx |= (OC_Config->OCMode << 8U); + 17412 .loc 1 7266 25 + 17413 003c 3B68 ldr r3, [r7] + 17414 003e 1B68 ldr r3, [r3] + 17415 .loc 1 7266 34 + 17416 0040 1B02 lsls r3, r3, #8 + 17417 .loc 1 7266 12 + 17418 0042 FA68 ldr r2, [r7, #12] + 17419 0044 1343 orrs r3, r3, r2 + 17420 0046 FB60 str r3, [r7, #12] +7267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Reset the Output Polarity level */ +7269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccer &= ~TIM_CCER_CC4P; + 17421 .loc 1 7269 11 + 17422 0048 3B69 ldr r3, [r7, #16] + 17423 004a 23F40053 bic r3, r3, #8192 + 17424 004e 3B61 str r3, [r7, #16] +7270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the Output Compare Polarity */ +7271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccer |= (OC_Config->OCPolarity << 12U); + 17425 .loc 1 7271 24 + 17426 0050 3B68 ldr r3, [r7] + 17427 0052 9B68 ldr r3, [r3, #8] + 17428 .loc 1 7271 37 + 17429 0054 1B03 lsls r3, r3, #12 + 17430 .loc 1 7271 11 + 17431 0056 3A69 ldr r2, [r7, #16] + 17432 0058 1343 orrs r3, r3, r2 + 17433 005a 3B61 str r3, [r7, #16] +7272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + ARM GAS /tmp/ccl4b9YO.s page 432 + + +7273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if defined(TIM_CR2_OIS4) +7274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (IS_TIM_BREAK_INSTANCE(TIMx)) + 17434 .loc 1 7274 6 + 17435 005c 7B68 ldr r3, [r7, #4] + 17436 005e 164A ldr r2, .L1234 + 17437 0060 9342 cmp r3, r2 + 17438 0062 0BD0 beq .L1232 + 17439 .loc 1 7274 7 discriminator 1 + 17440 0064 7B68 ldr r3, [r7, #4] + 17441 0066 154A ldr r2, .L1234+4 + 17442 0068 9342 cmp r3, r2 + 17443 006a 07D0 beq .L1232 + 17444 .loc 1 7274 7 is_stmt 0 discriminator 2 + 17445 006c 7B68 ldr r3, [r7, #4] + 17446 006e 144A ldr r2, .L1234+8 + 17447 0070 9342 cmp r3, r2 + 17448 0072 03D0 beq .L1232 + 17449 .loc 1 7274 7 discriminator 3 + 17450 0074 7B68 ldr r3, [r7, #4] + 17451 0076 134A ldr r2, .L1234+12 + 17452 0078 9342 cmp r3, r2 + 17453 007a 09D1 bne .L1233 + 17454 .L1232: +7275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +7276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check parameters */ +7277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); +7278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Reset the Output Compare IDLE State */ +7280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpcr2 &= ~TIM_CR2_OIS4; + 17455 .loc 1 7280 12 is_stmt 1 + 17456 007c 7B69 ldr r3, [r7, #20] + 17457 007e 23F48043 bic r3, r3, #16384 + 17458 0082 7B61 str r3, [r7, #20] +7281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the Output Idle state */ +7283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpcr2 |= (OC_Config->OCIdleState << 6U); + 17459 .loc 1 7283 25 + 17460 0084 3B68 ldr r3, [r7] + 17461 0086 5B69 ldr r3, [r3, #20] + 17462 .loc 1 7283 39 + 17463 0088 9B01 lsls r3, r3, #6 + 17464 .loc 1 7283 12 + 17465 008a 7A69 ldr r2, [r7, #20] + 17466 008c 1343 orrs r3, r3, r2 + 17467 008e 7B61 str r3, [r7, #20] + 17468 .L1233: +7284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +7285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* TIM_CR2_OIS4 */ +7286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Write to TIMx CR2 */ +7288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->CR2 = tmpcr2; + 17469 .loc 1 7288 13 + 17470 0090 7B68 ldr r3, [r7, #4] + 17471 0092 7A69 ldr r2, [r7, #20] + 17472 0094 5A60 str r2, [r3, #4] +7289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Write to TIMx CCMR2 */ + ARM GAS /tmp/ccl4b9YO.s page 433 + + +7291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->CCMR2 = tmpccmrx; + 17473 .loc 1 7291 15 + 17474 0096 7B68 ldr r3, [r7, #4] + 17475 0098 FA68 ldr r2, [r7, #12] + 17476 009a DA61 str r2, [r3, #28] +7292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the Capture Compare Register value */ +7294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->CCR4 = OC_Config->Pulse; + 17477 .loc 1 7294 25 + 17478 009c 3B68 ldr r3, [r7] + 17479 009e 5A68 ldr r2, [r3, #4] + 17480 .loc 1 7294 14 + 17481 00a0 7B68 ldr r3, [r7, #4] + 17482 00a2 1A64 str r2, [r3, #64] +7295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Write to TIMx CCER */ +7297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->CCER = tmpccer; + 17483 .loc 1 7297 14 + 17484 00a4 7B68 ldr r3, [r7, #4] + 17485 00a6 3A69 ldr r2, [r7, #16] + 17486 00a8 1A62 str r2, [r3, #32] +7298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 17487 .loc 1 7298 1 + 17488 00aa 00BF nop + 17489 00ac 1C37 adds r7, r7, #28 + 17490 .cfi_def_cfa_offset 4 + 17491 00ae BD46 mov sp, r7 + 17492 .cfi_def_cfa_register 13 + 17493 @ sp needed + 17494 00b0 5DF8047B ldr r7, [sp], #4 + 17495 .cfi_restore 7 + 17496 .cfi_def_cfa_offset 0 + 17497 00b4 7047 bx lr + 17498 .L1235: + 17499 00b6 00BF .align 2 + 17500 .L1234: + 17501 00b8 002C0140 .word 1073818624 + 17502 00bc 00400140 .word 1073823744 + 17503 00c0 00440140 .word 1073824768 + 17504 00c4 00480140 .word 1073825792 + 17505 .cfi_endproc + 17506 .LFE238: + 17508 .section .text.TIM_OC5_SetConfig,"ax",%progbits + 17509 .align 1 + 17510 .syntax unified + 17511 .thumb + 17512 .thumb_func + 17514 TIM_OC5_SetConfig: + 17515 .LFB239: +7299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if defined(TIM_CCER_CC5E) +7301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +7302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Timer Output Compare 5 configuration +7303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param TIMx to select the TIM peripheral +7304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param OC_Config The output configuration structure +7305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval None +7306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ + ARM GAS /tmp/ccl4b9YO.s page 434 + + +7307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, +7308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** const TIM_OC_InitTypeDef *OC_Config) +7309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 17516 .loc 1 7309 1 + 17517 .cfi_startproc + 17518 @ args = 0, pretend = 0, frame = 24 + 17519 @ frame_needed = 1, uses_anonymous_args = 0 + 17520 @ link register save eliminated. + 17521 0000 80B4 push {r7} + 17522 .cfi_def_cfa_offset 4 + 17523 .cfi_offset 7, -4 + 17524 0002 87B0 sub sp, sp, #28 + 17525 .cfi_def_cfa_offset 32 + 17526 0004 00AF add r7, sp, #0 + 17527 .cfi_def_cfa_register 7 + 17528 0006 7860 str r0, [r7, #4] + 17529 0008 3960 str r1, [r7] +7310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpccmrx; +7311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpccer; +7312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpcr2; +7313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the output: Reset the CCxE Bit */ +7315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->CCER &= ~TIM_CCER_CC5E; + 17530 .loc 1 7315 7 + 17531 000a 7B68 ldr r3, [r7, #4] + 17532 000c 1B6A ldr r3, [r3, #32] + 17533 .loc 1 7315 14 + 17534 000e 23F48032 bic r2, r3, #65536 + 17535 0012 7B68 ldr r3, [r7, #4] + 17536 0014 1A62 str r2, [r3, #32] +7316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Get the TIMx CCER register value */ +7318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccer = TIMx->CCER; + 17537 .loc 1 7318 11 + 17538 0016 7B68 ldr r3, [r7, #4] + 17539 0018 1B6A ldr r3, [r3, #32] + 17540 001a 3B61 str r3, [r7, #16] +7319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Get the TIMx CR2 register value */ +7320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpcr2 = TIMx->CR2; + 17541 .loc 1 7320 10 + 17542 001c 7B68 ldr r3, [r7, #4] + 17543 001e 5B68 ldr r3, [r3, #4] + 17544 0020 7B61 str r3, [r7, #20] +7321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Get the TIMx CCMR1 register value */ +7322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmrx = TIMx->CCMR3; + 17545 .loc 1 7322 12 + 17546 0022 7B68 ldr r3, [r7, #4] + 17547 0024 5B6D ldr r3, [r3, #84] + 17548 0026 FB60 str r3, [r7, #12] +7323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Reset the Output Compare Mode Bits */ +7325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmrx &= ~(TIM_CCMR3_OC5M); + 17549 .loc 1 7325 12 + 17550 0028 FB68 ldr r3, [r7, #12] + 17551 002a 23F48033 bic r3, r3, #65536 + 17552 002e 23F07003 bic r3, r3, #112 + 17553 0032 FB60 str r3, [r7, #12] + ARM GAS /tmp/ccl4b9YO.s page 435 + + +7326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Select the Output Compare Mode */ +7327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmrx |= OC_Config->OCMode; + 17554 .loc 1 7327 24 + 17555 0034 3B68 ldr r3, [r7] + 17556 0036 1B68 ldr r3, [r3] + 17557 .loc 1 7327 12 + 17558 0038 FA68 ldr r2, [r7, #12] + 17559 003a 1343 orrs r3, r3, r2 + 17560 003c FB60 str r3, [r7, #12] +7328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Reset the Output Polarity level */ +7330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccer &= ~TIM_CCER_CC5P; + 17561 .loc 1 7330 11 + 17562 003e 3B69 ldr r3, [r7, #16] + 17563 0040 23F40033 bic r3, r3, #131072 + 17564 0044 3B61 str r3, [r7, #16] +7331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the Output Compare Polarity */ +7332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccer |= (OC_Config->OCPolarity << 16U); + 17565 .loc 1 7332 24 + 17566 0046 3B68 ldr r3, [r7] + 17567 0048 9B68 ldr r3, [r3, #8] + 17568 .loc 1 7332 37 + 17569 004a 1B04 lsls r3, r3, #16 + 17570 .loc 1 7332 11 + 17571 004c 3A69 ldr r2, [r7, #16] + 17572 004e 1343 orrs r3, r3, r2 + 17573 0050 3B61 str r3, [r7, #16] +7333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (IS_TIM_BREAK_INSTANCE(TIMx)) + 17574 .loc 1 7334 6 + 17575 0052 7B68 ldr r3, [r7, #4] + 17576 0054 154A ldr r2, .L1239 + 17577 0056 9342 cmp r3, r2 + 17578 0058 0BD0 beq .L1237 + 17579 .loc 1 7334 7 discriminator 1 + 17580 005a 7B68 ldr r3, [r7, #4] + 17581 005c 144A ldr r2, .L1239+4 + 17582 005e 9342 cmp r3, r2 + 17583 0060 07D0 beq .L1237 + 17584 .loc 1 7334 7 is_stmt 0 discriminator 2 + 17585 0062 7B68 ldr r3, [r7, #4] + 17586 0064 134A ldr r2, .L1239+8 + 17587 0066 9342 cmp r3, r2 + 17588 0068 03D0 beq .L1237 + 17589 .loc 1 7334 7 discriminator 3 + 17590 006a 7B68 ldr r3, [r7, #4] + 17591 006c 124A ldr r2, .L1239+12 + 17592 006e 9342 cmp r3, r2 + 17593 0070 09D1 bne .L1238 + 17594 .L1237: +7335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +7336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Reset the Output Compare IDLE State */ +7337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpcr2 &= ~TIM_CR2_OIS5; + 17595 .loc 1 7337 12 is_stmt 1 + 17596 0072 7B69 ldr r3, [r7, #20] + 17597 0074 23F48033 bic r3, r3, #65536 + 17598 0078 7B61 str r3, [r7, #20] + ARM GAS /tmp/ccl4b9YO.s page 436 + + +7338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the Output Idle state */ +7339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpcr2 |= (OC_Config->OCIdleState << 8U); + 17599 .loc 1 7339 25 + 17600 007a 3B68 ldr r3, [r7] + 17601 007c 5B69 ldr r3, [r3, #20] + 17602 .loc 1 7339 39 + 17603 007e 1B02 lsls r3, r3, #8 + 17604 .loc 1 7339 12 + 17605 0080 7A69 ldr r2, [r7, #20] + 17606 0082 1343 orrs r3, r3, r2 + 17607 0084 7B61 str r3, [r7, #20] + 17608 .L1238: +7340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +7341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Write to TIMx CR2 */ +7342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->CR2 = tmpcr2; + 17609 .loc 1 7342 13 + 17610 0086 7B68 ldr r3, [r7, #4] + 17611 0088 7A69 ldr r2, [r7, #20] + 17612 008a 5A60 str r2, [r3, #4] +7343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Write to TIMx CCMR3 */ +7345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->CCMR3 = tmpccmrx; + 17613 .loc 1 7345 15 + 17614 008c 7B68 ldr r3, [r7, #4] + 17615 008e FA68 ldr r2, [r7, #12] + 17616 0090 5A65 str r2, [r3, #84] +7346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the Capture Compare Register value */ +7348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->CCR5 = OC_Config->Pulse; + 17617 .loc 1 7348 25 + 17618 0092 3B68 ldr r3, [r7] + 17619 0094 5A68 ldr r2, [r3, #4] + 17620 .loc 1 7348 14 + 17621 0096 7B68 ldr r3, [r7, #4] + 17622 0098 9A65 str r2, [r3, #88] +7349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Write to TIMx CCER */ +7351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->CCER = tmpccer; + 17623 .loc 1 7351 14 + 17624 009a 7B68 ldr r3, [r7, #4] + 17625 009c 3A69 ldr r2, [r7, #16] + 17626 009e 1A62 str r2, [r3, #32] +7352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 17627 .loc 1 7352 1 + 17628 00a0 00BF nop + 17629 00a2 1C37 adds r7, r7, #28 + 17630 .cfi_def_cfa_offset 4 + 17631 00a4 BD46 mov sp, r7 + 17632 .cfi_def_cfa_register 13 + 17633 @ sp needed + 17634 00a6 5DF8047B ldr r7, [sp], #4 + 17635 .cfi_restore 7 + 17636 .cfi_def_cfa_offset 0 + 17637 00aa 7047 bx lr + 17638 .L1240: + 17639 .align 2 + 17640 .L1239: + ARM GAS /tmp/ccl4b9YO.s page 437 + + + 17641 00ac 002C0140 .word 1073818624 + 17642 00b0 00400140 .word 1073823744 + 17643 00b4 00440140 .word 1073824768 + 17644 00b8 00480140 .word 1073825792 + 17645 .cfi_endproc + 17646 .LFE239: + 17648 .section .text.TIM_OC6_SetConfig,"ax",%progbits + 17649 .align 1 + 17650 .syntax unified + 17651 .thumb + 17652 .thumb_func + 17654 TIM_OC6_SetConfig: + 17655 .LFB240: +7353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* TIM_CCER_CC5E */ +7354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #if defined(TIM_CCER_CC6E) +7356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +7357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Timer Output Compare 6 configuration +7358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param TIMx to select the TIM peripheral +7359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param OC_Config The output configuration structure +7360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval None +7361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +7362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, +7363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** const TIM_OC_InitTypeDef *OC_Config) +7364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 17656 .loc 1 7364 1 + 17657 .cfi_startproc + 17658 @ args = 0, pretend = 0, frame = 24 + 17659 @ frame_needed = 1, uses_anonymous_args = 0 + 17660 @ link register save eliminated. + 17661 0000 80B4 push {r7} + 17662 .cfi_def_cfa_offset 4 + 17663 .cfi_offset 7, -4 + 17664 0002 87B0 sub sp, sp, #28 + 17665 .cfi_def_cfa_offset 32 + 17666 0004 00AF add r7, sp, #0 + 17667 .cfi_def_cfa_register 7 + 17668 0006 7860 str r0, [r7, #4] + 17669 0008 3960 str r1, [r7] +7365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpccmrx; +7366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpccer; +7367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpcr2; +7368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the output: Reset the CCxE Bit */ +7370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->CCER &= ~TIM_CCER_CC6E; + 17670 .loc 1 7370 7 + 17671 000a 7B68 ldr r3, [r7, #4] + 17672 000c 1B6A ldr r3, [r3, #32] + 17673 .loc 1 7370 14 + 17674 000e 23F48012 bic r2, r3, #1048576 + 17675 0012 7B68 ldr r3, [r7, #4] + 17676 0014 1A62 str r2, [r3, #32] +7371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Get the TIMx CCER register value */ +7373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccer = TIMx->CCER; + 17677 .loc 1 7373 11 + 17678 0016 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/ccl4b9YO.s page 438 + + + 17679 0018 1B6A ldr r3, [r3, #32] + 17680 001a 3B61 str r3, [r7, #16] +7374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Get the TIMx CR2 register value */ +7375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpcr2 = TIMx->CR2; + 17681 .loc 1 7375 10 + 17682 001c 7B68 ldr r3, [r7, #4] + 17683 001e 5B68 ldr r3, [r3, #4] + 17684 0020 7B61 str r3, [r7, #20] +7376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Get the TIMx CCMR1 register value */ +7377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmrx = TIMx->CCMR3; + 17685 .loc 1 7377 12 + 17686 0022 7B68 ldr r3, [r7, #4] + 17687 0024 5B6D ldr r3, [r3, #84] + 17688 0026 FB60 str r3, [r7, #12] +7378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Reset the Output Compare Mode Bits */ +7380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmrx &= ~(TIM_CCMR3_OC6M); + 17689 .loc 1 7380 12 + 17690 0028 FB68 ldr r3, [r7, #12] + 17691 002a 23F08073 bic r3, r3, #16777216 + 17692 002e 23F4E043 bic r3, r3, #28672 + 17693 0032 FB60 str r3, [r7, #12] +7381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Select the Output Compare Mode */ +7382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmrx |= (OC_Config->OCMode << 8U); + 17694 .loc 1 7382 25 + 17695 0034 3B68 ldr r3, [r7] + 17696 0036 1B68 ldr r3, [r3] + 17697 .loc 1 7382 34 + 17698 0038 1B02 lsls r3, r3, #8 + 17699 .loc 1 7382 12 + 17700 003a FA68 ldr r2, [r7, #12] + 17701 003c 1343 orrs r3, r3, r2 + 17702 003e FB60 str r3, [r7, #12] +7383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Reset the Output Polarity level */ +7385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccer &= (uint32_t)~TIM_CCER_CC6P; + 17703 .loc 1 7385 11 + 17704 0040 3B69 ldr r3, [r7, #16] + 17705 0042 23F40013 bic r3, r3, #2097152 + 17706 0046 3B61 str r3, [r7, #16] +7386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the Output Compare Polarity */ +7387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccer |= (OC_Config->OCPolarity << 20U); + 17707 .loc 1 7387 24 + 17708 0048 3B68 ldr r3, [r7] + 17709 004a 9B68 ldr r3, [r3, #8] + 17710 .loc 1 7387 37 + 17711 004c 1B05 lsls r3, r3, #20 + 17712 .loc 1 7387 11 + 17713 004e 3A69 ldr r2, [r7, #16] + 17714 0050 1343 orrs r3, r3, r2 + 17715 0052 3B61 str r3, [r7, #16] +7388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (IS_TIM_BREAK_INSTANCE(TIMx)) + 17716 .loc 1 7389 6 + 17717 0054 7B68 ldr r3, [r7, #4] + 17718 0056 164A ldr r2, .L1244 + 17719 0058 9342 cmp r3, r2 + ARM GAS /tmp/ccl4b9YO.s page 439 + + + 17720 005a 0BD0 beq .L1242 + 17721 .loc 1 7389 7 discriminator 1 + 17722 005c 7B68 ldr r3, [r7, #4] + 17723 005e 154A ldr r2, .L1244+4 + 17724 0060 9342 cmp r3, r2 + 17725 0062 07D0 beq .L1242 + 17726 .loc 1 7389 7 is_stmt 0 discriminator 2 + 17727 0064 7B68 ldr r3, [r7, #4] + 17728 0066 144A ldr r2, .L1244+8 + 17729 0068 9342 cmp r3, r2 + 17730 006a 03D0 beq .L1242 + 17731 .loc 1 7389 7 discriminator 3 + 17732 006c 7B68 ldr r3, [r7, #4] + 17733 006e 134A ldr r2, .L1244+12 + 17734 0070 9342 cmp r3, r2 + 17735 0072 09D1 bne .L1243 + 17736 .L1242: +7390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +7391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Reset the Output Compare IDLE State */ +7392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpcr2 &= ~TIM_CR2_OIS6; + 17737 .loc 1 7392 12 is_stmt 1 + 17738 0074 7B69 ldr r3, [r7, #20] + 17739 0076 23F48023 bic r3, r3, #262144 + 17740 007a 7B61 str r3, [r7, #20] +7393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the Output Idle state */ +7394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpcr2 |= (OC_Config->OCIdleState << 10U); + 17741 .loc 1 7394 25 + 17742 007c 3B68 ldr r3, [r7] + 17743 007e 5B69 ldr r3, [r3, #20] + 17744 .loc 1 7394 39 + 17745 0080 9B02 lsls r3, r3, #10 + 17746 .loc 1 7394 12 + 17747 0082 7A69 ldr r2, [r7, #20] + 17748 0084 1343 orrs r3, r3, r2 + 17749 0086 7B61 str r3, [r7, #20] + 17750 .L1243: +7395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +7396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Write to TIMx CR2 */ +7398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->CR2 = tmpcr2; + 17751 .loc 1 7398 13 + 17752 0088 7B68 ldr r3, [r7, #4] + 17753 008a 7A69 ldr r2, [r7, #20] + 17754 008c 5A60 str r2, [r3, #4] +7399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Write to TIMx CCMR3 */ +7401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->CCMR3 = tmpccmrx; + 17755 .loc 1 7401 15 + 17756 008e 7B68 ldr r3, [r7, #4] + 17757 0090 FA68 ldr r2, [r7, #12] + 17758 0092 5A65 str r2, [r3, #84] +7402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the Capture Compare Register value */ +7404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->CCR6 = OC_Config->Pulse; + 17759 .loc 1 7404 25 + 17760 0094 3B68 ldr r3, [r7] + 17761 0096 5A68 ldr r2, [r3, #4] + ARM GAS /tmp/ccl4b9YO.s page 440 + + + 17762 .loc 1 7404 14 + 17763 0098 7B68 ldr r3, [r7, #4] + 17764 009a DA65 str r2, [r3, #92] +7405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Write to TIMx CCER */ +7407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->CCER = tmpccer; + 17765 .loc 1 7407 14 + 17766 009c 7B68 ldr r3, [r7, #4] + 17767 009e 3A69 ldr r2, [r7, #16] + 17768 00a0 1A62 str r2, [r3, #32] +7408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 17769 .loc 1 7408 1 + 17770 00a2 00BF nop + 17771 00a4 1C37 adds r7, r7, #28 + 17772 .cfi_def_cfa_offset 4 + 17773 00a6 BD46 mov sp, r7 + 17774 .cfi_def_cfa_register 13 + 17775 @ sp needed + 17776 00a8 5DF8047B ldr r7, [sp], #4 + 17777 .cfi_restore 7 + 17778 .cfi_def_cfa_offset 0 + 17779 00ac 7047 bx lr + 17780 .L1245: + 17781 00ae 00BF .align 2 + 17782 .L1244: + 17783 00b0 002C0140 .word 1073818624 + 17784 00b4 00400140 .word 1073823744 + 17785 00b8 00440140 .word 1073824768 + 17786 00bc 00480140 .word 1073825792 + 17787 .cfi_endproc + 17788 .LFE240: + 17790 .section .text.TIM_SlaveTimer_SetConfig,"ax",%progbits + 17791 .align 1 + 17792 .syntax unified + 17793 .thumb + 17794 .thumb_func + 17796 TIM_SlaveTimer_SetConfig: + 17797 .LFB241: +7409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** #endif /* TIM_CCER_CC6E */ +7410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +7412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Slave Timer configuration function +7413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param htim TIM handle +7414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param sSlaveConfig Slave timer configuration +7415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval None +7416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +7417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, +7418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** const TIM_SlaveConfigTypeDef *sSlaveConfig) +7419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 17798 .loc 1 7419 1 + 17799 .cfi_startproc + 17800 @ args = 0, pretend = 0, frame = 24 + 17801 @ frame_needed = 1, uses_anonymous_args = 0 + 17802 0000 80B5 push {r7, lr} + 17803 .cfi_def_cfa_offset 8 + 17804 .cfi_offset 7, -8 + 17805 .cfi_offset 14, -4 + ARM GAS /tmp/ccl4b9YO.s page 441 + + + 17806 0002 86B0 sub sp, sp, #24 + 17807 .cfi_def_cfa_offset 32 + 17808 0004 00AF add r7, sp, #0 + 17809 .cfi_def_cfa_register 7 + 17810 0006 7860 str r0, [r7, #4] + 17811 0008 3960 str r1, [r7] +7420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** HAL_StatusTypeDef status = HAL_OK; + 17812 .loc 1 7420 21 + 17813 000a 0023 movs r3, #0 + 17814 000c FB75 strb r3, [r7, #23] +7421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpsmcr; +7422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpccmr1; +7423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpccer; +7424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Get the TIMx SMCR register value */ +7426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpsmcr = htim->Instance->SMCR; + 17815 .loc 1 7426 17 + 17816 000e 7B68 ldr r3, [r7, #4] + 17817 0010 1B68 ldr r3, [r3] + 17818 .loc 1 7426 11 + 17819 0012 9B68 ldr r3, [r3, #8] + 17820 0014 3B61 str r3, [r7, #16] +7427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Reset the Trigger Selection Bits */ +7429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpsmcr &= ~TIM_SMCR_TS; + 17821 .loc 1 7429 11 + 17822 0016 3B69 ldr r3, [r7, #16] + 17823 0018 23F07003 bic r3, r3, #112 + 17824 001c 3B61 str r3, [r7, #16] +7430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the Input Trigger source */ +7431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpsmcr |= sSlaveConfig->InputTrigger; + 17825 .loc 1 7431 26 + 17826 001e 3B68 ldr r3, [r7] + 17827 0020 5B68 ldr r3, [r3, #4] + 17828 .loc 1 7431 11 + 17829 0022 3A69 ldr r2, [r7, #16] + 17830 0024 1343 orrs r3, r3, r2 + 17831 0026 3B61 str r3, [r7, #16] +7432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Reset the slave mode Bits */ +7434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpsmcr &= ~TIM_SMCR_SMS; + 17832 .loc 1 7434 11 + 17833 0028 3B69 ldr r3, [r7, #16] + 17834 002a 23F48033 bic r3, r3, #65536 + 17835 002e 23F00703 bic r3, r3, #7 + 17836 0032 3B61 str r3, [r7, #16] +7435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the slave mode */ +7436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpsmcr |= sSlaveConfig->SlaveMode; + 17837 .loc 1 7436 26 + 17838 0034 3B68 ldr r3, [r7] + 17839 0036 1B68 ldr r3, [r3] + 17840 .loc 1 7436 11 + 17841 0038 3A69 ldr r2, [r7, #16] + 17842 003a 1343 orrs r3, r3, r2 + 17843 003c 3B61 str r3, [r7, #16] +7437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Write to TIMx SMCR */ + ARM GAS /tmp/ccl4b9YO.s page 442 + + +7439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->SMCR = tmpsmcr; + 17844 .loc 1 7439 7 + 17845 003e 7B68 ldr r3, [r7, #4] + 17846 0040 1B68 ldr r3, [r3] + 17847 .loc 1 7439 24 + 17848 0042 3A69 ldr r2, [r7, #16] + 17849 0044 9A60 str r2, [r3, #8] +7440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Configure the trigger prescaler, filter, and polarity */ +7442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** switch (sSlaveConfig->InputTrigger) + 17850 .loc 1 7442 23 + 17851 0046 3B68 ldr r3, [r7] + 17852 0048 5B68 ldr r3, [r3, #4] + 17853 .loc 1 7442 3 + 17854 004a 702B cmp r3, #112 + 17855 004c 1AD0 beq .L1247 + 17856 004e 702B cmp r3, #112 + 17857 0050 60D8 bhi .L1248 + 17858 0052 602B cmp r3, #96 + 17859 0054 54D0 beq .L1249 + 17860 0056 602B cmp r3, #96 + 17861 0058 5CD8 bhi .L1248 + 17862 005a 502B cmp r3, #80 + 17863 005c 46D0 beq .L1250 + 17864 005e 502B cmp r3, #80 + 17865 0060 58D8 bhi .L1248 + 17866 0062 402B cmp r3, #64 + 17867 0064 19D0 beq .L1251 + 17868 0066 402B cmp r3, #64 + 17869 0068 54D8 bhi .L1248 + 17870 006a 302B cmp r3, #48 + 17871 006c 55D0 beq .L1256 + 17872 006e 302B cmp r3, #48 + 17873 0070 50D8 bhi .L1248 + 17874 0072 202B cmp r3, #32 + 17875 0074 51D0 beq .L1256 + 17876 0076 202B cmp r3, #32 + 17877 0078 4CD8 bhi .L1248 + 17878 007a 002B cmp r3, #0 + 17879 007c 4DD0 beq .L1256 + 17880 007e 102B cmp r3, #16 + 17881 0080 4BD0 beq .L1256 + 17882 0082 47E0 b .L1248 + 17883 .L1247: +7443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +7444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_TS_ETRF: +7445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +7446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +7447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); +7448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); +7449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); +7450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); +7451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Configure the ETR Trigger source */ +7452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_ETR_SetConfig(htim->Instance, + 17884 .loc 1 7452 7 + 17885 0084 7B68 ldr r3, [r7, #4] + 17886 0086 1868 ldr r0, [r3] + ARM GAS /tmp/ccl4b9YO.s page 443 + + +7453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** sSlaveConfig->TriggerPrescaler, + 17887 .loc 1 7453 37 + 17888 0088 3B68 ldr r3, [r7] + 17889 008a D968 ldr r1, [r3, #12] +7454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** sSlaveConfig->TriggerPolarity, + 17890 .loc 1 7454 37 + 17891 008c 3B68 ldr r3, [r7] + 17892 008e 9A68 ldr r2, [r3, #8] +7455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** sSlaveConfig->TriggerFilter); + 17893 .loc 1 7455 37 + 17894 0090 3B68 ldr r3, [r7] + 17895 0092 1B69 ldr r3, [r3, #16] +7452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** sSlaveConfig->TriggerPrescaler, + 17896 .loc 1 7452 7 + 17897 0094 FFF7FEFF bl TIM_ETR_SetConfig +7456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 17898 .loc 1 7456 7 + 17899 0098 40E0 b .L1253 + 17900 .L1251: +7457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +7458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_TS_TI1F_ED: +7460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +7461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +7462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); +7463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); +7464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) + 17901 .loc 1 7465 23 + 17902 009a 3B68 ldr r3, [r7] + 17903 009c 1B68 ldr r3, [r3] + 17904 .loc 1 7465 10 + 17905 009e 052B cmp r3, #5 + 17906 00a0 01D1 bne .L1254 +7466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +7467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return HAL_ERROR; + 17907 .loc 1 7467 16 + 17908 00a2 0123 movs r3, #1 + 17909 00a4 3BE0 b .L1255 + 17910 .L1254: +7468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +7469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the Channel 1: Reset the CC1E Bit */ +7471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccer = htim->Instance->CCER; + 17911 .loc 1 7471 21 + 17912 00a6 7B68 ldr r3, [r7, #4] + 17913 00a8 1B68 ldr r3, [r3] + 17914 .loc 1 7471 15 + 17915 00aa 1B6A ldr r3, [r3, #32] + 17916 00ac FB60 str r3, [r7, #12] +7472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->CCER &= ~TIM_CCER_CC1E; + 17917 .loc 1 7472 11 + 17918 00ae 7B68 ldr r3, [r7, #4] + 17919 00b0 1B68 ldr r3, [r3] + 17920 .loc 1 7472 21 + 17921 00b2 1A6A ldr r2, [r3, #32] + 17922 .loc 1 7472 11 + ARM GAS /tmp/ccl4b9YO.s page 444 + + + 17923 00b4 7B68 ldr r3, [r7, #4] + 17924 00b6 1B68 ldr r3, [r3] + 17925 .loc 1 7472 28 + 17926 00b8 22F00102 bic r2, r2, #1 + 17927 00bc 1A62 str r2, [r3, #32] +7473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmr1 = htim->Instance->CCMR1; + 17928 .loc 1 7473 22 + 17929 00be 7B68 ldr r3, [r7, #4] + 17930 00c0 1B68 ldr r3, [r3] + 17931 .loc 1 7473 16 + 17932 00c2 9B69 ldr r3, [r3, #24] + 17933 00c4 BB60 str r3, [r7, #8] +7474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the filter */ +7476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmr1 &= ~TIM_CCMR1_IC1F; + 17934 .loc 1 7476 16 + 17935 00c6 BB68 ldr r3, [r7, #8] + 17936 00c8 23F0F003 bic r3, r3, #240 + 17937 00cc BB60 str r3, [r7, #8] +7477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U); + 17938 .loc 1 7477 33 + 17939 00ce 3B68 ldr r3, [r7] + 17940 00d0 1B69 ldr r3, [r3, #16] + 17941 .loc 1 7477 50 + 17942 00d2 1B01 lsls r3, r3, #4 + 17943 .loc 1 7477 16 + 17944 00d4 BA68 ldr r2, [r7, #8] + 17945 00d6 1343 orrs r3, r3, r2 + 17946 00d8 BB60 str r3, [r7, #8] +7478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Write to TIMx CCMR1 and CCER registers */ +7480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->CCMR1 = tmpccmr1; + 17947 .loc 1 7480 11 + 17948 00da 7B68 ldr r3, [r7, #4] + 17949 00dc 1B68 ldr r3, [r3] + 17950 .loc 1 7480 29 + 17951 00de BA68 ldr r2, [r7, #8] + 17952 00e0 9A61 str r2, [r3, #24] +7481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** htim->Instance->CCER = tmpccer; + 17953 .loc 1 7481 11 + 17954 00e2 7B68 ldr r3, [r7, #4] + 17955 00e4 1B68 ldr r3, [r3] + 17956 .loc 1 7481 28 + 17957 00e6 FA68 ldr r2, [r7, #12] + 17958 00e8 1A62 str r2, [r3, #32] +7482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 17959 .loc 1 7482 7 + 17960 00ea 17E0 b .L1253 + 17961 .L1250: +7483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +7484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_TS_TI1FP1: +7486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +7487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +7488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); +7489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); +7490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + ARM GAS /tmp/ccl4b9YO.s page 445 + + +7491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Configure TI1 Filter and Polarity */ +7493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_TI1_ConfigInputStage(htim->Instance, + 17962 .loc 1 7493 7 + 17963 00ec 7B68 ldr r3, [r7, #4] + 17964 00ee 1868 ldr r0, [r3] +7494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** sSlaveConfig->TriggerPolarity, + 17965 .loc 1 7494 44 + 17966 00f0 3B68 ldr r3, [r7] + 17967 00f2 9968 ldr r1, [r3, #8] +7495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** sSlaveConfig->TriggerFilter); + 17968 .loc 1 7495 44 + 17969 00f4 3B68 ldr r3, [r7] + 17970 00f6 1B69 ldr r3, [r3, #16] +7493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** sSlaveConfig->TriggerPolarity, + 17971 .loc 1 7493 7 + 17972 00f8 1A46 mov r2, r3 + 17973 00fa FFF7FEFF bl TIM_TI1_ConfigInputStage +7496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 17974 .loc 1 7496 7 + 17975 00fe 0DE0 b .L1253 + 17976 .L1249: +7497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +7498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_TS_TI2FP2: +7500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +7501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +7502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); +7503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); +7504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); +7505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Configure TI2 Filter and Polarity */ +7507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIM_TI2_ConfigInputStage(htim->Instance, + 17977 .loc 1 7507 7 + 17978 0100 7B68 ldr r3, [r7, #4] + 17979 0102 1868 ldr r0, [r3] +7508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** sSlaveConfig->TriggerPolarity, + 17980 .loc 1 7508 44 + 17981 0104 3B68 ldr r3, [r7] + 17982 0106 9968 ldr r1, [r3, #8] +7509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** sSlaveConfig->TriggerFilter); + 17983 .loc 1 7509 44 + 17984 0108 3B68 ldr r3, [r7] + 17985 010a 1B69 ldr r3, [r3, #16] +7507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** sSlaveConfig->TriggerPolarity, + 17986 .loc 1 7507 7 + 17987 010c 1A46 mov r2, r3 + 17988 010e FFF7FEFF bl TIM_TI2_ConfigInputStage +7510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 17989 .loc 1 7510 7 + 17990 0112 03E0 b .L1253 + 17991 .L1248: +7511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +7512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_TS_ITR0: +7514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_TS_ITR1: +7515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_TS_ITR2: + ARM GAS /tmp/ccl4b9YO.s page 446 + + +7516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** case TIM_TS_ITR3: +7517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +7518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameter */ +7519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); +7520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; +7521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +7522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** default: +7524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** status = HAL_ERROR; + 17992 .loc 1 7524 14 + 17993 0114 0123 movs r3, #1 + 17994 0116 FB75 strb r3, [r7, #23] +7525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** break; + 17995 .loc 1 7525 7 + 17996 0118 00E0 b .L1253 + 17997 .L1256: +7520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 17998 .loc 1 7520 7 + 17999 011a 00BF nop + 18000 .L1253: +7526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +7527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** return status; + 18001 .loc 1 7528 10 + 18002 011c FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 18003 .L1255: +7529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 18004 .loc 1 7529 1 + 18005 011e 1846 mov r0, r3 + 18006 0120 1837 adds r7, r7, #24 + 18007 .cfi_def_cfa_offset 8 + 18008 0122 BD46 mov sp, r7 + 18009 .cfi_def_cfa_register 13 + 18010 @ sp needed + 18011 0124 80BD pop {r7, pc} + 18012 .cfi_endproc + 18013 .LFE241: + 18015 .section .text.TIM_TI1_SetConfig,"ax",%progbits + 18016 .align 1 + 18017 .global TIM_TI1_SetConfig + 18018 .syntax unified + 18019 .thumb + 18020 .thumb_func + 18022 TIM_TI1_SetConfig: + 18023 .LFB242: +7530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +7532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Configure the TI1 as Input. +7533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param TIMx to select the TIM peripheral. +7534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param TIM_ICPolarity The Input Polarity. +7535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +7536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_ICPOLARITY_RISING +7537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_ICPOLARITY_FALLING +7538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_ICPOLARITY_BOTHEDGE +7539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param TIM_ICSelection specifies the input to be used. +7540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +7541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1. + ARM GAS /tmp/ccl4b9YO.s page 447 + + +7542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2. +7543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC. +7544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param TIM_ICFilter Specifies the Input Capture Filter. +7545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter must be a value between 0x00 and 0x0F. +7546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval None +7547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 +7548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * (on channel2 path) is used as the input signal. Therefore CCMR1 must be +7549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * protected against un-initialized filter and polarity values. +7550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +7551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, +7552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t TIM_ICFilter) +7553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 18024 .loc 1 7553 1 + 18025 .cfi_startproc + 18026 @ args = 0, pretend = 0, frame = 24 + 18027 @ frame_needed = 1, uses_anonymous_args = 0 + 18028 @ link register save eliminated. + 18029 0000 80B4 push {r7} + 18030 .cfi_def_cfa_offset 4 + 18031 .cfi_offset 7, -4 + 18032 0002 87B0 sub sp, sp, #28 + 18033 .cfi_def_cfa_offset 32 + 18034 0004 00AF add r7, sp, #0 + 18035 .cfi_def_cfa_register 7 + 18036 0006 F860 str r0, [r7, #12] + 18037 0008 B960 str r1, [r7, #8] + 18038 000a 7A60 str r2, [r7, #4] + 18039 000c 3B60 str r3, [r7] +7554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpccmr1; +7555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpccer; +7556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the Channel 1: Reset the CC1E Bit */ +7558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->CCER &= ~TIM_CCER_CC1E; + 18040 .loc 1 7558 7 + 18041 000e FB68 ldr r3, [r7, #12] + 18042 0010 1B6A ldr r3, [r3, #32] + 18043 .loc 1 7558 14 + 18044 0012 23F00102 bic r2, r3, #1 + 18045 0016 FB68 ldr r3, [r7, #12] + 18046 0018 1A62 str r2, [r3, #32] +7559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmr1 = TIMx->CCMR1; + 18047 .loc 1 7559 12 + 18048 001a FB68 ldr r3, [r7, #12] + 18049 001c 9B69 ldr r3, [r3, #24] + 18050 001e 7B61 str r3, [r7, #20] +7560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccer = TIMx->CCER; + 18051 .loc 1 7560 11 + 18052 0020 FB68 ldr r3, [r7, #12] + 18053 0022 1B6A ldr r3, [r3, #32] + 18054 0024 3B61 str r3, [r7, #16] +7561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Select the Input */ +7563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) + 18055 .loc 1 7563 7 + 18056 0026 FB68 ldr r3, [r7, #12] + 18057 0028 224A ldr r2, .L1263 + 18058 002a 9342 cmp r3, r2 + ARM GAS /tmp/ccl4b9YO.s page 448 + + + 18059 002c 0FD0 beq .L1258 + 18060 .loc 1 7563 7 is_stmt 0 discriminator 2 + 18061 002e FB68 ldr r3, [r7, #12] + 18062 0030 B3F1804F cmp r3, #1073741824 + 18063 0034 0BD0 beq .L1258 + 18064 .loc 1 7563 7 discriminator 4 + 18065 0036 FB68 ldr r3, [r7, #12] + 18066 0038 1F4A ldr r2, .L1263+4 + 18067 003a 9342 cmp r3, r2 + 18068 003c 07D0 beq .L1258 + 18069 .loc 1 7563 7 discriminator 6 + 18070 003e FB68 ldr r3, [r7, #12] + 18071 0040 1E4A ldr r2, .L1263+8 + 18072 0042 9342 cmp r3, r2 + 18073 0044 03D0 beq .L1258 + 18074 .loc 1 7563 7 discriminator 8 + 18075 0046 FB68 ldr r3, [r7, #12] + 18076 0048 1D4A ldr r2, .L1263+12 + 18077 004a 9342 cmp r3, r2 + 18078 004c 01D1 bne .L1259 + 18079 .L1258: + 18080 .loc 1 7563 7 discriminator 9 + 18081 004e 0123 movs r3, #1 + 18082 .loc 1 7563 7 + 18083 0050 00E0 b .L1260 + 18084 .L1259: + 18085 .loc 1 7563 7 discriminator 10 + 18086 0052 0023 movs r3, #0 + 18087 .L1260: + 18088 .loc 1 7563 6 is_stmt 1 discriminator 12 + 18089 0054 002B cmp r3, #0 + 18090 0056 08D0 beq .L1261 +7564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +7565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmr1 &= ~TIM_CCMR1_CC1S; + 18091 .loc 1 7565 14 + 18092 0058 7B69 ldr r3, [r7, #20] + 18093 005a 23F00303 bic r3, r3, #3 + 18094 005e 7B61 str r3, [r7, #20] +7566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmr1 |= TIM_ICSelection; + 18095 .loc 1 7566 14 + 18096 0060 7A69 ldr r2, [r7, #20] + 18097 0062 7B68 ldr r3, [r7, #4] + 18098 0064 1343 orrs r3, r3, r2 + 18099 0066 7B61 str r3, [r7, #20] + 18100 0068 03E0 b .L1262 + 18101 .L1261: +7567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +7568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** else +7569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { +7570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmr1 |= TIM_CCMR1_CC1S_0; + 18102 .loc 1 7570 14 + 18103 006a 7B69 ldr r3, [r7, #20] + 18104 006c 43F00103 orr r3, r3, #1 + 18105 0070 7B61 str r3, [r7, #20] + 18106 .L1262: +7571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } +7572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + ARM GAS /tmp/ccl4b9YO.s page 449 + + +7573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the filter */ +7574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmr1 &= ~TIM_CCMR1_IC1F; + 18107 .loc 1 7574 12 + 18108 0072 7B69 ldr r3, [r7, #20] + 18109 0074 23F0F003 bic r3, r3, #240 + 18110 0078 7B61 str r3, [r7, #20] +7575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F); + 18111 .loc 1 7575 30 + 18112 007a 3B68 ldr r3, [r7] + 18113 007c 1B01 lsls r3, r3, #4 + 18114 .loc 1 7575 37 + 18115 007e DBB2 uxtb r3, r3 + 18116 .loc 1 7575 12 + 18117 0080 7A69 ldr r2, [r7, #20] + 18118 0082 1343 orrs r3, r3, r2 + 18119 0084 7B61 str r3, [r7, #20] +7576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Select the Polarity and set the CC1E Bit */ +7578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + 18120 .loc 1 7578 11 + 18121 0086 3B69 ldr r3, [r7, #16] + 18122 0088 23F00A03 bic r3, r3, #10 + 18123 008c 3B61 str r3, [r7, #16] +7579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); + 18124 .loc 1 7579 30 + 18125 008e BB68 ldr r3, [r7, #8] + 18126 0090 03F00A03 and r3, r3, #10 + 18127 .loc 1 7579 11 + 18128 0094 3A69 ldr r2, [r7, #16] + 18129 0096 1343 orrs r3, r3, r2 + 18130 0098 3B61 str r3, [r7, #16] +7580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Write to TIMx CCMR1 and CCER registers */ +7582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->CCMR1 = tmpccmr1; + 18131 .loc 1 7582 15 + 18132 009a FB68 ldr r3, [r7, #12] + 18133 009c 7A69 ldr r2, [r7, #20] + 18134 009e 9A61 str r2, [r3, #24] +7583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->CCER = tmpccer; + 18135 .loc 1 7583 14 + 18136 00a0 FB68 ldr r3, [r7, #12] + 18137 00a2 3A69 ldr r2, [r7, #16] + 18138 00a4 1A62 str r2, [r3, #32] +7584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 18139 .loc 1 7584 1 + 18140 00a6 00BF nop + 18141 00a8 1C37 adds r7, r7, #28 + 18142 .cfi_def_cfa_offset 4 + 18143 00aa BD46 mov sp, r7 + 18144 .cfi_def_cfa_register 13 + 18145 @ sp needed + 18146 00ac 5DF8047B ldr r7, [sp], #4 + 18147 .cfi_restore 7 + 18148 .cfi_def_cfa_offset 0 + 18149 00b0 7047 bx lr + 18150 .L1264: + 18151 00b2 00BF .align 2 + ARM GAS /tmp/ccl4b9YO.s page 450 + + + 18152 .L1263: + 18153 00b4 002C0140 .word 1073818624 + 18154 00b8 00040040 .word 1073742848 + 18155 00bc 00080040 .word 1073743872 + 18156 00c0 00400140 .word 1073823744 + 18157 .cfi_endproc + 18158 .LFE242: + 18160 .section .text.TIM_TI1_ConfigInputStage,"ax",%progbits + 18161 .align 1 + 18162 .syntax unified + 18163 .thumb + 18164 .thumb_func + 18166 TIM_TI1_ConfigInputStage: + 18167 .LFB243: +7585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +7587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Configure the Polarity and Filter for TI1. +7588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param TIMx to select the TIM peripheral. +7589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param TIM_ICPolarity The Input Polarity. +7590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +7591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_ICPOLARITY_RISING +7592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_ICPOLARITY_FALLING +7593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_ICPOLARITY_BOTHEDGE +7594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param TIM_ICFilter Specifies the Input Capture Filter. +7595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter must be a value between 0x00 and 0x0F. +7596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval None +7597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +7598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFil +7599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 18168 .loc 1 7599 1 + 18169 .cfi_startproc + 18170 @ args = 0, pretend = 0, frame = 24 + 18171 @ frame_needed = 1, uses_anonymous_args = 0 + 18172 @ link register save eliminated. + 18173 0000 80B4 push {r7} + 18174 .cfi_def_cfa_offset 4 + 18175 .cfi_offset 7, -4 + 18176 0002 87B0 sub sp, sp, #28 + 18177 .cfi_def_cfa_offset 32 + 18178 0004 00AF add r7, sp, #0 + 18179 .cfi_def_cfa_register 7 + 18180 0006 F860 str r0, [r7, #12] + 18181 0008 B960 str r1, [r7, #8] + 18182 000a 7A60 str r2, [r7, #4] +7600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpccmr1; +7601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpccer; +7602:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the Channel 1: Reset the CC1E Bit */ +7604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccer = TIMx->CCER; + 18183 .loc 1 7604 11 + 18184 000c FB68 ldr r3, [r7, #12] + 18185 000e 1B6A ldr r3, [r3, #32] + 18186 0010 7B61 str r3, [r7, #20] +7605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->CCER &= ~TIM_CCER_CC1E; + 18187 .loc 1 7605 7 + 18188 0012 FB68 ldr r3, [r7, #12] + 18189 0014 1B6A ldr r3, [r3, #32] + ARM GAS /tmp/ccl4b9YO.s page 451 + + + 18190 .loc 1 7605 14 + 18191 0016 23F00102 bic r2, r3, #1 + 18192 001a FB68 ldr r3, [r7, #12] + 18193 001c 1A62 str r2, [r3, #32] +7606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmr1 = TIMx->CCMR1; + 18194 .loc 1 7606 12 + 18195 001e FB68 ldr r3, [r7, #12] + 18196 0020 9B69 ldr r3, [r3, #24] + 18197 0022 3B61 str r3, [r7, #16] +7607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the filter */ +7609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmr1 &= ~TIM_CCMR1_IC1F; + 18198 .loc 1 7609 12 + 18199 0024 3B69 ldr r3, [r7, #16] + 18200 0026 23F0F003 bic r3, r3, #240 + 18201 002a 3B61 str r3, [r7, #16] +7610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmr1 |= (TIM_ICFilter << 4U); + 18202 .loc 1 7610 29 + 18203 002c 7B68 ldr r3, [r7, #4] + 18204 002e 1B01 lsls r3, r3, #4 + 18205 .loc 1 7610 12 + 18206 0030 3A69 ldr r2, [r7, #16] + 18207 0032 1343 orrs r3, r3, r2 + 18208 0034 3B61 str r3, [r7, #16] +7611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7612:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Select the Polarity and set the CC1E Bit */ +7613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + 18209 .loc 1 7613 11 + 18210 0036 7B69 ldr r3, [r7, #20] + 18211 0038 23F00A03 bic r3, r3, #10 + 18212 003c 7B61 str r3, [r7, #20] +7614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccer |= TIM_ICPolarity; + 18213 .loc 1 7614 11 + 18214 003e 7A69 ldr r2, [r7, #20] + 18215 0040 BB68 ldr r3, [r7, #8] + 18216 0042 1343 orrs r3, r3, r2 + 18217 0044 7B61 str r3, [r7, #20] +7615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Write to TIMx CCMR1 and CCER registers */ +7617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->CCMR1 = tmpccmr1; + 18218 .loc 1 7617 15 + 18219 0046 FB68 ldr r3, [r7, #12] + 18220 0048 3A69 ldr r2, [r7, #16] + 18221 004a 9A61 str r2, [r3, #24] +7618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->CCER = tmpccer; + 18222 .loc 1 7618 14 + 18223 004c FB68 ldr r3, [r7, #12] + 18224 004e 7A69 ldr r2, [r7, #20] + 18225 0050 1A62 str r2, [r3, #32] +7619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 18226 .loc 1 7619 1 + 18227 0052 00BF nop + 18228 0054 1C37 adds r7, r7, #28 + 18229 .cfi_def_cfa_offset 4 + 18230 0056 BD46 mov sp, r7 + 18231 .cfi_def_cfa_register 13 + 18232 @ sp needed + ARM GAS /tmp/ccl4b9YO.s page 452 + + + 18233 0058 5DF8047B ldr r7, [sp], #4 + 18234 .cfi_restore 7 + 18235 .cfi_def_cfa_offset 0 + 18236 005c 7047 bx lr + 18237 .cfi_endproc + 18238 .LFE243: + 18240 .section .text.TIM_TI2_SetConfig,"ax",%progbits + 18241 .align 1 + 18242 .syntax unified + 18243 .thumb + 18244 .thumb_func + 18246 TIM_TI2_SetConfig: + 18247 .LFB244: +7620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +7622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Configure the TI2 as Input. +7623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param TIMx to select the TIM peripheral +7624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param TIM_ICPolarity The Input Polarity. +7625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +7626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_ICPOLARITY_RISING +7627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_ICPOLARITY_FALLING +7628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_ICPOLARITY_BOTHEDGE +7629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param TIM_ICSelection specifies the input to be used. +7630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +7631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2. +7632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1. +7633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC. +7634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param TIM_ICFilter Specifies the Input Capture Filter. +7635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter must be a value between 0x00 and 0x0F. +7636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval None +7637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 +7638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * (on channel1 path) is used as the input signal. Therefore CCMR1 must be +7639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * protected against un-initialized filter and polarity values. +7640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +7641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, +7642:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t TIM_ICFilter) +7643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 18248 .loc 1 7643 1 + 18249 .cfi_startproc + 18250 @ args = 0, pretend = 0, frame = 24 + 18251 @ frame_needed = 1, uses_anonymous_args = 0 + 18252 @ link register save eliminated. + 18253 0000 80B4 push {r7} + 18254 .cfi_def_cfa_offset 4 + 18255 .cfi_offset 7, -4 + 18256 0002 87B0 sub sp, sp, #28 + 18257 .cfi_def_cfa_offset 32 + 18258 0004 00AF add r7, sp, #0 + 18259 .cfi_def_cfa_register 7 + 18260 0006 F860 str r0, [r7, #12] + 18261 0008 B960 str r1, [r7, #8] + 18262 000a 7A60 str r2, [r7, #4] + 18263 000c 3B60 str r3, [r7] +7644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpccmr1; +7645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpccer; +7646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the Channel 2: Reset the CC2E Bit */ + ARM GAS /tmp/ccl4b9YO.s page 453 + + +7648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->CCER &= ~TIM_CCER_CC2E; + 18264 .loc 1 7648 7 + 18265 000e FB68 ldr r3, [r7, #12] + 18266 0010 1B6A ldr r3, [r3, #32] + 18267 .loc 1 7648 14 + 18268 0012 23F01002 bic r2, r3, #16 + 18269 0016 FB68 ldr r3, [r7, #12] + 18270 0018 1A62 str r2, [r3, #32] +7649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmr1 = TIMx->CCMR1; + 18271 .loc 1 7649 12 + 18272 001a FB68 ldr r3, [r7, #12] + 18273 001c 9B69 ldr r3, [r3, #24] + 18274 001e 7B61 str r3, [r7, #20] +7650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccer = TIMx->CCER; + 18275 .loc 1 7650 11 + 18276 0020 FB68 ldr r3, [r7, #12] + 18277 0022 1B6A ldr r3, [r3, #32] + 18278 0024 3B61 str r3, [r7, #16] +7651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Select the Input */ +7653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmr1 &= ~TIM_CCMR1_CC2S; + 18279 .loc 1 7653 12 + 18280 0026 7B69 ldr r3, [r7, #20] + 18281 0028 23F44073 bic r3, r3, #768 + 18282 002c 7B61 str r3, [r7, #20] +7654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmr1 |= (TIM_ICSelection << 8U); + 18283 .loc 1 7654 32 + 18284 002e 7B68 ldr r3, [r7, #4] + 18285 0030 1B02 lsls r3, r3, #8 + 18286 .loc 1 7654 12 + 18287 0032 7A69 ldr r2, [r7, #20] + 18288 0034 1343 orrs r3, r3, r2 + 18289 0036 7B61 str r3, [r7, #20] +7655:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the filter */ +7657:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmr1 &= ~TIM_CCMR1_IC2F; + 18290 .loc 1 7657 12 + 18291 0038 7B69 ldr r3, [r7, #20] + 18292 003a 23F47043 bic r3, r3, #61440 + 18293 003e 7B61 str r3, [r7, #20] +7658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F); + 18294 .loc 1 7658 30 + 18295 0040 3B68 ldr r3, [r7] + 18296 0042 1B03 lsls r3, r3, #12 + 18297 .loc 1 7658 38 + 18298 0044 9BB2 uxth r3, r3 + 18299 .loc 1 7658 12 + 18300 0046 7A69 ldr r2, [r7, #20] + 18301 0048 1343 orrs r3, r3, r2 + 18302 004a 7B61 str r3, [r7, #20] +7659:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Select the Polarity and set the CC2E Bit */ +7661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + 18303 .loc 1 7661 11 + 18304 004c 3B69 ldr r3, [r7, #16] + 18305 004e 23F0A003 bic r3, r3, #160 + 18306 0052 3B61 str r3, [r7, #16] + ARM GAS /tmp/ccl4b9YO.s page 454 + + +7662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); + 18307 .loc 1 7662 31 + 18308 0054 BB68 ldr r3, [r7, #8] + 18309 0056 1B01 lsls r3, r3, #4 + 18310 .loc 1 7662 38 + 18311 0058 03F0A003 and r3, r3, #160 + 18312 .loc 1 7662 11 + 18313 005c 3A69 ldr r2, [r7, #16] + 18314 005e 1343 orrs r3, r3, r2 + 18315 0060 3B61 str r3, [r7, #16] +7663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7664:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Write to TIMx CCMR1 and CCER registers */ +7665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->CCMR1 = tmpccmr1 ; + 18316 .loc 1 7665 15 + 18317 0062 FB68 ldr r3, [r7, #12] + 18318 0064 7A69 ldr r2, [r7, #20] + 18319 0066 9A61 str r2, [r3, #24] +7666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->CCER = tmpccer; + 18320 .loc 1 7666 14 + 18321 0068 FB68 ldr r3, [r7, #12] + 18322 006a 3A69 ldr r2, [r7, #16] + 18323 006c 1A62 str r2, [r3, #32] +7667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 18324 .loc 1 7667 1 + 18325 006e 00BF nop + 18326 0070 1C37 adds r7, r7, #28 + 18327 .cfi_def_cfa_offset 4 + 18328 0072 BD46 mov sp, r7 + 18329 .cfi_def_cfa_register 13 + 18330 @ sp needed + 18331 0074 5DF8047B ldr r7, [sp], #4 + 18332 .cfi_restore 7 + 18333 .cfi_def_cfa_offset 0 + 18334 0078 7047 bx lr + 18335 .cfi_endproc + 18336 .LFE244: + 18338 .section .text.TIM_TI2_ConfigInputStage,"ax",%progbits + 18339 .align 1 + 18340 .syntax unified + 18341 .thumb + 18342 .thumb_func + 18344 TIM_TI2_ConfigInputStage: + 18345 .LFB245: +7668:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +7670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Configure the Polarity and Filter for TI2. +7671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param TIMx to select the TIM peripheral. +7672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param TIM_ICPolarity The Input Polarity. +7673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +7674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_ICPOLARITY_RISING +7675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_ICPOLARITY_FALLING +7676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_ICPOLARITY_BOTHEDGE +7677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param TIM_ICFilter Specifies the Input Capture Filter. +7678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter must be a value between 0x00 and 0x0F. +7679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval None +7680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +7681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFil + ARM GAS /tmp/ccl4b9YO.s page 455 + + +7682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 18346 .loc 1 7682 1 + 18347 .cfi_startproc + 18348 @ args = 0, pretend = 0, frame = 24 + 18349 @ frame_needed = 1, uses_anonymous_args = 0 + 18350 @ link register save eliminated. + 18351 0000 80B4 push {r7} + 18352 .cfi_def_cfa_offset 4 + 18353 .cfi_offset 7, -4 + 18354 0002 87B0 sub sp, sp, #28 + 18355 .cfi_def_cfa_offset 32 + 18356 0004 00AF add r7, sp, #0 + 18357 .cfi_def_cfa_register 7 + 18358 0006 F860 str r0, [r7, #12] + 18359 0008 B960 str r1, [r7, #8] + 18360 000a 7A60 str r2, [r7, #4] +7683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpccmr1; +7684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpccer; +7685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the Channel 2: Reset the CC2E Bit */ +7687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->CCER &= ~TIM_CCER_CC2E; + 18361 .loc 1 7687 7 + 18362 000c FB68 ldr r3, [r7, #12] + 18363 000e 1B6A ldr r3, [r3, #32] + 18364 .loc 1 7687 14 + 18365 0010 23F01002 bic r2, r3, #16 + 18366 0014 FB68 ldr r3, [r7, #12] + 18367 0016 1A62 str r2, [r3, #32] +7688:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmr1 = TIMx->CCMR1; + 18368 .loc 1 7688 12 + 18369 0018 FB68 ldr r3, [r7, #12] + 18370 001a 9B69 ldr r3, [r3, #24] + 18371 001c 7B61 str r3, [r7, #20] +7689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccer = TIMx->CCER; + 18372 .loc 1 7689 11 + 18373 001e FB68 ldr r3, [r7, #12] + 18374 0020 1B6A ldr r3, [r3, #32] + 18375 0022 3B61 str r3, [r7, #16] +7690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the filter */ +7692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmr1 &= ~TIM_CCMR1_IC2F; + 18376 .loc 1 7692 12 + 18377 0024 7B69 ldr r3, [r7, #20] + 18378 0026 23F47043 bic r3, r3, #61440 + 18379 002a 7B61 str r3, [r7, #20] +7693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmr1 |= (TIM_ICFilter << 12U); + 18380 .loc 1 7693 29 + 18381 002c 7B68 ldr r3, [r7, #4] + 18382 002e 1B03 lsls r3, r3, #12 + 18383 .loc 1 7693 12 + 18384 0030 7A69 ldr r2, [r7, #20] + 18385 0032 1343 orrs r3, r3, r2 + 18386 0034 7B61 str r3, [r7, #20] +7694:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Select the Polarity and set the CC2E Bit */ +7696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + 18387 .loc 1 7696 11 + ARM GAS /tmp/ccl4b9YO.s page 456 + + + 18388 0036 3B69 ldr r3, [r7, #16] + 18389 0038 23F0A003 bic r3, r3, #160 + 18390 003c 3B61 str r3, [r7, #16] +7697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccer |= (TIM_ICPolarity << 4U); + 18391 .loc 1 7697 30 + 18392 003e BB68 ldr r3, [r7, #8] + 18393 0040 1B01 lsls r3, r3, #4 + 18394 .loc 1 7697 11 + 18395 0042 3A69 ldr r2, [r7, #16] + 18396 0044 1343 orrs r3, r3, r2 + 18397 0046 3B61 str r3, [r7, #16] +7698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Write to TIMx CCMR1 and CCER registers */ +7700:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->CCMR1 = tmpccmr1 ; + 18398 .loc 1 7700 15 + 18399 0048 FB68 ldr r3, [r7, #12] + 18400 004a 7A69 ldr r2, [r7, #20] + 18401 004c 9A61 str r2, [r3, #24] +7701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->CCER = tmpccer; + 18402 .loc 1 7701 14 + 18403 004e FB68 ldr r3, [r7, #12] + 18404 0050 3A69 ldr r2, [r7, #16] + 18405 0052 1A62 str r2, [r3, #32] +7702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 18406 .loc 1 7702 1 + 18407 0054 00BF nop + 18408 0056 1C37 adds r7, r7, #28 + 18409 .cfi_def_cfa_offset 4 + 18410 0058 BD46 mov sp, r7 + 18411 .cfi_def_cfa_register 13 + 18412 @ sp needed + 18413 005a 5DF8047B ldr r7, [sp], #4 + 18414 .cfi_restore 7 + 18415 .cfi_def_cfa_offset 0 + 18416 005e 7047 bx lr + 18417 .cfi_endproc + 18418 .LFE245: + 18420 .section .text.TIM_TI3_SetConfig,"ax",%progbits + 18421 .align 1 + 18422 .syntax unified + 18423 .thumb + 18424 .thumb_func + 18426 TIM_TI3_SetConfig: + 18427 .LFB246: +7703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7704:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +7705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Configure the TI3 as Input. +7706:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param TIMx to select the TIM peripheral +7707:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param TIM_ICPolarity The Input Polarity. +7708:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +7709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_ICPOLARITY_RISING +7710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_ICPOLARITY_FALLING +7711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_ICPOLARITY_BOTHEDGE +7712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param TIM_ICSelection specifies the input to be used. +7713:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +7714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3. +7715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4. + ARM GAS /tmp/ccl4b9YO.s page 457 + + +7716:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC. +7717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param TIM_ICFilter Specifies the Input Capture Filter. +7718:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter must be a value between 0x00 and 0x0F. +7719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval None +7720:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 +7721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * (on channel1 path) is used as the input signal. Therefore CCMR2 must be +7722:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * protected against un-initialized filter and polarity values. +7723:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +7724:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, +7725:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t TIM_ICFilter) +7726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 18428 .loc 1 7726 1 + 18429 .cfi_startproc + 18430 @ args = 0, pretend = 0, frame = 24 + 18431 @ frame_needed = 1, uses_anonymous_args = 0 + 18432 @ link register save eliminated. + 18433 0000 80B4 push {r7} + 18434 .cfi_def_cfa_offset 4 + 18435 .cfi_offset 7, -4 + 18436 0002 87B0 sub sp, sp, #28 + 18437 .cfi_def_cfa_offset 32 + 18438 0004 00AF add r7, sp, #0 + 18439 .cfi_def_cfa_register 7 + 18440 0006 F860 str r0, [r7, #12] + 18441 0008 B960 str r1, [r7, #8] + 18442 000a 7A60 str r2, [r7, #4] + 18443 000c 3B60 str r3, [r7] +7727:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpccmr2; +7728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpccer; +7729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the Channel 3: Reset the CC3E Bit */ +7731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->CCER &= ~TIM_CCER_CC3E; + 18444 .loc 1 7731 7 + 18445 000e FB68 ldr r3, [r7, #12] + 18446 0010 1B6A ldr r3, [r3, #32] + 18447 .loc 1 7731 14 + 18448 0012 23F48072 bic r2, r3, #256 + 18449 0016 FB68 ldr r3, [r7, #12] + 18450 0018 1A62 str r2, [r3, #32] +7732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmr2 = TIMx->CCMR2; + 18451 .loc 1 7732 12 + 18452 001a FB68 ldr r3, [r7, #12] + 18453 001c DB69 ldr r3, [r3, #28] + 18454 001e 7B61 str r3, [r7, #20] +7733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccer = TIMx->CCER; + 18455 .loc 1 7733 11 + 18456 0020 FB68 ldr r3, [r7, #12] + 18457 0022 1B6A ldr r3, [r3, #32] + 18458 0024 3B61 str r3, [r7, #16] +7734:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Select the Input */ +7736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmr2 &= ~TIM_CCMR2_CC3S; + 18459 .loc 1 7736 12 + 18460 0026 7B69 ldr r3, [r7, #20] + 18461 0028 23F00303 bic r3, r3, #3 + 18462 002c 7B61 str r3, [r7, #20] +7737:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmr2 |= TIM_ICSelection; + ARM GAS /tmp/ccl4b9YO.s page 458 + + + 18463 .loc 1 7737 12 + 18464 002e 7A69 ldr r2, [r7, #20] + 18465 0030 7B68 ldr r3, [r7, #4] + 18466 0032 1343 orrs r3, r3, r2 + 18467 0034 7B61 str r3, [r7, #20] +7738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7739:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the filter */ +7740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmr2 &= ~TIM_CCMR2_IC3F; + 18468 .loc 1 7740 12 + 18469 0036 7B69 ldr r3, [r7, #20] + 18470 0038 23F0F003 bic r3, r3, #240 + 18471 003c 7B61 str r3, [r7, #20] +7741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); + 18472 .loc 1 7741 30 + 18473 003e 3B68 ldr r3, [r7] + 18474 0040 1B01 lsls r3, r3, #4 + 18475 .loc 1 7741 37 + 18476 0042 DBB2 uxtb r3, r3 + 18477 .loc 1 7741 12 + 18478 0044 7A69 ldr r2, [r7, #20] + 18479 0046 1343 orrs r3, r3, r2 + 18480 0048 7B61 str r3, [r7, #20] +7742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7743:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Select the Polarity and set the CC3E Bit */ +7744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); + 18481 .loc 1 7744 11 + 18482 004a 3B69 ldr r3, [r7, #16] + 18483 004c 23F42063 bic r3, r3, #2560 + 18484 0050 3B61 str r3, [r7, #16] +7745:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); + 18485 .loc 1 7745 31 + 18486 0052 BB68 ldr r3, [r7, #8] + 18487 0054 1B02 lsls r3, r3, #8 + 18488 .loc 1 7745 38 + 18489 0056 03F42063 and r3, r3, #2560 + 18490 .loc 1 7745 11 + 18491 005a 3A69 ldr r2, [r7, #16] + 18492 005c 1343 orrs r3, r3, r2 + 18493 005e 3B61 str r3, [r7, #16] +7746:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7747:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Write to TIMx CCMR2 and CCER registers */ +7748:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->CCMR2 = tmpccmr2; + 18494 .loc 1 7748 15 + 18495 0060 FB68 ldr r3, [r7, #12] + 18496 0062 7A69 ldr r2, [r7, #20] + 18497 0064 DA61 str r2, [r3, #28] +7749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->CCER = tmpccer; + 18498 .loc 1 7749 14 + 18499 0066 FB68 ldr r3, [r7, #12] + 18500 0068 3A69 ldr r2, [r7, #16] + 18501 006a 1A62 str r2, [r3, #32] +7750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 18502 .loc 1 7750 1 + 18503 006c 00BF nop + 18504 006e 1C37 adds r7, r7, #28 + 18505 .cfi_def_cfa_offset 4 + 18506 0070 BD46 mov sp, r7 + ARM GAS /tmp/ccl4b9YO.s page 459 + + + 18507 .cfi_def_cfa_register 13 + 18508 @ sp needed + 18509 0072 5DF8047B ldr r7, [sp], #4 + 18510 .cfi_restore 7 + 18511 .cfi_def_cfa_offset 0 + 18512 0076 7047 bx lr + 18513 .cfi_endproc + 18514 .LFE246: + 18516 .section .text.TIM_TI4_SetConfig,"ax",%progbits + 18517 .align 1 + 18518 .syntax unified + 18519 .thumb + 18520 .thumb_func + 18522 TIM_TI4_SetConfig: + 18523 .LFB247: +7751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7752:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +7753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Configure the TI4 as Input. +7754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param TIMx to select the TIM peripheral +7755:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param TIM_ICPolarity The Input Polarity. +7756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +7757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_ICPOLARITY_RISING +7758:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_ICPOLARITY_FALLING +7759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_ICPOLARITY_BOTHEDGE +7760:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param TIM_ICSelection specifies the input to be used. +7761:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +7762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4. +7763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3. +7764:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC. +7765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param TIM_ICFilter Specifies the Input Capture Filter. +7766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter must be a value between 0x00 and 0x0F. +7767:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 +7768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * (on channel1 path) is used as the input signal. Therefore CCMR2 must be +7769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * protected against un-initialized filter and polarity values. +7770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval None +7771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +7772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, +7773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t TIM_ICFilter) +7774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 18524 .loc 1 7774 1 + 18525 .cfi_startproc + 18526 @ args = 0, pretend = 0, frame = 24 + 18527 @ frame_needed = 1, uses_anonymous_args = 0 + 18528 @ link register save eliminated. + 18529 0000 80B4 push {r7} + 18530 .cfi_def_cfa_offset 4 + 18531 .cfi_offset 7, -4 + 18532 0002 87B0 sub sp, sp, #28 + 18533 .cfi_def_cfa_offset 32 + 18534 0004 00AF add r7, sp, #0 + 18535 .cfi_def_cfa_register 7 + 18536 0006 F860 str r0, [r7, #12] + 18537 0008 B960 str r1, [r7, #8] + 18538 000a 7A60 str r2, [r7, #4] + 18539 000c 3B60 str r3, [r7] +7775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpccmr2; +7776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpccer; + ARM GAS /tmp/ccl4b9YO.s page 460 + + +7777:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Disable the Channel 4: Reset the CC4E Bit */ +7779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->CCER &= ~TIM_CCER_CC4E; + 18540 .loc 1 7779 7 + 18541 000e FB68 ldr r3, [r7, #12] + 18542 0010 1B6A ldr r3, [r3, #32] + 18543 .loc 1 7779 14 + 18544 0012 23F48052 bic r2, r3, #4096 + 18545 0016 FB68 ldr r3, [r7, #12] + 18546 0018 1A62 str r2, [r3, #32] +7780:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmr2 = TIMx->CCMR2; + 18547 .loc 1 7780 12 + 18548 001a FB68 ldr r3, [r7, #12] + 18549 001c DB69 ldr r3, [r3, #28] + 18550 001e 7B61 str r3, [r7, #20] +7781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccer = TIMx->CCER; + 18551 .loc 1 7781 11 + 18552 0020 FB68 ldr r3, [r7, #12] + 18553 0022 1B6A ldr r3, [r3, #32] + 18554 0024 3B61 str r3, [r7, #16] +7782:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Select the Input */ +7784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmr2 &= ~TIM_CCMR2_CC4S; + 18555 .loc 1 7784 12 + 18556 0026 7B69 ldr r3, [r7, #20] + 18557 0028 23F44073 bic r3, r3, #768 + 18558 002c 7B61 str r3, [r7, #20] +7785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmr2 |= (TIM_ICSelection << 8U); + 18559 .loc 1 7785 32 + 18560 002e 7B68 ldr r3, [r7, #4] + 18561 0030 1B02 lsls r3, r3, #8 + 18562 .loc 1 7785 12 + 18563 0032 7A69 ldr r2, [r7, #20] + 18564 0034 1343 orrs r3, r3, r2 + 18565 0036 7B61 str r3, [r7, #20] +7786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7787:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the filter */ +7788:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmr2 &= ~TIM_CCMR2_IC4F; + 18566 .loc 1 7788 12 + 18567 0038 7B69 ldr r3, [r7, #20] + 18568 003a 23F47043 bic r3, r3, #61440 + 18569 003e 7B61 str r3, [r7, #20] +7789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F); + 18570 .loc 1 7789 30 + 18571 0040 3B68 ldr r3, [r7] + 18572 0042 1B03 lsls r3, r3, #12 + 18573 .loc 1 7789 38 + 18574 0044 9BB2 uxth r3, r3 + 18575 .loc 1 7789 12 + 18576 0046 7A69 ldr r2, [r7, #20] + 18577 0048 1343 orrs r3, r3, r2 + 18578 004a 7B61 str r3, [r7, #20] +7790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Select the Polarity and set the CC4E Bit */ +7792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); + 18579 .loc 1 7792 11 + 18580 004c 3B69 ldr r3, [r7, #16] + ARM GAS /tmp/ccl4b9YO.s page 461 + + + 18581 004e 23F42043 bic r3, r3, #40960 + 18582 0052 3B61 str r3, [r7, #16] +7793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); + 18583 .loc 1 7793 31 + 18584 0054 BB68 ldr r3, [r7, #8] + 18585 0056 1B03 lsls r3, r3, #12 + 18586 .loc 1 7793 39 + 18587 0058 03F42043 and r3, r3, #40960 + 18588 .loc 1 7793 11 + 18589 005c 3A69 ldr r2, [r7, #16] + 18590 005e 1343 orrs r3, r3, r2 + 18591 0060 3B61 str r3, [r7, #16] +7794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Write to TIMx CCMR2 and CCER registers */ +7796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->CCMR2 = tmpccmr2; + 18592 .loc 1 7796 15 + 18593 0062 FB68 ldr r3, [r7, #12] + 18594 0064 7A69 ldr r2, [r7, #20] + 18595 0066 DA61 str r2, [r3, #28] +7797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->CCER = tmpccer ; + 18596 .loc 1 7797 14 + 18597 0068 FB68 ldr r3, [r7, #12] + 18598 006a 3A69 ldr r2, [r7, #16] + 18599 006c 1A62 str r2, [r3, #32] +7798:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 18600 .loc 1 7798 1 + 18601 006e 00BF nop + 18602 0070 1C37 adds r7, r7, #28 + 18603 .cfi_def_cfa_offset 4 + 18604 0072 BD46 mov sp, r7 + 18605 .cfi_def_cfa_register 13 + 18606 @ sp needed + 18607 0074 5DF8047B ldr r7, [sp], #4 + 18608 .cfi_restore 7 + 18609 .cfi_def_cfa_offset 0 + 18610 0078 7047 bx lr + 18611 .cfi_endproc + 18612 .LFE247: + 18614 .section .text.TIM_ITRx_SetConfig,"ax",%progbits + 18615 .align 1 + 18616 .syntax unified + 18617 .thumb + 18618 .thumb_func + 18620 TIM_ITRx_SetConfig: + 18621 .LFB248: +7799:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +7801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Selects the Input Trigger source +7802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param TIMx to select the TIM peripheral +7803:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param InputTriggerSource The Input Trigger source. +7804:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +7805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_TS_ITR0: Internal Trigger 0 +7806:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_TS_ITR1: Internal Trigger 1 +7807:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_TS_ITR2: Internal Trigger 2 +7808:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_TS_ITR3: Internal Trigger 3 +7809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_TS_TI1F_ED: TI1 Edge Detector +7810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 + ARM GAS /tmp/ccl4b9YO.s page 462 + + +7811:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 +7812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_TS_ETRF: External Trigger input +7813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval None +7814:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +7815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) +7816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 18622 .loc 1 7816 1 + 18623 .cfi_startproc + 18624 @ args = 0, pretend = 0, frame = 16 + 18625 @ frame_needed = 1, uses_anonymous_args = 0 + 18626 @ link register save eliminated. + 18627 0000 80B4 push {r7} + 18628 .cfi_def_cfa_offset 4 + 18629 .cfi_offset 7, -4 + 18630 0002 85B0 sub sp, sp, #20 + 18631 .cfi_def_cfa_offset 24 + 18632 0004 00AF add r7, sp, #0 + 18633 .cfi_def_cfa_register 7 + 18634 0006 7860 str r0, [r7, #4] + 18635 0008 3960 str r1, [r7] +7817:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpsmcr; +7818:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Get the TIMx SMCR register value */ +7820:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpsmcr = TIMx->SMCR; + 18636 .loc 1 7820 11 + 18637 000a 7B68 ldr r3, [r7, #4] + 18638 000c 9B68 ldr r3, [r3, #8] + 18639 000e FB60 str r3, [r7, #12] +7821:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Reset the TS Bits */ +7822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpsmcr &= ~TIM_SMCR_TS; + 18640 .loc 1 7822 11 + 18641 0010 FB68 ldr r3, [r7, #12] + 18642 0012 23F07003 bic r3, r3, #112 + 18643 0016 FB60 str r3, [r7, #12] +7823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the Input Trigger source and the slave mode*/ +7824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); + 18644 .loc 1 7824 11 + 18645 0018 3A68 ldr r2, [r7] + 18646 001a FB68 ldr r3, [r7, #12] + 18647 001c 1343 orrs r3, r3, r2 + 18648 001e 43F00703 orr r3, r3, #7 + 18649 0022 FB60 str r3, [r7, #12] +7825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Write to TIMx SMCR */ +7826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->SMCR = tmpsmcr; + 18650 .loc 1 7826 14 + 18651 0024 7B68 ldr r3, [r7, #4] + 18652 0026 FA68 ldr r2, [r7, #12] + 18653 0028 9A60 str r2, [r3, #8] +7827:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 18654 .loc 1 7827 1 + 18655 002a 00BF nop + 18656 002c 1437 adds r7, r7, #20 + 18657 .cfi_def_cfa_offset 4 + 18658 002e BD46 mov sp, r7 + 18659 .cfi_def_cfa_register 13 + 18660 @ sp needed + 18661 0030 5DF8047B ldr r7, [sp], #4 + ARM GAS /tmp/ccl4b9YO.s page 463 + + + 18662 .cfi_restore 7 + 18663 .cfi_def_cfa_offset 0 + 18664 0034 7047 bx lr + 18665 .cfi_endproc + 18666 .LFE248: + 18668 .section .text.TIM_ETR_SetConfig,"ax",%progbits + 18669 .align 1 + 18670 .global TIM_ETR_SetConfig + 18671 .syntax unified + 18672 .thumb + 18673 .thumb_func + 18675 TIM_ETR_SetConfig: + 18676 .LFB249: +7828:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +7829:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Configures the TIMx External Trigger (ETR). +7830:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param TIMx to select the TIM peripheral +7831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. +7832:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +7833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF. +7834:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2. +7835:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4. +7836:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8. +7837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param TIM_ExtTRGPolarity The external Trigger Polarity. +7838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: +7839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active. +7840:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active. +7841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param ExtTRGFilter External Trigger Filter. +7842:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter must be a value between 0x00 and 0x0F +7843:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval None +7844:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +7845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, +7846:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) +7847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 18677 .loc 1 7847 1 + 18678 .cfi_startproc + 18679 @ args = 0, pretend = 0, frame = 24 + 18680 @ frame_needed = 1, uses_anonymous_args = 0 + 18681 @ link register save eliminated. + 18682 0000 80B4 push {r7} + 18683 .cfi_def_cfa_offset 4 + 18684 .cfi_offset 7, -4 + 18685 0002 87B0 sub sp, sp, #28 + 18686 .cfi_def_cfa_offset 32 + 18687 0004 00AF add r7, sp, #0 + 18688 .cfi_def_cfa_register 7 + 18689 0006 F860 str r0, [r7, #12] + 18690 0008 B960 str r1, [r7, #8] + 18691 000a 7A60 str r2, [r7, #4] + 18692 000c 3B60 str r3, [r7] +7848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmpsmcr; +7849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpsmcr = TIMx->SMCR; + 18693 .loc 1 7850 11 + 18694 000e FB68 ldr r3, [r7, #12] + 18695 0010 9B68 ldr r3, [r3, #8] + 18696 0012 7B61 str r3, [r7, #20] +7851:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** + ARM GAS /tmp/ccl4b9YO.s page 464 + + +7852:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Reset the ETR Bits */ +7853:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + 18697 .loc 1 7853 11 + 18698 0014 7B69 ldr r3, [r7, #20] + 18699 0016 23F47F43 bic r3, r3, #65280 + 18700 001a 7B61 str r3, [r7, #20] +7854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7855:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set the Prescaler, the Filter value and the Polarity */ +7856:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); + 18701 .loc 1 7856 83 + 18702 001c 3B68 ldr r3, [r7] + 18703 001e 1A02 lsls r2, r3, #8 + 18704 .loc 1 7856 67 + 18705 0020 7B68 ldr r3, [r7, #4] + 18706 0022 1A43 orrs r2, r2, r3 + 18707 .loc 1 7856 45 + 18708 0024 BB68 ldr r3, [r7, #8] + 18709 0026 1343 orrs r3, r3, r2 + 18710 .loc 1 7856 11 + 18711 0028 7A69 ldr r2, [r7, #20] + 18712 002a 1343 orrs r3, r3, r2 + 18713 002c 7B61 str r3, [r7, #20] +7857:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Write to TIMx SMCR */ +7859:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->SMCR = tmpsmcr; + 18714 .loc 1 7859 14 + 18715 002e FB68 ldr r3, [r7, #12] + 18716 0030 7A69 ldr r2, [r7, #20] + 18717 0032 9A60 str r2, [r3, #8] +7860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 18718 .loc 1 7860 1 + 18719 0034 00BF nop + 18720 0036 1C37 adds r7, r7, #28 + 18721 .cfi_def_cfa_offset 4 + 18722 0038 BD46 mov sp, r7 + 18723 .cfi_def_cfa_register 13 + 18724 @ sp needed + 18725 003a 5DF8047B ldr r7, [sp], #4 + 18726 .cfi_restore 7 + 18727 .cfi_def_cfa_offset 0 + 18728 003e 7047 bx lr + 18729 .cfi_endproc + 18730 .LFE249: + 18732 .section .text.TIM_CCxChannelCmd,"ax",%progbits + 18733 .align 1 + 18734 .global TIM_CCxChannelCmd + 18735 .syntax unified + 18736 .thumb + 18737 .thumb_func + 18739 TIM_CCxChannelCmd: + 18740 .LFB250: +7861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /** +7863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @brief Enables or disables the TIM Capture Compare Channel x. +7864:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param TIMx to select the TIM peripheral +7865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param Channel specifies the TIM Channel +7866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be one of the following values: + ARM GAS /tmp/ccl4b9YO.s page 465 + + +7867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 +7868:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 +7869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 +7870:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_4: TIM Channel 4 +7871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_5: TIM Channel 5 selected +7872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @arg TIM_CHANNEL_6: TIM Channel 6 selected +7873:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @param ChannelState specifies the TIM Channel CCxE bit new state. +7874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. +7875:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** * @retval None +7876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** */ +7877:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) +7878:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** { + 18741 .loc 1 7878 1 + 18742 .cfi_startproc + 18743 @ args = 0, pretend = 0, frame = 24 + 18744 @ frame_needed = 1, uses_anonymous_args = 0 + 18745 @ link register save eliminated. + 18746 0000 80B4 push {r7} + 18747 .cfi_def_cfa_offset 4 + 18748 .cfi_offset 7, -4 + 18749 0002 87B0 sub sp, sp, #28 + 18750 .cfi_def_cfa_offset 32 + 18751 0004 00AF add r7, sp, #0 + 18752 .cfi_def_cfa_register 7 + 18753 0006 F860 str r0, [r7, #12] + 18754 0008 B960 str r1, [r7, #8] + 18755 000a 7A60 str r2, [r7, #4] +7879:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** uint32_t tmp; +7880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Check the parameters */ +7882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CC1_INSTANCE(TIMx)); +7883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** assert_param(IS_TIM_CHANNELS(Channel)); +7884:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ + 18756 .loc 1 7885 35 + 18757 000c BB68 ldr r3, [r7, #8] + 18758 000e 03F01F03 and r3, r3, #31 + 18759 .loc 1 7885 7 + 18760 0012 0122 movs r2, #1 + 18761 0014 02FA03F3 lsl r3, r2, r3 + 18762 0018 7B61 str r3, [r7, #20] +7886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7887:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Reset the CCxE Bit */ +7888:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->CCER &= ~tmp; + 18763 .loc 1 7888 7 + 18764 001a FB68 ldr r3, [r7, #12] + 18765 001c 1A6A ldr r2, [r3, #32] + 18766 .loc 1 7888 17 + 18767 001e 7B69 ldr r3, [r7, #20] + 18768 0020 DB43 mvns r3, r3 + 18769 .loc 1 7888 14 + 18770 0022 1A40 ands r2, r2, r3 + 18771 0024 FB68 ldr r3, [r7, #12] + 18772 0026 1A62 str r2, [r3, #32] +7889:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** +7890:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** /* Set or reset the CCxE Bit */ +7891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ + ARM GAS /tmp/ccl4b9YO.s page 466 + + + 18773 .loc 1 7891 7 + 18774 0028 FB68 ldr r3, [r7, #12] + 18775 002a 1A6A ldr r2, [r3, #32] + 18776 .loc 1 7891 53 + 18777 002c BB68 ldr r3, [r7, #8] + 18778 002e 03F01F03 and r3, r3, #31 + 18779 .loc 1 7891 41 + 18780 0032 7968 ldr r1, [r7, #4] + 18781 0034 01FA03F3 lsl r3, r1, r3 + 18782 .loc 1 7891 14 + 18783 0038 1A43 orrs r2, r2, r3 + 18784 003a FB68 ldr r3, [r7, #12] + 18785 003c 1A62 str r2, [r3, #32] +7892:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim.c **** } + 18786 .loc 1 7892 1 + 18787 003e 00BF nop + 18788 0040 1C37 adds r7, r7, #28 + 18789 .cfi_def_cfa_offset 4 + 18790 0042 BD46 mov sp, r7 + 18791 .cfi_def_cfa_register 13 + 18792 @ sp needed + 18793 0044 5DF8047B ldr r7, [sp], #4 + 18794 .cfi_restore 7 + 18795 .cfi_def_cfa_offset 0 + 18796 0048 7047 bx lr + 18797 .cfi_endproc + 18798 .LFE250: + 18800 .text + 18801 .Letext0: + 18802 .file 2 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 18803 .file 3 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 18804 .file 4 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + 18805 .file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h" + 18806 .file 6 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h" + 18807 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h" + 18808 .file 8 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h" + 18809 .file 9 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h" + ARM GAS /tmp/ccl4b9YO.s page 467 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f3xx_hal_tim.c + /tmp/ccl4b9YO.s:21 .text.HAL_TIM_Base_Init:00000000 $t + /tmp/ccl4b9YO.s:27 .text.HAL_TIM_Base_Init:00000000 HAL_TIM_Base_Init + /tmp/ccl4b9YO.s:251 .text.HAL_TIM_Base_MspInit:00000000 HAL_TIM_Base_MspInit + /tmp/ccl4b9YO.s:16634 .text.TIM_Base_SetConfig:00000000 TIM_Base_SetConfig + /tmp/ccl4b9YO.s:134 .text.HAL_TIM_Base_DeInit:00000000 $t + /tmp/ccl4b9YO.s:140 .text.HAL_TIM_Base_DeInit:00000000 HAL_TIM_Base_DeInit + /tmp/ccl4b9YO.s:287 .text.HAL_TIM_Base_MspDeInit:00000000 HAL_TIM_Base_MspDeInit + /tmp/ccl4b9YO.s:245 .text.HAL_TIM_Base_MspInit:00000000 $t + /tmp/ccl4b9YO.s:281 .text.HAL_TIM_Base_MspDeInit:00000000 $t + /tmp/ccl4b9YO.s:317 .text.HAL_TIM_Base_Start:00000000 $t + /tmp/ccl4b9YO.s:323 .text.HAL_TIM_Base_Start:00000000 HAL_TIM_Base_Start + /tmp/ccl4b9YO.s:442 .text.HAL_TIM_Base_Start:000000a0 $d + /tmp/ccl4b9YO.s:451 .text.HAL_TIM_Base_Stop:00000000 $t + /tmp/ccl4b9YO.s:457 .text.HAL_TIM_Base_Stop:00000000 HAL_TIM_Base_Stop + /tmp/ccl4b9YO.s:518 .text.HAL_TIM_Base_Start_IT:00000000 $t + /tmp/ccl4b9YO.s:524 .text.HAL_TIM_Base_Start_IT:00000000 HAL_TIM_Base_Start_IT + /tmp/ccl4b9YO.s:651 .text.HAL_TIM_Base_Start_IT:000000b0 $d + /tmp/ccl4b9YO.s:660 .text.HAL_TIM_Base_Stop_IT:00000000 $t + /tmp/ccl4b9YO.s:666 .text.HAL_TIM_Base_Stop_IT:00000000 HAL_TIM_Base_Stop_IT + /tmp/ccl4b9YO.s:735 .text.HAL_TIM_Base_Start_DMA:00000000 $t + /tmp/ccl4b9YO.s:741 .text.HAL_TIM_Base_Start_DMA:00000000 HAL_TIM_Base_Start_DMA + /tmp/ccl4b9YO.s:933 .text.HAL_TIM_Base_Start_DMA:0000010c $d + /tmp/ccl4b9YO.s:16451 .text.TIM_DMAPeriodElapsedCplt:00000000 TIM_DMAPeriodElapsedCplt + /tmp/ccl4b9YO.s:16503 .text.TIM_DMAPeriodElapsedHalfCplt:00000000 TIM_DMAPeriodElapsedHalfCplt + /tmp/ccl4b9YO.s:15860 .text.TIM_DMAError:00000000 TIM_DMAError + /tmp/ccl4b9YO.s:945 .text.HAL_TIM_Base_Stop_DMA:00000000 $t + /tmp/ccl4b9YO.s:951 .text.HAL_TIM_Base_Stop_DMA:00000000 HAL_TIM_Base_Stop_DMA + /tmp/ccl4b9YO.s:1022 .text.HAL_TIM_OC_Init:00000000 $t + /tmp/ccl4b9YO.s:1028 .text.HAL_TIM_OC_Init:00000000 HAL_TIM_OC_Init + /tmp/ccl4b9YO.s:1252 .text.HAL_TIM_OC_MspInit:00000000 HAL_TIM_OC_MspInit + /tmp/ccl4b9YO.s:1135 .text.HAL_TIM_OC_DeInit:00000000 $t + /tmp/ccl4b9YO.s:1141 .text.HAL_TIM_OC_DeInit:00000000 HAL_TIM_OC_DeInit + /tmp/ccl4b9YO.s:1288 .text.HAL_TIM_OC_MspDeInit:00000000 HAL_TIM_OC_MspDeInit + /tmp/ccl4b9YO.s:1246 .text.HAL_TIM_OC_MspInit:00000000 $t + /tmp/ccl4b9YO.s:1282 .text.HAL_TIM_OC_MspDeInit:00000000 $t + /tmp/ccl4b9YO.s:1318 .text.HAL_TIM_OC_Start:00000000 $t + /tmp/ccl4b9YO.s:1324 .text.HAL_TIM_OC_Start:00000000 HAL_TIM_OC_Start + /tmp/ccl4b9YO.s:18739 .text.TIM_CCxChannelCmd:00000000 TIM_CCxChannelCmd + /tmp/ccl4b9YO.s:1631 .text.HAL_TIM_OC_Start:000001cc $d + /tmp/ccl4b9YO.s:1642 .text.HAL_TIM_OC_Stop:00000000 $t + /tmp/ccl4b9YO.s:1648 .text.HAL_TIM_OC_Stop:00000000 HAL_TIM_OC_Stop + /tmp/ccl4b9YO.s:1825 .text.HAL_TIM_OC_Stop:0000010c $d + /tmp/ccl4b9YO.s:1833 .text.HAL_TIM_OC_Start_IT:00000000 $t + /tmp/ccl4b9YO.s:1839 .text.HAL_TIM_OC_Start_IT:00000000 HAL_TIM_OC_Start_IT + /tmp/ccl4b9YO.s:2019 .text.HAL_TIM_OC_Start_IT:00000110 $d + /tmp/ccl4b9YO.s:2032 .text.HAL_TIM_OC_Start_IT:00000144 $t + /tmp/ccl4b9YO.s:2226 .text.HAL_TIM_OC_Start_IT:00000264 $d + /tmp/ccl4b9YO.s:2237 .text.HAL_TIM_OC_Stop_IT:00000000 $t + /tmp/ccl4b9YO.s:2243 .text.HAL_TIM_OC_Stop_IT:00000000 HAL_TIM_OC_Stop_IT + /tmp/ccl4b9YO.s:2270 .text.HAL_TIM_OC_Stop_IT:0000001c $d + /tmp/ccl4b9YO.s:2283 .text.HAL_TIM_OC_Stop_IT:00000050 $t + /tmp/ccl4b9YO.s:2500 .text.HAL_TIM_OC_Stop_IT:000001a8 $d + /tmp/ccl4b9YO.s:2508 .text.HAL_TIM_OC_Start_DMA:00000000 $t + /tmp/ccl4b9YO.s:2514 .text.HAL_TIM_OC_Start_DMA:00000000 HAL_TIM_OC_Start_DMA + /tmp/ccl4b9YO.s:2812 .text.HAL_TIM_OC_Start_DMA:000001c4 $d + ARM GAS /tmp/ccl4b9YO.s page 468 + + + /tmp/ccl4b9YO.s:2825 .text.HAL_TIM_OC_Start_DMA:000001f8 $t + /tmp/ccl4b9YO.s:3175 .text.HAL_TIM_OC_Start_DMA:000003f0 $d + /tmp/ccl4b9YO.s:15976 .text.TIM_DMADelayPulseCplt:00000000 TIM_DMADelayPulseCplt + /tmp/ccl4b9YO.s:16111 .text.TIM_DMADelayPulseHalfCplt:00000000 TIM_DMADelayPulseHalfCplt + /tmp/ccl4b9YO.s:3189 .text.HAL_TIM_OC_Stop_DMA:00000000 $t + /tmp/ccl4b9YO.s:3195 .text.HAL_TIM_OC_Stop_DMA:00000000 HAL_TIM_OC_Stop_DMA + /tmp/ccl4b9YO.s:3222 .text.HAL_TIM_OC_Stop_DMA:0000001c $d + /tmp/ccl4b9YO.s:3235 .text.HAL_TIM_OC_Stop_DMA:00000050 $t + /tmp/ccl4b9YO.s:3472 .text.HAL_TIM_OC_Stop_DMA:000001d0 $d + /tmp/ccl4b9YO.s:3480 .text.HAL_TIM_PWM_Init:00000000 $t + /tmp/ccl4b9YO.s:3486 .text.HAL_TIM_PWM_Init:00000000 HAL_TIM_PWM_Init + /tmp/ccl4b9YO.s:3710 .text.HAL_TIM_PWM_MspInit:00000000 HAL_TIM_PWM_MspInit + /tmp/ccl4b9YO.s:3593 .text.HAL_TIM_PWM_DeInit:00000000 $t + /tmp/ccl4b9YO.s:3599 .text.HAL_TIM_PWM_DeInit:00000000 HAL_TIM_PWM_DeInit + /tmp/ccl4b9YO.s:3746 .text.HAL_TIM_PWM_MspDeInit:00000000 HAL_TIM_PWM_MspDeInit + /tmp/ccl4b9YO.s:3704 .text.HAL_TIM_PWM_MspInit:00000000 $t + /tmp/ccl4b9YO.s:3740 .text.HAL_TIM_PWM_MspDeInit:00000000 $t + /tmp/ccl4b9YO.s:3776 .text.HAL_TIM_PWM_Start:00000000 $t + /tmp/ccl4b9YO.s:3782 .text.HAL_TIM_PWM_Start:00000000 HAL_TIM_PWM_Start + /tmp/ccl4b9YO.s:4089 .text.HAL_TIM_PWM_Start:000001cc $d + /tmp/ccl4b9YO.s:4100 .text.HAL_TIM_PWM_Stop:00000000 $t + /tmp/ccl4b9YO.s:4106 .text.HAL_TIM_PWM_Stop:00000000 HAL_TIM_PWM_Stop + /tmp/ccl4b9YO.s:4283 .text.HAL_TIM_PWM_Stop:0000010c $d + /tmp/ccl4b9YO.s:4291 .text.HAL_TIM_PWM_Start_IT:00000000 $t + /tmp/ccl4b9YO.s:4297 .text.HAL_TIM_PWM_Start_IT:00000000 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TIM_TI1_ConfigInputStage + /tmp/ccl4b9YO.s:18620 .text.TIM_ITRx_SetConfig:00000000 TIM_ITRx_SetConfig + /tmp/ccl4b9YO.s:18344 .text.TIM_TI2_ConfigInputStage:00000000 TIM_TI2_ConfigInputStage + /tmp/ccl4b9YO.s:14717 .text.HAL_TIM_ConfigTI1Input:00000000 $t + /tmp/ccl4b9YO.s:14723 .text.HAL_TIM_ConfigTI1Input:00000000 HAL_TIM_ConfigTI1Input + /tmp/ccl4b9YO.s:14777 .text.HAL_TIM_SlaveConfigSynchro:00000000 $t + /tmp/ccl4b9YO.s:14783 .text.HAL_TIM_SlaveConfigSynchro:00000000 HAL_TIM_SlaveConfigSynchro + /tmp/ccl4b9YO.s:17796 .text.TIM_SlaveTimer_SetConfig:00000000 TIM_SlaveTimer_SetConfig + /tmp/ccl4b9YO.s:14876 .text.HAL_TIM_SlaveConfigSynchro_IT:00000000 $t + /tmp/ccl4b9YO.s:14882 .text.HAL_TIM_SlaveConfigSynchro_IT:00000000 HAL_TIM_SlaveConfigSynchro_IT + /tmp/ccl4b9YO.s:14975 .text.HAL_TIM_ReadCapturedValue:00000000 $t + /tmp/ccl4b9YO.s:14981 .text.HAL_TIM_ReadCapturedValue:00000000 HAL_TIM_ReadCapturedValue + /tmp/ccl4b9YO.s:15008 .text.HAL_TIM_ReadCapturedValue:0000001c $d + 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.text.HAL_TIM_TriggerCallback:00000000 $t + /tmp/ccl4b9YO.s:15367 .text.HAL_TIM_TriggerHalfCpltCallback:00000000 $t + /tmp/ccl4b9YO.s:15373 .text.HAL_TIM_TriggerHalfCpltCallback:00000000 HAL_TIM_TriggerHalfCpltCallback + /tmp/ccl4b9YO.s:15403 .text.HAL_TIM_ErrorCallback:00000000 $t + /tmp/ccl4b9YO.s:15409 .text.HAL_TIM_ErrorCallback:00000000 HAL_TIM_ErrorCallback + /tmp/ccl4b9YO.s:15439 .text.HAL_TIM_Base_GetState:00000000 $t + /tmp/ccl4b9YO.s:15445 .text.HAL_TIM_Base_GetState:00000000 HAL_TIM_Base_GetState + /tmp/ccl4b9YO.s:15479 .text.HAL_TIM_OC_GetState:00000000 $t + /tmp/ccl4b9YO.s:15485 .text.HAL_TIM_OC_GetState:00000000 HAL_TIM_OC_GetState + /tmp/ccl4b9YO.s:15519 .text.HAL_TIM_PWM_GetState:00000000 $t + /tmp/ccl4b9YO.s:15525 .text.HAL_TIM_PWM_GetState:00000000 HAL_TIM_PWM_GetState + /tmp/ccl4b9YO.s:15559 .text.HAL_TIM_IC_GetState:00000000 $t + /tmp/ccl4b9YO.s:15565 .text.HAL_TIM_IC_GetState:00000000 HAL_TIM_IC_GetState + /tmp/ccl4b9YO.s:15599 .text.HAL_TIM_OnePulse_GetState:00000000 $t + /tmp/ccl4b9YO.s:15605 .text.HAL_TIM_OnePulse_GetState:00000000 HAL_TIM_OnePulse_GetState + /tmp/ccl4b9YO.s:15639 .text.HAL_TIM_Encoder_GetState:00000000 $t + /tmp/ccl4b9YO.s:15645 .text.HAL_TIM_Encoder_GetState:00000000 HAL_TIM_Encoder_GetState + /tmp/ccl4b9YO.s:15679 .text.HAL_TIM_GetActiveChannel:00000000 $t + /tmp/ccl4b9YO.s:15685 .text.HAL_TIM_GetActiveChannel:00000000 HAL_TIM_GetActiveChannel + /tmp/ccl4b9YO.s:15718 .text.HAL_TIM_GetChannelState:00000000 $t + /tmp/ccl4b9YO.s:15724 .text.HAL_TIM_GetChannelState:00000000 HAL_TIM_GetChannelState + /tmp/ccl4b9YO.s:15814 .text.HAL_TIM_DMABurstState:00000000 $t + /tmp/ccl4b9YO.s:15820 .text.HAL_TIM_DMABurstState:00000000 HAL_TIM_DMABurstState + /tmp/ccl4b9YO.s:15854 .text.TIM_DMAError:00000000 $t + /tmp/ccl4b9YO.s:15971 .text.TIM_DMADelayPulseCplt:00000000 $t + /tmp/ccl4b9YO.s:16105 .text.TIM_DMADelayPulseHalfCplt:00000000 $t + /tmp/ccl4b9YO.s:16200 .text.TIM_DMACaptureCplt:00000000 $t + /tmp/ccl4b9YO.s:16351 .text.TIM_DMACaptureHalfCplt:00000000 $t + /tmp/ccl4b9YO.s:16446 .text.TIM_DMAPeriodElapsedCplt:00000000 $t + /tmp/ccl4b9YO.s:16498 .text.TIM_DMAPeriodElapsedHalfCplt:00000000 $t + /tmp/ccl4b9YO.s:16537 .text.TIM_DMATriggerCplt:00000000 $t + /tmp/ccl4b9YO.s:16589 .text.TIM_DMATriggerHalfCplt:00000000 $t + /tmp/ccl4b9YO.s:16628 .text.TIM_Base_SetConfig:00000000 $t + ARM GAS /tmp/ccl4b9YO.s page 472 + + + /tmp/ccl4b9YO.s:16802 .text.TIM_Base_SetConfig:000000ec $d + /tmp/ccl4b9YO.s:16812 .text.TIM_OC1_SetConfig:00000000 $t + /tmp/ccl4b9YO.s:16992 .text.TIM_OC1_SetConfig:000000fc $d + /tmp/ccl4b9YO.s:17000 .text.TIM_OC2_SetConfig:00000000 $t + /tmp/ccl4b9YO.s:17175 .text.TIM_OC2_SetConfig:000000f0 $d + /tmp/ccl4b9YO.s:17183 .text.TIM_OC3_SetConfig:00000000 $t + /tmp/ccl4b9YO.s:17355 .text.TIM_OC3_SetConfig:000000ec $d + /tmp/ccl4b9YO.s:17363 .text.TIM_OC4_SetConfig:00000000 $t + /tmp/ccl4b9YO.s:17501 .text.TIM_OC4_SetConfig:000000b8 $d + /tmp/ccl4b9YO.s:17509 .text.TIM_OC5_SetConfig:00000000 $t + /tmp/ccl4b9YO.s:17641 .text.TIM_OC5_SetConfig:000000ac $d + /tmp/ccl4b9YO.s:17649 .text.TIM_OC6_SetConfig:00000000 $t + /tmp/ccl4b9YO.s:17783 .text.TIM_OC6_SetConfig:000000b0 $d + /tmp/ccl4b9YO.s:17791 .text.TIM_SlaveTimer_SetConfig:00000000 $t + /tmp/ccl4b9YO.s:18016 .text.TIM_TI1_SetConfig:00000000 $t + /tmp/ccl4b9YO.s:18153 .text.TIM_TI1_SetConfig:000000b4 $d + /tmp/ccl4b9YO.s:18161 .text.TIM_TI1_ConfigInputStage:00000000 $t + /tmp/ccl4b9YO.s:18241 .text.TIM_TI2_SetConfig:00000000 $t + /tmp/ccl4b9YO.s:18339 .text.TIM_TI2_ConfigInputStage:00000000 $t + /tmp/ccl4b9YO.s:18421 .text.TIM_TI3_SetConfig:00000000 $t + /tmp/ccl4b9YO.s:18517 .text.TIM_TI4_SetConfig:00000000 $t + /tmp/ccl4b9YO.s:18615 .text.TIM_ITRx_SetConfig:00000000 $t + /tmp/ccl4b9YO.s:18669 .text.TIM_ETR_SetConfig:00000000 $t + /tmp/ccl4b9YO.s:18733 .text.TIM_CCxChannelCmd:00000000 $t + +UNDEFINED SYMBOLS +HAL_DMA_Start_IT +HAL_DMA_Abort_IT +HAL_TIMEx_BreakCallback +HAL_TIMEx_Break2Callback +HAL_TIMEx_CommutCallback +TIMEx_DMACommutationCplt +TIMEx_DMACommutationHalfCplt diff --git a/Software/build/stm32f3xx_hal_tim.o b/Software/build/stm32f3xx_hal_tim.o new file mode 100644 index 0000000..8637d6a Binary files /dev/null and b/Software/build/stm32f3xx_hal_tim.o differ diff --git a/Software/build/stm32f3xx_hal_tim_ex.d b/Software/build/stm32f3xx_hal_tim_ex.d new file mode 100644 index 0000000..1e65c44 --- /dev/null +++ b/Software/build/stm32f3xx_hal_tim_ex.d @@ -0,0 +1,62 @@ +build/stm32f3xx_hal_tim_ex.o: \ + Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + Core/Inc/stm32f3xx_hal_conf.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h: diff --git a/Software/build/stm32f3xx_hal_tim_ex.lst b/Software/build/stm32f3xx_hal_tim_ex.lst new file mode 100644 index 0000000..6701db5 --- /dev/null +++ b/Software/build/stm32f3xx_hal_tim_ex.lst @@ -0,0 +1,9661 @@ +ARM GAS /tmp/ccxRWv8k.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 6 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "stm32f3xx_hal_tim_ex.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c" + 20 .section .text.HAL_TIMEx_HallSensor_Init,"ax",%progbits + 21 .align 1 + 22 .global HAL_TIMEx_HallSensor_Init + 23 .syntax unified + 24 .thumb + 25 .thumb_func + 27 HAL_TIMEx_HallSensor_Init: + 28 .LFB130: + 1:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** + 2:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** ****************************************************************************** + 3:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @file stm32f3xx_hal_tim_ex.c + 4:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @author MCD Application Team + 5:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief TIM HAL module driver. + 6:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * This file provides firmware functions to manage the following + 7:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * functionalities of the Timer Extended peripheral: + 8:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * + Time Hall Sensor Interface Initialization + 9:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * + Time Hall Sensor Interface Start + 10:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * + Time Complementary signal break and dead time configuration + 11:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * + Time Master and Slave synchronization configuration + 12:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) + 13:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * + Time OCRef clear configuration + 14:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * + Timer remapping capabilities configuration + 15:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** ****************************************************************************** + 16:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @attention + 17:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * + 18:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * Copyright (c) 2016 STMicroelectronics. + 19:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * All rights reserved. + 20:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * + 21:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * This software is licensed under terms that can be found in the LICENSE file + 22:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * in the root directory of this software component. + 23:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 24:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * + 25:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** ****************************************************************************** + 26:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** @verbatim + 27:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** ============================================================================== + 28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** ##### TIMER Extended features ##### + 29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** ============================================================================== + 30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** [..] + ARM GAS /tmp/ccxRWv8k.s page 2 + + + 31:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** The Timer Extended features include: + 32:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (#) Complementary outputs with programmable dead-time for : + 33:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (++) Output Compare + 34:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (++) PWM generation (Edge and Center-aligned Mode) + 35:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (++) One-pulse mode output + 36:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (#) Synchronization circuit to control the timer with external signals and to + 37:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** interconnect several timers together. + 38:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (#) Break input to put the timer output signals in reset state or in a known state. + 39:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for + 40:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** positioning purposes + 41:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 42:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** ##### How to use this driver ##### + 43:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** ============================================================================== + 44:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** [..] + 45:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (#) Initialize the TIM low level resources by implementing the following functions + 46:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** depending on the selected feature: + 47:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit() + 48:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 49:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (#) Initialize the TIM low level resources : + 50:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); + 51:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (##) TIM pins configuration + 52:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (+++) Enable the clock for the TIM GPIOs using the following function: + 53:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_RCC_GPIOx_CLK_ENABLE(); + 54:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + 55:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 56:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (#) The external Clock can be configured, if needed (the default clock is the + 57:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** internal clock from the APBx), using the following function: + 58:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_TIM_ConfigClockSource, the clock configuration should be done before + 59:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** any start function. + 60:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 61:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (#) Configure the TIM in the desired functioning mode using one of the + 62:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** initialization function of this driver: + 63:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the + 64:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** Timer Hall Sensor Interface and the commutation event with the corresponding + 65:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** Interrupt and DMA request if needed (Note that One Timer is used to interface + 66:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** with the Hall sensor Interface and another Timer should be used to use + 67:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** the commutation event). + 68:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 69:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (#) Activate the TIM peripheral using one of the start functions: + 70:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), + 71:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_TIMEx_OCN_Start_IT() + 72:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), + 73:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_TIMEx_PWMN_Start_IT() + 74:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePul + 75:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA() + 76:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_TIMEx_HallSensor_Start_IT(). + 77:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 78:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** @endverbatim + 79:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** ****************************************************************************** + 80:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ + 81:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 82:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Includes ------------------------------------------------------------------*/ + 83:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** #include "stm32f3xx_hal.h" + 84:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** @addtogroup STM32F3xx_HAL_Driver + 86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @{ + 87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ + ARM GAS /tmp/ccxRWv8k.s page 3 + + + 88:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 89:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** @defgroup TIMEx TIMEx + 90:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief TIM Extended HAL module driver + 91:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @{ + 92:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ + 93:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 94:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** #ifdef HAL_TIM_MODULE_ENABLED + 95:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 96:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Private typedef -----------------------------------------------------------*/ + 97:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Private define ------------------------------------------------------------*/ + 98:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Private macros ------------------------------------------------------------*/ + 99:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Private variables ---------------------------------------------------------*/ + 100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Private function prototypes -----------------------------------------------*/ + 101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma); + 102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma); + 103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState); + 104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Exported functions --------------------------------------------------------*/ + 106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions + 107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @{ + 108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ + 109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions + 111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief Timer Hall Sensor functions + 112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * + 113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** @verbatim + 114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** ============================================================================== + 115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** ##### Timer Hall Sensor functions ##### + 116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** ============================================================================== + 117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** [..] + 118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** This section provides functions allowing to: + 119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (+) Initialize and configure TIM HAL Sensor. + 120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (+) De-initialize TIM HAL Sensor. + 121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (+) Start the Hall Sensor Interface. + 122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (+) Stop the Hall Sensor Interface. + 123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (+) Start the Hall Sensor Interface and enable interrupts. + 124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (+) Stop the Hall Sensor Interface and disable interrupts. + 125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (+) Start the Hall Sensor Interface and enable DMA transfers. + 126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (+) Stop the Hall Sensor Interface and disable DMA transfers. + 127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** @endverbatim + 129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @{ + 130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ + 131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** + 132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle. + 133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @note When the timer instance is initialized in Hall Sensor Interface mode, + 134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * timer channels 1 and channel 2 are reserved and cannot be used for + 135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * other purpose. + 136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param htim TIM Hall Sensor Interface handle + 137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param sConfig TIM Hall Sensor configuration structure + 138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @retval HAL status + 139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ + 140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeD + 141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 29 .loc 1 141 1 + 30 .cfi_startproc + 31 @ args = 0, pretend = 0, frame = 40 + ARM GAS /tmp/ccxRWv8k.s page 4 + + + 32 @ frame_needed = 1, uses_anonymous_args = 0 + 33 0000 80B5 push {r7, lr} + 34 .cfi_def_cfa_offset 8 + 35 .cfi_offset 7, -8 + 36 .cfi_offset 14, -4 + 37 0002 8AB0 sub sp, sp, #40 + 38 .cfi_def_cfa_offset 48 + 39 0004 00AF add r7, sp, #0 + 40 .cfi_def_cfa_register 7 + 41 0006 7860 str r0, [r7, #4] + 42 0008 3960 str r1, [r7] + 142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_OC_InitTypeDef OC_Config; + 143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Check the TIM handle allocation */ + 145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (htim == NULL) + 43 .loc 1 145 6 + 44 000a 7B68 ldr r3, [r7, #4] + 45 000c 002B cmp r3, #0 + 46 000e 01D1 bne .L2 + 146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return HAL_ERROR; + 47 .loc 1 147 12 + 48 0010 0123 movs r3, #1 + 49 0012 9CE0 b .L5 + 50 .L2: + 148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Check the parameters */ + 151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + 152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + 153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + 154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + 155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); + 156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + 157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + 158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + 159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (htim->State == HAL_TIM_STATE_RESET) + 51 .loc 1 160 11 + 52 0014 7B68 ldr r3, [r7, #4] + 53 0016 93F83D30 ldrb r3, [r3, #61] + 54 001a DBB2 uxtb r3, r3 + 55 .loc 1 160 6 + 56 001c 002B cmp r3, #0 + 57 001e 06D1 bne .L4 + 161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Allocate lock resource and initialize it */ + 163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->Lock = HAL_UNLOCKED; + 58 .loc 1 163 16 + 59 0020 7B68 ldr r3, [r7, #4] + 60 0022 0022 movs r2, #0 + 61 0024 83F83C20 strb r2, [r3, #60] + 164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + 166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Reset interrupt callbacks to legacy week callbacks */ + 167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_ResetCallback(htim); + 168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + ARM GAS /tmp/ccxRWv8k.s page 5 + + + 169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (htim->HallSensor_MspInitCallback == NULL) + 170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; + 172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Init the low level hardware : GPIO, CLOCK, NVIC */ + 174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->HallSensor_MspInitCallback(htim); + 175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** #else + 176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + 177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_TIMEx_HallSensor_MspInit(htim); + 62 .loc 1 177 5 + 63 0028 7868 ldr r0, [r7, #4] + 64 002a FFF7FEFF bl HAL_TIMEx_HallSensor_MspInit + 65 .L4: + 178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Set the TIM state */ + 182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->State = HAL_TIM_STATE_BUSY; + 66 .loc 1 182 15 + 67 002e 7B68 ldr r3, [r7, #4] + 68 0030 0222 movs r2, #2 + 69 0032 83F83D20 strb r2, [r3, #61] + 183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Configure the Time base in the Encoder Mode */ + 185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_Base_SetConfig(htim->Instance, &htim->Init); + 70 .loc 1 185 3 + 71 0036 7B68 ldr r3, [r7, #4] + 72 0038 1A68 ldr r2, [r3] + 73 .loc 1 185 38 + 74 003a 7B68 ldr r3, [r7, #4] + 75 003c 0433 adds r3, r3, #4 + 76 .loc 1 185 3 + 77 003e 1946 mov r1, r3 + 78 0040 1046 mov r0, r2 + 79 0042 FFF7FEFF bl TIM_Base_SetConfig + 186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sens + 188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter); + 80 .loc 1 188 3 + 81 0046 7B68 ldr r3, [r7, #4] + 82 0048 1868 ldr r0, [r3] + 83 .loc 1 188 44 + 84 004a 3B68 ldr r3, [r7] + 85 004c 1968 ldr r1, [r3] + 86 .loc 1 188 87 + 87 004e 3B68 ldr r3, [r7] + 88 0050 9B68 ldr r3, [r3, #8] + 89 .loc 1 188 3 + 90 0052 0322 movs r2, #3 + 91 0054 FFF7FEFF bl TIM_TI1_SetConfig + 189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Reset the IC1PSC Bits */ + 191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + 92 .loc 1 191 7 + 93 0058 7B68 ldr r3, [r7, #4] + 94 005a 1B68 ldr r3, [r3] + 95 .loc 1 191 17 + ARM GAS /tmp/ccxRWv8k.s page 6 + + + 96 005c 9A69 ldr r2, [r3, #24] + 97 .loc 1 191 7 + 98 005e 7B68 ldr r3, [r7, #4] + 99 0060 1B68 ldr r3, [r3] + 100 .loc 1 191 25 + 101 0062 22F00C02 bic r2, r2, #12 + 102 0066 9A61 str r2, [r3, #24] + 192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Set the IC1PSC value */ + 193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->Instance->CCMR1 |= sConfig->IC1Prescaler; + 103 .loc 1 193 7 + 104 0068 7B68 ldr r3, [r7, #4] + 105 006a 1B68 ldr r3, [r3] + 106 .loc 1 193 17 + 107 006c 9969 ldr r1, [r3, #24] + 108 .loc 1 193 35 + 109 006e 3B68 ldr r3, [r7] + 110 0070 5A68 ldr r2, [r3, #4] + 111 .loc 1 193 7 + 112 0072 7B68 ldr r3, [r7, #4] + 113 0074 1B68 ldr r3, [r3] + 114 .loc 1 193 25 + 115 0076 0A43 orrs r2, r2, r1 + 116 0078 9A61 str r2, [r3, #24] + 194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the Hall sensor interface (XOR function of the three inputs) */ + 196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->Instance->CR2 |= TIM_CR2_TI1S; + 117 .loc 1 196 7 + 118 007a 7B68 ldr r3, [r7, #4] + 119 007c 1B68 ldr r3, [r3] + 120 .loc 1 196 17 + 121 007e 5A68 ldr r2, [r3, #4] + 122 .loc 1 196 7 + 123 0080 7B68 ldr r3, [r7, #4] + 124 0082 1B68 ldr r3, [r3] + 125 .loc 1 196 23 + 126 0084 42F08002 orr r2, r2, #128 + 127 0088 5A60 str r2, [r3, #4] + 197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */ + 199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->Instance->SMCR &= ~TIM_SMCR_TS; + 128 .loc 1 199 7 + 129 008a 7B68 ldr r3, [r7, #4] + 130 008c 1B68 ldr r3, [r3] + 131 .loc 1 199 17 + 132 008e 9A68 ldr r2, [r3, #8] + 133 .loc 1 199 7 + 134 0090 7B68 ldr r3, [r7, #4] + 135 0092 1B68 ldr r3, [r3] + 136 .loc 1 199 24 + 137 0094 22F07002 bic r2, r2, #112 + 138 0098 9A60 str r2, [r3, #8] + 200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->Instance->SMCR |= TIM_TS_TI1F_ED; + 139 .loc 1 200 7 + 140 009a 7B68 ldr r3, [r7, #4] + 141 009c 1B68 ldr r3, [r3] + 142 .loc 1 200 17 + 143 009e 9A68 ldr r2, [r3, #8] + ARM GAS /tmp/ccxRWv8k.s page 7 + + + 144 .loc 1 200 7 + 145 00a0 7B68 ldr r3, [r7, #4] + 146 00a2 1B68 ldr r3, [r3] + 147 .loc 1 200 24 + 148 00a4 42F04002 orr r2, r2, #64 + 149 00a8 9A60 str r2, [r3, #8] + 201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */ + 203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->Instance->SMCR &= ~TIM_SMCR_SMS; + 150 .loc 1 203 7 + 151 00aa 7B68 ldr r3, [r7, #4] + 152 00ac 1B68 ldr r3, [r3] + 153 .loc 1 203 17 + 154 00ae 9B68 ldr r3, [r3, #8] + 155 .loc 1 203 7 + 156 00b0 7A68 ldr r2, [r7, #4] + 157 00b2 1268 ldr r2, [r2] + 158 .loc 1 203 24 + 159 00b4 23F48033 bic r3, r3, #65536 + 160 00b8 23F00703 bic r3, r3, #7 + 161 00bc 9360 str r3, [r2, #8] + 204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->Instance->SMCR |= TIM_SLAVEMODE_RESET; + 162 .loc 1 204 7 + 163 00be 7B68 ldr r3, [r7, #4] + 164 00c0 1B68 ldr r3, [r3] + 165 .loc 1 204 17 + 166 00c2 9A68 ldr r2, [r3, #8] + 167 .loc 1 204 7 + 168 00c4 7B68 ldr r3, [r7, #4] + 169 00c6 1B68 ldr r3, [r3] + 170 .loc 1 204 24 + 171 00c8 42F00402 orr r2, r2, #4 + 172 00cc 9A60 str r2, [r3, #8] + 205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/ + 207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** OC_Config.OCFastMode = TIM_OCFAST_DISABLE; + 173 .loc 1 207 24 + 174 00ce 0023 movs r3, #0 + 175 00d0 FB61 str r3, [r7, #28] + 208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET; + 176 .loc 1 208 25 + 177 00d2 0023 movs r3, #0 + 178 00d4 3B62 str r3, [r7, #32] + 209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** OC_Config.OCMode = TIM_OCMODE_PWM2; + 179 .loc 1 209 20 + 180 00d6 7023 movs r3, #112 + 181 00d8 FB60 str r3, [r7, #12] + 210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET; + 182 .loc 1 210 26 + 183 00da 0023 movs r3, #0 + 184 00dc 7B62 str r3, [r7, #36] + 211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH; + 185 .loc 1 211 25 + 186 00de 0023 movs r3, #0 + 187 00e0 BB61 str r3, [r7, #24] + 212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH; + 188 .loc 1 212 24 + ARM GAS /tmp/ccxRWv8k.s page 8 + + + 189 00e2 0023 movs r3, #0 + 190 00e4 7B61 str r3, [r7, #20] + 213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** OC_Config.Pulse = sConfig->Commutation_Delay; + 191 .loc 1 213 28 + 192 00e6 3B68 ldr r3, [r7] + 193 00e8 DB68 ldr r3, [r3, #12] + 194 .loc 1 213 19 + 195 00ea 3B61 str r3, [r7, #16] + 214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_OC2_SetConfig(htim->Instance, &OC_Config); + 196 .loc 1 215 3 + 197 00ec 7B68 ldr r3, [r7, #4] + 198 00ee 1B68 ldr r3, [r3] + 199 00f0 07F10C02 add r2, r7, #12 + 200 00f4 1146 mov r1, r2 + 201 00f6 1846 mov r0, r3 + 202 00f8 FFF7FEFF bl TIM_OC2_SetConfig + 216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 + 218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** register to 101 */ + 219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->Instance->CR2 &= ~TIM_CR2_MMS; + 203 .loc 1 219 7 + 204 00fc 7B68 ldr r3, [r7, #4] + 205 00fe 1B68 ldr r3, [r3] + 206 .loc 1 219 17 + 207 0100 5A68 ldr r2, [r3, #4] + 208 .loc 1 219 7 + 209 0102 7B68 ldr r3, [r7, #4] + 210 0104 1B68 ldr r3, [r3] + 211 .loc 1 219 23 + 212 0106 22F07002 bic r2, r2, #112 + 213 010a 5A60 str r2, [r3, #4] + 220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->Instance->CR2 |= TIM_TRGO_OC2REF; + 214 .loc 1 220 7 + 215 010c 7B68 ldr r3, [r7, #4] + 216 010e 1B68 ldr r3, [r3] + 217 .loc 1 220 17 + 218 0110 5A68 ldr r2, [r3, #4] + 219 .loc 1 220 7 + 220 0112 7B68 ldr r3, [r7, #4] + 221 0114 1B68 ldr r3, [r3] + 222 .loc 1 220 23 + 223 0116 42F05002 orr r2, r2, #80 + 224 011a 5A60 str r2, [r3, #4] + 221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Initialize the DMA burst operation state */ + 223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + 225 .loc 1 223 23 + 226 011c 7B68 ldr r3, [r7, #4] + 227 011e 0122 movs r2, #1 + 228 0120 83F84820 strb r2, [r3, #72] + 224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Initialize the TIM channels state */ + 226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 229 .loc 1 226 3 + 230 0124 7B68 ldr r3, [r7, #4] + 231 0126 0122 movs r2, #1 + ARM GAS /tmp/ccxRWv8k.s page 9 + + + 232 0128 83F83E20 strb r2, [r3, #62] + 227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 233 .loc 1 227 3 + 234 012c 7B68 ldr r3, [r7, #4] + 235 012e 0122 movs r2, #1 + 236 0130 83F83F20 strb r2, [r3, #63] + 228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 237 .loc 1 228 3 + 238 0134 7B68 ldr r3, [r7, #4] + 239 0136 0122 movs r2, #1 + 240 0138 83F84420 strb r2, [r3, #68] + 229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 241 .loc 1 229 3 + 242 013c 7B68 ldr r3, [r7, #4] + 243 013e 0122 movs r2, #1 + 244 0140 83F84520 strb r2, [r3, #69] + 230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Initialize the TIM state*/ + 232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->State = HAL_TIM_STATE_READY; + 245 .loc 1 232 15 + 246 0144 7B68 ldr r3, [r7, #4] + 247 0146 0122 movs r2, #1 + 248 0148 83F83D20 strb r2, [r3, #61] + 233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return HAL_OK; + 249 .loc 1 234 10 + 250 014c 0023 movs r3, #0 + 251 .L5: + 235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 252 .loc 1 235 1 + 253 014e 1846 mov r0, r3 + 254 0150 2837 adds r7, r7, #40 + 255 .cfi_def_cfa_offset 8 + 256 0152 BD46 mov sp, r7 + 257 .cfi_def_cfa_register 13 + 258 @ sp needed + 259 0154 80BD pop {r7, pc} + 260 .cfi_endproc + 261 .LFE130: + 263 .section .text.HAL_TIMEx_HallSensor_DeInit,"ax",%progbits + 264 .align 1 + 265 .global HAL_TIMEx_HallSensor_DeInit + 266 .syntax unified + 267 .thumb + 268 .thumb_func + 270 HAL_TIMEx_HallSensor_DeInit: + 271 .LFB131: + 236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** + 238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief DeInitializes the TIM Hall Sensor interface + 239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param htim TIM Hall Sensor Interface handle + 240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @retval HAL status + 241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ + 242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) + 243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 272 .loc 1 243 1 + 273 .cfi_startproc + ARM GAS /tmp/ccxRWv8k.s page 10 + + + 274 @ args = 0, pretend = 0, frame = 8 + 275 @ frame_needed = 1, uses_anonymous_args = 0 + 276 0000 80B5 push {r7, lr} + 277 .cfi_def_cfa_offset 8 + 278 .cfi_offset 7, -8 + 279 .cfi_offset 14, -4 + 280 0002 82B0 sub sp, sp, #8 + 281 .cfi_def_cfa_offset 16 + 282 0004 00AF add r7, sp, #0 + 283 .cfi_def_cfa_register 7 + 284 0006 7860 str r0, [r7, #4] + 244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Check the parameters */ + 245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_INSTANCE(htim->Instance)); + 246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->State = HAL_TIM_STATE_BUSY; + 285 .loc 1 247 15 + 286 0008 7B68 ldr r3, [r7, #4] + 287 000a 0222 movs r2, #2 + 288 000c 83F83D20 strb r2, [r3, #61] + 248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable the TIM Peripheral Clock */ + 250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_DISABLE(htim); + 289 .loc 1 250 3 + 290 0010 7B68 ldr r3, [r7, #4] + 291 0012 1B68 ldr r3, [r3] + 292 0014 1A6A ldr r2, [r3, #32] + 293 0016 41F21113 movw r3, #4369 + 294 001a 1340 ands r3, r3, r2 + 295 001c 002B cmp r3, #0 + 296 001e 0FD1 bne .L7 + 297 .loc 1 250 3 is_stmt 0 discriminator 1 + 298 0020 7B68 ldr r3, [r7, #4] + 299 0022 1B68 ldr r3, [r3] + 300 0024 1A6A ldr r2, [r3, #32] + 301 0026 40F24443 movw r3, #1092 + 302 002a 1340 ands r3, r3, r2 + 303 002c 002B cmp r3, #0 + 304 002e 07D1 bne .L7 + 305 .loc 1 250 3 discriminator 2 + 306 0030 7B68 ldr r3, [r7, #4] + 307 0032 1B68 ldr r3, [r3] + 308 0034 1A68 ldr r2, [r3] + 309 0036 7B68 ldr r3, [r7, #4] + 310 0038 1B68 ldr r3, [r3] + 311 003a 22F00102 bic r2, r2, #1 + 312 003e 1A60 str r2, [r3] + 313 .L7: + 251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + 253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (htim->HallSensor_MspDeInitCallback == NULL) + 254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; + 256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* DeInit the low level hardware */ + 258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->HallSensor_MspDeInitCallback(htim); + 259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** #else + 260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + ARM GAS /tmp/ccxRWv8k.s page 11 + + + 261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_TIMEx_HallSensor_MspDeInit(htim); + 314 .loc 1 261 3 is_stmt 1 + 315 0040 7868 ldr r0, [r7, #4] + 316 0042 FFF7FEFF bl HAL_TIMEx_HallSensor_MspDeInit + 262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + 263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Change the DMA burst operation state */ + 265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + 317 .loc 1 265 23 + 318 0046 7B68 ldr r3, [r7, #4] + 319 0048 0022 movs r2, #0 + 320 004a 83F84820 strb r2, [r3, #72] + 266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Change the TIM channels state */ + 268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + 321 .loc 1 268 3 + 322 004e 7B68 ldr r3, [r7, #4] + 323 0050 0022 movs r2, #0 + 324 0052 83F83E20 strb r2, [r3, #62] + 269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + 325 .loc 1 269 3 + 326 0056 7B68 ldr r3, [r7, #4] + 327 0058 0022 movs r2, #0 + 328 005a 83F83F20 strb r2, [r3, #63] + 270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + 329 .loc 1 270 3 + 330 005e 7B68 ldr r3, [r7, #4] + 331 0060 0022 movs r2, #0 + 332 0062 83F84420 strb r2, [r3, #68] + 271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + 333 .loc 1 271 3 + 334 0066 7B68 ldr r3, [r7, #4] + 335 0068 0022 movs r2, #0 + 336 006a 83F84520 strb r2, [r3, #69] + 272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Change TIM state */ + 274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->State = HAL_TIM_STATE_RESET; + 337 .loc 1 274 15 + 338 006e 7B68 ldr r3, [r7, #4] + 339 0070 0022 movs r2, #0 + 340 0072 83F83D20 strb r2, [r3, #61] + 275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Release Lock */ + 277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_UNLOCK(htim); + 341 .loc 1 277 3 + 342 0076 7B68 ldr r3, [r7, #4] + 343 0078 0022 movs r2, #0 + 344 007a 83F83C20 strb r2, [r3, #60] + 278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return HAL_OK; + 345 .loc 1 279 10 + 346 007e 0023 movs r3, #0 + 280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 347 .loc 1 280 1 + 348 0080 1846 mov r0, r3 + 349 0082 0837 adds r7, r7, #8 + 350 .cfi_def_cfa_offset 8 + ARM GAS /tmp/ccxRWv8k.s page 12 + + + 351 0084 BD46 mov sp, r7 + 352 .cfi_def_cfa_register 13 + 353 @ sp needed + 354 0086 80BD pop {r7, pc} + 355 .cfi_endproc + 356 .LFE131: + 358 .section .text.HAL_TIMEx_HallSensor_MspInit,"ax",%progbits + 359 .align 1 + 360 .weak HAL_TIMEx_HallSensor_MspInit + 361 .syntax unified + 362 .thumb + 363 .thumb_func + 365 HAL_TIMEx_HallSensor_MspInit: + 366 .LFB132: + 281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** + 283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief Initializes the TIM Hall Sensor MSP. + 284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param htim TIM Hall Sensor Interface handle + 285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @retval None + 286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ + 287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) + 288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 367 .loc 1 288 1 + 368 .cfi_startproc + 369 @ args = 0, pretend = 0, frame = 8 + 370 @ frame_needed = 1, uses_anonymous_args = 0 + 371 @ link register save eliminated. + 372 0000 80B4 push {r7} + 373 .cfi_def_cfa_offset 4 + 374 .cfi_offset 7, -4 + 375 0002 83B0 sub sp, sp, #12 + 376 .cfi_def_cfa_offset 16 + 377 0004 00AF add r7, sp, #0 + 378 .cfi_def_cfa_register 7 + 379 0006 7860 str r0, [r7, #4] + 289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Prevent unused argument(s) compilation warning */ + 290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** UNUSED(htim); + 291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* NOTE : This function should not be modified, when the callback is needed, + 293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file + 294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ + 295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 380 .loc 1 295 1 + 381 0008 00BF nop + 382 000a 0C37 adds r7, r7, #12 + 383 .cfi_def_cfa_offset 4 + 384 000c BD46 mov sp, r7 + 385 .cfi_def_cfa_register 13 + 386 @ sp needed + 387 000e 5DF8047B ldr r7, [sp], #4 + 388 .cfi_restore 7 + 389 .cfi_def_cfa_offset 0 + 390 0012 7047 bx lr + 391 .cfi_endproc + 392 .LFE132: + 394 .section .text.HAL_TIMEx_HallSensor_MspDeInit,"ax",%progbits + 395 .align 1 + ARM GAS /tmp/ccxRWv8k.s page 13 + + + 396 .weak HAL_TIMEx_HallSensor_MspDeInit + 397 .syntax unified + 398 .thumb + 399 .thumb_func + 401 HAL_TIMEx_HallSensor_MspDeInit: + 402 .LFB133: + 296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** + 298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief DeInitializes TIM Hall Sensor MSP. + 299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param htim TIM Hall Sensor Interface handle + 300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @retval None + 301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ + 302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) + 303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 403 .loc 1 303 1 + 404 .cfi_startproc + 405 @ args = 0, pretend = 0, frame = 8 + 406 @ frame_needed = 1, uses_anonymous_args = 0 + 407 @ link register save eliminated. + 408 0000 80B4 push {r7} + 409 .cfi_def_cfa_offset 4 + 410 .cfi_offset 7, -4 + 411 0002 83B0 sub sp, sp, #12 + 412 .cfi_def_cfa_offset 16 + 413 0004 00AF add r7, sp, #0 + 414 .cfi_def_cfa_register 7 + 415 0006 7860 str r0, [r7, #4] + 304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Prevent unused argument(s) compilation warning */ + 305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** UNUSED(htim); + 306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* NOTE : This function should not be modified, when the callback is needed, + 308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file + 309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ + 310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 416 .loc 1 310 1 + 417 0008 00BF nop + 418 000a 0C37 adds r7, r7, #12 + 419 .cfi_def_cfa_offset 4 + 420 000c BD46 mov sp, r7 + 421 .cfi_def_cfa_register 13 + 422 @ sp needed + 423 000e 5DF8047B ldr r7, [sp], #4 + 424 .cfi_restore 7 + 425 .cfi_def_cfa_offset 0 + 426 0012 7047 bx lr + 427 .cfi_endproc + 428 .LFE133: + 430 .section .text.HAL_TIMEx_HallSensor_Start,"ax",%progbits + 431 .align 1 + 432 .global HAL_TIMEx_HallSensor_Start + 433 .syntax unified + 434 .thumb + 435 .thumb_func + 437 HAL_TIMEx_HallSensor_Start: + 438 .LFB134: + 311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** + ARM GAS /tmp/ccxRWv8k.s page 14 + + + 313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief Starts the TIM Hall Sensor Interface. + 314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param htim TIM Hall Sensor Interface handle + 315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @retval HAL status + 316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ + 317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) + 318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 439 .loc 1 318 1 + 440 .cfi_startproc + 441 @ args = 0, pretend = 0, frame = 16 + 442 @ frame_needed = 1, uses_anonymous_args = 0 + 443 0000 80B5 push {r7, lr} + 444 .cfi_def_cfa_offset 8 + 445 .cfi_offset 7, -8 + 446 .cfi_offset 14, -4 + 447 0002 84B0 sub sp, sp, #16 + 448 .cfi_def_cfa_offset 24 + 449 0004 00AF add r7, sp, #0 + 450 .cfi_def_cfa_register 7 + 451 0006 7860 str r0, [r7, #4] + 319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** uint32_t tmpsmcr; + 320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + 452 .loc 1 320 31 + 453 0008 7B68 ldr r3, [r7, #4] + 454 000a 93F83E30 ldrb r3, [r3, #62] + 455 000e FB73 strb r3, [r7, #15] + 321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + 456 .loc 1 321 31 + 457 0010 7B68 ldr r3, [r7, #4] + 458 0012 93F83F30 ldrb r3, [r3, #63] + 459 0016 BB73 strb r3, [r7, #14] + 322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 460 .loc 1 322 31 + 461 0018 7B68 ldr r3, [r7, #4] + 462 001a 93F84430 ldrb r3, [r3, #68] + 463 001e 7B73 strb r3, [r7, #13] + 323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 464 .loc 1 323 31 + 465 0020 7B68 ldr r3, [r7, #4] + 466 0022 93F84530 ldrb r3, [r3, #69] + 467 0026 3B73 strb r3, [r7, #12] + 324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Check the parameters */ + 326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + 327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Check the TIM channels state */ + 329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + 468 .loc 1 329 6 + 469 0028 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 470 002a 012B cmp r3, #1 + 471 002c 08D1 bne .L12 + 330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + 472 .loc 1 330 7 + 473 002e BB7B ldrb r3, [r7, #14] @ zero_extendqisi2 + 474 0030 012B cmp r3, #1 + 475 0032 05D1 bne .L12 + 331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + 476 .loc 1 331 7 + ARM GAS /tmp/ccxRWv8k.s page 15 + + + 477 0034 7B7B ldrb r3, [r7, #13] @ zero_extendqisi2 + 478 0036 012B cmp r3, #1 + 479 0038 02D1 bne .L12 + 332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + 480 .loc 1 332 7 + 481 003a 3B7B ldrb r3, [r7, #12] @ zero_extendqisi2 + 482 003c 012B cmp r3, #1 + 483 003e 01D0 beq .L13 + 484 .L12: + 333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return HAL_ERROR; + 485 .loc 1 334 12 + 486 0040 0123 movs r3, #1 + 487 0042 50E0 b .L14 + 488 .L13: + 335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Set the TIM channels state */ + 338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + 489 .loc 1 338 3 + 490 0044 7B68 ldr r3, [r7, #4] + 491 0046 0222 movs r2, #2 + 492 0048 83F83E20 strb r2, [r3, #62] + 339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 493 .loc 1 339 3 + 494 004c 7B68 ldr r3, [r7, #4] + 495 004e 0222 movs r2, #2 + 496 0050 83F83F20 strb r2, [r3, #63] + 340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + 497 .loc 1 340 3 + 498 0054 7B68 ldr r3, [r7, #4] + 499 0056 0222 movs r2, #2 + 500 0058 83F84420 strb r2, [r3, #68] + 341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 501 .loc 1 341 3 + 502 005c 7B68 ldr r3, [r7, #4] + 503 005e 0222 movs r2, #2 + 504 0060 83F84520 strb r2, [r3, #69] + 342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the Input Capture channel 1 + 344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + 345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + 346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + 505 .loc 1 346 3 + 506 0064 7B68 ldr r3, [r7, #4] + 507 0066 1B68 ldr r3, [r3] + 508 0068 0122 movs r2, #1 + 509 006a 0021 movs r1, #0 + 510 006c 1846 mov r0, r3 + 511 006e FFF7FEFF bl TIM_CCxChannelCmd + 347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger + 349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 512 .loc 1 349 7 + 513 0072 7B68 ldr r3, [r7, #4] + 514 0074 1B68 ldr r3, [r3] + 515 .loc 1 349 6 + ARM GAS /tmp/ccxRWv8k.s page 16 + + + 516 0076 1E4A ldr r2, .L20 + 517 0078 9342 cmp r3, r2 + 518 007a 13D0 beq .L15 + 519 .loc 1 349 7 discriminator 1 + 520 007c 7B68 ldr r3, [r7, #4] + 521 007e 1B68 ldr r3, [r3] + 522 0080 B3F1804F cmp r3, #1073741824 + 523 0084 0ED0 beq .L15 + 524 .loc 1 349 7 is_stmt 0 discriminator 2 + 525 0086 7B68 ldr r3, [r7, #4] + 526 0088 1B68 ldr r3, [r3] + 527 008a 1A4A ldr r2, .L20+4 + 528 008c 9342 cmp r3, r2 + 529 008e 09D0 beq .L15 + 530 .loc 1 349 7 discriminator 3 + 531 0090 7B68 ldr r3, [r7, #4] + 532 0092 1B68 ldr r3, [r3] + 533 0094 184A ldr r2, .L20+8 + 534 0096 9342 cmp r3, r2 + 535 0098 04D0 beq .L15 + 536 .loc 1 349 7 discriminator 4 + 537 009a 7B68 ldr r3, [r7, #4] + 538 009c 1B68 ldr r3, [r3] + 539 009e 174A ldr r2, .L20+12 + 540 00a0 9342 cmp r3, r2 + 541 00a2 15D1 bne .L16 + 542 .L15: + 350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + 543 .loc 1 351 19 is_stmt 1 + 544 00a4 7B68 ldr r3, [r7, #4] + 545 00a6 1B68 ldr r3, [r3] + 546 .loc 1 351 29 + 547 00a8 9A68 ldr r2, [r3, #8] + 548 .loc 1 351 13 + 549 00aa 154B ldr r3, .L20+16 + 550 00ac 1340 ands r3, r3, r2 + 551 00ae BB60 str r3, [r7, #8] + 352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 552 .loc 1 352 8 + 553 00b0 BB68 ldr r3, [r7, #8] + 554 00b2 062B cmp r3, #6 + 555 00b4 15D0 beq .L19 + 556 .loc 1 352 9 discriminator 1 + 557 00b6 BB68 ldr r3, [r7, #8] + 558 00b8 B3F5803F cmp r3, #65536 + 559 00bc 11D0 beq .L19 + 353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_ENABLE(htim); + 560 .loc 1 354 7 + 561 00be 7B68 ldr r3, [r7, #4] + 562 00c0 1B68 ldr r3, [r3] + 563 00c2 1A68 ldr r2, [r3] + 564 00c4 7B68 ldr r3, [r7, #4] + 565 00c6 1B68 ldr r3, [r3] + 566 00c8 42F00102 orr r2, r2, #1 + 567 00cc 1A60 str r2, [r3] + ARM GAS /tmp/ccxRWv8k.s page 17 + + + 352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 568 .loc 1 352 8 + 569 00ce 08E0 b .L19 + 570 .L16: + 355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** else + 358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_ENABLE(htim); + 571 .loc 1 359 5 + 572 00d0 7B68 ldr r3, [r7, #4] + 573 00d2 1B68 ldr r3, [r3] + 574 00d4 1A68 ldr r2, [r3] + 575 00d6 7B68 ldr r3, [r7, #4] + 576 00d8 1B68 ldr r3, [r3] + 577 00da 42F00102 orr r2, r2, #1 + 578 00de 1A60 str r2, [r3] + 579 00e0 00E0 b .L18 + 580 .L19: + 352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 581 .loc 1 352 8 + 582 00e2 00BF nop + 583 .L18: + 360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Return function status */ + 363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return HAL_OK; + 584 .loc 1 363 10 + 585 00e4 0023 movs r3, #0 + 586 .L14: + 364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 587 .loc 1 364 1 + 588 00e6 1846 mov r0, r3 + 589 00e8 1037 adds r7, r7, #16 + 590 .cfi_def_cfa_offset 8 + 591 00ea BD46 mov sp, r7 + 592 .cfi_def_cfa_register 13 + 593 @ sp needed + 594 00ec 80BD pop {r7, pc} + 595 .L21: + 596 00ee 00BF .align 2 + 597 .L20: + 598 00f0 002C0140 .word 1073818624 + 599 00f4 00040040 .word 1073742848 + 600 00f8 00080040 .word 1073743872 + 601 00fc 00400140 .word 1073823744 + 602 0100 07000100 .word 65543 + 603 .cfi_endproc + 604 .LFE134: + 606 .section .text.HAL_TIMEx_HallSensor_Stop,"ax",%progbits + 607 .align 1 + 608 .global HAL_TIMEx_HallSensor_Stop + 609 .syntax unified + 610 .thumb + 611 .thumb_func + 613 HAL_TIMEx_HallSensor_Stop: + 614 .LFB135: + ARM GAS /tmp/ccxRWv8k.s page 18 + + + 365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** + 367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief Stops the TIM Hall sensor Interface. + 368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param htim TIM Hall Sensor Interface handle + 369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @retval HAL status + 370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ + 371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) + 372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 615 .loc 1 372 1 + 616 .cfi_startproc + 617 @ args = 0, pretend = 0, frame = 8 + 618 @ frame_needed = 1, uses_anonymous_args = 0 + 619 0000 80B5 push {r7, lr} + 620 .cfi_def_cfa_offset 8 + 621 .cfi_offset 7, -8 + 622 .cfi_offset 14, -4 + 623 0002 82B0 sub sp, sp, #8 + 624 .cfi_def_cfa_offset 16 + 625 0004 00AF add r7, sp, #0 + 626 .cfi_def_cfa_register 7 + 627 0006 7860 str r0, [r7, #4] + 373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Check the parameters */ + 374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + 375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable the Input Capture channels 1, 2 and 3 + 377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + 378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + 379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + 628 .loc 1 379 3 + 629 0008 7B68 ldr r3, [r7, #4] + 630 000a 1B68 ldr r3, [r3] + 631 000c 0022 movs r2, #0 + 632 000e 0021 movs r1, #0 + 633 0010 1846 mov r0, r3 + 634 0012 FFF7FEFF bl TIM_CCxChannelCmd + 380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable the Peripheral */ + 382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_DISABLE(htim); + 635 .loc 1 382 3 + 636 0016 7B68 ldr r3, [r7, #4] + 637 0018 1B68 ldr r3, [r3] + 638 001a 1A6A ldr r2, [r3, #32] + 639 001c 41F21113 movw r3, #4369 + 640 0020 1340 ands r3, r3, r2 + 641 0022 002B cmp r3, #0 + 642 0024 0FD1 bne .L23 + 643 .loc 1 382 3 is_stmt 0 discriminator 1 + 644 0026 7B68 ldr r3, [r7, #4] + 645 0028 1B68 ldr r3, [r3] + 646 002a 1A6A ldr r2, [r3, #32] + 647 002c 40F24443 movw r3, #1092 + 648 0030 1340 ands r3, r3, r2 + 649 0032 002B cmp r3, #0 + 650 0034 07D1 bne .L23 + 651 .loc 1 382 3 discriminator 2 + 652 0036 7B68 ldr r3, [r7, #4] + 653 0038 1B68 ldr r3, [r3] + ARM GAS /tmp/ccxRWv8k.s page 19 + + + 654 003a 1A68 ldr r2, [r3] + 655 003c 7B68 ldr r3, [r7, #4] + 656 003e 1B68 ldr r3, [r3] + 657 0040 22F00102 bic r2, r2, #1 + 658 0044 1A60 str r2, [r3] + 659 .L23: + 383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Set the TIM channels state */ + 385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 660 .loc 1 385 3 is_stmt 1 + 661 0046 7B68 ldr r3, [r7, #4] + 662 0048 0122 movs r2, #1 + 663 004a 83F83E20 strb r2, [r3, #62] + 386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 664 .loc 1 386 3 + 665 004e 7B68 ldr r3, [r7, #4] + 666 0050 0122 movs r2, #1 + 667 0052 83F83F20 strb r2, [r3, #63] + 387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 668 .loc 1 387 3 + 669 0056 7B68 ldr r3, [r7, #4] + 670 0058 0122 movs r2, #1 + 671 005a 83F84420 strb r2, [r3, #68] + 388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 672 .loc 1 388 3 + 673 005e 7B68 ldr r3, [r7, #4] + 674 0060 0122 movs r2, #1 + 675 0062 83F84520 strb r2, [r3, #69] + 389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Return function status */ + 391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return HAL_OK; + 676 .loc 1 391 10 + 677 0066 0023 movs r3, #0 + 392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 678 .loc 1 392 1 + 679 0068 1846 mov r0, r3 + 680 006a 0837 adds r7, r7, #8 + 681 .cfi_def_cfa_offset 8 + 682 006c BD46 mov sp, r7 + 683 .cfi_def_cfa_register 13 + 684 @ sp needed + 685 006e 80BD pop {r7, pc} + 686 .cfi_endproc + 687 .LFE135: + 689 .section .text.HAL_TIMEx_HallSensor_Start_IT,"ax",%progbits + 690 .align 1 + 691 .global HAL_TIMEx_HallSensor_Start_IT + 692 .syntax unified + 693 .thumb + 694 .thumb_func + 696 HAL_TIMEx_HallSensor_Start_IT: + 697 .LFB136: + 393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** + 395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief Starts the TIM Hall Sensor Interface in interrupt mode. + 396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param htim TIM Hall Sensor Interface handle + 397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @retval HAL status + ARM GAS /tmp/ccxRWv8k.s page 20 + + + 398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ + 399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) + 400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 698 .loc 1 400 1 + 699 .cfi_startproc + 700 @ args = 0, pretend = 0, frame = 16 + 701 @ frame_needed = 1, uses_anonymous_args = 0 + 702 0000 80B5 push {r7, lr} + 703 .cfi_def_cfa_offset 8 + 704 .cfi_offset 7, -8 + 705 .cfi_offset 14, -4 + 706 0002 84B0 sub sp, sp, #16 + 707 .cfi_def_cfa_offset 24 + 708 0004 00AF add r7, sp, #0 + 709 .cfi_def_cfa_register 7 + 710 0006 7860 str r0, [r7, #4] + 401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** uint32_t tmpsmcr; + 402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + 711 .loc 1 402 31 + 712 0008 7B68 ldr r3, [r7, #4] + 713 000a 93F83E30 ldrb r3, [r3, #62] + 714 000e FB73 strb r3, [r7, #15] + 403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + 715 .loc 1 403 31 + 716 0010 7B68 ldr r3, [r7, #4] + 717 0012 93F83F30 ldrb r3, [r3, #63] + 718 0016 BB73 strb r3, [r7, #14] + 404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 719 .loc 1 404 31 + 720 0018 7B68 ldr r3, [r7, #4] + 721 001a 93F84430 ldrb r3, [r3, #68] + 722 001e 7B73 strb r3, [r7, #13] + 405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 723 .loc 1 405 31 + 724 0020 7B68 ldr r3, [r7, #4] + 725 0022 93F84530 ldrb r3, [r3, #69] + 726 0026 3B73 strb r3, [r7, #12] + 406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Check the parameters */ + 408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + 409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Check the TIM channels state */ + 411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + 727 .loc 1 411 6 + 728 0028 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 729 002a 012B cmp r3, #1 + 730 002c 08D1 bne .L26 + 412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + 731 .loc 1 412 7 + 732 002e BB7B ldrb r3, [r7, #14] @ zero_extendqisi2 + 733 0030 012B cmp r3, #1 + 734 0032 05D1 bne .L26 + 413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + 735 .loc 1 413 7 + 736 0034 7B7B ldrb r3, [r7, #13] @ zero_extendqisi2 + 737 0036 012B cmp r3, #1 + 738 0038 02D1 bne .L26 + ARM GAS /tmp/ccxRWv8k.s page 21 + + + 414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + 739 .loc 1 414 7 + 740 003a 3B7B ldrb r3, [r7, #12] @ zero_extendqisi2 + 741 003c 012B cmp r3, #1 + 742 003e 01D0 beq .L27 + 743 .L26: + 415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return HAL_ERROR; + 744 .loc 1 416 12 + 745 0040 0123 movs r3, #1 + 746 0042 58E0 b .L28 + 747 .L27: + 417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Set the TIM channels state */ + 420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + 748 .loc 1 420 3 + 749 0044 7B68 ldr r3, [r7, #4] + 750 0046 0222 movs r2, #2 + 751 0048 83F83E20 strb r2, [r3, #62] + 421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 752 .loc 1 421 3 + 753 004c 7B68 ldr r3, [r7, #4] + 754 004e 0222 movs r2, #2 + 755 0050 83F83F20 strb r2, [r3, #63] + 422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + 756 .loc 1 422 3 + 757 0054 7B68 ldr r3, [r7, #4] + 758 0056 0222 movs r2, #2 + 759 0058 83F84420 strb r2, [r3, #68] + 423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 760 .loc 1 423 3 + 761 005c 7B68 ldr r3, [r7, #4] + 762 005e 0222 movs r2, #2 + 763 0060 83F84520 strb r2, [r3, #69] + 424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the capture compare Interrupts 1 event */ + 426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + 764 .loc 1 426 3 + 765 0064 7B68 ldr r3, [r7, #4] + 766 0066 1B68 ldr r3, [r3] + 767 0068 DA68 ldr r2, [r3, #12] + 768 006a 7B68 ldr r3, [r7, #4] + 769 006c 1B68 ldr r3, [r3] + 770 006e 42F00202 orr r2, r2, #2 + 771 0072 DA60 str r2, [r3, #12] + 427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the Input Capture channel 1 + 429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + 430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + 431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + 772 .loc 1 431 3 + 773 0074 7B68 ldr r3, [r7, #4] + 774 0076 1B68 ldr r3, [r3] + 775 0078 0122 movs r2, #1 + 776 007a 0021 movs r1, #0 + 777 007c 1846 mov r0, r3 + ARM GAS /tmp/ccxRWv8k.s page 22 + + + 778 007e FFF7FEFF bl TIM_CCxChannelCmd + 432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger + 434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 779 .loc 1 434 7 + 780 0082 7B68 ldr r3, [r7, #4] + 781 0084 1B68 ldr r3, [r3] + 782 .loc 1 434 6 + 783 0086 1E4A ldr r2, .L34 + 784 0088 9342 cmp r3, r2 + 785 008a 13D0 beq .L29 + 786 .loc 1 434 7 discriminator 1 + 787 008c 7B68 ldr r3, [r7, #4] + 788 008e 1B68 ldr r3, [r3] + 789 0090 B3F1804F cmp r3, #1073741824 + 790 0094 0ED0 beq .L29 + 791 .loc 1 434 7 is_stmt 0 discriminator 2 + 792 0096 7B68 ldr r3, [r7, #4] + 793 0098 1B68 ldr r3, [r3] + 794 009a 1A4A ldr r2, .L34+4 + 795 009c 9342 cmp r3, r2 + 796 009e 09D0 beq .L29 + 797 .loc 1 434 7 discriminator 3 + 798 00a0 7B68 ldr r3, [r7, #4] + 799 00a2 1B68 ldr r3, [r3] + 800 00a4 184A ldr r2, .L34+8 + 801 00a6 9342 cmp r3, r2 + 802 00a8 04D0 beq .L29 + 803 .loc 1 434 7 discriminator 4 + 804 00aa 7B68 ldr r3, [r7, #4] + 805 00ac 1B68 ldr r3, [r3] + 806 00ae 174A ldr r2, .L34+12 + 807 00b0 9342 cmp r3, r2 + 808 00b2 15D1 bne .L30 + 809 .L29: + 435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + 810 .loc 1 436 19 is_stmt 1 + 811 00b4 7B68 ldr r3, [r7, #4] + 812 00b6 1B68 ldr r3, [r3] + 813 .loc 1 436 29 + 814 00b8 9A68 ldr r2, [r3, #8] + 815 .loc 1 436 13 + 816 00ba 154B ldr r3, .L34+16 + 817 00bc 1340 ands r3, r3, r2 + 818 00be BB60 str r3, [r7, #8] + 437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 819 .loc 1 437 8 + 820 00c0 BB68 ldr r3, [r7, #8] + 821 00c2 062B cmp r3, #6 + 822 00c4 15D0 beq .L33 + 823 .loc 1 437 9 discriminator 1 + 824 00c6 BB68 ldr r3, [r7, #8] + 825 00c8 B3F5803F cmp r3, #65536 + 826 00cc 11D0 beq .L33 + 438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_ENABLE(htim); + ARM GAS /tmp/ccxRWv8k.s page 23 + + + 827 .loc 1 439 7 + 828 00ce 7B68 ldr r3, [r7, #4] + 829 00d0 1B68 ldr r3, [r3] + 830 00d2 1A68 ldr r2, [r3] + 831 00d4 7B68 ldr r3, [r7, #4] + 832 00d6 1B68 ldr r3, [r3] + 833 00d8 42F00102 orr r2, r2, #1 + 834 00dc 1A60 str r2, [r3] + 437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 835 .loc 1 437 8 + 836 00de 08E0 b .L33 + 837 .L30: + 440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** else + 443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_ENABLE(htim); + 838 .loc 1 444 5 + 839 00e0 7B68 ldr r3, [r7, #4] + 840 00e2 1B68 ldr r3, [r3] + 841 00e4 1A68 ldr r2, [r3] + 842 00e6 7B68 ldr r3, [r7, #4] + 843 00e8 1B68 ldr r3, [r3] + 844 00ea 42F00102 orr r2, r2, #1 + 845 00ee 1A60 str r2, [r3] + 846 00f0 00E0 b .L32 + 847 .L33: + 437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 848 .loc 1 437 8 + 849 00f2 00BF nop + 850 .L32: + 445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Return function status */ + 448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return HAL_OK; + 851 .loc 1 448 10 + 852 00f4 0023 movs r3, #0 + 853 .L28: + 449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 854 .loc 1 449 1 + 855 00f6 1846 mov r0, r3 + 856 00f8 1037 adds r7, r7, #16 + 857 .cfi_def_cfa_offset 8 + 858 00fa BD46 mov sp, r7 + 859 .cfi_def_cfa_register 13 + 860 @ sp needed + 861 00fc 80BD pop {r7, pc} + 862 .L35: + 863 00fe 00BF .align 2 + 864 .L34: + 865 0100 002C0140 .word 1073818624 + 866 0104 00040040 .word 1073742848 + 867 0108 00080040 .word 1073743872 + 868 010c 00400140 .word 1073823744 + 869 0110 07000100 .word 65543 + 870 .cfi_endproc + 871 .LFE136: + ARM GAS /tmp/ccxRWv8k.s page 24 + + + 873 .section .text.HAL_TIMEx_HallSensor_Stop_IT,"ax",%progbits + 874 .align 1 + 875 .global HAL_TIMEx_HallSensor_Stop_IT + 876 .syntax unified + 877 .thumb + 878 .thumb_func + 880 HAL_TIMEx_HallSensor_Stop_IT: + 881 .LFB137: + 450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** + 452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief Stops the TIM Hall Sensor Interface in interrupt mode. + 453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param htim TIM Hall Sensor Interface handle + 454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @retval HAL status + 455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ + 456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) + 457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 882 .loc 1 457 1 + 883 .cfi_startproc + 884 @ args = 0, pretend = 0, frame = 8 + 885 @ frame_needed = 1, uses_anonymous_args = 0 + 886 0000 80B5 push {r7, lr} + 887 .cfi_def_cfa_offset 8 + 888 .cfi_offset 7, -8 + 889 .cfi_offset 14, -4 + 890 0002 82B0 sub sp, sp, #8 + 891 .cfi_def_cfa_offset 16 + 892 0004 00AF add r7, sp, #0 + 893 .cfi_def_cfa_register 7 + 894 0006 7860 str r0, [r7, #4] + 458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Check the parameters */ + 459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + 460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable the Input Capture channel 1 + 462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + 463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + 464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + 895 .loc 1 464 3 + 896 0008 7B68 ldr r3, [r7, #4] + 897 000a 1B68 ldr r3, [r3] + 898 000c 0022 movs r2, #0 + 899 000e 0021 movs r1, #0 + 900 0010 1846 mov r0, r3 + 901 0012 FFF7FEFF bl TIM_CCxChannelCmd + 465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable the capture compare Interrupts event */ + 467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + 902 .loc 1 467 3 + 903 0016 7B68 ldr r3, [r7, #4] + 904 0018 1B68 ldr r3, [r3] + 905 001a DA68 ldr r2, [r3, #12] + 906 001c 7B68 ldr r3, [r7, #4] + 907 001e 1B68 ldr r3, [r3] + 908 0020 22F00202 bic r2, r2, #2 + 909 0024 DA60 str r2, [r3, #12] + 468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable the Peripheral */ + 470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_DISABLE(htim); + ARM GAS /tmp/ccxRWv8k.s page 25 + + + 910 .loc 1 470 3 + 911 0026 7B68 ldr r3, [r7, #4] + 912 0028 1B68 ldr r3, [r3] + 913 002a 1A6A ldr r2, [r3, #32] + 914 002c 41F21113 movw r3, #4369 + 915 0030 1340 ands r3, r3, r2 + 916 0032 002B cmp r3, #0 + 917 0034 0FD1 bne .L37 + 918 .loc 1 470 3 is_stmt 0 discriminator 1 + 919 0036 7B68 ldr r3, [r7, #4] + 920 0038 1B68 ldr r3, [r3] + 921 003a 1A6A ldr r2, [r3, #32] + 922 003c 40F24443 movw r3, #1092 + 923 0040 1340 ands r3, r3, r2 + 924 0042 002B cmp r3, #0 + 925 0044 07D1 bne .L37 + 926 .loc 1 470 3 discriminator 2 + 927 0046 7B68 ldr r3, [r7, #4] + 928 0048 1B68 ldr r3, [r3] + 929 004a 1A68 ldr r2, [r3] + 930 004c 7B68 ldr r3, [r7, #4] + 931 004e 1B68 ldr r3, [r3] + 932 0050 22F00102 bic r2, r2, #1 + 933 0054 1A60 str r2, [r3] + 934 .L37: + 471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Set the TIM channels state */ + 473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 935 .loc 1 473 3 is_stmt 1 + 936 0056 7B68 ldr r3, [r7, #4] + 937 0058 0122 movs r2, #1 + 938 005a 83F83E20 strb r2, [r3, #62] + 474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 939 .loc 1 474 3 + 940 005e 7B68 ldr r3, [r7, #4] + 941 0060 0122 movs r2, #1 + 942 0062 83F83F20 strb r2, [r3, #63] + 475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 943 .loc 1 475 3 + 944 0066 7B68 ldr r3, [r7, #4] + 945 0068 0122 movs r2, #1 + 946 006a 83F84420 strb r2, [r3, #68] + 476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 947 .loc 1 476 3 + 948 006e 7B68 ldr r3, [r7, #4] + 949 0070 0122 movs r2, #1 + 950 0072 83F84520 strb r2, [r3, #69] + 477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Return function status */ + 479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return HAL_OK; + 951 .loc 1 479 10 + 952 0076 0023 movs r3, #0 + 480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 953 .loc 1 480 1 + 954 0078 1846 mov r0, r3 + 955 007a 0837 adds r7, r7, #8 + 956 .cfi_def_cfa_offset 8 + ARM GAS /tmp/ccxRWv8k.s page 26 + + + 957 007c BD46 mov sp, r7 + 958 .cfi_def_cfa_register 13 + 959 @ sp needed + 960 007e 80BD pop {r7, pc} + 961 .cfi_endproc + 962 .LFE137: + 964 .section .text.HAL_TIMEx_HallSensor_Start_DMA,"ax",%progbits + 965 .align 1 + 966 .global HAL_TIMEx_HallSensor_Start_DMA + 967 .syntax unified + 968 .thumb + 969 .thumb_func + 971 HAL_TIMEx_HallSensor_Start_DMA: + 972 .LFB138: + 481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** + 483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief Starts the TIM Hall Sensor Interface in DMA mode. + 484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param htim TIM Hall Sensor Interface handle + 485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param pData The destination Buffer address. + 486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param Length The length of data to be transferred from TIM peripheral to memory. + 487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @retval HAL status + 488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ + 489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t + 490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 973 .loc 1 490 1 + 974 .cfi_startproc + 975 @ args = 0, pretend = 0, frame = 24 + 976 @ frame_needed = 1, uses_anonymous_args = 0 + 977 0000 80B5 push {r7, lr} + 978 .cfi_def_cfa_offset 8 + 979 .cfi_offset 7, -8 + 980 .cfi_offset 14, -4 + 981 0002 86B0 sub sp, sp, #24 + 982 .cfi_def_cfa_offset 32 + 983 0004 00AF add r7, sp, #0 + 984 .cfi_def_cfa_register 7 + 985 0006 F860 str r0, [r7, #12] + 986 0008 B960 str r1, [r7, #8] + 987 000a 1346 mov r3, r2 + 988 000c FB80 strh r3, [r7, #6] @ movhi + 491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** uint32_t tmpsmcr; + 492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + 989 .loc 1 492 31 + 990 000e FB68 ldr r3, [r7, #12] + 991 0010 93F83E30 ldrb r3, [r3, #62] + 992 0014 FB75 strb r3, [r7, #23] + 493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 993 .loc 1 493 31 + 994 0016 FB68 ldr r3, [r7, #12] + 995 0018 93F84430 ldrb r3, [r3, #68] + 996 001c BB75 strb r3, [r7, #22] + 494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Check the parameters */ + 496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + 497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Set the TIM channel state */ + 499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + ARM GAS /tmp/ccxRWv8k.s page 27 + + + 997 .loc 1 499 6 + 998 001e FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 999 0020 022B cmp r3, #2 + 1000 0022 02D0 beq .L40 + 500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) + 1001 .loc 1 500 7 + 1002 0024 BB7D ldrb r3, [r7, #22] @ zero_extendqisi2 + 1003 0026 022B cmp r3, #2 + 1004 0028 01D1 bne .L41 + 1005 .L40: + 501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return HAL_BUSY; + 1006 .loc 1 502 12 + 1007 002a 0223 movs r3, #2 + 1008 002c 7DE0 b .L42 + 1009 .L41: + 503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + 1010 .loc 1 504 11 + 1011 002e FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 1012 0030 012B cmp r3, #1 + 1013 0032 34D1 bne .L43 + 505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) + 1014 .loc 1 505 12 + 1015 0034 BB7D ldrb r3, [r7, #22] @ zero_extendqisi2 + 1016 0036 012B cmp r3, #1 + 1017 0038 31D1 bne .L43 + 506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if ((pData == NULL) || (Length == 0U)) + 1018 .loc 1 507 8 + 1019 003a BB68 ldr r3, [r7, #8] + 1020 003c 002B cmp r3, #0 + 1021 003e 02D0 beq .L44 + 1022 .loc 1 507 25 discriminator 1 + 1023 0040 FB88 ldrh r3, [r7, #6] + 1024 0042 002B cmp r3, #0 + 1025 0044 01D1 bne .L45 + 1026 .L44: + 508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return HAL_ERROR; + 1027 .loc 1 509 14 + 1028 0046 0123 movs r3, #1 + 1029 0048 6FE0 b .L42 + 1030 .L45: + 510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** else + 512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + 1031 .loc 1 513 7 + 1032 004a FB68 ldr r3, [r7, #12] + 1033 004c 0222 movs r2, #2 + 1034 004e 83F83E20 strb r2, [r3, #62] + 514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + 1035 .loc 1 514 7 + 1036 0052 FB68 ldr r3, [r7, #12] + 1037 0054 0222 movs r2, #2 + 1038 0056 83F84420 strb r2, [r3, #68] + ARM GAS /tmp/ccxRWv8k.s page 28 + + + 507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 1039 .loc 1 507 8 + 1040 005a 00BF nop + 515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** else + 518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return HAL_ERROR; + 520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the Input Capture channel 1 + 523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + 524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + 525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + 1041 .loc 1 525 3 + 1042 005c FB68 ldr r3, [r7, #12] + 1043 005e 1B68 ldr r3, [r3] + 1044 0060 0122 movs r2, #1 + 1045 0062 0021 movs r1, #0 + 1046 0064 1846 mov r0, r3 + 1047 0066 FFF7FEFF bl TIM_CCxChannelCmd + 526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Set the DMA Input Capture 1 Callbacks */ + 528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + 1048 .loc 1 528 13 + 1049 006a FB68 ldr r3, [r7, #12] + 1050 006c 5B6A ldr r3, [r3, #36] + 1051 .loc 1 528 48 + 1052 006e 314A ldr r2, .L54 + 1053 0070 9A62 str r2, [r3, #40] + 529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + 1054 .loc 1 529 13 + 1055 0072 FB68 ldr r3, [r7, #12] + 1056 0074 5B6A ldr r3, [r3, #36] + 1057 .loc 1 529 52 + 1058 0076 304A ldr r2, .L54+4 + 1059 0078 DA62 str r2, [r3, #44] + 530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Set the DMA error callback */ + 531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + 1060 .loc 1 531 13 + 1061 007a FB68 ldr r3, [r7, #12] + 1062 007c 5B6A ldr r3, [r3, #36] + 1063 .loc 1 531 49 + 1064 007e 2F4A ldr r2, .L54+8 + 1065 0080 1A63 str r2, [r3, #48] + 532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the DMA channel for Capture 1*/ + 534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData + 1066 .loc 1 534 7 + 1067 0082 FB68 ldr r3, [r7, #12] + 1068 0084 586A ldr r0, [r3, #36] + 1069 .loc 1 534 67 + 1070 0086 FB68 ldr r3, [r7, #12] + 1071 0088 1B68 ldr r3, [r3] + 1072 .loc 1 534 62 + 1073 008a 3433 adds r3, r3, #52 + 1074 .loc 1 534 7 + ARM GAS /tmp/ccxRWv8k.s page 29 + + + 1075 008c 1946 mov r1, r3 + 1076 008e BA68 ldr r2, [r7, #8] + 1077 0090 FB88 ldrh r3, [r7, #6] + 1078 0092 FFF7FEFF bl HAL_DMA_Start_IT + 1079 0096 0346 mov r3, r0 + 1080 .loc 1 534 6 discriminator 1 + 1081 0098 002B cmp r3, #0 + 1082 009a 04D0 beq .L47 + 1083 009c 01E0 b .L52 + 1084 .L43: + 519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 1085 .loc 1 519 12 + 1086 009e 0123 movs r3, #1 + 1087 00a0 43E0 b .L42 + 1088 .L52: + 535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Return error status */ + 537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return HAL_ERROR; + 1089 .loc 1 537 12 + 1090 00a2 0123 movs r3, #1 + 1091 00a4 41E0 b .L42 + 1092 .L47: + 538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the capture compare 1 Interrupt */ + 540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + 1093 .loc 1 540 3 + 1094 00a6 FB68 ldr r3, [r7, #12] + 1095 00a8 1B68 ldr r3, [r3] + 1096 00aa DA68 ldr r2, [r3, #12] + 1097 00ac FB68 ldr r3, [r7, #12] + 1098 00ae 1B68 ldr r3, [r3] + 1099 00b0 42F40072 orr r2, r2, #512 + 1100 00b4 DA60 str r2, [r3, #12] + 541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger + 543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 1101 .loc 1 543 7 + 1102 00b6 FB68 ldr r3, [r7, #12] + 1103 00b8 1B68 ldr r3, [r3] + 1104 .loc 1 543 6 + 1105 00ba 214A ldr r2, .L54+12 + 1106 00bc 9342 cmp r3, r2 + 1107 00be 13D0 beq .L48 + 1108 .loc 1 543 7 discriminator 1 + 1109 00c0 FB68 ldr r3, [r7, #12] + 1110 00c2 1B68 ldr r3, [r3] + 1111 00c4 B3F1804F cmp r3, #1073741824 + 1112 00c8 0ED0 beq .L48 + 1113 .loc 1 543 7 is_stmt 0 discriminator 2 + 1114 00ca FB68 ldr r3, [r7, #12] + 1115 00cc 1B68 ldr r3, [r3] + 1116 00ce 1D4A ldr r2, .L54+16 + 1117 00d0 9342 cmp r3, r2 + 1118 00d2 09D0 beq .L48 + 1119 .loc 1 543 7 discriminator 3 + 1120 00d4 FB68 ldr r3, [r7, #12] + 1121 00d6 1B68 ldr r3, [r3] + ARM GAS /tmp/ccxRWv8k.s page 30 + + + 1122 00d8 1B4A ldr r2, .L54+20 + 1123 00da 9342 cmp r3, r2 + 1124 00dc 04D0 beq .L48 + 1125 .loc 1 543 7 discriminator 4 + 1126 00de FB68 ldr r3, [r7, #12] + 1127 00e0 1B68 ldr r3, [r3] + 1128 00e2 1A4A ldr r2, .L54+24 + 1129 00e4 9342 cmp r3, r2 + 1130 00e6 15D1 bne .L49 + 1131 .L48: + 544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + 1132 .loc 1 545 19 is_stmt 1 + 1133 00e8 FB68 ldr r3, [r7, #12] + 1134 00ea 1B68 ldr r3, [r3] + 1135 .loc 1 545 29 + 1136 00ec 9A68 ldr r2, [r3, #8] + 1137 .loc 1 545 13 + 1138 00ee 184B ldr r3, .L54+28 + 1139 00f0 1340 ands r3, r3, r2 + 1140 00f2 3B61 str r3, [r7, #16] + 546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 1141 .loc 1 546 8 + 1142 00f4 3B69 ldr r3, [r7, #16] + 1143 00f6 062B cmp r3, #6 + 1144 00f8 15D0 beq .L53 + 1145 .loc 1 546 9 discriminator 1 + 1146 00fa 3B69 ldr r3, [r7, #16] + 1147 00fc B3F5803F cmp r3, #65536 + 1148 0100 11D0 beq .L53 + 547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_ENABLE(htim); + 1149 .loc 1 548 7 + 1150 0102 FB68 ldr r3, [r7, #12] + 1151 0104 1B68 ldr r3, [r3] + 1152 0106 1A68 ldr r2, [r3] + 1153 0108 FB68 ldr r3, [r7, #12] + 1154 010a 1B68 ldr r3, [r3] + 1155 010c 42F00102 orr r2, r2, #1 + 1156 0110 1A60 str r2, [r3] + 546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 1157 .loc 1 546 8 + 1158 0112 08E0 b .L53 + 1159 .L49: + 549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** else + 552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_ENABLE(htim); + 1160 .loc 1 553 5 + 1161 0114 FB68 ldr r3, [r7, #12] + 1162 0116 1B68 ldr r3, [r3] + 1163 0118 1A68 ldr r2, [r3] + 1164 011a FB68 ldr r3, [r7, #12] + 1165 011c 1B68 ldr r3, [r3] + 1166 011e 42F00102 orr r2, r2, #1 + 1167 0122 1A60 str r2, [r3] + ARM GAS /tmp/ccxRWv8k.s page 31 + + + 1168 0124 00E0 b .L51 + 1169 .L53: + 546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 1170 .loc 1 546 8 + 1171 0126 00BF nop + 1172 .L51: + 554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Return function status */ + 557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return HAL_OK; + 1173 .loc 1 557 10 + 1174 0128 0023 movs r3, #0 + 1175 .L42: + 558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 1176 .loc 1 558 1 + 1177 012a 1846 mov r0, r3 + 1178 012c 1837 adds r7, r7, #24 + 1179 .cfi_def_cfa_offset 8 + 1180 012e BD46 mov sp, r7 + 1181 .cfi_def_cfa_register 13 + 1182 @ sp needed + 1183 0130 80BD pop {r7, pc} + 1184 .L55: + 1185 0132 00BF .align 2 + 1186 .L54: + 1187 0134 00000000 .word TIM_DMACaptureCplt + 1188 0138 00000000 .word TIM_DMACaptureHalfCplt + 1189 013c 00000000 .word TIM_DMAError + 1190 0140 002C0140 .word 1073818624 + 1191 0144 00040040 .word 1073742848 + 1192 0148 00080040 .word 1073743872 + 1193 014c 00400140 .word 1073823744 + 1194 0150 07000100 .word 65543 + 1195 .cfi_endproc + 1196 .LFE138: + 1198 .section .text.HAL_TIMEx_HallSensor_Stop_DMA,"ax",%progbits + 1199 .align 1 + 1200 .global HAL_TIMEx_HallSensor_Stop_DMA + 1201 .syntax unified + 1202 .thumb + 1203 .thumb_func + 1205 HAL_TIMEx_HallSensor_Stop_DMA: + 1206 .LFB139: + 559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** + 561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief Stops the TIM Hall Sensor Interface in DMA mode. + 562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param htim TIM Hall Sensor Interface handle + 563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @retval HAL status + 564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ + 565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) + 566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 1207 .loc 1 566 1 + 1208 .cfi_startproc + 1209 @ args = 0, pretend = 0, frame = 8 + 1210 @ frame_needed = 1, uses_anonymous_args = 0 + 1211 0000 80B5 push {r7, lr} + 1212 .cfi_def_cfa_offset 8 + ARM GAS /tmp/ccxRWv8k.s page 32 + + + 1213 .cfi_offset 7, -8 + 1214 .cfi_offset 14, -4 + 1215 0002 82B0 sub sp, sp, #8 + 1216 .cfi_def_cfa_offset 16 + 1217 0004 00AF add r7, sp, #0 + 1218 .cfi_def_cfa_register 7 + 1219 0006 7860 str r0, [r7, #4] + 567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Check the parameters */ + 568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + 569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable the Input Capture channel 1 + 571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + 572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + 573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + 1220 .loc 1 573 3 + 1221 0008 7B68 ldr r3, [r7, #4] + 1222 000a 1B68 ldr r3, [r3] + 1223 000c 0022 movs r2, #0 + 1224 000e 0021 movs r1, #0 + 1225 0010 1846 mov r0, r3 + 1226 0012 FFF7FEFF bl TIM_CCxChannelCmd + 574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable the capture compare Interrupts 1 event */ + 577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + 1227 .loc 1 577 3 + 1228 0016 7B68 ldr r3, [r7, #4] + 1229 0018 1B68 ldr r3, [r3] + 1230 001a DA68 ldr r2, [r3, #12] + 1231 001c 7B68 ldr r3, [r7, #4] + 1232 001e 1B68 ldr r3, [r3] + 1233 0020 22F40072 bic r2, r2, #512 + 1234 0024 DA60 str r2, [r3, #12] + 578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + 1235 .loc 1 579 9 + 1236 0026 7B68 ldr r3, [r7, #4] + 1237 0028 5B6A ldr r3, [r3, #36] + 1238 002a 1846 mov r0, r3 + 1239 002c FFF7FEFF bl HAL_DMA_Abort_IT + 580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable the Peripheral */ + 582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_DISABLE(htim); + 1240 .loc 1 582 3 + 1241 0030 7B68 ldr r3, [r7, #4] + 1242 0032 1B68 ldr r3, [r3] + 1243 0034 1A6A ldr r2, [r3, #32] + 1244 0036 41F21113 movw r3, #4369 + 1245 003a 1340 ands r3, r3, r2 + 1246 003c 002B cmp r3, #0 + 1247 003e 0FD1 bne .L57 + 1248 .loc 1 582 3 is_stmt 0 discriminator 1 + 1249 0040 7B68 ldr r3, [r7, #4] + 1250 0042 1B68 ldr r3, [r3] + 1251 0044 1A6A ldr r2, [r3, #32] + 1252 0046 40F24443 movw r3, #1092 + 1253 004a 1340 ands r3, r3, r2 + ARM GAS /tmp/ccxRWv8k.s page 33 + + + 1254 004c 002B cmp r3, #0 + 1255 004e 07D1 bne .L57 + 1256 .loc 1 582 3 discriminator 2 + 1257 0050 7B68 ldr r3, [r7, #4] + 1258 0052 1B68 ldr r3, [r3] + 1259 0054 1A68 ldr r2, [r3] + 1260 0056 7B68 ldr r3, [r7, #4] + 1261 0058 1B68 ldr r3, [r3] + 1262 005a 22F00102 bic r2, r2, #1 + 1263 005e 1A60 str r2, [r3] + 1264 .L57: + 583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Set the TIM channel state */ + 585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 1265 .loc 1 585 3 is_stmt 1 + 1266 0060 7B68 ldr r3, [r7, #4] + 1267 0062 0122 movs r2, #1 + 1268 0064 83F83E20 strb r2, [r3, #62] + 586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 1269 .loc 1 586 3 + 1270 0068 7B68 ldr r3, [r7, #4] + 1271 006a 0122 movs r2, #1 + 1272 006c 83F84420 strb r2, [r3, #68] + 587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Return function status */ + 589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return HAL_OK; + 1273 .loc 1 589 10 + 1274 0070 0023 movs r3, #0 + 590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 1275 .loc 1 590 1 + 1276 0072 1846 mov r0, r3 + 1277 0074 0837 adds r7, r7, #8 + 1278 .cfi_def_cfa_offset 8 + 1279 0076 BD46 mov sp, r7 + 1280 .cfi_def_cfa_register 13 + 1281 @ sp needed + 1282 0078 80BD pop {r7, pc} + 1283 .cfi_endproc + 1284 .LFE139: + 1286 .section .text.HAL_TIMEx_OCN_Start,"ax",%progbits + 1287 .align 1 + 1288 .global HAL_TIMEx_OCN_Start + 1289 .syntax unified + 1290 .thumb + 1291 .thumb_func + 1293 HAL_TIMEx_OCN_Start: + 1294 .LFB140: + 591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** + 593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @} + 594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ + 595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions + 597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief Timer Complementary Output Compare functions + 598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * + 599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** @verbatim + 600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** ============================================================================== + ARM GAS /tmp/ccxRWv8k.s page 34 + + + 601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** ##### Timer Complementary Output Compare functions ##### + 602:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** ============================================================================== + 603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** [..] + 604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** This section provides functions allowing to: + 605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (+) Start the Complementary Output Compare/PWM. + 606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (+) Stop the Complementary Output Compare/PWM. + 607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (+) Start the Complementary Output Compare/PWM and enable interrupts. + 608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (+) Stop the Complementary Output Compare/PWM and disable interrupts. + 609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (+) Start the Complementary Output Compare/PWM and enable DMA transfers. + 610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (+) Stop the Complementary Output Compare/PWM and disable DMA transfers. + 611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 612:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** @endverbatim + 613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @{ + 614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ + 615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** + 617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief Starts the TIM Output Compare signal generation on the complementary + 618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * output. + 619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param htim TIM Output Compare handle + 620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param Channel TIM Channel to be enabled + 621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * This parameter can be one of the following values: + 622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected + 623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected + 624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected + 625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @retval HAL status + 626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ + 627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) + 628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 1295 .loc 1 628 1 + 1296 .cfi_startproc + 1297 @ args = 0, pretend = 0, frame = 16 + 1298 @ frame_needed = 1, uses_anonymous_args = 0 + 1299 0000 80B5 push {r7, lr} + 1300 .cfi_def_cfa_offset 8 + 1301 .cfi_offset 7, -8 + 1302 .cfi_offset 14, -4 + 1303 0002 84B0 sub sp, sp, #16 + 1304 .cfi_def_cfa_offset 24 + 1305 0004 00AF add r7, sp, #0 + 1306 .cfi_def_cfa_register 7 + 1307 0006 7860 str r0, [r7, #4] + 1308 0008 3960 str r1, [r7] + 629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** uint32_t tmpsmcr; + 630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Check the parameters */ + 632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + 633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Check the TIM complementary channel state */ + 635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + 1309 .loc 1 635 46 + 1310 000a 3B68 ldr r3, [r7] + 1311 000c 002B cmp r3, #0 + 1312 000e 09D1 bne .L60 + 1313 .loc 1 635 7 discriminator 1 + 1314 0010 7B68 ldr r3, [r7, #4] + 1315 0012 93F84430 ldrb r3, [r3, #68] + 1316 0016 DBB2 uxtb r3, r3 + ARM GAS /tmp/ccxRWv8k.s page 35 + + + 1317 .loc 1 635 46 discriminator 1 + 1318 0018 012B cmp r3, #1 + 1319 001a 14BF ite ne + 1320 001c 0123 movne r3, #1 + 1321 001e 0023 moveq r3, #0 + 1322 0020 DBB2 uxtb r3, r3 + 1323 0022 22E0 b .L61 + 1324 .L60: + 1325 .loc 1 635 46 is_stmt 0 discriminator 2 + 1326 0024 3B68 ldr r3, [r7] + 1327 0026 042B cmp r3, #4 + 1328 0028 09D1 bne .L62 + 1329 .loc 1 635 7 is_stmt 1 discriminator 4 + 1330 002a 7B68 ldr r3, [r7, #4] + 1331 002c 93F84530 ldrb r3, [r3, #69] + 1332 0030 DBB2 uxtb r3, r3 + 1333 .loc 1 635 46 discriminator 4 + 1334 0032 012B cmp r3, #1 + 1335 0034 14BF ite ne + 1336 0036 0123 movne r3, #1 + 1337 0038 0023 moveq r3, #0 + 1338 003a DBB2 uxtb r3, r3 + 1339 003c 15E0 b .L61 + 1340 .L62: + 1341 .loc 1 635 46 is_stmt 0 discriminator 5 + 1342 003e 3B68 ldr r3, [r7] + 1343 0040 082B cmp r3, #8 + 1344 0042 09D1 bne .L64 + 1345 .loc 1 635 7 is_stmt 1 discriminator 7 + 1346 0044 7B68 ldr r3, [r7, #4] + 1347 0046 93F84630 ldrb r3, [r3, #70] + 1348 004a DBB2 uxtb r3, r3 + 1349 .loc 1 635 46 discriminator 7 + 1350 004c 012B cmp r3, #1 + 1351 004e 14BF ite ne + 1352 0050 0123 movne r3, #1 + 1353 0052 0023 moveq r3, #0 + 1354 0054 DBB2 uxtb r3, r3 + 1355 0056 08E0 b .L61 + 1356 .L64: + 1357 .loc 1 635 7 discriminator 8 + 1358 0058 7B68 ldr r3, [r7, #4] + 1359 005a 93F84730 ldrb r3, [r3, #71] + 1360 005e DBB2 uxtb r3, r3 + 1361 .loc 1 635 46 discriminator 8 + 1362 0060 012B cmp r3, #1 + 1363 0062 14BF ite ne + 1364 0064 0123 movne r3, #1 + 1365 0066 0023 moveq r3, #0 + 1366 0068 DBB2 uxtb r3, r3 + 1367 .L61: + 1368 .loc 1 635 6 discriminator 12 + 1369 006a 002B cmp r3, #0 + 1370 006c 01D0 beq .L66 + 636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return HAL_ERROR; + 1371 .loc 1 637 12 + ARM GAS /tmp/ccxRWv8k.s page 36 + + + 1372 006e 0123 movs r3, #1 + 1373 0070 64E0 b .L67 + 1374 .L66: + 638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Set the TIM complementary channel state */ + 641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + 1375 .loc 1 641 3 + 1376 0072 3B68 ldr r3, [r7] + 1377 0074 002B cmp r3, #0 + 1378 0076 04D1 bne .L68 + 1379 .loc 1 641 3 is_stmt 0 discriminator 1 + 1380 0078 7B68 ldr r3, [r7, #4] + 1381 007a 0222 movs r2, #2 + 1382 007c 83F84420 strb r2, [r3, #68] + 1383 0080 13E0 b .L69 + 1384 .L68: + 1385 .loc 1 641 3 discriminator 2 + 1386 0082 3B68 ldr r3, [r7] + 1387 0084 042B cmp r3, #4 + 1388 0086 04D1 bne .L70 + 1389 .loc 1 641 3 discriminator 3 + 1390 0088 7B68 ldr r3, [r7, #4] + 1391 008a 0222 movs r2, #2 + 1392 008c 83F84520 strb r2, [r3, #69] + 1393 0090 0BE0 b .L69 + 1394 .L70: + 1395 .loc 1 641 3 discriminator 4 + 1396 0092 3B68 ldr r3, [r7] + 1397 0094 082B cmp r3, #8 + 1398 0096 04D1 bne .L72 + 1399 .loc 1 641 3 discriminator 6 + 1400 0098 7B68 ldr r3, [r7, #4] + 1401 009a 0222 movs r2, #2 + 1402 009c 83F84620 strb r2, [r3, #70] + 1403 00a0 03E0 b .L69 + 1404 .L72: + 1405 .loc 1 641 3 discriminator 7 + 1406 00a2 7B68 ldr r3, [r7, #4] + 1407 00a4 0222 movs r2, #2 + 1408 00a6 83F84720 strb r2, [r3, #71] + 1409 .L69: + 642:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the Capture compare channel N */ + 644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + 1410 .loc 1 644 3 is_stmt 1 + 1411 00aa 7B68 ldr r3, [r7, #4] + 1412 00ac 1B68 ldr r3, [r3] + 1413 00ae 0422 movs r2, #4 + 1414 00b0 3968 ldr r1, [r7] + 1415 00b2 1846 mov r0, r3 + 1416 00b4 FFF7FEFF bl TIM_CCxNChannelCmd + 645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the Main Output */ + 647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_MOE_ENABLE(htim); + 1417 .loc 1 647 3 + 1418 00b8 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/ccxRWv8k.s page 37 + + + 1419 00ba 1B68 ldr r3, [r3] + 1420 00bc 5A6C ldr r2, [r3, #68] + 1421 00be 7B68 ldr r3, [r7, #4] + 1422 00c0 1B68 ldr r3, [r3] + 1423 00c2 42F40042 orr r2, r2, #32768 + 1424 00c6 5A64 str r2, [r3, #68] + 648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger + 650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 1425 .loc 1 650 7 + 1426 00c8 7B68 ldr r3, [r7, #4] + 1427 00ca 1B68 ldr r3, [r3] + 1428 .loc 1 650 6 + 1429 00cc 1D4A ldr r2, .L79 + 1430 00ce 9342 cmp r3, r2 + 1431 00d0 13D0 beq .L74 + 1432 .loc 1 650 7 discriminator 1 + 1433 00d2 7B68 ldr r3, [r7, #4] + 1434 00d4 1B68 ldr r3, [r3] + 1435 00d6 B3F1804F cmp r3, #1073741824 + 1436 00da 0ED0 beq .L74 + 1437 .loc 1 650 7 is_stmt 0 discriminator 2 + 1438 00dc 7B68 ldr r3, [r7, #4] + 1439 00de 1B68 ldr r3, [r3] + 1440 00e0 194A ldr r2, .L79+4 + 1441 00e2 9342 cmp r3, r2 + 1442 00e4 09D0 beq .L74 + 1443 .loc 1 650 7 discriminator 3 + 1444 00e6 7B68 ldr r3, [r7, #4] + 1445 00e8 1B68 ldr r3, [r3] + 1446 00ea 184A ldr r2, .L79+8 + 1447 00ec 9342 cmp r3, r2 + 1448 00ee 04D0 beq .L74 + 1449 .loc 1 650 7 discriminator 4 + 1450 00f0 7B68 ldr r3, [r7, #4] + 1451 00f2 1B68 ldr r3, [r3] + 1452 00f4 164A ldr r2, .L79+12 + 1453 00f6 9342 cmp r3, r2 + 1454 00f8 15D1 bne .L75 + 1455 .L74: + 651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + 1456 .loc 1 652 19 is_stmt 1 + 1457 00fa 7B68 ldr r3, [r7, #4] + 1458 00fc 1B68 ldr r3, [r3] + 1459 .loc 1 652 29 + 1460 00fe 9A68 ldr r2, [r3, #8] + 1461 .loc 1 652 13 + 1462 0100 144B ldr r3, .L79+16 + 1463 0102 1340 ands r3, r3, r2 + 1464 0104 FB60 str r3, [r7, #12] + 653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 1465 .loc 1 653 8 + 1466 0106 FB68 ldr r3, [r7, #12] + 1467 0108 062B cmp r3, #6 + 1468 010a 15D0 beq .L78 + 1469 .loc 1 653 9 discriminator 1 + ARM GAS /tmp/ccxRWv8k.s page 38 + + + 1470 010c FB68 ldr r3, [r7, #12] + 1471 010e B3F5803F cmp r3, #65536 + 1472 0112 11D0 beq .L78 + 654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 655:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_ENABLE(htim); + 1473 .loc 1 655 7 + 1474 0114 7B68 ldr r3, [r7, #4] + 1475 0116 1B68 ldr r3, [r3] + 1476 0118 1A68 ldr r2, [r3] + 1477 011a 7B68 ldr r3, [r7, #4] + 1478 011c 1B68 ldr r3, [r3] + 1479 011e 42F00102 orr r2, r2, #1 + 1480 0122 1A60 str r2, [r3] + 653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 1481 .loc 1 653 8 + 1482 0124 08E0 b .L78 + 1483 .L75: + 656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 657:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** else + 659:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_ENABLE(htim); + 1484 .loc 1 660 5 + 1485 0126 7B68 ldr r3, [r7, #4] + 1486 0128 1B68 ldr r3, [r3] + 1487 012a 1A68 ldr r2, [r3] + 1488 012c 7B68 ldr r3, [r7, #4] + 1489 012e 1B68 ldr r3, [r3] + 1490 0130 42F00102 orr r2, r2, #1 + 1491 0134 1A60 str r2, [r3] + 1492 0136 00E0 b .L77 + 1493 .L78: + 653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 1494 .loc 1 653 8 + 1495 0138 00BF nop + 1496 .L77: + 661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Return function status */ + 664:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return HAL_OK; + 1497 .loc 1 664 10 + 1498 013a 0023 movs r3, #0 + 1499 .L67: + 665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 1500 .loc 1 665 1 + 1501 013c 1846 mov r0, r3 + 1502 013e 1037 adds r7, r7, #16 + 1503 .cfi_def_cfa_offset 8 + 1504 0140 BD46 mov sp, r7 + 1505 .cfi_def_cfa_register 13 + 1506 @ sp needed + 1507 0142 80BD pop {r7, pc} + 1508 .L80: + 1509 .align 2 + 1510 .L79: + 1511 0144 002C0140 .word 1073818624 + 1512 0148 00040040 .word 1073742848 + ARM GAS /tmp/ccxRWv8k.s page 39 + + + 1513 014c 00080040 .word 1073743872 + 1514 0150 00400140 .word 1073823744 + 1515 0154 07000100 .word 65543 + 1516 .cfi_endproc + 1517 .LFE140: + 1519 .section .text.HAL_TIMEx_OCN_Stop,"ax",%progbits + 1520 .align 1 + 1521 .global HAL_TIMEx_OCN_Stop + 1522 .syntax unified + 1523 .thumb + 1524 .thumb_func + 1526 HAL_TIMEx_OCN_Stop: + 1527 .LFB141: + 666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** + 668:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief Stops the TIM Output Compare signal generation on the complementary + 669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * output. + 670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param htim TIM handle + 671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param Channel TIM Channel to be disabled + 672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * This parameter can be one of the following values: + 673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected + 674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected + 675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected + 676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @retval HAL status + 677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ + 678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) + 679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 1528 .loc 1 679 1 + 1529 .cfi_startproc + 1530 @ args = 0, pretend = 0, frame = 8 + 1531 @ frame_needed = 1, uses_anonymous_args = 0 + 1532 0000 80B5 push {r7, lr} + 1533 .cfi_def_cfa_offset 8 + 1534 .cfi_offset 7, -8 + 1535 .cfi_offset 14, -4 + 1536 0002 82B0 sub sp, sp, #8 + 1537 .cfi_def_cfa_offset 16 + 1538 0004 00AF add r7, sp, #0 + 1539 .cfi_def_cfa_register 7 + 1540 0006 7860 str r0, [r7, #4] + 1541 0008 3960 str r1, [r7] + 680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Check the parameters */ + 681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + 682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable the Capture compare channel N */ + 684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + 1542 .loc 1 684 3 + 1543 000a 7B68 ldr r3, [r7, #4] + 1544 000c 1B68 ldr r3, [r3] + 1545 000e 0022 movs r2, #0 + 1546 0010 3968 ldr r1, [r7] + 1547 0012 1846 mov r0, r3 + 1548 0014 FFF7FEFF bl TIM_CCxNChannelCmd + 685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable the Main Output */ + 687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_MOE_DISABLE(htim); + 1549 .loc 1 687 3 + ARM GAS /tmp/ccxRWv8k.s page 40 + + + 1550 0018 7B68 ldr r3, [r7, #4] + 1551 001a 1B68 ldr r3, [r3] + 1552 001c 1A6A ldr r2, [r3, #32] + 1553 001e 41F21113 movw r3, #4369 + 1554 0022 1340 ands r3, r3, r2 + 1555 0024 002B cmp r3, #0 + 1556 0026 0FD1 bne .L82 + 1557 .loc 1 687 3 is_stmt 0 discriminator 1 + 1558 0028 7B68 ldr r3, [r7, #4] + 1559 002a 1B68 ldr r3, [r3] + 1560 002c 1A6A ldr r2, [r3, #32] + 1561 002e 40F24443 movw r3, #1092 + 1562 0032 1340 ands r3, r3, r2 + 1563 0034 002B cmp r3, #0 + 1564 0036 07D1 bne .L82 + 1565 .loc 1 687 3 discriminator 2 + 1566 0038 7B68 ldr r3, [r7, #4] + 1567 003a 1B68 ldr r3, [r3] + 1568 003c 5A6C ldr r2, [r3, #68] + 1569 003e 7B68 ldr r3, [r7, #4] + 1570 0040 1B68 ldr r3, [r3] + 1571 0042 22F40042 bic r2, r2, #32768 + 1572 0046 5A64 str r2, [r3, #68] + 1573 .L82: + 688:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable the Peripheral */ + 690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_DISABLE(htim); + 1574 .loc 1 690 3 is_stmt 1 + 1575 0048 7B68 ldr r3, [r7, #4] + 1576 004a 1B68 ldr r3, [r3] + 1577 004c 1A6A ldr r2, [r3, #32] + 1578 004e 41F21113 movw r3, #4369 + 1579 0052 1340 ands r3, r3, r2 + 1580 0054 002B cmp r3, #0 + 1581 0056 0FD1 bne .L83 + 1582 .loc 1 690 3 is_stmt 0 discriminator 1 + 1583 0058 7B68 ldr r3, [r7, #4] + 1584 005a 1B68 ldr r3, [r3] + 1585 005c 1A6A ldr r2, [r3, #32] + 1586 005e 40F24443 movw r3, #1092 + 1587 0062 1340 ands r3, r3, r2 + 1588 0064 002B cmp r3, #0 + 1589 0066 07D1 bne .L83 + 1590 .loc 1 690 3 discriminator 2 + 1591 0068 7B68 ldr r3, [r7, #4] + 1592 006a 1B68 ldr r3, [r3] + 1593 006c 1A68 ldr r2, [r3] + 1594 006e 7B68 ldr r3, [r7, #4] + 1595 0070 1B68 ldr r3, [r3] + 1596 0072 22F00102 bic r2, r2, #1 + 1597 0076 1A60 str r2, [r3] + 1598 .L83: + 691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Set the TIM complementary channel state */ + 693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 1599 .loc 1 693 3 is_stmt 1 + 1600 0078 3B68 ldr r3, [r7] + ARM GAS /tmp/ccxRWv8k.s page 41 + + + 1601 007a 002B cmp r3, #0 + 1602 007c 04D1 bne .L84 + 1603 .loc 1 693 3 is_stmt 0 discriminator 1 + 1604 007e 7B68 ldr r3, [r7, #4] + 1605 0080 0122 movs r2, #1 + 1606 0082 83F84420 strb r2, [r3, #68] + 1607 0086 13E0 b .L85 + 1608 .L84: + 1609 .loc 1 693 3 discriminator 2 + 1610 0088 3B68 ldr r3, [r7] + 1611 008a 042B cmp r3, #4 + 1612 008c 04D1 bne .L86 + 1613 .loc 1 693 3 discriminator 3 + 1614 008e 7B68 ldr r3, [r7, #4] + 1615 0090 0122 movs r2, #1 + 1616 0092 83F84520 strb r2, [r3, #69] + 1617 0096 0BE0 b .L85 + 1618 .L86: + 1619 .loc 1 693 3 discriminator 4 + 1620 0098 3B68 ldr r3, [r7] + 1621 009a 082B cmp r3, #8 + 1622 009c 04D1 bne .L88 + 1623 .loc 1 693 3 discriminator 6 + 1624 009e 7B68 ldr r3, [r7, #4] + 1625 00a0 0122 movs r2, #1 + 1626 00a2 83F84620 strb r2, [r3, #70] + 1627 00a6 03E0 b .L85 + 1628 .L88: + 1629 .loc 1 693 3 discriminator 7 + 1630 00a8 7B68 ldr r3, [r7, #4] + 1631 00aa 0122 movs r2, #1 + 1632 00ac 83F84720 strb r2, [r3, #71] + 1633 .L85: + 694:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Return function status */ + 696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return HAL_OK; + 1634 .loc 1 696 10 is_stmt 1 + 1635 00b0 0023 movs r3, #0 + 697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 1636 .loc 1 697 1 + 1637 00b2 1846 mov r0, r3 + 1638 00b4 0837 adds r7, r7, #8 + 1639 .cfi_def_cfa_offset 8 + 1640 00b6 BD46 mov sp, r7 + 1641 .cfi_def_cfa_register 13 + 1642 @ sp needed + 1643 00b8 80BD pop {r7, pc} + 1644 .cfi_endproc + 1645 .LFE141: + 1647 .section .text.HAL_TIMEx_OCN_Start_IT,"ax",%progbits + 1648 .align 1 + 1649 .global HAL_TIMEx_OCN_Start_IT + 1650 .syntax unified + 1651 .thumb + 1652 .thumb_func + 1654 HAL_TIMEx_OCN_Start_IT: + 1655 .LFB142: + ARM GAS /tmp/ccxRWv8k.s page 42 + + + 698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** + 700:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief Starts the TIM Output Compare signal generation in interrupt mode + 701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * on the complementary output. + 702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param htim TIM OC handle + 703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param Channel TIM Channel to be enabled + 704:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * This parameter can be one of the following values: + 705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected + 706:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected + 707:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected + 708:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @retval HAL status + 709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ + 710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) + 711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 1656 .loc 1 711 1 + 1657 .cfi_startproc + 1658 @ args = 0, pretend = 0, frame = 16 + 1659 @ frame_needed = 1, uses_anonymous_args = 0 + 1660 0000 80B5 push {r7, lr} + 1661 .cfi_def_cfa_offset 8 + 1662 .cfi_offset 7, -8 + 1663 .cfi_offset 14, -4 + 1664 0002 84B0 sub sp, sp, #16 + 1665 .cfi_def_cfa_offset 24 + 1666 0004 00AF add r7, sp, #0 + 1667 .cfi_def_cfa_register 7 + 1668 0006 7860 str r0, [r7, #4] + 1669 0008 3960 str r1, [r7] + 712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 1670 .loc 1 712 21 + 1671 000a 0023 movs r3, #0 + 1672 000c FB73 strb r3, [r7, #15] + 713:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** uint32_t tmpsmcr; + 714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Check the parameters */ + 716:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + 717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 718:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Check the TIM complementary channel state */ + 719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + 1673 .loc 1 719 46 + 1674 000e 3B68 ldr r3, [r7] + 1675 0010 002B cmp r3, #0 + 1676 0012 09D1 bne .L92 + 1677 .loc 1 719 7 discriminator 1 + 1678 0014 7B68 ldr r3, [r7, #4] + 1679 0016 93F84430 ldrb r3, [r3, #68] + 1680 001a DBB2 uxtb r3, r3 + 1681 .loc 1 719 46 discriminator 1 + 1682 001c 012B cmp r3, #1 + 1683 001e 14BF ite ne + 1684 0020 0123 movne r3, #1 + 1685 0022 0023 moveq r3, #0 + 1686 0024 DBB2 uxtb r3, r3 + 1687 0026 22E0 b .L93 + 1688 .L92: + 1689 .loc 1 719 46 is_stmt 0 discriminator 2 + 1690 0028 3B68 ldr r3, [r7] + ARM GAS /tmp/ccxRWv8k.s page 43 + + + 1691 002a 042B cmp r3, #4 + 1692 002c 09D1 bne .L94 + 1693 .loc 1 719 7 is_stmt 1 discriminator 4 + 1694 002e 7B68 ldr r3, [r7, #4] + 1695 0030 93F84530 ldrb r3, [r3, #69] + 1696 0034 DBB2 uxtb r3, r3 + 1697 .loc 1 719 46 discriminator 4 + 1698 0036 012B cmp r3, #1 + 1699 0038 14BF ite ne + 1700 003a 0123 movne r3, #1 + 1701 003c 0023 moveq r3, #0 + 1702 003e DBB2 uxtb r3, r3 + 1703 0040 15E0 b .L93 + 1704 .L94: + 1705 .loc 1 719 46 is_stmt 0 discriminator 5 + 1706 0042 3B68 ldr r3, [r7] + 1707 0044 082B cmp r3, #8 + 1708 0046 09D1 bne .L96 + 1709 .loc 1 719 7 is_stmt 1 discriminator 7 + 1710 0048 7B68 ldr r3, [r7, #4] + 1711 004a 93F84630 ldrb r3, [r3, #70] + 1712 004e DBB2 uxtb r3, r3 + 1713 .loc 1 719 46 discriminator 7 + 1714 0050 012B cmp r3, #1 + 1715 0052 14BF ite ne + 1716 0054 0123 movne r3, #1 + 1717 0056 0023 moveq r3, #0 + 1718 0058 DBB2 uxtb r3, r3 + 1719 005a 08E0 b .L93 + 1720 .L96: + 1721 .loc 1 719 7 discriminator 8 + 1722 005c 7B68 ldr r3, [r7, #4] + 1723 005e 93F84730 ldrb r3, [r3, #71] + 1724 0062 DBB2 uxtb r3, r3 + 1725 .loc 1 719 46 discriminator 8 + 1726 0064 012B cmp r3, #1 + 1727 0066 14BF ite ne + 1728 0068 0123 movne r3, #1 + 1729 006a 0023 moveq r3, #0 + 1730 006c DBB2 uxtb r3, r3 + 1731 .L93: + 1732 .loc 1 719 6 discriminator 12 + 1733 006e 002B cmp r3, #0 + 1734 0070 01D0 beq .L98 + 720:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return HAL_ERROR; + 1735 .loc 1 721 12 + 1736 0072 0123 movs r3, #1 + 1737 0074 9AE0 b .L99 + 1738 .L98: + 722:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 723:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 724:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Set the TIM complementary channel state */ + 725:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + 1739 .loc 1 725 3 + 1740 0076 3B68 ldr r3, [r7] + 1741 0078 002B cmp r3, #0 + ARM GAS /tmp/ccxRWv8k.s page 44 + + + 1742 007a 04D1 bne .L100 + 1743 .loc 1 725 3 is_stmt 0 discriminator 1 + 1744 007c 7B68 ldr r3, [r7, #4] + 1745 007e 0222 movs r2, #2 + 1746 0080 83F84420 strb r2, [r3, #68] + 1747 0084 13E0 b .L101 + 1748 .L100: + 1749 .loc 1 725 3 discriminator 2 + 1750 0086 3B68 ldr r3, [r7] + 1751 0088 042B cmp r3, #4 + 1752 008a 04D1 bne .L102 + 1753 .loc 1 725 3 discriminator 3 + 1754 008c 7B68 ldr r3, [r7, #4] + 1755 008e 0222 movs r2, #2 + 1756 0090 83F84520 strb r2, [r3, #69] + 1757 0094 0BE0 b .L101 + 1758 .L102: + 1759 .loc 1 725 3 discriminator 4 + 1760 0096 3B68 ldr r3, [r7] + 1761 0098 082B cmp r3, #8 + 1762 009a 04D1 bne .L104 + 1763 .loc 1 725 3 discriminator 6 + 1764 009c 7B68 ldr r3, [r7, #4] + 1765 009e 0222 movs r2, #2 + 1766 00a0 83F84620 strb r2, [r3, #70] + 1767 00a4 03E0 b .L101 + 1768 .L104: + 1769 .loc 1 725 3 discriminator 7 + 1770 00a6 7B68 ldr r3, [r7, #4] + 1771 00a8 0222 movs r2, #2 + 1772 00aa 83F84720 strb r2, [r3, #71] + 1773 .L101: + 726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 727:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** switch (Channel) + 1774 .loc 1 727 3 is_stmt 1 + 1775 00ae 3B68 ldr r3, [r7] + 1776 00b0 082B cmp r3, #8 + 1777 00b2 1BD0 beq .L106 + 1778 00b4 3B68 ldr r3, [r7] + 1779 00b6 082B cmp r3, #8 + 1780 00b8 21D8 bhi .L107 + 1781 00ba 3B68 ldr r3, [r7] + 1782 00bc 002B cmp r3, #0 + 1783 00be 03D0 beq .L108 + 1784 00c0 3B68 ldr r3, [r7] + 1785 00c2 042B cmp r3, #4 + 1786 00c4 09D0 beq .L109 + 1787 00c6 1AE0 b .L107 + 1788 .L108: + 728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** case TIM_CHANNEL_1: + 730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the TIM Output Compare interrupt */ + 732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + 1789 .loc 1 732 7 + 1790 00c8 7B68 ldr r3, [r7, #4] + 1791 00ca 1B68 ldr r3, [r3] + ARM GAS /tmp/ccxRWv8k.s page 45 + + + 1792 00cc DA68 ldr r2, [r3, #12] + 1793 00ce 7B68 ldr r3, [r7, #4] + 1794 00d0 1B68 ldr r3, [r3] + 1795 00d2 42F00202 orr r2, r2, #2 + 1796 00d6 DA60 str r2, [r3, #12] + 733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** break; + 1797 .loc 1 733 7 + 1798 00d8 14E0 b .L110 + 1799 .L109: + 734:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** case TIM_CHANNEL_2: + 737:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the TIM Output Compare interrupt */ + 739:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + 1800 .loc 1 739 7 + 1801 00da 7B68 ldr r3, [r7, #4] + 1802 00dc 1B68 ldr r3, [r3] + 1803 00de DA68 ldr r2, [r3, #12] + 1804 00e0 7B68 ldr r3, [r7, #4] + 1805 00e2 1B68 ldr r3, [r3] + 1806 00e4 42F00402 orr r2, r2, #4 + 1807 00e8 DA60 str r2, [r3, #12] + 740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** break; + 1808 .loc 1 740 7 + 1809 00ea 0BE0 b .L110 + 1810 .L106: + 741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 743:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** case TIM_CHANNEL_3: + 744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 745:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the TIM Output Compare interrupt */ + 746:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + 1811 .loc 1 746 7 + 1812 00ec 7B68 ldr r3, [r7, #4] + 1813 00ee 1B68 ldr r3, [r3] + 1814 00f0 DA68 ldr r2, [r3, #12] + 1815 00f2 7B68 ldr r3, [r7, #4] + 1816 00f4 1B68 ldr r3, [r3] + 1817 00f6 42F00802 orr r2, r2, #8 + 1818 00fa DA60 str r2, [r3, #12] + 747:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** break; + 1819 .loc 1 747 7 + 1820 00fc 02E0 b .L110 + 1821 .L107: + 748:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** default: + 752:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** status = HAL_ERROR; + 1822 .loc 1 752 14 + 1823 00fe 0123 movs r3, #1 + 1824 0100 FB73 strb r3, [r7, #15] + 753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** break; + 1825 .loc 1 753 7 + 1826 0102 00BF nop + 1827 .L110: + ARM GAS /tmp/ccxRWv8k.s page 46 + + + 754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 755:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (status == HAL_OK) + 1828 .loc 1 756 6 + 1829 0104 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 1830 0106 002B cmp r3, #0 + 1831 0108 4FD1 bne .L111 + 757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 758:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the TIM Break interrupt */ + 759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + 1832 .loc 1 759 5 + 1833 010a 7B68 ldr r3, [r7, #4] + 1834 010c 1B68 ldr r3, [r3] + 1835 010e DA68 ldr r2, [r3, #12] + 1836 0110 7B68 ldr r3, [r7, #4] + 1837 0112 1B68 ldr r3, [r3] + 1838 0114 42F08002 orr r2, r2, #128 + 1839 0118 DA60 str r2, [r3, #12] + 760:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 761:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the Capture compare channel N */ + 762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + 1840 .loc 1 762 5 + 1841 011a 7B68 ldr r3, [r7, #4] + 1842 011c 1B68 ldr r3, [r3] + 1843 011e 0422 movs r2, #4 + 1844 0120 3968 ldr r1, [r7] + 1845 0122 1846 mov r0, r3 + 1846 0124 FFF7FEFF bl TIM_CCxNChannelCmd + 763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 764:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the Main Output */ + 765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_MOE_ENABLE(htim); + 1847 .loc 1 765 5 + 1848 0128 7B68 ldr r3, [r7, #4] + 1849 012a 1B68 ldr r3, [r3] + 1850 012c 5A6C ldr r2, [r3, #68] + 1851 012e 7B68 ldr r3, [r7, #4] + 1852 0130 1B68 ldr r3, [r3] + 1853 0132 42F40042 orr r2, r2, #32768 + 1854 0136 5A64 str r2, [r3, #68] + 766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 767:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigge + 768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 1855 .loc 1 768 9 + 1856 0138 7B68 ldr r3, [r7, #4] + 1857 013a 1B68 ldr r3, [r3] + 1858 .loc 1 768 8 + 1859 013c 1D4A ldr r2, .L116 + 1860 013e 9342 cmp r3, r2 + 1861 0140 13D0 beq .L112 + 1862 .loc 1 768 9 discriminator 1 + 1863 0142 7B68 ldr r3, [r7, #4] + 1864 0144 1B68 ldr r3, [r3] + 1865 0146 B3F1804F cmp r3, #1073741824 + 1866 014a 0ED0 beq .L112 + 1867 .loc 1 768 9 is_stmt 0 discriminator 2 + 1868 014c 7B68 ldr r3, [r7, #4] + 1869 014e 1B68 ldr r3, [r3] + ARM GAS /tmp/ccxRWv8k.s page 47 + + + 1870 0150 194A ldr r2, .L116+4 + 1871 0152 9342 cmp r3, r2 + 1872 0154 09D0 beq .L112 + 1873 .loc 1 768 9 discriminator 3 + 1874 0156 7B68 ldr r3, [r7, #4] + 1875 0158 1B68 ldr r3, [r3] + 1876 015a 184A ldr r2, .L116+8 + 1877 015c 9342 cmp r3, r2 + 1878 015e 04D0 beq .L112 + 1879 .loc 1 768 9 discriminator 4 + 1880 0160 7B68 ldr r3, [r7, #4] + 1881 0162 1B68 ldr r3, [r3] + 1882 0164 164A ldr r2, .L116+12 + 1883 0166 9342 cmp r3, r2 + 1884 0168 15D1 bne .L113 + 1885 .L112: + 769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + 1886 .loc 1 770 21 is_stmt 1 + 1887 016a 7B68 ldr r3, [r7, #4] + 1888 016c 1B68 ldr r3, [r3] + 1889 .loc 1 770 31 + 1890 016e 9A68 ldr r2, [r3, #8] + 1891 .loc 1 770 15 + 1892 0170 144B ldr r3, .L116+16 + 1893 0172 1340 ands r3, r3, r2 + 1894 0174 BB60 str r3, [r7, #8] + 771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 1895 .loc 1 771 10 + 1896 0176 BB68 ldr r3, [r7, #8] + 1897 0178 062B cmp r3, #6 + 1898 017a 15D0 beq .L115 + 1899 .loc 1 771 11 discriminator 1 + 1900 017c BB68 ldr r3, [r7, #8] + 1901 017e B3F5803F cmp r3, #65536 + 1902 0182 11D0 beq .L115 + 772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_ENABLE(htim); + 1903 .loc 1 773 9 + 1904 0184 7B68 ldr r3, [r7, #4] + 1905 0186 1B68 ldr r3, [r3] + 1906 0188 1A68 ldr r2, [r3] + 1907 018a 7B68 ldr r3, [r7, #4] + 1908 018c 1B68 ldr r3, [r3] + 1909 018e 42F00102 orr r2, r2, #1 + 1910 0192 1A60 str r2, [r3] + 771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 1911 .loc 1 771 10 + 1912 0194 08E0 b .L115 + 1913 .L113: + 774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** else + 777:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_ENABLE(htim); + 1914 .loc 1 778 7 + 1915 0196 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/ccxRWv8k.s page 48 + + + 1916 0198 1B68 ldr r3, [r3] + 1917 019a 1A68 ldr r2, [r3] + 1918 019c 7B68 ldr r3, [r7, #4] + 1919 019e 1B68 ldr r3, [r3] + 1920 01a0 42F00102 orr r2, r2, #1 + 1921 01a4 1A60 str r2, [r3] + 1922 01a6 00E0 b .L111 + 1923 .L115: + 771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 1924 .loc 1 771 10 + 1925 01a8 00BF nop + 1926 .L111: + 779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 780:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 782:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Return function status */ + 783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return status; + 1927 .loc 1 783 10 + 1928 01aa FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 1929 .L99: + 784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 1930 .loc 1 784 1 + 1931 01ac 1846 mov r0, r3 + 1932 01ae 1037 adds r7, r7, #16 + 1933 .cfi_def_cfa_offset 8 + 1934 01b0 BD46 mov sp, r7 + 1935 .cfi_def_cfa_register 13 + 1936 @ sp needed + 1937 01b2 80BD pop {r7, pc} + 1938 .L117: + 1939 .align 2 + 1940 .L116: + 1941 01b4 002C0140 .word 1073818624 + 1942 01b8 00040040 .word 1073742848 + 1943 01bc 00080040 .word 1073743872 + 1944 01c0 00400140 .word 1073823744 + 1945 01c4 07000100 .word 65543 + 1946 .cfi_endproc + 1947 .LFE142: + 1949 .section .text.HAL_TIMEx_OCN_Stop_IT,"ax",%progbits + 1950 .align 1 + 1951 .global HAL_TIMEx_OCN_Stop_IT + 1952 .syntax unified + 1953 .thumb + 1954 .thumb_func + 1956 HAL_TIMEx_OCN_Stop_IT: + 1957 .LFB143: + 785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** + 787:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief Stops the TIM Output Compare signal generation in interrupt mode + 788:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * on the complementary output. + 789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param htim TIM Output Compare handle + 790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param Channel TIM Channel to be disabled + 791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * This parameter can be one of the following values: + 792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected + 793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected + 794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected + ARM GAS /tmp/ccxRWv8k.s page 49 + + + 795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @retval HAL status + 796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ + 797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) + 798:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 1958 .loc 1 798 1 + 1959 .cfi_startproc + 1960 @ args = 0, pretend = 0, frame = 16 + 1961 @ frame_needed = 1, uses_anonymous_args = 0 + 1962 0000 80B5 push {r7, lr} + 1963 .cfi_def_cfa_offset 8 + 1964 .cfi_offset 7, -8 + 1965 .cfi_offset 14, -4 + 1966 0002 84B0 sub sp, sp, #16 + 1967 .cfi_def_cfa_offset 24 + 1968 0004 00AF add r7, sp, #0 + 1969 .cfi_def_cfa_register 7 + 1970 0006 7860 str r0, [r7, #4] + 1971 0008 3960 str r1, [r7] + 799:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 1972 .loc 1 799 21 + 1973 000a 0023 movs r3, #0 + 1974 000c FB73 strb r3, [r7, #15] + 800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** uint32_t tmpccer; + 801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Check the parameters */ + 803:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + 804:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** switch (Channel) + 1975 .loc 1 805 3 + 1976 000e 3B68 ldr r3, [r7] + 1977 0010 082B cmp r3, #8 + 1978 0012 1BD0 beq .L119 + 1979 0014 3B68 ldr r3, [r7] + 1980 0016 082B cmp r3, #8 + 1981 0018 21D8 bhi .L120 + 1982 001a 3B68 ldr r3, [r7] + 1983 001c 002B cmp r3, #0 + 1984 001e 03D0 beq .L121 + 1985 0020 3B68 ldr r3, [r7] + 1986 0022 042B cmp r3, #4 + 1987 0024 09D0 beq .L122 + 1988 0026 1AE0 b .L120 + 1989 .L121: + 806:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 807:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** case TIM_CHANNEL_1: + 808:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable the TIM Output Compare interrupt */ + 810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + 1990 .loc 1 810 7 + 1991 0028 7B68 ldr r3, [r7, #4] + 1992 002a 1B68 ldr r3, [r3] + 1993 002c DA68 ldr r2, [r3, #12] + 1994 002e 7B68 ldr r3, [r7, #4] + 1995 0030 1B68 ldr r3, [r3] + 1996 0032 22F00202 bic r2, r2, #2 + 1997 0036 DA60 str r2, [r3, #12] + 811:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** break; + ARM GAS /tmp/ccxRWv8k.s page 50 + + + 1998 .loc 1 811 7 + 1999 0038 14E0 b .L123 + 2000 .L122: + 812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 814:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** case TIM_CHANNEL_2: + 815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable the TIM Output Compare interrupt */ + 817:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + 2001 .loc 1 817 7 + 2002 003a 7B68 ldr r3, [r7, #4] + 2003 003c 1B68 ldr r3, [r3] + 2004 003e DA68 ldr r2, [r3, #12] + 2005 0040 7B68 ldr r3, [r7, #4] + 2006 0042 1B68 ldr r3, [r3] + 2007 0044 22F00402 bic r2, r2, #4 + 2008 0048 DA60 str r2, [r3, #12] + 818:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** break; + 2009 .loc 1 818 7 + 2010 004a 0BE0 b .L123 + 2011 .L119: + 819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 820:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 821:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** case TIM_CHANNEL_3: + 822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable the TIM Output Compare interrupt */ + 824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + 2012 .loc 1 824 7 + 2013 004c 7B68 ldr r3, [r7, #4] + 2014 004e 1B68 ldr r3, [r3] + 2015 0050 DA68 ldr r2, [r3, #12] + 2016 0052 7B68 ldr r3, [r7, #4] + 2017 0054 1B68 ldr r3, [r3] + 2018 0056 22F00802 bic r2, r2, #8 + 2019 005a DA60 str r2, [r3, #12] + 825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** break; + 2020 .loc 1 825 7 + 2021 005c 02E0 b .L123 + 2022 .L120: + 826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 827:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 828:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** default: + 829:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** status = HAL_ERROR; + 2023 .loc 1 829 14 + 2024 005e 0123 movs r3, #1 + 2025 0060 FB73 strb r3, [r7, #15] + 830:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** break; + 2026 .loc 1 830 7 + 2027 0062 00BF nop + 2028 .L123: + 831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 832:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (status == HAL_OK) + 2029 .loc 1 833 6 + 2030 0064 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 2031 0066 002B cmp r3, #0 + 2032 0068 64D1 bne .L124 + ARM GAS /tmp/ccxRWv8k.s page 51 + + + 834:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 835:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable the Capture compare channel N */ + 836:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + 2033 .loc 1 836 5 + 2034 006a 7B68 ldr r3, [r7, #4] + 2035 006c 1B68 ldr r3, [r3] + 2036 006e 0022 movs r2, #0 + 2037 0070 3968 ldr r1, [r7] + 2038 0072 1846 mov r0, r3 + 2039 0074 FFF7FEFF bl TIM_CCxNChannelCmd + 837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable the TIM Break interrupt (only if no more channel is active) */ + 839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** tmpccer = htim->Instance->CCER; + 2040 .loc 1 839 19 + 2041 0078 7B68 ldr r3, [r7, #4] + 2042 007a 1B68 ldr r3, [r3] + 2043 .loc 1 839 13 + 2044 007c 1B6A ldr r3, [r3, #32] + 2045 007e BB60 str r3, [r7, #8] + 840:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + 2046 .loc 1 840 18 + 2047 0080 BA68 ldr r2, [r7, #8] + 2048 0082 40F24443 movw r3, #1092 + 2049 0086 1340 ands r3, r3, r2 + 2050 .loc 1 840 8 + 2051 0088 002B cmp r3, #0 + 2052 008a 07D1 bne .L125 + 841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 842:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + 2053 .loc 1 842 7 + 2054 008c 7B68 ldr r3, [r7, #4] + 2055 008e 1B68 ldr r3, [r3] + 2056 0090 DA68 ldr r2, [r3, #12] + 2057 0092 7B68 ldr r3, [r7, #4] + 2058 0094 1B68 ldr r3, [r3] + 2059 0096 22F08002 bic r2, r2, #128 + 2060 009a DA60 str r2, [r3, #12] + 2061 .L125: + 843:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 844:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable the Main Output */ + 846:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_MOE_DISABLE(htim); + 2062 .loc 1 846 5 + 2063 009c 7B68 ldr r3, [r7, #4] + 2064 009e 1B68 ldr r3, [r3] + 2065 00a0 1A6A ldr r2, [r3, #32] + 2066 00a2 41F21113 movw r3, #4369 + 2067 00a6 1340 ands r3, r3, r2 + 2068 00a8 002B cmp r3, #0 + 2069 00aa 0FD1 bne .L126 + 2070 .loc 1 846 5 is_stmt 0 discriminator 1 + 2071 00ac 7B68 ldr r3, [r7, #4] + 2072 00ae 1B68 ldr r3, [r3] + 2073 00b0 1A6A ldr r2, [r3, #32] + 2074 00b2 40F24443 movw r3, #1092 + 2075 00b6 1340 ands r3, r3, r2 + 2076 00b8 002B cmp r3, #0 + ARM GAS /tmp/ccxRWv8k.s page 52 + + + 2077 00ba 07D1 bne .L126 + 2078 .loc 1 846 5 discriminator 2 + 2079 00bc 7B68 ldr r3, [r7, #4] + 2080 00be 1B68 ldr r3, [r3] + 2081 00c0 5A6C ldr r2, [r3, #68] + 2082 00c2 7B68 ldr r3, [r7, #4] + 2083 00c4 1B68 ldr r3, [r3] + 2084 00c6 22F40042 bic r2, r2, #32768 + 2085 00ca 5A64 str r2, [r3, #68] + 2086 .L126: + 847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable the Peripheral */ + 849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_DISABLE(htim); + 2087 .loc 1 849 5 is_stmt 1 + 2088 00cc 7B68 ldr r3, [r7, #4] + 2089 00ce 1B68 ldr r3, [r3] + 2090 00d0 1A6A ldr r2, [r3, #32] + 2091 00d2 41F21113 movw r3, #4369 + 2092 00d6 1340 ands r3, r3, r2 + 2093 00d8 002B cmp r3, #0 + 2094 00da 0FD1 bne .L127 + 2095 .loc 1 849 5 is_stmt 0 discriminator 1 + 2096 00dc 7B68 ldr r3, [r7, #4] + 2097 00de 1B68 ldr r3, [r3] + 2098 00e0 1A6A ldr r2, [r3, #32] + 2099 00e2 40F24443 movw r3, #1092 + 2100 00e6 1340 ands r3, r3, r2 + 2101 00e8 002B cmp r3, #0 + 2102 00ea 07D1 bne .L127 + 2103 .loc 1 849 5 discriminator 2 + 2104 00ec 7B68 ldr r3, [r7, #4] + 2105 00ee 1B68 ldr r3, [r3] + 2106 00f0 1A68 ldr r2, [r3] + 2107 00f2 7B68 ldr r3, [r7, #4] + 2108 00f4 1B68 ldr r3, [r3] + 2109 00f6 22F00102 bic r2, r2, #1 + 2110 00fa 1A60 str r2, [r3] + 2111 .L127: + 850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 851:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Set the TIM complementary channel state */ + 852:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 2112 .loc 1 852 5 is_stmt 1 + 2113 00fc 3B68 ldr r3, [r7] + 2114 00fe 002B cmp r3, #0 + 2115 0100 04D1 bne .L128 + 2116 .loc 1 852 5 is_stmt 0 discriminator 1 + 2117 0102 7B68 ldr r3, [r7, #4] + 2118 0104 0122 movs r2, #1 + 2119 0106 83F84420 strb r2, [r3, #68] + 2120 010a 13E0 b .L124 + 2121 .L128: + 2122 .loc 1 852 5 discriminator 2 + 2123 010c 3B68 ldr r3, [r7] + 2124 010e 042B cmp r3, #4 + 2125 0110 04D1 bne .L129 + 2126 .loc 1 852 5 discriminator 3 + 2127 0112 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/ccxRWv8k.s page 53 + + + 2128 0114 0122 movs r2, #1 + 2129 0116 83F84520 strb r2, [r3, #69] + 2130 011a 0BE0 b .L124 + 2131 .L129: + 2132 .loc 1 852 5 discriminator 4 + 2133 011c 3B68 ldr r3, [r7] + 2134 011e 082B cmp r3, #8 + 2135 0120 04D1 bne .L131 + 2136 .loc 1 852 5 discriminator 6 + 2137 0122 7B68 ldr r3, [r7, #4] + 2138 0124 0122 movs r2, #1 + 2139 0126 83F84620 strb r2, [r3, #70] + 2140 012a 03E0 b .L124 + 2141 .L131: + 2142 .loc 1 852 5 discriminator 7 + 2143 012c 7B68 ldr r3, [r7, #4] + 2144 012e 0122 movs r2, #1 + 2145 0130 83F84720 strb r2, [r3, #71] + 2146 .L124: + 853:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 855:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Return function status */ + 856:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return status; + 2147 .loc 1 856 10 is_stmt 1 + 2148 0134 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 857:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 2149 .loc 1 857 1 + 2150 0136 1846 mov r0, r3 + 2151 0138 1037 adds r7, r7, #16 + 2152 .cfi_def_cfa_offset 8 + 2153 013a BD46 mov sp, r7 + 2154 .cfi_def_cfa_register 13 + 2155 @ sp needed + 2156 013c 80BD pop {r7, pc} + 2157 .cfi_endproc + 2158 .LFE143: + 2160 .section .text.HAL_TIMEx_OCN_Start_DMA,"ax",%progbits + 2161 .align 1 + 2162 .global HAL_TIMEx_OCN_Start_DMA + 2163 .syntax unified + 2164 .thumb + 2165 .thumb_func + 2167 HAL_TIMEx_OCN_Start_DMA: + 2168 .LFB144: + 858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 859:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** + 860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief Starts the TIM Output Compare signal generation in DMA mode + 861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * on the complementary output. + 862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param htim TIM Output Compare handle + 863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param Channel TIM Channel to be enabled + 864:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * This parameter can be one of the following values: + 865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected + 866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected + 867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected + 868:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param pData The source Buffer address. + 869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param Length The length of data to be transferred from memory to TIM peripheral + 870:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @retval HAL status + ARM GAS /tmp/ccxRWv8k.s page 54 + + + 871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ + 872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t + 873:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** uint16_t Length) + 874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 2169 .loc 1 874 1 + 2170 .cfi_startproc + 2171 @ args = 0, pretend = 0, frame = 24 + 2172 @ frame_needed = 1, uses_anonymous_args = 0 + 2173 0000 80B5 push {r7, lr} + 2174 .cfi_def_cfa_offset 8 + 2175 .cfi_offset 7, -8 + 2176 .cfi_offset 14, -4 + 2177 0002 86B0 sub sp, sp, #24 + 2178 .cfi_def_cfa_offset 32 + 2179 0004 00AF add r7, sp, #0 + 2180 .cfi_def_cfa_register 7 + 2181 0006 F860 str r0, [r7, #12] + 2182 0008 B960 str r1, [r7, #8] + 2183 000a 7A60 str r2, [r7, #4] + 2184 000c 7B80 strh r3, [r7, #2] @ movhi + 875:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 2185 .loc 1 875 21 + 2186 000e 0023 movs r3, #0 + 2187 0010 FB75 strb r3, [r7, #23] + 876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** uint32_t tmpsmcr; + 877:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 878:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Check the parameters */ + 879:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + 880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Set the TIM complementary channel state */ + 882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + 2188 .loc 1 882 46 + 2189 0012 BB68 ldr r3, [r7, #8] + 2190 0014 002B cmp r3, #0 + 2191 0016 09D1 bne .L135 + 2192 .loc 1 882 7 discriminator 1 + 2193 0018 FB68 ldr r3, [r7, #12] + 2194 001a 93F84430 ldrb r3, [r3, #68] + 2195 001e DBB2 uxtb r3, r3 + 2196 .loc 1 882 46 discriminator 1 + 2197 0020 022B cmp r3, #2 + 2198 0022 0CBF ite eq + 2199 0024 0123 moveq r3, #1 + 2200 0026 0023 movne r3, #0 + 2201 0028 DBB2 uxtb r3, r3 + 2202 002a 22E0 b .L136 + 2203 .L135: + 2204 .loc 1 882 46 is_stmt 0 discriminator 2 + 2205 002c BB68 ldr r3, [r7, #8] + 2206 002e 042B cmp r3, #4 + 2207 0030 09D1 bne .L137 + 2208 .loc 1 882 7 is_stmt 1 discriminator 4 + 2209 0032 FB68 ldr r3, [r7, #12] + 2210 0034 93F84530 ldrb r3, [r3, #69] + 2211 0038 DBB2 uxtb r3, r3 + 2212 .loc 1 882 46 discriminator 4 + 2213 003a 022B cmp r3, #2 + ARM GAS /tmp/ccxRWv8k.s page 55 + + + 2214 003c 0CBF ite eq + 2215 003e 0123 moveq r3, #1 + 2216 0040 0023 movne r3, #0 + 2217 0042 DBB2 uxtb r3, r3 + 2218 0044 15E0 b .L136 + 2219 .L137: + 2220 .loc 1 882 46 is_stmt 0 discriminator 5 + 2221 0046 BB68 ldr r3, [r7, #8] + 2222 0048 082B cmp r3, #8 + 2223 004a 09D1 bne .L139 + 2224 .loc 1 882 7 is_stmt 1 discriminator 7 + 2225 004c FB68 ldr r3, [r7, #12] + 2226 004e 93F84630 ldrb r3, [r3, #70] + 2227 0052 DBB2 uxtb r3, r3 + 2228 .loc 1 882 46 discriminator 7 + 2229 0054 022B cmp r3, #2 + 2230 0056 0CBF ite eq + 2231 0058 0123 moveq r3, #1 + 2232 005a 0023 movne r3, #0 + 2233 005c DBB2 uxtb r3, r3 + 2234 005e 08E0 b .L136 + 2235 .L139: + 2236 .loc 1 882 7 discriminator 8 + 2237 0060 FB68 ldr r3, [r7, #12] + 2238 0062 93F84730 ldrb r3, [r3, #71] + 2239 0066 DBB2 uxtb r3, r3 + 2240 .loc 1 882 46 discriminator 8 + 2241 0068 022B cmp r3, #2 + 2242 006a 0CBF ite eq + 2243 006c 0123 moveq r3, #1 + 2244 006e 0023 movne r3, #0 + 2245 0070 DBB2 uxtb r3, r3 + 2246 .L136: + 2247 .loc 1 882 6 discriminator 12 + 2248 0072 002B cmp r3, #0 + 2249 0074 01D0 beq .L141 + 883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 884:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return HAL_BUSY; + 2250 .loc 1 884 12 + 2251 0076 0223 movs r3, #2 + 2252 0078 20E1 b .L142 + 2253 .L141: + 885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + 2254 .loc 1 886 51 + 2255 007a BB68 ldr r3, [r7, #8] + 2256 007c 002B cmp r3, #0 + 2257 007e 09D1 bne .L143 + 2258 .loc 1 886 12 discriminator 1 + 2259 0080 FB68 ldr r3, [r7, #12] + 2260 0082 93F84430 ldrb r3, [r3, #68] + 2261 0086 DBB2 uxtb r3, r3 + 2262 .loc 1 886 51 discriminator 1 + 2263 0088 012B cmp r3, #1 + 2264 008a 0CBF ite eq + 2265 008c 0123 moveq r3, #1 + 2266 008e 0023 movne r3, #0 + ARM GAS /tmp/ccxRWv8k.s page 56 + + + 2267 0090 DBB2 uxtb r3, r3 + 2268 0092 22E0 b .L144 + 2269 .L143: + 2270 .loc 1 886 51 is_stmt 0 discriminator 2 + 2271 0094 BB68 ldr r3, [r7, #8] + 2272 0096 042B cmp r3, #4 + 2273 0098 09D1 bne .L145 + 2274 .loc 1 886 12 is_stmt 1 discriminator 4 + 2275 009a FB68 ldr r3, [r7, #12] + 2276 009c 93F84530 ldrb r3, [r3, #69] + 2277 00a0 DBB2 uxtb r3, r3 + 2278 .loc 1 886 51 discriminator 4 + 2279 00a2 012B cmp r3, #1 + 2280 00a4 0CBF ite eq + 2281 00a6 0123 moveq r3, #1 + 2282 00a8 0023 movne r3, #0 + 2283 00aa DBB2 uxtb r3, r3 + 2284 00ac 15E0 b .L144 + 2285 .L145: + 2286 .loc 1 886 51 is_stmt 0 discriminator 5 + 2287 00ae BB68 ldr r3, [r7, #8] + 2288 00b0 082B cmp r3, #8 + 2289 00b2 09D1 bne .L147 + 2290 .loc 1 886 12 is_stmt 1 discriminator 7 + 2291 00b4 FB68 ldr r3, [r7, #12] + 2292 00b6 93F84630 ldrb r3, [r3, #70] + 2293 00ba DBB2 uxtb r3, r3 + 2294 .loc 1 886 51 discriminator 7 + 2295 00bc 012B cmp r3, #1 + 2296 00be 0CBF ite eq + 2297 00c0 0123 moveq r3, #1 + 2298 00c2 0023 movne r3, #0 + 2299 00c4 DBB2 uxtb r3, r3 + 2300 00c6 08E0 b .L144 + 2301 .L147: + 2302 .loc 1 886 12 discriminator 8 + 2303 00c8 FB68 ldr r3, [r7, #12] + 2304 00ca 93F84730 ldrb r3, [r3, #71] + 2305 00ce DBB2 uxtb r3, r3 + 2306 .loc 1 886 51 discriminator 8 + 2307 00d0 012B cmp r3, #1 + 2308 00d2 0CBF ite eq + 2309 00d4 0123 moveq r3, #1 + 2310 00d6 0023 movne r3, #0 + 2311 00d8 DBB2 uxtb r3, r3 + 2312 .L144: + 2313 .loc 1 886 11 discriminator 12 + 2314 00da 002B cmp r3, #0 + 2315 00dc 24D0 beq .L149 + 887:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 888:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if ((pData == NULL) || (Length == 0U)) + 2316 .loc 1 888 8 + 2317 00de 7B68 ldr r3, [r7, #4] + 2318 00e0 002B cmp r3, #0 + 2319 00e2 02D0 beq .L150 + 2320 .loc 1 888 25 discriminator 1 + 2321 00e4 7B88 ldrh r3, [r7, #2] + ARM GAS /tmp/ccxRWv8k.s page 57 + + + 2322 00e6 002B cmp r3, #0 + 2323 00e8 01D1 bne .L151 + 2324 .L150: + 889:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 890:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return HAL_ERROR; + 2325 .loc 1 890 14 + 2326 00ea 0123 movs r3, #1 + 2327 00ec E6E0 b .L142 + 2328 .L151: + 891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 892:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** else + 893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 894:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + 2329 .loc 1 894 7 + 2330 00ee BB68 ldr r3, [r7, #8] + 2331 00f0 002B cmp r3, #0 + 2332 00f2 04D1 bne .L152 + 2333 .loc 1 894 7 is_stmt 0 discriminator 1 + 2334 00f4 FB68 ldr r3, [r7, #12] + 2335 00f6 0222 movs r2, #2 + 2336 00f8 83F84420 strb r2, [r3, #68] + 2337 00fc 16E0 b .L153 + 2338 .L152: + 2339 .loc 1 894 7 discriminator 2 + 2340 00fe BB68 ldr r3, [r7, #8] + 2341 0100 042B cmp r3, #4 + 2342 0102 04D1 bne .L154 + 2343 .loc 1 894 7 discriminator 3 + 2344 0104 FB68 ldr r3, [r7, #12] + 2345 0106 0222 movs r2, #2 + 2346 0108 83F84520 strb r2, [r3, #69] + 2347 .loc 1 894 7 discriminator 10 + 2348 010c 0EE0 b .L153 + 2349 .L154: + 2350 .loc 1 894 7 discriminator 4 + 2351 010e BB68 ldr r3, [r7, #8] + 2352 0110 082B cmp r3, #8 + 2353 0112 04D1 bne .L156 + 2354 .loc 1 894 7 discriminator 6 + 2355 0114 FB68 ldr r3, [r7, #12] + 2356 0116 0222 movs r2, #2 + 2357 0118 83F84620 strb r2, [r3, #70] + 2358 .loc 1 894 7 discriminator 10 + 2359 011c 06E0 b .L153 + 2360 .L156: + 2361 .loc 1 894 7 discriminator 7 + 2362 011e FB68 ldr r3, [r7, #12] + 2363 0120 0222 movs r2, #2 + 2364 0122 83F84720 strb r2, [r3, #71] + 2365 0126 01E0 b .L153 + 2366 .L149: + 895:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 897:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** else + 898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 899:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return HAL_ERROR; + 2367 .loc 1 899 12 is_stmt 1 + ARM GAS /tmp/ccxRWv8k.s page 58 + + + 2368 0128 0123 movs r3, #1 + 2369 012a C7E0 b .L142 + 2370 .L153: + 900:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 902:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** switch (Channel) + 2371 .loc 1 902 3 + 2372 012c BB68 ldr r3, [r7, #8] + 2373 012e 082B cmp r3, #8 + 2374 0130 51D0 beq .L158 + 2375 0132 BB68 ldr r3, [r7, #8] + 2376 0134 082B cmp r3, #8 + 2377 0136 72D8 bhi .L159 + 2378 0138 BB68 ldr r3, [r7, #8] + 2379 013a 002B cmp r3, #0 + 2380 013c 03D0 beq .L160 + 2381 013e BB68 ldr r3, [r7, #8] + 2382 0140 042B cmp r3, #4 + 2383 0142 24D0 beq .L161 + 2384 0144 6BE0 b .L159 + 2385 .L160: + 903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 904:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** case TIM_CHANNEL_1: + 905:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 906:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Set the DMA compare callbacks */ + 907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; + 2386 .loc 1 907 17 + 2387 0146 FB68 ldr r3, [r7, #12] + 2388 0148 5B6A ldr r3, [r3, #36] + 2389 .loc 1 907 52 + 2390 014a 5E4A ldr r2, .L171 + 2391 014c 9A62 str r2, [r3, #40] + 908:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 2392 .loc 1 908 17 + 2393 014e FB68 ldr r3, [r7, #12] + 2394 0150 5B6A ldr r3, [r3, #36] + 2395 .loc 1 908 56 + 2396 0152 5D4A ldr r2, .L171+4 + 2397 0154 DA62 str r2, [r3, #44] + 909:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Set the DMA error callback */ + 911:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; + 2398 .loc 1 911 17 + 2399 0156 FB68 ldr r3, [r7, #12] + 2400 0158 5B6A ldr r3, [r3, #36] + 2401 .loc 1 911 53 + 2402 015a 5C4A ldr r2, .L171+8 + 2403 015c 1A63 str r2, [r3, #48] + 912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 913:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the DMA channel */ + 914:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance-> + 2404 .loc 1 914 11 + 2405 015e FB68 ldr r3, [r7, #12] + 2406 0160 586A ldr r0, [r3, #36] + 2407 0162 7968 ldr r1, [r7, #4] + 2408 .loc 1 914 88 + 2409 0164 FB68 ldr r3, [r7, #12] + ARM GAS /tmp/ccxRWv8k.s page 59 + + + 2410 0166 1B68 ldr r3, [r3] + 2411 .loc 1 914 83 + 2412 0168 3433 adds r3, r3, #52 + 2413 .loc 1 914 11 + 2414 016a 1A46 mov r2, r3 + 2415 016c 7B88 ldrh r3, [r7, #2] + 2416 016e FFF7FEFF bl HAL_DMA_Start_IT + 2417 0172 0346 mov r3, r0 + 2418 .loc 1 914 10 discriminator 1 + 2419 0174 002B cmp r3, #0 + 2420 0176 01D0 beq .L162 + 915:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** Length) != HAL_OK) + 916:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 917:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Return error status */ + 918:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return HAL_ERROR; + 2421 .loc 1 918 16 + 2422 0178 0123 movs r3, #1 + 2423 017a 9FE0 b .L142 + 2424 .L162: + 919:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 920:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the TIM Output Compare DMA request */ + 921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + 2425 .loc 1 921 7 + 2426 017c FB68 ldr r3, [r7, #12] + 2427 017e 1B68 ldr r3, [r3] + 2428 0180 DA68 ldr r2, [r3, #12] + 2429 0182 FB68 ldr r3, [r7, #12] + 2430 0184 1B68 ldr r3, [r3] + 2431 0186 42F40072 orr r2, r2, #512 + 2432 018a DA60 str r2, [r3, #12] + 922:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** break; + 2433 .loc 1 922 7 + 2434 018c 4AE0 b .L163 + 2435 .L161: + 923:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 924:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 925:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** case TIM_CHANNEL_2: + 926:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Set the DMA compare callbacks */ + 928:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; + 2436 .loc 1 928 17 + 2437 018e FB68 ldr r3, [r7, #12] + 2438 0190 9B6A ldr r3, [r3, #40] + 2439 .loc 1 928 52 + 2440 0192 4C4A ldr r2, .L171 + 2441 0194 9A62 str r2, [r3, #40] + 929:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 2442 .loc 1 929 17 + 2443 0196 FB68 ldr r3, [r7, #12] + 2444 0198 9B6A ldr r3, [r3, #40] + 2445 .loc 1 929 56 + 2446 019a 4B4A ldr r2, .L171+4 + 2447 019c DA62 str r2, [r3, #44] + 930:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 931:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Set the DMA error callback */ + 932:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; + 2448 .loc 1 932 17 + ARM GAS /tmp/ccxRWv8k.s page 60 + + + 2449 019e FB68 ldr r3, [r7, #12] + 2450 01a0 9B6A ldr r3, [r3, #40] + 2451 .loc 1 932 53 + 2452 01a2 4A4A ldr r2, .L171+8 + 2453 01a4 1A63 str r2, [r3, #48] + 933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 934:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the DMA channel */ + 935:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance-> + 2454 .loc 1 935 11 + 2455 01a6 FB68 ldr r3, [r7, #12] + 2456 01a8 986A ldr r0, [r3, #40] + 2457 01aa 7968 ldr r1, [r7, #4] + 2458 .loc 1 935 88 + 2459 01ac FB68 ldr r3, [r7, #12] + 2460 01ae 1B68 ldr r3, [r3] + 2461 .loc 1 935 83 + 2462 01b0 3833 adds r3, r3, #56 + 2463 .loc 1 935 11 + 2464 01b2 1A46 mov r2, r3 + 2465 01b4 7B88 ldrh r3, [r7, #2] + 2466 01b6 FFF7FEFF bl HAL_DMA_Start_IT + 2467 01ba 0346 mov r3, r0 + 2468 .loc 1 935 10 discriminator 1 + 2469 01bc 002B cmp r3, #0 + 2470 01be 01D0 beq .L164 + 936:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** Length) != HAL_OK) + 937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Return error status */ + 939:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return HAL_ERROR; + 2471 .loc 1 939 16 + 2472 01c0 0123 movs r3, #1 + 2473 01c2 7BE0 b .L142 + 2474 .L164: + 940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 941:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the TIM Output Compare DMA request */ + 942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + 2475 .loc 1 942 7 + 2476 01c4 FB68 ldr r3, [r7, #12] + 2477 01c6 1B68 ldr r3, [r3] + 2478 01c8 DA68 ldr r2, [r3, #12] + 2479 01ca FB68 ldr r3, [r7, #12] + 2480 01cc 1B68 ldr r3, [r3] + 2481 01ce 42F48062 orr r2, r2, #1024 + 2482 01d2 DA60 str r2, [r3, #12] + 943:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** break; + 2483 .loc 1 943 7 + 2484 01d4 26E0 b .L163 + 2485 .L158: + 944:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** case TIM_CHANNEL_3: + 947:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 948:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Set the DMA compare callbacks */ + 949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; + 2486 .loc 1 949 17 + 2487 01d6 FB68 ldr r3, [r7, #12] + 2488 01d8 DB6A ldr r3, [r3, #44] + ARM GAS /tmp/ccxRWv8k.s page 61 + + + 2489 .loc 1 949 52 + 2490 01da 3A4A ldr r2, .L171 + 2491 01dc 9A62 str r2, [r3, #40] + 950:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 2492 .loc 1 950 17 + 2493 01de FB68 ldr r3, [r7, #12] + 2494 01e0 DB6A ldr r3, [r3, #44] + 2495 .loc 1 950 56 + 2496 01e2 394A ldr r2, .L171+4 + 2497 01e4 DA62 str r2, [r3, #44] + 951:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Set the DMA error callback */ + 953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; + 2498 .loc 1 953 17 + 2499 01e6 FB68 ldr r3, [r7, #12] + 2500 01e8 DB6A ldr r3, [r3, #44] + 2501 .loc 1 953 53 + 2502 01ea 384A ldr r2, .L171+8 + 2503 01ec 1A63 str r2, [r3, #48] + 954:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the DMA channel */ + 956:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance-> + 2504 .loc 1 956 11 + 2505 01ee FB68 ldr r3, [r7, #12] + 2506 01f0 D86A ldr r0, [r3, #44] + 2507 01f2 7968 ldr r1, [r7, #4] + 2508 .loc 1 956 88 + 2509 01f4 FB68 ldr r3, [r7, #12] + 2510 01f6 1B68 ldr r3, [r3] + 2511 .loc 1 956 83 + 2512 01f8 3C33 adds r3, r3, #60 + 2513 .loc 1 956 11 + 2514 01fa 1A46 mov r2, r3 + 2515 01fc 7B88 ldrh r3, [r7, #2] + 2516 01fe FFF7FEFF bl HAL_DMA_Start_IT + 2517 0202 0346 mov r3, r0 + 2518 .loc 1 956 10 discriminator 1 + 2519 0204 002B cmp r3, #0 + 2520 0206 01D0 beq .L165 + 957:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** Length) != HAL_OK) + 958:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Return error status */ + 960:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return HAL_ERROR; + 2521 .loc 1 960 16 + 2522 0208 0123 movs r3, #1 + 2523 020a 57E0 b .L142 + 2524 .L165: + 961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the TIM Output Compare DMA request */ + 963:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + 2525 .loc 1 963 7 + 2526 020c FB68 ldr r3, [r7, #12] + 2527 020e 1B68 ldr r3, [r3] + 2528 0210 DA68 ldr r2, [r3, #12] + 2529 0212 FB68 ldr r3, [r7, #12] + 2530 0214 1B68 ldr r3, [r3] + 2531 0216 42F40062 orr r2, r2, #2048 + ARM GAS /tmp/ccxRWv8k.s page 62 + + + 2532 021a DA60 str r2, [r3, #12] + 964:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** break; + 2533 .loc 1 964 7 + 2534 021c 02E0 b .L163 + 2535 .L159: + 965:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 966:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 967:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** default: + 968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** status = HAL_ERROR; + 2536 .loc 1 968 14 + 2537 021e 0123 movs r3, #1 + 2538 0220 FB75 strb r3, [r7, #23] + 969:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** break; + 2539 .loc 1 969 7 + 2540 0222 00BF nop + 2541 .L163: + 970:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 971:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 972:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (status == HAL_OK) + 2542 .loc 1 972 6 + 2543 0224 FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 2544 0226 002B cmp r3, #0 + 2545 0228 47D1 bne .L166 + 973:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 974:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the Capture compare channel N */ + 975:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + 2546 .loc 1 975 5 + 2547 022a FB68 ldr r3, [r7, #12] + 2548 022c 1B68 ldr r3, [r3] + 2549 022e 0422 movs r2, #4 + 2550 0230 B968 ldr r1, [r7, #8] + 2551 0232 1846 mov r0, r3 + 2552 0234 FFF7FEFF bl TIM_CCxNChannelCmd + 976:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 977:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the Main Output */ + 978:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_MOE_ENABLE(htim); + 2553 .loc 1 978 5 + 2554 0238 FB68 ldr r3, [r7, #12] + 2555 023a 1B68 ldr r3, [r3] + 2556 023c 5A6C ldr r2, [r3, #68] + 2557 023e FB68 ldr r3, [r7, #12] + 2558 0240 1B68 ldr r3, [r3] + 2559 0242 42F40042 orr r2, r2, #32768 + 2560 0246 5A64 str r2, [r3, #68] + 979:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigge + 981:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 2561 .loc 1 981 9 + 2562 0248 FB68 ldr r3, [r7, #12] + 2563 024a 1B68 ldr r3, [r3] + 2564 .loc 1 981 8 + 2565 024c 204A ldr r2, .L171+12 + 2566 024e 9342 cmp r3, r2 + 2567 0250 13D0 beq .L167 + 2568 .loc 1 981 9 discriminator 1 + 2569 0252 FB68 ldr r3, [r7, #12] + 2570 0254 1B68 ldr r3, [r3] + ARM GAS /tmp/ccxRWv8k.s page 63 + + + 2571 0256 B3F1804F cmp r3, #1073741824 + 2572 025a 0ED0 beq .L167 + 2573 .loc 1 981 9 is_stmt 0 discriminator 2 + 2574 025c FB68 ldr r3, [r7, #12] + 2575 025e 1B68 ldr r3, [r3] + 2576 0260 1C4A ldr r2, .L171+16 + 2577 0262 9342 cmp r3, r2 + 2578 0264 09D0 beq .L167 + 2579 .loc 1 981 9 discriminator 3 + 2580 0266 FB68 ldr r3, [r7, #12] + 2581 0268 1B68 ldr r3, [r3] + 2582 026a 1B4A ldr r2, .L171+20 + 2583 026c 9342 cmp r3, r2 + 2584 026e 04D0 beq .L167 + 2585 .loc 1 981 9 discriminator 4 + 2586 0270 FB68 ldr r3, [r7, #12] + 2587 0272 1B68 ldr r3, [r3] + 2588 0274 194A ldr r2, .L171+24 + 2589 0276 9342 cmp r3, r2 + 2590 0278 15D1 bne .L168 + 2591 .L167: + 982:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 983:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + 2592 .loc 1 983 21 is_stmt 1 + 2593 027a FB68 ldr r3, [r7, #12] + 2594 027c 1B68 ldr r3, [r3] + 2595 .loc 1 983 31 + 2596 027e 9A68 ldr r2, [r3, #8] + 2597 .loc 1 983 15 + 2598 0280 174B ldr r3, .L171+28 + 2599 0282 1340 ands r3, r3, r2 + 2600 0284 3B61 str r3, [r7, #16] + 984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 2601 .loc 1 984 10 + 2602 0286 3B69 ldr r3, [r7, #16] + 2603 0288 062B cmp r3, #6 + 2604 028a 15D0 beq .L170 + 2605 .loc 1 984 11 discriminator 1 + 2606 028c 3B69 ldr r3, [r7, #16] + 2607 028e B3F5803F cmp r3, #65536 + 2608 0292 11D0 beq .L170 + 985:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 986:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_ENABLE(htim); + 2609 .loc 1 986 9 + 2610 0294 FB68 ldr r3, [r7, #12] + 2611 0296 1B68 ldr r3, [r3] + 2612 0298 1A68 ldr r2, [r3] + 2613 029a FB68 ldr r3, [r7, #12] + 2614 029c 1B68 ldr r3, [r3] + 2615 029e 42F00102 orr r2, r2, #1 + 2616 02a2 1A60 str r2, [r3] + 984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 2617 .loc 1 984 10 + 2618 02a4 08E0 b .L170 + 2619 .L168: + 987:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 988:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + ARM GAS /tmp/ccxRWv8k.s page 64 + + + 989:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** else + 990:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 991:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_ENABLE(htim); + 2620 .loc 1 991 7 + 2621 02a6 FB68 ldr r3, [r7, #12] + 2622 02a8 1B68 ldr r3, [r3] + 2623 02aa 1A68 ldr r2, [r3] + 2624 02ac FB68 ldr r3, [r7, #12] + 2625 02ae 1B68 ldr r3, [r3] + 2626 02b0 42F00102 orr r2, r2, #1 + 2627 02b4 1A60 str r2, [r3] + 2628 02b6 00E0 b .L166 + 2629 .L170: + 984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 2630 .loc 1 984 10 + 2631 02b8 00BF nop + 2632 .L166: + 992:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 993:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 994:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Return function status */ + 996:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return status; + 2633 .loc 1 996 10 + 2634 02ba FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 2635 .L142: + 997:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 2636 .loc 1 997 1 + 2637 02bc 1846 mov r0, r3 + 2638 02be 1837 adds r7, r7, #24 + 2639 .cfi_def_cfa_offset 8 + 2640 02c0 BD46 mov sp, r7 + 2641 .cfi_def_cfa_register 13 + 2642 @ sp needed + 2643 02c2 80BD pop {r7, pc} + 2644 .L172: + 2645 .align 2 + 2646 .L171: + 2647 02c4 00000000 .word TIM_DMADelayPulseNCplt + 2648 02c8 00000000 .word TIM_DMADelayPulseHalfCplt + 2649 02cc 00000000 .word TIM_DMAErrorCCxN + 2650 02d0 002C0140 .word 1073818624 + 2651 02d4 00040040 .word 1073742848 + 2652 02d8 00080040 .word 1073743872 + 2653 02dc 00400140 .word 1073823744 + 2654 02e0 07000100 .word 65543 + 2655 .cfi_endproc + 2656 .LFE144: + 2658 .section .text.HAL_TIMEx_OCN_Stop_DMA,"ax",%progbits + 2659 .align 1 + 2660 .global HAL_TIMEx_OCN_Stop_DMA + 2661 .syntax unified + 2662 .thumb + 2663 .thumb_func + 2665 HAL_TIMEx_OCN_Stop_DMA: + 2666 .LFB145: + 998:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + 999:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** + ARM GAS /tmp/ccxRWv8k.s page 65 + + +1000:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief Stops the TIM Output Compare signal generation in DMA mode +1001:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * on the complementary output. +1002:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param htim TIM Output Compare handle +1003:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param Channel TIM Channel to be disabled +1004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * This parameter can be one of the following values: +1005:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +1006:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +1007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +1008:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @retval HAL status +1009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ +1010:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +1011:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 2667 .loc 1 1011 1 + 2668 .cfi_startproc + 2669 @ args = 0, pretend = 0, frame = 16 + 2670 @ frame_needed = 1, uses_anonymous_args = 0 + 2671 0000 80B5 push {r7, lr} + 2672 .cfi_def_cfa_offset 8 + 2673 .cfi_offset 7, -8 + 2674 .cfi_offset 14, -4 + 2675 0002 84B0 sub sp, sp, #16 + 2676 .cfi_def_cfa_offset 24 + 2677 0004 00AF add r7, sp, #0 + 2678 .cfi_def_cfa_register 7 + 2679 0006 7860 str r0, [r7, #4] + 2680 0008 3960 str r1, [r7] +1012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 2681 .loc 1 1012 21 + 2682 000a 0023 movs r3, #0 + 2683 000c FB73 strb r3, [r7, #15] +1013:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1014:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Check the parameters */ +1015:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); +1016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1017:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** switch (Channel) + 2684 .loc 1 1017 3 + 2685 000e 3B68 ldr r3, [r7] + 2686 0010 082B cmp r3, #8 + 2687 0012 25D0 beq .L174 + 2688 0014 3B68 ldr r3, [r7] + 2689 0016 082B cmp r3, #8 + 2690 0018 30D8 bhi .L175 + 2691 001a 3B68 ldr r3, [r7] + 2692 001c 002B cmp r3, #0 + 2693 001e 03D0 beq .L176 + 2694 0020 3B68 ldr r3, [r7] + 2695 0022 042B cmp r3, #4 + 2696 0024 0ED0 beq .L177 + 2697 0026 29E0 b .L175 + 2698 .L176: +1018:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +1019:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** case TIM_CHANNEL_1: +1020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +1021:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable the TIM Output Compare DMA request */ +1022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + 2699 .loc 1 1022 7 + 2700 0028 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/ccxRWv8k.s page 66 + + + 2701 002a 1B68 ldr r3, [r3] + 2702 002c DA68 ldr r2, [r3, #12] + 2703 002e 7B68 ldr r3, [r7, #4] + 2704 0030 1B68 ldr r3, [r3] + 2705 0032 22F40072 bic r2, r2, #512 + 2706 0036 DA60 str r2, [r3, #12] +1023:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + 2707 .loc 1 1023 13 + 2708 0038 7B68 ldr r3, [r7, #4] + 2709 003a 5B6A ldr r3, [r3, #36] + 2710 003c 1846 mov r0, r3 + 2711 003e FFF7FEFF bl HAL_DMA_Abort_IT +1024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** break; + 2712 .loc 1 1024 7 + 2713 0042 1EE0 b .L178 + 2714 .L177: +1025:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +1026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** case TIM_CHANNEL_2: +1028:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +1029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable the TIM Output Compare DMA request */ +1030:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + 2715 .loc 1 1030 7 + 2716 0044 7B68 ldr r3, [r7, #4] + 2717 0046 1B68 ldr r3, [r3] + 2718 0048 DA68 ldr r2, [r3, #12] + 2719 004a 7B68 ldr r3, [r7, #4] + 2720 004c 1B68 ldr r3, [r3] + 2721 004e 22F48062 bic r2, r2, #1024 + 2722 0052 DA60 str r2, [r3, #12] +1031:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + 2723 .loc 1 1031 13 + 2724 0054 7B68 ldr r3, [r7, #4] + 2725 0056 9B6A ldr r3, [r3, #40] + 2726 0058 1846 mov r0, r3 + 2727 005a FFF7FEFF bl HAL_DMA_Abort_IT +1032:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** break; + 2728 .loc 1 1032 7 + 2729 005e 10E0 b .L178 + 2730 .L174: +1033:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +1034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1035:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** case TIM_CHANNEL_3: +1036:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +1037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable the TIM Output Compare DMA request */ +1038:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + 2731 .loc 1 1038 7 + 2732 0060 7B68 ldr r3, [r7, #4] + 2733 0062 1B68 ldr r3, [r3] + 2734 0064 DA68 ldr r2, [r3, #12] + 2735 0066 7B68 ldr r3, [r7, #4] + 2736 0068 1B68 ldr r3, [r3] + 2737 006a 22F40062 bic r2, r2, #2048 + 2738 006e DA60 str r2, [r3, #12] +1039:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + 2739 .loc 1 1039 13 + 2740 0070 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/ccxRWv8k.s page 67 + + + 2741 0072 DB6A ldr r3, [r3, #44] + 2742 0074 1846 mov r0, r3 + 2743 0076 FFF7FEFF bl HAL_DMA_Abort_IT +1040:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** break; + 2744 .loc 1 1040 7 + 2745 007a 02E0 b .L178 + 2746 .L175: +1041:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +1042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1043:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** default: +1044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** status = HAL_ERROR; + 2747 .loc 1 1044 14 + 2748 007c 0123 movs r3, #1 + 2749 007e FB73 strb r3, [r7, #15] +1045:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** break; + 2750 .loc 1 1045 7 + 2751 0080 00BF nop + 2752 .L178: +1046:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +1047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (status == HAL_OK) + 2753 .loc 1 1048 6 + 2754 0082 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 2755 0084 002B cmp r3, #0 + 2756 0086 52D1 bne .L179 +1049:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +1050:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable the Capture compare channel N */ +1051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + 2757 .loc 1 1051 5 + 2758 0088 7B68 ldr r3, [r7, #4] + 2759 008a 1B68 ldr r3, [r3] + 2760 008c 0022 movs r2, #0 + 2761 008e 3968 ldr r1, [r7] + 2762 0090 1846 mov r0, r3 + 2763 0092 FFF7FEFF bl TIM_CCxNChannelCmd +1052:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable the Main Output */ +1054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_MOE_DISABLE(htim); + 2764 .loc 1 1054 5 + 2765 0096 7B68 ldr r3, [r7, #4] + 2766 0098 1B68 ldr r3, [r3] + 2767 009a 1A6A ldr r2, [r3, #32] + 2768 009c 41F21113 movw r3, #4369 + 2769 00a0 1340 ands r3, r3, r2 + 2770 00a2 002B cmp r3, #0 + 2771 00a4 0FD1 bne .L180 + 2772 .loc 1 1054 5 is_stmt 0 discriminator 1 + 2773 00a6 7B68 ldr r3, [r7, #4] + 2774 00a8 1B68 ldr r3, [r3] + 2775 00aa 1A6A ldr r2, [r3, #32] + 2776 00ac 40F24443 movw r3, #1092 + 2777 00b0 1340 ands r3, r3, r2 + 2778 00b2 002B cmp r3, #0 + 2779 00b4 07D1 bne .L180 + 2780 .loc 1 1054 5 discriminator 2 + 2781 00b6 7B68 ldr r3, [r7, #4] + 2782 00b8 1B68 ldr r3, [r3] + ARM GAS /tmp/ccxRWv8k.s page 68 + + + 2783 00ba 5A6C ldr r2, [r3, #68] + 2784 00bc 7B68 ldr r3, [r7, #4] + 2785 00be 1B68 ldr r3, [r3] + 2786 00c0 22F40042 bic r2, r2, #32768 + 2787 00c4 5A64 str r2, [r3, #68] + 2788 .L180: +1055:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable the Peripheral */ +1057:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_DISABLE(htim); + 2789 .loc 1 1057 5 is_stmt 1 + 2790 00c6 7B68 ldr r3, [r7, #4] + 2791 00c8 1B68 ldr r3, [r3] + 2792 00ca 1A6A ldr r2, [r3, #32] + 2793 00cc 41F21113 movw r3, #4369 + 2794 00d0 1340 ands r3, r3, r2 + 2795 00d2 002B cmp r3, #0 + 2796 00d4 0FD1 bne .L181 + 2797 .loc 1 1057 5 is_stmt 0 discriminator 1 + 2798 00d6 7B68 ldr r3, [r7, #4] + 2799 00d8 1B68 ldr r3, [r3] + 2800 00da 1A6A ldr r2, [r3, #32] + 2801 00dc 40F24443 movw r3, #1092 + 2802 00e0 1340 ands r3, r3, r2 + 2803 00e2 002B cmp r3, #0 + 2804 00e4 07D1 bne .L181 + 2805 .loc 1 1057 5 discriminator 2 + 2806 00e6 7B68 ldr r3, [r7, #4] + 2807 00e8 1B68 ldr r3, [r3] + 2808 00ea 1A68 ldr r2, [r3] + 2809 00ec 7B68 ldr r3, [r7, #4] + 2810 00ee 1B68 ldr r3, [r3] + 2811 00f0 22F00102 bic r2, r2, #1 + 2812 00f4 1A60 str r2, [r3] + 2813 .L181: +1058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Set the TIM complementary channel state */ +1060:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 2814 .loc 1 1060 5 is_stmt 1 + 2815 00f6 3B68 ldr r3, [r7] + 2816 00f8 002B cmp r3, #0 + 2817 00fa 04D1 bne .L182 + 2818 .loc 1 1060 5 is_stmt 0 discriminator 1 + 2819 00fc 7B68 ldr r3, [r7, #4] + 2820 00fe 0122 movs r2, #1 + 2821 0100 83F84420 strb r2, [r3, #68] + 2822 0104 13E0 b .L179 + 2823 .L182: + 2824 .loc 1 1060 5 discriminator 2 + 2825 0106 3B68 ldr r3, [r7] + 2826 0108 042B cmp r3, #4 + 2827 010a 04D1 bne .L183 + 2828 .loc 1 1060 5 discriminator 3 + 2829 010c 7B68 ldr r3, [r7, #4] + 2830 010e 0122 movs r2, #1 + 2831 0110 83F84520 strb r2, [r3, #69] + 2832 0114 0BE0 b .L179 + 2833 .L183: + ARM GAS /tmp/ccxRWv8k.s page 69 + + + 2834 .loc 1 1060 5 discriminator 4 + 2835 0116 3B68 ldr r3, [r7] + 2836 0118 082B cmp r3, #8 + 2837 011a 04D1 bne .L185 + 2838 .loc 1 1060 5 discriminator 6 + 2839 011c 7B68 ldr r3, [r7, #4] + 2840 011e 0122 movs r2, #1 + 2841 0120 83F84620 strb r2, [r3, #70] + 2842 0124 03E0 b .L179 + 2843 .L185: + 2844 .loc 1 1060 5 discriminator 7 + 2845 0126 7B68 ldr r3, [r7, #4] + 2846 0128 0122 movs r2, #1 + 2847 012a 83F84720 strb r2, [r3, #71] + 2848 .L179: +1061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +1062:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1063:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Return function status */ +1064:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return status; + 2849 .loc 1 1064 10 is_stmt 1 + 2850 012e FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 +1065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 2851 .loc 1 1065 1 + 2852 0130 1846 mov r0, r3 + 2853 0132 1037 adds r7, r7, #16 + 2854 .cfi_def_cfa_offset 8 + 2855 0134 BD46 mov sp, r7 + 2856 .cfi_def_cfa_register 13 + 2857 @ sp needed + 2858 0136 80BD pop {r7, pc} + 2859 .cfi_endproc + 2860 .LFE145: + 2862 .section .text.HAL_TIMEx_PWMN_Start,"ax",%progbits + 2863 .align 1 + 2864 .global HAL_TIMEx_PWMN_Start + 2865 .syntax unified + 2866 .thumb + 2867 .thumb_func + 2869 HAL_TIMEx_PWMN_Start: + 2870 .LFB146: +1066:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1067:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** +1068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @} +1069:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ +1070:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions +1072:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief Timer Complementary PWM functions +1073:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * +1074:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** @verbatim +1075:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** ============================================================================== +1076:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** ##### Timer Complementary PWM functions ##### +1077:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** ============================================================================== +1078:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** [..] +1079:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** This section provides functions allowing to: +1080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (+) Start the Complementary PWM. +1081:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (+) Stop the Complementary PWM. +1082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (+) Start the Complementary PWM and enable interrupts. + ARM GAS /tmp/ccxRWv8k.s page 70 + + +1083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (+) Stop the Complementary PWM and disable interrupts. +1084:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (+) Start the Complementary PWM and enable DMA transfers. +1085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (+) Stop the Complementary PWM and disable DMA transfers. +1086:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (+) Start the Complementary Input Capture measurement. +1087:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (+) Stop the Complementary Input Capture. +1088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (+) Start the Complementary Input Capture and enable interrupts. +1089:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (+) Stop the Complementary Input Capture and disable interrupts. +1090:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (+) Start the Complementary Input Capture and enable DMA transfers. +1091:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (+) Stop the Complementary Input Capture and disable DMA transfers. +1092:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (+) Start the Complementary One Pulse generation. +1093:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (+) Stop the Complementary One Pulse. +1094:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (+) Start the Complementary One Pulse and enable interrupts. +1095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (+) Stop the Complementary One Pulse and disable interrupts. +1096:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1097:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** @endverbatim +1098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @{ +1099:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ +1100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** +1102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief Starts the PWM signal generation on the complementary output. +1103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param htim TIM handle +1104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param Channel TIM Channel to be enabled +1105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * This parameter can be one of the following values: +1106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +1107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +1108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +1109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @retval HAL status +1110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ +1111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +1112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 2871 .loc 1 1112 1 + 2872 .cfi_startproc + 2873 @ args = 0, pretend = 0, frame = 16 + 2874 @ frame_needed = 1, uses_anonymous_args = 0 + 2875 0000 80B5 push {r7, lr} + 2876 .cfi_def_cfa_offset 8 + 2877 .cfi_offset 7, -8 + 2878 .cfi_offset 14, -4 + 2879 0002 84B0 sub sp, sp, #16 + 2880 .cfi_def_cfa_offset 24 + 2881 0004 00AF add r7, sp, #0 + 2882 .cfi_def_cfa_register 7 + 2883 0006 7860 str r0, [r7, #4] + 2884 0008 3960 str r1, [r7] +1113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** uint32_t tmpsmcr; +1114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Check the parameters */ +1116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); +1117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Check the TIM complementary channel state */ +1119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + 2885 .loc 1 1119 46 + 2886 000a 3B68 ldr r3, [r7] + 2887 000c 002B cmp r3, #0 + 2888 000e 09D1 bne .L189 + 2889 .loc 1 1119 7 discriminator 1 + 2890 0010 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/ccxRWv8k.s page 71 + + + 2891 0012 93F84430 ldrb r3, [r3, #68] + 2892 0016 DBB2 uxtb r3, r3 + 2893 .loc 1 1119 46 discriminator 1 + 2894 0018 012B cmp r3, #1 + 2895 001a 14BF ite ne + 2896 001c 0123 movne r3, #1 + 2897 001e 0023 moveq r3, #0 + 2898 0020 DBB2 uxtb r3, r3 + 2899 0022 22E0 b .L190 + 2900 .L189: + 2901 .loc 1 1119 46 is_stmt 0 discriminator 2 + 2902 0024 3B68 ldr r3, [r7] + 2903 0026 042B cmp r3, #4 + 2904 0028 09D1 bne .L191 + 2905 .loc 1 1119 7 is_stmt 1 discriminator 4 + 2906 002a 7B68 ldr r3, [r7, #4] + 2907 002c 93F84530 ldrb r3, [r3, #69] + 2908 0030 DBB2 uxtb r3, r3 + 2909 .loc 1 1119 46 discriminator 4 + 2910 0032 012B cmp r3, #1 + 2911 0034 14BF ite ne + 2912 0036 0123 movne r3, #1 + 2913 0038 0023 moveq r3, #0 + 2914 003a DBB2 uxtb r3, r3 + 2915 003c 15E0 b .L190 + 2916 .L191: + 2917 .loc 1 1119 46 is_stmt 0 discriminator 5 + 2918 003e 3B68 ldr r3, [r7] + 2919 0040 082B cmp r3, #8 + 2920 0042 09D1 bne .L193 + 2921 .loc 1 1119 7 is_stmt 1 discriminator 7 + 2922 0044 7B68 ldr r3, [r7, #4] + 2923 0046 93F84630 ldrb r3, [r3, #70] + 2924 004a DBB2 uxtb r3, r3 + 2925 .loc 1 1119 46 discriminator 7 + 2926 004c 012B cmp r3, #1 + 2927 004e 14BF ite ne + 2928 0050 0123 movne r3, #1 + 2929 0052 0023 moveq r3, #0 + 2930 0054 DBB2 uxtb r3, r3 + 2931 0056 08E0 b .L190 + 2932 .L193: + 2933 .loc 1 1119 7 discriminator 8 + 2934 0058 7B68 ldr r3, [r7, #4] + 2935 005a 93F84730 ldrb r3, [r3, #71] + 2936 005e DBB2 uxtb r3, r3 + 2937 .loc 1 1119 46 discriminator 8 + 2938 0060 012B cmp r3, #1 + 2939 0062 14BF ite ne + 2940 0064 0123 movne r3, #1 + 2941 0066 0023 moveq r3, #0 + 2942 0068 DBB2 uxtb r3, r3 + 2943 .L190: + 2944 .loc 1 1119 6 discriminator 12 + 2945 006a 002B cmp r3, #0 + 2946 006c 01D0 beq .L195 +1120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + ARM GAS /tmp/ccxRWv8k.s page 72 + + +1121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return HAL_ERROR; + 2947 .loc 1 1121 12 + 2948 006e 0123 movs r3, #1 + 2949 0070 64E0 b .L196 + 2950 .L195: +1122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +1123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Set the TIM complementary channel state */ +1125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + 2951 .loc 1 1125 3 + 2952 0072 3B68 ldr r3, [r7] + 2953 0074 002B cmp r3, #0 + 2954 0076 04D1 bne .L197 + 2955 .loc 1 1125 3 is_stmt 0 discriminator 1 + 2956 0078 7B68 ldr r3, [r7, #4] + 2957 007a 0222 movs r2, #2 + 2958 007c 83F84420 strb r2, [r3, #68] + 2959 0080 13E0 b .L198 + 2960 .L197: + 2961 .loc 1 1125 3 discriminator 2 + 2962 0082 3B68 ldr r3, [r7] + 2963 0084 042B cmp r3, #4 + 2964 0086 04D1 bne .L199 + 2965 .loc 1 1125 3 discriminator 3 + 2966 0088 7B68 ldr r3, [r7, #4] + 2967 008a 0222 movs r2, #2 + 2968 008c 83F84520 strb r2, [r3, #69] + 2969 0090 0BE0 b .L198 + 2970 .L199: + 2971 .loc 1 1125 3 discriminator 4 + 2972 0092 3B68 ldr r3, [r7] + 2973 0094 082B cmp r3, #8 + 2974 0096 04D1 bne .L201 + 2975 .loc 1 1125 3 discriminator 6 + 2976 0098 7B68 ldr r3, [r7, #4] + 2977 009a 0222 movs r2, #2 + 2978 009c 83F84620 strb r2, [r3, #70] + 2979 00a0 03E0 b .L198 + 2980 .L201: + 2981 .loc 1 1125 3 discriminator 7 + 2982 00a2 7B68 ldr r3, [r7, #4] + 2983 00a4 0222 movs r2, #2 + 2984 00a6 83F84720 strb r2, [r3, #71] + 2985 .L198: +1126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the complementary PWM output */ +1128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + 2986 .loc 1 1128 3 is_stmt 1 + 2987 00aa 7B68 ldr r3, [r7, #4] + 2988 00ac 1B68 ldr r3, [r3] + 2989 00ae 0422 movs r2, #4 + 2990 00b0 3968 ldr r1, [r7] + 2991 00b2 1846 mov r0, r3 + 2992 00b4 FFF7FEFF bl TIM_CCxNChannelCmd +1129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the Main Output */ +1131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_MOE_ENABLE(htim); + ARM GAS /tmp/ccxRWv8k.s page 73 + + + 2993 .loc 1 1131 3 + 2994 00b8 7B68 ldr r3, [r7, #4] + 2995 00ba 1B68 ldr r3, [r3] + 2996 00bc 5A6C ldr r2, [r3, #68] + 2997 00be 7B68 ldr r3, [r7, #4] + 2998 00c0 1B68 ldr r3, [r3] + 2999 00c2 42F40042 orr r2, r2, #32768 + 3000 00c6 5A64 str r2, [r3, #68] +1132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger +1134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 3001 .loc 1 1134 7 + 3002 00c8 7B68 ldr r3, [r7, #4] + 3003 00ca 1B68 ldr r3, [r3] + 3004 .loc 1 1134 6 + 3005 00cc 1D4A ldr r2, .L208 + 3006 00ce 9342 cmp r3, r2 + 3007 00d0 13D0 beq .L203 + 3008 .loc 1 1134 7 discriminator 1 + 3009 00d2 7B68 ldr r3, [r7, #4] + 3010 00d4 1B68 ldr r3, [r3] + 3011 00d6 B3F1804F cmp r3, #1073741824 + 3012 00da 0ED0 beq .L203 + 3013 .loc 1 1134 7 is_stmt 0 discriminator 2 + 3014 00dc 7B68 ldr r3, [r7, #4] + 3015 00de 1B68 ldr r3, [r3] + 3016 00e0 194A ldr r2, .L208+4 + 3017 00e2 9342 cmp r3, r2 + 3018 00e4 09D0 beq .L203 + 3019 .loc 1 1134 7 discriminator 3 + 3020 00e6 7B68 ldr r3, [r7, #4] + 3021 00e8 1B68 ldr r3, [r3] + 3022 00ea 184A ldr r2, .L208+8 + 3023 00ec 9342 cmp r3, r2 + 3024 00ee 04D0 beq .L203 + 3025 .loc 1 1134 7 discriminator 4 + 3026 00f0 7B68 ldr r3, [r7, #4] + 3027 00f2 1B68 ldr r3, [r3] + 3028 00f4 164A ldr r2, .L208+12 + 3029 00f6 9342 cmp r3, r2 + 3030 00f8 15D1 bne .L204 + 3031 .L203: +1135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +1136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + 3032 .loc 1 1136 19 is_stmt 1 + 3033 00fa 7B68 ldr r3, [r7, #4] + 3034 00fc 1B68 ldr r3, [r3] + 3035 .loc 1 1136 29 + 3036 00fe 9A68 ldr r2, [r3, #8] + 3037 .loc 1 1136 13 + 3038 0100 144B ldr r3, .L208+16 + 3039 0102 1340 ands r3, r3, r2 + 3040 0104 FB60 str r3, [r7, #12] +1137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 3041 .loc 1 1137 8 + 3042 0106 FB68 ldr r3, [r7, #12] + 3043 0108 062B cmp r3, #6 + ARM GAS /tmp/ccxRWv8k.s page 74 + + + 3044 010a 15D0 beq .L207 + 3045 .loc 1 1137 9 discriminator 1 + 3046 010c FB68 ldr r3, [r7, #12] + 3047 010e B3F5803F cmp r3, #65536 + 3048 0112 11D0 beq .L207 +1138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +1139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_ENABLE(htim); + 3049 .loc 1 1139 7 + 3050 0114 7B68 ldr r3, [r7, #4] + 3051 0116 1B68 ldr r3, [r3] + 3052 0118 1A68 ldr r2, [r3] + 3053 011a 7B68 ldr r3, [r7, #4] + 3054 011c 1B68 ldr r3, [r3] + 3055 011e 42F00102 orr r2, r2, #1 + 3056 0122 1A60 str r2, [r3] +1137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 3057 .loc 1 1137 8 + 3058 0124 08E0 b .L207 + 3059 .L204: +1140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +1141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +1142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** else +1143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +1144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_ENABLE(htim); + 3060 .loc 1 1144 5 + 3061 0126 7B68 ldr r3, [r7, #4] + 3062 0128 1B68 ldr r3, [r3] + 3063 012a 1A68 ldr r2, [r3] + 3064 012c 7B68 ldr r3, [r7, #4] + 3065 012e 1B68 ldr r3, [r3] + 3066 0130 42F00102 orr r2, r2, #1 + 3067 0134 1A60 str r2, [r3] + 3068 0136 00E0 b .L206 + 3069 .L207: +1137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 3070 .loc 1 1137 8 + 3071 0138 00BF nop + 3072 .L206: +1145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +1146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Return function status */ +1148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return HAL_OK; + 3073 .loc 1 1148 10 + 3074 013a 0023 movs r3, #0 + 3075 .L196: +1149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 3076 .loc 1 1149 1 + 3077 013c 1846 mov r0, r3 + 3078 013e 1037 adds r7, r7, #16 + 3079 .cfi_def_cfa_offset 8 + 3080 0140 BD46 mov sp, r7 + 3081 .cfi_def_cfa_register 13 + 3082 @ sp needed + 3083 0142 80BD pop {r7, pc} + 3084 .L209: + 3085 .align 2 + 3086 .L208: + ARM GAS /tmp/ccxRWv8k.s page 75 + + + 3087 0144 002C0140 .word 1073818624 + 3088 0148 00040040 .word 1073742848 + 3089 014c 00080040 .word 1073743872 + 3090 0150 00400140 .word 1073823744 + 3091 0154 07000100 .word 65543 + 3092 .cfi_endproc + 3093 .LFE146: + 3095 .section .text.HAL_TIMEx_PWMN_Stop,"ax",%progbits + 3096 .align 1 + 3097 .global HAL_TIMEx_PWMN_Stop + 3098 .syntax unified + 3099 .thumb + 3100 .thumb_func + 3102 HAL_TIMEx_PWMN_Stop: + 3103 .LFB147: +1150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** +1152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief Stops the PWM signal generation on the complementary output. +1153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param htim TIM handle +1154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param Channel TIM Channel to be disabled +1155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * This parameter can be one of the following values: +1156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +1157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +1158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +1159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @retval HAL status +1160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ +1161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +1162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 3104 .loc 1 1162 1 + 3105 .cfi_startproc + 3106 @ args = 0, pretend = 0, frame = 8 + 3107 @ frame_needed = 1, uses_anonymous_args = 0 + 3108 0000 80B5 push {r7, lr} + 3109 .cfi_def_cfa_offset 8 + 3110 .cfi_offset 7, -8 + 3111 .cfi_offset 14, -4 + 3112 0002 82B0 sub sp, sp, #8 + 3113 .cfi_def_cfa_offset 16 + 3114 0004 00AF add r7, sp, #0 + 3115 .cfi_def_cfa_register 7 + 3116 0006 7860 str r0, [r7, #4] + 3117 0008 3960 str r1, [r7] +1163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Check the parameters */ +1164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); +1165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable the complementary PWM output */ +1167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + 3118 .loc 1 1167 3 + 3119 000a 7B68 ldr r3, [r7, #4] + 3120 000c 1B68 ldr r3, [r3] + 3121 000e 0022 movs r2, #0 + 3122 0010 3968 ldr r1, [r7] + 3123 0012 1846 mov r0, r3 + 3124 0014 FFF7FEFF bl TIM_CCxNChannelCmd +1168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable the Main Output */ +1170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_MOE_DISABLE(htim); + ARM GAS /tmp/ccxRWv8k.s page 76 + + + 3125 .loc 1 1170 3 + 3126 0018 7B68 ldr r3, [r7, #4] + 3127 001a 1B68 ldr r3, [r3] + 3128 001c 1A6A ldr r2, [r3, #32] + 3129 001e 41F21113 movw r3, #4369 + 3130 0022 1340 ands r3, r3, r2 + 3131 0024 002B cmp r3, #0 + 3132 0026 0FD1 bne .L211 + 3133 .loc 1 1170 3 is_stmt 0 discriminator 1 + 3134 0028 7B68 ldr r3, [r7, #4] + 3135 002a 1B68 ldr r3, [r3] + 3136 002c 1A6A ldr r2, [r3, #32] + 3137 002e 40F24443 movw r3, #1092 + 3138 0032 1340 ands r3, r3, r2 + 3139 0034 002B cmp r3, #0 + 3140 0036 07D1 bne .L211 + 3141 .loc 1 1170 3 discriminator 2 + 3142 0038 7B68 ldr r3, [r7, #4] + 3143 003a 1B68 ldr r3, [r3] + 3144 003c 5A6C ldr r2, [r3, #68] + 3145 003e 7B68 ldr r3, [r7, #4] + 3146 0040 1B68 ldr r3, [r3] + 3147 0042 22F40042 bic r2, r2, #32768 + 3148 0046 5A64 str r2, [r3, #68] + 3149 .L211: +1171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable the Peripheral */ +1173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_DISABLE(htim); + 3150 .loc 1 1173 3 is_stmt 1 + 3151 0048 7B68 ldr r3, [r7, #4] + 3152 004a 1B68 ldr r3, [r3] + 3153 004c 1A6A ldr r2, [r3, #32] + 3154 004e 41F21113 movw r3, #4369 + 3155 0052 1340 ands r3, r3, r2 + 3156 0054 002B cmp r3, #0 + 3157 0056 0FD1 bne .L212 + 3158 .loc 1 1173 3 is_stmt 0 discriminator 1 + 3159 0058 7B68 ldr r3, [r7, #4] + 3160 005a 1B68 ldr r3, [r3] + 3161 005c 1A6A ldr r2, [r3, #32] + 3162 005e 40F24443 movw r3, #1092 + 3163 0062 1340 ands r3, r3, r2 + 3164 0064 002B cmp r3, #0 + 3165 0066 07D1 bne .L212 + 3166 .loc 1 1173 3 discriminator 2 + 3167 0068 7B68 ldr r3, [r7, #4] + 3168 006a 1B68 ldr r3, [r3] + 3169 006c 1A68 ldr r2, [r3] + 3170 006e 7B68 ldr r3, [r7, #4] + 3171 0070 1B68 ldr r3, [r3] + 3172 0072 22F00102 bic r2, r2, #1 + 3173 0076 1A60 str r2, [r3] + 3174 .L212: +1174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Set the TIM complementary channel state */ +1176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 3175 .loc 1 1176 3 is_stmt 1 + ARM GAS /tmp/ccxRWv8k.s page 77 + + + 3176 0078 3B68 ldr r3, [r7] + 3177 007a 002B cmp r3, #0 + 3178 007c 04D1 bne .L213 + 3179 .loc 1 1176 3 is_stmt 0 discriminator 1 + 3180 007e 7B68 ldr r3, [r7, #4] + 3181 0080 0122 movs r2, #1 + 3182 0082 83F84420 strb r2, [r3, #68] + 3183 0086 13E0 b .L214 + 3184 .L213: + 3185 .loc 1 1176 3 discriminator 2 + 3186 0088 3B68 ldr r3, [r7] + 3187 008a 042B cmp r3, #4 + 3188 008c 04D1 bne .L215 + 3189 .loc 1 1176 3 discriminator 3 + 3190 008e 7B68 ldr r3, [r7, #4] + 3191 0090 0122 movs r2, #1 + 3192 0092 83F84520 strb r2, [r3, #69] + 3193 0096 0BE0 b .L214 + 3194 .L215: + 3195 .loc 1 1176 3 discriminator 4 + 3196 0098 3B68 ldr r3, [r7] + 3197 009a 082B cmp r3, #8 + 3198 009c 04D1 bne .L217 + 3199 .loc 1 1176 3 discriminator 6 + 3200 009e 7B68 ldr r3, [r7, #4] + 3201 00a0 0122 movs r2, #1 + 3202 00a2 83F84620 strb r2, [r3, #70] + 3203 00a6 03E0 b .L214 + 3204 .L217: + 3205 .loc 1 1176 3 discriminator 7 + 3206 00a8 7B68 ldr r3, [r7, #4] + 3207 00aa 0122 movs r2, #1 + 3208 00ac 83F84720 strb r2, [r3, #71] + 3209 .L214: +1177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Return function status */ +1179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return HAL_OK; + 3210 .loc 1 1179 10 is_stmt 1 + 3211 00b0 0023 movs r3, #0 +1180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 3212 .loc 1 1180 1 + 3213 00b2 1846 mov r0, r3 + 3214 00b4 0837 adds r7, r7, #8 + 3215 .cfi_def_cfa_offset 8 + 3216 00b6 BD46 mov sp, r7 + 3217 .cfi_def_cfa_register 13 + 3218 @ sp needed + 3219 00b8 80BD pop {r7, pc} + 3220 .cfi_endproc + 3221 .LFE147: + 3223 .section .text.HAL_TIMEx_PWMN_Start_IT,"ax",%progbits + 3224 .align 1 + 3225 .global HAL_TIMEx_PWMN_Start_IT + 3226 .syntax unified + 3227 .thumb + 3228 .thumb_func + 3230 HAL_TIMEx_PWMN_Start_IT: + ARM GAS /tmp/ccxRWv8k.s page 78 + + + 3231 .LFB148: +1181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** +1183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief Starts the PWM signal generation in interrupt mode on the +1184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * complementary output. +1185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param htim TIM handle +1186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param Channel TIM Channel to be disabled +1187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * This parameter can be one of the following values: +1188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +1189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +1190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +1191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @retval HAL status +1192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ +1193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +1194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 3232 .loc 1 1194 1 + 3233 .cfi_startproc + 3234 @ args = 0, pretend = 0, frame = 16 + 3235 @ frame_needed = 1, uses_anonymous_args = 0 + 3236 0000 80B5 push {r7, lr} + 3237 .cfi_def_cfa_offset 8 + 3238 .cfi_offset 7, -8 + 3239 .cfi_offset 14, -4 + 3240 0002 84B0 sub sp, sp, #16 + 3241 .cfi_def_cfa_offset 24 + 3242 0004 00AF add r7, sp, #0 + 3243 .cfi_def_cfa_register 7 + 3244 0006 7860 str r0, [r7, #4] + 3245 0008 3960 str r1, [r7] +1195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 3246 .loc 1 1195 21 + 3247 000a 0023 movs r3, #0 + 3248 000c FB73 strb r3, [r7, #15] +1196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** uint32_t tmpsmcr; +1197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Check the parameters */ +1199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); +1200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Check the TIM complementary channel state */ +1202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + 3249 .loc 1 1202 46 + 3250 000e 3B68 ldr r3, [r7] + 3251 0010 002B cmp r3, #0 + 3252 0012 09D1 bne .L221 + 3253 .loc 1 1202 7 discriminator 1 + 3254 0014 7B68 ldr r3, [r7, #4] + 3255 0016 93F84430 ldrb r3, [r3, #68] + 3256 001a DBB2 uxtb r3, r3 + 3257 .loc 1 1202 46 discriminator 1 + 3258 001c 012B cmp r3, #1 + 3259 001e 14BF ite ne + 3260 0020 0123 movne r3, #1 + 3261 0022 0023 moveq r3, #0 + 3262 0024 DBB2 uxtb r3, r3 + 3263 0026 22E0 b .L222 + 3264 .L221: + 3265 .loc 1 1202 46 is_stmt 0 discriminator 2 + ARM GAS /tmp/ccxRWv8k.s page 79 + + + 3266 0028 3B68 ldr r3, [r7] + 3267 002a 042B cmp r3, #4 + 3268 002c 09D1 bne .L223 + 3269 .loc 1 1202 7 is_stmt 1 discriminator 4 + 3270 002e 7B68 ldr r3, [r7, #4] + 3271 0030 93F84530 ldrb r3, [r3, #69] + 3272 0034 DBB2 uxtb r3, r3 + 3273 .loc 1 1202 46 discriminator 4 + 3274 0036 012B cmp r3, #1 + 3275 0038 14BF ite ne + 3276 003a 0123 movne r3, #1 + 3277 003c 0023 moveq r3, #0 + 3278 003e DBB2 uxtb r3, r3 + 3279 0040 15E0 b .L222 + 3280 .L223: + 3281 .loc 1 1202 46 is_stmt 0 discriminator 5 + 3282 0042 3B68 ldr r3, [r7] + 3283 0044 082B cmp r3, #8 + 3284 0046 09D1 bne .L225 + 3285 .loc 1 1202 7 is_stmt 1 discriminator 7 + 3286 0048 7B68 ldr r3, [r7, #4] + 3287 004a 93F84630 ldrb r3, [r3, #70] + 3288 004e DBB2 uxtb r3, r3 + 3289 .loc 1 1202 46 discriminator 7 + 3290 0050 012B cmp r3, #1 + 3291 0052 14BF ite ne + 3292 0054 0123 movne r3, #1 + 3293 0056 0023 moveq r3, #0 + 3294 0058 DBB2 uxtb r3, r3 + 3295 005a 08E0 b .L222 + 3296 .L225: + 3297 .loc 1 1202 7 discriminator 8 + 3298 005c 7B68 ldr r3, [r7, #4] + 3299 005e 93F84730 ldrb r3, [r3, #71] + 3300 0062 DBB2 uxtb r3, r3 + 3301 .loc 1 1202 46 discriminator 8 + 3302 0064 012B cmp r3, #1 + 3303 0066 14BF ite ne + 3304 0068 0123 movne r3, #1 + 3305 006a 0023 moveq r3, #0 + 3306 006c DBB2 uxtb r3, r3 + 3307 .L222: + 3308 .loc 1 1202 6 discriminator 12 + 3309 006e 002B cmp r3, #0 + 3310 0070 01D0 beq .L227 +1203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +1204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return HAL_ERROR; + 3311 .loc 1 1204 12 + 3312 0072 0123 movs r3, #1 + 3313 0074 9AE0 b .L228 + 3314 .L227: +1205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +1206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Set the TIM complementary channel state */ +1208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + 3315 .loc 1 1208 3 + 3316 0076 3B68 ldr r3, [r7] + ARM GAS /tmp/ccxRWv8k.s page 80 + + + 3317 0078 002B cmp r3, #0 + 3318 007a 04D1 bne .L229 + 3319 .loc 1 1208 3 is_stmt 0 discriminator 1 + 3320 007c 7B68 ldr r3, [r7, #4] + 3321 007e 0222 movs r2, #2 + 3322 0080 83F84420 strb r2, [r3, #68] + 3323 0084 13E0 b .L230 + 3324 .L229: + 3325 .loc 1 1208 3 discriminator 2 + 3326 0086 3B68 ldr r3, [r7] + 3327 0088 042B cmp r3, #4 + 3328 008a 04D1 bne .L231 + 3329 .loc 1 1208 3 discriminator 3 + 3330 008c 7B68 ldr r3, [r7, #4] + 3331 008e 0222 movs r2, #2 + 3332 0090 83F84520 strb r2, [r3, #69] + 3333 0094 0BE0 b .L230 + 3334 .L231: + 3335 .loc 1 1208 3 discriminator 4 + 3336 0096 3B68 ldr r3, [r7] + 3337 0098 082B cmp r3, #8 + 3338 009a 04D1 bne .L233 + 3339 .loc 1 1208 3 discriminator 6 + 3340 009c 7B68 ldr r3, [r7, #4] + 3341 009e 0222 movs r2, #2 + 3342 00a0 83F84620 strb r2, [r3, #70] + 3343 00a4 03E0 b .L230 + 3344 .L233: + 3345 .loc 1 1208 3 discriminator 7 + 3346 00a6 7B68 ldr r3, [r7, #4] + 3347 00a8 0222 movs r2, #2 + 3348 00aa 83F84720 strb r2, [r3, #71] + 3349 .L230: +1209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** switch (Channel) + 3350 .loc 1 1210 3 is_stmt 1 + 3351 00ae 3B68 ldr r3, [r7] + 3352 00b0 082B cmp r3, #8 + 3353 00b2 1BD0 beq .L235 + 3354 00b4 3B68 ldr r3, [r7] + 3355 00b6 082B cmp r3, #8 + 3356 00b8 21D8 bhi .L236 + 3357 00ba 3B68 ldr r3, [r7] + 3358 00bc 002B cmp r3, #0 + 3359 00be 03D0 beq .L237 + 3360 00c0 3B68 ldr r3, [r7] + 3361 00c2 042B cmp r3, #4 + 3362 00c4 09D0 beq .L238 + 3363 00c6 1AE0 b .L236 + 3364 .L237: +1211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +1212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** case TIM_CHANNEL_1: +1213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +1214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the TIM Capture/Compare 1 interrupt */ +1215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + 3365 .loc 1 1215 7 + 3366 00c8 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/ccxRWv8k.s page 81 + + + 3367 00ca 1B68 ldr r3, [r3] + 3368 00cc DA68 ldr r2, [r3, #12] + 3369 00ce 7B68 ldr r3, [r7, #4] + 3370 00d0 1B68 ldr r3, [r3] + 3371 00d2 42F00202 orr r2, r2, #2 + 3372 00d6 DA60 str r2, [r3, #12] +1216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** break; + 3373 .loc 1 1216 7 + 3374 00d8 14E0 b .L239 + 3375 .L238: +1217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +1218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** case TIM_CHANNEL_2: +1220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +1221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the TIM Capture/Compare 2 interrupt */ +1222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + 3376 .loc 1 1222 7 + 3377 00da 7B68 ldr r3, [r7, #4] + 3378 00dc 1B68 ldr r3, [r3] + 3379 00de DA68 ldr r2, [r3, #12] + 3380 00e0 7B68 ldr r3, [r7, #4] + 3381 00e2 1B68 ldr r3, [r3] + 3382 00e4 42F00402 orr r2, r2, #4 + 3383 00e8 DA60 str r2, [r3, #12] +1223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** break; + 3384 .loc 1 1223 7 + 3385 00ea 0BE0 b .L239 + 3386 .L235: +1224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +1225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** case TIM_CHANNEL_3: +1227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +1228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the TIM Capture/Compare 3 interrupt */ +1229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + 3387 .loc 1 1229 7 + 3388 00ec 7B68 ldr r3, [r7, #4] + 3389 00ee 1B68 ldr r3, [r3] + 3390 00f0 DA68 ldr r2, [r3, #12] + 3391 00f2 7B68 ldr r3, [r7, #4] + 3392 00f4 1B68 ldr r3, [r3] + 3393 00f6 42F00802 orr r2, r2, #8 + 3394 00fa DA60 str r2, [r3, #12] +1230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** break; + 3395 .loc 1 1230 7 + 3396 00fc 02E0 b .L239 + 3397 .L236: +1231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +1232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** default: +1234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** status = HAL_ERROR; + 3398 .loc 1 1234 14 + 3399 00fe 0123 movs r3, #1 + 3400 0100 FB73 strb r3, [r7, #15] +1235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** break; + 3401 .loc 1 1235 7 + 3402 0102 00BF nop + 3403 .L239: + ARM GAS /tmp/ccxRWv8k.s page 82 + + +1236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +1237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (status == HAL_OK) + 3404 .loc 1 1238 6 + 3405 0104 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 3406 0106 002B cmp r3, #0 + 3407 0108 4FD1 bne .L240 +1239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +1240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the TIM Break interrupt */ +1241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + 3408 .loc 1 1241 5 + 3409 010a 7B68 ldr r3, [r7, #4] + 3410 010c 1B68 ldr r3, [r3] + 3411 010e DA68 ldr r2, [r3, #12] + 3412 0110 7B68 ldr r3, [r7, #4] + 3413 0112 1B68 ldr r3, [r3] + 3414 0114 42F08002 orr r2, r2, #128 + 3415 0118 DA60 str r2, [r3, #12] +1242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the complementary PWM output */ +1244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + 3416 .loc 1 1244 5 + 3417 011a 7B68 ldr r3, [r7, #4] + 3418 011c 1B68 ldr r3, [r3] + 3419 011e 0422 movs r2, #4 + 3420 0120 3968 ldr r1, [r7] + 3421 0122 1846 mov r0, r3 + 3422 0124 FFF7FEFF bl TIM_CCxNChannelCmd +1245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the Main Output */ +1247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_MOE_ENABLE(htim); + 3423 .loc 1 1247 5 + 3424 0128 7B68 ldr r3, [r7, #4] + 3425 012a 1B68 ldr r3, [r3] + 3426 012c 5A6C ldr r2, [r3, #68] + 3427 012e 7B68 ldr r3, [r7, #4] + 3428 0130 1B68 ldr r3, [r3] + 3429 0132 42F40042 orr r2, r2, #32768 + 3430 0136 5A64 str r2, [r3, #68] +1248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigge +1250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 3431 .loc 1 1250 9 + 3432 0138 7B68 ldr r3, [r7, #4] + 3433 013a 1B68 ldr r3, [r3] + 3434 .loc 1 1250 8 + 3435 013c 1D4A ldr r2, .L245 + 3436 013e 9342 cmp r3, r2 + 3437 0140 13D0 beq .L241 + 3438 .loc 1 1250 9 discriminator 1 + 3439 0142 7B68 ldr r3, [r7, #4] + 3440 0144 1B68 ldr r3, [r3] + 3441 0146 B3F1804F cmp r3, #1073741824 + 3442 014a 0ED0 beq .L241 + 3443 .loc 1 1250 9 is_stmt 0 discriminator 2 + 3444 014c 7B68 ldr r3, [r7, #4] + 3445 014e 1B68 ldr r3, [r3] + ARM GAS /tmp/ccxRWv8k.s page 83 + + + 3446 0150 194A ldr r2, .L245+4 + 3447 0152 9342 cmp r3, r2 + 3448 0154 09D0 beq .L241 + 3449 .loc 1 1250 9 discriminator 3 + 3450 0156 7B68 ldr r3, [r7, #4] + 3451 0158 1B68 ldr r3, [r3] + 3452 015a 184A ldr r2, .L245+8 + 3453 015c 9342 cmp r3, r2 + 3454 015e 04D0 beq .L241 + 3455 .loc 1 1250 9 discriminator 4 + 3456 0160 7B68 ldr r3, [r7, #4] + 3457 0162 1B68 ldr r3, [r3] + 3458 0164 164A ldr r2, .L245+12 + 3459 0166 9342 cmp r3, r2 + 3460 0168 15D1 bne .L242 + 3461 .L241: +1251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +1252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + 3462 .loc 1 1252 21 is_stmt 1 + 3463 016a 7B68 ldr r3, [r7, #4] + 3464 016c 1B68 ldr r3, [r3] + 3465 .loc 1 1252 31 + 3466 016e 9A68 ldr r2, [r3, #8] + 3467 .loc 1 1252 15 + 3468 0170 144B ldr r3, .L245+16 + 3469 0172 1340 ands r3, r3, r2 + 3470 0174 BB60 str r3, [r7, #8] +1253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 3471 .loc 1 1253 10 + 3472 0176 BB68 ldr r3, [r7, #8] + 3473 0178 062B cmp r3, #6 + 3474 017a 15D0 beq .L244 + 3475 .loc 1 1253 11 discriminator 1 + 3476 017c BB68 ldr r3, [r7, #8] + 3477 017e B3F5803F cmp r3, #65536 + 3478 0182 11D0 beq .L244 +1254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +1255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_ENABLE(htim); + 3479 .loc 1 1255 9 + 3480 0184 7B68 ldr r3, [r7, #4] + 3481 0186 1B68 ldr r3, [r3] + 3482 0188 1A68 ldr r2, [r3] + 3483 018a 7B68 ldr r3, [r7, #4] + 3484 018c 1B68 ldr r3, [r3] + 3485 018e 42F00102 orr r2, r2, #1 + 3486 0192 1A60 str r2, [r3] +1253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 3487 .loc 1 1253 10 + 3488 0194 08E0 b .L244 + 3489 .L242: +1256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +1257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +1258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** else +1259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +1260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_ENABLE(htim); + 3490 .loc 1 1260 7 + 3491 0196 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/ccxRWv8k.s page 84 + + + 3492 0198 1B68 ldr r3, [r3] + 3493 019a 1A68 ldr r2, [r3] + 3494 019c 7B68 ldr r3, [r7, #4] + 3495 019e 1B68 ldr r3, [r3] + 3496 01a0 42F00102 orr r2, r2, #1 + 3497 01a4 1A60 str r2, [r3] + 3498 01a6 00E0 b .L240 + 3499 .L244: +1253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 3500 .loc 1 1253 10 + 3501 01a8 00BF nop + 3502 .L240: +1261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +1262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +1263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Return function status */ +1265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return status; + 3503 .loc 1 1265 10 + 3504 01aa FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 3505 .L228: +1266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 3506 .loc 1 1266 1 + 3507 01ac 1846 mov r0, r3 + 3508 01ae 1037 adds r7, r7, #16 + 3509 .cfi_def_cfa_offset 8 + 3510 01b0 BD46 mov sp, r7 + 3511 .cfi_def_cfa_register 13 + 3512 @ sp needed + 3513 01b2 80BD pop {r7, pc} + 3514 .L246: + 3515 .align 2 + 3516 .L245: + 3517 01b4 002C0140 .word 1073818624 + 3518 01b8 00040040 .word 1073742848 + 3519 01bc 00080040 .word 1073743872 + 3520 01c0 00400140 .word 1073823744 + 3521 01c4 07000100 .word 65543 + 3522 .cfi_endproc + 3523 .LFE148: + 3525 .section .text.HAL_TIMEx_PWMN_Stop_IT,"ax",%progbits + 3526 .align 1 + 3527 .global HAL_TIMEx_PWMN_Stop_IT + 3528 .syntax unified + 3529 .thumb + 3530 .thumb_func + 3532 HAL_TIMEx_PWMN_Stop_IT: + 3533 .LFB149: +1267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** +1269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief Stops the PWM signal generation in interrupt mode on the +1270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * complementary output. +1271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param htim TIM handle +1272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param Channel TIM Channel to be disabled +1273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * This parameter can be one of the following values: +1274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +1275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +1276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected + ARM GAS /tmp/ccxRWv8k.s page 85 + + +1277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @retval HAL status +1278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ +1279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +1280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 3534 .loc 1 1280 1 + 3535 .cfi_startproc + 3536 @ args = 0, pretend = 0, frame = 16 + 3537 @ frame_needed = 1, uses_anonymous_args = 0 + 3538 0000 80B5 push {r7, lr} + 3539 .cfi_def_cfa_offset 8 + 3540 .cfi_offset 7, -8 + 3541 .cfi_offset 14, -4 + 3542 0002 84B0 sub sp, sp, #16 + 3543 .cfi_def_cfa_offset 24 + 3544 0004 00AF add r7, sp, #0 + 3545 .cfi_def_cfa_register 7 + 3546 0006 7860 str r0, [r7, #4] + 3547 0008 3960 str r1, [r7] +1281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 3548 .loc 1 1281 21 + 3549 000a 0023 movs r3, #0 + 3550 000c FB73 strb r3, [r7, #15] +1282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** uint32_t tmpccer; +1283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Check the parameters */ +1285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); +1286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** switch (Channel) + 3551 .loc 1 1287 3 + 3552 000e 3B68 ldr r3, [r7] + 3553 0010 082B cmp r3, #8 + 3554 0012 1BD0 beq .L248 + 3555 0014 3B68 ldr r3, [r7] + 3556 0016 082B cmp r3, #8 + 3557 0018 21D8 bhi .L249 + 3558 001a 3B68 ldr r3, [r7] + 3559 001c 002B cmp r3, #0 + 3560 001e 03D0 beq .L250 + 3561 0020 3B68 ldr r3, [r7] + 3562 0022 042B cmp r3, #4 + 3563 0024 09D0 beq .L251 + 3564 0026 1AE0 b .L249 + 3565 .L250: +1288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +1289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** case TIM_CHANNEL_1: +1290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +1291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable the TIM Capture/Compare 1 interrupt */ +1292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + 3566 .loc 1 1292 7 + 3567 0028 7B68 ldr r3, [r7, #4] + 3568 002a 1B68 ldr r3, [r3] + 3569 002c DA68 ldr r2, [r3, #12] + 3570 002e 7B68 ldr r3, [r7, #4] + 3571 0030 1B68 ldr r3, [r3] + 3572 0032 22F00202 bic r2, r2, #2 + 3573 0036 DA60 str r2, [r3, #12] +1293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** break; + ARM GAS /tmp/ccxRWv8k.s page 86 + + + 3574 .loc 1 1293 7 + 3575 0038 14E0 b .L252 + 3576 .L251: +1294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +1295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** case TIM_CHANNEL_2: +1297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +1298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable the TIM Capture/Compare 2 interrupt */ +1299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + 3577 .loc 1 1299 7 + 3578 003a 7B68 ldr r3, [r7, #4] + 3579 003c 1B68 ldr r3, [r3] + 3580 003e DA68 ldr r2, [r3, #12] + 3581 0040 7B68 ldr r3, [r7, #4] + 3582 0042 1B68 ldr r3, [r3] + 3583 0044 22F00402 bic r2, r2, #4 + 3584 0048 DA60 str r2, [r3, #12] +1300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** break; + 3585 .loc 1 1300 7 + 3586 004a 0BE0 b .L252 + 3587 .L248: +1301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +1302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** case TIM_CHANNEL_3: +1304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +1305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable the TIM Capture/Compare 3 interrupt */ +1306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + 3588 .loc 1 1306 7 + 3589 004c 7B68 ldr r3, [r7, #4] + 3590 004e 1B68 ldr r3, [r3] + 3591 0050 DA68 ldr r2, [r3, #12] + 3592 0052 7B68 ldr r3, [r7, #4] + 3593 0054 1B68 ldr r3, [r3] + 3594 0056 22F00802 bic r2, r2, #8 + 3595 005a DA60 str r2, [r3, #12] +1307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** break; + 3596 .loc 1 1307 7 + 3597 005c 02E0 b .L252 + 3598 .L249: +1308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +1309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** default: +1311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** status = HAL_ERROR; + 3599 .loc 1 1311 14 + 3600 005e 0123 movs r3, #1 + 3601 0060 FB73 strb r3, [r7, #15] +1312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** break; + 3602 .loc 1 1312 7 + 3603 0062 00BF nop + 3604 .L252: +1313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +1314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (status == HAL_OK) + 3605 .loc 1 1315 6 + 3606 0064 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 3607 0066 002B cmp r3, #0 + 3608 0068 64D1 bne .L253 + ARM GAS /tmp/ccxRWv8k.s page 87 + + +1316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +1317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable the complementary PWM output */ +1318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + 3609 .loc 1 1318 5 + 3610 006a 7B68 ldr r3, [r7, #4] + 3611 006c 1B68 ldr r3, [r3] + 3612 006e 0022 movs r2, #0 + 3613 0070 3968 ldr r1, [r7] + 3614 0072 1846 mov r0, r3 + 3615 0074 FFF7FEFF bl TIM_CCxNChannelCmd +1319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable the TIM Break interrupt (only if no more channel is active) */ +1321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** tmpccer = htim->Instance->CCER; + 3616 .loc 1 1321 19 + 3617 0078 7B68 ldr r3, [r7, #4] + 3618 007a 1B68 ldr r3, [r3] + 3619 .loc 1 1321 13 + 3620 007c 1B6A ldr r3, [r3, #32] + 3621 007e BB60 str r3, [r7, #8] +1322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + 3622 .loc 1 1322 18 + 3623 0080 BA68 ldr r2, [r7, #8] + 3624 0082 40F24443 movw r3, #1092 + 3625 0086 1340 ands r3, r3, r2 + 3626 .loc 1 1322 8 + 3627 0088 002B cmp r3, #0 + 3628 008a 07D1 bne .L254 +1323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +1324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + 3629 .loc 1 1324 7 + 3630 008c 7B68 ldr r3, [r7, #4] + 3631 008e 1B68 ldr r3, [r3] + 3632 0090 DA68 ldr r2, [r3, #12] + 3633 0092 7B68 ldr r3, [r7, #4] + 3634 0094 1B68 ldr r3, [r3] + 3635 0096 22F08002 bic r2, r2, #128 + 3636 009a DA60 str r2, [r3, #12] + 3637 .L254: +1325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +1326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable the Main Output */ +1328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_MOE_DISABLE(htim); + 3638 .loc 1 1328 5 + 3639 009c 7B68 ldr r3, [r7, #4] + 3640 009e 1B68 ldr r3, [r3] + 3641 00a0 1A6A ldr r2, [r3, #32] + 3642 00a2 41F21113 movw r3, #4369 + 3643 00a6 1340 ands r3, r3, r2 + 3644 00a8 002B cmp r3, #0 + 3645 00aa 0FD1 bne .L255 + 3646 .loc 1 1328 5 is_stmt 0 discriminator 1 + 3647 00ac 7B68 ldr r3, [r7, #4] + 3648 00ae 1B68 ldr r3, [r3] + 3649 00b0 1A6A ldr r2, [r3, #32] + 3650 00b2 40F24443 movw r3, #1092 + 3651 00b6 1340 ands r3, r3, r2 + 3652 00b8 002B cmp r3, #0 + ARM GAS /tmp/ccxRWv8k.s page 88 + + + 3653 00ba 07D1 bne .L255 + 3654 .loc 1 1328 5 discriminator 2 + 3655 00bc 7B68 ldr r3, [r7, #4] + 3656 00be 1B68 ldr r3, [r3] + 3657 00c0 5A6C ldr r2, [r3, #68] + 3658 00c2 7B68 ldr r3, [r7, #4] + 3659 00c4 1B68 ldr r3, [r3] + 3660 00c6 22F40042 bic r2, r2, #32768 + 3661 00ca 5A64 str r2, [r3, #68] + 3662 .L255: +1329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable the Peripheral */ +1331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_DISABLE(htim); + 3663 .loc 1 1331 5 is_stmt 1 + 3664 00cc 7B68 ldr r3, [r7, #4] + 3665 00ce 1B68 ldr r3, [r3] + 3666 00d0 1A6A ldr r2, [r3, #32] + 3667 00d2 41F21113 movw r3, #4369 + 3668 00d6 1340 ands r3, r3, r2 + 3669 00d8 002B cmp r3, #0 + 3670 00da 0FD1 bne .L256 + 3671 .loc 1 1331 5 is_stmt 0 discriminator 1 + 3672 00dc 7B68 ldr r3, [r7, #4] + 3673 00de 1B68 ldr r3, [r3] + 3674 00e0 1A6A ldr r2, [r3, #32] + 3675 00e2 40F24443 movw r3, #1092 + 3676 00e6 1340 ands r3, r3, r2 + 3677 00e8 002B cmp r3, #0 + 3678 00ea 07D1 bne .L256 + 3679 .loc 1 1331 5 discriminator 2 + 3680 00ec 7B68 ldr r3, [r7, #4] + 3681 00ee 1B68 ldr r3, [r3] + 3682 00f0 1A68 ldr r2, [r3] + 3683 00f2 7B68 ldr r3, [r7, #4] + 3684 00f4 1B68 ldr r3, [r3] + 3685 00f6 22F00102 bic r2, r2, #1 + 3686 00fa 1A60 str r2, [r3] + 3687 .L256: +1332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Set the TIM complementary channel state */ +1334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 3688 .loc 1 1334 5 is_stmt 1 + 3689 00fc 3B68 ldr r3, [r7] + 3690 00fe 002B cmp r3, #0 + 3691 0100 04D1 bne .L257 + 3692 .loc 1 1334 5 is_stmt 0 discriminator 1 + 3693 0102 7B68 ldr r3, [r7, #4] + 3694 0104 0122 movs r2, #1 + 3695 0106 83F84420 strb r2, [r3, #68] + 3696 010a 13E0 b .L253 + 3697 .L257: + 3698 .loc 1 1334 5 discriminator 2 + 3699 010c 3B68 ldr r3, [r7] + 3700 010e 042B cmp r3, #4 + 3701 0110 04D1 bne .L258 + 3702 .loc 1 1334 5 discriminator 3 + 3703 0112 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/ccxRWv8k.s page 89 + + + 3704 0114 0122 movs r2, #1 + 3705 0116 83F84520 strb r2, [r3, #69] + 3706 011a 0BE0 b .L253 + 3707 .L258: + 3708 .loc 1 1334 5 discriminator 4 + 3709 011c 3B68 ldr r3, [r7] + 3710 011e 082B cmp r3, #8 + 3711 0120 04D1 bne .L260 + 3712 .loc 1 1334 5 discriminator 6 + 3713 0122 7B68 ldr r3, [r7, #4] + 3714 0124 0122 movs r2, #1 + 3715 0126 83F84620 strb r2, [r3, #70] + 3716 012a 03E0 b .L253 + 3717 .L260: + 3718 .loc 1 1334 5 discriminator 7 + 3719 012c 7B68 ldr r3, [r7, #4] + 3720 012e 0122 movs r2, #1 + 3721 0130 83F84720 strb r2, [r3, #71] + 3722 .L253: +1335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +1336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Return function status */ +1338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return status; + 3723 .loc 1 1338 10 is_stmt 1 + 3724 0134 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 +1339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 3725 .loc 1 1339 1 + 3726 0136 1846 mov r0, r3 + 3727 0138 1037 adds r7, r7, #16 + 3728 .cfi_def_cfa_offset 8 + 3729 013a BD46 mov sp, r7 + 3730 .cfi_def_cfa_register 13 + 3731 @ sp needed + 3732 013c 80BD pop {r7, pc} + 3733 .cfi_endproc + 3734 .LFE149: + 3736 .section .text.HAL_TIMEx_PWMN_Start_DMA,"ax",%progbits + 3737 .align 1 + 3738 .global HAL_TIMEx_PWMN_Start_DMA + 3739 .syntax unified + 3740 .thumb + 3741 .thumb_func + 3743 HAL_TIMEx_PWMN_Start_DMA: + 3744 .LFB150: +1340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** +1342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief Starts the TIM PWM signal generation in DMA mode on the +1343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * complementary output +1344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param htim TIM handle +1345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param Channel TIM Channel to be enabled +1346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * This parameter can be one of the following values: +1347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +1348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +1349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +1350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param pData The source Buffer address. +1351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param Length The length of data to be transferred from memory to TIM peripheral +1352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @retval HAL status + ARM GAS /tmp/ccxRWv8k.s page 90 + + +1353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ +1354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_ +1355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** uint16_t Length) +1356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 3745 .loc 1 1356 1 + 3746 .cfi_startproc + 3747 @ args = 0, pretend = 0, frame = 24 + 3748 @ frame_needed = 1, uses_anonymous_args = 0 + 3749 0000 80B5 push {r7, lr} + 3750 .cfi_def_cfa_offset 8 + 3751 .cfi_offset 7, -8 + 3752 .cfi_offset 14, -4 + 3753 0002 86B0 sub sp, sp, #24 + 3754 .cfi_def_cfa_offset 32 + 3755 0004 00AF add r7, sp, #0 + 3756 .cfi_def_cfa_register 7 + 3757 0006 F860 str r0, [r7, #12] + 3758 0008 B960 str r1, [r7, #8] + 3759 000a 7A60 str r2, [r7, #4] + 3760 000c 7B80 strh r3, [r7, #2] @ movhi +1357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 3761 .loc 1 1357 21 + 3762 000e 0023 movs r3, #0 + 3763 0010 FB75 strb r3, [r7, #23] +1358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** uint32_t tmpsmcr; +1359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Check the parameters */ +1361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); +1362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Set the TIM complementary channel state */ +1364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + 3764 .loc 1 1364 46 + 3765 0012 BB68 ldr r3, [r7, #8] + 3766 0014 002B cmp r3, #0 + 3767 0016 09D1 bne .L264 + 3768 .loc 1 1364 7 discriminator 1 + 3769 0018 FB68 ldr r3, [r7, #12] + 3770 001a 93F84430 ldrb r3, [r3, #68] + 3771 001e DBB2 uxtb r3, r3 + 3772 .loc 1 1364 46 discriminator 1 + 3773 0020 022B cmp r3, #2 + 3774 0022 0CBF ite eq + 3775 0024 0123 moveq r3, #1 + 3776 0026 0023 movne r3, #0 + 3777 0028 DBB2 uxtb r3, r3 + 3778 002a 22E0 b .L265 + 3779 .L264: + 3780 .loc 1 1364 46 is_stmt 0 discriminator 2 + 3781 002c BB68 ldr r3, [r7, #8] + 3782 002e 042B cmp r3, #4 + 3783 0030 09D1 bne .L266 + 3784 .loc 1 1364 7 is_stmt 1 discriminator 4 + 3785 0032 FB68 ldr r3, [r7, #12] + 3786 0034 93F84530 ldrb r3, [r3, #69] + 3787 0038 DBB2 uxtb r3, r3 + 3788 .loc 1 1364 46 discriminator 4 + 3789 003a 022B cmp r3, #2 + ARM GAS /tmp/ccxRWv8k.s page 91 + + + 3790 003c 0CBF ite eq + 3791 003e 0123 moveq r3, #1 + 3792 0040 0023 movne r3, #0 + 3793 0042 DBB2 uxtb r3, r3 + 3794 0044 15E0 b .L265 + 3795 .L266: + 3796 .loc 1 1364 46 is_stmt 0 discriminator 5 + 3797 0046 BB68 ldr r3, [r7, #8] + 3798 0048 082B cmp r3, #8 + 3799 004a 09D1 bne .L268 + 3800 .loc 1 1364 7 is_stmt 1 discriminator 7 + 3801 004c FB68 ldr r3, [r7, #12] + 3802 004e 93F84630 ldrb r3, [r3, #70] + 3803 0052 DBB2 uxtb r3, r3 + 3804 .loc 1 1364 46 discriminator 7 + 3805 0054 022B cmp r3, #2 + 3806 0056 0CBF ite eq + 3807 0058 0123 moveq r3, #1 + 3808 005a 0023 movne r3, #0 + 3809 005c DBB2 uxtb r3, r3 + 3810 005e 08E0 b .L265 + 3811 .L268: + 3812 .loc 1 1364 7 discriminator 8 + 3813 0060 FB68 ldr r3, [r7, #12] + 3814 0062 93F84730 ldrb r3, [r3, #71] + 3815 0066 DBB2 uxtb r3, r3 + 3816 .loc 1 1364 46 discriminator 8 + 3817 0068 022B cmp r3, #2 + 3818 006a 0CBF ite eq + 3819 006c 0123 moveq r3, #1 + 3820 006e 0023 movne r3, #0 + 3821 0070 DBB2 uxtb r3, r3 + 3822 .L265: + 3823 .loc 1 1364 6 discriminator 12 + 3824 0072 002B cmp r3, #0 + 3825 0074 01D0 beq .L270 +1365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +1366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return HAL_BUSY; + 3826 .loc 1 1366 12 + 3827 0076 0223 movs r3, #2 + 3828 0078 20E1 b .L271 + 3829 .L270: +1367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +1368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + 3830 .loc 1 1368 51 + 3831 007a BB68 ldr r3, [r7, #8] + 3832 007c 002B cmp r3, #0 + 3833 007e 09D1 bne .L272 + 3834 .loc 1 1368 12 discriminator 1 + 3835 0080 FB68 ldr r3, [r7, #12] + 3836 0082 93F84430 ldrb r3, [r3, #68] + 3837 0086 DBB2 uxtb r3, r3 + 3838 .loc 1 1368 51 discriminator 1 + 3839 0088 012B cmp r3, #1 + 3840 008a 0CBF ite eq + 3841 008c 0123 moveq r3, #1 + 3842 008e 0023 movne r3, #0 + ARM GAS /tmp/ccxRWv8k.s page 92 + + + 3843 0090 DBB2 uxtb r3, r3 + 3844 0092 22E0 b .L273 + 3845 .L272: + 3846 .loc 1 1368 51 is_stmt 0 discriminator 2 + 3847 0094 BB68 ldr r3, [r7, #8] + 3848 0096 042B cmp r3, #4 + 3849 0098 09D1 bne .L274 + 3850 .loc 1 1368 12 is_stmt 1 discriminator 4 + 3851 009a FB68 ldr r3, [r7, #12] + 3852 009c 93F84530 ldrb r3, [r3, #69] + 3853 00a0 DBB2 uxtb r3, r3 + 3854 .loc 1 1368 51 discriminator 4 + 3855 00a2 012B cmp r3, #1 + 3856 00a4 0CBF ite eq + 3857 00a6 0123 moveq r3, #1 + 3858 00a8 0023 movne r3, #0 + 3859 00aa DBB2 uxtb r3, r3 + 3860 00ac 15E0 b .L273 + 3861 .L274: + 3862 .loc 1 1368 51 is_stmt 0 discriminator 5 + 3863 00ae BB68 ldr r3, [r7, #8] + 3864 00b0 082B cmp r3, #8 + 3865 00b2 09D1 bne .L276 + 3866 .loc 1 1368 12 is_stmt 1 discriminator 7 + 3867 00b4 FB68 ldr r3, [r7, #12] + 3868 00b6 93F84630 ldrb r3, [r3, #70] + 3869 00ba DBB2 uxtb r3, r3 + 3870 .loc 1 1368 51 discriminator 7 + 3871 00bc 012B cmp r3, #1 + 3872 00be 0CBF ite eq + 3873 00c0 0123 moveq r3, #1 + 3874 00c2 0023 movne r3, #0 + 3875 00c4 DBB2 uxtb r3, r3 + 3876 00c6 08E0 b .L273 + 3877 .L276: + 3878 .loc 1 1368 12 discriminator 8 + 3879 00c8 FB68 ldr r3, [r7, #12] + 3880 00ca 93F84730 ldrb r3, [r3, #71] + 3881 00ce DBB2 uxtb r3, r3 + 3882 .loc 1 1368 51 discriminator 8 + 3883 00d0 012B cmp r3, #1 + 3884 00d2 0CBF ite eq + 3885 00d4 0123 moveq r3, #1 + 3886 00d6 0023 movne r3, #0 + 3887 00d8 DBB2 uxtb r3, r3 + 3888 .L273: + 3889 .loc 1 1368 11 discriminator 12 + 3890 00da 002B cmp r3, #0 + 3891 00dc 24D0 beq .L278 +1369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +1370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if ((pData == NULL) || (Length == 0U)) + 3892 .loc 1 1370 8 + 3893 00de 7B68 ldr r3, [r7, #4] + 3894 00e0 002B cmp r3, #0 + 3895 00e2 02D0 beq .L279 + 3896 .loc 1 1370 25 discriminator 1 + 3897 00e4 7B88 ldrh r3, [r7, #2] + ARM GAS /tmp/ccxRWv8k.s page 93 + + + 3898 00e6 002B cmp r3, #0 + 3899 00e8 01D1 bne .L280 + 3900 .L279: +1371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +1372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return HAL_ERROR; + 3901 .loc 1 1372 14 + 3902 00ea 0123 movs r3, #1 + 3903 00ec E6E0 b .L271 + 3904 .L280: +1373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +1374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** else +1375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +1376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + 3905 .loc 1 1376 7 + 3906 00ee BB68 ldr r3, [r7, #8] + 3907 00f0 002B cmp r3, #0 + 3908 00f2 04D1 bne .L281 + 3909 .loc 1 1376 7 is_stmt 0 discriminator 1 + 3910 00f4 FB68 ldr r3, [r7, #12] + 3911 00f6 0222 movs r2, #2 + 3912 00f8 83F84420 strb r2, [r3, #68] + 3913 00fc 16E0 b .L282 + 3914 .L281: + 3915 .loc 1 1376 7 discriminator 2 + 3916 00fe BB68 ldr r3, [r7, #8] + 3917 0100 042B cmp r3, #4 + 3918 0102 04D1 bne .L283 + 3919 .loc 1 1376 7 discriminator 3 + 3920 0104 FB68 ldr r3, [r7, #12] + 3921 0106 0222 movs r2, #2 + 3922 0108 83F84520 strb r2, [r3, #69] + 3923 .loc 1 1376 7 discriminator 10 + 3924 010c 0EE0 b .L282 + 3925 .L283: + 3926 .loc 1 1376 7 discriminator 4 + 3927 010e BB68 ldr r3, [r7, #8] + 3928 0110 082B cmp r3, #8 + 3929 0112 04D1 bne .L285 + 3930 .loc 1 1376 7 discriminator 6 + 3931 0114 FB68 ldr r3, [r7, #12] + 3932 0116 0222 movs r2, #2 + 3933 0118 83F84620 strb r2, [r3, #70] + 3934 .loc 1 1376 7 discriminator 10 + 3935 011c 06E0 b .L282 + 3936 .L285: + 3937 .loc 1 1376 7 discriminator 7 + 3938 011e FB68 ldr r3, [r7, #12] + 3939 0120 0222 movs r2, #2 + 3940 0122 83F84720 strb r2, [r3, #71] + 3941 0126 01E0 b .L282 + 3942 .L278: +1377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +1378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +1379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** else +1380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +1381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return HAL_ERROR; + 3943 .loc 1 1381 12 is_stmt 1 + ARM GAS /tmp/ccxRWv8k.s page 94 + + + 3944 0128 0123 movs r3, #1 + 3945 012a C7E0 b .L271 + 3946 .L282: +1382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +1383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** switch (Channel) + 3947 .loc 1 1384 3 + 3948 012c BB68 ldr r3, [r7, #8] + 3949 012e 082B cmp r3, #8 + 3950 0130 51D0 beq .L287 + 3951 0132 BB68 ldr r3, [r7, #8] + 3952 0134 082B cmp r3, #8 + 3953 0136 72D8 bhi .L288 + 3954 0138 BB68 ldr r3, [r7, #8] + 3955 013a 002B cmp r3, #0 + 3956 013c 03D0 beq .L289 + 3957 013e BB68 ldr r3, [r7, #8] + 3958 0140 042B cmp r3, #4 + 3959 0142 24D0 beq .L290 + 3960 0144 6BE0 b .L288 + 3961 .L289: +1385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +1386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** case TIM_CHANNEL_1: +1387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +1388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Set the DMA compare callbacks */ +1389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; + 3962 .loc 1 1389 17 + 3963 0146 FB68 ldr r3, [r7, #12] + 3964 0148 5B6A ldr r3, [r3, #36] + 3965 .loc 1 1389 52 + 3966 014a 5E4A ldr r2, .L300 + 3967 014c 9A62 str r2, [r3, #40] +1390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 3968 .loc 1 1390 17 + 3969 014e FB68 ldr r3, [r7, #12] + 3970 0150 5B6A ldr r3, [r3, #36] + 3971 .loc 1 1390 56 + 3972 0152 5D4A ldr r2, .L300+4 + 3973 0154 DA62 str r2, [r3, #44] +1391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Set the DMA error callback */ +1393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; + 3974 .loc 1 1393 17 + 3975 0156 FB68 ldr r3, [r7, #12] + 3976 0158 5B6A ldr r3, [r3, #36] + 3977 .loc 1 1393 53 + 3978 015a 5C4A ldr r2, .L300+8 + 3979 015c 1A63 str r2, [r3, #48] +1394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the DMA channel */ +1396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance-> + 3980 .loc 1 1396 11 + 3981 015e FB68 ldr r3, [r7, #12] + 3982 0160 586A ldr r0, [r3, #36] + 3983 0162 7968 ldr r1, [r7, #4] + 3984 .loc 1 1396 88 + 3985 0164 FB68 ldr r3, [r7, #12] + ARM GAS /tmp/ccxRWv8k.s page 95 + + + 3986 0166 1B68 ldr r3, [r3] + 3987 .loc 1 1396 83 + 3988 0168 3433 adds r3, r3, #52 + 3989 .loc 1 1396 11 + 3990 016a 1A46 mov r2, r3 + 3991 016c 7B88 ldrh r3, [r7, #2] + 3992 016e FFF7FEFF bl HAL_DMA_Start_IT + 3993 0172 0346 mov r3, r0 + 3994 .loc 1 1396 10 discriminator 1 + 3995 0174 002B cmp r3, #0 + 3996 0176 01D0 beq .L291 +1397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** Length) != HAL_OK) +1398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +1399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Return error status */ +1400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return HAL_ERROR; + 3997 .loc 1 1400 16 + 3998 0178 0123 movs r3, #1 + 3999 017a 9FE0 b .L271 + 4000 .L291: +1401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +1402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the TIM Capture/Compare 1 DMA request */ +1403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + 4001 .loc 1 1403 7 + 4002 017c FB68 ldr r3, [r7, #12] + 4003 017e 1B68 ldr r3, [r3] + 4004 0180 DA68 ldr r2, [r3, #12] + 4005 0182 FB68 ldr r3, [r7, #12] + 4006 0184 1B68 ldr r3, [r3] + 4007 0186 42F40072 orr r2, r2, #512 + 4008 018a DA60 str r2, [r3, #12] +1404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** break; + 4009 .loc 1 1404 7 + 4010 018c 4AE0 b .L292 + 4011 .L290: +1405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +1406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** case TIM_CHANNEL_2: +1408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +1409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Set the DMA compare callbacks */ +1410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; + 4012 .loc 1 1410 17 + 4013 018e FB68 ldr r3, [r7, #12] + 4014 0190 9B6A ldr r3, [r3, #40] + 4015 .loc 1 1410 52 + 4016 0192 4C4A ldr r2, .L300 + 4017 0194 9A62 str r2, [r3, #40] +1411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 4018 .loc 1 1411 17 + 4019 0196 FB68 ldr r3, [r7, #12] + 4020 0198 9B6A ldr r3, [r3, #40] + 4021 .loc 1 1411 56 + 4022 019a 4B4A ldr r2, .L300+4 + 4023 019c DA62 str r2, [r3, #44] +1412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Set the DMA error callback */ +1414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; + 4024 .loc 1 1414 17 + ARM GAS /tmp/ccxRWv8k.s page 96 + + + 4025 019e FB68 ldr r3, [r7, #12] + 4026 01a0 9B6A ldr r3, [r3, #40] + 4027 .loc 1 1414 53 + 4028 01a2 4A4A ldr r2, .L300+8 + 4029 01a4 1A63 str r2, [r3, #48] +1415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the DMA channel */ +1417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance-> + 4030 .loc 1 1417 11 + 4031 01a6 FB68 ldr r3, [r7, #12] + 4032 01a8 986A ldr r0, [r3, #40] + 4033 01aa 7968 ldr r1, [r7, #4] + 4034 .loc 1 1417 88 + 4035 01ac FB68 ldr r3, [r7, #12] + 4036 01ae 1B68 ldr r3, [r3] + 4037 .loc 1 1417 83 + 4038 01b0 3833 adds r3, r3, #56 + 4039 .loc 1 1417 11 + 4040 01b2 1A46 mov r2, r3 + 4041 01b4 7B88 ldrh r3, [r7, #2] + 4042 01b6 FFF7FEFF bl HAL_DMA_Start_IT + 4043 01ba 0346 mov r3, r0 + 4044 .loc 1 1417 10 discriminator 1 + 4045 01bc 002B cmp r3, #0 + 4046 01be 01D0 beq .L293 +1418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** Length) != HAL_OK) +1419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +1420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Return error status */ +1421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return HAL_ERROR; + 4047 .loc 1 1421 16 + 4048 01c0 0123 movs r3, #1 + 4049 01c2 7BE0 b .L271 + 4050 .L293: +1422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +1423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the TIM Capture/Compare 2 DMA request */ +1424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + 4051 .loc 1 1424 7 + 4052 01c4 FB68 ldr r3, [r7, #12] + 4053 01c6 1B68 ldr r3, [r3] + 4054 01c8 DA68 ldr r2, [r3, #12] + 4055 01ca FB68 ldr r3, [r7, #12] + 4056 01cc 1B68 ldr r3, [r3] + 4057 01ce 42F48062 orr r2, r2, #1024 + 4058 01d2 DA60 str r2, [r3, #12] +1425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** break; + 4059 .loc 1 1425 7 + 4060 01d4 26E0 b .L292 + 4061 .L287: +1426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +1427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** case TIM_CHANNEL_3: +1429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +1430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Set the DMA compare callbacks */ +1431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; + 4062 .loc 1 1431 17 + 4063 01d6 FB68 ldr r3, [r7, #12] + 4064 01d8 DB6A ldr r3, [r3, #44] + ARM GAS /tmp/ccxRWv8k.s page 97 + + + 4065 .loc 1 1431 52 + 4066 01da 3A4A ldr r2, .L300 + 4067 01dc 9A62 str r2, [r3, #40] +1432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + 4068 .loc 1 1432 17 + 4069 01de FB68 ldr r3, [r7, #12] + 4070 01e0 DB6A ldr r3, [r3, #44] + 4071 .loc 1 1432 56 + 4072 01e2 394A ldr r2, .L300+4 + 4073 01e4 DA62 str r2, [r3, #44] +1433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Set the DMA error callback */ +1435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; + 4074 .loc 1 1435 17 + 4075 01e6 FB68 ldr r3, [r7, #12] + 4076 01e8 DB6A ldr r3, [r3, #44] + 4077 .loc 1 1435 53 + 4078 01ea 384A ldr r2, .L300+8 + 4079 01ec 1A63 str r2, [r3, #48] +1436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the DMA channel */ +1438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance-> + 4080 .loc 1 1438 11 + 4081 01ee FB68 ldr r3, [r7, #12] + 4082 01f0 D86A ldr r0, [r3, #44] + 4083 01f2 7968 ldr r1, [r7, #4] + 4084 .loc 1 1438 88 + 4085 01f4 FB68 ldr r3, [r7, #12] + 4086 01f6 1B68 ldr r3, [r3] + 4087 .loc 1 1438 83 + 4088 01f8 3C33 adds r3, r3, #60 + 4089 .loc 1 1438 11 + 4090 01fa 1A46 mov r2, r3 + 4091 01fc 7B88 ldrh r3, [r7, #2] + 4092 01fe FFF7FEFF bl HAL_DMA_Start_IT + 4093 0202 0346 mov r3, r0 + 4094 .loc 1 1438 10 discriminator 1 + 4095 0204 002B cmp r3, #0 + 4096 0206 01D0 beq .L294 +1439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** Length) != HAL_OK) +1440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +1441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Return error status */ +1442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return HAL_ERROR; + 4097 .loc 1 1442 16 + 4098 0208 0123 movs r3, #1 + 4099 020a 57E0 b .L271 + 4100 .L294: +1443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +1444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the TIM Capture/Compare 3 DMA request */ +1445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + 4101 .loc 1 1445 7 + 4102 020c FB68 ldr r3, [r7, #12] + 4103 020e 1B68 ldr r3, [r3] + 4104 0210 DA68 ldr r2, [r3, #12] + 4105 0212 FB68 ldr r3, [r7, #12] + 4106 0214 1B68 ldr r3, [r3] + 4107 0216 42F40062 orr r2, r2, #2048 + ARM GAS /tmp/ccxRWv8k.s page 98 + + + 4108 021a DA60 str r2, [r3, #12] +1446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** break; + 4109 .loc 1 1446 7 + 4110 021c 02E0 b .L292 + 4111 .L288: +1447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +1448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** default: +1450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** status = HAL_ERROR; + 4112 .loc 1 1450 14 + 4113 021e 0123 movs r3, #1 + 4114 0220 FB75 strb r3, [r7, #23] +1451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** break; + 4115 .loc 1 1451 7 + 4116 0222 00BF nop + 4117 .L292: +1452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +1453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (status == HAL_OK) + 4118 .loc 1 1454 6 + 4119 0224 FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 4120 0226 002B cmp r3, #0 + 4121 0228 47D1 bne .L295 +1455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +1456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the complementary PWM output */ +1457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + 4122 .loc 1 1457 5 + 4123 022a FB68 ldr r3, [r7, #12] + 4124 022c 1B68 ldr r3, [r3] + 4125 022e 0422 movs r2, #4 + 4126 0230 B968 ldr r1, [r7, #8] + 4127 0232 1846 mov r0, r3 + 4128 0234 FFF7FEFF bl TIM_CCxNChannelCmd +1458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the Main Output */ +1460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_MOE_ENABLE(htim); + 4129 .loc 1 1460 5 + 4130 0238 FB68 ldr r3, [r7, #12] + 4131 023a 1B68 ldr r3, [r3] + 4132 023c 5A6C ldr r2, [r3, #68] + 4133 023e FB68 ldr r3, [r7, #12] + 4134 0240 1B68 ldr r3, [r3] + 4135 0242 42F40042 orr r2, r2, #32768 + 4136 0246 5A64 str r2, [r3, #68] +1461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigge +1463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 4137 .loc 1 1463 9 + 4138 0248 FB68 ldr r3, [r7, #12] + 4139 024a 1B68 ldr r3, [r3] + 4140 .loc 1 1463 8 + 4141 024c 204A ldr r2, .L300+12 + 4142 024e 9342 cmp r3, r2 + 4143 0250 13D0 beq .L296 + 4144 .loc 1 1463 9 discriminator 1 + 4145 0252 FB68 ldr r3, [r7, #12] + 4146 0254 1B68 ldr r3, [r3] + ARM GAS /tmp/ccxRWv8k.s page 99 + + + 4147 0256 B3F1804F cmp r3, #1073741824 + 4148 025a 0ED0 beq .L296 + 4149 .loc 1 1463 9 is_stmt 0 discriminator 2 + 4150 025c FB68 ldr r3, [r7, #12] + 4151 025e 1B68 ldr r3, [r3] + 4152 0260 1C4A ldr r2, .L300+16 + 4153 0262 9342 cmp r3, r2 + 4154 0264 09D0 beq .L296 + 4155 .loc 1 1463 9 discriminator 3 + 4156 0266 FB68 ldr r3, [r7, #12] + 4157 0268 1B68 ldr r3, [r3] + 4158 026a 1B4A ldr r2, .L300+20 + 4159 026c 9342 cmp r3, r2 + 4160 026e 04D0 beq .L296 + 4161 .loc 1 1463 9 discriminator 4 + 4162 0270 FB68 ldr r3, [r7, #12] + 4163 0272 1B68 ldr r3, [r3] + 4164 0274 194A ldr r2, .L300+24 + 4165 0276 9342 cmp r3, r2 + 4166 0278 15D1 bne .L297 + 4167 .L296: +1464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +1465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + 4168 .loc 1 1465 21 is_stmt 1 + 4169 027a FB68 ldr r3, [r7, #12] + 4170 027c 1B68 ldr r3, [r3] + 4171 .loc 1 1465 31 + 4172 027e 9A68 ldr r2, [r3, #8] + 4173 .loc 1 1465 15 + 4174 0280 174B ldr r3, .L300+28 + 4175 0282 1340 ands r3, r3, r2 + 4176 0284 3B61 str r3, [r7, #16] +1466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 4177 .loc 1 1466 10 + 4178 0286 3B69 ldr r3, [r7, #16] + 4179 0288 062B cmp r3, #6 + 4180 028a 15D0 beq .L299 + 4181 .loc 1 1466 11 discriminator 1 + 4182 028c 3B69 ldr r3, [r7, #16] + 4183 028e B3F5803F cmp r3, #65536 + 4184 0292 11D0 beq .L299 +1467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +1468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_ENABLE(htim); + 4185 .loc 1 1468 9 + 4186 0294 FB68 ldr r3, [r7, #12] + 4187 0296 1B68 ldr r3, [r3] + 4188 0298 1A68 ldr r2, [r3] + 4189 029a FB68 ldr r3, [r7, #12] + 4190 029c 1B68 ldr r3, [r3] + 4191 029e 42F00102 orr r2, r2, #1 + 4192 02a2 1A60 str r2, [r3] +1466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + 4193 .loc 1 1466 10 + 4194 02a4 08E0 b .L299 + 4195 .L297: +1469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +1470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + ARM GAS /tmp/ccxRWv8k.s page 100 + + +1471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** else +1472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +1473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_ENABLE(htim); + 4196 .loc 1 1473 7 + 4197 02a6 FB68 ldr r3, [r7, #12] + 4198 02a8 1B68 ldr r3, [r3] + 4199 02aa 1A68 ldr r2, [r3] + 4200 02ac FB68 ldr r3, [r7, #12] + 4201 02ae 1B68 ldr r3, [r3] + 4202 02b0 42F00102 orr r2, r2, #1 + 4203 02b4 1A60 str r2, [r3] + 4204 02b6 00E0 b .L295 + 4205 .L299: +1466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 4206 .loc 1 1466 10 + 4207 02b8 00BF nop + 4208 .L295: +1474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +1475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +1476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Return function status */ +1478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return status; + 4209 .loc 1 1478 10 + 4210 02ba FB7D ldrb r3, [r7, #23] @ zero_extendqisi2 + 4211 .L271: +1479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 4212 .loc 1 1479 1 + 4213 02bc 1846 mov r0, r3 + 4214 02be 1837 adds r7, r7, #24 + 4215 .cfi_def_cfa_offset 8 + 4216 02c0 BD46 mov sp, r7 + 4217 .cfi_def_cfa_register 13 + 4218 @ sp needed + 4219 02c2 80BD pop {r7, pc} + 4220 .L301: + 4221 .align 2 + 4222 .L300: + 4223 02c4 00000000 .word TIM_DMADelayPulseNCplt + 4224 02c8 00000000 .word TIM_DMADelayPulseHalfCplt + 4225 02cc 00000000 .word TIM_DMAErrorCCxN + 4226 02d0 002C0140 .word 1073818624 + 4227 02d4 00040040 .word 1073742848 + 4228 02d8 00080040 .word 1073743872 + 4229 02dc 00400140 .word 1073823744 + 4230 02e0 07000100 .word 65543 + 4231 .cfi_endproc + 4232 .LFE150: + 4234 .section .text.HAL_TIMEx_PWMN_Stop_DMA,"ax",%progbits + 4235 .align 1 + 4236 .global HAL_TIMEx_PWMN_Stop_DMA + 4237 .syntax unified + 4238 .thumb + 4239 .thumb_func + 4241 HAL_TIMEx_PWMN_Stop_DMA: + 4242 .LFB151: +1480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** + ARM GAS /tmp/ccxRWv8k.s page 101 + + +1482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief Stops the TIM PWM signal generation in DMA mode on the complementary +1483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * output +1484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param htim TIM handle +1485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param Channel TIM Channel to be disabled +1486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * This parameter can be one of the following values: +1487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +1488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +1489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 selected +1490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @retval HAL status +1491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ +1492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +1493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 4243 .loc 1 1493 1 + 4244 .cfi_startproc + 4245 @ args = 0, pretend = 0, frame = 16 + 4246 @ frame_needed = 1, uses_anonymous_args = 0 + 4247 0000 80B5 push {r7, lr} + 4248 .cfi_def_cfa_offset 8 + 4249 .cfi_offset 7, -8 + 4250 .cfi_offset 14, -4 + 4251 0002 84B0 sub sp, sp, #16 + 4252 .cfi_def_cfa_offset 24 + 4253 0004 00AF add r7, sp, #0 + 4254 .cfi_def_cfa_register 7 + 4255 0006 7860 str r0, [r7, #4] + 4256 0008 3960 str r1, [r7] +1494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_StatusTypeDef status = HAL_OK; + 4257 .loc 1 1494 21 + 4258 000a 0023 movs r3, #0 + 4259 000c FB73 strb r3, [r7, #15] +1495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Check the parameters */ +1497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); +1498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** switch (Channel) + 4260 .loc 1 1499 3 + 4261 000e 3B68 ldr r3, [r7] + 4262 0010 082B cmp r3, #8 + 4263 0012 25D0 beq .L303 + 4264 0014 3B68 ldr r3, [r7] + 4265 0016 082B cmp r3, #8 + 4266 0018 30D8 bhi .L304 + 4267 001a 3B68 ldr r3, [r7] + 4268 001c 002B cmp r3, #0 + 4269 001e 03D0 beq .L305 + 4270 0020 3B68 ldr r3, [r7] + 4271 0022 042B cmp r3, #4 + 4272 0024 0ED0 beq .L306 + 4273 0026 29E0 b .L304 + 4274 .L305: +1500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +1501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** case TIM_CHANNEL_1: +1502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +1503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable the TIM Capture/Compare 1 DMA request */ +1504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + 4275 .loc 1 1504 7 + 4276 0028 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/ccxRWv8k.s page 102 + + + 4277 002a 1B68 ldr r3, [r3] + 4278 002c DA68 ldr r2, [r3, #12] + 4279 002e 7B68 ldr r3, [r7, #4] + 4280 0030 1B68 ldr r3, [r3] + 4281 0032 22F40072 bic r2, r2, #512 + 4282 0036 DA60 str r2, [r3, #12] +1505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + 4283 .loc 1 1505 13 + 4284 0038 7B68 ldr r3, [r7, #4] + 4285 003a 5B6A ldr r3, [r3, #36] + 4286 003c 1846 mov r0, r3 + 4287 003e FFF7FEFF bl HAL_DMA_Abort_IT +1506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** break; + 4288 .loc 1 1506 7 + 4289 0042 1EE0 b .L307 + 4290 .L306: +1507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +1508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** case TIM_CHANNEL_2: +1510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +1511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable the TIM Capture/Compare 2 DMA request */ +1512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + 4291 .loc 1 1512 7 + 4292 0044 7B68 ldr r3, [r7, #4] + 4293 0046 1B68 ldr r3, [r3] + 4294 0048 DA68 ldr r2, [r3, #12] + 4295 004a 7B68 ldr r3, [r7, #4] + 4296 004c 1B68 ldr r3, [r3] + 4297 004e 22F48062 bic r2, r2, #1024 + 4298 0052 DA60 str r2, [r3, #12] +1513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + 4299 .loc 1 1513 13 + 4300 0054 7B68 ldr r3, [r7, #4] + 4301 0056 9B6A ldr r3, [r3, #40] + 4302 0058 1846 mov r0, r3 + 4303 005a FFF7FEFF bl HAL_DMA_Abort_IT +1514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** break; + 4304 .loc 1 1514 7 + 4305 005e 10E0 b .L307 + 4306 .L303: +1515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +1516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** case TIM_CHANNEL_3: +1518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +1519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable the TIM Capture/Compare 3 DMA request */ +1520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + 4307 .loc 1 1520 7 + 4308 0060 7B68 ldr r3, [r7, #4] + 4309 0062 1B68 ldr r3, [r3] + 4310 0064 DA68 ldr r2, [r3, #12] + 4311 0066 7B68 ldr r3, [r7, #4] + 4312 0068 1B68 ldr r3, [r3] + 4313 006a 22F40062 bic r2, r2, #2048 + 4314 006e DA60 str r2, [r3, #12] +1521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + 4315 .loc 1 1521 13 + 4316 0070 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/ccxRWv8k.s page 103 + + + 4317 0072 DB6A ldr r3, [r3, #44] + 4318 0074 1846 mov r0, r3 + 4319 0076 FFF7FEFF bl HAL_DMA_Abort_IT +1522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** break; + 4320 .loc 1 1522 7 + 4321 007a 02E0 b .L307 + 4322 .L304: +1523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +1524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** default: +1526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** status = HAL_ERROR; + 4323 .loc 1 1526 14 + 4324 007c 0123 movs r3, #1 + 4325 007e FB73 strb r3, [r7, #15] +1527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** break; + 4326 .loc 1 1527 7 + 4327 0080 00BF nop + 4328 .L307: +1528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +1529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (status == HAL_OK) + 4329 .loc 1 1530 6 + 4330 0082 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 + 4331 0084 002B cmp r3, #0 + 4332 0086 52D1 bne .L308 +1531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +1532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable the complementary PWM output */ +1533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + 4333 .loc 1 1533 5 + 4334 0088 7B68 ldr r3, [r7, #4] + 4335 008a 1B68 ldr r3, [r3] + 4336 008c 0022 movs r2, #0 + 4337 008e 3968 ldr r1, [r7] + 4338 0090 1846 mov r0, r3 + 4339 0092 FFF7FEFF bl TIM_CCxNChannelCmd +1534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable the Main Output */ +1536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_MOE_DISABLE(htim); + 4340 .loc 1 1536 5 + 4341 0096 7B68 ldr r3, [r7, #4] + 4342 0098 1B68 ldr r3, [r3] + 4343 009a 1A6A ldr r2, [r3, #32] + 4344 009c 41F21113 movw r3, #4369 + 4345 00a0 1340 ands r3, r3, r2 + 4346 00a2 002B cmp r3, #0 + 4347 00a4 0FD1 bne .L309 + 4348 .loc 1 1536 5 is_stmt 0 discriminator 1 + 4349 00a6 7B68 ldr r3, [r7, #4] + 4350 00a8 1B68 ldr r3, [r3] + 4351 00aa 1A6A ldr r2, [r3, #32] + 4352 00ac 40F24443 movw r3, #1092 + 4353 00b0 1340 ands r3, r3, r2 + 4354 00b2 002B cmp r3, #0 + 4355 00b4 07D1 bne .L309 + 4356 .loc 1 1536 5 discriminator 2 + 4357 00b6 7B68 ldr r3, [r7, #4] + 4358 00b8 1B68 ldr r3, [r3] + ARM GAS /tmp/ccxRWv8k.s page 104 + + + 4359 00ba 5A6C ldr r2, [r3, #68] + 4360 00bc 7B68 ldr r3, [r7, #4] + 4361 00be 1B68 ldr r3, [r3] + 4362 00c0 22F40042 bic r2, r2, #32768 + 4363 00c4 5A64 str r2, [r3, #68] + 4364 .L309: +1537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable the Peripheral */ +1539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_DISABLE(htim); + 4365 .loc 1 1539 5 is_stmt 1 + 4366 00c6 7B68 ldr r3, [r7, #4] + 4367 00c8 1B68 ldr r3, [r3] + 4368 00ca 1A6A ldr r2, [r3, #32] + 4369 00cc 41F21113 movw r3, #4369 + 4370 00d0 1340 ands r3, r3, r2 + 4371 00d2 002B cmp r3, #0 + 4372 00d4 0FD1 bne .L310 + 4373 .loc 1 1539 5 is_stmt 0 discriminator 1 + 4374 00d6 7B68 ldr r3, [r7, #4] + 4375 00d8 1B68 ldr r3, [r3] + 4376 00da 1A6A ldr r2, [r3, #32] + 4377 00dc 40F24443 movw r3, #1092 + 4378 00e0 1340 ands r3, r3, r2 + 4379 00e2 002B cmp r3, #0 + 4380 00e4 07D1 bne .L310 + 4381 .loc 1 1539 5 discriminator 2 + 4382 00e6 7B68 ldr r3, [r7, #4] + 4383 00e8 1B68 ldr r3, [r3] + 4384 00ea 1A68 ldr r2, [r3] + 4385 00ec 7B68 ldr r3, [r7, #4] + 4386 00ee 1B68 ldr r3, [r3] + 4387 00f0 22F00102 bic r2, r2, #1 + 4388 00f4 1A60 str r2, [r3] + 4389 .L310: +1540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Set the TIM complementary channel state */ +1542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + 4390 .loc 1 1542 5 is_stmt 1 + 4391 00f6 3B68 ldr r3, [r7] + 4392 00f8 002B cmp r3, #0 + 4393 00fa 04D1 bne .L311 + 4394 .loc 1 1542 5 is_stmt 0 discriminator 1 + 4395 00fc 7B68 ldr r3, [r7, #4] + 4396 00fe 0122 movs r2, #1 + 4397 0100 83F84420 strb r2, [r3, #68] + 4398 0104 13E0 b .L308 + 4399 .L311: + 4400 .loc 1 1542 5 discriminator 2 + 4401 0106 3B68 ldr r3, [r7] + 4402 0108 042B cmp r3, #4 + 4403 010a 04D1 bne .L312 + 4404 .loc 1 1542 5 discriminator 3 + 4405 010c 7B68 ldr r3, [r7, #4] + 4406 010e 0122 movs r2, #1 + 4407 0110 83F84520 strb r2, [r3, #69] + 4408 0114 0BE0 b .L308 + 4409 .L312: + ARM GAS /tmp/ccxRWv8k.s page 105 + + + 4410 .loc 1 1542 5 discriminator 4 + 4411 0116 3B68 ldr r3, [r7] + 4412 0118 082B cmp r3, #8 + 4413 011a 04D1 bne .L314 + 4414 .loc 1 1542 5 discriminator 6 + 4415 011c 7B68 ldr r3, [r7, #4] + 4416 011e 0122 movs r2, #1 + 4417 0120 83F84620 strb r2, [r3, #70] + 4418 0124 03E0 b .L308 + 4419 .L314: + 4420 .loc 1 1542 5 discriminator 7 + 4421 0126 7B68 ldr r3, [r7, #4] + 4422 0128 0122 movs r2, #1 + 4423 012a 83F84720 strb r2, [r3, #71] + 4424 .L308: +1543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +1544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1545:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Return function status */ +1546:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return status; + 4425 .loc 1 1546 10 is_stmt 1 + 4426 012e FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 +1547:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 4427 .loc 1 1547 1 + 4428 0130 1846 mov r0, r3 + 4429 0132 1037 adds r7, r7, #16 + 4430 .cfi_def_cfa_offset 8 + 4431 0134 BD46 mov sp, r7 + 4432 .cfi_def_cfa_register 13 + 4433 @ sp needed + 4434 0136 80BD pop {r7, pc} + 4435 .cfi_endproc + 4436 .LFE151: + 4438 .section .text.HAL_TIMEx_OnePulseN_Start,"ax",%progbits + 4439 .align 1 + 4440 .global HAL_TIMEx_OnePulseN_Start + 4441 .syntax unified + 4442 .thumb + 4443 .thumb_func + 4445 HAL_TIMEx_OnePulseN_Start: + 4446 .LFB152: +1548:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1549:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** +1550:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @} +1551:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ +1552:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1553:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions +1554:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief Timer Complementary One Pulse functions +1555:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * +1556:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** @verbatim +1557:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** ============================================================================== +1558:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** ##### Timer Complementary One Pulse functions ##### +1559:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** ============================================================================== +1560:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** [..] +1561:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** This section provides functions allowing to: +1562:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (+) Start the Complementary One Pulse generation. +1563:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (+) Stop the Complementary One Pulse. +1564:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (+) Start the Complementary One Pulse and enable interrupts. + ARM GAS /tmp/ccxRWv8k.s page 106 + + +1565:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (+) Stop the Complementary One Pulse and disable interrupts. +1566:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1567:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** @endverbatim +1568:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @{ +1569:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ +1570:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1571:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** +1572:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief Starts the TIM One Pulse signal generation on the complementary +1573:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * output. +1574:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @note OutputChannel must match the pulse output channel chosen when calling +1575:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @ref HAL_TIM_OnePulse_ConfigChannel(). +1576:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param htim TIM One Pulse handle +1577:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param OutputChannel pulse output channel to enable +1578:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * This parameter can be one of the following values: +1579:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +1580:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +1581:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @retval HAL status +1582:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ +1583:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +1584:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 4447 .loc 1 1584 1 + 4448 .cfi_startproc + 4449 @ args = 0, pretend = 0, frame = 16 + 4450 @ frame_needed = 1, uses_anonymous_args = 0 + 4451 0000 80B5 push {r7, lr} + 4452 .cfi_def_cfa_offset 8 + 4453 .cfi_offset 7, -8 + 4454 .cfi_offset 14, -4 + 4455 0002 84B0 sub sp, sp, #16 + 4456 .cfi_def_cfa_offset 24 + 4457 0004 00AF add r7, sp, #0 + 4458 .cfi_def_cfa_register 7 + 4459 0006 7860 str r0, [r7, #4] + 4460 0008 3960 str r1, [r7] +1585:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + 4461 .loc 1 1585 77 + 4462 000a 3B68 ldr r3, [r7] + 4463 000c 002B cmp r3, #0 + 4464 000e 01D1 bne .L318 + 4465 .loc 1 1585 77 is_stmt 0 discriminator 1 + 4466 0010 0423 movs r3, #4 + 4467 0012 00E0 b .L319 + 4468 .L318: + 4469 .loc 1 1585 77 discriminator 2 + 4470 0014 0023 movs r3, #0 + 4471 .L319: + 4472 .loc 1 1585 12 is_stmt 1 discriminator 4 + 4473 0016 FB60 str r3, [r7, #12] +1586:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + 4474 .loc 1 1586 31 + 4475 0018 7B68 ldr r3, [r7, #4] + 4476 001a 93F83E30 ldrb r3, [r3, #62] + 4477 001e FB72 strb r3, [r7, #11] +1587:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + 4478 .loc 1 1587 31 + 4479 0020 7B68 ldr r3, [r7, #4] + 4480 0022 93F83F30 ldrb r3, [r3, #63] + ARM GAS /tmp/ccxRWv8k.s page 107 + + + 4481 0026 BB72 strb r3, [r7, #10] +1588:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 4482 .loc 1 1588 31 + 4483 0028 7B68 ldr r3, [r7, #4] + 4484 002a 93F84430 ldrb r3, [r3, #68] + 4485 002e 7B72 strb r3, [r7, #9] +1589:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 4486 .loc 1 1589 31 + 4487 0030 7B68 ldr r3, [r7, #4] + 4488 0032 93F84530 ldrb r3, [r3, #69] + 4489 0036 3B72 strb r3, [r7, #8] +1590:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1591:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Check the parameters */ +1592:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); +1593:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1594:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Check the TIM channels state */ +1595:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + 4490 .loc 1 1595 6 + 4491 0038 FB7A ldrb r3, [r7, #11] @ zero_extendqisi2 + 4492 003a 012B cmp r3, #1 + 4493 003c 08D1 bne .L320 +1596:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + 4494 .loc 1 1596 7 + 4495 003e BB7A ldrb r3, [r7, #10] @ zero_extendqisi2 + 4496 0040 012B cmp r3, #1 + 4497 0042 05D1 bne .L320 +1597:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + 4498 .loc 1 1597 7 + 4499 0044 7B7A ldrb r3, [r7, #9] @ zero_extendqisi2 + 4500 0046 012B cmp r3, #1 + 4501 0048 02D1 bne .L320 +1598:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + 4502 .loc 1 1598 7 + 4503 004a 3B7A ldrb r3, [r7, #8] @ zero_extendqisi2 + 4504 004c 012B cmp r3, #1 + 4505 004e 01D0 beq .L321 + 4506 .L320: +1599:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +1600:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return HAL_ERROR; + 4507 .loc 1 1600 12 + 4508 0050 0123 movs r3, #1 + 4509 0052 26E0 b .L322 + 4510 .L321: +1601:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +1602:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1603:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Set the TIM channels state */ +1604:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + 4511 .loc 1 1604 3 + 4512 0054 7B68 ldr r3, [r7, #4] + 4513 0056 0222 movs r2, #2 + 4514 0058 83F83E20 strb r2, [r3, #62] +1605:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 4515 .loc 1 1605 3 + 4516 005c 7B68 ldr r3, [r7, #4] + 4517 005e 0222 movs r2, #2 + 4518 0060 83F83F20 strb r2, [r3, #63] +1606:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + ARM GAS /tmp/ccxRWv8k.s page 108 + + + 4519 .loc 1 1606 3 + 4520 0064 7B68 ldr r3, [r7, #4] + 4521 0066 0222 movs r2, #2 + 4522 0068 83F84420 strb r2, [r3, #68] +1607:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 4523 .loc 1 1607 3 + 4524 006c 7B68 ldr r3, [r7, #4] + 4525 006e 0222 movs r2, #2 + 4526 0070 83F84520 strb r2, [r3, #69] +1608:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1609:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the complementary One Pulse output channel and the Input Capture channel */ +1610:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + 4527 .loc 1 1610 3 + 4528 0074 7B68 ldr r3, [r7, #4] + 4529 0076 1B68 ldr r3, [r3] + 4530 0078 0422 movs r2, #4 + 4531 007a 3968 ldr r1, [r7] + 4532 007c 1846 mov r0, r3 + 4533 007e FFF7FEFF bl TIM_CCxNChannelCmd +1611:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); + 4534 .loc 1 1611 3 + 4535 0082 7B68 ldr r3, [r7, #4] + 4536 0084 1B68 ldr r3, [r3] + 4537 0086 0122 movs r2, #1 + 4538 0088 F968 ldr r1, [r7, #12] + 4539 008a 1846 mov r0, r3 + 4540 008c FFF7FEFF bl TIM_CCxChannelCmd +1612:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1613:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the Main Output */ +1614:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_MOE_ENABLE(htim); + 4541 .loc 1 1614 3 + 4542 0090 7B68 ldr r3, [r7, #4] + 4543 0092 1B68 ldr r3, [r3] + 4544 0094 5A6C ldr r2, [r3, #68] + 4545 0096 7B68 ldr r3, [r7, #4] + 4546 0098 1B68 ldr r3, [r3] + 4547 009a 42F40042 orr r2, r2, #32768 + 4548 009e 5A64 str r2, [r3, #68] +1615:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1616:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Return function status */ +1617:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return HAL_OK; + 4549 .loc 1 1617 10 + 4550 00a0 0023 movs r3, #0 + 4551 .L322: +1618:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 4552 .loc 1 1618 1 + 4553 00a2 1846 mov r0, r3 + 4554 00a4 1037 adds r7, r7, #16 + 4555 .cfi_def_cfa_offset 8 + 4556 00a6 BD46 mov sp, r7 + 4557 .cfi_def_cfa_register 13 + 4558 @ sp needed + 4559 00a8 80BD pop {r7, pc} + 4560 .cfi_endproc + 4561 .LFE152: + 4563 .section .text.HAL_TIMEx_OnePulseN_Stop,"ax",%progbits + 4564 .align 1 + ARM GAS /tmp/ccxRWv8k.s page 109 + + + 4565 .global HAL_TIMEx_OnePulseN_Stop + 4566 .syntax unified + 4567 .thumb + 4568 .thumb_func + 4570 HAL_TIMEx_OnePulseN_Stop: + 4571 .LFB153: +1619:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1620:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** +1621:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief Stops the TIM One Pulse signal generation on the complementary +1622:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * output. +1623:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @note OutputChannel must match the pulse output channel chosen when calling +1624:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @ref HAL_TIM_OnePulse_ConfigChannel(). +1625:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param htim TIM One Pulse handle +1626:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param OutputChannel pulse output channel to disable +1627:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * This parameter can be one of the following values: +1628:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +1629:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +1630:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @retval HAL status +1631:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ +1632:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +1633:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 4572 .loc 1 1633 1 + 4573 .cfi_startproc + 4574 @ args = 0, pretend = 0, frame = 16 + 4575 @ frame_needed = 1, uses_anonymous_args = 0 + 4576 0000 80B5 push {r7, lr} + 4577 .cfi_def_cfa_offset 8 + 4578 .cfi_offset 7, -8 + 4579 .cfi_offset 14, -4 + 4580 0002 84B0 sub sp, sp, #16 + 4581 .cfi_def_cfa_offset 24 + 4582 0004 00AF add r7, sp, #0 + 4583 .cfi_def_cfa_register 7 + 4584 0006 7860 str r0, [r7, #4] + 4585 0008 3960 str r1, [r7] +1634:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + 4586 .loc 1 1634 77 + 4587 000a 3B68 ldr r3, [r7] + 4588 000c 002B cmp r3, #0 + 4589 000e 01D1 bne .L324 + 4590 .loc 1 1634 77 is_stmt 0 discriminator 1 + 4591 0010 0423 movs r3, #4 + 4592 0012 00E0 b .L325 + 4593 .L324: + 4594 .loc 1 1634 77 discriminator 2 + 4595 0014 0023 movs r3, #0 + 4596 .L325: + 4597 .loc 1 1634 12 is_stmt 1 discriminator 4 + 4598 0016 FB60 str r3, [r7, #12] +1635:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1636:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Check the parameters */ +1637:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); +1638:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1639:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable the complementary One Pulse output channel and the Input Capture channel */ +1640:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + 4599 .loc 1 1640 3 + 4600 0018 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/ccxRWv8k.s page 110 + + + 4601 001a 1B68 ldr r3, [r3] + 4602 001c 0022 movs r2, #0 + 4603 001e 3968 ldr r1, [r7] + 4604 0020 1846 mov r0, r3 + 4605 0022 FFF7FEFF bl TIM_CCxNChannelCmd +1641:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); + 4606 .loc 1 1641 3 + 4607 0026 7B68 ldr r3, [r7, #4] + 4608 0028 1B68 ldr r3, [r3] + 4609 002a 0022 movs r2, #0 + 4610 002c F968 ldr r1, [r7, #12] + 4611 002e 1846 mov r0, r3 + 4612 0030 FFF7FEFF bl TIM_CCxChannelCmd +1642:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1643:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable the Main Output */ +1644:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_MOE_DISABLE(htim); + 4613 .loc 1 1644 3 + 4614 0034 7B68 ldr r3, [r7, #4] + 4615 0036 1B68 ldr r3, [r3] + 4616 0038 1A6A ldr r2, [r3, #32] + 4617 003a 41F21113 movw r3, #4369 + 4618 003e 1340 ands r3, r3, r2 + 4619 0040 002B cmp r3, #0 + 4620 0042 0FD1 bne .L326 + 4621 .loc 1 1644 3 is_stmt 0 discriminator 1 + 4622 0044 7B68 ldr r3, [r7, #4] + 4623 0046 1B68 ldr r3, [r3] + 4624 0048 1A6A ldr r2, [r3, #32] + 4625 004a 40F24443 movw r3, #1092 + 4626 004e 1340 ands r3, r3, r2 + 4627 0050 002B cmp r3, #0 + 4628 0052 07D1 bne .L326 + 4629 .loc 1 1644 3 discriminator 2 + 4630 0054 7B68 ldr r3, [r7, #4] + 4631 0056 1B68 ldr r3, [r3] + 4632 0058 5A6C ldr r2, [r3, #68] + 4633 005a 7B68 ldr r3, [r7, #4] + 4634 005c 1B68 ldr r3, [r3] + 4635 005e 22F40042 bic r2, r2, #32768 + 4636 0062 5A64 str r2, [r3, #68] + 4637 .L326: +1645:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1646:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable the Peripheral */ +1647:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_DISABLE(htim); + 4638 .loc 1 1647 3 is_stmt 1 + 4639 0064 7B68 ldr r3, [r7, #4] + 4640 0066 1B68 ldr r3, [r3] + 4641 0068 1A6A ldr r2, [r3, #32] + 4642 006a 41F21113 movw r3, #4369 + 4643 006e 1340 ands r3, r3, r2 + 4644 0070 002B cmp r3, #0 + 4645 0072 0FD1 bne .L327 + 4646 .loc 1 1647 3 is_stmt 0 discriminator 1 + 4647 0074 7B68 ldr r3, [r7, #4] + 4648 0076 1B68 ldr r3, [r3] + 4649 0078 1A6A ldr r2, [r3, #32] + 4650 007a 40F24443 movw r3, #1092 + ARM GAS /tmp/ccxRWv8k.s page 111 + + + 4651 007e 1340 ands r3, r3, r2 + 4652 0080 002B cmp r3, #0 + 4653 0082 07D1 bne .L327 + 4654 .loc 1 1647 3 discriminator 2 + 4655 0084 7B68 ldr r3, [r7, #4] + 4656 0086 1B68 ldr r3, [r3] + 4657 0088 1A68 ldr r2, [r3] + 4658 008a 7B68 ldr r3, [r7, #4] + 4659 008c 1B68 ldr r3, [r3] + 4660 008e 22F00102 bic r2, r2, #1 + 4661 0092 1A60 str r2, [r3] + 4662 .L327: +1648:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1649:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Set the TIM channels state */ +1650:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 4663 .loc 1 1650 3 is_stmt 1 + 4664 0094 7B68 ldr r3, [r7, #4] + 4665 0096 0122 movs r2, #1 + 4666 0098 83F83E20 strb r2, [r3, #62] +1651:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 4667 .loc 1 1651 3 + 4668 009c 7B68 ldr r3, [r7, #4] + 4669 009e 0122 movs r2, #1 + 4670 00a0 83F83F20 strb r2, [r3, #63] +1652:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 4671 .loc 1 1652 3 + 4672 00a4 7B68 ldr r3, [r7, #4] + 4673 00a6 0122 movs r2, #1 + 4674 00a8 83F84420 strb r2, [r3, #68] +1653:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 4675 .loc 1 1653 3 + 4676 00ac 7B68 ldr r3, [r7, #4] + 4677 00ae 0122 movs r2, #1 + 4678 00b0 83F84520 strb r2, [r3, #69] +1654:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1655:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Return function status */ +1656:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return HAL_OK; + 4679 .loc 1 1656 10 + 4680 00b4 0023 movs r3, #0 +1657:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 4681 .loc 1 1657 1 + 4682 00b6 1846 mov r0, r3 + 4683 00b8 1037 adds r7, r7, #16 + 4684 .cfi_def_cfa_offset 8 + 4685 00ba BD46 mov sp, r7 + 4686 .cfi_def_cfa_register 13 + 4687 @ sp needed + 4688 00bc 80BD pop {r7, pc} + 4689 .cfi_endproc + 4690 .LFE153: + 4692 .section .text.HAL_TIMEx_OnePulseN_Start_IT,"ax",%progbits + 4693 .align 1 + 4694 .global HAL_TIMEx_OnePulseN_Start_IT + 4695 .syntax unified + 4696 .thumb + 4697 .thumb_func + 4699 HAL_TIMEx_OnePulseN_Start_IT: + ARM GAS /tmp/ccxRWv8k.s page 112 + + + 4700 .LFB154: +1658:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1659:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** +1660:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief Starts the TIM One Pulse signal generation in interrupt mode on the +1661:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * complementary channel. +1662:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @note OutputChannel must match the pulse output channel chosen when calling +1663:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @ref HAL_TIM_OnePulse_ConfigChannel(). +1664:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param htim TIM One Pulse handle +1665:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param OutputChannel pulse output channel to enable +1666:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * This parameter can be one of the following values: +1667:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +1668:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +1669:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @retval HAL status +1670:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ +1671:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +1672:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 4701 .loc 1 1672 1 + 4702 .cfi_startproc + 4703 @ args = 0, pretend = 0, frame = 16 + 4704 @ frame_needed = 1, uses_anonymous_args = 0 + 4705 0000 80B5 push {r7, lr} + 4706 .cfi_def_cfa_offset 8 + 4707 .cfi_offset 7, -8 + 4708 .cfi_offset 14, -4 + 4709 0002 84B0 sub sp, sp, #16 + 4710 .cfi_def_cfa_offset 24 + 4711 0004 00AF add r7, sp, #0 + 4712 .cfi_def_cfa_register 7 + 4713 0006 7860 str r0, [r7, #4] + 4714 0008 3960 str r1, [r7] +1673:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + 4715 .loc 1 1673 77 + 4716 000a 3B68 ldr r3, [r7] + 4717 000c 002B cmp r3, #0 + 4718 000e 01D1 bne .L330 + 4719 .loc 1 1673 77 is_stmt 0 discriminator 1 + 4720 0010 0423 movs r3, #4 + 4721 0012 00E0 b .L331 + 4722 .L330: + 4723 .loc 1 1673 77 discriminator 2 + 4724 0014 0023 movs r3, #0 + 4725 .L331: + 4726 .loc 1 1673 12 is_stmt 1 discriminator 4 + 4727 0016 FB60 str r3, [r7, #12] +1674:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + 4728 .loc 1 1674 31 + 4729 0018 7B68 ldr r3, [r7, #4] + 4730 001a 93F83E30 ldrb r3, [r3, #62] + 4731 001e FB72 strb r3, [r7, #11] +1675:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + 4732 .loc 1 1675 31 + 4733 0020 7B68 ldr r3, [r7, #4] + 4734 0022 93F83F30 ldrb r3, [r3, #63] + 4735 0026 BB72 strb r3, [r7, #10] +1676:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 4736 .loc 1 1676 31 + 4737 0028 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/ccxRWv8k.s page 113 + + + 4738 002a 93F84430 ldrb r3, [r3, #68] + 4739 002e 7B72 strb r3, [r7, #9] +1677:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHA + 4740 .loc 1 1677 31 + 4741 0030 7B68 ldr r3, [r7, #4] + 4742 0032 93F84530 ldrb r3, [r3, #69] + 4743 0036 3B72 strb r3, [r7, #8] +1678:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1679:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Check the parameters */ +1680:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); +1681:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1682:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Check the TIM channels state */ +1683:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + 4744 .loc 1 1683 6 + 4745 0038 FB7A ldrb r3, [r7, #11] @ zero_extendqisi2 + 4746 003a 012B cmp r3, #1 + 4747 003c 08D1 bne .L332 +1684:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + 4748 .loc 1 1684 7 + 4749 003e BB7A ldrb r3, [r7, #10] @ zero_extendqisi2 + 4750 0040 012B cmp r3, #1 + 4751 0042 05D1 bne .L332 +1685:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + 4752 .loc 1 1685 7 + 4753 0044 7B7A ldrb r3, [r7, #9] @ zero_extendqisi2 + 4754 0046 012B cmp r3, #1 + 4755 0048 02D1 bne .L332 +1686:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + 4756 .loc 1 1686 7 + 4757 004a 3B7A ldrb r3, [r7, #8] @ zero_extendqisi2 + 4758 004c 012B cmp r3, #1 + 4759 004e 01D0 beq .L333 + 4760 .L332: +1687:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +1688:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return HAL_ERROR; + 4761 .loc 1 1688 12 + 4762 0050 0123 movs r3, #1 + 4763 0052 36E0 b .L334 + 4764 .L333: +1689:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +1690:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1691:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Set the TIM channels state */ +1692:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + 4765 .loc 1 1692 3 + 4766 0054 7B68 ldr r3, [r7, #4] + 4767 0056 0222 movs r2, #2 + 4768 0058 83F83E20 strb r2, [r3, #62] +1693:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 4769 .loc 1 1693 3 + 4770 005c 7B68 ldr r3, [r7, #4] + 4771 005e 0222 movs r2, #2 + 4772 0060 83F83F20 strb r2, [r3, #63] +1694:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + 4773 .loc 1 1694 3 + 4774 0064 7B68 ldr r3, [r7, #4] + 4775 0066 0222 movs r2, #2 + 4776 0068 83F84420 strb r2, [r3, #68] + ARM GAS /tmp/ccxRWv8k.s page 114 + + +1695:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + 4777 .loc 1 1695 3 + 4778 006c 7B68 ldr r3, [r7, #4] + 4779 006e 0222 movs r2, #2 + 4780 0070 83F84520 strb r2, [r3, #69] +1696:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1697:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the TIM Capture/Compare 1 interrupt */ +1698:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + 4781 .loc 1 1698 3 + 4782 0074 7B68 ldr r3, [r7, #4] + 4783 0076 1B68 ldr r3, [r3] + 4784 0078 DA68 ldr r2, [r3, #12] + 4785 007a 7B68 ldr r3, [r7, #4] + 4786 007c 1B68 ldr r3, [r3] + 4787 007e 42F00202 orr r2, r2, #2 + 4788 0082 DA60 str r2, [r3, #12] +1699:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1700:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the TIM Capture/Compare 2 interrupt */ +1701:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + 4789 .loc 1 1701 3 + 4790 0084 7B68 ldr r3, [r7, #4] + 4791 0086 1B68 ldr r3, [r3] + 4792 0088 DA68 ldr r2, [r3, #12] + 4793 008a 7B68 ldr r3, [r7, #4] + 4794 008c 1B68 ldr r3, [r3] + 4795 008e 42F00402 orr r2, r2, #4 + 4796 0092 DA60 str r2, [r3, #12] +1702:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1703:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the complementary One Pulse output channel and the Input Capture channel */ +1704:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + 4797 .loc 1 1704 3 + 4798 0094 7B68 ldr r3, [r7, #4] + 4799 0096 1B68 ldr r3, [r3] + 4800 0098 0422 movs r2, #4 + 4801 009a 3968 ldr r1, [r7] + 4802 009c 1846 mov r0, r3 + 4803 009e FFF7FEFF bl TIM_CCxNChannelCmd +1705:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); + 4804 .loc 1 1705 3 + 4805 00a2 7B68 ldr r3, [r7, #4] + 4806 00a4 1B68 ldr r3, [r3] + 4807 00a6 0122 movs r2, #1 + 4808 00a8 F968 ldr r1, [r7, #12] + 4809 00aa 1846 mov r0, r3 + 4810 00ac FFF7FEFF bl TIM_CCxChannelCmd +1706:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1707:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the Main Output */ +1708:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_MOE_ENABLE(htim); + 4811 .loc 1 1708 3 + 4812 00b0 7B68 ldr r3, [r7, #4] + 4813 00b2 1B68 ldr r3, [r3] + 4814 00b4 5A6C ldr r2, [r3, #68] + 4815 00b6 7B68 ldr r3, [r7, #4] + 4816 00b8 1B68 ldr r3, [r3] + 4817 00ba 42F40042 orr r2, r2, #32768 + 4818 00be 5A64 str r2, [r3, #68] +1709:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** + ARM GAS /tmp/ccxRWv8k.s page 115 + + +1710:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Return function status */ +1711:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return HAL_OK; + 4819 .loc 1 1711 10 + 4820 00c0 0023 movs r3, #0 + 4821 .L334: +1712:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 4822 .loc 1 1712 1 + 4823 00c2 1846 mov r0, r3 + 4824 00c4 1037 adds r7, r7, #16 + 4825 .cfi_def_cfa_offset 8 + 4826 00c6 BD46 mov sp, r7 + 4827 .cfi_def_cfa_register 13 + 4828 @ sp needed + 4829 00c8 80BD pop {r7, pc} + 4830 .cfi_endproc + 4831 .LFE154: + 4833 .section .text.HAL_TIMEx_OnePulseN_Stop_IT,"ax",%progbits + 4834 .align 1 + 4835 .global HAL_TIMEx_OnePulseN_Stop_IT + 4836 .syntax unified + 4837 .thumb + 4838 .thumb_func + 4840 HAL_TIMEx_OnePulseN_Stop_IT: + 4841 .LFB155: +1713:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1714:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** +1715:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief Stops the TIM One Pulse signal generation in interrupt mode on the +1716:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * complementary channel. +1717:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @note OutputChannel must match the pulse output channel chosen when calling +1718:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @ref HAL_TIM_OnePulse_ConfigChannel(). +1719:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param htim TIM One Pulse handle +1720:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param OutputChannel pulse output channel to disable +1721:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * This parameter can be one of the following values: +1722:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 selected +1723:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 selected +1724:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @retval HAL status +1725:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ +1726:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +1727:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 4842 .loc 1 1727 1 + 4843 .cfi_startproc + 4844 @ args = 0, pretend = 0, frame = 16 + 4845 @ frame_needed = 1, uses_anonymous_args = 0 + 4846 0000 80B5 push {r7, lr} + 4847 .cfi_def_cfa_offset 8 + 4848 .cfi_offset 7, -8 + 4849 .cfi_offset 14, -4 + 4850 0002 84B0 sub sp, sp, #16 + 4851 .cfi_def_cfa_offset 24 + 4852 0004 00AF add r7, sp, #0 + 4853 .cfi_def_cfa_register 7 + 4854 0006 7860 str r0, [r7, #4] + 4855 0008 3960 str r1, [r7] +1728:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + 4856 .loc 1 1728 77 + 4857 000a 3B68 ldr r3, [r7] + 4858 000c 002B cmp r3, #0 + ARM GAS /tmp/ccxRWv8k.s page 116 + + + 4859 000e 01D1 bne .L336 + 4860 .loc 1 1728 77 is_stmt 0 discriminator 1 + 4861 0010 0423 movs r3, #4 + 4862 0012 00E0 b .L337 + 4863 .L336: + 4864 .loc 1 1728 77 discriminator 2 + 4865 0014 0023 movs r3, #0 + 4866 .L337: + 4867 .loc 1 1728 12 is_stmt 1 discriminator 4 + 4868 0016 FB60 str r3, [r7, #12] +1729:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1730:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Check the parameters */ +1731:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); +1732:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1733:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable the TIM Capture/Compare 1 interrupt */ +1734:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + 4869 .loc 1 1734 3 + 4870 0018 7B68 ldr r3, [r7, #4] + 4871 001a 1B68 ldr r3, [r3] + 4872 001c DA68 ldr r2, [r3, #12] + 4873 001e 7B68 ldr r3, [r7, #4] + 4874 0020 1B68 ldr r3, [r3] + 4875 0022 22F00202 bic r2, r2, #2 + 4876 0026 DA60 str r2, [r3, #12] +1735:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1736:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable the TIM Capture/Compare 2 interrupt */ +1737:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + 4877 .loc 1 1737 3 + 4878 0028 7B68 ldr r3, [r7, #4] + 4879 002a 1B68 ldr r3, [r3] + 4880 002c DA68 ldr r2, [r3, #12] + 4881 002e 7B68 ldr r3, [r7, #4] + 4882 0030 1B68 ldr r3, [r3] + 4883 0032 22F00402 bic r2, r2, #4 + 4884 0036 DA60 str r2, [r3, #12] +1738:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1739:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable the complementary One Pulse output channel and the Input Capture channel */ +1740:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + 4885 .loc 1 1740 3 + 4886 0038 7B68 ldr r3, [r7, #4] + 4887 003a 1B68 ldr r3, [r3] + 4888 003c 0022 movs r2, #0 + 4889 003e 3968 ldr r1, [r7] + 4890 0040 1846 mov r0, r3 + 4891 0042 FFF7FEFF bl TIM_CCxNChannelCmd +1741:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); + 4892 .loc 1 1741 3 + 4893 0046 7B68 ldr r3, [r7, #4] + 4894 0048 1B68 ldr r3, [r3] + 4895 004a 0022 movs r2, #0 + 4896 004c F968 ldr r1, [r7, #12] + 4897 004e 1846 mov r0, r3 + 4898 0050 FFF7FEFF bl TIM_CCxChannelCmd +1742:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1743:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable the Main Output */ +1744:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_MOE_DISABLE(htim); + 4899 .loc 1 1744 3 + ARM GAS /tmp/ccxRWv8k.s page 117 + + + 4900 0054 7B68 ldr r3, [r7, #4] + 4901 0056 1B68 ldr r3, [r3] + 4902 0058 1A6A ldr r2, [r3, #32] + 4903 005a 41F21113 movw r3, #4369 + 4904 005e 1340 ands r3, r3, r2 + 4905 0060 002B cmp r3, #0 + 4906 0062 0FD1 bne .L338 + 4907 .loc 1 1744 3 is_stmt 0 discriminator 1 + 4908 0064 7B68 ldr r3, [r7, #4] + 4909 0066 1B68 ldr r3, [r3] + 4910 0068 1A6A ldr r2, [r3, #32] + 4911 006a 40F24443 movw r3, #1092 + 4912 006e 1340 ands r3, r3, r2 + 4913 0070 002B cmp r3, #0 + 4914 0072 07D1 bne .L338 + 4915 .loc 1 1744 3 discriminator 2 + 4916 0074 7B68 ldr r3, [r7, #4] + 4917 0076 1B68 ldr r3, [r3] + 4918 0078 5A6C ldr r2, [r3, #68] + 4919 007a 7B68 ldr r3, [r7, #4] + 4920 007c 1B68 ldr r3, [r3] + 4921 007e 22F40042 bic r2, r2, #32768 + 4922 0082 5A64 str r2, [r3, #68] + 4923 .L338: +1745:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1746:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable the Peripheral */ +1747:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_DISABLE(htim); + 4924 .loc 1 1747 3 is_stmt 1 + 4925 0084 7B68 ldr r3, [r7, #4] + 4926 0086 1B68 ldr r3, [r3] + 4927 0088 1A6A ldr r2, [r3, #32] + 4928 008a 41F21113 movw r3, #4369 + 4929 008e 1340 ands r3, r3, r2 + 4930 0090 002B cmp r3, #0 + 4931 0092 0FD1 bne .L339 + 4932 .loc 1 1747 3 is_stmt 0 discriminator 1 + 4933 0094 7B68 ldr r3, [r7, #4] + 4934 0096 1B68 ldr r3, [r3] + 4935 0098 1A6A ldr r2, [r3, #32] + 4936 009a 40F24443 movw r3, #1092 + 4937 009e 1340 ands r3, r3, r2 + 4938 00a0 002B cmp r3, #0 + 4939 00a2 07D1 bne .L339 + 4940 .loc 1 1747 3 discriminator 2 + 4941 00a4 7B68 ldr r3, [r7, #4] + 4942 00a6 1B68 ldr r3, [r3] + 4943 00a8 1A68 ldr r2, [r3] + 4944 00aa 7B68 ldr r3, [r7, #4] + 4945 00ac 1B68 ldr r3, [r3] + 4946 00ae 22F00102 bic r2, r2, #1 + 4947 00b2 1A60 str r2, [r3] + 4948 .L339: +1748:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1749:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Set the TIM channels state */ +1750:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 4949 .loc 1 1750 3 is_stmt 1 + 4950 00b4 7B68 ldr r3, [r7, #4] + ARM GAS /tmp/ccxRWv8k.s page 118 + + + 4951 00b6 0122 movs r2, #1 + 4952 00b8 83F83E20 strb r2, [r3, #62] +1751:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 4953 .loc 1 1751 3 + 4954 00bc 7B68 ldr r3, [r7, #4] + 4955 00be 0122 movs r2, #1 + 4956 00c0 83F83F20 strb r2, [r3, #63] +1752:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 4957 .loc 1 1752 3 + 4958 00c4 7B68 ldr r3, [r7, #4] + 4959 00c6 0122 movs r2, #1 + 4960 00c8 83F84420 strb r2, [r3, #68] +1753:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 4961 .loc 1 1753 3 + 4962 00cc 7B68 ldr r3, [r7, #4] + 4963 00ce 0122 movs r2, #1 + 4964 00d0 83F84520 strb r2, [r3, #69] +1754:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1755:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Return function status */ +1756:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return HAL_OK; + 4965 .loc 1 1756 10 + 4966 00d4 0023 movs r3, #0 +1757:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 4967 .loc 1 1757 1 + 4968 00d6 1846 mov r0, r3 + 4969 00d8 1037 adds r7, r7, #16 + 4970 .cfi_def_cfa_offset 8 + 4971 00da BD46 mov sp, r7 + 4972 .cfi_def_cfa_register 13 + 4973 @ sp needed + 4974 00dc 80BD pop {r7, pc} + 4975 .cfi_endproc + 4976 .LFE155: + 4978 .section .text.HAL_TIMEx_ConfigCommutEvent,"ax",%progbits + 4979 .align 1 + 4980 .global HAL_TIMEx_ConfigCommutEvent + 4981 .syntax unified + 4982 .thumb + 4983 .thumb_func + 4985 HAL_TIMEx_ConfigCommutEvent: + 4986 .LFB156: +1758:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1759:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** +1760:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @} +1761:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ +1762:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1763:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions +1764:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief Peripheral Control functions +1765:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * +1766:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** @verbatim +1767:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** ============================================================================== +1768:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** ##### Peripheral Control functions ##### +1769:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** ============================================================================== +1770:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** [..] +1771:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** This section provides functions allowing to: +1772:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (+) Configure the commutation event in case of use of the Hall sensor interface. +1773:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (+) Configure Output channels for OC and PWM mode. + ARM GAS /tmp/ccxRWv8k.s page 119 + + +1774:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1775:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (+) Configure Complementary channels, break features and dead time. +1776:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (+) Configure Master synchronization. +1777:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (+) Configure timer remapping capabilities. +1778:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (+) Enable or disable channel grouping. +1779:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1780:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** @endverbatim +1781:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @{ +1782:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ +1783:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1784:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** +1785:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief Configure the TIM commutation event sequence. +1786:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @note This function is mandatory to use the commutation event in order to +1787:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * update the configuration at each commutation detection on the TRGI input of the Timer, +1788:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * the typical use of this feature is with the use of another Timer(interface Timer) +1789:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * configured in Hall sensor interface, this interface Timer will generate the +1790:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * commutation at its TRGO output (connected to Timer used in this function) each time +1791:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * the TI1 of the Interface Timer detect a commutation at its input TI1. +1792:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param htim TIM handle +1793:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall +1794:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * This parameter can be one of the following values: +1795:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TS_ITR0: Internal trigger 0 selected +1796:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TS_ITR1: Internal trigger 1 selected +1797:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TS_ITR2: Internal trigger 2 selected +1798:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TS_ITR3: Internal trigger 3 selected +1799:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TS_NONE: No trigger is needed +1800:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param CommutationSource the Commutation Event source +1801:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * This parameter can be one of the following values: +1802:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer +1803:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG +1804:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @retval HAL status +1805:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ +1806:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, +1807:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** uint32_t CommutationSource) +1808:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 4987 .loc 1 1808 1 + 4988 .cfi_startproc + 4989 @ args = 0, pretend = 0, frame = 16 + 4990 @ frame_needed = 1, uses_anonymous_args = 0 + 4991 @ link register save eliminated. + 4992 0000 80B4 push {r7} + 4993 .cfi_def_cfa_offset 4 + 4994 .cfi_offset 7, -4 + 4995 0002 85B0 sub sp, sp, #20 + 4996 .cfi_def_cfa_offset 24 + 4997 0004 00AF add r7, sp, #0 + 4998 .cfi_def_cfa_register 7 + 4999 0006 F860 str r0, [r7, #12] + 5000 0008 B960 str r1, [r7, #8] + 5001 000a 7A60 str r2, [r7, #4] +1809:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Check the parameters */ +1810:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); +1811:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); +1812:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1813:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_LOCK(htim); + 5002 .loc 1 1813 3 + 5003 000c FB68 ldr r3, [r7, #12] + ARM GAS /tmp/ccxRWv8k.s page 120 + + + 5004 000e 93F83C30 ldrb r3, [r3, #60] @ zero_extendqisi2 + 5005 0012 012B cmp r3, #1 + 5006 0014 01D1 bne .L342 + 5007 .loc 1 1813 3 is_stmt 0 discriminator 1 + 5008 0016 0223 movs r3, #2 + 5009 .loc 1 1813 3 + 5010 0018 4CE0 b .L343 + 5011 .L342: + 5012 .loc 1 1813 3 discriminator 2 + 5013 001a FB68 ldr r3, [r7, #12] + 5014 001c 0122 movs r2, #1 + 5015 001e 83F83C20 strb r2, [r3, #60] +1814:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1815:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + 5016 .loc 1 1815 6 is_stmt 1 + 5017 0022 BB68 ldr r3, [r7, #8] + 5018 0024 002B cmp r3, #0 + 5019 0026 08D0 beq .L344 + 5020 .loc 1 1815 37 discriminator 1 + 5021 0028 BB68 ldr r3, [r7, #8] + 5022 002a 102B cmp r3, #16 + 5023 002c 05D0 beq .L344 + 5024 .loc 1 1815 70 discriminator 2 + 5025 002e BB68 ldr r3, [r7, #8] + 5026 0030 202B cmp r3, #32 + 5027 0032 02D0 beq .L344 +1816:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + 5028 .loc 1 1816 37 + 5029 0034 BB68 ldr r3, [r7, #8] + 5030 0036 302B cmp r3, #48 + 5031 0038 0FD1 bne .L345 + 5032 .L344: +1817:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +1818:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Select the Input trigger */ +1819:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->Instance->SMCR &= ~TIM_SMCR_TS; + 5033 .loc 1 1819 9 + 5034 003a FB68 ldr r3, [r7, #12] + 5035 003c 1B68 ldr r3, [r3] + 5036 .loc 1 1819 19 + 5037 003e 9A68 ldr r2, [r3, #8] + 5038 .loc 1 1819 9 + 5039 0040 FB68 ldr r3, [r7, #12] + 5040 0042 1B68 ldr r3, [r3] + 5041 .loc 1 1819 26 + 5042 0044 22F07002 bic r2, r2, #112 + 5043 0048 9A60 str r2, [r3, #8] +1820:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->Instance->SMCR |= InputTrigger; + 5044 .loc 1 1820 9 + 5045 004a FB68 ldr r3, [r7, #12] + 5046 004c 1B68 ldr r3, [r3] + 5047 .loc 1 1820 19 + 5048 004e 9968 ldr r1, [r3, #8] + 5049 .loc 1 1820 9 + 5050 0050 FB68 ldr r3, [r7, #12] + 5051 0052 1B68 ldr r3, [r3] + 5052 .loc 1 1820 26 + 5053 0054 BA68 ldr r2, [r7, #8] + ARM GAS /tmp/ccxRWv8k.s page 121 + + + 5054 0056 0A43 orrs r2, r2, r1 + 5055 0058 9A60 str r2, [r3, #8] + 5056 .L345: +1821:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +1822:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1823:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Select the Capture Compare preload feature */ +1824:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->Instance->CR2 |= TIM_CR2_CCPC; + 5057 .loc 1 1824 7 + 5058 005a FB68 ldr r3, [r7, #12] + 5059 005c 1B68 ldr r3, [r3] + 5060 .loc 1 1824 17 + 5061 005e 5A68 ldr r2, [r3, #4] + 5062 .loc 1 1824 7 + 5063 0060 FB68 ldr r3, [r7, #12] + 5064 0062 1B68 ldr r3, [r3] + 5065 .loc 1 1824 23 + 5066 0064 42F00102 orr r2, r2, #1 + 5067 0068 5A60 str r2, [r3, #4] +1825:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Select the Commutation event source */ +1826:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->Instance->CR2 &= ~TIM_CR2_CCUS; + 5068 .loc 1 1826 7 + 5069 006a FB68 ldr r3, [r7, #12] + 5070 006c 1B68 ldr r3, [r3] + 5071 .loc 1 1826 17 + 5072 006e 5A68 ldr r2, [r3, #4] + 5073 .loc 1 1826 7 + 5074 0070 FB68 ldr r3, [r7, #12] + 5075 0072 1B68 ldr r3, [r3] + 5076 .loc 1 1826 23 + 5077 0074 22F00402 bic r2, r2, #4 + 5078 0078 5A60 str r2, [r3, #4] +1827:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->Instance->CR2 |= CommutationSource; + 5079 .loc 1 1827 7 + 5080 007a FB68 ldr r3, [r7, #12] + 5081 007c 1B68 ldr r3, [r3] + 5082 .loc 1 1827 17 + 5083 007e 5968 ldr r1, [r3, #4] + 5084 .loc 1 1827 7 + 5085 0080 FB68 ldr r3, [r7, #12] + 5086 0082 1B68 ldr r3, [r3] + 5087 .loc 1 1827 23 + 5088 0084 7A68 ldr r2, [r7, #4] + 5089 0086 0A43 orrs r2, r2, r1 + 5090 0088 5A60 str r2, [r3, #4] +1828:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1829:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable Commutation Interrupt */ +1830:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); + 5091 .loc 1 1830 3 + 5092 008a FB68 ldr r3, [r7, #12] + 5093 008c 1B68 ldr r3, [r3] + 5094 008e DA68 ldr r2, [r3, #12] + 5095 0090 FB68 ldr r3, [r7, #12] + 5096 0092 1B68 ldr r3, [r3] + 5097 0094 22F02002 bic r2, r2, #32 + 5098 0098 DA60 str r2, [r3, #12] +1831:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1832:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable Commutation DMA request */ + ARM GAS /tmp/ccxRWv8k.s page 122 + + +1833:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); + 5099 .loc 1 1833 3 + 5100 009a FB68 ldr r3, [r7, #12] + 5101 009c 1B68 ldr r3, [r3] + 5102 009e DA68 ldr r2, [r3, #12] + 5103 00a0 FB68 ldr r3, [r7, #12] + 5104 00a2 1B68 ldr r3, [r3] + 5105 00a4 22F40052 bic r2, r2, #8192 + 5106 00a8 DA60 str r2, [r3, #12] +1834:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1835:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_UNLOCK(htim); + 5107 .loc 1 1835 3 + 5108 00aa FB68 ldr r3, [r7, #12] + 5109 00ac 0022 movs r2, #0 + 5110 00ae 83F83C20 strb r2, [r3, #60] +1836:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1837:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return HAL_OK; + 5111 .loc 1 1837 10 + 5112 00b2 0023 movs r3, #0 + 5113 .L343: +1838:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 5114 .loc 1 1838 1 + 5115 00b4 1846 mov r0, r3 + 5116 00b6 1437 adds r7, r7, #20 + 5117 .cfi_def_cfa_offset 4 + 5118 00b8 BD46 mov sp, r7 + 5119 .cfi_def_cfa_register 13 + 5120 @ sp needed + 5121 00ba 5DF8047B ldr r7, [sp], #4 + 5122 .cfi_restore 7 + 5123 .cfi_def_cfa_offset 0 + 5124 00be 7047 bx lr + 5125 .cfi_endproc + 5126 .LFE156: + 5128 .section .text.HAL_TIMEx_ConfigCommutEvent_IT,"ax",%progbits + 5129 .align 1 + 5130 .global HAL_TIMEx_ConfigCommutEvent_IT + 5131 .syntax unified + 5132 .thumb + 5133 .thumb_func + 5135 HAL_TIMEx_ConfigCommutEvent_IT: + 5136 .LFB157: +1839:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1840:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** +1841:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief Configure the TIM commutation event sequence with interrupt. +1842:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @note This function is mandatory to use the commutation event in order to +1843:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * update the configuration at each commutation detection on the TRGI input of the Timer, +1844:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * the typical use of this feature is with the use of another Timer(interface Timer) +1845:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * configured in Hall sensor interface, this interface Timer will generate the +1846:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * commutation at its TRGO output (connected to Timer used in this function) each time +1847:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * the TI1 of the Interface Timer detect a commutation at its input TI1. +1848:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param htim TIM handle +1849:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall +1850:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * This parameter can be one of the following values: +1851:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TS_ITR0: Internal trigger 0 selected +1852:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TS_ITR1: Internal trigger 1 selected +1853:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TS_ITR2: Internal trigger 2 selected + ARM GAS /tmp/ccxRWv8k.s page 123 + + +1854:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TS_ITR3: Internal trigger 3 selected +1855:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TS_NONE: No trigger is needed +1856:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param CommutationSource the Commutation Event source +1857:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * This parameter can be one of the following values: +1858:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer +1859:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG +1860:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @retval HAL status +1861:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ +1862:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, +1863:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** uint32_t CommutationSource) +1864:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 5137 .loc 1 1864 1 + 5138 .cfi_startproc + 5139 @ args = 0, pretend = 0, frame = 16 + 5140 @ frame_needed = 1, uses_anonymous_args = 0 + 5141 @ link register save eliminated. + 5142 0000 80B4 push {r7} + 5143 .cfi_def_cfa_offset 4 + 5144 .cfi_offset 7, -4 + 5145 0002 85B0 sub sp, sp, #20 + 5146 .cfi_def_cfa_offset 24 + 5147 0004 00AF add r7, sp, #0 + 5148 .cfi_def_cfa_register 7 + 5149 0006 F860 str r0, [r7, #12] + 5150 0008 B960 str r1, [r7, #8] + 5151 000a 7A60 str r2, [r7, #4] +1865:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Check the parameters */ +1866:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); +1867:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); +1868:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1869:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_LOCK(htim); + 5152 .loc 1 1869 3 + 5153 000c FB68 ldr r3, [r7, #12] + 5154 000e 93F83C30 ldrb r3, [r3, #60] @ zero_extendqisi2 + 5155 0012 012B cmp r3, #1 + 5156 0014 01D1 bne .L347 + 5157 .loc 1 1869 3 is_stmt 0 discriminator 1 + 5158 0016 0223 movs r3, #2 + 5159 .loc 1 1869 3 + 5160 0018 4CE0 b .L348 + 5161 .L347: + 5162 .loc 1 1869 3 discriminator 2 + 5163 001a FB68 ldr r3, [r7, #12] + 5164 001c 0122 movs r2, #1 + 5165 001e 83F83C20 strb r2, [r3, #60] +1870:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1871:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + 5166 .loc 1 1871 6 is_stmt 1 + 5167 0022 BB68 ldr r3, [r7, #8] + 5168 0024 002B cmp r3, #0 + 5169 0026 08D0 beq .L349 + 5170 .loc 1 1871 37 discriminator 1 + 5171 0028 BB68 ldr r3, [r7, #8] + 5172 002a 102B cmp r3, #16 + 5173 002c 05D0 beq .L349 + 5174 .loc 1 1871 70 discriminator 2 + 5175 002e BB68 ldr r3, [r7, #8] + ARM GAS /tmp/ccxRWv8k.s page 124 + + + 5176 0030 202B cmp r3, #32 + 5177 0032 02D0 beq .L349 +1872:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + 5178 .loc 1 1872 37 + 5179 0034 BB68 ldr r3, [r7, #8] + 5180 0036 302B cmp r3, #48 + 5181 0038 0FD1 bne .L350 + 5182 .L349: +1873:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +1874:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Select the Input trigger */ +1875:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->Instance->SMCR &= ~TIM_SMCR_TS; + 5183 .loc 1 1875 9 + 5184 003a FB68 ldr r3, [r7, #12] + 5185 003c 1B68 ldr r3, [r3] + 5186 .loc 1 1875 19 + 5187 003e 9A68 ldr r2, [r3, #8] + 5188 .loc 1 1875 9 + 5189 0040 FB68 ldr r3, [r7, #12] + 5190 0042 1B68 ldr r3, [r3] + 5191 .loc 1 1875 26 + 5192 0044 22F07002 bic r2, r2, #112 + 5193 0048 9A60 str r2, [r3, #8] +1876:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->Instance->SMCR |= InputTrigger; + 5194 .loc 1 1876 9 + 5195 004a FB68 ldr r3, [r7, #12] + 5196 004c 1B68 ldr r3, [r3] + 5197 .loc 1 1876 19 + 5198 004e 9968 ldr r1, [r3, #8] + 5199 .loc 1 1876 9 + 5200 0050 FB68 ldr r3, [r7, #12] + 5201 0052 1B68 ldr r3, [r3] + 5202 .loc 1 1876 26 + 5203 0054 BA68 ldr r2, [r7, #8] + 5204 0056 0A43 orrs r2, r2, r1 + 5205 0058 9A60 str r2, [r3, #8] + 5206 .L350: +1877:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +1878:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1879:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Select the Capture Compare preload feature */ +1880:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->Instance->CR2 |= TIM_CR2_CCPC; + 5207 .loc 1 1880 7 + 5208 005a FB68 ldr r3, [r7, #12] + 5209 005c 1B68 ldr r3, [r3] + 5210 .loc 1 1880 17 + 5211 005e 5A68 ldr r2, [r3, #4] + 5212 .loc 1 1880 7 + 5213 0060 FB68 ldr r3, [r7, #12] + 5214 0062 1B68 ldr r3, [r3] + 5215 .loc 1 1880 23 + 5216 0064 42F00102 orr r2, r2, #1 + 5217 0068 5A60 str r2, [r3, #4] +1881:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Select the Commutation event source */ +1882:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->Instance->CR2 &= ~TIM_CR2_CCUS; + 5218 .loc 1 1882 7 + 5219 006a FB68 ldr r3, [r7, #12] + 5220 006c 1B68 ldr r3, [r3] + 5221 .loc 1 1882 17 + ARM GAS /tmp/ccxRWv8k.s page 125 + + + 5222 006e 5A68 ldr r2, [r3, #4] + 5223 .loc 1 1882 7 + 5224 0070 FB68 ldr r3, [r7, #12] + 5225 0072 1B68 ldr r3, [r3] + 5226 .loc 1 1882 23 + 5227 0074 22F00402 bic r2, r2, #4 + 5228 0078 5A60 str r2, [r3, #4] +1883:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->Instance->CR2 |= CommutationSource; + 5229 .loc 1 1883 7 + 5230 007a FB68 ldr r3, [r7, #12] + 5231 007c 1B68 ldr r3, [r3] + 5232 .loc 1 1883 17 + 5233 007e 5968 ldr r1, [r3, #4] + 5234 .loc 1 1883 7 + 5235 0080 FB68 ldr r3, [r7, #12] + 5236 0082 1B68 ldr r3, [r3] + 5237 .loc 1 1883 23 + 5238 0084 7A68 ldr r2, [r7, #4] + 5239 0086 0A43 orrs r2, r2, r1 + 5240 0088 5A60 str r2, [r3, #4] +1884:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1885:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable Commutation DMA request */ +1886:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); + 5241 .loc 1 1886 3 + 5242 008a FB68 ldr r3, [r7, #12] + 5243 008c 1B68 ldr r3, [r3] + 5244 008e DA68 ldr r2, [r3, #12] + 5245 0090 FB68 ldr r3, [r7, #12] + 5246 0092 1B68 ldr r3, [r3] + 5247 0094 22F40052 bic r2, r2, #8192 + 5248 0098 DA60 str r2, [r3, #12] +1887:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1888:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the Commutation Interrupt */ +1889:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM); + 5249 .loc 1 1889 3 + 5250 009a FB68 ldr r3, [r7, #12] + 5251 009c 1B68 ldr r3, [r3] + 5252 009e DA68 ldr r2, [r3, #12] + 5253 00a0 FB68 ldr r3, [r7, #12] + 5254 00a2 1B68 ldr r3, [r3] + 5255 00a4 42F02002 orr r2, r2, #32 + 5256 00a8 DA60 str r2, [r3, #12] +1890:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1891:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_UNLOCK(htim); + 5257 .loc 1 1891 3 + 5258 00aa FB68 ldr r3, [r7, #12] + 5259 00ac 0022 movs r2, #0 + 5260 00ae 83F83C20 strb r2, [r3, #60] +1892:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1893:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return HAL_OK; + 5261 .loc 1 1893 10 + 5262 00b2 0023 movs r3, #0 + 5263 .L348: +1894:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 5264 .loc 1 1894 1 + 5265 00b4 1846 mov r0, r3 + 5266 00b6 1437 adds r7, r7, #20 + ARM GAS /tmp/ccxRWv8k.s page 126 + + + 5267 .cfi_def_cfa_offset 4 + 5268 00b8 BD46 mov sp, r7 + 5269 .cfi_def_cfa_register 13 + 5270 @ sp needed + 5271 00ba 5DF8047B ldr r7, [sp], #4 + 5272 .cfi_restore 7 + 5273 .cfi_def_cfa_offset 0 + 5274 00be 7047 bx lr + 5275 .cfi_endproc + 5276 .LFE157: + 5278 .section .text.HAL_TIMEx_ConfigCommutEvent_DMA,"ax",%progbits + 5279 .align 1 + 5280 .global HAL_TIMEx_ConfigCommutEvent_DMA + 5281 .syntax unified + 5282 .thumb + 5283 .thumb_func + 5285 HAL_TIMEx_ConfigCommutEvent_DMA: + 5286 .LFB158: +1895:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1896:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** +1897:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief Configure the TIM commutation event sequence with DMA. +1898:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @note This function is mandatory to use the commutation event in order to +1899:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * update the configuration at each commutation detection on the TRGI input of the Timer, +1900:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * the typical use of this feature is with the use of another Timer(interface Timer) +1901:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * configured in Hall sensor interface, this interface Timer will generate the +1902:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * commutation at its TRGO output (connected to Timer used in this function) each time +1903:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * the TI1 of the Interface Timer detect a commutation at its input TI1. +1904:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @note The user should configure the DMA in his own software, in This function only the COMDE b +1905:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param htim TIM handle +1906:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall +1907:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * This parameter can be one of the following values: +1908:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TS_ITR0: Internal trigger 0 selected +1909:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TS_ITR1: Internal trigger 1 selected +1910:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TS_ITR2: Internal trigger 2 selected +1911:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TS_ITR3: Internal trigger 3 selected +1912:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TS_NONE: No trigger is needed +1913:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param CommutationSource the Commutation Event source +1914:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * This parameter can be one of the following values: +1915:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer +1916:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG +1917:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @retval HAL status +1918:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ +1919:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, +1920:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** uint32_t CommutationSource) +1921:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 5287 .loc 1 1921 1 + 5288 .cfi_startproc + 5289 @ args = 0, pretend = 0, frame = 16 + 5290 @ frame_needed = 1, uses_anonymous_args = 0 + 5291 @ link register save eliminated. + 5292 0000 80B4 push {r7} + 5293 .cfi_def_cfa_offset 4 + 5294 .cfi_offset 7, -4 + 5295 0002 85B0 sub sp, sp, #20 + 5296 .cfi_def_cfa_offset 24 + 5297 0004 00AF add r7, sp, #0 + 5298 .cfi_def_cfa_register 7 + ARM GAS /tmp/ccxRWv8k.s page 127 + + + 5299 0006 F860 str r0, [r7, #12] + 5300 0008 B960 str r1, [r7, #8] + 5301 000a 7A60 str r2, [r7, #4] +1922:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Check the parameters */ +1923:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); +1924:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); +1925:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1926:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_LOCK(htim); + 5302 .loc 1 1926 3 + 5303 000c FB68 ldr r3, [r7, #12] + 5304 000e 93F83C30 ldrb r3, [r3, #60] @ zero_extendqisi2 + 5305 0012 012B cmp r3, #1 + 5306 0014 01D1 bne .L352 + 5307 .loc 1 1926 3 is_stmt 0 discriminator 1 + 5308 0016 0223 movs r3, #2 + 5309 .loc 1 1926 3 + 5310 0018 58E0 b .L353 + 5311 .L352: + 5312 .loc 1 1926 3 discriminator 2 + 5313 001a FB68 ldr r3, [r7, #12] + 5314 001c 0122 movs r2, #1 + 5315 001e 83F83C20 strb r2, [r3, #60] +1927:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1928:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + 5316 .loc 1 1928 6 is_stmt 1 + 5317 0022 BB68 ldr r3, [r7, #8] + 5318 0024 002B cmp r3, #0 + 5319 0026 08D0 beq .L354 + 5320 .loc 1 1928 37 discriminator 1 + 5321 0028 BB68 ldr r3, [r7, #8] + 5322 002a 102B cmp r3, #16 + 5323 002c 05D0 beq .L354 + 5324 .loc 1 1928 70 discriminator 2 + 5325 002e BB68 ldr r3, [r7, #8] + 5326 0030 202B cmp r3, #32 + 5327 0032 02D0 beq .L354 +1929:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + 5328 .loc 1 1929 37 + 5329 0034 BB68 ldr r3, [r7, #8] + 5330 0036 302B cmp r3, #48 + 5331 0038 0FD1 bne .L355 + 5332 .L354: +1930:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +1931:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Select the Input trigger */ +1932:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->Instance->SMCR &= ~TIM_SMCR_TS; + 5333 .loc 1 1932 9 + 5334 003a FB68 ldr r3, [r7, #12] + 5335 003c 1B68 ldr r3, [r3] + 5336 .loc 1 1932 19 + 5337 003e 9A68 ldr r2, [r3, #8] + 5338 .loc 1 1932 9 + 5339 0040 FB68 ldr r3, [r7, #12] + 5340 0042 1B68 ldr r3, [r3] + 5341 .loc 1 1932 26 + 5342 0044 22F07002 bic r2, r2, #112 + 5343 0048 9A60 str r2, [r3, #8] +1933:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->Instance->SMCR |= InputTrigger; + ARM GAS /tmp/ccxRWv8k.s page 128 + + + 5344 .loc 1 1933 9 + 5345 004a FB68 ldr r3, [r7, #12] + 5346 004c 1B68 ldr r3, [r3] + 5347 .loc 1 1933 19 + 5348 004e 9968 ldr r1, [r3, #8] + 5349 .loc 1 1933 9 + 5350 0050 FB68 ldr r3, [r7, #12] + 5351 0052 1B68 ldr r3, [r3] + 5352 .loc 1 1933 26 + 5353 0054 BA68 ldr r2, [r7, #8] + 5354 0056 0A43 orrs r2, r2, r1 + 5355 0058 9A60 str r2, [r3, #8] + 5356 .L355: +1934:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +1935:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1936:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Select the Capture Compare preload feature */ +1937:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->Instance->CR2 |= TIM_CR2_CCPC; + 5357 .loc 1 1937 7 + 5358 005a FB68 ldr r3, [r7, #12] + 5359 005c 1B68 ldr r3, [r3] + 5360 .loc 1 1937 17 + 5361 005e 5A68 ldr r2, [r3, #4] + 5362 .loc 1 1937 7 + 5363 0060 FB68 ldr r3, [r7, #12] + 5364 0062 1B68 ldr r3, [r3] + 5365 .loc 1 1937 23 + 5366 0064 42F00102 orr r2, r2, #1 + 5367 0068 5A60 str r2, [r3, #4] +1938:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Select the Commutation event source */ +1939:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->Instance->CR2 &= ~TIM_CR2_CCUS; + 5368 .loc 1 1939 7 + 5369 006a FB68 ldr r3, [r7, #12] + 5370 006c 1B68 ldr r3, [r3] + 5371 .loc 1 1939 17 + 5372 006e 5A68 ldr r2, [r3, #4] + 5373 .loc 1 1939 7 + 5374 0070 FB68 ldr r3, [r7, #12] + 5375 0072 1B68 ldr r3, [r3] + 5376 .loc 1 1939 23 + 5377 0074 22F00402 bic r2, r2, #4 + 5378 0078 5A60 str r2, [r3, #4] +1940:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->Instance->CR2 |= CommutationSource; + 5379 .loc 1 1940 7 + 5380 007a FB68 ldr r3, [r7, #12] + 5381 007c 1B68 ldr r3, [r3] + 5382 .loc 1 1940 17 + 5383 007e 5968 ldr r1, [r3, #4] + 5384 .loc 1 1940 7 + 5385 0080 FB68 ldr r3, [r7, #12] + 5386 0082 1B68 ldr r3, [r3] + 5387 .loc 1 1940 23 + 5388 0084 7A68 ldr r2, [r7, #4] + 5389 0086 0A43 orrs r2, r2, r1 + 5390 0088 5A60 str r2, [r3, #4] +1941:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1942:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the Commutation DMA Request */ +1943:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Set the DMA Commutation Callback */ + ARM GAS /tmp/ccxRWv8k.s page 129 + + +1944:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + 5391 .loc 1 1944 13 + 5392 008a FB68 ldr r3, [r7, #12] + 5393 008c 5B6B ldr r3, [r3, #52] + 5394 .loc 1 1944 56 + 5395 008e 124A ldr r2, .L356 + 5396 0090 9A62 str r2, [r3, #40] +1945:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + 5397 .loc 1 1945 13 + 5398 0092 FB68 ldr r3, [r7, #12] + 5399 0094 5B6B ldr r3, [r3, #52] + 5400 .loc 1 1945 60 + 5401 0096 114A ldr r2, .L356+4 + 5402 0098 DA62 str r2, [r3, #44] +1946:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Set the DMA error callback */ +1947:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError; + 5403 .loc 1 1947 13 + 5404 009a FB68 ldr r3, [r7, #12] + 5405 009c 5B6B ldr r3, [r3, #52] + 5406 .loc 1 1947 57 + 5407 009e 104A ldr r2, .L356+8 + 5408 00a0 1A63 str r2, [r3, #48] +1948:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1949:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Disable Commutation Interrupt */ +1950:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); + 5409 .loc 1 1950 3 + 5410 00a2 FB68 ldr r3, [r7, #12] + 5411 00a4 1B68 ldr r3, [r3] + 5412 00a6 DA68 ldr r2, [r3, #12] + 5413 00a8 FB68 ldr r3, [r7, #12] + 5414 00aa 1B68 ldr r3, [r3] + 5415 00ac 22F02002 bic r2, r2, #32 + 5416 00b0 DA60 str r2, [r3, #12] +1951:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1952:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Enable the Commutation DMA Request */ +1953:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM); + 5417 .loc 1 1953 3 + 5418 00b2 FB68 ldr r3, [r7, #12] + 5419 00b4 1B68 ldr r3, [r3] + 5420 00b6 DA68 ldr r2, [r3, #12] + 5421 00b8 FB68 ldr r3, [r7, #12] + 5422 00ba 1B68 ldr r3, [r3] + 5423 00bc 42F40052 orr r2, r2, #8192 + 5424 00c0 DA60 str r2, [r3, #12] +1954:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1955:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_UNLOCK(htim); + 5425 .loc 1 1955 3 + 5426 00c2 FB68 ldr r3, [r7, #12] + 5427 00c4 0022 movs r2, #0 + 5428 00c6 83F83C20 strb r2, [r3, #60] +1956:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1957:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return HAL_OK; + 5429 .loc 1 1957 10 + 5430 00ca 0023 movs r3, #0 + 5431 .L353: +1958:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 5432 .loc 1 1958 1 + ARM GAS /tmp/ccxRWv8k.s page 130 + + + 5433 00cc 1846 mov r0, r3 + 5434 00ce 1437 adds r7, r7, #20 + 5435 .cfi_def_cfa_offset 4 + 5436 00d0 BD46 mov sp, r7 + 5437 .cfi_def_cfa_register 13 + 5438 @ sp needed + 5439 00d2 5DF8047B ldr r7, [sp], #4 + 5440 .cfi_restore 7 + 5441 .cfi_def_cfa_offset 0 + 5442 00d6 7047 bx lr + 5443 .L357: + 5444 .align 2 + 5445 .L356: + 5446 00d8 00000000 .word TIMEx_DMACommutationCplt + 5447 00dc 00000000 .word TIMEx_DMACommutationHalfCplt + 5448 00e0 00000000 .word TIM_DMAError + 5449 .cfi_endproc + 5450 .LFE158: + 5452 .section .text.HAL_TIMEx_MasterConfigSynchronization,"ax",%progbits + 5453 .align 1 + 5454 .global HAL_TIMEx_MasterConfigSynchronization + 5455 .syntax unified + 5456 .thumb + 5457 .thumb_func + 5459 HAL_TIMEx_MasterConfigSynchronization: + 5460 .LFB159: +1959:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1960:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** +1961:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief Configures the TIM in master mode. +1962:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param htim TIM handle. +1963:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that +1964:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * contains the selected trigger output (TRGO) and the Master/Slave +1965:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * mode. +1966:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @retval HAL status +1967:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ +1968:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, +1969:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** const TIM_MasterConfigTypeDef *sMasterConfi +1970:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 5461 .loc 1 1970 1 + 5462 .cfi_startproc + 5463 @ args = 0, pretend = 0, frame = 16 + 5464 @ frame_needed = 1, uses_anonymous_args = 0 + 5465 @ link register save eliminated. + 5466 0000 80B4 push {r7} + 5467 .cfi_def_cfa_offset 4 + 5468 .cfi_offset 7, -4 + 5469 0002 85B0 sub sp, sp, #20 + 5470 .cfi_def_cfa_offset 24 + 5471 0004 00AF add r7, sp, #0 + 5472 .cfi_def_cfa_register 7 + 5473 0006 7860 str r0, [r7, #4] + 5474 0008 3960 str r1, [r7] +1971:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** uint32_t tmpcr2; +1972:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** uint32_t tmpsmcr; +1973:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1974:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Check the parameters */ +1975:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); + ARM GAS /tmp/ccxRWv8k.s page 131 + + +1976:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); +1977:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); +1978:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1979:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Check input state */ +1980:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_LOCK(htim); + 5475 .loc 1 1980 3 + 5476 000a 7B68 ldr r3, [r7, #4] + 5477 000c 93F83C30 ldrb r3, [r3, #60] @ zero_extendqisi2 + 5478 0010 012B cmp r3, #1 + 5479 0012 01D1 bne .L359 + 5480 .loc 1 1980 3 is_stmt 0 discriminator 1 + 5481 0014 0223 movs r3, #2 + 5482 .loc 1 1980 3 + 5483 0016 59E0 b .L360 + 5484 .L359: + 5485 .loc 1 1980 3 discriminator 2 + 5486 0018 7B68 ldr r3, [r7, #4] + 5487 001a 0122 movs r2, #1 + 5488 001c 83F83C20 strb r2, [r3, #60] +1981:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1982:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Change the handler state */ +1983:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->State = HAL_TIM_STATE_BUSY; + 5489 .loc 1 1983 15 is_stmt 1 + 5490 0020 7B68 ldr r3, [r7, #4] + 5491 0022 0222 movs r2, #2 + 5492 0024 83F83D20 strb r2, [r3, #61] +1984:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1985:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Get the TIMx CR2 register value */ +1986:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** tmpcr2 = htim->Instance->CR2; + 5493 .loc 1 1986 16 + 5494 0028 7B68 ldr r3, [r7, #4] + 5495 002a 1B68 ldr r3, [r3] + 5496 .loc 1 1986 10 + 5497 002c 5B68 ldr r3, [r3, #4] + 5498 002e FB60 str r3, [r7, #12] +1987:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1988:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Get the TIMx SMCR register value */ +1989:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** tmpsmcr = htim->Instance->SMCR; + 5499 .loc 1 1989 17 + 5500 0030 7B68 ldr r3, [r7, #4] + 5501 0032 1B68 ldr r3, [r3] + 5502 .loc 1 1989 11 + 5503 0034 9B68 ldr r3, [r3, #8] + 5504 0036 BB60 str r3, [r7, #8] +1990:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1991:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** #if defined(TIM_CR2_MMS2) +1992:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ +1993:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) + 5505 .loc 1 1993 7 + 5506 0038 7B68 ldr r3, [r7, #4] + 5507 003a 1B68 ldr r3, [r3] + 5508 .loc 1 1993 6 + 5509 003c 264A ldr r2, .L364 + 5510 003e 9342 cmp r3, r2 + 5511 0040 08D1 bne .L361 +1994:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +1995:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Check the parameters */ + ARM GAS /tmp/ccxRWv8k.s page 132 + + +1996:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); +1997:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +1998:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Clear the MMS2 bits */ +1999:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** tmpcr2 &= ~TIM_CR2_MMS2; + 5512 .loc 1 1999 12 + 5513 0042 FB68 ldr r3, [r7, #12] + 5514 0044 23F47003 bic r3, r3, #15728640 + 5515 0048 FB60 str r3, [r7, #12] +2000:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Select the TRGO2 source*/ +2001:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** tmpcr2 |= sMasterConfig->MasterOutputTrigger2; + 5516 .loc 1 2001 28 + 5517 004a 3B68 ldr r3, [r7] + 5518 004c 5B68 ldr r3, [r3, #4] + 5519 .loc 1 2001 12 + 5520 004e FA68 ldr r2, [r7, #12] + 5521 0050 1343 orrs r3, r3, r2 + 5522 0052 FB60 str r3, [r7, #12] + 5523 .L361: +2002:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +2003:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** #endif /* TIM_CR2_MMS2 */ +2004:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2005:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Reset the MMS Bits */ +2006:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** tmpcr2 &= ~TIM_CR2_MMS; + 5524 .loc 1 2006 10 + 5525 0054 FB68 ldr r3, [r7, #12] + 5526 0056 23F07003 bic r3, r3, #112 + 5527 005a FB60 str r3, [r7, #12] +2007:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Select the TRGO source */ +2008:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** tmpcr2 |= sMasterConfig->MasterOutputTrigger; + 5528 .loc 1 2008 27 + 5529 005c 3B68 ldr r3, [r7] + 5530 005e 1B68 ldr r3, [r3] + 5531 .loc 1 2008 10 + 5532 0060 FA68 ldr r2, [r7, #12] + 5533 0062 1343 orrs r3, r3, r2 + 5534 0064 FB60 str r3, [r7, #12] +2009:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2010:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Update TIMx CR2 */ +2011:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->Instance->CR2 = tmpcr2; + 5535 .loc 1 2011 7 + 5536 0066 7B68 ldr r3, [r7, #4] + 5537 0068 1B68 ldr r3, [r3] + 5538 .loc 1 2011 23 + 5539 006a FA68 ldr r2, [r7, #12] + 5540 006c 5A60 str r2, [r3, #4] +2012:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2013:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + 5541 .loc 1 2013 7 + 5542 006e 7B68 ldr r3, [r7, #4] + 5543 0070 1B68 ldr r3, [r3] + 5544 .loc 1 2013 6 + 5545 0072 194A ldr r2, .L364 + 5546 0074 9342 cmp r3, r2 + 5547 0076 13D0 beq .L362 + 5548 .loc 1 2013 7 discriminator 1 + 5549 0078 7B68 ldr r3, [r7, #4] + 5550 007a 1B68 ldr r3, [r3] + ARM GAS /tmp/ccxRWv8k.s page 133 + + + 5551 007c B3F1804F cmp r3, #1073741824 + 5552 0080 0ED0 beq .L362 + 5553 .loc 1 2013 7 is_stmt 0 discriminator 2 + 5554 0082 7B68 ldr r3, [r7, #4] + 5555 0084 1B68 ldr r3, [r3] + 5556 0086 154A ldr r2, .L364+4 + 5557 0088 9342 cmp r3, r2 + 5558 008a 09D0 beq .L362 + 5559 .loc 1 2013 7 discriminator 3 + 5560 008c 7B68 ldr r3, [r7, #4] + 5561 008e 1B68 ldr r3, [r3] + 5562 0090 134A ldr r2, .L364+8 + 5563 0092 9342 cmp r3, r2 + 5564 0094 04D0 beq .L362 + 5565 .loc 1 2013 7 discriminator 4 + 5566 0096 7B68 ldr r3, [r7, #4] + 5567 0098 1B68 ldr r3, [r3] + 5568 009a 124A ldr r2, .L364+12 + 5569 009c 9342 cmp r3, r2 + 5570 009e 0CD1 bne .L363 + 5571 .L362: +2014:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +2015:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Reset the MSM Bit */ +2016:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** tmpsmcr &= ~TIM_SMCR_MSM; + 5572 .loc 1 2016 13 is_stmt 1 + 5573 00a0 BB68 ldr r3, [r7, #8] + 5574 00a2 23F08003 bic r3, r3, #128 + 5575 00a6 BB60 str r3, [r7, #8] +2017:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Set master mode */ +2018:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** tmpsmcr |= sMasterConfig->MasterSlaveMode; + 5576 .loc 1 2018 29 + 5577 00a8 3B68 ldr r3, [r7] + 5578 00aa 9B68 ldr r3, [r3, #8] + 5579 .loc 1 2018 13 + 5580 00ac BA68 ldr r2, [r7, #8] + 5581 00ae 1343 orrs r3, r3, r2 + 5582 00b0 BB60 str r3, [r7, #8] +2019:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2020:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Update TIMx SMCR */ +2021:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->Instance->SMCR = tmpsmcr; + 5583 .loc 1 2021 9 + 5584 00b2 7B68 ldr r3, [r7, #4] + 5585 00b4 1B68 ldr r3, [r3] + 5586 .loc 1 2021 26 + 5587 00b6 BA68 ldr r2, [r7, #8] + 5588 00b8 9A60 str r2, [r3, #8] + 5589 .L363: +2022:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +2023:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2024:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Change the htim state */ +2025:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->State = HAL_TIM_STATE_READY; + 5590 .loc 1 2025 15 + 5591 00ba 7B68 ldr r3, [r7, #4] + 5592 00bc 0122 movs r2, #1 + 5593 00be 83F83D20 strb r2, [r3, #61] +2026:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2027:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_UNLOCK(htim); + ARM GAS /tmp/ccxRWv8k.s page 134 + + + 5594 .loc 1 2027 3 + 5595 00c2 7B68 ldr r3, [r7, #4] + 5596 00c4 0022 movs r2, #0 + 5597 00c6 83F83C20 strb r2, [r3, #60] +2028:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2029:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return HAL_OK; + 5598 .loc 1 2029 10 + 5599 00ca 0023 movs r3, #0 + 5600 .L360: +2030:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 5601 .loc 1 2030 1 + 5602 00cc 1846 mov r0, r3 + 5603 00ce 1437 adds r7, r7, #20 + 5604 .cfi_def_cfa_offset 4 + 5605 00d0 BD46 mov sp, r7 + 5606 .cfi_def_cfa_register 13 + 5607 @ sp needed + 5608 00d2 5DF8047B ldr r7, [sp], #4 + 5609 .cfi_restore 7 + 5610 .cfi_def_cfa_offset 0 + 5611 00d6 7047 bx lr + 5612 .L365: + 5613 .align 2 + 5614 .L364: + 5615 00d8 002C0140 .word 1073818624 + 5616 00dc 00040040 .word 1073742848 + 5617 00e0 00080040 .word 1073743872 + 5618 00e4 00400140 .word 1073823744 + 5619 .cfi_endproc + 5620 .LFE159: + 5622 .section .text.HAL_TIMEx_ConfigBreakDeadTime,"ax",%progbits + 5623 .align 1 + 5624 .global HAL_TIMEx_ConfigBreakDeadTime + 5625 .syntax unified + 5626 .thumb + 5627 .thumb_func + 5629 HAL_TIMEx_ConfigBreakDeadTime: + 5630 .LFB160: +2031:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2032:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** +2033:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State +2034:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * and the AOE(automatic output enable). +2035:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param htim TIM handle +2036:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that +2037:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * contains the BDTR Register configuration information for the TIM peripheral. +2038:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @note Interrupts can be generated when an active level is detected on the +2039:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * break input, the break 2 input or the system break input. Break +2040:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro. +2041:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @retval HAL status +2042:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ +2043:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, +2044:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTim +2045:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 5631 .loc 1 2045 1 + 5632 .cfi_startproc + 5633 @ args = 0, pretend = 0, frame = 16 + 5634 @ frame_needed = 1, uses_anonymous_args = 0 + ARM GAS /tmp/ccxRWv8k.s page 135 + + + 5635 @ link register save eliminated. + 5636 0000 80B4 push {r7} + 5637 .cfi_def_cfa_offset 4 + 5638 .cfi_offset 7, -4 + 5639 0002 85B0 sub sp, sp, #20 + 5640 .cfi_def_cfa_offset 24 + 5641 0004 00AF add r7, sp, #0 + 5642 .cfi_def_cfa_register 7 + 5643 0006 7860 str r0, [r7, #4] + 5644 0008 3960 str r1, [r7] +2046:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Keep this variable initialized to 0 as it is used to configure BDTR register */ +2047:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** uint32_t tmpbdtr = 0U; + 5645 .loc 1 2047 12 + 5646 000a 0023 movs r3, #0 + 5647 000c FB60 str r3, [r7, #12] +2048:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2049:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Check the parameters */ +2050:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); +2051:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode)); +2052:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode)); +2053:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel)); +2054:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime)); +2055:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState)); +2056:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); +2057:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** #if defined(TIM_BDTR_BKF) +2058:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter)); +2059:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** #endif /* TIM_BDTR_BKF */ +2060:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); +2061:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2062:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Check input state */ +2063:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_LOCK(htim); + 5648 .loc 1 2063 3 + 5649 000e 7B68 ldr r3, [r7, #4] + 5650 0010 93F83C30 ldrb r3, [r3, #60] @ zero_extendqisi2 + 5651 0014 012B cmp r3, #1 + 5652 0016 01D1 bne .L367 + 5653 .loc 1 2063 3 is_stmt 0 discriminator 1 + 5654 0018 0223 movs r3, #2 + 5655 .loc 1 2063 3 + 5656 001a 60E0 b .L368 + 5657 .L367: + 5658 .loc 1 2063 3 discriminator 2 + 5659 001c 7B68 ldr r3, [r7, #4] + 5660 001e 0122 movs r2, #1 + 5661 0020 83F83C20 strb r2, [r3, #60] +2064:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2065:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, +2066:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** the OSSI State, the dead time value and the Automatic Output Enable Bit */ +2067:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2068:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Set the BDTR bits */ +2069:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); + 5662 .loc 1 2069 3 is_stmt 1 + 5663 0024 FB68 ldr r3, [r7, #12] + 5664 0026 23F0FF02 bic r2, r3, #255 + 5665 002a 3B68 ldr r3, [r7] + 5666 002c DB68 ldr r3, [r3, #12] + 5667 002e 1343 orrs r3, r3, r2 + ARM GAS /tmp/ccxRWv8k.s page 136 + + + 5668 0030 FB60 str r3, [r7, #12] +2070:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); + 5669 .loc 1 2070 3 + 5670 0032 FB68 ldr r3, [r7, #12] + 5671 0034 23F44072 bic r2, r3, #768 + 5672 0038 3B68 ldr r3, [r7] + 5673 003a 9B68 ldr r3, [r3, #8] + 5674 003c 1343 orrs r3, r3, r2 + 5675 003e FB60 str r3, [r7, #12] +2071:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); + 5676 .loc 1 2071 3 + 5677 0040 FB68 ldr r3, [r7, #12] + 5678 0042 23F48062 bic r2, r3, #1024 + 5679 0046 3B68 ldr r3, [r7] + 5680 0048 5B68 ldr r3, [r3, #4] + 5681 004a 1343 orrs r3, r3, r2 + 5682 004c FB60 str r3, [r7, #12] +2072:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); + 5683 .loc 1 2072 3 + 5684 004e FB68 ldr r3, [r7, #12] + 5685 0050 23F40062 bic r2, r3, #2048 + 5686 0054 3B68 ldr r3, [r7] + 5687 0056 1B68 ldr r3, [r3] + 5688 0058 1343 orrs r3, r3, r2 + 5689 005a FB60 str r3, [r7, #12] +2073:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); + 5690 .loc 1 2073 3 + 5691 005c FB68 ldr r3, [r7, #12] + 5692 005e 23F48052 bic r2, r3, #4096 + 5693 0062 3B68 ldr r3, [r7] + 5694 0064 1B69 ldr r3, [r3, #16] + 5695 0066 1343 orrs r3, r3, r2 + 5696 0068 FB60 str r3, [r7, #12] +2074:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); + 5697 .loc 1 2074 3 + 5698 006a FB68 ldr r3, [r7, #12] + 5699 006c 23F40052 bic r2, r3, #8192 + 5700 0070 3B68 ldr r3, [r7] + 5701 0072 5B69 ldr r3, [r3, #20] + 5702 0074 1343 orrs r3, r3, r2 + 5703 0076 FB60 str r3, [r7, #12] +2075:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); + 5704 .loc 1 2075 3 + 5705 0078 FB68 ldr r3, [r7, #12] + 5706 007a 23F48042 bic r2, r3, #16384 + 5707 007e 3B68 ldr r3, [r7] + 5708 0080 9B6A ldr r3, [r3, #40] + 5709 0082 1343 orrs r3, r3, r2 + 5710 0084 FB60 str r3, [r7, #12] +2076:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** #if defined(TIM_BDTR_BKF) +2077:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); + 5711 .loc 1 2077 3 + 5712 0086 FB68 ldr r3, [r7, #12] + 5713 0088 23F47022 bic r2, r3, #983040 + 5714 008c 3B68 ldr r3, [r7] + 5715 008e 9B69 ldr r3, [r3, #24] + 5716 0090 1B04 lsls r3, r3, #16 + ARM GAS /tmp/ccxRWv8k.s page 137 + + + 5717 0092 1343 orrs r3, r3, r2 + 5718 0094 FB60 str r3, [r7, #12] +2078:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** #endif /* TIM_BDTR_BKF */ +2079:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2080:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** #if defined(TIM_BDTR_BK2E) +2081:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) + 5719 .loc 1 2081 7 + 5720 0096 7B68 ldr r3, [r7, #4] + 5721 0098 1B68 ldr r3, [r3] + 5722 .loc 1 2081 6 + 5723 009a 144A ldr r2, .L370 + 5724 009c 9342 cmp r3, r2 + 5725 009e 15D1 bne .L369 +2082:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +2083:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Check the parameters */ +2084:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State)); +2085:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity)); +2086:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter)); +2087:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2088:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Set the BREAK2 input related BDTR bits */ +2089:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos)); + 5726 .loc 1 2089 5 + 5727 00a0 FB68 ldr r3, [r7, #12] + 5728 00a2 23F47002 bic r2, r3, #15728640 + 5729 00a6 3B68 ldr r3, [r7] + 5730 00a8 5B6A ldr r3, [r3, #36] + 5731 00aa 1B05 lsls r3, r3, #20 + 5732 00ac 1343 orrs r3, r3, r2 + 5733 00ae FB60 str r3, [r7, #12] +2090:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); + 5734 .loc 1 2090 5 + 5735 00b0 FB68 ldr r3, [r7, #12] + 5736 00b2 23F08072 bic r2, r3, #16777216 + 5737 00b6 3B68 ldr r3, [r7] + 5738 00b8 DB69 ldr r3, [r3, #28] + 5739 00ba 1343 orrs r3, r3, r2 + 5740 00bc FB60 str r3, [r7, #12] +2091:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); + 5741 .loc 1 2091 5 + 5742 00be FB68 ldr r3, [r7, #12] + 5743 00c0 23F00072 bic r2, r3, #33554432 + 5744 00c4 3B68 ldr r3, [r7] + 5745 00c6 1B6A ldr r3, [r3, #32] + 5746 00c8 1343 orrs r3, r3, r2 + 5747 00ca FB60 str r3, [r7, #12] + 5748 .L369: +2092:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +2093:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** #endif /* TIM_BDTR_BK2E */ +2094:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2095:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Set TIMx_BDTR */ +2096:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->Instance->BDTR = tmpbdtr; + 5749 .loc 1 2096 7 + 5750 00cc 7B68 ldr r3, [r7, #4] + 5751 00ce 1B68 ldr r3, [r3] + 5752 .loc 1 2096 24 + 5753 00d0 FA68 ldr r2, [r7, #12] + 5754 00d2 5A64 str r2, [r3, #68] + ARM GAS /tmp/ccxRWv8k.s page 138 + + +2097:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2098:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_UNLOCK(htim); + 5755 .loc 1 2098 3 + 5756 00d4 7B68 ldr r3, [r7, #4] + 5757 00d6 0022 movs r2, #0 + 5758 00d8 83F83C20 strb r2, [r3, #60] +2099:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return HAL_OK; + 5759 .loc 1 2100 10 + 5760 00dc 0023 movs r3, #0 + 5761 .L368: +2101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 5762 .loc 1 2101 1 + 5763 00de 1846 mov r0, r3 + 5764 00e0 1437 adds r7, r7, #20 + 5765 .cfi_def_cfa_offset 4 + 5766 00e2 BD46 mov sp, r7 + 5767 .cfi_def_cfa_register 13 + 5768 @ sp needed + 5769 00e4 5DF8047B ldr r7, [sp], #4 + 5770 .cfi_restore 7 + 5771 .cfi_def_cfa_offset 0 + 5772 00e8 7047 bx lr + 5773 .L371: + 5774 00ea 00BF .align 2 + 5775 .L370: + 5776 00ec 002C0140 .word 1073818624 + 5777 .cfi_endproc + 5778 .LFE160: + 5780 .section .text.HAL_TIMEx_RemapConfig,"ax",%progbits + 5781 .align 1 + 5782 .global HAL_TIMEx_RemapConfig + 5783 .syntax unified + 5784 .thumb + 5785 .thumb_func + 5787 HAL_TIMEx_RemapConfig: + 5788 .LFB161: +2102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** +2104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief Configures the TIMx Remapping input capabilities. +2105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param htim TIM handle. +2106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param Remap specifies the TIM remapping source. +2107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** @if STM32F301x8 +2108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * For TIM1, the parameter can have the following values: +2109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any AWD (analog watchdog) +2110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TIM1_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1 +2111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TIM1_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2 +2112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TIM1_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD2 +2113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** @elseif STM32F303xE +2114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * For TIM1, the parameter is a combination of 2 fields (field1 | field2): +2115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * +2116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * field1 can have the following values: +2117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any AWD (analog watchdog) +2118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TIM1_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1 +2119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TIM1_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2 +2120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TIM1_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD2 +2121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * + ARM GAS /tmp/ccxRWv8k.s page 139 + + +2122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * field2 can have the following values: +2123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TIM1_ADC4_NONE : TIM1_ETR is not connected to any AWD (analog watchdog) +2124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TIM1_ADC4_AWD1: TIM1_ETR is connected to ADC4 AWD1 +2125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TIM1_ADC4_AWD2: TIM1_ETR is connected to ADC4 AWD2 +2126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TIM1_ADC4_AWD3: TIM1_ETR is connected to ADC4 AWD3 +2127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** @elseif STM32F334x8 +2128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * For TIM1, the parameter is a combination of 2 fields (field1 | field2): +2129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * +2130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * field1 can have the following values: +2131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any AWD (analog watchdog) +2132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TIM1_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1 +2133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TIM1_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2 +2134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TIM1_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD2 +2135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * +2136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * field2 can have the following values: +2137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TIM1_ADC2_NONE : TIM1_ETR is not connected to any AWD (analog watchdog) +2138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TIM1_ADC2_AWD1: TIM1_ETR is connected to ADC2 AWD1 +2139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TIM1_ADC2_AWD2: TIM1_ETR is connected to ADC2 AWD2 +2140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TIM1_ADC2_AWD3: TIM1_ETR is connected to ADC2 AWD3 +2141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** @endif +2142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** @if STM32F303xE +2143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * For TIM8, the parameter is a combination of 2 fields (field1 | field2): +2144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * +2145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * field1 can have the following values: +2146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TIM8_ADC2_NONE: TIM1_ETR is not connected to any AWD (analog watchdog) +2147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TIM8_ADC2_AWD1: TIM1_ETR is connected to ADC2 AWD1 +2148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TIM8_ADC2_AWD2: TIM1_ETR is connected to ADC2 AWD2 +2149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TIM8_ADC2_AWD3: TIM1_ETR is connected to ADC2 AWD2 +2150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * +2151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * field2 can have the following values: +2152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TIM8_ADC3_NONE : TIM1_ETR is not connected to any AWD (analog watchdog) +2153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TIM8_ADC3_AWD1: TIM1_ETR is connected to ADC3 AWD1 +2154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TIM8_ADC3_AWD2: TIM1_ETR is connected to ADC3 AWD2 +2155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TIM8_ADC3_AWD3: TIM1_ETR is connected to ADC3 AWD3 +2156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** @endif +2157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** @if STM32F373xC +2158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * For TIM14, the parameter can have the following values: +2159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TIM14_GPIO: TIM14 TI1 is connected to GPIO +2160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TIM14_RTC: TIM14 TI1 is connected to RTC_clock +2161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TIM14_HSE: TIM14 TI1 is connected to HSE/32 +2162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TIM14_MCO: TIM14 TI1 is connected to MCO +2163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** @else +2164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * For TIM16, the parameter can have the following values: +2165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TIM16_GPIO: TIM16 TI1 is connected to GPIO +2166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TIM16_RTC: TIM16 TI1 is connected to RTC_clock +2167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TIM16_HSE: TIM16 TI1 is connected to HSE/32 +2168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TIM16_MCO: TIM16 TI1 is connected to MCO +2169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** @endif +2170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** @if STM32F303xE +2171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * For TIM20, the parameter is a combination of 2 fields (field1 | field2): +2172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * +2173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * field1 can have the following values: +2174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TIM20_ADC3_NONE: TIM1_ETR is not connected to any AWD (analog watchdog) +2175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TIM20_ADC3_AWD1: TIM1_ETR is connected to ADC3 AWD1 +2176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TIM20_ADC3_AWD2: TIM1_ETR is connected to ADC3 AWD2 +2177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TIM20_ADC3_AWD3: TIM1_ETR is connected to ADC3 AWD2 +2178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * + ARM GAS /tmp/ccxRWv8k.s page 140 + + +2179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * field2 can have the following values: +2180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TIM20_ADC4_NONE : TIM1_ETR is not connected to any AWD (analog watchdog) +2181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TIM20_ADC4_AWD1: TIM1_ETR is connected to ADC4 AWD1 +2182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TIM20_ADC4_AWD2: TIM1_ETR is connected to ADC4 AWD2 +2183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_TIM20_ADC4_AWD3: TIM1_ETR is connected to ADC4 AWD3 +2184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** @endif +2185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * +2186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @retval HAL status +2187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ +2188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) +2189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 5789 .loc 1 2189 1 + 5790 .cfi_startproc + 5791 @ args = 0, pretend = 0, frame = 8 + 5792 @ frame_needed = 1, uses_anonymous_args = 0 + 5793 @ link register save eliminated. + 5794 0000 80B4 push {r7} + 5795 .cfi_def_cfa_offset 4 + 5796 .cfi_offset 7, -4 + 5797 0002 83B0 sub sp, sp, #12 + 5798 .cfi_def_cfa_offset 16 + 5799 0004 00AF add r7, sp, #0 + 5800 .cfi_def_cfa_register 7 + 5801 0006 7860 str r0, [r7, #4] + 5802 0008 3960 str r1, [r7] +2190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Check parameters */ +2192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_REMAP(htim->Instance, Remap)); +2193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_LOCK(htim); + 5803 .loc 1 2194 3 + 5804 000a 7B68 ldr r3, [r7, #4] + 5805 000c 93F83C30 ldrb r3, [r3, #60] @ zero_extendqisi2 + 5806 0010 012B cmp r3, #1 + 5807 0012 01D1 bne .L373 + 5808 .loc 1 2194 3 is_stmt 0 discriminator 1 + 5809 0014 0223 movs r3, #2 + 5810 .loc 1 2194 3 + 5811 0016 0CE0 b .L374 + 5812 .L373: + 5813 .loc 1 2194 3 discriminator 2 + 5814 0018 7B68 ldr r3, [r7, #4] + 5815 001a 0122 movs r2, #1 + 5816 001c 83F83C20 strb r2, [r3, #60] +2195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Set the Timer remapping configuration */ +2197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** WRITE_REG(htim->Instance->OR, Remap); + 5817 .loc 1 2197 3 is_stmt 1 + 5818 0020 7B68 ldr r3, [r7, #4] + 5819 0022 1B68 ldr r3, [r3] + 5820 0024 3A68 ldr r2, [r7] + 5821 0026 1A65 str r2, [r3, #80] +2198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_UNLOCK(htim); + 5822 .loc 1 2199 3 + 5823 0028 7B68 ldr r3, [r7, #4] + 5824 002a 0022 movs r2, #0 + ARM GAS /tmp/ccxRWv8k.s page 141 + + + 5825 002c 83F83C20 strb r2, [r3, #60] +2200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return HAL_OK; + 5826 .loc 1 2201 10 + 5827 0030 0023 movs r3, #0 + 5828 .L374: +2202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 5829 .loc 1 2202 1 + 5830 0032 1846 mov r0, r3 + 5831 0034 0C37 adds r7, r7, #12 + 5832 .cfi_def_cfa_offset 4 + 5833 0036 BD46 mov sp, r7 + 5834 .cfi_def_cfa_register 13 + 5835 @ sp needed + 5836 0038 5DF8047B ldr r7, [sp], #4 + 5837 .cfi_restore 7 + 5838 .cfi_def_cfa_offset 0 + 5839 003c 7047 bx lr + 5840 .cfi_endproc + 5841 .LFE161: + 5843 .section .text.HAL_TIMEx_GroupChannel5,"ax",%progbits + 5844 .align 1 + 5845 .global HAL_TIMEx_GroupChannel5 + 5846 .syntax unified + 5847 .thumb + 5848 .thumb_func + 5850 HAL_TIMEx_GroupChannel5: + 5851 .LFB162: +2203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** #if defined(TIM_CCR5_CCR5) +2205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** +2206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief Group channel 5 and channel 1, 2 or 3 +2207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param htim TIM handle. +2208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param Channels specifies the reference signal(s) the OC5REF is combined with. +2209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * This parameter can be any combination of the following values: +2210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC +2211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF +2212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF +2213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF +2214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @retval HAL status +2215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ +2216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels) +2217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 5852 .loc 1 2217 1 + 5853 .cfi_startproc + 5854 @ args = 0, pretend = 0, frame = 8 + 5855 @ frame_needed = 1, uses_anonymous_args = 0 + 5856 @ link register save eliminated. + 5857 0000 80B4 push {r7} + 5858 .cfi_def_cfa_offset 4 + 5859 .cfi_offset 7, -4 + 5860 0002 83B0 sub sp, sp, #12 + 5861 .cfi_def_cfa_offset 16 + 5862 0004 00AF add r7, sp, #0 + 5863 .cfi_def_cfa_register 7 + 5864 0006 7860 str r0, [r7, #4] + 5865 0008 3960 str r1, [r7] + ARM GAS /tmp/ccxRWv8k.s page 142 + + +2218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Check parameters */ +2219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance)); +2220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_GROUPCH5(Channels)); +2221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Process Locked */ +2223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_LOCK(htim); + 5866 .loc 1 2223 3 + 5867 000a 7B68 ldr r3, [r7, #4] + 5868 000c 93F83C30 ldrb r3, [r3, #60] @ zero_extendqisi2 + 5869 0010 012B cmp r3, #1 + 5870 0012 01D1 bne .L376 + 5871 .loc 1 2223 3 is_stmt 0 discriminator 1 + 5872 0014 0223 movs r3, #2 + 5873 .loc 1 2223 3 + 5874 0016 20E0 b .L377 + 5875 .L376: + 5876 .loc 1 2223 3 discriminator 2 + 5877 0018 7B68 ldr r3, [r7, #4] + 5878 001a 0122 movs r2, #1 + 5879 001c 83F83C20 strb r2, [r3, #60] +2224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->State = HAL_TIM_STATE_BUSY; + 5880 .loc 1 2225 15 is_stmt 1 + 5881 0020 7B68 ldr r3, [r7, #4] + 5882 0022 0222 movs r2, #2 + 5883 0024 83F83D20 strb r2, [r3, #61] +2226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Clear GC5Cx bit fields */ +2228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1); + 5884 .loc 1 2228 7 + 5885 0028 7B68 ldr r3, [r7, #4] + 5886 002a 1B68 ldr r3, [r3] + 5887 .loc 1 2228 17 + 5888 002c 9A6D ldr r2, [r3, #88] + 5889 .loc 1 2228 7 + 5890 002e 7B68 ldr r3, [r7, #4] + 5891 0030 1B68 ldr r3, [r3] + 5892 .loc 1 2228 24 + 5893 0032 22F06042 bic r2, r2, #-536870912 + 5894 0036 9A65 str r2, [r3, #88] +2229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Set GC5Cx bit fields */ +2231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->Instance->CCR5 |= Channels; + 5895 .loc 1 2231 7 + 5896 0038 7B68 ldr r3, [r7, #4] + 5897 003a 1B68 ldr r3, [r3] + 5898 .loc 1 2231 17 + 5899 003c 996D ldr r1, [r3, #88] + 5900 .loc 1 2231 7 + 5901 003e 7B68 ldr r3, [r7, #4] + 5902 0040 1B68 ldr r3, [r3] + 5903 .loc 1 2231 24 + 5904 0042 3A68 ldr r2, [r7] + 5905 0044 0A43 orrs r2, r2, r1 + 5906 0046 9A65 str r2, [r3, #88] +2232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Change the htim state */ + ARM GAS /tmp/ccxRWv8k.s page 143 + + +2234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->State = HAL_TIM_STATE_READY; + 5907 .loc 1 2234 15 + 5908 0048 7B68 ldr r3, [r7, #4] + 5909 004a 0122 movs r2, #1 + 5910 004c 83F83D20 strb r2, [r3, #61] +2235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __HAL_UNLOCK(htim); + 5911 .loc 1 2236 3 + 5912 0050 7B68 ldr r3, [r7, #4] + 5913 0052 0022 movs r2, #0 + 5914 0054 83F83C20 strb r2, [r3, #60] +2237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return HAL_OK; + 5915 .loc 1 2238 10 + 5916 0058 0023 movs r3, #0 + 5917 .L377: +2239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 5918 .loc 1 2239 1 + 5919 005a 1846 mov r0, r3 + 5920 005c 0C37 adds r7, r7, #12 + 5921 .cfi_def_cfa_offset 4 + 5922 005e BD46 mov sp, r7 + 5923 .cfi_def_cfa_register 13 + 5924 @ sp needed + 5925 0060 5DF8047B ldr r7, [sp], #4 + 5926 .cfi_restore 7 + 5927 .cfi_def_cfa_offset 0 + 5928 0064 7047 bx lr + 5929 .cfi_endproc + 5930 .LFE162: + 5932 .section .text.HAL_TIMEx_CommutCallback,"ax",%progbits + 5933 .align 1 + 5934 .weak HAL_TIMEx_CommutCallback + 5935 .syntax unified + 5936 .thumb + 5937 .thumb_func + 5939 HAL_TIMEx_CommutCallback: + 5940 .LFB163: +2240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** #endif /* TIM_CCR5_CCR5 */ +2241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** +2243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @} +2244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ +2245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions +2247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief Extended Callbacks functions +2248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * +2249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** @verbatim +2250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** ============================================================================== +2251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** ##### Extended Callbacks functions ##### +2252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** ============================================================================== +2253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** [..] +2254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** This section provides Extended TIM callback functions: +2255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (+) Timer Commutation callback +2256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** (+) Timer Break callback +2257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** @endverbatim + ARM GAS /tmp/ccxRWv8k.s page 144 + + +2259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @{ +2260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ +2261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** +2263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief Hall commutation changed callback in non-blocking mode +2264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param htim TIM handle +2265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @retval None +2266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ +2267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) +2268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 5941 .loc 1 2268 1 + 5942 .cfi_startproc + 5943 @ args = 0, pretend = 0, frame = 8 + 5944 @ frame_needed = 1, uses_anonymous_args = 0 + 5945 @ link register save eliminated. + 5946 0000 80B4 push {r7} + 5947 .cfi_def_cfa_offset 4 + 5948 .cfi_offset 7, -4 + 5949 0002 83B0 sub sp, sp, #12 + 5950 .cfi_def_cfa_offset 16 + 5951 0004 00AF add r7, sp, #0 + 5952 .cfi_def_cfa_register 7 + 5953 0006 7860 str r0, [r7, #4] +2269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Prevent unused argument(s) compilation warning */ +2270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** UNUSED(htim); +2271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* NOTE : This function should not be modified, when the callback is needed, +2273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** the HAL_TIMEx_CommutCallback could be implemented in the user file +2274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ +2275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 5954 .loc 1 2275 1 + 5955 0008 00BF nop + 5956 000a 0C37 adds r7, r7, #12 + 5957 .cfi_def_cfa_offset 4 + 5958 000c BD46 mov sp, r7 + 5959 .cfi_def_cfa_register 13 + 5960 @ sp needed + 5961 000e 5DF8047B ldr r7, [sp], #4 + 5962 .cfi_restore 7 + 5963 .cfi_def_cfa_offset 0 + 5964 0012 7047 bx lr + 5965 .cfi_endproc + 5966 .LFE163: + 5968 .section .text.HAL_TIMEx_CommutHalfCpltCallback,"ax",%progbits + 5969 .align 1 + 5970 .weak HAL_TIMEx_CommutHalfCpltCallback + 5971 .syntax unified + 5972 .thumb + 5973 .thumb_func + 5975 HAL_TIMEx_CommutHalfCpltCallback: + 5976 .LFB164: +2276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** +2277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief Hall commutation changed half complete callback in non-blocking mode +2278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param htim TIM handle +2279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @retval None +2280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ +2281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim) + ARM GAS /tmp/ccxRWv8k.s page 145 + + +2282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 5977 .loc 1 2282 1 + 5978 .cfi_startproc + 5979 @ args = 0, pretend = 0, frame = 8 + 5980 @ frame_needed = 1, uses_anonymous_args = 0 + 5981 @ link register save eliminated. + 5982 0000 80B4 push {r7} + 5983 .cfi_def_cfa_offset 4 + 5984 .cfi_offset 7, -4 + 5985 0002 83B0 sub sp, sp, #12 + 5986 .cfi_def_cfa_offset 16 + 5987 0004 00AF add r7, sp, #0 + 5988 .cfi_def_cfa_register 7 + 5989 0006 7860 str r0, [r7, #4] +2283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Prevent unused argument(s) compilation warning */ +2284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** UNUSED(htim); +2285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* NOTE : This function should not be modified, when the callback is needed, +2287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file +2288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ +2289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 5990 .loc 1 2289 1 + 5991 0008 00BF nop + 5992 000a 0C37 adds r7, r7, #12 + 5993 .cfi_def_cfa_offset 4 + 5994 000c BD46 mov sp, r7 + 5995 .cfi_def_cfa_register 13 + 5996 @ sp needed + 5997 000e 5DF8047B ldr r7, [sp], #4 + 5998 .cfi_restore 7 + 5999 .cfi_def_cfa_offset 0 + 6000 0012 7047 bx lr + 6001 .cfi_endproc + 6002 .LFE164: + 6004 .section .text.HAL_TIMEx_BreakCallback,"ax",%progbits + 6005 .align 1 + 6006 .weak HAL_TIMEx_BreakCallback + 6007 .syntax unified + 6008 .thumb + 6009 .thumb_func + 6011 HAL_TIMEx_BreakCallback: + 6012 .LFB165: +2290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** +2292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief Hall Break detection callback in non-blocking mode +2293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param htim TIM handle +2294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @retval None +2295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ +2296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) +2297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 6013 .loc 1 2297 1 + 6014 .cfi_startproc + 6015 @ args = 0, pretend = 0, frame = 8 + 6016 @ frame_needed = 1, uses_anonymous_args = 0 + 6017 @ link register save eliminated. + 6018 0000 80B4 push {r7} + 6019 .cfi_def_cfa_offset 4 + ARM GAS /tmp/ccxRWv8k.s page 146 + + + 6020 .cfi_offset 7, -4 + 6021 0002 83B0 sub sp, sp, #12 + 6022 .cfi_def_cfa_offset 16 + 6023 0004 00AF add r7, sp, #0 + 6024 .cfi_def_cfa_register 7 + 6025 0006 7860 str r0, [r7, #4] +2298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Prevent unused argument(s) compilation warning */ +2299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** UNUSED(htim); +2300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* NOTE : This function should not be modified, when the callback is needed, +2302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** the HAL_TIMEx_BreakCallback could be implemented in the user file +2303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ +2304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 6026 .loc 1 2304 1 + 6027 0008 00BF nop + 6028 000a 0C37 adds r7, r7, #12 + 6029 .cfi_def_cfa_offset 4 + 6030 000c BD46 mov sp, r7 + 6031 .cfi_def_cfa_register 13 + 6032 @ sp needed + 6033 000e 5DF8047B ldr r7, [sp], #4 + 6034 .cfi_restore 7 + 6035 .cfi_def_cfa_offset 0 + 6036 0012 7047 bx lr + 6037 .cfi_endproc + 6038 .LFE165: + 6040 .section .text.HAL_TIMEx_Break2Callback,"ax",%progbits + 6041 .align 1 + 6042 .weak HAL_TIMEx_Break2Callback + 6043 .syntax unified + 6044 .thumb + 6045 .thumb_func + 6047 HAL_TIMEx_Break2Callback: + 6048 .LFB166: +2305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** #if defined(TIM_BDTR_BK2E) +2307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** +2308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief Hall Break2 detection callback in non blocking mode +2309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param htim: TIM handle +2310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @retval None +2311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ +2312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) +2313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 6049 .loc 1 2313 1 + 6050 .cfi_startproc + 6051 @ args = 0, pretend = 0, frame = 8 + 6052 @ frame_needed = 1, uses_anonymous_args = 0 + 6053 @ link register save eliminated. + 6054 0000 80B4 push {r7} + 6055 .cfi_def_cfa_offset 4 + 6056 .cfi_offset 7, -4 + 6057 0002 83B0 sub sp, sp, #12 + 6058 .cfi_def_cfa_offset 16 + 6059 0004 00AF add r7, sp, #0 + 6060 .cfi_def_cfa_register 7 + 6061 0006 7860 str r0, [r7, #4] +2314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Prevent unused argument(s) compilation warning */ + ARM GAS /tmp/ccxRWv8k.s page 147 + + +2315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** UNUSED(htim); +2316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* NOTE : This function Should not be modified, when the callback is needed, +2318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** the HAL_TIMEx_Break2Callback could be implemented in the user file +2319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ +2320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 6062 .loc 1 2320 1 + 6063 0008 00BF nop + 6064 000a 0C37 adds r7, r7, #12 + 6065 .cfi_def_cfa_offset 4 + 6066 000c BD46 mov sp, r7 + 6067 .cfi_def_cfa_register 13 + 6068 @ sp needed + 6069 000e 5DF8047B ldr r7, [sp], #4 + 6070 .cfi_restore 7 + 6071 .cfi_def_cfa_offset 0 + 6072 0012 7047 bx lr + 6073 .cfi_endproc + 6074 .LFE166: + 6076 .section .text.HAL_TIMEx_HallSensor_GetState,"ax",%progbits + 6077 .align 1 + 6078 .global HAL_TIMEx_HallSensor_GetState + 6079 .syntax unified + 6080 .thumb + 6081 .thumb_func + 6083 HAL_TIMEx_HallSensor_GetState: + 6084 .LFB167: +2321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** #endif /* TIM_BDTR_BK2E */ +2322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** +2323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @} +2324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ +2325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions +2327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief Extended Peripheral State functions +2328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * +2329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** @verbatim +2330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** ============================================================================== +2331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** ##### Extended Peripheral State functions ##### +2332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** ============================================================================== +2333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** [..] +2334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** This subsection permits to get in run-time the status of the peripheral +2335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** and the data flow. +2336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** @endverbatim +2338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @{ +2339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ +2340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** +2342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief Return the TIM Hall Sensor interface handle state. +2343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param htim TIM Hall Sensor handle +2344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @retval HAL state +2345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ +2346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim) +2347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 6085 .loc 1 2347 1 + 6086 .cfi_startproc + 6087 @ args = 0, pretend = 0, frame = 8 + ARM GAS /tmp/ccxRWv8k.s page 148 + + + 6088 @ frame_needed = 1, uses_anonymous_args = 0 + 6089 @ link register save eliminated. + 6090 0000 80B4 push {r7} + 6091 .cfi_def_cfa_offset 4 + 6092 .cfi_offset 7, -4 + 6093 0002 83B0 sub sp, sp, #12 + 6094 .cfi_def_cfa_offset 16 + 6095 0004 00AF add r7, sp, #0 + 6096 .cfi_def_cfa_register 7 + 6097 0006 7860 str r0, [r7, #4] +2348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return htim->State; + 6098 .loc 1 2348 14 + 6099 0008 7B68 ldr r3, [r7, #4] + 6100 000a 93F83D30 ldrb r3, [r3, #61] + 6101 000e DBB2 uxtb r3, r3 +2349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 6102 .loc 1 2349 1 + 6103 0010 1846 mov r0, r3 + 6104 0012 0C37 adds r7, r7, #12 + 6105 .cfi_def_cfa_offset 4 + 6106 0014 BD46 mov sp, r7 + 6107 .cfi_def_cfa_register 13 + 6108 @ sp needed + 6109 0016 5DF8047B ldr r7, [sp], #4 + 6110 .cfi_restore 7 + 6111 .cfi_def_cfa_offset 0 + 6112 001a 7047 bx lr + 6113 .cfi_endproc + 6114 .LFE167: + 6116 .section .text.HAL_TIMEx_GetChannelNState,"ax",%progbits + 6117 .align 1 + 6118 .global HAL_TIMEx_GetChannelNState + 6119 .syntax unified + 6120 .thumb + 6121 .thumb_func + 6123 HAL_TIMEx_GetChannelNState: + 6124 .LFB168: +2350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** +2352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief Return actual state of the TIM complementary channel. +2353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param htim TIM handle +2354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param ChannelN TIM Complementary channel +2355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * This parameter can be one of the following values: +2356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 +2357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 +2358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 +2359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @retval TIM Complementary channel state +2360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ +2361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t Cha +2362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 6125 .loc 1 2362 1 + 6126 .cfi_startproc + 6127 @ args = 0, pretend = 0, frame = 16 + 6128 @ frame_needed = 1, uses_anonymous_args = 0 + 6129 @ link register save eliminated. + 6130 0000 80B4 push {r7} + 6131 .cfi_def_cfa_offset 4 + ARM GAS /tmp/ccxRWv8k.s page 149 + + + 6132 .cfi_offset 7, -4 + 6133 0002 85B0 sub sp, sp, #20 + 6134 .cfi_def_cfa_offset 24 + 6135 0004 00AF add r7, sp, #0 + 6136 .cfi_def_cfa_register 7 + 6137 0006 7860 str r0, [r7, #4] + 6138 0008 3960 str r1, [r7] +2363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_TIM_ChannelStateTypeDef channel_state; +2364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Check the parameters */ +2366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN)); +2367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN); + 6139 .loc 1 2368 19 + 6140 000a 3B68 ldr r3, [r7] + 6141 000c 002B cmp r3, #0 + 6142 000e 04D1 bne .L385 + 6143 .loc 1 2368 19 is_stmt 0 discriminator 1 + 6144 0010 7B68 ldr r3, [r7, #4] + 6145 0012 93F84430 ldrb r3, [r3, #68] + 6146 0016 DBB2 uxtb r3, r3 + 6147 0018 13E0 b .L386 + 6148 .L385: + 6149 .loc 1 2368 19 discriminator 2 + 6150 001a 3B68 ldr r3, [r7] + 6151 001c 042B cmp r3, #4 + 6152 001e 04D1 bne .L387 + 6153 .loc 1 2368 19 discriminator 4 + 6154 0020 7B68 ldr r3, [r7, #4] + 6155 0022 93F84530 ldrb r3, [r3, #69] + 6156 0026 DBB2 uxtb r3, r3 + 6157 0028 0BE0 b .L386 + 6158 .L387: + 6159 .loc 1 2368 19 discriminator 5 + 6160 002a 3B68 ldr r3, [r7] + 6161 002c 082B cmp r3, #8 + 6162 002e 04D1 bne .L389 + 6163 .loc 1 2368 19 discriminator 7 + 6164 0030 7B68 ldr r3, [r7, #4] + 6165 0032 93F84630 ldrb r3, [r3, #70] + 6166 0036 DBB2 uxtb r3, r3 + 6167 0038 03E0 b .L386 + 6168 .L389: + 6169 .loc 1 2368 19 discriminator 8 + 6170 003a 7B68 ldr r3, [r7, #4] + 6171 003c 93F84730 ldrb r3, [r3, #71] + 6172 0040 DBB2 uxtb r3, r3 + 6173 .L386: + 6174 .loc 1 2368 17 is_stmt 1 discriminator 12 + 6175 0042 FB73 strb r3, [r7, #15] +2369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** return channel_state; + 6176 .loc 1 2370 10 + 6177 0044 FB7B ldrb r3, [r7, #15] @ zero_extendqisi2 +2371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 6178 .loc 1 2371 1 + 6179 0046 1846 mov r0, r3 + ARM GAS /tmp/ccxRWv8k.s page 150 + + + 6180 0048 1437 adds r7, r7, #20 + 6181 .cfi_def_cfa_offset 4 + 6182 004a BD46 mov sp, r7 + 6183 .cfi_def_cfa_register 13 + 6184 @ sp needed + 6185 004c 5DF8047B ldr r7, [sp], #4 + 6186 .cfi_restore 7 + 6187 .cfi_def_cfa_offset 0 + 6188 0050 7047 bx lr + 6189 .cfi_endproc + 6190 .LFE168: + 6192 .section .text.TIMEx_DMACommutationCplt,"ax",%progbits + 6193 .align 1 + 6194 .global TIMEx_DMACommutationCplt + 6195 .syntax unified + 6196 .thumb + 6197 .thumb_func + 6199 TIMEx_DMACommutationCplt: + 6200 .LFB169: +2372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** +2373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @} +2374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ +2375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** +2377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @} +2378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ +2379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Private functions ---------------------------------------------------------*/ +2381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** @defgroup TIMEx_Private_Functions TIM Extended Private Functions +2382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @{ +2383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ +2384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** +2386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief TIM DMA Commutation callback. +2387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param hdma pointer to DMA handle. +2388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @retval None +2389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ +2390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) +2391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 6201 .loc 1 2391 1 + 6202 .cfi_startproc + 6203 @ args = 0, pretend = 0, frame = 16 + 6204 @ frame_needed = 1, uses_anonymous_args = 0 + 6205 0000 80B5 push {r7, lr} + 6206 .cfi_def_cfa_offset 8 + 6207 .cfi_offset 7, -8 + 6208 .cfi_offset 14, -4 + 6209 0002 84B0 sub sp, sp, #16 + 6210 .cfi_def_cfa_offset 24 + 6211 0004 00AF add r7, sp, #0 + 6212 .cfi_def_cfa_register 7 + 6213 0006 7860 str r0, [r7, #4] +2392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + 6214 .loc 1 2392 22 + 6215 0008 7B68 ldr r3, [r7, #4] + 6216 000a 5B6A ldr r3, [r3, #36] + 6217 000c FB60 str r3, [r7, #12] + ARM GAS /tmp/ccxRWv8k.s page 151 + + +2393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Change the htim state */ +2395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->State = HAL_TIM_STATE_READY; + 6218 .loc 1 2395 15 + 6219 000e FB68 ldr r3, [r7, #12] + 6220 0010 0122 movs r2, #1 + 6221 0012 83F83D20 strb r2, [r3, #61] +2396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +2398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->CommutationCallback(htim); +2399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** #else +2400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_TIMEx_CommutCallback(htim); + 6222 .loc 1 2400 3 + 6223 0016 F868 ldr r0, [r7, #12] + 6224 0018 FFF7FEFF bl HAL_TIMEx_CommutCallback +2401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +2402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 6225 .loc 1 2402 1 + 6226 001c 00BF nop + 6227 001e 1037 adds r7, r7, #16 + 6228 .cfi_def_cfa_offset 8 + 6229 0020 BD46 mov sp, r7 + 6230 .cfi_def_cfa_register 13 + 6231 @ sp needed + 6232 0022 80BD pop {r7, pc} + 6233 .cfi_endproc + 6234 .LFE169: + 6236 .section .text.TIMEx_DMACommutationHalfCplt,"ax",%progbits + 6237 .align 1 + 6238 .global TIMEx_DMACommutationHalfCplt + 6239 .syntax unified + 6240 .thumb + 6241 .thumb_func + 6243 TIMEx_DMACommutationHalfCplt: + 6244 .LFB170: +2403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** +2405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief TIM DMA Commutation half complete callback. +2406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param hdma pointer to DMA handle. +2407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @retval None +2408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ +2409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma) +2410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 6245 .loc 1 2410 1 + 6246 .cfi_startproc + 6247 @ args = 0, pretend = 0, frame = 16 + 6248 @ frame_needed = 1, uses_anonymous_args = 0 + 6249 0000 80B5 push {r7, lr} + 6250 .cfi_def_cfa_offset 8 + 6251 .cfi_offset 7, -8 + 6252 .cfi_offset 14, -4 + 6253 0002 84B0 sub sp, sp, #16 + 6254 .cfi_def_cfa_offset 24 + 6255 0004 00AF add r7, sp, #0 + 6256 .cfi_def_cfa_register 7 + 6257 0006 7860 str r0, [r7, #4] +2411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + ARM GAS /tmp/ccxRWv8k.s page 152 + + + 6258 .loc 1 2411 22 + 6259 0008 7B68 ldr r3, [r7, #4] + 6260 000a 5B6A ldr r3, [r3, #36] + 6261 000c FB60 str r3, [r7, #12] +2412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Change the htim state */ +2414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->State = HAL_TIM_STATE_READY; + 6262 .loc 1 2414 15 + 6263 000e FB68 ldr r3, [r7, #12] + 6264 0010 0122 movs r2, #1 + 6265 0012 83F83D20 strb r2, [r3, #61] +2415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +2417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->CommutationHalfCpltCallback(htim); +2418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** #else +2419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_TIMEx_CommutHalfCpltCallback(htim); + 6266 .loc 1 2419 3 + 6267 0016 F868 ldr r0, [r7, #12] + 6268 0018 FFF7FEFF bl HAL_TIMEx_CommutHalfCpltCallback +2420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +2421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 6269 .loc 1 2421 1 + 6270 001c 00BF nop + 6271 001e 1037 adds r7, r7, #16 + 6272 .cfi_def_cfa_offset 8 + 6273 0020 BD46 mov sp, r7 + 6274 .cfi_def_cfa_register 13 + 6275 @ sp needed + 6276 0022 80BD pop {r7, pc} + 6277 .cfi_endproc + 6278 .LFE170: + 6280 .section .text.TIM_DMADelayPulseNCplt,"ax",%progbits + 6281 .align 1 + 6282 .syntax unified + 6283 .thumb + 6284 .thumb_func + 6286 TIM_DMADelayPulseNCplt: + 6287 .LFB171: +2422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** +2425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief TIM DMA Delay Pulse complete callback (complementary channel). +2426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param hdma pointer to DMA handle. +2427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @retval None +2428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ +2429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) +2430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 6288 .loc 1 2430 1 + 6289 .cfi_startproc + 6290 @ args = 0, pretend = 0, frame = 16 + 6291 @ frame_needed = 1, uses_anonymous_args = 0 + 6292 0000 80B5 push {r7, lr} + 6293 .cfi_def_cfa_offset 8 + 6294 .cfi_offset 7, -8 + 6295 .cfi_offset 14, -4 + 6296 0002 84B0 sub sp, sp, #16 + 6297 .cfi_def_cfa_offset 24 + ARM GAS /tmp/ccxRWv8k.s page 153 + + + 6298 0004 00AF add r7, sp, #0 + 6299 .cfi_def_cfa_register 7 + 6300 0006 7860 str r0, [r7, #4] +2431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + 6301 .loc 1 2431 22 + 6302 0008 7B68 ldr r3, [r7, #4] + 6303 000a 5B6A ldr r3, [r3, #36] + 6304 000c FB60 str r3, [r7, #12] +2432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + 6305 .loc 1 2433 25 + 6306 000e FB68 ldr r3, [r7, #12] + 6307 0010 5B6A ldr r3, [r3, #36] + 6308 .loc 1 2433 6 + 6309 0012 7A68 ldr r2, [r7, #4] + 6310 0014 9A42 cmp r2, r3 + 6311 0016 0BD1 bne .L395 +2434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +2435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + 6312 .loc 1 2435 19 + 6313 0018 FB68 ldr r3, [r7, #12] + 6314 001a 0122 movs r2, #1 + 6315 001c 1A77 strb r2, [r3, #28] +2436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (hdma->Init.Mode == DMA_NORMAL) + 6316 .loc 1 2437 19 + 6317 001e 7B68 ldr r3, [r7, #4] + 6318 0020 9B69 ldr r3, [r3, #24] + 6319 .loc 1 2437 8 + 6320 0022 002B cmp r3, #0 + 6321 0024 36D1 bne .L396 +2438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +2439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 6322 .loc 1 2439 7 + 6323 0026 FB68 ldr r3, [r7, #12] + 6324 0028 0122 movs r2, #1 + 6325 002a 83F84420 strb r2, [r3, #68] + 6326 002e 31E0 b .L396 + 6327 .L395: +2440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +2441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +2442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + 6328 .loc 1 2442 30 + 6329 0030 FB68 ldr r3, [r7, #12] + 6330 0032 9B6A ldr r3, [r3, #40] + 6331 .loc 1 2442 11 + 6332 0034 7A68 ldr r2, [r7, #4] + 6333 0036 9A42 cmp r2, r3 + 6334 0038 0BD1 bne .L397 +2443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +2444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + 6335 .loc 1 2444 19 + 6336 003a FB68 ldr r3, [r7, #12] + 6337 003c 0222 movs r2, #2 + 6338 003e 1A77 strb r2, [r3, #28] +2445:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2446:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (hdma->Init.Mode == DMA_NORMAL) + ARM GAS /tmp/ccxRWv8k.s page 154 + + + 6339 .loc 1 2446 19 + 6340 0040 7B68 ldr r3, [r7, #4] + 6341 0042 9B69 ldr r3, [r3, #24] + 6342 .loc 1 2446 8 + 6343 0044 002B cmp r3, #0 + 6344 0046 25D1 bne .L396 +2447:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +2448:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 6345 .loc 1 2448 7 + 6346 0048 FB68 ldr r3, [r7, #12] + 6347 004a 0122 movs r2, #1 + 6348 004c 83F84520 strb r2, [r3, #69] + 6349 0050 20E0 b .L396 + 6350 .L397: +2449:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +2450:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +2451:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + 6351 .loc 1 2451 30 + 6352 0052 FB68 ldr r3, [r7, #12] + 6353 0054 DB6A ldr r3, [r3, #44] + 6354 .loc 1 2451 11 + 6355 0056 7A68 ldr r2, [r7, #4] + 6356 0058 9A42 cmp r2, r3 + 6357 005a 0BD1 bne .L398 +2452:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +2453:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + 6358 .loc 1 2453 19 + 6359 005c FB68 ldr r3, [r7, #12] + 6360 005e 0422 movs r2, #4 + 6361 0060 1A77 strb r2, [r3, #28] +2454:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2455:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (hdma->Init.Mode == DMA_NORMAL) + 6362 .loc 1 2455 19 + 6363 0062 7B68 ldr r3, [r7, #4] + 6364 0064 9B69 ldr r3, [r3, #24] + 6365 .loc 1 2455 8 + 6366 0066 002B cmp r3, #0 + 6367 0068 14D1 bne .L396 +2456:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +2457:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + 6368 .loc 1 2457 7 + 6369 006a FB68 ldr r3, [r7, #12] + 6370 006c 0122 movs r2, #1 + 6371 006e 83F84620 strb r2, [r3, #70] + 6372 0072 0FE0 b .L396 + 6373 .L398: +2458:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +2459:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +2460:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + 6374 .loc 1 2460 30 + 6375 0074 FB68 ldr r3, [r7, #12] + 6376 0076 1B6B ldr r3, [r3, #48] + 6377 .loc 1 2460 11 + 6378 0078 7A68 ldr r2, [r7, #4] + 6379 007a 9A42 cmp r2, r3 + 6380 007c 0AD1 bne .L396 +2461:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + ARM GAS /tmp/ccxRWv8k.s page 155 + + +2462:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + 6381 .loc 1 2462 19 + 6382 007e FB68 ldr r3, [r7, #12] + 6383 0080 0822 movs r2, #8 + 6384 0082 1A77 strb r2, [r3, #28] +2463:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2464:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (hdma->Init.Mode == DMA_NORMAL) + 6385 .loc 1 2464 19 + 6386 0084 7B68 ldr r3, [r7, #4] + 6387 0086 9B69 ldr r3, [r3, #24] + 6388 .loc 1 2464 8 + 6389 0088 002B cmp r3, #0 + 6390 008a 03D1 bne .L396 +2465:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +2466:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + 6391 .loc 1 2466 7 + 6392 008c FB68 ldr r3, [r7, #12] + 6393 008e 0122 movs r2, #1 + 6394 0090 83F84720 strb r2, [r3, #71] + 6395 .L396: +2467:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +2468:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +2469:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** else +2470:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +2471:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* nothing to do */ +2472:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +2473:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2474:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +2475:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->PWM_PulseFinishedCallback(htim); +2476:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** #else +2477:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_TIM_PWM_PulseFinishedCallback(htim); + 6396 .loc 1 2477 3 + 6397 0094 F868 ldr r0, [r7, #12] + 6398 0096 FFF7FEFF bl HAL_TIM_PWM_PulseFinishedCallback +2478:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +2479:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2480:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 6399 .loc 1 2480 17 + 6400 009a FB68 ldr r3, [r7, #12] + 6401 009c 0022 movs r2, #0 + 6402 009e 1A77 strb r2, [r3, #28] +2481:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 6403 .loc 1 2481 1 + 6404 00a0 00BF nop + 6405 00a2 1037 adds r7, r7, #16 + 6406 .cfi_def_cfa_offset 8 + 6407 00a4 BD46 mov sp, r7 + 6408 .cfi_def_cfa_register 13 + 6409 @ sp needed + 6410 00a6 80BD pop {r7, pc} + 6411 .cfi_endproc + 6412 .LFE171: + 6414 .section .text.TIM_DMAErrorCCxN,"ax",%progbits + 6415 .align 1 + 6416 .syntax unified + 6417 .thumb + 6418 .thumb_func + ARM GAS /tmp/ccxRWv8k.s page 156 + + + 6420 TIM_DMAErrorCCxN: + 6421 .LFB172: +2482:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2483:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** +2484:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief TIM DMA error callback (complementary channel) +2485:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param hdma pointer to DMA handle. +2486:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @retval None +2487:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ +2488:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) +2489:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 6422 .loc 1 2489 1 + 6423 .cfi_startproc + 6424 @ args = 0, pretend = 0, frame = 16 + 6425 @ frame_needed = 1, uses_anonymous_args = 0 + 6426 0000 80B5 push {r7, lr} + 6427 .cfi_def_cfa_offset 8 + 6428 .cfi_offset 7, -8 + 6429 .cfi_offset 14, -4 + 6430 0002 84B0 sub sp, sp, #16 + 6431 .cfi_def_cfa_offset 24 + 6432 0004 00AF add r7, sp, #0 + 6433 .cfi_def_cfa_register 7 + 6434 0006 7860 str r0, [r7, #4] +2490:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + 6435 .loc 1 2490 22 + 6436 0008 7B68 ldr r3, [r7, #4] + 6437 000a 5B6A ldr r3, [r3, #36] + 6438 000c FB60 str r3, [r7, #12] +2491:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2492:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + 6439 .loc 1 2492 25 + 6440 000e FB68 ldr r3, [r7, #12] + 6441 0010 5B6A ldr r3, [r3, #36] + 6442 .loc 1 2492 6 + 6443 0012 7A68 ldr r2, [r7, #4] + 6444 0014 9A42 cmp r2, r3 + 6445 0016 07D1 bne .L400 +2493:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +2494:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + 6446 .loc 1 2494 19 + 6447 0018 FB68 ldr r3, [r7, #12] + 6448 001a 0122 movs r2, #1 + 6449 001c 1A77 strb r2, [r3, #28] +2495:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + 6450 .loc 1 2495 5 + 6451 001e FB68 ldr r3, [r7, #12] + 6452 0020 0122 movs r2, #1 + 6453 0022 83F84420 strb r2, [r3, #68] + 6454 0026 18E0 b .L401 + 6455 .L400: +2496:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +2497:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + 6456 .loc 1 2497 30 + 6457 0028 FB68 ldr r3, [r7, #12] + 6458 002a 9B6A ldr r3, [r3, #40] + 6459 .loc 1 2497 11 + 6460 002c 7A68 ldr r2, [r7, #4] + ARM GAS /tmp/ccxRWv8k.s page 157 + + + 6461 002e 9A42 cmp r2, r3 + 6462 0030 07D1 bne .L402 +2498:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +2499:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + 6463 .loc 1 2499 19 + 6464 0032 FB68 ldr r3, [r7, #12] + 6465 0034 0222 movs r2, #2 + 6466 0036 1A77 strb r2, [r3, #28] +2500:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + 6467 .loc 1 2500 5 + 6468 0038 FB68 ldr r3, [r7, #12] + 6469 003a 0122 movs r2, #1 + 6470 003c 83F84520 strb r2, [r3, #69] + 6471 0040 0BE0 b .L401 + 6472 .L402: +2501:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +2502:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + 6473 .loc 1 2502 30 + 6474 0042 FB68 ldr r3, [r7, #12] + 6475 0044 DB6A ldr r3, [r3, #44] + 6476 .loc 1 2502 11 + 6477 0046 7A68 ldr r2, [r7, #4] + 6478 0048 9A42 cmp r2, r3 + 6479 004a 06D1 bne .L401 +2503:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +2504:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + 6480 .loc 1 2504 19 + 6481 004c FB68 ldr r3, [r7, #12] + 6482 004e 0422 movs r2, #4 + 6483 0050 1A77 strb r2, [r3, #28] +2505:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + 6484 .loc 1 2505 5 + 6485 0052 FB68 ldr r3, [r7, #12] + 6486 0054 0122 movs r2, #1 + 6487 0056 83F84620 strb r2, [r3, #70] + 6488 .L401: +2506:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +2507:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** else +2508:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { +2509:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* nothing to do */ +2510:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } +2511:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2512:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +2513:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->ErrorCallback(htim); +2514:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** #else +2515:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** HAL_TIM_ErrorCallback(htim); + 6489 .loc 1 2515 3 + 6490 005a F868 ldr r0, [r7, #12] + 6491 005c FFF7FEFF bl HAL_TIM_ErrorCallback +2516:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +2517:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2518:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + 6492 .loc 1 2518 17 + 6493 0060 FB68 ldr r3, [r7, #12] + 6494 0062 0022 movs r2, #0 + 6495 0064 1A77 strb r2, [r3, #28] +2519:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + ARM GAS /tmp/ccxRWv8k.s page 158 + + + 6496 .loc 1 2519 1 + 6497 0066 00BF nop + 6498 0068 1037 adds r7, r7, #16 + 6499 .cfi_def_cfa_offset 8 + 6500 006a BD46 mov sp, r7 + 6501 .cfi_def_cfa_register 13 + 6502 @ sp needed + 6503 006c 80BD pop {r7, pc} + 6504 .cfi_endproc + 6505 .LFE172: + 6507 .section .text.TIM_CCxNChannelCmd,"ax",%progbits + 6508 .align 1 + 6509 .syntax unified + 6510 .thumb + 6511 .thumb_func + 6513 TIM_CCxNChannelCmd: + 6514 .LFB173: +2520:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2521:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /** +2522:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @brief Enables or disables the TIM Capture Compare Channel xN. +2523:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param TIMx to select the TIM peripheral +2524:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param Channel specifies the TIM Channel +2525:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * This parameter can be one of the following values: +2526:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_1: TIM Channel 1 +2527:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_2: TIM Channel 2 +2528:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @arg TIM_CHANNEL_3: TIM Channel 3 +2529:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @param ChannelNState specifies the TIM Channel CCxNE bit new state. +2530:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. +2531:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** * @retval None +2532:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** */ +2533:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState) +2534:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** { + 6515 .loc 1 2534 1 + 6516 .cfi_startproc + 6517 @ args = 0, pretend = 0, frame = 24 + 6518 @ frame_needed = 1, uses_anonymous_args = 0 + 6519 @ link register save eliminated. + 6520 0000 80B4 push {r7} + 6521 .cfi_def_cfa_offset 4 + 6522 .cfi_offset 7, -4 + 6523 0002 87B0 sub sp, sp, #28 + 6524 .cfi_def_cfa_offset 32 + 6525 0004 00AF add r7, sp, #0 + 6526 .cfi_def_cfa_register 7 + 6527 0006 F860 str r0, [r7, #12] + 6528 0008 B960 str r1, [r7, #8] + 6529 000a 7A60 str r2, [r7, #4] +2535:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** uint32_t tmp; +2536:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2537:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ + 6530 .loc 1 2537 36 + 6531 000c BB68 ldr r3, [r7, #8] + 6532 000e 03F01F03 and r3, r3, #31 + 6533 .loc 1 2537 7 + 6534 0012 0422 movs r2, #4 + 6535 0014 02FA03F3 lsl r3, r2, r3 + 6536 0018 7B61 str r3, [r7, #20] + ARM GAS /tmp/ccxRWv8k.s page 159 + + +2538:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2539:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Reset the CCxNE Bit */ +2540:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIMx->CCER &= ~tmp; + 6537 .loc 1 2540 7 + 6538 001a FB68 ldr r3, [r7, #12] + 6539 001c 1A6A ldr r2, [r3, #32] + 6540 .loc 1 2540 18 + 6541 001e 7B69 ldr r3, [r7, #20] + 6542 0020 DB43 mvns r3, r3 + 6543 .loc 1 2540 14 + 6544 0022 1A40 ands r2, r2, r3 + 6545 0024 FB68 ldr r3, [r7, #12] + 6546 0026 1A62 str r2, [r3, #32] +2541:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** +2542:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** /* Set or reset the CCxNE Bit */ +2543:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ + 6547 .loc 1 2543 7 + 6548 0028 FB68 ldr r3, [r7, #12] + 6549 002a 1A6A ldr r2, [r3, #32] + 6550 .loc 1 2543 54 + 6551 002c BB68 ldr r3, [r7, #8] + 6552 002e 03F01F03 and r3, r3, #31 + 6553 .loc 1 2543 42 + 6554 0032 7968 ldr r1, [r7, #4] + 6555 0034 01FA03F3 lsl r3, r1, r3 + 6556 .loc 1 2543 14 + 6557 0038 1A43 orrs r2, r2, r3 + 6558 003a FB68 ldr r3, [r7, #12] + 6559 003c 1A62 str r2, [r3, #32] +2544:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_tim_ex.c **** } + 6560 .loc 1 2544 1 + 6561 003e 00BF nop + 6562 0040 1C37 adds r7, r7, #28 + 6563 .cfi_def_cfa_offset 4 + 6564 0042 BD46 mov sp, r7 + 6565 .cfi_def_cfa_register 13 + 6566 @ sp needed + 6567 0044 5DF8047B ldr r7, [sp], #4 + 6568 .cfi_restore 7 + 6569 .cfi_def_cfa_offset 0 + 6570 0048 7047 bx lr + 6571 .cfi_endproc + 6572 .LFE173: + 6574 .text + 6575 .Letext0: + 6576 .file 2 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 6577 .file 3 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 6578 .file 4 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + 6579 .file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h" + 6580 .file 6 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h" + 6581 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h" + 6582 .file 8 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h" + 6583 .file 9 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h" + ARM GAS /tmp/ccxRWv8k.s page 160 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f3xx_hal_tim_ex.c + /tmp/ccxRWv8k.s:21 .text.HAL_TIMEx_HallSensor_Init:00000000 $t + /tmp/ccxRWv8k.s:27 .text.HAL_TIMEx_HallSensor_Init:00000000 HAL_TIMEx_HallSensor_Init + /tmp/ccxRWv8k.s:365 .text.HAL_TIMEx_HallSensor_MspInit:00000000 HAL_TIMEx_HallSensor_MspInit + /tmp/ccxRWv8k.s:264 .text.HAL_TIMEx_HallSensor_DeInit:00000000 $t + /tmp/ccxRWv8k.s:270 .text.HAL_TIMEx_HallSensor_DeInit:00000000 HAL_TIMEx_HallSensor_DeInit + /tmp/ccxRWv8k.s:401 .text.HAL_TIMEx_HallSensor_MspDeInit:00000000 HAL_TIMEx_HallSensor_MspDeInit + /tmp/ccxRWv8k.s:359 .text.HAL_TIMEx_HallSensor_MspInit:00000000 $t + /tmp/ccxRWv8k.s:395 .text.HAL_TIMEx_HallSensor_MspDeInit:00000000 $t + /tmp/ccxRWv8k.s:431 .text.HAL_TIMEx_HallSensor_Start:00000000 $t + /tmp/ccxRWv8k.s:437 .text.HAL_TIMEx_HallSensor_Start:00000000 HAL_TIMEx_HallSensor_Start + /tmp/ccxRWv8k.s:598 .text.HAL_TIMEx_HallSensor_Start:000000f0 $d + /tmp/ccxRWv8k.s:607 .text.HAL_TIMEx_HallSensor_Stop:00000000 $t + /tmp/ccxRWv8k.s:613 .text.HAL_TIMEx_HallSensor_Stop:00000000 HAL_TIMEx_HallSensor_Stop + /tmp/ccxRWv8k.s:690 .text.HAL_TIMEx_HallSensor_Start_IT:00000000 $t + /tmp/ccxRWv8k.s:696 .text.HAL_TIMEx_HallSensor_Start_IT:00000000 HAL_TIMEx_HallSensor_Start_IT + /tmp/ccxRWv8k.s:865 .text.HAL_TIMEx_HallSensor_Start_IT:00000100 $d + /tmp/ccxRWv8k.s:874 .text.HAL_TIMEx_HallSensor_Stop_IT:00000000 $t + /tmp/ccxRWv8k.s:880 .text.HAL_TIMEx_HallSensor_Stop_IT:00000000 HAL_TIMEx_HallSensor_Stop_IT + /tmp/ccxRWv8k.s:965 .text.HAL_TIMEx_HallSensor_Start_DMA:00000000 $t + /tmp/ccxRWv8k.s:971 .text.HAL_TIMEx_HallSensor_Start_DMA:00000000 HAL_TIMEx_HallSensor_Start_DMA + /tmp/ccxRWv8k.s:1187 .text.HAL_TIMEx_HallSensor_Start_DMA:00000134 $d + /tmp/ccxRWv8k.s:1199 .text.HAL_TIMEx_HallSensor_Stop_DMA:00000000 $t + /tmp/ccxRWv8k.s:1205 .text.HAL_TIMEx_HallSensor_Stop_DMA:00000000 HAL_TIMEx_HallSensor_Stop_DMA + /tmp/ccxRWv8k.s:1287 .text.HAL_TIMEx_OCN_Start:00000000 $t + /tmp/ccxRWv8k.s:1293 .text.HAL_TIMEx_OCN_Start:00000000 HAL_TIMEx_OCN_Start + /tmp/ccxRWv8k.s:6513 .text.TIM_CCxNChannelCmd:00000000 TIM_CCxNChannelCmd + /tmp/ccxRWv8k.s:1511 .text.HAL_TIMEx_OCN_Start:00000144 $d + /tmp/ccxRWv8k.s:1520 .text.HAL_TIMEx_OCN_Stop:00000000 $t + /tmp/ccxRWv8k.s:1526 .text.HAL_TIMEx_OCN_Stop:00000000 HAL_TIMEx_OCN_Stop + /tmp/ccxRWv8k.s:1648 .text.HAL_TIMEx_OCN_Start_IT:00000000 $t + /tmp/ccxRWv8k.s:1654 .text.HAL_TIMEx_OCN_Start_IT:00000000 HAL_TIMEx_OCN_Start_IT + /tmp/ccxRWv8k.s:1941 .text.HAL_TIMEx_OCN_Start_IT:000001b4 $d + /tmp/ccxRWv8k.s:1950 .text.HAL_TIMEx_OCN_Stop_IT:00000000 $t + /tmp/ccxRWv8k.s:1956 .text.HAL_TIMEx_OCN_Stop_IT:00000000 HAL_TIMEx_OCN_Stop_IT + /tmp/ccxRWv8k.s:2161 .text.HAL_TIMEx_OCN_Start_DMA:00000000 $t + /tmp/ccxRWv8k.s:2167 .text.HAL_TIMEx_OCN_Start_DMA:00000000 HAL_TIMEx_OCN_Start_DMA + /tmp/ccxRWv8k.s:2647 .text.HAL_TIMEx_OCN_Start_DMA:000002c4 $d + /tmp/ccxRWv8k.s:6286 .text.TIM_DMADelayPulseNCplt:00000000 TIM_DMADelayPulseNCplt + /tmp/ccxRWv8k.s:6420 .text.TIM_DMAErrorCCxN:00000000 TIM_DMAErrorCCxN + /tmp/ccxRWv8k.s:2659 .text.HAL_TIMEx_OCN_Stop_DMA:00000000 $t + /tmp/ccxRWv8k.s:2665 .text.HAL_TIMEx_OCN_Stop_DMA:00000000 HAL_TIMEx_OCN_Stop_DMA + /tmp/ccxRWv8k.s:2863 .text.HAL_TIMEx_PWMN_Start:00000000 $t + /tmp/ccxRWv8k.s:2869 .text.HAL_TIMEx_PWMN_Start:00000000 HAL_TIMEx_PWMN_Start + /tmp/ccxRWv8k.s:3087 .text.HAL_TIMEx_PWMN_Start:00000144 $d + /tmp/ccxRWv8k.s:3096 .text.HAL_TIMEx_PWMN_Stop:00000000 $t + /tmp/ccxRWv8k.s:3102 .text.HAL_TIMEx_PWMN_Stop:00000000 HAL_TIMEx_PWMN_Stop + /tmp/ccxRWv8k.s:3224 .text.HAL_TIMEx_PWMN_Start_IT:00000000 $t + /tmp/ccxRWv8k.s:3230 .text.HAL_TIMEx_PWMN_Start_IT:00000000 HAL_TIMEx_PWMN_Start_IT + /tmp/ccxRWv8k.s:3517 .text.HAL_TIMEx_PWMN_Start_IT:000001b4 $d + /tmp/ccxRWv8k.s:3526 .text.HAL_TIMEx_PWMN_Stop_IT:00000000 $t + /tmp/ccxRWv8k.s:3532 .text.HAL_TIMEx_PWMN_Stop_IT:00000000 HAL_TIMEx_PWMN_Stop_IT + /tmp/ccxRWv8k.s:3737 .text.HAL_TIMEx_PWMN_Start_DMA:00000000 $t + /tmp/ccxRWv8k.s:3743 .text.HAL_TIMEx_PWMN_Start_DMA:00000000 HAL_TIMEx_PWMN_Start_DMA + /tmp/ccxRWv8k.s:4223 .text.HAL_TIMEx_PWMN_Start_DMA:000002c4 $d + /tmp/ccxRWv8k.s:4235 .text.HAL_TIMEx_PWMN_Stop_DMA:00000000 $t + ARM GAS /tmp/ccxRWv8k.s page 161 + + + /tmp/ccxRWv8k.s:4241 .text.HAL_TIMEx_PWMN_Stop_DMA:00000000 HAL_TIMEx_PWMN_Stop_DMA + /tmp/ccxRWv8k.s:4439 .text.HAL_TIMEx_OnePulseN_Start:00000000 $t + /tmp/ccxRWv8k.s:4445 .text.HAL_TIMEx_OnePulseN_Start:00000000 HAL_TIMEx_OnePulseN_Start + /tmp/ccxRWv8k.s:4564 .text.HAL_TIMEx_OnePulseN_Stop:00000000 $t + /tmp/ccxRWv8k.s:4570 .text.HAL_TIMEx_OnePulseN_Stop:00000000 HAL_TIMEx_OnePulseN_Stop + /tmp/ccxRWv8k.s:4693 .text.HAL_TIMEx_OnePulseN_Start_IT:00000000 $t + /tmp/ccxRWv8k.s:4699 .text.HAL_TIMEx_OnePulseN_Start_IT:00000000 HAL_TIMEx_OnePulseN_Start_IT + /tmp/ccxRWv8k.s:4834 .text.HAL_TIMEx_OnePulseN_Stop_IT:00000000 $t + /tmp/ccxRWv8k.s:4840 .text.HAL_TIMEx_OnePulseN_Stop_IT:00000000 HAL_TIMEx_OnePulseN_Stop_IT + /tmp/ccxRWv8k.s:4979 .text.HAL_TIMEx_ConfigCommutEvent:00000000 $t + /tmp/ccxRWv8k.s:4985 .text.HAL_TIMEx_ConfigCommutEvent:00000000 HAL_TIMEx_ConfigCommutEvent + /tmp/ccxRWv8k.s:5129 .text.HAL_TIMEx_ConfigCommutEvent_IT:00000000 $t + /tmp/ccxRWv8k.s:5135 .text.HAL_TIMEx_ConfigCommutEvent_IT:00000000 HAL_TIMEx_ConfigCommutEvent_IT + /tmp/ccxRWv8k.s:5279 .text.HAL_TIMEx_ConfigCommutEvent_DMA:00000000 $t + /tmp/ccxRWv8k.s:5285 .text.HAL_TIMEx_ConfigCommutEvent_DMA:00000000 HAL_TIMEx_ConfigCommutEvent_DMA + /tmp/ccxRWv8k.s:5446 .text.HAL_TIMEx_ConfigCommutEvent_DMA:000000d8 $d + /tmp/ccxRWv8k.s:6199 .text.TIMEx_DMACommutationCplt:00000000 TIMEx_DMACommutationCplt + /tmp/ccxRWv8k.s:6243 .text.TIMEx_DMACommutationHalfCplt:00000000 TIMEx_DMACommutationHalfCplt + /tmp/ccxRWv8k.s:5453 .text.HAL_TIMEx_MasterConfigSynchronization:00000000 $t + /tmp/ccxRWv8k.s:5459 .text.HAL_TIMEx_MasterConfigSynchronization:00000000 HAL_TIMEx_MasterConfigSynchronization + /tmp/ccxRWv8k.s:5615 .text.HAL_TIMEx_MasterConfigSynchronization:000000d8 $d + /tmp/ccxRWv8k.s:5623 .text.HAL_TIMEx_ConfigBreakDeadTime:00000000 $t + /tmp/ccxRWv8k.s:5629 .text.HAL_TIMEx_ConfigBreakDeadTime:00000000 HAL_TIMEx_ConfigBreakDeadTime + /tmp/ccxRWv8k.s:5776 .text.HAL_TIMEx_ConfigBreakDeadTime:000000ec $d + /tmp/ccxRWv8k.s:5781 .text.HAL_TIMEx_RemapConfig:00000000 $t + /tmp/ccxRWv8k.s:5787 .text.HAL_TIMEx_RemapConfig:00000000 HAL_TIMEx_RemapConfig + /tmp/ccxRWv8k.s:5844 .text.HAL_TIMEx_GroupChannel5:00000000 $t + /tmp/ccxRWv8k.s:5850 .text.HAL_TIMEx_GroupChannel5:00000000 HAL_TIMEx_GroupChannel5 + /tmp/ccxRWv8k.s:5933 .text.HAL_TIMEx_CommutCallback:00000000 $t + /tmp/ccxRWv8k.s:5939 .text.HAL_TIMEx_CommutCallback:00000000 HAL_TIMEx_CommutCallback + /tmp/ccxRWv8k.s:5969 .text.HAL_TIMEx_CommutHalfCpltCallback:00000000 $t + /tmp/ccxRWv8k.s:5975 .text.HAL_TIMEx_CommutHalfCpltCallback:00000000 HAL_TIMEx_CommutHalfCpltCallback + /tmp/ccxRWv8k.s:6005 .text.HAL_TIMEx_BreakCallback:00000000 $t + /tmp/ccxRWv8k.s:6011 .text.HAL_TIMEx_BreakCallback:00000000 HAL_TIMEx_BreakCallback + /tmp/ccxRWv8k.s:6041 .text.HAL_TIMEx_Break2Callback:00000000 $t + /tmp/ccxRWv8k.s:6047 .text.HAL_TIMEx_Break2Callback:00000000 HAL_TIMEx_Break2Callback + /tmp/ccxRWv8k.s:6077 .text.HAL_TIMEx_HallSensor_GetState:00000000 $t + /tmp/ccxRWv8k.s:6083 .text.HAL_TIMEx_HallSensor_GetState:00000000 HAL_TIMEx_HallSensor_GetState + /tmp/ccxRWv8k.s:6117 .text.HAL_TIMEx_GetChannelNState:00000000 $t + /tmp/ccxRWv8k.s:6123 .text.HAL_TIMEx_GetChannelNState:00000000 HAL_TIMEx_GetChannelNState + /tmp/ccxRWv8k.s:6193 .text.TIMEx_DMACommutationCplt:00000000 $t + /tmp/ccxRWv8k.s:6237 .text.TIMEx_DMACommutationHalfCplt:00000000 $t + /tmp/ccxRWv8k.s:6281 .text.TIM_DMADelayPulseNCplt:00000000 $t + /tmp/ccxRWv8k.s:6415 .text.TIM_DMAErrorCCxN:00000000 $t + /tmp/ccxRWv8k.s:6508 .text.TIM_CCxNChannelCmd:00000000 $t + +UNDEFINED SYMBOLS +TIM_Base_SetConfig +TIM_TI1_SetConfig +TIM_OC2_SetConfig +TIM_CCxChannelCmd +HAL_DMA_Start_IT +TIM_DMACaptureCplt +TIM_DMACaptureHalfCplt +TIM_DMAError +HAL_DMA_Abort_IT +TIM_DMADelayPulseHalfCplt + ARM GAS /tmp/ccxRWv8k.s page 162 + + +HAL_TIM_PWM_PulseFinishedCallback +HAL_TIM_ErrorCallback diff --git a/Software/build/stm32f3xx_hal_tim_ex.o b/Software/build/stm32f3xx_hal_tim_ex.o new file mode 100644 index 0000000..9523452 Binary files /dev/null and b/Software/build/stm32f3xx_hal_tim_ex.o differ diff --git a/Software/build/stm32f3xx_it.d b/Software/build/stm32f3xx_it.d new file mode 100644 index 0000000..cdca7d8 --- /dev/null +++ b/Software/build/stm32f3xx_it.d @@ -0,0 +1,64 @@ +build/stm32f3xx_it.o: Core/Src/stm32f3xx_it.c Core/Inc/main.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + Core/Inc/stm32f3xx_hal_conf.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h \ + Core/Inc/stm32f3xx_it.h +Core/Inc/main.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h: +Core/Inc/stm32f3xx_it.h: diff --git a/Software/build/stm32f3xx_it.lst b/Software/build/stm32f3xx_it.lst new file mode 100644 index 0000000..84fbe91 --- /dev/null +++ b/Software/build/stm32f3xx_it.lst @@ -0,0 +1,610 @@ +ARM GAS /tmp/ccpm1fqH.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 6 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "stm32f3xx_it.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Core/Src/stm32f3xx_it.c" + 20 .section .text.NMI_Handler,"ax",%progbits + 21 .align 1 + 22 .global NMI_Handler + 23 .syntax unified + 24 .thumb + 25 .thumb_func + 27 NMI_Handler: + 28 .LFB130: + 1:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN Header */ + 2:Core/Src/stm32f3xx_it.c **** /** + 3:Core/Src/stm32f3xx_it.c **** ****************************************************************************** + 4:Core/Src/stm32f3xx_it.c **** * @file stm32f3xx_it.c + 5:Core/Src/stm32f3xx_it.c **** * @brief Interrupt Service Routines. + 6:Core/Src/stm32f3xx_it.c **** ****************************************************************************** + 7:Core/Src/stm32f3xx_it.c **** * @attention + 8:Core/Src/stm32f3xx_it.c **** * + 9:Core/Src/stm32f3xx_it.c **** * Copyright (c) 2024 STMicroelectronics. + 10:Core/Src/stm32f3xx_it.c **** * All rights reserved. + 11:Core/Src/stm32f3xx_it.c **** * + 12:Core/Src/stm32f3xx_it.c **** * This software is licensed under terms that can be found in the LICENSE file + 13:Core/Src/stm32f3xx_it.c **** * in the root directory of this software component. + 14:Core/Src/stm32f3xx_it.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 15:Core/Src/stm32f3xx_it.c **** * + 16:Core/Src/stm32f3xx_it.c **** ****************************************************************************** + 17:Core/Src/stm32f3xx_it.c **** */ + 18:Core/Src/stm32f3xx_it.c **** /* USER CODE END Header */ + 19:Core/Src/stm32f3xx_it.c **** + 20:Core/Src/stm32f3xx_it.c **** /* Includes ------------------------------------------------------------------*/ + 21:Core/Src/stm32f3xx_it.c **** #include "main.h" + 22:Core/Src/stm32f3xx_it.c **** #include "stm32f3xx_it.h" + 23:Core/Src/stm32f3xx_it.c **** /* Private includes ----------------------------------------------------------*/ + 24:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN Includes */ + 25:Core/Src/stm32f3xx_it.c **** /* USER CODE END Includes */ + 26:Core/Src/stm32f3xx_it.c **** + 27:Core/Src/stm32f3xx_it.c **** /* Private typedef -----------------------------------------------------------*/ + 28:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN TD */ + 29:Core/Src/stm32f3xx_it.c **** + 30:Core/Src/stm32f3xx_it.c **** /* USER CODE END TD */ + ARM GAS /tmp/ccpm1fqH.s page 2 + + + 31:Core/Src/stm32f3xx_it.c **** + 32:Core/Src/stm32f3xx_it.c **** /* Private define ------------------------------------------------------------*/ + 33:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN PD */ + 34:Core/Src/stm32f3xx_it.c **** + 35:Core/Src/stm32f3xx_it.c **** /* USER CODE END PD */ + 36:Core/Src/stm32f3xx_it.c **** + 37:Core/Src/stm32f3xx_it.c **** /* Private macro -------------------------------------------------------------*/ + 38:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN PM */ + 39:Core/Src/stm32f3xx_it.c **** + 40:Core/Src/stm32f3xx_it.c **** /* USER CODE END PM */ + 41:Core/Src/stm32f3xx_it.c **** + 42:Core/Src/stm32f3xx_it.c **** /* Private variables ---------------------------------------------------------*/ + 43:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN PV */ + 44:Core/Src/stm32f3xx_it.c **** + 45:Core/Src/stm32f3xx_it.c **** /* USER CODE END PV */ + 46:Core/Src/stm32f3xx_it.c **** + 47:Core/Src/stm32f3xx_it.c **** /* Private function prototypes -----------------------------------------------*/ + 48:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN PFP */ + 49:Core/Src/stm32f3xx_it.c **** + 50:Core/Src/stm32f3xx_it.c **** /* USER CODE END PFP */ + 51:Core/Src/stm32f3xx_it.c **** + 52:Core/Src/stm32f3xx_it.c **** /* Private user code ---------------------------------------------------------*/ + 53:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN 0 */ + 54:Core/Src/stm32f3xx_it.c **** + 55:Core/Src/stm32f3xx_it.c **** /* USER CODE END 0 */ + 56:Core/Src/stm32f3xx_it.c **** + 57:Core/Src/stm32f3xx_it.c **** /* External variables --------------------------------------------------------*/ + 58:Core/Src/stm32f3xx_it.c **** extern CAN_HandleTypeDef hcan; + 59:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN EV */ + 60:Core/Src/stm32f3xx_it.c **** + 61:Core/Src/stm32f3xx_it.c **** /* USER CODE END EV */ + 62:Core/Src/stm32f3xx_it.c **** + 63:Core/Src/stm32f3xx_it.c **** /******************************************************************************/ + 64:Core/Src/stm32f3xx_it.c **** /* Cortex-M4 Processor Interruption and Exception Handlers */ + 65:Core/Src/stm32f3xx_it.c **** /******************************************************************************/ + 66:Core/Src/stm32f3xx_it.c **** /** + 67:Core/Src/stm32f3xx_it.c **** * @brief This function handles Non maskable interrupt. + 68:Core/Src/stm32f3xx_it.c **** */ + 69:Core/Src/stm32f3xx_it.c **** void NMI_Handler(void) + 70:Core/Src/stm32f3xx_it.c **** { + 29 .loc 1 70 1 + 30 .cfi_startproc + 31 @ args = 0, pretend = 0, frame = 0 + 32 @ frame_needed = 1, uses_anonymous_args = 0 + 33 @ link register save eliminated. + 34 0000 80B4 push {r7} + 35 .cfi_def_cfa_offset 4 + 36 .cfi_offset 7, -4 + 37 0002 00AF add r7, sp, #0 + 38 .cfi_def_cfa_register 7 + 39 .L2: + 71:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + 72:Core/Src/stm32f3xx_it.c **** + 73:Core/Src/stm32f3xx_it.c **** /* USER CODE END NonMaskableInt_IRQn 0 */ + 74:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + 75:Core/Src/stm32f3xx_it.c **** while (1) + 40 .loc 1 75 10 + ARM GAS /tmp/ccpm1fqH.s page 3 + + + 41 0004 00BF nop + 42 0006 FDE7 b .L2 + 43 .cfi_endproc + 44 .LFE130: + 46 .section .text.HardFault_Handler,"ax",%progbits + 47 .align 1 + 48 .global HardFault_Handler + 49 .syntax unified + 50 .thumb + 51 .thumb_func + 53 HardFault_Handler: + 54 .LFB131: + 76:Core/Src/stm32f3xx_it.c **** { + 77:Core/Src/stm32f3xx_it.c **** } + 78:Core/Src/stm32f3xx_it.c **** /* USER CODE END NonMaskableInt_IRQn 1 */ + 79:Core/Src/stm32f3xx_it.c **** } + 80:Core/Src/stm32f3xx_it.c **** + 81:Core/Src/stm32f3xx_it.c **** /** + 82:Core/Src/stm32f3xx_it.c **** * @brief This function handles Hard fault interrupt. + 83:Core/Src/stm32f3xx_it.c **** */ + 84:Core/Src/stm32f3xx_it.c **** void HardFault_Handler(void) + 85:Core/Src/stm32f3xx_it.c **** { + 55 .loc 1 85 1 + 56 .cfi_startproc + 57 @ args = 0, pretend = 0, frame = 0 + 58 @ frame_needed = 1, uses_anonymous_args = 0 + 59 @ link register save eliminated. + 60 0000 80B4 push {r7} + 61 .cfi_def_cfa_offset 4 + 62 .cfi_offset 7, -4 + 63 0002 00AF add r7, sp, #0 + 64 .cfi_def_cfa_register 7 + 65 .L4: + 86:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN HardFault_IRQn 0 */ + 87:Core/Src/stm32f3xx_it.c **** + 88:Core/Src/stm32f3xx_it.c **** /* USER CODE END HardFault_IRQn 0 */ + 89:Core/Src/stm32f3xx_it.c **** while (1) + 66 .loc 1 89 9 + 67 0004 00BF nop + 68 0006 FDE7 b .L4 + 69 .cfi_endproc + 70 .LFE131: + 72 .section .text.MemManage_Handler,"ax",%progbits + 73 .align 1 + 74 .global MemManage_Handler + 75 .syntax unified + 76 .thumb + 77 .thumb_func + 79 MemManage_Handler: + 80 .LFB132: + 90:Core/Src/stm32f3xx_it.c **** { + 91:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN W1_HardFault_IRQn 0 */ + 92:Core/Src/stm32f3xx_it.c **** /* USER CODE END W1_HardFault_IRQn 0 */ + 93:Core/Src/stm32f3xx_it.c **** } + 94:Core/Src/stm32f3xx_it.c **** } + 95:Core/Src/stm32f3xx_it.c **** + 96:Core/Src/stm32f3xx_it.c **** /** + ARM GAS /tmp/ccpm1fqH.s page 4 + + + 97:Core/Src/stm32f3xx_it.c **** * @brief This function handles Memory management fault. + 98:Core/Src/stm32f3xx_it.c **** */ + 99:Core/Src/stm32f3xx_it.c **** void MemManage_Handler(void) + 100:Core/Src/stm32f3xx_it.c **** { + 81 .loc 1 100 1 + 82 .cfi_startproc + 83 @ args = 0, pretend = 0, frame = 0 + 84 @ frame_needed = 1, uses_anonymous_args = 0 + 85 @ link register save eliminated. + 86 0000 80B4 push {r7} + 87 .cfi_def_cfa_offset 4 + 88 .cfi_offset 7, -4 + 89 0002 00AF add r7, sp, #0 + 90 .cfi_def_cfa_register 7 + 91 .L6: + 101:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + 102:Core/Src/stm32f3xx_it.c **** + 103:Core/Src/stm32f3xx_it.c **** /* USER CODE END MemoryManagement_IRQn 0 */ + 104:Core/Src/stm32f3xx_it.c **** while (1) + 92 .loc 1 104 9 + 93 0004 00BF nop + 94 0006 FDE7 b .L6 + 95 .cfi_endproc + 96 .LFE132: + 98 .section .text.BusFault_Handler,"ax",%progbits + 99 .align 1 + 100 .global BusFault_Handler + 101 .syntax unified + 102 .thumb + 103 .thumb_func + 105 BusFault_Handler: + 106 .LFB133: + 105:Core/Src/stm32f3xx_it.c **** { + 106:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ + 107:Core/Src/stm32f3xx_it.c **** /* USER CODE END W1_MemoryManagement_IRQn 0 */ + 108:Core/Src/stm32f3xx_it.c **** } + 109:Core/Src/stm32f3xx_it.c **** } + 110:Core/Src/stm32f3xx_it.c **** + 111:Core/Src/stm32f3xx_it.c **** /** + 112:Core/Src/stm32f3xx_it.c **** * @brief This function handles Pre-fetch fault, memory access fault. + 113:Core/Src/stm32f3xx_it.c **** */ + 114:Core/Src/stm32f3xx_it.c **** void BusFault_Handler(void) + 115:Core/Src/stm32f3xx_it.c **** { + 107 .loc 1 115 1 + 108 .cfi_startproc + 109 @ args = 0, pretend = 0, frame = 0 + 110 @ frame_needed = 1, uses_anonymous_args = 0 + 111 @ link register save eliminated. + 112 0000 80B4 push {r7} + 113 .cfi_def_cfa_offset 4 + 114 .cfi_offset 7, -4 + 115 0002 00AF add r7, sp, #0 + 116 .cfi_def_cfa_register 7 + 117 .L8: + 116:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN BusFault_IRQn 0 */ + 117:Core/Src/stm32f3xx_it.c **** + 118:Core/Src/stm32f3xx_it.c **** /* USER CODE END BusFault_IRQn 0 */ + ARM GAS /tmp/ccpm1fqH.s page 5 + + + 119:Core/Src/stm32f3xx_it.c **** while (1) + 118 .loc 1 119 9 + 119 0004 00BF nop + 120 0006 FDE7 b .L8 + 121 .cfi_endproc + 122 .LFE133: + 124 .section .text.UsageFault_Handler,"ax",%progbits + 125 .align 1 + 126 .global UsageFault_Handler + 127 .syntax unified + 128 .thumb + 129 .thumb_func + 131 UsageFault_Handler: + 132 .LFB134: + 120:Core/Src/stm32f3xx_it.c **** { + 121:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN W1_BusFault_IRQn 0 */ + 122:Core/Src/stm32f3xx_it.c **** /* USER CODE END W1_BusFault_IRQn 0 */ + 123:Core/Src/stm32f3xx_it.c **** } + 124:Core/Src/stm32f3xx_it.c **** } + 125:Core/Src/stm32f3xx_it.c **** + 126:Core/Src/stm32f3xx_it.c **** /** + 127:Core/Src/stm32f3xx_it.c **** * @brief This function handles Undefined instruction or illegal state. + 128:Core/Src/stm32f3xx_it.c **** */ + 129:Core/Src/stm32f3xx_it.c **** void UsageFault_Handler(void) + 130:Core/Src/stm32f3xx_it.c **** { + 133 .loc 1 130 1 + 134 .cfi_startproc + 135 @ args = 0, pretend = 0, frame = 0 + 136 @ frame_needed = 1, uses_anonymous_args = 0 + 137 @ link register save eliminated. + 138 0000 80B4 push {r7} + 139 .cfi_def_cfa_offset 4 + 140 .cfi_offset 7, -4 + 141 0002 00AF add r7, sp, #0 + 142 .cfi_def_cfa_register 7 + 143 .L10: + 131:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN UsageFault_IRQn 0 */ + 132:Core/Src/stm32f3xx_it.c **** + 133:Core/Src/stm32f3xx_it.c **** /* USER CODE END UsageFault_IRQn 0 */ + 134:Core/Src/stm32f3xx_it.c **** while (1) + 144 .loc 1 134 9 + 145 0004 00BF nop + 146 0006 FDE7 b .L10 + 147 .cfi_endproc + 148 .LFE134: + 150 .section .text.SVC_Handler,"ax",%progbits + 151 .align 1 + 152 .global SVC_Handler + 153 .syntax unified + 154 .thumb + 155 .thumb_func + 157 SVC_Handler: + 158 .LFB135: + 135:Core/Src/stm32f3xx_it.c **** { + 136:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ + 137:Core/Src/stm32f3xx_it.c **** /* USER CODE END W1_UsageFault_IRQn 0 */ + 138:Core/Src/stm32f3xx_it.c **** } + ARM GAS /tmp/ccpm1fqH.s page 6 + + + 139:Core/Src/stm32f3xx_it.c **** } + 140:Core/Src/stm32f3xx_it.c **** + 141:Core/Src/stm32f3xx_it.c **** /** + 142:Core/Src/stm32f3xx_it.c **** * @brief This function handles System service call via SWI instruction. + 143:Core/Src/stm32f3xx_it.c **** */ + 144:Core/Src/stm32f3xx_it.c **** void SVC_Handler(void) + 145:Core/Src/stm32f3xx_it.c **** { + 159 .loc 1 145 1 + 160 .cfi_startproc + 161 @ args = 0, pretend = 0, frame = 0 + 162 @ frame_needed = 1, uses_anonymous_args = 0 + 163 @ link register save eliminated. + 164 0000 80B4 push {r7} + 165 .cfi_def_cfa_offset 4 + 166 .cfi_offset 7, -4 + 167 0002 00AF add r7, sp, #0 + 168 .cfi_def_cfa_register 7 + 146:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN SVCall_IRQn 0 */ + 147:Core/Src/stm32f3xx_it.c **** + 148:Core/Src/stm32f3xx_it.c **** /* USER CODE END SVCall_IRQn 0 */ + 149:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN SVCall_IRQn 1 */ + 150:Core/Src/stm32f3xx_it.c **** + 151:Core/Src/stm32f3xx_it.c **** /* USER CODE END SVCall_IRQn 1 */ + 152:Core/Src/stm32f3xx_it.c **** } + 169 .loc 1 152 1 + 170 0004 00BF nop + 171 0006 BD46 mov sp, r7 + 172 .cfi_def_cfa_register 13 + 173 @ sp needed + 174 0008 5DF8047B ldr r7, [sp], #4 + 175 .cfi_restore 7 + 176 .cfi_def_cfa_offset 0 + 177 000c 7047 bx lr + 178 .cfi_endproc + 179 .LFE135: + 181 .section .text.DebugMon_Handler,"ax",%progbits + 182 .align 1 + 183 .global DebugMon_Handler + 184 .syntax unified + 185 .thumb + 186 .thumb_func + 188 DebugMon_Handler: + 189 .LFB136: + 153:Core/Src/stm32f3xx_it.c **** + 154:Core/Src/stm32f3xx_it.c **** /** + 155:Core/Src/stm32f3xx_it.c **** * @brief This function handles Debug monitor. + 156:Core/Src/stm32f3xx_it.c **** */ + 157:Core/Src/stm32f3xx_it.c **** void DebugMon_Handler(void) + 158:Core/Src/stm32f3xx_it.c **** { + 190 .loc 1 158 1 + 191 .cfi_startproc + 192 @ args = 0, pretend = 0, frame = 0 + 193 @ frame_needed = 1, uses_anonymous_args = 0 + 194 @ link register save eliminated. + 195 0000 80B4 push {r7} + 196 .cfi_def_cfa_offset 4 + 197 .cfi_offset 7, -4 + ARM GAS /tmp/ccpm1fqH.s page 7 + + + 198 0002 00AF add r7, sp, #0 + 199 .cfi_def_cfa_register 7 + 159:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN DebugMonitor_IRQn 0 */ + 160:Core/Src/stm32f3xx_it.c **** + 161:Core/Src/stm32f3xx_it.c **** /* USER CODE END DebugMonitor_IRQn 0 */ + 162:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + 163:Core/Src/stm32f3xx_it.c **** + 164:Core/Src/stm32f3xx_it.c **** /* USER CODE END DebugMonitor_IRQn 1 */ + 165:Core/Src/stm32f3xx_it.c **** } + 200 .loc 1 165 1 + 201 0004 00BF nop + 202 0006 BD46 mov sp, r7 + 203 .cfi_def_cfa_register 13 + 204 @ sp needed + 205 0008 5DF8047B ldr r7, [sp], #4 + 206 .cfi_restore 7 + 207 .cfi_def_cfa_offset 0 + 208 000c 7047 bx lr + 209 .cfi_endproc + 210 .LFE136: + 212 .section .text.PendSV_Handler,"ax",%progbits + 213 .align 1 + 214 .global PendSV_Handler + 215 .syntax unified + 216 .thumb + 217 .thumb_func + 219 PendSV_Handler: + 220 .LFB137: + 166:Core/Src/stm32f3xx_it.c **** + 167:Core/Src/stm32f3xx_it.c **** /** + 168:Core/Src/stm32f3xx_it.c **** * @brief This function handles Pendable request for system service. + 169:Core/Src/stm32f3xx_it.c **** */ + 170:Core/Src/stm32f3xx_it.c **** void PendSV_Handler(void) + 171:Core/Src/stm32f3xx_it.c **** { + 221 .loc 1 171 1 + 222 .cfi_startproc + 223 @ args = 0, pretend = 0, frame = 0 + 224 @ frame_needed = 1, uses_anonymous_args = 0 + 225 @ link register save eliminated. + 226 0000 80B4 push {r7} + 227 .cfi_def_cfa_offset 4 + 228 .cfi_offset 7, -4 + 229 0002 00AF add r7, sp, #0 + 230 .cfi_def_cfa_register 7 + 172:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN PendSV_IRQn 0 */ + 173:Core/Src/stm32f3xx_it.c **** + 174:Core/Src/stm32f3xx_it.c **** /* USER CODE END PendSV_IRQn 0 */ + 175:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN PendSV_IRQn 1 */ + 176:Core/Src/stm32f3xx_it.c **** + 177:Core/Src/stm32f3xx_it.c **** /* USER CODE END PendSV_IRQn 1 */ + 178:Core/Src/stm32f3xx_it.c **** } + 231 .loc 1 178 1 + 232 0004 00BF nop + 233 0006 BD46 mov sp, r7 + 234 .cfi_def_cfa_register 13 + 235 @ sp needed + 236 0008 5DF8047B ldr r7, [sp], #4 + ARM GAS /tmp/ccpm1fqH.s page 8 + + + 237 .cfi_restore 7 + 238 .cfi_def_cfa_offset 0 + 239 000c 7047 bx lr + 240 .cfi_endproc + 241 .LFE137: + 243 .section .text.SysTick_Handler,"ax",%progbits + 244 .align 1 + 245 .global SysTick_Handler + 246 .syntax unified + 247 .thumb + 248 .thumb_func + 250 SysTick_Handler: + 251 .LFB138: + 179:Core/Src/stm32f3xx_it.c **** + 180:Core/Src/stm32f3xx_it.c **** /** + 181:Core/Src/stm32f3xx_it.c **** * @brief This function handles System tick timer. + 182:Core/Src/stm32f3xx_it.c **** */ + 183:Core/Src/stm32f3xx_it.c **** void SysTick_Handler(void) + 184:Core/Src/stm32f3xx_it.c **** { + 252 .loc 1 184 1 + 253 .cfi_startproc + 254 @ args = 0, pretend = 0, frame = 0 + 255 @ frame_needed = 1, uses_anonymous_args = 0 + 256 0000 80B5 push {r7, lr} + 257 .cfi_def_cfa_offset 8 + 258 .cfi_offset 7, -8 + 259 .cfi_offset 14, -4 + 260 0002 00AF add r7, sp, #0 + 261 .cfi_def_cfa_register 7 + 185:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN SysTick_IRQn 0 */ + 186:Core/Src/stm32f3xx_it.c **** + 187:Core/Src/stm32f3xx_it.c **** /* USER CODE END SysTick_IRQn 0 */ + 188:Core/Src/stm32f3xx_it.c **** HAL_IncTick(); + 262 .loc 1 188 3 + 263 0004 FFF7FEFF bl HAL_IncTick + 189:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN SysTick_IRQn 1 */ + 190:Core/Src/stm32f3xx_it.c **** + 191:Core/Src/stm32f3xx_it.c **** /* USER CODE END SysTick_IRQn 1 */ + 192:Core/Src/stm32f3xx_it.c **** } + 264 .loc 1 192 1 + 265 0008 00BF nop + 266 000a 80BD pop {r7, pc} + 267 .cfi_endproc + 268 .LFE138: + 270 .section .text.USB_LP_CAN_RX0_IRQHandler,"ax",%progbits + 271 .align 1 + 272 .global USB_LP_CAN_RX0_IRQHandler + 273 .syntax unified + 274 .thumb + 275 .thumb_func + 277 USB_LP_CAN_RX0_IRQHandler: + 278 .LFB139: + 193:Core/Src/stm32f3xx_it.c **** + 194:Core/Src/stm32f3xx_it.c **** /******************************************************************************/ + 195:Core/Src/stm32f3xx_it.c **** /* STM32F3xx Peripheral Interrupt Handlers */ + 196:Core/Src/stm32f3xx_it.c **** /* Add here the Interrupt Handlers for the used peripherals. */ + 197:Core/Src/stm32f3xx_it.c **** /* For the available peripheral interrupt handler names, */ + ARM GAS /tmp/ccpm1fqH.s page 9 + + + 198:Core/Src/stm32f3xx_it.c **** /* please refer to the startup file (startup_stm32f3xx.s). */ + 199:Core/Src/stm32f3xx_it.c **** /******************************************************************************/ + 200:Core/Src/stm32f3xx_it.c **** + 201:Core/Src/stm32f3xx_it.c **** /** + 202:Core/Src/stm32f3xx_it.c **** * @brief This function handles USB low priority or CAN_RX0 interrupts. + 203:Core/Src/stm32f3xx_it.c **** */ + 204:Core/Src/stm32f3xx_it.c **** void USB_LP_CAN_RX0_IRQHandler(void) + 205:Core/Src/stm32f3xx_it.c **** { + 279 .loc 1 205 1 + 280 .cfi_startproc + 281 @ args = 0, pretend = 0, frame = 0 + 282 @ frame_needed = 1, uses_anonymous_args = 0 + 283 0000 80B5 push {r7, lr} + 284 .cfi_def_cfa_offset 8 + 285 .cfi_offset 7, -8 + 286 .cfi_offset 14, -4 + 287 0002 00AF add r7, sp, #0 + 288 .cfi_def_cfa_register 7 + 206:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN USB_LP_CAN_RX0_IRQn 0 */ + 207:Core/Src/stm32f3xx_it.c **** + 208:Core/Src/stm32f3xx_it.c **** /* USER CODE END USB_LP_CAN_RX0_IRQn 0 */ + 209:Core/Src/stm32f3xx_it.c **** HAL_CAN_IRQHandler(&hcan); + 289 .loc 1 209 3 + 290 0004 0248 ldr r0, .L16 + 291 0006 FFF7FEFF bl HAL_CAN_IRQHandler + 210:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN USB_LP_CAN_RX0_IRQn 1 */ + 211:Core/Src/stm32f3xx_it.c **** + 212:Core/Src/stm32f3xx_it.c **** /* USER CODE END USB_LP_CAN_RX0_IRQn 1 */ + 213:Core/Src/stm32f3xx_it.c **** } + 292 .loc 1 213 1 + 293 000a 00BF nop + 294 000c 80BD pop {r7, pc} + 295 .L17: + 296 000e 00BF .align 2 + 297 .L16: + 298 0010 00000000 .word hcan + 299 .cfi_endproc + 300 .LFE139: + 302 .section .text.CAN_RX1_IRQHandler,"ax",%progbits + 303 .align 1 + 304 .global CAN_RX1_IRQHandler + 305 .syntax unified + 306 .thumb + 307 .thumb_func + 309 CAN_RX1_IRQHandler: + 310 .LFB140: + 214:Core/Src/stm32f3xx_it.c **** + 215:Core/Src/stm32f3xx_it.c **** /** + 216:Core/Src/stm32f3xx_it.c **** * @brief This function handles CAN RX1 interrupt. + 217:Core/Src/stm32f3xx_it.c **** */ + 218:Core/Src/stm32f3xx_it.c **** void CAN_RX1_IRQHandler(void) + 219:Core/Src/stm32f3xx_it.c **** { + 311 .loc 1 219 1 + 312 .cfi_startproc + 313 @ args = 0, pretend = 0, frame = 0 + 314 @ frame_needed = 1, uses_anonymous_args = 0 + 315 0000 80B5 push {r7, lr} + ARM GAS /tmp/ccpm1fqH.s page 10 + + + 316 .cfi_def_cfa_offset 8 + 317 .cfi_offset 7, -8 + 318 .cfi_offset 14, -4 + 319 0002 00AF add r7, sp, #0 + 320 .cfi_def_cfa_register 7 + 220:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN CAN_RX1_IRQn 0 */ + 221:Core/Src/stm32f3xx_it.c **** + 222:Core/Src/stm32f3xx_it.c **** /* USER CODE END CAN_RX1_IRQn 0 */ + 223:Core/Src/stm32f3xx_it.c **** HAL_CAN_IRQHandler(&hcan); + 321 .loc 1 223 3 + 322 0004 0248 ldr r0, .L19 + 323 0006 FFF7FEFF bl HAL_CAN_IRQHandler + 224:Core/Src/stm32f3xx_it.c **** /* USER CODE BEGIN CAN_RX1_IRQn 1 */ + 225:Core/Src/stm32f3xx_it.c **** + 226:Core/Src/stm32f3xx_it.c **** /* USER CODE END CAN_RX1_IRQn 1 */ + 227:Core/Src/stm32f3xx_it.c **** } + 324 .loc 1 227 1 + 325 000a 00BF nop + 326 000c 80BD pop {r7, pc} + 327 .L20: + 328 000e 00BF .align 2 + 329 .L19: + 330 0010 00000000 .word hcan + 331 .cfi_endproc + 332 .LFE140: + 334 .text + 335 .Letext0: + 336 .file 2 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 337 .file 3 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 338 .file 4 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + 339 .file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h" + 340 .file 6 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h" + 341 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h" + ARM GAS /tmp/ccpm1fqH.s page 11 + + +DEFINED SYMBOLS + *ABS*:00000000 stm32f3xx_it.c + /tmp/ccpm1fqH.s:21 .text.NMI_Handler:00000000 $t + /tmp/ccpm1fqH.s:27 .text.NMI_Handler:00000000 NMI_Handler + /tmp/ccpm1fqH.s:47 .text.HardFault_Handler:00000000 $t + /tmp/ccpm1fqH.s:53 .text.HardFault_Handler:00000000 HardFault_Handler + /tmp/ccpm1fqH.s:73 .text.MemManage_Handler:00000000 $t + /tmp/ccpm1fqH.s:79 .text.MemManage_Handler:00000000 MemManage_Handler + /tmp/ccpm1fqH.s:99 .text.BusFault_Handler:00000000 $t + /tmp/ccpm1fqH.s:105 .text.BusFault_Handler:00000000 BusFault_Handler + /tmp/ccpm1fqH.s:125 .text.UsageFault_Handler:00000000 $t + /tmp/ccpm1fqH.s:131 .text.UsageFault_Handler:00000000 UsageFault_Handler + /tmp/ccpm1fqH.s:151 .text.SVC_Handler:00000000 $t + /tmp/ccpm1fqH.s:157 .text.SVC_Handler:00000000 SVC_Handler + /tmp/ccpm1fqH.s:182 .text.DebugMon_Handler:00000000 $t + /tmp/ccpm1fqH.s:188 .text.DebugMon_Handler:00000000 DebugMon_Handler + /tmp/ccpm1fqH.s:213 .text.PendSV_Handler:00000000 $t + /tmp/ccpm1fqH.s:219 .text.PendSV_Handler:00000000 PendSV_Handler + /tmp/ccpm1fqH.s:244 .text.SysTick_Handler:00000000 $t + /tmp/ccpm1fqH.s:250 .text.SysTick_Handler:00000000 SysTick_Handler + /tmp/ccpm1fqH.s:271 .text.USB_LP_CAN_RX0_IRQHandler:00000000 $t + /tmp/ccpm1fqH.s:277 .text.USB_LP_CAN_RX0_IRQHandler:00000000 USB_LP_CAN_RX0_IRQHandler + /tmp/ccpm1fqH.s:298 .text.USB_LP_CAN_RX0_IRQHandler:00000010 $d + /tmp/ccpm1fqH.s:303 .text.CAN_RX1_IRQHandler:00000000 $t + /tmp/ccpm1fqH.s:309 .text.CAN_RX1_IRQHandler:00000000 CAN_RX1_IRQHandler + /tmp/ccpm1fqH.s:330 .text.CAN_RX1_IRQHandler:00000010 $d + +UNDEFINED SYMBOLS +HAL_IncTick +HAL_CAN_IRQHandler +hcan diff --git a/Software/build/stm32f3xx_it.o b/Software/build/stm32f3xx_it.o new file mode 100644 index 0000000..9a94e20 Binary files /dev/null and b/Software/build/stm32f3xx_it.o differ diff --git a/Software/build/syscalls.d b/Software/build/syscalls.d new file mode 100644 index 0000000..8efb132 --- /dev/null +++ b/Software/build/syscalls.d @@ -0,0 +1 @@ +build/syscalls.o: Core/Src/syscalls.c diff --git a/Software/build/syscalls.lst b/Software/build/syscalls.lst new file mode 100644 index 0000000..ec39595 --- /dev/null +++ b/Software/build/syscalls.lst @@ -0,0 +1,1038 @@ +ARM GAS /tmp/ccqbk4Th.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 6 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "syscalls.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Core/Src/syscalls.c" + 20 .global __env + 21 .section .bss.__env,"aw",%nobits + 22 .align 2 + 25 __env: + 26 0000 00000000 .space 4 + 27 .global environ + 28 .section .data.environ,"aw" + 29 .align 2 + 32 environ: + 33 0000 00000000 .word __env + 34 .section .text.initialise_monitor_handles,"ax",%progbits + 35 .align 1 + 36 .global initialise_monitor_handles + 37 .syntax unified + 38 .thumb + 39 .thumb_func + 41 initialise_monitor_handles: + 42 .LFB25: + 1:Core/Src/syscalls.c **** /** + 2:Core/Src/syscalls.c **** ****************************************************************************** + 3:Core/Src/syscalls.c **** * @file syscalls.c + 4:Core/Src/syscalls.c **** * @author Auto-generated by STM32CubeMX + 5:Core/Src/syscalls.c **** * @brief Minimal System calls file + 6:Core/Src/syscalls.c **** * + 7:Core/Src/syscalls.c **** * For more information about which c-functions + 8:Core/Src/syscalls.c **** * need which of these lowlevel functions + 9:Core/Src/syscalls.c **** * please consult the Newlib libc-manual + 10:Core/Src/syscalls.c **** ****************************************************************************** + 11:Core/Src/syscalls.c **** * @attention + 12:Core/Src/syscalls.c **** * + 13:Core/Src/syscalls.c **** * Copyright (c) 2020-2024 STMicroelectronics. + 14:Core/Src/syscalls.c **** * All rights reserved. + 15:Core/Src/syscalls.c **** * + 16:Core/Src/syscalls.c **** * This software is licensed under terms that can be found in the LICENSE file + 17:Core/Src/syscalls.c **** * in the root directory of this software component. + 18:Core/Src/syscalls.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 19:Core/Src/syscalls.c **** * + 20:Core/Src/syscalls.c **** ****************************************************************************** + ARM GAS /tmp/ccqbk4Th.s page 2 + + + 21:Core/Src/syscalls.c **** */ + 22:Core/Src/syscalls.c **** + 23:Core/Src/syscalls.c **** /* Includes */ + 24:Core/Src/syscalls.c **** #include + 25:Core/Src/syscalls.c **** #include + 26:Core/Src/syscalls.c **** #include + 27:Core/Src/syscalls.c **** #include + 28:Core/Src/syscalls.c **** #include + 29:Core/Src/syscalls.c **** #include + 30:Core/Src/syscalls.c **** #include + 31:Core/Src/syscalls.c **** #include + 32:Core/Src/syscalls.c **** + 33:Core/Src/syscalls.c **** + 34:Core/Src/syscalls.c **** /* Variables */ + 35:Core/Src/syscalls.c **** extern int __io_putchar(int ch) __attribute__((weak)); + 36:Core/Src/syscalls.c **** extern int __io_getchar(void) __attribute__((weak)); + 37:Core/Src/syscalls.c **** + 38:Core/Src/syscalls.c **** + 39:Core/Src/syscalls.c **** char *__env[1] = { 0 }; + 40:Core/Src/syscalls.c **** char **environ = __env; + 41:Core/Src/syscalls.c **** + 42:Core/Src/syscalls.c **** + 43:Core/Src/syscalls.c **** /* Functions */ + 44:Core/Src/syscalls.c **** void initialise_monitor_handles() + 45:Core/Src/syscalls.c **** { + 43 .loc 1 45 1 + 44 .cfi_startproc + 45 @ args = 0, pretend = 0, frame = 0 + 46 @ frame_needed = 1, uses_anonymous_args = 0 + 47 @ link register save eliminated. + 48 0000 80B4 push {r7} + 49 .cfi_def_cfa_offset 4 + 50 .cfi_offset 7, -4 + 51 0002 00AF add r7, sp, #0 + 52 .cfi_def_cfa_register 7 + 46:Core/Src/syscalls.c **** } + 53 .loc 1 46 1 + 54 0004 00BF nop + 55 0006 BD46 mov sp, r7 + 56 .cfi_def_cfa_register 13 + 57 @ sp needed + 58 0008 5DF8047B ldr r7, [sp], #4 + 59 .cfi_restore 7 + 60 .cfi_def_cfa_offset 0 + 61 000c 7047 bx lr + 62 .cfi_endproc + 63 .LFE25: + 65 .section .text._getpid,"ax",%progbits + 66 .align 1 + 67 .global _getpid + 68 .syntax unified + 69 .thumb + 70 .thumb_func + 72 _getpid: + 73 .LFB26: + 47:Core/Src/syscalls.c **** + 48:Core/Src/syscalls.c **** int _getpid(void) + ARM GAS /tmp/ccqbk4Th.s page 3 + + + 49:Core/Src/syscalls.c **** { + 74 .loc 1 49 1 + 75 .cfi_startproc + 76 @ args = 0, pretend = 0, frame = 0 + 77 @ frame_needed = 1, uses_anonymous_args = 0 + 78 @ link register save eliminated. + 79 0000 80B4 push {r7} + 80 .cfi_def_cfa_offset 4 + 81 .cfi_offset 7, -4 + 82 0002 00AF add r7, sp, #0 + 83 .cfi_def_cfa_register 7 + 50:Core/Src/syscalls.c **** return 1; + 84 .loc 1 50 10 + 85 0004 0123 movs r3, #1 + 51:Core/Src/syscalls.c **** } + 86 .loc 1 51 1 + 87 0006 1846 mov r0, r3 + 88 0008 BD46 mov sp, r7 + 89 .cfi_def_cfa_register 13 + 90 @ sp needed + 91 000a 5DF8047B ldr r7, [sp], #4 + 92 .cfi_restore 7 + 93 .cfi_def_cfa_offset 0 + 94 000e 7047 bx lr + 95 .cfi_endproc + 96 .LFE26: + 98 .section .text._kill,"ax",%progbits + 99 .align 1 + 100 .global _kill + 101 .syntax unified + 102 .thumb + 103 .thumb_func + 105 _kill: + 106 .LFB27: + 52:Core/Src/syscalls.c **** + 53:Core/Src/syscalls.c **** int _kill(int pid, int sig) + 54:Core/Src/syscalls.c **** { + 107 .loc 1 54 1 + 108 .cfi_startproc + 109 @ args = 0, pretend = 0, frame = 8 + 110 @ frame_needed = 1, uses_anonymous_args = 0 + 111 0000 80B5 push {r7, lr} + 112 .cfi_def_cfa_offset 8 + 113 .cfi_offset 7, -8 + 114 .cfi_offset 14, -4 + 115 0002 82B0 sub sp, sp, #8 + 116 .cfi_def_cfa_offset 16 + 117 0004 00AF add r7, sp, #0 + 118 .cfi_def_cfa_register 7 + 119 0006 7860 str r0, [r7, #4] + 120 0008 3960 str r1, [r7] + 55:Core/Src/syscalls.c **** (void)pid; + 56:Core/Src/syscalls.c **** (void)sig; + 57:Core/Src/syscalls.c **** errno = EINVAL; + 121 .loc 1 57 3 + 122 000a FFF7FEFF bl __errno + 123 000e 0346 mov r3, r0 + ARM GAS /tmp/ccqbk4Th.s page 4 + + + 124 .loc 1 57 9 discriminator 1 + 125 0010 1622 movs r2, #22 + 126 0012 1A60 str r2, [r3] + 58:Core/Src/syscalls.c **** return -1; + 127 .loc 1 58 10 + 128 0014 4FF0FF33 mov r3, #-1 + 59:Core/Src/syscalls.c **** } + 129 .loc 1 59 1 + 130 0018 1846 mov r0, r3 + 131 001a 0837 adds r7, r7, #8 + 132 .cfi_def_cfa_offset 8 + 133 001c BD46 mov sp, r7 + 134 .cfi_def_cfa_register 13 + 135 @ sp needed + 136 001e 80BD pop {r7, pc} + 137 .cfi_endproc + 138 .LFE27: + 140 .section .text._exit,"ax",%progbits + 141 .align 1 + 142 .global _exit + 143 .syntax unified + 144 .thumb + 145 .thumb_func + 147 _exit: + 148 .LFB28: + 60:Core/Src/syscalls.c **** + 61:Core/Src/syscalls.c **** void _exit (int status) + 62:Core/Src/syscalls.c **** { + 149 .loc 1 62 1 + 150 .cfi_startproc + 151 @ args = 0, pretend = 0, frame = 8 + 152 @ frame_needed = 1, uses_anonymous_args = 0 + 153 0000 80B5 push {r7, lr} + 154 .cfi_def_cfa_offset 8 + 155 .cfi_offset 7, -8 + 156 .cfi_offset 14, -4 + 157 0002 82B0 sub sp, sp, #8 + 158 .cfi_def_cfa_offset 16 + 159 0004 00AF add r7, sp, #0 + 160 .cfi_def_cfa_register 7 + 161 0006 7860 str r0, [r7, #4] + 63:Core/Src/syscalls.c **** _kill(status, -1); + 162 .loc 1 63 3 + 163 0008 4FF0FF31 mov r1, #-1 + 164 000c 7868 ldr r0, [r7, #4] + 165 000e FFF7FEFF bl _kill + 166 .L7: + 64:Core/Src/syscalls.c **** while (1) {} /* Make sure we hang here */ + 167 .loc 1 64 9 + 168 0012 00BF nop + 169 0014 FDE7 b .L7 + 170 .cfi_endproc + 171 .LFE28: + 173 .section .text._read,"ax",%progbits + 174 .align 1 + 175 .weak _read + 176 .syntax unified + ARM GAS /tmp/ccqbk4Th.s page 5 + + + 177 .thumb + 178 .thumb_func + 180 _read: + 181 .LFB29: + 65:Core/Src/syscalls.c **** } + 66:Core/Src/syscalls.c **** + 67:Core/Src/syscalls.c **** __attribute__((weak)) int _read(int file, char *ptr, int len) + 68:Core/Src/syscalls.c **** { + 182 .loc 1 68 1 + 183 .cfi_startproc + 184 @ args = 0, pretend = 0, frame = 24 + 185 @ frame_needed = 1, uses_anonymous_args = 0 + 186 0000 80B5 push {r7, lr} + 187 .cfi_def_cfa_offset 8 + 188 .cfi_offset 7, -8 + 189 .cfi_offset 14, -4 + 190 0002 86B0 sub sp, sp, #24 + 191 .cfi_def_cfa_offset 32 + 192 0004 00AF add r7, sp, #0 + 193 .cfi_def_cfa_register 7 + 194 0006 F860 str r0, [r7, #12] + 195 0008 B960 str r1, [r7, #8] + 196 000a 7A60 str r2, [r7, #4] + 69:Core/Src/syscalls.c **** (void)file; + 70:Core/Src/syscalls.c **** int DataIdx; + 71:Core/Src/syscalls.c **** + 72:Core/Src/syscalls.c **** for (DataIdx = 0; DataIdx < len; DataIdx++) + 197 .loc 1 72 16 + 198 000c 0023 movs r3, #0 + 199 000e 7B61 str r3, [r7, #20] + 200 .loc 1 72 3 + 201 0010 0AE0 b .L9 + 202 .L10: + 73:Core/Src/syscalls.c **** { + 74:Core/Src/syscalls.c **** *ptr++ = __io_getchar(); + 203 .loc 1 74 14 + 204 0012 FFF7FEFF bl __io_getchar + 205 0016 0146 mov r1, r0 + 206 .loc 1 74 9 discriminator 1 + 207 0018 BB68 ldr r3, [r7, #8] + 208 001a 5A1C adds r2, r3, #1 + 209 001c BA60 str r2, [r7, #8] + 210 .loc 1 74 12 discriminator 1 + 211 001e CAB2 uxtb r2, r1 + 212 0020 1A70 strb r2, [r3] + 72:Core/Src/syscalls.c **** { + 213 .loc 1 72 43 discriminator 3 + 214 0022 7B69 ldr r3, [r7, #20] + 215 0024 0133 adds r3, r3, #1 + 216 0026 7B61 str r3, [r7, #20] + 217 .L9: + 72:Core/Src/syscalls.c **** { + 218 .loc 1 72 29 discriminator 1 + 219 0028 7A69 ldr r2, [r7, #20] + 220 002a 7B68 ldr r3, [r7, #4] + 221 002c 9A42 cmp r2, r3 + 222 002e F0DB blt .L10 + ARM GAS /tmp/ccqbk4Th.s page 6 + + + 75:Core/Src/syscalls.c **** } + 76:Core/Src/syscalls.c **** + 77:Core/Src/syscalls.c **** return len; + 223 .loc 1 77 10 + 224 0030 7B68 ldr r3, [r7, #4] + 78:Core/Src/syscalls.c **** } + 225 .loc 1 78 1 + 226 0032 1846 mov r0, r3 + 227 0034 1837 adds r7, r7, #24 + 228 .cfi_def_cfa_offset 8 + 229 0036 BD46 mov sp, r7 + 230 .cfi_def_cfa_register 13 + 231 @ sp needed + 232 0038 80BD pop {r7, pc} + 233 .cfi_endproc + 234 .LFE29: + 236 .section .text._write,"ax",%progbits + 237 .align 1 + 238 .weak _write + 239 .syntax unified + 240 .thumb + 241 .thumb_func + 243 _write: + 244 .LFB30: + 79:Core/Src/syscalls.c **** + 80:Core/Src/syscalls.c **** __attribute__((weak)) int _write(int file, char *ptr, int len) + 81:Core/Src/syscalls.c **** { + 245 .loc 1 81 1 + 246 .cfi_startproc + 247 @ args = 0, pretend = 0, frame = 24 + 248 @ frame_needed = 1, uses_anonymous_args = 0 + 249 0000 80B5 push {r7, lr} + 250 .cfi_def_cfa_offset 8 + 251 .cfi_offset 7, -8 + 252 .cfi_offset 14, -4 + 253 0002 86B0 sub sp, sp, #24 + 254 .cfi_def_cfa_offset 32 + 255 0004 00AF add r7, sp, #0 + 256 .cfi_def_cfa_register 7 + 257 0006 F860 str r0, [r7, #12] + 258 0008 B960 str r1, [r7, #8] + 259 000a 7A60 str r2, [r7, #4] + 82:Core/Src/syscalls.c **** (void)file; + 83:Core/Src/syscalls.c **** int DataIdx; + 84:Core/Src/syscalls.c **** + 85:Core/Src/syscalls.c **** for (DataIdx = 0; DataIdx < len; DataIdx++) + 260 .loc 1 85 16 + 261 000c 0023 movs r3, #0 + 262 000e 7B61 str r3, [r7, #20] + 263 .loc 1 85 3 + 264 0010 09E0 b .L13 + 265 .L14: + 86:Core/Src/syscalls.c **** { + 87:Core/Src/syscalls.c **** __io_putchar(*ptr++); + 266 .loc 1 87 22 + 267 0012 BB68 ldr r3, [r7, #8] + 268 0014 5A1C adds r2, r3, #1 + ARM GAS /tmp/ccqbk4Th.s page 7 + + + 269 0016 BA60 str r2, [r7, #8] + 270 .loc 1 87 18 + 271 0018 1B78 ldrb r3, [r3] @ zero_extendqisi2 + 272 .loc 1 87 5 + 273 001a 1846 mov r0, r3 + 274 001c FFF7FEFF bl __io_putchar + 85:Core/Src/syscalls.c **** { + 275 .loc 1 85 43 discriminator 3 + 276 0020 7B69 ldr r3, [r7, #20] + 277 0022 0133 adds r3, r3, #1 + 278 0024 7B61 str r3, [r7, #20] + 279 .L13: + 85:Core/Src/syscalls.c **** { + 280 .loc 1 85 29 discriminator 1 + 281 0026 7A69 ldr r2, [r7, #20] + 282 0028 7B68 ldr r3, [r7, #4] + 283 002a 9A42 cmp r2, r3 + 284 002c F1DB blt .L14 + 88:Core/Src/syscalls.c **** } + 89:Core/Src/syscalls.c **** return len; + 285 .loc 1 89 10 + 286 002e 7B68 ldr r3, [r7, #4] + 90:Core/Src/syscalls.c **** } + 287 .loc 1 90 1 + 288 0030 1846 mov r0, r3 + 289 0032 1837 adds r7, r7, #24 + 290 .cfi_def_cfa_offset 8 + 291 0034 BD46 mov sp, r7 + 292 .cfi_def_cfa_register 13 + 293 @ sp needed + 294 0036 80BD pop {r7, pc} + 295 .cfi_endproc + 296 .LFE30: + 298 .section .text._close,"ax",%progbits + 299 .align 1 + 300 .global _close + 301 .syntax unified + 302 .thumb + 303 .thumb_func + 305 _close: + 306 .LFB31: + 91:Core/Src/syscalls.c **** + 92:Core/Src/syscalls.c **** int _close(int file) + 93:Core/Src/syscalls.c **** { + 307 .loc 1 93 1 + 308 .cfi_startproc + 309 @ args = 0, pretend = 0, frame = 8 + 310 @ frame_needed = 1, uses_anonymous_args = 0 + 311 @ link register save eliminated. + 312 0000 80B4 push {r7} + 313 .cfi_def_cfa_offset 4 + 314 .cfi_offset 7, -4 + 315 0002 83B0 sub sp, sp, #12 + 316 .cfi_def_cfa_offset 16 + 317 0004 00AF add r7, sp, #0 + 318 .cfi_def_cfa_register 7 + 319 0006 7860 str r0, [r7, #4] + ARM GAS /tmp/ccqbk4Th.s page 8 + + + 94:Core/Src/syscalls.c **** (void)file; + 95:Core/Src/syscalls.c **** return -1; + 320 .loc 1 95 10 + 321 0008 4FF0FF33 mov r3, #-1 + 96:Core/Src/syscalls.c **** } + 322 .loc 1 96 1 + 323 000c 1846 mov r0, r3 + 324 000e 0C37 adds r7, r7, #12 + 325 .cfi_def_cfa_offset 4 + 326 0010 BD46 mov sp, r7 + 327 .cfi_def_cfa_register 13 + 328 @ sp needed + 329 0012 5DF8047B ldr r7, [sp], #4 + 330 .cfi_restore 7 + 331 .cfi_def_cfa_offset 0 + 332 0016 7047 bx lr + 333 .cfi_endproc + 334 .LFE31: + 336 .section .text._fstat,"ax",%progbits + 337 .align 1 + 338 .global _fstat + 339 .syntax unified + 340 .thumb + 341 .thumb_func + 343 _fstat: + 344 .LFB32: + 97:Core/Src/syscalls.c **** + 98:Core/Src/syscalls.c **** + 99:Core/Src/syscalls.c **** int _fstat(int file, struct stat *st) + 100:Core/Src/syscalls.c **** { + 345 .loc 1 100 1 + 346 .cfi_startproc + 347 @ args = 0, pretend = 0, frame = 8 + 348 @ frame_needed = 1, uses_anonymous_args = 0 + 349 @ link register save eliminated. + 350 0000 80B4 push {r7} + 351 .cfi_def_cfa_offset 4 + 352 .cfi_offset 7, -4 + 353 0002 83B0 sub sp, sp, #12 + 354 .cfi_def_cfa_offset 16 + 355 0004 00AF add r7, sp, #0 + 356 .cfi_def_cfa_register 7 + 357 0006 7860 str r0, [r7, #4] + 358 0008 3960 str r1, [r7] + 101:Core/Src/syscalls.c **** (void)file; + 102:Core/Src/syscalls.c **** st->st_mode = S_IFCHR; + 359 .loc 1 102 15 + 360 000a 3B68 ldr r3, [r7] + 361 000c 4FF40052 mov r2, #8192 + 362 0010 5A60 str r2, [r3, #4] + 103:Core/Src/syscalls.c **** return 0; + 363 .loc 1 103 10 + 364 0012 0023 movs r3, #0 + 104:Core/Src/syscalls.c **** } + 365 .loc 1 104 1 + 366 0014 1846 mov r0, r3 + 367 0016 0C37 adds r7, r7, #12 + ARM GAS /tmp/ccqbk4Th.s page 9 + + + 368 .cfi_def_cfa_offset 4 + 369 0018 BD46 mov sp, r7 + 370 .cfi_def_cfa_register 13 + 371 @ sp needed + 372 001a 5DF8047B ldr r7, [sp], #4 + 373 .cfi_restore 7 + 374 .cfi_def_cfa_offset 0 + 375 001e 7047 bx lr + 376 .cfi_endproc + 377 .LFE32: + 379 .section .text._isatty,"ax",%progbits + 380 .align 1 + 381 .global _isatty + 382 .syntax unified + 383 .thumb + 384 .thumb_func + 386 _isatty: + 387 .LFB33: + 105:Core/Src/syscalls.c **** + 106:Core/Src/syscalls.c **** int _isatty(int file) + 107:Core/Src/syscalls.c **** { + 388 .loc 1 107 1 + 389 .cfi_startproc + 390 @ args = 0, pretend = 0, frame = 8 + 391 @ frame_needed = 1, uses_anonymous_args = 0 + 392 @ link register save eliminated. + 393 0000 80B4 push {r7} + 394 .cfi_def_cfa_offset 4 + 395 .cfi_offset 7, -4 + 396 0002 83B0 sub sp, sp, #12 + 397 .cfi_def_cfa_offset 16 + 398 0004 00AF add r7, sp, #0 + 399 .cfi_def_cfa_register 7 + 400 0006 7860 str r0, [r7, #4] + 108:Core/Src/syscalls.c **** (void)file; + 109:Core/Src/syscalls.c **** return 1; + 401 .loc 1 109 10 + 402 0008 0123 movs r3, #1 + 110:Core/Src/syscalls.c **** } + 403 .loc 1 110 1 + 404 000a 1846 mov r0, r3 + 405 000c 0C37 adds r7, r7, #12 + 406 .cfi_def_cfa_offset 4 + 407 000e BD46 mov sp, r7 + 408 .cfi_def_cfa_register 13 + 409 @ sp needed + 410 0010 5DF8047B ldr r7, [sp], #4 + 411 .cfi_restore 7 + 412 .cfi_def_cfa_offset 0 + 413 0014 7047 bx lr + 414 .cfi_endproc + 415 .LFE33: + 417 .section .text._lseek,"ax",%progbits + 418 .align 1 + 419 .global _lseek + 420 .syntax unified + 421 .thumb + ARM GAS /tmp/ccqbk4Th.s page 10 + + + 422 .thumb_func + 424 _lseek: + 425 .LFB34: + 111:Core/Src/syscalls.c **** + 112:Core/Src/syscalls.c **** int _lseek(int file, int ptr, int dir) + 113:Core/Src/syscalls.c **** { + 426 .loc 1 113 1 + 427 .cfi_startproc + 428 @ args = 0, pretend = 0, frame = 16 + 429 @ frame_needed = 1, uses_anonymous_args = 0 + 430 @ link register save eliminated. + 431 0000 80B4 push {r7} + 432 .cfi_def_cfa_offset 4 + 433 .cfi_offset 7, -4 + 434 0002 85B0 sub sp, sp, #20 + 435 .cfi_def_cfa_offset 24 + 436 0004 00AF add r7, sp, #0 + 437 .cfi_def_cfa_register 7 + 438 0006 F860 str r0, [r7, #12] + 439 0008 B960 str r1, [r7, #8] + 440 000a 7A60 str r2, [r7, #4] + 114:Core/Src/syscalls.c **** (void)file; + 115:Core/Src/syscalls.c **** (void)ptr; + 116:Core/Src/syscalls.c **** (void)dir; + 117:Core/Src/syscalls.c **** return 0; + 441 .loc 1 117 10 + 442 000c 0023 movs r3, #0 + 118:Core/Src/syscalls.c **** } + 443 .loc 1 118 1 + 444 000e 1846 mov r0, r3 + 445 0010 1437 adds r7, r7, #20 + 446 .cfi_def_cfa_offset 4 + 447 0012 BD46 mov sp, r7 + 448 .cfi_def_cfa_register 13 + 449 @ sp needed + 450 0014 5DF8047B ldr r7, [sp], #4 + 451 .cfi_restore 7 + 452 .cfi_def_cfa_offset 0 + 453 0018 7047 bx lr + 454 .cfi_endproc + 455 .LFE34: + 457 .section .text._open,"ax",%progbits + 458 .align 1 + 459 .global _open + 460 .syntax unified + 461 .thumb + 462 .thumb_func + 464 _open: + 465 .LFB35: + 119:Core/Src/syscalls.c **** + 120:Core/Src/syscalls.c **** int _open(char *path, int flags, ...) + 121:Core/Src/syscalls.c **** { + 466 .loc 1 121 1 + 467 .cfi_startproc + 468 @ args = 4, pretend = 12, frame = 8 + 469 @ frame_needed = 1, uses_anonymous_args = 1 + 470 @ link register save eliminated. + ARM GAS /tmp/ccqbk4Th.s page 11 + + + 471 0000 0EB4 push {r1, r2, r3} + 472 .cfi_def_cfa_offset 12 + 473 .cfi_offset 1, -12 + 474 .cfi_offset 2, -8 + 475 .cfi_offset 3, -4 + 476 0002 80B4 push {r7} + 477 .cfi_def_cfa_offset 16 + 478 .cfi_offset 7, -16 + 479 0004 82B0 sub sp, sp, #8 + 480 .cfi_def_cfa_offset 24 + 481 0006 00AF add r7, sp, #0 + 482 .cfi_def_cfa_register 7 + 483 0008 7860 str r0, [r7, #4] + 122:Core/Src/syscalls.c **** (void)path; + 123:Core/Src/syscalls.c **** (void)flags; + 124:Core/Src/syscalls.c **** /* Pretend like we always fail */ + 125:Core/Src/syscalls.c **** return -1; + 484 .loc 1 125 10 + 485 000a 4FF0FF33 mov r3, #-1 + 126:Core/Src/syscalls.c **** } + 486 .loc 1 126 1 + 487 000e 1846 mov r0, r3 + 488 0010 0837 adds r7, r7, #8 + 489 .cfi_def_cfa_offset 16 + 490 0012 BD46 mov sp, r7 + 491 .cfi_def_cfa_register 13 + 492 @ sp needed + 493 0014 5DF8047B ldr r7, [sp], #4 + 494 .cfi_restore 7 + 495 .cfi_def_cfa_offset 12 + 496 0018 03B0 add sp, sp, #12 + 497 .cfi_restore 3 + 498 .cfi_restore 2 + 499 .cfi_restore 1 + 500 .cfi_def_cfa_offset 0 + 501 001a 7047 bx lr + 502 .cfi_endproc + 503 .LFE35: + 505 .section .text._wait,"ax",%progbits + 506 .align 1 + 507 .global _wait + 508 .syntax unified + 509 .thumb + 510 .thumb_func + 512 _wait: + 513 .LFB36: + 127:Core/Src/syscalls.c **** + 128:Core/Src/syscalls.c **** int _wait(int *status) + 129:Core/Src/syscalls.c **** { + 514 .loc 1 129 1 + 515 .cfi_startproc + 516 @ args = 0, pretend = 0, frame = 8 + 517 @ frame_needed = 1, uses_anonymous_args = 0 + 518 0000 80B5 push {r7, lr} + 519 .cfi_def_cfa_offset 8 + 520 .cfi_offset 7, -8 + 521 .cfi_offset 14, -4 + ARM GAS /tmp/ccqbk4Th.s page 12 + + + 522 0002 82B0 sub sp, sp, #8 + 523 .cfi_def_cfa_offset 16 + 524 0004 00AF add r7, sp, #0 + 525 .cfi_def_cfa_register 7 + 526 0006 7860 str r0, [r7, #4] + 130:Core/Src/syscalls.c **** (void)status; + 131:Core/Src/syscalls.c **** errno = ECHILD; + 527 .loc 1 131 3 + 528 0008 FFF7FEFF bl __errno + 529 000c 0346 mov r3, r0 + 530 .loc 1 131 9 discriminator 1 + 531 000e 0A22 movs r2, #10 + 532 0010 1A60 str r2, [r3] + 132:Core/Src/syscalls.c **** return -1; + 533 .loc 1 132 10 + 534 0012 4FF0FF33 mov r3, #-1 + 133:Core/Src/syscalls.c **** } + 535 .loc 1 133 1 + 536 0016 1846 mov r0, r3 + 537 0018 0837 adds r7, r7, #8 + 538 .cfi_def_cfa_offset 8 + 539 001a BD46 mov sp, r7 + 540 .cfi_def_cfa_register 13 + 541 @ sp needed + 542 001c 80BD pop {r7, pc} + 543 .cfi_endproc + 544 .LFE36: + 546 .section .text._unlink,"ax",%progbits + 547 .align 1 + 548 .global _unlink + 549 .syntax unified + 550 .thumb + 551 .thumb_func + 553 _unlink: + 554 .LFB37: + 134:Core/Src/syscalls.c **** + 135:Core/Src/syscalls.c **** int _unlink(char *name) + 136:Core/Src/syscalls.c **** { + 555 .loc 1 136 1 + 556 .cfi_startproc + 557 @ args = 0, pretend = 0, frame = 8 + 558 @ frame_needed = 1, uses_anonymous_args = 0 + 559 0000 80B5 push {r7, lr} + 560 .cfi_def_cfa_offset 8 + 561 .cfi_offset 7, -8 + 562 .cfi_offset 14, -4 + 563 0002 82B0 sub sp, sp, #8 + 564 .cfi_def_cfa_offset 16 + 565 0004 00AF add r7, sp, #0 + 566 .cfi_def_cfa_register 7 + 567 0006 7860 str r0, [r7, #4] + 137:Core/Src/syscalls.c **** (void)name; + 138:Core/Src/syscalls.c **** errno = ENOENT; + 568 .loc 1 138 3 + 569 0008 FFF7FEFF bl __errno + 570 000c 0346 mov r3, r0 + 571 .loc 1 138 9 discriminator 1 + ARM GAS /tmp/ccqbk4Th.s page 13 + + + 572 000e 0222 movs r2, #2 + 573 0010 1A60 str r2, [r3] + 139:Core/Src/syscalls.c **** return -1; + 574 .loc 1 139 10 + 575 0012 4FF0FF33 mov r3, #-1 + 140:Core/Src/syscalls.c **** } + 576 .loc 1 140 1 + 577 0016 1846 mov r0, r3 + 578 0018 0837 adds r7, r7, #8 + 579 .cfi_def_cfa_offset 8 + 580 001a BD46 mov sp, r7 + 581 .cfi_def_cfa_register 13 + 582 @ sp needed + 583 001c 80BD pop {r7, pc} + 584 .cfi_endproc + 585 .LFE37: + 587 .section .text._times,"ax",%progbits + 588 .align 1 + 589 .global _times + 590 .syntax unified + 591 .thumb + 592 .thumb_func + 594 _times: + 595 .LFB38: + 141:Core/Src/syscalls.c **** + 142:Core/Src/syscalls.c **** int _times(struct tms *buf) + 143:Core/Src/syscalls.c **** { + 596 .loc 1 143 1 + 597 .cfi_startproc + 598 @ args = 0, pretend = 0, frame = 8 + 599 @ frame_needed = 1, uses_anonymous_args = 0 + 600 @ link register save eliminated. + 601 0000 80B4 push {r7} + 602 .cfi_def_cfa_offset 4 + 603 .cfi_offset 7, -4 + 604 0002 83B0 sub sp, sp, #12 + 605 .cfi_def_cfa_offset 16 + 606 0004 00AF add r7, sp, #0 + 607 .cfi_def_cfa_register 7 + 608 0006 7860 str r0, [r7, #4] + 144:Core/Src/syscalls.c **** (void)buf; + 145:Core/Src/syscalls.c **** return -1; + 609 .loc 1 145 10 + 610 0008 4FF0FF33 mov r3, #-1 + 146:Core/Src/syscalls.c **** } + 611 .loc 1 146 1 + 612 000c 1846 mov r0, r3 + 613 000e 0C37 adds r7, r7, #12 + 614 .cfi_def_cfa_offset 4 + 615 0010 BD46 mov sp, r7 + 616 .cfi_def_cfa_register 13 + 617 @ sp needed + 618 0012 5DF8047B ldr r7, [sp], #4 + 619 .cfi_restore 7 + 620 .cfi_def_cfa_offset 0 + 621 0016 7047 bx lr + 622 .cfi_endproc + ARM GAS /tmp/ccqbk4Th.s page 14 + + + 623 .LFE38: + 625 .section .text._stat,"ax",%progbits + 626 .align 1 + 627 .global _stat + 628 .syntax unified + 629 .thumb + 630 .thumb_func + 632 _stat: + 633 .LFB39: + 147:Core/Src/syscalls.c **** + 148:Core/Src/syscalls.c **** int _stat(char *file, struct stat *st) + 149:Core/Src/syscalls.c **** { + 634 .loc 1 149 1 + 635 .cfi_startproc + 636 @ args = 0, pretend = 0, frame = 8 + 637 @ frame_needed = 1, uses_anonymous_args = 0 + 638 @ link register save eliminated. + 639 0000 80B4 push {r7} + 640 .cfi_def_cfa_offset 4 + 641 .cfi_offset 7, -4 + 642 0002 83B0 sub sp, sp, #12 + 643 .cfi_def_cfa_offset 16 + 644 0004 00AF add r7, sp, #0 + 645 .cfi_def_cfa_register 7 + 646 0006 7860 str r0, [r7, #4] + 647 0008 3960 str r1, [r7] + 150:Core/Src/syscalls.c **** (void)file; + 151:Core/Src/syscalls.c **** st->st_mode = S_IFCHR; + 648 .loc 1 151 15 + 649 000a 3B68 ldr r3, [r7] + 650 000c 4FF40052 mov r2, #8192 + 651 0010 5A60 str r2, [r3, #4] + 152:Core/Src/syscalls.c **** return 0; + 652 .loc 1 152 10 + 653 0012 0023 movs r3, #0 + 153:Core/Src/syscalls.c **** } + 654 .loc 1 153 1 + 655 0014 1846 mov r0, r3 + 656 0016 0C37 adds r7, r7, #12 + 657 .cfi_def_cfa_offset 4 + 658 0018 BD46 mov sp, r7 + 659 .cfi_def_cfa_register 13 + 660 @ sp needed + 661 001a 5DF8047B ldr r7, [sp], #4 + 662 .cfi_restore 7 + 663 .cfi_def_cfa_offset 0 + 664 001e 7047 bx lr + 665 .cfi_endproc + 666 .LFE39: + 668 .section .text._link,"ax",%progbits + 669 .align 1 + 670 .global _link + 671 .syntax unified + 672 .thumb + 673 .thumb_func + 675 _link: + 676 .LFB40: + ARM GAS /tmp/ccqbk4Th.s page 15 + + + 154:Core/Src/syscalls.c **** + 155:Core/Src/syscalls.c **** int _link(char *old, char *new) + 156:Core/Src/syscalls.c **** { + 677 .loc 1 156 1 + 678 .cfi_startproc + 679 @ args = 0, pretend = 0, frame = 8 + 680 @ frame_needed = 1, uses_anonymous_args = 0 + 681 0000 80B5 push {r7, lr} + 682 .cfi_def_cfa_offset 8 + 683 .cfi_offset 7, -8 + 684 .cfi_offset 14, -4 + 685 0002 82B0 sub sp, sp, #8 + 686 .cfi_def_cfa_offset 16 + 687 0004 00AF add r7, sp, #0 + 688 .cfi_def_cfa_register 7 + 689 0006 7860 str r0, [r7, #4] + 690 0008 3960 str r1, [r7] + 157:Core/Src/syscalls.c **** (void)old; + 158:Core/Src/syscalls.c **** (void)new; + 159:Core/Src/syscalls.c **** errno = EMLINK; + 691 .loc 1 159 3 + 692 000a FFF7FEFF bl __errno + 693 000e 0346 mov r3, r0 + 694 .loc 1 159 9 discriminator 1 + 695 0010 1F22 movs r2, #31 + 696 0012 1A60 str r2, [r3] + 160:Core/Src/syscalls.c **** return -1; + 697 .loc 1 160 10 + 698 0014 4FF0FF33 mov r3, #-1 + 161:Core/Src/syscalls.c **** } + 699 .loc 1 161 1 + 700 0018 1846 mov r0, r3 + 701 001a 0837 adds r7, r7, #8 + 702 .cfi_def_cfa_offset 8 + 703 001c BD46 mov sp, r7 + 704 .cfi_def_cfa_register 13 + 705 @ sp needed + 706 001e 80BD pop {r7, pc} + 707 .cfi_endproc + 708 .LFE40: + 710 .section .text._fork,"ax",%progbits + 711 .align 1 + 712 .global _fork + 713 .syntax unified + 714 .thumb + 715 .thumb_func + 717 _fork: + 718 .LFB41: + 162:Core/Src/syscalls.c **** + 163:Core/Src/syscalls.c **** int _fork(void) + 164:Core/Src/syscalls.c **** { + 719 .loc 1 164 1 + 720 .cfi_startproc + 721 @ args = 0, pretend = 0, frame = 0 + 722 @ frame_needed = 1, uses_anonymous_args = 0 + 723 0000 80B5 push {r7, lr} + 724 .cfi_def_cfa_offset 8 + ARM GAS /tmp/ccqbk4Th.s page 16 + + + 725 .cfi_offset 7, -8 + 726 .cfi_offset 14, -4 + 727 0002 00AF add r7, sp, #0 + 728 .cfi_def_cfa_register 7 + 165:Core/Src/syscalls.c **** errno = EAGAIN; + 729 .loc 1 165 3 + 730 0004 FFF7FEFF bl __errno + 731 0008 0346 mov r3, r0 + 732 .loc 1 165 9 discriminator 1 + 733 000a 0B22 movs r2, #11 + 734 000c 1A60 str r2, [r3] + 166:Core/Src/syscalls.c **** return -1; + 735 .loc 1 166 10 + 736 000e 4FF0FF33 mov r3, #-1 + 167:Core/Src/syscalls.c **** } + 737 .loc 1 167 1 + 738 0012 1846 mov r0, r3 + 739 0014 80BD pop {r7, pc} + 740 .cfi_endproc + 741 .LFE41: + 743 .section .text._execve,"ax",%progbits + 744 .align 1 + 745 .global _execve + 746 .syntax unified + 747 .thumb + 748 .thumb_func + 750 _execve: + 751 .LFB42: + 168:Core/Src/syscalls.c **** + 169:Core/Src/syscalls.c **** int _execve(char *name, char **argv, char **env) + 170:Core/Src/syscalls.c **** { + 752 .loc 1 170 1 + 753 .cfi_startproc + 754 @ args = 0, pretend = 0, frame = 16 + 755 @ frame_needed = 1, uses_anonymous_args = 0 + 756 0000 80B5 push {r7, lr} + 757 .cfi_def_cfa_offset 8 + 758 .cfi_offset 7, -8 + 759 .cfi_offset 14, -4 + 760 0002 84B0 sub sp, sp, #16 + 761 .cfi_def_cfa_offset 24 + 762 0004 00AF add r7, sp, #0 + 763 .cfi_def_cfa_register 7 + 764 0006 F860 str r0, [r7, #12] + 765 0008 B960 str r1, [r7, #8] + 766 000a 7A60 str r2, [r7, #4] + 171:Core/Src/syscalls.c **** (void)name; + 172:Core/Src/syscalls.c **** (void)argv; + 173:Core/Src/syscalls.c **** (void)env; + 174:Core/Src/syscalls.c **** errno = ENOMEM; + 767 .loc 1 174 3 + 768 000c FFF7FEFF bl __errno + 769 0010 0346 mov r3, r0 + 770 .loc 1 174 9 discriminator 1 + 771 0012 0C22 movs r2, #12 + 772 0014 1A60 str r2, [r3] + 175:Core/Src/syscalls.c **** return -1; + ARM GAS /tmp/ccqbk4Th.s page 17 + + + 773 .loc 1 175 10 + 774 0016 4FF0FF33 mov r3, #-1 + 176:Core/Src/syscalls.c **** } + 775 .loc 1 176 1 + 776 001a 1846 mov r0, r3 + 777 001c 1037 adds r7, r7, #16 + 778 .cfi_def_cfa_offset 8 + 779 001e BD46 mov sp, r7 + 780 .cfi_def_cfa_register 13 + 781 @ sp needed + 782 0020 80BD pop {r7, pc} + 783 .cfi_endproc + 784 .LFE42: + 786 .weak __io_putchar + 787 .weak __io_getchar + 788 .text + 789 .Letext0: + 790 .file 2 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 791 .file 3 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 792 .file 4 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 793 .file 5 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 794 .file 6 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 795 .file 7 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 796 .file 8 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 797 .file 9 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + ARM GAS /tmp/ccqbk4Th.s page 18 + + +DEFINED SYMBOLS + *ABS*:00000000 syscalls.c + /tmp/ccqbk4Th.s:25 .bss.__env:00000000 __env + /tmp/ccqbk4Th.s:22 .bss.__env:00000000 $d + /tmp/ccqbk4Th.s:32 .data.environ:00000000 environ + /tmp/ccqbk4Th.s:29 .data.environ:00000000 $d + /tmp/ccqbk4Th.s:35 .text.initialise_monitor_handles:00000000 $t + /tmp/ccqbk4Th.s:41 .text.initialise_monitor_handles:00000000 initialise_monitor_handles + /tmp/ccqbk4Th.s:66 .text._getpid:00000000 $t + /tmp/ccqbk4Th.s:72 .text._getpid:00000000 _getpid + /tmp/ccqbk4Th.s:99 .text._kill:00000000 $t + /tmp/ccqbk4Th.s:105 .text._kill:00000000 _kill + /tmp/ccqbk4Th.s:141 .text._exit:00000000 $t + /tmp/ccqbk4Th.s:147 .text._exit:00000000 _exit + /tmp/ccqbk4Th.s:174 .text._read:00000000 $t + /tmp/ccqbk4Th.s:180 .text._read:00000000 _read + /tmp/ccqbk4Th.s:237 .text._write:00000000 $t + /tmp/ccqbk4Th.s:243 .text._write:00000000 _write + /tmp/ccqbk4Th.s:299 .text._close:00000000 $t + /tmp/ccqbk4Th.s:305 .text._close:00000000 _close + /tmp/ccqbk4Th.s:337 .text._fstat:00000000 $t + /tmp/ccqbk4Th.s:343 .text._fstat:00000000 _fstat + /tmp/ccqbk4Th.s:380 .text._isatty:00000000 $t + /tmp/ccqbk4Th.s:386 .text._isatty:00000000 _isatty + /tmp/ccqbk4Th.s:418 .text._lseek:00000000 $t + /tmp/ccqbk4Th.s:424 .text._lseek:00000000 _lseek + /tmp/ccqbk4Th.s:458 .text._open:00000000 $t + /tmp/ccqbk4Th.s:464 .text._open:00000000 _open + /tmp/ccqbk4Th.s:506 .text._wait:00000000 $t + /tmp/ccqbk4Th.s:512 .text._wait:00000000 _wait + /tmp/ccqbk4Th.s:547 .text._unlink:00000000 $t + /tmp/ccqbk4Th.s:553 .text._unlink:00000000 _unlink + /tmp/ccqbk4Th.s:588 .text._times:00000000 $t + /tmp/ccqbk4Th.s:594 .text._times:00000000 _times + /tmp/ccqbk4Th.s:626 .text._stat:00000000 $t + /tmp/ccqbk4Th.s:632 .text._stat:00000000 _stat + /tmp/ccqbk4Th.s:669 .text._link:00000000 $t + /tmp/ccqbk4Th.s:675 .text._link:00000000 _link + /tmp/ccqbk4Th.s:711 .text._fork:00000000 $t + /tmp/ccqbk4Th.s:717 .text._fork:00000000 _fork + /tmp/ccqbk4Th.s:744 .text._execve:00000000 $t + /tmp/ccqbk4Th.s:750 .text._execve:00000000 _execve + +UNDEFINED SYMBOLS +__errno +__io_getchar +__io_putchar diff --git a/Software/build/syscalls.o b/Software/build/syscalls.o new file mode 100644 index 0000000..03e4e17 Binary files /dev/null and b/Software/build/syscalls.o differ diff --git a/Software/build/sysmem.d b/Software/build/sysmem.d new file mode 100644 index 0000000..5d0bd84 --- /dev/null +++ b/Software/build/sysmem.d @@ -0,0 +1 @@ +build/sysmem.o: Core/Src/sysmem.c diff --git a/Software/build/sysmem.lst b/Software/build/sysmem.lst new file mode 100644 index 0000000..63d6e9b --- /dev/null +++ b/Software/build/sysmem.lst @@ -0,0 +1,228 @@ +ARM GAS /tmp/ccQxFjE3.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 6 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "sysmem.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Core/Src/sysmem.c" + 20 .section .bss.__sbrk_heap_end,"aw",%nobits + 21 .align 2 + 24 __sbrk_heap_end: + 25 0000 00000000 .space 4 + 26 .section .text._sbrk,"ax",%progbits + 27 .align 1 + 28 .global _sbrk + 29 .syntax unified + 30 .thumb + 31 .thumb_func + 33 _sbrk: + 34 .LFB0: + 1:Core/Src/sysmem.c **** /** + 2:Core/Src/sysmem.c **** ****************************************************************************** + 3:Core/Src/sysmem.c **** * @file sysmem.c + 4:Core/Src/sysmem.c **** * @author Generated by STM32CubeMX + 5:Core/Src/sysmem.c **** * @brief System Memory calls file + 6:Core/Src/sysmem.c **** * + 7:Core/Src/sysmem.c **** * For more information about which C functions + 8:Core/Src/sysmem.c **** * need which of these lowlevel functions + 9:Core/Src/sysmem.c **** * please consult the newlib libc manual + 10:Core/Src/sysmem.c **** ****************************************************************************** + 11:Core/Src/sysmem.c **** * @attention + 12:Core/Src/sysmem.c **** * + 13:Core/Src/sysmem.c **** * Copyright (c) 2024 STMicroelectronics. + 14:Core/Src/sysmem.c **** * All rights reserved. + 15:Core/Src/sysmem.c **** * + 16:Core/Src/sysmem.c **** * This software is licensed under terms that can be found in the LICENSE file + 17:Core/Src/sysmem.c **** * in the root directory of this software component. + 18:Core/Src/sysmem.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 19:Core/Src/sysmem.c **** * + 20:Core/Src/sysmem.c **** ****************************************************************************** + 21:Core/Src/sysmem.c **** */ + 22:Core/Src/sysmem.c **** + 23:Core/Src/sysmem.c **** /* Includes */ + 24:Core/Src/sysmem.c **** #include + 25:Core/Src/sysmem.c **** #include + 26:Core/Src/sysmem.c **** + ARM GAS /tmp/ccQxFjE3.s page 2 + + + 27:Core/Src/sysmem.c **** /** + 28:Core/Src/sysmem.c **** * Pointer to the current high watermark of the heap usage + 29:Core/Src/sysmem.c **** */ + 30:Core/Src/sysmem.c **** static uint8_t *__sbrk_heap_end = NULL; + 31:Core/Src/sysmem.c **** + 32:Core/Src/sysmem.c **** /** + 33:Core/Src/sysmem.c **** * @brief _sbrk() allocates memory to the newlib heap and is used by malloc + 34:Core/Src/sysmem.c **** * and others from the C library + 35:Core/Src/sysmem.c **** * + 36:Core/Src/sysmem.c **** * @verbatim + 37:Core/Src/sysmem.c **** * ############################################################################ + 38:Core/Src/sysmem.c **** * # .data # .bss # newlib heap # MSP stack # + 39:Core/Src/sysmem.c **** * # # # # Reserved by _Min_Stack_Size # + 40:Core/Src/sysmem.c **** * ############################################################################ + 41:Core/Src/sysmem.c **** * ^-- RAM start ^-- _end _estack, RAM end --^ + 42:Core/Src/sysmem.c **** * @endverbatim + 43:Core/Src/sysmem.c **** * + 44:Core/Src/sysmem.c **** * This implementation starts allocating at the '_end' linker symbol + 45:Core/Src/sysmem.c **** * The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack + 46:Core/Src/sysmem.c **** * The implementation considers '_estack' linker symbol to be RAM end + 47:Core/Src/sysmem.c **** * NOTE: If the MSP stack, at any point during execution, grows larger than the + 48:Core/Src/sysmem.c **** * reserved size, please increase the '_Min_Stack_Size'. + 49:Core/Src/sysmem.c **** * + 50:Core/Src/sysmem.c **** * @param incr Memory size + 51:Core/Src/sysmem.c **** * @return Pointer to allocated memory + 52:Core/Src/sysmem.c **** */ + 53:Core/Src/sysmem.c **** void *_sbrk(ptrdiff_t incr) + 54:Core/Src/sysmem.c **** { + 35 .loc 1 54 1 + 36 .cfi_startproc + 37 @ args = 0, pretend = 0, frame = 24 + 38 @ frame_needed = 1, uses_anonymous_args = 0 + 39 0000 80B5 push {r7, lr} + 40 .cfi_def_cfa_offset 8 + 41 .cfi_offset 7, -8 + 42 .cfi_offset 14, -4 + 43 0002 86B0 sub sp, sp, #24 + 44 .cfi_def_cfa_offset 32 + 45 0004 00AF add r7, sp, #0 + 46 .cfi_def_cfa_register 7 + 47 0006 7860 str r0, [r7, #4] + 55:Core/Src/sysmem.c **** extern uint8_t _end; /* Symbol defined in the linker script */ + 56:Core/Src/sysmem.c **** extern uint8_t _estack; /* Symbol defined in the linker script */ + 57:Core/Src/sysmem.c **** extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ + 58:Core/Src/sysmem.c **** const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; + 48 .loc 1 58 32 + 49 0008 144A ldr r2, .L5 + 50 .loc 1 58 53 + 51 000a 154B ldr r3, .L5+4 + 52 .loc 1 58 18 + 53 000c D31A subs r3, r2, r3 + 54 000e 7B61 str r3, [r7, #20] + 59:Core/Src/sysmem.c **** const uint8_t *max_heap = (uint8_t *)stack_limit; + 55 .loc 1 59 18 + 56 0010 7B69 ldr r3, [r7, #20] + 57 0012 3B61 str r3, [r7, #16] + 60:Core/Src/sysmem.c **** uint8_t *prev_heap_end; + ARM GAS /tmp/ccQxFjE3.s page 3 + + + 61:Core/Src/sysmem.c **** + 62:Core/Src/sysmem.c **** /* Initialize heap end at first call */ + 63:Core/Src/sysmem.c **** if (NULL == __sbrk_heap_end) + 58 .loc 1 63 12 + 59 0014 134B ldr r3, .L5+8 + 60 0016 1B68 ldr r3, [r3] + 61 .loc 1 63 6 + 62 0018 002B cmp r3, #0 + 63 001a 02D1 bne .L2 + 64:Core/Src/sysmem.c **** { + 65:Core/Src/sysmem.c **** __sbrk_heap_end = &_end; + 64 .loc 1 65 21 + 65 001c 114B ldr r3, .L5+8 + 66 001e 124A ldr r2, .L5+12 + 67 0020 1A60 str r2, [r3] + 68 .L2: + 66:Core/Src/sysmem.c **** } + 67:Core/Src/sysmem.c **** + 68:Core/Src/sysmem.c **** /* Protect heap from growing into the reserved MSP stack */ + 69:Core/Src/sysmem.c **** if (__sbrk_heap_end + incr > max_heap) + 69 .loc 1 69 23 + 70 0022 104B ldr r3, .L5+8 + 71 0024 1A68 ldr r2, [r3] + 72 0026 7B68 ldr r3, [r7, #4] + 73 0028 1344 add r3, r3, r2 + 74 .loc 1 69 6 + 75 002a 3A69 ldr r2, [r7, #16] + 76 002c 9A42 cmp r2, r3 + 77 002e 07D2 bcs .L3 + 70:Core/Src/sysmem.c **** { + 71:Core/Src/sysmem.c **** errno = ENOMEM; + 78 .loc 1 71 5 + 79 0030 FFF7FEFF bl __errno + 80 0034 0346 mov r3, r0 + 81 .loc 1 71 11 discriminator 1 + 82 0036 0C22 movs r2, #12 + 83 0038 1A60 str r2, [r3] + 72:Core/Src/sysmem.c **** return (void *)-1; + 84 .loc 1 72 12 + 85 003a 4FF0FF33 mov r3, #-1 + 86 003e 09E0 b .L4 + 87 .L3: + 73:Core/Src/sysmem.c **** } + 74:Core/Src/sysmem.c **** + 75:Core/Src/sysmem.c **** prev_heap_end = __sbrk_heap_end; + 88 .loc 1 75 17 + 89 0040 084B ldr r3, .L5+8 + 90 0042 1B68 ldr r3, [r3] + 91 0044 FB60 str r3, [r7, #12] + 76:Core/Src/sysmem.c **** __sbrk_heap_end += incr; + 92 .loc 1 76 19 + 93 0046 074B ldr r3, .L5+8 + 94 0048 1A68 ldr r2, [r3] + 95 004a 7B68 ldr r3, [r7, #4] + 96 004c 1344 add r3, r3, r2 + 97 004e 054A ldr r2, .L5+8 + 98 0050 1360 str r3, [r2] + ARM GAS /tmp/ccQxFjE3.s page 4 + + + 77:Core/Src/sysmem.c **** + 78:Core/Src/sysmem.c **** return (void *)prev_heap_end; + 99 .loc 1 78 10 + 100 0052 FB68 ldr r3, [r7, #12] + 101 .L4: + 79:Core/Src/sysmem.c **** } + 102 .loc 1 79 1 + 103 0054 1846 mov r0, r3 + 104 0056 1837 adds r7, r7, #24 + 105 .cfi_def_cfa_offset 8 + 106 0058 BD46 mov sp, r7 + 107 .cfi_def_cfa_register 13 + 108 @ sp needed + 109 005a 80BD pop {r7, pc} + 110 .L6: + 111 .align 2 + 112 .L5: + 113 005c 00000000 .word _estack + 114 0060 00000000 .word _Min_Stack_Size + 115 0064 00000000 .word __sbrk_heap_end + 116 0068 00000000 .word _end + 117 .cfi_endproc + 118 .LFE0: + 120 .text + 121 .Letext0: + 122 .file 2 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/lib/gcc/arm-none-e + 123 .file 3 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 124 .file 4 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 125 .file 5 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + ARM GAS /tmp/ccQxFjE3.s page 5 + + +DEFINED SYMBOLS + *ABS*:00000000 sysmem.c + /tmp/ccQxFjE3.s:21 .bss.__sbrk_heap_end:00000000 $d + /tmp/ccQxFjE3.s:24 .bss.__sbrk_heap_end:00000000 __sbrk_heap_end + /tmp/ccQxFjE3.s:27 .text._sbrk:00000000 $t + /tmp/ccQxFjE3.s:33 .text._sbrk:00000000 _sbrk + /tmp/ccQxFjE3.s:113 .text._sbrk:0000005c $d + +UNDEFINED SYMBOLS +__errno +_estack +_Min_Stack_Size +_end diff --git a/Software/build/sysmem.o b/Software/build/sysmem.o new file mode 100644 index 0000000..3f11465 Binary files /dev/null and b/Software/build/sysmem.o differ diff --git a/Software/build/system_stm32f3xx.d b/Software/build/system_stm32f3xx.d new file mode 100644 index 0000000..bf00b7b --- /dev/null +++ b/Software/build/system_stm32f3xx.d @@ -0,0 +1,61 @@ +build/system_stm32f3xx.o: Core/Src/system_stm32f3xx.c \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h \ + Drivers/CMSIS/Include/core_cm4.h Drivers/CMSIS/Include/cmsis_version.h \ + Drivers/CMSIS/Include/cmsis_compiler.h Drivers/CMSIS/Include/cmsis_gcc.h \ + Drivers/CMSIS/Include/mpu_armv7.h \ + Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h \ + Core/Inc/stm32f3xx_hal_conf.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h \ + Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h: +Drivers/CMSIS/Include/core_cm4.h: +Drivers/CMSIS/Include/cmsis_version.h: +Drivers/CMSIS/Include/cmsis_compiler.h: +Drivers/CMSIS/Include/cmsis_gcc.h: +Drivers/CMSIS/Include/mpu_armv7.h: +Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h: +Core/Inc/stm32f3xx_hal_conf.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h: +Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cortex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_can.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi_ex.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim.h: +Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_tim_ex.h: diff --git a/Software/build/system_stm32f3xx.lst b/Software/build/system_stm32f3xx.lst new file mode 100644 index 0000000..cd301ab --- /dev/null +++ b/Software/build/system_stm32f3xx.lst @@ -0,0 +1,583 @@ +ARM GAS /tmp/cc0EV5A6.s page 1 + + + 1 .cpu cortex-m4 + 2 .arch armv7e-m + 3 .fpu fpv4-sp-d16 + 4 .eabi_attribute 27, 1 + 5 .eabi_attribute 28, 1 + 6 .eabi_attribute 20, 1 + 7 .eabi_attribute 21, 1 + 8 .eabi_attribute 23, 3 + 9 .eabi_attribute 24, 1 + 10 .eabi_attribute 25, 1 + 11 .eabi_attribute 26, 1 + 12 .eabi_attribute 30, 6 + 13 .eabi_attribute 34, 1 + 14 .eabi_attribute 18, 4 + 15 .file "system_stm32f3xx.c" + 16 .text + 17 .Ltext0: + 18 .cfi_sections .debug_frame + 19 .file 1 "Core/Src/system_stm32f3xx.c" + 20 .global SystemCoreClock + 21 .section .data.SystemCoreClock,"aw" + 22 .align 2 + 25 SystemCoreClock: + 26 0000 00127A00 .word 8000000 + 27 .global AHBPrescTable + 28 .section .rodata.AHBPrescTable,"a" + 29 .align 2 + 32 AHBPrescTable: + 33 0000 00000000 .ascii "\000\000\000\000\000\000\000\000\001\002\003\004\006" + 33 00000000 + 33 01020304 + 33 06 + 34 000d 070809 .ascii "\007\010\011" + 35 .global APBPrescTable + 36 .section .rodata.APBPrescTable,"a" + 37 .align 2 + 40 APBPrescTable: + 41 0000 00000000 .ascii "\000\000\000\000\001\002\003\004" + 41 01020304 + 42 .section .text.SystemInit,"ax",%progbits + 43 .align 1 + 44 .global SystemInit + 45 .syntax unified + 46 .thumb + 47 .thumb_func + 49 SystemInit: + 50 .LFB130: + 1:Core/Src/system_stm32f3xx.c **** /** + 2:Core/Src/system_stm32f3xx.c **** ****************************************************************************** + 3:Core/Src/system_stm32f3xx.c **** * @file system_stm32f3xx.c + 4:Core/Src/system_stm32f3xx.c **** * @author MCD Application Team + 5:Core/Src/system_stm32f3xx.c **** * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. + 6:Core/Src/system_stm32f3xx.c **** * + 7:Core/Src/system_stm32f3xx.c **** * 1. This file provides two functions and one global variable to be called from + 8:Core/Src/system_stm32f3xx.c **** * user application: + 9:Core/Src/system_stm32f3xx.c **** * - SystemInit(): This function is called at startup just after reset and + 10:Core/Src/system_stm32f3xx.c **** * before branch to main program. This call is made inside + ARM GAS /tmp/cc0EV5A6.s page 2 + + + 11:Core/Src/system_stm32f3xx.c **** * the "startup_stm32f3xx.s" file. + 12:Core/Src/system_stm32f3xx.c **** * + 13:Core/Src/system_stm32f3xx.c **** * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + 14:Core/Src/system_stm32f3xx.c **** * by the user application to setup the SysTick + 15:Core/Src/system_stm32f3xx.c **** * timer or configure other parameters. + 16:Core/Src/system_stm32f3xx.c **** * + 17:Core/Src/system_stm32f3xx.c **** * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + 18:Core/Src/system_stm32f3xx.c **** * be called whenever the core clock is changed + 19:Core/Src/system_stm32f3xx.c **** * during program execution. + 20:Core/Src/system_stm32f3xx.c **** * + 21:Core/Src/system_stm32f3xx.c **** * 2. After each device reset the HSI (8 MHz) is used as system clock source. + 22:Core/Src/system_stm32f3xx.c **** * Then SystemInit() function is called, in "startup_stm32f3xx.s" file, to + 23:Core/Src/system_stm32f3xx.c **** * configure the system clock before to branch to main program. + 24:Core/Src/system_stm32f3xx.c **** * + 25:Core/Src/system_stm32f3xx.c **** * 3. This file configures the system clock as follows: + 26:Core/Src/system_stm32f3xx.c **** *============================================================================= + 27:Core/Src/system_stm32f3xx.c **** * Supported STM32F3xx device + 28:Core/Src/system_stm32f3xx.c **** *----------------------------------------------------------------------------- + 29:Core/Src/system_stm32f3xx.c **** * System Clock source | HSI + 30:Core/Src/system_stm32f3xx.c **** *----------------------------------------------------------------------------- + 31:Core/Src/system_stm32f3xx.c **** * SYSCLK(Hz) | 8000000 + 32:Core/Src/system_stm32f3xx.c **** *----------------------------------------------------------------------------- + 33:Core/Src/system_stm32f3xx.c **** * HCLK(Hz) | 8000000 + 34:Core/Src/system_stm32f3xx.c **** *----------------------------------------------------------------------------- + 35:Core/Src/system_stm32f3xx.c **** * AHB Prescaler | 1 + 36:Core/Src/system_stm32f3xx.c **** *----------------------------------------------------------------------------- + 37:Core/Src/system_stm32f3xx.c **** * APB2 Prescaler | 1 + 38:Core/Src/system_stm32f3xx.c **** *----------------------------------------------------------------------------- + 39:Core/Src/system_stm32f3xx.c **** * APB1 Prescaler | 1 + 40:Core/Src/system_stm32f3xx.c **** *----------------------------------------------------------------------------- + 41:Core/Src/system_stm32f3xx.c **** * USB Clock | DISABLE + 42:Core/Src/system_stm32f3xx.c **** *----------------------------------------------------------------------------- + 43:Core/Src/system_stm32f3xx.c **** *============================================================================= + 44:Core/Src/system_stm32f3xx.c **** ****************************************************************************** + 45:Core/Src/system_stm32f3xx.c **** * @attention + 46:Core/Src/system_stm32f3xx.c **** * + 47:Core/Src/system_stm32f3xx.c **** * Copyright (c) 2016 STMicroelectronics. + 48:Core/Src/system_stm32f3xx.c **** * All rights reserved. + 49:Core/Src/system_stm32f3xx.c **** * + 50:Core/Src/system_stm32f3xx.c **** * This software is licensed under terms that can be found in the LICENSE file + 51:Core/Src/system_stm32f3xx.c **** * in the root directory of this software component. + 52:Core/Src/system_stm32f3xx.c **** * If no LICENSE file comes with this software, it is provided AS-IS. + 53:Core/Src/system_stm32f3xx.c **** * + 54:Core/Src/system_stm32f3xx.c **** ****************************************************************************** + 55:Core/Src/system_stm32f3xx.c **** */ + 56:Core/Src/system_stm32f3xx.c **** + 57:Core/Src/system_stm32f3xx.c **** /** @addtogroup CMSIS + 58:Core/Src/system_stm32f3xx.c **** * @{ + 59:Core/Src/system_stm32f3xx.c **** */ + 60:Core/Src/system_stm32f3xx.c **** + 61:Core/Src/system_stm32f3xx.c **** /** @addtogroup stm32f3xx_system + 62:Core/Src/system_stm32f3xx.c **** * @{ + 63:Core/Src/system_stm32f3xx.c **** */ + 64:Core/Src/system_stm32f3xx.c **** + 65:Core/Src/system_stm32f3xx.c **** /** @addtogroup STM32F3xx_System_Private_Includes + 66:Core/Src/system_stm32f3xx.c **** * @{ + 67:Core/Src/system_stm32f3xx.c **** */ + ARM GAS /tmp/cc0EV5A6.s page 3 + + + 68:Core/Src/system_stm32f3xx.c **** + 69:Core/Src/system_stm32f3xx.c **** #include "stm32f3xx.h" + 70:Core/Src/system_stm32f3xx.c **** + 71:Core/Src/system_stm32f3xx.c **** /** + 72:Core/Src/system_stm32f3xx.c **** * @} + 73:Core/Src/system_stm32f3xx.c **** */ + 74:Core/Src/system_stm32f3xx.c **** + 75:Core/Src/system_stm32f3xx.c **** /** @addtogroup STM32F3xx_System_Private_TypesDefinitions + 76:Core/Src/system_stm32f3xx.c **** * @{ + 77:Core/Src/system_stm32f3xx.c **** */ + 78:Core/Src/system_stm32f3xx.c **** + 79:Core/Src/system_stm32f3xx.c **** /** + 80:Core/Src/system_stm32f3xx.c **** * @} + 81:Core/Src/system_stm32f3xx.c **** */ + 82:Core/Src/system_stm32f3xx.c **** + 83:Core/Src/system_stm32f3xx.c **** /** @addtogroup STM32F3xx_System_Private_Defines + 84:Core/Src/system_stm32f3xx.c **** * @{ + 85:Core/Src/system_stm32f3xx.c **** */ + 86:Core/Src/system_stm32f3xx.c **** #if !defined (HSE_VALUE) + 87:Core/Src/system_stm32f3xx.c **** #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz. + 88:Core/Src/system_stm32f3xx.c **** This value can be provided and adapted by the user + 89:Core/Src/system_stm32f3xx.c **** #endif /* HSE_VALUE */ + 90:Core/Src/system_stm32f3xx.c **** + 91:Core/Src/system_stm32f3xx.c **** #if !defined (HSI_VALUE) + 92:Core/Src/system_stm32f3xx.c **** #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz. + 93:Core/Src/system_stm32f3xx.c **** This value can be provided and adapted by the user + 94:Core/Src/system_stm32f3xx.c **** #endif /* HSI_VALUE */ + 95:Core/Src/system_stm32f3xx.c **** + 96:Core/Src/system_stm32f3xx.c **** /* Note: Following vector table addresses must be defined in line with linker + 97:Core/Src/system_stm32f3xx.c **** configuration. */ + 98:Core/Src/system_stm32f3xx.c **** /*!< Uncomment the following line if you need to relocate the vector table + 99:Core/Src/system_stm32f3xx.c **** anywhere in Flash or Sram, else the vector table is kept at the automatic + 100:Core/Src/system_stm32f3xx.c **** remap of boot address selected */ + 101:Core/Src/system_stm32f3xx.c **** /* #define USER_VECT_TAB_ADDRESS */ + 102:Core/Src/system_stm32f3xx.c **** + 103:Core/Src/system_stm32f3xx.c **** #if defined(USER_VECT_TAB_ADDRESS) + 104:Core/Src/system_stm32f3xx.c **** /*!< Uncomment the following line if you need to relocate your vector Table + 105:Core/Src/system_stm32f3xx.c **** in Sram else user remap will be done in Flash. */ + 106:Core/Src/system_stm32f3xx.c **** /* #define VECT_TAB_SRAM */ + 107:Core/Src/system_stm32f3xx.c **** #if defined(VECT_TAB_SRAM) + 108:Core/Src/system_stm32f3xx.c **** #define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field. + 109:Core/Src/system_stm32f3xx.c **** This value must be a multiple of 0x200. */ + 110:Core/Src/system_stm32f3xx.c **** #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + 111:Core/Src/system_stm32f3xx.c **** This value must be a multiple of 0x200. */ + 112:Core/Src/system_stm32f3xx.c **** #else + 113:Core/Src/system_stm32f3xx.c **** #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. + 114:Core/Src/system_stm32f3xx.c **** This value must be a multiple of 0x200. */ + 115:Core/Src/system_stm32f3xx.c **** #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + 116:Core/Src/system_stm32f3xx.c **** This value must be a multiple of 0x200. */ + 117:Core/Src/system_stm32f3xx.c **** #endif /* VECT_TAB_SRAM */ + 118:Core/Src/system_stm32f3xx.c **** #endif /* USER_VECT_TAB_ADDRESS */ + 119:Core/Src/system_stm32f3xx.c **** + 120:Core/Src/system_stm32f3xx.c **** /******************************************************************************/ + 121:Core/Src/system_stm32f3xx.c **** /** + 122:Core/Src/system_stm32f3xx.c **** * @} + 123:Core/Src/system_stm32f3xx.c **** */ + 124:Core/Src/system_stm32f3xx.c **** + ARM GAS /tmp/cc0EV5A6.s page 4 + + + 125:Core/Src/system_stm32f3xx.c **** /** @addtogroup STM32F3xx_System_Private_Macros + 126:Core/Src/system_stm32f3xx.c **** * @{ + 127:Core/Src/system_stm32f3xx.c **** */ + 128:Core/Src/system_stm32f3xx.c **** + 129:Core/Src/system_stm32f3xx.c **** /** + 130:Core/Src/system_stm32f3xx.c **** * @} + 131:Core/Src/system_stm32f3xx.c **** */ + 132:Core/Src/system_stm32f3xx.c **** + 133:Core/Src/system_stm32f3xx.c **** /** @addtogroup STM32F3xx_System_Private_Variables + 134:Core/Src/system_stm32f3xx.c **** * @{ + 135:Core/Src/system_stm32f3xx.c **** */ + 136:Core/Src/system_stm32f3xx.c **** /* This variable is updated in three ways: + 137:Core/Src/system_stm32f3xx.c **** 1) by calling CMSIS function SystemCoreClockUpdate() + 138:Core/Src/system_stm32f3xx.c **** 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 139:Core/Src/system_stm32f3xx.c **** 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + 140:Core/Src/system_stm32f3xx.c **** Note: If you use this function to configure the system clock there is no need to + 141:Core/Src/system_stm32f3xx.c **** call the 2 first functions listed above, since SystemCoreClock variable is + 142:Core/Src/system_stm32f3xx.c **** updated automatically. + 143:Core/Src/system_stm32f3xx.c **** */ + 144:Core/Src/system_stm32f3xx.c **** uint32_t SystemCoreClock = 8000000; + 145:Core/Src/system_stm32f3xx.c **** + 146:Core/Src/system_stm32f3xx.c **** const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + 147:Core/Src/system_stm32f3xx.c **** const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + 148:Core/Src/system_stm32f3xx.c **** + 149:Core/Src/system_stm32f3xx.c **** /** + 150:Core/Src/system_stm32f3xx.c **** * @} + 151:Core/Src/system_stm32f3xx.c **** */ + 152:Core/Src/system_stm32f3xx.c **** + 153:Core/Src/system_stm32f3xx.c **** /** @addtogroup STM32F3xx_System_Private_FunctionPrototypes + 154:Core/Src/system_stm32f3xx.c **** * @{ + 155:Core/Src/system_stm32f3xx.c **** */ + 156:Core/Src/system_stm32f3xx.c **** + 157:Core/Src/system_stm32f3xx.c **** /** + 158:Core/Src/system_stm32f3xx.c **** * @} + 159:Core/Src/system_stm32f3xx.c **** */ + 160:Core/Src/system_stm32f3xx.c **** + 161:Core/Src/system_stm32f3xx.c **** /** @addtogroup STM32F3xx_System_Private_Functions + 162:Core/Src/system_stm32f3xx.c **** * @{ + 163:Core/Src/system_stm32f3xx.c **** */ + 164:Core/Src/system_stm32f3xx.c **** + 165:Core/Src/system_stm32f3xx.c **** /** + 166:Core/Src/system_stm32f3xx.c **** * @brief Setup the microcontroller system + 167:Core/Src/system_stm32f3xx.c **** * @param None + 168:Core/Src/system_stm32f3xx.c **** * @retval None + 169:Core/Src/system_stm32f3xx.c **** */ + 170:Core/Src/system_stm32f3xx.c **** void SystemInit(void) + 171:Core/Src/system_stm32f3xx.c **** { + 51 .loc 1 171 1 + 52 .cfi_startproc + 53 @ args = 0, pretend = 0, frame = 0 + 54 @ frame_needed = 1, uses_anonymous_args = 0 + 55 @ link register save eliminated. + 56 0000 80B4 push {r7} + 57 .cfi_def_cfa_offset 4 + 58 .cfi_offset 7, -4 + 59 0002 00AF add r7, sp, #0 + 60 .cfi_def_cfa_register 7 + ARM GAS /tmp/cc0EV5A6.s page 5 + + + 172:Core/Src/system_stm32f3xx.c **** /* FPU settings --------------------------------------------------------------*/ + 173:Core/Src/system_stm32f3xx.c **** #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + 174:Core/Src/system_stm32f3xx.c **** SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + 61 .loc 1 174 6 + 62 0004 064B ldr r3, .L2 + 63 0006 D3F88830 ldr r3, [r3, #136] + 64 000a 054A ldr r2, .L2 + 65 .loc 1 174 14 + 66 000c 43F47003 orr r3, r3, #15728640 + 67 0010 C2F88830 str r3, [r2, #136] + 175:Core/Src/system_stm32f3xx.c **** #endif + 176:Core/Src/system_stm32f3xx.c **** + 177:Core/Src/system_stm32f3xx.c **** /* Configure the Vector Table location -------------------------------------*/ + 178:Core/Src/system_stm32f3xx.c **** #if defined(USER_VECT_TAB_ADDRESS) + 179:Core/Src/system_stm32f3xx.c **** SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM + 180:Core/Src/system_stm32f3xx.c **** #endif /* USER_VECT_TAB_ADDRESS */ + 181:Core/Src/system_stm32f3xx.c **** } + 68 .loc 1 181 1 + 69 0014 00BF nop + 70 0016 BD46 mov sp, r7 + 71 .cfi_def_cfa_register 13 + 72 @ sp needed + 73 0018 5DF8047B ldr r7, [sp], #4 + 74 .cfi_restore 7 + 75 .cfi_def_cfa_offset 0 + 76 001c 7047 bx lr + 77 .L3: + 78 001e 00BF .align 2 + 79 .L2: + 80 0020 00ED00E0 .word -536810240 + 81 .cfi_endproc + 82 .LFE130: + 84 .section .text.SystemCoreClockUpdate,"ax",%progbits + 85 .align 1 + 86 .global SystemCoreClockUpdate + 87 .syntax unified + 88 .thumb + 89 .thumb_func + 91 SystemCoreClockUpdate: + 92 .LFB131: + 182:Core/Src/system_stm32f3xx.c **** + 183:Core/Src/system_stm32f3xx.c **** /** + 184:Core/Src/system_stm32f3xx.c **** * @brief Update SystemCoreClock variable according to Clock Register Values. + 185:Core/Src/system_stm32f3xx.c **** * The SystemCoreClock variable contains the core clock (HCLK), it can + 186:Core/Src/system_stm32f3xx.c **** * be used by the user application to setup the SysTick timer or configure + 187:Core/Src/system_stm32f3xx.c **** * other parameters. + 188:Core/Src/system_stm32f3xx.c **** * + 189:Core/Src/system_stm32f3xx.c **** * @note Each time the core clock (HCLK) changes, this function must be called + 190:Core/Src/system_stm32f3xx.c **** * to update SystemCoreClock variable value. Otherwise, any configuration + 191:Core/Src/system_stm32f3xx.c **** * based on this variable will be incorrect. + 192:Core/Src/system_stm32f3xx.c **** * + 193:Core/Src/system_stm32f3xx.c **** * @note - The system frequency computed by this function is not the real + 194:Core/Src/system_stm32f3xx.c **** * frequency in the chip. It is calculated based on the predefined + 195:Core/Src/system_stm32f3xx.c **** * constant and the selected clock source: + 196:Core/Src/system_stm32f3xx.c **** * + 197:Core/Src/system_stm32f3xx.c **** * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + 198:Core/Src/system_stm32f3xx.c **** * + ARM GAS /tmp/cc0EV5A6.s page 6 + + + 199:Core/Src/system_stm32f3xx.c **** * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + 200:Core/Src/system_stm32f3xx.c **** * + 201:Core/Src/system_stm32f3xx.c **** * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + 202:Core/Src/system_stm32f3xx.c **** * or HSI_VALUE(*) multiplied/divided by the PLL factors. + 203:Core/Src/system_stm32f3xx.c **** * + 204:Core/Src/system_stm32f3xx.c **** * (*) HSI_VALUE is a constant defined in stm32f3xx_hal.h file (default value + 205:Core/Src/system_stm32f3xx.c **** * 8 MHz) but the real value may vary depending on the variations + 206:Core/Src/system_stm32f3xx.c **** * in voltage and temperature. + 207:Core/Src/system_stm32f3xx.c **** * + 208:Core/Src/system_stm32f3xx.c **** * (**) HSE_VALUE is a constant defined in stm32f3xx_hal.h file (default value + 209:Core/Src/system_stm32f3xx.c **** * 8 MHz), user has to ensure that HSE_VALUE is same as the real + 210:Core/Src/system_stm32f3xx.c **** * frequency of the crystal used. Otherwise, this function may + 211:Core/Src/system_stm32f3xx.c **** * have wrong result. + 212:Core/Src/system_stm32f3xx.c **** * + 213:Core/Src/system_stm32f3xx.c **** * - The result of this function could be not correct when using fractional + 214:Core/Src/system_stm32f3xx.c **** * value for HSE crystal. + 215:Core/Src/system_stm32f3xx.c **** * + 216:Core/Src/system_stm32f3xx.c **** * @param None + 217:Core/Src/system_stm32f3xx.c **** * @retval None + 218:Core/Src/system_stm32f3xx.c **** */ + 219:Core/Src/system_stm32f3xx.c **** void SystemCoreClockUpdate (void) + 220:Core/Src/system_stm32f3xx.c **** { + 93 .loc 1 220 1 + 94 .cfi_startproc + 95 @ args = 0, pretend = 0, frame = 16 + 96 @ frame_needed = 1, uses_anonymous_args = 0 + 97 @ link register save eliminated. + 98 0000 80B4 push {r7} + 99 .cfi_def_cfa_offset 4 + 100 .cfi_offset 7, -4 + 101 0002 85B0 sub sp, sp, #20 + 102 .cfi_def_cfa_offset 24 + 103 0004 00AF add r7, sp, #0 + 104 .cfi_def_cfa_register 7 + 221:Core/Src/system_stm32f3xx.c **** uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0; + 105 .loc 1 221 12 + 106 0006 0023 movs r3, #0 + 107 0008 FB60 str r3, [r7, #12] + 108 .loc 1 221 21 + 109 000a 0023 movs r3, #0 + 110 000c BB60 str r3, [r7, #8] + 111 .loc 1 221 34 + 112 000e 0023 movs r3, #0 + 113 0010 7B60 str r3, [r7, #4] + 114 .loc 1 221 49 + 115 0012 0023 movs r3, #0 + 116 0014 3B60 str r3, [r7] + 222:Core/Src/system_stm32f3xx.c **** + 223:Core/Src/system_stm32f3xx.c **** /* Get SYSCLK source -------------------------------------------------------*/ + 224:Core/Src/system_stm32f3xx.c **** tmp = RCC->CFGR & RCC_CFGR_SWS; + 117 .loc 1 224 12 + 118 0016 2D4B ldr r3, .L12 + 119 0018 5B68 ldr r3, [r3, #4] + 120 .loc 1 224 7 + 121 001a 03F00C03 and r3, r3, #12 + 122 001e FB60 str r3, [r7, #12] + 225:Core/Src/system_stm32f3xx.c **** + ARM GAS /tmp/cc0EV5A6.s page 7 + + + 226:Core/Src/system_stm32f3xx.c **** switch (tmp) + 123 .loc 1 226 3 + 124 0020 FB68 ldr r3, [r7, #12] + 125 0022 082B cmp r3, #8 + 126 0024 11D0 beq .L5 + 127 0026 FB68 ldr r3, [r7, #12] + 128 0028 082B cmp r3, #8 + 129 002a 36D8 bhi .L6 + 130 002c FB68 ldr r3, [r7, #12] + 131 002e 002B cmp r3, #0 + 132 0030 03D0 beq .L7 + 133 0032 FB68 ldr r3, [r7, #12] + 134 0034 042B cmp r3, #4 + 135 0036 04D0 beq .L8 + 136 0038 2FE0 b .L6 + 137 .L7: + 227:Core/Src/system_stm32f3xx.c **** { + 228:Core/Src/system_stm32f3xx.c **** case RCC_CFGR_SWS_HSI: /* HSI used as system clock */ + 229:Core/Src/system_stm32f3xx.c **** SystemCoreClock = HSI_VALUE; + 138 .loc 1 229 23 + 139 003a 254B ldr r3, .L12+4 + 140 003c 254A ldr r2, .L12+8 + 141 003e 1A60 str r2, [r3] + 230:Core/Src/system_stm32f3xx.c **** break; + 142 .loc 1 230 7 + 143 0040 2FE0 b .L9 + 144 .L8: + 231:Core/Src/system_stm32f3xx.c **** case RCC_CFGR_SWS_HSE: /* HSE used as system clock */ + 232:Core/Src/system_stm32f3xx.c **** SystemCoreClock = HSE_VALUE; + 145 .loc 1 232 23 + 146 0042 234B ldr r3, .L12+4 + 147 0044 244A ldr r2, .L12+12 + 148 0046 1A60 str r2, [r3] + 233:Core/Src/system_stm32f3xx.c **** break; + 149 .loc 1 233 7 + 150 0048 2BE0 b .L9 + 151 .L5: + 234:Core/Src/system_stm32f3xx.c **** case RCC_CFGR_SWS_PLL: /* PLL used as system clock */ + 235:Core/Src/system_stm32f3xx.c **** /* Get PLL clock source and multiplication factor ----------------------*/ + 236:Core/Src/system_stm32f3xx.c **** pllmull = RCC->CFGR & RCC_CFGR_PLLMUL; + 152 .loc 1 236 20 + 153 004a 204B ldr r3, .L12 + 154 004c 5B68 ldr r3, [r3, #4] + 155 .loc 1 236 15 + 156 004e 03F47013 and r3, r3, #3932160 + 157 0052 BB60 str r3, [r7, #8] + 237:Core/Src/system_stm32f3xx.c **** pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + 158 .loc 1 237 22 + 159 0054 1D4B ldr r3, .L12 + 160 0056 5B68 ldr r3, [r3, #4] + 161 .loc 1 237 17 + 162 0058 03F48033 and r3, r3, #65536 + 163 005c 7B60 str r3, [r7, #4] + 238:Core/Src/system_stm32f3xx.c **** pllmull = ( pllmull >> 18) + 2; + 164 .loc 1 238 27 + 165 005e BB68 ldr r3, [r7, #8] + 166 0060 9B0C lsrs r3, r3, #18 + ARM GAS /tmp/cc0EV5A6.s page 8 + + + 167 .loc 1 238 15 + 168 0062 0233 adds r3, r3, #2 + 169 0064 BB60 str r3, [r7, #8] + 239:Core/Src/system_stm32f3xx.c **** + 240:Core/Src/system_stm32f3xx.c **** #if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx) + 241:Core/Src/system_stm32f3xx.c **** predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1; + 242:Core/Src/system_stm32f3xx.c **** if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV) + 243:Core/Src/system_stm32f3xx.c **** { + 244:Core/Src/system_stm32f3xx.c **** /* HSE oscillator clock selected as PREDIV1 clock entry */ + 245:Core/Src/system_stm32f3xx.c **** SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull; + 246:Core/Src/system_stm32f3xx.c **** } + 247:Core/Src/system_stm32f3xx.c **** else + 248:Core/Src/system_stm32f3xx.c **** { + 249:Core/Src/system_stm32f3xx.c **** /* HSI oscillator clock selected as PREDIV1 clock entry */ + 250:Core/Src/system_stm32f3xx.c **** SystemCoreClock = (HSI_VALUE / predivfactor) * pllmull; + 251:Core/Src/system_stm32f3xx.c **** } + 252:Core/Src/system_stm32f3xx.c **** #else + 253:Core/Src/system_stm32f3xx.c **** if (pllsource == RCC_CFGR_PLLSRC_HSI_DIV2) + 170 .loc 1 253 10 + 171 0066 7B68 ldr r3, [r7, #4] + 172 0068 002B cmp r3, #0 + 173 006a 06D1 bne .L10 + 254:Core/Src/system_stm32f3xx.c **** { + 255:Core/Src/system_stm32f3xx.c **** /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + 256:Core/Src/system_stm32f3xx.c **** SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + 174 .loc 1 256 44 + 175 006c BB68 ldr r3, [r7, #8] + 176 006e 1B4A ldr r2, .L12+16 + 177 0070 02FB03F3 mul r3, r2, r3 + 178 .loc 1 256 25 + 179 0074 164A ldr r2, .L12+4 + 180 0076 1360 str r3, [r2] + 257:Core/Src/system_stm32f3xx.c **** } + 258:Core/Src/system_stm32f3xx.c **** else + 259:Core/Src/system_stm32f3xx.c **** { + 260:Core/Src/system_stm32f3xx.c **** predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1; + 261:Core/Src/system_stm32f3xx.c **** /* HSE oscillator clock selected as PREDIV1 clock entry */ + 262:Core/Src/system_stm32f3xx.c **** SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull; + 263:Core/Src/system_stm32f3xx.c **** } + 264:Core/Src/system_stm32f3xx.c **** #endif /* STM32F302xE || STM32F303xE || STM32F398xx */ + 265:Core/Src/system_stm32f3xx.c **** break; + 181 .loc 1 265 7 + 182 0078 13E0 b .L9 + 183 .L10: + 260:Core/Src/system_stm32f3xx.c **** /* HSE oscillator clock selected as PREDIV1 clock entry */ + 184 .loc 1 260 28 + 185 007a 144B ldr r3, .L12 + 186 007c DB6A ldr r3, [r3, #44] + 260:Core/Src/system_stm32f3xx.c **** /* HSE oscillator clock selected as PREDIV1 clock entry */ + 187 .loc 1 260 36 + 188 007e 03F00F03 and r3, r3, #15 + 260:Core/Src/system_stm32f3xx.c **** /* HSE oscillator clock selected as PREDIV1 clock entry */ + 189 .loc 1 260 22 + 190 0082 0133 adds r3, r3, #1 + 191 0084 3B60 str r3, [r7] + 262:Core/Src/system_stm32f3xx.c **** } + 192 .loc 1 262 38 + ARM GAS /tmp/cc0EV5A6.s page 9 + + + 193 0086 144A ldr r2, .L12+12 + 194 0088 3B68 ldr r3, [r7] + 195 008a B2FBF3F3 udiv r3, r2, r3 + 262:Core/Src/system_stm32f3xx.c **** } + 196 .loc 1 262 54 + 197 008e BA68 ldr r2, [r7, #8] + 198 0090 02FB03F3 mul r3, r2, r3 + 262:Core/Src/system_stm32f3xx.c **** } + 199 .loc 1 262 25 + 200 0094 0E4A ldr r2, .L12+4 + 201 0096 1360 str r3, [r2] + 202 .loc 1 265 7 + 203 0098 03E0 b .L9 + 204 .L6: + 266:Core/Src/system_stm32f3xx.c **** default: /* HSI used as system clock */ + 267:Core/Src/system_stm32f3xx.c **** SystemCoreClock = HSI_VALUE; + 205 .loc 1 267 23 + 206 009a 0D4B ldr r3, .L12+4 + 207 009c 0D4A ldr r2, .L12+8 + 208 009e 1A60 str r2, [r3] + 268:Core/Src/system_stm32f3xx.c **** break; + 209 .loc 1 268 7 + 210 00a0 00BF nop + 211 .L9: + 269:Core/Src/system_stm32f3xx.c **** } + 270:Core/Src/system_stm32f3xx.c **** /* Compute HCLK clock frequency ----------------*/ + 271:Core/Src/system_stm32f3xx.c **** /* Get HCLK prescaler */ + 272:Core/Src/system_stm32f3xx.c **** tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + 212 .loc 1 272 28 + 213 00a2 0A4B ldr r3, .L12 + 214 00a4 5B68 ldr r3, [r3, #4] + 215 .loc 1 272 52 + 216 00a6 1B09 lsrs r3, r3, #4 + 217 00a8 03F00F03 and r3, r3, #15 + 218 .loc 1 272 22 + 219 00ac 0C4A ldr r2, .L12+20 + 220 00ae D35C ldrb r3, [r2, r3] @ zero_extendqisi2 + 221 .loc 1 272 7 + 222 00b0 FB60 str r3, [r7, #12] + 273:Core/Src/system_stm32f3xx.c **** /* HCLK clock frequency */ + 274:Core/Src/system_stm32f3xx.c **** SystemCoreClock >>= tmp; + 223 .loc 1 274 19 + 224 00b2 074B ldr r3, .L12+4 + 225 00b4 1A68 ldr r2, [r3] + 226 00b6 FB68 ldr r3, [r7, #12] + 227 00b8 22FA03F3 lsr r3, r2, r3 + 228 00bc 044A ldr r2, .L12+4 + 229 00be 1360 str r3, [r2] + 275:Core/Src/system_stm32f3xx.c **** } + 230 .loc 1 275 1 + 231 00c0 00BF nop + 232 00c2 1437 adds r7, r7, #20 + 233 .cfi_def_cfa_offset 4 + 234 00c4 BD46 mov sp, r7 + 235 .cfi_def_cfa_register 13 + 236 @ sp needed + 237 00c6 5DF8047B ldr r7, [sp], #4 + ARM GAS /tmp/cc0EV5A6.s page 10 + + + 238 .cfi_restore 7 + 239 .cfi_def_cfa_offset 0 + 240 00ca 7047 bx lr + 241 .L13: + 242 .align 2 + 243 .L12: + 244 00cc 00100240 .word 1073876992 + 245 00d0 00000000 .word SystemCoreClock + 246 00d4 00127A00 .word 8000000 + 247 00d8 0024F400 .word 16000000 + 248 00dc 00093D00 .word 4000000 + 249 00e0 00000000 .word AHBPrescTable + 250 .cfi_endproc + 251 .LFE131: + 253 .text + 254 .Letext0: + 255 .file 2 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 256 .file 3 "/nix/store/p8vkamc9b2vlibs9aw76vnasdbifhcbm-gcc-arm-embedded-13.2.rel1/arm-none-eabi/incl + 257 .file 4 "Drivers/CMSIS/Include/core_cm4.h" + 258 .file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h" + 259 .file 6 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h" + ARM GAS /tmp/cc0EV5A6.s page 11 + + +DEFINED SYMBOLS + *ABS*:00000000 system_stm32f3xx.c + /tmp/cc0EV5A6.s:25 .data.SystemCoreClock:00000000 SystemCoreClock + /tmp/cc0EV5A6.s:22 .data.SystemCoreClock:00000000 $d + /tmp/cc0EV5A6.s:32 .rodata.AHBPrescTable:00000000 AHBPrescTable + /tmp/cc0EV5A6.s:29 .rodata.AHBPrescTable:00000000 $d + /tmp/cc0EV5A6.s:40 .rodata.APBPrescTable:00000000 APBPrescTable + /tmp/cc0EV5A6.s:37 .rodata.APBPrescTable:00000000 $d + /tmp/cc0EV5A6.s:43 .text.SystemInit:00000000 $t + /tmp/cc0EV5A6.s:49 .text.SystemInit:00000000 SystemInit + /tmp/cc0EV5A6.s:80 .text.SystemInit:00000020 $d + /tmp/cc0EV5A6.s:85 .text.SystemCoreClockUpdate:00000000 $t + /tmp/cc0EV5A6.s:91 .text.SystemCoreClockUpdate:00000000 SystemCoreClockUpdate + /tmp/cc0EV5A6.s:244 .text.SystemCoreClockUpdate:000000cc $d + +NO UNDEFINED SYMBOLS diff --git a/Software/build/system_stm32f3xx.o b/Software/build/system_stm32f3xx.o new file mode 100644 index 0000000..ede37a6 Binary files /dev/null and b/Software/build/system_stm32f3xx.o differ diff --git a/Software/compile_commands.json b/Software/compile_commands.json new file mode 100644 index 0000000..9cb5113 --- /dev/null +++ b/Software/compile_commands.json @@ -0,0 +1,32 @@ +[ + { + "arguments": [ + "/run/current-system/sw/bin/arm-none-eabi-gcc", + "-c", + "-mcpu=cortex-m4", + "-mthumb", + "-mfpu=fpv4-sp-d16", + "-mfloat-abi=hard", + "-DUSE_HAL_DRIVER", + "-DSTM32F302xC", + "-ICore/Inc", + "-IDrivers/STM32F3xx_HAL_Driver/Inc", + "-IDrivers/STM32F3xx_HAL_Driver/Inc/Legacy", + "-IDrivers/CMSIS/Device/ST/STM32F3xx/Include", + "-IDrivers/CMSIS/Include", + "-Og", + "-Wall", + "-fdata-sections", + "-ffunction-sections", + "-g", + "-gdwarf-2", + "-Wa,-a,-ad,-alms=build/main.lst", + "-o", + "build/main.o", + "Core/Src/main.c" + ], + "directory": "/home/h/FASTTUBE/git/mv-bms", + "file": "/home/h/FASTTUBE/git/mv-bms/Core/Src/main.c", + "output": "/home/h/FASTTUBE/git/mv-bms/build/main.o" + } +] diff --git a/mvbms-test-24.ioc b/Software/mvbms-test-24.ioc similarity index 100% rename from mvbms-test-24.ioc rename to Software/mvbms-test-24.ioc diff --git a/mvbms.ioc b/Software/mvbms.ioc similarity index 100% rename from mvbms.ioc rename to Software/mvbms.ioc diff --git a/Software/openocd.cfg b/Software/openocd.cfg new file mode 100644 index 0000000..0cd157b --- /dev/null +++ b/Software/openocd.cfg @@ -0,0 +1,8 @@ +#OpenOCD configuration file, generated by STM32 for VSCode + +# Programmer, can be changed to several interfaces +# Standard will be the stlink interface as this is the standard for STM32 dev boards +source [find interface/stlink.cfg] + +# The target MCU. This should match your board +source [find target/stm32f3x.cfg] diff --git a/startup_stm32f302xc.s b/Software/startup_stm32f302xc.s similarity index 100% rename from startup_stm32f302xc.s rename to Software/startup_stm32f302xc.s