V1.8
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@ -17,6 +17,8 @@
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/* The PWM period (1/FPWM) is defined by the following parameters:
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ARR value, the Prescaler value, and the internal clock itself which drives the timer module FCLK.
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F_PWM = (F_CLK)/((ARR + 1) * (PSC + 1))
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(ARR + 1) * (PSC + 1) = (F_CLK)/(F_PWM)
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(PSC + 1) = (F_CLK)/(F_PWM * (ARR + 1))
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F_CLK = 16 MHz
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