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ft22-charger/Debug/TestCANChargerPCB.list

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TestCANChargerPCB.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 00000188 08000000 08000000 00010000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00004874 08000188 08000188 00010188 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000044 080049fc 080049fc 000149fc 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08004a40 08004a40 00020010 2**0
CONTENTS
4 .ARM 00000000 08004a40 08004a40 00020010 2**0
CONTENTS
5 .preinit_array 00000000 08004a40 08004a40 00020010 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 08004a40 08004a40 00014a40 2**2
CONTENTS, ALLOC, LOAD, DATA
7 .fini_array 00000004 08004a44 08004a44 00014a44 2**2
CONTENTS, ALLOC, LOAD, DATA
8 .data 00000010 20000000 08004a48 00020000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 00000140 20000010 08004a58 00020010 2**2
ALLOC
10 ._user_heap_stack 00000600 20000150 08004a58 00020150 2**0
ALLOC
11 .ARM.attributes 00000030 00000000 00000000 00020010 2**0
CONTENTS, READONLY
12 .debug_info 0000c6f2 00000000 00000000 00020040 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 00001cb8 00000000 00000000 0002c732 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 000008b0 00000000 00000000 0002e3f0 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_ranges 00000808 00000000 00000000 0002eca0 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 0001b408 00000000 00000000 0002f4a8 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 0000b514 00000000 00000000 0004a8b0 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 0009eb8a 00000000 00000000 00055dc4 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000050 00000000 00000000 000f494e 2**0
CONTENTS, READONLY
20 .debug_frame 000022cc 00000000 00000000 000f49a0 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
08000188 <__do_global_dtors_aux>:
8000188: b510 push {r4, lr}
800018a: 4c05 ldr r4, [pc, #20] ; (80001a0 <__do_global_dtors_aux+0x18>)
800018c: 7823 ldrb r3, [r4, #0]
800018e: b933 cbnz r3, 800019e <__do_global_dtors_aux+0x16>
8000190: 4b04 ldr r3, [pc, #16] ; (80001a4 <__do_global_dtors_aux+0x1c>)
8000192: b113 cbz r3, 800019a <__do_global_dtors_aux+0x12>
8000194: 4804 ldr r0, [pc, #16] ; (80001a8 <__do_global_dtors_aux+0x20>)
8000196: f3af 8000 nop.w
800019a: 2301 movs r3, #1
800019c: 7023 strb r3, [r4, #0]
800019e: bd10 pop {r4, pc}
80001a0: 20000010 .word 0x20000010
80001a4: 00000000 .word 0x00000000
80001a8: 080049e4 .word 0x080049e4
080001ac <frame_dummy>:
80001ac: b508 push {r3, lr}
80001ae: 4b03 ldr r3, [pc, #12] ; (80001bc <frame_dummy+0x10>)
80001b0: b11b cbz r3, 80001ba <frame_dummy+0xe>
80001b2: 4903 ldr r1, [pc, #12] ; (80001c0 <frame_dummy+0x14>)
80001b4: 4803 ldr r0, [pc, #12] ; (80001c4 <frame_dummy+0x18>)
80001b6: f3af 8000 nop.w
80001ba: bd08 pop {r3, pc}
80001bc: 00000000 .word 0x00000000
80001c0: 20000014 .word 0x20000014
80001c4: 080049e4 .word 0x080049e4
080001c8 <HAL_CAN_RxFifo0MsgPendingCallback>:
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan) {
80001c8: b580 push {r7, lr}
80001ca: b082 sub sp, #8
80001cc: af00 add r7, sp, #0
80001ce: 6078 str r0, [r7, #4]
if (HAL_CAN_GetRxMessage(hcan, CAN_RX_FIFO0, &RxHeader, RxData) != HAL_OK) {
80001d0: 4b21 ldr r3, [pc, #132] ; (8000258 <HAL_CAN_RxFifo0MsgPendingCallback+0x90>)
80001d2: 4a22 ldr r2, [pc, #136] ; (800025c <HAL_CAN_RxFifo0MsgPendingCallback+0x94>)
80001d4: 2100 movs r1, #0
80001d6: 6878 ldr r0, [r7, #4]
80001d8: f000 fedc bl 8000f94 <HAL_CAN_GetRxMessage>
80001dc: 4603 mov r3, r0
80001de: 2b00 cmp r3, #0
80001e0: d002 beq.n 80001e8 <HAL_CAN_RxFifo0MsgPendingCallback+0x20>
Error_Handler();
80001e2: f000 fa0f bl 8000604 <Error_Handler>
80001e6: e033 b.n 8000250 <HAL_CAN_RxFifo0MsgPendingCallback+0x88>
} else {
switch (RxHeader.StdId) {
80001e8: 4b1c ldr r3, [pc, #112] ; (800025c <HAL_CAN_RxFifo0MsgPendingCallback+0x94>)
80001ea: 681b ldr r3, [r3, #0]
80001ec: f240 5221 movw r2, #1313 ; 0x521
80001f0: 4293 cmp r3, r2
80001f2: d00e beq.n 8000212 <HAL_CAN_RxFifo0MsgPendingCallback+0x4a>
80001f4: f240 5221 movw r2, #1313 ; 0x521
80001f8: 4293 cmp r3, r2
80001fa: d828 bhi.n 800024e <HAL_CAN_RxFifo0MsgPendingCallback+0x86>
80001fc: 2b42 cmp r3, #66 ; 0x42
80001fe: d00e beq.n 800021e <HAL_CAN_RxFifo0MsgPendingCallback+0x56>
8000200: f5b3 6fa0 cmp.w r3, #1280 ; 0x500
8000204: d123 bne.n 800024e <HAL_CAN_RxFifo0MsgPendingCallback+0x86>
case 0x500: // Logging frame
memcpy(buffer, "LOG", 3);
8000206: 2203 movs r2, #3
8000208: 4915 ldr r1, [pc, #84] ; (8000260 <HAL_CAN_RxFifo0MsgPendingCallback+0x98>)
800020a: 4816 ldr r0, [pc, #88] ; (8000264 <HAL_CAN_RxFifo0MsgPendingCallback+0x9c>)
800020c: f004 fbd4 bl 80049b8 <memcpy>
break;
8000210: e011 b.n 8000236 <HAL_CAN_RxFifo0MsgPendingCallback+0x6e>
case 0x521: // Shunt current
memcpy(buffer, "CUR", 3);
8000212: 2203 movs r2, #3
8000214: 4914 ldr r1, [pc, #80] ; (8000268 <HAL_CAN_RxFifo0MsgPendingCallback+0xa0>)
8000216: 4813 ldr r0, [pc, #76] ; (8000264 <HAL_CAN_RxFifo0MsgPendingCallback+0x9c>)
8000218: f004 fbce bl 80049b8 <memcpy>
return;
800021c: e018 b.n 8000250 <HAL_CAN_RxFifo0MsgPendingCallback+0x88>
break;
case 0x42: // Panic frame
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_15, GPIO_PIN_RESET); // Open relay
800021e: 2200 movs r2, #0
8000220: f44f 4100 mov.w r1, #32768 ; 0x8000
8000224: 4811 ldr r0, [pc, #68] ; (800026c <HAL_CAN_RxFifo0MsgPendingCallback+0xa4>)
8000226: f001 fd25 bl 8001c74 <HAL_GPIO_WritePin>
memcpy(buffer, "PAN", 3);
800022a: 2203 movs r2, #3
800022c: 4910 ldr r1, [pc, #64] ; (8000270 <HAL_CAN_RxFifo0MsgPendingCallback+0xa8>)
800022e: 480d ldr r0, [pc, #52] ; (8000264 <HAL_CAN_RxFifo0MsgPendingCallback+0x9c>)
8000230: f004 fbc2 bl 80049b8 <memcpy>
break;
8000234: bf00 nop
default:
return;
memcpy(buffer, "???", 3);
}
memcpy(buffer + 3, RxData, 8);
8000236: 4b0f ldr r3, [pc, #60] ; (8000274 <HAL_CAN_RxFifo0MsgPendingCallback+0xac>)
8000238: 2208 movs r2, #8
800023a: 4907 ldr r1, [pc, #28] ; (8000258 <HAL_CAN_RxFifo0MsgPendingCallback+0x90>)
800023c: 4618 mov r0, r3
800023e: f004 fbbb bl 80049b8 <memcpy>
HAL_UART_Transmit_IT(&huart1, buffer, 11);
8000242: 220b movs r2, #11
8000244: 4907 ldr r1, [pc, #28] ; (8000264 <HAL_CAN_RxFifo0MsgPendingCallback+0x9c>)
8000246: 480c ldr r0, [pc, #48] ; (8000278 <HAL_CAN_RxFifo0MsgPendingCallback+0xb0>)
8000248: f003 f980 bl 800354c <HAL_UART_Transmit_IT>
800024c: e000 b.n 8000250 <HAL_CAN_RxFifo0MsgPendingCallback+0x88>
return;
800024e: bf00 nop
}
}
8000250: 3708 adds r7, #8
8000252: 46bd mov sp, r7
8000254: bd80 pop {r7, pc}
8000256: bf00 nop
8000258: 2000010c .word 0x2000010c
800025c: 200000f0 .word 0x200000f0
8000260: 080049fc .word 0x080049fc
8000264: 20000140 .word 0x20000140
8000268: 08004a00 .word 0x08004a00
800026c: 48000400 .word 0x48000400
8000270: 08004a04 .word 0x08004a04
8000274: 20000143 .word 0x20000143
8000278: 20000054 .word 0x20000054
0800027c <HAL_CAN_RxFifo1MsgPendingCallback>:
void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef* handle) {
800027c: b580 push {r7, lr}
800027e: b082 sub sp, #8
8000280: af00 add r7, sp, #0
8000282: 6078 str r0, [r7, #4]
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_15, GPIO_PIN_RESET);
8000284: 2200 movs r2, #0
8000286: f44f 4100 mov.w r1, #32768 ; 0x8000
800028a: 4803 ldr r0, [pc, #12] ; (8000298 <HAL_CAN_RxFifo1MsgPendingCallback+0x1c>)
800028c: f001 fcf2 bl 8001c74 <HAL_GPIO_WritePin>
}
8000290: bf00 nop
8000292: 3708 adds r7, #8
8000294: 46bd mov sp, r7
8000296: bd80 pop {r7, pc}
8000298: 48000400 .word 0x48000400
0800029c <HAL_UART_RxCpltCallback>:
void HAL_UART_RxCpltCallback(UART_HandleTypeDef* handle) {
800029c: b580 push {r7, lr}
800029e: b082 sub sp, #8
80002a0: af00 add r7, sp, #0
80002a2: 6078 str r0, [r7, #4]
if (uart_data[0] == 'C') {
80002a4: 4b0c ldr r3, [pc, #48] ; (80002d8 <HAL_UART_RxCpltCallback+0x3c>)
80002a6: 781b ldrb r3, [r3, #0]
80002a8: 2b43 cmp r3, #67 ; 0x43
80002aa: d10b bne.n 80002c4 <HAL_UART_RxCpltCallback+0x28>
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_15, GPIO_PIN_SET);
80002ac: 2201 movs r2, #1
80002ae: f44f 4100 mov.w r1, #32768 ; 0x8000
80002b2: 480a ldr r0, [pc, #40] ; (80002dc <HAL_UART_RxCpltCallback+0x40>)
80002b4: f001 fcde bl 8001c74 <HAL_GPIO_WritePin>
// HAL_Delay(500);
HAL_CAN_AddTxMessage(&hcan, &TxHeader, TxData, &TxMailbox);
80002b8: 4b09 ldr r3, [pc, #36] ; (80002e0 <HAL_UART_RxCpltCallback+0x44>)
80002ba: 4a0a ldr r2, [pc, #40] ; (80002e4 <HAL_UART_RxCpltCallback+0x48>)
80002bc: 490a ldr r1, [pc, #40] ; (80002e8 <HAL_UART_RxCpltCallback+0x4c>)
80002be: 480b ldr r0, [pc, #44] ; (80002ec <HAL_UART_RxCpltCallback+0x50>)
80002c0: f000 fd8d bl 8000dde <HAL_CAN_AddTxMessage>
}
HAL_UART_Receive_IT(&huart1, uart_data, 1);
80002c4: 2201 movs r2, #1
80002c6: 4904 ldr r1, [pc, #16] ; (80002d8 <HAL_UART_RxCpltCallback+0x3c>)
80002c8: 4809 ldr r0, [pc, #36] ; (80002f0 <HAL_UART_RxCpltCallback+0x54>)
80002ca: f003 f9ad bl 8003628 <HAL_UART_Receive_IT>
}
80002ce: bf00 nop
80002d0: 3708 adds r7, #8
80002d2: 46bd mov sp, r7
80002d4: bd80 pop {r7, pc}
80002d6: bf00 nop
80002d8: 20000134 .word 0x20000134
80002dc: 48000400 .word 0x48000400
80002e0: 2000013c .word 0x2000013c
80002e4: 20000120 .word 0x20000120
80002e8: 200000d8 .word 0x200000d8
80002ec: 2000002c .word 0x2000002c
80002f0: 20000054 .word 0x20000054
080002f4 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
80002f4: b580 push {r7, lr}
80002f6: b08a sub sp, #40 ; 0x28
80002f8: af00 add r7, sp, #0
/* USER CODE BEGIN 1 */
buffer[0] = 'l';
80002fa: 4b36 ldr r3, [pc, #216] ; (80003d4 <main+0xe0>)
80002fc: 226c movs r2, #108 ; 0x6c
80002fe: 701a strb r2, [r3, #0]
buffer[1] = 'o';
8000300: 4b34 ldr r3, [pc, #208] ; (80003d4 <main+0xe0>)
8000302: 226f movs r2, #111 ; 0x6f
8000304: 705a strb r2, [r3, #1]
buffer[2] = 'g';
8000306: 4b33 ldr r3, [pc, #204] ; (80003d4 <main+0xe0>)
8000308: 2267 movs r2, #103 ; 0x67
800030a: 709a strb r2, [r3, #2]
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
800030c: f000 fad4 bl 80008b8 <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
8000310: f000 f86c bl 80003ec <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
8000314: f000 f928 bl 8000568 <MX_GPIO_Init>
MX_CAN_Init();
8000318: f000 f8be bl 8000498 <MX_CAN_Init>
MX_USART1_UART_Init();
800031c: f000 f8f4 bl 8000508 <MX_USART1_UART_Init>
/* USER CODE BEGIN 2 */
if (HAL_CAN_Start(&hcan) != HAL_OK) {
8000320: 482d ldr r0, [pc, #180] ; (80003d8 <main+0xe4>)
8000322: f000 fd18 bl 8000d56 <HAL_CAN_Start>
8000326: 4603 mov r3, r0
8000328: 2b00 cmp r3, #0
800032a: d001 beq.n 8000330 <main+0x3c>
Error_Handler();
800032c: f000 f96a bl 8000604 <Error_Handler>
}
CAN_FilterTypeDef canfilterconfig;
canfilterconfig.FilterActivation = CAN_FILTER_ENABLE;
8000330: 2301 movs r3, #1
8000332: 623b str r3, [r7, #32]
canfilterconfig.FilterBank = 0;
8000334: 2300 movs r3, #0
8000336: 617b str r3, [r7, #20]
canfilterconfig.FilterFIFOAssignment = CAN_FILTER_FIFO0;
8000338: 2300 movs r3, #0
800033a: 613b str r3, [r7, #16]
canfilterconfig.FilterIdHigh = 0;
800033c: 2300 movs r3, #0
800033e: 603b str r3, [r7, #0]
canfilterconfig.FilterIdLow = 0;
8000340: 2300 movs r3, #0
8000342: 607b str r3, [r7, #4]
canfilterconfig.FilterMaskIdHigh = 0;
8000344: 2300 movs r3, #0
8000346: 60bb str r3, [r7, #8]
canfilterconfig.FilterMaskIdLow = 0;
8000348: 2300 movs r3, #0
800034a: 60fb str r3, [r7, #12]
canfilterconfig.FilterMode = CAN_FILTERMODE_IDMASK;
800034c: 2300 movs r3, #0
800034e: 61bb str r3, [r7, #24]
canfilterconfig.FilterScale = CAN_FILTERSCALE_32BIT;
8000350: 2301 movs r3, #1
8000352: 61fb str r3, [r7, #28]
canfilterconfig.SlaveStartFilterBank = 14;
8000354: 230e movs r3, #14
8000356: 627b str r3, [r7, #36] ; 0x24
if (HAL_CAN_ConfigFilter(&hcan, &canfilterconfig) != HAL_OK) {
8000358: 463b mov r3, r7
800035a: 4619 mov r1, r3
800035c: 481e ldr r0, [pc, #120] ; (80003d8 <main+0xe4>)
800035e: f000 fc30 bl 8000bc2 <HAL_CAN_ConfigFilter>
8000362: 4603 mov r3, r0
8000364: 2b00 cmp r3, #0
8000366: d001 beq.n 800036c <main+0x78>
Error_Handler();
8000368: f000 f94c bl 8000604 <Error_Handler>
}
if (HAL_CAN_ActivateNotification(&hcan, CAN_IT_RX_FIFO0_MSG_PENDING) !=
800036c: 2102 movs r1, #2
800036e: 481a ldr r0, [pc, #104] ; (80003d8 <main+0xe4>)
8000370: f000 ff22 bl 80011b8 <HAL_CAN_ActivateNotification>
8000374: 4603 mov r3, r0
8000376: 2b00 cmp r3, #0
8000378: d001 beq.n 800037e <main+0x8a>
HAL_OK) {
Error_Handler();
800037a: f000 f943 bl 8000604 <Error_Handler>
}
TxHeader.StdId = 0x446; // ID assigned to the charger
800037e: 4b17 ldr r3, [pc, #92] ; (80003dc <main+0xe8>)
8000380: f240 4246 movw r2, #1094 ; 0x446
8000384: 601a str r2, [r3, #0]
TxHeader.ExtId = 0x00;
8000386: 4b15 ldr r3, [pc, #84] ; (80003dc <main+0xe8>)
8000388: 2200 movs r2, #0
800038a: 605a str r2, [r3, #4]
TxHeader.RTR = CAN_RTR_DATA;
800038c: 4b13 ldr r3, [pc, #76] ; (80003dc <main+0xe8>)
800038e: 2200 movs r2, #0
8000390: 60da str r2, [r3, #12]
TxHeader.IDE = CAN_ID_STD;
8000392: 4b12 ldr r3, [pc, #72] ; (80003dc <main+0xe8>)
8000394: 2200 movs r2, #0
8000396: 609a str r2, [r3, #8]
TxHeader.DLC = 0;
8000398: 4b10 ldr r3, [pc, #64] ; (80003dc <main+0xe8>)
800039a: 2200 movs r2, #0
800039c: 611a str r2, [r3, #16]
TxHeader.TransmitGlobalTime = DISABLE;
800039e: 4b0f ldr r3, [pc, #60] ; (80003dc <main+0xe8>)
80003a0: 2200 movs r2, #0
80003a2: 751a strb r2, [r3, #20]
HAL_Delay(1000);
80003a4: f44f 707a mov.w r0, #1000 ; 0x3e8
80003a8: f000 faec bl 8000984 <HAL_Delay>
// strcpy((char *)TxData, "akku");
// HAL_CAN_AddTxMessage(&hcan, &TxHeader, TxData, &TxMailbox);
HAL_UART_Receive_IT(&huart1, uart_data, 1);
80003ac: 2201 movs r2, #1
80003ae: 490c ldr r1, [pc, #48] ; (80003e0 <main+0xec>)
80003b0: 480c ldr r0, [pc, #48] ; (80003e4 <main+0xf0>)
80003b2: f003 f939 bl 8003628 <HAL_UART_Receive_IT>
/* USER CODE END WHILE */
/* USER CODE BEGIN 3 */
// if (HAL_UART_Receive(&huart1, data, 1, 100) == HAL_OK && data[0] == 'C') {
// }
if (HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_12) == 0) {
80003b6: f44f 5180 mov.w r1, #4096 ; 0x1000
80003ba: 480b ldr r0, [pc, #44] ; (80003e8 <main+0xf4>)
80003bc: f001 fc42 bl 8001c44 <HAL_GPIO_ReadPin>
80003c0: 4603 mov r3, r0
80003c2: 2b00 cmp r3, #0
80003c4: d1f7 bne.n 80003b6 <main+0xc2>
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_15, GPIO_PIN_RESET); // Relay schliessen
80003c6: 2200 movs r2, #0
80003c8: f44f 4100 mov.w r1, #32768 ; 0x8000
80003cc: 4806 ldr r0, [pc, #24] ; (80003e8 <main+0xf4>)
80003ce: f001 fc51 bl 8001c74 <HAL_GPIO_WritePin>
if (HAL_GPIO_ReadPin(GPIOB, GPIO_PIN_12) == 0) {
80003d2: e7f0 b.n 80003b6 <main+0xc2>
80003d4: 20000140 .word 0x20000140
80003d8: 2000002c .word 0x2000002c
80003dc: 200000d8 .word 0x200000d8
80003e0: 20000134 .word 0x20000134
80003e4: 20000054 .word 0x20000054
80003e8: 48000400 .word 0x48000400
080003ec <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
80003ec: b580 push {r7, lr}
80003ee: b09c sub sp, #112 ; 0x70
80003f0: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
80003f2: f107 0348 add.w r3, r7, #72 ; 0x48
80003f6: 2228 movs r2, #40 ; 0x28
80003f8: 2100 movs r1, #0
80003fa: 4618 mov r0, r3
80003fc: f004 faea bl 80049d4 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
8000400: f107 0334 add.w r3, r7, #52 ; 0x34
8000404: 2200 movs r2, #0
8000406: 601a str r2, [r3, #0]
8000408: 605a str r2, [r3, #4]
800040a: 609a str r2, [r3, #8]
800040c: 60da str r2, [r3, #12]
800040e: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
8000410: 463b mov r3, r7
8000412: 2234 movs r2, #52 ; 0x34
8000414: 2100 movs r1, #0
8000416: 4618 mov r0, r3
8000418: f004 fadc bl 80049d4 <memset>
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
800041c: 2302 movs r3, #2
800041e: 64bb str r3, [r7, #72] ; 0x48
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
8000420: 2301 movs r3, #1
8000422: 65bb str r3, [r7, #88] ; 0x58
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
8000424: 2310 movs r3, #16
8000426: 65fb str r3, [r7, #92] ; 0x5c
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
8000428: 2302 movs r3, #2
800042a: 667b str r3, [r7, #100] ; 0x64
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
800042c: 2300 movs r3, #0
800042e: 66bb str r3, [r7, #104] ; 0x68
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL4;
8000430: f44f 2300 mov.w r3, #524288 ; 0x80000
8000434: 66fb str r3, [r7, #108] ; 0x6c
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
8000436: f107 0348 add.w r3, r7, #72 ; 0x48
800043a: 4618 mov r0, r3
800043c: f001 fc32 bl 8001ca4 <HAL_RCC_OscConfig>
8000440: 4603 mov r3, r0
8000442: 2b00 cmp r3, #0
8000444: d001 beq.n 800044a <SystemClock_Config+0x5e>
{
Error_Handler();
8000446: f000 f8dd bl 8000604 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
800044a: 230f movs r3, #15
800044c: 637b str r3, [r7, #52] ; 0x34
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
800044e: 2302 movs r3, #2
8000450: 63bb str r3, [r7, #56] ; 0x38
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
8000452: 2300 movs r3, #0
8000454: 63fb str r3, [r7, #60] ; 0x3c
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
8000456: f44f 6380 mov.w r3, #1024 ; 0x400
800045a: 643b str r3, [r7, #64] ; 0x40
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
800045c: 2300 movs r3, #0
800045e: 647b str r3, [r7, #68] ; 0x44
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
8000460: f107 0334 add.w r3, r7, #52 ; 0x34
8000464: 2100 movs r1, #0
8000466: 4618 mov r0, r3
8000468: f002 fc5a bl 8002d20 <HAL_RCC_ClockConfig>
800046c: 4603 mov r3, r0
800046e: 2b00 cmp r3, #0
8000470: d001 beq.n 8000476 <SystemClock_Config+0x8a>
{
Error_Handler();
8000472: f000 f8c7 bl 8000604 <Error_Handler>
}
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1;
8000476: 2301 movs r3, #1
8000478: 603b str r3, [r7, #0]
PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK1;
800047a: 2300 movs r3, #0
800047c: 60bb str r3, [r7, #8]
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
800047e: 463b mov r3, r7
8000480: 4618 mov r0, r3
8000482: f002 fe83 bl 800318c <HAL_RCCEx_PeriphCLKConfig>
8000486: 4603 mov r3, r0
8000488: 2b00 cmp r3, #0
800048a: d001 beq.n 8000490 <SystemClock_Config+0xa4>
{
Error_Handler();
800048c: f000 f8ba bl 8000604 <Error_Handler>
}
}
8000490: bf00 nop
8000492: 3770 adds r7, #112 ; 0x70
8000494: 46bd mov sp, r7
8000496: bd80 pop {r7, pc}
08000498 <MX_CAN_Init>:
* @brief CAN Initialization Function
* @param None
* @retval None
*/
static void MX_CAN_Init(void)
{
8000498: b580 push {r7, lr}
800049a: af00 add r7, sp, #0
/* USER CODE END CAN_Init 0 */
/* USER CODE BEGIN CAN_Init 1 */
/* USER CODE END CAN_Init 1 */
hcan.Instance = CAN;
800049c: 4b18 ldr r3, [pc, #96] ; (8000500 <MX_CAN_Init+0x68>)
800049e: 4a19 ldr r2, [pc, #100] ; (8000504 <MX_CAN_Init+0x6c>)
80004a0: 601a str r2, [r3, #0]
hcan.Init.Prescaler = 1;
80004a2: 4b17 ldr r3, [pc, #92] ; (8000500 <MX_CAN_Init+0x68>)
80004a4: 2201 movs r2, #1
80004a6: 605a str r2, [r3, #4]
hcan.Init.Mode = CAN_MODE_NORMAL;
80004a8: 4b15 ldr r3, [pc, #84] ; (8000500 <MX_CAN_Init+0x68>)
80004aa: 2200 movs r2, #0
80004ac: 609a str r2, [r3, #8]
hcan.Init.SyncJumpWidth = CAN_SJW_3TQ;
80004ae: 4b14 ldr r3, [pc, #80] ; (8000500 <MX_CAN_Init+0x68>)
80004b0: f04f 7200 mov.w r2, #33554432 ; 0x2000000
80004b4: 60da str r2, [r3, #12]
hcan.Init.TimeSeg1 = CAN_BS1_13TQ;
80004b6: 4b12 ldr r3, [pc, #72] ; (8000500 <MX_CAN_Init+0x68>)
80004b8: f44f 2240 mov.w r2, #786432 ; 0xc0000
80004bc: 611a str r2, [r3, #16]
hcan.Init.TimeSeg2 = CAN_BS2_2TQ;
80004be: 4b10 ldr r3, [pc, #64] ; (8000500 <MX_CAN_Init+0x68>)
80004c0: f44f 1280 mov.w r2, #1048576 ; 0x100000
80004c4: 615a str r2, [r3, #20]
hcan.Init.TimeTriggeredMode = DISABLE;
80004c6: 4b0e ldr r3, [pc, #56] ; (8000500 <MX_CAN_Init+0x68>)
80004c8: 2200 movs r2, #0
80004ca: 761a strb r2, [r3, #24]
hcan.Init.AutoBusOff = DISABLE;
80004cc: 4b0c ldr r3, [pc, #48] ; (8000500 <MX_CAN_Init+0x68>)
80004ce: 2200 movs r2, #0
80004d0: 765a strb r2, [r3, #25]
hcan.Init.AutoWakeUp = DISABLE;
80004d2: 4b0b ldr r3, [pc, #44] ; (8000500 <MX_CAN_Init+0x68>)
80004d4: 2200 movs r2, #0
80004d6: 769a strb r2, [r3, #26]
hcan.Init.AutoRetransmission = DISABLE;
80004d8: 4b09 ldr r3, [pc, #36] ; (8000500 <MX_CAN_Init+0x68>)
80004da: 2200 movs r2, #0
80004dc: 76da strb r2, [r3, #27]
hcan.Init.ReceiveFifoLocked = DISABLE;
80004de: 4b08 ldr r3, [pc, #32] ; (8000500 <MX_CAN_Init+0x68>)
80004e0: 2200 movs r2, #0
80004e2: 771a strb r2, [r3, #28]
hcan.Init.TransmitFifoPriority = DISABLE;
80004e4: 4b06 ldr r3, [pc, #24] ; (8000500 <MX_CAN_Init+0x68>)
80004e6: 2200 movs r2, #0
80004e8: 775a strb r2, [r3, #29]
if (HAL_CAN_Init(&hcan) != HAL_OK)
80004ea: 4805 ldr r0, [pc, #20] ; (8000500 <MX_CAN_Init+0x68>)
80004ec: f000 fa6e bl 80009cc <HAL_CAN_Init>
80004f0: 4603 mov r3, r0
80004f2: 2b00 cmp r3, #0
80004f4: d001 beq.n 80004fa <MX_CAN_Init+0x62>
{
Error_Handler();
80004f6: f000 f885 bl 8000604 <Error_Handler>
}
/* USER CODE BEGIN CAN_Init 2 */
/* USER CODE END CAN_Init 2 */
}
80004fa: bf00 nop
80004fc: bd80 pop {r7, pc}
80004fe: bf00 nop
8000500: 2000002c .word 0x2000002c
8000504: 40006400 .word 0x40006400
08000508 <MX_USART1_UART_Init>:
* @brief USART1 Initialization Function
* @param None
* @retval None
*/
static void MX_USART1_UART_Init(void)
{
8000508: b580 push {r7, lr}
800050a: af00 add r7, sp, #0
/* USER CODE END USART1_Init 0 */
/* USER CODE BEGIN USART1_Init 1 */
/* USER CODE END USART1_Init 1 */
huart1.Instance = USART1;
800050c: 4b14 ldr r3, [pc, #80] ; (8000560 <MX_USART1_UART_Init+0x58>)
800050e: 4a15 ldr r2, [pc, #84] ; (8000564 <MX_USART1_UART_Init+0x5c>)
8000510: 601a str r2, [r3, #0]
huart1.Init.BaudRate = 115200;
8000512: 4b13 ldr r3, [pc, #76] ; (8000560 <MX_USART1_UART_Init+0x58>)
8000514: f44f 32e1 mov.w r2, #115200 ; 0x1c200
8000518: 605a str r2, [r3, #4]
huart1.Init.WordLength = UART_WORDLENGTH_8B;
800051a: 4b11 ldr r3, [pc, #68] ; (8000560 <MX_USART1_UART_Init+0x58>)
800051c: 2200 movs r2, #0
800051e: 609a str r2, [r3, #8]
huart1.Init.StopBits = UART_STOPBITS_1;
8000520: 4b0f ldr r3, [pc, #60] ; (8000560 <MX_USART1_UART_Init+0x58>)
8000522: 2200 movs r2, #0
8000524: 60da str r2, [r3, #12]
huart1.Init.Parity = UART_PARITY_NONE;
8000526: 4b0e ldr r3, [pc, #56] ; (8000560 <MX_USART1_UART_Init+0x58>)
8000528: 2200 movs r2, #0
800052a: 611a str r2, [r3, #16]
huart1.Init.Mode = UART_MODE_TX_RX;
800052c: 4b0c ldr r3, [pc, #48] ; (8000560 <MX_USART1_UART_Init+0x58>)
800052e: 220c movs r2, #12
8000530: 615a str r2, [r3, #20]
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
8000532: 4b0b ldr r3, [pc, #44] ; (8000560 <MX_USART1_UART_Init+0x58>)
8000534: 2200 movs r2, #0
8000536: 619a str r2, [r3, #24]
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
8000538: 4b09 ldr r3, [pc, #36] ; (8000560 <MX_USART1_UART_Init+0x58>)
800053a: 2200 movs r2, #0
800053c: 61da str r2, [r3, #28]
huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
800053e: 4b08 ldr r3, [pc, #32] ; (8000560 <MX_USART1_UART_Init+0x58>)
8000540: 2200 movs r2, #0
8000542: 621a str r2, [r3, #32]
huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
8000544: 4b06 ldr r3, [pc, #24] ; (8000560 <MX_USART1_UART_Init+0x58>)
8000546: 2200 movs r2, #0
8000548: 625a str r2, [r3, #36] ; 0x24
if (HAL_UART_Init(&huart1) != HAL_OK)
800054a: 4805 ldr r0, [pc, #20] ; (8000560 <MX_USART1_UART_Init+0x58>)
800054c: f002 ffb0 bl 80034b0 <HAL_UART_Init>
8000550: 4603 mov r3, r0
8000552: 2b00 cmp r3, #0
8000554: d001 beq.n 800055a <MX_USART1_UART_Init+0x52>
{
Error_Handler();
8000556: f000 f855 bl 8000604 <Error_Handler>
}
/* USER CODE BEGIN USART1_Init 2 */
/* USER CODE END USART1_Init 2 */
}
800055a: bf00 nop
800055c: bd80 pop {r7, pc}
800055e: bf00 nop
8000560: 20000054 .word 0x20000054
8000564: 40013800 .word 0x40013800
08000568 <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
8000568: b580 push {r7, lr}
800056a: b088 sub sp, #32
800056c: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
800056e: f107 030c add.w r3, r7, #12
8000572: 2200 movs r2, #0
8000574: 601a str r2, [r3, #0]
8000576: 605a str r2, [r3, #4]
8000578: 609a str r2, [r3, #8]
800057a: 60da str r2, [r3, #12]
800057c: 611a str r2, [r3, #16]
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOB_CLK_ENABLE();
800057e: 4b1f ldr r3, [pc, #124] ; (80005fc <MX_GPIO_Init+0x94>)
8000580: 695b ldr r3, [r3, #20]
8000582: 4a1e ldr r2, [pc, #120] ; (80005fc <MX_GPIO_Init+0x94>)
8000584: f443 2380 orr.w r3, r3, #262144 ; 0x40000
8000588: 6153 str r3, [r2, #20]
800058a: 4b1c ldr r3, [pc, #112] ; (80005fc <MX_GPIO_Init+0x94>)
800058c: 695b ldr r3, [r3, #20]
800058e: f403 2380 and.w r3, r3, #262144 ; 0x40000
8000592: 60bb str r3, [r7, #8]
8000594: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOA_CLK_ENABLE();
8000596: 4b19 ldr r3, [pc, #100] ; (80005fc <MX_GPIO_Init+0x94>)
8000598: 695b ldr r3, [r3, #20]
800059a: 4a18 ldr r2, [pc, #96] ; (80005fc <MX_GPIO_Init+0x94>)
800059c: f443 3300 orr.w r3, r3, #131072 ; 0x20000
80005a0: 6153 str r3, [r2, #20]
80005a2: 4b16 ldr r3, [pc, #88] ; (80005fc <MX_GPIO_Init+0x94>)
80005a4: 695b ldr r3, [r3, #20]
80005a6: f403 3300 and.w r3, r3, #131072 ; 0x20000
80005aa: 607b str r3, [r7, #4]
80005ac: 687b ldr r3, [r7, #4]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(RelayCtrl_GPIO_Port, RelayCtrl_Pin, GPIO_PIN_RESET);
80005ae: 2200 movs r2, #0
80005b0: f44f 4100 mov.w r1, #32768 ; 0x8000
80005b4: 4812 ldr r0, [pc, #72] ; (8000600 <MX_GPIO_Init+0x98>)
80005b6: f001 fb5d bl 8001c74 <HAL_GPIO_WritePin>
/*Configure GPIO pin : SC_IN_Pin */
GPIO_InitStruct.Pin = SC_IN_Pin;
80005ba: f44f 5380 mov.w r3, #4096 ; 0x1000
80005be: 60fb str r3, [r7, #12]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
80005c0: 2300 movs r3, #0
80005c2: 613b str r3, [r7, #16]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80005c4: 2300 movs r3, #0
80005c6: 617b str r3, [r7, #20]
HAL_GPIO_Init(SC_IN_GPIO_Port, &GPIO_InitStruct);
80005c8: f107 030c add.w r3, r7, #12
80005cc: 4619 mov r1, r3
80005ce: 480c ldr r0, [pc, #48] ; (8000600 <MX_GPIO_Init+0x98>)
80005d0: f001 f9c6 bl 8001960 <HAL_GPIO_Init>
/*Configure GPIO pin : RelayCtrl_Pin */
GPIO_InitStruct.Pin = RelayCtrl_Pin;
80005d4: f44f 4300 mov.w r3, #32768 ; 0x8000
80005d8: 60fb str r3, [r7, #12]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
80005da: 2301 movs r3, #1
80005dc: 613b str r3, [r7, #16]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80005de: 2300 movs r3, #0
80005e0: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80005e2: 2300 movs r3, #0
80005e4: 61bb str r3, [r7, #24]
HAL_GPIO_Init(RelayCtrl_GPIO_Port, &GPIO_InitStruct);
80005e6: f107 030c add.w r3, r7, #12
80005ea: 4619 mov r1, r3
80005ec: 4804 ldr r0, [pc, #16] ; (8000600 <MX_GPIO_Init+0x98>)
80005ee: f001 f9b7 bl 8001960 <HAL_GPIO_Init>
}
80005f2: bf00 nop
80005f4: 3720 adds r7, #32
80005f6: 46bd mov sp, r7
80005f8: bd80 pop {r7, pc}
80005fa: bf00 nop
80005fc: 40021000 .word 0x40021000
8000600: 48000400 .word 0x48000400
08000604 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
8000604: b480 push {r7}
8000606: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
8000608: b672 cpsid i
}
800060a: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1) {
800060c: e7fe b.n 800060c <Error_Handler+0x8>
...
08000610 <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8000610: b480 push {r7}
8000612: b083 sub sp, #12
8000614: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8000616: 4b0f ldr r3, [pc, #60] ; (8000654 <HAL_MspInit+0x44>)
8000618: 699b ldr r3, [r3, #24]
800061a: 4a0e ldr r2, [pc, #56] ; (8000654 <HAL_MspInit+0x44>)
800061c: f043 0301 orr.w r3, r3, #1
8000620: 6193 str r3, [r2, #24]
8000622: 4b0c ldr r3, [pc, #48] ; (8000654 <HAL_MspInit+0x44>)
8000624: 699b ldr r3, [r3, #24]
8000626: f003 0301 and.w r3, r3, #1
800062a: 607b str r3, [r7, #4]
800062c: 687b ldr r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
800062e: 4b09 ldr r3, [pc, #36] ; (8000654 <HAL_MspInit+0x44>)
8000630: 69db ldr r3, [r3, #28]
8000632: 4a08 ldr r2, [pc, #32] ; (8000654 <HAL_MspInit+0x44>)
8000634: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8000638: 61d3 str r3, [r2, #28]
800063a: 4b06 ldr r3, [pc, #24] ; (8000654 <HAL_MspInit+0x44>)
800063c: 69db ldr r3, [r3, #28]
800063e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8000642: 603b str r3, [r7, #0]
8000644: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
8000646: bf00 nop
8000648: 370c adds r7, #12
800064a: 46bd mov sp, r7
800064c: f85d 7b04 ldr.w r7, [sp], #4
8000650: 4770 bx lr
8000652: bf00 nop
8000654: 40021000 .word 0x40021000
08000658 <HAL_CAN_MspInit>:
* This function configures the hardware resources used in this example
* @param hcan: CAN handle pointer
* @retval None
*/
void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
{
8000658: b580 push {r7, lr}
800065a: b08a sub sp, #40 ; 0x28
800065c: af00 add r7, sp, #0
800065e: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000660: f107 0314 add.w r3, r7, #20
8000664: 2200 movs r2, #0
8000666: 601a str r2, [r3, #0]
8000668: 605a str r2, [r3, #4]
800066a: 609a str r2, [r3, #8]
800066c: 60da str r2, [r3, #12]
800066e: 611a str r2, [r3, #16]
if(hcan->Instance==CAN)
8000670: 687b ldr r3, [r7, #4]
8000672: 681b ldr r3, [r3, #0]
8000674: 4a1f ldr r2, [pc, #124] ; (80006f4 <HAL_CAN_MspInit+0x9c>)
8000676: 4293 cmp r3, r2
8000678: d138 bne.n 80006ec <HAL_CAN_MspInit+0x94>
{
/* USER CODE BEGIN CAN_MspInit 0 */
/* USER CODE END CAN_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_CAN1_CLK_ENABLE();
800067a: 4b1f ldr r3, [pc, #124] ; (80006f8 <HAL_CAN_MspInit+0xa0>)
800067c: 69db ldr r3, [r3, #28]
800067e: 4a1e ldr r2, [pc, #120] ; (80006f8 <HAL_CAN_MspInit+0xa0>)
8000680: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000
8000684: 61d3 str r3, [r2, #28]
8000686: 4b1c ldr r3, [pc, #112] ; (80006f8 <HAL_CAN_MspInit+0xa0>)
8000688: 69db ldr r3, [r3, #28]
800068a: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
800068e: 613b str r3, [r7, #16]
8000690: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOB_CLK_ENABLE();
8000692: 4b19 ldr r3, [pc, #100] ; (80006f8 <HAL_CAN_MspInit+0xa0>)
8000694: 695b ldr r3, [r3, #20]
8000696: 4a18 ldr r2, [pc, #96] ; (80006f8 <HAL_CAN_MspInit+0xa0>)
8000698: f443 2380 orr.w r3, r3, #262144 ; 0x40000
800069c: 6153 str r3, [r2, #20]
800069e: 4b16 ldr r3, [pc, #88] ; (80006f8 <HAL_CAN_MspInit+0xa0>)
80006a0: 695b ldr r3, [r3, #20]
80006a2: f403 2380 and.w r3, r3, #262144 ; 0x40000
80006a6: 60fb str r3, [r7, #12]
80006a8: 68fb ldr r3, [r7, #12]
/**CAN GPIO Configuration
PB8 ------> CAN_RX
PB9 ------> CAN_TX
*/
GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9;
80006aa: f44f 7340 mov.w r3, #768 ; 0x300
80006ae: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80006b0: 2302 movs r3, #2
80006b2: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80006b4: 2300 movs r3, #0
80006b6: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
80006b8: 2303 movs r3, #3
80006ba: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF9_TIM1;
80006bc: 2309 movs r3, #9
80006be: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80006c0: f107 0314 add.w r3, r7, #20
80006c4: 4619 mov r1, r3
80006c6: 480d ldr r0, [pc, #52] ; (80006fc <HAL_CAN_MspInit+0xa4>)
80006c8: f001 f94a bl 8001960 <HAL_GPIO_Init>
/* CAN interrupt Init */
HAL_NVIC_SetPriority(USB_LP_CAN_RX0_IRQn, 0, 0);
80006cc: 2200 movs r2, #0
80006ce: 2100 movs r1, #0
80006d0: 2014 movs r0, #20
80006d2: f001 f898 bl 8001806 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(USB_LP_CAN_RX0_IRQn);
80006d6: 2014 movs r0, #20
80006d8: f001 f8b1 bl 800183e <HAL_NVIC_EnableIRQ>
HAL_NVIC_SetPriority(CAN_RX1_IRQn, 0, 0);
80006dc: 2200 movs r2, #0
80006de: 2100 movs r1, #0
80006e0: 2015 movs r0, #21
80006e2: f001 f890 bl 8001806 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(CAN_RX1_IRQn);
80006e6: 2015 movs r0, #21
80006e8: f001 f8a9 bl 800183e <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN CAN_MspInit 1 */
/* USER CODE END CAN_MspInit 1 */
}
}
80006ec: bf00 nop
80006ee: 3728 adds r7, #40 ; 0x28
80006f0: 46bd mov sp, r7
80006f2: bd80 pop {r7, pc}
80006f4: 40006400 .word 0x40006400
80006f8: 40021000 .word 0x40021000
80006fc: 48000400 .word 0x48000400
08000700 <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
8000700: b580 push {r7, lr}
8000702: b08a sub sp, #40 ; 0x28
8000704: af00 add r7, sp, #0
8000706: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000708: f107 0314 add.w r3, r7, #20
800070c: 2200 movs r2, #0
800070e: 601a str r2, [r3, #0]
8000710: 605a str r2, [r3, #4]
8000712: 609a str r2, [r3, #8]
8000714: 60da str r2, [r3, #12]
8000716: 611a str r2, [r3, #16]
if(huart->Instance==USART1)
8000718: 687b ldr r3, [r7, #4]
800071a: 681b ldr r3, [r3, #0]
800071c: 4a1c ldr r2, [pc, #112] ; (8000790 <HAL_UART_MspInit+0x90>)
800071e: 4293 cmp r3, r2
8000720: d131 bne.n 8000786 <HAL_UART_MspInit+0x86>
{
/* USER CODE BEGIN USART1_MspInit 0 */
/* USER CODE END USART1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_USART1_CLK_ENABLE();
8000722: 4b1c ldr r3, [pc, #112] ; (8000794 <HAL_UART_MspInit+0x94>)
8000724: 699b ldr r3, [r3, #24]
8000726: 4a1b ldr r2, [pc, #108] ; (8000794 <HAL_UART_MspInit+0x94>)
8000728: f443 4380 orr.w r3, r3, #16384 ; 0x4000
800072c: 6193 str r3, [r2, #24]
800072e: 4b19 ldr r3, [pc, #100] ; (8000794 <HAL_UART_MspInit+0x94>)
8000730: 699b ldr r3, [r3, #24]
8000732: f403 4380 and.w r3, r3, #16384 ; 0x4000
8000736: 613b str r3, [r7, #16]
8000738: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
800073a: 4b16 ldr r3, [pc, #88] ; (8000794 <HAL_UART_MspInit+0x94>)
800073c: 695b ldr r3, [r3, #20]
800073e: 4a15 ldr r2, [pc, #84] ; (8000794 <HAL_UART_MspInit+0x94>)
8000740: f443 3300 orr.w r3, r3, #131072 ; 0x20000
8000744: 6153 str r3, [r2, #20]
8000746: 4b13 ldr r3, [pc, #76] ; (8000794 <HAL_UART_MspInit+0x94>)
8000748: 695b ldr r3, [r3, #20]
800074a: f403 3300 and.w r3, r3, #131072 ; 0x20000
800074e: 60fb str r3, [r7, #12]
8000750: 68fb ldr r3, [r7, #12]
/**USART1 GPIO Configuration
PA9 ------> USART1_TX
PA10 ------> USART1_RX
*/
GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10;
8000752: f44f 63c0 mov.w r3, #1536 ; 0x600
8000756: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000758: 2302 movs r3, #2
800075a: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800075c: 2300 movs r3, #0
800075e: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
8000760: 2303 movs r3, #3
8000762: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
8000764: 2307 movs r3, #7
8000766: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000768: f107 0314 add.w r3, r7, #20
800076c: 4619 mov r1, r3
800076e: f04f 4090 mov.w r0, #1207959552 ; 0x48000000
8000772: f001 f8f5 bl 8001960 <HAL_GPIO_Init>
/* USART1 interrupt Init */
HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
8000776: 2200 movs r2, #0
8000778: 2100 movs r1, #0
800077a: 2025 movs r0, #37 ; 0x25
800077c: f001 f843 bl 8001806 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(USART1_IRQn);
8000780: 2025 movs r0, #37 ; 0x25
8000782: f001 f85c bl 800183e <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN USART1_MspInit 1 */
/* USER CODE END USART1_MspInit 1 */
}
}
8000786: bf00 nop
8000788: 3728 adds r7, #40 ; 0x28
800078a: 46bd mov sp, r7
800078c: bd80 pop {r7, pc}
800078e: bf00 nop
8000790: 40013800 .word 0x40013800
8000794: 40021000 .word 0x40021000
08000798 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8000798: b480 push {r7}
800079a: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
800079c: e7fe b.n 800079c <NMI_Handler+0x4>
0800079e <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
800079e: b480 push {r7}
80007a0: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
80007a2: e7fe b.n 80007a2 <HardFault_Handler+0x4>
080007a4 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
80007a4: b480 push {r7}
80007a6: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
80007a8: e7fe b.n 80007a8 <MemManage_Handler+0x4>
080007aa <BusFault_Handler>:
/**
* @brief This function handles Pre-fetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
80007aa: b480 push {r7}
80007ac: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
80007ae: e7fe b.n 80007ae <BusFault_Handler+0x4>
080007b0 <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
80007b0: b480 push {r7}
80007b2: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
80007b4: e7fe b.n 80007b4 <UsageFault_Handler+0x4>
080007b6 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
80007b6: b480 push {r7}
80007b8: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
80007ba: bf00 nop
80007bc: 46bd mov sp, r7
80007be: f85d 7b04 ldr.w r7, [sp], #4
80007c2: 4770 bx lr
080007c4 <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
80007c4: b480 push {r7}
80007c6: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
80007c8: bf00 nop
80007ca: 46bd mov sp, r7
80007cc: f85d 7b04 ldr.w r7, [sp], #4
80007d0: 4770 bx lr
080007d2 <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
80007d2: b480 push {r7}
80007d4: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
80007d6: bf00 nop
80007d8: 46bd mov sp, r7
80007da: f85d 7b04 ldr.w r7, [sp], #4
80007de: 4770 bx lr
080007e0 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
80007e0: b580 push {r7, lr}
80007e2: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
80007e4: f000 f8ae bl 8000944 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
failsafe--;
80007e8: 4b05 ldr r3, [pc, #20] ; (8000800 <SysTick_Handler+0x20>)
80007ea: f9b3 3000 ldrsh.w r3, [r3]
80007ee: b29b uxth r3, r3
80007f0: 3b01 subs r3, #1
80007f2: b29b uxth r3, r3
80007f4: b21a sxth r2, r3
80007f6: 4b02 ldr r3, [pc, #8] ; (8000800 <SysTick_Handler+0x20>)
80007f8: 801a strh r2, [r3, #0]
/* USER CODE END SysTick_IRQn 1 */
}
80007fa: bf00 nop
80007fc: bd80 pop {r7, pc}
80007fe: bf00 nop
8000800: 20000000 .word 0x20000000
08000804 <USB_LP_CAN_RX0_IRQHandler>:
/**
* @brief This function handles CAN RX0 and USB low priority interrupts.
*/
void USB_LP_CAN_RX0_IRQHandler(void)
{
8000804: b580 push {r7, lr}
8000806: af00 add r7, sp, #0
/* USER CODE BEGIN USB_LP_CAN_RX0_IRQn 0 */
/* USER CODE END USB_LP_CAN_RX0_IRQn 0 */
HAL_CAN_IRQHandler(&hcan);
8000808: 4802 ldr r0, [pc, #8] ; (8000814 <USB_LP_CAN_RX0_IRQHandler+0x10>)
800080a: f000 fcfb bl 8001204 <HAL_CAN_IRQHandler>
/* USER CODE BEGIN USB_LP_CAN_RX0_IRQn 1 */
/* USER CODE END USB_LP_CAN_RX0_IRQn 1 */
}
800080e: bf00 nop
8000810: bd80 pop {r7, pc}
8000812: bf00 nop
8000814: 2000002c .word 0x2000002c
08000818 <CAN_RX1_IRQHandler>:
/**
* @brief This function handles CAN RX1 interrupt.
*/
void CAN_RX1_IRQHandler(void)
{
8000818: b580 push {r7, lr}
800081a: af00 add r7, sp, #0
/* USER CODE BEGIN CAN_RX1_IRQn 0 */
/* USER CODE END CAN_RX1_IRQn 0 */
HAL_CAN_IRQHandler(&hcan);
800081c: 4802 ldr r0, [pc, #8] ; (8000828 <CAN_RX1_IRQHandler+0x10>)
800081e: f000 fcf1 bl 8001204 <HAL_CAN_IRQHandler>
/* USER CODE BEGIN CAN_RX1_IRQn 1 */
/* USER CODE END CAN_RX1_IRQn 1 */
}
8000822: bf00 nop
8000824: bd80 pop {r7, pc}
8000826: bf00 nop
8000828: 2000002c .word 0x2000002c
0800082c <USART1_IRQHandler>:
/**
* @brief This function handles USART1 global interrupt / USART1 wake-up interrupt through EXTI line 25.
*/
void USART1_IRQHandler(void)
{
800082c: b580 push {r7, lr}
800082e: af00 add r7, sp, #0
/* USER CODE BEGIN USART1_IRQn 0 */
/* USER CODE END USART1_IRQn 0 */
HAL_UART_IRQHandler(&huart1);
8000830: 4802 ldr r0, [pc, #8] ; (800083c <USART1_IRQHandler+0x10>)
8000832: f002 ff47 bl 80036c4 <HAL_UART_IRQHandler>
/* USER CODE BEGIN USART1_IRQn 1 */
/* USER CODE END USART1_IRQn 1 */
}
8000836: bf00 nop
8000838: bd80 pop {r7, pc}
800083a: bf00 nop
800083c: 20000054 .word 0x20000054
08000840 <SystemInit>:
* @brief Setup the microcontroller system
* @param None
* @retval None
*/
void SystemInit(void)
{
8000840: b480 push {r7}
8000842: af00 add r7, sp, #0
/* FPU settings --------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
8000844: 4b06 ldr r3, [pc, #24] ; (8000860 <SystemInit+0x20>)
8000846: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
800084a: 4a05 ldr r2, [pc, #20] ; (8000860 <SystemInit+0x20>)
800084c: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
8000850: f8c2 3088 str.w r3, [r2, #136] ; 0x88
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
}
8000854: bf00 nop
8000856: 46bd mov sp, r7
8000858: f85d 7b04 ldr.w r7, [sp], #4
800085c: 4770 bx lr
800085e: bf00 nop
8000860: e000ed00 .word 0xe000ed00
08000864 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* Atollic update: set stack pointer */
8000864: f8df d034 ldr.w sp, [pc, #52] ; 800089c <LoopForever+0x2>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
8000868: 480d ldr r0, [pc, #52] ; (80008a0 <LoopForever+0x6>)
ldr r1, =_edata
800086a: 490e ldr r1, [pc, #56] ; (80008a4 <LoopForever+0xa>)
ldr r2, =_sidata
800086c: 4a0e ldr r2, [pc, #56] ; (80008a8 <LoopForever+0xe>)
movs r3, #0
800086e: 2300 movs r3, #0
b LoopCopyDataInit
8000870: e002 b.n 8000878 <LoopCopyDataInit>
08000872 <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
8000872: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
8000874: 50c4 str r4, [r0, r3]
adds r3, r3, #4
8000876: 3304 adds r3, #4
08000878 <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
8000878: 18c4 adds r4, r0, r3
cmp r4, r1
800087a: 428c cmp r4, r1
bcc CopyDataInit
800087c: d3f9 bcc.n 8000872 <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
800087e: 4a0b ldr r2, [pc, #44] ; (80008ac <LoopForever+0x12>)
ldr r4, =_ebss
8000880: 4c0b ldr r4, [pc, #44] ; (80008b0 <LoopForever+0x16>)
movs r3, #0
8000882: 2300 movs r3, #0
b LoopFillZerobss
8000884: e001 b.n 800088a <LoopFillZerobss>
08000886 <FillZerobss>:
FillZerobss:
str r3, [r2]
8000886: 6013 str r3, [r2, #0]
adds r2, r2, #4
8000888: 3204 adds r2, #4
0800088a <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
800088a: 42a2 cmp r2, r4
bcc FillZerobss
800088c: d3fb bcc.n 8000886 <FillZerobss>
/* Call the clock system intitialization function.*/
bl SystemInit
800088e: f7ff ffd7 bl 8000840 <SystemInit>
/* Call static constructors */
bl __libc_init_array
8000892: f004 f86d bl 8004970 <__libc_init_array>
/* Call the application's entry point.*/
bl main
8000896: f7ff fd2d bl 80002f4 <main>
0800089a <LoopForever>:
LoopForever:
b LoopForever
800089a: e7fe b.n 800089a <LoopForever>
ldr sp, =_estack /* Atollic update: set stack pointer */
800089c: 20004000 .word 0x20004000
ldr r0, =_sdata
80008a0: 20000000 .word 0x20000000
ldr r1, =_edata
80008a4: 20000010 .word 0x20000010
ldr r2, =_sidata
80008a8: 08004a48 .word 0x08004a48
ldr r2, =_sbss
80008ac: 20000010 .word 0x20000010
ldr r4, =_ebss
80008b0: 20000150 .word 0x20000150
080008b4 <ADC1_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
80008b4: e7fe b.n 80008b4 <ADC1_IRQHandler>
...
080008b8 <HAL_Init>:
* In the default implementation,Systick is used as source of time base.
* The tick variable is incremented each 1ms in its ISR.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
80008b8: b580 push {r7, lr}
80008ba: af00 add r7, sp, #0
/* Configure Flash prefetch */
#if (PREFETCH_ENABLE != 0U)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
80008bc: 4b08 ldr r3, [pc, #32] ; (80008e0 <HAL_Init+0x28>)
80008be: 681b ldr r3, [r3, #0]
80008c0: 4a07 ldr r2, [pc, #28] ; (80008e0 <HAL_Init+0x28>)
80008c2: f043 0310 orr.w r3, r3, #16
80008c6: 6013 str r3, [r2, #0]
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
80008c8: 2003 movs r0, #3
80008ca: f000 ff91 bl 80017f0 <HAL_NVIC_SetPriorityGrouping>
/* Enable systick and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
80008ce: 2000 movs r0, #0
80008d0: f000 f808 bl 80008e4 <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
80008d4: f7ff fe9c bl 8000610 <HAL_MspInit>
/* Return function status */
return HAL_OK;
80008d8: 2300 movs r3, #0
}
80008da: 4618 mov r0, r3
80008dc: bd80 pop {r7, pc}
80008de: bf00 nop
80008e0: 40022000 .word 0x40022000
080008e4 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
80008e4: b580 push {r7, lr}
80008e6: b082 sub sp, #8
80008e8: af00 add r7, sp, #0
80008ea: 6078 str r0, [r7, #4]
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
80008ec: 4b12 ldr r3, [pc, #72] ; (8000938 <HAL_InitTick+0x54>)
80008ee: 681a ldr r2, [r3, #0]
80008f0: 4b12 ldr r3, [pc, #72] ; (800093c <HAL_InitTick+0x58>)
80008f2: 781b ldrb r3, [r3, #0]
80008f4: 4619 mov r1, r3
80008f6: f44f 737a mov.w r3, #1000 ; 0x3e8
80008fa: fbb3 f3f1 udiv r3, r3, r1
80008fe: fbb2 f3f3 udiv r3, r2, r3
8000902: 4618 mov r0, r3
8000904: f000 ffa9 bl 800185a <HAL_SYSTICK_Config>
8000908: 4603 mov r3, r0
800090a: 2b00 cmp r3, #0
800090c: d001 beq.n 8000912 <HAL_InitTick+0x2e>
{
return HAL_ERROR;
800090e: 2301 movs r3, #1
8000910: e00e b.n 8000930 <HAL_InitTick+0x4c>
}
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8000912: 687b ldr r3, [r7, #4]
8000914: 2b0f cmp r3, #15
8000916: d80a bhi.n 800092e <HAL_InitTick+0x4a>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
8000918: 2200 movs r2, #0
800091a: 6879 ldr r1, [r7, #4]
800091c: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
8000920: f000 ff71 bl 8001806 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8000924: 4a06 ldr r2, [pc, #24] ; (8000940 <HAL_InitTick+0x5c>)
8000926: 687b ldr r3, [r7, #4]
8000928: 6013 str r3, [r2, #0]
else
{
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
800092a: 2300 movs r3, #0
800092c: e000 b.n 8000930 <HAL_InitTick+0x4c>
return HAL_ERROR;
800092e: 2301 movs r3, #1
}
8000930: 4618 mov r0, r3
8000932: 3708 adds r7, #8
8000934: 46bd mov sp, r7
8000936: bd80 pop {r7, pc}
8000938: 20000004 .word 0x20000004
800093c: 2000000c .word 0x2000000c
8000940: 20000008 .word 0x20000008
08000944 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8000944: b480 push {r7}
8000946: af00 add r7, sp, #0
uwTick += uwTickFreq;
8000948: 4b06 ldr r3, [pc, #24] ; (8000964 <HAL_IncTick+0x20>)
800094a: 781b ldrb r3, [r3, #0]
800094c: 461a mov r2, r3
800094e: 4b06 ldr r3, [pc, #24] ; (8000968 <HAL_IncTick+0x24>)
8000950: 681b ldr r3, [r3, #0]
8000952: 4413 add r3, r2
8000954: 4a04 ldr r2, [pc, #16] ; (8000968 <HAL_IncTick+0x24>)
8000956: 6013 str r3, [r2, #0]
}
8000958: bf00 nop
800095a: 46bd mov sp, r7
800095c: f85d 7b04 ldr.w r7, [sp], #4
8000960: 4770 bx lr
8000962: bf00 nop
8000964: 2000000c .word 0x2000000c
8000968: 2000014c .word 0x2000014c
0800096c <HAL_GetTick>:
* @note The function is declared as __Weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
800096c: b480 push {r7}
800096e: af00 add r7, sp, #0
return uwTick;
8000970: 4b03 ldr r3, [pc, #12] ; (8000980 <HAL_GetTick+0x14>)
8000972: 681b ldr r3, [r3, #0]
}
8000974: 4618 mov r0, r3
8000976: 46bd mov sp, r7
8000978: f85d 7b04 ldr.w r7, [sp], #4
800097c: 4770 bx lr
800097e: bf00 nop
8000980: 2000014c .word 0x2000014c
08000984 <HAL_Delay>:
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
8000984: b580 push {r7, lr}
8000986: b084 sub sp, #16
8000988: af00 add r7, sp, #0
800098a: 6078 str r0, [r7, #4]
uint32_t tickstart = HAL_GetTick();
800098c: f7ff ffee bl 800096c <HAL_GetTick>
8000990: 60b8 str r0, [r7, #8]
uint32_t wait = Delay;
8000992: 687b ldr r3, [r7, #4]
8000994: 60fb str r3, [r7, #12]
/* Add freq to guarantee minimum wait */
if (wait < HAL_MAX_DELAY)
8000996: 68fb ldr r3, [r7, #12]
8000998: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
800099c: d005 beq.n 80009aa <HAL_Delay+0x26>
{
wait += (uint32_t)(uwTickFreq);
800099e: 4b0a ldr r3, [pc, #40] ; (80009c8 <HAL_Delay+0x44>)
80009a0: 781b ldrb r3, [r3, #0]
80009a2: 461a mov r2, r3
80009a4: 68fb ldr r3, [r7, #12]
80009a6: 4413 add r3, r2
80009a8: 60fb str r3, [r7, #12]
}
while((HAL_GetTick() - tickstart) < wait)
80009aa: bf00 nop
80009ac: f7ff ffde bl 800096c <HAL_GetTick>
80009b0: 4602 mov r2, r0
80009b2: 68bb ldr r3, [r7, #8]
80009b4: 1ad3 subs r3, r2, r3
80009b6: 68fa ldr r2, [r7, #12]
80009b8: 429a cmp r2, r3
80009ba: d8f7 bhi.n 80009ac <HAL_Delay+0x28>
{
}
}
80009bc: bf00 nop
80009be: bf00 nop
80009c0: 3710 adds r7, #16
80009c2: 46bd mov sp, r7
80009c4: bd80 pop {r7, pc}
80009c6: bf00 nop
80009c8: 2000000c .word 0x2000000c
080009cc <HAL_CAN_Init>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan)
{
80009cc: b580 push {r7, lr}
80009ce: b084 sub sp, #16
80009d0: af00 add r7, sp, #0
80009d2: 6078 str r0, [r7, #4]
uint32_t tickstart;
/* Check CAN handle */
if (hcan == NULL)
80009d4: 687b ldr r3, [r7, #4]
80009d6: 2b00 cmp r3, #0
80009d8: d101 bne.n 80009de <HAL_CAN_Init+0x12>
{
return HAL_ERROR;
80009da: 2301 movs r3, #1
80009dc: e0ed b.n 8000bba <HAL_CAN_Init+0x1ee>
/* Init the low level hardware: CLOCK, NVIC */
hcan->MspInitCallback(hcan);
}
#else
if (hcan->State == HAL_CAN_STATE_RESET)
80009de: 687b ldr r3, [r7, #4]
80009e0: f893 3020 ldrb.w r3, [r3, #32]
80009e4: b2db uxtb r3, r3
80009e6: 2b00 cmp r3, #0
80009e8: d102 bne.n 80009f0 <HAL_CAN_Init+0x24>
{
/* Init the low level hardware: CLOCK, NVIC */
HAL_CAN_MspInit(hcan);
80009ea: 6878 ldr r0, [r7, #4]
80009ec: f7ff fe34 bl 8000658 <HAL_CAN_MspInit>
}
#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
/* Request initialisation */
SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
80009f0: 687b ldr r3, [r7, #4]
80009f2: 681b ldr r3, [r3, #0]
80009f4: 681a ldr r2, [r3, #0]
80009f6: 687b ldr r3, [r7, #4]
80009f8: 681b ldr r3, [r3, #0]
80009fa: f042 0201 orr.w r2, r2, #1
80009fe: 601a str r2, [r3, #0]
/* Get tick */
tickstart = HAL_GetTick();
8000a00: f7ff ffb4 bl 800096c <HAL_GetTick>
8000a04: 60f8 str r0, [r7, #12]
/* Wait initialisation acknowledge */
while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U)
8000a06: e012 b.n 8000a2e <HAL_CAN_Init+0x62>
{
if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
8000a08: f7ff ffb0 bl 800096c <HAL_GetTick>
8000a0c: 4602 mov r2, r0
8000a0e: 68fb ldr r3, [r7, #12]
8000a10: 1ad3 subs r3, r2, r3
8000a12: 2b0a cmp r3, #10
8000a14: d90b bls.n 8000a2e <HAL_CAN_Init+0x62>
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
8000a16: 687b ldr r3, [r7, #4]
8000a18: 6a5b ldr r3, [r3, #36] ; 0x24
8000a1a: f443 3200 orr.w r2, r3, #131072 ; 0x20000
8000a1e: 687b ldr r3, [r7, #4]
8000a20: 625a str r2, [r3, #36] ; 0x24
/* Change CAN state */
hcan->State = HAL_CAN_STATE_ERROR;
8000a22: 687b ldr r3, [r7, #4]
8000a24: 2205 movs r2, #5
8000a26: f883 2020 strb.w r2, [r3, #32]
return HAL_ERROR;
8000a2a: 2301 movs r3, #1
8000a2c: e0c5 b.n 8000bba <HAL_CAN_Init+0x1ee>
while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U)
8000a2e: 687b ldr r3, [r7, #4]
8000a30: 681b ldr r3, [r3, #0]
8000a32: 685b ldr r3, [r3, #4]
8000a34: f003 0301 and.w r3, r3, #1
8000a38: 2b00 cmp r3, #0
8000a3a: d0e5 beq.n 8000a08 <HAL_CAN_Init+0x3c>
}
}
/* Exit from sleep mode */
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
8000a3c: 687b ldr r3, [r7, #4]
8000a3e: 681b ldr r3, [r3, #0]
8000a40: 681a ldr r2, [r3, #0]
8000a42: 687b ldr r3, [r7, #4]
8000a44: 681b ldr r3, [r3, #0]
8000a46: f022 0202 bic.w r2, r2, #2
8000a4a: 601a str r2, [r3, #0]
/* Get tick */
tickstart = HAL_GetTick();
8000a4c: f7ff ff8e bl 800096c <HAL_GetTick>
8000a50: 60f8 str r0, [r7, #12]
/* Check Sleep mode leave acknowledge */
while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
8000a52: e012 b.n 8000a7a <HAL_CAN_Init+0xae>
{
if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
8000a54: f7ff ff8a bl 800096c <HAL_GetTick>
8000a58: 4602 mov r2, r0
8000a5a: 68fb ldr r3, [r7, #12]
8000a5c: 1ad3 subs r3, r2, r3
8000a5e: 2b0a cmp r3, #10
8000a60: d90b bls.n 8000a7a <HAL_CAN_Init+0xae>
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
8000a62: 687b ldr r3, [r7, #4]
8000a64: 6a5b ldr r3, [r3, #36] ; 0x24
8000a66: f443 3200 orr.w r2, r3, #131072 ; 0x20000
8000a6a: 687b ldr r3, [r7, #4]
8000a6c: 625a str r2, [r3, #36] ; 0x24
/* Change CAN state */
hcan->State = HAL_CAN_STATE_ERROR;
8000a6e: 687b ldr r3, [r7, #4]
8000a70: 2205 movs r2, #5
8000a72: f883 2020 strb.w r2, [r3, #32]
return HAL_ERROR;
8000a76: 2301 movs r3, #1
8000a78: e09f b.n 8000bba <HAL_CAN_Init+0x1ee>
while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
8000a7a: 687b ldr r3, [r7, #4]
8000a7c: 681b ldr r3, [r3, #0]
8000a7e: 685b ldr r3, [r3, #4]
8000a80: f003 0302 and.w r3, r3, #2
8000a84: 2b00 cmp r3, #0
8000a86: d1e5 bne.n 8000a54 <HAL_CAN_Init+0x88>
}
}
/* Set the time triggered communication mode */
if (hcan->Init.TimeTriggeredMode == ENABLE)
8000a88: 687b ldr r3, [r7, #4]
8000a8a: 7e1b ldrb r3, [r3, #24]
8000a8c: 2b01 cmp r3, #1
8000a8e: d108 bne.n 8000aa2 <HAL_CAN_Init+0xd6>
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
8000a90: 687b ldr r3, [r7, #4]
8000a92: 681b ldr r3, [r3, #0]
8000a94: 681a ldr r2, [r3, #0]
8000a96: 687b ldr r3, [r7, #4]
8000a98: 681b ldr r3, [r3, #0]
8000a9a: f042 0280 orr.w r2, r2, #128 ; 0x80
8000a9e: 601a str r2, [r3, #0]
8000aa0: e007 b.n 8000ab2 <HAL_CAN_Init+0xe6>
}
else
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
8000aa2: 687b ldr r3, [r7, #4]
8000aa4: 681b ldr r3, [r3, #0]
8000aa6: 681a ldr r2, [r3, #0]
8000aa8: 687b ldr r3, [r7, #4]
8000aaa: 681b ldr r3, [r3, #0]
8000aac: f022 0280 bic.w r2, r2, #128 ; 0x80
8000ab0: 601a str r2, [r3, #0]
}
/* Set the automatic bus-off management */
if (hcan->Init.AutoBusOff == ENABLE)
8000ab2: 687b ldr r3, [r7, #4]
8000ab4: 7e5b ldrb r3, [r3, #25]
8000ab6: 2b01 cmp r3, #1
8000ab8: d108 bne.n 8000acc <HAL_CAN_Init+0x100>
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
8000aba: 687b ldr r3, [r7, #4]
8000abc: 681b ldr r3, [r3, #0]
8000abe: 681a ldr r2, [r3, #0]
8000ac0: 687b ldr r3, [r7, #4]
8000ac2: 681b ldr r3, [r3, #0]
8000ac4: f042 0240 orr.w r2, r2, #64 ; 0x40
8000ac8: 601a str r2, [r3, #0]
8000aca: e007 b.n 8000adc <HAL_CAN_Init+0x110>
}
else
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
8000acc: 687b ldr r3, [r7, #4]
8000ace: 681b ldr r3, [r3, #0]
8000ad0: 681a ldr r2, [r3, #0]
8000ad2: 687b ldr r3, [r7, #4]
8000ad4: 681b ldr r3, [r3, #0]
8000ad6: f022 0240 bic.w r2, r2, #64 ; 0x40
8000ada: 601a str r2, [r3, #0]
}
/* Set the automatic wake-up mode */
if (hcan->Init.AutoWakeUp == ENABLE)
8000adc: 687b ldr r3, [r7, #4]
8000ade: 7e9b ldrb r3, [r3, #26]
8000ae0: 2b01 cmp r3, #1
8000ae2: d108 bne.n 8000af6 <HAL_CAN_Init+0x12a>
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
8000ae4: 687b ldr r3, [r7, #4]
8000ae6: 681b ldr r3, [r3, #0]
8000ae8: 681a ldr r2, [r3, #0]
8000aea: 687b ldr r3, [r7, #4]
8000aec: 681b ldr r3, [r3, #0]
8000aee: f042 0220 orr.w r2, r2, #32
8000af2: 601a str r2, [r3, #0]
8000af4: e007 b.n 8000b06 <HAL_CAN_Init+0x13a>
}
else
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
8000af6: 687b ldr r3, [r7, #4]
8000af8: 681b ldr r3, [r3, #0]
8000afa: 681a ldr r2, [r3, #0]
8000afc: 687b ldr r3, [r7, #4]
8000afe: 681b ldr r3, [r3, #0]
8000b00: f022 0220 bic.w r2, r2, #32
8000b04: 601a str r2, [r3, #0]
}
/* Set the automatic retransmission */
if (hcan->Init.AutoRetransmission == ENABLE)
8000b06: 687b ldr r3, [r7, #4]
8000b08: 7edb ldrb r3, [r3, #27]
8000b0a: 2b01 cmp r3, #1
8000b0c: d108 bne.n 8000b20 <HAL_CAN_Init+0x154>
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART);
8000b0e: 687b ldr r3, [r7, #4]
8000b10: 681b ldr r3, [r3, #0]
8000b12: 681a ldr r2, [r3, #0]
8000b14: 687b ldr r3, [r7, #4]
8000b16: 681b ldr r3, [r3, #0]
8000b18: f022 0210 bic.w r2, r2, #16
8000b1c: 601a str r2, [r3, #0]
8000b1e: e007 b.n 8000b30 <HAL_CAN_Init+0x164>
}
else
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_NART);
8000b20: 687b ldr r3, [r7, #4]
8000b22: 681b ldr r3, [r3, #0]
8000b24: 681a ldr r2, [r3, #0]
8000b26: 687b ldr r3, [r7, #4]
8000b28: 681b ldr r3, [r3, #0]
8000b2a: f042 0210 orr.w r2, r2, #16
8000b2e: 601a str r2, [r3, #0]
}
/* Set the receive FIFO locked mode */
if (hcan->Init.ReceiveFifoLocked == ENABLE)
8000b30: 687b ldr r3, [r7, #4]
8000b32: 7f1b ldrb r3, [r3, #28]
8000b34: 2b01 cmp r3, #1
8000b36: d108 bne.n 8000b4a <HAL_CAN_Init+0x17e>
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
8000b38: 687b ldr r3, [r7, #4]
8000b3a: 681b ldr r3, [r3, #0]
8000b3c: 681a ldr r2, [r3, #0]
8000b3e: 687b ldr r3, [r7, #4]
8000b40: 681b ldr r3, [r3, #0]
8000b42: f042 0208 orr.w r2, r2, #8
8000b46: 601a str r2, [r3, #0]
8000b48: e007 b.n 8000b5a <HAL_CAN_Init+0x18e>
}
else
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
8000b4a: 687b ldr r3, [r7, #4]
8000b4c: 681b ldr r3, [r3, #0]
8000b4e: 681a ldr r2, [r3, #0]
8000b50: 687b ldr r3, [r7, #4]
8000b52: 681b ldr r3, [r3, #0]
8000b54: f022 0208 bic.w r2, r2, #8
8000b58: 601a str r2, [r3, #0]
}
/* Set the transmit FIFO priority */
if (hcan->Init.TransmitFifoPriority == ENABLE)
8000b5a: 687b ldr r3, [r7, #4]
8000b5c: 7f5b ldrb r3, [r3, #29]
8000b5e: 2b01 cmp r3, #1
8000b60: d108 bne.n 8000b74 <HAL_CAN_Init+0x1a8>
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
8000b62: 687b ldr r3, [r7, #4]
8000b64: 681b ldr r3, [r3, #0]
8000b66: 681a ldr r2, [r3, #0]
8000b68: 687b ldr r3, [r7, #4]
8000b6a: 681b ldr r3, [r3, #0]
8000b6c: f042 0204 orr.w r2, r2, #4
8000b70: 601a str r2, [r3, #0]
8000b72: e007 b.n 8000b84 <HAL_CAN_Init+0x1b8>
}
else
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
8000b74: 687b ldr r3, [r7, #4]
8000b76: 681b ldr r3, [r3, #0]
8000b78: 681a ldr r2, [r3, #0]
8000b7a: 687b ldr r3, [r7, #4]
8000b7c: 681b ldr r3, [r3, #0]
8000b7e: f022 0204 bic.w r2, r2, #4
8000b82: 601a str r2, [r3, #0]
}
/* Set the bit timing register */
WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode |
8000b84: 687b ldr r3, [r7, #4]
8000b86: 689a ldr r2, [r3, #8]
8000b88: 687b ldr r3, [r7, #4]
8000b8a: 68db ldr r3, [r3, #12]
8000b8c: 431a orrs r2, r3
8000b8e: 687b ldr r3, [r7, #4]
8000b90: 691b ldr r3, [r3, #16]
8000b92: 431a orrs r2, r3
8000b94: 687b ldr r3, [r7, #4]
8000b96: 695b ldr r3, [r3, #20]
8000b98: ea42 0103 orr.w r1, r2, r3
8000b9c: 687b ldr r3, [r7, #4]
8000b9e: 685b ldr r3, [r3, #4]
8000ba0: 1e5a subs r2, r3, #1
8000ba2: 687b ldr r3, [r7, #4]
8000ba4: 681b ldr r3, [r3, #0]
8000ba6: 430a orrs r2, r1
8000ba8: 61da str r2, [r3, #28]
hcan->Init.TimeSeg1 |
hcan->Init.TimeSeg2 |
(hcan->Init.Prescaler - 1U)));
/* Initialize the error code */
hcan->ErrorCode = HAL_CAN_ERROR_NONE;
8000baa: 687b ldr r3, [r7, #4]
8000bac: 2200 movs r2, #0
8000bae: 625a str r2, [r3, #36] ; 0x24
/* Initialize the CAN state */
hcan->State = HAL_CAN_STATE_READY;
8000bb0: 687b ldr r3, [r7, #4]
8000bb2: 2201 movs r2, #1
8000bb4: f883 2020 strb.w r2, [r3, #32]
/* Return function status */
return HAL_OK;
8000bb8: 2300 movs r3, #0
}
8000bba: 4618 mov r0, r3
8000bbc: 3710 adds r7, #16
8000bbe: 46bd mov sp, r7
8000bc0: bd80 pop {r7, pc}
08000bc2 <HAL_CAN_ConfigFilter>:
* @param sFilterConfig pointer to a CAN_FilterTypeDef structure that
* contains the filter configuration information.
* @retval None
*/
HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig)
{
8000bc2: b480 push {r7}
8000bc4: b087 sub sp, #28
8000bc6: af00 add r7, sp, #0
8000bc8: 6078 str r0, [r7, #4]
8000bca: 6039 str r1, [r7, #0]
uint32_t filternbrbitpos;
CAN_TypeDef *can_ip = hcan->Instance;
8000bcc: 687b ldr r3, [r7, #4]
8000bce: 681b ldr r3, [r3, #0]
8000bd0: 617b str r3, [r7, #20]
HAL_CAN_StateTypeDef state = hcan->State;
8000bd2: 687b ldr r3, [r7, #4]
8000bd4: f893 3020 ldrb.w r3, [r3, #32]
8000bd8: 74fb strb r3, [r7, #19]
if ((state == HAL_CAN_STATE_READY) ||
8000bda: 7cfb ldrb r3, [r7, #19]
8000bdc: 2b01 cmp r3, #1
8000bde: d003 beq.n 8000be8 <HAL_CAN_ConfigFilter+0x26>
8000be0: 7cfb ldrb r3, [r7, #19]
8000be2: 2b02 cmp r3, #2
8000be4: f040 80aa bne.w 8000d3c <HAL_CAN_ConfigFilter+0x17a>
/* Check the parameters */
assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank));
/* Initialisation mode for the filter */
SET_BIT(can_ip->FMR, CAN_FMR_FINIT);
8000be8: 697b ldr r3, [r7, #20]
8000bea: f8d3 3200 ldr.w r3, [r3, #512] ; 0x200
8000bee: f043 0201 orr.w r2, r3, #1
8000bf2: 697b ldr r3, [r7, #20]
8000bf4: f8c3 2200 str.w r2, [r3, #512] ; 0x200
/* Convert filter number into bit position */
filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU);
8000bf8: 683b ldr r3, [r7, #0]
8000bfa: 695b ldr r3, [r3, #20]
8000bfc: f003 031f and.w r3, r3, #31
8000c00: 2201 movs r2, #1
8000c02: fa02 f303 lsl.w r3, r2, r3
8000c06: 60fb str r3, [r7, #12]
/* Filter Deactivation */
CLEAR_BIT(can_ip->FA1R, filternbrbitpos);
8000c08: 697b ldr r3, [r7, #20]
8000c0a: f8d3 221c ldr.w r2, [r3, #540] ; 0x21c
8000c0e: 68fb ldr r3, [r7, #12]
8000c10: 43db mvns r3, r3
8000c12: 401a ands r2, r3
8000c14: 697b ldr r3, [r7, #20]
8000c16: f8c3 221c str.w r2, [r3, #540] ; 0x21c
/* Filter Scale */
if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
8000c1a: 683b ldr r3, [r7, #0]
8000c1c: 69db ldr r3, [r3, #28]
8000c1e: 2b00 cmp r3, #0
8000c20: d123 bne.n 8000c6a <HAL_CAN_ConfigFilter+0xa8>
{
/* 16-bit scale for the filter */
CLEAR_BIT(can_ip->FS1R, filternbrbitpos);
8000c22: 697b ldr r3, [r7, #20]
8000c24: f8d3 220c ldr.w r2, [r3, #524] ; 0x20c
8000c28: 68fb ldr r3, [r7, #12]
8000c2a: 43db mvns r3, r3
8000c2c: 401a ands r2, r3
8000c2e: 697b ldr r3, [r7, #20]
8000c30: f8c3 220c str.w r2, [r3, #524] ; 0x20c
/* First 16-bit identifier and First 16-bit mask */
/* Or First 16-bit identifier and Second 16-bit identifier */
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
8000c34: 683b ldr r3, [r7, #0]
8000c36: 68db ldr r3, [r3, #12]
8000c38: 0419 lsls r1, r3, #16
(0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
8000c3a: 683b ldr r3, [r7, #0]
8000c3c: 685b ldr r3, [r3, #4]
8000c3e: b29b uxth r3, r3
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
8000c40: 683a ldr r2, [r7, #0]
8000c42: 6952 ldr r2, [r2, #20]
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
8000c44: 4319 orrs r1, r3
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
8000c46: 697b ldr r3, [r7, #20]
8000c48: 3248 adds r2, #72 ; 0x48
8000c4a: f843 1032 str.w r1, [r3, r2, lsl #3]
/* Second 16-bit identifier and Second 16-bit mask */
/* Or Third 16-bit identifier and Fourth 16-bit identifier */
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
8000c4e: 683b ldr r3, [r7, #0]
8000c50: 689b ldr r3, [r3, #8]
8000c52: 0419 lsls r1, r3, #16
(0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh);
8000c54: 683b ldr r3, [r7, #0]
8000c56: 681b ldr r3, [r3, #0]
8000c58: b29a uxth r2, r3
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
8000c5a: 683b ldr r3, [r7, #0]
8000c5c: 695b ldr r3, [r3, #20]
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
8000c5e: 430a orrs r2, r1
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
8000c60: 6979 ldr r1, [r7, #20]
8000c62: 3348 adds r3, #72 ; 0x48
8000c64: 00db lsls r3, r3, #3
8000c66: 440b add r3, r1
8000c68: 605a str r2, [r3, #4]
}
if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
8000c6a: 683b ldr r3, [r7, #0]
8000c6c: 69db ldr r3, [r3, #28]
8000c6e: 2b01 cmp r3, #1
8000c70: d122 bne.n 8000cb8 <HAL_CAN_ConfigFilter+0xf6>
{
/* 32-bit scale for the filter */
SET_BIT(can_ip->FS1R, filternbrbitpos);
8000c72: 697b ldr r3, [r7, #20]
8000c74: f8d3 220c ldr.w r2, [r3, #524] ; 0x20c
8000c78: 68fb ldr r3, [r7, #12]
8000c7a: 431a orrs r2, r3
8000c7c: 697b ldr r3, [r7, #20]
8000c7e: f8c3 220c str.w r2, [r3, #524] ; 0x20c
/* 32-bit identifier or First 32-bit identifier */
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
8000c82: 683b ldr r3, [r7, #0]
8000c84: 681b ldr r3, [r3, #0]
8000c86: 0419 lsls r1, r3, #16
(0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
8000c88: 683b ldr r3, [r7, #0]
8000c8a: 685b ldr r3, [r3, #4]
8000c8c: b29b uxth r3, r3
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
8000c8e: 683a ldr r2, [r7, #0]
8000c90: 6952 ldr r2, [r2, #20]
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
8000c92: 4319 orrs r1, r3
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
8000c94: 697b ldr r3, [r7, #20]
8000c96: 3248 adds r2, #72 ; 0x48
8000c98: f843 1032 str.w r1, [r3, r2, lsl #3]
/* 32-bit mask or Second 32-bit identifier */
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
8000c9c: 683b ldr r3, [r7, #0]
8000c9e: 689b ldr r3, [r3, #8]
8000ca0: 0419 lsls r1, r3, #16
(0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow);
8000ca2: 683b ldr r3, [r7, #0]
8000ca4: 68db ldr r3, [r3, #12]
8000ca6: b29a uxth r2, r3
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
8000ca8: 683b ldr r3, [r7, #0]
8000caa: 695b ldr r3, [r3, #20]
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
8000cac: 430a orrs r2, r1
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
8000cae: 6979 ldr r1, [r7, #20]
8000cb0: 3348 adds r3, #72 ; 0x48
8000cb2: 00db lsls r3, r3, #3
8000cb4: 440b add r3, r1
8000cb6: 605a str r2, [r3, #4]
}
/* Filter Mode */
if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
8000cb8: 683b ldr r3, [r7, #0]
8000cba: 699b ldr r3, [r3, #24]
8000cbc: 2b00 cmp r3, #0
8000cbe: d109 bne.n 8000cd4 <HAL_CAN_ConfigFilter+0x112>
{
/* Id/Mask mode for the filter*/
CLEAR_BIT(can_ip->FM1R, filternbrbitpos);
8000cc0: 697b ldr r3, [r7, #20]
8000cc2: f8d3 2204 ldr.w r2, [r3, #516] ; 0x204
8000cc6: 68fb ldr r3, [r7, #12]
8000cc8: 43db mvns r3, r3
8000cca: 401a ands r2, r3
8000ccc: 697b ldr r3, [r7, #20]
8000cce: f8c3 2204 str.w r2, [r3, #516] ; 0x204
8000cd2: e007 b.n 8000ce4 <HAL_CAN_ConfigFilter+0x122>
}
else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
{
/* Identifier list mode for the filter*/
SET_BIT(can_ip->FM1R, filternbrbitpos);
8000cd4: 697b ldr r3, [r7, #20]
8000cd6: f8d3 2204 ldr.w r2, [r3, #516] ; 0x204
8000cda: 68fb ldr r3, [r7, #12]
8000cdc: 431a orrs r2, r3
8000cde: 697b ldr r3, [r7, #20]
8000ce0: f8c3 2204 str.w r2, [r3, #516] ; 0x204
}
/* Filter FIFO assignment */
if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
8000ce4: 683b ldr r3, [r7, #0]
8000ce6: 691b ldr r3, [r3, #16]
8000ce8: 2b00 cmp r3, #0
8000cea: d109 bne.n 8000d00 <HAL_CAN_ConfigFilter+0x13e>
{
/* FIFO 0 assignation for the filter */
CLEAR_BIT(can_ip->FFA1R, filternbrbitpos);
8000cec: 697b ldr r3, [r7, #20]
8000cee: f8d3 2214 ldr.w r2, [r3, #532] ; 0x214
8000cf2: 68fb ldr r3, [r7, #12]
8000cf4: 43db mvns r3, r3
8000cf6: 401a ands r2, r3
8000cf8: 697b ldr r3, [r7, #20]
8000cfa: f8c3 2214 str.w r2, [r3, #532] ; 0x214
8000cfe: e007 b.n 8000d10 <HAL_CAN_ConfigFilter+0x14e>
}
else
{
/* FIFO 1 assignation for the filter */
SET_BIT(can_ip->FFA1R, filternbrbitpos);
8000d00: 697b ldr r3, [r7, #20]
8000d02: f8d3 2214 ldr.w r2, [r3, #532] ; 0x214
8000d06: 68fb ldr r3, [r7, #12]
8000d08: 431a orrs r2, r3
8000d0a: 697b ldr r3, [r7, #20]
8000d0c: f8c3 2214 str.w r2, [r3, #532] ; 0x214
}
/* Filter activation */
if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE)
8000d10: 683b ldr r3, [r7, #0]
8000d12: 6a1b ldr r3, [r3, #32]
8000d14: 2b01 cmp r3, #1
8000d16: d107 bne.n 8000d28 <HAL_CAN_ConfigFilter+0x166>
{
SET_BIT(can_ip->FA1R, filternbrbitpos);
8000d18: 697b ldr r3, [r7, #20]
8000d1a: f8d3 221c ldr.w r2, [r3, #540] ; 0x21c
8000d1e: 68fb ldr r3, [r7, #12]
8000d20: 431a orrs r2, r3
8000d22: 697b ldr r3, [r7, #20]
8000d24: f8c3 221c str.w r2, [r3, #540] ; 0x21c
}
/* Leave the initialisation mode for the filter */
CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT);
8000d28: 697b ldr r3, [r7, #20]
8000d2a: f8d3 3200 ldr.w r3, [r3, #512] ; 0x200
8000d2e: f023 0201 bic.w r2, r3, #1
8000d32: 697b ldr r3, [r7, #20]
8000d34: f8c3 2200 str.w r2, [r3, #512] ; 0x200
/* Return function status */
return HAL_OK;
8000d38: 2300 movs r3, #0
8000d3a: e006 b.n 8000d4a <HAL_CAN_ConfigFilter+0x188>
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
8000d3c: 687b ldr r3, [r7, #4]
8000d3e: 6a5b ldr r3, [r3, #36] ; 0x24
8000d40: f443 2280 orr.w r2, r3, #262144 ; 0x40000
8000d44: 687b ldr r3, [r7, #4]
8000d46: 625a str r2, [r3, #36] ; 0x24
return HAL_ERROR;
8000d48: 2301 movs r3, #1
}
}
8000d4a: 4618 mov r0, r3
8000d4c: 371c adds r7, #28
8000d4e: 46bd mov sp, r7
8000d50: f85d 7b04 ldr.w r7, [sp], #4
8000d54: 4770 bx lr
08000d56 <HAL_CAN_Start>:
* @param hcan pointer to an CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan)
{
8000d56: b580 push {r7, lr}
8000d58: b084 sub sp, #16
8000d5a: af00 add r7, sp, #0
8000d5c: 6078 str r0, [r7, #4]
uint32_t tickstart;
if (hcan->State == HAL_CAN_STATE_READY)
8000d5e: 687b ldr r3, [r7, #4]
8000d60: f893 3020 ldrb.w r3, [r3, #32]
8000d64: b2db uxtb r3, r3
8000d66: 2b01 cmp r3, #1
8000d68: d12e bne.n 8000dc8 <HAL_CAN_Start+0x72>
{
/* Change CAN peripheral state */
hcan->State = HAL_CAN_STATE_LISTENING;
8000d6a: 687b ldr r3, [r7, #4]
8000d6c: 2202 movs r2, #2
8000d6e: f883 2020 strb.w r2, [r3, #32]
/* Request leave initialisation */
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
8000d72: 687b ldr r3, [r7, #4]
8000d74: 681b ldr r3, [r3, #0]
8000d76: 681a ldr r2, [r3, #0]
8000d78: 687b ldr r3, [r7, #4]
8000d7a: 681b ldr r3, [r3, #0]
8000d7c: f022 0201 bic.w r2, r2, #1
8000d80: 601a str r2, [r3, #0]
/* Get tick */
tickstart = HAL_GetTick();
8000d82: f7ff fdf3 bl 800096c <HAL_GetTick>
8000d86: 60f8 str r0, [r7, #12]
/* Wait the acknowledge */
while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U)
8000d88: e012 b.n 8000db0 <HAL_CAN_Start+0x5a>
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
8000d8a: f7ff fdef bl 800096c <HAL_GetTick>
8000d8e: 4602 mov r2, r0
8000d90: 68fb ldr r3, [r7, #12]
8000d92: 1ad3 subs r3, r2, r3
8000d94: 2b0a cmp r3, #10
8000d96: d90b bls.n 8000db0 <HAL_CAN_Start+0x5a>
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
8000d98: 687b ldr r3, [r7, #4]
8000d9a: 6a5b ldr r3, [r3, #36] ; 0x24
8000d9c: f443 3200 orr.w r2, r3, #131072 ; 0x20000
8000da0: 687b ldr r3, [r7, #4]
8000da2: 625a str r2, [r3, #36] ; 0x24
/* Change CAN state */
hcan->State = HAL_CAN_STATE_ERROR;
8000da4: 687b ldr r3, [r7, #4]
8000da6: 2205 movs r2, #5
8000da8: f883 2020 strb.w r2, [r3, #32]
return HAL_ERROR;
8000dac: 2301 movs r3, #1
8000dae: e012 b.n 8000dd6 <HAL_CAN_Start+0x80>
while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U)
8000db0: 687b ldr r3, [r7, #4]
8000db2: 681b ldr r3, [r3, #0]
8000db4: 685b ldr r3, [r3, #4]
8000db6: f003 0301 and.w r3, r3, #1
8000dba: 2b00 cmp r3, #0
8000dbc: d1e5 bne.n 8000d8a <HAL_CAN_Start+0x34>
}
}
/* Reset the CAN ErrorCode */
hcan->ErrorCode = HAL_CAN_ERROR_NONE;
8000dbe: 687b ldr r3, [r7, #4]
8000dc0: 2200 movs r2, #0
8000dc2: 625a str r2, [r3, #36] ; 0x24
/* Return function status */
return HAL_OK;
8000dc4: 2300 movs r3, #0
8000dc6: e006 b.n 8000dd6 <HAL_CAN_Start+0x80>
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY;
8000dc8: 687b ldr r3, [r7, #4]
8000dca: 6a5b ldr r3, [r3, #36] ; 0x24
8000dcc: f443 2200 orr.w r2, r3, #524288 ; 0x80000
8000dd0: 687b ldr r3, [r7, #4]
8000dd2: 625a str r2, [r3, #36] ; 0x24
return HAL_ERROR;
8000dd4: 2301 movs r3, #1
}
}
8000dd6: 4618 mov r0, r3
8000dd8: 3710 adds r7, #16
8000dda: 46bd mov sp, r7
8000ddc: bd80 pop {r7, pc}
08000dde <HAL_CAN_AddTxMessage>:
* the TxMailbox used to store the Tx message.
* This parameter can be a value of @arg CAN_Tx_Mailboxes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox)
{
8000dde: b480 push {r7}
8000de0: b089 sub sp, #36 ; 0x24
8000de2: af00 add r7, sp, #0
8000de4: 60f8 str r0, [r7, #12]
8000de6: 60b9 str r1, [r7, #8]
8000de8: 607a str r2, [r7, #4]
8000dea: 603b str r3, [r7, #0]
uint32_t transmitmailbox;
HAL_CAN_StateTypeDef state = hcan->State;
8000dec: 68fb ldr r3, [r7, #12]
8000dee: f893 3020 ldrb.w r3, [r3, #32]
8000df2: 77fb strb r3, [r7, #31]
uint32_t tsr = READ_REG(hcan->Instance->TSR);
8000df4: 68fb ldr r3, [r7, #12]
8000df6: 681b ldr r3, [r3, #0]
8000df8: 689b ldr r3, [r3, #8]
8000dfa: 61bb str r3, [r7, #24]
{
assert_param(IS_CAN_EXTID(pHeader->ExtId));
}
assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime));
if ((state == HAL_CAN_STATE_READY) ||
8000dfc: 7ffb ldrb r3, [r7, #31]
8000dfe: 2b01 cmp r3, #1
8000e00: d003 beq.n 8000e0a <HAL_CAN_AddTxMessage+0x2c>
8000e02: 7ffb ldrb r3, [r7, #31]
8000e04: 2b02 cmp r3, #2
8000e06: f040 80b8 bne.w 8000f7a <HAL_CAN_AddTxMessage+0x19c>
(state == HAL_CAN_STATE_LISTENING))
{
/* Check that all the Tx mailboxes are not full */
if (((tsr & CAN_TSR_TME0) != 0U) ||
8000e0a: 69bb ldr r3, [r7, #24]
8000e0c: f003 6380 and.w r3, r3, #67108864 ; 0x4000000
8000e10: 2b00 cmp r3, #0
8000e12: d10a bne.n 8000e2a <HAL_CAN_AddTxMessage+0x4c>
((tsr & CAN_TSR_TME1) != 0U) ||
8000e14: 69bb ldr r3, [r7, #24]
8000e16: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
if (((tsr & CAN_TSR_TME0) != 0U) ||
8000e1a: 2b00 cmp r3, #0
8000e1c: d105 bne.n 8000e2a <HAL_CAN_AddTxMessage+0x4c>
((tsr & CAN_TSR_TME2) != 0U))
8000e1e: 69bb ldr r3, [r7, #24]
8000e20: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
((tsr & CAN_TSR_TME1) != 0U) ||
8000e24: 2b00 cmp r3, #0
8000e26: f000 80a0 beq.w 8000f6a <HAL_CAN_AddTxMessage+0x18c>
{
/* Select an empty transmit mailbox */
transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos;
8000e2a: 69bb ldr r3, [r7, #24]
8000e2c: 0e1b lsrs r3, r3, #24
8000e2e: f003 0303 and.w r3, r3, #3
8000e32: 617b str r3, [r7, #20]
/* Check transmit mailbox value */
if (transmitmailbox > 2U)
8000e34: 697b ldr r3, [r7, #20]
8000e36: 2b02 cmp r3, #2
8000e38: d907 bls.n 8000e4a <HAL_CAN_AddTxMessage+0x6c>
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_INTERNAL;
8000e3a: 68fb ldr r3, [r7, #12]
8000e3c: 6a5b ldr r3, [r3, #36] ; 0x24
8000e3e: f443 0200 orr.w r2, r3, #8388608 ; 0x800000
8000e42: 68fb ldr r3, [r7, #12]
8000e44: 625a str r2, [r3, #36] ; 0x24
return HAL_ERROR;
8000e46: 2301 movs r3, #1
8000e48: e09e b.n 8000f88 <HAL_CAN_AddTxMessage+0x1aa>
}
/* Store the Tx mailbox */
*pTxMailbox = (uint32_t)1 << transmitmailbox;
8000e4a: 2201 movs r2, #1
8000e4c: 697b ldr r3, [r7, #20]
8000e4e: 409a lsls r2, r3
8000e50: 683b ldr r3, [r7, #0]
8000e52: 601a str r2, [r3, #0]
/* Set up the Id */
if (pHeader->IDE == CAN_ID_STD)
8000e54: 68bb ldr r3, [r7, #8]
8000e56: 689b ldr r3, [r3, #8]
8000e58: 2b00 cmp r3, #0
8000e5a: d10d bne.n 8000e78 <HAL_CAN_AddTxMessage+0x9a>
{
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) |
8000e5c: 68bb ldr r3, [r7, #8]
8000e5e: 681b ldr r3, [r3, #0]
8000e60: 055a lsls r2, r3, #21
pHeader->RTR);
8000e62: 68bb ldr r3, [r7, #8]
8000e64: 68db ldr r3, [r3, #12]
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) |
8000e66: 68f9 ldr r1, [r7, #12]
8000e68: 6809 ldr r1, [r1, #0]
8000e6a: 431a orrs r2, r3
8000e6c: 697b ldr r3, [r7, #20]
8000e6e: 3318 adds r3, #24
8000e70: 011b lsls r3, r3, #4
8000e72: 440b add r3, r1
8000e74: 601a str r2, [r3, #0]
8000e76: e00f b.n 8000e98 <HAL_CAN_AddTxMessage+0xba>
}
else
{
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
8000e78: 68bb ldr r3, [r7, #8]
8000e7a: 685b ldr r3, [r3, #4]
8000e7c: 00da lsls r2, r3, #3
pHeader->IDE |
8000e7e: 68bb ldr r3, [r7, #8]
8000e80: 689b ldr r3, [r3, #8]
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
8000e82: 431a orrs r2, r3
pHeader->RTR);
8000e84: 68bb ldr r3, [r7, #8]
8000e86: 68db ldr r3, [r3, #12]
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
8000e88: 68f9 ldr r1, [r7, #12]
8000e8a: 6809 ldr r1, [r1, #0]
pHeader->IDE |
8000e8c: 431a orrs r2, r3
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
8000e8e: 697b ldr r3, [r7, #20]
8000e90: 3318 adds r3, #24
8000e92: 011b lsls r3, r3, #4
8000e94: 440b add r3, r1
8000e96: 601a str r2, [r3, #0]
}
/* Set up the DLC */
hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC);
8000e98: 68fb ldr r3, [r7, #12]
8000e9a: 6819 ldr r1, [r3, #0]
8000e9c: 68bb ldr r3, [r7, #8]
8000e9e: 691a ldr r2, [r3, #16]
8000ea0: 697b ldr r3, [r7, #20]
8000ea2: 3318 adds r3, #24
8000ea4: 011b lsls r3, r3, #4
8000ea6: 440b add r3, r1
8000ea8: 3304 adds r3, #4
8000eaa: 601a str r2, [r3, #0]
/* Set up the Transmit Global Time mode */
if (pHeader->TransmitGlobalTime == ENABLE)
8000eac: 68bb ldr r3, [r7, #8]
8000eae: 7d1b ldrb r3, [r3, #20]
8000eb0: 2b01 cmp r3, #1
8000eb2: d111 bne.n 8000ed8 <HAL_CAN_AddTxMessage+0xfa>
{
SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT);
8000eb4: 68fb ldr r3, [r7, #12]
8000eb6: 681a ldr r2, [r3, #0]
8000eb8: 697b ldr r3, [r7, #20]
8000eba: 3318 adds r3, #24
8000ebc: 011b lsls r3, r3, #4
8000ebe: 4413 add r3, r2
8000ec0: 3304 adds r3, #4
8000ec2: 681b ldr r3, [r3, #0]
8000ec4: 68fa ldr r2, [r7, #12]
8000ec6: 6811 ldr r1, [r2, #0]
8000ec8: f443 7280 orr.w r2, r3, #256 ; 0x100
8000ecc: 697b ldr r3, [r7, #20]
8000ece: 3318 adds r3, #24
8000ed0: 011b lsls r3, r3, #4
8000ed2: 440b add r3, r1
8000ed4: 3304 adds r3, #4
8000ed6: 601a str r2, [r3, #0]
}
/* Set up the data field */
WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR,
8000ed8: 687b ldr r3, [r7, #4]
8000eda: 3307 adds r3, #7
8000edc: 781b ldrb r3, [r3, #0]
8000ede: 061a lsls r2, r3, #24
8000ee0: 687b ldr r3, [r7, #4]
8000ee2: 3306 adds r3, #6
8000ee4: 781b ldrb r3, [r3, #0]
8000ee6: 041b lsls r3, r3, #16
8000ee8: 431a orrs r2, r3
8000eea: 687b ldr r3, [r7, #4]
8000eec: 3305 adds r3, #5
8000eee: 781b ldrb r3, [r3, #0]
8000ef0: 021b lsls r3, r3, #8
8000ef2: 4313 orrs r3, r2
8000ef4: 687a ldr r2, [r7, #4]
8000ef6: 3204 adds r2, #4
8000ef8: 7812 ldrb r2, [r2, #0]
8000efa: 4610 mov r0, r2
8000efc: 68fa ldr r2, [r7, #12]
8000efe: 6811 ldr r1, [r2, #0]
8000f00: ea43 0200 orr.w r2, r3, r0
8000f04: 697b ldr r3, [r7, #20]
8000f06: 011b lsls r3, r3, #4
8000f08: 440b add r3, r1
8000f0a: f503 73c6 add.w r3, r3, #396 ; 0x18c
8000f0e: 601a str r2, [r3, #0]
((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) |
((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) |
((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) |
((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos));
WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR,
8000f10: 687b ldr r3, [r7, #4]
8000f12: 3303 adds r3, #3
8000f14: 781b ldrb r3, [r3, #0]
8000f16: 061a lsls r2, r3, #24
8000f18: 687b ldr r3, [r7, #4]
8000f1a: 3302 adds r3, #2
8000f1c: 781b ldrb r3, [r3, #0]
8000f1e: 041b lsls r3, r3, #16
8000f20: 431a orrs r2, r3
8000f22: 687b ldr r3, [r7, #4]
8000f24: 3301 adds r3, #1
8000f26: 781b ldrb r3, [r3, #0]
8000f28: 021b lsls r3, r3, #8
8000f2a: 4313 orrs r3, r2
8000f2c: 687a ldr r2, [r7, #4]
8000f2e: 7812 ldrb r2, [r2, #0]
8000f30: 4610 mov r0, r2
8000f32: 68fa ldr r2, [r7, #12]
8000f34: 6811 ldr r1, [r2, #0]
8000f36: ea43 0200 orr.w r2, r3, r0
8000f3a: 697b ldr r3, [r7, #20]
8000f3c: 011b lsls r3, r3, #4
8000f3e: 440b add r3, r1
8000f40: f503 73c4 add.w r3, r3, #392 ; 0x188
8000f44: 601a str r2, [r3, #0]
((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) |
((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) |
((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos));
/* Request transmission */
SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ);
8000f46: 68fb ldr r3, [r7, #12]
8000f48: 681a ldr r2, [r3, #0]
8000f4a: 697b ldr r3, [r7, #20]
8000f4c: 3318 adds r3, #24
8000f4e: 011b lsls r3, r3, #4
8000f50: 4413 add r3, r2
8000f52: 681b ldr r3, [r3, #0]
8000f54: 68fa ldr r2, [r7, #12]
8000f56: 6811 ldr r1, [r2, #0]
8000f58: f043 0201 orr.w r2, r3, #1
8000f5c: 697b ldr r3, [r7, #20]
8000f5e: 3318 adds r3, #24
8000f60: 011b lsls r3, r3, #4
8000f62: 440b add r3, r1
8000f64: 601a str r2, [r3, #0]
/* Return function status */
return HAL_OK;
8000f66: 2300 movs r3, #0
8000f68: e00e b.n 8000f88 <HAL_CAN_AddTxMessage+0x1aa>
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
8000f6a: 68fb ldr r3, [r7, #12]
8000f6c: 6a5b ldr r3, [r3, #36] ; 0x24
8000f6e: f443 1200 orr.w r2, r3, #2097152 ; 0x200000
8000f72: 68fb ldr r3, [r7, #12]
8000f74: 625a str r2, [r3, #36] ; 0x24
return HAL_ERROR;
8000f76: 2301 movs r3, #1
8000f78: e006 b.n 8000f88 <HAL_CAN_AddTxMessage+0x1aa>
}
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
8000f7a: 68fb ldr r3, [r7, #12]
8000f7c: 6a5b ldr r3, [r3, #36] ; 0x24
8000f7e: f443 2280 orr.w r2, r3, #262144 ; 0x40000
8000f82: 68fb ldr r3, [r7, #12]
8000f84: 625a str r2, [r3, #36] ; 0x24
return HAL_ERROR;
8000f86: 2301 movs r3, #1
}
}
8000f88: 4618 mov r0, r3
8000f8a: 3724 adds r7, #36 ; 0x24
8000f8c: 46bd mov sp, r7
8000f8e: f85d 7b04 ldr.w r7, [sp], #4
8000f92: 4770 bx lr
08000f94 <HAL_CAN_GetRxMessage>:
* of the Rx frame will be stored.
* @param aData array where the payload of the Rx frame will be stored.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[])
{
8000f94: b480 push {r7}
8000f96: b087 sub sp, #28
8000f98: af00 add r7, sp, #0
8000f9a: 60f8 str r0, [r7, #12]
8000f9c: 60b9 str r1, [r7, #8]
8000f9e: 607a str r2, [r7, #4]
8000fa0: 603b str r3, [r7, #0]
HAL_CAN_StateTypeDef state = hcan->State;
8000fa2: 68fb ldr r3, [r7, #12]
8000fa4: f893 3020 ldrb.w r3, [r3, #32]
8000fa8: 75fb strb r3, [r7, #23]
assert_param(IS_CAN_RX_FIFO(RxFifo));
if ((state == HAL_CAN_STATE_READY) ||
8000faa: 7dfb ldrb r3, [r7, #23]
8000fac: 2b01 cmp r3, #1
8000fae: d003 beq.n 8000fb8 <HAL_CAN_GetRxMessage+0x24>
8000fb0: 7dfb ldrb r3, [r7, #23]
8000fb2: 2b02 cmp r3, #2
8000fb4: f040 80f3 bne.w 800119e <HAL_CAN_GetRxMessage+0x20a>
(state == HAL_CAN_STATE_LISTENING))
{
/* Check the Rx FIFO */
if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */
8000fb8: 68bb ldr r3, [r7, #8]
8000fba: 2b00 cmp r3, #0
8000fbc: d10e bne.n 8000fdc <HAL_CAN_GetRxMessage+0x48>
{
/* Check that the Rx FIFO 0 is not empty */
if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U)
8000fbe: 68fb ldr r3, [r7, #12]
8000fc0: 681b ldr r3, [r3, #0]
8000fc2: 68db ldr r3, [r3, #12]
8000fc4: f003 0303 and.w r3, r3, #3
8000fc8: 2b00 cmp r3, #0
8000fca: d116 bne.n 8000ffa <HAL_CAN_GetRxMessage+0x66>
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
8000fcc: 68fb ldr r3, [r7, #12]
8000fce: 6a5b ldr r3, [r3, #36] ; 0x24
8000fd0: f443 1200 orr.w r2, r3, #2097152 ; 0x200000
8000fd4: 68fb ldr r3, [r7, #12]
8000fd6: 625a str r2, [r3, #36] ; 0x24
return HAL_ERROR;
8000fd8: 2301 movs r3, #1
8000fda: e0e7 b.n 80011ac <HAL_CAN_GetRxMessage+0x218>
}
}
else /* Rx element is assigned to Rx FIFO 1 */
{
/* Check that the Rx FIFO 1 is not empty */
if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U)
8000fdc: 68fb ldr r3, [r7, #12]
8000fde: 681b ldr r3, [r3, #0]
8000fe0: 691b ldr r3, [r3, #16]
8000fe2: f003 0303 and.w r3, r3, #3
8000fe6: 2b00 cmp r3, #0
8000fe8: d107 bne.n 8000ffa <HAL_CAN_GetRxMessage+0x66>
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
8000fea: 68fb ldr r3, [r7, #12]
8000fec: 6a5b ldr r3, [r3, #36] ; 0x24
8000fee: f443 1200 orr.w r2, r3, #2097152 ; 0x200000
8000ff2: 68fb ldr r3, [r7, #12]
8000ff4: 625a str r2, [r3, #36] ; 0x24
return HAL_ERROR;
8000ff6: 2301 movs r3, #1
8000ff8: e0d8 b.n 80011ac <HAL_CAN_GetRxMessage+0x218>
}
}
/* Get the header */
pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR;
8000ffa: 68fb ldr r3, [r7, #12]
8000ffc: 681a ldr r2, [r3, #0]
8000ffe: 68bb ldr r3, [r7, #8]
8001000: 331b adds r3, #27
8001002: 011b lsls r3, r3, #4
8001004: 4413 add r3, r2
8001006: 681b ldr r3, [r3, #0]
8001008: f003 0204 and.w r2, r3, #4
800100c: 687b ldr r3, [r7, #4]
800100e: 609a str r2, [r3, #8]
if (pHeader->IDE == CAN_ID_STD)
8001010: 687b ldr r3, [r7, #4]
8001012: 689b ldr r3, [r3, #8]
8001014: 2b00 cmp r3, #0
8001016: d10c bne.n 8001032 <HAL_CAN_GetRxMessage+0x9e>
{
pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos;
8001018: 68fb ldr r3, [r7, #12]
800101a: 681a ldr r2, [r3, #0]
800101c: 68bb ldr r3, [r7, #8]
800101e: 331b adds r3, #27
8001020: 011b lsls r3, r3, #4
8001022: 4413 add r3, r2
8001024: 681b ldr r3, [r3, #0]
8001026: 0d5b lsrs r3, r3, #21
8001028: f3c3 020a ubfx r2, r3, #0, #11
800102c: 687b ldr r3, [r7, #4]
800102e: 601a str r2, [r3, #0]
8001030: e00b b.n 800104a <HAL_CAN_GetRxMessage+0xb6>
}
else
{
pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos;
8001032: 68fb ldr r3, [r7, #12]
8001034: 681a ldr r2, [r3, #0]
8001036: 68bb ldr r3, [r7, #8]
8001038: 331b adds r3, #27
800103a: 011b lsls r3, r3, #4
800103c: 4413 add r3, r2
800103e: 681b ldr r3, [r3, #0]
8001040: 08db lsrs r3, r3, #3
8001042: f023 4260 bic.w r2, r3, #3758096384 ; 0xe0000000
8001046: 687b ldr r3, [r7, #4]
8001048: 605a str r2, [r3, #4]
}
pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR);
800104a: 68fb ldr r3, [r7, #12]
800104c: 681a ldr r2, [r3, #0]
800104e: 68bb ldr r3, [r7, #8]
8001050: 331b adds r3, #27
8001052: 011b lsls r3, r3, #4
8001054: 4413 add r3, r2
8001056: 681b ldr r3, [r3, #0]
8001058: f003 0202 and.w r2, r3, #2
800105c: 687b ldr r3, [r7, #4]
800105e: 60da str r2, [r3, #12]
pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos;
8001060: 68fb ldr r3, [r7, #12]
8001062: 681a ldr r2, [r3, #0]
8001064: 68bb ldr r3, [r7, #8]
8001066: 331b adds r3, #27
8001068: 011b lsls r3, r3, #4
800106a: 4413 add r3, r2
800106c: 3304 adds r3, #4
800106e: 681b ldr r3, [r3, #0]
8001070: f003 020f and.w r2, r3, #15
8001074: 687b ldr r3, [r7, #4]
8001076: 611a str r2, [r3, #16]
pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos;
8001078: 68fb ldr r3, [r7, #12]
800107a: 681a ldr r2, [r3, #0]
800107c: 68bb ldr r3, [r7, #8]
800107e: 331b adds r3, #27
8001080: 011b lsls r3, r3, #4
8001082: 4413 add r3, r2
8001084: 3304 adds r3, #4
8001086: 681b ldr r3, [r3, #0]
8001088: 0a1b lsrs r3, r3, #8
800108a: b2da uxtb r2, r3
800108c: 687b ldr r3, [r7, #4]
800108e: 619a str r2, [r3, #24]
pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos;
8001090: 68fb ldr r3, [r7, #12]
8001092: 681a ldr r2, [r3, #0]
8001094: 68bb ldr r3, [r7, #8]
8001096: 331b adds r3, #27
8001098: 011b lsls r3, r3, #4
800109a: 4413 add r3, r2
800109c: 3304 adds r3, #4
800109e: 681b ldr r3, [r3, #0]
80010a0: 0c1b lsrs r3, r3, #16
80010a2: b29a uxth r2, r3
80010a4: 687b ldr r3, [r7, #4]
80010a6: 615a str r2, [r3, #20]
/* Get the data */
aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos);
80010a8: 68fb ldr r3, [r7, #12]
80010aa: 681a ldr r2, [r3, #0]
80010ac: 68bb ldr r3, [r7, #8]
80010ae: 011b lsls r3, r3, #4
80010b0: 4413 add r3, r2
80010b2: f503 73dc add.w r3, r3, #440 ; 0x1b8
80010b6: 681b ldr r3, [r3, #0]
80010b8: b2da uxtb r2, r3
80010ba: 683b ldr r3, [r7, #0]
80010bc: 701a strb r2, [r3, #0]
aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos);
80010be: 68fb ldr r3, [r7, #12]
80010c0: 681a ldr r2, [r3, #0]
80010c2: 68bb ldr r3, [r7, #8]
80010c4: 011b lsls r3, r3, #4
80010c6: 4413 add r3, r2
80010c8: f503 73dc add.w r3, r3, #440 ; 0x1b8
80010cc: 681b ldr r3, [r3, #0]
80010ce: 0a1a lsrs r2, r3, #8
80010d0: 683b ldr r3, [r7, #0]
80010d2: 3301 adds r3, #1
80010d4: b2d2 uxtb r2, r2
80010d6: 701a strb r2, [r3, #0]
aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos);
80010d8: 68fb ldr r3, [r7, #12]
80010da: 681a ldr r2, [r3, #0]
80010dc: 68bb ldr r3, [r7, #8]
80010de: 011b lsls r3, r3, #4
80010e0: 4413 add r3, r2
80010e2: f503 73dc add.w r3, r3, #440 ; 0x1b8
80010e6: 681b ldr r3, [r3, #0]
80010e8: 0c1a lsrs r2, r3, #16
80010ea: 683b ldr r3, [r7, #0]
80010ec: 3302 adds r3, #2
80010ee: b2d2 uxtb r2, r2
80010f0: 701a strb r2, [r3, #0]
aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos);
80010f2: 68fb ldr r3, [r7, #12]
80010f4: 681a ldr r2, [r3, #0]
80010f6: 68bb ldr r3, [r7, #8]
80010f8: 011b lsls r3, r3, #4
80010fa: 4413 add r3, r2
80010fc: f503 73dc add.w r3, r3, #440 ; 0x1b8
8001100: 681b ldr r3, [r3, #0]
8001102: 0e1a lsrs r2, r3, #24
8001104: 683b ldr r3, [r7, #0]
8001106: 3303 adds r3, #3
8001108: b2d2 uxtb r2, r2
800110a: 701a strb r2, [r3, #0]
aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos);
800110c: 68fb ldr r3, [r7, #12]
800110e: 681a ldr r2, [r3, #0]
8001110: 68bb ldr r3, [r7, #8]
8001112: 011b lsls r3, r3, #4
8001114: 4413 add r3, r2
8001116: f503 73de add.w r3, r3, #444 ; 0x1bc
800111a: 681a ldr r2, [r3, #0]
800111c: 683b ldr r3, [r7, #0]
800111e: 3304 adds r3, #4
8001120: b2d2 uxtb r2, r2
8001122: 701a strb r2, [r3, #0]
aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos);
8001124: 68fb ldr r3, [r7, #12]
8001126: 681a ldr r2, [r3, #0]
8001128: 68bb ldr r3, [r7, #8]
800112a: 011b lsls r3, r3, #4
800112c: 4413 add r3, r2
800112e: f503 73de add.w r3, r3, #444 ; 0x1bc
8001132: 681b ldr r3, [r3, #0]
8001134: 0a1a lsrs r2, r3, #8
8001136: 683b ldr r3, [r7, #0]
8001138: 3305 adds r3, #5
800113a: b2d2 uxtb r2, r2
800113c: 701a strb r2, [r3, #0]
aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos);
800113e: 68fb ldr r3, [r7, #12]
8001140: 681a ldr r2, [r3, #0]
8001142: 68bb ldr r3, [r7, #8]
8001144: 011b lsls r3, r3, #4
8001146: 4413 add r3, r2
8001148: f503 73de add.w r3, r3, #444 ; 0x1bc
800114c: 681b ldr r3, [r3, #0]
800114e: 0c1a lsrs r2, r3, #16
8001150: 683b ldr r3, [r7, #0]
8001152: 3306 adds r3, #6
8001154: b2d2 uxtb r2, r2
8001156: 701a strb r2, [r3, #0]
aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos);
8001158: 68fb ldr r3, [r7, #12]
800115a: 681a ldr r2, [r3, #0]
800115c: 68bb ldr r3, [r7, #8]
800115e: 011b lsls r3, r3, #4
8001160: 4413 add r3, r2
8001162: f503 73de add.w r3, r3, #444 ; 0x1bc
8001166: 681b ldr r3, [r3, #0]
8001168: 0e1a lsrs r2, r3, #24
800116a: 683b ldr r3, [r7, #0]
800116c: 3307 adds r3, #7
800116e: b2d2 uxtb r2, r2
8001170: 701a strb r2, [r3, #0]
/* Release the FIFO */
if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */
8001172: 68bb ldr r3, [r7, #8]
8001174: 2b00 cmp r3, #0
8001176: d108 bne.n 800118a <HAL_CAN_GetRxMessage+0x1f6>
{
/* Release RX FIFO 0 */
SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0);
8001178: 68fb ldr r3, [r7, #12]
800117a: 681b ldr r3, [r3, #0]
800117c: 68da ldr r2, [r3, #12]
800117e: 68fb ldr r3, [r7, #12]
8001180: 681b ldr r3, [r3, #0]
8001182: f042 0220 orr.w r2, r2, #32
8001186: 60da str r2, [r3, #12]
8001188: e007 b.n 800119a <HAL_CAN_GetRxMessage+0x206>
}
else /* Rx element is assigned to Rx FIFO 1 */
{
/* Release RX FIFO 1 */
SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1);
800118a: 68fb ldr r3, [r7, #12]
800118c: 681b ldr r3, [r3, #0]
800118e: 691a ldr r2, [r3, #16]
8001190: 68fb ldr r3, [r7, #12]
8001192: 681b ldr r3, [r3, #0]
8001194: f042 0220 orr.w r2, r2, #32
8001198: 611a str r2, [r3, #16]
}
/* Return function status */
return HAL_OK;
800119a: 2300 movs r3, #0
800119c: e006 b.n 80011ac <HAL_CAN_GetRxMessage+0x218>
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
800119e: 68fb ldr r3, [r7, #12]
80011a0: 6a5b ldr r3, [r3, #36] ; 0x24
80011a2: f443 2280 orr.w r2, r3, #262144 ; 0x40000
80011a6: 68fb ldr r3, [r7, #12]
80011a8: 625a str r2, [r3, #36] ; 0x24
return HAL_ERROR;
80011aa: 2301 movs r3, #1
}
}
80011ac: 4618 mov r0, r3
80011ae: 371c adds r7, #28
80011b0: 46bd mov sp, r7
80011b2: f85d 7b04 ldr.w r7, [sp], #4
80011b6: 4770 bx lr
080011b8 <HAL_CAN_ActivateNotification>:
* @param ActiveITs indicates which interrupts will be enabled.
* This parameter can be any combination of @arg CAN_Interrupts.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs)
{
80011b8: b480 push {r7}
80011ba: b085 sub sp, #20
80011bc: af00 add r7, sp, #0
80011be: 6078 str r0, [r7, #4]
80011c0: 6039 str r1, [r7, #0]
HAL_CAN_StateTypeDef state = hcan->State;
80011c2: 687b ldr r3, [r7, #4]
80011c4: f893 3020 ldrb.w r3, [r3, #32]
80011c8: 73fb strb r3, [r7, #15]
/* Check function parameters */
assert_param(IS_CAN_IT(ActiveITs));
if ((state == HAL_CAN_STATE_READY) ||
80011ca: 7bfb ldrb r3, [r7, #15]
80011cc: 2b01 cmp r3, #1
80011ce: d002 beq.n 80011d6 <HAL_CAN_ActivateNotification+0x1e>
80011d0: 7bfb ldrb r3, [r7, #15]
80011d2: 2b02 cmp r3, #2
80011d4: d109 bne.n 80011ea <HAL_CAN_ActivateNotification+0x32>
(state == HAL_CAN_STATE_LISTENING))
{
/* Enable the selected interrupts */
__HAL_CAN_ENABLE_IT(hcan, ActiveITs);
80011d6: 687b ldr r3, [r7, #4]
80011d8: 681b ldr r3, [r3, #0]
80011da: 6959 ldr r1, [r3, #20]
80011dc: 687b ldr r3, [r7, #4]
80011de: 681b ldr r3, [r3, #0]
80011e0: 683a ldr r2, [r7, #0]
80011e2: 430a orrs r2, r1
80011e4: 615a str r2, [r3, #20]
/* Return function status */
return HAL_OK;
80011e6: 2300 movs r3, #0
80011e8: e006 b.n 80011f8 <HAL_CAN_ActivateNotification+0x40>
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
80011ea: 687b ldr r3, [r7, #4]
80011ec: 6a5b ldr r3, [r3, #36] ; 0x24
80011ee: f443 2280 orr.w r2, r3, #262144 ; 0x40000
80011f2: 687b ldr r3, [r7, #4]
80011f4: 625a str r2, [r3, #36] ; 0x24
return HAL_ERROR;
80011f6: 2301 movs r3, #1
}
}
80011f8: 4618 mov r0, r3
80011fa: 3714 adds r7, #20
80011fc: 46bd mov sp, r7
80011fe: f85d 7b04 ldr.w r7, [sp], #4
8001202: 4770 bx lr
08001204 <HAL_CAN_IRQHandler>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
{
8001204: b580 push {r7, lr}
8001206: b08a sub sp, #40 ; 0x28
8001208: af00 add r7, sp, #0
800120a: 6078 str r0, [r7, #4]
uint32_t errorcode = HAL_CAN_ERROR_NONE;
800120c: 2300 movs r3, #0
800120e: 627b str r3, [r7, #36] ; 0x24
uint32_t interrupts = READ_REG(hcan->Instance->IER);
8001210: 687b ldr r3, [r7, #4]
8001212: 681b ldr r3, [r3, #0]
8001214: 695b ldr r3, [r3, #20]
8001216: 623b str r3, [r7, #32]
uint32_t msrflags = READ_REG(hcan->Instance->MSR);
8001218: 687b ldr r3, [r7, #4]
800121a: 681b ldr r3, [r3, #0]
800121c: 685b ldr r3, [r3, #4]
800121e: 61fb str r3, [r7, #28]
uint32_t tsrflags = READ_REG(hcan->Instance->TSR);
8001220: 687b ldr r3, [r7, #4]
8001222: 681b ldr r3, [r3, #0]
8001224: 689b ldr r3, [r3, #8]
8001226: 61bb str r3, [r7, #24]
uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R);
8001228: 687b ldr r3, [r7, #4]
800122a: 681b ldr r3, [r3, #0]
800122c: 68db ldr r3, [r3, #12]
800122e: 617b str r3, [r7, #20]
uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R);
8001230: 687b ldr r3, [r7, #4]
8001232: 681b ldr r3, [r3, #0]
8001234: 691b ldr r3, [r3, #16]
8001236: 613b str r3, [r7, #16]
uint32_t esrflags = READ_REG(hcan->Instance->ESR);
8001238: 687b ldr r3, [r7, #4]
800123a: 681b ldr r3, [r3, #0]
800123c: 699b ldr r3, [r3, #24]
800123e: 60fb str r3, [r7, #12]
/* Transmit Mailbox empty interrupt management *****************************/
if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U)
8001240: 6a3b ldr r3, [r7, #32]
8001242: f003 0301 and.w r3, r3, #1
8001246: 2b00 cmp r3, #0
8001248: d07c beq.n 8001344 <HAL_CAN_IRQHandler+0x140>
{
/* Transmit Mailbox 0 management *****************************************/
if ((tsrflags & CAN_TSR_RQCP0) != 0U)
800124a: 69bb ldr r3, [r7, #24]
800124c: f003 0301 and.w r3, r3, #1
8001250: 2b00 cmp r3, #0
8001252: d023 beq.n 800129c <HAL_CAN_IRQHandler+0x98>
{
/* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0);
8001254: 687b ldr r3, [r7, #4]
8001256: 681b ldr r3, [r3, #0]
8001258: 2201 movs r2, #1
800125a: 609a str r2, [r3, #8]
if ((tsrflags & CAN_TSR_TXOK0) != 0U)
800125c: 69bb ldr r3, [r7, #24]
800125e: f003 0302 and.w r3, r3, #2
8001262: 2b00 cmp r3, #0
8001264: d003 beq.n 800126e <HAL_CAN_IRQHandler+0x6a>
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->TxMailbox0CompleteCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox0CompleteCallback(hcan);
8001266: 6878 ldr r0, [r7, #4]
8001268: f000 f983 bl 8001572 <HAL_CAN_TxMailbox0CompleteCallback>
800126c: e016 b.n 800129c <HAL_CAN_IRQHandler+0x98>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
else
{
if ((tsrflags & CAN_TSR_ALST0) != 0U)
800126e: 69bb ldr r3, [r7, #24]
8001270: f003 0304 and.w r3, r3, #4
8001274: 2b00 cmp r3, #0
8001276: d004 beq.n 8001282 <HAL_CAN_IRQHandler+0x7e>
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_ALST0;
8001278: 6a7b ldr r3, [r7, #36] ; 0x24
800127a: f443 6300 orr.w r3, r3, #2048 ; 0x800
800127e: 627b str r3, [r7, #36] ; 0x24
8001280: e00c b.n 800129c <HAL_CAN_IRQHandler+0x98>
}
else if ((tsrflags & CAN_TSR_TERR0) != 0U)
8001282: 69bb ldr r3, [r7, #24]
8001284: f003 0308 and.w r3, r3, #8
8001288: 2b00 cmp r3, #0
800128a: d004 beq.n 8001296 <HAL_CAN_IRQHandler+0x92>
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_TERR0;
800128c: 6a7b ldr r3, [r7, #36] ; 0x24
800128e: f443 5380 orr.w r3, r3, #4096 ; 0x1000
8001292: 627b str r3, [r7, #36] ; 0x24
8001294: e002 b.n 800129c <HAL_CAN_IRQHandler+0x98>
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->TxMailbox0AbortCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox0AbortCallback(hcan);
8001296: 6878 ldr r0, [r7, #4]
8001298: f000 f989 bl 80015ae <HAL_CAN_TxMailbox0AbortCallback>
}
}
}
/* Transmit Mailbox 1 management *****************************************/
if ((tsrflags & CAN_TSR_RQCP1) != 0U)
800129c: 69bb ldr r3, [r7, #24]
800129e: f403 7380 and.w r3, r3, #256 ; 0x100
80012a2: 2b00 cmp r3, #0
80012a4: d024 beq.n 80012f0 <HAL_CAN_IRQHandler+0xec>
{
/* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1);
80012a6: 687b ldr r3, [r7, #4]
80012a8: 681b ldr r3, [r3, #0]
80012aa: f44f 7280 mov.w r2, #256 ; 0x100
80012ae: 609a str r2, [r3, #8]
if ((tsrflags & CAN_TSR_TXOK1) != 0U)
80012b0: 69bb ldr r3, [r7, #24]
80012b2: f403 7300 and.w r3, r3, #512 ; 0x200
80012b6: 2b00 cmp r3, #0
80012b8: d003 beq.n 80012c2 <HAL_CAN_IRQHandler+0xbe>
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->TxMailbox1CompleteCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox1CompleteCallback(hcan);
80012ba: 6878 ldr r0, [r7, #4]
80012bc: f000 f963 bl 8001586 <HAL_CAN_TxMailbox1CompleteCallback>
80012c0: e016 b.n 80012f0 <HAL_CAN_IRQHandler+0xec>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
else
{
if ((tsrflags & CAN_TSR_ALST1) != 0U)
80012c2: 69bb ldr r3, [r7, #24]
80012c4: f403 6380 and.w r3, r3, #1024 ; 0x400
80012c8: 2b00 cmp r3, #0
80012ca: d004 beq.n 80012d6 <HAL_CAN_IRQHandler+0xd2>
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_ALST1;
80012cc: 6a7b ldr r3, [r7, #36] ; 0x24
80012ce: f443 5300 orr.w r3, r3, #8192 ; 0x2000
80012d2: 627b str r3, [r7, #36] ; 0x24
80012d4: e00c b.n 80012f0 <HAL_CAN_IRQHandler+0xec>
}
else if ((tsrflags & CAN_TSR_TERR1) != 0U)
80012d6: 69bb ldr r3, [r7, #24]
80012d8: f403 6300 and.w r3, r3, #2048 ; 0x800
80012dc: 2b00 cmp r3, #0
80012de: d004 beq.n 80012ea <HAL_CAN_IRQHandler+0xe6>
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_TERR1;
80012e0: 6a7b ldr r3, [r7, #36] ; 0x24
80012e2: f443 4380 orr.w r3, r3, #16384 ; 0x4000
80012e6: 627b str r3, [r7, #36] ; 0x24
80012e8: e002 b.n 80012f0 <HAL_CAN_IRQHandler+0xec>
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->TxMailbox1AbortCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox1AbortCallback(hcan);
80012ea: 6878 ldr r0, [r7, #4]
80012ec: f000 f969 bl 80015c2 <HAL_CAN_TxMailbox1AbortCallback>
}
}
}
/* Transmit Mailbox 2 management *****************************************/
if ((tsrflags & CAN_TSR_RQCP2) != 0U)
80012f0: 69bb ldr r3, [r7, #24]
80012f2: f403 3380 and.w r3, r3, #65536 ; 0x10000
80012f6: 2b00 cmp r3, #0
80012f8: d024 beq.n 8001344 <HAL_CAN_IRQHandler+0x140>
{
/* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2);
80012fa: 687b ldr r3, [r7, #4]
80012fc: 681b ldr r3, [r3, #0]
80012fe: f44f 3280 mov.w r2, #65536 ; 0x10000
8001302: 609a str r2, [r3, #8]
if ((tsrflags & CAN_TSR_TXOK2) != 0U)
8001304: 69bb ldr r3, [r7, #24]
8001306: f403 3300 and.w r3, r3, #131072 ; 0x20000
800130a: 2b00 cmp r3, #0
800130c: d003 beq.n 8001316 <HAL_CAN_IRQHandler+0x112>
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->TxMailbox2CompleteCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox2CompleteCallback(hcan);
800130e: 6878 ldr r0, [r7, #4]
8001310: f000 f943 bl 800159a <HAL_CAN_TxMailbox2CompleteCallback>
8001314: e016 b.n 8001344 <HAL_CAN_IRQHandler+0x140>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
else
{
if ((tsrflags & CAN_TSR_ALST2) != 0U)
8001316: 69bb ldr r3, [r7, #24]
8001318: f403 2380 and.w r3, r3, #262144 ; 0x40000
800131c: 2b00 cmp r3, #0
800131e: d004 beq.n 800132a <HAL_CAN_IRQHandler+0x126>
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_ALST2;
8001320: 6a7b ldr r3, [r7, #36] ; 0x24
8001322: f443 4300 orr.w r3, r3, #32768 ; 0x8000
8001326: 627b str r3, [r7, #36] ; 0x24
8001328: e00c b.n 8001344 <HAL_CAN_IRQHandler+0x140>
}
else if ((tsrflags & CAN_TSR_TERR2) != 0U)
800132a: 69bb ldr r3, [r7, #24]
800132c: f403 2300 and.w r3, r3, #524288 ; 0x80000
8001330: 2b00 cmp r3, #0
8001332: d004 beq.n 800133e <HAL_CAN_IRQHandler+0x13a>
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_TERR2;
8001334: 6a7b ldr r3, [r7, #36] ; 0x24
8001336: f443 3380 orr.w r3, r3, #65536 ; 0x10000
800133a: 627b str r3, [r7, #36] ; 0x24
800133c: e002 b.n 8001344 <HAL_CAN_IRQHandler+0x140>
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->TxMailbox2AbortCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox2AbortCallback(hcan);
800133e: 6878 ldr r0, [r7, #4]
8001340: f000 f949 bl 80015d6 <HAL_CAN_TxMailbox2AbortCallback>
}
}
}
/* Receive FIFO 0 overrun interrupt management *****************************/
if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U)
8001344: 6a3b ldr r3, [r7, #32]
8001346: f003 0308 and.w r3, r3, #8
800134a: 2b00 cmp r3, #0
800134c: d00c beq.n 8001368 <HAL_CAN_IRQHandler+0x164>
{
if ((rf0rflags & CAN_RF0R_FOVR0) != 0U)
800134e: 697b ldr r3, [r7, #20]
8001350: f003 0310 and.w r3, r3, #16
8001354: 2b00 cmp r3, #0
8001356: d007 beq.n 8001368 <HAL_CAN_IRQHandler+0x164>
{
/* Set CAN error code to Rx Fifo 0 overrun error */
errorcode |= HAL_CAN_ERROR_RX_FOV0;
8001358: 6a7b ldr r3, [r7, #36] ; 0x24
800135a: f443 7300 orr.w r3, r3, #512 ; 0x200
800135e: 627b str r3, [r7, #36] ; 0x24
/* Clear FIFO0 Overrun Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0);
8001360: 687b ldr r3, [r7, #4]
8001362: 681b ldr r3, [r3, #0]
8001364: 2210 movs r2, #16
8001366: 60da str r2, [r3, #12]
}
}
/* Receive FIFO 0 full interrupt management ********************************/
if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U)
8001368: 6a3b ldr r3, [r7, #32]
800136a: f003 0304 and.w r3, r3, #4
800136e: 2b00 cmp r3, #0
8001370: d00b beq.n 800138a <HAL_CAN_IRQHandler+0x186>
{
if ((rf0rflags & CAN_RF0R_FULL0) != 0U)
8001372: 697b ldr r3, [r7, #20]
8001374: f003 0308 and.w r3, r3, #8
8001378: 2b00 cmp r3, #0
800137a: d006 beq.n 800138a <HAL_CAN_IRQHandler+0x186>
{
/* Clear FIFO 0 full Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0);
800137c: 687b ldr r3, [r7, #4]
800137e: 681b ldr r3, [r3, #0]
8001380: 2208 movs r2, #8
8001382: 60da str r2, [r3, #12]
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->RxFifo0FullCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_RxFifo0FullCallback(hcan);
8001384: 6878 ldr r0, [r7, #4]
8001386: f000 f930 bl 80015ea <HAL_CAN_RxFifo0FullCallback>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* Receive FIFO 0 message pending interrupt management *********************/
if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U)
800138a: 6a3b ldr r3, [r7, #32]
800138c: f003 0302 and.w r3, r3, #2
8001390: 2b00 cmp r3, #0
8001392: d009 beq.n 80013a8 <HAL_CAN_IRQHandler+0x1a4>
{
/* Check if message is still pending */
if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U)
8001394: 687b ldr r3, [r7, #4]
8001396: 681b ldr r3, [r3, #0]
8001398: 68db ldr r3, [r3, #12]
800139a: f003 0303 and.w r3, r3, #3
800139e: 2b00 cmp r3, #0
80013a0: d002 beq.n 80013a8 <HAL_CAN_IRQHandler+0x1a4>
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->RxFifo0MsgPendingCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_RxFifo0MsgPendingCallback(hcan);
80013a2: 6878 ldr r0, [r7, #4]
80013a4: f7fe ff10 bl 80001c8 <HAL_CAN_RxFifo0MsgPendingCallback>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* Receive FIFO 1 overrun interrupt management *****************************/
if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U)
80013a8: 6a3b ldr r3, [r7, #32]
80013aa: f003 0340 and.w r3, r3, #64 ; 0x40
80013ae: 2b00 cmp r3, #0
80013b0: d00c beq.n 80013cc <HAL_CAN_IRQHandler+0x1c8>
{
if ((rf1rflags & CAN_RF1R_FOVR1) != 0U)
80013b2: 693b ldr r3, [r7, #16]
80013b4: f003 0310 and.w r3, r3, #16
80013b8: 2b00 cmp r3, #0
80013ba: d007 beq.n 80013cc <HAL_CAN_IRQHandler+0x1c8>
{
/* Set CAN error code to Rx Fifo 1 overrun error */
errorcode |= HAL_CAN_ERROR_RX_FOV1;
80013bc: 6a7b ldr r3, [r7, #36] ; 0x24
80013be: f443 6380 orr.w r3, r3, #1024 ; 0x400
80013c2: 627b str r3, [r7, #36] ; 0x24
/* Clear FIFO1 Overrun Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1);
80013c4: 687b ldr r3, [r7, #4]
80013c6: 681b ldr r3, [r3, #0]
80013c8: 2210 movs r2, #16
80013ca: 611a str r2, [r3, #16]
}
}
/* Receive FIFO 1 full interrupt management ********************************/
if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U)
80013cc: 6a3b ldr r3, [r7, #32]
80013ce: f003 0320 and.w r3, r3, #32
80013d2: 2b00 cmp r3, #0
80013d4: d00b beq.n 80013ee <HAL_CAN_IRQHandler+0x1ea>
{
if ((rf1rflags & CAN_RF1R_FULL1) != 0U)
80013d6: 693b ldr r3, [r7, #16]
80013d8: f003 0308 and.w r3, r3, #8
80013dc: 2b00 cmp r3, #0
80013de: d006 beq.n 80013ee <HAL_CAN_IRQHandler+0x1ea>
{
/* Clear FIFO 1 full Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1);
80013e0: 687b ldr r3, [r7, #4]
80013e2: 681b ldr r3, [r3, #0]
80013e4: 2208 movs r2, #8
80013e6: 611a str r2, [r3, #16]
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->RxFifo1FullCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_RxFifo1FullCallback(hcan);
80013e8: 6878 ldr r0, [r7, #4]
80013ea: f000 f908 bl 80015fe <HAL_CAN_RxFifo1FullCallback>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* Receive FIFO 1 message pending interrupt management *********************/
if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U)
80013ee: 6a3b ldr r3, [r7, #32]
80013f0: f003 0310 and.w r3, r3, #16
80013f4: 2b00 cmp r3, #0
80013f6: d009 beq.n 800140c <HAL_CAN_IRQHandler+0x208>
{
/* Check if message is still pending */
if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U)
80013f8: 687b ldr r3, [r7, #4]
80013fa: 681b ldr r3, [r3, #0]
80013fc: 691b ldr r3, [r3, #16]
80013fe: f003 0303 and.w r3, r3, #3
8001402: 2b00 cmp r3, #0
8001404: d002 beq.n 800140c <HAL_CAN_IRQHandler+0x208>
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->RxFifo1MsgPendingCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_RxFifo1MsgPendingCallback(hcan);
8001406: 6878 ldr r0, [r7, #4]
8001408: f7fe ff38 bl 800027c <HAL_CAN_RxFifo1MsgPendingCallback>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* Sleep interrupt management *********************************************/
if ((interrupts & CAN_IT_SLEEP_ACK) != 0U)
800140c: 6a3b ldr r3, [r7, #32]
800140e: f403 3300 and.w r3, r3, #131072 ; 0x20000
8001412: 2b00 cmp r3, #0
8001414: d00b beq.n 800142e <HAL_CAN_IRQHandler+0x22a>
{
if ((msrflags & CAN_MSR_SLAKI) != 0U)
8001416: 69fb ldr r3, [r7, #28]
8001418: f003 0310 and.w r3, r3, #16
800141c: 2b00 cmp r3, #0
800141e: d006 beq.n 800142e <HAL_CAN_IRQHandler+0x22a>
{
/* Clear Sleep interrupt Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI);
8001420: 687b ldr r3, [r7, #4]
8001422: 681b ldr r3, [r3, #0]
8001424: 2210 movs r2, #16
8001426: 605a str r2, [r3, #4]
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->SleepCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_SleepCallback(hcan);
8001428: 6878 ldr r0, [r7, #4]
800142a: f000 f8f2 bl 8001612 <HAL_CAN_SleepCallback>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* WakeUp interrupt management *********************************************/
if ((interrupts & CAN_IT_WAKEUP) != 0U)
800142e: 6a3b ldr r3, [r7, #32]
8001430: f403 3380 and.w r3, r3, #65536 ; 0x10000
8001434: 2b00 cmp r3, #0
8001436: d00b beq.n 8001450 <HAL_CAN_IRQHandler+0x24c>
{
if ((msrflags & CAN_MSR_WKUI) != 0U)
8001438: 69fb ldr r3, [r7, #28]
800143a: f003 0308 and.w r3, r3, #8
800143e: 2b00 cmp r3, #0
8001440: d006 beq.n 8001450 <HAL_CAN_IRQHandler+0x24c>
{
/* Clear WakeUp Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU);
8001442: 687b ldr r3, [r7, #4]
8001444: 681b ldr r3, [r3, #0]
8001446: 2208 movs r2, #8
8001448: 605a str r2, [r3, #4]
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->WakeUpFromRxMsgCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_WakeUpFromRxMsgCallback(hcan);
800144a: 6878 ldr r0, [r7, #4]
800144c: f000 f8eb bl 8001626 <HAL_CAN_WakeUpFromRxMsgCallback>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* Error interrupts management *********************************************/
if ((interrupts & CAN_IT_ERROR) != 0U)
8001450: 6a3b ldr r3, [r7, #32]
8001452: f403 4300 and.w r3, r3, #32768 ; 0x8000
8001456: 2b00 cmp r3, #0
8001458: d07b beq.n 8001552 <HAL_CAN_IRQHandler+0x34e>
{
if ((msrflags & CAN_MSR_ERRI) != 0U)
800145a: 69fb ldr r3, [r7, #28]
800145c: f003 0304 and.w r3, r3, #4
8001460: 2b00 cmp r3, #0
8001462: d072 beq.n 800154a <HAL_CAN_IRQHandler+0x346>
{
/* Check Error Warning Flag */
if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) &&
8001464: 6a3b ldr r3, [r7, #32]
8001466: f403 7380 and.w r3, r3, #256 ; 0x100
800146a: 2b00 cmp r3, #0
800146c: d008 beq.n 8001480 <HAL_CAN_IRQHandler+0x27c>
((esrflags & CAN_ESR_EWGF) != 0U))
800146e: 68fb ldr r3, [r7, #12]
8001470: f003 0301 and.w r3, r3, #1
if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) &&
8001474: 2b00 cmp r3, #0
8001476: d003 beq.n 8001480 <HAL_CAN_IRQHandler+0x27c>
{
/* Set CAN error code to Error Warning */
errorcode |= HAL_CAN_ERROR_EWG;
8001478: 6a7b ldr r3, [r7, #36] ; 0x24
800147a: f043 0301 orr.w r3, r3, #1
800147e: 627b str r3, [r7, #36] ; 0x24
/* No need for clear of Error Warning Flag as read-only */
}
/* Check Error Passive Flag */
if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) &&
8001480: 6a3b ldr r3, [r7, #32]
8001482: f403 7300 and.w r3, r3, #512 ; 0x200
8001486: 2b00 cmp r3, #0
8001488: d008 beq.n 800149c <HAL_CAN_IRQHandler+0x298>
((esrflags & CAN_ESR_EPVF) != 0U))
800148a: 68fb ldr r3, [r7, #12]
800148c: f003 0302 and.w r3, r3, #2
if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) &&
8001490: 2b00 cmp r3, #0
8001492: d003 beq.n 800149c <HAL_CAN_IRQHandler+0x298>
{
/* Set CAN error code to Error Passive */
errorcode |= HAL_CAN_ERROR_EPV;
8001494: 6a7b ldr r3, [r7, #36] ; 0x24
8001496: f043 0302 orr.w r3, r3, #2
800149a: 627b str r3, [r7, #36] ; 0x24
/* No need for clear of Error Passive Flag as read-only */
}
/* Check Bus-off Flag */
if (((interrupts & CAN_IT_BUSOFF) != 0U) &&
800149c: 6a3b ldr r3, [r7, #32]
800149e: f403 6380 and.w r3, r3, #1024 ; 0x400
80014a2: 2b00 cmp r3, #0
80014a4: d008 beq.n 80014b8 <HAL_CAN_IRQHandler+0x2b4>
((esrflags & CAN_ESR_BOFF) != 0U))
80014a6: 68fb ldr r3, [r7, #12]
80014a8: f003 0304 and.w r3, r3, #4
if (((interrupts & CAN_IT_BUSOFF) != 0U) &&
80014ac: 2b00 cmp r3, #0
80014ae: d003 beq.n 80014b8 <HAL_CAN_IRQHandler+0x2b4>
{
/* Set CAN error code to Bus-Off */
errorcode |= HAL_CAN_ERROR_BOF;
80014b0: 6a7b ldr r3, [r7, #36] ; 0x24
80014b2: f043 0304 orr.w r3, r3, #4
80014b6: 627b str r3, [r7, #36] ; 0x24
/* No need for clear of Error Bus-Off as read-only */
}
/* Check Last Error Code Flag */
if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) &&
80014b8: 6a3b ldr r3, [r7, #32]
80014ba: f403 6300 and.w r3, r3, #2048 ; 0x800
80014be: 2b00 cmp r3, #0
80014c0: d043 beq.n 800154a <HAL_CAN_IRQHandler+0x346>
((esrflags & CAN_ESR_LEC) != 0U))
80014c2: 68fb ldr r3, [r7, #12]
80014c4: f003 0370 and.w r3, r3, #112 ; 0x70
if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) &&
80014c8: 2b00 cmp r3, #0
80014ca: d03e beq.n 800154a <HAL_CAN_IRQHandler+0x346>
{
switch (esrflags & CAN_ESR_LEC)
80014cc: 68fb ldr r3, [r7, #12]
80014ce: f003 0370 and.w r3, r3, #112 ; 0x70
80014d2: 2b60 cmp r3, #96 ; 0x60
80014d4: d02b beq.n 800152e <HAL_CAN_IRQHandler+0x32a>
80014d6: 2b60 cmp r3, #96 ; 0x60
80014d8: d82e bhi.n 8001538 <HAL_CAN_IRQHandler+0x334>
80014da: 2b50 cmp r3, #80 ; 0x50
80014dc: d022 beq.n 8001524 <HAL_CAN_IRQHandler+0x320>
80014de: 2b50 cmp r3, #80 ; 0x50
80014e0: d82a bhi.n 8001538 <HAL_CAN_IRQHandler+0x334>
80014e2: 2b40 cmp r3, #64 ; 0x40
80014e4: d019 beq.n 800151a <HAL_CAN_IRQHandler+0x316>
80014e6: 2b40 cmp r3, #64 ; 0x40
80014e8: d826 bhi.n 8001538 <HAL_CAN_IRQHandler+0x334>
80014ea: 2b30 cmp r3, #48 ; 0x30
80014ec: d010 beq.n 8001510 <HAL_CAN_IRQHandler+0x30c>
80014ee: 2b30 cmp r3, #48 ; 0x30
80014f0: d822 bhi.n 8001538 <HAL_CAN_IRQHandler+0x334>
80014f2: 2b10 cmp r3, #16
80014f4: d002 beq.n 80014fc <HAL_CAN_IRQHandler+0x2f8>
80014f6: 2b20 cmp r3, #32
80014f8: d005 beq.n 8001506 <HAL_CAN_IRQHandler+0x302>
case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
/* Set CAN error code to CRC error */
errorcode |= HAL_CAN_ERROR_CRC;
break;
default:
break;
80014fa: e01d b.n 8001538 <HAL_CAN_IRQHandler+0x334>
errorcode |= HAL_CAN_ERROR_STF;
80014fc: 6a7b ldr r3, [r7, #36] ; 0x24
80014fe: f043 0308 orr.w r3, r3, #8
8001502: 627b str r3, [r7, #36] ; 0x24
break;
8001504: e019 b.n 800153a <HAL_CAN_IRQHandler+0x336>
errorcode |= HAL_CAN_ERROR_FOR;
8001506: 6a7b ldr r3, [r7, #36] ; 0x24
8001508: f043 0310 orr.w r3, r3, #16
800150c: 627b str r3, [r7, #36] ; 0x24
break;
800150e: e014 b.n 800153a <HAL_CAN_IRQHandler+0x336>
errorcode |= HAL_CAN_ERROR_ACK;
8001510: 6a7b ldr r3, [r7, #36] ; 0x24
8001512: f043 0320 orr.w r3, r3, #32
8001516: 627b str r3, [r7, #36] ; 0x24
break;
8001518: e00f b.n 800153a <HAL_CAN_IRQHandler+0x336>
errorcode |= HAL_CAN_ERROR_BR;
800151a: 6a7b ldr r3, [r7, #36] ; 0x24
800151c: f043 0340 orr.w r3, r3, #64 ; 0x40
8001520: 627b str r3, [r7, #36] ; 0x24
break;
8001522: e00a b.n 800153a <HAL_CAN_IRQHandler+0x336>
errorcode |= HAL_CAN_ERROR_BD;
8001524: 6a7b ldr r3, [r7, #36] ; 0x24
8001526: f043 0380 orr.w r3, r3, #128 ; 0x80
800152a: 627b str r3, [r7, #36] ; 0x24
break;
800152c: e005 b.n 800153a <HAL_CAN_IRQHandler+0x336>
errorcode |= HAL_CAN_ERROR_CRC;
800152e: 6a7b ldr r3, [r7, #36] ; 0x24
8001530: f443 7380 orr.w r3, r3, #256 ; 0x100
8001534: 627b str r3, [r7, #36] ; 0x24
break;
8001536: e000 b.n 800153a <HAL_CAN_IRQHandler+0x336>
break;
8001538: bf00 nop
}
/* Clear Last error code Flag */
CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC);
800153a: 687b ldr r3, [r7, #4]
800153c: 681b ldr r3, [r3, #0]
800153e: 699a ldr r2, [r3, #24]
8001540: 687b ldr r3, [r7, #4]
8001542: 681b ldr r3, [r3, #0]
8001544: f022 0270 bic.w r2, r2, #112 ; 0x70
8001548: 619a str r2, [r3, #24]
}
}
/* Clear ERRI Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI);
800154a: 687b ldr r3, [r7, #4]
800154c: 681b ldr r3, [r3, #0]
800154e: 2204 movs r2, #4
8001550: 605a str r2, [r3, #4]
}
/* Call the Error call Back in case of Errors */
if (errorcode != HAL_CAN_ERROR_NONE)
8001552: 6a7b ldr r3, [r7, #36] ; 0x24
8001554: 2b00 cmp r3, #0
8001556: d008 beq.n 800156a <HAL_CAN_IRQHandler+0x366>
{
/* Update error code in handle */
hcan->ErrorCode |= errorcode;
8001558: 687b ldr r3, [r7, #4]
800155a: 6a5a ldr r2, [r3, #36] ; 0x24
800155c: 6a7b ldr r3, [r7, #36] ; 0x24
800155e: 431a orrs r2, r3
8001560: 687b ldr r3, [r7, #4]
8001562: 625a str r2, [r3, #36] ; 0x24
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->ErrorCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_ErrorCallback(hcan);
8001564: 6878 ldr r0, [r7, #4]
8001566: f000 f868 bl 800163a <HAL_CAN_ErrorCallback>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
800156a: bf00 nop
800156c: 3728 adds r7, #40 ; 0x28
800156e: 46bd mov sp, r7
8001570: bd80 pop {r7, pc}
08001572 <HAL_CAN_TxMailbox0CompleteCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan)
{
8001572: b480 push {r7}
8001574: b083 sub sp, #12
8001576: af00 add r7, sp, #0
8001578: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the
user file
*/
}
800157a: bf00 nop
800157c: 370c adds r7, #12
800157e: 46bd mov sp, r7
8001580: f85d 7b04 ldr.w r7, [sp], #4
8001584: 4770 bx lr
08001586 <HAL_CAN_TxMailbox1CompleteCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan)
{
8001586: b480 push {r7}
8001588: b083 sub sp, #12
800158a: af00 add r7, sp, #0
800158c: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the
user file
*/
}
800158e: bf00 nop
8001590: 370c adds r7, #12
8001592: 46bd mov sp, r7
8001594: f85d 7b04 ldr.w r7, [sp], #4
8001598: 4770 bx lr
0800159a <HAL_CAN_TxMailbox2CompleteCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan)
{
800159a: b480 push {r7}
800159c: b083 sub sp, #12
800159e: af00 add r7, sp, #0
80015a0: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the
user file
*/
}
80015a2: bf00 nop
80015a4: 370c adds r7, #12
80015a6: 46bd mov sp, r7
80015a8: f85d 7b04 ldr.w r7, [sp], #4
80015ac: 4770 bx lr
080015ae <HAL_CAN_TxMailbox0AbortCallback>:
* @param hcan pointer to an CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan)
{
80015ae: b480 push {r7}
80015b0: b083 sub sp, #12
80015b2: af00 add r7, sp, #0
80015b4: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_TxMailbox0AbortCallback could be implemented in the
user file
*/
}
80015b6: bf00 nop
80015b8: 370c adds r7, #12
80015ba: 46bd mov sp, r7
80015bc: f85d 7b04 ldr.w r7, [sp], #4
80015c0: 4770 bx lr
080015c2 <HAL_CAN_TxMailbox1AbortCallback>:
* @param hcan pointer to an CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan)
{
80015c2: b480 push {r7}
80015c4: b083 sub sp, #12
80015c6: af00 add r7, sp, #0
80015c8: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_TxMailbox1AbortCallback could be implemented in the
user file
*/
}
80015ca: bf00 nop
80015cc: 370c adds r7, #12
80015ce: 46bd mov sp, r7
80015d0: f85d 7b04 ldr.w r7, [sp], #4
80015d4: 4770 bx lr
080015d6 <HAL_CAN_TxMailbox2AbortCallback>:
* @param hcan pointer to an CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan)
{
80015d6: b480 push {r7}
80015d8: b083 sub sp, #12
80015da: af00 add r7, sp, #0
80015dc: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_TxMailbox2AbortCallback could be implemented in the
user file
*/
}
80015de: bf00 nop
80015e0: 370c adds r7, #12
80015e2: 46bd mov sp, r7
80015e4: f85d 7b04 ldr.w r7, [sp], #4
80015e8: 4770 bx lr
080015ea <HAL_CAN_RxFifo0FullCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan)
{
80015ea: b480 push {r7}
80015ec: b083 sub sp, #12
80015ee: af00 add r7, sp, #0
80015f0: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_RxFifo0FullCallback could be implemented in the user
file
*/
}
80015f2: bf00 nop
80015f4: 370c adds r7, #12
80015f6: 46bd mov sp, r7
80015f8: f85d 7b04 ldr.w r7, [sp], #4
80015fc: 4770 bx lr
080015fe <HAL_CAN_RxFifo1FullCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan)
{
80015fe: b480 push {r7}
8001600: b083 sub sp, #12
8001602: af00 add r7, sp, #0
8001604: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_RxFifo1FullCallback could be implemented in the user
file
*/
}
8001606: bf00 nop
8001608: 370c adds r7, #12
800160a: 46bd mov sp, r7
800160c: f85d 7b04 ldr.w r7, [sp], #4
8001610: 4770 bx lr
08001612 <HAL_CAN_SleepCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan)
{
8001612: b480 push {r7}
8001614: b083 sub sp, #12
8001616: af00 add r7, sp, #0
8001618: 6078 str r0, [r7, #4]
UNUSED(hcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_SleepCallback could be implemented in the user file
*/
}
800161a: bf00 nop
800161c: 370c adds r7, #12
800161e: 46bd mov sp, r7
8001620: f85d 7b04 ldr.w r7, [sp], #4
8001624: 4770 bx lr
08001626 <HAL_CAN_WakeUpFromRxMsgCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan)
{
8001626: b480 push {r7}
8001628: b083 sub sp, #12
800162a: af00 add r7, sp, #0
800162c: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the
user file
*/
}
800162e: bf00 nop
8001630: 370c adds r7, #12
8001632: 46bd mov sp, r7
8001634: f85d 7b04 ldr.w r7, [sp], #4
8001638: 4770 bx lr
0800163a <HAL_CAN_ErrorCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
{
800163a: b480 push {r7}
800163c: b083 sub sp, #12
800163e: af00 add r7, sp, #0
8001640: 6078 str r0, [r7, #4]
UNUSED(hcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_ErrorCallback could be implemented in the user file
*/
}
8001642: bf00 nop
8001644: 370c adds r7, #12
8001646: 46bd mov sp, r7
8001648: f85d 7b04 ldr.w r7, [sp], #4
800164c: 4770 bx lr
...
08001650 <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8001650: b480 push {r7}
8001652: b085 sub sp, #20
8001654: af00 add r7, sp, #0
8001656: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8001658: 687b ldr r3, [r7, #4]
800165a: f003 0307 and.w r3, r3, #7
800165e: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
8001660: 4b0c ldr r3, [pc, #48] ; (8001694 <__NVIC_SetPriorityGrouping+0x44>)
8001662: 68db ldr r3, [r3, #12]
8001664: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
8001666: 68ba ldr r2, [r7, #8]
8001668: f64f 03ff movw r3, #63743 ; 0xf8ff
800166c: 4013 ands r3, r2
800166e: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
8001670: 68fb ldr r3, [r7, #12]
8001672: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
8001674: 68bb ldr r3, [r7, #8]
8001676: 4313 orrs r3, r2
reg_value = (reg_value |
8001678: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000
800167c: f443 3300 orr.w r3, r3, #131072 ; 0x20000
8001680: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
8001682: 4a04 ldr r2, [pc, #16] ; (8001694 <__NVIC_SetPriorityGrouping+0x44>)
8001684: 68bb ldr r3, [r7, #8]
8001686: 60d3 str r3, [r2, #12]
}
8001688: bf00 nop
800168a: 3714 adds r7, #20
800168c: 46bd mov sp, r7
800168e: f85d 7b04 ldr.w r7, [sp], #4
8001692: 4770 bx lr
8001694: e000ed00 .word 0xe000ed00
08001698 <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
8001698: b480 push {r7}
800169a: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
800169c: 4b04 ldr r3, [pc, #16] ; (80016b0 <__NVIC_GetPriorityGrouping+0x18>)
800169e: 68db ldr r3, [r3, #12]
80016a0: 0a1b lsrs r3, r3, #8
80016a2: f003 0307 and.w r3, r3, #7
}
80016a6: 4618 mov r0, r3
80016a8: 46bd mov sp, r7
80016aa: f85d 7b04 ldr.w r7, [sp], #4
80016ae: 4770 bx lr
80016b0: e000ed00 .word 0xe000ed00
080016b4 <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
80016b4: b480 push {r7}
80016b6: b083 sub sp, #12
80016b8: af00 add r7, sp, #0
80016ba: 4603 mov r3, r0
80016bc: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
80016be: f997 3007 ldrsb.w r3, [r7, #7]
80016c2: 2b00 cmp r3, #0
80016c4: db0b blt.n 80016de <__NVIC_EnableIRQ+0x2a>
{
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
80016c6: 79fb ldrb r3, [r7, #7]
80016c8: f003 021f and.w r2, r3, #31
80016cc: 4907 ldr r1, [pc, #28] ; (80016ec <__NVIC_EnableIRQ+0x38>)
80016ce: f997 3007 ldrsb.w r3, [r7, #7]
80016d2: 095b lsrs r3, r3, #5
80016d4: 2001 movs r0, #1
80016d6: fa00 f202 lsl.w r2, r0, r2
80016da: f841 2023 str.w r2, [r1, r3, lsl #2]
}
}
80016de: bf00 nop
80016e0: 370c adds r7, #12
80016e2: 46bd mov sp, r7
80016e4: f85d 7b04 ldr.w r7, [sp], #4
80016e8: 4770 bx lr
80016ea: bf00 nop
80016ec: e000e100 .word 0xe000e100
080016f0 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
80016f0: b480 push {r7}
80016f2: b083 sub sp, #12
80016f4: af00 add r7, sp, #0
80016f6: 4603 mov r3, r0
80016f8: 6039 str r1, [r7, #0]
80016fa: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
80016fc: f997 3007 ldrsb.w r3, [r7, #7]
8001700: 2b00 cmp r3, #0
8001702: db0a blt.n 800171a <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8001704: 683b ldr r3, [r7, #0]
8001706: b2da uxtb r2, r3
8001708: 490c ldr r1, [pc, #48] ; (800173c <__NVIC_SetPriority+0x4c>)
800170a: f997 3007 ldrsb.w r3, [r7, #7]
800170e: 0112 lsls r2, r2, #4
8001710: b2d2 uxtb r2, r2
8001712: 440b add r3, r1
8001714: f883 2300 strb.w r2, [r3, #768] ; 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
8001718: e00a b.n 8001730 <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
800171a: 683b ldr r3, [r7, #0]
800171c: b2da uxtb r2, r3
800171e: 4908 ldr r1, [pc, #32] ; (8001740 <__NVIC_SetPriority+0x50>)
8001720: 79fb ldrb r3, [r7, #7]
8001722: f003 030f and.w r3, r3, #15
8001726: 3b04 subs r3, #4
8001728: 0112 lsls r2, r2, #4
800172a: b2d2 uxtb r2, r2
800172c: 440b add r3, r1
800172e: 761a strb r2, [r3, #24]
}
8001730: bf00 nop
8001732: 370c adds r7, #12
8001734: 46bd mov sp, r7
8001736: f85d 7b04 ldr.w r7, [sp], #4
800173a: 4770 bx lr
800173c: e000e100 .word 0xe000e100
8001740: e000ed00 .word 0xe000ed00
08001744 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
8001744: b480 push {r7}
8001746: b089 sub sp, #36 ; 0x24
8001748: af00 add r7, sp, #0
800174a: 60f8 str r0, [r7, #12]
800174c: 60b9 str r1, [r7, #8]
800174e: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8001750: 68fb ldr r3, [r7, #12]
8001752: f003 0307 and.w r3, r3, #7
8001756: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
8001758: 69fb ldr r3, [r7, #28]
800175a: f1c3 0307 rsb r3, r3, #7
800175e: 2b04 cmp r3, #4
8001760: bf28 it cs
8001762: 2304 movcs r3, #4
8001764: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
8001766: 69fb ldr r3, [r7, #28]
8001768: 3304 adds r3, #4
800176a: 2b06 cmp r3, #6
800176c: d902 bls.n 8001774 <NVIC_EncodePriority+0x30>
800176e: 69fb ldr r3, [r7, #28]
8001770: 3b03 subs r3, #3
8001772: e000 b.n 8001776 <NVIC_EncodePriority+0x32>
8001774: 2300 movs r3, #0
8001776: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8001778: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff
800177c: 69bb ldr r3, [r7, #24]
800177e: fa02 f303 lsl.w r3, r2, r3
8001782: 43da mvns r2, r3
8001784: 68bb ldr r3, [r7, #8]
8001786: 401a ands r2, r3
8001788: 697b ldr r3, [r7, #20]
800178a: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
800178c: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff
8001790: 697b ldr r3, [r7, #20]
8001792: fa01 f303 lsl.w r3, r1, r3
8001796: 43d9 mvns r1, r3
8001798: 687b ldr r3, [r7, #4]
800179a: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
800179c: 4313 orrs r3, r2
);
}
800179e: 4618 mov r0, r3
80017a0: 3724 adds r7, #36 ; 0x24
80017a2: 46bd mov sp, r7
80017a4: f85d 7b04 ldr.w r7, [sp], #4
80017a8: 4770 bx lr
...
080017ac <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
80017ac: b580 push {r7, lr}
80017ae: b082 sub sp, #8
80017b0: af00 add r7, sp, #0
80017b2: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
80017b4: 687b ldr r3, [r7, #4]
80017b6: 3b01 subs r3, #1
80017b8: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
80017bc: d301 bcc.n 80017c2 <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
80017be: 2301 movs r3, #1
80017c0: e00f b.n 80017e2 <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
80017c2: 4a0a ldr r2, [pc, #40] ; (80017ec <SysTick_Config+0x40>)
80017c4: 687b ldr r3, [r7, #4]
80017c6: 3b01 subs r3, #1
80017c8: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
80017ca: 210f movs r1, #15
80017cc: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff
80017d0: f7ff ff8e bl 80016f0 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
80017d4: 4b05 ldr r3, [pc, #20] ; (80017ec <SysTick_Config+0x40>)
80017d6: 2200 movs r2, #0
80017d8: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
80017da: 4b04 ldr r3, [pc, #16] ; (80017ec <SysTick_Config+0x40>)
80017dc: 2207 movs r2, #7
80017de: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
80017e0: 2300 movs r3, #0
}
80017e2: 4618 mov r0, r3
80017e4: 3708 adds r7, #8
80017e6: 46bd mov sp, r7
80017e8: bd80 pop {r7, pc}
80017ea: bf00 nop
80017ec: e000e010 .word 0xe000e010
080017f0 <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
80017f0: b580 push {r7, lr}
80017f2: b082 sub sp, #8
80017f4: af00 add r7, sp, #0
80017f6: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
80017f8: 6878 ldr r0, [r7, #4]
80017fa: f7ff ff29 bl 8001650 <__NVIC_SetPriorityGrouping>
}
80017fe: bf00 nop
8001800: 3708 adds r7, #8
8001802: 46bd mov sp, r7
8001804: bd80 pop {r7, pc}
08001806 <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15 as described in the table CORTEX_NVIC_Priority_Table
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8001806: b580 push {r7, lr}
8001808: b086 sub sp, #24
800180a: af00 add r7, sp, #0
800180c: 4603 mov r3, r0
800180e: 60b9 str r1, [r7, #8]
8001810: 607a str r2, [r7, #4]
8001812: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00U;
8001814: 2300 movs r3, #0
8001816: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
8001818: f7ff ff3e bl 8001698 <__NVIC_GetPriorityGrouping>
800181c: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
800181e: 687a ldr r2, [r7, #4]
8001820: 68b9 ldr r1, [r7, #8]
8001822: 6978 ldr r0, [r7, #20]
8001824: f7ff ff8e bl 8001744 <NVIC_EncodePriority>
8001828: 4602 mov r2, r0
800182a: f997 300f ldrsb.w r3, [r7, #15]
800182e: 4611 mov r1, r2
8001830: 4618 mov r0, r3
8001832: f7ff ff5d bl 80016f0 <__NVIC_SetPriority>
}
8001836: bf00 nop
8001838: 3718 adds r7, #24
800183a: 46bd mov sp, r7
800183c: bd80 pop {r7, pc}
0800183e <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
800183e: b580 push {r7, lr}
8001840: b082 sub sp, #8
8001842: af00 add r7, sp, #0
8001844: 4603 mov r3, r0
8001846: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
8001848: f997 3007 ldrsb.w r3, [r7, #7]
800184c: 4618 mov r0, r3
800184e: f7ff ff31 bl 80016b4 <__NVIC_EnableIRQ>
}
8001852: bf00 nop
8001854: 3708 adds r7, #8
8001856: 46bd mov sp, r7
8001858: bd80 pop {r7, pc}
0800185a <HAL_SYSTICK_Config>:
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
800185a: b580 push {r7, lr}
800185c: b082 sub sp, #8
800185e: af00 add r7, sp, #0
8001860: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
8001862: 6878 ldr r0, [r7, #4]
8001864: f7ff ffa2 bl 80017ac <SysTick_Config>
8001868: 4603 mov r3, r0
}
800186a: 4618 mov r0, r3
800186c: 3708 adds r7, #8
800186e: 46bd mov sp, r7
8001870: bd80 pop {r7, pc}
08001872 <HAL_DMA_Abort>:
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
{
8001872: b480 push {r7}
8001874: b083 sub sp, #12
8001876: af00 add r7, sp, #0
8001878: 6078 str r0, [r7, #4]
if(hdma->State != HAL_DMA_STATE_BUSY)
800187a: 687b ldr r3, [r7, #4]
800187c: f893 3021 ldrb.w r3, [r3, #33] ; 0x21
8001880: 2b02 cmp r3, #2
8001882: d008 beq.n 8001896 <HAL_DMA_Abort+0x24>
{
/* no transfer ongoing */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
8001884: 687b ldr r3, [r7, #4]
8001886: 2204 movs r2, #4
8001888: 639a str r2, [r3, #56] ; 0x38
/* Process Unlocked */
__HAL_UNLOCK(hdma);
800188a: 687b ldr r3, [r7, #4]
800188c: 2200 movs r2, #0
800188e: f883 2020 strb.w r2, [r3, #32]
return HAL_ERROR;
8001892: 2301 movs r3, #1
8001894: e020 b.n 80018d8 <HAL_DMA_Abort+0x66>
}
else
{
/* Disable DMA IT */
hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
8001896: 687b ldr r3, [r7, #4]
8001898: 681b ldr r3, [r3, #0]
800189a: 681a ldr r2, [r3, #0]
800189c: 687b ldr r3, [r7, #4]
800189e: 681b ldr r3, [r3, #0]
80018a0: f022 020e bic.w r2, r2, #14
80018a4: 601a str r2, [r3, #0]
/* Disable the channel */
hdma->Instance->CCR &= ~DMA_CCR_EN;
80018a6: 687b ldr r3, [r7, #4]
80018a8: 681b ldr r3, [r3, #0]
80018aa: 681a ldr r2, [r3, #0]
80018ac: 687b ldr r3, [r7, #4]
80018ae: 681b ldr r3, [r3, #0]
80018b0: f022 0201 bic.w r2, r2, #1
80018b4: 601a str r2, [r3, #0]
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_FLAG_GL1 << hdma->ChannelIndex);
80018b6: 687b ldr r3, [r7, #4]
80018b8: 6c1a ldr r2, [r3, #64] ; 0x40
80018ba: 687b ldr r3, [r7, #4]
80018bc: 6bdb ldr r3, [r3, #60] ; 0x3c
80018be: 2101 movs r1, #1
80018c0: fa01 f202 lsl.w r2, r1, r2
80018c4: 605a str r2, [r3, #4]
}
/* Change the DMA state*/
hdma->State = HAL_DMA_STATE_READY;
80018c6: 687b ldr r3, [r7, #4]
80018c8: 2201 movs r2, #1
80018ca: f883 2021 strb.w r2, [r3, #33] ; 0x21
/* Process Unlocked */
__HAL_UNLOCK(hdma);
80018ce: 687b ldr r3, [r7, #4]
80018d0: 2200 movs r2, #0
80018d2: f883 2020 strb.w r2, [r3, #32]
return HAL_OK;
80018d6: 2300 movs r3, #0
}
80018d8: 4618 mov r0, r3
80018da: 370c adds r7, #12
80018dc: 46bd mov sp, r7
80018de: f85d 7b04 ldr.w r7, [sp], #4
80018e2: 4770 bx lr
080018e4 <HAL_DMA_Abort_IT>:
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
{
80018e4: b580 push {r7, lr}
80018e6: b084 sub sp, #16
80018e8: af00 add r7, sp, #0
80018ea: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
80018ec: 2300 movs r3, #0
80018ee: 73fb strb r3, [r7, #15]
if(HAL_DMA_STATE_BUSY != hdma->State)
80018f0: 687b ldr r3, [r7, #4]
80018f2: f893 3021 ldrb.w r3, [r3, #33] ; 0x21
80018f6: 2b02 cmp r3, #2
80018f8: d005 beq.n 8001906 <HAL_DMA_Abort_IT+0x22>
{
/* no transfer ongoing */
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
80018fa: 687b ldr r3, [r7, #4]
80018fc: 2204 movs r2, #4
80018fe: 639a str r2, [r3, #56] ; 0x38
status = HAL_ERROR;
8001900: 2301 movs r3, #1
8001902: 73fb strb r3, [r7, #15]
8001904: e027 b.n 8001956 <HAL_DMA_Abort_IT+0x72>
}
else
{
/* Disable DMA IT */
hdma->Instance->CCR &= ~(DMA_IT_TC | DMA_IT_HT | DMA_IT_TE);
8001906: 687b ldr r3, [r7, #4]
8001908: 681b ldr r3, [r3, #0]
800190a: 681a ldr r2, [r3, #0]
800190c: 687b ldr r3, [r7, #4]
800190e: 681b ldr r3, [r3, #0]
8001910: f022 020e bic.w r2, r2, #14
8001914: 601a str r2, [r3, #0]
/* Disable the channel */
hdma->Instance->CCR &= ~DMA_CCR_EN;
8001916: 687b ldr r3, [r7, #4]
8001918: 681b ldr r3, [r3, #0]
800191a: 681a ldr r2, [r3, #0]
800191c: 687b ldr r3, [r7, #4]
800191e: 681b ldr r3, [r3, #0]
8001920: f022 0201 bic.w r2, r2, #1
8001924: 601a str r2, [r3, #0]
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = DMA_FLAG_GL1 << hdma->ChannelIndex;
8001926: 687b ldr r3, [r7, #4]
8001928: 6c1a ldr r2, [r3, #64] ; 0x40
800192a: 687b ldr r3, [r7, #4]
800192c: 6bdb ldr r3, [r3, #60] ; 0x3c
800192e: 2101 movs r1, #1
8001930: fa01 f202 lsl.w r2, r1, r2
8001934: 605a str r2, [r3, #4]
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
8001936: 687b ldr r3, [r7, #4]
8001938: 2201 movs r2, #1
800193a: f883 2021 strb.w r2, [r3, #33] ; 0x21
/* Process Unlocked */
__HAL_UNLOCK(hdma);
800193e: 687b ldr r3, [r7, #4]
8001940: 2200 movs r2, #0
8001942: f883 2020 strb.w r2, [r3, #32]
/* Call User Abort callback */
if(hdma->XferAbortCallback != NULL)
8001946: 687b ldr r3, [r7, #4]
8001948: 6b5b ldr r3, [r3, #52] ; 0x34
800194a: 2b00 cmp r3, #0
800194c: d003 beq.n 8001956 <HAL_DMA_Abort_IT+0x72>
{
hdma->XferAbortCallback(hdma);
800194e: 687b ldr r3, [r7, #4]
8001950: 6b5b ldr r3, [r3, #52] ; 0x34
8001952: 6878 ldr r0, [r7, #4]
8001954: 4798 blx r3
}
}
return status;
8001956: 7bfb ldrb r3, [r7, #15]
}
8001958: 4618 mov r0, r3
800195a: 3710 adds r7, #16
800195c: 46bd mov sp, r7
800195e: bd80 pop {r7, pc}
08001960 <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
8001960: b480 push {r7}
8001962: b087 sub sp, #28
8001964: af00 add r7, sp, #0
8001966: 6078 str r0, [r7, #4]
8001968: 6039 str r1, [r7, #0]
uint32_t position = 0x00u;
800196a: 2300 movs r3, #0
800196c: 617b str r3, [r7, #20]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00u)
800196e: e14e b.n 8001c0e <HAL_GPIO_Init+0x2ae>
{
/* Get current io position */
iocurrent = (GPIO_Init->Pin) & (1uL << position);
8001970: 683b ldr r3, [r7, #0]
8001972: 681a ldr r2, [r3, #0]
8001974: 2101 movs r1, #1
8001976: 697b ldr r3, [r7, #20]
8001978: fa01 f303 lsl.w r3, r1, r3
800197c: 4013 ands r3, r2
800197e: 60fb str r3, [r7, #12]
if (iocurrent != 0x00u)
8001980: 68fb ldr r3, [r7, #12]
8001982: 2b00 cmp r3, #0
8001984: f000 8140 beq.w 8001c08 <HAL_GPIO_Init+0x2a8>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
8001988: 683b ldr r3, [r7, #0]
800198a: 685b ldr r3, [r3, #4]
800198c: f003 0303 and.w r3, r3, #3
8001990: 2b01 cmp r3, #1
8001992: d005 beq.n 80019a0 <HAL_GPIO_Init+0x40>
8001994: 683b ldr r3, [r7, #0]
8001996: 685b ldr r3, [r3, #4]
8001998: f003 0303 and.w r3, r3, #3
800199c: 2b02 cmp r3, #2
800199e: d130 bne.n 8001a02 <HAL_GPIO_Init+0xa2>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
80019a0: 687b ldr r3, [r7, #4]
80019a2: 689b ldr r3, [r3, #8]
80019a4: 613b str r3, [r7, #16]
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u));
80019a6: 697b ldr r3, [r7, #20]
80019a8: 005b lsls r3, r3, #1
80019aa: 2203 movs r2, #3
80019ac: fa02 f303 lsl.w r3, r2, r3
80019b0: 43db mvns r3, r3
80019b2: 693a ldr r2, [r7, #16]
80019b4: 4013 ands r3, r2
80019b6: 613b str r3, [r7, #16]
temp |= (GPIO_Init->Speed << (position * 2u));
80019b8: 683b ldr r3, [r7, #0]
80019ba: 68da ldr r2, [r3, #12]
80019bc: 697b ldr r3, [r7, #20]
80019be: 005b lsls r3, r3, #1
80019c0: fa02 f303 lsl.w r3, r2, r3
80019c4: 693a ldr r2, [r7, #16]
80019c6: 4313 orrs r3, r2
80019c8: 613b str r3, [r7, #16]
GPIOx->OSPEEDR = temp;
80019ca: 687b ldr r3, [r7, #4]
80019cc: 693a ldr r2, [r7, #16]
80019ce: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
80019d0: 687b ldr r3, [r7, #4]
80019d2: 685b ldr r3, [r3, #4]
80019d4: 613b str r3, [r7, #16]
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
80019d6: 2201 movs r2, #1
80019d8: 697b ldr r3, [r7, #20]
80019da: fa02 f303 lsl.w r3, r2, r3
80019de: 43db mvns r3, r3
80019e0: 693a ldr r2, [r7, #16]
80019e2: 4013 ands r3, r2
80019e4: 613b str r3, [r7, #16]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
80019e6: 683b ldr r3, [r7, #0]
80019e8: 685b ldr r3, [r3, #4]
80019ea: 091b lsrs r3, r3, #4
80019ec: f003 0201 and.w r2, r3, #1
80019f0: 697b ldr r3, [r7, #20]
80019f2: fa02 f303 lsl.w r3, r2, r3
80019f6: 693a ldr r2, [r7, #16]
80019f8: 4313 orrs r3, r2
80019fa: 613b str r3, [r7, #16]
GPIOx->OTYPER = temp;
80019fc: 687b ldr r3, [r7, #4]
80019fe: 693a ldr r2, [r7, #16]
8001a00: 605a str r2, [r3, #4]
}
if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
8001a02: 683b ldr r3, [r7, #0]
8001a04: 685b ldr r3, [r3, #4]
8001a06: f003 0303 and.w r3, r3, #3
8001a0a: 2b03 cmp r3, #3
8001a0c: d017 beq.n 8001a3e <HAL_GPIO_Init+0xde>
{
/* Check the Pull parameter */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
8001a0e: 687b ldr r3, [r7, #4]
8001a10: 68db ldr r3, [r3, #12]
8001a12: 613b str r3, [r7, #16]
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u));
8001a14: 697b ldr r3, [r7, #20]
8001a16: 005b lsls r3, r3, #1
8001a18: 2203 movs r2, #3
8001a1a: fa02 f303 lsl.w r3, r2, r3
8001a1e: 43db mvns r3, r3
8001a20: 693a ldr r2, [r7, #16]
8001a22: 4013 ands r3, r2
8001a24: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Pull) << (position * 2u));
8001a26: 683b ldr r3, [r7, #0]
8001a28: 689a ldr r2, [r3, #8]
8001a2a: 697b ldr r3, [r7, #20]
8001a2c: 005b lsls r3, r3, #1
8001a2e: fa02 f303 lsl.w r3, r2, r3
8001a32: 693a ldr r2, [r7, #16]
8001a34: 4313 orrs r3, r2
8001a36: 613b str r3, [r7, #16]
GPIOx->PUPDR = temp;
8001a38: 687b ldr r3, [r7, #4]
8001a3a: 693a ldr r2, [r7, #16]
8001a3c: 60da str r2, [r3, #12]
}
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Alternate function mode selection */
if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
8001a3e: 683b ldr r3, [r7, #0]
8001a40: 685b ldr r3, [r3, #4]
8001a42: f003 0303 and.w r3, r3, #3
8001a46: 2b02 cmp r3, #2
8001a48: d123 bne.n 8001a92 <HAL_GPIO_Init+0x132>
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3u];
8001a4a: 697b ldr r3, [r7, #20]
8001a4c: 08da lsrs r2, r3, #3
8001a4e: 687b ldr r3, [r7, #4]
8001a50: 3208 adds r2, #8
8001a52: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8001a56: 613b str r3, [r7, #16]
temp &= ~(0xFu << ((position & 0x07u) * 4u));
8001a58: 697b ldr r3, [r7, #20]
8001a5a: f003 0307 and.w r3, r3, #7
8001a5e: 009b lsls r3, r3, #2
8001a60: 220f movs r2, #15
8001a62: fa02 f303 lsl.w r3, r2, r3
8001a66: 43db mvns r3, r3
8001a68: 693a ldr r2, [r7, #16]
8001a6a: 4013 ands r3, r2
8001a6c: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
8001a6e: 683b ldr r3, [r7, #0]
8001a70: 691a ldr r2, [r3, #16]
8001a72: 697b ldr r3, [r7, #20]
8001a74: f003 0307 and.w r3, r3, #7
8001a78: 009b lsls r3, r3, #2
8001a7a: fa02 f303 lsl.w r3, r2, r3
8001a7e: 693a ldr r2, [r7, #16]
8001a80: 4313 orrs r3, r2
8001a82: 613b str r3, [r7, #16]
GPIOx->AFR[position >> 3u] = temp;
8001a84: 697b ldr r3, [r7, #20]
8001a86: 08da lsrs r2, r3, #3
8001a88: 687b ldr r3, [r7, #4]
8001a8a: 3208 adds r2, #8
8001a8c: 6939 ldr r1, [r7, #16]
8001a8e: f843 1022 str.w r1, [r3, r2, lsl #2]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
8001a92: 687b ldr r3, [r7, #4]
8001a94: 681b ldr r3, [r3, #0]
8001a96: 613b str r3, [r7, #16]
temp &= ~(GPIO_MODER_MODER0 << (position * 2u));
8001a98: 697b ldr r3, [r7, #20]
8001a9a: 005b lsls r3, r3, #1
8001a9c: 2203 movs r2, #3
8001a9e: fa02 f303 lsl.w r3, r2, r3
8001aa2: 43db mvns r3, r3
8001aa4: 693a ldr r2, [r7, #16]
8001aa6: 4013 ands r3, r2
8001aa8: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
8001aaa: 683b ldr r3, [r7, #0]
8001aac: 685b ldr r3, [r3, #4]
8001aae: f003 0203 and.w r2, r3, #3
8001ab2: 697b ldr r3, [r7, #20]
8001ab4: 005b lsls r3, r3, #1
8001ab6: fa02 f303 lsl.w r3, r2, r3
8001aba: 693a ldr r2, [r7, #16]
8001abc: 4313 orrs r3, r2
8001abe: 613b str r3, [r7, #16]
GPIOx->MODER = temp;
8001ac0: 687b ldr r3, [r7, #4]
8001ac2: 693a ldr r2, [r7, #16]
8001ac4: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
8001ac6: 683b ldr r3, [r7, #0]
8001ac8: 685b ldr r3, [r3, #4]
8001aca: f403 3340 and.w r3, r3, #196608 ; 0x30000
8001ace: 2b00 cmp r3, #0
8001ad0: f000 809a beq.w 8001c08 <HAL_GPIO_Init+0x2a8>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8001ad4: 4b55 ldr r3, [pc, #340] ; (8001c2c <HAL_GPIO_Init+0x2cc>)
8001ad6: 699b ldr r3, [r3, #24]
8001ad8: 4a54 ldr r2, [pc, #336] ; (8001c2c <HAL_GPIO_Init+0x2cc>)
8001ada: f043 0301 orr.w r3, r3, #1
8001ade: 6193 str r3, [r2, #24]
8001ae0: 4b52 ldr r3, [pc, #328] ; (8001c2c <HAL_GPIO_Init+0x2cc>)
8001ae2: 699b ldr r3, [r3, #24]
8001ae4: f003 0301 and.w r3, r3, #1
8001ae8: 60bb str r3, [r7, #8]
8001aea: 68bb ldr r3, [r7, #8]
temp = SYSCFG->EXTICR[position >> 2u];
8001aec: 4a50 ldr r2, [pc, #320] ; (8001c30 <HAL_GPIO_Init+0x2d0>)
8001aee: 697b ldr r3, [r7, #20]
8001af0: 089b lsrs r3, r3, #2
8001af2: 3302 adds r3, #2
8001af4: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8001af8: 613b str r3, [r7, #16]
temp &= ~(0x0FuL << (4u * (position & 0x03u)));
8001afa: 697b ldr r3, [r7, #20]
8001afc: f003 0303 and.w r3, r3, #3
8001b00: 009b lsls r3, r3, #2
8001b02: 220f movs r2, #15
8001b04: fa02 f303 lsl.w r3, r2, r3
8001b08: 43db mvns r3, r3
8001b0a: 693a ldr r2, [r7, #16]
8001b0c: 4013 ands r3, r2
8001b0e: 613b str r3, [r7, #16]
temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
8001b10: 687b ldr r3, [r7, #4]
8001b12: f1b3 4f90 cmp.w r3, #1207959552 ; 0x48000000
8001b16: d013 beq.n 8001b40 <HAL_GPIO_Init+0x1e0>
8001b18: 687b ldr r3, [r7, #4]
8001b1a: 4a46 ldr r2, [pc, #280] ; (8001c34 <HAL_GPIO_Init+0x2d4>)
8001b1c: 4293 cmp r3, r2
8001b1e: d00d beq.n 8001b3c <HAL_GPIO_Init+0x1dc>
8001b20: 687b ldr r3, [r7, #4]
8001b22: 4a45 ldr r2, [pc, #276] ; (8001c38 <HAL_GPIO_Init+0x2d8>)
8001b24: 4293 cmp r3, r2
8001b26: d007 beq.n 8001b38 <HAL_GPIO_Init+0x1d8>
8001b28: 687b ldr r3, [r7, #4]
8001b2a: 4a44 ldr r2, [pc, #272] ; (8001c3c <HAL_GPIO_Init+0x2dc>)
8001b2c: 4293 cmp r3, r2
8001b2e: d101 bne.n 8001b34 <HAL_GPIO_Init+0x1d4>
8001b30: 2303 movs r3, #3
8001b32: e006 b.n 8001b42 <HAL_GPIO_Init+0x1e2>
8001b34: 2305 movs r3, #5
8001b36: e004 b.n 8001b42 <HAL_GPIO_Init+0x1e2>
8001b38: 2302 movs r3, #2
8001b3a: e002 b.n 8001b42 <HAL_GPIO_Init+0x1e2>
8001b3c: 2301 movs r3, #1
8001b3e: e000 b.n 8001b42 <HAL_GPIO_Init+0x1e2>
8001b40: 2300 movs r3, #0
8001b42: 697a ldr r2, [r7, #20]
8001b44: f002 0203 and.w r2, r2, #3
8001b48: 0092 lsls r2, r2, #2
8001b4a: 4093 lsls r3, r2
8001b4c: 693a ldr r2, [r7, #16]
8001b4e: 4313 orrs r3, r2
8001b50: 613b str r3, [r7, #16]
SYSCFG->EXTICR[position >> 2u] = temp;
8001b52: 4937 ldr r1, [pc, #220] ; (8001c30 <HAL_GPIO_Init+0x2d0>)
8001b54: 697b ldr r3, [r7, #20]
8001b56: 089b lsrs r3, r3, #2
8001b58: 3302 adds r3, #2
8001b5a: 693a ldr r2, [r7, #16]
8001b5c: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Clear EXTI line configuration */
temp = EXTI->IMR;
8001b60: 4b37 ldr r3, [pc, #220] ; (8001c40 <HAL_GPIO_Init+0x2e0>)
8001b62: 681b ldr r3, [r3, #0]
8001b64: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8001b66: 68fb ldr r3, [r7, #12]
8001b68: 43db mvns r3, r3
8001b6a: 693a ldr r2, [r7, #16]
8001b6c: 4013 ands r3, r2
8001b6e: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & EXTI_IT) != 0x00u)
8001b70: 683b ldr r3, [r7, #0]
8001b72: 685b ldr r3, [r3, #4]
8001b74: f403 3380 and.w r3, r3, #65536 ; 0x10000
8001b78: 2b00 cmp r3, #0
8001b7a: d003 beq.n 8001b84 <HAL_GPIO_Init+0x224>
{
temp |= iocurrent;
8001b7c: 693a ldr r2, [r7, #16]
8001b7e: 68fb ldr r3, [r7, #12]
8001b80: 4313 orrs r3, r2
8001b82: 613b str r3, [r7, #16]
}
EXTI->IMR = temp;
8001b84: 4a2e ldr r2, [pc, #184] ; (8001c40 <HAL_GPIO_Init+0x2e0>)
8001b86: 693b ldr r3, [r7, #16]
8001b88: 6013 str r3, [r2, #0]
temp = EXTI->EMR;
8001b8a: 4b2d ldr r3, [pc, #180] ; (8001c40 <HAL_GPIO_Init+0x2e0>)
8001b8c: 685b ldr r3, [r3, #4]
8001b8e: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8001b90: 68fb ldr r3, [r7, #12]
8001b92: 43db mvns r3, r3
8001b94: 693a ldr r2, [r7, #16]
8001b96: 4013 ands r3, r2
8001b98: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
8001b9a: 683b ldr r3, [r7, #0]
8001b9c: 685b ldr r3, [r3, #4]
8001b9e: f403 3300 and.w r3, r3, #131072 ; 0x20000
8001ba2: 2b00 cmp r3, #0
8001ba4: d003 beq.n 8001bae <HAL_GPIO_Init+0x24e>
{
temp |= iocurrent;
8001ba6: 693a ldr r2, [r7, #16]
8001ba8: 68fb ldr r3, [r7, #12]
8001baa: 4313 orrs r3, r2
8001bac: 613b str r3, [r7, #16]
}
EXTI->EMR = temp;
8001bae: 4a24 ldr r2, [pc, #144] ; (8001c40 <HAL_GPIO_Init+0x2e0>)
8001bb0: 693b ldr r3, [r7, #16]
8001bb2: 6053 str r3, [r2, #4]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
8001bb4: 4b22 ldr r3, [pc, #136] ; (8001c40 <HAL_GPIO_Init+0x2e0>)
8001bb6: 689b ldr r3, [r3, #8]
8001bb8: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8001bba: 68fb ldr r3, [r7, #12]
8001bbc: 43db mvns r3, r3
8001bbe: 693a ldr r2, [r7, #16]
8001bc0: 4013 ands r3, r2
8001bc2: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
8001bc4: 683b ldr r3, [r7, #0]
8001bc6: 685b ldr r3, [r3, #4]
8001bc8: f403 1380 and.w r3, r3, #1048576 ; 0x100000
8001bcc: 2b00 cmp r3, #0
8001bce: d003 beq.n 8001bd8 <HAL_GPIO_Init+0x278>
{
temp |= iocurrent;
8001bd0: 693a ldr r2, [r7, #16]
8001bd2: 68fb ldr r3, [r7, #12]
8001bd4: 4313 orrs r3, r2
8001bd6: 613b str r3, [r7, #16]
}
EXTI->RTSR = temp;
8001bd8: 4a19 ldr r2, [pc, #100] ; (8001c40 <HAL_GPIO_Init+0x2e0>)
8001bda: 693b ldr r3, [r7, #16]
8001bdc: 6093 str r3, [r2, #8]
temp = EXTI->FTSR;
8001bde: 4b18 ldr r3, [pc, #96] ; (8001c40 <HAL_GPIO_Init+0x2e0>)
8001be0: 68db ldr r3, [r3, #12]
8001be2: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8001be4: 68fb ldr r3, [r7, #12]
8001be6: 43db mvns r3, r3
8001be8: 693a ldr r2, [r7, #16]
8001bea: 4013 ands r3, r2
8001bec: 613b str r3, [r7, #16]
if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
8001bee: 683b ldr r3, [r7, #0]
8001bf0: 685b ldr r3, [r3, #4]
8001bf2: f403 1300 and.w r3, r3, #2097152 ; 0x200000
8001bf6: 2b00 cmp r3, #0
8001bf8: d003 beq.n 8001c02 <HAL_GPIO_Init+0x2a2>
{
temp |= iocurrent;
8001bfa: 693a ldr r2, [r7, #16]
8001bfc: 68fb ldr r3, [r7, #12]
8001bfe: 4313 orrs r3, r2
8001c00: 613b str r3, [r7, #16]
}
EXTI->FTSR = temp;
8001c02: 4a0f ldr r2, [pc, #60] ; (8001c40 <HAL_GPIO_Init+0x2e0>)
8001c04: 693b ldr r3, [r7, #16]
8001c06: 60d3 str r3, [r2, #12]
}
}
position++;
8001c08: 697b ldr r3, [r7, #20]
8001c0a: 3301 adds r3, #1
8001c0c: 617b str r3, [r7, #20]
while (((GPIO_Init->Pin) >> position) != 0x00u)
8001c0e: 683b ldr r3, [r7, #0]
8001c10: 681a ldr r2, [r3, #0]
8001c12: 697b ldr r3, [r7, #20]
8001c14: fa22 f303 lsr.w r3, r2, r3
8001c18: 2b00 cmp r3, #0
8001c1a: f47f aea9 bne.w 8001970 <HAL_GPIO_Init+0x10>
}
}
8001c1e: bf00 nop
8001c20: bf00 nop
8001c22: 371c adds r7, #28
8001c24: 46bd mov sp, r7
8001c26: f85d 7b04 ldr.w r7, [sp], #4
8001c2a: 4770 bx lr
8001c2c: 40021000 .word 0x40021000
8001c30: 40010000 .word 0x40010000
8001c34: 48000400 .word 0x48000400
8001c38: 48000800 .word 0x48000800
8001c3c: 48000c00 .word 0x48000c00
8001c40: 40010400 .word 0x40010400
08001c44 <HAL_GPIO_ReadPin>:
* @param GPIO_Pin specifies the port bit to read.
* This parameter can be GPIO_PIN_x where x can be (0..15).
* @retval The input port pin value.
*/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
8001c44: b480 push {r7}
8001c46: b085 sub sp, #20
8001c48: af00 add r7, sp, #0
8001c4a: 6078 str r0, [r7, #4]
8001c4c: 460b mov r3, r1
8001c4e: 807b strh r3, [r7, #2]
GPIO_PinState bitstatus;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
8001c50: 687b ldr r3, [r7, #4]
8001c52: 691a ldr r2, [r3, #16]
8001c54: 887b ldrh r3, [r7, #2]
8001c56: 4013 ands r3, r2
8001c58: 2b00 cmp r3, #0
8001c5a: d002 beq.n 8001c62 <HAL_GPIO_ReadPin+0x1e>
{
bitstatus = GPIO_PIN_SET;
8001c5c: 2301 movs r3, #1
8001c5e: 73fb strb r3, [r7, #15]
8001c60: e001 b.n 8001c66 <HAL_GPIO_ReadPin+0x22>
}
else
{
bitstatus = GPIO_PIN_RESET;
8001c62: 2300 movs r3, #0
8001c64: 73fb strb r3, [r7, #15]
}
return bitstatus;
8001c66: 7bfb ldrb r3, [r7, #15]
}
8001c68: 4618 mov r0, r3
8001c6a: 3714 adds r7, #20
8001c6c: 46bd mov sp, r7
8001c6e: f85d 7b04 ldr.w r7, [sp], #4
8001c72: 4770 bx lr
08001c74 <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
8001c74: b480 push {r7}
8001c76: b083 sub sp, #12
8001c78: af00 add r7, sp, #0
8001c7a: 6078 str r0, [r7, #4]
8001c7c: 460b mov r3, r1
8001c7e: 807b strh r3, [r7, #2]
8001c80: 4613 mov r3, r2
8001c82: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if(PinState != GPIO_PIN_RESET)
8001c84: 787b ldrb r3, [r7, #1]
8001c86: 2b00 cmp r3, #0
8001c88: d003 beq.n 8001c92 <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = (uint32_t)GPIO_Pin;
8001c8a: 887a ldrh r2, [r7, #2]
8001c8c: 687b ldr r3, [r7, #4]
8001c8e: 619a str r2, [r3, #24]
}
else
{
GPIOx->BRR = (uint32_t)GPIO_Pin;
}
}
8001c90: e002 b.n 8001c98 <HAL_GPIO_WritePin+0x24>
GPIOx->BRR = (uint32_t)GPIO_Pin;
8001c92: 887a ldrh r2, [r7, #2]
8001c94: 687b ldr r3, [r7, #4]
8001c96: 629a str r2, [r3, #40] ; 0x28
}
8001c98: bf00 nop
8001c9a: 370c adds r7, #12
8001c9c: 46bd mov sp, r7
8001c9e: f85d 7b04 ldr.w r7, [sp], #4
8001ca2: 4770 bx lr
08001ca4 <HAL_RCC_OscConfig>:
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8001ca4: b580 push {r7, lr}
8001ca6: f5ad 7d00 sub.w sp, sp, #512 ; 0x200
8001caa: af00 add r7, sp, #0
8001cac: f507 7300 add.w r3, r7, #512 ; 0x200
8001cb0: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
8001cb4: 6018 str r0, [r3, #0]
#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
uint32_t pll_config2;
#endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */
/* Check Null pointer */
if(RCC_OscInitStruct == NULL)
8001cb6: f507 7300 add.w r3, r7, #512 ; 0x200
8001cba: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
8001cbe: 681b ldr r3, [r3, #0]
8001cc0: 2b00 cmp r3, #0
8001cc2: d102 bne.n 8001cca <HAL_RCC_OscConfig+0x26>
{
return HAL_ERROR;
8001cc4: 2301 movs r3, #1
8001cc6: f001 b823 b.w 8002d10 <HAL_RCC_OscConfig+0x106c>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
8001cca: f507 7300 add.w r3, r7, #512 ; 0x200
8001cce: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
8001cd2: 681b ldr r3, [r3, #0]
8001cd4: 681b ldr r3, [r3, #0]
8001cd6: f003 0301 and.w r3, r3, #1
8001cda: 2b00 cmp r3, #0
8001cdc: f000 817d beq.w 8001fda <HAL_RCC_OscConfig+0x336>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
8001ce0: 4bbc ldr r3, [pc, #752] ; (8001fd4 <HAL_RCC_OscConfig+0x330>)
8001ce2: 685b ldr r3, [r3, #4]
8001ce4: f003 030c and.w r3, r3, #12
8001ce8: 2b04 cmp r3, #4
8001cea: d00c beq.n 8001d06 <HAL_RCC_OscConfig+0x62>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
8001cec: 4bb9 ldr r3, [pc, #740] ; (8001fd4 <HAL_RCC_OscConfig+0x330>)
8001cee: 685b ldr r3, [r3, #4]
8001cf0: f003 030c and.w r3, r3, #12
8001cf4: 2b08 cmp r3, #8
8001cf6: d15c bne.n 8001db2 <HAL_RCC_OscConfig+0x10e>
8001cf8: 4bb6 ldr r3, [pc, #728] ; (8001fd4 <HAL_RCC_OscConfig+0x330>)
8001cfa: 685b ldr r3, [r3, #4]
8001cfc: f403 3380 and.w r3, r3, #65536 ; 0x10000
8001d00: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8001d04: d155 bne.n 8001db2 <HAL_RCC_OscConfig+0x10e>
8001d06: f44f 3300 mov.w r3, #131072 ; 0x20000
8001d0a: f8c7 31f0 str.w r3, [r7, #496] ; 0x1f0
uint32_t result;
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8001d0e: f8d7 31f0 ldr.w r3, [r7, #496] ; 0x1f0
8001d12: fa93 f3a3 rbit r3, r3
8001d16: f8c7 31ec str.w r3, [r7, #492] ; 0x1ec
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
#endif
return result;
8001d1a: f8d7 31ec ldr.w r3, [r7, #492] ; 0x1ec
{
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8001d1e: fab3 f383 clz r3, r3
8001d22: b2db uxtb r3, r3
8001d24: 095b lsrs r3, r3, #5
8001d26: b2db uxtb r3, r3
8001d28: f043 0301 orr.w r3, r3, #1
8001d2c: b2db uxtb r3, r3
8001d2e: 2b01 cmp r3, #1
8001d30: d102 bne.n 8001d38 <HAL_RCC_OscConfig+0x94>
8001d32: 4ba8 ldr r3, [pc, #672] ; (8001fd4 <HAL_RCC_OscConfig+0x330>)
8001d34: 681b ldr r3, [r3, #0]
8001d36: e015 b.n 8001d64 <HAL_RCC_OscConfig+0xc0>
8001d38: f44f 3300 mov.w r3, #131072 ; 0x20000
8001d3c: f8c7 31e8 str.w r3, [r7, #488] ; 0x1e8
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8001d40: f8d7 31e8 ldr.w r3, [r7, #488] ; 0x1e8
8001d44: fa93 f3a3 rbit r3, r3
8001d48: f8c7 31e4 str.w r3, [r7, #484] ; 0x1e4
8001d4c: f44f 3300 mov.w r3, #131072 ; 0x20000
8001d50: f8c7 31e0 str.w r3, [r7, #480] ; 0x1e0
8001d54: f8d7 31e0 ldr.w r3, [r7, #480] ; 0x1e0
8001d58: fa93 f3a3 rbit r3, r3
8001d5c: f8c7 31dc str.w r3, [r7, #476] ; 0x1dc
8001d60: 4b9c ldr r3, [pc, #624] ; (8001fd4 <HAL_RCC_OscConfig+0x330>)
8001d62: 6a5b ldr r3, [r3, #36] ; 0x24
8001d64: f44f 3200 mov.w r2, #131072 ; 0x20000
8001d68: f8c7 21d8 str.w r2, [r7, #472] ; 0x1d8
8001d6c: f8d7 21d8 ldr.w r2, [r7, #472] ; 0x1d8
8001d70: fa92 f2a2 rbit r2, r2
8001d74: f8c7 21d4 str.w r2, [r7, #468] ; 0x1d4
return result;
8001d78: f8d7 21d4 ldr.w r2, [r7, #468] ; 0x1d4
8001d7c: fab2 f282 clz r2, r2
8001d80: b2d2 uxtb r2, r2
8001d82: f042 0220 orr.w r2, r2, #32
8001d86: b2d2 uxtb r2, r2
8001d88: f002 021f and.w r2, r2, #31
8001d8c: 2101 movs r1, #1
8001d8e: fa01 f202 lsl.w r2, r1, r2
8001d92: 4013 ands r3, r2
8001d94: 2b00 cmp r3, #0
8001d96: f000 811f beq.w 8001fd8 <HAL_RCC_OscConfig+0x334>
8001d9a: f507 7300 add.w r3, r7, #512 ; 0x200
8001d9e: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
8001da2: 681b ldr r3, [r3, #0]
8001da4: 685b ldr r3, [r3, #4]
8001da6: 2b00 cmp r3, #0
8001da8: f040 8116 bne.w 8001fd8 <HAL_RCC_OscConfig+0x334>
{
return HAL_ERROR;
8001dac: 2301 movs r3, #1
8001dae: f000 bfaf b.w 8002d10 <HAL_RCC_OscConfig+0x106c>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
8001db2: f507 7300 add.w r3, r7, #512 ; 0x200
8001db6: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
8001dba: 681b ldr r3, [r3, #0]
8001dbc: 685b ldr r3, [r3, #4]
8001dbe: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8001dc2: d106 bne.n 8001dd2 <HAL_RCC_OscConfig+0x12e>
8001dc4: 4b83 ldr r3, [pc, #524] ; (8001fd4 <HAL_RCC_OscConfig+0x330>)
8001dc6: 681b ldr r3, [r3, #0]
8001dc8: 4a82 ldr r2, [pc, #520] ; (8001fd4 <HAL_RCC_OscConfig+0x330>)
8001dca: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8001dce: 6013 str r3, [r2, #0]
8001dd0: e036 b.n 8001e40 <HAL_RCC_OscConfig+0x19c>
8001dd2: f507 7300 add.w r3, r7, #512 ; 0x200
8001dd6: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
8001dda: 681b ldr r3, [r3, #0]
8001ddc: 685b ldr r3, [r3, #4]
8001dde: 2b00 cmp r3, #0
8001de0: d10c bne.n 8001dfc <HAL_RCC_OscConfig+0x158>
8001de2: 4b7c ldr r3, [pc, #496] ; (8001fd4 <HAL_RCC_OscConfig+0x330>)
8001de4: 681b ldr r3, [r3, #0]
8001de6: 4a7b ldr r2, [pc, #492] ; (8001fd4 <HAL_RCC_OscConfig+0x330>)
8001de8: f423 3380 bic.w r3, r3, #65536 ; 0x10000
8001dec: 6013 str r3, [r2, #0]
8001dee: 4b79 ldr r3, [pc, #484] ; (8001fd4 <HAL_RCC_OscConfig+0x330>)
8001df0: 681b ldr r3, [r3, #0]
8001df2: 4a78 ldr r2, [pc, #480] ; (8001fd4 <HAL_RCC_OscConfig+0x330>)
8001df4: f423 2380 bic.w r3, r3, #262144 ; 0x40000
8001df8: 6013 str r3, [r2, #0]
8001dfa: e021 b.n 8001e40 <HAL_RCC_OscConfig+0x19c>
8001dfc: f507 7300 add.w r3, r7, #512 ; 0x200
8001e00: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
8001e04: 681b ldr r3, [r3, #0]
8001e06: 685b ldr r3, [r3, #4]
8001e08: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
8001e0c: d10c bne.n 8001e28 <HAL_RCC_OscConfig+0x184>
8001e0e: 4b71 ldr r3, [pc, #452] ; (8001fd4 <HAL_RCC_OscConfig+0x330>)
8001e10: 681b ldr r3, [r3, #0]
8001e12: 4a70 ldr r2, [pc, #448] ; (8001fd4 <HAL_RCC_OscConfig+0x330>)
8001e14: f443 2380 orr.w r3, r3, #262144 ; 0x40000
8001e18: 6013 str r3, [r2, #0]
8001e1a: 4b6e ldr r3, [pc, #440] ; (8001fd4 <HAL_RCC_OscConfig+0x330>)
8001e1c: 681b ldr r3, [r3, #0]
8001e1e: 4a6d ldr r2, [pc, #436] ; (8001fd4 <HAL_RCC_OscConfig+0x330>)
8001e20: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8001e24: 6013 str r3, [r2, #0]
8001e26: e00b b.n 8001e40 <HAL_RCC_OscConfig+0x19c>
8001e28: 4b6a ldr r3, [pc, #424] ; (8001fd4 <HAL_RCC_OscConfig+0x330>)
8001e2a: 681b ldr r3, [r3, #0]
8001e2c: 4a69 ldr r2, [pc, #420] ; (8001fd4 <HAL_RCC_OscConfig+0x330>)
8001e2e: f423 3380 bic.w r3, r3, #65536 ; 0x10000
8001e32: 6013 str r3, [r2, #0]
8001e34: 4b67 ldr r3, [pc, #412] ; (8001fd4 <HAL_RCC_OscConfig+0x330>)
8001e36: 681b ldr r3, [r3, #0]
8001e38: 4a66 ldr r2, [pc, #408] ; (8001fd4 <HAL_RCC_OscConfig+0x330>)
8001e3a: f423 2380 bic.w r3, r3, #262144 ; 0x40000
8001e3e: 6013 str r3, [r2, #0]
#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
/* Configure the HSE predivision factor --------------------------------*/
__HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
8001e40: 4b64 ldr r3, [pc, #400] ; (8001fd4 <HAL_RCC_OscConfig+0x330>)
8001e42: 6adb ldr r3, [r3, #44] ; 0x2c
8001e44: f023 020f bic.w r2, r3, #15
8001e48: f507 7300 add.w r3, r7, #512 ; 0x200
8001e4c: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
8001e50: 681b ldr r3, [r3, #0]
8001e52: 689b ldr r3, [r3, #8]
8001e54: 495f ldr r1, [pc, #380] ; (8001fd4 <HAL_RCC_OscConfig+0x330>)
8001e56: 4313 orrs r3, r2
8001e58: 62cb str r3, [r1, #44] ; 0x2c
#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
/* Check the HSE State */
if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
8001e5a: f507 7300 add.w r3, r7, #512 ; 0x200
8001e5e: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
8001e62: 681b ldr r3, [r3, #0]
8001e64: 685b ldr r3, [r3, #4]
8001e66: 2b00 cmp r3, #0
8001e68: d059 beq.n 8001f1e <HAL_RCC_OscConfig+0x27a>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8001e6a: f7fe fd7f bl 800096c <HAL_GetTick>
8001e6e: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8
/* Wait till HSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8001e72: e00a b.n 8001e8a <HAL_RCC_OscConfig+0x1e6>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
8001e74: f7fe fd7a bl 800096c <HAL_GetTick>
8001e78: 4602 mov r2, r0
8001e7a: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8
8001e7e: 1ad3 subs r3, r2, r3
8001e80: 2b64 cmp r3, #100 ; 0x64
8001e82: d902 bls.n 8001e8a <HAL_RCC_OscConfig+0x1e6>
{
return HAL_TIMEOUT;
8001e84: 2303 movs r3, #3
8001e86: f000 bf43 b.w 8002d10 <HAL_RCC_OscConfig+0x106c>
8001e8a: f44f 3300 mov.w r3, #131072 ; 0x20000
8001e8e: f8c7 31d0 str.w r3, [r7, #464] ; 0x1d0
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8001e92: f8d7 31d0 ldr.w r3, [r7, #464] ; 0x1d0
8001e96: fa93 f3a3 rbit r3, r3
8001e9a: f8c7 31cc str.w r3, [r7, #460] ; 0x1cc
return result;
8001e9e: f8d7 31cc ldr.w r3, [r7, #460] ; 0x1cc
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8001ea2: fab3 f383 clz r3, r3
8001ea6: b2db uxtb r3, r3
8001ea8: 095b lsrs r3, r3, #5
8001eaa: b2db uxtb r3, r3
8001eac: f043 0301 orr.w r3, r3, #1
8001eb0: b2db uxtb r3, r3
8001eb2: 2b01 cmp r3, #1
8001eb4: d102 bne.n 8001ebc <HAL_RCC_OscConfig+0x218>
8001eb6: 4b47 ldr r3, [pc, #284] ; (8001fd4 <HAL_RCC_OscConfig+0x330>)
8001eb8: 681b ldr r3, [r3, #0]
8001eba: e015 b.n 8001ee8 <HAL_RCC_OscConfig+0x244>
8001ebc: f44f 3300 mov.w r3, #131072 ; 0x20000
8001ec0: f8c7 31c8 str.w r3, [r7, #456] ; 0x1c8
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8001ec4: f8d7 31c8 ldr.w r3, [r7, #456] ; 0x1c8
8001ec8: fa93 f3a3 rbit r3, r3
8001ecc: f8c7 31c4 str.w r3, [r7, #452] ; 0x1c4
8001ed0: f44f 3300 mov.w r3, #131072 ; 0x20000
8001ed4: f8c7 31c0 str.w r3, [r7, #448] ; 0x1c0
8001ed8: f8d7 31c0 ldr.w r3, [r7, #448] ; 0x1c0
8001edc: fa93 f3a3 rbit r3, r3
8001ee0: f8c7 31bc str.w r3, [r7, #444] ; 0x1bc
8001ee4: 4b3b ldr r3, [pc, #236] ; (8001fd4 <HAL_RCC_OscConfig+0x330>)
8001ee6: 6a5b ldr r3, [r3, #36] ; 0x24
8001ee8: f44f 3200 mov.w r2, #131072 ; 0x20000
8001eec: f8c7 21b8 str.w r2, [r7, #440] ; 0x1b8
8001ef0: f8d7 21b8 ldr.w r2, [r7, #440] ; 0x1b8
8001ef4: fa92 f2a2 rbit r2, r2
8001ef8: f8c7 21b4 str.w r2, [r7, #436] ; 0x1b4
return result;
8001efc: f8d7 21b4 ldr.w r2, [r7, #436] ; 0x1b4
8001f00: fab2 f282 clz r2, r2
8001f04: b2d2 uxtb r2, r2
8001f06: f042 0220 orr.w r2, r2, #32
8001f0a: b2d2 uxtb r2, r2
8001f0c: f002 021f and.w r2, r2, #31
8001f10: 2101 movs r1, #1
8001f12: fa01 f202 lsl.w r2, r1, r2
8001f16: 4013 ands r3, r2
8001f18: 2b00 cmp r3, #0
8001f1a: d0ab beq.n 8001e74 <HAL_RCC_OscConfig+0x1d0>
8001f1c: e05d b.n 8001fda <HAL_RCC_OscConfig+0x336>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8001f1e: f7fe fd25 bl 800096c <HAL_GetTick>
8001f22: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8
/* Wait till HSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8001f26: e00a b.n 8001f3e <HAL_RCC_OscConfig+0x29a>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
8001f28: f7fe fd20 bl 800096c <HAL_GetTick>
8001f2c: 4602 mov r2, r0
8001f2e: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8
8001f32: 1ad3 subs r3, r2, r3
8001f34: 2b64 cmp r3, #100 ; 0x64
8001f36: d902 bls.n 8001f3e <HAL_RCC_OscConfig+0x29a>
{
return HAL_TIMEOUT;
8001f38: 2303 movs r3, #3
8001f3a: f000 bee9 b.w 8002d10 <HAL_RCC_OscConfig+0x106c>
8001f3e: f44f 3300 mov.w r3, #131072 ; 0x20000
8001f42: f8c7 31b0 str.w r3, [r7, #432] ; 0x1b0
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8001f46: f8d7 31b0 ldr.w r3, [r7, #432] ; 0x1b0
8001f4a: fa93 f3a3 rbit r3, r3
8001f4e: f8c7 31ac str.w r3, [r7, #428] ; 0x1ac
return result;
8001f52: f8d7 31ac ldr.w r3, [r7, #428] ; 0x1ac
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8001f56: fab3 f383 clz r3, r3
8001f5a: b2db uxtb r3, r3
8001f5c: 095b lsrs r3, r3, #5
8001f5e: b2db uxtb r3, r3
8001f60: f043 0301 orr.w r3, r3, #1
8001f64: b2db uxtb r3, r3
8001f66: 2b01 cmp r3, #1
8001f68: d102 bne.n 8001f70 <HAL_RCC_OscConfig+0x2cc>
8001f6a: 4b1a ldr r3, [pc, #104] ; (8001fd4 <HAL_RCC_OscConfig+0x330>)
8001f6c: 681b ldr r3, [r3, #0]
8001f6e: e015 b.n 8001f9c <HAL_RCC_OscConfig+0x2f8>
8001f70: f44f 3300 mov.w r3, #131072 ; 0x20000
8001f74: f8c7 31a8 str.w r3, [r7, #424] ; 0x1a8
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8001f78: f8d7 31a8 ldr.w r3, [r7, #424] ; 0x1a8
8001f7c: fa93 f3a3 rbit r3, r3
8001f80: f8c7 31a4 str.w r3, [r7, #420] ; 0x1a4
8001f84: f44f 3300 mov.w r3, #131072 ; 0x20000
8001f88: f8c7 31a0 str.w r3, [r7, #416] ; 0x1a0
8001f8c: f8d7 31a0 ldr.w r3, [r7, #416] ; 0x1a0
8001f90: fa93 f3a3 rbit r3, r3
8001f94: f8c7 319c str.w r3, [r7, #412] ; 0x19c
8001f98: 4b0e ldr r3, [pc, #56] ; (8001fd4 <HAL_RCC_OscConfig+0x330>)
8001f9a: 6a5b ldr r3, [r3, #36] ; 0x24
8001f9c: f44f 3200 mov.w r2, #131072 ; 0x20000
8001fa0: f8c7 2198 str.w r2, [r7, #408] ; 0x198
8001fa4: f8d7 2198 ldr.w r2, [r7, #408] ; 0x198
8001fa8: fa92 f2a2 rbit r2, r2
8001fac: f8c7 2194 str.w r2, [r7, #404] ; 0x194
return result;
8001fb0: f8d7 2194 ldr.w r2, [r7, #404] ; 0x194
8001fb4: fab2 f282 clz r2, r2
8001fb8: b2d2 uxtb r2, r2
8001fba: f042 0220 orr.w r2, r2, #32
8001fbe: b2d2 uxtb r2, r2
8001fc0: f002 021f and.w r2, r2, #31
8001fc4: 2101 movs r1, #1
8001fc6: fa01 f202 lsl.w r2, r1, r2
8001fca: 4013 ands r3, r2
8001fcc: 2b00 cmp r3, #0
8001fce: d1ab bne.n 8001f28 <HAL_RCC_OscConfig+0x284>
8001fd0: e003 b.n 8001fda <HAL_RCC_OscConfig+0x336>
8001fd2: bf00 nop
8001fd4: 40021000 .word 0x40021000
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8001fd8: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
8001fda: f507 7300 add.w r3, r7, #512 ; 0x200
8001fde: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
8001fe2: 681b ldr r3, [r3, #0]
8001fe4: 681b ldr r3, [r3, #0]
8001fe6: f003 0302 and.w r3, r3, #2
8001fea: 2b00 cmp r3, #0
8001fec: f000 817d beq.w 80022ea <HAL_RCC_OscConfig+0x646>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
8001ff0: 4ba6 ldr r3, [pc, #664] ; (800228c <HAL_RCC_OscConfig+0x5e8>)
8001ff2: 685b ldr r3, [r3, #4]
8001ff4: f003 030c and.w r3, r3, #12
8001ff8: 2b00 cmp r3, #0
8001ffa: d00b beq.n 8002014 <HAL_RCC_OscConfig+0x370>
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)))
8001ffc: 4ba3 ldr r3, [pc, #652] ; (800228c <HAL_RCC_OscConfig+0x5e8>)
8001ffe: 685b ldr r3, [r3, #4]
8002000: f003 030c and.w r3, r3, #12
8002004: 2b08 cmp r3, #8
8002006: d172 bne.n 80020ee <HAL_RCC_OscConfig+0x44a>
8002008: 4ba0 ldr r3, [pc, #640] ; (800228c <HAL_RCC_OscConfig+0x5e8>)
800200a: 685b ldr r3, [r3, #4]
800200c: f403 3380 and.w r3, r3, #65536 ; 0x10000
8002010: 2b00 cmp r3, #0
8002012: d16c bne.n 80020ee <HAL_RCC_OscConfig+0x44a>
8002014: 2302 movs r3, #2
8002016: f8c7 3190 str.w r3, [r7, #400] ; 0x190
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
800201a: f8d7 3190 ldr.w r3, [r7, #400] ; 0x190
800201e: fa93 f3a3 rbit r3, r3
8002022: f8c7 318c str.w r3, [r7, #396] ; 0x18c
return result;
8002026: f8d7 318c ldr.w r3, [r7, #396] ; 0x18c
{
/* When HSI is used as system clock it will not disabled */
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
800202a: fab3 f383 clz r3, r3
800202e: b2db uxtb r3, r3
8002030: 095b lsrs r3, r3, #5
8002032: b2db uxtb r3, r3
8002034: f043 0301 orr.w r3, r3, #1
8002038: b2db uxtb r3, r3
800203a: 2b01 cmp r3, #1
800203c: d102 bne.n 8002044 <HAL_RCC_OscConfig+0x3a0>
800203e: 4b93 ldr r3, [pc, #588] ; (800228c <HAL_RCC_OscConfig+0x5e8>)
8002040: 681b ldr r3, [r3, #0]
8002042: e013 b.n 800206c <HAL_RCC_OscConfig+0x3c8>
8002044: 2302 movs r3, #2
8002046: f8c7 3188 str.w r3, [r7, #392] ; 0x188
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
800204a: f8d7 3188 ldr.w r3, [r7, #392] ; 0x188
800204e: fa93 f3a3 rbit r3, r3
8002052: f8c7 3184 str.w r3, [r7, #388] ; 0x184
8002056: 2302 movs r3, #2
8002058: f8c7 3180 str.w r3, [r7, #384] ; 0x180
800205c: f8d7 3180 ldr.w r3, [r7, #384] ; 0x180
8002060: fa93 f3a3 rbit r3, r3
8002064: f8c7 317c str.w r3, [r7, #380] ; 0x17c
8002068: 4b88 ldr r3, [pc, #544] ; (800228c <HAL_RCC_OscConfig+0x5e8>)
800206a: 6a5b ldr r3, [r3, #36] ; 0x24
800206c: 2202 movs r2, #2
800206e: f8c7 2178 str.w r2, [r7, #376] ; 0x178
8002072: f8d7 2178 ldr.w r2, [r7, #376] ; 0x178
8002076: fa92 f2a2 rbit r2, r2
800207a: f8c7 2174 str.w r2, [r7, #372] ; 0x174
return result;
800207e: f8d7 2174 ldr.w r2, [r7, #372] ; 0x174
8002082: fab2 f282 clz r2, r2
8002086: b2d2 uxtb r2, r2
8002088: f042 0220 orr.w r2, r2, #32
800208c: b2d2 uxtb r2, r2
800208e: f002 021f and.w r2, r2, #31
8002092: 2101 movs r1, #1
8002094: fa01 f202 lsl.w r2, r1, r2
8002098: 4013 ands r3, r2
800209a: 2b00 cmp r3, #0
800209c: d00a beq.n 80020b4 <HAL_RCC_OscConfig+0x410>
800209e: f507 7300 add.w r3, r7, #512 ; 0x200
80020a2: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
80020a6: 681b ldr r3, [r3, #0]
80020a8: 691b ldr r3, [r3, #16]
80020aa: 2b01 cmp r3, #1
80020ac: d002 beq.n 80020b4 <HAL_RCC_OscConfig+0x410>
{
return HAL_ERROR;
80020ae: 2301 movs r3, #1
80020b0: f000 be2e b.w 8002d10 <HAL_RCC_OscConfig+0x106c>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
80020b4: 4b75 ldr r3, [pc, #468] ; (800228c <HAL_RCC_OscConfig+0x5e8>)
80020b6: 681b ldr r3, [r3, #0]
80020b8: f023 02f8 bic.w r2, r3, #248 ; 0xf8
80020bc: f507 7300 add.w r3, r7, #512 ; 0x200
80020c0: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
80020c4: 681b ldr r3, [r3, #0]
80020c6: 695b ldr r3, [r3, #20]
80020c8: 21f8 movs r1, #248 ; 0xf8
80020ca: f8c7 1170 str.w r1, [r7, #368] ; 0x170
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80020ce: f8d7 1170 ldr.w r1, [r7, #368] ; 0x170
80020d2: fa91 f1a1 rbit r1, r1
80020d6: f8c7 116c str.w r1, [r7, #364] ; 0x16c
return result;
80020da: f8d7 116c ldr.w r1, [r7, #364] ; 0x16c
80020de: fab1 f181 clz r1, r1
80020e2: b2c9 uxtb r1, r1
80020e4: 408b lsls r3, r1
80020e6: 4969 ldr r1, [pc, #420] ; (800228c <HAL_RCC_OscConfig+0x5e8>)
80020e8: 4313 orrs r3, r2
80020ea: 600b str r3, [r1, #0]
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
80020ec: e0fd b.n 80022ea <HAL_RCC_OscConfig+0x646>
}
}
else
{
/* Check the HSI State */
if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
80020ee: f507 7300 add.w r3, r7, #512 ; 0x200
80020f2: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
80020f6: 681b ldr r3, [r3, #0]
80020f8: 691b ldr r3, [r3, #16]
80020fa: 2b00 cmp r3, #0
80020fc: f000 8088 beq.w 8002210 <HAL_RCC_OscConfig+0x56c>
8002100: 2301 movs r3, #1
8002102: f8c7 3168 str.w r3, [r7, #360] ; 0x168
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002106: f8d7 3168 ldr.w r3, [r7, #360] ; 0x168
800210a: fa93 f3a3 rbit r3, r3
800210e: f8c7 3164 str.w r3, [r7, #356] ; 0x164
return result;
8002112: f8d7 3164 ldr.w r3, [r7, #356] ; 0x164
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
8002116: fab3 f383 clz r3, r3
800211a: b2db uxtb r3, r3
800211c: f103 5384 add.w r3, r3, #276824064 ; 0x10800000
8002120: f503 1384 add.w r3, r3, #1081344 ; 0x108000
8002124: 009b lsls r3, r3, #2
8002126: 461a mov r2, r3
8002128: 2301 movs r3, #1
800212a: 6013 str r3, [r2, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
800212c: f7fe fc1e bl 800096c <HAL_GetTick>
8002130: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8002134: e00a b.n 800214c <HAL_RCC_OscConfig+0x4a8>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
8002136: f7fe fc19 bl 800096c <HAL_GetTick>
800213a: 4602 mov r2, r0
800213c: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8
8002140: 1ad3 subs r3, r2, r3
8002142: 2b02 cmp r3, #2
8002144: d902 bls.n 800214c <HAL_RCC_OscConfig+0x4a8>
{
return HAL_TIMEOUT;
8002146: 2303 movs r3, #3
8002148: f000 bde2 b.w 8002d10 <HAL_RCC_OscConfig+0x106c>
800214c: 2302 movs r3, #2
800214e: f8c7 3160 str.w r3, [r7, #352] ; 0x160
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002152: f8d7 3160 ldr.w r3, [r7, #352] ; 0x160
8002156: fa93 f3a3 rbit r3, r3
800215a: f8c7 315c str.w r3, [r7, #348] ; 0x15c
return result;
800215e: f8d7 315c ldr.w r3, [r7, #348] ; 0x15c
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8002162: fab3 f383 clz r3, r3
8002166: b2db uxtb r3, r3
8002168: 095b lsrs r3, r3, #5
800216a: b2db uxtb r3, r3
800216c: f043 0301 orr.w r3, r3, #1
8002170: b2db uxtb r3, r3
8002172: 2b01 cmp r3, #1
8002174: d102 bne.n 800217c <HAL_RCC_OscConfig+0x4d8>
8002176: 4b45 ldr r3, [pc, #276] ; (800228c <HAL_RCC_OscConfig+0x5e8>)
8002178: 681b ldr r3, [r3, #0]
800217a: e013 b.n 80021a4 <HAL_RCC_OscConfig+0x500>
800217c: 2302 movs r3, #2
800217e: f8c7 3158 str.w r3, [r7, #344] ; 0x158
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002182: f8d7 3158 ldr.w r3, [r7, #344] ; 0x158
8002186: fa93 f3a3 rbit r3, r3
800218a: f8c7 3154 str.w r3, [r7, #340] ; 0x154
800218e: 2302 movs r3, #2
8002190: f8c7 3150 str.w r3, [r7, #336] ; 0x150
8002194: f8d7 3150 ldr.w r3, [r7, #336] ; 0x150
8002198: fa93 f3a3 rbit r3, r3
800219c: f8c7 314c str.w r3, [r7, #332] ; 0x14c
80021a0: 4b3a ldr r3, [pc, #232] ; (800228c <HAL_RCC_OscConfig+0x5e8>)
80021a2: 6a5b ldr r3, [r3, #36] ; 0x24
80021a4: 2202 movs r2, #2
80021a6: f8c7 2148 str.w r2, [r7, #328] ; 0x148
80021aa: f8d7 2148 ldr.w r2, [r7, #328] ; 0x148
80021ae: fa92 f2a2 rbit r2, r2
80021b2: f8c7 2144 str.w r2, [r7, #324] ; 0x144
return result;
80021b6: f8d7 2144 ldr.w r2, [r7, #324] ; 0x144
80021ba: fab2 f282 clz r2, r2
80021be: b2d2 uxtb r2, r2
80021c0: f042 0220 orr.w r2, r2, #32
80021c4: b2d2 uxtb r2, r2
80021c6: f002 021f and.w r2, r2, #31
80021ca: 2101 movs r1, #1
80021cc: fa01 f202 lsl.w r2, r1, r2
80021d0: 4013 ands r3, r2
80021d2: 2b00 cmp r3, #0
80021d4: d0af beq.n 8002136 <HAL_RCC_OscConfig+0x492>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
80021d6: 4b2d ldr r3, [pc, #180] ; (800228c <HAL_RCC_OscConfig+0x5e8>)
80021d8: 681b ldr r3, [r3, #0]
80021da: f023 02f8 bic.w r2, r3, #248 ; 0xf8
80021de: f507 7300 add.w r3, r7, #512 ; 0x200
80021e2: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
80021e6: 681b ldr r3, [r3, #0]
80021e8: 695b ldr r3, [r3, #20]
80021ea: 21f8 movs r1, #248 ; 0xf8
80021ec: f8c7 1140 str.w r1, [r7, #320] ; 0x140
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80021f0: f8d7 1140 ldr.w r1, [r7, #320] ; 0x140
80021f4: fa91 f1a1 rbit r1, r1
80021f8: f8c7 113c str.w r1, [r7, #316] ; 0x13c
return result;
80021fc: f8d7 113c ldr.w r1, [r7, #316] ; 0x13c
8002200: fab1 f181 clz r1, r1
8002204: b2c9 uxtb r1, r1
8002206: 408b lsls r3, r1
8002208: 4920 ldr r1, [pc, #128] ; (800228c <HAL_RCC_OscConfig+0x5e8>)
800220a: 4313 orrs r3, r2
800220c: 600b str r3, [r1, #0]
800220e: e06c b.n 80022ea <HAL_RCC_OscConfig+0x646>
8002210: 2301 movs r3, #1
8002212: f8c7 3138 str.w r3, [r7, #312] ; 0x138
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002216: f8d7 3138 ldr.w r3, [r7, #312] ; 0x138
800221a: fa93 f3a3 rbit r3, r3
800221e: f8c7 3134 str.w r3, [r7, #308] ; 0x134
return result;
8002222: f8d7 3134 ldr.w r3, [r7, #308] ; 0x134
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
8002226: fab3 f383 clz r3, r3
800222a: b2db uxtb r3, r3
800222c: f103 5384 add.w r3, r3, #276824064 ; 0x10800000
8002230: f503 1384 add.w r3, r3, #1081344 ; 0x108000
8002234: 009b lsls r3, r3, #2
8002236: 461a mov r2, r3
8002238: 2300 movs r3, #0
800223a: 6013 str r3, [r2, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
800223c: f7fe fb96 bl 800096c <HAL_GetTick>
8002240: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8
/* Wait till HSI is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8002244: e00a b.n 800225c <HAL_RCC_OscConfig+0x5b8>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
8002246: f7fe fb91 bl 800096c <HAL_GetTick>
800224a: 4602 mov r2, r0
800224c: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8
8002250: 1ad3 subs r3, r2, r3
8002252: 2b02 cmp r3, #2
8002254: d902 bls.n 800225c <HAL_RCC_OscConfig+0x5b8>
{
return HAL_TIMEOUT;
8002256: 2303 movs r3, #3
8002258: f000 bd5a b.w 8002d10 <HAL_RCC_OscConfig+0x106c>
800225c: 2302 movs r3, #2
800225e: f8c7 3130 str.w r3, [r7, #304] ; 0x130
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002262: f8d7 3130 ldr.w r3, [r7, #304] ; 0x130
8002266: fa93 f3a3 rbit r3, r3
800226a: f8c7 312c str.w r3, [r7, #300] ; 0x12c
return result;
800226e: f8d7 312c ldr.w r3, [r7, #300] ; 0x12c
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8002272: fab3 f383 clz r3, r3
8002276: b2db uxtb r3, r3
8002278: 095b lsrs r3, r3, #5
800227a: b2db uxtb r3, r3
800227c: f043 0301 orr.w r3, r3, #1
8002280: b2db uxtb r3, r3
8002282: 2b01 cmp r3, #1
8002284: d104 bne.n 8002290 <HAL_RCC_OscConfig+0x5ec>
8002286: 4b01 ldr r3, [pc, #4] ; (800228c <HAL_RCC_OscConfig+0x5e8>)
8002288: 681b ldr r3, [r3, #0]
800228a: e015 b.n 80022b8 <HAL_RCC_OscConfig+0x614>
800228c: 40021000 .word 0x40021000
8002290: 2302 movs r3, #2
8002292: f8c7 3128 str.w r3, [r7, #296] ; 0x128
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002296: f8d7 3128 ldr.w r3, [r7, #296] ; 0x128
800229a: fa93 f3a3 rbit r3, r3
800229e: f8c7 3124 str.w r3, [r7, #292] ; 0x124
80022a2: 2302 movs r3, #2
80022a4: f8c7 3120 str.w r3, [r7, #288] ; 0x120
80022a8: f8d7 3120 ldr.w r3, [r7, #288] ; 0x120
80022ac: fa93 f3a3 rbit r3, r3
80022b0: f8c7 311c str.w r3, [r7, #284] ; 0x11c
80022b4: 4bc8 ldr r3, [pc, #800] ; (80025d8 <HAL_RCC_OscConfig+0x934>)
80022b6: 6a5b ldr r3, [r3, #36] ; 0x24
80022b8: 2202 movs r2, #2
80022ba: f8c7 2118 str.w r2, [r7, #280] ; 0x118
80022be: f8d7 2118 ldr.w r2, [r7, #280] ; 0x118
80022c2: fa92 f2a2 rbit r2, r2
80022c6: f8c7 2114 str.w r2, [r7, #276] ; 0x114
return result;
80022ca: f8d7 2114 ldr.w r2, [r7, #276] ; 0x114
80022ce: fab2 f282 clz r2, r2
80022d2: b2d2 uxtb r2, r2
80022d4: f042 0220 orr.w r2, r2, #32
80022d8: b2d2 uxtb r2, r2
80022da: f002 021f and.w r2, r2, #31
80022de: 2101 movs r1, #1
80022e0: fa01 f202 lsl.w r2, r1, r2
80022e4: 4013 ands r3, r2
80022e6: 2b00 cmp r3, #0
80022e8: d1ad bne.n 8002246 <HAL_RCC_OscConfig+0x5a2>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
80022ea: f507 7300 add.w r3, r7, #512 ; 0x200
80022ee: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
80022f2: 681b ldr r3, [r3, #0]
80022f4: 681b ldr r3, [r3, #0]
80022f6: f003 0308 and.w r3, r3, #8
80022fa: 2b00 cmp r3, #0
80022fc: f000 8110 beq.w 8002520 <HAL_RCC_OscConfig+0x87c>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
8002300: f507 7300 add.w r3, r7, #512 ; 0x200
8002304: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
8002308: 681b ldr r3, [r3, #0]
800230a: 699b ldr r3, [r3, #24]
800230c: 2b00 cmp r3, #0
800230e: d079 beq.n 8002404 <HAL_RCC_OscConfig+0x760>
8002310: 2301 movs r3, #1
8002312: f8c7 3110 str.w r3, [r7, #272] ; 0x110
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002316: f8d7 3110 ldr.w r3, [r7, #272] ; 0x110
800231a: fa93 f3a3 rbit r3, r3
800231e: f8c7 310c str.w r3, [r7, #268] ; 0x10c
return result;
8002322: f8d7 310c ldr.w r3, [r7, #268] ; 0x10c
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
8002326: fab3 f383 clz r3, r3
800232a: b2db uxtb r3, r3
800232c: 461a mov r2, r3
800232e: 4bab ldr r3, [pc, #684] ; (80025dc <HAL_RCC_OscConfig+0x938>)
8002330: 4413 add r3, r2
8002332: 009b lsls r3, r3, #2
8002334: 461a mov r2, r3
8002336: 2301 movs r3, #1
8002338: 6013 str r3, [r2, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
800233a: f7fe fb17 bl 800096c <HAL_GetTick>
800233e: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8002342: e00a b.n 800235a <HAL_RCC_OscConfig+0x6b6>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
8002344: f7fe fb12 bl 800096c <HAL_GetTick>
8002348: 4602 mov r2, r0
800234a: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8
800234e: 1ad3 subs r3, r2, r3
8002350: 2b02 cmp r3, #2
8002352: d902 bls.n 800235a <HAL_RCC_OscConfig+0x6b6>
{
return HAL_TIMEOUT;
8002354: 2303 movs r3, #3
8002356: f000 bcdb b.w 8002d10 <HAL_RCC_OscConfig+0x106c>
800235a: 2302 movs r3, #2
800235c: f8c7 3108 str.w r3, [r7, #264] ; 0x108
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002360: f8d7 3108 ldr.w r3, [r7, #264] ; 0x108
8002364: fa93 f3a3 rbit r3, r3
8002368: f8c7 3104 str.w r3, [r7, #260] ; 0x104
800236c: f507 7300 add.w r3, r7, #512 ; 0x200
8002370: f5a3 7380 sub.w r3, r3, #256 ; 0x100
8002374: 2202 movs r2, #2
8002376: 601a str r2, [r3, #0]
8002378: f507 7300 add.w r3, r7, #512 ; 0x200
800237c: f5a3 7380 sub.w r3, r3, #256 ; 0x100
8002380: 681b ldr r3, [r3, #0]
8002382: fa93 f2a3 rbit r2, r3
8002386: f507 7300 add.w r3, r7, #512 ; 0x200
800238a: f5a3 7382 sub.w r3, r3, #260 ; 0x104
800238e: 601a str r2, [r3, #0]
8002390: f507 7300 add.w r3, r7, #512 ; 0x200
8002394: f5a3 7384 sub.w r3, r3, #264 ; 0x108
8002398: 2202 movs r2, #2
800239a: 601a str r2, [r3, #0]
800239c: f507 7300 add.w r3, r7, #512 ; 0x200
80023a0: f5a3 7384 sub.w r3, r3, #264 ; 0x108
80023a4: 681b ldr r3, [r3, #0]
80023a6: fa93 f2a3 rbit r2, r3
80023aa: f507 7300 add.w r3, r7, #512 ; 0x200
80023ae: f5a3 7386 sub.w r3, r3, #268 ; 0x10c
80023b2: 601a str r2, [r3, #0]
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
80023b4: 4b88 ldr r3, [pc, #544] ; (80025d8 <HAL_RCC_OscConfig+0x934>)
80023b6: 6a5a ldr r2, [r3, #36] ; 0x24
80023b8: f507 7300 add.w r3, r7, #512 ; 0x200
80023bc: f5a3 7388 sub.w r3, r3, #272 ; 0x110
80023c0: 2102 movs r1, #2
80023c2: 6019 str r1, [r3, #0]
80023c4: f507 7300 add.w r3, r7, #512 ; 0x200
80023c8: f5a3 7388 sub.w r3, r3, #272 ; 0x110
80023cc: 681b ldr r3, [r3, #0]
80023ce: fa93 f1a3 rbit r1, r3
80023d2: f507 7300 add.w r3, r7, #512 ; 0x200
80023d6: f5a3 738a sub.w r3, r3, #276 ; 0x114
80023da: 6019 str r1, [r3, #0]
return result;
80023dc: f507 7300 add.w r3, r7, #512 ; 0x200
80023e0: f5a3 738a sub.w r3, r3, #276 ; 0x114
80023e4: 681b ldr r3, [r3, #0]
80023e6: fab3 f383 clz r3, r3
80023ea: b2db uxtb r3, r3
80023ec: f043 0360 orr.w r3, r3, #96 ; 0x60
80023f0: b2db uxtb r3, r3
80023f2: f003 031f and.w r3, r3, #31
80023f6: 2101 movs r1, #1
80023f8: fa01 f303 lsl.w r3, r1, r3
80023fc: 4013 ands r3, r2
80023fe: 2b00 cmp r3, #0
8002400: d0a0 beq.n 8002344 <HAL_RCC_OscConfig+0x6a0>
8002402: e08d b.n 8002520 <HAL_RCC_OscConfig+0x87c>
8002404: f507 7300 add.w r3, r7, #512 ; 0x200
8002408: f5a3 738c sub.w r3, r3, #280 ; 0x118
800240c: 2201 movs r2, #1
800240e: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002410: f507 7300 add.w r3, r7, #512 ; 0x200
8002414: f5a3 738c sub.w r3, r3, #280 ; 0x118
8002418: 681b ldr r3, [r3, #0]
800241a: fa93 f2a3 rbit r2, r3
800241e: f507 7300 add.w r3, r7, #512 ; 0x200
8002422: f5a3 738e sub.w r3, r3, #284 ; 0x11c
8002426: 601a str r2, [r3, #0]
return result;
8002428: f507 7300 add.w r3, r7, #512 ; 0x200
800242c: f5a3 738e sub.w r3, r3, #284 ; 0x11c
8002430: 681b ldr r3, [r3, #0]
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8002432: fab3 f383 clz r3, r3
8002436: b2db uxtb r3, r3
8002438: 461a mov r2, r3
800243a: 4b68 ldr r3, [pc, #416] ; (80025dc <HAL_RCC_OscConfig+0x938>)
800243c: 4413 add r3, r2
800243e: 009b lsls r3, r3, #2
8002440: 461a mov r2, r3
8002442: 2300 movs r3, #0
8002444: 6013 str r3, [r2, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8002446: f7fe fa91 bl 800096c <HAL_GetTick>
800244a: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8
/* Wait till LSI is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
800244e: e00a b.n 8002466 <HAL_RCC_OscConfig+0x7c2>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
8002450: f7fe fa8c bl 800096c <HAL_GetTick>
8002454: 4602 mov r2, r0
8002456: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8
800245a: 1ad3 subs r3, r2, r3
800245c: 2b02 cmp r3, #2
800245e: d902 bls.n 8002466 <HAL_RCC_OscConfig+0x7c2>
{
return HAL_TIMEOUT;
8002460: 2303 movs r3, #3
8002462: f000 bc55 b.w 8002d10 <HAL_RCC_OscConfig+0x106c>
8002466: f507 7300 add.w r3, r7, #512 ; 0x200
800246a: f5a3 7390 sub.w r3, r3, #288 ; 0x120
800246e: 2202 movs r2, #2
8002470: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002472: f507 7300 add.w r3, r7, #512 ; 0x200
8002476: f5a3 7390 sub.w r3, r3, #288 ; 0x120
800247a: 681b ldr r3, [r3, #0]
800247c: fa93 f2a3 rbit r2, r3
8002480: f507 7300 add.w r3, r7, #512 ; 0x200
8002484: f5a3 7392 sub.w r3, r3, #292 ; 0x124
8002488: 601a str r2, [r3, #0]
800248a: f507 7300 add.w r3, r7, #512 ; 0x200
800248e: f5a3 7394 sub.w r3, r3, #296 ; 0x128
8002492: 2202 movs r2, #2
8002494: 601a str r2, [r3, #0]
8002496: f507 7300 add.w r3, r7, #512 ; 0x200
800249a: f5a3 7394 sub.w r3, r3, #296 ; 0x128
800249e: 681b ldr r3, [r3, #0]
80024a0: fa93 f2a3 rbit r2, r3
80024a4: f507 7300 add.w r3, r7, #512 ; 0x200
80024a8: f5a3 7396 sub.w r3, r3, #300 ; 0x12c
80024ac: 601a str r2, [r3, #0]
80024ae: f507 7300 add.w r3, r7, #512 ; 0x200
80024b2: f5a3 7398 sub.w r3, r3, #304 ; 0x130
80024b6: 2202 movs r2, #2
80024b8: 601a str r2, [r3, #0]
80024ba: f507 7300 add.w r3, r7, #512 ; 0x200
80024be: f5a3 7398 sub.w r3, r3, #304 ; 0x130
80024c2: 681b ldr r3, [r3, #0]
80024c4: fa93 f2a3 rbit r2, r3
80024c8: f507 7300 add.w r3, r7, #512 ; 0x200
80024cc: f5a3 739a sub.w r3, r3, #308 ; 0x134
80024d0: 601a str r2, [r3, #0]
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
80024d2: 4b41 ldr r3, [pc, #260] ; (80025d8 <HAL_RCC_OscConfig+0x934>)
80024d4: 6a5a ldr r2, [r3, #36] ; 0x24
80024d6: f507 7300 add.w r3, r7, #512 ; 0x200
80024da: f5a3 739c sub.w r3, r3, #312 ; 0x138
80024de: 2102 movs r1, #2
80024e0: 6019 str r1, [r3, #0]
80024e2: f507 7300 add.w r3, r7, #512 ; 0x200
80024e6: f5a3 739c sub.w r3, r3, #312 ; 0x138
80024ea: 681b ldr r3, [r3, #0]
80024ec: fa93 f1a3 rbit r1, r3
80024f0: f507 7300 add.w r3, r7, #512 ; 0x200
80024f4: f5a3 739e sub.w r3, r3, #316 ; 0x13c
80024f8: 6019 str r1, [r3, #0]
return result;
80024fa: f507 7300 add.w r3, r7, #512 ; 0x200
80024fe: f5a3 739e sub.w r3, r3, #316 ; 0x13c
8002502: 681b ldr r3, [r3, #0]
8002504: fab3 f383 clz r3, r3
8002508: b2db uxtb r3, r3
800250a: f043 0360 orr.w r3, r3, #96 ; 0x60
800250e: b2db uxtb r3, r3
8002510: f003 031f and.w r3, r3, #31
8002514: 2101 movs r1, #1
8002516: fa01 f303 lsl.w r3, r1, r3
800251a: 4013 ands r3, r2
800251c: 2b00 cmp r3, #0
800251e: d197 bne.n 8002450 <HAL_RCC_OscConfig+0x7ac>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8002520: f507 7300 add.w r3, r7, #512 ; 0x200
8002524: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
8002528: 681b ldr r3, [r3, #0]
800252a: 681b ldr r3, [r3, #0]
800252c: f003 0304 and.w r3, r3, #4
8002530: 2b00 cmp r3, #0
8002532: f000 81a1 beq.w 8002878 <HAL_RCC_OscConfig+0xbd4>
{
FlagStatus pwrclkchanged = RESET;
8002536: 2300 movs r3, #0
8002538: f887 31ff strb.w r3, [r7, #511] ; 0x1ff
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
800253c: 4b26 ldr r3, [pc, #152] ; (80025d8 <HAL_RCC_OscConfig+0x934>)
800253e: 69db ldr r3, [r3, #28]
8002540: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8002544: 2b00 cmp r3, #0
8002546: d116 bne.n 8002576 <HAL_RCC_OscConfig+0x8d2>
{
__HAL_RCC_PWR_CLK_ENABLE();
8002548: 4b23 ldr r3, [pc, #140] ; (80025d8 <HAL_RCC_OscConfig+0x934>)
800254a: 69db ldr r3, [r3, #28]
800254c: 4a22 ldr r2, [pc, #136] ; (80025d8 <HAL_RCC_OscConfig+0x934>)
800254e: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8002552: 61d3 str r3, [r2, #28]
8002554: 4b20 ldr r3, [pc, #128] ; (80025d8 <HAL_RCC_OscConfig+0x934>)
8002556: 69db ldr r3, [r3, #28]
8002558: f003 5280 and.w r2, r3, #268435456 ; 0x10000000
800255c: f507 7300 add.w r3, r7, #512 ; 0x200
8002560: f5a3 73fc sub.w r3, r3, #504 ; 0x1f8
8002564: 601a str r2, [r3, #0]
8002566: f507 7300 add.w r3, r7, #512 ; 0x200
800256a: f5a3 73fc sub.w r3, r3, #504 ; 0x1f8
800256e: 681b ldr r3, [r3, #0]
pwrclkchanged = SET;
8002570: 2301 movs r3, #1
8002572: f887 31ff strb.w r3, [r7, #511] ; 0x1ff
}
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8002576: 4b1a ldr r3, [pc, #104] ; (80025e0 <HAL_RCC_OscConfig+0x93c>)
8002578: 681b ldr r3, [r3, #0]
800257a: f403 7380 and.w r3, r3, #256 ; 0x100
800257e: 2b00 cmp r3, #0
8002580: d11a bne.n 80025b8 <HAL_RCC_OscConfig+0x914>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
8002582: 4b17 ldr r3, [pc, #92] ; (80025e0 <HAL_RCC_OscConfig+0x93c>)
8002584: 681b ldr r3, [r3, #0]
8002586: 4a16 ldr r2, [pc, #88] ; (80025e0 <HAL_RCC_OscConfig+0x93c>)
8002588: f443 7380 orr.w r3, r3, #256 ; 0x100
800258c: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
800258e: f7fe f9ed bl 800096c <HAL_GetTick>
8002592: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8002596: e009 b.n 80025ac <HAL_RCC_OscConfig+0x908>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8002598: f7fe f9e8 bl 800096c <HAL_GetTick>
800259c: 4602 mov r2, r0
800259e: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8
80025a2: 1ad3 subs r3, r2, r3
80025a4: 2b64 cmp r3, #100 ; 0x64
80025a6: d901 bls.n 80025ac <HAL_RCC_OscConfig+0x908>
{
return HAL_TIMEOUT;
80025a8: 2303 movs r3, #3
80025aa: e3b1 b.n 8002d10 <HAL_RCC_OscConfig+0x106c>
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80025ac: 4b0c ldr r3, [pc, #48] ; (80025e0 <HAL_RCC_OscConfig+0x93c>)
80025ae: 681b ldr r3, [r3, #0]
80025b0: f403 7380 and.w r3, r3, #256 ; 0x100
80025b4: 2b00 cmp r3, #0
80025b6: d0ef beq.n 8002598 <HAL_RCC_OscConfig+0x8f4>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
80025b8: f507 7300 add.w r3, r7, #512 ; 0x200
80025bc: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
80025c0: 681b ldr r3, [r3, #0]
80025c2: 68db ldr r3, [r3, #12]
80025c4: 2b01 cmp r3, #1
80025c6: d10d bne.n 80025e4 <HAL_RCC_OscConfig+0x940>
80025c8: 4b03 ldr r3, [pc, #12] ; (80025d8 <HAL_RCC_OscConfig+0x934>)
80025ca: 6a1b ldr r3, [r3, #32]
80025cc: 4a02 ldr r2, [pc, #8] ; (80025d8 <HAL_RCC_OscConfig+0x934>)
80025ce: f043 0301 orr.w r3, r3, #1
80025d2: 6213 str r3, [r2, #32]
80025d4: e03c b.n 8002650 <HAL_RCC_OscConfig+0x9ac>
80025d6: bf00 nop
80025d8: 40021000 .word 0x40021000
80025dc: 10908120 .word 0x10908120
80025e0: 40007000 .word 0x40007000
80025e4: f507 7300 add.w r3, r7, #512 ; 0x200
80025e8: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
80025ec: 681b ldr r3, [r3, #0]
80025ee: 68db ldr r3, [r3, #12]
80025f0: 2b00 cmp r3, #0
80025f2: d10c bne.n 800260e <HAL_RCC_OscConfig+0x96a>
80025f4: 4bc1 ldr r3, [pc, #772] ; (80028fc <HAL_RCC_OscConfig+0xc58>)
80025f6: 6a1b ldr r3, [r3, #32]
80025f8: 4ac0 ldr r2, [pc, #768] ; (80028fc <HAL_RCC_OscConfig+0xc58>)
80025fa: f023 0301 bic.w r3, r3, #1
80025fe: 6213 str r3, [r2, #32]
8002600: 4bbe ldr r3, [pc, #760] ; (80028fc <HAL_RCC_OscConfig+0xc58>)
8002602: 6a1b ldr r3, [r3, #32]
8002604: 4abd ldr r2, [pc, #756] ; (80028fc <HAL_RCC_OscConfig+0xc58>)
8002606: f023 0304 bic.w r3, r3, #4
800260a: 6213 str r3, [r2, #32]
800260c: e020 b.n 8002650 <HAL_RCC_OscConfig+0x9ac>
800260e: f507 7300 add.w r3, r7, #512 ; 0x200
8002612: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
8002616: 681b ldr r3, [r3, #0]
8002618: 68db ldr r3, [r3, #12]
800261a: 2b05 cmp r3, #5
800261c: d10c bne.n 8002638 <HAL_RCC_OscConfig+0x994>
800261e: 4bb7 ldr r3, [pc, #732] ; (80028fc <HAL_RCC_OscConfig+0xc58>)
8002620: 6a1b ldr r3, [r3, #32]
8002622: 4ab6 ldr r2, [pc, #728] ; (80028fc <HAL_RCC_OscConfig+0xc58>)
8002624: f043 0304 orr.w r3, r3, #4
8002628: 6213 str r3, [r2, #32]
800262a: 4bb4 ldr r3, [pc, #720] ; (80028fc <HAL_RCC_OscConfig+0xc58>)
800262c: 6a1b ldr r3, [r3, #32]
800262e: 4ab3 ldr r2, [pc, #716] ; (80028fc <HAL_RCC_OscConfig+0xc58>)
8002630: f043 0301 orr.w r3, r3, #1
8002634: 6213 str r3, [r2, #32]
8002636: e00b b.n 8002650 <HAL_RCC_OscConfig+0x9ac>
8002638: 4bb0 ldr r3, [pc, #704] ; (80028fc <HAL_RCC_OscConfig+0xc58>)
800263a: 6a1b ldr r3, [r3, #32]
800263c: 4aaf ldr r2, [pc, #700] ; (80028fc <HAL_RCC_OscConfig+0xc58>)
800263e: f023 0301 bic.w r3, r3, #1
8002642: 6213 str r3, [r2, #32]
8002644: 4bad ldr r3, [pc, #692] ; (80028fc <HAL_RCC_OscConfig+0xc58>)
8002646: 6a1b ldr r3, [r3, #32]
8002648: 4aac ldr r2, [pc, #688] ; (80028fc <HAL_RCC_OscConfig+0xc58>)
800264a: f023 0304 bic.w r3, r3, #4
800264e: 6213 str r3, [r2, #32]
/* Check the LSE State */
if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
8002650: f507 7300 add.w r3, r7, #512 ; 0x200
8002654: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
8002658: 681b ldr r3, [r3, #0]
800265a: 68db ldr r3, [r3, #12]
800265c: 2b00 cmp r3, #0
800265e: f000 8081 beq.w 8002764 <HAL_RCC_OscConfig+0xac0>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8002662: f7fe f983 bl 800096c <HAL_GetTick>
8002666: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
800266a: e00b b.n 8002684 <HAL_RCC_OscConfig+0x9e0>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
800266c: f7fe f97e bl 800096c <HAL_GetTick>
8002670: 4602 mov r2, r0
8002672: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8
8002676: 1ad3 subs r3, r2, r3
8002678: f241 3288 movw r2, #5000 ; 0x1388
800267c: 4293 cmp r3, r2
800267e: d901 bls.n 8002684 <HAL_RCC_OscConfig+0x9e0>
{
return HAL_TIMEOUT;
8002680: 2303 movs r3, #3
8002682: e345 b.n 8002d10 <HAL_RCC_OscConfig+0x106c>
8002684: f507 7300 add.w r3, r7, #512 ; 0x200
8002688: f5a3 73a0 sub.w r3, r3, #320 ; 0x140
800268c: 2202 movs r2, #2
800268e: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002690: f507 7300 add.w r3, r7, #512 ; 0x200
8002694: f5a3 73a0 sub.w r3, r3, #320 ; 0x140
8002698: 681b ldr r3, [r3, #0]
800269a: fa93 f2a3 rbit r2, r3
800269e: f507 7300 add.w r3, r7, #512 ; 0x200
80026a2: f5a3 73a2 sub.w r3, r3, #324 ; 0x144
80026a6: 601a str r2, [r3, #0]
80026a8: f507 7300 add.w r3, r7, #512 ; 0x200
80026ac: f5a3 73a4 sub.w r3, r3, #328 ; 0x148
80026b0: 2202 movs r2, #2
80026b2: 601a str r2, [r3, #0]
80026b4: f507 7300 add.w r3, r7, #512 ; 0x200
80026b8: f5a3 73a4 sub.w r3, r3, #328 ; 0x148
80026bc: 681b ldr r3, [r3, #0]
80026be: fa93 f2a3 rbit r2, r3
80026c2: f507 7300 add.w r3, r7, #512 ; 0x200
80026c6: f5a3 73a6 sub.w r3, r3, #332 ; 0x14c
80026ca: 601a str r2, [r3, #0]
return result;
80026cc: f507 7300 add.w r3, r7, #512 ; 0x200
80026d0: f5a3 73a6 sub.w r3, r3, #332 ; 0x14c
80026d4: 681b ldr r3, [r3, #0]
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
80026d6: fab3 f383 clz r3, r3
80026da: b2db uxtb r3, r3
80026dc: 095b lsrs r3, r3, #5
80026de: b2db uxtb r3, r3
80026e0: f043 0302 orr.w r3, r3, #2
80026e4: b2db uxtb r3, r3
80026e6: 2b02 cmp r3, #2
80026e8: d102 bne.n 80026f0 <HAL_RCC_OscConfig+0xa4c>
80026ea: 4b84 ldr r3, [pc, #528] ; (80028fc <HAL_RCC_OscConfig+0xc58>)
80026ec: 6a1b ldr r3, [r3, #32]
80026ee: e013 b.n 8002718 <HAL_RCC_OscConfig+0xa74>
80026f0: f507 7300 add.w r3, r7, #512 ; 0x200
80026f4: f5a3 73a8 sub.w r3, r3, #336 ; 0x150
80026f8: 2202 movs r2, #2
80026fa: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80026fc: f507 7300 add.w r3, r7, #512 ; 0x200
8002700: f5a3 73a8 sub.w r3, r3, #336 ; 0x150
8002704: 681b ldr r3, [r3, #0]
8002706: fa93 f2a3 rbit r2, r3
800270a: f507 7300 add.w r3, r7, #512 ; 0x200
800270e: f5a3 73aa sub.w r3, r3, #340 ; 0x154
8002712: 601a str r2, [r3, #0]
8002714: 4b79 ldr r3, [pc, #484] ; (80028fc <HAL_RCC_OscConfig+0xc58>)
8002716: 6a5b ldr r3, [r3, #36] ; 0x24
8002718: f507 7200 add.w r2, r7, #512 ; 0x200
800271c: f5a2 72ac sub.w r2, r2, #344 ; 0x158
8002720: 2102 movs r1, #2
8002722: 6011 str r1, [r2, #0]
8002724: f507 7200 add.w r2, r7, #512 ; 0x200
8002728: f5a2 72ac sub.w r2, r2, #344 ; 0x158
800272c: 6812 ldr r2, [r2, #0]
800272e: fa92 f1a2 rbit r1, r2
8002732: f507 7200 add.w r2, r7, #512 ; 0x200
8002736: f5a2 72ae sub.w r2, r2, #348 ; 0x15c
800273a: 6011 str r1, [r2, #0]
return result;
800273c: f507 7200 add.w r2, r7, #512 ; 0x200
8002740: f5a2 72ae sub.w r2, r2, #348 ; 0x15c
8002744: 6812 ldr r2, [r2, #0]
8002746: fab2 f282 clz r2, r2
800274a: b2d2 uxtb r2, r2
800274c: f042 0240 orr.w r2, r2, #64 ; 0x40
8002750: b2d2 uxtb r2, r2
8002752: f002 021f and.w r2, r2, #31
8002756: 2101 movs r1, #1
8002758: fa01 f202 lsl.w r2, r1, r2
800275c: 4013 ands r3, r2
800275e: 2b00 cmp r3, #0
8002760: d084 beq.n 800266c <HAL_RCC_OscConfig+0x9c8>
8002762: e07f b.n 8002864 <HAL_RCC_OscConfig+0xbc0>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8002764: f7fe f902 bl 800096c <HAL_GetTick>
8002768: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8
/* Wait till LSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
800276c: e00b b.n 8002786 <HAL_RCC_OscConfig+0xae2>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
800276e: f7fe f8fd bl 800096c <HAL_GetTick>
8002772: 4602 mov r2, r0
8002774: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8
8002778: 1ad3 subs r3, r2, r3
800277a: f241 3288 movw r2, #5000 ; 0x1388
800277e: 4293 cmp r3, r2
8002780: d901 bls.n 8002786 <HAL_RCC_OscConfig+0xae2>
{
return HAL_TIMEOUT;
8002782: 2303 movs r3, #3
8002784: e2c4 b.n 8002d10 <HAL_RCC_OscConfig+0x106c>
8002786: f507 7300 add.w r3, r7, #512 ; 0x200
800278a: f5a3 73b0 sub.w r3, r3, #352 ; 0x160
800278e: 2202 movs r2, #2
8002790: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002792: f507 7300 add.w r3, r7, #512 ; 0x200
8002796: f5a3 73b0 sub.w r3, r3, #352 ; 0x160
800279a: 681b ldr r3, [r3, #0]
800279c: fa93 f2a3 rbit r2, r3
80027a0: f507 7300 add.w r3, r7, #512 ; 0x200
80027a4: f5a3 73b2 sub.w r3, r3, #356 ; 0x164
80027a8: 601a str r2, [r3, #0]
80027aa: f507 7300 add.w r3, r7, #512 ; 0x200
80027ae: f5a3 73b4 sub.w r3, r3, #360 ; 0x168
80027b2: 2202 movs r2, #2
80027b4: 601a str r2, [r3, #0]
80027b6: f507 7300 add.w r3, r7, #512 ; 0x200
80027ba: f5a3 73b4 sub.w r3, r3, #360 ; 0x168
80027be: 681b ldr r3, [r3, #0]
80027c0: fa93 f2a3 rbit r2, r3
80027c4: f507 7300 add.w r3, r7, #512 ; 0x200
80027c8: f5a3 73b6 sub.w r3, r3, #364 ; 0x16c
80027cc: 601a str r2, [r3, #0]
return result;
80027ce: f507 7300 add.w r3, r7, #512 ; 0x200
80027d2: f5a3 73b6 sub.w r3, r3, #364 ; 0x16c
80027d6: 681b ldr r3, [r3, #0]
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
80027d8: fab3 f383 clz r3, r3
80027dc: b2db uxtb r3, r3
80027de: 095b lsrs r3, r3, #5
80027e0: b2db uxtb r3, r3
80027e2: f043 0302 orr.w r3, r3, #2
80027e6: b2db uxtb r3, r3
80027e8: 2b02 cmp r3, #2
80027ea: d102 bne.n 80027f2 <HAL_RCC_OscConfig+0xb4e>
80027ec: 4b43 ldr r3, [pc, #268] ; (80028fc <HAL_RCC_OscConfig+0xc58>)
80027ee: 6a1b ldr r3, [r3, #32]
80027f0: e013 b.n 800281a <HAL_RCC_OscConfig+0xb76>
80027f2: f507 7300 add.w r3, r7, #512 ; 0x200
80027f6: f5a3 73b8 sub.w r3, r3, #368 ; 0x170
80027fa: 2202 movs r2, #2
80027fc: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80027fe: f507 7300 add.w r3, r7, #512 ; 0x200
8002802: f5a3 73b8 sub.w r3, r3, #368 ; 0x170
8002806: 681b ldr r3, [r3, #0]
8002808: fa93 f2a3 rbit r2, r3
800280c: f507 7300 add.w r3, r7, #512 ; 0x200
8002810: f5a3 73ba sub.w r3, r3, #372 ; 0x174
8002814: 601a str r2, [r3, #0]
8002816: 4b39 ldr r3, [pc, #228] ; (80028fc <HAL_RCC_OscConfig+0xc58>)
8002818: 6a5b ldr r3, [r3, #36] ; 0x24
800281a: f507 7200 add.w r2, r7, #512 ; 0x200
800281e: f5a2 72bc sub.w r2, r2, #376 ; 0x178
8002822: 2102 movs r1, #2
8002824: 6011 str r1, [r2, #0]
8002826: f507 7200 add.w r2, r7, #512 ; 0x200
800282a: f5a2 72bc sub.w r2, r2, #376 ; 0x178
800282e: 6812 ldr r2, [r2, #0]
8002830: fa92 f1a2 rbit r1, r2
8002834: f507 7200 add.w r2, r7, #512 ; 0x200
8002838: f5a2 72be sub.w r2, r2, #380 ; 0x17c
800283c: 6011 str r1, [r2, #0]
return result;
800283e: f507 7200 add.w r2, r7, #512 ; 0x200
8002842: f5a2 72be sub.w r2, r2, #380 ; 0x17c
8002846: 6812 ldr r2, [r2, #0]
8002848: fab2 f282 clz r2, r2
800284c: b2d2 uxtb r2, r2
800284e: f042 0240 orr.w r2, r2, #64 ; 0x40
8002852: b2d2 uxtb r2, r2
8002854: f002 021f and.w r2, r2, #31
8002858: 2101 movs r1, #1
800285a: fa01 f202 lsl.w r2, r1, r2
800285e: 4013 ands r3, r2
8002860: 2b00 cmp r3, #0
8002862: d184 bne.n 800276e <HAL_RCC_OscConfig+0xaca>
}
}
}
/* Require to disable power clock if necessary */
if(pwrclkchanged == SET)
8002864: f897 31ff ldrb.w r3, [r7, #511] ; 0x1ff
8002868: 2b01 cmp r3, #1
800286a: d105 bne.n 8002878 <HAL_RCC_OscConfig+0xbd4>
{
__HAL_RCC_PWR_CLK_DISABLE();
800286c: 4b23 ldr r3, [pc, #140] ; (80028fc <HAL_RCC_OscConfig+0xc58>)
800286e: 69db ldr r3, [r3, #28]
8002870: 4a22 ldr r2, [pc, #136] ; (80028fc <HAL_RCC_OscConfig+0xc58>)
8002872: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
8002876: 61d3 str r3, [r2, #28]
}
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
8002878: f507 7300 add.w r3, r7, #512 ; 0x200
800287c: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
8002880: 681b ldr r3, [r3, #0]
8002882: 69db ldr r3, [r3, #28]
8002884: 2b00 cmp r3, #0
8002886: f000 8242 beq.w 8002d0e <HAL_RCC_OscConfig+0x106a>
{
/* Check if the PLL is used as system clock or not */
if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
800288a: 4b1c ldr r3, [pc, #112] ; (80028fc <HAL_RCC_OscConfig+0xc58>)
800288c: 685b ldr r3, [r3, #4]
800288e: f003 030c and.w r3, r3, #12
8002892: 2b08 cmp r3, #8
8002894: f000 8213 beq.w 8002cbe <HAL_RCC_OscConfig+0x101a>
{
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
8002898: f507 7300 add.w r3, r7, #512 ; 0x200
800289c: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
80028a0: 681b ldr r3, [r3, #0]
80028a2: 69db ldr r3, [r3, #28]
80028a4: 2b02 cmp r3, #2
80028a6: f040 8162 bne.w 8002b6e <HAL_RCC_OscConfig+0xeca>
80028aa: f507 7300 add.w r3, r7, #512 ; 0x200
80028ae: f5a3 73c0 sub.w r3, r3, #384 ; 0x180
80028b2: f04f 7280 mov.w r2, #16777216 ; 0x1000000
80028b6: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80028b8: f507 7300 add.w r3, r7, #512 ; 0x200
80028bc: f5a3 73c0 sub.w r3, r3, #384 ; 0x180
80028c0: 681b ldr r3, [r3, #0]
80028c2: fa93 f2a3 rbit r2, r3
80028c6: f507 7300 add.w r3, r7, #512 ; 0x200
80028ca: f5a3 73c2 sub.w r3, r3, #388 ; 0x184
80028ce: 601a str r2, [r3, #0]
return result;
80028d0: f507 7300 add.w r3, r7, #512 ; 0x200
80028d4: f5a3 73c2 sub.w r3, r3, #388 ; 0x184
80028d8: 681b ldr r3, [r3, #0]
#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV));
#endif
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
80028da: fab3 f383 clz r3, r3
80028de: b2db uxtb r3, r3
80028e0: f103 5384 add.w r3, r3, #276824064 ; 0x10800000
80028e4: f503 1384 add.w r3, r3, #1081344 ; 0x108000
80028e8: 009b lsls r3, r3, #2
80028ea: 461a mov r2, r3
80028ec: 2300 movs r3, #0
80028ee: 6013 str r3, [r2, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80028f0: f7fe f83c bl 800096c <HAL_GetTick>
80028f4: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8
/* Wait till PLL is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80028f8: e00c b.n 8002914 <HAL_RCC_OscConfig+0xc70>
80028fa: bf00 nop
80028fc: 40021000 .word 0x40021000
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8002900: f7fe f834 bl 800096c <HAL_GetTick>
8002904: 4602 mov r2, r0
8002906: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8
800290a: 1ad3 subs r3, r2, r3
800290c: 2b02 cmp r3, #2
800290e: d901 bls.n 8002914 <HAL_RCC_OscConfig+0xc70>
{
return HAL_TIMEOUT;
8002910: 2303 movs r3, #3
8002912: e1fd b.n 8002d10 <HAL_RCC_OscConfig+0x106c>
8002914: f507 7300 add.w r3, r7, #512 ; 0x200
8002918: f5a3 73c4 sub.w r3, r3, #392 ; 0x188
800291c: f04f 7200 mov.w r2, #33554432 ; 0x2000000
8002920: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002922: f507 7300 add.w r3, r7, #512 ; 0x200
8002926: f5a3 73c4 sub.w r3, r3, #392 ; 0x188
800292a: 681b ldr r3, [r3, #0]
800292c: fa93 f2a3 rbit r2, r3
8002930: f507 7300 add.w r3, r7, #512 ; 0x200
8002934: f5a3 73c6 sub.w r3, r3, #396 ; 0x18c
8002938: 601a str r2, [r3, #0]
return result;
800293a: f507 7300 add.w r3, r7, #512 ; 0x200
800293e: f5a3 73c6 sub.w r3, r3, #396 ; 0x18c
8002942: 681b ldr r3, [r3, #0]
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8002944: fab3 f383 clz r3, r3
8002948: b2db uxtb r3, r3
800294a: 095b lsrs r3, r3, #5
800294c: b2db uxtb r3, r3
800294e: f043 0301 orr.w r3, r3, #1
8002952: b2db uxtb r3, r3
8002954: 2b01 cmp r3, #1
8002956: d102 bne.n 800295e <HAL_RCC_OscConfig+0xcba>
8002958: 4bb0 ldr r3, [pc, #704] ; (8002c1c <HAL_RCC_OscConfig+0xf78>)
800295a: 681b ldr r3, [r3, #0]
800295c: e027 b.n 80029ae <HAL_RCC_OscConfig+0xd0a>
800295e: f507 7300 add.w r3, r7, #512 ; 0x200
8002962: f5a3 73c8 sub.w r3, r3, #400 ; 0x190
8002966: f04f 7200 mov.w r2, #33554432 ; 0x2000000
800296a: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
800296c: f507 7300 add.w r3, r7, #512 ; 0x200
8002970: f5a3 73c8 sub.w r3, r3, #400 ; 0x190
8002974: 681b ldr r3, [r3, #0]
8002976: fa93 f2a3 rbit r2, r3
800297a: f507 7300 add.w r3, r7, #512 ; 0x200
800297e: f5a3 73ca sub.w r3, r3, #404 ; 0x194
8002982: 601a str r2, [r3, #0]
8002984: f507 7300 add.w r3, r7, #512 ; 0x200
8002988: f5a3 73cc sub.w r3, r3, #408 ; 0x198
800298c: f04f 7200 mov.w r2, #33554432 ; 0x2000000
8002990: 601a str r2, [r3, #0]
8002992: f507 7300 add.w r3, r7, #512 ; 0x200
8002996: f5a3 73cc sub.w r3, r3, #408 ; 0x198
800299a: 681b ldr r3, [r3, #0]
800299c: fa93 f2a3 rbit r2, r3
80029a0: f507 7300 add.w r3, r7, #512 ; 0x200
80029a4: f5a3 73ce sub.w r3, r3, #412 ; 0x19c
80029a8: 601a str r2, [r3, #0]
80029aa: 4b9c ldr r3, [pc, #624] ; (8002c1c <HAL_RCC_OscConfig+0xf78>)
80029ac: 6a5b ldr r3, [r3, #36] ; 0x24
80029ae: f507 7200 add.w r2, r7, #512 ; 0x200
80029b2: f5a2 72d0 sub.w r2, r2, #416 ; 0x1a0
80029b6: f04f 7100 mov.w r1, #33554432 ; 0x2000000
80029ba: 6011 str r1, [r2, #0]
80029bc: f507 7200 add.w r2, r7, #512 ; 0x200
80029c0: f5a2 72d0 sub.w r2, r2, #416 ; 0x1a0
80029c4: 6812 ldr r2, [r2, #0]
80029c6: fa92 f1a2 rbit r1, r2
80029ca: f507 7200 add.w r2, r7, #512 ; 0x200
80029ce: f5a2 72d2 sub.w r2, r2, #420 ; 0x1a4
80029d2: 6011 str r1, [r2, #0]
return result;
80029d4: f507 7200 add.w r2, r7, #512 ; 0x200
80029d8: f5a2 72d2 sub.w r2, r2, #420 ; 0x1a4
80029dc: 6812 ldr r2, [r2, #0]
80029de: fab2 f282 clz r2, r2
80029e2: b2d2 uxtb r2, r2
80029e4: f042 0220 orr.w r2, r2, #32
80029e8: b2d2 uxtb r2, r2
80029ea: f002 021f and.w r2, r2, #31
80029ee: 2101 movs r1, #1
80029f0: fa01 f202 lsl.w r2, r1, r2
80029f4: 4013 ands r3, r2
80029f6: 2b00 cmp r3, #0
80029f8: d182 bne.n 8002900 <HAL_RCC_OscConfig+0xc5c>
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
RCC_OscInitStruct->PLL.PREDIV,
RCC_OscInitStruct->PLL.PLLMUL);
#else
/* Configure the main PLL clock source and multiplication factor. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
80029fa: 4b88 ldr r3, [pc, #544] ; (8002c1c <HAL_RCC_OscConfig+0xf78>)
80029fc: 685b ldr r3, [r3, #4]
80029fe: f423 1274 bic.w r2, r3, #3997696 ; 0x3d0000
8002a02: f507 7300 add.w r3, r7, #512 ; 0x200
8002a06: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
8002a0a: 681b ldr r3, [r3, #0]
8002a0c: 6a59 ldr r1, [r3, #36] ; 0x24
8002a0e: f507 7300 add.w r3, r7, #512 ; 0x200
8002a12: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
8002a16: 681b ldr r3, [r3, #0]
8002a18: 6a1b ldr r3, [r3, #32]
8002a1a: 430b orrs r3, r1
8002a1c: 497f ldr r1, [pc, #508] ; (8002c1c <HAL_RCC_OscConfig+0xf78>)
8002a1e: 4313 orrs r3, r2
8002a20: 604b str r3, [r1, #4]
8002a22: f507 7300 add.w r3, r7, #512 ; 0x200
8002a26: f5a3 73d4 sub.w r3, r3, #424 ; 0x1a8
8002a2a: f04f 7280 mov.w r2, #16777216 ; 0x1000000
8002a2e: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002a30: f507 7300 add.w r3, r7, #512 ; 0x200
8002a34: f5a3 73d4 sub.w r3, r3, #424 ; 0x1a8
8002a38: 681b ldr r3, [r3, #0]
8002a3a: fa93 f2a3 rbit r2, r3
8002a3e: f507 7300 add.w r3, r7, #512 ; 0x200
8002a42: f5a3 73d6 sub.w r3, r3, #428 ; 0x1ac
8002a46: 601a str r2, [r3, #0]
return result;
8002a48: f507 7300 add.w r3, r7, #512 ; 0x200
8002a4c: f5a3 73d6 sub.w r3, r3, #428 ; 0x1ac
8002a50: 681b ldr r3, [r3, #0]
RCC_OscInitStruct->PLL.PLLMUL);
#endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8002a52: fab3 f383 clz r3, r3
8002a56: b2db uxtb r3, r3
8002a58: f103 5384 add.w r3, r3, #276824064 ; 0x10800000
8002a5c: f503 1384 add.w r3, r3, #1081344 ; 0x108000
8002a60: 009b lsls r3, r3, #2
8002a62: 461a mov r2, r3
8002a64: 2301 movs r3, #1
8002a66: 6013 str r3, [r2, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8002a68: f7fd ff80 bl 800096c <HAL_GetTick>
8002a6c: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8002a70: e009 b.n 8002a86 <HAL_RCC_OscConfig+0xde2>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8002a72: f7fd ff7b bl 800096c <HAL_GetTick>
8002a76: 4602 mov r2, r0
8002a78: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8
8002a7c: 1ad3 subs r3, r2, r3
8002a7e: 2b02 cmp r3, #2
8002a80: d901 bls.n 8002a86 <HAL_RCC_OscConfig+0xde2>
{
return HAL_TIMEOUT;
8002a82: 2303 movs r3, #3
8002a84: e144 b.n 8002d10 <HAL_RCC_OscConfig+0x106c>
8002a86: f507 7300 add.w r3, r7, #512 ; 0x200
8002a8a: f5a3 73d8 sub.w r3, r3, #432 ; 0x1b0
8002a8e: f04f 7200 mov.w r2, #33554432 ; 0x2000000
8002a92: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002a94: f507 7300 add.w r3, r7, #512 ; 0x200
8002a98: f5a3 73d8 sub.w r3, r3, #432 ; 0x1b0
8002a9c: 681b ldr r3, [r3, #0]
8002a9e: fa93 f2a3 rbit r2, r3
8002aa2: f507 7300 add.w r3, r7, #512 ; 0x200
8002aa6: f5a3 73da sub.w r3, r3, #436 ; 0x1b4
8002aaa: 601a str r2, [r3, #0]
return result;
8002aac: f507 7300 add.w r3, r7, #512 ; 0x200
8002ab0: f5a3 73da sub.w r3, r3, #436 ; 0x1b4
8002ab4: 681b ldr r3, [r3, #0]
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8002ab6: fab3 f383 clz r3, r3
8002aba: b2db uxtb r3, r3
8002abc: 095b lsrs r3, r3, #5
8002abe: b2db uxtb r3, r3
8002ac0: f043 0301 orr.w r3, r3, #1
8002ac4: b2db uxtb r3, r3
8002ac6: 2b01 cmp r3, #1
8002ac8: d102 bne.n 8002ad0 <HAL_RCC_OscConfig+0xe2c>
8002aca: 4b54 ldr r3, [pc, #336] ; (8002c1c <HAL_RCC_OscConfig+0xf78>)
8002acc: 681b ldr r3, [r3, #0]
8002ace: e027 b.n 8002b20 <HAL_RCC_OscConfig+0xe7c>
8002ad0: f507 7300 add.w r3, r7, #512 ; 0x200
8002ad4: f5a3 73dc sub.w r3, r3, #440 ; 0x1b8
8002ad8: f04f 7200 mov.w r2, #33554432 ; 0x2000000
8002adc: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002ade: f507 7300 add.w r3, r7, #512 ; 0x200
8002ae2: f5a3 73dc sub.w r3, r3, #440 ; 0x1b8
8002ae6: 681b ldr r3, [r3, #0]
8002ae8: fa93 f2a3 rbit r2, r3
8002aec: f507 7300 add.w r3, r7, #512 ; 0x200
8002af0: f5a3 73de sub.w r3, r3, #444 ; 0x1bc
8002af4: 601a str r2, [r3, #0]
8002af6: f507 7300 add.w r3, r7, #512 ; 0x200
8002afa: f5a3 73e0 sub.w r3, r3, #448 ; 0x1c0
8002afe: f04f 7200 mov.w r2, #33554432 ; 0x2000000
8002b02: 601a str r2, [r3, #0]
8002b04: f507 7300 add.w r3, r7, #512 ; 0x200
8002b08: f5a3 73e0 sub.w r3, r3, #448 ; 0x1c0
8002b0c: 681b ldr r3, [r3, #0]
8002b0e: fa93 f2a3 rbit r2, r3
8002b12: f507 7300 add.w r3, r7, #512 ; 0x200
8002b16: f5a3 73e2 sub.w r3, r3, #452 ; 0x1c4
8002b1a: 601a str r2, [r3, #0]
8002b1c: 4b3f ldr r3, [pc, #252] ; (8002c1c <HAL_RCC_OscConfig+0xf78>)
8002b1e: 6a5b ldr r3, [r3, #36] ; 0x24
8002b20: f507 7200 add.w r2, r7, #512 ; 0x200
8002b24: f5a2 72e4 sub.w r2, r2, #456 ; 0x1c8
8002b28: f04f 7100 mov.w r1, #33554432 ; 0x2000000
8002b2c: 6011 str r1, [r2, #0]
8002b2e: f507 7200 add.w r2, r7, #512 ; 0x200
8002b32: f5a2 72e4 sub.w r2, r2, #456 ; 0x1c8
8002b36: 6812 ldr r2, [r2, #0]
8002b38: fa92 f1a2 rbit r1, r2
8002b3c: f507 7200 add.w r2, r7, #512 ; 0x200
8002b40: f5a2 72e6 sub.w r2, r2, #460 ; 0x1cc
8002b44: 6011 str r1, [r2, #0]
return result;
8002b46: f507 7200 add.w r2, r7, #512 ; 0x200
8002b4a: f5a2 72e6 sub.w r2, r2, #460 ; 0x1cc
8002b4e: 6812 ldr r2, [r2, #0]
8002b50: fab2 f282 clz r2, r2
8002b54: b2d2 uxtb r2, r2
8002b56: f042 0220 orr.w r2, r2, #32
8002b5a: b2d2 uxtb r2, r2
8002b5c: f002 021f and.w r2, r2, #31
8002b60: 2101 movs r1, #1
8002b62: fa01 f202 lsl.w r2, r1, r2
8002b66: 4013 ands r3, r2
8002b68: 2b00 cmp r3, #0
8002b6a: d082 beq.n 8002a72 <HAL_RCC_OscConfig+0xdce>
8002b6c: e0cf b.n 8002d0e <HAL_RCC_OscConfig+0x106a>
8002b6e: f507 7300 add.w r3, r7, #512 ; 0x200
8002b72: f5a3 73e8 sub.w r3, r3, #464 ; 0x1d0
8002b76: f04f 7280 mov.w r2, #16777216 ; 0x1000000
8002b7a: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002b7c: f507 7300 add.w r3, r7, #512 ; 0x200
8002b80: f5a3 73e8 sub.w r3, r3, #464 ; 0x1d0
8002b84: 681b ldr r3, [r3, #0]
8002b86: fa93 f2a3 rbit r2, r3
8002b8a: f507 7300 add.w r3, r7, #512 ; 0x200
8002b8e: f5a3 73ea sub.w r3, r3, #468 ; 0x1d4
8002b92: 601a str r2, [r3, #0]
return result;
8002b94: f507 7300 add.w r3, r7, #512 ; 0x200
8002b98: f5a3 73ea sub.w r3, r3, #468 ; 0x1d4
8002b9c: 681b ldr r3, [r3, #0]
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8002b9e: fab3 f383 clz r3, r3
8002ba2: b2db uxtb r3, r3
8002ba4: f103 5384 add.w r3, r3, #276824064 ; 0x10800000
8002ba8: f503 1384 add.w r3, r3, #1081344 ; 0x108000
8002bac: 009b lsls r3, r3, #2
8002bae: 461a mov r2, r3
8002bb0: 2300 movs r3, #0
8002bb2: 6013 str r3, [r2, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8002bb4: f7fd feda bl 800096c <HAL_GetTick>
8002bb8: f8c7 01f8 str.w r0, [r7, #504] ; 0x1f8
/* Wait till PLL is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8002bbc: e009 b.n 8002bd2 <HAL_RCC_OscConfig+0xf2e>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8002bbe: f7fd fed5 bl 800096c <HAL_GetTick>
8002bc2: 4602 mov r2, r0
8002bc4: f8d7 31f8 ldr.w r3, [r7, #504] ; 0x1f8
8002bc8: 1ad3 subs r3, r2, r3
8002bca: 2b02 cmp r3, #2
8002bcc: d901 bls.n 8002bd2 <HAL_RCC_OscConfig+0xf2e>
{
return HAL_TIMEOUT;
8002bce: 2303 movs r3, #3
8002bd0: e09e b.n 8002d10 <HAL_RCC_OscConfig+0x106c>
8002bd2: f507 7300 add.w r3, r7, #512 ; 0x200
8002bd6: f5a3 73ec sub.w r3, r3, #472 ; 0x1d8
8002bda: f04f 7200 mov.w r2, #33554432 ; 0x2000000
8002bde: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002be0: f507 7300 add.w r3, r7, #512 ; 0x200
8002be4: f5a3 73ec sub.w r3, r3, #472 ; 0x1d8
8002be8: 681b ldr r3, [r3, #0]
8002bea: fa93 f2a3 rbit r2, r3
8002bee: f507 7300 add.w r3, r7, #512 ; 0x200
8002bf2: f5a3 73ee sub.w r3, r3, #476 ; 0x1dc
8002bf6: 601a str r2, [r3, #0]
return result;
8002bf8: f507 7300 add.w r3, r7, #512 ; 0x200
8002bfc: f5a3 73ee sub.w r3, r3, #476 ; 0x1dc
8002c00: 681b ldr r3, [r3, #0]
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8002c02: fab3 f383 clz r3, r3
8002c06: b2db uxtb r3, r3
8002c08: 095b lsrs r3, r3, #5
8002c0a: b2db uxtb r3, r3
8002c0c: f043 0301 orr.w r3, r3, #1
8002c10: b2db uxtb r3, r3
8002c12: 2b01 cmp r3, #1
8002c14: d104 bne.n 8002c20 <HAL_RCC_OscConfig+0xf7c>
8002c16: 4b01 ldr r3, [pc, #4] ; (8002c1c <HAL_RCC_OscConfig+0xf78>)
8002c18: 681b ldr r3, [r3, #0]
8002c1a: e029 b.n 8002c70 <HAL_RCC_OscConfig+0xfcc>
8002c1c: 40021000 .word 0x40021000
8002c20: f507 7300 add.w r3, r7, #512 ; 0x200
8002c24: f5a3 73f0 sub.w r3, r3, #480 ; 0x1e0
8002c28: f04f 7200 mov.w r2, #33554432 ; 0x2000000
8002c2c: 601a str r2, [r3, #0]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002c2e: f507 7300 add.w r3, r7, #512 ; 0x200
8002c32: f5a3 73f0 sub.w r3, r3, #480 ; 0x1e0
8002c36: 681b ldr r3, [r3, #0]
8002c38: fa93 f2a3 rbit r2, r3
8002c3c: f507 7300 add.w r3, r7, #512 ; 0x200
8002c40: f5a3 73f2 sub.w r3, r3, #484 ; 0x1e4
8002c44: 601a str r2, [r3, #0]
8002c46: f507 7300 add.w r3, r7, #512 ; 0x200
8002c4a: f5a3 73f4 sub.w r3, r3, #488 ; 0x1e8
8002c4e: f04f 7200 mov.w r2, #33554432 ; 0x2000000
8002c52: 601a str r2, [r3, #0]
8002c54: f507 7300 add.w r3, r7, #512 ; 0x200
8002c58: f5a3 73f4 sub.w r3, r3, #488 ; 0x1e8
8002c5c: 681b ldr r3, [r3, #0]
8002c5e: fa93 f2a3 rbit r2, r3
8002c62: f507 7300 add.w r3, r7, #512 ; 0x200
8002c66: f5a3 73f6 sub.w r3, r3, #492 ; 0x1ec
8002c6a: 601a str r2, [r3, #0]
8002c6c: 4b2b ldr r3, [pc, #172] ; (8002d1c <HAL_RCC_OscConfig+0x1078>)
8002c6e: 6a5b ldr r3, [r3, #36] ; 0x24
8002c70: f507 7200 add.w r2, r7, #512 ; 0x200
8002c74: f5a2 72f8 sub.w r2, r2, #496 ; 0x1f0
8002c78: f04f 7100 mov.w r1, #33554432 ; 0x2000000
8002c7c: 6011 str r1, [r2, #0]
8002c7e: f507 7200 add.w r2, r7, #512 ; 0x200
8002c82: f5a2 72f8 sub.w r2, r2, #496 ; 0x1f0
8002c86: 6812 ldr r2, [r2, #0]
8002c88: fa92 f1a2 rbit r1, r2
8002c8c: f507 7200 add.w r2, r7, #512 ; 0x200
8002c90: f5a2 72fa sub.w r2, r2, #500 ; 0x1f4
8002c94: 6011 str r1, [r2, #0]
return result;
8002c96: f507 7200 add.w r2, r7, #512 ; 0x200
8002c9a: f5a2 72fa sub.w r2, r2, #500 ; 0x1f4
8002c9e: 6812 ldr r2, [r2, #0]
8002ca0: fab2 f282 clz r2, r2
8002ca4: b2d2 uxtb r2, r2
8002ca6: f042 0220 orr.w r2, r2, #32
8002caa: b2d2 uxtb r2, r2
8002cac: f002 021f and.w r2, r2, #31
8002cb0: 2101 movs r1, #1
8002cb2: fa01 f202 lsl.w r2, r1, r2
8002cb6: 4013 ands r3, r2
8002cb8: 2b00 cmp r3, #0
8002cba: d180 bne.n 8002bbe <HAL_RCC_OscConfig+0xf1a>
8002cbc: e027 b.n 8002d0e <HAL_RCC_OscConfig+0x106a>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
8002cbe: f507 7300 add.w r3, r7, #512 ; 0x200
8002cc2: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
8002cc6: 681b ldr r3, [r3, #0]
8002cc8: 69db ldr r3, [r3, #28]
8002cca: 2b01 cmp r3, #1
8002ccc: d101 bne.n 8002cd2 <HAL_RCC_OscConfig+0x102e>
{
return HAL_ERROR;
8002cce: 2301 movs r3, #1
8002cd0: e01e b.n 8002d10 <HAL_RCC_OscConfig+0x106c>
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->CFGR;
8002cd2: 4b12 ldr r3, [pc, #72] ; (8002d1c <HAL_RCC_OscConfig+0x1078>)
8002cd4: 685b ldr r3, [r3, #4]
8002cd6: f8c7 31f4 str.w r3, [r7, #500] ; 0x1f4
pll_config2 = RCC->CFGR2;
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
(READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) ||
(READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV))
#else
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8002cda: f8d7 31f4 ldr.w r3, [r7, #500] ; 0x1f4
8002cde: f403 3280 and.w r2, r3, #65536 ; 0x10000
8002ce2: f507 7300 add.w r3, r7, #512 ; 0x200
8002ce6: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
8002cea: 681b ldr r3, [r3, #0]
8002cec: 6a1b ldr r3, [r3, #32]
8002cee: 429a cmp r2, r3
8002cf0: d10b bne.n 8002d0a <HAL_RCC_OscConfig+0x1066>
(READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL))
8002cf2: f8d7 31f4 ldr.w r3, [r7, #500] ; 0x1f4
8002cf6: f403 1270 and.w r2, r3, #3932160 ; 0x3c0000
8002cfa: f507 7300 add.w r3, r7, #512 ; 0x200
8002cfe: f5a3 73fe sub.w r3, r3, #508 ; 0x1fc
8002d02: 681b ldr r3, [r3, #0]
8002d04: 6a5b ldr r3, [r3, #36] ; 0x24
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8002d06: 429a cmp r2, r3
8002d08: d001 beq.n 8002d0e <HAL_RCC_OscConfig+0x106a>
#endif
{
return HAL_ERROR;
8002d0a: 2301 movs r3, #1
8002d0c: e000 b.n 8002d10 <HAL_RCC_OscConfig+0x106c>
}
}
}
}
return HAL_OK;
8002d0e: 2300 movs r3, #0
}
8002d10: 4618 mov r0, r3
8002d12: f507 7700 add.w r7, r7, #512 ; 0x200
8002d16: 46bd mov sp, r7
8002d18: bd80 pop {r7, pc}
8002d1a: bf00 nop
8002d1c: 40021000 .word 0x40021000
08002d20 <HAL_RCC_ClockConfig>:
* You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
* currently used as system clock source.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8002d20: b580 push {r7, lr}
8002d22: b09e sub sp, #120 ; 0x78
8002d24: af00 add r7, sp, #0
8002d26: 6078 str r0, [r7, #4]
8002d28: 6039 str r1, [r7, #0]
uint32_t tickstart = 0U;
8002d2a: 2300 movs r3, #0
8002d2c: 677b str r3, [r7, #116] ; 0x74
/* Check Null pointer */
if(RCC_ClkInitStruct == NULL)
8002d2e: 687b ldr r3, [r7, #4]
8002d30: 2b00 cmp r3, #0
8002d32: d101 bne.n 8002d38 <HAL_RCC_ClockConfig+0x18>
{
return HAL_ERROR;
8002d34: 2301 movs r3, #1
8002d36: e162 b.n 8002ffe <HAL_RCC_ClockConfig+0x2de>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if(FLatency > __HAL_FLASH_GET_LATENCY())
8002d38: 4b90 ldr r3, [pc, #576] ; (8002f7c <HAL_RCC_ClockConfig+0x25c>)
8002d3a: 681b ldr r3, [r3, #0]
8002d3c: f003 0307 and.w r3, r3, #7
8002d40: 683a ldr r2, [r7, #0]
8002d42: 429a cmp r2, r3
8002d44: d910 bls.n 8002d68 <HAL_RCC_ClockConfig+0x48>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8002d46: 4b8d ldr r3, [pc, #564] ; (8002f7c <HAL_RCC_ClockConfig+0x25c>)
8002d48: 681b ldr r3, [r3, #0]
8002d4a: f023 0207 bic.w r2, r3, #7
8002d4e: 498b ldr r1, [pc, #556] ; (8002f7c <HAL_RCC_ClockConfig+0x25c>)
8002d50: 683b ldr r3, [r7, #0]
8002d52: 4313 orrs r3, r2
8002d54: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
8002d56: 4b89 ldr r3, [pc, #548] ; (8002f7c <HAL_RCC_ClockConfig+0x25c>)
8002d58: 681b ldr r3, [r3, #0]
8002d5a: f003 0307 and.w r3, r3, #7
8002d5e: 683a ldr r2, [r7, #0]
8002d60: 429a cmp r2, r3
8002d62: d001 beq.n 8002d68 <HAL_RCC_ClockConfig+0x48>
{
return HAL_ERROR;
8002d64: 2301 movs r3, #1
8002d66: e14a b.n 8002ffe <HAL_RCC_ClockConfig+0x2de>
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
8002d68: 687b ldr r3, [r7, #4]
8002d6a: 681b ldr r3, [r3, #0]
8002d6c: f003 0302 and.w r3, r3, #2
8002d70: 2b00 cmp r3, #0
8002d72: d008 beq.n 8002d86 <HAL_RCC_ClockConfig+0x66>
{
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8002d74: 4b82 ldr r3, [pc, #520] ; (8002f80 <HAL_RCC_ClockConfig+0x260>)
8002d76: 685b ldr r3, [r3, #4]
8002d78: f023 02f0 bic.w r2, r3, #240 ; 0xf0
8002d7c: 687b ldr r3, [r7, #4]
8002d7e: 689b ldr r3, [r3, #8]
8002d80: 497f ldr r1, [pc, #508] ; (8002f80 <HAL_RCC_ClockConfig+0x260>)
8002d82: 4313 orrs r3, r2
8002d84: 604b str r3, [r1, #4]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8002d86: 687b ldr r3, [r7, #4]
8002d88: 681b ldr r3, [r3, #0]
8002d8a: f003 0301 and.w r3, r3, #1
8002d8e: 2b00 cmp r3, #0
8002d90: f000 80dc beq.w 8002f4c <HAL_RCC_ClockConfig+0x22c>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8002d94: 687b ldr r3, [r7, #4]
8002d96: 685b ldr r3, [r3, #4]
8002d98: 2b01 cmp r3, #1
8002d9a: d13c bne.n 8002e16 <HAL_RCC_ClockConfig+0xf6>
8002d9c: f44f 3300 mov.w r3, #131072 ; 0x20000
8002da0: 673b str r3, [r7, #112] ; 0x70
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002da2: 6f3b ldr r3, [r7, #112] ; 0x70
8002da4: fa93 f3a3 rbit r3, r3
8002da8: 66fb str r3, [r7, #108] ; 0x6c
return result;
8002daa: 6efb ldr r3, [r7, #108] ; 0x6c
{
/* Check the HSE ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8002dac: fab3 f383 clz r3, r3
8002db0: b2db uxtb r3, r3
8002db2: 095b lsrs r3, r3, #5
8002db4: b2db uxtb r3, r3
8002db6: f043 0301 orr.w r3, r3, #1
8002dba: b2db uxtb r3, r3
8002dbc: 2b01 cmp r3, #1
8002dbe: d102 bne.n 8002dc6 <HAL_RCC_ClockConfig+0xa6>
8002dc0: 4b6f ldr r3, [pc, #444] ; (8002f80 <HAL_RCC_ClockConfig+0x260>)
8002dc2: 681b ldr r3, [r3, #0]
8002dc4: e00f b.n 8002de6 <HAL_RCC_ClockConfig+0xc6>
8002dc6: f44f 3300 mov.w r3, #131072 ; 0x20000
8002dca: 66bb str r3, [r7, #104] ; 0x68
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002dcc: 6ebb ldr r3, [r7, #104] ; 0x68
8002dce: fa93 f3a3 rbit r3, r3
8002dd2: 667b str r3, [r7, #100] ; 0x64
8002dd4: f44f 3300 mov.w r3, #131072 ; 0x20000
8002dd8: 663b str r3, [r7, #96] ; 0x60
8002dda: 6e3b ldr r3, [r7, #96] ; 0x60
8002ddc: fa93 f3a3 rbit r3, r3
8002de0: 65fb str r3, [r7, #92] ; 0x5c
8002de2: 4b67 ldr r3, [pc, #412] ; (8002f80 <HAL_RCC_ClockConfig+0x260>)
8002de4: 6a5b ldr r3, [r3, #36] ; 0x24
8002de6: f44f 3200 mov.w r2, #131072 ; 0x20000
8002dea: 65ba str r2, [r7, #88] ; 0x58
8002dec: 6dba ldr r2, [r7, #88] ; 0x58
8002dee: fa92 f2a2 rbit r2, r2
8002df2: 657a str r2, [r7, #84] ; 0x54
return result;
8002df4: 6d7a ldr r2, [r7, #84] ; 0x54
8002df6: fab2 f282 clz r2, r2
8002dfa: b2d2 uxtb r2, r2
8002dfc: f042 0220 orr.w r2, r2, #32
8002e00: b2d2 uxtb r2, r2
8002e02: f002 021f and.w r2, r2, #31
8002e06: 2101 movs r1, #1
8002e08: fa01 f202 lsl.w r2, r1, r2
8002e0c: 4013 ands r3, r2
8002e0e: 2b00 cmp r3, #0
8002e10: d17b bne.n 8002f0a <HAL_RCC_ClockConfig+0x1ea>
{
return HAL_ERROR;
8002e12: 2301 movs r3, #1
8002e14: e0f3 b.n 8002ffe <HAL_RCC_ClockConfig+0x2de>
}
}
/* PLL is selected as System Clock Source */
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
8002e16: 687b ldr r3, [r7, #4]
8002e18: 685b ldr r3, [r3, #4]
8002e1a: 2b02 cmp r3, #2
8002e1c: d13c bne.n 8002e98 <HAL_RCC_ClockConfig+0x178>
8002e1e: f04f 7300 mov.w r3, #33554432 ; 0x2000000
8002e22: 653b str r3, [r7, #80] ; 0x50
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002e24: 6d3b ldr r3, [r7, #80] ; 0x50
8002e26: fa93 f3a3 rbit r3, r3
8002e2a: 64fb str r3, [r7, #76] ; 0x4c
return result;
8002e2c: 6cfb ldr r3, [r7, #76] ; 0x4c
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8002e2e: fab3 f383 clz r3, r3
8002e32: b2db uxtb r3, r3
8002e34: 095b lsrs r3, r3, #5
8002e36: b2db uxtb r3, r3
8002e38: f043 0301 orr.w r3, r3, #1
8002e3c: b2db uxtb r3, r3
8002e3e: 2b01 cmp r3, #1
8002e40: d102 bne.n 8002e48 <HAL_RCC_ClockConfig+0x128>
8002e42: 4b4f ldr r3, [pc, #316] ; (8002f80 <HAL_RCC_ClockConfig+0x260>)
8002e44: 681b ldr r3, [r3, #0]
8002e46: e00f b.n 8002e68 <HAL_RCC_ClockConfig+0x148>
8002e48: f04f 7300 mov.w r3, #33554432 ; 0x2000000
8002e4c: 64bb str r3, [r7, #72] ; 0x48
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002e4e: 6cbb ldr r3, [r7, #72] ; 0x48
8002e50: fa93 f3a3 rbit r3, r3
8002e54: 647b str r3, [r7, #68] ; 0x44
8002e56: f04f 7300 mov.w r3, #33554432 ; 0x2000000
8002e5a: 643b str r3, [r7, #64] ; 0x40
8002e5c: 6c3b ldr r3, [r7, #64] ; 0x40
8002e5e: fa93 f3a3 rbit r3, r3
8002e62: 63fb str r3, [r7, #60] ; 0x3c
8002e64: 4b46 ldr r3, [pc, #280] ; (8002f80 <HAL_RCC_ClockConfig+0x260>)
8002e66: 6a5b ldr r3, [r3, #36] ; 0x24
8002e68: f04f 7200 mov.w r2, #33554432 ; 0x2000000
8002e6c: 63ba str r2, [r7, #56] ; 0x38
8002e6e: 6bba ldr r2, [r7, #56] ; 0x38
8002e70: fa92 f2a2 rbit r2, r2
8002e74: 637a str r2, [r7, #52] ; 0x34
return result;
8002e76: 6b7a ldr r2, [r7, #52] ; 0x34
8002e78: fab2 f282 clz r2, r2
8002e7c: b2d2 uxtb r2, r2
8002e7e: f042 0220 orr.w r2, r2, #32
8002e82: b2d2 uxtb r2, r2
8002e84: f002 021f and.w r2, r2, #31
8002e88: 2101 movs r1, #1
8002e8a: fa01 f202 lsl.w r2, r1, r2
8002e8e: 4013 ands r3, r2
8002e90: 2b00 cmp r3, #0
8002e92: d13a bne.n 8002f0a <HAL_RCC_ClockConfig+0x1ea>
{
return HAL_ERROR;
8002e94: 2301 movs r3, #1
8002e96: e0b2 b.n 8002ffe <HAL_RCC_ClockConfig+0x2de>
8002e98: 2302 movs r3, #2
8002e9a: 633b str r3, [r7, #48] ; 0x30
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002e9c: 6b3b ldr r3, [r7, #48] ; 0x30
8002e9e: fa93 f3a3 rbit r3, r3
8002ea2: 62fb str r3, [r7, #44] ; 0x2c
return result;
8002ea4: 6afb ldr r3, [r7, #44] ; 0x2c
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8002ea6: fab3 f383 clz r3, r3
8002eaa: b2db uxtb r3, r3
8002eac: 095b lsrs r3, r3, #5
8002eae: b2db uxtb r3, r3
8002eb0: f043 0301 orr.w r3, r3, #1
8002eb4: b2db uxtb r3, r3
8002eb6: 2b01 cmp r3, #1
8002eb8: d102 bne.n 8002ec0 <HAL_RCC_ClockConfig+0x1a0>
8002eba: 4b31 ldr r3, [pc, #196] ; (8002f80 <HAL_RCC_ClockConfig+0x260>)
8002ebc: 681b ldr r3, [r3, #0]
8002ebe: e00d b.n 8002edc <HAL_RCC_ClockConfig+0x1bc>
8002ec0: 2302 movs r3, #2
8002ec2: 62bb str r3, [r7, #40] ; 0x28
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002ec4: 6abb ldr r3, [r7, #40] ; 0x28
8002ec6: fa93 f3a3 rbit r3, r3
8002eca: 627b str r3, [r7, #36] ; 0x24
8002ecc: 2302 movs r3, #2
8002ece: 623b str r3, [r7, #32]
8002ed0: 6a3b ldr r3, [r7, #32]
8002ed2: fa93 f3a3 rbit r3, r3
8002ed6: 61fb str r3, [r7, #28]
8002ed8: 4b29 ldr r3, [pc, #164] ; (8002f80 <HAL_RCC_ClockConfig+0x260>)
8002eda: 6a5b ldr r3, [r3, #36] ; 0x24
8002edc: 2202 movs r2, #2
8002ede: 61ba str r2, [r7, #24]
8002ee0: 69ba ldr r2, [r7, #24]
8002ee2: fa92 f2a2 rbit r2, r2
8002ee6: 617a str r2, [r7, #20]
return result;
8002ee8: 697a ldr r2, [r7, #20]
8002eea: fab2 f282 clz r2, r2
8002eee: b2d2 uxtb r2, r2
8002ef0: f042 0220 orr.w r2, r2, #32
8002ef4: b2d2 uxtb r2, r2
8002ef6: f002 021f and.w r2, r2, #31
8002efa: 2101 movs r1, #1
8002efc: fa01 f202 lsl.w r2, r1, r2
8002f00: 4013 ands r3, r2
8002f02: 2b00 cmp r3, #0
8002f04: d101 bne.n 8002f0a <HAL_RCC_ClockConfig+0x1ea>
{
return HAL_ERROR;
8002f06: 2301 movs r3, #1
8002f08: e079 b.n 8002ffe <HAL_RCC_ClockConfig+0x2de>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
8002f0a: 4b1d ldr r3, [pc, #116] ; (8002f80 <HAL_RCC_ClockConfig+0x260>)
8002f0c: 685b ldr r3, [r3, #4]
8002f0e: f023 0203 bic.w r2, r3, #3
8002f12: 687b ldr r3, [r7, #4]
8002f14: 685b ldr r3, [r3, #4]
8002f16: 491a ldr r1, [pc, #104] ; (8002f80 <HAL_RCC_ClockConfig+0x260>)
8002f18: 4313 orrs r3, r2
8002f1a: 604b str r3, [r1, #4]
/* Get Start Tick */
tickstart = HAL_GetTick();
8002f1c: f7fd fd26 bl 800096c <HAL_GetTick>
8002f20: 6778 str r0, [r7, #116] ; 0x74
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8002f22: e00a b.n 8002f3a <HAL_RCC_ClockConfig+0x21a>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8002f24: f7fd fd22 bl 800096c <HAL_GetTick>
8002f28: 4602 mov r2, r0
8002f2a: 6f7b ldr r3, [r7, #116] ; 0x74
8002f2c: 1ad3 subs r3, r2, r3
8002f2e: f241 3288 movw r2, #5000 ; 0x1388
8002f32: 4293 cmp r3, r2
8002f34: d901 bls.n 8002f3a <HAL_RCC_ClockConfig+0x21a>
{
return HAL_TIMEOUT;
8002f36: 2303 movs r3, #3
8002f38: e061 b.n 8002ffe <HAL_RCC_ClockConfig+0x2de>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8002f3a: 4b11 ldr r3, [pc, #68] ; (8002f80 <HAL_RCC_ClockConfig+0x260>)
8002f3c: 685b ldr r3, [r3, #4]
8002f3e: f003 020c and.w r2, r3, #12
8002f42: 687b ldr r3, [r7, #4]
8002f44: 685b ldr r3, [r3, #4]
8002f46: 009b lsls r3, r3, #2
8002f48: 429a cmp r2, r3
8002f4a: d1eb bne.n 8002f24 <HAL_RCC_ClockConfig+0x204>
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if(FLatency < __HAL_FLASH_GET_LATENCY())
8002f4c: 4b0b ldr r3, [pc, #44] ; (8002f7c <HAL_RCC_ClockConfig+0x25c>)
8002f4e: 681b ldr r3, [r3, #0]
8002f50: f003 0307 and.w r3, r3, #7
8002f54: 683a ldr r2, [r7, #0]
8002f56: 429a cmp r2, r3
8002f58: d214 bcs.n 8002f84 <HAL_RCC_ClockConfig+0x264>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8002f5a: 4b08 ldr r3, [pc, #32] ; (8002f7c <HAL_RCC_ClockConfig+0x25c>)
8002f5c: 681b ldr r3, [r3, #0]
8002f5e: f023 0207 bic.w r2, r3, #7
8002f62: 4906 ldr r1, [pc, #24] ; (8002f7c <HAL_RCC_ClockConfig+0x25c>)
8002f64: 683b ldr r3, [r7, #0]
8002f66: 4313 orrs r3, r2
8002f68: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
8002f6a: 4b04 ldr r3, [pc, #16] ; (8002f7c <HAL_RCC_ClockConfig+0x25c>)
8002f6c: 681b ldr r3, [r3, #0]
8002f6e: f003 0307 and.w r3, r3, #7
8002f72: 683a ldr r2, [r7, #0]
8002f74: 429a cmp r2, r3
8002f76: d005 beq.n 8002f84 <HAL_RCC_ClockConfig+0x264>
{
return HAL_ERROR;
8002f78: 2301 movs r3, #1
8002f7a: e040 b.n 8002ffe <HAL_RCC_ClockConfig+0x2de>
8002f7c: 40022000 .word 0x40022000
8002f80: 40021000 .word 0x40021000
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8002f84: 687b ldr r3, [r7, #4]
8002f86: 681b ldr r3, [r3, #0]
8002f88: f003 0304 and.w r3, r3, #4
8002f8c: 2b00 cmp r3, #0
8002f8e: d008 beq.n 8002fa2 <HAL_RCC_ClockConfig+0x282>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
8002f90: 4b1d ldr r3, [pc, #116] ; (8003008 <HAL_RCC_ClockConfig+0x2e8>)
8002f92: 685b ldr r3, [r3, #4]
8002f94: f423 62e0 bic.w r2, r3, #1792 ; 0x700
8002f98: 687b ldr r3, [r7, #4]
8002f9a: 68db ldr r3, [r3, #12]
8002f9c: 491a ldr r1, [pc, #104] ; (8003008 <HAL_RCC_ClockConfig+0x2e8>)
8002f9e: 4313 orrs r3, r2
8002fa0: 604b str r3, [r1, #4]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8002fa2: 687b ldr r3, [r7, #4]
8002fa4: 681b ldr r3, [r3, #0]
8002fa6: f003 0308 and.w r3, r3, #8
8002faa: 2b00 cmp r3, #0
8002fac: d009 beq.n 8002fc2 <HAL_RCC_ClockConfig+0x2a2>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
8002fae: 4b16 ldr r3, [pc, #88] ; (8003008 <HAL_RCC_ClockConfig+0x2e8>)
8002fb0: 685b ldr r3, [r3, #4]
8002fb2: f423 5260 bic.w r2, r3, #14336 ; 0x3800
8002fb6: 687b ldr r3, [r7, #4]
8002fb8: 691b ldr r3, [r3, #16]
8002fba: 00db lsls r3, r3, #3
8002fbc: 4912 ldr r1, [pc, #72] ; (8003008 <HAL_RCC_ClockConfig+0x2e8>)
8002fbe: 4313 orrs r3, r2
8002fc0: 604b str r3, [r1, #4]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER];
8002fc2: f000 f829 bl 8003018 <HAL_RCC_GetSysClockFreq>
8002fc6: 4601 mov r1, r0
8002fc8: 4b0f ldr r3, [pc, #60] ; (8003008 <HAL_RCC_ClockConfig+0x2e8>)
8002fca: 685b ldr r3, [r3, #4]
8002fcc: f003 03f0 and.w r3, r3, #240 ; 0xf0
8002fd0: 22f0 movs r2, #240 ; 0xf0
8002fd2: 613a str r2, [r7, #16]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002fd4: 693a ldr r2, [r7, #16]
8002fd6: fa92 f2a2 rbit r2, r2
8002fda: 60fa str r2, [r7, #12]
return result;
8002fdc: 68fa ldr r2, [r7, #12]
8002fde: fab2 f282 clz r2, r2
8002fe2: b2d2 uxtb r2, r2
8002fe4: 40d3 lsrs r3, r2
8002fe6: 4a09 ldr r2, [pc, #36] ; (800300c <HAL_RCC_ClockConfig+0x2ec>)
8002fe8: 5cd3 ldrb r3, [r2, r3]
8002fea: fa21 f303 lsr.w r3, r1, r3
8002fee: 4a08 ldr r2, [pc, #32] ; (8003010 <HAL_RCC_ClockConfig+0x2f0>)
8002ff0: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick (uwTickPrio);
8002ff2: 4b08 ldr r3, [pc, #32] ; (8003014 <HAL_RCC_ClockConfig+0x2f4>)
8002ff4: 681b ldr r3, [r3, #0]
8002ff6: 4618 mov r0, r3
8002ff8: f7fd fc74 bl 80008e4 <HAL_InitTick>
return HAL_OK;
8002ffc: 2300 movs r3, #0
}
8002ffe: 4618 mov r0, r3
8003000: 3778 adds r7, #120 ; 0x78
8003002: 46bd mov sp, r7
8003004: bd80 pop {r7, pc}
8003006: bf00 nop
8003008: 40021000 .word 0x40021000
800300c: 08004a08 .word 0x08004a08
8003010: 20000004 .word 0x20000004
8003014: 20000008 .word 0x20000008
08003018 <HAL_RCC_GetSysClockFreq>:
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
8003018: b480 push {r7}
800301a: b08b sub sp, #44 ; 0x2c
800301c: af00 add r7, sp, #0
uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
800301e: 2300 movs r3, #0
8003020: 61fb str r3, [r7, #28]
8003022: 2300 movs r3, #0
8003024: 61bb str r3, [r7, #24]
8003026: 2300 movs r3, #0
8003028: 627b str r3, [r7, #36] ; 0x24
800302a: 2300 movs r3, #0
800302c: 617b str r3, [r7, #20]
uint32_t sysclockfreq = 0U;
800302e: 2300 movs r3, #0
8003030: 623b str r3, [r7, #32]
tmpreg = RCC->CFGR;
8003032: 4b29 ldr r3, [pc, #164] ; (80030d8 <HAL_RCC_GetSysClockFreq+0xc0>)
8003034: 685b ldr r3, [r3, #4]
8003036: 61fb str r3, [r7, #28]
/* Get SYSCLK source -------------------------------------------------------*/
switch (tmpreg & RCC_CFGR_SWS)
8003038: 69fb ldr r3, [r7, #28]
800303a: f003 030c and.w r3, r3, #12
800303e: 2b04 cmp r3, #4
8003040: d002 beq.n 8003048 <HAL_RCC_GetSysClockFreq+0x30>
8003042: 2b08 cmp r3, #8
8003044: d003 beq.n 800304e <HAL_RCC_GetSysClockFreq+0x36>
8003046: e03c b.n 80030c2 <HAL_RCC_GetSysClockFreq+0xaa>
{
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
{
sysclockfreq = HSE_VALUE;
8003048: 4b24 ldr r3, [pc, #144] ; (80030dc <HAL_RCC_GetSysClockFreq+0xc4>)
800304a: 623b str r3, [r7, #32]
break;
800304c: e03c b.n 80030c8 <HAL_RCC_GetSysClockFreq+0xb0>
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
{
pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> POSITION_VAL(RCC_CFGR_PLLMUL)];
800304e: 69fb ldr r3, [r7, #28]
8003050: f403 1370 and.w r3, r3, #3932160 ; 0x3c0000
8003054: f44f 1270 mov.w r2, #3932160 ; 0x3c0000
8003058: 60ba str r2, [r7, #8]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
800305a: 68ba ldr r2, [r7, #8]
800305c: fa92 f2a2 rbit r2, r2
8003060: 607a str r2, [r7, #4]
return result;
8003062: 687a ldr r2, [r7, #4]
8003064: fab2 f282 clz r2, r2
8003068: b2d2 uxtb r2, r2
800306a: 40d3 lsrs r3, r2
800306c: 4a1c ldr r2, [pc, #112] ; (80030e0 <HAL_RCC_GetSysClockFreq+0xc8>)
800306e: 5cd3 ldrb r3, [r2, r3]
8003070: 617b str r3, [r7, #20]
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> POSITION_VAL(RCC_CFGR2_PREDIV)];
8003072: 4b19 ldr r3, [pc, #100] ; (80030d8 <HAL_RCC_GetSysClockFreq+0xc0>)
8003074: 6adb ldr r3, [r3, #44] ; 0x2c
8003076: f003 030f and.w r3, r3, #15
800307a: 220f movs r2, #15
800307c: 613a str r2, [r7, #16]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
800307e: 693a ldr r2, [r7, #16]
8003080: fa92 f2a2 rbit r2, r2
8003084: 60fa str r2, [r7, #12]
return result;
8003086: 68fa ldr r2, [r7, #12]
8003088: fab2 f282 clz r2, r2
800308c: b2d2 uxtb r2, r2
800308e: 40d3 lsrs r3, r2
8003090: 4a14 ldr r2, [pc, #80] ; (80030e4 <HAL_RCC_GetSysClockFreq+0xcc>)
8003092: 5cd3 ldrb r3, [r2, r3]
8003094: 61bb str r3, [r7, #24]
#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI)
8003096: 69fb ldr r3, [r7, #28]
8003098: f403 3380 and.w r3, r3, #65536 ; 0x10000
800309c: 2b00 cmp r3, #0
800309e: d008 beq.n 80030b2 <HAL_RCC_GetSysClockFreq+0x9a>
{
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
80030a0: 4a0e ldr r2, [pc, #56] ; (80030dc <HAL_RCC_GetSysClockFreq+0xc4>)
80030a2: 69bb ldr r3, [r7, #24]
80030a4: fbb2 f2f3 udiv r2, r2, r3
80030a8: 697b ldr r3, [r7, #20]
80030aa: fb02 f303 mul.w r3, r2, r3
80030ae: 627b str r3, [r7, #36] ; 0x24
80030b0: e004 b.n 80030bc <HAL_RCC_GetSysClockFreq+0xa4>
}
else
{
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
pllclk = (uint32_t)((uint64_t) (HSI_VALUE >> 1U) * ((uint64_t) pllmul));
80030b2: 697b ldr r3, [r7, #20]
80030b4: 4a0c ldr r2, [pc, #48] ; (80030e8 <HAL_RCC_GetSysClockFreq+0xd0>)
80030b6: fb02 f303 mul.w r3, r2, r3
80030ba: 627b str r3, [r7, #36] ; 0x24
{
/* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */
pllclk = (uint32_t)((uint64_t) HSI_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
}
#endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
sysclockfreq = pllclk;
80030bc: 6a7b ldr r3, [r7, #36] ; 0x24
80030be: 623b str r3, [r7, #32]
break;
80030c0: e002 b.n 80030c8 <HAL_RCC_GetSysClockFreq+0xb0>
}
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
default: /* HSI used as system clock */
{
sysclockfreq = HSI_VALUE;
80030c2: 4b06 ldr r3, [pc, #24] ; (80030dc <HAL_RCC_GetSysClockFreq+0xc4>)
80030c4: 623b str r3, [r7, #32]
break;
80030c6: bf00 nop
}
}
return sysclockfreq;
80030c8: 6a3b ldr r3, [r7, #32]
}
80030ca: 4618 mov r0, r3
80030cc: 372c adds r7, #44 ; 0x2c
80030ce: 46bd mov sp, r7
80030d0: f85d 7b04 ldr.w r7, [sp], #4
80030d4: 4770 bx lr
80030d6: bf00 nop
80030d8: 40021000 .word 0x40021000
80030dc: 007a1200 .word 0x007a1200
80030e0: 08004a20 .word 0x08004a20
80030e4: 08004a30 .word 0x08004a30
80030e8: 003d0900 .word 0x003d0900
080030ec <HAL_RCC_GetHCLKFreq>:
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
* and updated within this function
* @retval HCLK frequency
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
80030ec: b480 push {r7}
80030ee: af00 add r7, sp, #0
return SystemCoreClock;
80030f0: 4b03 ldr r3, [pc, #12] ; (8003100 <HAL_RCC_GetHCLKFreq+0x14>)
80030f2: 681b ldr r3, [r3, #0]
}
80030f4: 4618 mov r0, r3
80030f6: 46bd mov sp, r7
80030f8: f85d 7b04 ldr.w r7, [sp], #4
80030fc: 4770 bx lr
80030fe: bf00 nop
8003100: 20000004 .word 0x20000004
08003104 <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
8003104: b580 push {r7, lr}
8003106: b082 sub sp, #8
8003108: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_BITNUMBER]);
800310a: f7ff ffef bl 80030ec <HAL_RCC_GetHCLKFreq>
800310e: 4601 mov r1, r0
8003110: 4b0b ldr r3, [pc, #44] ; (8003140 <HAL_RCC_GetPCLK1Freq+0x3c>)
8003112: 685b ldr r3, [r3, #4]
8003114: f403 63e0 and.w r3, r3, #1792 ; 0x700
8003118: f44f 62e0 mov.w r2, #1792 ; 0x700
800311c: 607a str r2, [r7, #4]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
800311e: 687a ldr r2, [r7, #4]
8003120: fa92 f2a2 rbit r2, r2
8003124: 603a str r2, [r7, #0]
return result;
8003126: 683a ldr r2, [r7, #0]
8003128: fab2 f282 clz r2, r2
800312c: b2d2 uxtb r2, r2
800312e: 40d3 lsrs r3, r2
8003130: 4a04 ldr r2, [pc, #16] ; (8003144 <HAL_RCC_GetPCLK1Freq+0x40>)
8003132: 5cd3 ldrb r3, [r2, r3]
8003134: fa21 f303 lsr.w r3, r1, r3
}
8003138: 4618 mov r0, r3
800313a: 3708 adds r7, #8
800313c: 46bd mov sp, r7
800313e: bd80 pop {r7, pc}
8003140: 40021000 .word 0x40021000
8003144: 08004a18 .word 0x08004a18
08003148 <HAL_RCC_GetPCLK2Freq>:
* @note Each time PCLK2 changes, this function must be called to update the
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK2 frequency
*/
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
8003148: b580 push {r7, lr}
800314a: b082 sub sp, #8
800314c: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_BITNUMBER]);
800314e: f7ff ffcd bl 80030ec <HAL_RCC_GetHCLKFreq>
8003152: 4601 mov r1, r0
8003154: 4b0b ldr r3, [pc, #44] ; (8003184 <HAL_RCC_GetPCLK2Freq+0x3c>)
8003156: 685b ldr r3, [r3, #4]
8003158: f403 5360 and.w r3, r3, #14336 ; 0x3800
800315c: f44f 5260 mov.w r2, #14336 ; 0x3800
8003160: 607a str r2, [r7, #4]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8003162: 687a ldr r2, [r7, #4]
8003164: fa92 f2a2 rbit r2, r2
8003168: 603a str r2, [r7, #0]
return result;
800316a: 683a ldr r2, [r7, #0]
800316c: fab2 f282 clz r2, r2
8003170: b2d2 uxtb r2, r2
8003172: 40d3 lsrs r3, r2
8003174: 4a04 ldr r2, [pc, #16] ; (8003188 <HAL_RCC_GetPCLK2Freq+0x40>)
8003176: 5cd3 ldrb r3, [r2, r3]
8003178: fa21 f303 lsr.w r3, r1, r3
}
800317c: 4618 mov r0, r3
800317e: 3708 adds r7, #8
8003180: 46bd mov sp, r7
8003182: bd80 pop {r7, pc}
8003184: 40021000 .word 0x40021000
8003188: 08004a18 .word 0x08004a18
0800318c <HAL_RCCEx_PeriphCLKConfig>:
* When the TIMx clock source is PLL clock, so the TIMx clock is PLL clock x 2.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
800318c: b580 push {r7, lr}
800318e: b092 sub sp, #72 ; 0x48
8003190: af00 add r7, sp, #0
8003192: 6078 str r0, [r7, #4]
uint32_t tickstart = 0U;
8003194: 2300 movs r3, #0
8003196: 643b str r3, [r7, #64] ; 0x40
uint32_t temp_reg = 0U;
8003198: 2300 movs r3, #0
800319a: 63fb str r3, [r7, #60] ; 0x3c
FlagStatus pwrclkchanged = RESET;
800319c: 2300 movs r3, #0
800319e: f887 3047 strb.w r3, [r7, #71] ; 0x47
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
/*---------------------------- RTC configuration -------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
80031a2: 687b ldr r3, [r7, #4]
80031a4: 681b ldr r3, [r3, #0]
80031a6: f403 3380 and.w r3, r3, #65536 ; 0x10000
80031aa: 2b00 cmp r3, #0
80031ac: f000 80d4 beq.w 8003358 <HAL_RCCEx_PeriphCLKConfig+0x1cc>
/* As soon as function is called to change RTC clock source, activation of the
power domain is done. */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
80031b0: 4b4e ldr r3, [pc, #312] ; (80032ec <HAL_RCCEx_PeriphCLKConfig+0x160>)
80031b2: 69db ldr r3, [r3, #28]
80031b4: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
80031b8: 2b00 cmp r3, #0
80031ba: d10e bne.n 80031da <HAL_RCCEx_PeriphCLKConfig+0x4e>
{
__HAL_RCC_PWR_CLK_ENABLE();
80031bc: 4b4b ldr r3, [pc, #300] ; (80032ec <HAL_RCCEx_PeriphCLKConfig+0x160>)
80031be: 69db ldr r3, [r3, #28]
80031c0: 4a4a ldr r2, [pc, #296] ; (80032ec <HAL_RCCEx_PeriphCLKConfig+0x160>)
80031c2: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
80031c6: 61d3 str r3, [r2, #28]
80031c8: 4b48 ldr r3, [pc, #288] ; (80032ec <HAL_RCCEx_PeriphCLKConfig+0x160>)
80031ca: 69db ldr r3, [r3, #28]
80031cc: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
80031d0: 60bb str r3, [r7, #8]
80031d2: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
80031d4: 2301 movs r3, #1
80031d6: f887 3047 strb.w r3, [r7, #71] ; 0x47
}
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80031da: 4b45 ldr r3, [pc, #276] ; (80032f0 <HAL_RCCEx_PeriphCLKConfig+0x164>)
80031dc: 681b ldr r3, [r3, #0]
80031de: f403 7380 and.w r3, r3, #256 ; 0x100
80031e2: 2b00 cmp r3, #0
80031e4: d118 bne.n 8003218 <HAL_RCCEx_PeriphCLKConfig+0x8c>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
80031e6: 4b42 ldr r3, [pc, #264] ; (80032f0 <HAL_RCCEx_PeriphCLKConfig+0x164>)
80031e8: 681b ldr r3, [r3, #0]
80031ea: 4a41 ldr r2, [pc, #260] ; (80032f0 <HAL_RCCEx_PeriphCLKConfig+0x164>)
80031ec: f443 7380 orr.w r3, r3, #256 ; 0x100
80031f0: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
80031f2: f7fd fbbb bl 800096c <HAL_GetTick>
80031f6: 6438 str r0, [r7, #64] ; 0x40
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80031f8: e008 b.n 800320c <HAL_RCCEx_PeriphCLKConfig+0x80>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
80031fa: f7fd fbb7 bl 800096c <HAL_GetTick>
80031fe: 4602 mov r2, r0
8003200: 6c3b ldr r3, [r7, #64] ; 0x40
8003202: 1ad3 subs r3, r2, r3
8003204: 2b64 cmp r3, #100 ; 0x64
8003206: d901 bls.n 800320c <HAL_RCCEx_PeriphCLKConfig+0x80>
{
return HAL_TIMEOUT;
8003208: 2303 movs r3, #3
800320a: e14b b.n 80034a4 <HAL_RCCEx_PeriphCLKConfig+0x318>
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
800320c: 4b38 ldr r3, [pc, #224] ; (80032f0 <HAL_RCCEx_PeriphCLKConfig+0x164>)
800320e: 681b ldr r3, [r3, #0]
8003210: f403 7380 and.w r3, r3, #256 ; 0x100
8003214: 2b00 cmp r3, #0
8003216: d0f0 beq.n 80031fa <HAL_RCCEx_PeriphCLKConfig+0x6e>
}
}
}
/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
8003218: 4b34 ldr r3, [pc, #208] ; (80032ec <HAL_RCCEx_PeriphCLKConfig+0x160>)
800321a: 6a1b ldr r3, [r3, #32]
800321c: f403 7340 and.w r3, r3, #768 ; 0x300
8003220: 63fb str r3, [r7, #60] ; 0x3c
if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
8003222: 6bfb ldr r3, [r7, #60] ; 0x3c
8003224: 2b00 cmp r3, #0
8003226: f000 8084 beq.w 8003332 <HAL_RCCEx_PeriphCLKConfig+0x1a6>
800322a: 687b ldr r3, [r7, #4]
800322c: 685b ldr r3, [r3, #4]
800322e: f403 7340 and.w r3, r3, #768 ; 0x300
8003232: 6bfa ldr r2, [r7, #60] ; 0x3c
8003234: 429a cmp r2, r3
8003236: d07c beq.n 8003332 <HAL_RCCEx_PeriphCLKConfig+0x1a6>
{
/* Store the content of BDCR register before the reset of Backup Domain */
temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
8003238: 4b2c ldr r3, [pc, #176] ; (80032ec <HAL_RCCEx_PeriphCLKConfig+0x160>)
800323a: 6a1b ldr r3, [r3, #32]
800323c: f423 7340 bic.w r3, r3, #768 ; 0x300
8003240: 63fb str r3, [r7, #60] ; 0x3c
8003242: f44f 3380 mov.w r3, #65536 ; 0x10000
8003246: 633b str r3, [r7, #48] ; 0x30
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8003248: 6b3b ldr r3, [r7, #48] ; 0x30
800324a: fa93 f3a3 rbit r3, r3
800324e: 62fb str r3, [r7, #44] ; 0x2c
return result;
8003250: 6afb ldr r3, [r7, #44] ; 0x2c
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
8003252: fab3 f383 clz r3, r3
8003256: b2db uxtb r3, r3
8003258: 461a mov r2, r3
800325a: 4b26 ldr r3, [pc, #152] ; (80032f4 <HAL_RCCEx_PeriphCLKConfig+0x168>)
800325c: 4413 add r3, r2
800325e: 009b lsls r3, r3, #2
8003260: 461a mov r2, r3
8003262: 2301 movs r3, #1
8003264: 6013 str r3, [r2, #0]
8003266: f44f 3380 mov.w r3, #65536 ; 0x10000
800326a: 63bb str r3, [r7, #56] ; 0x38
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
800326c: 6bbb ldr r3, [r7, #56] ; 0x38
800326e: fa93 f3a3 rbit r3, r3
8003272: 637b str r3, [r7, #52] ; 0x34
return result;
8003274: 6b7b ldr r3, [r7, #52] ; 0x34
__HAL_RCC_BACKUPRESET_RELEASE();
8003276: fab3 f383 clz r3, r3
800327a: b2db uxtb r3, r3
800327c: 461a mov r2, r3
800327e: 4b1d ldr r3, [pc, #116] ; (80032f4 <HAL_RCCEx_PeriphCLKConfig+0x168>)
8003280: 4413 add r3, r2
8003282: 009b lsls r3, r3, #2
8003284: 461a mov r2, r3
8003286: 2300 movs r3, #0
8003288: 6013 str r3, [r2, #0]
/* Restore the Content of BDCR register */
RCC->BDCR = temp_reg;
800328a: 4a18 ldr r2, [pc, #96] ; (80032ec <HAL_RCCEx_PeriphCLKConfig+0x160>)
800328c: 6bfb ldr r3, [r7, #60] ; 0x3c
800328e: 6213 str r3, [r2, #32]
/* Wait for LSERDY if LSE was enabled */
if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
8003290: 6bfb ldr r3, [r7, #60] ; 0x3c
8003292: f003 0301 and.w r3, r3, #1
8003296: 2b00 cmp r3, #0
8003298: d04b beq.n 8003332 <HAL_RCCEx_PeriphCLKConfig+0x1a6>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
800329a: f7fd fb67 bl 800096c <HAL_GetTick>
800329e: 6438 str r0, [r7, #64] ; 0x40
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
80032a0: e00a b.n 80032b8 <HAL_RCCEx_PeriphCLKConfig+0x12c>
{
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
80032a2: f7fd fb63 bl 800096c <HAL_GetTick>
80032a6: 4602 mov r2, r0
80032a8: 6c3b ldr r3, [r7, #64] ; 0x40
80032aa: 1ad3 subs r3, r2, r3
80032ac: f241 3288 movw r2, #5000 ; 0x1388
80032b0: 4293 cmp r3, r2
80032b2: d901 bls.n 80032b8 <HAL_RCCEx_PeriphCLKConfig+0x12c>
{
return HAL_TIMEOUT;
80032b4: 2303 movs r3, #3
80032b6: e0f5 b.n 80034a4 <HAL_RCCEx_PeriphCLKConfig+0x318>
80032b8: 2302 movs r3, #2
80032ba: 62bb str r3, [r7, #40] ; 0x28
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80032bc: 6abb ldr r3, [r7, #40] ; 0x28
80032be: fa93 f3a3 rbit r3, r3
80032c2: 627b str r3, [r7, #36] ; 0x24
80032c4: 2302 movs r3, #2
80032c6: 623b str r3, [r7, #32]
80032c8: 6a3b ldr r3, [r7, #32]
80032ca: fa93 f3a3 rbit r3, r3
80032ce: 61fb str r3, [r7, #28]
return result;
80032d0: 69fb ldr r3, [r7, #28]
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
80032d2: fab3 f383 clz r3, r3
80032d6: b2db uxtb r3, r3
80032d8: 095b lsrs r3, r3, #5
80032da: b2db uxtb r3, r3
80032dc: f043 0302 orr.w r3, r3, #2
80032e0: b2db uxtb r3, r3
80032e2: 2b02 cmp r3, #2
80032e4: d108 bne.n 80032f8 <HAL_RCCEx_PeriphCLKConfig+0x16c>
80032e6: 4b01 ldr r3, [pc, #4] ; (80032ec <HAL_RCCEx_PeriphCLKConfig+0x160>)
80032e8: 6a1b ldr r3, [r3, #32]
80032ea: e00d b.n 8003308 <HAL_RCCEx_PeriphCLKConfig+0x17c>
80032ec: 40021000 .word 0x40021000
80032f0: 40007000 .word 0x40007000
80032f4: 10908100 .word 0x10908100
80032f8: 2302 movs r3, #2
80032fa: 61bb str r3, [r7, #24]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80032fc: 69bb ldr r3, [r7, #24]
80032fe: fa93 f3a3 rbit r3, r3
8003302: 617b str r3, [r7, #20]
8003304: 4b69 ldr r3, [pc, #420] ; (80034ac <HAL_RCCEx_PeriphCLKConfig+0x320>)
8003306: 6a5b ldr r3, [r3, #36] ; 0x24
8003308: 2202 movs r2, #2
800330a: 613a str r2, [r7, #16]
800330c: 693a ldr r2, [r7, #16]
800330e: fa92 f2a2 rbit r2, r2
8003312: 60fa str r2, [r7, #12]
return result;
8003314: 68fa ldr r2, [r7, #12]
8003316: fab2 f282 clz r2, r2
800331a: b2d2 uxtb r2, r2
800331c: f042 0240 orr.w r2, r2, #64 ; 0x40
8003320: b2d2 uxtb r2, r2
8003322: f002 021f and.w r2, r2, #31
8003326: 2101 movs r1, #1
8003328: fa01 f202 lsl.w r2, r1, r2
800332c: 4013 ands r3, r2
800332e: 2b00 cmp r3, #0
8003330: d0b7 beq.n 80032a2 <HAL_RCCEx_PeriphCLKConfig+0x116>
}
}
}
}
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
8003332: 4b5e ldr r3, [pc, #376] ; (80034ac <HAL_RCCEx_PeriphCLKConfig+0x320>)
8003334: 6a1b ldr r3, [r3, #32]
8003336: f423 7240 bic.w r2, r3, #768 ; 0x300
800333a: 687b ldr r3, [r7, #4]
800333c: 685b ldr r3, [r3, #4]
800333e: 495b ldr r1, [pc, #364] ; (80034ac <HAL_RCCEx_PeriphCLKConfig+0x320>)
8003340: 4313 orrs r3, r2
8003342: 620b str r3, [r1, #32]
/* Require to disable power clock if necessary */
if(pwrclkchanged == SET)
8003344: f897 3047 ldrb.w r3, [r7, #71] ; 0x47
8003348: 2b01 cmp r3, #1
800334a: d105 bne.n 8003358 <HAL_RCCEx_PeriphCLKConfig+0x1cc>
{
__HAL_RCC_PWR_CLK_DISABLE();
800334c: 4b57 ldr r3, [pc, #348] ; (80034ac <HAL_RCCEx_PeriphCLKConfig+0x320>)
800334e: 69db ldr r3, [r3, #28]
8003350: 4a56 ldr r2, [pc, #344] ; (80034ac <HAL_RCCEx_PeriphCLKConfig+0x320>)
8003352: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
8003356: 61d3 str r3, [r2, #28]
}
}
/*------------------------------- USART1 Configuration ------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
8003358: 687b ldr r3, [r7, #4]
800335a: 681b ldr r3, [r3, #0]
800335c: f003 0301 and.w r3, r3, #1
8003360: 2b00 cmp r3, #0
8003362: d008 beq.n 8003376 <HAL_RCCEx_PeriphCLKConfig+0x1ea>
{
/* Check the parameters */
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
/* Configure the USART1 clock source */
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
8003364: 4b51 ldr r3, [pc, #324] ; (80034ac <HAL_RCCEx_PeriphCLKConfig+0x320>)
8003366: 6b1b ldr r3, [r3, #48] ; 0x30
8003368: f023 0203 bic.w r2, r3, #3
800336c: 687b ldr r3, [r7, #4]
800336e: 689b ldr r3, [r3, #8]
8003370: 494e ldr r1, [pc, #312] ; (80034ac <HAL_RCCEx_PeriphCLKConfig+0x320>)
8003372: 4313 orrs r3, r2
8003374: 630b str r3, [r1, #48] ; 0x30
__HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
}
#endif /* RCC_CFGR3_USART3SW */
/*------------------------------ I2C1 Configuration ------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
8003376: 687b ldr r3, [r7, #4]
8003378: 681b ldr r3, [r3, #0]
800337a: f003 0320 and.w r3, r3, #32
800337e: 2b00 cmp r3, #0
8003380: d008 beq.n 8003394 <HAL_RCCEx_PeriphCLKConfig+0x208>
{
/* Check the parameters */
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
/* Configure the I2C1 clock source */
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
8003382: 4b4a ldr r3, [pc, #296] ; (80034ac <HAL_RCCEx_PeriphCLKConfig+0x320>)
8003384: 6b1b ldr r3, [r3, #48] ; 0x30
8003386: f023 0210 bic.w r2, r3, #16
800338a: 687b ldr r3, [r7, #4]
800338c: 68db ldr r3, [r3, #12]
800338e: 4947 ldr r1, [pc, #284] ; (80034ac <HAL_RCCEx_PeriphCLKConfig+0x320>)
8003390: 4313 orrs r3, r2
8003392: 630b str r3, [r1, #48] ; 0x30
#if defined(STM32F302xE) || defined(STM32F303xE)\
|| defined(STM32F302xC) || defined(STM32F303xC)\
|| defined(STM32F302x8) \
|| defined(STM32F373xC)
/*------------------------------ USB Configuration ------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
8003394: 687b ldr r3, [r7, #4]
8003396: 681b ldr r3, [r3, #0]
8003398: f403 3300 and.w r3, r3, #131072 ; 0x20000
800339c: 2b00 cmp r3, #0
800339e: d008 beq.n 80033b2 <HAL_RCCEx_PeriphCLKConfig+0x226>
{
/* Check the parameters */
assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->USBClockSelection));
/* Configure the USB clock source */
__HAL_RCC_USB_CONFIG(PeriphClkInit->USBClockSelection);
80033a0: 4b42 ldr r3, [pc, #264] ; (80034ac <HAL_RCCEx_PeriphCLKConfig+0x320>)
80033a2: 685b ldr r3, [r3, #4]
80033a4: f423 0280 bic.w r2, r3, #4194304 ; 0x400000
80033a8: 687b ldr r3, [r7, #4]
80033aa: 6b1b ldr r3, [r3, #48] ; 0x30
80033ac: 493f ldr r1, [pc, #252] ; (80034ac <HAL_RCCEx_PeriphCLKConfig+0x320>)
80033ae: 4313 orrs r3, r2
80033b0: 604b str r3, [r1, #4]
|| defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
|| defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)\
|| defined(STM32F373xC) || defined(STM32F378xx)
/*------------------------------ I2C2 Configuration ------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
80033b2: 687b ldr r3, [r7, #4]
80033b4: 681b ldr r3, [r3, #0]
80033b6: f003 0340 and.w r3, r3, #64 ; 0x40
80033ba: 2b00 cmp r3, #0
80033bc: d008 beq.n 80033d0 <HAL_RCCEx_PeriphCLKConfig+0x244>
{
/* Check the parameters */
assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
/* Configure the I2C2 clock source */
__HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
80033be: 4b3b ldr r3, [pc, #236] ; (80034ac <HAL_RCCEx_PeriphCLKConfig+0x320>)
80033c0: 6b1b ldr r3, [r3, #48] ; 0x30
80033c2: f023 0220 bic.w r2, r3, #32
80033c6: 687b ldr r3, [r7, #4]
80033c8: 691b ldr r3, [r3, #16]
80033ca: 4938 ldr r1, [pc, #224] ; (80034ac <HAL_RCCEx_PeriphCLKConfig+0x320>)
80033cc: 4313 orrs r3, r2
80033ce: 630b str r3, [r1, #48] ; 0x30
#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
|| defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
/*------------------------------ I2C3 Configuration ------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
80033d0: 687b ldr r3, [r7, #4]
80033d2: 681b ldr r3, [r3, #0]
80033d4: f403 4300 and.w r3, r3, #32768 ; 0x8000
80033d8: 2b00 cmp r3, #0
80033da: d008 beq.n 80033ee <HAL_RCCEx_PeriphCLKConfig+0x262>
{
/* Check the parameters */
assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
/* Configure the I2C3 clock source */
__HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
80033dc: 4b33 ldr r3, [pc, #204] ; (80034ac <HAL_RCCEx_PeriphCLKConfig+0x320>)
80033de: 6b1b ldr r3, [r3, #48] ; 0x30
80033e0: f023 0240 bic.w r2, r3, #64 ; 0x40
80033e4: 687b ldr r3, [r7, #4]
80033e6: 695b ldr r3, [r3, #20]
80033e8: 4930 ldr r1, [pc, #192] ; (80034ac <HAL_RCCEx_PeriphCLKConfig+0x320>)
80033ea: 4313 orrs r3, r2
80033ec: 630b str r3, [r1, #48] ; 0x30
#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)\
|| defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
|| defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
/*------------------------------ I2S Configuration ------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S)
80033ee: 687b ldr r3, [r7, #4]
80033f0: 681b ldr r3, [r3, #0]
80033f2: f403 7300 and.w r3, r3, #512 ; 0x200
80033f6: 2b00 cmp r3, #0
80033f8: d008 beq.n 800340c <HAL_RCCEx_PeriphCLKConfig+0x280>
{
/* Check the parameters */
assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
/* Configure the I2S clock source */
__HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
80033fa: 4b2c ldr r3, [pc, #176] ; (80034ac <HAL_RCCEx_PeriphCLKConfig+0x320>)
80033fc: 685b ldr r3, [r3, #4]
80033fe: f423 0200 bic.w r2, r3, #8388608 ; 0x800000
8003402: 687b ldr r3, [r7, #4]
8003404: 69db ldr r3, [r3, #28]
8003406: 4929 ldr r1, [pc, #164] ; (80034ac <HAL_RCCEx_PeriphCLKConfig+0x320>)
8003408: 4313 orrs r3, r2
800340a: 604b str r3, [r1, #4]
/* STM32F301x8 || STM32F302x8 || STM32F318xx */
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
/*------------------------------ ADC1 clock Configuration ------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC1) == RCC_PERIPHCLK_ADC1)
800340c: 687b ldr r3, [r7, #4]
800340e: 681b ldr r3, [r3, #0]
8003410: f003 0380 and.w r3, r3, #128 ; 0x80
8003414: 2b00 cmp r3, #0
8003416: d008 beq.n 800342a <HAL_RCCEx_PeriphCLKConfig+0x29e>
{
/* Check the parameters */
assert_param(IS_RCC_ADC1PLLCLK_DIV(PeriphClkInit->Adc1ClockSelection));
/* Configure the ADC1 clock source */
__HAL_RCC_ADC1_CONFIG(PeriphClkInit->Adc1ClockSelection);
8003418: 4b24 ldr r3, [pc, #144] ; (80034ac <HAL_RCCEx_PeriphCLKConfig+0x320>)
800341a: 6adb ldr r3, [r3, #44] ; 0x2c
800341c: f423 72f8 bic.w r2, r3, #496 ; 0x1f0
8003420: 687b ldr r3, [r7, #4]
8003422: 699b ldr r3, [r3, #24]
8003424: 4921 ldr r1, [pc, #132] ; (80034ac <HAL_RCCEx_PeriphCLKConfig+0x320>)
8003426: 4313 orrs r3, r2
8003428: 62cb str r3, [r1, #44] ; 0x2c
|| defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)\
|| defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\
|| defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
/*------------------------------ TIM1 clock Configuration ----------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1)
800342a: 687b ldr r3, [r7, #4]
800342c: 681b ldr r3, [r3, #0]
800342e: f403 5380 and.w r3, r3, #4096 ; 0x1000
8003432: 2b00 cmp r3, #0
8003434: d008 beq.n 8003448 <HAL_RCCEx_PeriphCLKConfig+0x2bc>
{
/* Check the parameters */
assert_param(IS_RCC_TIM1CLKSOURCE(PeriphClkInit->Tim1ClockSelection));
/* Configure the TIM1 clock source */
__HAL_RCC_TIM1_CONFIG(PeriphClkInit->Tim1ClockSelection);
8003436: 4b1d ldr r3, [pc, #116] ; (80034ac <HAL_RCCEx_PeriphCLKConfig+0x320>)
8003438: 6b1b ldr r3, [r3, #48] ; 0x30
800343a: f423 7280 bic.w r2, r3, #256 ; 0x100
800343e: 687b ldr r3, [r7, #4]
8003440: 6a1b ldr r3, [r3, #32]
8003442: 491a ldr r1, [pc, #104] ; (80034ac <HAL_RCCEx_PeriphCLKConfig+0x320>)
8003444: 4313 orrs r3, r2
8003446: 630b str r3, [r1, #48] ; 0x30
/* STM32F303xC || STM32F358xx */
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
/*------------------------------ TIM15 clock Configuration ----------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)
8003448: 687b ldr r3, [r7, #4]
800344a: 681b ldr r3, [r3, #0]
800344c: f403 2380 and.w r3, r3, #262144 ; 0x40000
8003450: 2b00 cmp r3, #0
8003452: d008 beq.n 8003466 <HAL_RCCEx_PeriphCLKConfig+0x2da>
{
/* Check the parameters */
assert_param(IS_RCC_TIM15CLKSOURCE(PeriphClkInit->Tim15ClockSelection));
/* Configure the TIM15 clock source */
__HAL_RCC_TIM15_CONFIG(PeriphClkInit->Tim15ClockSelection);
8003454: 4b15 ldr r3, [pc, #84] ; (80034ac <HAL_RCCEx_PeriphCLKConfig+0x320>)
8003456: 6b1b ldr r3, [r3, #48] ; 0x30
8003458: f423 6280 bic.w r2, r3, #1024 ; 0x400
800345c: 687b ldr r3, [r7, #4]
800345e: 6a5b ldr r3, [r3, #36] ; 0x24
8003460: 4912 ldr r1, [pc, #72] ; (80034ac <HAL_RCCEx_PeriphCLKConfig+0x320>)
8003462: 4313 orrs r3, r2
8003464: 630b str r3, [r1, #48] ; 0x30
}
/*------------------------------ TIM16 clock Configuration ----------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM16) == RCC_PERIPHCLK_TIM16)
8003466: 687b ldr r3, [r7, #4]
8003468: 681b ldr r3, [r3, #0]
800346a: f403 2300 and.w r3, r3, #524288 ; 0x80000
800346e: 2b00 cmp r3, #0
8003470: d008 beq.n 8003484 <HAL_RCCEx_PeriphCLKConfig+0x2f8>
{
/* Check the parameters */
assert_param(IS_RCC_TIM16CLKSOURCE(PeriphClkInit->Tim16ClockSelection));
/* Configure the TIM16 clock source */
__HAL_RCC_TIM16_CONFIG(PeriphClkInit->Tim16ClockSelection);
8003472: 4b0e ldr r3, [pc, #56] ; (80034ac <HAL_RCCEx_PeriphCLKConfig+0x320>)
8003474: 6b1b ldr r3, [r3, #48] ; 0x30
8003476: f423 6200 bic.w r2, r3, #2048 ; 0x800
800347a: 687b ldr r3, [r7, #4]
800347c: 6a9b ldr r3, [r3, #40] ; 0x28
800347e: 490b ldr r1, [pc, #44] ; (80034ac <HAL_RCCEx_PeriphCLKConfig+0x320>)
8003480: 4313 orrs r3, r2
8003482: 630b str r3, [r1, #48] ; 0x30
}
/*------------------------------ TIM17 clock Configuration ----------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM17) == RCC_PERIPHCLK_TIM17)
8003484: 687b ldr r3, [r7, #4]
8003486: 681b ldr r3, [r3, #0]
8003488: f403 1380 and.w r3, r3, #1048576 ; 0x100000
800348c: 2b00 cmp r3, #0
800348e: d008 beq.n 80034a2 <HAL_RCCEx_PeriphCLKConfig+0x316>
{
/* Check the parameters */
assert_param(IS_RCC_TIM17CLKSOURCE(PeriphClkInit->Tim17ClockSelection));
/* Configure the TIM17 clock source */
__HAL_RCC_TIM17_CONFIG(PeriphClkInit->Tim17ClockSelection);
8003490: 4b06 ldr r3, [pc, #24] ; (80034ac <HAL_RCCEx_PeriphCLKConfig+0x320>)
8003492: 6b1b ldr r3, [r3, #48] ; 0x30
8003494: f423 5200 bic.w r2, r3, #8192 ; 0x2000
8003498: 687b ldr r3, [r7, #4]
800349a: 6adb ldr r3, [r3, #44] ; 0x2c
800349c: 4903 ldr r1, [pc, #12] ; (80034ac <HAL_RCCEx_PeriphCLKConfig+0x320>)
800349e: 4313 orrs r3, r2
80034a0: 630b str r3, [r1, #48] ; 0x30
__HAL_RCC_TIM20_CONFIG(PeriphClkInit->Tim20ClockSelection);
}
#endif /* STM32F303xE || STM32F398xx */
return HAL_OK;
80034a2: 2300 movs r3, #0
}
80034a4: 4618 mov r0, r3
80034a6: 3748 adds r7, #72 ; 0x48
80034a8: 46bd mov sp, r7
80034aa: bd80 pop {r7, pc}
80034ac: 40021000 .word 0x40021000
080034b0 <HAL_UART_Init>:
* parameters in the UART_InitTypeDef and initialize the associated handle.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
80034b0: b580 push {r7, lr}
80034b2: b082 sub sp, #8
80034b4: af00 add r7, sp, #0
80034b6: 6078 str r0, [r7, #4]
/* Check the UART handle allocation */
if (huart == NULL)
80034b8: 687b ldr r3, [r7, #4]
80034ba: 2b00 cmp r3, #0
80034bc: d101 bne.n 80034c2 <HAL_UART_Init+0x12>
{
return HAL_ERROR;
80034be: 2301 movs r3, #1
80034c0: e040 b.n 8003544 <HAL_UART_Init+0x94>
{
/* Check the parameters */
assert_param(IS_UART_INSTANCE(huart->Instance));
}
if (huart->gState == HAL_UART_STATE_RESET)
80034c2: 687b ldr r3, [r7, #4]
80034c4: 6f9b ldr r3, [r3, #120] ; 0x78
80034c6: 2b00 cmp r3, #0
80034c8: d106 bne.n 80034d8 <HAL_UART_Init+0x28>
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
80034ca: 687b ldr r3, [r7, #4]
80034cc: 2200 movs r2, #0
80034ce: f883 2074 strb.w r2, [r3, #116] ; 0x74
/* Init the low level hardware */
huart->MspInitCallback(huart);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
80034d2: 6878 ldr r0, [r7, #4]
80034d4: f7fd f914 bl 8000700 <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
80034d8: 687b ldr r3, [r7, #4]
80034da: 2224 movs r2, #36 ; 0x24
80034dc: 679a str r2, [r3, #120] ; 0x78
__HAL_UART_DISABLE(huart);
80034de: 687b ldr r3, [r7, #4]
80034e0: 681b ldr r3, [r3, #0]
80034e2: 681a ldr r2, [r3, #0]
80034e4: 687b ldr r3, [r7, #4]
80034e6: 681b ldr r3, [r3, #0]
80034e8: f022 0201 bic.w r2, r2, #1
80034ec: 601a str r2, [r3, #0]
/* Set the UART Communication parameters */
if (UART_SetConfig(huart) == HAL_ERROR)
80034ee: 6878 ldr r0, [r7, #4]
80034f0: f000 fbe6 bl 8003cc0 <UART_SetConfig>
80034f4: 4603 mov r3, r0
80034f6: 2b01 cmp r3, #1
80034f8: d101 bne.n 80034fe <HAL_UART_Init+0x4e>
{
return HAL_ERROR;
80034fa: 2301 movs r3, #1
80034fc: e022 b.n 8003544 <HAL_UART_Init+0x94>
}
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
80034fe: 687b ldr r3, [r7, #4]
8003500: 6a5b ldr r3, [r3, #36] ; 0x24
8003502: 2b00 cmp r3, #0
8003504: d002 beq.n 800350c <HAL_UART_Init+0x5c>
{
UART_AdvFeatureConfig(huart);
8003506: 6878 ldr r0, [r7, #4]
8003508: f000 fd10 bl 8003f2c <UART_AdvFeatureConfig>
}
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
800350c: 687b ldr r3, [r7, #4]
800350e: 681b ldr r3, [r3, #0]
8003510: 685a ldr r2, [r3, #4]
8003512: 687b ldr r3, [r7, #4]
8003514: 681b ldr r3, [r3, #0]
8003516: f422 4290 bic.w r2, r2, #18432 ; 0x4800
800351a: 605a str r2, [r3, #4]
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
800351c: 687b ldr r3, [r7, #4]
800351e: 681b ldr r3, [r3, #0]
8003520: 689a ldr r2, [r3, #8]
8003522: 687b ldr r3, [r7, #4]
8003524: 681b ldr r3, [r3, #0]
8003526: f022 022a bic.w r2, r2, #42 ; 0x2a
800352a: 609a str r2, [r3, #8]
__HAL_UART_ENABLE(huart);
800352c: 687b ldr r3, [r7, #4]
800352e: 681b ldr r3, [r3, #0]
8003530: 681a ldr r2, [r3, #0]
8003532: 687b ldr r3, [r7, #4]
8003534: 681b ldr r3, [r3, #0]
8003536: f042 0201 orr.w r2, r2, #1
800353a: 601a str r2, [r3, #0]
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
return (UART_CheckIdleState(huart));
800353c: 6878 ldr r0, [r7, #4]
800353e: f000 fd97 bl 8004070 <UART_CheckIdleState>
8003542: 4603 mov r3, r0
}
8003544: 4618 mov r0, r3
8003546: 3708 adds r7, #8
8003548: 46bd mov sp, r7
800354a: bd80 pop {r7, pc}
0800354c <HAL_UART_Transmit_IT>:
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be sent.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
800354c: b480 push {r7}
800354e: b08b sub sp, #44 ; 0x2c
8003550: af00 add r7, sp, #0
8003552: 60f8 str r0, [r7, #12]
8003554: 60b9 str r1, [r7, #8]
8003556: 4613 mov r3, r2
8003558: 80fb strh r3, [r7, #6]
/* Check that a Tx process is not already ongoing */
if (huart->gState == HAL_UART_STATE_READY)
800355a: 68fb ldr r3, [r7, #12]
800355c: 6f9b ldr r3, [r3, #120] ; 0x78
800355e: 2b20 cmp r3, #32
8003560: d156 bne.n 8003610 <HAL_UART_Transmit_IT+0xc4>
{
if ((pData == NULL) || (Size == 0U))
8003562: 68bb ldr r3, [r7, #8]
8003564: 2b00 cmp r3, #0
8003566: d002 beq.n 800356e <HAL_UART_Transmit_IT+0x22>
8003568: 88fb ldrh r3, [r7, #6]
800356a: 2b00 cmp r3, #0
800356c: d101 bne.n 8003572 <HAL_UART_Transmit_IT+0x26>
{
return HAL_ERROR;
800356e: 2301 movs r3, #1
8003570: e04f b.n 8003612 <HAL_UART_Transmit_IT+0xc6>
}
__HAL_LOCK(huart);
8003572: 68fb ldr r3, [r7, #12]
8003574: f893 3074 ldrb.w r3, [r3, #116] ; 0x74
8003578: 2b01 cmp r3, #1
800357a: d101 bne.n 8003580 <HAL_UART_Transmit_IT+0x34>
800357c: 2302 movs r3, #2
800357e: e048 b.n 8003612 <HAL_UART_Transmit_IT+0xc6>
8003580: 68fb ldr r3, [r7, #12]
8003582: 2201 movs r2, #1
8003584: f883 2074 strb.w r2, [r3, #116] ; 0x74
huart->pTxBuffPtr = pData;
8003588: 68fb ldr r3, [r7, #12]
800358a: 68ba ldr r2, [r7, #8]
800358c: 64da str r2, [r3, #76] ; 0x4c
huart->TxXferSize = Size;
800358e: 68fb ldr r3, [r7, #12]
8003590: 88fa ldrh r2, [r7, #6]
8003592: f8a3 2050 strh.w r2, [r3, #80] ; 0x50
huart->TxXferCount = Size;
8003596: 68fb ldr r3, [r7, #12]
8003598: 88fa ldrh r2, [r7, #6]
800359a: f8a3 2052 strh.w r2, [r3, #82] ; 0x52
huart->TxISR = NULL;
800359e: 68fb ldr r3, [r7, #12]
80035a0: 2200 movs r2, #0
80035a2: 669a str r2, [r3, #104] ; 0x68
huart->ErrorCode = HAL_UART_ERROR_NONE;
80035a4: 68fb ldr r3, [r7, #12]
80035a6: 2200 movs r2, #0
80035a8: f8c3 2080 str.w r2, [r3, #128] ; 0x80
huart->gState = HAL_UART_STATE_BUSY_TX;
80035ac: 68fb ldr r3, [r7, #12]
80035ae: 2221 movs r2, #33 ; 0x21
80035b0: 679a str r2, [r3, #120] ; 0x78
/* Set the Tx ISR function pointer according to the data word length */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
80035b2: 68fb ldr r3, [r7, #12]
80035b4: 689b ldr r3, [r3, #8]
80035b6: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
80035ba: d107 bne.n 80035cc <HAL_UART_Transmit_IT+0x80>
80035bc: 68fb ldr r3, [r7, #12]
80035be: 691b ldr r3, [r3, #16]
80035c0: 2b00 cmp r3, #0
80035c2: d103 bne.n 80035cc <HAL_UART_Transmit_IT+0x80>
{
huart->TxISR = UART_TxISR_16BIT;
80035c4: 68fb ldr r3, [r7, #12]
80035c6: 4a16 ldr r2, [pc, #88] ; (8003620 <HAL_UART_Transmit_IT+0xd4>)
80035c8: 669a str r2, [r3, #104] ; 0x68
80035ca: e002 b.n 80035d2 <HAL_UART_Transmit_IT+0x86>
}
else
{
huart->TxISR = UART_TxISR_8BIT;
80035cc: 68fb ldr r3, [r7, #12]
80035ce: 4a15 ldr r2, [pc, #84] ; (8003624 <HAL_UART_Transmit_IT+0xd8>)
80035d0: 669a str r2, [r3, #104] ; 0x68
}
__HAL_UNLOCK(huart);
80035d2: 68fb ldr r3, [r7, #12]
80035d4: 2200 movs r2, #0
80035d6: f883 2074 strb.w r2, [r3, #116] ; 0x74
/* Enable the Transmit Data Register Empty interrupt */
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
80035da: 68fb ldr r3, [r7, #12]
80035dc: 681b ldr r3, [r3, #0]
80035de: 617b str r3, [r7, #20]
*/
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80035e0: 697b ldr r3, [r7, #20]
80035e2: e853 3f00 ldrex r3, [r3]
80035e6: 613b str r3, [r7, #16]
return(result);
80035e8: 693b ldr r3, [r7, #16]
80035ea: f043 0380 orr.w r3, r3, #128 ; 0x80
80035ee: 627b str r3, [r7, #36] ; 0x24
80035f0: 68fb ldr r3, [r7, #12]
80035f2: 681b ldr r3, [r3, #0]
80035f4: 461a mov r2, r3
80035f6: 6a7b ldr r3, [r7, #36] ; 0x24
80035f8: 623b str r3, [r7, #32]
80035fa: 61fa str r2, [r7, #28]
*/
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80035fc: 69f9 ldr r1, [r7, #28]
80035fe: 6a3a ldr r2, [r7, #32]
8003600: e841 2300 strex r3, r2, [r1]
8003604: 61bb str r3, [r7, #24]
return(result);
8003606: 69bb ldr r3, [r7, #24]
8003608: 2b00 cmp r3, #0
800360a: d1e6 bne.n 80035da <HAL_UART_Transmit_IT+0x8e>
return HAL_OK;
800360c: 2300 movs r3, #0
800360e: e000 b.n 8003612 <HAL_UART_Transmit_IT+0xc6>
}
else
{
return HAL_BUSY;
8003610: 2302 movs r3, #2
}
}
8003612: 4618 mov r0, r3
8003614: 372c adds r7, #44 ; 0x2c
8003616: 46bd mov sp, r7
8003618: f85d 7b04 ldr.w r7, [sp], #4
800361c: 4770 bx lr
800361e: bf00 nop
8003620: 0800458f .word 0x0800458f
8003624: 080044d7 .word 0x080044d7
08003628 <HAL_UART_Receive_IT>:
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
8003628: b580 push {r7, lr}
800362a: b08a sub sp, #40 ; 0x28
800362c: af00 add r7, sp, #0
800362e: 60f8 str r0, [r7, #12]
8003630: 60b9 str r1, [r7, #8]
8003632: 4613 mov r3, r2
8003634: 80fb strh r3, [r7, #6]
/* Check that a Rx process is not already ongoing */
if (huart->RxState == HAL_UART_STATE_READY)
8003636: 68fb ldr r3, [r7, #12]
8003638: 6fdb ldr r3, [r3, #124] ; 0x7c
800363a: 2b20 cmp r3, #32
800363c: d13d bne.n 80036ba <HAL_UART_Receive_IT+0x92>
{
if ((pData == NULL) || (Size == 0U))
800363e: 68bb ldr r3, [r7, #8]
8003640: 2b00 cmp r3, #0
8003642: d002 beq.n 800364a <HAL_UART_Receive_IT+0x22>
8003644: 88fb ldrh r3, [r7, #6]
8003646: 2b00 cmp r3, #0
8003648: d101 bne.n 800364e <HAL_UART_Receive_IT+0x26>
{
return HAL_ERROR;
800364a: 2301 movs r3, #1
800364c: e036 b.n 80036bc <HAL_UART_Receive_IT+0x94>
}
__HAL_LOCK(huart);
800364e: 68fb ldr r3, [r7, #12]
8003650: f893 3074 ldrb.w r3, [r3, #116] ; 0x74
8003654: 2b01 cmp r3, #1
8003656: d101 bne.n 800365c <HAL_UART_Receive_IT+0x34>
8003658: 2302 movs r3, #2
800365a: e02f b.n 80036bc <HAL_UART_Receive_IT+0x94>
800365c: 68fb ldr r3, [r7, #12]
800365e: 2201 movs r2, #1
8003660: f883 2074 strb.w r2, [r3, #116] ; 0x74
/* Set Reception type to Standard reception */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8003664: 68fb ldr r3, [r7, #12]
8003666: 2200 movs r2, #0
8003668: 661a str r2, [r3, #96] ; 0x60
/* Check that USART RTOEN bit is set */
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
800366a: 68fb ldr r3, [r7, #12]
800366c: 681b ldr r3, [r3, #0]
800366e: 685b ldr r3, [r3, #4]
8003670: f403 0300 and.w r3, r3, #8388608 ; 0x800000
8003674: 2b00 cmp r3, #0
8003676: d018 beq.n 80036aa <HAL_UART_Receive_IT+0x82>
{
/* Enable the UART Receiver Timeout Interrupt */
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
8003678: 68fb ldr r3, [r7, #12]
800367a: 681b ldr r3, [r3, #0]
800367c: 617b str r3, [r7, #20]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
800367e: 697b ldr r3, [r7, #20]
8003680: e853 3f00 ldrex r3, [r3]
8003684: 613b str r3, [r7, #16]
return(result);
8003686: 693b ldr r3, [r7, #16]
8003688: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000
800368c: 627b str r3, [r7, #36] ; 0x24
800368e: 68fb ldr r3, [r7, #12]
8003690: 681b ldr r3, [r3, #0]
8003692: 461a mov r2, r3
8003694: 6a7b ldr r3, [r7, #36] ; 0x24
8003696: 623b str r3, [r7, #32]
8003698: 61fa str r2, [r7, #28]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
800369a: 69f9 ldr r1, [r7, #28]
800369c: 6a3a ldr r2, [r7, #32]
800369e: e841 2300 strex r3, r2, [r1]
80036a2: 61bb str r3, [r7, #24]
return(result);
80036a4: 69bb ldr r3, [r7, #24]
80036a6: 2b00 cmp r3, #0
80036a8: d1e6 bne.n 8003678 <HAL_UART_Receive_IT+0x50>
}
return (UART_Start_Receive_IT(huart, pData, Size));
80036aa: 88fb ldrh r3, [r7, #6]
80036ac: 461a mov r2, r3
80036ae: 68b9 ldr r1, [r7, #8]
80036b0: 68f8 ldr r0, [r7, #12]
80036b2: f000 fdeb bl 800428c <UART_Start_Receive_IT>
80036b6: 4603 mov r3, r0
80036b8: e000 b.n 80036bc <HAL_UART_Receive_IT+0x94>
}
else
{
return HAL_BUSY;
80036ba: 2302 movs r3, #2
}
}
80036bc: 4618 mov r0, r3
80036be: 3728 adds r7, #40 ; 0x28
80036c0: 46bd mov sp, r7
80036c2: bd80 pop {r7, pc}
080036c4 <HAL_UART_IRQHandler>:
* @brief Handle UART interrupt request.
* @param huart UART handle.
* @retval None
*/
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
{
80036c4: b580 push {r7, lr}
80036c6: b0ba sub sp, #232 ; 0xe8
80036c8: af00 add r7, sp, #0
80036ca: 6078 str r0, [r7, #4]
uint32_t isrflags = READ_REG(huart->Instance->ISR);
80036cc: 687b ldr r3, [r7, #4]
80036ce: 681b ldr r3, [r3, #0]
80036d0: 69db ldr r3, [r3, #28]
80036d2: f8c7 30e4 str.w r3, [r7, #228] ; 0xe4
uint32_t cr1its = READ_REG(huart->Instance->CR1);
80036d6: 687b ldr r3, [r7, #4]
80036d8: 681b ldr r3, [r3, #0]
80036da: 681b ldr r3, [r3, #0]
80036dc: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0
uint32_t cr3its = READ_REG(huart->Instance->CR3);
80036e0: 687b ldr r3, [r7, #4]
80036e2: 681b ldr r3, [r3, #0]
80036e4: 689b ldr r3, [r3, #8]
80036e6: f8c7 30dc str.w r3, [r7, #220] ; 0xdc
uint32_t errorflags;
uint32_t errorcode;
/* If no error occurs */
errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
80036ea: f8d7 20e4 ldr.w r2, [r7, #228] ; 0xe4
80036ee: f640 030f movw r3, #2063 ; 0x80f
80036f2: 4013 ands r3, r2
80036f4: f8c7 30d8 str.w r3, [r7, #216] ; 0xd8
if (errorflags == 0U)
80036f8: f8d7 30d8 ldr.w r3, [r7, #216] ; 0xd8
80036fc: 2b00 cmp r3, #0
80036fe: d115 bne.n 800372c <HAL_UART_IRQHandler+0x68>
{
/* UART in mode Receiver ---------------------------------------------------*/
if (((isrflags & USART_ISR_RXNE) != 0U)
8003700: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4
8003704: f003 0320 and.w r3, r3, #32
8003708: 2b00 cmp r3, #0
800370a: d00f beq.n 800372c <HAL_UART_IRQHandler+0x68>
&& ((cr1its & USART_CR1_RXNEIE) != 0U))
800370c: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0
8003710: f003 0320 and.w r3, r3, #32
8003714: 2b00 cmp r3, #0
8003716: d009 beq.n 800372c <HAL_UART_IRQHandler+0x68>
{
if (huart->RxISR != NULL)
8003718: 687b ldr r3, [r7, #4]
800371a: 6e5b ldr r3, [r3, #100] ; 0x64
800371c: 2b00 cmp r3, #0
800371e: f000 82a3 beq.w 8003c68 <HAL_UART_IRQHandler+0x5a4>
{
huart->RxISR(huart);
8003722: 687b ldr r3, [r7, #4]
8003724: 6e5b ldr r3, [r3, #100] ; 0x64
8003726: 6878 ldr r0, [r7, #4]
8003728: 4798 blx r3
}
return;
800372a: e29d b.n 8003c68 <HAL_UART_IRQHandler+0x5a4>
}
}
/* If some errors occur */
if ((errorflags != 0U)
800372c: f8d7 30d8 ldr.w r3, [r7, #216] ; 0xd8
8003730: 2b00 cmp r3, #0
8003732: f000 8117 beq.w 8003964 <HAL_UART_IRQHandler+0x2a0>
&& (((cr3its & USART_CR3_EIE) != 0U)
8003736: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc
800373a: f003 0301 and.w r3, r3, #1
800373e: 2b00 cmp r3, #0
8003740: d106 bne.n 8003750 <HAL_UART_IRQHandler+0x8c>
|| ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U)))
8003742: f8d7 20e0 ldr.w r2, [r7, #224] ; 0xe0
8003746: 4b85 ldr r3, [pc, #532] ; (800395c <HAL_UART_IRQHandler+0x298>)
8003748: 4013 ands r3, r2
800374a: 2b00 cmp r3, #0
800374c: f000 810a beq.w 8003964 <HAL_UART_IRQHandler+0x2a0>
{
/* UART parity error interrupt occurred -------------------------------------*/
if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
8003750: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4
8003754: f003 0301 and.w r3, r3, #1
8003758: 2b00 cmp r3, #0
800375a: d011 beq.n 8003780 <HAL_UART_IRQHandler+0xbc>
800375c: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0
8003760: f403 7380 and.w r3, r3, #256 ; 0x100
8003764: 2b00 cmp r3, #0
8003766: d00b beq.n 8003780 <HAL_UART_IRQHandler+0xbc>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
8003768: 687b ldr r3, [r7, #4]
800376a: 681b ldr r3, [r3, #0]
800376c: 2201 movs r2, #1
800376e: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_PE;
8003770: 687b ldr r3, [r7, #4]
8003772: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
8003776: f043 0201 orr.w r2, r3, #1
800377a: 687b ldr r3, [r7, #4]
800377c: f8c3 2080 str.w r2, [r3, #128] ; 0x80
}
/* UART frame error interrupt occurred --------------------------------------*/
if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
8003780: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4
8003784: f003 0302 and.w r3, r3, #2
8003788: 2b00 cmp r3, #0
800378a: d011 beq.n 80037b0 <HAL_UART_IRQHandler+0xec>
800378c: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc
8003790: f003 0301 and.w r3, r3, #1
8003794: 2b00 cmp r3, #0
8003796: d00b beq.n 80037b0 <HAL_UART_IRQHandler+0xec>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
8003798: 687b ldr r3, [r7, #4]
800379a: 681b ldr r3, [r3, #0]
800379c: 2202 movs r2, #2
800379e: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_FE;
80037a0: 687b ldr r3, [r7, #4]
80037a2: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
80037a6: f043 0204 orr.w r2, r3, #4
80037aa: 687b ldr r3, [r7, #4]
80037ac: f8c3 2080 str.w r2, [r3, #128] ; 0x80
}
/* UART noise error interrupt occurred --------------------------------------*/
if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
80037b0: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4
80037b4: f003 0304 and.w r3, r3, #4
80037b8: 2b00 cmp r3, #0
80037ba: d011 beq.n 80037e0 <HAL_UART_IRQHandler+0x11c>
80037bc: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc
80037c0: f003 0301 and.w r3, r3, #1
80037c4: 2b00 cmp r3, #0
80037c6: d00b beq.n 80037e0 <HAL_UART_IRQHandler+0x11c>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
80037c8: 687b ldr r3, [r7, #4]
80037ca: 681b ldr r3, [r3, #0]
80037cc: 2204 movs r2, #4
80037ce: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_NE;
80037d0: 687b ldr r3, [r7, #4]
80037d2: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
80037d6: f043 0202 orr.w r2, r3, #2
80037da: 687b ldr r3, [r7, #4]
80037dc: f8c3 2080 str.w r2, [r3, #128] ; 0x80
}
/* UART Over-Run interrupt occurred -----------------------------------------*/
if (((isrflags & USART_ISR_ORE) != 0U)
80037e0: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4
80037e4: f003 0308 and.w r3, r3, #8
80037e8: 2b00 cmp r3, #0
80037ea: d017 beq.n 800381c <HAL_UART_IRQHandler+0x158>
&& (((cr1its & USART_CR1_RXNEIE) != 0U) ||
80037ec: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0
80037f0: f003 0320 and.w r3, r3, #32
80037f4: 2b00 cmp r3, #0
80037f6: d105 bne.n 8003804 <HAL_UART_IRQHandler+0x140>
((cr3its & USART_CR3_EIE) != 0U)))
80037f8: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc
80037fc: f003 0301 and.w r3, r3, #1
&& (((cr1its & USART_CR1_RXNEIE) != 0U) ||
8003800: 2b00 cmp r3, #0
8003802: d00b beq.n 800381c <HAL_UART_IRQHandler+0x158>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
8003804: 687b ldr r3, [r7, #4]
8003806: 681b ldr r3, [r3, #0]
8003808: 2208 movs r2, #8
800380a: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_ORE;
800380c: 687b ldr r3, [r7, #4]
800380e: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
8003812: f043 0208 orr.w r2, r3, #8
8003816: 687b ldr r3, [r7, #4]
8003818: f8c3 2080 str.w r2, [r3, #128] ; 0x80
}
/* UART Receiver Timeout interrupt occurred ---------------------------------*/
if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
800381c: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4
8003820: f403 6300 and.w r3, r3, #2048 ; 0x800
8003824: 2b00 cmp r3, #0
8003826: d012 beq.n 800384e <HAL_UART_IRQHandler+0x18a>
8003828: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0
800382c: f003 6380 and.w r3, r3, #67108864 ; 0x4000000
8003830: 2b00 cmp r3, #0
8003832: d00c beq.n 800384e <HAL_UART_IRQHandler+0x18a>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
8003834: 687b ldr r3, [r7, #4]
8003836: 681b ldr r3, [r3, #0]
8003838: f44f 6200 mov.w r2, #2048 ; 0x800
800383c: 621a str r2, [r3, #32]
huart->ErrorCode |= HAL_UART_ERROR_RTO;
800383e: 687b ldr r3, [r7, #4]
8003840: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
8003844: f043 0220 orr.w r2, r3, #32
8003848: 687b ldr r3, [r7, #4]
800384a: f8c3 2080 str.w r2, [r3, #128] ; 0x80
}
/* Call UART Error Call back function if need be ----------------------------*/
if (huart->ErrorCode != HAL_UART_ERROR_NONE)
800384e: 687b ldr r3, [r7, #4]
8003850: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
8003854: 2b00 cmp r3, #0
8003856: f000 8209 beq.w 8003c6c <HAL_UART_IRQHandler+0x5a8>
{
/* UART in mode Receiver --------------------------------------------------*/
if (((isrflags & USART_ISR_RXNE) != 0U)
800385a: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4
800385e: f003 0320 and.w r3, r3, #32
8003862: 2b00 cmp r3, #0
8003864: d00d beq.n 8003882 <HAL_UART_IRQHandler+0x1be>
&& ((cr1its & USART_CR1_RXNEIE) != 0U))
8003866: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0
800386a: f003 0320 and.w r3, r3, #32
800386e: 2b00 cmp r3, #0
8003870: d007 beq.n 8003882 <HAL_UART_IRQHandler+0x1be>
{
if (huart->RxISR != NULL)
8003872: 687b ldr r3, [r7, #4]
8003874: 6e5b ldr r3, [r3, #100] ; 0x64
8003876: 2b00 cmp r3, #0
8003878: d003 beq.n 8003882 <HAL_UART_IRQHandler+0x1be>
{
huart->RxISR(huart);
800387a: 687b ldr r3, [r7, #4]
800387c: 6e5b ldr r3, [r3, #100] ; 0x64
800387e: 6878 ldr r0, [r7, #4]
8003880: 4798 blx r3
/* If Error is to be considered as blocking :
- Receiver Timeout error in Reception
- Overrun error in Reception
- any error occurs in DMA mode reception
*/
errorcode = huart->ErrorCode;
8003882: 687b ldr r3, [r7, #4]
8003884: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80
8003888: f8c7 30d4 str.w r3, [r7, #212] ; 0xd4
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
800388c: 687b ldr r3, [r7, #4]
800388e: 681b ldr r3, [r3, #0]
8003890: 689b ldr r3, [r3, #8]
8003892: f003 0340 and.w r3, r3, #64 ; 0x40
8003896: 2b40 cmp r3, #64 ; 0x40
8003898: d005 beq.n 80038a6 <HAL_UART_IRQHandler+0x1e2>
((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
800389a: f8d7 30d4 ldr.w r3, [r7, #212] ; 0xd4
800389e: f003 0328 and.w r3, r3, #40 ; 0x28
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
80038a2: 2b00 cmp r3, #0
80038a4: d04f beq.n 8003946 <HAL_UART_IRQHandler+0x282>
{
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
UART_EndRxTransfer(huart);
80038a6: 6878 ldr r0, [r7, #4]
80038a8: f000 fd9c bl 80043e4 <UART_EndRxTransfer>
/* Disable the UART DMA Rx request if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
80038ac: 687b ldr r3, [r7, #4]
80038ae: 681b ldr r3, [r3, #0]
80038b0: 689b ldr r3, [r3, #8]
80038b2: f003 0340 and.w r3, r3, #64 ; 0x40
80038b6: 2b40 cmp r3, #64 ; 0x40
80038b8: d141 bne.n 800393e <HAL_UART_IRQHandler+0x27a>
{
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
80038ba: 687b ldr r3, [r7, #4]
80038bc: 681b ldr r3, [r3, #0]
80038be: 3308 adds r3, #8
80038c0: f8c7 309c str.w r3, [r7, #156] ; 0x9c
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80038c4: f8d7 309c ldr.w r3, [r7, #156] ; 0x9c
80038c8: e853 3f00 ldrex r3, [r3]
80038cc: f8c7 3098 str.w r3, [r7, #152] ; 0x98
return(result);
80038d0: f8d7 3098 ldr.w r3, [r7, #152] ; 0x98
80038d4: f023 0340 bic.w r3, r3, #64 ; 0x40
80038d8: f8c7 30d0 str.w r3, [r7, #208] ; 0xd0
80038dc: 687b ldr r3, [r7, #4]
80038de: 681b ldr r3, [r3, #0]
80038e0: 3308 adds r3, #8
80038e2: f8d7 20d0 ldr.w r2, [r7, #208] ; 0xd0
80038e6: f8c7 20a8 str.w r2, [r7, #168] ; 0xa8
80038ea: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80038ee: f8d7 10a4 ldr.w r1, [r7, #164] ; 0xa4
80038f2: f8d7 20a8 ldr.w r2, [r7, #168] ; 0xa8
80038f6: e841 2300 strex r3, r2, [r1]
80038fa: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0
return(result);
80038fe: f8d7 30a0 ldr.w r3, [r7, #160] ; 0xa0
8003902: 2b00 cmp r3, #0
8003904: d1d9 bne.n 80038ba <HAL_UART_IRQHandler+0x1f6>
/* Abort the UART DMA Rx channel */
if (huart->hdmarx != NULL)
8003906: 687b ldr r3, [r7, #4]
8003908: 6f1b ldr r3, [r3, #112] ; 0x70
800390a: 2b00 cmp r3, #0
800390c: d013 beq.n 8003936 <HAL_UART_IRQHandler+0x272>
{
/* Set the UART DMA Abort callback :
will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
800390e: 687b ldr r3, [r7, #4]
8003910: 6f1b ldr r3, [r3, #112] ; 0x70
8003912: 4a13 ldr r2, [pc, #76] ; (8003960 <HAL_UART_IRQHandler+0x29c>)
8003914: 635a str r2, [r3, #52] ; 0x34
/* Abort DMA RX */
if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
8003916: 687b ldr r3, [r7, #4]
8003918: 6f1b ldr r3, [r3, #112] ; 0x70
800391a: 4618 mov r0, r3
800391c: f7fd ffe2 bl 80018e4 <HAL_DMA_Abort_IT>
8003920: 4603 mov r3, r0
8003922: 2b00 cmp r3, #0
8003924: d017 beq.n 8003956 <HAL_UART_IRQHandler+0x292>
{
/* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
huart->hdmarx->XferAbortCallback(huart->hdmarx);
8003926: 687b ldr r3, [r7, #4]
8003928: 6f1b ldr r3, [r3, #112] ; 0x70
800392a: 6b5b ldr r3, [r3, #52] ; 0x34
800392c: 687a ldr r2, [r7, #4]
800392e: 6f12 ldr r2, [r2, #112] ; 0x70
8003930: 4610 mov r0, r2
8003932: 4798 blx r3
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
8003934: e00f b.n 8003956 <HAL_UART_IRQHandler+0x292>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
8003936: 6878 ldr r0, [r7, #4]
8003938: f000 f9ac bl 8003c94 <HAL_UART_ErrorCallback>
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
800393c: e00b b.n 8003956 <HAL_UART_IRQHandler+0x292>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
800393e: 6878 ldr r0, [r7, #4]
8003940: f000 f9a8 bl 8003c94 <HAL_UART_ErrorCallback>
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
8003944: e007 b.n 8003956 <HAL_UART_IRQHandler+0x292>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
8003946: 6878 ldr r0, [r7, #4]
8003948: f000 f9a4 bl 8003c94 <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
huart->ErrorCode = HAL_UART_ERROR_NONE;
800394c: 687b ldr r3, [r7, #4]
800394e: 2200 movs r2, #0
8003950: f8c3 2080 str.w r2, [r3, #128] ; 0x80
}
}
return;
8003954: e18a b.n 8003c6c <HAL_UART_IRQHandler+0x5a8>
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
8003956: bf00 nop
return;
8003958: e188 b.n 8003c6c <HAL_UART_IRQHandler+0x5a8>
800395a: bf00 nop
800395c: 04000120 .word 0x04000120
8003960: 080044ab .word 0x080044ab
} /* End if some error occurs */
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8003964: 687b ldr r3, [r7, #4]
8003966: 6e1b ldr r3, [r3, #96] ; 0x60
8003968: 2b01 cmp r3, #1
800396a: f040 8143 bne.w 8003bf4 <HAL_UART_IRQHandler+0x530>
&& ((isrflags & USART_ISR_IDLE) != 0U)
800396e: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4
8003972: f003 0310 and.w r3, r3, #16
8003976: 2b00 cmp r3, #0
8003978: f000 813c beq.w 8003bf4 <HAL_UART_IRQHandler+0x530>
&& ((cr1its & USART_ISR_IDLE) != 0U))
800397c: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0
8003980: f003 0310 and.w r3, r3, #16
8003984: 2b00 cmp r3, #0
8003986: f000 8135 beq.w 8003bf4 <HAL_UART_IRQHandler+0x530>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
800398a: 687b ldr r3, [r7, #4]
800398c: 681b ldr r3, [r3, #0]
800398e: 2210 movs r2, #16
8003990: 621a str r2, [r3, #32]
/* Check if DMA mode is enabled in UART */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
8003992: 687b ldr r3, [r7, #4]
8003994: 681b ldr r3, [r3, #0]
8003996: 689b ldr r3, [r3, #8]
8003998: f003 0340 and.w r3, r3, #64 ; 0x40
800399c: 2b40 cmp r3, #64 ; 0x40
800399e: f040 80b1 bne.w 8003b04 <HAL_UART_IRQHandler+0x440>
{
/* DMA mode enabled */
/* Check received length : If all expected data are received, do nothing,
(DMA cplt callback will be called).
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
80039a2: 687b ldr r3, [r7, #4]
80039a4: 6f1b ldr r3, [r3, #112] ; 0x70
80039a6: 681b ldr r3, [r3, #0]
80039a8: 685b ldr r3, [r3, #4]
80039aa: f8a7 30be strh.w r3, [r7, #190] ; 0xbe
if ((nb_remaining_rx_data > 0U)
80039ae: f8b7 30be ldrh.w r3, [r7, #190] ; 0xbe
80039b2: 2b00 cmp r3, #0
80039b4: f000 815c beq.w 8003c70 <HAL_UART_IRQHandler+0x5ac>
&& (nb_remaining_rx_data < huart->RxXferSize))
80039b8: 687b ldr r3, [r7, #4]
80039ba: f8b3 3058 ldrh.w r3, [r3, #88] ; 0x58
80039be: f8b7 20be ldrh.w r2, [r7, #190] ; 0xbe
80039c2: 429a cmp r2, r3
80039c4: f080 8154 bcs.w 8003c70 <HAL_UART_IRQHandler+0x5ac>
{
/* Reception is not complete */
huart->RxXferCount = nb_remaining_rx_data;
80039c8: 687b ldr r3, [r7, #4]
80039ca: f8b7 20be ldrh.w r2, [r7, #190] ; 0xbe
80039ce: f8a3 205a strh.w r2, [r3, #90] ; 0x5a
/* In Normal mode, end DMA xfer and HAL UART Rx process*/
if (huart->hdmarx->Init.Mode != DMA_CIRCULAR)
80039d2: 687b ldr r3, [r7, #4]
80039d4: 6f1b ldr r3, [r3, #112] ; 0x70
80039d6: 699b ldr r3, [r3, #24]
80039d8: 2b20 cmp r3, #32
80039da: f000 8085 beq.w 8003ae8 <HAL_UART_IRQHandler+0x424>
{
/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
80039de: 687b ldr r3, [r7, #4]
80039e0: 681b ldr r3, [r3, #0]
80039e2: f8c7 3088 str.w r3, [r7, #136] ; 0x88
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80039e6: f8d7 3088 ldr.w r3, [r7, #136] ; 0x88
80039ea: e853 3f00 ldrex r3, [r3]
80039ee: f8c7 3084 str.w r3, [r7, #132] ; 0x84
return(result);
80039f2: f8d7 3084 ldr.w r3, [r7, #132] ; 0x84
80039f6: f423 7380 bic.w r3, r3, #256 ; 0x100
80039fa: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8
80039fe: 687b ldr r3, [r7, #4]
8003a00: 681b ldr r3, [r3, #0]
8003a02: 461a mov r2, r3
8003a04: f8d7 30b8 ldr.w r3, [r7, #184] ; 0xb8
8003a08: f8c7 3094 str.w r3, [r7, #148] ; 0x94
8003a0c: f8c7 2090 str.w r2, [r7, #144] ; 0x90
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8003a10: f8d7 1090 ldr.w r1, [r7, #144] ; 0x90
8003a14: f8d7 2094 ldr.w r2, [r7, #148] ; 0x94
8003a18: e841 2300 strex r3, r2, [r1]
8003a1c: f8c7 308c str.w r3, [r7, #140] ; 0x8c
return(result);
8003a20: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c
8003a24: 2b00 cmp r3, #0
8003a26: d1da bne.n 80039de <HAL_UART_IRQHandler+0x31a>
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8003a28: 687b ldr r3, [r7, #4]
8003a2a: 681b ldr r3, [r3, #0]
8003a2c: 3308 adds r3, #8
8003a2e: 677b str r3, [r7, #116] ; 0x74
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8003a30: 6f7b ldr r3, [r7, #116] ; 0x74
8003a32: e853 3f00 ldrex r3, [r3]
8003a36: 673b str r3, [r7, #112] ; 0x70
return(result);
8003a38: 6f3b ldr r3, [r7, #112] ; 0x70
8003a3a: f023 0301 bic.w r3, r3, #1
8003a3e: f8c7 30b4 str.w r3, [r7, #180] ; 0xb4
8003a42: 687b ldr r3, [r7, #4]
8003a44: 681b ldr r3, [r3, #0]
8003a46: 3308 adds r3, #8
8003a48: f8d7 20b4 ldr.w r2, [r7, #180] ; 0xb4
8003a4c: f8c7 2080 str.w r2, [r7, #128] ; 0x80
8003a50: 67fb str r3, [r7, #124] ; 0x7c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8003a52: 6ff9 ldr r1, [r7, #124] ; 0x7c
8003a54: f8d7 2080 ldr.w r2, [r7, #128] ; 0x80
8003a58: e841 2300 strex r3, r2, [r1]
8003a5c: 67bb str r3, [r7, #120] ; 0x78
return(result);
8003a5e: 6fbb ldr r3, [r7, #120] ; 0x78
8003a60: 2b00 cmp r3, #0
8003a62: d1e1 bne.n 8003a28 <HAL_UART_IRQHandler+0x364>
/* Disable the DMA transfer for the receiver request by resetting the DMAR bit
in the UART CR3 register */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
8003a64: 687b ldr r3, [r7, #4]
8003a66: 681b ldr r3, [r3, #0]
8003a68: 3308 adds r3, #8
8003a6a: 663b str r3, [r7, #96] ; 0x60
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8003a6c: 6e3b ldr r3, [r7, #96] ; 0x60
8003a6e: e853 3f00 ldrex r3, [r3]
8003a72: 65fb str r3, [r7, #92] ; 0x5c
return(result);
8003a74: 6dfb ldr r3, [r7, #92] ; 0x5c
8003a76: f023 0340 bic.w r3, r3, #64 ; 0x40
8003a7a: f8c7 30b0 str.w r3, [r7, #176] ; 0xb0
8003a7e: 687b ldr r3, [r7, #4]
8003a80: 681b ldr r3, [r3, #0]
8003a82: 3308 adds r3, #8
8003a84: f8d7 20b0 ldr.w r2, [r7, #176] ; 0xb0
8003a88: 66fa str r2, [r7, #108] ; 0x6c
8003a8a: 66bb str r3, [r7, #104] ; 0x68
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8003a8c: 6eb9 ldr r1, [r7, #104] ; 0x68
8003a8e: 6efa ldr r2, [r7, #108] ; 0x6c
8003a90: e841 2300 strex r3, r2, [r1]
8003a94: 667b str r3, [r7, #100] ; 0x64
return(result);
8003a96: 6e7b ldr r3, [r7, #100] ; 0x64
8003a98: 2b00 cmp r3, #0
8003a9a: d1e3 bne.n 8003a64 <HAL_UART_IRQHandler+0x3a0>
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8003a9c: 687b ldr r3, [r7, #4]
8003a9e: 2220 movs r2, #32
8003aa0: 67da str r2, [r3, #124] ; 0x7c
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8003aa2: 687b ldr r3, [r7, #4]
8003aa4: 2200 movs r2, #0
8003aa6: 661a str r2, [r3, #96] ; 0x60
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8003aa8: 687b ldr r3, [r7, #4]
8003aaa: 681b ldr r3, [r3, #0]
8003aac: 64fb str r3, [r7, #76] ; 0x4c
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8003aae: 6cfb ldr r3, [r7, #76] ; 0x4c
8003ab0: e853 3f00 ldrex r3, [r3]
8003ab4: 64bb str r3, [r7, #72] ; 0x48
return(result);
8003ab6: 6cbb ldr r3, [r7, #72] ; 0x48
8003ab8: f023 0310 bic.w r3, r3, #16
8003abc: f8c7 30ac str.w r3, [r7, #172] ; 0xac
8003ac0: 687b ldr r3, [r7, #4]
8003ac2: 681b ldr r3, [r3, #0]
8003ac4: 461a mov r2, r3
8003ac6: f8d7 30ac ldr.w r3, [r7, #172] ; 0xac
8003aca: 65bb str r3, [r7, #88] ; 0x58
8003acc: 657a str r2, [r7, #84] ; 0x54
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8003ace: 6d79 ldr r1, [r7, #84] ; 0x54
8003ad0: 6dba ldr r2, [r7, #88] ; 0x58
8003ad2: e841 2300 strex r3, r2, [r1]
8003ad6: 653b str r3, [r7, #80] ; 0x50
return(result);
8003ad8: 6d3b ldr r3, [r7, #80] ; 0x50
8003ada: 2b00 cmp r3, #0
8003adc: d1e4 bne.n 8003aa8 <HAL_UART_IRQHandler+0x3e4>
/* Last bytes received, so no need as the abort is immediate */
(void)HAL_DMA_Abort(huart->hdmarx);
8003ade: 687b ldr r3, [r7, #4]
8003ae0: 6f1b ldr r3, [r3, #112] ; 0x70
8003ae2: 4618 mov r0, r3
8003ae4: f7fd fec5 bl 8001872 <HAL_DMA_Abort>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
8003ae8: 687b ldr r3, [r7, #4]
8003aea: f8b3 2058 ldrh.w r2, [r3, #88] ; 0x58
8003aee: 687b ldr r3, [r7, #4]
8003af0: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
8003af4: b29b uxth r3, r3
8003af6: 1ad3 subs r3, r2, r3
8003af8: b29b uxth r3, r3
8003afa: 4619 mov r1, r3
8003afc: 6878 ldr r0, [r7, #4]
8003afe: f000 f8d3 bl 8003ca8 <HAL_UARTEx_RxEventCallback>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
return;
8003b02: e0b5 b.n 8003c70 <HAL_UART_IRQHandler+0x5ac>
else
{
/* DMA mode not enabled */
/* Check received length : If all expected data are received, do nothing.
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
8003b04: 687b ldr r3, [r7, #4]
8003b06: f8b3 2058 ldrh.w r2, [r3, #88] ; 0x58
8003b0a: 687b ldr r3, [r7, #4]
8003b0c: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
8003b10: b29b uxth r3, r3
8003b12: 1ad3 subs r3, r2, r3
8003b14: f8a7 30ce strh.w r3, [r7, #206] ; 0xce
if ((huart->RxXferCount > 0U)
8003b18: 687b ldr r3, [r7, #4]
8003b1a: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
8003b1e: b29b uxth r3, r3
8003b20: 2b00 cmp r3, #0
8003b22: f000 80a7 beq.w 8003c74 <HAL_UART_IRQHandler+0x5b0>
&& (nb_rx_data > 0U))
8003b26: f8b7 30ce ldrh.w r3, [r7, #206] ; 0xce
8003b2a: 2b00 cmp r3, #0
8003b2c: f000 80a2 beq.w 8003c74 <HAL_UART_IRQHandler+0x5b0>
{
/* Disable the UART Parity Error Interrupt and RXNE interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
8003b30: 687b ldr r3, [r7, #4]
8003b32: 681b ldr r3, [r3, #0]
8003b34: 63bb str r3, [r7, #56] ; 0x38
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8003b36: 6bbb ldr r3, [r7, #56] ; 0x38
8003b38: e853 3f00 ldrex r3, [r3]
8003b3c: 637b str r3, [r7, #52] ; 0x34
return(result);
8003b3e: 6b7b ldr r3, [r7, #52] ; 0x34
8003b40: f423 7390 bic.w r3, r3, #288 ; 0x120
8003b44: f8c7 30c8 str.w r3, [r7, #200] ; 0xc8
8003b48: 687b ldr r3, [r7, #4]
8003b4a: 681b ldr r3, [r3, #0]
8003b4c: 461a mov r2, r3
8003b4e: f8d7 30c8 ldr.w r3, [r7, #200] ; 0xc8
8003b52: 647b str r3, [r7, #68] ; 0x44
8003b54: 643a str r2, [r7, #64] ; 0x40
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8003b56: 6c39 ldr r1, [r7, #64] ; 0x40
8003b58: 6c7a ldr r2, [r7, #68] ; 0x44
8003b5a: e841 2300 strex r3, r2, [r1]
8003b5e: 63fb str r3, [r7, #60] ; 0x3c
return(result);
8003b60: 6bfb ldr r3, [r7, #60] ; 0x3c
8003b62: 2b00 cmp r3, #0
8003b64: d1e4 bne.n 8003b30 <HAL_UART_IRQHandler+0x46c>
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8003b66: 687b ldr r3, [r7, #4]
8003b68: 681b ldr r3, [r3, #0]
8003b6a: 3308 adds r3, #8
8003b6c: 627b str r3, [r7, #36] ; 0x24
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8003b6e: 6a7b ldr r3, [r7, #36] ; 0x24
8003b70: e853 3f00 ldrex r3, [r3]
8003b74: 623b str r3, [r7, #32]
return(result);
8003b76: 6a3b ldr r3, [r7, #32]
8003b78: f023 0301 bic.w r3, r3, #1
8003b7c: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4
8003b80: 687b ldr r3, [r7, #4]
8003b82: 681b ldr r3, [r3, #0]
8003b84: 3308 adds r3, #8
8003b86: f8d7 20c4 ldr.w r2, [r7, #196] ; 0xc4
8003b8a: 633a str r2, [r7, #48] ; 0x30
8003b8c: 62fb str r3, [r7, #44] ; 0x2c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8003b8e: 6af9 ldr r1, [r7, #44] ; 0x2c
8003b90: 6b3a ldr r2, [r7, #48] ; 0x30
8003b92: e841 2300 strex r3, r2, [r1]
8003b96: 62bb str r3, [r7, #40] ; 0x28
return(result);
8003b98: 6abb ldr r3, [r7, #40] ; 0x28
8003b9a: 2b00 cmp r3, #0
8003b9c: d1e3 bne.n 8003b66 <HAL_UART_IRQHandler+0x4a2>
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8003b9e: 687b ldr r3, [r7, #4]
8003ba0: 2220 movs r2, #32
8003ba2: 67da str r2, [r3, #124] ; 0x7c
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8003ba4: 687b ldr r3, [r7, #4]
8003ba6: 2200 movs r2, #0
8003ba8: 661a str r2, [r3, #96] ; 0x60
/* Clear RxISR function pointer */
huart->RxISR = NULL;
8003baa: 687b ldr r3, [r7, #4]
8003bac: 2200 movs r2, #0
8003bae: 665a str r2, [r3, #100] ; 0x64
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8003bb0: 687b ldr r3, [r7, #4]
8003bb2: 681b ldr r3, [r3, #0]
8003bb4: 613b str r3, [r7, #16]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8003bb6: 693b ldr r3, [r7, #16]
8003bb8: e853 3f00 ldrex r3, [r3]
8003bbc: 60fb str r3, [r7, #12]
return(result);
8003bbe: 68fb ldr r3, [r7, #12]
8003bc0: f023 0310 bic.w r3, r3, #16
8003bc4: f8c7 30c0 str.w r3, [r7, #192] ; 0xc0
8003bc8: 687b ldr r3, [r7, #4]
8003bca: 681b ldr r3, [r3, #0]
8003bcc: 461a mov r2, r3
8003bce: f8d7 30c0 ldr.w r3, [r7, #192] ; 0xc0
8003bd2: 61fb str r3, [r7, #28]
8003bd4: 61ba str r2, [r7, #24]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8003bd6: 69b9 ldr r1, [r7, #24]
8003bd8: 69fa ldr r2, [r7, #28]
8003bda: e841 2300 strex r3, r2, [r1]
8003bde: 617b str r3, [r7, #20]
return(result);
8003be0: 697b ldr r3, [r7, #20]
8003be2: 2b00 cmp r3, #0
8003be4: d1e4 bne.n 8003bb0 <HAL_UART_IRQHandler+0x4ec>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx complete callback*/
huart->RxEventCallback(huart, nb_rx_data);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
8003be6: f8b7 30ce ldrh.w r3, [r7, #206] ; 0xce
8003bea: 4619 mov r1, r3
8003bec: 6878 ldr r0, [r7, #4]
8003bee: f000 f85b bl 8003ca8 <HAL_UARTEx_RxEventCallback>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
return;
8003bf2: e03f b.n 8003c74 <HAL_UART_IRQHandler+0x5b0>
}
}
/* UART wakeup from Stop mode interrupt occurred ---------------------------*/
if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U))
8003bf4: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4
8003bf8: f403 1380 and.w r3, r3, #1048576 ; 0x100000
8003bfc: 2b00 cmp r3, #0
8003bfe: d00e beq.n 8003c1e <HAL_UART_IRQHandler+0x55a>
8003c00: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc
8003c04: f403 0380 and.w r3, r3, #4194304 ; 0x400000
8003c08: 2b00 cmp r3, #0
8003c0a: d008 beq.n 8003c1e <HAL_UART_IRQHandler+0x55a>
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF);
8003c0c: 687b ldr r3, [r7, #4]
8003c0e: 681b ldr r3, [r3, #0]
8003c10: f44f 1280 mov.w r2, #1048576 ; 0x100000
8003c14: 621a str r2, [r3, #32]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/* Call registered Wakeup Callback */
huart->WakeupCallback(huart);
#else
/* Call legacy weak Wakeup Callback */
HAL_UARTEx_WakeupCallback(huart);
8003c16: 6878 ldr r0, [r7, #4]
8003c18: f000 fe9f bl 800495a <HAL_UARTEx_WakeupCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
return;
8003c1c: e02d b.n 8003c7a <HAL_UART_IRQHandler+0x5b6>
}
/* UART in mode Transmitter ------------------------------------------------*/
if (((isrflags & USART_ISR_TXE) != 0U)
8003c1e: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4
8003c22: f003 0380 and.w r3, r3, #128 ; 0x80
8003c26: 2b00 cmp r3, #0
8003c28: d00e beq.n 8003c48 <HAL_UART_IRQHandler+0x584>
&& ((cr1its & USART_CR1_TXEIE) != 0U))
8003c2a: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0
8003c2e: f003 0380 and.w r3, r3, #128 ; 0x80
8003c32: 2b00 cmp r3, #0
8003c34: d008 beq.n 8003c48 <HAL_UART_IRQHandler+0x584>
{
if (huart->TxISR != NULL)
8003c36: 687b ldr r3, [r7, #4]
8003c38: 6e9b ldr r3, [r3, #104] ; 0x68
8003c3a: 2b00 cmp r3, #0
8003c3c: d01c beq.n 8003c78 <HAL_UART_IRQHandler+0x5b4>
{
huart->TxISR(huart);
8003c3e: 687b ldr r3, [r7, #4]
8003c40: 6e9b ldr r3, [r3, #104] ; 0x68
8003c42: 6878 ldr r0, [r7, #4]
8003c44: 4798 blx r3
}
return;
8003c46: e017 b.n 8003c78 <HAL_UART_IRQHandler+0x5b4>
}
/* UART in mode Transmitter (transmission end) -----------------------------*/
if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
8003c48: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4
8003c4c: f003 0340 and.w r3, r3, #64 ; 0x40
8003c50: 2b00 cmp r3, #0
8003c52: d012 beq.n 8003c7a <HAL_UART_IRQHandler+0x5b6>
8003c54: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0
8003c58: f003 0340 and.w r3, r3, #64 ; 0x40
8003c5c: 2b00 cmp r3, #0
8003c5e: d00c beq.n 8003c7a <HAL_UART_IRQHandler+0x5b6>
{
UART_EndTransmit_IT(huart);
8003c60: 6878 ldr r0, [r7, #4]
8003c62: f000 fcf4 bl 800464e <UART_EndTransmit_IT>
return;
8003c66: e008 b.n 8003c7a <HAL_UART_IRQHandler+0x5b6>
return;
8003c68: bf00 nop
8003c6a: e006 b.n 8003c7a <HAL_UART_IRQHandler+0x5b6>
return;
8003c6c: bf00 nop
8003c6e: e004 b.n 8003c7a <HAL_UART_IRQHandler+0x5b6>
return;
8003c70: bf00 nop
8003c72: e002 b.n 8003c7a <HAL_UART_IRQHandler+0x5b6>
return;
8003c74: bf00 nop
8003c76: e000 b.n 8003c7a <HAL_UART_IRQHandler+0x5b6>
return;
8003c78: bf00 nop
}
}
8003c7a: 37e8 adds r7, #232 ; 0xe8
8003c7c: 46bd mov sp, r7
8003c7e: bd80 pop {r7, pc}
08003c80 <HAL_UART_TxCpltCallback>:
* @brief Tx Transfer completed callback.
* @param huart UART handle.
* @retval None
*/
__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
{
8003c80: b480 push {r7}
8003c82: b083 sub sp, #12
8003c84: af00 add r7, sp, #0
8003c86: 6078 str r0, [r7, #4]
UNUSED(huart);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UART_TxCpltCallback can be implemented in the user file.
*/
}
8003c88: bf00 nop
8003c8a: 370c adds r7, #12
8003c8c: 46bd mov sp, r7
8003c8e: f85d 7b04 ldr.w r7, [sp], #4
8003c92: 4770 bx lr
08003c94 <HAL_UART_ErrorCallback>:
* @brief UART error callback.
* @param huart UART handle.
* @retval None
*/
__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
{
8003c94: b480 push {r7}
8003c96: b083 sub sp, #12
8003c98: af00 add r7, sp, #0
8003c9a: 6078 str r0, [r7, #4]
UNUSED(huart);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UART_ErrorCallback can be implemented in the user file.
*/
}
8003c9c: bf00 nop
8003c9e: 370c adds r7, #12
8003ca0: 46bd mov sp, r7
8003ca2: f85d 7b04 ldr.w r7, [sp], #4
8003ca6: 4770 bx lr
08003ca8 <HAL_UARTEx_RxEventCallback>:
* @param Size Number of data available in application reception buffer (indicates a position in
* reception buffer until which, data are available)
* @retval None
*/
__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
{
8003ca8: b480 push {r7}
8003caa: b083 sub sp, #12
8003cac: af00 add r7, sp, #0
8003cae: 6078 str r0, [r7, #4]
8003cb0: 460b mov r3, r1
8003cb2: 807b strh r3, [r7, #2]
UNUSED(Size);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UARTEx_RxEventCallback can be implemented in the user file.
*/
}
8003cb4: bf00 nop
8003cb6: 370c adds r7, #12
8003cb8: 46bd mov sp, r7
8003cba: f85d 7b04 ldr.w r7, [sp], #4
8003cbe: 4770 bx lr
08003cc0 <UART_SetConfig>:
* @brief Configure the UART peripheral.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
{
8003cc0: b580 push {r7, lr}
8003cc2: b088 sub sp, #32
8003cc4: af00 add r7, sp, #0
8003cc6: 6078 str r0, [r7, #4]
uint32_t tmpreg;
uint16_t brrtemp;
UART_ClockSourceTypeDef clocksource;
uint32_t usartdiv;
HAL_StatusTypeDef ret = HAL_OK;
8003cc8: 2300 movs r3, #0
8003cca: 77bb strb r3, [r7, #30]
* the UART Word Length, Parity, Mode and oversampling:
* set the M bits according to huart->Init.WordLength value
* set PCE and PS bits according to huart->Init.Parity value
* set TE and RE bits according to huart->Init.Mode value
* set OVER8 bit according to huart->Init.OverSampling value */
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
8003ccc: 687b ldr r3, [r7, #4]
8003cce: 689a ldr r2, [r3, #8]
8003cd0: 687b ldr r3, [r7, #4]
8003cd2: 691b ldr r3, [r3, #16]
8003cd4: 431a orrs r2, r3
8003cd6: 687b ldr r3, [r7, #4]
8003cd8: 695b ldr r3, [r3, #20]
8003cda: 431a orrs r2, r3
8003cdc: 687b ldr r3, [r7, #4]
8003cde: 69db ldr r3, [r3, #28]
8003ce0: 4313 orrs r3, r2
8003ce2: 617b str r3, [r7, #20]
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
8003ce4: 687b ldr r3, [r7, #4]
8003ce6: 681b ldr r3, [r3, #0]
8003ce8: 681a ldr r2, [r3, #0]
8003cea: 4b8a ldr r3, [pc, #552] ; (8003f14 <UART_SetConfig+0x254>)
8003cec: 4013 ands r3, r2
8003cee: 687a ldr r2, [r7, #4]
8003cf0: 6812 ldr r2, [r2, #0]
8003cf2: 6979 ldr r1, [r7, #20]
8003cf4: 430b orrs r3, r1
8003cf6: 6013 str r3, [r2, #0]
/*-------------------------- USART CR2 Configuration -----------------------*/
/* Configure the UART Stop Bits: Set STOP[13:12] bits according
* to huart->Init.StopBits value */
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
8003cf8: 687b ldr r3, [r7, #4]
8003cfa: 681b ldr r3, [r3, #0]
8003cfc: 685b ldr r3, [r3, #4]
8003cfe: f423 5140 bic.w r1, r3, #12288 ; 0x3000
8003d02: 687b ldr r3, [r7, #4]
8003d04: 68da ldr r2, [r3, #12]
8003d06: 687b ldr r3, [r7, #4]
8003d08: 681b ldr r3, [r3, #0]
8003d0a: 430a orrs r2, r1
8003d0c: 605a str r2, [r3, #4]
/* Configure
* - UART HardWare Flow Control: set CTSE and RTSE bits according
* to huart->Init.HwFlowCtl value
* - one-bit sampling method versus three samples' majority rule according
* to huart->Init.OneBitSampling (not applicable to LPUART) */
tmpreg = (uint32_t)huart->Init.HwFlowCtl;
8003d0e: 687b ldr r3, [r7, #4]
8003d10: 699b ldr r3, [r3, #24]
8003d12: 617b str r3, [r7, #20]
tmpreg |= huart->Init.OneBitSampling;
8003d14: 687b ldr r3, [r7, #4]
8003d16: 6a1b ldr r3, [r3, #32]
8003d18: 697a ldr r2, [r7, #20]
8003d1a: 4313 orrs r3, r2
8003d1c: 617b str r3, [r7, #20]
MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
8003d1e: 687b ldr r3, [r7, #4]
8003d20: 681b ldr r3, [r3, #0]
8003d22: 689b ldr r3, [r3, #8]
8003d24: f423 6130 bic.w r1, r3, #2816 ; 0xb00
8003d28: 687b ldr r3, [r7, #4]
8003d2a: 681b ldr r3, [r3, #0]
8003d2c: 697a ldr r2, [r7, #20]
8003d2e: 430a orrs r2, r1
8003d30: 609a str r2, [r3, #8]
/*-------------------------- USART BRR Configuration -----------------------*/
UART_GETCLOCKSOURCE(huart, clocksource);
8003d32: 687b ldr r3, [r7, #4]
8003d34: 681b ldr r3, [r3, #0]
8003d36: 4a78 ldr r2, [pc, #480] ; (8003f18 <UART_SetConfig+0x258>)
8003d38: 4293 cmp r3, r2
8003d3a: d120 bne.n 8003d7e <UART_SetConfig+0xbe>
8003d3c: 4b77 ldr r3, [pc, #476] ; (8003f1c <UART_SetConfig+0x25c>)
8003d3e: 6b1b ldr r3, [r3, #48] ; 0x30
8003d40: f003 0303 and.w r3, r3, #3
8003d44: 2b03 cmp r3, #3
8003d46: d817 bhi.n 8003d78 <UART_SetConfig+0xb8>
8003d48: a201 add r2, pc, #4 ; (adr r2, 8003d50 <UART_SetConfig+0x90>)
8003d4a: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8003d4e: bf00 nop
8003d50: 08003d61 .word 0x08003d61
8003d54: 08003d6d .word 0x08003d6d
8003d58: 08003d73 .word 0x08003d73
8003d5c: 08003d67 .word 0x08003d67
8003d60: 2300 movs r3, #0
8003d62: 77fb strb r3, [r7, #31]
8003d64: e01d b.n 8003da2 <UART_SetConfig+0xe2>
8003d66: 2302 movs r3, #2
8003d68: 77fb strb r3, [r7, #31]
8003d6a: e01a b.n 8003da2 <UART_SetConfig+0xe2>
8003d6c: 2304 movs r3, #4
8003d6e: 77fb strb r3, [r7, #31]
8003d70: e017 b.n 8003da2 <UART_SetConfig+0xe2>
8003d72: 2308 movs r3, #8
8003d74: 77fb strb r3, [r7, #31]
8003d76: e014 b.n 8003da2 <UART_SetConfig+0xe2>
8003d78: 2310 movs r3, #16
8003d7a: 77fb strb r3, [r7, #31]
8003d7c: e011 b.n 8003da2 <UART_SetConfig+0xe2>
8003d7e: 687b ldr r3, [r7, #4]
8003d80: 681b ldr r3, [r3, #0]
8003d82: 4a67 ldr r2, [pc, #412] ; (8003f20 <UART_SetConfig+0x260>)
8003d84: 4293 cmp r3, r2
8003d86: d102 bne.n 8003d8e <UART_SetConfig+0xce>
8003d88: 2300 movs r3, #0
8003d8a: 77fb strb r3, [r7, #31]
8003d8c: e009 b.n 8003da2 <UART_SetConfig+0xe2>
8003d8e: 687b ldr r3, [r7, #4]
8003d90: 681b ldr r3, [r3, #0]
8003d92: 4a64 ldr r2, [pc, #400] ; (8003f24 <UART_SetConfig+0x264>)
8003d94: 4293 cmp r3, r2
8003d96: d102 bne.n 8003d9e <UART_SetConfig+0xde>
8003d98: 2300 movs r3, #0
8003d9a: 77fb strb r3, [r7, #31]
8003d9c: e001 b.n 8003da2 <UART_SetConfig+0xe2>
8003d9e: 2310 movs r3, #16
8003da0: 77fb strb r3, [r7, #31]
if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
8003da2: 687b ldr r3, [r7, #4]
8003da4: 69db ldr r3, [r3, #28]
8003da6: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
8003daa: d15b bne.n 8003e64 <UART_SetConfig+0x1a4>
{
switch (clocksource)
8003dac: 7ffb ldrb r3, [r7, #31]
8003dae: 2b08 cmp r3, #8
8003db0: d827 bhi.n 8003e02 <UART_SetConfig+0x142>
8003db2: a201 add r2, pc, #4 ; (adr r2, 8003db8 <UART_SetConfig+0xf8>)
8003db4: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8003db8: 08003ddd .word 0x08003ddd
8003dbc: 08003de5 .word 0x08003de5
8003dc0: 08003ded .word 0x08003ded
8003dc4: 08003e03 .word 0x08003e03
8003dc8: 08003df3 .word 0x08003df3
8003dcc: 08003e03 .word 0x08003e03
8003dd0: 08003e03 .word 0x08003e03
8003dd4: 08003e03 .word 0x08003e03
8003dd8: 08003dfb .word 0x08003dfb
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
8003ddc: f7ff f992 bl 8003104 <HAL_RCC_GetPCLK1Freq>
8003de0: 61b8 str r0, [r7, #24]
break;
8003de2: e013 b.n 8003e0c <UART_SetConfig+0x14c>
case UART_CLOCKSOURCE_PCLK2:
pclk = HAL_RCC_GetPCLK2Freq();
8003de4: f7ff f9b0 bl 8003148 <HAL_RCC_GetPCLK2Freq>
8003de8: 61b8 str r0, [r7, #24]
break;
8003dea: e00f b.n 8003e0c <UART_SetConfig+0x14c>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
8003dec: 4b4e ldr r3, [pc, #312] ; (8003f28 <UART_SetConfig+0x268>)
8003dee: 61bb str r3, [r7, #24]
break;
8003df0: e00c b.n 8003e0c <UART_SetConfig+0x14c>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
8003df2: f7ff f911 bl 8003018 <HAL_RCC_GetSysClockFreq>
8003df6: 61b8 str r0, [r7, #24]
break;
8003df8: e008 b.n 8003e0c <UART_SetConfig+0x14c>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
8003dfa: f44f 4300 mov.w r3, #32768 ; 0x8000
8003dfe: 61bb str r3, [r7, #24]
break;
8003e00: e004 b.n 8003e0c <UART_SetConfig+0x14c>
default:
pclk = 0U;
8003e02: 2300 movs r3, #0
8003e04: 61bb str r3, [r7, #24]
ret = HAL_ERROR;
8003e06: 2301 movs r3, #1
8003e08: 77bb strb r3, [r7, #30]
break;
8003e0a: bf00 nop
}
/* USARTDIV must be greater than or equal to 0d16 */
if (pclk != 0U)
8003e0c: 69bb ldr r3, [r7, #24]
8003e0e: 2b00 cmp r3, #0
8003e10: d074 beq.n 8003efc <UART_SetConfig+0x23c>
{
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate));
8003e12: 69bb ldr r3, [r7, #24]
8003e14: 005a lsls r2, r3, #1
8003e16: 687b ldr r3, [r7, #4]
8003e18: 685b ldr r3, [r3, #4]
8003e1a: 085b lsrs r3, r3, #1
8003e1c: 441a add r2, r3
8003e1e: 687b ldr r3, [r7, #4]
8003e20: 685b ldr r3, [r3, #4]
8003e22: fbb2 f3f3 udiv r3, r2, r3
8003e26: b29b uxth r3, r3
8003e28: 613b str r3, [r7, #16]
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
8003e2a: 693b ldr r3, [r7, #16]
8003e2c: 2b0f cmp r3, #15
8003e2e: d916 bls.n 8003e5e <UART_SetConfig+0x19e>
8003e30: 693b ldr r3, [r7, #16]
8003e32: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8003e36: d212 bcs.n 8003e5e <UART_SetConfig+0x19e>
{
brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
8003e38: 693b ldr r3, [r7, #16]
8003e3a: b29b uxth r3, r3
8003e3c: f023 030f bic.w r3, r3, #15
8003e40: 81fb strh r3, [r7, #14]
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
8003e42: 693b ldr r3, [r7, #16]
8003e44: 085b lsrs r3, r3, #1
8003e46: b29b uxth r3, r3
8003e48: f003 0307 and.w r3, r3, #7
8003e4c: b29a uxth r2, r3
8003e4e: 89fb ldrh r3, [r7, #14]
8003e50: 4313 orrs r3, r2
8003e52: 81fb strh r3, [r7, #14]
huart->Instance->BRR = brrtemp;
8003e54: 687b ldr r3, [r7, #4]
8003e56: 681b ldr r3, [r3, #0]
8003e58: 89fa ldrh r2, [r7, #14]
8003e5a: 60da str r2, [r3, #12]
8003e5c: e04e b.n 8003efc <UART_SetConfig+0x23c>
}
else
{
ret = HAL_ERROR;
8003e5e: 2301 movs r3, #1
8003e60: 77bb strb r3, [r7, #30]
8003e62: e04b b.n 8003efc <UART_SetConfig+0x23c>
}
}
}
else
{
switch (clocksource)
8003e64: 7ffb ldrb r3, [r7, #31]
8003e66: 2b08 cmp r3, #8
8003e68: d827 bhi.n 8003eba <UART_SetConfig+0x1fa>
8003e6a: a201 add r2, pc, #4 ; (adr r2, 8003e70 <UART_SetConfig+0x1b0>)
8003e6c: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8003e70: 08003e95 .word 0x08003e95
8003e74: 08003e9d .word 0x08003e9d
8003e78: 08003ea5 .word 0x08003ea5
8003e7c: 08003ebb .word 0x08003ebb
8003e80: 08003eab .word 0x08003eab
8003e84: 08003ebb .word 0x08003ebb
8003e88: 08003ebb .word 0x08003ebb
8003e8c: 08003ebb .word 0x08003ebb
8003e90: 08003eb3 .word 0x08003eb3
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
8003e94: f7ff f936 bl 8003104 <HAL_RCC_GetPCLK1Freq>
8003e98: 61b8 str r0, [r7, #24]
break;
8003e9a: e013 b.n 8003ec4 <UART_SetConfig+0x204>
case UART_CLOCKSOURCE_PCLK2:
pclk = HAL_RCC_GetPCLK2Freq();
8003e9c: f7ff f954 bl 8003148 <HAL_RCC_GetPCLK2Freq>
8003ea0: 61b8 str r0, [r7, #24]
break;
8003ea2: e00f b.n 8003ec4 <UART_SetConfig+0x204>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
8003ea4: 4b20 ldr r3, [pc, #128] ; (8003f28 <UART_SetConfig+0x268>)
8003ea6: 61bb str r3, [r7, #24]
break;
8003ea8: e00c b.n 8003ec4 <UART_SetConfig+0x204>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
8003eaa: f7ff f8b5 bl 8003018 <HAL_RCC_GetSysClockFreq>
8003eae: 61b8 str r0, [r7, #24]
break;
8003eb0: e008 b.n 8003ec4 <UART_SetConfig+0x204>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
8003eb2: f44f 4300 mov.w r3, #32768 ; 0x8000
8003eb6: 61bb str r3, [r7, #24]
break;
8003eb8: e004 b.n 8003ec4 <UART_SetConfig+0x204>
default:
pclk = 0U;
8003eba: 2300 movs r3, #0
8003ebc: 61bb str r3, [r7, #24]
ret = HAL_ERROR;
8003ebe: 2301 movs r3, #1
8003ec0: 77bb strb r3, [r7, #30]
break;
8003ec2: bf00 nop
}
if (pclk != 0U)
8003ec4: 69bb ldr r3, [r7, #24]
8003ec6: 2b00 cmp r3, #0
8003ec8: d018 beq.n 8003efc <UART_SetConfig+0x23c>
{
/* USARTDIV must be greater than or equal to 0d16 */
usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate));
8003eca: 687b ldr r3, [r7, #4]
8003ecc: 685b ldr r3, [r3, #4]
8003ece: 085a lsrs r2, r3, #1
8003ed0: 69bb ldr r3, [r7, #24]
8003ed2: 441a add r2, r3
8003ed4: 687b ldr r3, [r7, #4]
8003ed6: 685b ldr r3, [r3, #4]
8003ed8: fbb2 f3f3 udiv r3, r2, r3
8003edc: b29b uxth r3, r3
8003ede: 613b str r3, [r7, #16]
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
8003ee0: 693b ldr r3, [r7, #16]
8003ee2: 2b0f cmp r3, #15
8003ee4: d908 bls.n 8003ef8 <UART_SetConfig+0x238>
8003ee6: 693b ldr r3, [r7, #16]
8003ee8: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8003eec: d204 bcs.n 8003ef8 <UART_SetConfig+0x238>
{
huart->Instance->BRR = usartdiv;
8003eee: 687b ldr r3, [r7, #4]
8003ef0: 681b ldr r3, [r3, #0]
8003ef2: 693a ldr r2, [r7, #16]
8003ef4: 60da str r2, [r3, #12]
8003ef6: e001 b.n 8003efc <UART_SetConfig+0x23c>
}
else
{
ret = HAL_ERROR;
8003ef8: 2301 movs r3, #1
8003efa: 77bb strb r3, [r7, #30]
}
}
/* Clear ISR function pointers */
huart->RxISR = NULL;
8003efc: 687b ldr r3, [r7, #4]
8003efe: 2200 movs r2, #0
8003f00: 665a str r2, [r3, #100] ; 0x64
huart->TxISR = NULL;
8003f02: 687b ldr r3, [r7, #4]
8003f04: 2200 movs r2, #0
8003f06: 669a str r2, [r3, #104] ; 0x68
return ret;
8003f08: 7fbb ldrb r3, [r7, #30]
}
8003f0a: 4618 mov r0, r3
8003f0c: 3720 adds r7, #32
8003f0e: 46bd mov sp, r7
8003f10: bd80 pop {r7, pc}
8003f12: bf00 nop
8003f14: efff69f3 .word 0xefff69f3
8003f18: 40013800 .word 0x40013800
8003f1c: 40021000 .word 0x40021000
8003f20: 40004400 .word 0x40004400
8003f24: 40004800 .word 0x40004800
8003f28: 007a1200 .word 0x007a1200
08003f2c <UART_AdvFeatureConfig>:
* @brief Configure the UART peripheral advanced features.
* @param huart UART handle.
* @retval None
*/
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
{
8003f2c: b480 push {r7}
8003f2e: b083 sub sp, #12
8003f30: af00 add r7, sp, #0
8003f32: 6078 str r0, [r7, #4]
/* Check whether the set of advanced features to configure is properly set */
assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
/* if required, configure TX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
8003f34: 687b ldr r3, [r7, #4]
8003f36: 6a5b ldr r3, [r3, #36] ; 0x24
8003f38: f003 0301 and.w r3, r3, #1
8003f3c: 2b00 cmp r3, #0
8003f3e: d00a beq.n 8003f56 <UART_AdvFeatureConfig+0x2a>
{
assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
8003f40: 687b ldr r3, [r7, #4]
8003f42: 681b ldr r3, [r3, #0]
8003f44: 685b ldr r3, [r3, #4]
8003f46: f423 3100 bic.w r1, r3, #131072 ; 0x20000
8003f4a: 687b ldr r3, [r7, #4]
8003f4c: 6a9a ldr r2, [r3, #40] ; 0x28
8003f4e: 687b ldr r3, [r7, #4]
8003f50: 681b ldr r3, [r3, #0]
8003f52: 430a orrs r2, r1
8003f54: 605a str r2, [r3, #4]
}
/* if required, configure RX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
8003f56: 687b ldr r3, [r7, #4]
8003f58: 6a5b ldr r3, [r3, #36] ; 0x24
8003f5a: f003 0302 and.w r3, r3, #2
8003f5e: 2b00 cmp r3, #0
8003f60: d00a beq.n 8003f78 <UART_AdvFeatureConfig+0x4c>
{
assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
8003f62: 687b ldr r3, [r7, #4]
8003f64: 681b ldr r3, [r3, #0]
8003f66: 685b ldr r3, [r3, #4]
8003f68: f423 3180 bic.w r1, r3, #65536 ; 0x10000
8003f6c: 687b ldr r3, [r7, #4]
8003f6e: 6ada ldr r2, [r3, #44] ; 0x2c
8003f70: 687b ldr r3, [r7, #4]
8003f72: 681b ldr r3, [r3, #0]
8003f74: 430a orrs r2, r1
8003f76: 605a str r2, [r3, #4]
}
/* if required, configure data inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
8003f78: 687b ldr r3, [r7, #4]
8003f7a: 6a5b ldr r3, [r3, #36] ; 0x24
8003f7c: f003 0304 and.w r3, r3, #4
8003f80: 2b00 cmp r3, #0
8003f82: d00a beq.n 8003f9a <UART_AdvFeatureConfig+0x6e>
{
assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
8003f84: 687b ldr r3, [r7, #4]
8003f86: 681b ldr r3, [r3, #0]
8003f88: 685b ldr r3, [r3, #4]
8003f8a: f423 2180 bic.w r1, r3, #262144 ; 0x40000
8003f8e: 687b ldr r3, [r7, #4]
8003f90: 6b1a ldr r2, [r3, #48] ; 0x30
8003f92: 687b ldr r3, [r7, #4]
8003f94: 681b ldr r3, [r3, #0]
8003f96: 430a orrs r2, r1
8003f98: 605a str r2, [r3, #4]
}
/* if required, configure RX/TX pins swap */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
8003f9a: 687b ldr r3, [r7, #4]
8003f9c: 6a5b ldr r3, [r3, #36] ; 0x24
8003f9e: f003 0308 and.w r3, r3, #8
8003fa2: 2b00 cmp r3, #0
8003fa4: d00a beq.n 8003fbc <UART_AdvFeatureConfig+0x90>
{
assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
8003fa6: 687b ldr r3, [r7, #4]
8003fa8: 681b ldr r3, [r3, #0]
8003faa: 685b ldr r3, [r3, #4]
8003fac: f423 4100 bic.w r1, r3, #32768 ; 0x8000
8003fb0: 687b ldr r3, [r7, #4]
8003fb2: 6b5a ldr r2, [r3, #52] ; 0x34
8003fb4: 687b ldr r3, [r7, #4]
8003fb6: 681b ldr r3, [r3, #0]
8003fb8: 430a orrs r2, r1
8003fba: 605a str r2, [r3, #4]
}
/* if required, configure RX overrun detection disabling */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
8003fbc: 687b ldr r3, [r7, #4]
8003fbe: 6a5b ldr r3, [r3, #36] ; 0x24
8003fc0: f003 0310 and.w r3, r3, #16
8003fc4: 2b00 cmp r3, #0
8003fc6: d00a beq.n 8003fde <UART_AdvFeatureConfig+0xb2>
{
assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
8003fc8: 687b ldr r3, [r7, #4]
8003fca: 681b ldr r3, [r3, #0]
8003fcc: 689b ldr r3, [r3, #8]
8003fce: f423 5180 bic.w r1, r3, #4096 ; 0x1000
8003fd2: 687b ldr r3, [r7, #4]
8003fd4: 6b9a ldr r2, [r3, #56] ; 0x38
8003fd6: 687b ldr r3, [r7, #4]
8003fd8: 681b ldr r3, [r3, #0]
8003fda: 430a orrs r2, r1
8003fdc: 609a str r2, [r3, #8]
}
/* if required, configure DMA disabling on reception error */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
8003fde: 687b ldr r3, [r7, #4]
8003fe0: 6a5b ldr r3, [r3, #36] ; 0x24
8003fe2: f003 0320 and.w r3, r3, #32
8003fe6: 2b00 cmp r3, #0
8003fe8: d00a beq.n 8004000 <UART_AdvFeatureConfig+0xd4>
{
assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
8003fea: 687b ldr r3, [r7, #4]
8003fec: 681b ldr r3, [r3, #0]
8003fee: 689b ldr r3, [r3, #8]
8003ff0: f423 5100 bic.w r1, r3, #8192 ; 0x2000
8003ff4: 687b ldr r3, [r7, #4]
8003ff6: 6bda ldr r2, [r3, #60] ; 0x3c
8003ff8: 687b ldr r3, [r7, #4]
8003ffa: 681b ldr r3, [r3, #0]
8003ffc: 430a orrs r2, r1
8003ffe: 609a str r2, [r3, #8]
}
/* if required, configure auto Baud rate detection scheme */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
8004000: 687b ldr r3, [r7, #4]
8004002: 6a5b ldr r3, [r3, #36] ; 0x24
8004004: f003 0340 and.w r3, r3, #64 ; 0x40
8004008: 2b00 cmp r3, #0
800400a: d01a beq.n 8004042 <UART_AdvFeatureConfig+0x116>
{
assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
800400c: 687b ldr r3, [r7, #4]
800400e: 681b ldr r3, [r3, #0]
8004010: 685b ldr r3, [r3, #4]
8004012: f423 1180 bic.w r1, r3, #1048576 ; 0x100000
8004016: 687b ldr r3, [r7, #4]
8004018: 6c1a ldr r2, [r3, #64] ; 0x40
800401a: 687b ldr r3, [r7, #4]
800401c: 681b ldr r3, [r3, #0]
800401e: 430a orrs r2, r1
8004020: 605a str r2, [r3, #4]
/* set auto Baudrate detection parameters if detection is enabled */
if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
8004022: 687b ldr r3, [r7, #4]
8004024: 6c1b ldr r3, [r3, #64] ; 0x40
8004026: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000
800402a: d10a bne.n 8004042 <UART_AdvFeatureConfig+0x116>
{
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
800402c: 687b ldr r3, [r7, #4]
800402e: 681b ldr r3, [r3, #0]
8004030: 685b ldr r3, [r3, #4]
8004032: f423 01c0 bic.w r1, r3, #6291456 ; 0x600000
8004036: 687b ldr r3, [r7, #4]
8004038: 6c5a ldr r2, [r3, #68] ; 0x44
800403a: 687b ldr r3, [r7, #4]
800403c: 681b ldr r3, [r3, #0]
800403e: 430a orrs r2, r1
8004040: 605a str r2, [r3, #4]
}
}
/* if required, configure MSB first on communication line */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
8004042: 687b ldr r3, [r7, #4]
8004044: 6a5b ldr r3, [r3, #36] ; 0x24
8004046: f003 0380 and.w r3, r3, #128 ; 0x80
800404a: 2b00 cmp r3, #0
800404c: d00a beq.n 8004064 <UART_AdvFeatureConfig+0x138>
{
assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
800404e: 687b ldr r3, [r7, #4]
8004050: 681b ldr r3, [r3, #0]
8004052: 685b ldr r3, [r3, #4]
8004054: f423 2100 bic.w r1, r3, #524288 ; 0x80000
8004058: 687b ldr r3, [r7, #4]
800405a: 6c9a ldr r2, [r3, #72] ; 0x48
800405c: 687b ldr r3, [r7, #4]
800405e: 681b ldr r3, [r3, #0]
8004060: 430a orrs r2, r1
8004062: 605a str r2, [r3, #4]
}
}
8004064: bf00 nop
8004066: 370c adds r7, #12
8004068: 46bd mov sp, r7
800406a: f85d 7b04 ldr.w r7, [sp], #4
800406e: 4770 bx lr
08004070 <UART_CheckIdleState>:
* @brief Check the UART Idle State.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
{
8004070: b580 push {r7, lr}
8004072: b086 sub sp, #24
8004074: af02 add r7, sp, #8
8004076: 6078 str r0, [r7, #4]
uint32_t tickstart;
/* Initialize the UART ErrorCode */
huart->ErrorCode = HAL_UART_ERROR_NONE;
8004078: 687b ldr r3, [r7, #4]
800407a: 2200 movs r2, #0
800407c: f8c3 2080 str.w r2, [r3, #128] ; 0x80
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
8004080: f7fc fc74 bl 800096c <HAL_GetTick>
8004084: 60f8 str r0, [r7, #12]
/* Check if the Transmitter is enabled */
if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
8004086: 687b ldr r3, [r7, #4]
8004088: 681b ldr r3, [r3, #0]
800408a: 681b ldr r3, [r3, #0]
800408c: f003 0308 and.w r3, r3, #8
8004090: 2b08 cmp r3, #8
8004092: d10e bne.n 80040b2 <UART_CheckIdleState+0x42>
{
/* Wait until TEACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
8004094: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000
8004098: 9300 str r3, [sp, #0]
800409a: 68fb ldr r3, [r7, #12]
800409c: 2200 movs r2, #0
800409e: f44f 1100 mov.w r1, #2097152 ; 0x200000
80040a2: 6878 ldr r0, [r7, #4]
80040a4: f000 f82d bl 8004102 <UART_WaitOnFlagUntilTimeout>
80040a8: 4603 mov r3, r0
80040aa: 2b00 cmp r3, #0
80040ac: d001 beq.n 80040b2 <UART_CheckIdleState+0x42>
{
/* Timeout occurred */
return HAL_TIMEOUT;
80040ae: 2303 movs r3, #3
80040b0: e023 b.n 80040fa <UART_CheckIdleState+0x8a>
}
}
/* Check if the Receiver is enabled */
if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
80040b2: 687b ldr r3, [r7, #4]
80040b4: 681b ldr r3, [r3, #0]
80040b6: 681b ldr r3, [r3, #0]
80040b8: f003 0304 and.w r3, r3, #4
80040bc: 2b04 cmp r3, #4
80040be: d10e bne.n 80040de <UART_CheckIdleState+0x6e>
{
/* Wait until REACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
80040c0: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000
80040c4: 9300 str r3, [sp, #0]
80040c6: 68fb ldr r3, [r7, #12]
80040c8: 2200 movs r2, #0
80040ca: f44f 0180 mov.w r1, #4194304 ; 0x400000
80040ce: 6878 ldr r0, [r7, #4]
80040d0: f000 f817 bl 8004102 <UART_WaitOnFlagUntilTimeout>
80040d4: 4603 mov r3, r0
80040d6: 2b00 cmp r3, #0
80040d8: d001 beq.n 80040de <UART_CheckIdleState+0x6e>
{
/* Timeout occurred */
return HAL_TIMEOUT;
80040da: 2303 movs r3, #3
80040dc: e00d b.n 80040fa <UART_CheckIdleState+0x8a>
}
}
/* Initialize the UART State */
huart->gState = HAL_UART_STATE_READY;
80040de: 687b ldr r3, [r7, #4]
80040e0: 2220 movs r2, #32
80040e2: 679a str r2, [r3, #120] ; 0x78
huart->RxState = HAL_UART_STATE_READY;
80040e4: 687b ldr r3, [r7, #4]
80040e6: 2220 movs r2, #32
80040e8: 67da str r2, [r3, #124] ; 0x7c
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
80040ea: 687b ldr r3, [r7, #4]
80040ec: 2200 movs r2, #0
80040ee: 661a str r2, [r3, #96] ; 0x60
__HAL_UNLOCK(huart);
80040f0: 687b ldr r3, [r7, #4]
80040f2: 2200 movs r2, #0
80040f4: f883 2074 strb.w r2, [r3, #116] ; 0x74
return HAL_OK;
80040f8: 2300 movs r3, #0
}
80040fa: 4618 mov r0, r3
80040fc: 3710 adds r7, #16
80040fe: 46bd mov sp, r7
8004100: bd80 pop {r7, pc}
08004102 <UART_WaitOnFlagUntilTimeout>:
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout)
{
8004102: b580 push {r7, lr}
8004104: b09c sub sp, #112 ; 0x70
8004106: af00 add r7, sp, #0
8004108: 60f8 str r0, [r7, #12]
800410a: 60b9 str r1, [r7, #8]
800410c: 603b str r3, [r7, #0]
800410e: 4613 mov r3, r2
8004110: 71fb strb r3, [r7, #7]
/* Wait until flag is set */
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
8004112: e0a5 b.n 8004260 <UART_WaitOnFlagUntilTimeout+0x15e>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
8004114: 6fbb ldr r3, [r7, #120] ; 0x78
8004116: f1b3 3fff cmp.w r3, #4294967295 ; 0xffffffff
800411a: f000 80a1 beq.w 8004260 <UART_WaitOnFlagUntilTimeout+0x15e>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
800411e: f7fc fc25 bl 800096c <HAL_GetTick>
8004122: 4602 mov r2, r0
8004124: 683b ldr r3, [r7, #0]
8004126: 1ad3 subs r3, r2, r3
8004128: 6fba ldr r2, [r7, #120] ; 0x78
800412a: 429a cmp r2, r3
800412c: d302 bcc.n 8004134 <UART_WaitOnFlagUntilTimeout+0x32>
800412e: 6fbb ldr r3, [r7, #120] ; 0x78
8004130: 2b00 cmp r3, #0
8004132: d13e bne.n 80041b2 <UART_WaitOnFlagUntilTimeout+0xb0>
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
interrupts for the interrupt process */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
8004134: 68fb ldr r3, [r7, #12]
8004136: 681b ldr r3, [r3, #0]
8004138: 653b str r3, [r7, #80] ; 0x50
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
800413a: 6d3b ldr r3, [r7, #80] ; 0x50
800413c: e853 3f00 ldrex r3, [r3]
8004140: 64fb str r3, [r7, #76] ; 0x4c
return(result);
8004142: 6cfb ldr r3, [r7, #76] ; 0x4c
8004144: f423 73d0 bic.w r3, r3, #416 ; 0x1a0
8004148: 667b str r3, [r7, #100] ; 0x64
800414a: 68fb ldr r3, [r7, #12]
800414c: 681b ldr r3, [r3, #0]
800414e: 461a mov r2, r3
8004150: 6e7b ldr r3, [r7, #100] ; 0x64
8004152: 65fb str r3, [r7, #92] ; 0x5c
8004154: 65ba str r2, [r7, #88] ; 0x58
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004156: 6db9 ldr r1, [r7, #88] ; 0x58
8004158: 6dfa ldr r2, [r7, #92] ; 0x5c
800415a: e841 2300 strex r3, r2, [r1]
800415e: 657b str r3, [r7, #84] ; 0x54
return(result);
8004160: 6d7b ldr r3, [r7, #84] ; 0x54
8004162: 2b00 cmp r3, #0
8004164: d1e6 bne.n 8004134 <UART_WaitOnFlagUntilTimeout+0x32>
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8004166: 68fb ldr r3, [r7, #12]
8004168: 681b ldr r3, [r3, #0]
800416a: 3308 adds r3, #8
800416c: 63fb str r3, [r7, #60] ; 0x3c
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
800416e: 6bfb ldr r3, [r7, #60] ; 0x3c
8004170: e853 3f00 ldrex r3, [r3]
8004174: 63bb str r3, [r7, #56] ; 0x38
return(result);
8004176: 6bbb ldr r3, [r7, #56] ; 0x38
8004178: f023 0301 bic.w r3, r3, #1
800417c: 663b str r3, [r7, #96] ; 0x60
800417e: 68fb ldr r3, [r7, #12]
8004180: 681b ldr r3, [r3, #0]
8004182: 3308 adds r3, #8
8004184: 6e3a ldr r2, [r7, #96] ; 0x60
8004186: 64ba str r2, [r7, #72] ; 0x48
8004188: 647b str r3, [r7, #68] ; 0x44
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
800418a: 6c79 ldr r1, [r7, #68] ; 0x44
800418c: 6cba ldr r2, [r7, #72] ; 0x48
800418e: e841 2300 strex r3, r2, [r1]
8004192: 643b str r3, [r7, #64] ; 0x40
return(result);
8004194: 6c3b ldr r3, [r7, #64] ; 0x40
8004196: 2b00 cmp r3, #0
8004198: d1e5 bne.n 8004166 <UART_WaitOnFlagUntilTimeout+0x64>
huart->gState = HAL_UART_STATE_READY;
800419a: 68fb ldr r3, [r7, #12]
800419c: 2220 movs r2, #32
800419e: 679a str r2, [r3, #120] ; 0x78
huart->RxState = HAL_UART_STATE_READY;
80041a0: 68fb ldr r3, [r7, #12]
80041a2: 2220 movs r2, #32
80041a4: 67da str r2, [r3, #124] ; 0x7c
__HAL_UNLOCK(huart);
80041a6: 68fb ldr r3, [r7, #12]
80041a8: 2200 movs r2, #0
80041aa: f883 2074 strb.w r2, [r3, #116] ; 0x74
return HAL_TIMEOUT;
80041ae: 2303 movs r3, #3
80041b0: e067 b.n 8004282 <UART_WaitOnFlagUntilTimeout+0x180>
}
if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U)
80041b2: 68fb ldr r3, [r7, #12]
80041b4: 681b ldr r3, [r3, #0]
80041b6: 681b ldr r3, [r3, #0]
80041b8: f003 0304 and.w r3, r3, #4
80041bc: 2b00 cmp r3, #0
80041be: d04f beq.n 8004260 <UART_WaitOnFlagUntilTimeout+0x15e>
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
80041c0: 68fb ldr r3, [r7, #12]
80041c2: 681b ldr r3, [r3, #0]
80041c4: 69db ldr r3, [r3, #28]
80041c6: f403 6300 and.w r3, r3, #2048 ; 0x800
80041ca: f5b3 6f00 cmp.w r3, #2048 ; 0x800
80041ce: d147 bne.n 8004260 <UART_WaitOnFlagUntilTimeout+0x15e>
{
/* Clear Receiver Timeout flag*/
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
80041d0: 68fb ldr r3, [r7, #12]
80041d2: 681b ldr r3, [r3, #0]
80041d4: f44f 6200 mov.w r2, #2048 ; 0x800
80041d8: 621a str r2, [r3, #32]
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
interrupts for the interrupt process */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
80041da: 68fb ldr r3, [r7, #12]
80041dc: 681b ldr r3, [r3, #0]
80041de: 62bb str r3, [r7, #40] ; 0x28
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80041e0: 6abb ldr r3, [r7, #40] ; 0x28
80041e2: e853 3f00 ldrex r3, [r3]
80041e6: 627b str r3, [r7, #36] ; 0x24
return(result);
80041e8: 6a7b ldr r3, [r7, #36] ; 0x24
80041ea: f423 73d0 bic.w r3, r3, #416 ; 0x1a0
80041ee: 66fb str r3, [r7, #108] ; 0x6c
80041f0: 68fb ldr r3, [r7, #12]
80041f2: 681b ldr r3, [r3, #0]
80041f4: 461a mov r2, r3
80041f6: 6efb ldr r3, [r7, #108] ; 0x6c
80041f8: 637b str r3, [r7, #52] ; 0x34
80041fa: 633a str r2, [r7, #48] ; 0x30
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80041fc: 6b39 ldr r1, [r7, #48] ; 0x30
80041fe: 6b7a ldr r2, [r7, #52] ; 0x34
8004200: e841 2300 strex r3, r2, [r1]
8004204: 62fb str r3, [r7, #44] ; 0x2c
return(result);
8004206: 6afb ldr r3, [r7, #44] ; 0x2c
8004208: 2b00 cmp r3, #0
800420a: d1e6 bne.n 80041da <UART_WaitOnFlagUntilTimeout+0xd8>
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
800420c: 68fb ldr r3, [r7, #12]
800420e: 681b ldr r3, [r3, #0]
8004210: 3308 adds r3, #8
8004212: 617b str r3, [r7, #20]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004214: 697b ldr r3, [r7, #20]
8004216: e853 3f00 ldrex r3, [r3]
800421a: 613b str r3, [r7, #16]
return(result);
800421c: 693b ldr r3, [r7, #16]
800421e: f023 0301 bic.w r3, r3, #1
8004222: 66bb str r3, [r7, #104] ; 0x68
8004224: 68fb ldr r3, [r7, #12]
8004226: 681b ldr r3, [r3, #0]
8004228: 3308 adds r3, #8
800422a: 6eba ldr r2, [r7, #104] ; 0x68
800422c: 623a str r2, [r7, #32]
800422e: 61fb str r3, [r7, #28]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004230: 69f9 ldr r1, [r7, #28]
8004232: 6a3a ldr r2, [r7, #32]
8004234: e841 2300 strex r3, r2, [r1]
8004238: 61bb str r3, [r7, #24]
return(result);
800423a: 69bb ldr r3, [r7, #24]
800423c: 2b00 cmp r3, #0
800423e: d1e5 bne.n 800420c <UART_WaitOnFlagUntilTimeout+0x10a>
huart->gState = HAL_UART_STATE_READY;
8004240: 68fb ldr r3, [r7, #12]
8004242: 2220 movs r2, #32
8004244: 679a str r2, [r3, #120] ; 0x78
huart->RxState = HAL_UART_STATE_READY;
8004246: 68fb ldr r3, [r7, #12]
8004248: 2220 movs r2, #32
800424a: 67da str r2, [r3, #124] ; 0x7c
huart->ErrorCode = HAL_UART_ERROR_RTO;
800424c: 68fb ldr r3, [r7, #12]
800424e: 2220 movs r2, #32
8004250: f8c3 2080 str.w r2, [r3, #128] ; 0x80
/* Process Unlocked */
__HAL_UNLOCK(huart);
8004254: 68fb ldr r3, [r7, #12]
8004256: 2200 movs r2, #0
8004258: f883 2074 strb.w r2, [r3, #116] ; 0x74
return HAL_TIMEOUT;
800425c: 2303 movs r3, #3
800425e: e010 b.n 8004282 <UART_WaitOnFlagUntilTimeout+0x180>
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
8004260: 68fb ldr r3, [r7, #12]
8004262: 681b ldr r3, [r3, #0]
8004264: 69da ldr r2, [r3, #28]
8004266: 68bb ldr r3, [r7, #8]
8004268: 4013 ands r3, r2
800426a: 68ba ldr r2, [r7, #8]
800426c: 429a cmp r2, r3
800426e: bf0c ite eq
8004270: 2301 moveq r3, #1
8004272: 2300 movne r3, #0
8004274: b2db uxtb r3, r3
8004276: 461a mov r2, r3
8004278: 79fb ldrb r3, [r7, #7]
800427a: 429a cmp r2, r3
800427c: f43f af4a beq.w 8004114 <UART_WaitOnFlagUntilTimeout+0x12>
}
}
}
}
return HAL_OK;
8004280: 2300 movs r3, #0
}
8004282: 4618 mov r0, r3
8004284: 3770 adds r7, #112 ; 0x70
8004286: 46bd mov sp, r7
8004288: bd80 pop {r7, pc}
...
0800428c <UART_Start_Receive_IT>:
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
800428c: b480 push {r7}
800428e: b091 sub sp, #68 ; 0x44
8004290: af00 add r7, sp, #0
8004292: 60f8 str r0, [r7, #12]
8004294: 60b9 str r1, [r7, #8]
8004296: 4613 mov r3, r2
8004298: 80fb strh r3, [r7, #6]
huart->pRxBuffPtr = pData;
800429a: 68fb ldr r3, [r7, #12]
800429c: 68ba ldr r2, [r7, #8]
800429e: 655a str r2, [r3, #84] ; 0x54
huart->RxXferSize = Size;
80042a0: 68fb ldr r3, [r7, #12]
80042a2: 88fa ldrh r2, [r7, #6]
80042a4: f8a3 2058 strh.w r2, [r3, #88] ; 0x58
huart->RxXferCount = Size;
80042a8: 68fb ldr r3, [r7, #12]
80042aa: 88fa ldrh r2, [r7, #6]
80042ac: f8a3 205a strh.w r2, [r3, #90] ; 0x5a
huart->RxISR = NULL;
80042b0: 68fb ldr r3, [r7, #12]
80042b2: 2200 movs r2, #0
80042b4: 665a str r2, [r3, #100] ; 0x64
/* Computation of UART mask to apply to RDR register */
UART_MASK_COMPUTATION(huart);
80042b6: 68fb ldr r3, [r7, #12]
80042b8: 689b ldr r3, [r3, #8]
80042ba: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
80042be: d10e bne.n 80042de <UART_Start_Receive_IT+0x52>
80042c0: 68fb ldr r3, [r7, #12]
80042c2: 691b ldr r3, [r3, #16]
80042c4: 2b00 cmp r3, #0
80042c6: d105 bne.n 80042d4 <UART_Start_Receive_IT+0x48>
80042c8: 68fb ldr r3, [r7, #12]
80042ca: f240 12ff movw r2, #511 ; 0x1ff
80042ce: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
80042d2: e02d b.n 8004330 <UART_Start_Receive_IT+0xa4>
80042d4: 68fb ldr r3, [r7, #12]
80042d6: 22ff movs r2, #255 ; 0xff
80042d8: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
80042dc: e028 b.n 8004330 <UART_Start_Receive_IT+0xa4>
80042de: 68fb ldr r3, [r7, #12]
80042e0: 689b ldr r3, [r3, #8]
80042e2: 2b00 cmp r3, #0
80042e4: d10d bne.n 8004302 <UART_Start_Receive_IT+0x76>
80042e6: 68fb ldr r3, [r7, #12]
80042e8: 691b ldr r3, [r3, #16]
80042ea: 2b00 cmp r3, #0
80042ec: d104 bne.n 80042f8 <UART_Start_Receive_IT+0x6c>
80042ee: 68fb ldr r3, [r7, #12]
80042f0: 22ff movs r2, #255 ; 0xff
80042f2: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
80042f6: e01b b.n 8004330 <UART_Start_Receive_IT+0xa4>
80042f8: 68fb ldr r3, [r7, #12]
80042fa: 227f movs r2, #127 ; 0x7f
80042fc: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
8004300: e016 b.n 8004330 <UART_Start_Receive_IT+0xa4>
8004302: 68fb ldr r3, [r7, #12]
8004304: 689b ldr r3, [r3, #8]
8004306: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000
800430a: d10d bne.n 8004328 <UART_Start_Receive_IT+0x9c>
800430c: 68fb ldr r3, [r7, #12]
800430e: 691b ldr r3, [r3, #16]
8004310: 2b00 cmp r3, #0
8004312: d104 bne.n 800431e <UART_Start_Receive_IT+0x92>
8004314: 68fb ldr r3, [r7, #12]
8004316: 227f movs r2, #127 ; 0x7f
8004318: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
800431c: e008 b.n 8004330 <UART_Start_Receive_IT+0xa4>
800431e: 68fb ldr r3, [r7, #12]
8004320: 223f movs r2, #63 ; 0x3f
8004322: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
8004326: e003 b.n 8004330 <UART_Start_Receive_IT+0xa4>
8004328: 68fb ldr r3, [r7, #12]
800432a: 2200 movs r2, #0
800432c: f8a3 205c strh.w r2, [r3, #92] ; 0x5c
huart->ErrorCode = HAL_UART_ERROR_NONE;
8004330: 68fb ldr r3, [r7, #12]
8004332: 2200 movs r2, #0
8004334: f8c3 2080 str.w r2, [r3, #128] ; 0x80
huart->RxState = HAL_UART_STATE_BUSY_RX;
8004338: 68fb ldr r3, [r7, #12]
800433a: 2222 movs r2, #34 ; 0x22
800433c: 67da str r2, [r3, #124] ; 0x7c
/* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
800433e: 68fb ldr r3, [r7, #12]
8004340: 681b ldr r3, [r3, #0]
8004342: 3308 adds r3, #8
8004344: 62bb str r3, [r7, #40] ; 0x28
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004346: 6abb ldr r3, [r7, #40] ; 0x28
8004348: e853 3f00 ldrex r3, [r3]
800434c: 627b str r3, [r7, #36] ; 0x24
return(result);
800434e: 6a7b ldr r3, [r7, #36] ; 0x24
8004350: f043 0301 orr.w r3, r3, #1
8004354: 63fb str r3, [r7, #60] ; 0x3c
8004356: 68fb ldr r3, [r7, #12]
8004358: 681b ldr r3, [r3, #0]
800435a: 3308 adds r3, #8
800435c: 6bfa ldr r2, [r7, #60] ; 0x3c
800435e: 637a str r2, [r7, #52] ; 0x34
8004360: 633b str r3, [r7, #48] ; 0x30
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004362: 6b39 ldr r1, [r7, #48] ; 0x30
8004364: 6b7a ldr r2, [r7, #52] ; 0x34
8004366: e841 2300 strex r3, r2, [r1]
800436a: 62fb str r3, [r7, #44] ; 0x2c
return(result);
800436c: 6afb ldr r3, [r7, #44] ; 0x2c
800436e: 2b00 cmp r3, #0
8004370: d1e5 bne.n 800433e <UART_Start_Receive_IT+0xb2>
/* Set the Rx ISR function pointer according to the data word length */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
8004372: 68fb ldr r3, [r7, #12]
8004374: 689b ldr r3, [r3, #8]
8004376: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
800437a: d107 bne.n 800438c <UART_Start_Receive_IT+0x100>
800437c: 68fb ldr r3, [r7, #12]
800437e: 691b ldr r3, [r3, #16]
8004380: 2b00 cmp r3, #0
8004382: d103 bne.n 800438c <UART_Start_Receive_IT+0x100>
{
huart->RxISR = UART_RxISR_16BIT;
8004384: 68fb ldr r3, [r7, #12]
8004386: 4a15 ldr r2, [pc, #84] ; (80043dc <UART_Start_Receive_IT+0x150>)
8004388: 665a str r2, [r3, #100] ; 0x64
800438a: e002 b.n 8004392 <UART_Start_Receive_IT+0x106>
}
else
{
huart->RxISR = UART_RxISR_8BIT;
800438c: 68fb ldr r3, [r7, #12]
800438e: 4a14 ldr r2, [pc, #80] ; (80043e0 <UART_Start_Receive_IT+0x154>)
8004390: 665a str r2, [r3, #100] ; 0x64
}
__HAL_UNLOCK(huart);
8004392: 68fb ldr r3, [r7, #12]
8004394: 2200 movs r2, #0
8004396: f883 2074 strb.w r2, [r3, #116] ; 0x74
/* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
800439a: 68fb ldr r3, [r7, #12]
800439c: 681b ldr r3, [r3, #0]
800439e: 617b str r3, [r7, #20]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80043a0: 697b ldr r3, [r7, #20]
80043a2: e853 3f00 ldrex r3, [r3]
80043a6: 613b str r3, [r7, #16]
return(result);
80043a8: 693b ldr r3, [r7, #16]
80043aa: f443 7390 orr.w r3, r3, #288 ; 0x120
80043ae: 63bb str r3, [r7, #56] ; 0x38
80043b0: 68fb ldr r3, [r7, #12]
80043b2: 681b ldr r3, [r3, #0]
80043b4: 461a mov r2, r3
80043b6: 6bbb ldr r3, [r7, #56] ; 0x38
80043b8: 623b str r3, [r7, #32]
80043ba: 61fa str r2, [r7, #28]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80043bc: 69f9 ldr r1, [r7, #28]
80043be: 6a3a ldr r2, [r7, #32]
80043c0: e841 2300 strex r3, r2, [r1]
80043c4: 61bb str r3, [r7, #24]
return(result);
80043c6: 69bb ldr r3, [r7, #24]
80043c8: 2b00 cmp r3, #0
80043ca: d1e6 bne.n 800439a <UART_Start_Receive_IT+0x10e>
return HAL_OK;
80043cc: 2300 movs r3, #0
}
80043ce: 4618 mov r0, r3
80043d0: 3744 adds r7, #68 ; 0x44
80043d2: 46bd mov sp, r7
80043d4: f85d 7b04 ldr.w r7, [sp], #4
80043d8: 4770 bx lr
80043da: bf00 nop
80043dc: 080047ff .word 0x080047ff
80043e0: 080046a3 .word 0x080046a3
080043e4 <UART_EndRxTransfer>:
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
* @param huart UART handle.
* @retval None
*/
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
{
80043e4: b480 push {r7}
80043e6: b095 sub sp, #84 ; 0x54
80043e8: af00 add r7, sp, #0
80043ea: 6078 str r0, [r7, #4]
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
80043ec: 687b ldr r3, [r7, #4]
80043ee: 681b ldr r3, [r3, #0]
80043f0: 637b str r3, [r7, #52] ; 0x34
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80043f2: 6b7b ldr r3, [r7, #52] ; 0x34
80043f4: e853 3f00 ldrex r3, [r3]
80043f8: 633b str r3, [r7, #48] ; 0x30
return(result);
80043fa: 6b3b ldr r3, [r7, #48] ; 0x30
80043fc: f423 7390 bic.w r3, r3, #288 ; 0x120
8004400: 64fb str r3, [r7, #76] ; 0x4c
8004402: 687b ldr r3, [r7, #4]
8004404: 681b ldr r3, [r3, #0]
8004406: 461a mov r2, r3
8004408: 6cfb ldr r3, [r7, #76] ; 0x4c
800440a: 643b str r3, [r7, #64] ; 0x40
800440c: 63fa str r2, [r7, #60] ; 0x3c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
800440e: 6bf9 ldr r1, [r7, #60] ; 0x3c
8004410: 6c3a ldr r2, [r7, #64] ; 0x40
8004412: e841 2300 strex r3, r2, [r1]
8004416: 63bb str r3, [r7, #56] ; 0x38
return(result);
8004418: 6bbb ldr r3, [r7, #56] ; 0x38
800441a: 2b00 cmp r3, #0
800441c: d1e6 bne.n 80043ec <UART_EndRxTransfer+0x8>
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
800441e: 687b ldr r3, [r7, #4]
8004420: 681b ldr r3, [r3, #0]
8004422: 3308 adds r3, #8
8004424: 623b str r3, [r7, #32]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004426: 6a3b ldr r3, [r7, #32]
8004428: e853 3f00 ldrex r3, [r3]
800442c: 61fb str r3, [r7, #28]
return(result);
800442e: 69fb ldr r3, [r7, #28]
8004430: f023 0301 bic.w r3, r3, #1
8004434: 64bb str r3, [r7, #72] ; 0x48
8004436: 687b ldr r3, [r7, #4]
8004438: 681b ldr r3, [r3, #0]
800443a: 3308 adds r3, #8
800443c: 6cba ldr r2, [r7, #72] ; 0x48
800443e: 62fa str r2, [r7, #44] ; 0x2c
8004440: 62bb str r3, [r7, #40] ; 0x28
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004442: 6ab9 ldr r1, [r7, #40] ; 0x28
8004444: 6afa ldr r2, [r7, #44] ; 0x2c
8004446: e841 2300 strex r3, r2, [r1]
800444a: 627b str r3, [r7, #36] ; 0x24
return(result);
800444c: 6a7b ldr r3, [r7, #36] ; 0x24
800444e: 2b00 cmp r3, #0
8004450: d1e5 bne.n 800441e <UART_EndRxTransfer+0x3a>
/* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8004452: 687b ldr r3, [r7, #4]
8004454: 6e1b ldr r3, [r3, #96] ; 0x60
8004456: 2b01 cmp r3, #1
8004458: d118 bne.n 800448c <UART_EndRxTransfer+0xa8>
{
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
800445a: 687b ldr r3, [r7, #4]
800445c: 681b ldr r3, [r3, #0]
800445e: 60fb str r3, [r7, #12]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004460: 68fb ldr r3, [r7, #12]
8004462: e853 3f00 ldrex r3, [r3]
8004466: 60bb str r3, [r7, #8]
return(result);
8004468: 68bb ldr r3, [r7, #8]
800446a: f023 0310 bic.w r3, r3, #16
800446e: 647b str r3, [r7, #68] ; 0x44
8004470: 687b ldr r3, [r7, #4]
8004472: 681b ldr r3, [r3, #0]
8004474: 461a mov r2, r3
8004476: 6c7b ldr r3, [r7, #68] ; 0x44
8004478: 61bb str r3, [r7, #24]
800447a: 617a str r2, [r7, #20]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
800447c: 6979 ldr r1, [r7, #20]
800447e: 69ba ldr r2, [r7, #24]
8004480: e841 2300 strex r3, r2, [r1]
8004484: 613b str r3, [r7, #16]
return(result);
8004486: 693b ldr r3, [r7, #16]
8004488: 2b00 cmp r3, #0
800448a: d1e6 bne.n 800445a <UART_EndRxTransfer+0x76>
}
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
800448c: 687b ldr r3, [r7, #4]
800448e: 2220 movs r2, #32
8004490: 67da str r2, [r3, #124] ; 0x7c
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8004492: 687b ldr r3, [r7, #4]
8004494: 2200 movs r2, #0
8004496: 661a str r2, [r3, #96] ; 0x60
/* Reset RxIsr function pointer */
huart->RxISR = NULL;
8004498: 687b ldr r3, [r7, #4]
800449a: 2200 movs r2, #0
800449c: 665a str r2, [r3, #100] ; 0x64
}
800449e: bf00 nop
80044a0: 3754 adds r7, #84 ; 0x54
80044a2: 46bd mov sp, r7
80044a4: f85d 7b04 ldr.w r7, [sp], #4
80044a8: 4770 bx lr
080044aa <UART_DMAAbortOnError>:
* (To be called at end of DMA Abort procedure following error occurrence).
* @param hdma DMA handle.
* @retval None
*/
static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
80044aa: b580 push {r7, lr}
80044ac: b084 sub sp, #16
80044ae: af00 add r7, sp, #0
80044b0: 6078 str r0, [r7, #4]
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
80044b2: 687b ldr r3, [r7, #4]
80044b4: 6a5b ldr r3, [r3, #36] ; 0x24
80044b6: 60fb str r3, [r7, #12]
huart->RxXferCount = 0U;
80044b8: 68fb ldr r3, [r7, #12]
80044ba: 2200 movs r2, #0
80044bc: f8a3 205a strh.w r2, [r3, #90] ; 0x5a
huart->TxXferCount = 0U;
80044c0: 68fb ldr r3, [r7, #12]
80044c2: 2200 movs r2, #0
80044c4: f8a3 2052 strh.w r2, [r3, #82] ; 0x52
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
80044c8: 68f8 ldr r0, [r7, #12]
80044ca: f7ff fbe3 bl 8003c94 <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
80044ce: bf00 nop
80044d0: 3710 adds r7, #16
80044d2: 46bd mov sp, r7
80044d4: bd80 pop {r7, pc}
080044d6 <UART_TxISR_8BIT>:
* interruptions have been enabled by HAL_UART_Transmit_IT().
* @param huart UART handle.
* @retval None
*/
static void UART_TxISR_8BIT(UART_HandleTypeDef *huart)
{
80044d6: b480 push {r7}
80044d8: b08f sub sp, #60 ; 0x3c
80044da: af00 add r7, sp, #0
80044dc: 6078 str r0, [r7, #4]
/* Check that a Tx process is ongoing */
if (huart->gState == HAL_UART_STATE_BUSY_TX)
80044de: 687b ldr r3, [r7, #4]
80044e0: 6f9b ldr r3, [r3, #120] ; 0x78
80044e2: 2b21 cmp r3, #33 ; 0x21
80044e4: d14d bne.n 8004582 <UART_TxISR_8BIT+0xac>
{
if (huart->TxXferCount == 0U)
80044e6: 687b ldr r3, [r7, #4]
80044e8: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52
80044ec: b29b uxth r3, r3
80044ee: 2b00 cmp r3, #0
80044f0: d132 bne.n 8004558 <UART_TxISR_8BIT+0x82>
{
/* Disable the UART Transmit Data Register Empty Interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
80044f2: 687b ldr r3, [r7, #4]
80044f4: 681b ldr r3, [r3, #0]
80044f6: 623b str r3, [r7, #32]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80044f8: 6a3b ldr r3, [r7, #32]
80044fa: e853 3f00 ldrex r3, [r3]
80044fe: 61fb str r3, [r7, #28]
return(result);
8004500: 69fb ldr r3, [r7, #28]
8004502: f023 0380 bic.w r3, r3, #128 ; 0x80
8004506: 637b str r3, [r7, #52] ; 0x34
8004508: 687b ldr r3, [r7, #4]
800450a: 681b ldr r3, [r3, #0]
800450c: 461a mov r2, r3
800450e: 6b7b ldr r3, [r7, #52] ; 0x34
8004510: 62fb str r3, [r7, #44] ; 0x2c
8004512: 62ba str r2, [r7, #40] ; 0x28
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004514: 6ab9 ldr r1, [r7, #40] ; 0x28
8004516: 6afa ldr r2, [r7, #44] ; 0x2c
8004518: e841 2300 strex r3, r2, [r1]
800451c: 627b str r3, [r7, #36] ; 0x24
return(result);
800451e: 6a7b ldr r3, [r7, #36] ; 0x24
8004520: 2b00 cmp r3, #0
8004522: d1e6 bne.n 80044f2 <UART_TxISR_8BIT+0x1c>
/* Enable the UART Transmit Complete Interrupt */
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
8004524: 687b ldr r3, [r7, #4]
8004526: 681b ldr r3, [r3, #0]
8004528: 60fb str r3, [r7, #12]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
800452a: 68fb ldr r3, [r7, #12]
800452c: e853 3f00 ldrex r3, [r3]
8004530: 60bb str r3, [r7, #8]
return(result);
8004532: 68bb ldr r3, [r7, #8]
8004534: f043 0340 orr.w r3, r3, #64 ; 0x40
8004538: 633b str r3, [r7, #48] ; 0x30
800453a: 687b ldr r3, [r7, #4]
800453c: 681b ldr r3, [r3, #0]
800453e: 461a mov r2, r3
8004540: 6b3b ldr r3, [r7, #48] ; 0x30
8004542: 61bb str r3, [r7, #24]
8004544: 617a str r2, [r7, #20]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004546: 6979 ldr r1, [r7, #20]
8004548: 69ba ldr r2, [r7, #24]
800454a: e841 2300 strex r3, r2, [r1]
800454e: 613b str r3, [r7, #16]
return(result);
8004550: 693b ldr r3, [r7, #16]
8004552: 2b00 cmp r3, #0
8004554: d1e6 bne.n 8004524 <UART_TxISR_8BIT+0x4e>
huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
huart->pTxBuffPtr++;
huart->TxXferCount--;
}
}
}
8004556: e014 b.n 8004582 <UART_TxISR_8BIT+0xac>
huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
8004558: 687b ldr r3, [r7, #4]
800455a: 6cdb ldr r3, [r3, #76] ; 0x4c
800455c: 781a ldrb r2, [r3, #0]
800455e: 687b ldr r3, [r7, #4]
8004560: 681b ldr r3, [r3, #0]
8004562: b292 uxth r2, r2
8004564: 851a strh r2, [r3, #40] ; 0x28
huart->pTxBuffPtr++;
8004566: 687b ldr r3, [r7, #4]
8004568: 6cdb ldr r3, [r3, #76] ; 0x4c
800456a: 1c5a adds r2, r3, #1
800456c: 687b ldr r3, [r7, #4]
800456e: 64da str r2, [r3, #76] ; 0x4c
huart->TxXferCount--;
8004570: 687b ldr r3, [r7, #4]
8004572: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52
8004576: b29b uxth r3, r3
8004578: 3b01 subs r3, #1
800457a: b29a uxth r2, r3
800457c: 687b ldr r3, [r7, #4]
800457e: f8a3 2052 strh.w r2, [r3, #82] ; 0x52
}
8004582: bf00 nop
8004584: 373c adds r7, #60 ; 0x3c
8004586: 46bd mov sp, r7
8004588: f85d 7b04 ldr.w r7, [sp], #4
800458c: 4770 bx lr
0800458e <UART_TxISR_16BIT>:
* interruptions have been enabled by HAL_UART_Transmit_IT().
* @param huart UART handle.
* @retval None
*/
static void UART_TxISR_16BIT(UART_HandleTypeDef *huart)
{
800458e: b480 push {r7}
8004590: b091 sub sp, #68 ; 0x44
8004592: af00 add r7, sp, #0
8004594: 6078 str r0, [r7, #4]
uint16_t *tmp;
/* Check that a Tx process is ongoing */
if (huart->gState == HAL_UART_STATE_BUSY_TX)
8004596: 687b ldr r3, [r7, #4]
8004598: 6f9b ldr r3, [r3, #120] ; 0x78
800459a: 2b21 cmp r3, #33 ; 0x21
800459c: d151 bne.n 8004642 <UART_TxISR_16BIT+0xb4>
{
if (huart->TxXferCount == 0U)
800459e: 687b ldr r3, [r7, #4]
80045a0: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52
80045a4: b29b uxth r3, r3
80045a6: 2b00 cmp r3, #0
80045a8: d132 bne.n 8004610 <UART_TxISR_16BIT+0x82>
{
/* Disable the UART Transmit Data Register Empty Interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE);
80045aa: 687b ldr r3, [r7, #4]
80045ac: 681b ldr r3, [r3, #0]
80045ae: 627b str r3, [r7, #36] ; 0x24
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80045b0: 6a7b ldr r3, [r7, #36] ; 0x24
80045b2: e853 3f00 ldrex r3, [r3]
80045b6: 623b str r3, [r7, #32]
return(result);
80045b8: 6a3b ldr r3, [r7, #32]
80045ba: f023 0380 bic.w r3, r3, #128 ; 0x80
80045be: 63bb str r3, [r7, #56] ; 0x38
80045c0: 687b ldr r3, [r7, #4]
80045c2: 681b ldr r3, [r3, #0]
80045c4: 461a mov r2, r3
80045c6: 6bbb ldr r3, [r7, #56] ; 0x38
80045c8: 633b str r3, [r7, #48] ; 0x30
80045ca: 62fa str r2, [r7, #44] ; 0x2c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80045cc: 6af9 ldr r1, [r7, #44] ; 0x2c
80045ce: 6b3a ldr r2, [r7, #48] ; 0x30
80045d0: e841 2300 strex r3, r2, [r1]
80045d4: 62bb str r3, [r7, #40] ; 0x28
return(result);
80045d6: 6abb ldr r3, [r7, #40] ; 0x28
80045d8: 2b00 cmp r3, #0
80045da: d1e6 bne.n 80045aa <UART_TxISR_16BIT+0x1c>
/* Enable the UART Transmit Complete Interrupt */
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
80045dc: 687b ldr r3, [r7, #4]
80045de: 681b ldr r3, [r3, #0]
80045e0: 613b str r3, [r7, #16]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80045e2: 693b ldr r3, [r7, #16]
80045e4: e853 3f00 ldrex r3, [r3]
80045e8: 60fb str r3, [r7, #12]
return(result);
80045ea: 68fb ldr r3, [r7, #12]
80045ec: f043 0340 orr.w r3, r3, #64 ; 0x40
80045f0: 637b str r3, [r7, #52] ; 0x34
80045f2: 687b ldr r3, [r7, #4]
80045f4: 681b ldr r3, [r3, #0]
80045f6: 461a mov r2, r3
80045f8: 6b7b ldr r3, [r7, #52] ; 0x34
80045fa: 61fb str r3, [r7, #28]
80045fc: 61ba str r2, [r7, #24]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80045fe: 69b9 ldr r1, [r7, #24]
8004600: 69fa ldr r2, [r7, #28]
8004602: e841 2300 strex r3, r2, [r1]
8004606: 617b str r3, [r7, #20]
return(result);
8004608: 697b ldr r3, [r7, #20]
800460a: 2b00 cmp r3, #0
800460c: d1e6 bne.n 80045dc <UART_TxISR_16BIT+0x4e>
huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
huart->pTxBuffPtr += 2U;
huart->TxXferCount--;
}
}
}
800460e: e018 b.n 8004642 <UART_TxISR_16BIT+0xb4>
tmp = (uint16_t *) huart->pTxBuffPtr;
8004610: 687b ldr r3, [r7, #4]
8004612: 6cdb ldr r3, [r3, #76] ; 0x4c
8004614: 63fb str r3, [r7, #60] ; 0x3c
huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
8004616: 6bfb ldr r3, [r7, #60] ; 0x3c
8004618: 881a ldrh r2, [r3, #0]
800461a: 687b ldr r3, [r7, #4]
800461c: 681b ldr r3, [r3, #0]
800461e: f3c2 0208 ubfx r2, r2, #0, #9
8004622: b292 uxth r2, r2
8004624: 851a strh r2, [r3, #40] ; 0x28
huart->pTxBuffPtr += 2U;
8004626: 687b ldr r3, [r7, #4]
8004628: 6cdb ldr r3, [r3, #76] ; 0x4c
800462a: 1c9a adds r2, r3, #2
800462c: 687b ldr r3, [r7, #4]
800462e: 64da str r2, [r3, #76] ; 0x4c
huart->TxXferCount--;
8004630: 687b ldr r3, [r7, #4]
8004632: f8b3 3052 ldrh.w r3, [r3, #82] ; 0x52
8004636: b29b uxth r3, r3
8004638: 3b01 subs r3, #1
800463a: b29a uxth r2, r3
800463c: 687b ldr r3, [r7, #4]
800463e: f8a3 2052 strh.w r2, [r3, #82] ; 0x52
}
8004642: bf00 nop
8004644: 3744 adds r7, #68 ; 0x44
8004646: 46bd mov sp, r7
8004648: f85d 7b04 ldr.w r7, [sp], #4
800464c: 4770 bx lr
0800464e <UART_EndTransmit_IT>:
* @param huart pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
{
800464e: b580 push {r7, lr}
8004650: b088 sub sp, #32
8004652: af00 add r7, sp, #0
8004654: 6078 str r0, [r7, #4]
/* Disable the UART Transmit Complete Interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
8004656: 687b ldr r3, [r7, #4]
8004658: 681b ldr r3, [r3, #0]
800465a: 60fb str r3, [r7, #12]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
800465c: 68fb ldr r3, [r7, #12]
800465e: e853 3f00 ldrex r3, [r3]
8004662: 60bb str r3, [r7, #8]
return(result);
8004664: 68bb ldr r3, [r7, #8]
8004666: f023 0340 bic.w r3, r3, #64 ; 0x40
800466a: 61fb str r3, [r7, #28]
800466c: 687b ldr r3, [r7, #4]
800466e: 681b ldr r3, [r3, #0]
8004670: 461a mov r2, r3
8004672: 69fb ldr r3, [r7, #28]
8004674: 61bb str r3, [r7, #24]
8004676: 617a str r2, [r7, #20]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004678: 6979 ldr r1, [r7, #20]
800467a: 69ba ldr r2, [r7, #24]
800467c: e841 2300 strex r3, r2, [r1]
8004680: 613b str r3, [r7, #16]
return(result);
8004682: 693b ldr r3, [r7, #16]
8004684: 2b00 cmp r3, #0
8004686: d1e6 bne.n 8004656 <UART_EndTransmit_IT+0x8>
/* Tx process is ended, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
8004688: 687b ldr r3, [r7, #4]
800468a: 2220 movs r2, #32
800468c: 679a str r2, [r3, #120] ; 0x78
/* Cleat TxISR function pointer */
huart->TxISR = NULL;
800468e: 687b ldr r3, [r7, #4]
8004690: 2200 movs r2, #0
8004692: 669a str r2, [r3, #104] ; 0x68
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Tx complete callback*/
huart->TxCpltCallback(huart);
#else
/*Call legacy weak Tx complete callback*/
HAL_UART_TxCpltCallback(huart);
8004694: 6878 ldr r0, [r7, #4]
8004696: f7ff faf3 bl 8003c80 <HAL_UART_TxCpltCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
800469a: bf00 nop
800469c: 3720 adds r7, #32
800469e: 46bd mov sp, r7
80046a0: bd80 pop {r7, pc}
080046a2 <UART_RxISR_8BIT>:
* @brief RX interrupt handler for 7 or 8 bits data word length .
* @param huart UART handle.
* @retval None
*/
static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)
{
80046a2: b580 push {r7, lr}
80046a4: b096 sub sp, #88 ; 0x58
80046a6: af00 add r7, sp, #0
80046a8: 6078 str r0, [r7, #4]
uint16_t uhMask = huart->Mask;
80046aa: 687b ldr r3, [r7, #4]
80046ac: f8b3 305c ldrh.w r3, [r3, #92] ; 0x5c
80046b0: f8a7 3056 strh.w r3, [r7, #86] ; 0x56
uint16_t uhdata;
/* Check that a Rx process is ongoing */
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
80046b4: 687b ldr r3, [r7, #4]
80046b6: 6fdb ldr r3, [r3, #124] ; 0x7c
80046b8: 2b22 cmp r3, #34 ; 0x22
80046ba: f040 8094 bne.w 80047e6 <UART_RxISR_8BIT+0x144>
{
uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
80046be: 687b ldr r3, [r7, #4]
80046c0: 681b ldr r3, [r3, #0]
80046c2: 8c9b ldrh r3, [r3, #36] ; 0x24
80046c4: f8a7 3054 strh.w r3, [r7, #84] ; 0x54
*huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
80046c8: f8b7 3054 ldrh.w r3, [r7, #84] ; 0x54
80046cc: b2d9 uxtb r1, r3
80046ce: f8b7 3056 ldrh.w r3, [r7, #86] ; 0x56
80046d2: b2da uxtb r2, r3
80046d4: 687b ldr r3, [r7, #4]
80046d6: 6d5b ldr r3, [r3, #84] ; 0x54
80046d8: 400a ands r2, r1
80046da: b2d2 uxtb r2, r2
80046dc: 701a strb r2, [r3, #0]
huart->pRxBuffPtr++;
80046de: 687b ldr r3, [r7, #4]
80046e0: 6d5b ldr r3, [r3, #84] ; 0x54
80046e2: 1c5a adds r2, r3, #1
80046e4: 687b ldr r3, [r7, #4]
80046e6: 655a str r2, [r3, #84] ; 0x54
huart->RxXferCount--;
80046e8: 687b ldr r3, [r7, #4]
80046ea: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
80046ee: b29b uxth r3, r3
80046f0: 3b01 subs r3, #1
80046f2: b29a uxth r2, r3
80046f4: 687b ldr r3, [r7, #4]
80046f6: f8a3 205a strh.w r2, [r3, #90] ; 0x5a
if (huart->RxXferCount == 0U)
80046fa: 687b ldr r3, [r7, #4]
80046fc: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
8004700: b29b uxth r3, r3
8004702: 2b00 cmp r3, #0
8004704: d177 bne.n 80047f6 <UART_RxISR_8BIT+0x154>
{
/* Disable the UART Parity Error Interrupt and RXNE interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
8004706: 687b ldr r3, [r7, #4]
8004708: 681b ldr r3, [r3, #0]
800470a: 63bb str r3, [r7, #56] ; 0x38
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
800470c: 6bbb ldr r3, [r7, #56] ; 0x38
800470e: e853 3f00 ldrex r3, [r3]
8004712: 637b str r3, [r7, #52] ; 0x34
return(result);
8004714: 6b7b ldr r3, [r7, #52] ; 0x34
8004716: f423 7390 bic.w r3, r3, #288 ; 0x120
800471a: 653b str r3, [r7, #80] ; 0x50
800471c: 687b ldr r3, [r7, #4]
800471e: 681b ldr r3, [r3, #0]
8004720: 461a mov r2, r3
8004722: 6d3b ldr r3, [r7, #80] ; 0x50
8004724: 647b str r3, [r7, #68] ; 0x44
8004726: 643a str r2, [r7, #64] ; 0x40
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004728: 6c39 ldr r1, [r7, #64] ; 0x40
800472a: 6c7a ldr r2, [r7, #68] ; 0x44
800472c: e841 2300 strex r3, r2, [r1]
8004730: 63fb str r3, [r7, #60] ; 0x3c
return(result);
8004732: 6bfb ldr r3, [r7, #60] ; 0x3c
8004734: 2b00 cmp r3, #0
8004736: d1e6 bne.n 8004706 <UART_RxISR_8BIT+0x64>
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8004738: 687b ldr r3, [r7, #4]
800473a: 681b ldr r3, [r3, #0]
800473c: 3308 adds r3, #8
800473e: 627b str r3, [r7, #36] ; 0x24
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004740: 6a7b ldr r3, [r7, #36] ; 0x24
8004742: e853 3f00 ldrex r3, [r3]
8004746: 623b str r3, [r7, #32]
return(result);
8004748: 6a3b ldr r3, [r7, #32]
800474a: f023 0301 bic.w r3, r3, #1
800474e: 64fb str r3, [r7, #76] ; 0x4c
8004750: 687b ldr r3, [r7, #4]
8004752: 681b ldr r3, [r3, #0]
8004754: 3308 adds r3, #8
8004756: 6cfa ldr r2, [r7, #76] ; 0x4c
8004758: 633a str r2, [r7, #48] ; 0x30
800475a: 62fb str r3, [r7, #44] ; 0x2c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
800475c: 6af9 ldr r1, [r7, #44] ; 0x2c
800475e: 6b3a ldr r2, [r7, #48] ; 0x30
8004760: e841 2300 strex r3, r2, [r1]
8004764: 62bb str r3, [r7, #40] ; 0x28
return(result);
8004766: 6abb ldr r3, [r7, #40] ; 0x28
8004768: 2b00 cmp r3, #0
800476a: d1e5 bne.n 8004738 <UART_RxISR_8BIT+0x96>
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
800476c: 687b ldr r3, [r7, #4]
800476e: 2220 movs r2, #32
8004770: 67da str r2, [r3, #124] ; 0x7c
/* Clear RxISR function pointer */
huart->RxISR = NULL;
8004772: 687b ldr r3, [r7, #4]
8004774: 2200 movs r2, #0
8004776: 665a str r2, [r3, #100] ; 0x64
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8004778: 687b ldr r3, [r7, #4]
800477a: 6e1b ldr r3, [r3, #96] ; 0x60
800477c: 2b01 cmp r3, #1
800477e: d12e bne.n 80047de <UART_RxISR_8BIT+0x13c>
{
/* Set reception type to Standard */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8004780: 687b ldr r3, [r7, #4]
8004782: 2200 movs r2, #0
8004784: 661a str r2, [r3, #96] ; 0x60
/* Disable IDLE interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8004786: 687b ldr r3, [r7, #4]
8004788: 681b ldr r3, [r3, #0]
800478a: 613b str r3, [r7, #16]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
800478c: 693b ldr r3, [r7, #16]
800478e: e853 3f00 ldrex r3, [r3]
8004792: 60fb str r3, [r7, #12]
return(result);
8004794: 68fb ldr r3, [r7, #12]
8004796: f023 0310 bic.w r3, r3, #16
800479a: 64bb str r3, [r7, #72] ; 0x48
800479c: 687b ldr r3, [r7, #4]
800479e: 681b ldr r3, [r3, #0]
80047a0: 461a mov r2, r3
80047a2: 6cbb ldr r3, [r7, #72] ; 0x48
80047a4: 61fb str r3, [r7, #28]
80047a6: 61ba str r2, [r7, #24]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80047a8: 69b9 ldr r1, [r7, #24]
80047aa: 69fa ldr r2, [r7, #28]
80047ac: e841 2300 strex r3, r2, [r1]
80047b0: 617b str r3, [r7, #20]
return(result);
80047b2: 697b ldr r3, [r7, #20]
80047b4: 2b00 cmp r3, #0
80047b6: d1e6 bne.n 8004786 <UART_RxISR_8BIT+0xe4>
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
80047b8: 687b ldr r3, [r7, #4]
80047ba: 681b ldr r3, [r3, #0]
80047bc: 69db ldr r3, [r3, #28]
80047be: f003 0310 and.w r3, r3, #16
80047c2: 2b10 cmp r3, #16
80047c4: d103 bne.n 80047ce <UART_RxISR_8BIT+0x12c>
{
/* Clear IDLE Flag */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
80047c6: 687b ldr r3, [r7, #4]
80047c8: 681b ldr r3, [r3, #0]
80047ca: 2210 movs r2, #16
80047cc: 621a str r2, [r3, #32]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
80047ce: 687b ldr r3, [r7, #4]
80047d0: f8b3 3058 ldrh.w r3, [r3, #88] ; 0x58
80047d4: 4619 mov r1, r3
80047d6: 6878 ldr r0, [r7, #4]
80047d8: f7ff fa66 bl 8003ca8 <HAL_UARTEx_RxEventCallback>
else
{
/* Clear RXNE interrupt flag */
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
}
}
80047dc: e00b b.n 80047f6 <UART_RxISR_8BIT+0x154>
HAL_UART_RxCpltCallback(huart);
80047de: 6878 ldr r0, [r7, #4]
80047e0: f7fb fd5c bl 800029c <HAL_UART_RxCpltCallback>
}
80047e4: e007 b.n 80047f6 <UART_RxISR_8BIT+0x154>
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
80047e6: 687b ldr r3, [r7, #4]
80047e8: 681b ldr r3, [r3, #0]
80047ea: 699a ldr r2, [r3, #24]
80047ec: 687b ldr r3, [r7, #4]
80047ee: 681b ldr r3, [r3, #0]
80047f0: f042 0208 orr.w r2, r2, #8
80047f4: 619a str r2, [r3, #24]
}
80047f6: bf00 nop
80047f8: 3758 adds r7, #88 ; 0x58
80047fa: 46bd mov sp, r7
80047fc: bd80 pop {r7, pc}
080047fe <UART_RxISR_16BIT>:
* interruptions have been enabled by HAL_UART_Receive_IT()
* @param huart UART handle.
* @retval None
*/
static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)
{
80047fe: b580 push {r7, lr}
8004800: b096 sub sp, #88 ; 0x58
8004802: af00 add r7, sp, #0
8004804: 6078 str r0, [r7, #4]
uint16_t *tmp;
uint16_t uhMask = huart->Mask;
8004806: 687b ldr r3, [r7, #4]
8004808: f8b3 305c ldrh.w r3, [r3, #92] ; 0x5c
800480c: f8a7 3056 strh.w r3, [r7, #86] ; 0x56
uint16_t uhdata;
/* Check that a Rx process is ongoing */
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
8004810: 687b ldr r3, [r7, #4]
8004812: 6fdb ldr r3, [r3, #124] ; 0x7c
8004814: 2b22 cmp r3, #34 ; 0x22
8004816: f040 8094 bne.w 8004942 <UART_RxISR_16BIT+0x144>
{
uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
800481a: 687b ldr r3, [r7, #4]
800481c: 681b ldr r3, [r3, #0]
800481e: 8c9b ldrh r3, [r3, #36] ; 0x24
8004820: f8a7 3054 strh.w r3, [r7, #84] ; 0x54
tmp = (uint16_t *) huart->pRxBuffPtr ;
8004824: 687b ldr r3, [r7, #4]
8004826: 6d5b ldr r3, [r3, #84] ; 0x54
8004828: 653b str r3, [r7, #80] ; 0x50
*tmp = (uint16_t)(uhdata & uhMask);
800482a: f8b7 2054 ldrh.w r2, [r7, #84] ; 0x54
800482e: f8b7 3056 ldrh.w r3, [r7, #86] ; 0x56
8004832: 4013 ands r3, r2
8004834: b29a uxth r2, r3
8004836: 6d3b ldr r3, [r7, #80] ; 0x50
8004838: 801a strh r2, [r3, #0]
huart->pRxBuffPtr += 2U;
800483a: 687b ldr r3, [r7, #4]
800483c: 6d5b ldr r3, [r3, #84] ; 0x54
800483e: 1c9a adds r2, r3, #2
8004840: 687b ldr r3, [r7, #4]
8004842: 655a str r2, [r3, #84] ; 0x54
huart->RxXferCount--;
8004844: 687b ldr r3, [r7, #4]
8004846: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
800484a: b29b uxth r3, r3
800484c: 3b01 subs r3, #1
800484e: b29a uxth r2, r3
8004850: 687b ldr r3, [r7, #4]
8004852: f8a3 205a strh.w r2, [r3, #90] ; 0x5a
if (huart->RxXferCount == 0U)
8004856: 687b ldr r3, [r7, #4]
8004858: f8b3 305a ldrh.w r3, [r3, #90] ; 0x5a
800485c: b29b uxth r3, r3
800485e: 2b00 cmp r3, #0
8004860: d177 bne.n 8004952 <UART_RxISR_16BIT+0x154>
{
/* Disable the UART Parity Error Interrupt and RXNE interrupt*/
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
8004862: 687b ldr r3, [r7, #4]
8004864: 681b ldr r3, [r3, #0]
8004866: 637b str r3, [r7, #52] ; 0x34
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004868: 6b7b ldr r3, [r7, #52] ; 0x34
800486a: e853 3f00 ldrex r3, [r3]
800486e: 633b str r3, [r7, #48] ; 0x30
return(result);
8004870: 6b3b ldr r3, [r7, #48] ; 0x30
8004872: f423 7390 bic.w r3, r3, #288 ; 0x120
8004876: 64fb str r3, [r7, #76] ; 0x4c
8004878: 687b ldr r3, [r7, #4]
800487a: 681b ldr r3, [r3, #0]
800487c: 461a mov r2, r3
800487e: 6cfb ldr r3, [r7, #76] ; 0x4c
8004880: 643b str r3, [r7, #64] ; 0x40
8004882: 63fa str r2, [r7, #60] ; 0x3c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004884: 6bf9 ldr r1, [r7, #60] ; 0x3c
8004886: 6c3a ldr r2, [r7, #64] ; 0x40
8004888: e841 2300 strex r3, r2, [r1]
800488c: 63bb str r3, [r7, #56] ; 0x38
return(result);
800488e: 6bbb ldr r3, [r7, #56] ; 0x38
8004890: 2b00 cmp r3, #0
8004892: d1e6 bne.n 8004862 <UART_RxISR_16BIT+0x64>
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8004894: 687b ldr r3, [r7, #4]
8004896: 681b ldr r3, [r3, #0]
8004898: 3308 adds r3, #8
800489a: 623b str r3, [r7, #32]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
800489c: 6a3b ldr r3, [r7, #32]
800489e: e853 3f00 ldrex r3, [r3]
80048a2: 61fb str r3, [r7, #28]
return(result);
80048a4: 69fb ldr r3, [r7, #28]
80048a6: f023 0301 bic.w r3, r3, #1
80048aa: 64bb str r3, [r7, #72] ; 0x48
80048ac: 687b ldr r3, [r7, #4]
80048ae: 681b ldr r3, [r3, #0]
80048b0: 3308 adds r3, #8
80048b2: 6cba ldr r2, [r7, #72] ; 0x48
80048b4: 62fa str r2, [r7, #44] ; 0x2c
80048b6: 62bb str r3, [r7, #40] ; 0x28
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80048b8: 6ab9 ldr r1, [r7, #40] ; 0x28
80048ba: 6afa ldr r2, [r7, #44] ; 0x2c
80048bc: e841 2300 strex r3, r2, [r1]
80048c0: 627b str r3, [r7, #36] ; 0x24
return(result);
80048c2: 6a7b ldr r3, [r7, #36] ; 0x24
80048c4: 2b00 cmp r3, #0
80048c6: d1e5 bne.n 8004894 <UART_RxISR_16BIT+0x96>
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
80048c8: 687b ldr r3, [r7, #4]
80048ca: 2220 movs r2, #32
80048cc: 67da str r2, [r3, #124] ; 0x7c
/* Clear RxISR function pointer */
huart->RxISR = NULL;
80048ce: 687b ldr r3, [r7, #4]
80048d0: 2200 movs r2, #0
80048d2: 665a str r2, [r3, #100] ; 0x64
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
80048d4: 687b ldr r3, [r7, #4]
80048d6: 6e1b ldr r3, [r3, #96] ; 0x60
80048d8: 2b01 cmp r3, #1
80048da: d12e bne.n 800493a <UART_RxISR_16BIT+0x13c>
{
/* Set reception type to Standard */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
80048dc: 687b ldr r3, [r7, #4]
80048de: 2200 movs r2, #0
80048e0: 661a str r2, [r3, #96] ; 0x60
/* Disable IDLE interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
80048e2: 687b ldr r3, [r7, #4]
80048e4: 681b ldr r3, [r3, #0]
80048e6: 60fb str r3, [r7, #12]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80048e8: 68fb ldr r3, [r7, #12]
80048ea: e853 3f00 ldrex r3, [r3]
80048ee: 60bb str r3, [r7, #8]
return(result);
80048f0: 68bb ldr r3, [r7, #8]
80048f2: f023 0310 bic.w r3, r3, #16
80048f6: 647b str r3, [r7, #68] ; 0x44
80048f8: 687b ldr r3, [r7, #4]
80048fa: 681b ldr r3, [r3, #0]
80048fc: 461a mov r2, r3
80048fe: 6c7b ldr r3, [r7, #68] ; 0x44
8004900: 61bb str r3, [r7, #24]
8004902: 617a str r2, [r7, #20]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004904: 6979 ldr r1, [r7, #20]
8004906: 69ba ldr r2, [r7, #24]
8004908: e841 2300 strex r3, r2, [r1]
800490c: 613b str r3, [r7, #16]
return(result);
800490e: 693b ldr r3, [r7, #16]
8004910: 2b00 cmp r3, #0
8004912: d1e6 bne.n 80048e2 <UART_RxISR_16BIT+0xe4>
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
8004914: 687b ldr r3, [r7, #4]
8004916: 681b ldr r3, [r3, #0]
8004918: 69db ldr r3, [r3, #28]
800491a: f003 0310 and.w r3, r3, #16
800491e: 2b10 cmp r3, #16
8004920: d103 bne.n 800492a <UART_RxISR_16BIT+0x12c>
{
/* Clear IDLE Flag */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
8004922: 687b ldr r3, [r7, #4]
8004924: 681b ldr r3, [r3, #0]
8004926: 2210 movs r2, #16
8004928: 621a str r2, [r3, #32]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
800492a: 687b ldr r3, [r7, #4]
800492c: f8b3 3058 ldrh.w r3, [r3, #88] ; 0x58
8004930: 4619 mov r1, r3
8004932: 6878 ldr r0, [r7, #4]
8004934: f7ff f9b8 bl 8003ca8 <HAL_UARTEx_RxEventCallback>
else
{
/* Clear RXNE interrupt flag */
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
}
}
8004938: e00b b.n 8004952 <UART_RxISR_16BIT+0x154>
HAL_UART_RxCpltCallback(huart);
800493a: 6878 ldr r0, [r7, #4]
800493c: f7fb fcae bl 800029c <HAL_UART_RxCpltCallback>
}
8004940: e007 b.n 8004952 <UART_RxISR_16BIT+0x154>
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
8004942: 687b ldr r3, [r7, #4]
8004944: 681b ldr r3, [r3, #0]
8004946: 699a ldr r2, [r3, #24]
8004948: 687b ldr r3, [r7, #4]
800494a: 681b ldr r3, [r3, #0]
800494c: f042 0208 orr.w r2, r2, #8
8004950: 619a str r2, [r3, #24]
}
8004952: bf00 nop
8004954: 3758 adds r7, #88 ; 0x58
8004956: 46bd mov sp, r7
8004958: bd80 pop {r7, pc}
0800495a <HAL_UARTEx_WakeupCallback>:
* @brief UART wakeup from Stop mode callback.
* @param huart UART handle.
* @retval None
*/
__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
{
800495a: b480 push {r7}
800495c: b083 sub sp, #12
800495e: af00 add r7, sp, #0
8004960: 6078 str r0, [r7, #4]
UNUSED(huart);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UARTEx_WakeupCallback can be implemented in the user file.
*/
}
8004962: bf00 nop
8004964: 370c adds r7, #12
8004966: 46bd mov sp, r7
8004968: f85d 7b04 ldr.w r7, [sp], #4
800496c: 4770 bx lr
...
08004970 <__libc_init_array>:
8004970: b570 push {r4, r5, r6, lr}
8004972: 4d0d ldr r5, [pc, #52] ; (80049a8 <__libc_init_array+0x38>)
8004974: 4c0d ldr r4, [pc, #52] ; (80049ac <__libc_init_array+0x3c>)
8004976: 1b64 subs r4, r4, r5
8004978: 10a4 asrs r4, r4, #2
800497a: 2600 movs r6, #0
800497c: 42a6 cmp r6, r4
800497e: d109 bne.n 8004994 <__libc_init_array+0x24>
8004980: 4d0b ldr r5, [pc, #44] ; (80049b0 <__libc_init_array+0x40>)
8004982: 4c0c ldr r4, [pc, #48] ; (80049b4 <__libc_init_array+0x44>)
8004984: f000 f82e bl 80049e4 <_init>
8004988: 1b64 subs r4, r4, r5
800498a: 10a4 asrs r4, r4, #2
800498c: 2600 movs r6, #0
800498e: 42a6 cmp r6, r4
8004990: d105 bne.n 800499e <__libc_init_array+0x2e>
8004992: bd70 pop {r4, r5, r6, pc}
8004994: f855 3b04 ldr.w r3, [r5], #4
8004998: 4798 blx r3
800499a: 3601 adds r6, #1
800499c: e7ee b.n 800497c <__libc_init_array+0xc>
800499e: f855 3b04 ldr.w r3, [r5], #4
80049a2: 4798 blx r3
80049a4: 3601 adds r6, #1
80049a6: e7f2 b.n 800498e <__libc_init_array+0x1e>
80049a8: 08004a40 .word 0x08004a40
80049ac: 08004a40 .word 0x08004a40
80049b0: 08004a40 .word 0x08004a40
80049b4: 08004a44 .word 0x08004a44
080049b8 <memcpy>:
80049b8: 440a add r2, r1
80049ba: 4291 cmp r1, r2
80049bc: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff
80049c0: d100 bne.n 80049c4 <memcpy+0xc>
80049c2: 4770 bx lr
80049c4: b510 push {r4, lr}
80049c6: f811 4b01 ldrb.w r4, [r1], #1
80049ca: f803 4f01 strb.w r4, [r3, #1]!
80049ce: 4291 cmp r1, r2
80049d0: d1f9 bne.n 80049c6 <memcpy+0xe>
80049d2: bd10 pop {r4, pc}
080049d4 <memset>:
80049d4: 4402 add r2, r0
80049d6: 4603 mov r3, r0
80049d8: 4293 cmp r3, r2
80049da: d100 bne.n 80049de <memset+0xa>
80049dc: 4770 bx lr
80049de: f803 1b01 strb.w r1, [r3], #1
80049e2: e7f9 b.n 80049d8 <memset+0x4>
080049e4 <_init>:
80049e4: b5f8 push {r3, r4, r5, r6, r7, lr}
80049e6: bf00 nop
80049e8: bcf8 pop {r3, r4, r5, r6, r7}
80049ea: bc08 pop {r3}
80049ec: 469e mov lr, r3
80049ee: 4770 bx lr
080049f0 <_fini>:
80049f0: b5f8 push {r3, r4, r5, r6, r7, lr}
80049f2: bf00 nop
80049f4: bcf8 pop {r3, r4, r5, r6, r7}
80049f6: bc08 pop {r3}
80049f8: 469e mov lr, r3
80049fa: 4770 bx lr
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