finishing schematic, starting to try layout position

This commit is contained in:
2025-02-16 21:23:55 +01:00
parent 6c67a2a88b
commit f3088f4504
13 changed files with 30579 additions and 23408 deletions

View File

@ -410,7 +410,7 @@
"missing_input_pin": "warning",
"missing_power_pin": "error",
"missing_unit": "warning",
"multiple_net_names": "warning",
"multiple_net_names": "ignore",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
@ -452,6 +452,91 @@
"via_diameter": 0.6,
"via_drill": 0.3,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "LTDC",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.2,
"via_diameter": 0.6,
"via_drill": 0.3,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "LVDS",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.2,
"via_diameter": 0.6,
"via_drill": 0.3,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "MDI",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.2,
"via_diameter": 0.6,
"via_drill": 0.3,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "RMII",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.2,
"via_diameter": 0.6,
"via_drill": 0.3,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "SDRAM",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.2,
"via_diameter": 0.6,
"via_drill": 0.3,
"wire_width": 6
}
],
"meta": {
@ -459,6 +544,33 @@
},
"net_colors": null,
"netclass_assignments": {
"/Display/B0": "LTDC",
"/Display/B1": "LTDC",
"/Display/B2": "LTDC",
"/Display/B3": "LTDC",
"/Display/B4": "LTDC",
"/Display/B5": "LTDC",
"/Display/B6": "LTDC",
"/Display/B7": "LTDC",
"/Display/CLK": "LTDC",
"/Display/DE": "LTDC",
"/Display/G0": "LTDC",
"/Display/G1": "LTDC",
"/Display/G2": "LTDC",
"/Display/G3": "LTDC",
"/Display/G4": "LTDC",
"/Display/G5": "LTDC",
"/Display/G6": "LTDC",
"/Display/G7": "LTDC",
"/Display/HSYNC": "LTDC",
"/Display/R0": "LTDC",
"/Display/R1": "LTDC",
"/Display/R2": "LTDC",
"/Display/R3": "LTDC",
"/Display/R4": "LTDC",
"/Display/R5": "LTDC",
"/Display/R6": "LTDC",
"/Display/R7": "LTDC",
"/Display/RXCLKIN+": "LVDS",
"/Display/RXCLKIN-": "LVDS",
"/Display/RXIN0+": "LVDS",
@ -469,6 +581,7 @@
"/Display/RXIN2-": "LVDS",
"/Display/RXIN3+": "LVDS",
"/Display/RXIN3-": "LVDS",
"/Display/VSYNC": "LTDC",
"/Ethernet/RMII_CRS_DV": "RMII",
"/Ethernet/RMII_MDC": "RMII",
"/Ethernet/RMII_MDIO": "RMII",
@ -477,7 +590,50 @@
"/Ethernet/RMII_RXD1": "RMII",
"/Ethernet/RMII_TXD0": "RMII",
"/Ethernet/RMII_TXD1": "RMII",
"/Ethernet/RMII_TX_EN": "RMII"
"/Ethernet/RMII_TX_EN": "RMII",
"/Ethernet/RXN": "MDI",
"/Ethernet/RXP": "MDI",
"/Ethernet/TXN": "MDI",
"/Ethernet/TXP": "MDI",
"/SDRAM/A0": "SDRAM",
"/SDRAM/A1": "SDRAM",
"/SDRAM/A10": "SDRAM",
"/SDRAM/A11": "SDRAM",
"/SDRAM/A12": "SDRAM",
"/SDRAM/A2": "SDRAM",
"/SDRAM/A3": "SDRAM",
"/SDRAM/A4": "SDRAM",
"/SDRAM/A5": "SDRAM",
"/SDRAM/A6": "SDRAM",
"/SDRAM/A7": "SDRAM",
"/SDRAM/A8": "SDRAM",
"/SDRAM/A9": "SDRAM",
"/SDRAM/BA0": "SDRAM",
"/SDRAM/BA1": "SDRAM",
"/SDRAM/D0": "SDRAM",
"/SDRAM/D1": "SDRAM",
"/SDRAM/D10": "SDRAM",
"/SDRAM/D11": "SDRAM",
"/SDRAM/D12": "SDRAM",
"/SDRAM/D13": "SDRAM",
"/SDRAM/D14": "SDRAM",
"/SDRAM/D15": "SDRAM",
"/SDRAM/D2": "SDRAM",
"/SDRAM/D3": "SDRAM",
"/SDRAM/D4": "SDRAM",
"/SDRAM/D5": "SDRAM",
"/SDRAM/D6": "SDRAM",
"/SDRAM/D7": "SDRAM",
"/SDRAM/D8": "SDRAM",
"/SDRAM/D9": "SDRAM",
"/SDRAM/NBL0": "SDRAM",
"/SDRAM/NBL1": "SDRAM",
"/SDRAM/SDCKE0": "SDRAM",
"/SDRAM/SDCLK": "SDRAM",
"/SDRAM/SDNCAS": "SDRAM",
"/SDRAM/SDNE0": "SDRAM",
"/SDRAM/SDNRAS": "SDRAM",
"/SDRAM/SDNWE": "SDRAM"
},
"netclass_patterns": []
},