create new branch for 23 charger testing
This commit is contained in:
@ -400,15 +400,9 @@
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* @}
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*/
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/* Private macros ------------------------------------------------------------*/
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/** @addtogroup I2C_Private_Macro
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* @{
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*/
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/* Private macro -------------------------------------------------------------*/
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/* Macro to get remaining data to transfer on DMA side */
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#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) __HAL_DMA_GET_COUNTER(__HANDLE__)
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/**
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* @}
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*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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@ -424,7 +418,6 @@ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
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static void I2C_DMAError(DMA_HandleTypeDef *hdma);
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static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
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/* Private functions to handle IT transfer */
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static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
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static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c);
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@ -608,12 +601,7 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
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/* Configure I2Cx: Addressing Master mode */
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if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
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{
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SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
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}
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else
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{
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/* Clear the I2C ADD10 bit */
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CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
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hi2c->Instance->CR2 = (I2C_CR2_ADD10);
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}
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/* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
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hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
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@ -1120,7 +1108,6 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
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uint16_t Size, uint32_t Timeout)
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{
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uint32_t tickstart;
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uint32_t xfermode;
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if (hi2c->State == HAL_I2C_STATE_READY)
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{
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@ -1144,39 +1131,18 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
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hi2c->XferCount = Size;
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hi2c->XferISR = NULL;
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/* Send Slave Address */
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/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
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if (hi2c->XferCount > MAX_NBYTE_SIZE)
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{
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hi2c->XferSize = MAX_NBYTE_SIZE;
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xfermode = I2C_RELOAD_MODE;
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}
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else
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{
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hi2c->XferSize = hi2c->XferCount;
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xfermode = I2C_AUTOEND_MODE;
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}
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if (hi2c->XferSize > 0U)
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{
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/* Preload TX register */
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/* Write data to TXDR */
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hi2c->Instance->TXDR = *hi2c->pBuffPtr;
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/* Increment Buffer pointer */
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hi2c->pBuffPtr++;
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hi2c->XferCount--;
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hi2c->XferSize--;
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/* Send Slave Address */
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/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
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I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), xfermode,
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I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
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I2C_GENERATE_START_WRITE);
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}
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else
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{
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/* Send Slave Address */
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/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
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I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode,
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hi2c->XferSize = hi2c->XferCount;
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I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
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I2C_GENERATE_START_WRITE);
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}
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@ -1379,8 +1345,6 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
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uint32_t Timeout)
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{
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uint32_t tickstart;
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uint16_t tmpXferCount;
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HAL_StatusTypeDef error;
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if (hi2c->State == HAL_I2C_STATE_READY)
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{
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@ -1474,48 +1438,31 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
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}
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/* Wait until AF flag is set */
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error = I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart);
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if (error != HAL_OK)
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if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
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{
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/* Check that I2C transfer finished */
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/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
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/* Mean XferCount == 0 */
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tmpXferCount = hi2c->XferCount;
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if ((hi2c->ErrorCode == HAL_I2C_ERROR_AF) && (tmpXferCount == 0U))
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{
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/* Reset ErrorCode to NONE */
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hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
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}
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else
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{
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/* Disable Address Acknowledge */
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hi2c->Instance->CR2 |= I2C_CR2_NACK;
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return HAL_ERROR;
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}
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/* Disable Address Acknowledge */
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hi2c->Instance->CR2 |= I2C_CR2_NACK;
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return HAL_ERROR;
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}
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else
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/* Flush TX register */
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I2C_Flush_TXDR(hi2c);
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/* Clear AF flag */
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__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
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/* Wait until STOP flag is set */
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if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
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{
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/* Flush TX register */
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I2C_Flush_TXDR(hi2c);
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/* Disable Address Acknowledge */
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hi2c->Instance->CR2 |= I2C_CR2_NACK;
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/* Clear AF flag */
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__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
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/* Wait until STOP flag is set */
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if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
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{
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/* Disable Address Acknowledge */
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hi2c->Instance->CR2 |= I2C_CR2_NACK;
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return HAL_ERROR;
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}
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/* Clear STOP flag */
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__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
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return HAL_ERROR;
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}
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/* Clear STOP flag */
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__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
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/* Wait until BUSY flag is reset */
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if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
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{
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@ -1718,26 +1665,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D
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/* Send Slave Address */
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/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
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if (hi2c->XferSize > 0U)
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{
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/* Preload TX register */
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/* Write data to TXDR */
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hi2c->Instance->TXDR = *hi2c->pBuffPtr;
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/* Increment Buffer pointer */
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hi2c->pBuffPtr++;
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hi2c->XferCount--;
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hi2c->XferSize--;
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I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), xfermode,
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I2C_GENERATE_START_WRITE);
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}
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else
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{
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I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode,
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I2C_GENERATE_START_WRITE);
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}
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I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
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/* Process Unlocked */
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__HAL_UNLOCK(hi2c);
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@ -1960,7 +1888,6 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
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{
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uint32_t xfermode;
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HAL_StatusTypeDef dmaxferstatus;
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uint32_t sizetoxfer = 0U;
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if (hi2c->State == HAL_I2C_STATE_READY)
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{
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@ -1993,20 +1920,6 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
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xfermode = I2C_AUTOEND_MODE;
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}
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if (hi2c->XferSize > 0U)
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{
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/* Preload TX register */
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/* Write data to TXDR */
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hi2c->Instance->TXDR = *hi2c->pBuffPtr;
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/* Increment Buffer pointer */
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hi2c->pBuffPtr++;
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sizetoxfer = hi2c->XferSize;
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hi2c->XferCount--;
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hi2c->XferSize--;
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}
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if (hi2c->XferSize > 0U)
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{
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if (hi2c->hdmatx != NULL)
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@ -2022,8 +1935,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
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hi2c->hdmatx->XferAbortCallback = NULL;
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/* Enable the DMA stream or channel depends on Instance */
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dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr,
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(uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
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dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
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hi2c->XferSize);
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}
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else
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{
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@ -2044,8 +1957,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
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{
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/* Send Slave Address */
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/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
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I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U),
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xfermode, I2C_GENERATE_START_WRITE);
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I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
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/* Update XferCount value */
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hi2c->XferCount -= hi2c->XferSize;
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@ -2084,7 +1996,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
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/* Send Slave Address */
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/* Set NBYTES to write and generate START condition */
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I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, I2C_AUTOEND_MODE,
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I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
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I2C_GENERATE_START_WRITE);
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/* Process Unlocked */
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@ -2240,11 +2152,11 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D
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/* Note : The I2C interrupts must be enabled after unlocking current process
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to avoid the risk of I2C interrupt handle execution before current
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process unlock */
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/* Enable ERR, TC, STOP, NACK, RXI interrupt */
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/* Enable ERR, TC, STOP, NACK, TXI interrupt */
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/* possible to enable all of these */
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/* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
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I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
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I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
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I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
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}
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return HAL_OK;
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@ -2494,7 +2406,6 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD
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return HAL_BUSY;
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}
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}
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/**
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* @brief Write an amount of data in blocking mode to a specific memory address
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* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
||||
@ -2809,7 +2720,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
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hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
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/* Prepare transfer parameters */
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hi2c->XferSize = 0U;
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hi2c->pBuffPtr = pData;
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hi2c->XferCount = Size;
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hi2c->XferOptions = I2C_NO_OPTION_FRAME;
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@ -2931,11 +2841,11 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
|
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to avoid the risk of I2C interrupt handle execution before current
|
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process unlock */
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|
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/* Enable ERR, TC, STOP, NACK, TXI interrupt */
|
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/* Enable ERR, TC, STOP, NACK, RXI interrupt */
|
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/* possible to enable all of these */
|
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/* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
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I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
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I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
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I2C_Enable_IRQ(hi2c, (I2C_XFER_TX_IT | I2C_XFER_RX_IT));
|
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|
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return HAL_OK;
|
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}
|
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@ -2944,7 +2854,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
|
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return HAL_BUSY;
|
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}
|
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}
|
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|
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/**
|
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* @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
|
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* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
||||
@ -3341,6 +3250,22 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
|
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__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
|
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}
|
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|
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/* Check if the maximum allowed number of trials has been reached */
|
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if (I2C_Trials == Trials)
|
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{
|
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/* Generate Stop */
|
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hi2c->Instance->CR2 |= I2C_CR2_STOP;
|
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|
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/* Wait until STOPF flag is reset */
|
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if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Clear STOP Flag */
|
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__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
|
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}
|
||||
|
||||
/* Increment Trials */
|
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I2C_Trials++;
|
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} while (I2C_Trials < Trials);
|
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@ -3379,7 +3304,6 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16
|
||||
{
|
||||
uint32_t xfermode;
|
||||
uint32_t xferrequest = I2C_GENERATE_START_WRITE;
|
||||
uint32_t sizetoxfer = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
|
||||
@ -3411,21 +3335,6 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16
|
||||
xfermode = hi2c->XferOptions;
|
||||
}
|
||||
|
||||
if ((hi2c->XferSize > 0U) && ((XferOptions == I2C_FIRST_FRAME) || \
|
||||
(XferOptions == I2C_FIRST_AND_LAST_FRAME)))
|
||||
{
|
||||
/* Preload TX register */
|
||||
/* Write data to TXDR */
|
||||
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
|
||||
|
||||
/* Increment Buffer pointer */
|
||||
hi2c->pBuffPtr++;
|
||||
|
||||
sizetoxfer = hi2c->XferSize;
|
||||
hi2c->XferCount--;
|
||||
hi2c->XferSize--;
|
||||
}
|
||||
|
||||
/* If transfer direction not change and there is no request to start another frame,
|
||||
do not generate Restart Condition */
|
||||
/* Mean Previous state is same as current state */
|
||||
@ -3447,14 +3356,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16
|
||||
}
|
||||
|
||||
/* Send Slave Address and set NBYTES to write */
|
||||
if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME))
|
||||
{
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest);
|
||||
}
|
||||
else
|
||||
{
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
|
||||
}
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
@ -3494,7 +3396,6 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1
|
||||
uint32_t xfermode;
|
||||
uint32_t xferrequest = I2C_GENERATE_START_WRITE;
|
||||
HAL_StatusTypeDef dmaxferstatus;
|
||||
uint32_t sizetoxfer = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
|
||||
@ -3526,21 +3427,6 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1
|
||||
xfermode = hi2c->XferOptions;
|
||||
}
|
||||
|
||||
if ((hi2c->XferSize > 0U) && ((XferOptions == I2C_FIRST_FRAME) || \
|
||||
(XferOptions == I2C_FIRST_AND_LAST_FRAME)))
|
||||
{
|
||||
/* Preload TX register */
|
||||
/* Write data to TXDR */
|
||||
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
|
||||
|
||||
/* Increment Buffer pointer */
|
||||
hi2c->pBuffPtr++;
|
||||
|
||||
sizetoxfer = hi2c->XferSize;
|
||||
hi2c->XferCount--;
|
||||
hi2c->XferSize--;
|
||||
}
|
||||
|
||||
/* If transfer direction not change and there is no request to start another frame,
|
||||
do not generate Restart Condition */
|
||||
/* Mean Previous state is same as current state */
|
||||
@ -3576,8 +3462,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1
|
||||
hi2c->hdmatx->XferAbortCallback = NULL;
|
||||
|
||||
/* Enable the DMA stream or channel depends on Instance */
|
||||
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr,
|
||||
(uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
|
||||
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
|
||||
hi2c->XferSize);
|
||||
}
|
||||
else
|
||||
{
|
||||
@ -3597,14 +3483,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1
|
||||
if (dmaxferstatus == HAL_OK)
|
||||
{
|
||||
/* Send Slave Address and set NBYTES to write */
|
||||
if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME))
|
||||
{
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest);
|
||||
}
|
||||
else
|
||||
{
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
|
||||
}
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
|
||||
|
||||
/* Update XferCount value */
|
||||
hi2c->XferCount -= hi2c->XferSize;
|
||||
@ -3643,14 +3522,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1
|
||||
|
||||
/* Send Slave Address */
|
||||
/* Set NBYTES to write and generate START condition */
|
||||
if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME))
|
||||
{
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest);
|
||||
}
|
||||
else
|
||||
{
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
|
||||
}
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
|
||||
I2C_GENERATE_START_WRITE);
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
@ -3913,11 +3786,11 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16
|
||||
/* Note : The I2C interrupts must be enabled after unlocking current process
|
||||
to avoid the risk of I2C interrupt handle execution before current
|
||||
process unlock */
|
||||
/* Enable ERR, TC, STOP, NACK, RXI interrupt */
|
||||
/* Enable ERR, TC, STOP, NACK, TXI interrupt */
|
||||
/* possible to enable all of these */
|
||||
/* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
|
||||
I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
|
||||
I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
|
||||
I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
@ -4621,7 +4494,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA
|
||||
* the configuration information for the specified I2C.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /* Derogation MISRAC2012-Rule-8.13 */
|
||||
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
|
||||
{
|
||||
/* Get current IT Flags and IT sources value */
|
||||
uint32_t itflags = READ_REG(hi2c->Instance->ISR);
|
||||
@ -4874,7 +4747,7 @@ __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
|
||||
* the configuration information for the specified I2C.
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c)
|
||||
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
|
||||
{
|
||||
/* Return I2C handle state */
|
||||
return hi2c->State;
|
||||
@ -4886,7 +4759,7 @@ HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c)
|
||||
* the configuration information for I2C module
|
||||
* @retval HAL mode
|
||||
*/
|
||||
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c)
|
||||
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
|
||||
{
|
||||
return hi2c->Mode;
|
||||
}
|
||||
@ -4897,7 +4770,7 @@ HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c)
|
||||
* the configuration information for the specified I2C.
|
||||
* @retval I2C Error Code
|
||||
*/
|
||||
uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c)
|
||||
uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
|
||||
{
|
||||
return hi2c->ErrorCode;
|
||||
}
|
||||
@ -4960,22 +4833,17 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin
|
||||
hi2c->XferSize--;
|
||||
hi2c->XferCount--;
|
||||
}
|
||||
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) == RESET) && \
|
||||
((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
|
||||
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)))
|
||||
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
|
||||
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
|
||||
{
|
||||
/* Write data to TXDR */
|
||||
if (hi2c->XferCount != 0U)
|
||||
{
|
||||
/* Write data to TXDR */
|
||||
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
|
||||
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
|
||||
|
||||
/* Increment Buffer pointer */
|
||||
hi2c->pBuffPtr++;
|
||||
/* Increment Buffer pointer */
|
||||
hi2c->pBuffPtr++;
|
||||
|
||||
hi2c->XferSize--;
|
||||
hi2c->XferCount--;
|
||||
}
|
||||
hi2c->XferSize--;
|
||||
hi2c->XferCount--;
|
||||
}
|
||||
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
|
||||
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
|
||||
@ -5162,12 +5030,6 @@ static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32
|
||||
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
|
||||
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
|
||||
{
|
||||
/* Disable Interrupt related to address step */
|
||||
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
|
||||
|
||||
/* Enable ERR, TC, STOP, NACK and RXI interrupts */
|
||||
I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
|
||||
|
||||
if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
|
||||
{
|
||||
direction = I2C_GENERATE_START_READ;
|
||||
@ -5232,8 +5094,9 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint
|
||||
/* Call I2C Slave complete process */
|
||||
I2C_ITSlaveCplt(hi2c, tmpITFlags);
|
||||
}
|
||||
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
|
||||
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
|
||||
|
||||
if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
|
||||
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
|
||||
{
|
||||
/* Check that I2C transfer finished */
|
||||
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
|
||||
@ -5533,9 +5396,6 @@ static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint3
|
||||
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
|
||||
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
|
||||
{
|
||||
/* Disable Interrupt related to address step */
|
||||
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
|
||||
|
||||
/* Enable only Error interrupt */
|
||||
I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
|
||||
|
||||
@ -5578,12 +5438,6 @@ static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint3
|
||||
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
|
||||
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
|
||||
{
|
||||
/* Disable Interrupt related to address step */
|
||||
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
|
||||
|
||||
/* Enable only Error and NACK interrupt for data transfer */
|
||||
I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
|
||||
|
||||
if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
|
||||
{
|
||||
direction = I2C_GENERATE_START_READ;
|
||||
@ -5661,8 +5515,9 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin
|
||||
/* Call I2C Slave complete process */
|
||||
I2C_ITSlaveCplt(hi2c, ITFlags);
|
||||
}
|
||||
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
|
||||
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
|
||||
|
||||
if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
|
||||
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
|
||||
{
|
||||
/* Check that I2C transfer finished */
|
||||
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
|
||||
@ -6261,7 +6116,6 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
|
||||
{
|
||||
uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
|
||||
uint32_t tmpITFlags = ITFlags;
|
||||
uint32_t tmpoptions = hi2c->XferOptions;
|
||||
HAL_I2C_StateTypeDef tmpstate = hi2c->State;
|
||||
|
||||
/* Clear STOP Flag */
|
||||
@ -6278,11 +6132,6 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
|
||||
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
|
||||
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
|
||||
}
|
||||
else if (tmpstate == HAL_I2C_STATE_LISTEN)
|
||||
{
|
||||
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
|
||||
hi2c->PreviousState = I2C_STATE_NONE;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Do nothing */
|
||||
@ -6349,57 +6198,6 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
|
||||
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
|
||||
}
|
||||
|
||||
if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
|
||||
(I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_IT_NACKI) != RESET))
|
||||
{
|
||||
/* Check that I2C transfer finished */
|
||||
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
|
||||
/* Mean XferCount == 0*/
|
||||
/* So clear Flag NACKF only */
|
||||
if (hi2c->XferCount == 0U)
|
||||
{
|
||||
if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
|
||||
/* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
|
||||
Warning[Pa134]: left and right operands are identical */
|
||||
{
|
||||
/* Call I2C Listen complete process */
|
||||
I2C_ITListenCplt(hi2c, tmpITFlags);
|
||||
}
|
||||
else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
|
||||
{
|
||||
/* Clear NACK Flag */
|
||||
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
|
||||
|
||||
/* Flush TX register */
|
||||
I2C_Flush_TXDR(hi2c);
|
||||
|
||||
/* Last Byte is Transmitted */
|
||||
/* Call I2C Slave Sequential complete process */
|
||||
I2C_ITSlaveSeqCplt(hi2c);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Clear NACK Flag */
|
||||
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
|
||||
/* Clear NACK Flag */
|
||||
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
|
||||
|
||||
/* Set ErrorCode corresponding to a Non-Acknowledge */
|
||||
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
|
||||
|
||||
if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
|
||||
{
|
||||
/* Call the corresponding callback to inform upper layer of End of Transfer */
|
||||
I2C_ITError(hi2c, hi2c->ErrorCode);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
hi2c->Mode = HAL_I2C_MODE_NONE;
|
||||
hi2c->XferISR = NULL;
|
||||
|
||||
@ -6527,7 +6325,6 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
|
||||
static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
|
||||
{
|
||||
HAL_I2C_StateTypeDef tmpstate = hi2c->State;
|
||||
|
||||
uint32_t tmppreviousstate;
|
||||
|
||||
/* Reset handle parameters */
|
||||
@ -6584,7 +6381,6 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
|
||||
|
||||
/* Abort DMA TX transfer if any */
|
||||
tmppreviousstate = hi2c->PreviousState;
|
||||
|
||||
if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \
|
||||
(tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
|
||||
{
|
||||
@ -6759,7 +6555,6 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief DMA I2C slave transmit process complete callback.
|
||||
* @param hdma DMA handle
|
||||
@ -6788,7 +6583,6 @@ static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief DMA I2C master receive process complete callback.
|
||||
* @param hdma DMA handle
|
||||
@ -6839,7 +6633,6 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief DMA I2C slave receive process complete callback.
|
||||
* @param hdma DMA handle
|
||||
@ -6868,7 +6661,6 @@ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief DMA I2C communication error callback.
|
||||
* @param hdma DMA handle
|
||||
@ -6907,7 +6699,6 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma)
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief DMA I2C communication abort callback
|
||||
* (To be called at end of DMA Abort procedure).
|
||||
@ -6932,7 +6723,6 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
|
||||
I2C_TreatErrorCallback(hi2c);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief This function handles I2C Communication Timeout. It waits
|
||||
* until a flag is no longer in the specified status.
|
||||
@ -6949,12 +6739,6 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin
|
||||
{
|
||||
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
|
||||
{
|
||||
/* Check if an error is detected */
|
||||
if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check for the Timeout */
|
||||
if (Timeout != HAL_MAX_DELAY)
|
||||
{
|
||||
@ -7066,18 +6850,16 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
|
||||
static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
|
||||
uint32_t Tickstart)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) && (status == HAL_OK))
|
||||
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
|
||||
{
|
||||
/* Check if an error is detected */
|
||||
if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check if a STOPF is detected */
|
||||
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) && (status == HAL_OK))
|
||||
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
|
||||
{
|
||||
/* Check if an RXNE is pending */
|
||||
/* Store Last receive data if any */
|
||||
@ -7085,14 +6867,19 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
|
||||
{
|
||||
/* Return HAL_OK */
|
||||
/* The Reading of data from RXDR will be done in caller function */
|
||||
status = HAL_OK;
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/* Check a no-acknowledge have been detected */
|
||||
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
|
||||
else
|
||||
{
|
||||
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
|
||||
hi2c->ErrorCode = HAL_I2C_ERROR_AF;
|
||||
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
|
||||
{
|
||||
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
|
||||
hi2c->ErrorCode = HAL_I2C_ERROR_AF;
|
||||
}
|
||||
else
|
||||
{
|
||||
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
|
||||
}
|
||||
|
||||
/* Clear STOP Flag */
|
||||
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
|
||||
@ -7106,16 +6893,12 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/* Check for the Timeout */
|
||||
if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK))
|
||||
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
||||
{
|
||||
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET))
|
||||
{
|
||||
@ -7125,11 +6908,11 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
||||
status = HAL_ERROR;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
}
|
||||
return status;
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
@ -7312,9 +7095,8 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
|
||||
{
|
||||
uint32_t tmpisr = 0U;
|
||||
|
||||
if ((hi2c->XferISR != I2C_Master_ISR_DMA) && \
|
||||
(hi2c->XferISR != I2C_Slave_ISR_DMA) && \
|
||||
(hi2c->XferISR != I2C_Mem_ISR_DMA))
|
||||
if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \
|
||||
(hi2c->XferISR == I2C_Slave_ISR_DMA))
|
||||
{
|
||||
if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
|
||||
{
|
||||
@ -7322,51 +7104,6 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
|
||||
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
|
||||
}
|
||||
|
||||
if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
|
||||
{
|
||||
/* Enable ERR, TC, STOP, NACK and TXI interrupts */
|
||||
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
|
||||
}
|
||||
|
||||
if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
|
||||
{
|
||||
/* Enable ERR, TC, STOP, NACK and RXI interrupts */
|
||||
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
|
||||
}
|
||||
|
||||
if (InterruptRequest == I2C_XFER_ERROR_IT)
|
||||
{
|
||||
/* Enable ERR and NACK interrupts */
|
||||
tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
|
||||
}
|
||||
|
||||
if (InterruptRequest == I2C_XFER_CPLT_IT)
|
||||
{
|
||||
/* Enable STOP interrupts */
|
||||
tmpisr |= I2C_IT_STOPI;
|
||||
}
|
||||
}
|
||||
|
||||
else
|
||||
{
|
||||
if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
|
||||
{
|
||||
/* Enable ERR, STOP, NACK and ADDR interrupts */
|
||||
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
|
||||
}
|
||||
|
||||
if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
|
||||
{
|
||||
/* Enable ERR, TC, STOP, NACK and TXI interrupts */
|
||||
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
|
||||
}
|
||||
|
||||
if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
|
||||
{
|
||||
/* Enable ERR, TC, STOP, NACK and RXI interrupts */
|
||||
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
|
||||
}
|
||||
|
||||
if (InterruptRequest == I2C_XFER_ERROR_IT)
|
||||
{
|
||||
/* Enable ERR and NACK interrupts */
|
||||
@ -7385,6 +7122,38 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
|
||||
tmpisr |= I2C_IT_TCI;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
|
||||
{
|
||||
/* Enable ERR, STOP, NACK, and ADDR interrupts */
|
||||
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
|
||||
}
|
||||
|
||||
if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
|
||||
{
|
||||
/* Enable ERR, TC, STOP, NACK and RXI interrupts */
|
||||
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
|
||||
}
|
||||
|
||||
if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
|
||||
{
|
||||
/* Enable ERR, TC, STOP, NACK and TXI interrupts */
|
||||
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
|
||||
}
|
||||
|
||||
if (InterruptRequest == I2C_XFER_ERROR_IT)
|
||||
{
|
||||
/* Enable ERR and NACK interrupts */
|
||||
tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
|
||||
}
|
||||
|
||||
if (InterruptRequest == I2C_XFER_CPLT_IT)
|
||||
{
|
||||
/* Enable STOP interrupts */
|
||||
tmpisr |= I2C_IT_STOPI;
|
||||
}
|
||||
}
|
||||
|
||||
/* Enable interrupts only at the end */
|
||||
/* to avoid the risk of I2C interrupt handle execution before */
|
||||
|
||||
Reference in New Issue
Block a user