diff --git a/Software/.cproject b/Software/.cproject new file mode 100644 index 0000000..99a8ba3 --- /dev/null +++ b/Software/.cproject @@ -0,0 +1,212 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Software/.mxproject b/Software/.mxproject index 59c5738..99a6f12 100644 --- a/Software/.mxproject +++ b/Software/.mxproject @@ -6,6 +6,11 @@ SourceFiles=Core/Src/main.c;Core/Src/stm32h7xx_it.c;Core/Src/stm32h7xx_hal_msp.c HeaderPath=Drivers/STM32H7xx_HAL_Driver/Inc;Drivers/STM32H7xx_HAL_Driver/Inc/Legacy;Drivers/CMSIS/Device/ST/STM32H7xx/Include;Drivers/CMSIS/Include;Core/Inc; CDefines=USE_PWR_LDO_SUPPLY;USE_PWR_LDO_SUPPLY;USE_PWR_LDO_SUPPLY;USE_HAL_DRIVER;STM32H7A3xx;USE_HAL_DRIVER;USE_HAL_DRIVER; +[PreviousUsedCubeIDEFiles] +SourceFiles=Core/Src/main.c;Core/Src/stm32h7xx_it.c;Core/Src/stm32h7xx_hal_msp.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_crc.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_crc_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_fmc.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_nor.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sram.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_nand.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sdram.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c;Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx.c;Core/Src/system_stm32h7xx.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_crc.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_crc_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_hsem.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_fmc.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_nor.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sram.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_nand.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_sdram.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_ltdc_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_uart_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pcd_ex.c;Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_usb.c;Drivers/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx.c;Core/Src/system_stm32h7xx.c;;; +HeaderPath=Drivers/STM32H7xx_HAL_Driver/Inc;Drivers/STM32H7xx_HAL_Driver/Inc/Legacy;Drivers/CMSIS/Device/ST/STM32H7xx/Include;Drivers/CMSIS/Include;Core/Inc; +CDefines=USE_PWR_LDO_SUPPLY;USE_PWR_LDO_SUPPLY;USE_PWR_LDO_SUPPLY;USE_HAL_DRIVER;STM32H7A3xx;USE_HAL_DRIVER;USE_HAL_DRIVER; + [PreviousGenFiles] AdvancedFolderStructure=true HeaderFileListSize=3 diff --git a/Software/.project b/Software/.project new file mode 100644 index 0000000..df9e35b --- /dev/null +++ b/Software/.project @@ -0,0 +1,33 @@ + + + FT23_Charger + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.st.stm32cube.ide.mcu.MCUProjectNature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAev2ProjectNature + com.st.stm32cube.ide.mcu.MCUCubeProjectNature + com.st.stm32cube.ide.mcu.MCUAdvancedStructureProjectNature + com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature + com.st.stm32cube.ide.mcu.MCURootProjectNature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/Software/Core/Inc/stm32h7xx_it.h b/Software/Core/Inc/stm32h7xx_it.h index bbbeb7c..723516c 100644 --- a/Software/Core/Inc/stm32h7xx_it.h +++ b/Software/Core/Inc/stm32h7xx_it.h @@ -60,6 +60,7 @@ void FDCAN1_IT1_IRQHandler(void); void FMC_IRQHandler(void); void FDCAN_CAL_IRQHandler(void); void LTDC_IRQHandler(void); +void LTDC_ER_IRQHandler(void); /* USER CODE BEGIN EFP */ /* USER CODE END EFP */ diff --git a/Software/Core/Src/main.c b/Software/Core/Src/main.c index 86b31b6..f574860 100644 --- a/Software/Core/Src/main.c +++ b/Software/Core/Src/main.c @@ -179,7 +179,7 @@ void SystemClock_Config(void) /** Configure the main internal regulator output voltage */ - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} @@ -191,11 +191,11 @@ void SystemClock_Config(void) RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = 2; - RCC_OscInitStruct.PLL.PLLN = 70; + RCC_OscInitStruct.PLL.PLLM = 1; + RCC_OscInitStruct.PLL.PLLN = 20; RCC_OscInitStruct.PLL.PLLP = 2; RCC_OscInitStruct.PLL.PLLQ = 4; - RCC_OscInitStruct.PLL.PLLR = 4; + RCC_OscInitStruct.PLL.PLLR = 2; RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3; RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; RCC_OscInitStruct.PLL.PLLFRACN = 0; @@ -217,7 +217,7 @@ void SystemClock_Config(void) RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_6) != HAL_OK) + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { Error_Handler(); } @@ -323,7 +323,7 @@ static void MX_I2C4_Init(void) /* USER CODE END I2C4_Init 1 */ hi2c4.Instance = I2C4; - hi2c4.Init.Timing = 0x20B0CCFF; + hi2c4.Init.Timing = 0x10909CEC; hi2c4.Init.OwnAddress1 = 0; hi2c4.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; hi2c4.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; @@ -379,23 +379,23 @@ static void MX_LTDC_Init(void) hltdc.Init.PCPolarity = LTDC_PCPOLARITY_IPC; hltdc.Init.HorizontalSync = 19; hltdc.Init.VerticalSync = 2; - hltdc.Init.AccumulatedHBP = 69; + hltdc.Init.AccumulatedHBP = 159; hltdc.Init.AccumulatedVBP = 22; - hltdc.Init.AccumulatedActiveW = 549; - hltdc.Init.AccumulatedActiveH = 294; - hltdc.Init.TotalWidth = 599; - hltdc.Init.TotalHeigh = 306; + hltdc.Init.AccumulatedActiveW = 1183; + hltdc.Init.AccumulatedActiveH = 622; + hltdc.Init.TotalWidth = 1343; + hltdc.Init.TotalHeigh = 634; hltdc.Init.Backcolor.Blue = 0; hltdc.Init.Backcolor.Green = 0; - hltdc.Init.Backcolor.Red = 255; + hltdc.Init.Backcolor.Red = 0; if (HAL_LTDC_Init(&hltdc) != HAL_OK) { Error_Handler(); } pLayerCfg.WindowX0 = 0; - pLayerCfg.WindowX1 = 480; + pLayerCfg.WindowX1 = 1024; pLayerCfg.WindowY0 = 0; - pLayerCfg.WindowY1 = 272; + pLayerCfg.WindowY1 = 600; pLayerCfg.PixelFormat = LTDC_PIXEL_FORMAT_RGB888; pLayerCfg.Alpha = 1; pLayerCfg.Alpha0 = 0; @@ -574,16 +574,16 @@ static void MX_FMC_Init(void) hsdram1.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4; hsdram1.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_3; hsdram1.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE; - hsdram1.Init.SDClockPeriod = FMC_SDRAM_CLOCK_DISABLE; + hsdram1.Init.SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2; hsdram1.Init.ReadBurst = FMC_SDRAM_RBURST_DISABLE; hsdram1.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_1; /* SdramTiming */ SdramTiming.LoadToActiveDelay = 2; - SdramTiming.ExitSelfRefreshDelay = 10; - SdramTiming.SelfRefreshTime = 6; - SdramTiming.RowCycleDelay = 8; - SdramTiming.WriteRecoveryTime = 4; - SdramTiming.RPDelay = 2; + SdramTiming.ExitSelfRefreshDelay = 5; + SdramTiming.SelfRefreshTime = 3; + SdramTiming.RowCycleDelay = 4; + SdramTiming.WriteRecoveryTime = 3; + SdramTiming.RPDelay = 3; SdramTiming.RCDDelay = 2; if (HAL_SDRAM_Init(&hsdram1, &SdramTiming) != HAL_OK) diff --git a/Software/Core/Src/stm32h7xx_hal_msp.c b/Software/Core/Src/stm32h7xx_hal_msp.c index 3b8291e..4864650 100644 --- a/Software/Core/Src/stm32h7xx_hal_msp.c +++ b/Software/Core/Src/stm32h7xx_hal_msp.c @@ -433,6 +433,8 @@ void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc) /* LTDC interrupt Init */ HAL_NVIC_SetPriority(LTDC_IRQn, 0, 0); HAL_NVIC_EnableIRQ(LTDC_IRQn); + HAL_NVIC_SetPriority(LTDC_ER_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(LTDC_ER_IRQn); /* USER CODE BEGIN LTDC_MspInit 1 */ /* USER CODE END LTDC_MspInit 1 */ @@ -498,6 +500,7 @@ void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc) /* LTDC interrupt DeInit */ HAL_NVIC_DisableIRQ(LTDC_IRQn); + HAL_NVIC_DisableIRQ(LTDC_ER_IRQn); /* USER CODE BEGIN LTDC_MspDeInit 1 */ /* USER CODE END LTDC_MspDeInit 1 */ @@ -735,8 +738,8 @@ static void HAL_FMC_MspInit(void){ /** Initializes the peripherals clock */ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_FMC; - PeriphClkInitStruct.PLL2.PLL2M = 2; - PeriphClkInitStruct.PLL2.PLL2N = 70; + PeriphClkInitStruct.PLL2.PLL2M = 1; + PeriphClkInitStruct.PLL2.PLL2N = 20; PeriphClkInitStruct.PLL2.PLL2P = 2; PeriphClkInitStruct.PLL2.PLL2Q = 4; PeriphClkInitStruct.PLL2.PLL2R = 2; diff --git a/Software/Core/Src/stm32h7xx_it.c b/Software/Core/Src/stm32h7xx_it.c index 8f01f00..f7a1b25 100644 --- a/Software/Core/Src/stm32h7xx_it.c +++ b/Software/Core/Src/stm32h7xx_it.c @@ -270,6 +270,20 @@ void LTDC_IRQHandler(void) /* USER CODE END LTDC_IRQn 1 */ } +/** + * @brief This function handles LTDC Error global Interrupt. + */ +void LTDC_ER_IRQHandler(void) +{ + /* USER CODE BEGIN LTDC_ER_IRQn 0 */ + + /* USER CODE END LTDC_ER_IRQn 0 */ + HAL_LTDC_IRQHandler(&hltdc); + /* USER CODE BEGIN LTDC_ER_IRQn 1 */ + + /* USER CODE END LTDC_ER_IRQn 1 */ +} + /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ diff --git a/Software/Core/Startup/startup_stm32h7a3zitx.s b/Software/Core/Startup/startup_stm32h7a3zitx.s new file mode 100644 index 0000000..26c26a2 --- /dev/null +++ b/Software/Core/Startup/startup_stm32h7a3zitx.s @@ -0,0 +1,745 @@ +/** + ****************************************************************************** + * @file startup_stm32h7a3xx.s + * @author MCD Application Team + * @brief STM32H7B3xx Devices vector table for GCC based toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * Copyright (c) 2019 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m7 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Call the ExitRun0Mode function to configure the power supply */ + bl ExitRun0Mode +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + + +g_pfnVectors: + .word _estack + .word Reset_Handler + + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_PVM_IRQHandler /* PVD/PVM through EXTI Line detection */ + .word RTC_TAMP_STAMP_CSS_LSE_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */ + .word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */ + .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */ + .word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */ + .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */ + .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word DFSDM2_IRQHandler /* DFSDM2 Interrupt */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FMC_IRQHandler /* FMC */ + .word SDMMC1_IRQHandler /* SDMMC1 */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/ + .word DFSDM1_FLT4_IRQHandler /* DFSDM Filter4 Interrupt */ + .word DFSDM1_FLT5_IRQHandler /* DFSDM Filter5 Interrupt */ + .word DFSDM1_FLT6_IRQHandler /* DFSDM Filter6 Interrupt */ + .word DFSDM1_FLT7_IRQHandler /* DFSDM Filter7 Interrupt */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_PSSI_IRQHandler /* DCMI, PSSI */ + .word 0 /* Reserved */ + .word RNG_IRQHandler /* RNG */ + .word FPU_IRQHandler /* FPU */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + .word SPI6_IRQHandler /* SPI6 */ + .word SAI1_IRQHandler /* SAI1 */ + .word LTDC_IRQHandler /* LTDC */ + .word LTDC_ER_IRQHandler /* LTDC error */ + .word DMA2D_IRQHandler /* DMA2D */ + .word SAI2_IRQHandler /* SAI2 */ + .word OCTOSPI1_IRQHandler /* OCTOSPI1 */ + .word LPTIM1_IRQHandler /* LPTIM1 */ + .word CEC_IRQHandler /* HDMI_CEC */ + .word I2C4_EV_IRQHandler /* I2C4 Event */ + .word I2C4_ER_IRQHandler /* I2C4 Error */ + .word SPDIF_RX_IRQHandler /* SPDIF_RX */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */ + .word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */ + .word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */ + .word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */ + .word 0 /* Reserved */ + .word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */ + .word TIM15_IRQHandler /* TIM15 global Interrupt */ + .word TIM16_IRQHandler /* TIM16 global Interrupt */ + .word TIM17_IRQHandler /* TIM17 global Interrupt */ + .word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */ + .word MDIOS_IRQHandler /* MDIOS global Interrupt */ + .word JPEG_IRQHandler /* JPEG global Interrupt */ + .word MDMA_IRQHandler /* MDMA global Interrupt */ + .word 0 /* Reserved */ + .word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */ + .word HSEM1_IRQHandler /* HSEM1 global Interrupt */ + .word 0 /* Reserved */ + .word DAC2_IRQHandler /* DAC2 global Interrupt */ + .word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */ + .word BDMA2_Channel0_IRQHandler /* BDMA2 Channel 0 global Interrupt */ + .word BDMA2_Channel1_IRQHandler /* BDMA2 Channel 1 global Interrupt */ + .word BDMA2_Channel2_IRQHandler /* BDMA2 Channel 2 global Interrupt */ + .word BDMA2_Channel3_IRQHandler /* BDMA2 Channel 3 global Interrupt */ + .word BDMA2_Channel4_IRQHandler /* BDMA2 Channel 4 global Interrupt */ + .word BDMA2_Channel5_IRQHandler /* BDMA2 Channel 5 global Interrupt */ + .word BDMA2_Channel6_IRQHandler /* BDMA2 Channel 6 global Interrupt */ + .word BDMA2_Channel7_IRQHandler /* BDMA2 Channel 7 global Interrupt */ + .word COMP_IRQHandler /* COMP global Interrupt */ + .word LPTIM2_IRQHandler /* LP TIM2 global interrupt */ + .word LPTIM3_IRQHandler /* LP TIM3 global interrupt */ + .word UART9_IRQHandler /* UART9 global interrupt */ + .word USART10_IRQHandler /* USART10 global interrupt */ + .word LPUART1_IRQHandler /* LP UART1 interrupt */ + .word 0 /* Reserved */ + .word CRS_IRQHandler /* Clock Recovery Global Interrupt */ + .word ECC_IRQHandler /* ECC diagnostic Global Interrupt */ + .word 0 /* Reserved */ + .word DTS_IRQHandler /* DTS */ + .word 0 /* Reserved */ + .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */ + .word OCTOSPI2_IRQHandler /* OCTOSPI2 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word GFXMMU_IRQHandler /* GFXMMU */ + .word BDMA1_IRQHandler /* BDMA1 */ + + .size g_pfnVectors, .-g_pfnVectors + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_PVM_IRQHandler + .thumb_set PVD_PVM_IRQHandler,Default_Handler + + .weak RTC_TAMP_STAMP_CSS_LSE_IRQHandler + .thumb_set RTC_TAMP_STAMP_CSS_LSE_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak FDCAN1_IT0_IRQHandler + .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler + + .weak FDCAN2_IT0_IRQHandler + .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler + + .weak FDCAN1_IT1_IRQHandler + .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler + + .weak FDCAN2_IT1_IRQHandler + .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_IRQHandler + .thumb_set TIM1_BRK_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_IRQHandler + .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak DFSDM2_IRQHandler + .thumb_set DFSDM2_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak FDCAN_CAL_IRQHandler + .thumb_set FDCAN_CAL_IRQHandler,Default_Handler + + .weak DFSDM1_FLT4_IRQHandler + .thumb_set DFSDM1_FLT4_IRQHandler,Default_Handler + + .weak DFSDM1_FLT5_IRQHandler + .thumb_set DFSDM1_FLT5_IRQHandler,Default_Handler + + .weak DFSDM1_FLT6_IRQHandler + .thumb_set DFSDM1_FLT6_IRQHandler,Default_Handler + + .weak DFSDM1_FLT7_IRQHandler + .thumb_set DFSDM1_FLT7_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak DCMI_PSSI_IRQHandler + .thumb_set DCMI_PSSI_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak SPI6_IRQHandler + .thumb_set SPI6_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak LTDC_IRQHandler + .thumb_set LTDC_IRQHandler,Default_Handler + + .weak LTDC_ER_IRQHandler + .thumb_set LTDC_ER_IRQHandler,Default_Handler + + .weak DMA2D_IRQHandler + .thumb_set DMA2D_IRQHandler,Default_Handler + + .weak SAI2_IRQHandler + .thumb_set SAI2_IRQHandler,Default_Handler + + .weak OCTOSPI1_IRQHandler + .thumb_set OCTOSPI1_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak I2C4_EV_IRQHandler + .thumb_set I2C4_EV_IRQHandler,Default_Handler + + .weak I2C4_ER_IRQHandler + .thumb_set I2C4_ER_IRQHandler,Default_Handler + + .weak SPDIF_RX_IRQHandler + .thumb_set SPDIF_RX_IRQHandler,Default_Handler + + .weak DMAMUX1_OVR_IRQHandler + .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler + + .weak DFSDM1_FLT0_IRQHandler + .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler + + .weak DFSDM1_FLT1_IRQHandler + .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler + + .weak DFSDM1_FLT2_IRQHandler + .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler + + .weak DFSDM1_FLT3_IRQHandler + .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler + + .weak SWPMI1_IRQHandler + .thumb_set SWPMI1_IRQHandler,Default_Handler + + .weak TIM15_IRQHandler + .thumb_set TIM15_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak MDIOS_WKUP_IRQHandler + .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler + + .weak MDIOS_IRQHandler + .thumb_set MDIOS_IRQHandler,Default_Handler + + .weak JPEG_IRQHandler + .thumb_set JPEG_IRQHandler,Default_Handler + + .weak MDMA_IRQHandler + .thumb_set MDMA_IRQHandler,Default_Handler + + .weak SDMMC2_IRQHandler + .thumb_set SDMMC2_IRQHandler,Default_Handler + + .weak HSEM1_IRQHandler + .thumb_set HSEM1_IRQHandler,Default_Handler + + .weak DAC2_IRQHandler + .thumb_set DAC2_IRQHandler,Default_Handler + + .weak DMAMUX2_OVR_IRQHandler + .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler + + .weak BDMA2_Channel0_IRQHandler + .thumb_set BDMA2_Channel0_IRQHandler,Default_Handler + + .weak BDMA2_Channel1_IRQHandler + .thumb_set BDMA2_Channel1_IRQHandler,Default_Handler + + .weak BDMA2_Channel2_IRQHandler + .thumb_set BDMA2_Channel2_IRQHandler,Default_Handler + + .weak BDMA2_Channel3_IRQHandler + .thumb_set BDMA2_Channel3_IRQHandler,Default_Handler + + .weak BDMA2_Channel4_IRQHandler + .thumb_set BDMA2_Channel4_IRQHandler,Default_Handler + + .weak BDMA2_Channel5_IRQHandler + .thumb_set BDMA2_Channel5_IRQHandler,Default_Handler + + .weak BDMA2_Channel6_IRQHandler + .thumb_set BDMA2_Channel6_IRQHandler,Default_Handler + + .weak BDMA2_Channel7_IRQHandler + .thumb_set BDMA2_Channel7_IRQHandler,Default_Handler + + .weak COMP_IRQHandler + .thumb_set COMP_IRQHandler,Default_Handler + + .weak LPTIM2_IRQHandler + .thumb_set LPTIM2_IRQHandler,Default_Handler + + .weak LPTIM3_IRQHandler + .thumb_set LPTIM3_IRQHandler,Default_Handler + + .weak LPTIM4_IRQHandler + .thumb_set LPTIM4_IRQHandler,Default_Handler + + .weak LPTIM5_IRQHandler + .thumb_set LPTIM5_IRQHandler,Default_Handler + + .weak UART9_IRQHandler + .thumb_set UART9_IRQHandler,Default_Handler + + .weak USART10_IRQHandler + .thumb_set USART10_IRQHandler,Default_Handler + + .weak LPUART1_IRQHandler + .thumb_set LPUART1_IRQHandler,Default_Handler + + .weak CRS_IRQHandler + .thumb_set CRS_IRQHandler,Default_Handler + + .weak ECC_IRQHandler + .thumb_set ECC_IRQHandler,Default_Handler + + .weak DTS_IRQHandler + .thumb_set DTS_IRQHandler,Default_Handler + + .weak WAKEUP_PIN_IRQHandler + .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler + + .weak OCTOSPI2_IRQHandler + .thumb_set OCTOSPI2_IRQHandler,Default_Handler + + .weak GFXMMU_IRQHandler + .thumb_set GFXMMU_IRQHandler,Default_Handler + + .weak BDMA1_IRQHandler + .thumb_set BDMA1_IRQHandler,Default_Handler + + diff --git a/Software/FT23_Charger.ioc b/Software/FT23_Charger.ioc index 12d131b..3508d28 100644 --- a/Software/FT23_Charger.ioc +++ b/Software/FT23_Charger.ioc @@ -2,9 +2,9 @@ CAD.formats= CAD.pinconfig= CAD.provider= -FDCAN1.CalculateBaudRateNominal=875000 -FDCAN1.CalculateTimeBitNominal=1142 -FDCAN1.CalculateTimeQuantumNominal=14.285714285714286 +FDCAN1.CalculateBaudRateNominal=500000 +FDCAN1.CalculateTimeBitNominal=2000 +FDCAN1.CalculateTimeQuantumNominal=25.0 FDCAN1.IPParameters=CalculateTimeQuantumNominal,CalculateTimeBitNominal,CalculateBaudRateNominal,StdFiltersNbr,RxFifo0ElmtsNbr,TxFifoQueueElmtsNbr,NominalPrescaler,NominalTimeSeg1,NominalTimeSeg2 FDCAN1.NominalPrescaler=2 FDCAN1.NominalTimeSeg1=63 @@ -14,48 +14,47 @@ FDCAN1.StdFiltersNbr=32 FDCAN1.TxFifoQueueElmtsNbr=1 FMC.CASLatency1=FMC_SDRAM_CAS_LATENCY_3 FMC.ColumnBitsNumber1=FMC_SDRAM_COLUMN_BITS_NUM_9 -FMC.ExitSelfRefreshDelay1=10 -FMC.IPParameters=ReadBurst1,WriteProtection1,LoadToActiveDelay1,ExitSelfRefreshDelay1,CASLatency1,SelfRefreshTime1,RowCycleDelay1,RowCycleDelay2,RCDDelay1,RPDelay1,RPDelay2,ColumnBitsNumber1,ReadPipeDelay1,SDClockPeriod1,WriteRecoveryTime1,ReadPipeDelay2,SDClockPeriod2 +FMC.ExitSelfRefreshDelay1=5 +FMC.IPParameters=ReadBurst1,WriteProtection1,LoadToActiveDelay1,ExitSelfRefreshDelay1,CASLatency1,SelfRefreshTime1,RowCycleDelay1,RowCycleDelay2,RCDDelay1,RPDelay1,RPDelay2,WriteRecoveryTime1,ColumnBitsNumber1,ReadPipeDelay1,ReadPipeDelay2,SDClockPeriod1,SDClockPeriod2 FMC.LoadToActiveDelay1=2 FMC.RCDDelay1=2 -FMC.RPDelay1=2 -FMC.RPDelay2=2 +FMC.RPDelay1=3 +FMC.RPDelay2=3 FMC.ReadBurst1=FMC_SDRAM_RBURST_DISABLE FMC.ReadPipeDelay1=FMC_SDRAM_RPIPE_DELAY_1 FMC.ReadPipeDelay2=FMC_SDRAM_RPIPE_DELAY_1 -FMC.RowCycleDelay1=8 -FMC.RowCycleDelay2=8 +FMC.RowCycleDelay1=4 +FMC.RowCycleDelay2=4 FMC.SDClockPeriod1=FMC_SDRAM_CLOCK_PERIOD_2 FMC.SDClockPeriod2=FMC_SDRAM_CLOCK_PERIOD_2 -FMC.SelfRefreshTime1=6 +FMC.SelfRefreshTime1=3 FMC.WriteProtection1=FMC_SDRAM_WRITE_PROTECTION_DISABLE -FMC.WriteRecoveryTime1=4 +FMC.WriteRecoveryTime1=3 File.Version=6 GPIO.groupedBy=Group By Peripherals I2C4.IPParameters=Timing -I2C4.Timing=0x20B0CCFF +I2C4.Timing=0x10909CEC KeepUserPlacement=false -LTDC.ActiveH=272 -LTDC.ActiveW=480 +LTDC.ActiveH=600 +LTDC.ActiveW=1024 LTDC.Alpha_L0=1 LTDC.Blue_L0=100 LTDC.FBStartAdress_L0=201326592 -LTDC.HBP=50 -LTDC.HFP=50 +LTDC.HBP=140 +LTDC.HFP=160 LTDC.HSync=20 -LTDC.IPParameters=ActiveW,ActiveH,HFP,HBP,HSync,VSync,VBP,VFP,Layers,FBStartAdress_L0,ImageWidth_L0,ImageHeight_L0,PixelFormat_L0,Blue_L0,WindowX0_L0,WindowX1_L0,WindowY0_L0,WindowY1_L0,Alpha_L0,Red +LTDC.IPParameters=ActiveW,ActiveH,HFP,HBP,HSync,VSync,VBP,VFP,Layers,FBStartAdress_L0,ImageWidth_L0,ImageHeight_L0,PixelFormat_L0,Blue_L0,WindowX0_L0,WindowX1_L0,WindowY0_L0,WindowY1_L0,Alpha_L0 LTDC.ImageHeight_L0=600 LTDC.ImageWidth_L0=1024 LTDC.Layers=0 LTDC.PixelFormat_L0=LTDC_PIXEL_FORMAT_RGB888 -LTDC.Red=255 LTDC.VBP=20 LTDC.VFP=12 LTDC.VSync=3 LTDC.WindowX0_L0=0 -LTDC.WindowX1_L0=480 +LTDC.WindowX1_L0=1024 LTDC.WindowY0_L0=0 -LTDC.WindowY1_L0=272 +LTDC.WindowY1_L0=600 MMTAppRegionsCount=0 MMTConfigApplied=false Mcu.CPN=STM32H7A3ZIT6 @@ -187,6 +186,7 @@ NVIC.FDCAN_CAL_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true NVIC.FMC_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true NVIC.ForceEnableDMAVector=true NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.LTDC_ER_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true NVIC.LTDC_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false @@ -402,22 +402,23 @@ ProjectManager.ProjectName=FT23_Charger ProjectManager.ProjectStructure= ProjectManager.RegisterCallBack= ProjectManager.StackSize=0x400 -ProjectManager.TargetToolchain=Makefile +ProjectManager.TargetToolchain=STM32CubeIDE ProjectManager.ToolChainLocation= ProjectManager.UAScriptAfterPath= ProjectManager.UAScriptBeforePath= -ProjectManager.UnderRoot=false -ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_FDCAN1_Init-FDCAN1-false-HAL-true,4-MX_FMC_Init-FMC-false-HAL-true,5-MX_I2C4_Init-I2C4-false-HAL-true,6-MX_SDMMC2_SD_Init-SDMMC2-false-HAL-true,6-MX_USART10_UART_Init-USART10-false-HAL-true,7-MX_USB_OTG_HS_PCD_Init-USB_OTG_HS-false-HAL-true,8-MX_UART5_Init-UART5-false-HAL-true,9-MX_LTDC_Init-LTDC-false-HAL-true,10-MX_CRC_Init-CRC-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true +ProjectManager.UnderRoot=true +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_FDCAN1_Init-FDCAN1-false-HAL-true,4-MX_FMC_Init-FMC-false-HAL-true,5-MX_I2C4_Init-I2C4-false-HAL-true,6-MX_USART10_UART_Init-USART10-false-HAL-true,7-MX_USB_OTG_HS_PCD_Init-USB_OTG_HS-false-HAL-true,8-MX_UART5_Init-UART5-false-HAL-true,9-MX_LTDC_Init-LTDC-false-HAL-true,10-MX_CRC_Init-CRC-false-HAL-true,12-MX_TouchGFX_Init-STMicroelectronics.X-CUBE-TOUCHGFX.4.21.0-false-HAL-false,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true,13-MX_TouchGFX_Process-STMicroelectronics.X-CUBE-TOUCHGFX.4.21.0-false-HAL-false RCC.ADCCLockSelection=RCC_ADCCLKSOURCE_PLL2 -RCC.ADCFreq_Value=280000000 -RCC.AHB12Freq_Value=280000000 -RCC.AHB4Freq_Value=280000000 -RCC.APB1Freq_Value=140000000 -RCC.APB2Freq_Value=140000000 -RCC.APB3Freq_Value=140000000 -RCC.APB4Freq_Value=140000000 -RCC.AXIClockFreq_Value=280000000 -RCC.CDCPREFreq_Value=280000000 +RCC.ADCFreq_Value=160000000 +RCC.AHB12Freq_Value=160000000 +RCC.AHB4Freq_Value=160000000 +RCC.APB1Freq_Value=80000000 +RCC.APB2Freq_Value=80000000 +RCC.APB3Freq_Value=80000000 +RCC.APB4Freq_Value=80000000 +RCC.AXIClockFreq_Value=160000000 +RCC.CDCPRE=RCC_SYSCLK_DIV1 +RCC.CDCPREFreq_Value=160000000 RCC.CDPPRE=RCC_APB3_DIV2 RCC.CDPPRE1=RCC_APB1_DIV2 RCC.CDPPRE2=RCC_APB2_DIV2 @@ -426,74 +427,75 @@ RCC.CECFreq_Value=32000 RCC.CKPERFreq_Value=64000000 RCC.CKPERSourceSelection=RCC_CLKPSOURCE_HSI RCC.CSI_VALUE=4000000 -RCC.CortexFreq_Value=280000000 +RCC.CortexFreq_Value=160000000 RCC.Cortex_Div=SYSTICK_CLKSOURCE_HCLK RCC.Cortex_DivARG=SystemCoreClock/1000 -RCC.CpuClockFreq_Value=280000000 +RCC.CpuClockFreq_Value=160000000 RCC.DAC1Freq_Value=32000 RCC.DAC2Freq_Value=32000 -RCC.DFSDM2ACLkFreq_Value=140000000 -RCC.DFSDM2Freq_Value=140000000 -RCC.DFSDMACLkFreq_Value=140000000 +RCC.DFSDM2ACLkFreq_Value=80000000 +RCC.DFSDM2Freq_Value=80000000 +RCC.DFSDMACLkFreq_Value=80000000 RCC.DFSDMCLockSelection=RCC_DFSDM1CLKSOURCE_D2PCLK1 -RCC.DFSDMFreq_Value=140000000 -RCC.DIVM1=2 -RCC.DIVM2=2 +RCC.DFSDMFreq_Value=80000000 +RCC.DIVM1=1 +RCC.DIVM2=1 RCC.DIVM3=1 -RCC.DIVN1=70 -RCC.DIVN2=70 +RCC.DIVN1=20 +RCC.DIVN2=20 RCC.DIVN3=12 -RCC.DIVP1Freq_Value=280000000 +RCC.DIVP1=2 +RCC.DIVP1Freq_Value=160000000 RCC.DIVP2=2 -RCC.DIVP2Freq_Value=280000000 +RCC.DIVP2Freq_Value=160000000 RCC.DIVP3=2 RCC.DIVP3Freq_Value=96000000 RCC.DIVQ1=4 -RCC.DIVQ1Freq_Value=140000000 +RCC.DIVQ1Freq_Value=80000000 RCC.DIVQ2=4 -RCC.DIVQ2Freq_Value=140000000 +RCC.DIVQ2Freq_Value=80000000 RCC.DIVQ3=3 RCC.DIVQ3Freq_Value=64000000 -RCC.DIVR1=4 -RCC.DIVR1Freq_Value=140000000 -RCC.DIVR2Freq_Value=280000000 +RCC.DIVR1=2 +RCC.DIVR1Freq_Value=160000000 +RCC.DIVR2Freq_Value=160000000 RCC.DIVR3=3 RCC.DIVR3Freq_Value=64000000 RCC.EXTERNAL_CLOCK_VALUE=12288000 -RCC.FDCANFreq_Value=140000000 +RCC.FDCANFreq_Value=80000000 RCC.FMCCLockSelection=RCC_FMCCLKSOURCE_PLL2 -RCC.FMCFreq_Value=280000000 +RCC.FMCFreq_Value=160000000 RCC.FamilyName=M -RCC.HCLK3ClockFreq_Value=280000000 -RCC.HCLKFreq_Value=280000000 +RCC.HCLK3ClockFreq_Value=160000000 +RCC.HCLKFreq_Value=160000000 RCC.HPRE=RCC_HCLK_DIV1 RCC.HSE_VALUE=16000000 RCC.HSI48_VALUE=48000000 RCC.HSIDiv=RCC_PLLSAIDIVR_1 RCC.HSI_VALUE=64000000 RCC.I2C123CLockSelection=RCC_I2C123CLKSOURCE_D2PCLK1 -RCC.I2C123Freq_Value=140000000 +RCC.I2C123Freq_Value=80000000 RCC.I2C4CLockSelection=RCC_I2C4CLKSOURCE_D3PCLK1 -RCC.I2C4Freq_Value=140000000 -RCC.IPParameters=ADCCLockSelection,ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CDCPREFreq_Value,CDPPRE,CDPPRE1,CDPPRE2,CECCLockSelection,CECFreq_Value,CKPERFreq_Value,CKPERSourceSelection,CSI_VALUE,CortexFreq_Value,Cortex_Div,Cortex_DivARG,CpuClockFreq_Value,DAC1Freq_Value,DAC2Freq_Value,DFSDM2ACLkFreq_Value,DFSDM2Freq_Value,DFSDMACLkFreq_Value,DFSDMCLockSelection,DFSDMFreq_Value,DIVM1,DIVM2,DIVM3,DIVN1,DIVN2,DIVN3,DIVP1Freq_Value,DIVP2,DIVP2Freq_Value,DIVP3,DIVP3Freq_Value,DIVQ1,DIVQ1Freq_Value,DIVQ2,DIVQ2Freq_Value,DIVQ3,DIVQ3Freq_Value,DIVR1,DIVR1Freq_Value,DIVR2Freq_Value,DIVR3,DIVR3Freq_Value,EXTERNAL_CLOCK_VALUE,FDCANFreq_Value,FMCCLockSelection,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,HPRE,HSE_VALUE,HSI48_VALUE,HSIDiv,HSI_VALUE,I2C123CLockSelection,I2C123Freq_Value,I2C4CLockSelection,I2C4Freq_Value,LPTIM1CLockSelection,LPTIM1Freq_Value,LPTIM2CLockSelection,LPTIM2Freq_Value,LPTIM345CLockSelection,LPTIM345Freq_Value,LPUART1CLockSelection,LPUART1Freq_Value,LSI_VALUE,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,PLL2FRACN,PLL3FRACN,PLLFRACN,PLLSourceVirtual,QSPICLockSelection,QSPIFreq_Value,RCC_MCO1Source,RCC_MCO2Source,RCC_MCODiv1,RCC_MCODiv2,RCC_RTC_Clock_Source_FROM_HSE,RNGCLockSelection,RNGFreq_Value,RTCFreq_Value,SAI1CLockSelection,SAI1Freq_Value,SAI2AFreq_Value,SAI2BCLockSelection,SAI2BFreq_Value,SDMMC1CLockSelection,SDMMCFreq_Value,SPDIFCLockSelection,SPDIFRXFreq_Value,SPI123CLockSelection,SPI123Freq_Value,SPI45Freq_Value,SPI6CLockSelection,SPI6Freq_Value,SRDPPRE,SWPCLockSelection,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,Spi45ClockSelection,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16CLockSelection,USART16Freq_Value,USART234578CLockSelection,USART234578Freq_Value,USBCLockSelection,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value,WatchDogFreq_Value +RCC.I2C4Freq_Value=80000000 +RCC.IPParameters=ADCCLockSelection,ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CDCPRE,CDCPREFreq_Value,CDPPRE,CDPPRE1,CDPPRE2,CECCLockSelection,CECFreq_Value,CKPERFreq_Value,CKPERSourceSelection,CSI_VALUE,CortexFreq_Value,Cortex_Div,Cortex_DivARG,CpuClockFreq_Value,DAC1Freq_Value,DAC2Freq_Value,DFSDM2ACLkFreq_Value,DFSDM2Freq_Value,DFSDMACLkFreq_Value,DFSDMCLockSelection,DFSDMFreq_Value,DIVM1,DIVM2,DIVM3,DIVN1,DIVN2,DIVN3,DIVP1,DIVP1Freq_Value,DIVP2,DIVP2Freq_Value,DIVP3,DIVP3Freq_Value,DIVQ1,DIVQ1Freq_Value,DIVQ2,DIVQ2Freq_Value,DIVQ3,DIVQ3Freq_Value,DIVR1,DIVR1Freq_Value,DIVR2Freq_Value,DIVR3,DIVR3Freq_Value,EXTERNAL_CLOCK_VALUE,FDCANFreq_Value,FMCCLockSelection,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,HPRE,HSE_VALUE,HSI48_VALUE,HSIDiv,HSI_VALUE,I2C123CLockSelection,I2C123Freq_Value,I2C4CLockSelection,I2C4Freq_Value,LPTIM1CLockSelection,LPTIM1Freq_Value,LPTIM2CLockSelection,LPTIM2Freq_Value,LPTIM345CLockSelection,LPTIM345Freq_Value,LPUART1CLockSelection,LPUART1Freq_Value,LSI_VALUE,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,PLL2FRACN,PLL3FRACN,PLLFRACN,PLLSourceVirtual,QSPICLockSelection,QSPIFreq_Value,RCC_MCO1Source,RCC_MCO2Source,RCC_MCODiv1,RCC_MCODiv2,RCC_RTC_Clock_Source_FROM_HSE,RNGCLockSelection,RNGFreq_Value,RTCFreq_Value,SAI1CLockSelection,SAI1Freq_Value,SAI2AFreq_Value,SAI2BCLockSelection,SAI2BFreq_Value,SDMMC1CLockSelection,SDMMCFreq_Value,SPDIFCLockSelection,SPDIFRXFreq_Value,SPI123CLockSelection,SPI123Freq_Value,SPI45Freq_Value,SPI6CLockSelection,SPI6Freq_Value,SRDPPRE,SWPCLockSelection,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,Spi45ClockSelection,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16CLockSelection,USART16Freq_Value,USART234578CLockSelection,USART234578Freq_Value,USBCLockSelection,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value,WatchDogFreq_Value RCC.LPTIM1CLockSelection=RCC_LPTIM1CLKSOURCE_D2PCLK1 -RCC.LPTIM1Freq_Value=140000000 +RCC.LPTIM1Freq_Value=80000000 RCC.LPTIM2CLockSelection=RCC_LPTIM2CLKSOURCE_D3PCLK1 -RCC.LPTIM2Freq_Value=140000000 +RCC.LPTIM2Freq_Value=80000000 RCC.LPTIM345CLockSelection=RCC_LPTIM3CLKSOURCE_D3PCLK1 -RCC.LPTIM345Freq_Value=140000000 +RCC.LPTIM345Freq_Value=80000000 RCC.LPUART1CLockSelection=RCC_LPUART1CLKSOURCE_D3PCLK1 -RCC.LPUART1Freq_Value=140000000 +RCC.LPUART1Freq_Value=80000000 RCC.LSI_VALUE=32000 RCC.LTDCFreq_Value=64000000 RCC.MCO1PinFreq_Value=64000000 -RCC.MCO2PinFreq_Value=280000000 +RCC.MCO2PinFreq_Value=160000000 RCC.PLL2FRACN=0 RCC.PLL3FRACN=0 RCC.PLLFRACN=0 RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE RCC.QSPICLockSelection=RCC_OSPICLKSOURCE_D1HCLK -RCC.QSPIFreq_Value=280000000 +RCC.QSPIFreq_Value=160000000 RCC.RCC_MCO1Source=RCC_MCO1SOURCE_HSI RCC.RCC_MCO2Source=RCC_MCO2SOURCE_SYSCLK RCC.RCC_MCODiv1=RCC_MCODIV_1 @@ -503,39 +505,39 @@ RCC.RNGCLockSelection=RCC_RNGCLKSOURCE_HSI48 RCC.RNGFreq_Value=48000000 RCC.RTCFreq_Value=32000 RCC.SAI1CLockSelection=RCC_SAI1CLKSOURCE_PLL -RCC.SAI1Freq_Value=140000000 -RCC.SAI2AFreq_Value=140000000 +RCC.SAI1Freq_Value=80000000 +RCC.SAI2AFreq_Value=80000000 RCC.SAI2BCLockSelection=RCC_SAI2BCLKSOURCE_PLL -RCC.SAI2BFreq_Value=140000000 +RCC.SAI2BFreq_Value=80000000 RCC.SDMMC1CLockSelection=RCC_SDMMCCLKSOURCE_PLL2 -RCC.SDMMCFreq_Value=280000000 +RCC.SDMMCFreq_Value=160000000 RCC.SPDIFCLockSelection=RCC_SPDIFRXCLKSOURCE_PLL -RCC.SPDIFRXFreq_Value=140000000 +RCC.SPDIFRXFreq_Value=80000000 RCC.SPI123CLockSelection=RCC_SPI123CLKSOURCE_PLL -RCC.SPI123Freq_Value=140000000 -RCC.SPI45Freq_Value=140000000 +RCC.SPI123Freq_Value=80000000 +RCC.SPI45Freq_Value=80000000 RCC.SPI6CLockSelection=RCC_SPI6CLKSOURCE_D3PCLK1 -RCC.SPI6Freq_Value=140000000 +RCC.SPI6Freq_Value=80000000 RCC.SRDPPRE=RCC_APB4_DIV2 RCC.SWPCLockSelection=RCC_SWPMI1CLKSOURCE_D2PCLK1 -RCC.SWPMI1Freq_Value=140000000 -RCC.SYSCLKFreq_VALUE=280000000 +RCC.SWPMI1Freq_Value=80000000 +RCC.SYSCLKFreq_VALUE=160000000 RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK RCC.Spi45ClockSelection=RCC_SPI45CLKSOURCE_D2PCLK1 -RCC.Tim1OutputFreq_Value=280000000 -RCC.Tim2OutputFreq_Value=280000000 -RCC.TraceFreq_Value=140000000 +RCC.Tim1OutputFreq_Value=160000000 +RCC.Tim2OutputFreq_Value=160000000 +RCC.TraceFreq_Value=160000000 RCC.USART16CLockSelection=RCC_USART16910CLKSOURCE_D2PCLK2 -RCC.USART16Freq_Value=140000000 +RCC.USART16Freq_Value=80000000 RCC.USART234578CLockSelection=RCC_USART234578CLKSOURCE_D2PCLK1 -RCC.USART234578Freq_Value=140000000 +RCC.USART234578Freq_Value=80000000 RCC.USBCLockSelection=RCC_USBCLKSOURCE_HSI48 RCC.USBFreq_Value=48000000 -RCC.VCO1OutputFreq_Value=560000000 -RCC.VCO2OutputFreq_Value=560000000 +RCC.VCO1OutputFreq_Value=320000000 +RCC.VCO2OutputFreq_Value=320000000 RCC.VCO3OutputFreq_Value=192000000 -RCC.VCOInput1Freq_Value=8000000 -RCC.VCOInput2Freq_Value=8000000 +RCC.VCOInput1Freq_Value=16000000 +RCC.VCOInput2Freq_Value=16000000 RCC.VCOInput3Freq_Value=16000000 RCC.WatchDogFreq_Value=32000 SH.FMC_A0.0=FMC_A0,13b-sda1 diff --git a/Software/STM32H7A3ZITX_FLASH.ld b/Software/STM32H7A3ZITX_FLASH.ld new file mode 100644 index 0000000..10f4fb5 --- /dev/null +++ b/Software/STM32H7A3ZITX_FLASH.ld @@ -0,0 +1,179 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld +** +** Author : STM32CubeIDE +** +** Abstract : Linker script for STM32H7 series +** 2048Kbytes FLASH and 1376Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +***************************************************************************** +** @attention +** +** Copyright (c) 2024 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +**************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ + ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 2048K + DTCMRAM1 (xrw) : ORIGIN = 0x20000000, LENGTH = 64K + DTCMRAM2 (xrw) : ORIGIN = 0x20010000, LENGTH = 64K + RAM (xrw) : ORIGIN = 0x24000000, LENGTH = 1024K + RAM_CD (xrw) : ORIGIN = 0x30000000, LENGTH = 128K + RAM_SRD (xrw) : ORIGIN = 0x38000000, LENGTH = 32K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >FLASH + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/Software/STM32H7A3ZITX_RAM.ld b/Software/STM32H7A3ZITX_RAM.ld new file mode 100644 index 0000000..bd86040 --- /dev/null +++ b/Software/STM32H7A3ZITX_RAM.ld @@ -0,0 +1,178 @@ +/* +****************************************************************************** +** +** File : LinkerScript.ld (debug in RAM dedicated) +** +** Author : STM32CubeIDE +** +** Abstract : Linker script for STM32H7 series +** 1024Kbytes RAM_EXEC and 352Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +***************************************************************************** +** @attention +** +** Copyright (c) 2024 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +**************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM_EXEC) + LENGTH(RAM_EXEC); /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ + ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K + RAM_EXEC (xrw) : ORIGIN = 0x24000000, LENGTH = 1024K + DTCMRAM1 (xrw) : ORIGIN = 0x20000000, LENGTH = 64K + DTCMRAM2 (xrw) : ORIGIN = 0x20010000, LENGTH = 64K + RAM_CD (xrw) : ORIGIN = 0x30000000, LENGTH = 128K + RAM_SRD (xrw) : ORIGIN = 0x38000000, LENGTH = 32K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into RAM_EXEC */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >RAM_EXEC + + /* The program code and other data goes into RAM_EXEC */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >RAM_EXEC + + /* Constant data goes into RAM_EXEC */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >RAM_EXEC + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >RAM_EXEC + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >RAM_EXEC + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >RAM_EXEC + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >RAM_EXEC + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >RAM_EXEC + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM_EXEC + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM_EXEC + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM_EXEC + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/Software/TouchGFX/ApplicationTemplate.touchgfx.part b/Software/TouchGFX/ApplicationTemplate.touchgfx.part new file mode 100644 index 0000000..16b99d8 --- /dev/null +++ b/Software/TouchGFX/ApplicationTemplate.touchgfx.part @@ -0,0 +1,30 @@ + +{ + "Application": { + "Name": "FT23_Charger", + "TouchGfxPath": "../Middlewares/ST/touchgfx", + "AvailableColorDepths": [ 24 ], + "AvailableLCDs": + { + "24": "LCD24bpp" + }, + "AvailableResolutions": [ + { + "Width": 1024, + "Height": 600 + } + ], + "PostGenerateTargetCommand": "touchgfx update_project", + "Family": "STM32H7", + "SubFamily": "STM32H7A3/7B3", + "Platform": "m7", + "Toolchain": "STM32CubeIDE", + "ProjectFile": "../FT23_Charger.ioc", + "OptionalComponentsRoot": "../Middlewares/ST/touchgfx_components", + "OptionalComponents": [ + ], + "AdditionalFeatures": [ + ], + }, + "Version": "4.21.0" +} diff --git a/Software/build/FT23_Charger.map b/Software/build/FT23_Charger.map index d998bd2..b309b25 100644 --- a/Software/build/FT23_Charger.map +++ b/Software/build/FT23_Charger.map @@ -1031,7 +1031,7 @@ Discarded input sections .text.HAL_I2C_MspDeInit 0x00000000 0x3c build/debug/stm32h7xx_hal_msp.o .text.HAL_LTDC_MspDeInit - 0x00000000 0x7c build/debug/stm32h7xx_hal_msp.o + 0x00000000 0x80 build/debug/stm32h7xx_hal_msp.o .text.HAL_UART_MspDeInit 0x00000000 0x58 build/debug/stm32h7xx_hal_msp.o .text.HAL_PCD_MspDeInit @@ -2343,7 +2343,7 @@ LOAD /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/crtn.o 0x08000000 g_pfnVectors 0x080002ac . = ALIGN (0x4) -.text 0x080002ac 0x57f0 +.text 0x080002ac 0x581c 0x080002ac . = ALIGN (0x4) *(.text) .text 0x080002ac 0x88 /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/crtbegin.o @@ -2363,593 +2363,595 @@ LOAD /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/crtn.o .text.MX_FDCAN1_Init 0x08000800 0x60 build/debug/main.o .text.MX_FMC_Init - 0x08000860 0xd8 build/debug/main.o + 0x08000860 0xec build/debug/main.o .text.MX_I2C4_Init - 0x08000938 0x54 build/debug/main.o + 0x0800094c 0x54 build/debug/main.o .text.MX_USART10_UART_Init - 0x0800098c 0x60 build/debug/main.o + 0x080009a0 0x60 build/debug/main.o .text.MX_USB_OTG_HS_PCD_Init - 0x080009ec 0x38 build/debug/main.o + 0x08000a00 0x38 build/debug/main.o .text.MX_UART5_Init - 0x08000a24 0x60 build/debug/main.o + 0x08000a38 0x60 build/debug/main.o .text.MX_LTDC_Init - 0x08000a84 0xbc build/debug/main.o + 0x08000a98 0xb0 build/debug/main.o .text.MX_CRC_Init - 0x08000b40 0x2c build/debug/main.o + 0x08000b48 0x2c build/debug/main.o .text.SystemClock_Config - 0x08000b6c 0xbc build/debug/main.o - 0x08000b6c SystemClock_Config - .text.main 0x08000c28 0x5c build/debug/main.o - 0x08000c28 main + 0x08000b74 0xc0 build/debug/main.o + 0x08000b74 SystemClock_Config + .text.main 0x08000c34 0x5c build/debug/main.o + 0x08000c34 main .text.HAL_InitTick - 0x08000c84 0x50 build/debug/stm32h7xx_hal.o - 0x08000c84 HAL_InitTick + 0x08000c90 0x50 build/debug/stm32h7xx_hal.o + 0x08000c90 HAL_InitTick .text.HAL_Init - 0x08000cd4 0x5c build/debug/stm32h7xx_hal.o - 0x08000cd4 HAL_Init + 0x08000ce0 0x5c build/debug/stm32h7xx_hal.o + 0x08000ce0 HAL_Init .text.HAL_IncTick - 0x08000d30 0x18 build/debug/stm32h7xx_hal.o - 0x08000d30 HAL_IncTick + 0x08000d3c 0x18 build/debug/stm32h7xx_hal.o + 0x08000d3c HAL_IncTick .text.HAL_GetTick - 0x08000d48 0xc build/debug/stm32h7xx_hal.o - 0x08000d48 HAL_GetTick + 0x08000d54 0xc build/debug/stm32h7xx_hal.o + 0x08000d54 HAL_GetTick .text.HAL_Delay - 0x08000d54 0x28 build/debug/stm32h7xx_hal.o - 0x08000d54 HAL_Delay + 0x08000d60 0x28 build/debug/stm32h7xx_hal.o + 0x08000d60 HAL_Delay .text.__NVIC_EnableIRQ - 0x08000d7c 0x1c build/debug/stm32h7xx_hal_cortex.o + 0x08000d88 0x1c build/debug/stm32h7xx_hal_cortex.o .text.__NVIC_SetPriority - 0x08000d98 0x24 build/debug/stm32h7xx_hal_cortex.o + 0x08000da4 0x24 build/debug/stm32h7xx_hal_cortex.o .text.NVIC_EncodePriority - 0x08000dbc 0x3e build/debug/stm32h7xx_hal_cortex.o - *fill* 0x08000dfa 0x2 + 0x08000dc8 0x3e build/debug/stm32h7xx_hal_cortex.o + *fill* 0x08000e06 0x2 .text.HAL_NVIC_SetPriorityGrouping - 0x08000dfc 0x24 build/debug/stm32h7xx_hal_cortex.o - 0x08000dfc HAL_NVIC_SetPriorityGrouping + 0x08000e08 0x24 build/debug/stm32h7xx_hal_cortex.o + 0x08000e08 HAL_NVIC_SetPriorityGrouping .text.HAL_NVIC_SetPriority - 0x08000e20 0x20 build/debug/stm32h7xx_hal_cortex.o - 0x08000e20 HAL_NVIC_SetPriority + 0x08000e2c 0x20 build/debug/stm32h7xx_hal_cortex.o + 0x08000e2c HAL_NVIC_SetPriority .text.HAL_NVIC_EnableIRQ - 0x08000e40 0x8 build/debug/stm32h7xx_hal_cortex.o - 0x08000e40 HAL_NVIC_EnableIRQ + 0x08000e4c 0x8 build/debug/stm32h7xx_hal_cortex.o + 0x08000e4c HAL_NVIC_EnableIRQ .text.HAL_SYSTICK_Config - 0x08000e48 0x28 build/debug/stm32h7xx_hal_cortex.o - 0x08000e48 HAL_SYSTICK_Config + 0x08000e54 0x28 build/debug/stm32h7xx_hal_cortex.o + 0x08000e54 HAL_SYSTICK_Config .text.HAL_CRC_Init - 0x08000e70 0x80 build/debug/stm32h7xx_hal_crc.o - 0x08000e70 HAL_CRC_Init + 0x08000e7c 0x80 build/debug/stm32h7xx_hal_crc.o + 0x08000e7c HAL_CRC_Init .text.HAL_CRCEx_Polynomial_Set - 0x08000ef0 0xc4 build/debug/stm32h7xx_hal_crc_ex.o - 0x08000ef0 HAL_CRCEx_Polynomial_Set + 0x08000efc 0xc4 build/debug/stm32h7xx_hal_crc_ex.o + 0x08000efc HAL_CRCEx_Polynomial_Set .text.FDCAN_CalcultateRamBlockAddresses - 0x08000fb4 0x1d4 build/debug/stm32h7xx_hal_fdcan.o + 0x08000fc0 0x1d4 build/debug/stm32h7xx_hal_fdcan.o .text.HAL_FDCAN_Init - 0x08001188 0x294 build/debug/stm32h7xx_hal_fdcan.o - 0x08001188 HAL_FDCAN_Init + 0x08001194 0x294 build/debug/stm32h7xx_hal_fdcan.o + 0x08001194 HAL_FDCAN_Init .text.HAL_FDCAN_ClockCalibrationCallback - 0x0800141c 0x2 build/debug/stm32h7xx_hal_fdcan.o - 0x0800141c HAL_FDCAN_ClockCalibrationCallback - .text.HAL_FDCAN_TxEventFifoCallback - 0x0800141e 0x2 build/debug/stm32h7xx_hal_fdcan.o - 0x0800141e HAL_FDCAN_TxEventFifoCallback - .text.HAL_FDCAN_RxFifo0Callback - 0x08001420 0x2 build/debug/stm32h7xx_hal_fdcan.o - 0x08001420 HAL_FDCAN_RxFifo0Callback - .text.HAL_FDCAN_RxFifo1Callback - 0x08001422 0x2 build/debug/stm32h7xx_hal_fdcan.o - 0x08001422 HAL_FDCAN_RxFifo1Callback - .text.HAL_FDCAN_TxFifoEmptyCallback - 0x08001424 0x2 build/debug/stm32h7xx_hal_fdcan.o - 0x08001424 HAL_FDCAN_TxFifoEmptyCallback - .text.HAL_FDCAN_TxBufferCompleteCallback - 0x08001426 0x2 build/debug/stm32h7xx_hal_fdcan.o - 0x08001426 HAL_FDCAN_TxBufferCompleteCallback - .text.HAL_FDCAN_TxBufferAbortCallback 0x08001428 0x2 build/debug/stm32h7xx_hal_fdcan.o - 0x08001428 HAL_FDCAN_TxBufferAbortCallback - .text.HAL_FDCAN_RxBufferNewMessageCallback + 0x08001428 HAL_FDCAN_ClockCalibrationCallback + .text.HAL_FDCAN_TxEventFifoCallback 0x0800142a 0x2 build/debug/stm32h7xx_hal_fdcan.o - 0x0800142a HAL_FDCAN_RxBufferNewMessageCallback - .text.HAL_FDCAN_TimestampWraparoundCallback + 0x0800142a HAL_FDCAN_TxEventFifoCallback + .text.HAL_FDCAN_RxFifo0Callback 0x0800142c 0x2 build/debug/stm32h7xx_hal_fdcan.o - 0x0800142c HAL_FDCAN_TimestampWraparoundCallback - .text.HAL_FDCAN_TimeoutOccurredCallback + 0x0800142c HAL_FDCAN_RxFifo0Callback + .text.HAL_FDCAN_RxFifo1Callback 0x0800142e 0x2 build/debug/stm32h7xx_hal_fdcan.o - 0x0800142e HAL_FDCAN_TimeoutOccurredCallback - .text.HAL_FDCAN_HighPriorityMessageCallback + 0x0800142e HAL_FDCAN_RxFifo1Callback + .text.HAL_FDCAN_TxFifoEmptyCallback 0x08001430 0x2 build/debug/stm32h7xx_hal_fdcan.o - 0x08001430 HAL_FDCAN_HighPriorityMessageCallback - .text.HAL_FDCAN_ErrorCallback + 0x08001430 HAL_FDCAN_TxFifoEmptyCallback + .text.HAL_FDCAN_TxBufferCompleteCallback 0x08001432 0x2 build/debug/stm32h7xx_hal_fdcan.o - 0x08001432 HAL_FDCAN_ErrorCallback - .text.HAL_FDCAN_ErrorStatusCallback + 0x08001432 HAL_FDCAN_TxBufferCompleteCallback + .text.HAL_FDCAN_TxBufferAbortCallback 0x08001434 0x2 build/debug/stm32h7xx_hal_fdcan.o - 0x08001434 HAL_FDCAN_ErrorStatusCallback - .text.HAL_FDCAN_TT_ScheduleSyncCallback + 0x08001434 HAL_FDCAN_TxBufferAbortCallback + .text.HAL_FDCAN_RxBufferNewMessageCallback 0x08001436 0x2 build/debug/stm32h7xx_hal_fdcan.o - 0x08001436 HAL_FDCAN_TT_ScheduleSyncCallback - .text.HAL_FDCAN_TT_TimeMarkCallback + 0x08001436 HAL_FDCAN_RxBufferNewMessageCallback + .text.HAL_FDCAN_TimestampWraparoundCallback 0x08001438 0x2 build/debug/stm32h7xx_hal_fdcan.o - 0x08001438 HAL_FDCAN_TT_TimeMarkCallback - .text.HAL_FDCAN_TT_StopWatchCallback + 0x08001438 HAL_FDCAN_TimestampWraparoundCallback + .text.HAL_FDCAN_TimeoutOccurredCallback 0x0800143a 0x2 build/debug/stm32h7xx_hal_fdcan.o - 0x0800143a HAL_FDCAN_TT_StopWatchCallback - .text.HAL_FDCAN_TT_GlobalTimeCallback + 0x0800143a HAL_FDCAN_TimeoutOccurredCallback + .text.HAL_FDCAN_HighPriorityMessageCallback 0x0800143c 0x2 build/debug/stm32h7xx_hal_fdcan.o - 0x0800143c HAL_FDCAN_TT_GlobalTimeCallback - *fill* 0x0800143e 0x2 + 0x0800143c HAL_FDCAN_HighPriorityMessageCallback + .text.HAL_FDCAN_ErrorCallback + 0x0800143e 0x2 build/debug/stm32h7xx_hal_fdcan.o + 0x0800143e HAL_FDCAN_ErrorCallback + .text.HAL_FDCAN_ErrorStatusCallback + 0x08001440 0x2 build/debug/stm32h7xx_hal_fdcan.o + 0x08001440 HAL_FDCAN_ErrorStatusCallback + .text.HAL_FDCAN_TT_ScheduleSyncCallback + 0x08001442 0x2 build/debug/stm32h7xx_hal_fdcan.o + 0x08001442 HAL_FDCAN_TT_ScheduleSyncCallback + .text.HAL_FDCAN_TT_TimeMarkCallback + 0x08001444 0x2 build/debug/stm32h7xx_hal_fdcan.o + 0x08001444 HAL_FDCAN_TT_TimeMarkCallback + .text.HAL_FDCAN_TT_StopWatchCallback + 0x08001446 0x2 build/debug/stm32h7xx_hal_fdcan.o + 0x08001446 HAL_FDCAN_TT_StopWatchCallback + .text.HAL_FDCAN_TT_GlobalTimeCallback + 0x08001448 0x2 build/debug/stm32h7xx_hal_fdcan.o + 0x08001448 HAL_FDCAN_TT_GlobalTimeCallback + *fill* 0x0800144a 0x2 .text.HAL_FDCAN_IRQHandler - 0x08001440 0x320 build/debug/stm32h7xx_hal_fdcan.o - 0x08001440 HAL_FDCAN_IRQHandler + 0x0800144c 0x320 build/debug/stm32h7xx_hal_fdcan.o + 0x0800144c HAL_FDCAN_IRQHandler .text.HAL_GPIO_Init - 0x08001760 0x220 build/debug/stm32h7xx_hal_gpio.o - 0x08001760 HAL_GPIO_Init + 0x0800176c 0x220 build/debug/stm32h7xx_hal_gpio.o + 0x0800176c HAL_GPIO_Init .text.HAL_GPIO_WritePin - 0x08001980 0xc build/debug/stm32h7xx_hal_gpio.o - 0x08001980 HAL_GPIO_WritePin + 0x0800198c 0xc build/debug/stm32h7xx_hal_gpio.o + 0x0800198c HAL_GPIO_WritePin .text.HAL_I2C_Init - 0x0800198c 0xc8 build/debug/stm32h7xx_hal_i2c.o - 0x0800198c HAL_I2C_Init + 0x08001998 0xc8 build/debug/stm32h7xx_hal_i2c.o + 0x08001998 HAL_I2C_Init .text.HAL_I2CEx_ConfigAnalogFilter - 0x08001a54 0x5a build/debug/stm32h7xx_hal_i2c_ex.o - 0x08001a54 HAL_I2CEx_ConfigAnalogFilter + 0x08001a60 0x5a build/debug/stm32h7xx_hal_i2c_ex.o + 0x08001a60 HAL_I2CEx_ConfigAnalogFilter .text.HAL_I2CEx_ConfigDigitalFilter - 0x08001aae 0x56 build/debug/stm32h7xx_hal_i2c_ex.o - 0x08001aae HAL_I2CEx_ConfigDigitalFilter + 0x08001aba 0x56 build/debug/stm32h7xx_hal_i2c_ex.o + 0x08001aba HAL_I2CEx_ConfigDigitalFilter .text.LTDC_SetConfig - 0x08001b04 0x1a8 build/debug/stm32h7xx_hal_ltdc.o + 0x08001b10 0x1a8 build/debug/stm32h7xx_hal_ltdc.o .text.HAL_LTDC_Init - 0x08001cac 0xbc build/debug/stm32h7xx_hal_ltdc.o - 0x08001cac HAL_LTDC_Init + 0x08001cb8 0xbc build/debug/stm32h7xx_hal_ltdc.o + 0x08001cb8 HAL_LTDC_Init .text.HAL_LTDC_ErrorCallback - 0x08001d68 0x2 build/debug/stm32h7xx_hal_ltdc.o - 0x08001d68 HAL_LTDC_ErrorCallback + 0x08001d74 0x2 build/debug/stm32h7xx_hal_ltdc.o + 0x08001d74 HAL_LTDC_ErrorCallback .text.HAL_LTDC_LineEventCallback - 0x08001d6a 0x2 build/debug/stm32h7xx_hal_ltdc.o - 0x08001d6a HAL_LTDC_LineEventCallback + 0x08001d76 0x2 build/debug/stm32h7xx_hal_ltdc.o + 0x08001d76 HAL_LTDC_LineEventCallback .text.HAL_LTDC_ReloadEventCallback - 0x08001d6c 0x2 build/debug/stm32h7xx_hal_ltdc.o - 0x08001d6c HAL_LTDC_ReloadEventCallback + 0x08001d78 0x2 build/debug/stm32h7xx_hal_ltdc.o + 0x08001d78 HAL_LTDC_ReloadEventCallback .text.HAL_LTDC_IRQHandler - 0x08001d6e 0xda build/debug/stm32h7xx_hal_ltdc.o - 0x08001d6e HAL_LTDC_IRQHandler + 0x08001d7a 0xda build/debug/stm32h7xx_hal_ltdc.o + 0x08001d7a HAL_LTDC_IRQHandler .text.HAL_LTDC_ConfigLayer - 0x08001e48 0x68 build/debug/stm32h7xx_hal_ltdc.o - 0x08001e48 HAL_LTDC_ConfigLayer + 0x08001e54 0x68 build/debug/stm32h7xx_hal_ltdc.o + 0x08001e54 HAL_LTDC_ConfigLayer .text.HAL_LTDC_ProgramLineEvent - 0x08001eb0 0x48 build/debug/stm32h7xx_hal_ltdc.o - 0x08001eb0 HAL_LTDC_ProgramLineEvent + 0x08001ebc 0x48 build/debug/stm32h7xx_hal_ltdc.o + 0x08001ebc HAL_LTDC_ProgramLineEvent .text.HAL_FMC_MspInit - 0x08001ef8 0x144 build/debug/stm32h7xx_hal_msp.o + 0x08001f04 0x144 build/debug/stm32h7xx_hal_msp.o .text.HAL_MspInit - 0x0800203c 0x24 build/debug/stm32h7xx_hal_msp.o - 0x0800203c HAL_MspInit + 0x08002048 0x24 build/debug/stm32h7xx_hal_msp.o + 0x08002048 HAL_MspInit .text.HAL_CRC_MspInit - 0x08002060 0x34 build/debug/stm32h7xx_hal_msp.o - 0x08002060 HAL_CRC_MspInit + 0x0800206c 0x34 build/debug/stm32h7xx_hal_msp.o + 0x0800206c HAL_CRC_MspInit .text.HAL_FDCAN_MspInit - 0x08002094 0xd4 build/debug/stm32h7xx_hal_msp.o - 0x08002094 HAL_FDCAN_MspInit + 0x080020a0 0xd4 build/debug/stm32h7xx_hal_msp.o + 0x080020a0 HAL_FDCAN_MspInit .text.HAL_I2C_MspInit - 0x08002168 0x98 build/debug/stm32h7xx_hal_msp.o - 0x08002168 HAL_I2C_MspInit + 0x08002174 0x98 build/debug/stm32h7xx_hal_msp.o + 0x08002174 HAL_I2C_MspInit .text.HAL_LTDC_MspInit - 0x08002200 0x240 build/debug/stm32h7xx_hal_msp.o - 0x08002200 HAL_LTDC_MspInit + 0x0800220c 0x250 build/debug/stm32h7xx_hal_msp.o + 0x0800220c HAL_LTDC_MspInit .text.HAL_UART_MspInit - 0x08002440 0x10c build/debug/stm32h7xx_hal_msp.o - 0x08002440 HAL_UART_MspInit + 0x0800245c 0x10c build/debug/stm32h7xx_hal_msp.o + 0x0800245c HAL_UART_MspInit .text.HAL_PCD_MspInit - 0x0800254c 0xb8 build/debug/stm32h7xx_hal_msp.o - 0x0800254c HAL_PCD_MspInit + 0x08002568 0xb8 build/debug/stm32h7xx_hal_msp.o + 0x08002568 HAL_PCD_MspInit .text.HAL_SDRAM_MspInit - 0x08002604 0x8 build/debug/stm32h7xx_hal_msp.o - 0x08002604 HAL_SDRAM_MspInit + 0x08002620 0x8 build/debug/stm32h7xx_hal_msp.o + 0x08002620 HAL_SDRAM_MspInit .text.HAL_PCD_Init - 0x0800260c 0x102 build/debug/stm32h7xx_hal_pcd.o - 0x0800260c HAL_PCD_Init - *fill* 0x0800270e 0x2 + 0x08002628 0x102 build/debug/stm32h7xx_hal_pcd.o + 0x08002628 HAL_PCD_Init + *fill* 0x0800272a 0x2 .text.HAL_PCDEx_ActivateLPM - 0x08002710 0x28 build/debug/stm32h7xx_hal_pcd_ex.o - 0x08002710 HAL_PCDEx_ActivateLPM + 0x0800272c 0x28 build/debug/stm32h7xx_hal_pcd_ex.o + 0x0800272c HAL_PCDEx_ActivateLPM .text.HAL_PWREx_ConfigSupply - 0x08002738 0x54 build/debug/stm32h7xx_hal_pwr_ex.o - 0x08002738 HAL_PWREx_ConfigSupply + 0x08002754 0x54 build/debug/stm32h7xx_hal_pwr_ex.o + 0x08002754 HAL_PWREx_ConfigSupply .text.HAL_PWREx_EnableUSBVoltageDetector - 0x0800278c 0x10 build/debug/stm32h7xx_hal_pwr_ex.o - 0x0800278c HAL_PWREx_EnableUSBVoltageDetector + 0x080027a8 0x10 build/debug/stm32h7xx_hal_pwr_ex.o + 0x080027a8 HAL_PWREx_EnableUSBVoltageDetector .text.HAL_RCC_OscConfig - 0x0800279c 0x660 build/debug/stm32h7xx_hal_rcc.o - 0x0800279c HAL_RCC_OscConfig + 0x080027b8 0x660 build/debug/stm32h7xx_hal_rcc.o + 0x080027b8 HAL_RCC_OscConfig .text.HAL_RCC_GetSysClockFreq - 0x08002dfc 0x1f8 build/debug/stm32h7xx_hal_rcc.o - 0x08002dfc HAL_RCC_GetSysClockFreq + 0x08002e18 0x1f8 build/debug/stm32h7xx_hal_rcc.o + 0x08002e18 HAL_RCC_GetSysClockFreq .text.HAL_RCC_ClockConfig - 0x08002ff4 0x294 build/debug/stm32h7xx_hal_rcc.o - 0x08002ff4 HAL_RCC_ClockConfig + 0x08003010 0x294 build/debug/stm32h7xx_hal_rcc.o + 0x08003010 HAL_RCC_ClockConfig .text.HAL_RCC_GetHCLKFreq - 0x08003288 0x44 build/debug/stm32h7xx_hal_rcc.o - 0x08003288 HAL_RCC_GetHCLKFreq + 0x080032a4 0x44 build/debug/stm32h7xx_hal_rcc.o + 0x080032a4 HAL_RCC_GetHCLKFreq .text.HAL_RCC_GetPCLK1Freq - 0x080032cc 0x24 build/debug/stm32h7xx_hal_rcc.o - 0x080032cc HAL_RCC_GetPCLK1Freq + 0x080032e8 0x24 build/debug/stm32h7xx_hal_rcc.o + 0x080032e8 HAL_RCC_GetPCLK1Freq .text.HAL_RCC_GetPCLK2Freq - 0x080032f0 0x24 build/debug/stm32h7xx_hal_rcc.o - 0x080032f0 HAL_RCC_GetPCLK2Freq + 0x0800330c 0x24 build/debug/stm32h7xx_hal_rcc.o + 0x0800330c HAL_RCC_GetPCLK2Freq .text.RCCEx_PLL2_Config - 0x08003314 0x108 build/debug/stm32h7xx_hal_rcc_ex.o + 0x08003330 0x108 build/debug/stm32h7xx_hal_rcc_ex.o .text.RCCEx_PLL3_Config - 0x0800341c 0x108 build/debug/stm32h7xx_hal_rcc_ex.o + 0x08003438 0x108 build/debug/stm32h7xx_hal_rcc_ex.o .text.HAL_RCCEx_PeriphCLKConfig - 0x08003524 0xb1c build/debug/stm32h7xx_hal_rcc_ex.o - 0x08003524 HAL_RCCEx_PeriphCLKConfig + 0x08003540 0xb1c build/debug/stm32h7xx_hal_rcc_ex.o + 0x08003540 HAL_RCCEx_PeriphCLKConfig .text.HAL_RCCEx_GetD3PCLK1Freq - 0x08004040 0x24 build/debug/stm32h7xx_hal_rcc_ex.o - 0x08004040 HAL_RCCEx_GetD3PCLK1Freq + 0x0800405c 0x24 build/debug/stm32h7xx_hal_rcc_ex.o + 0x0800405c HAL_RCCEx_GetD3PCLK1Freq .text.HAL_RCCEx_GetPLL2ClockFreq - 0x08004064 0x200 build/debug/stm32h7xx_hal_rcc_ex.o - 0x08004064 HAL_RCCEx_GetPLL2ClockFreq + 0x08004080 0x200 build/debug/stm32h7xx_hal_rcc_ex.o + 0x08004080 HAL_RCCEx_GetPLL2ClockFreq .text.HAL_RCCEx_GetPLL3ClockFreq - 0x08004264 0x200 build/debug/stm32h7xx_hal_rcc_ex.o - 0x08004264 HAL_RCCEx_GetPLL3ClockFreq + 0x08004280 0x200 build/debug/stm32h7xx_hal_rcc_ex.o + 0x08004280 HAL_RCCEx_GetPLL3ClockFreq .text.HAL_SDRAM_Init - 0x08004464 0x50 build/debug/stm32h7xx_hal_sdram.o - 0x08004464 HAL_SDRAM_Init + 0x08004480 0x50 build/debug/stm32h7xx_hal_sdram.o + 0x08004480 HAL_SDRAM_Init .text.HAL_SDRAM_RefreshErrorCallback - 0x080044b4 0x2 build/debug/stm32h7xx_hal_sdram.o - 0x080044b4 HAL_SDRAM_RefreshErrorCallback + 0x080044d0 0x2 build/debug/stm32h7xx_hal_sdram.o + 0x080044d0 HAL_SDRAM_RefreshErrorCallback .text.HAL_SDRAM_IRQHandler - 0x080044b6 0x20 build/debug/stm32h7xx_hal_sdram.o - 0x080044b6 HAL_SDRAM_IRQHandler + 0x080044d2 0x20 build/debug/stm32h7xx_hal_sdram.o + 0x080044d2 HAL_SDRAM_IRQHandler .text.HAL_SDRAM_SendCommand - 0x080044d6 0x42 build/debug/stm32h7xx_hal_sdram.o - 0x080044d6 HAL_SDRAM_SendCommand + 0x080044f2 0x42 build/debug/stm32h7xx_hal_sdram.o + 0x080044f2 HAL_SDRAM_SendCommand .text.HAL_SDRAM_ProgramRefreshRate - 0x08004518 0x30 build/debug/stm32h7xx_hal_sdram.o - 0x08004518 HAL_SDRAM_ProgramRefreshRate + 0x08004534 0x30 build/debug/stm32h7xx_hal_sdram.o + 0x08004534 HAL_SDRAM_ProgramRefreshRate .text.UART_EndRxTransfer - 0x08004548 0x58 build/debug/stm32h7xx_hal_uart.o + 0x08004564 0x58 build/debug/stm32h7xx_hal_uart.o .text.UART_SetConfig - 0x080045a0 0x9f8 build/debug/stm32h7xx_hal_uart.o - 0x080045a0 UART_SetConfig + 0x080045bc 0x9f8 build/debug/stm32h7xx_hal_uart.o + 0x080045bc UART_SetConfig .text.UART_AdvFeatureConfig - 0x08004f98 0xca build/debug/stm32h7xx_hal_uart.o - 0x08004f98 UART_AdvFeatureConfig + 0x08004fb4 0xca build/debug/stm32h7xx_hal_uart.o + 0x08004fb4 UART_AdvFeatureConfig .text.UART_WaitOnFlagUntilTimeout - 0x08005062 0xa6 build/debug/stm32h7xx_hal_uart.o - 0x08005062 UART_WaitOnFlagUntilTimeout + 0x0800507e 0xa6 build/debug/stm32h7xx_hal_uart.o + 0x0800507e UART_WaitOnFlagUntilTimeout .text.UART_CheckIdleState - 0x08005108 0xca build/debug/stm32h7xx_hal_uart.o - 0x08005108 UART_CheckIdleState + 0x08005124 0xca build/debug/stm32h7xx_hal_uart.o + 0x08005124 UART_CheckIdleState .text.HAL_UART_Init - 0x080051d2 0x66 build/debug/stm32h7xx_hal_uart.o - 0x080051d2 HAL_UART_Init + 0x080051ee 0x66 build/debug/stm32h7xx_hal_uart.o + 0x080051ee HAL_UART_Init .text.UARTEx_SetNbDataToProcess - 0x08005238 0x4c build/debug/stm32h7xx_hal_uart_ex.o + 0x08005254 0x4c build/debug/stm32h7xx_hal_uart_ex.o .text.HAL_UARTEx_DisableFifoMode - 0x08005284 0x3e build/debug/stm32h7xx_hal_uart_ex.o - 0x08005284 HAL_UARTEx_DisableFifoMode + 0x080052a0 0x3e build/debug/stm32h7xx_hal_uart_ex.o + 0x080052a0 HAL_UARTEx_DisableFifoMode .text.HAL_UARTEx_SetTxFifoThreshold - 0x080052c2 0x4a build/debug/stm32h7xx_hal_uart_ex.o - 0x080052c2 HAL_UARTEx_SetTxFifoThreshold + 0x080052de 0x4a build/debug/stm32h7xx_hal_uart_ex.o + 0x080052de HAL_UARTEx_SetTxFifoThreshold .text.HAL_UARTEx_SetRxFifoThreshold - 0x0800530c 0x4a build/debug/stm32h7xx_hal_uart_ex.o - 0x0800530c HAL_UARTEx_SetRxFifoThreshold + 0x08005328 0x4a build/debug/stm32h7xx_hal_uart_ex.o + 0x08005328 HAL_UARTEx_SetRxFifoThreshold .text.NMI_Handler - 0x08005356 0x2 build/debug/stm32h7xx_it.o - 0x08005356 NMI_Handler + 0x08005372 0x2 build/debug/stm32h7xx_it.o + 0x08005372 NMI_Handler .text.HardFault_Handler - 0x08005358 0x2 build/debug/stm32h7xx_it.o - 0x08005358 HardFault_Handler + 0x08005374 0x2 build/debug/stm32h7xx_it.o + 0x08005374 HardFault_Handler .text.MemManage_Handler - 0x0800535a 0x2 build/debug/stm32h7xx_it.o - 0x0800535a MemManage_Handler + 0x08005376 0x2 build/debug/stm32h7xx_it.o + 0x08005376 MemManage_Handler .text.BusFault_Handler - 0x0800535c 0x2 build/debug/stm32h7xx_it.o - 0x0800535c BusFault_Handler + 0x08005378 0x2 build/debug/stm32h7xx_it.o + 0x08005378 BusFault_Handler .text.UsageFault_Handler - 0x0800535e 0x2 build/debug/stm32h7xx_it.o - 0x0800535e UsageFault_Handler + 0x0800537a 0x2 build/debug/stm32h7xx_it.o + 0x0800537a UsageFault_Handler .text.SVC_Handler - 0x08005360 0x2 build/debug/stm32h7xx_it.o - 0x08005360 SVC_Handler + 0x0800537c 0x2 build/debug/stm32h7xx_it.o + 0x0800537c SVC_Handler .text.DebugMon_Handler - 0x08005362 0x2 build/debug/stm32h7xx_it.o - 0x08005362 DebugMon_Handler + 0x0800537e 0x2 build/debug/stm32h7xx_it.o + 0x0800537e DebugMon_Handler .text.PendSV_Handler - 0x08005364 0x2 build/debug/stm32h7xx_it.o - 0x08005364 PendSV_Handler + 0x08005380 0x2 build/debug/stm32h7xx_it.o + 0x08005380 PendSV_Handler .text.SysTick_Handler - 0x08005366 0x8 build/debug/stm32h7xx_it.o - 0x08005366 SysTick_Handler - *fill* 0x0800536e 0x2 + 0x08005382 0x8 build/debug/stm32h7xx_it.o + 0x08005382 SysTick_Handler + *fill* 0x0800538a 0x2 .text.FDCAN1_IT0_IRQHandler - 0x08005370 0x10 build/debug/stm32h7xx_it.o - 0x08005370 FDCAN1_IT0_IRQHandler + 0x0800538c 0x10 build/debug/stm32h7xx_it.o + 0x0800538c FDCAN1_IT0_IRQHandler .text.FDCAN1_IT1_IRQHandler - 0x08005380 0x10 build/debug/stm32h7xx_it.o - 0x08005380 FDCAN1_IT1_IRQHandler + 0x0800539c 0x10 build/debug/stm32h7xx_it.o + 0x0800539c FDCAN1_IT1_IRQHandler .text.FMC_IRQHandler - 0x08005390 0x10 build/debug/stm32h7xx_it.o - 0x08005390 FMC_IRQHandler + 0x080053ac 0x10 build/debug/stm32h7xx_it.o + 0x080053ac FMC_IRQHandler .text.FDCAN_CAL_IRQHandler - 0x080053a0 0x10 build/debug/stm32h7xx_it.o - 0x080053a0 FDCAN_CAL_IRQHandler + 0x080053bc 0x10 build/debug/stm32h7xx_it.o + 0x080053bc FDCAN_CAL_IRQHandler .text.LTDC_IRQHandler - 0x080053b0 0x18 build/debug/stm32h7xx_it.o - 0x080053b0 LTDC_IRQHandler + 0x080053cc 0x18 build/debug/stm32h7xx_it.o + 0x080053cc LTDC_IRQHandler + .text.LTDC_ER_IRQHandler + 0x080053e4 0x10 build/debug/stm32h7xx_it.o + 0x080053e4 LTDC_ER_IRQHandler .text.FMC_SDRAM_Init - 0x080053c8 0x70 build/debug/stm32h7xx_ll_fmc.o - 0x080053c8 FMC_SDRAM_Init + 0x080053f4 0x70 build/debug/stm32h7xx_ll_fmc.o + 0x080053f4 FMC_SDRAM_Init .text.FMC_SDRAM_Timing_Init - 0x08005438 0xa8 build/debug/stm32h7xx_ll_fmc.o - 0x08005438 FMC_SDRAM_Timing_Init + 0x08005464 0xa8 build/debug/stm32h7xx_ll_fmc.o + 0x08005464 FMC_SDRAM_Timing_Init .text.FMC_SDRAM_SendCommand - 0x080054e0 0x2a build/debug/stm32h7xx_ll_fmc.o - 0x080054e0 FMC_SDRAM_SendCommand + 0x0800550c 0x2a build/debug/stm32h7xx_ll_fmc.o + 0x0800550c FMC_SDRAM_SendCommand .text.FMC_SDRAM_ProgramRefreshRate - 0x0800550a 0x10 build/debug/stm32h7xx_ll_fmc.o - 0x0800550a FMC_SDRAM_ProgramRefreshRate + 0x08005536 0x10 build/debug/stm32h7xx_ll_fmc.o + 0x08005536 FMC_SDRAM_ProgramRefreshRate .text.USB_CoreReset - 0x0800551a 0x4a build/debug/stm32h7xx_ll_usb.o + 0x08005546 0x4a build/debug/stm32h7xx_ll_usb.o .text.USB_CoreInit - 0x08005564 0xa4 build/debug/stm32h7xx_ll_usb.o - 0x08005564 USB_CoreInit + 0x08005590 0xa4 build/debug/stm32h7xx_ll_usb.o + 0x08005590 USB_CoreInit .text.USB_DisableGlobalInt - 0x08005608 0xc build/debug/stm32h7xx_ll_usb.o - 0x08005608 USB_DisableGlobalInt + 0x08005634 0xc build/debug/stm32h7xx_ll_usb.o + 0x08005634 USB_DisableGlobalInt .text.USB_FlushTxFifo - 0x08005614 0x4a build/debug/stm32h7xx_ll_usb.o - 0x08005614 USB_FlushTxFifo + 0x08005640 0x4a build/debug/stm32h7xx_ll_usb.o + 0x08005640 USB_FlushTxFifo .text.USB_FlushRxFifo - 0x0800565e 0x46 build/debug/stm32h7xx_ll_usb.o - 0x0800565e USB_FlushRxFifo + 0x0800568a 0x46 build/debug/stm32h7xx_ll_usb.o + 0x0800568a USB_FlushRxFifo .text.USB_SetDevSpeed - 0x080056a4 0xe build/debug/stm32h7xx_ll_usb.o - 0x080056a4 USB_SetDevSpeed - *fill* 0x080056b2 0x2 + 0x080056d0 0xe build/debug/stm32h7xx_ll_usb.o + 0x080056d0 USB_SetDevSpeed + *fill* 0x080056de 0x2 .text.USB_DevInit - 0x080056b4 0x190 build/debug/stm32h7xx_ll_usb.o - 0x080056b4 USB_DevInit + 0x080056e0 0x190 build/debug/stm32h7xx_ll_usb.o + 0x080056e0 USB_DevInit .text.USB_DevDisconnect - 0x08005844 0x1c build/debug/stm32h7xx_ll_usb.o - 0x08005844 USB_DevDisconnect + 0x08005870 0x1c build/debug/stm32h7xx_ll_usb.o + 0x08005870 USB_DevDisconnect .text.USB_GetMode - 0x08005860 0x8 build/debug/stm32h7xx_ll_usb.o - 0x08005860 USB_GetMode + 0x0800588c 0x8 build/debug/stm32h7xx_ll_usb.o + 0x0800588c USB_GetMode .text.USB_SetCurrentMode - 0x08005868 0x62 build/debug/stm32h7xx_ll_usb.o - 0x08005868 USB_SetCurrentMode - *fill* 0x080058ca 0x2 + 0x08005894 0x62 build/debug/stm32h7xx_ll_usb.o + 0x08005894 USB_SetCurrentMode + *fill* 0x080058f6 0x2 .text.SystemInit - 0x080058cc 0xd0 build/debug/system_stm32h7xx.o - 0x080058cc SystemInit + 0x080058f8 0xd0 build/debug/system_stm32h7xx.o + 0x080058f8 SystemInit .text.ExitRun0Mode - 0x0800599c 0x1c build/debug/system_stm32h7xx.o - 0x0800599c ExitRun0Mode + 0x080059c8 0x1c build/debug/system_stm32h7xx.o + 0x080059c8 ExitRun0Mode .text.Reset_Handler - 0x080059b8 0x54 build/debug/startup_stm32h7a3xx.o - 0x080059b8 Reset_Handler + 0x080059e4 0x54 build/debug/startup_stm32h7a3xx.o + 0x080059e4 Reset_Handler .text.Default_Handler - 0x08005a0c 0x2 build/debug/startup_stm32h7a3xx.o - 0x08005a0c RTC_Alarm_IRQHandler - 0x08005a0c EXTI2_IRQHandler - 0x08005a0c TIM8_CC_IRQHandler - 0x08005a0c UART8_IRQHandler - 0x08005a0c BDMA2_Channel1_IRQHandler - 0x08005a0c SPI4_IRQHandler - 0x08005a0c BDMA2_Channel0_IRQHandler - 0x08005a0c TIM1_CC_IRQHandler - 0x08005a0c DMA2_Stream5_IRQHandler - 0x08005a0c JPEG_IRQHandler - 0x08005a0c DMA1_Stream5_IRQHandler - 0x08005a0c EXTI3_IRQHandler - 0x08005a0c LPTIM4_IRQHandler - 0x08005a0c TIM8_TRG_COM_TIM14_IRQHandler - 0x08005a0c LPTIM2_IRQHandler - 0x08005a0c DFSDM1_FLT1_IRQHandler - 0x08005a0c DMAMUX2_OVR_IRQHandler - 0x08005a0c GFXMMU_IRQHandler - 0x08005a0c TIM8_UP_TIM13_IRQHandler - 0x08005a0c I2C3_ER_IRQHandler - 0x08005a0c DFSDM1_FLT2_IRQHandler - 0x08005a0c USART10_IRQHandler - 0x08005a0c MDMA_IRQHandler - 0x08005a0c LPTIM3_IRQHandler - 0x08005a0c BDMA2_Channel3_IRQHandler - 0x08005a0c HSEM1_IRQHandler - 0x08005a0c EXTI0_IRQHandler - 0x08005a0c I2C2_EV_IRQHandler - 0x08005a0c DAC2_IRQHandler - 0x08005a0c DMA1_Stream2_IRQHandler - 0x08005a0c FPU_IRQHandler - 0x08005a0c OTG_HS_WKUP_IRQHandler - 0x08005a0c LTDC_ER_IRQHandler - 0x08005a0c DMA2_Stream2_IRQHandler - 0x08005a0c SPI1_IRQHandler - 0x08005a0c OCTOSPI1_IRQHandler - 0x08005a0c TIM6_DAC_IRQHandler - 0x08005a0c BDMA2_Channel6_IRQHandler - 0x08005a0c DMA2_Stream3_IRQHandler - 0x08005a0c OCTOSPI2_IRQHandler - 0x08005a0c SAI2_IRQHandler - 0x08005a0c BDMA1_IRQHandler - 0x08005a0c DFSDM1_FLT3_IRQHandler - 0x08005a0c USART6_IRQHandler - 0x08005a0c TIM17_IRQHandler - 0x08005a0c USART3_IRQHandler - 0x08005a0c LPTIM5_IRQHandler - 0x08005a0c UART5_IRQHandler - 0x08005a0c DMA2_Stream0_IRQHandler - 0x08005a0c TIM4_IRQHandler - 0x08005a0c I2C1_EV_IRQHandler - 0x08005a0c DMA1_Stream6_IRQHandler - 0x08005a0c DMAMUX1_OVR_IRQHandler - 0x08005a0c DMA1_Stream1_IRQHandler - 0x08005a0c TIM16_IRQHandler - 0x08005a0c UART4_IRQHandler - 0x08005a0c TIM3_IRQHandler - 0x08005a0c RCC_IRQHandler - 0x08005a0c UART9_IRQHandler - 0x08005a0c TIM8_BRK_TIM12_IRQHandler - 0x08005a0c TIM1_TRG_COM_IRQHandler - 0x08005a0c Default_Handler - 0x08005a0c ECC_IRQHandler - 0x08005a0c BDMA2_Channel2_IRQHandler - 0x08005a0c CEC_IRQHandler - 0x08005a0c EXTI15_10_IRQHandler - 0x08005a0c DFSDM1_FLT4_IRQHandler - 0x08005a0c ADC_IRQHandler - 0x08005a0c DMA1_Stream7_IRQHandler - 0x08005a0c SPI5_IRQHandler - 0x08005a0c TIM7_IRQHandler - 0x08005a0c SDMMC1_IRQHandler - 0x08005a0c TIM5_IRQHandler - 0x08005a0c DMA2_Stream7_IRQHandler - 0x08005a0c TIM15_IRQHandler - 0x08005a0c I2C3_EV_IRQHandler - 0x08005a0c DFSDM2_IRQHandler - 0x08005a0c EXTI9_5_IRQHandler - 0x08005a0c RTC_WKUP_IRQHandler - 0x08005a0c SPDIF_RX_IRQHandler - 0x08005a0c PVD_PVM_IRQHandler - 0x08005a0c SPI2_IRQHandler - 0x08005a0c OTG_HS_EP1_IN_IRQHandler - 0x08005a0c DFSDM1_FLT5_IRQHandler - 0x08005a0c DMA1_Stream0_IRQHandler - 0x08005a0c CRS_IRQHandler - 0x08005a0c EXTI4_IRQHandler - 0x08005a0c DFSDM1_FLT6_IRQHandler - 0x08005a0c RNG_IRQHandler - 0x08005a0c FDCAN2_IT1_IRQHandler - 0x08005a0c COMP_IRQHandler - 0x08005a0c TIM1_UP_IRQHandler - 0x08005a0c OTG_HS_EP1_OUT_IRQHandler - 0x08005a0c WWDG_IRQHandler - 0x08005a0c SPI6_IRQHandler - 0x08005a0c MDIOS_IRQHandler - 0x08005a0c I2C4_EV_IRQHandler - 0x08005a0c FDCAN2_IT0_IRQHandler - 0x08005a0c LPUART1_IRQHandler - 0x08005a0c TIM2_IRQHandler - 0x08005a0c BDMA2_Channel5_IRQHandler - 0x08005a0c OTG_HS_IRQHandler - 0x08005a0c DMA2D_IRQHandler - 0x08005a0c TIM1_BRK_IRQHandler - 0x08005a0c EXTI1_IRQHandler - 0x08005a0c SDMMC2_IRQHandler - 0x08005a0c DTS_IRQHandler - 0x08005a0c UART7_IRQHandler - 0x08005a0c MDIOS_WKUP_IRQHandler - 0x08005a0c USART2_IRQHandler - 0x08005a0c DFSDM1_FLT0_IRQHandler - 0x08005a0c I2C2_ER_IRQHandler - 0x08005a0c DMA2_Stream1_IRQHandler - 0x08005a0c DFSDM1_FLT7_IRQHandler - 0x08005a0c FLASH_IRQHandler - 0x08005a0c DMA2_Stream4_IRQHandler - 0x08005a0c USART1_IRQHandler - 0x08005a0c SPI3_IRQHandler - 0x08005a0c WAKEUP_PIN_IRQHandler - 0x08005a0c DMA1_Stream4_IRQHandler - 0x08005a0c I2C1_ER_IRQHandler - 0x08005a0c BDMA2_Channel7_IRQHandler - 0x08005a0c SWPMI1_IRQHandler - 0x08005a0c LPTIM1_IRQHandler - 0x08005a0c DCMI_PSSI_IRQHandler - 0x08005a0c I2C4_ER_IRQHandler - 0x08005a0c DMA2_Stream6_IRQHandler - 0x08005a0c SAI1_IRQHandler - 0x08005a0c DMA1_Stream3_IRQHandler - 0x08005a0c RTC_TAMP_STAMP_CSS_LSE_IRQHandler - 0x08005a0c BDMA2_Channel4_IRQHandler - .text.memset 0x08005a0e 0x10 /usr/lib/gcc/arm-none-eabi/14.1.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memset.o) - 0x08005a0e memset - *fill* 0x08005a1e 0x2 + 0x08005a38 0x2 build/debug/startup_stm32h7a3xx.o + 0x08005a38 RTC_Alarm_IRQHandler + 0x08005a38 EXTI2_IRQHandler + 0x08005a38 TIM8_CC_IRQHandler + 0x08005a38 UART8_IRQHandler + 0x08005a38 BDMA2_Channel1_IRQHandler + 0x08005a38 SPI4_IRQHandler + 0x08005a38 BDMA2_Channel0_IRQHandler + 0x08005a38 TIM1_CC_IRQHandler + 0x08005a38 DMA2_Stream5_IRQHandler + 0x08005a38 JPEG_IRQHandler + 0x08005a38 DMA1_Stream5_IRQHandler + 0x08005a38 EXTI3_IRQHandler + 0x08005a38 LPTIM4_IRQHandler + 0x08005a38 TIM8_TRG_COM_TIM14_IRQHandler + 0x08005a38 LPTIM2_IRQHandler + 0x08005a38 DFSDM1_FLT1_IRQHandler + 0x08005a38 DMAMUX2_OVR_IRQHandler + 0x08005a38 GFXMMU_IRQHandler + 0x08005a38 TIM8_UP_TIM13_IRQHandler + 0x08005a38 I2C3_ER_IRQHandler + 0x08005a38 DFSDM1_FLT2_IRQHandler + 0x08005a38 USART10_IRQHandler + 0x08005a38 MDMA_IRQHandler + 0x08005a38 LPTIM3_IRQHandler + 0x08005a38 BDMA2_Channel3_IRQHandler + 0x08005a38 HSEM1_IRQHandler + 0x08005a38 EXTI0_IRQHandler + 0x08005a38 I2C2_EV_IRQHandler + 0x08005a38 DAC2_IRQHandler + 0x08005a38 DMA1_Stream2_IRQHandler + 0x08005a38 FPU_IRQHandler + 0x08005a38 OTG_HS_WKUP_IRQHandler + 0x08005a38 DMA2_Stream2_IRQHandler + 0x08005a38 SPI1_IRQHandler + 0x08005a38 OCTOSPI1_IRQHandler + 0x08005a38 TIM6_DAC_IRQHandler + 0x08005a38 BDMA2_Channel6_IRQHandler + 0x08005a38 DMA2_Stream3_IRQHandler + 0x08005a38 OCTOSPI2_IRQHandler + 0x08005a38 SAI2_IRQHandler + 0x08005a38 BDMA1_IRQHandler + 0x08005a38 DFSDM1_FLT3_IRQHandler + 0x08005a38 USART6_IRQHandler + 0x08005a38 TIM17_IRQHandler + 0x08005a38 USART3_IRQHandler + 0x08005a38 LPTIM5_IRQHandler + 0x08005a38 UART5_IRQHandler + 0x08005a38 DMA2_Stream0_IRQHandler + 0x08005a38 TIM4_IRQHandler + 0x08005a38 I2C1_EV_IRQHandler + 0x08005a38 DMA1_Stream6_IRQHandler + 0x08005a38 DMAMUX1_OVR_IRQHandler + 0x08005a38 DMA1_Stream1_IRQHandler + 0x08005a38 TIM16_IRQHandler + 0x08005a38 UART4_IRQHandler + 0x08005a38 TIM3_IRQHandler + 0x08005a38 RCC_IRQHandler + 0x08005a38 UART9_IRQHandler + 0x08005a38 TIM8_BRK_TIM12_IRQHandler + 0x08005a38 TIM1_TRG_COM_IRQHandler + 0x08005a38 Default_Handler + 0x08005a38 ECC_IRQHandler + 0x08005a38 BDMA2_Channel2_IRQHandler + 0x08005a38 CEC_IRQHandler + 0x08005a38 EXTI15_10_IRQHandler + 0x08005a38 DFSDM1_FLT4_IRQHandler + 0x08005a38 ADC_IRQHandler + 0x08005a38 DMA1_Stream7_IRQHandler + 0x08005a38 SPI5_IRQHandler + 0x08005a38 TIM7_IRQHandler + 0x08005a38 SDMMC1_IRQHandler + 0x08005a38 TIM5_IRQHandler + 0x08005a38 DMA2_Stream7_IRQHandler + 0x08005a38 TIM15_IRQHandler + 0x08005a38 I2C3_EV_IRQHandler + 0x08005a38 DFSDM2_IRQHandler + 0x08005a38 EXTI9_5_IRQHandler + 0x08005a38 RTC_WKUP_IRQHandler + 0x08005a38 SPDIF_RX_IRQHandler + 0x08005a38 PVD_PVM_IRQHandler + 0x08005a38 SPI2_IRQHandler + 0x08005a38 OTG_HS_EP1_IN_IRQHandler + 0x08005a38 DFSDM1_FLT5_IRQHandler + 0x08005a38 DMA1_Stream0_IRQHandler + 0x08005a38 CRS_IRQHandler + 0x08005a38 EXTI4_IRQHandler + 0x08005a38 DFSDM1_FLT6_IRQHandler + 0x08005a38 RNG_IRQHandler + 0x08005a38 FDCAN2_IT1_IRQHandler + 0x08005a38 COMP_IRQHandler + 0x08005a38 TIM1_UP_IRQHandler + 0x08005a38 OTG_HS_EP1_OUT_IRQHandler + 0x08005a38 WWDG_IRQHandler + 0x08005a38 SPI6_IRQHandler + 0x08005a38 MDIOS_IRQHandler + 0x08005a38 I2C4_EV_IRQHandler + 0x08005a38 FDCAN2_IT0_IRQHandler + 0x08005a38 LPUART1_IRQHandler + 0x08005a38 TIM2_IRQHandler + 0x08005a38 BDMA2_Channel5_IRQHandler + 0x08005a38 OTG_HS_IRQHandler + 0x08005a38 DMA2D_IRQHandler + 0x08005a38 TIM1_BRK_IRQHandler + 0x08005a38 EXTI1_IRQHandler + 0x08005a38 SDMMC2_IRQHandler + 0x08005a38 DTS_IRQHandler + 0x08005a38 UART7_IRQHandler + 0x08005a38 MDIOS_WKUP_IRQHandler + 0x08005a38 USART2_IRQHandler + 0x08005a38 DFSDM1_FLT0_IRQHandler + 0x08005a38 I2C2_ER_IRQHandler + 0x08005a38 DMA2_Stream1_IRQHandler + 0x08005a38 DFSDM1_FLT7_IRQHandler + 0x08005a38 FLASH_IRQHandler + 0x08005a38 DMA2_Stream4_IRQHandler + 0x08005a38 USART1_IRQHandler + 0x08005a38 SPI3_IRQHandler + 0x08005a38 WAKEUP_PIN_IRQHandler + 0x08005a38 DMA1_Stream4_IRQHandler + 0x08005a38 I2C1_ER_IRQHandler + 0x08005a38 BDMA2_Channel7_IRQHandler + 0x08005a38 SWPMI1_IRQHandler + 0x08005a38 LPTIM1_IRQHandler + 0x08005a38 DCMI_PSSI_IRQHandler + 0x08005a38 I2C4_ER_IRQHandler + 0x08005a38 DMA2_Stream6_IRQHandler + 0x08005a38 SAI1_IRQHandler + 0x08005a38 DMA1_Stream3_IRQHandler + 0x08005a38 RTC_TAMP_STAMP_CSS_LSE_IRQHandler + 0x08005a38 BDMA2_Channel4_IRQHandler + .text.memset 0x08005a3a 0x10 /usr/lib/gcc/arm-none-eabi/14.1.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memset.o) + 0x08005a3a memset + *fill* 0x08005a4a 0x2 .text.__libc_init_array - 0x08005a20 0x48 /usr/lib/gcc/arm-none-eabi/14.1.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-init.o) - 0x08005a20 __libc_init_array - .text.memcpy 0x08005a68 0x1c /usr/lib/gcc/arm-none-eabi/14.1.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memcpy-stub.o) - 0x08005a68 memcpy + 0x08005a4c 0x48 /usr/lib/gcc/arm-none-eabi/14.1.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-init.o) + 0x08005a4c __libc_init_array + .text.memcpy 0x08005a94 0x1c /usr/lib/gcc/arm-none-eabi/14.1.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memcpy-stub.o) + 0x08005a94 memcpy *(.glue_7) - .glue_7 0x08005a84 0x0 linker stubs + .glue_7 0x08005ab0 0x0 linker stubs *(.glue_7t) - .glue_7t 0x08005a84 0x0 linker stubs + .glue_7t 0x08005ab0 0x0 linker stubs *(.eh_frame) - .eh_frame 0x08005a84 0x0 /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/crtbegin.o + .eh_frame 0x08005ab0 0x0 /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/crtbegin.o *(.init) - .init 0x08005a84 0x4 /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/crti.o - 0x08005a84 _init - .init 0x08005a88 0x8 /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/crtn.o + .init 0x08005ab0 0x4 /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/crti.o + 0x08005ab0 _init + .init 0x08005ab4 0x8 /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/crtn.o *(.fini) - .fini 0x08005a90 0x4 /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/crti.o - 0x08005a90 _fini - .fini 0x08005a94 0x8 /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/crtn.o - 0x08005a9c . = ALIGN (0x4) - 0x08005a9c _etext = . + .fini 0x08005abc 0x4 /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/crti.o + 0x08005abc _fini + .fini 0x08005ac0 0x8 /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/crtn.o + 0x08005ac8 . = ALIGN (0x4) + 0x08005ac8 _etext = . -.vfp11_veneer 0x08005a9c 0x0 - .vfp11_veneer 0x08005a9c 0x0 linker stubs +.vfp11_veneer 0x08005ac8 0x0 + .vfp11_veneer 0x08005ac8 0x0 linker stubs -.v4_bx 0x08005a9c 0x0 - .v4_bx 0x08005a9c 0x0 linker stubs +.v4_bx 0x08005ac8 0x0 + .v4_bx 0x08005ac8 0x0 linker stubs -.iplt 0x08005a9c 0x0 - .iplt 0x08005a9c 0x0 /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/crtbegin.o +.iplt 0x08005ac8 0x0 + .iplt 0x08005ac8 0x0 /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/crtbegin.o -.rodata 0x08005a9c 0x8c - 0x08005a9c . = ALIGN (0x4) +.rodata 0x08005ac8 0x8c + 0x08005ac8 . = ALIGN (0x4) *(.rodata) - .rodata 0x08005a9c 0x4c build/debug/stm32h7xx_hal_fdcan.o + .rodata 0x08005ac8 0x4c build/debug/stm32h7xx_hal_fdcan.o *(.rodata*) .rodata.main.str1.4 - 0x08005ae8 0x6 build/debug/main.o - *fill* 0x08005aee 0x2 + 0x08005b14 0x6 build/debug/main.o + *fill* 0x08005b1a 0x2 .rodata.UARTPrescTable - 0x08005af0 0x18 build/debug/stm32h7xx_hal_uart.o - 0x08005af0 UARTPrescTable + 0x08005b1c 0x18 build/debug/stm32h7xx_hal_uart.o + 0x08005b1c UARTPrescTable .rodata.denominator.0 - 0x08005b08 0x8 build/debug/stm32h7xx_hal_uart_ex.o + 0x08005b34 0x8 build/debug/stm32h7xx_hal_uart_ex.o .rodata.numerator.1 - 0x08005b10 0x8 build/debug/stm32h7xx_hal_uart_ex.o + 0x08005b3c 0x8 build/debug/stm32h7xx_hal_uart_ex.o .rodata.D1CorePrescTable - 0x08005b18 0x10 build/debug/system_stm32h7xx.o - 0x08005b18 D1CorePrescTable - 0x08005b28 . = ALIGN (0x4) + 0x08005b44 0x10 build/debug/system_stm32h7xx.o + 0x08005b44 D1CorePrescTable + 0x08005b54 . = ALIGN (0x4) .ARM.extab *(.ARM.extab* .gnu.linkonce.armextab.*) -.ARM 0x08005b28 0x8 - 0x08005b28 __exidx_start = . +.ARM 0x08005b54 0x8 + 0x08005b54 __exidx_start = . *(.ARM.exidx*) - .ARM.exidx 0x08005b28 0x8 /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/libgcc.a(_udivmoddi4.o) - 0x08005b30 __exidx_end = . + .ARM.exidx 0x08005b54 0x8 /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/libgcc.a(_udivmoddi4.o) + 0x08005b5c __exidx_end = . -.rel.dyn 0x08005b30 0x0 - .rel.iplt 0x08005b30 0x0 /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/crtbegin.o +.rel.dyn 0x08005b5c 0x0 + .rel.iplt 0x08005b5c 0x0 /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/crtbegin.o -.preinit_array 0x08005b30 0x0 - 0x08005b30 PROVIDE (__preinit_array_start = .) +.preinit_array 0x08005b5c 0x0 + 0x08005b5c PROVIDE (__preinit_array_start = .) *(.preinit_array*) - 0x08005b30 PROVIDE (__preinit_array_end = .) + 0x08005b5c PROVIDE (__preinit_array_end = .) -.init_array 0x08005b30 0x4 - 0x08005b30 PROVIDE (__init_array_start = .) +.init_array 0x08005b5c 0x4 + 0x08005b5c PROVIDE (__init_array_start = .) *(SORT_BY_NAME(.init_array.*)) *(.init_array*) - .init_array 0x08005b30 0x4 /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/crtbegin.o - 0x08005b34 PROVIDE (__init_array_end = .) + .init_array 0x08005b5c 0x4 /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/crtbegin.o + 0x08005b60 PROVIDE (__init_array_end = .) -.fini_array 0x08005b34 0x4 - 0x08005b34 PROVIDE (__fini_array_start = .) +.fini_array 0x08005b60 0x4 + 0x08005b60 PROVIDE (__fini_array_start = .) *(SORT_BY_NAME(.fini_array.*)) *(.fini_array*) - .fini_array 0x08005b34 0x4 /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/crtbegin.o - 0x08005b38 PROVIDE (__fini_array_end = .) - 0x08005b38 _sidata = LOADADDR (.data) + .fini_array 0x08005b60 0x4 /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/crtbegin.o + 0x08005b64 PROVIDE (__fini_array_end = .) + 0x08005b64 _sidata = LOADADDR (.data) -.data 0x20000000 0x10 load address 0x08005b38 +.data 0x20000000 0x10 load address 0x08005b64 0x20000000 . = ALIGN (0x4) 0x20000000 _sdata = . *(.data) @@ -2971,13 +2973,13 @@ LOAD /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/crtn.o 0x20000010 _edata = . .tm_clone_table - 0x20000010 0x0 load address 0x08005b48 + 0x20000010 0x0 load address 0x08005b74 .tm_clone_table 0x20000010 0x0 /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/crtbegin.o .tm_clone_table 0x20000010 0x0 /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/crtend.o -.igot.plt 0x20000010 0x0 load address 0x08005b48 +.igot.plt 0x20000010 0x0 load address 0x08005b74 .igot.plt 0x20000010 0x0 /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/crtbegin.o 0x20000010 . = ALIGN (0x4) @@ -3137,71 +3139,71 @@ LOAD /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/libgcc.a .comment 0x00000046 0x24 /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/libgcc.a(_udivmoddi4.o) .comment 0x00000046 0x24 /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/crtend.o -.debug_info 0x00000000 0x28767 - .debug_info 0x00000000 0x343b build/debug/main.o - .debug_info 0x0000343b 0x14ef build/debug/stm32h7xx_hal.o - .debug_info 0x0000492a 0x12fc build/debug/stm32h7xx_hal_cortex.o - .debug_info 0x00005c26 0x600 build/debug/stm32h7xx_hal_crc.o - .debug_info 0x00006226 0x352 build/debug/stm32h7xx_hal_crc_ex.o - .debug_info 0x00006578 0x3275 build/debug/stm32h7xx_hal_fdcan.o - .debug_info 0x000097ed 0xb76 build/debug/stm32h7xx_hal_gpio.o - .debug_info 0x0000a363 0x44f5 build/debug/stm32h7xx_hal_i2c.o - .debug_info 0x0000e858 0xc81 build/debug/stm32h7xx_hal_i2c_ex.o - .debug_info 0x0000f4d9 0x1504 build/debug/stm32h7xx_hal_ltdc.o - .debug_info 0x000109dd 0x39fd build/debug/stm32h7xx_hal_msp.o - .debug_info 0x000143da 0x1c4f build/debug/stm32h7xx_hal_pcd.o - .debug_info 0x00016029 0xa1a build/debug/stm32h7xx_hal_pcd_ex.o - .debug_info 0x00016a43 0x107c build/debug/stm32h7xx_hal_pwr_ex.o - .debug_info 0x00017abf 0x1174 build/debug/stm32h7xx_hal_rcc.o - .debug_info 0x00018c33 0x1986 build/debug/stm32h7xx_hal_rcc_ex.o - .debug_info 0x0001a5b9 0x132d build/debug/stm32h7xx_hal_sdram.o - .debug_info 0x0001b8e6 0x657c build/debug/stm32h7xx_hal_uart.o - .debug_info 0x00021e62 0x1226 build/debug/stm32h7xx_hal_uart_ex.o - .debug_info 0x00023088 0x1327 build/debug/stm32h7xx_it.o - .debug_info 0x000243af 0xcbe build/debug/stm32h7xx_ll_fmc.o - .debug_info 0x0002506d 0x1f0d build/debug/stm32h7xx_ll_usb.o - .debug_info 0x00026f7a 0xd5c build/debug/system_stm32h7xx.o - .debug_info 0x00027cd6 0x30 build/debug/startup_stm32h7a3xx.o - .debug_info 0x00027d06 0xe0 /usr/lib/gcc/arm-none-eabi/14.1.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memset.o) - .debug_info 0x00027de6 0x10b /usr/lib/gcc/arm-none-eabi/14.1.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-init.o) - .debug_info 0x00027ef1 0x121 /usr/lib/gcc/arm-none-eabi/14.1.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memcpy-stub.o) - .debug_info 0x00028012 0x24 /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/libgcc.a(_aeabi_uldivmod.o) - .debug_info 0x00028036 0x6f5 /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/libgcc.a(_udivmoddi4.o) - .debug_info 0x0002872b 0x3c /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/libgcc.a(_dvmd_tls.o) +.debug_info 0x00000000 0x287d9 + .debug_info 0x00000000 0x3448 build/debug/main.o + .debug_info 0x00003448 0x14ef build/debug/stm32h7xx_hal.o + .debug_info 0x00004937 0x12fc build/debug/stm32h7xx_hal_cortex.o + .debug_info 0x00005c33 0x600 build/debug/stm32h7xx_hal_crc.o + .debug_info 0x00006233 0x352 build/debug/stm32h7xx_hal_crc_ex.o + .debug_info 0x00006585 0x3275 build/debug/stm32h7xx_hal_fdcan.o + .debug_info 0x000097fa 0xb76 build/debug/stm32h7xx_hal_gpio.o + .debug_info 0x0000a370 0x44f5 build/debug/stm32h7xx_hal_i2c.o + .debug_info 0x0000e865 0xc81 build/debug/stm32h7xx_hal_i2c_ex.o + .debug_info 0x0000f4e6 0x1504 build/debug/stm32h7xx_hal_ltdc.o + .debug_info 0x000109ea 0x3a45 build/debug/stm32h7xx_hal_msp.o + .debug_info 0x0001442f 0x1c4f build/debug/stm32h7xx_hal_pcd.o + .debug_info 0x0001607e 0xa1a build/debug/stm32h7xx_hal_pcd_ex.o + .debug_info 0x00016a98 0x107c build/debug/stm32h7xx_hal_pwr_ex.o + .debug_info 0x00017b14 0x1174 build/debug/stm32h7xx_hal_rcc.o + .debug_info 0x00018c88 0x1986 build/debug/stm32h7xx_hal_rcc_ex.o + .debug_info 0x0001a60e 0x132d build/debug/stm32h7xx_hal_sdram.o + .debug_info 0x0001b93b 0x657c build/debug/stm32h7xx_hal_uart.o + .debug_info 0x00021eb7 0x1226 build/debug/stm32h7xx_hal_uart_ex.o + .debug_info 0x000230dd 0x1344 build/debug/stm32h7xx_it.o + .debug_info 0x00024421 0xcbe build/debug/stm32h7xx_ll_fmc.o + .debug_info 0x000250df 0x1f0d build/debug/stm32h7xx_ll_usb.o + .debug_info 0x00026fec 0xd5c build/debug/system_stm32h7xx.o + .debug_info 0x00027d48 0x30 build/debug/startup_stm32h7a3xx.o + .debug_info 0x00027d78 0xe0 /usr/lib/gcc/arm-none-eabi/14.1.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memset.o) + .debug_info 0x00027e58 0x10b /usr/lib/gcc/arm-none-eabi/14.1.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-init.o) + .debug_info 0x00027f63 0x121 /usr/lib/gcc/arm-none-eabi/14.1.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memcpy-stub.o) + .debug_info 0x00028084 0x24 /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/libgcc.a(_aeabi_uldivmod.o) + .debug_info 0x000280a8 0x6f5 /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/libgcc.a(_udivmoddi4.o) + .debug_info 0x0002879d 0x3c /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/libgcc.a(_dvmd_tls.o) -.debug_abbrev 0x00000000 0x3ed6 - .debug_abbrev 0x00000000 0x33d build/debug/main.o - .debug_abbrev 0x0000033d 0x2b6 build/debug/stm32h7xx_hal.o - .debug_abbrev 0x000005f3 0x3ad build/debug/stm32h7xx_hal_cortex.o - .debug_abbrev 0x000009a0 0x223 build/debug/stm32h7xx_hal_crc.o - .debug_abbrev 0x00000bc3 0x16d build/debug/stm32h7xx_hal_crc_ex.o - .debug_abbrev 0x00000d30 0x2be build/debug/stm32h7xx_hal_fdcan.o - .debug_abbrev 0x00000fee 0x251 build/debug/stm32h7xx_hal_gpio.o - .debug_abbrev 0x0000123f 0x296 build/debug/stm32h7xx_hal_i2c.o - .debug_abbrev 0x000014d5 0x1f5 build/debug/stm32h7xx_hal_i2c_ex.o - .debug_abbrev 0x000016ca 0x24a build/debug/stm32h7xx_hal_ltdc.o - .debug_abbrev 0x00001914 0x2ed build/debug/stm32h7xx_hal_msp.o - .debug_abbrev 0x00001c01 0x2fa build/debug/stm32h7xx_hal_pcd.o - .debug_abbrev 0x00001efb 0x2ad build/debug/stm32h7xx_hal_pcd_ex.o - .debug_abbrev 0x000021a8 0x2b7 build/debug/stm32h7xx_hal_pwr_ex.o - .debug_abbrev 0x0000245f 0x2a8 build/debug/stm32h7xx_hal_rcc.o - .debug_abbrev 0x00002707 0x293 build/debug/stm32h7xx_hal_rcc_ex.o - .debug_abbrev 0x0000299a 0x20e build/debug/stm32h7xx_hal_sdram.o - .debug_abbrev 0x00002ba8 0x38b build/debug/stm32h7xx_hal_uart.o - .debug_abbrev 0x00002f33 0x343 build/debug/stm32h7xx_hal_uart_ex.o - .debug_abbrev 0x00003276 0x21a build/debug/stm32h7xx_it.o - .debug_abbrev 0x00003490 0x1c4 build/debug/stm32h7xx_ll_fmc.o - .debug_abbrev 0x00003654 0x329 build/debug/stm32h7xx_ll_usb.o - .debug_abbrev 0x0000397d 0x169 build/debug/system_stm32h7xx.o - .debug_abbrev 0x00003ae6 0x24 build/debug/startup_stm32h7a3xx.o - .debug_abbrev 0x00003b0a 0x9e /usr/lib/gcc/arm-none-eabi/14.1.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memset.o) - .debug_abbrev 0x00003ba8 0xc9 /usr/lib/gcc/arm-none-eabi/14.1.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-init.o) - .debug_abbrev 0x00003c71 0xc1 /usr/lib/gcc/arm-none-eabi/14.1.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memcpy-stub.o) - .debug_abbrev 0x00003d32 0x14 /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/libgcc.a(_aeabi_uldivmod.o) - .debug_abbrev 0x00003d46 0x16a /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/libgcc.a(_udivmoddi4.o) - .debug_abbrev 0x00003eb0 0x26 /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/libgcc.a(_dvmd_tls.o) +.debug_abbrev 0x00000000 0x3ee7 + .debug_abbrev 0x00000000 0x34c build/debug/main.o + .debug_abbrev 0x0000034c 0x2b6 build/debug/stm32h7xx_hal.o + .debug_abbrev 0x00000602 0x3ad build/debug/stm32h7xx_hal_cortex.o + .debug_abbrev 0x000009af 0x223 build/debug/stm32h7xx_hal_crc.o + .debug_abbrev 0x00000bd2 0x16d build/debug/stm32h7xx_hal_crc_ex.o + .debug_abbrev 0x00000d3f 0x2be build/debug/stm32h7xx_hal_fdcan.o + .debug_abbrev 0x00000ffd 0x251 build/debug/stm32h7xx_hal_gpio.o + .debug_abbrev 0x0000124e 0x296 build/debug/stm32h7xx_hal_i2c.o + .debug_abbrev 0x000014e4 0x1f5 build/debug/stm32h7xx_hal_i2c_ex.o + .debug_abbrev 0x000016d9 0x24a build/debug/stm32h7xx_hal_ltdc.o + .debug_abbrev 0x00001923 0x2ed build/debug/stm32h7xx_hal_msp.o + .debug_abbrev 0x00001c10 0x2fa build/debug/stm32h7xx_hal_pcd.o + .debug_abbrev 0x00001f0a 0x2ad build/debug/stm32h7xx_hal_pcd_ex.o + .debug_abbrev 0x000021b7 0x2b7 build/debug/stm32h7xx_hal_pwr_ex.o + .debug_abbrev 0x0000246e 0x2a8 build/debug/stm32h7xx_hal_rcc.o + .debug_abbrev 0x00002716 0x293 build/debug/stm32h7xx_hal_rcc_ex.o + .debug_abbrev 0x000029a9 0x20e build/debug/stm32h7xx_hal_sdram.o + .debug_abbrev 0x00002bb7 0x38b build/debug/stm32h7xx_hal_uart.o + .debug_abbrev 0x00002f42 0x343 build/debug/stm32h7xx_hal_uart_ex.o + .debug_abbrev 0x00003285 0x21c build/debug/stm32h7xx_it.o + .debug_abbrev 0x000034a1 0x1c4 build/debug/stm32h7xx_ll_fmc.o + .debug_abbrev 0x00003665 0x329 build/debug/stm32h7xx_ll_usb.o + .debug_abbrev 0x0000398e 0x169 build/debug/system_stm32h7xx.o + .debug_abbrev 0x00003af7 0x24 build/debug/startup_stm32h7a3xx.o + .debug_abbrev 0x00003b1b 0x9e /usr/lib/gcc/arm-none-eabi/14.1.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memset.o) + .debug_abbrev 0x00003bb9 0xc9 /usr/lib/gcc/arm-none-eabi/14.1.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-init.o) + .debug_abbrev 0x00003c82 0xc1 /usr/lib/gcc/arm-none-eabi/14.1.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memcpy-stub.o) + .debug_abbrev 0x00003d43 0x14 /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/libgcc.a(_aeabi_uldivmod.o) + .debug_abbrev 0x00003d57 0x16a /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/libgcc.a(_udivmoddi4.o) + .debug_abbrev 0x00003ec1 0x26 /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/libgcc.a(_dvmd_tls.o) -.debug_aranges 0x00000000 0x1890 +.debug_aranges 0x00000000 0x1898 .debug_aranges 0x00000000 0x78 build/debug/main.o .debug_aranges @@ -3241,30 +3243,30 @@ LOAD /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/libgcc.a .debug_aranges 0x000013e0 0xa8 build/debug/stm32h7xx_hal_uart_ex.o .debug_aranges - 0x00001488 0x88 build/debug/stm32h7xx_it.o + 0x00001488 0x90 build/debug/stm32h7xx_it.o .debug_aranges - 0x00001510 0xc8 build/debug/stm32h7xx_ll_fmc.o + 0x00001518 0xc8 build/debug/stm32h7xx_ll_fmc.o .debug_aranges - 0x000015d8 0x1a0 build/debug/stm32h7xx_ll_usb.o + 0x000015e0 0x1a0 build/debug/stm32h7xx_ll_usb.o .debug_aranges - 0x00001778 0x30 build/debug/system_stm32h7xx.o + 0x00001780 0x30 build/debug/system_stm32h7xx.o .debug_aranges - 0x000017a8 0x28 build/debug/startup_stm32h7a3xx.o + 0x000017b0 0x28 build/debug/startup_stm32h7a3xx.o .debug_aranges - 0x000017d0 0x20 /usr/lib/gcc/arm-none-eabi/14.1.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memset.o) + 0x000017d8 0x20 /usr/lib/gcc/arm-none-eabi/14.1.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memset.o) .debug_aranges - 0x000017f0 0x20 /usr/lib/gcc/arm-none-eabi/14.1.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-init.o) + 0x000017f8 0x20 /usr/lib/gcc/arm-none-eabi/14.1.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-init.o) .debug_aranges - 0x00001810 0x20 /usr/lib/gcc/arm-none-eabi/14.1.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memcpy-stub.o) + 0x00001818 0x20 /usr/lib/gcc/arm-none-eabi/14.1.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memcpy-stub.o) .debug_aranges - 0x00001830 0x20 /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/libgcc.a(_aeabi_uldivmod.o) + 0x00001838 0x20 /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/libgcc.a(_aeabi_uldivmod.o) .debug_aranges - 0x00001850 0x20 /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/libgcc.a(_udivmoddi4.o) + 0x00001858 0x20 /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/libgcc.a(_udivmoddi4.o) .debug_aranges - 0x00001870 0x20 /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/libgcc.a(_dvmd_tls.o) + 0x00001878 0x20 /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/libgcc.a(_dvmd_tls.o) .debug_rnglists - 0x00000000 0x1367 + 0x00000000 0x136e .debug_rnglists 0x00000000 0x59 build/debug/main.o .debug_rnglists @@ -3286,139 +3288,139 @@ LOAD /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/libgcc.a .debug_rnglists 0x000007d0 0x103 build/debug/stm32h7xx_hal_ltdc.o .debug_rnglists - 0x000008d3 0x7a build/debug/stm32h7xx_hal_msp.o + 0x000008d3 0x7b build/debug/stm32h7xx_hal_msp.o .debug_rnglists - 0x0000094d 0xf1 build/debug/stm32h7xx_hal_pcd.o + 0x0000094e 0xf1 build/debug/stm32h7xx_hal_pcd.o .debug_rnglists - 0x00000a3e 0x44 build/debug/stm32h7xx_hal_pcd_ex.o + 0x00000a3f 0x44 build/debug/stm32h7xx_hal_pcd_ex.o .debug_rnglists - 0x00000a82 0x156 build/debug/stm32h7xx_hal_pwr_ex.o + 0x00000a83 0x156 build/debug/stm32h7xx_hal_pwr_ex.o .debug_rnglists - 0x00000bd8 0xa9 build/debug/stm32h7xx_hal_rcc.o + 0x00000bd9 0xa9 build/debug/stm32h7xx_hal_rcc.o .debug_rnglists - 0x00000c81 0xb9 build/debug/stm32h7xx_hal_rcc_ex.o + 0x00000c82 0xb9 build/debug/stm32h7xx_hal_rcc_ex.o .debug_rnglists - 0x00000d3a 0xa9 build/debug/stm32h7xx_hal_sdram.o + 0x00000d3b 0xa9 build/debug/stm32h7xx_hal_sdram.o .debug_rnglists - 0x00000de3 0x1cb build/debug/stm32h7xx_hal_uart.o + 0x00000de4 0x1cb build/debug/stm32h7xx_hal_uart.o .debug_rnglists - 0x00000fae 0x88 build/debug/stm32h7xx_hal_uart_ex.o + 0x00000faf 0x88 build/debug/stm32h7xx_hal_uart_ex.o .debug_rnglists - 0x00001036 0x61 build/debug/stm32h7xx_it.o + 0x00001037 0x67 build/debug/stm32h7xx_it.o .debug_rnglists - 0x00001097 0x93 build/debug/stm32h7xx_ll_fmc.o + 0x0000109e 0x93 build/debug/stm32h7xx_ll_fmc.o .debug_rnglists - 0x0000112a 0x141 build/debug/stm32h7xx_ll_usb.o + 0x00001131 0x141 build/debug/stm32h7xx_ll_usb.o .debug_rnglists - 0x0000126b 0x21 build/debug/system_stm32h7xx.o + 0x00001272 0x21 build/debug/system_stm32h7xx.o .debug_rnglists - 0x0000128c 0x19 build/debug/startup_stm32h7a3xx.o + 0x00001293 0x19 build/debug/startup_stm32h7a3xx.o .debug_rnglists - 0x000012a5 0x13 /usr/lib/gcc/arm-none-eabi/14.1.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memset.o) + 0x000012ac 0x13 /usr/lib/gcc/arm-none-eabi/14.1.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memset.o) .debug_rnglists - 0x000012b8 0x13 /usr/lib/gcc/arm-none-eabi/14.1.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-init.o) + 0x000012bf 0x13 /usr/lib/gcc/arm-none-eabi/14.1.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-init.o) .debug_rnglists - 0x000012cb 0x13 /usr/lib/gcc/arm-none-eabi/14.1.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memcpy-stub.o) + 0x000012d2 0x13 /usr/lib/gcc/arm-none-eabi/14.1.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memcpy-stub.o) .debug_rnglists - 0x000012de 0x89 /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/libgcc.a(_udivmoddi4.o) + 0x000012e5 0x89 /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/libgcc.a(_udivmoddi4.o) -.debug_line 0x00000000 0x1bdff - .debug_line 0x00000000 0xbcb build/debug/main.o - .debug_line 0x00000bcb 0x88f build/debug/stm32h7xx_hal.o - .debug_line 0x0000145a 0x7d3 build/debug/stm32h7xx_hal_cortex.o - .debug_line 0x00001c2d 0x519 build/debug/stm32h7xx_hal_crc.o - .debug_line 0x00002146 0x24b build/debug/stm32h7xx_hal_crc_ex.o - .debug_line 0x00002391 0x3338 build/debug/stm32h7xx_hal_fdcan.o - .debug_line 0x000056c9 0x6af build/debug/stm32h7xx_hal_gpio.o - .debug_line 0x00005d78 0x4fdb build/debug/stm32h7xx_hal_i2c.o - .debug_line 0x0000ad53 0x367 build/debug/stm32h7xx_hal_i2c_ex.o - .debug_line 0x0000b0ba 0x11af build/debug/stm32h7xx_hal_ltdc.o - .debug_line 0x0000c269 0xb91 build/debug/stm32h7xx_hal_msp.o - .debug_line 0x0000cdfa 0x13d7 build/debug/stm32h7xx_hal_pcd.o - .debug_line 0x0000e1d1 0x458 build/debug/stm32h7xx_hal_pcd_ex.o - .debug_line 0x0000e629 0xae4 build/debug/stm32h7xx_hal_pwr_ex.o - .debug_line 0x0000f10d 0x1337 build/debug/stm32h7xx_hal_rcc.o - .debug_line 0x00010444 0x1e24 build/debug/stm32h7xx_hal_rcc_ex.o - .debug_line 0x00012268 0x9d9 build/debug/stm32h7xx_hal_sdram.o - .debug_line 0x00012c41 0x50e3 build/debug/stm32h7xx_hal_uart.o - .debug_line 0x00017d24 0xa10 build/debug/stm32h7xx_hal_uart_ex.o - .debug_line 0x00018734 0x2f7 build/debug/stm32h7xx_it.o - .debug_line 0x00018a2b 0x6af build/debug/stm32h7xx_ll_fmc.o - .debug_line 0x000190da 0x1e92 build/debug/stm32h7xx_ll_usb.o - .debug_line 0x0001af6c 0x3ef build/debug/system_stm32h7xx.o - .debug_line 0x0001b35b 0x77 build/debug/startup_stm32h7a3xx.o - .debug_line 0x0001b3d2 0x12d /usr/lib/gcc/arm-none-eabi/14.1.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memset.o) - .debug_line 0x0001b4ff 0xff /usr/lib/gcc/arm-none-eabi/14.1.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-init.o) - .debug_line 0x0001b5fe 0x185 /usr/lib/gcc/arm-none-eabi/14.1.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memcpy-stub.o) - .debug_line 0x0001b783 0x4e /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/libgcc.a(_aeabi_uldivmod.o) - .debug_line 0x0001b7d1 0x5e4 /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/libgcc.a(_udivmoddi4.o) - .debug_line 0x0001bdb5 0x4a /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/libgcc.a(_dvmd_tls.o) +.debug_line 0x00000000 0x1be50 + .debug_line 0x00000000 0xc01 build/debug/main.o + .debug_line 0x00000c01 0x88f build/debug/stm32h7xx_hal.o + .debug_line 0x00001490 0x7d3 build/debug/stm32h7xx_hal_cortex.o + .debug_line 0x00001c63 0x519 build/debug/stm32h7xx_hal_crc.o + .debug_line 0x0000217c 0x24b build/debug/stm32h7xx_hal_crc_ex.o + .debug_line 0x000023c7 0x3338 build/debug/stm32h7xx_hal_fdcan.o + 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0x2226 (size before relaxing) - .debug_str 0x000099c5 0x1456 build/debug/stm32h7xx_hal.o - .debug_str 0x000099c5 0x1029 build/debug/stm32h7xx_hal_cortex.o - .debug_str 0x000099c5 0x47c build/debug/stm32h7xx_hal_crc.o - .debug_str 0x000099c5 0x422 build/debug/stm32h7xx_hal_crc_ex.o - .debug_str 0x000099c5 0x1d96 build/debug/stm32h7xx_hal_fdcan.o - .debug_str 0x000099c5 0x6ac build/debug/stm32h7xx_hal_gpio.o - .debug_str 0x000099c5 0x1170 build/debug/stm32h7xx_hal_i2c.o - .debug_str 0x000099c5 0xb03 build/debug/stm32h7xx_hal_i2c_ex.o - .debug_str 0x000099c5 0x9c2 build/debug/stm32h7xx_hal_ltdc.o - .debug_str 0x000099c5 0x29d3 build/debug/stm32h7xx_hal_msp.o - .debug_str 0x000099c5 0xe36 build/debug/stm32h7xx_hal_pcd.o - .debug_str 0x000099c5 0x822 build/debug/stm32h7xx_hal_pcd_ex.o - .debug_str 0x000099c5 0xae5 build/debug/stm32h7xx_hal_pwr_ex.o - .debug_str 0x000099c5 0xa36 build/debug/stm32h7xx_hal_rcc.o - .debug_str 0x000099c5 0xef5 build/debug/stm32h7xx_hal_rcc_ex.o - .debug_str 0x000099c5 0xb9e build/debug/stm32h7xx_hal_sdram.o - .debug_str 0x000099c5 0x14be build/debug/stm32h7xx_hal_uart.o - .debug_str 0x000099c5 0xb91 build/debug/stm32h7xx_hal_uart_ex.o - .debug_str 0x000099c5 0xf04 build/debug/stm32h7xx_it.o - .debug_str 0x000099c5 0x8a3 build/debug/stm32h7xx_ll_fmc.o - .debug_str 0x000099c5 0xd7e build/debug/stm32h7xx_ll_usb.o - .debug_str 0x000099c5 0x74d build/debug/system_stm32h7xx.o - .debug_str 0x000099c5 0x6d build/debug/startup_stm32h7a3xx.o - .debug_str 0x000099c5 0x1e2 /usr/lib/gcc/arm-none-eabi/14.1.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memset.o) - .debug_str 0x000099c5 0x243 /usr/lib/gcc/arm-none-eabi/14.1.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-init.o) - .debug_str 0x000099c5 0x200 /usr/lib/gcc/arm-none-eabi/14.1.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memcpy-stub.o) - .debug_str 0x000099c5 0xd2 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0x000099e0 0x29d3 build/debug/stm32h7xx_hal_msp.o + .debug_str 0x000099e0 0xe36 build/debug/stm32h7xx_hal_pcd.o + .debug_str 0x000099e0 0x822 build/debug/stm32h7xx_hal_pcd_ex.o + .debug_str 0x000099e0 0xae5 build/debug/stm32h7xx_hal_pwr_ex.o + .debug_str 0x000099e0 0xa36 build/debug/stm32h7xx_hal_rcc.o + .debug_str 0x000099e0 0xef5 build/debug/stm32h7xx_hal_rcc_ex.o + .debug_str 0x000099e0 0xb9e build/debug/stm32h7xx_hal_sdram.o + .debug_str 0x000099e0 0x14be build/debug/stm32h7xx_hal_uart.o + .debug_str 0x000099e0 0xb91 build/debug/stm32h7xx_hal_uart_ex.o + .debug_str 0x000099e0 0xf17 build/debug/stm32h7xx_it.o + .debug_str 0x000099e0 0x8a3 build/debug/stm32h7xx_ll_fmc.o + .debug_str 0x000099e0 0xd7e build/debug/stm32h7xx_ll_usb.o + .debug_str 0x000099e0 0x74d build/debug/system_stm32h7xx.o + .debug_str 0x000099e0 0x6d build/debug/startup_stm32h7a3xx.o + .debug_str 0x000099e0 0x1e2 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.debug_frame 0x000007cc 0x58 build/debug/stm32h7xx_hal_crc_ex.o - .debug_frame 0x00000824 0x7a4 build/debug/stm32h7xx_hal_fdcan.o - .debug_frame 0x00000fc8 0xd4 build/debug/stm32h7xx_hal_gpio.o - .debug_frame 0x0000109c 0x98c build/debug/stm32h7xx_hal_i2c.o - .debug_frame 0x00001a28 0x80 build/debug/stm32h7xx_hal_i2c_ex.o - .debug_frame 0x00001aa8 0x3c4 build/debug/stm32h7xx_hal_ltdc.o - .debug_frame 0x00001e6c 0x200 build/debug/stm32h7xx_hal_msp.o - .debug_frame 0x0000206c 0x378 build/debug/stm32h7xx_hal_pcd.o - .debug_frame 0x000023e4 0xb8 build/debug/stm32h7xx_hal_pcd_ex.o - .debug_frame 0x0000249c 0x354 build/debug/stm32h7xx_hal_pwr_ex.o - .debug_frame 0x000027f0 0x184 build/debug/stm32h7xx_hal_rcc.o - .debug_frame 0x00002974 0x274 build/debug/stm32h7xx_hal_rcc_ex.o - .debug_frame 0x00002be8 0x284 build/debug/stm32h7xx_hal_sdram.o - .debug_frame 0x00002e6c 0x680 build/debug/stm32h7xx_hal_uart.o - .debug_frame 0x000034ec 0x1c8 build/debug/stm32h7xx_hal_uart_ex.o - .debug_frame 0x000036b4 0x120 build/debug/stm32h7xx_it.o - .debug_frame 0x000037d4 0x1d8 build/debug/stm32h7xx_ll_fmc.o - .debug_frame 0x000039ac 0x498 build/debug/stm32h7xx_ll_usb.o - .debug_frame 0x00003e44 0x50 build/debug/system_stm32h7xx.o - .debug_frame 0x00003e94 0x20 /usr/lib/gcc/arm-none-eabi/14.1.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memset.o) - .debug_frame 0x00003eb4 0x2c /usr/lib/gcc/arm-none-eabi/14.1.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-init.o) - .debug_frame 0x00003ee0 0x28 /usr/lib/gcc/arm-none-eabi/14.1.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memcpy-stub.o) - .debug_frame 0x00003f08 0x2c /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/libgcc.a(_aeabi_uldivmod.o) - .debug_frame 0x00003f34 0x34 /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/libgcc.a(_udivmoddi4.o) +.debug_frame 0x00000000 0x3f84 + .debug_frame 0x00000000 0x160 build/debug/main.o + .debug_frame 0x00000160 0x370 build/debug/stm32h7xx_hal.o + .debug_frame 0x000004d0 0x214 build/debug/stm32h7xx_hal_cortex.o + .debug_frame 0x000006e4 0xec build/debug/stm32h7xx_hal_crc.o + .debug_frame 0x000007d0 0x58 build/debug/stm32h7xx_hal_crc_ex.o + .debug_frame 0x00000828 0x7a4 build/debug/stm32h7xx_hal_fdcan.o + .debug_frame 0x00000fcc 0xd4 build/debug/stm32h7xx_hal_gpio.o + .debug_frame 0x000010a0 0x98c build/debug/stm32h7xx_hal_i2c.o + .debug_frame 0x00001a2c 0x80 build/debug/stm32h7xx_hal_i2c_ex.o + .debug_frame 0x00001aac 0x3c4 build/debug/stm32h7xx_hal_ltdc.o + .debug_frame 0x00001e70 0x200 build/debug/stm32h7xx_hal_msp.o + .debug_frame 0x00002070 0x378 build/debug/stm32h7xx_hal_pcd.o + .debug_frame 0x000023e8 0xb8 build/debug/stm32h7xx_hal_pcd_ex.o + .debug_frame 0x000024a0 0x354 build/debug/stm32h7xx_hal_pwr_ex.o + .debug_frame 0x000027f4 0x184 build/debug/stm32h7xx_hal_rcc.o + .debug_frame 0x00002978 0x274 build/debug/stm32h7xx_hal_rcc_ex.o + .debug_frame 0x00002bec 0x284 build/debug/stm32h7xx_hal_sdram.o + .debug_frame 0x00002e70 0x680 build/debug/stm32h7xx_hal_uart.o + .debug_frame 0x000034f0 0x1c8 build/debug/stm32h7xx_hal_uart_ex.o + .debug_frame 0x000036b8 0x138 build/debug/stm32h7xx_it.o + .debug_frame 0x000037f0 0x1d8 build/debug/stm32h7xx_ll_fmc.o + .debug_frame 0x000039c8 0x498 build/debug/stm32h7xx_ll_usb.o + .debug_frame 0x00003e60 0x50 build/debug/system_stm32h7xx.o + .debug_frame 0x00003eb0 0x20 /usr/lib/gcc/arm-none-eabi/14.1.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memset.o) + .debug_frame 0x00003ed0 0x2c /usr/lib/gcc/arm-none-eabi/14.1.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-init.o) + .debug_frame 0x00003efc 0x28 /usr/lib/gcc/arm-none-eabi/14.1.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memcpy-stub.o) + .debug_frame 0x00003f24 0x2c /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/libgcc.a(_aeabi_uldivmod.o) + .debug_frame 0x00003f50 0x34 /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/libgcc.a(_udivmoddi4.o) .debug_loclists - 0x00000000 0x12ba1 + 0x00000000 0x12ba2 .debug_loclists 0x00000000 0x2d8 build/debug/stm32h7xx_hal.o .debug_loclists @@ -3438,37 +3440,37 @@ LOAD /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/libgcc.a .debug_loclists 0x00007525 0x116c build/debug/stm32h7xx_hal_ltdc.o .debug_loclists - 0x00008691 0x275 build/debug/stm32h7xx_hal_msp.o + 0x00008691 0x276 build/debug/stm32h7xx_hal_msp.o .debug_loclists - 0x00008906 0xd74 build/debug/stm32h7xx_hal_pcd.o + 0x00008907 0xd74 build/debug/stm32h7xx_hal_pcd.o .debug_loclists - 0x0000967a 0x18e build/debug/stm32h7xx_hal_pcd_ex.o + 0x0000967b 0x18e build/debug/stm32h7xx_hal_pcd_ex.o .debug_loclists - 0x00009808 0x2b2 build/debug/stm32h7xx_hal_pwr_ex.o + 0x00009809 0x2b2 build/debug/stm32h7xx_hal_pwr_ex.o .debug_loclists - 0x00009aba 0x621 build/debug/stm32h7xx_hal_rcc.o + 0x00009abb 0x621 build/debug/stm32h7xx_hal_rcc.o .debug_loclists - 0x0000a0db 0x1426 build/debug/stm32h7xx_hal_rcc_ex.o + 0x0000a0dc 0x1426 build/debug/stm32h7xx_hal_rcc_ex.o .debug_loclists - 0x0000b501 0xa76 build/debug/stm32h7xx_hal_sdram.o + 0x0000b502 0xa76 build/debug/stm32h7xx_hal_sdram.o .debug_loclists - 0x0000bf77 0x38d3 build/debug/stm32h7xx_hal_uart.o + 0x0000bf78 0x38d3 build/debug/stm32h7xx_hal_uart.o .debug_loclists - 0x0000f84a 0x7dc build/debug/stm32h7xx_hal_uart_ex.o + 0x0000f84b 0x7dc build/debug/stm32h7xx_hal_uart_ex.o .debug_loclists - 0x00010026 0x578 build/debug/stm32h7xx_ll_fmc.o + 0x00010027 0x578 build/debug/stm32h7xx_ll_fmc.o .debug_loclists - 0x0001059e 0x18ca build/debug/stm32h7xx_ll_usb.o + 0x0001059f 0x18ca build/debug/stm32h7xx_ll_usb.o .debug_loclists - 0x00011e68 0x120 build/debug/system_stm32h7xx.o + 0x00011e69 0x120 build/debug/system_stm32h7xx.o .debug_loclists - 0x00011f88 0x4d /usr/lib/gcc/arm-none-eabi/14.1.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memset.o) + 0x00011f89 0x4d /usr/lib/gcc/arm-none-eabi/14.1.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memset.o) .debug_loclists - 0x00011fd5 0x54 /usr/lib/gcc/arm-none-eabi/14.1.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-init.o) + 0x00011fd6 0x54 /usr/lib/gcc/arm-none-eabi/14.1.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-init.o) .debug_loclists - 0x00012029 0xad /usr/lib/gcc/arm-none-eabi/14.1.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memcpy-stub.o) + 0x0001202a 0xad /usr/lib/gcc/arm-none-eabi/14.1.0/../../../../arm-none-eabi/lib/thumb/v7e-m+dp/hard/libc_nano.a(libc_a-memcpy-stub.o) .debug_loclists - 0x000120d6 0xacb /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/libgcc.a(_udivmoddi4.o) + 0x000120d7 0xacb /usr/lib/gcc/arm-none-eabi/14.1.0/thumb/v7e-m+dp/hard/libgcc.a(_udivmoddi4.o) .debug_line_str 0x00000000 0x125 @@ -4288,7 +4290,7 @@ LPTIM3_IRQHandler build/debug/startup_stm32h7a3x LPTIM4_IRQHandler build/debug/startup_stm32h7a3xx.o LPTIM5_IRQHandler build/debug/startup_stm32h7a3xx.o LPUART1_IRQHandler build/debug/startup_stm32h7a3xx.o -LTDC_ER_IRQHandler build/debug/startup_stm32h7a3xx.o +LTDC_ER_IRQHandler build/debug/stm32h7xx_it.o LTDC_IRQHandler build/debug/stm32h7xx_it.o MDIOS_IRQHandler build/debug/startup_stm32h7a3xx.o MDIOS_WKUP_IRQHandler build/debug/startup_stm32h7a3xx.o