FaSTTUBe/ams-slave-22
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ams-slave-22/Debug/AMS_Slave.list

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AMS_Slave.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 000001c4 08000000 08000000 00010000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00004f18 080001c4 080001c4 000101c4 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000224 080050dc 080050dc 000150dc 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08005300 08005300 00020074 2**0
CONTENTS
4 .ARM 00000008 08005300 08005300 00015300 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
5 .preinit_array 00000000 08005308 08005308 00020074 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 08005308 08005308 00015308 2**2
CONTENTS, ALLOC, LOAD, DATA
7 .fini_array 00000004 0800530c 0800530c 0001530c 2**2
CONTENTS, ALLOC, LOAD, DATA
8 .data 00000074 20000000 08005310 00020000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 000002fc 20000074 08005384 00020074 2**2
ALLOC
10 ._user_heap_stack 00000600 20000370 08005384 00020370 2**0
ALLOC
11 .ARM.attributes 00000030 00000000 00000000 00020074 2**0
CONTENTS, READONLY
12 .debug_info 000124ed 00000000 00000000 000200a4 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 0000277f 00000000 00000000 00032591 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 00000d00 00000000 00000000 00034d10 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_ranges 00000c30 00000000 00000000 00035a10 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 000204b4 00000000 00000000 00036640 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 00011116 00000000 00000000 00056af4 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 000bf5d6 00000000 00000000 00067c0a 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000053 00000000 00000000 001271e0 2**0
CONTENTS, READONLY
20 .debug_frame 0000378c 00000000 00000000 00127234 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
080001c4 <__do_global_dtors_aux>:
80001c4: b510 push {r4, lr}
80001c6: 4c05 ldr r4, [pc, #20] ; (80001dc <__do_global_dtors_aux+0x18>)
80001c8: 7823 ldrb r3, [r4, #0]
80001ca: b933 cbnz r3, 80001da <__do_global_dtors_aux+0x16>
80001cc: 4b04 ldr r3, [pc, #16] ; (80001e0 <__do_global_dtors_aux+0x1c>)
80001ce: b113 cbz r3, 80001d6 <__do_global_dtors_aux+0x12>
80001d0: 4804 ldr r0, [pc, #16] ; (80001e4 <__do_global_dtors_aux+0x20>)
80001d2: f3af 8000 nop.w
80001d6: 2301 movs r3, #1
80001d8: 7023 strb r3, [r4, #0]
80001da: bd10 pop {r4, pc}
80001dc: 20000074 .word 0x20000074
80001e0: 00000000 .word 0x00000000
80001e4: 080050c4 .word 0x080050c4
080001e8 <frame_dummy>:
80001e8: b508 push {r3, lr}
80001ea: 4b03 ldr r3, [pc, #12] ; (80001f8 <frame_dummy+0x10>)
80001ec: b11b cbz r3, 80001f6 <frame_dummy+0xe>
80001ee: 4903 ldr r1, [pc, #12] ; (80001fc <frame_dummy+0x14>)
80001f0: 4803 ldr r0, [pc, #12] ; (8000200 <frame_dummy+0x18>)
80001f2: f3af 8000 nop.w
80001f6: bd08 pop {r3, pc}
80001f8: 00000000 .word 0x00000000
80001fc: 20000078 .word 0x20000078
8000200: 080050c4 .word 0x080050c4
08000204 <__aeabi_uldivmod>:
8000204: b953 cbnz r3, 800021c <__aeabi_uldivmod+0x18>
8000206: b94a cbnz r2, 800021c <__aeabi_uldivmod+0x18>
8000208: 2900 cmp r1, #0
800020a: bf08 it eq
800020c: 2800 cmpeq r0, #0
800020e: bf1c itt ne
8000210: f04f 31ff movne.w r1, #4294967295
8000214: f04f 30ff movne.w r0, #4294967295
8000218: f000 b96e b.w 80004f8 <__aeabi_idiv0>
800021c: f1ad 0c08 sub.w ip, sp, #8
8000220: e96d ce04 strd ip, lr, [sp, #-16]!
8000224: f000 f806 bl 8000234 <__udivmoddi4>
8000228: f8dd e004 ldr.w lr, [sp, #4]
800022c: e9dd 2302 ldrd r2, r3, [sp, #8]
8000230: b004 add sp, #16
8000232: 4770 bx lr
08000234 <__udivmoddi4>:
8000234: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
8000238: 9d08 ldr r5, [sp, #32]
800023a: 4604 mov r4, r0
800023c: 468c mov ip, r1
800023e: 2b00 cmp r3, #0
8000240: f040 8083 bne.w 800034a <__udivmoddi4+0x116>
8000244: 428a cmp r2, r1
8000246: 4617 mov r7, r2
8000248: d947 bls.n 80002da <__udivmoddi4+0xa6>
800024a: fab2 f282 clz r2, r2
800024e: b142 cbz r2, 8000262 <__udivmoddi4+0x2e>
8000250: f1c2 0020 rsb r0, r2, #32
8000254: fa24 f000 lsr.w r0, r4, r0
8000258: 4091 lsls r1, r2
800025a: 4097 lsls r7, r2
800025c: ea40 0c01 orr.w ip, r0, r1
8000260: 4094 lsls r4, r2
8000262: ea4f 4817 mov.w r8, r7, lsr #16
8000266: 0c23 lsrs r3, r4, #16
8000268: fbbc f6f8 udiv r6, ip, r8
800026c: fa1f fe87 uxth.w lr, r7
8000270: fb08 c116 mls r1, r8, r6, ip
8000274: ea43 4301 orr.w r3, r3, r1, lsl #16
8000278: fb06 f10e mul.w r1, r6, lr
800027c: 4299 cmp r1, r3
800027e: d909 bls.n 8000294 <__udivmoddi4+0x60>
8000280: 18fb adds r3, r7, r3
8000282: f106 30ff add.w r0, r6, #4294967295
8000286: f080 8119 bcs.w 80004bc <__udivmoddi4+0x288>
800028a: 4299 cmp r1, r3
800028c: f240 8116 bls.w 80004bc <__udivmoddi4+0x288>
8000290: 3e02 subs r6, #2
8000292: 443b add r3, r7
8000294: 1a5b subs r3, r3, r1
8000296: b2a4 uxth r4, r4
8000298: fbb3 f0f8 udiv r0, r3, r8
800029c: fb08 3310 mls r3, r8, r0, r3
80002a0: ea44 4403 orr.w r4, r4, r3, lsl #16
80002a4: fb00 fe0e mul.w lr, r0, lr
80002a8: 45a6 cmp lr, r4
80002aa: d909 bls.n 80002c0 <__udivmoddi4+0x8c>
80002ac: 193c adds r4, r7, r4
80002ae: f100 33ff add.w r3, r0, #4294967295
80002b2: f080 8105 bcs.w 80004c0 <__udivmoddi4+0x28c>
80002b6: 45a6 cmp lr, r4
80002b8: f240 8102 bls.w 80004c0 <__udivmoddi4+0x28c>
80002bc: 3802 subs r0, #2
80002be: 443c add r4, r7
80002c0: ea40 4006 orr.w r0, r0, r6, lsl #16
80002c4: eba4 040e sub.w r4, r4, lr
80002c8: 2600 movs r6, #0
80002ca: b11d cbz r5, 80002d4 <__udivmoddi4+0xa0>
80002cc: 40d4 lsrs r4, r2
80002ce: 2300 movs r3, #0
80002d0: e9c5 4300 strd r4, r3, [r5]
80002d4: 4631 mov r1, r6
80002d6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
80002da: b902 cbnz r2, 80002de <__udivmoddi4+0xaa>
80002dc: deff udf #255 ; 0xff
80002de: fab2 f282 clz r2, r2
80002e2: 2a00 cmp r2, #0
80002e4: d150 bne.n 8000388 <__udivmoddi4+0x154>
80002e6: 1bcb subs r3, r1, r7
80002e8: ea4f 4e17 mov.w lr, r7, lsr #16
80002ec: fa1f f887 uxth.w r8, r7
80002f0: 2601 movs r6, #1
80002f2: fbb3 fcfe udiv ip, r3, lr
80002f6: 0c21 lsrs r1, r4, #16
80002f8: fb0e 331c mls r3, lr, ip, r3
80002fc: ea41 4103 orr.w r1, r1, r3, lsl #16
8000300: fb08 f30c mul.w r3, r8, ip
8000304: 428b cmp r3, r1
8000306: d907 bls.n 8000318 <__udivmoddi4+0xe4>
8000308: 1879 adds r1, r7, r1
800030a: f10c 30ff add.w r0, ip, #4294967295
800030e: d202 bcs.n 8000316 <__udivmoddi4+0xe2>
8000310: 428b cmp r3, r1
8000312: f200 80e9 bhi.w 80004e8 <__udivmoddi4+0x2b4>
8000316: 4684 mov ip, r0
8000318: 1ac9 subs r1, r1, r3
800031a: b2a3 uxth r3, r4
800031c: fbb1 f0fe udiv r0, r1, lr
8000320: fb0e 1110 mls r1, lr, r0, r1
8000324: ea43 4401 orr.w r4, r3, r1, lsl #16
8000328: fb08 f800 mul.w r8, r8, r0
800032c: 45a0 cmp r8, r4
800032e: d907 bls.n 8000340 <__udivmoddi4+0x10c>
8000330: 193c adds r4, r7, r4
8000332: f100 33ff add.w r3, r0, #4294967295
8000336: d202 bcs.n 800033e <__udivmoddi4+0x10a>
8000338: 45a0 cmp r8, r4
800033a: f200 80d9 bhi.w 80004f0 <__udivmoddi4+0x2bc>
800033e: 4618 mov r0, r3
8000340: eba4 0408 sub.w r4, r4, r8
8000344: ea40 400c orr.w r0, r0, ip, lsl #16
8000348: e7bf b.n 80002ca <__udivmoddi4+0x96>
800034a: 428b cmp r3, r1
800034c: d909 bls.n 8000362 <__udivmoddi4+0x12e>
800034e: 2d00 cmp r5, #0
8000350: f000 80b1 beq.w 80004b6 <__udivmoddi4+0x282>
8000354: 2600 movs r6, #0
8000356: e9c5 0100 strd r0, r1, [r5]
800035a: 4630 mov r0, r6
800035c: 4631 mov r1, r6
800035e: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
8000362: fab3 f683 clz r6, r3
8000366: 2e00 cmp r6, #0
8000368: d14a bne.n 8000400 <__udivmoddi4+0x1cc>
800036a: 428b cmp r3, r1
800036c: d302 bcc.n 8000374 <__udivmoddi4+0x140>
800036e: 4282 cmp r2, r0
8000370: f200 80b8 bhi.w 80004e4 <__udivmoddi4+0x2b0>
8000374: 1a84 subs r4, r0, r2
8000376: eb61 0103 sbc.w r1, r1, r3
800037a: 2001 movs r0, #1
800037c: 468c mov ip, r1
800037e: 2d00 cmp r5, #0
8000380: d0a8 beq.n 80002d4 <__udivmoddi4+0xa0>
8000382: e9c5 4c00 strd r4, ip, [r5]
8000386: e7a5 b.n 80002d4 <__udivmoddi4+0xa0>
8000388: f1c2 0320 rsb r3, r2, #32
800038c: fa20 f603 lsr.w r6, r0, r3
8000390: 4097 lsls r7, r2
8000392: fa01 f002 lsl.w r0, r1, r2
8000396: ea4f 4e17 mov.w lr, r7, lsr #16
800039a: 40d9 lsrs r1, r3
800039c: 4330 orrs r0, r6
800039e: 0c03 lsrs r3, r0, #16
80003a0: fbb1 f6fe udiv r6, r1, lr
80003a4: fa1f f887 uxth.w r8, r7
80003a8: fb0e 1116 mls r1, lr, r6, r1
80003ac: ea43 4301 orr.w r3, r3, r1, lsl #16
80003b0: fb06 f108 mul.w r1, r6, r8
80003b4: 4299 cmp r1, r3
80003b6: fa04 f402 lsl.w r4, r4, r2
80003ba: d909 bls.n 80003d0 <__udivmoddi4+0x19c>
80003bc: 18fb adds r3, r7, r3
80003be: f106 3cff add.w ip, r6, #4294967295
80003c2: f080 808d bcs.w 80004e0 <__udivmoddi4+0x2ac>
80003c6: 4299 cmp r1, r3
80003c8: f240 808a bls.w 80004e0 <__udivmoddi4+0x2ac>
80003cc: 3e02 subs r6, #2
80003ce: 443b add r3, r7
80003d0: 1a5b subs r3, r3, r1
80003d2: b281 uxth r1, r0
80003d4: fbb3 f0fe udiv r0, r3, lr
80003d8: fb0e 3310 mls r3, lr, r0, r3
80003dc: ea41 4103 orr.w r1, r1, r3, lsl #16
80003e0: fb00 f308 mul.w r3, r0, r8
80003e4: 428b cmp r3, r1
80003e6: d907 bls.n 80003f8 <__udivmoddi4+0x1c4>
80003e8: 1879 adds r1, r7, r1
80003ea: f100 3cff add.w ip, r0, #4294967295
80003ee: d273 bcs.n 80004d8 <__udivmoddi4+0x2a4>
80003f0: 428b cmp r3, r1
80003f2: d971 bls.n 80004d8 <__udivmoddi4+0x2a4>
80003f4: 3802 subs r0, #2
80003f6: 4439 add r1, r7
80003f8: 1acb subs r3, r1, r3
80003fa: ea40 4606 orr.w r6, r0, r6, lsl #16
80003fe: e778 b.n 80002f2 <__udivmoddi4+0xbe>
8000400: f1c6 0c20 rsb ip, r6, #32
8000404: fa03 f406 lsl.w r4, r3, r6
8000408: fa22 f30c lsr.w r3, r2, ip
800040c: 431c orrs r4, r3
800040e: fa20 f70c lsr.w r7, r0, ip
8000412: fa01 f306 lsl.w r3, r1, r6
8000416: ea4f 4e14 mov.w lr, r4, lsr #16
800041a: fa21 f10c lsr.w r1, r1, ip
800041e: 431f orrs r7, r3
8000420: 0c3b lsrs r3, r7, #16
8000422: fbb1 f9fe udiv r9, r1, lr
8000426: fa1f f884 uxth.w r8, r4
800042a: fb0e 1119 mls r1, lr, r9, r1
800042e: ea43 4101 orr.w r1, r3, r1, lsl #16
8000432: fb09 fa08 mul.w sl, r9, r8
8000436: 458a cmp sl, r1
8000438: fa02 f206 lsl.w r2, r2, r6
800043c: fa00 f306 lsl.w r3, r0, r6
8000440: d908 bls.n 8000454 <__udivmoddi4+0x220>
8000442: 1861 adds r1, r4, r1
8000444: f109 30ff add.w r0, r9, #4294967295
8000448: d248 bcs.n 80004dc <__udivmoddi4+0x2a8>
800044a: 458a cmp sl, r1
800044c: d946 bls.n 80004dc <__udivmoddi4+0x2a8>
800044e: f1a9 0902 sub.w r9, r9, #2
8000452: 4421 add r1, r4
8000454: eba1 010a sub.w r1, r1, sl
8000458: b2bf uxth r7, r7
800045a: fbb1 f0fe udiv r0, r1, lr
800045e: fb0e 1110 mls r1, lr, r0, r1
8000462: ea47 4701 orr.w r7, r7, r1, lsl #16
8000466: fb00 f808 mul.w r8, r0, r8
800046a: 45b8 cmp r8, r7
800046c: d907 bls.n 800047e <__udivmoddi4+0x24a>
800046e: 19e7 adds r7, r4, r7
8000470: f100 31ff add.w r1, r0, #4294967295
8000474: d22e bcs.n 80004d4 <__udivmoddi4+0x2a0>
8000476: 45b8 cmp r8, r7
8000478: d92c bls.n 80004d4 <__udivmoddi4+0x2a0>
800047a: 3802 subs r0, #2
800047c: 4427 add r7, r4
800047e: ea40 4009 orr.w r0, r0, r9, lsl #16
8000482: eba7 0708 sub.w r7, r7, r8
8000486: fba0 8902 umull r8, r9, r0, r2
800048a: 454f cmp r7, r9
800048c: 46c6 mov lr, r8
800048e: 4649 mov r1, r9
8000490: d31a bcc.n 80004c8 <__udivmoddi4+0x294>
8000492: d017 beq.n 80004c4 <__udivmoddi4+0x290>
8000494: b15d cbz r5, 80004ae <__udivmoddi4+0x27a>
8000496: ebb3 020e subs.w r2, r3, lr
800049a: eb67 0701 sbc.w r7, r7, r1
800049e: fa07 fc0c lsl.w ip, r7, ip
80004a2: 40f2 lsrs r2, r6
80004a4: ea4c 0202 orr.w r2, ip, r2
80004a8: 40f7 lsrs r7, r6
80004aa: e9c5 2700 strd r2, r7, [r5]
80004ae: 2600 movs r6, #0
80004b0: 4631 mov r1, r6
80004b2: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
80004b6: 462e mov r6, r5
80004b8: 4628 mov r0, r5
80004ba: e70b b.n 80002d4 <__udivmoddi4+0xa0>
80004bc: 4606 mov r6, r0
80004be: e6e9 b.n 8000294 <__udivmoddi4+0x60>
80004c0: 4618 mov r0, r3
80004c2: e6fd b.n 80002c0 <__udivmoddi4+0x8c>
80004c4: 4543 cmp r3, r8
80004c6: d2e5 bcs.n 8000494 <__udivmoddi4+0x260>
80004c8: ebb8 0e02 subs.w lr, r8, r2
80004cc: eb69 0104 sbc.w r1, r9, r4
80004d0: 3801 subs r0, #1
80004d2: e7df b.n 8000494 <__udivmoddi4+0x260>
80004d4: 4608 mov r0, r1
80004d6: e7d2 b.n 800047e <__udivmoddi4+0x24a>
80004d8: 4660 mov r0, ip
80004da: e78d b.n 80003f8 <__udivmoddi4+0x1c4>
80004dc: 4681 mov r9, r0
80004de: e7b9 b.n 8000454 <__udivmoddi4+0x220>
80004e0: 4666 mov r6, ip
80004e2: e775 b.n 80003d0 <__udivmoddi4+0x19c>
80004e4: 4630 mov r0, r6
80004e6: e74a b.n 800037e <__udivmoddi4+0x14a>
80004e8: f1ac 0c02 sub.w ip, ip, #2
80004ec: 4439 add r1, r7
80004ee: e713 b.n 8000318 <__udivmoddi4+0xe4>
80004f0: 3802 subs r0, #2
80004f2: 443c add r4, r7
80004f4: e724 b.n 8000340 <__udivmoddi4+0x10c>
80004f6: bf00 nop
080004f8 <__aeabi_idiv0>:
80004f8: 4770 bx lr
80004fa: bf00 nop
080004fc <ams_can_init>:
#include "TMP144.h"
static CAN_HandleTypeDef* handle_ams;
static CAN_HandleTypeDef* handle_car;
void ams_can_init(CAN_HandleTypeDef* ams_handle, CAN_HandleTypeDef* car_handle) {
80004fc: b580 push {r7, lr}
80004fe: b08c sub sp, #48 ; 0x30
8000500: af00 add r7, sp, #0
8000502: 6078 str r0, [r7, #4]
8000504: 6039 str r1, [r7, #0]
handle_ams = ams_handle;
8000506: 4a2c ldr r2, [pc, #176] ; (80005b8 <ams_can_init+0xbc>)
8000508: 687b ldr r3, [r7, #4]
800050a: 6013 str r3, [r2, #0]
handle_car = car_handle;
800050c: 4a2b ldr r2, [pc, #172] ; (80005bc <ams_can_init+0xc0>)
800050e: 683b ldr r3, [r7, #0]
8000510: 6013 str r3, [r2, #0]
// Configure filters
CAN_FilterTypeDef filter_car;
filter_car.FilterBank = 14;
8000512: 230e movs r3, #14
8000514: 61fb str r3, [r7, #28]
filter_car.FilterMode = CAN_FILTERMODE_IDMASK;
8000516: 2300 movs r3, #0
8000518: 623b str r3, [r7, #32]
filter_car.FilterScale = CAN_FILTERSCALE_32BIT;
800051a: 2301 movs r3, #1
800051c: 627b str r3, [r7, #36] ; 0x24
filter_car.FilterIdHigh = CAN_ID_AMS_SLAVE_HEARTBEAT_BASE >> 16;
800051e: 2300 movs r3, #0
8000520: 60bb str r3, [r7, #8]
filter_car.FilterIdLow = CAN_ID_AMS_SLAVE_HEARTBEAT_BASE & 0xFFFF;
8000522: f44f 7380 mov.w r3, #256 ; 0x100
8000526: 60fb str r3, [r7, #12]
filter_car.FilterMaskIdHigh = 0xFFFF;
8000528: f64f 73ff movw r3, #65535 ; 0xffff
800052c: 613b str r3, [r7, #16]
filter_car.FilterMaskIdLow = 0xFF00;
800052e: f44f 437f mov.w r3, #65280 ; 0xff00
8000532: 617b str r3, [r7, #20]
filter_car.FilterFIFOAssignment = CAN_RX_FIFO0;
8000534: 2300 movs r3, #0
8000536: 61bb str r3, [r7, #24]
filter_car.FilterActivation = ENABLE;
8000538: 2301 movs r3, #1
800053a: 62bb str r3, [r7, #40] ; 0x28
filter_car.SlaveStartFilterBank = 14;
800053c: 230e movs r3, #14
800053e: 62fb str r3, [r7, #44] ; 0x2c
if (HAL_CAN_ConfigFilter(handle_car, &filter_car) != HAL_OK) {
8000540: 4b1e ldr r3, [pc, #120] ; (80005bc <ams_can_init+0xc0>)
8000542: 681b ldr r3, [r3, #0]
8000544: f107 0208 add.w r2, r7, #8
8000548: 4611 mov r1, r2
800054a: 4618 mov r0, r3
800054c: f001 fdb8 bl 80020c0 <HAL_CAN_ConfigFilter>
8000550: 4603 mov r3, r0
8000552: 2b00 cmp r3, #0
8000554: d001 beq.n 800055a <ams_can_init+0x5e>
Error_Handler();
8000556: f001 f8e3 bl 8001720 <Error_Handler>
}
// Start peripheral
if (HAL_CAN_Start(handle_ams) != HAL_OK) {
800055a: 4b17 ldr r3, [pc, #92] ; (80005b8 <ams_can_init+0xbc>)
800055c: 681b ldr r3, [r3, #0]
800055e: 4618 mov r0, r3
8000560: f001 fe8e bl 8002280 <HAL_CAN_Start>
8000564: 4603 mov r3, r0
8000566: 2b00 cmp r3, #0
8000568: d001 beq.n 800056e <ams_can_init+0x72>
Error_Handler();
800056a: f001 f8d9 bl 8001720 <Error_Handler>
}
if (HAL_CAN_Start(handle_car) != HAL_OK) {
800056e: 4b13 ldr r3, [pc, #76] ; (80005bc <ams_can_init+0xc0>)
8000570: 681b ldr r3, [r3, #0]
8000572: 4618 mov r0, r3
8000574: f001 fe84 bl 8002280 <HAL_CAN_Start>
8000578: 4603 mov r3, r0
800057a: 2b00 cmp r3, #0
800057c: d001 beq.n 8000582 <ams_can_init+0x86>
Error_Handler();
800057e: f001 f8cf bl 8001720 <Error_Handler>
}
// Activate RX notifications
if (HAL_CAN_ActivateNotification(handle_ams, CAN_IT_RX_FIFO0_MSG_PENDING) != HAL_OK) {
8000582: 4b0d ldr r3, [pc, #52] ; (80005b8 <ams_can_init+0xbc>)
8000584: 681b ldr r3, [r3, #0]
8000586: 2102 movs r1, #2
8000588: 4618 mov r0, r3
800058a: f002 f8aa bl 80026e2 <HAL_CAN_ActivateNotification>
800058e: 4603 mov r3, r0
8000590: 2b00 cmp r3, #0
8000592: d001 beq.n 8000598 <ams_can_init+0x9c>
Error_Handler();
8000594: f001 f8c4 bl 8001720 <Error_Handler>
}
if (HAL_CAN_ActivateNotification(handle_car, CAN_IT_RX_FIFO0_MSG_PENDING | CAN_IT_ERROR | CAN_IT_LAST_ERROR_CODE) != HAL_OK) {
8000598: 4b08 ldr r3, [pc, #32] ; (80005bc <ams_can_init+0xc0>)
800059a: 681b ldr r3, [r3, #0]
800059c: f648 0102 movw r1, #34818 ; 0x8802
80005a0: 4618 mov r0, r3
80005a2: f002 f89e bl 80026e2 <HAL_CAN_ActivateNotification>
80005a6: 4603 mov r3, r0
80005a8: 2b00 cmp r3, #0
80005aa: d001 beq.n 80005b0 <ams_can_init+0xb4>
Error_Handler();
80005ac: f001 f8b8 bl 8001720 <Error_Handler>
}
}
80005b0: bf00 nop
80005b2: 3730 adds r7, #48 ; 0x30
80005b4: 46bd mov sp, r7
80005b6: bd80 pop {r7, pc}
80005b8: 20000090 .word 0x20000090
80005bc: 20000094 .word 0x20000094
080005c0 <HAL_CAN_RxFifo0MsgPendingCallback>:
static int cb_triggered = 0;
void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *handle) {
80005c0: b580 push {r7, lr}
80005c2: b082 sub sp, #8
80005c4: af00 add r7, sp, #0
80005c6: 6078 str r0, [r7, #4]
static CAN_RxHeaderTypeDef header;
static uint8_t data[8];
cb_triggered = 1;
80005c8: 4b13 ldr r3, [pc, #76] ; (8000618 <HAL_CAN_RxFifo0MsgPendingCallback+0x58>)
80005ca: 2201 movs r2, #1
80005cc: 601a str r2, [r3, #0]
if (HAL_CAN_GetRxMessage(handle, CAN_RX_FIFO0, &header, data) != HAL_OK) {
80005ce: 4b13 ldr r3, [pc, #76] ; (800061c <HAL_CAN_RxFifo0MsgPendingCallback+0x5c>)
80005d0: 4a13 ldr r2, [pc, #76] ; (8000620 <HAL_CAN_RxFifo0MsgPendingCallback+0x60>)
80005d2: 2100 movs r1, #0
80005d4: 6878 ldr r0, [r7, #4]
80005d6: f001 ff72 bl 80024be <HAL_CAN_GetRxMessage>
80005da: 4603 mov r3, r0
80005dc: 2b00 cmp r3, #0
80005de: d001 beq.n 80005e4 <HAL_CAN_RxFifo0MsgPendingCallback+0x24>
Error_Handler();
80005e0: f001 f89e bl 8001720 <Error_Handler>
}
if (handle == handle_ams) {
80005e4: 4b0f ldr r3, [pc, #60] ; (8000624 <HAL_CAN_RxFifo0MsgPendingCallback+0x64>)
80005e6: 681b ldr r3, [r3, #0]
80005e8: 687a ldr r2, [r7, #4]
80005ea: 429a cmp r2, r3
80005ec: d104 bne.n 80005f8 <HAL_CAN_RxFifo0MsgPendingCallback+0x38>
ams_can_handle_ams_msg(&header, data);
80005ee: 490b ldr r1, [pc, #44] ; (800061c <HAL_CAN_RxFifo0MsgPendingCallback+0x5c>)
80005f0: 480b ldr r0, [pc, #44] ; (8000620 <HAL_CAN_RxFifo0MsgPendingCallback+0x60>)
80005f2: f000 f81b bl 800062c <ams_can_handle_ams_msg>
} else if (handle == handle_car) {
ams_can_handle_car_msg(&header, data);
} else {
Error_Handler();
}
}
80005f6: e00b b.n 8000610 <HAL_CAN_RxFifo0MsgPendingCallback+0x50>
} else if (handle == handle_car) {
80005f8: 4b0b ldr r3, [pc, #44] ; (8000628 <HAL_CAN_RxFifo0MsgPendingCallback+0x68>)
80005fa: 681b ldr r3, [r3, #0]
80005fc: 687a ldr r2, [r7, #4]
80005fe: 429a cmp r2, r3
8000600: d104 bne.n 800060c <HAL_CAN_RxFifo0MsgPendingCallback+0x4c>
ams_can_handle_car_msg(&header, data);
8000602: 4906 ldr r1, [pc, #24] ; (800061c <HAL_CAN_RxFifo0MsgPendingCallback+0x5c>)
8000604: 4806 ldr r0, [pc, #24] ; (8000620 <HAL_CAN_RxFifo0MsgPendingCallback+0x60>)
8000606: f000 f81c bl 8000642 <ams_can_handle_car_msg>
}
800060a: e001 b.n 8000610 <HAL_CAN_RxFifo0MsgPendingCallback+0x50>
Error_Handler();
800060c: f001 f888 bl 8001720 <Error_Handler>
}
8000610: bf00 nop
8000612: 3708 adds r7, #8
8000614: 46bd mov sp, r7
8000616: bd80 pop {r7, pc}
8000618: 20000098 .word 0x20000098
800061c: 200000b8 .word 0x200000b8
8000620: 2000009c .word 0x2000009c
8000624: 20000090 .word 0x20000090
8000628: 20000094 .word 0x20000094
0800062c <ams_can_handle_ams_msg>:
void ams_can_handle_ams_msg(CAN_RxHeaderTypeDef* header, uint8_t* data) {
800062c: b480 push {r7}
800062e: b083 sub sp, #12
8000630: af00 add r7, sp, #0
8000632: 6078 str r0, [r7, #4]
8000634: 6039 str r1, [r7, #0]
}
8000636: bf00 nop
8000638: 370c adds r7, #12
800063a: 46bd mov sp, r7
800063c: f85d 7b04 ldr.w r7, [sp], #4
8000640: 4770 bx lr
08000642 <ams_can_handle_car_msg>:
void ams_can_handle_car_msg(CAN_RxHeaderTypeDef* header, uint8_t* data) {
8000642: b480 push {r7}
8000644: b083 sub sp, #12
8000646: af00 add r7, sp, #0
8000648: 6078 str r0, [r7, #4]
800064a: 6039 str r1, [r7, #0]
}
800064c: bf00 nop
800064e: 370c adds r7, #12
8000650: 46bd mov sp, r7
8000652: f85d 7b04 ldr.w r7, [sp], #4
8000656: 4770 bx lr
08000658 <ams_can_send_heartbeat>:
void ams_can_send_heartbeat() {
8000658: b580 push {r7, lr}
800065a: b086 sub sp, #24
800065c: af00 add r7, sp, #0
static CAN_TxHeaderTypeDef header;
static uint8_t data[8];
static uint8_t SLAVE_ID = 0;
header.IDE = CAN_ID_STD;
800065e: 4b3c ldr r3, [pc, #240] ; (8000750 <ams_can_send_heartbeat+0xf8>)
8000660: 2200 movs r2, #0
8000662: 609a str r2, [r3, #8]
header.DLC = 8;
8000664: 4b3a ldr r3, [pc, #232] ; (8000750 <ams_can_send_heartbeat+0xf8>)
8000666: 2208 movs r2, #8
8000668: 611a str r2, [r3, #16]
header.RTR = CAN_RTR_DATA;
800066a: 4b39 ldr r3, [pc, #228] ; (8000750 <ams_can_send_heartbeat+0xf8>)
800066c: 2200 movs r2, #0
800066e: 60da str r2, [r3, #12]
header.TransmitGlobalTime = DISABLE;
8000670: 4b37 ldr r3, [pc, #220] ; (8000750 <ams_can_send_heartbeat+0xf8>)
8000672: 2200 movs r2, #0
8000674: 751a strb r2, [r3, #20]
for (int i = 0; i < N_CELLS / 2; i++) {
8000676: 2300 movs r3, #0
8000678: 617b str r3, [r7, #20]
800067a: e060 b.n 800073e <ams_can_send_heartbeat+0xe6>
header.StdId = CAN_ID_AMS_SLAVE_HEARTBEAT_BASE | (SLAVE_ID) << 4 | i;
800067c: 4b35 ldr r3, [pc, #212] ; (8000754 <ams_can_send_heartbeat+0xfc>)
800067e: 781b ldrb r3, [r3, #0]
8000680: 011b lsls r3, r3, #4
8000682: f443 7280 orr.w r2, r3, #256 ; 0x100
8000686: 697b ldr r3, [r7, #20]
8000688: 4313 orrs r3, r2
800068a: 461a mov r2, r3
800068c: 4b30 ldr r3, [pc, #192] ; (8000750 <ams_can_send_heartbeat+0xf8>)
800068e: 601a str r2, [r3, #0]
uint16_t v1 = cell_voltages[i * 2];
8000690: 697b ldr r3, [r7, #20]
8000692: 005b lsls r3, r3, #1
8000694: 4a30 ldr r2, [pc, #192] ; (8000758 <ams_can_send_heartbeat+0x100>)
8000696: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
800069a: 827b strh r3, [r7, #18]
uint16_t v2 = cell_voltages[i * 2 + 1];
800069c: 697b ldr r3, [r7, #20]
800069e: 005b lsls r3, r3, #1
80006a0: 3301 adds r3, #1
80006a2: 4a2d ldr r2, [pc, #180] ; (8000758 <ams_can_send_heartbeat+0x100>)
80006a4: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
80006a8: 823b strh r3, [r7, #16]
data[0] = v1 >> 8;
80006aa: 8a7b ldrh r3, [r7, #18]
80006ac: 0a1b lsrs r3, r3, #8
80006ae: b29b uxth r3, r3
80006b0: b2da uxtb r2, r3
80006b2: 4b2a ldr r3, [pc, #168] ; (800075c <ams_can_send_heartbeat+0x104>)
80006b4: 701a strb r2, [r3, #0]
data[1] = v1 & 0xFF;
80006b6: 8a7b ldrh r3, [r7, #18]
80006b8: b2da uxtb r2, r3
80006ba: 4b28 ldr r3, [pc, #160] ; (800075c <ams_can_send_heartbeat+0x104>)
80006bc: 705a strb r2, [r3, #1]
data[2] = v2 >> 8;
80006be: 8a3b ldrh r3, [r7, #16]
80006c0: 0a1b lsrs r3, r3, #8
80006c2: b29b uxth r3, r3
80006c4: b2da uxtb r2, r3
80006c6: 4b25 ldr r3, [pc, #148] ; (800075c <ams_can_send_heartbeat+0x104>)
80006c8: 709a strb r2, [r3, #2]
data[3] = v2 & 0xFF;
80006ca: 8a3b ldrh r3, [r7, #16]
80006cc: b2da uxtb r2, r3
80006ce: 4b23 ldr r3, [pc, #140] ; (800075c <ams_can_send_heartbeat+0x104>)
80006d0: 70da strb r2, [r3, #3]
uint16_t t1 = temperatures[i * 2];
80006d2: 697b ldr r3, [r7, #20]
80006d4: 005b lsls r3, r3, #1
80006d6: 4a22 ldr r2, [pc, #136] ; (8000760 <ams_can_send_heartbeat+0x108>)
80006d8: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
80006dc: 81fb strh r3, [r7, #14]
uint16_t t2 = temperatures[i * 2 + 1];
80006de: 697b ldr r3, [r7, #20]
80006e0: 005b lsls r3, r3, #1
80006e2: 3301 adds r3, #1
80006e4: 4a1e ldr r2, [pc, #120] ; (8000760 <ams_can_send_heartbeat+0x108>)
80006e6: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
80006ea: 81bb strh r3, [r7, #12]
data[4] = t1 >> 8;
80006ec: 89fb ldrh r3, [r7, #14]
80006ee: 0a1b lsrs r3, r3, #8
80006f0: b29b uxth r3, r3
80006f2: b2da uxtb r2, r3
80006f4: 4b19 ldr r3, [pc, #100] ; (800075c <ams_can_send_heartbeat+0x104>)
80006f6: 711a strb r2, [r3, #4]
data[5] = t1 & 0xFF;
80006f8: 89fb ldrh r3, [r7, #14]
80006fa: b2da uxtb r2, r3
80006fc: 4b17 ldr r3, [pc, #92] ; (800075c <ams_can_send_heartbeat+0x104>)
80006fe: 715a strb r2, [r3, #5]
data[6] = t2 >> 8;
8000700: 89bb ldrh r3, [r7, #12]
8000702: 0a1b lsrs r3, r3, #8
8000704: b29b uxth r3, r3
8000706: b2da uxtb r2, r3
8000708: 4b14 ldr r3, [pc, #80] ; (800075c <ams_can_send_heartbeat+0x104>)
800070a: 719a strb r2, [r3, #6]
data[7] = t2 & 0xFF;
800070c: 89bb ldrh r3, [r7, #12]
800070e: b2da uxtb r2, r3
8000710: 4b12 ldr r3, [pc, #72] ; (800075c <ams_can_send_heartbeat+0x104>)
8000712: 71da strb r2, [r3, #7]
uint32_t mailbox;
HAL_StatusTypeDef status;
if ((status = HAL_CAN_AddTxMessage(handle_ams, &header, data, &mailbox)) != HAL_OK) {
8000714: 4b13 ldr r3, [pc, #76] ; (8000764 <ams_can_send_heartbeat+0x10c>)
8000716: 6818 ldr r0, [r3, #0]
8000718: 1d3b adds r3, r7, #4
800071a: 4a10 ldr r2, [pc, #64] ; (800075c <ams_can_send_heartbeat+0x104>)
800071c: 490c ldr r1, [pc, #48] ; (8000750 <ams_can_send_heartbeat+0xf8>)
800071e: f001 fdf3 bl 8002308 <HAL_CAN_AddTxMessage>
8000722: 4603 mov r3, r0
8000724: 72fb strb r3, [r7, #11]
8000726: 7afb ldrb r3, [r7, #11]
8000728: 2b00 cmp r3, #0
800072a: d002 beq.n 8000732 <ams_can_send_heartbeat+0xda>
Error_Handler();
800072c: f000 fff8 bl 8001720 <Error_Handler>
8000730: e002 b.n 8000738 <ams_can_send_heartbeat+0xe0>
} else {
HAL_Delay(100);
8000732: 2064 movs r0, #100 ; 0x64
8000734: f001 fba4 bl 8001e80 <HAL_Delay>
for (int i = 0; i < N_CELLS / 2; i++) {
8000738: 697b ldr r3, [r7, #20]
800073a: 3301 adds r3, #1
800073c: 617b str r3, [r7, #20]
800073e: 697b ldr r3, [r7, #20]
8000740: 2b04 cmp r3, #4
8000742: dd9b ble.n 800067c <ams_can_send_heartbeat+0x24>
}
}
}
8000744: bf00 nop
8000746: bf00 nop
8000748: 3718 adds r7, #24
800074a: 46bd mov sp, r7
800074c: bd80 pop {r7, pc}
800074e: bf00 nop
8000750: 200000c0 .word 0x200000c0
8000754: 200000d8 .word 0x200000d8
8000758: 20000178 .word 0x20000178
800075c: 200000dc .word 0x200000dc
8000760: 20000194 .word 0x20000194
8000764: 20000090 .word 0x20000090
08000768 <afe_init>:
uint8_t bq_status;
uint32_t lastmeasurementtime;
void afe_init(UART_HandleTypeDef* uarthandle)
{
8000768: b580 push {r7, lr}
800076a: b082 sub sp, #8
800076c: af00 add r7, sp, #0
800076e: 6078 str r0, [r7, #4]
//Initialise underlying BQ Communication Functions
init_BQCom(uarthandle);
8000770: 6878 ldr r0, [r7, #4]
8000772: f000 f92b bl 80009cc <init_BQCom>
//Turn the AFE on off on to cycle a full reset
afe_wakeup();
8000776: f000 f837 bl 80007e8 <afe_wakeup>
HAL_Delay(10);
800077a: 200a movs r0, #10
800077c: f001 fb80 bl 8001e80 <HAL_Delay>
afe_shutdown();
8000780: f000 f828 bl 80007d4 <afe_shutdown>
HAL_Delay(100);
8000784: 2064 movs r0, #100 ; 0x64
8000786: f001 fb7b bl 8001e80 <HAL_Delay>
afe_wakeup();
800078a: f000 f82d bl 80007e8 <afe_wakeup>
HAL_Delay(10);
800078e: 200a movs r0, #10
8000790: f001 fb76 bl 8001e80 <HAL_Delay>
bq_status = BQ_INIT_PHASE;
8000794: 4b0e ldr r3, [pc, #56] ; (80007d0 <afe_init+0x68>)
8000796: 2203 movs r2, #3
8000798: 701a strb r2, [r3, #0]
afe_config_communication();
800079a: f000 f8fb bl 8000994 <afe_config_communication>
afe_config_measurement_channels();
800079e: f000 f8d9 bl 8000954 <afe_config_measurement_channels>
afe_config_gpios();
80007a2: f000 f901 bl 80009a8 <afe_config_gpios>
afe_activate_LED();
80007a6: f000 f908 bl 80009ba <afe_activate_LED>
afe_init_fault_thresholds();
80007aa: f000 f8a9 bl 8000900 <afe_init_fault_thresholds>
HAL_Delay(1000);
80007ae: f44f 707a mov.w r0, #1000 ; 0x3e8
80007b2: f001 fb65 bl 8001e80 <HAL_Delay>
afe_update_Checksum();
80007b6: f000 f8b7 bl 8000928 <afe_update_Checksum>
afe_clear_all_faults();
80007ba: f000 f885 bl 80008c8 <afe_clear_all_faults>
HAL_Delay(10);
80007be: 200a movs r0, #10
80007c0: f001 fb5e bl 8001e80 <HAL_Delay>
afe_check_faults();
80007c4: f000 f868 bl 8000898 <afe_check_faults>
}
80007c8: bf00 nop
80007ca: 3708 adds r7, #8
80007cc: 46bd mov sp, r7
80007ce: bd80 pop {r7, pc}
80007d0: 20000174 .word 0x20000174
080007d4 <afe_shutdown>:
void afe_shutdown()
{
80007d4: b580 push {r7, lr}
80007d6: af00 add r7, sp, #0
BQ_Write_Register(DEV_CNTRL, DEV_CNTRL_SIZE, 0x40);
80007d8: 2240 movs r2, #64 ; 0x40
80007da: 2101 movs r1, #1
80007dc: 200c movs r0, #12
80007de: f000 f99b bl 8000b18 <BQ_Write_Register>
}
80007e2: bf00 nop
80007e4: bd80 pop {r7, pc}
...
080007e8 <afe_wakeup>:
void afe_wakeup()
{
80007e8: b580 push {r7, lr}
80007ea: af00 add r7, sp, #0
HAL_GPIO_WritePin(WAKEUP_PORT, WAKEUP_PIN, GPIO_PIN_SET);
80007ec: 2201 movs r2, #1
80007ee: 2110 movs r1, #16
80007f0: 4806 ldr r0, [pc, #24] ; (800080c <afe_wakeup+0x24>)
80007f2: f002 fceb bl 80031cc <HAL_GPIO_WritePin>
HAL_Delay(1);
80007f6: 2001 movs r0, #1
80007f8: f001 fb42 bl 8001e80 <HAL_Delay>
HAL_GPIO_WritePin(WAKEUP_PORT, WAKEUP_PIN, GPIO_PIN_RESET);
80007fc: 2200 movs r2, #0
80007fe: 2110 movs r1, #16
8000800: 4802 ldr r0, [pc, #8] ; (800080c <afe_wakeup+0x24>)
8000802: f002 fce3 bl 80031cc <HAL_GPIO_WritePin>
}
8000806: bf00 nop
8000808: bd80 pop {r7, pc}
800080a: bf00 nop
800080c: 40020400 .word 0x40020400
08000810 <afe_measure>:
void afe_measure()
{
8000810: b580 push {r7, lr}
8000812: b088 sub sp, #32
8000814: af00 add r7, sp, #0
uint8_t cellvoltagebuffer[2*N_CELLS];
uint8_t retval = BQ_ReadMeasurements(cellvoltagebuffer, 2*N_CELLS);
8000816: 1d3b adds r3, r7, #4
8000818: 2114 movs r1, #20
800081a: 4618 mov r0, r3
800081c: f000 fa40 bl 8000ca0 <BQ_ReadMeasurements>
8000820: 4603 mov r3, r0
8000822: 76fb strb r3, [r7, #27]
lastmeasurementtime = HAL_GetTick();
8000824: f001 fb20 bl 8001e68 <HAL_GetTick>
8000828: 4603 mov r3, r0
800082a: 4a18 ldr r2, [pc, #96] ; (800088c <afe_measure+0x7c>)
800082c: 6013 str r3, [r2, #0]
if(retval == 0)
800082e: 7efb ldrb r3, [r7, #27]
8000830: 2b00 cmp r3, #0
8000832: d103 bne.n 800083c <afe_measure+0x2c>
{
bq_status = BQ_ERROR;
8000834: 4b16 ldr r3, [pc, #88] ; (8000890 <afe_measure+0x80>)
8000836: 2204 movs r2, #4
8000838: 701a strb r2, [r3, #0]
for(int n = 0; n < N_CELLS; n++)
{
cell_voltages[N_CELLS-1-n] = (uint16_t) (cellvoltagebuffer[2*n]<<8) + (uint16_t) cellvoltagebuffer[2*n+1];
}
}
}
800083a: e023 b.n 8000884 <afe_measure+0x74>
for(int n = 0; n < N_CELLS; n++)
800083c: 2300 movs r3, #0
800083e: 61fb str r3, [r7, #28]
8000840: e01d b.n 800087e <afe_measure+0x6e>
cell_voltages[N_CELLS-1-n] = (uint16_t) (cellvoltagebuffer[2*n]<<8) + (uint16_t) cellvoltagebuffer[2*n+1];
8000842: 69fb ldr r3, [r7, #28]
8000844: 005b lsls r3, r3, #1
8000846: f107 0220 add.w r2, r7, #32
800084a: 4413 add r3, r2
800084c: f813 3c1c ldrb.w r3, [r3, #-28]
8000850: b29b uxth r3, r3
8000852: 021b lsls r3, r3, #8
8000854: b299 uxth r1, r3
8000856: 69fb ldr r3, [r7, #28]
8000858: 005b lsls r3, r3, #1
800085a: 3301 adds r3, #1
800085c: f107 0220 add.w r2, r7, #32
8000860: 4413 add r3, r2
8000862: f813 3c1c ldrb.w r3, [r3, #-28]
8000866: b29a uxth r2, r3
8000868: 69fb ldr r3, [r7, #28]
800086a: f1c3 0309 rsb r3, r3, #9
800086e: 440a add r2, r1
8000870: b291 uxth r1, r2
8000872: 4a08 ldr r2, [pc, #32] ; (8000894 <afe_measure+0x84>)
8000874: f822 1013 strh.w r1, [r2, r3, lsl #1]
for(int n = 0; n < N_CELLS; n++)
8000878: 69fb ldr r3, [r7, #28]
800087a: 3301 adds r3, #1
800087c: 61fb str r3, [r7, #28]
800087e: 69fb ldr r3, [r7, #28]
8000880: 2b09 cmp r3, #9
8000882: ddde ble.n 8000842 <afe_measure+0x32>
}
8000884: bf00 nop
8000886: 3720 adds r7, #32
8000888: 46bd mov sp, r7
800088a: bd80 pop {r7, pc}
800088c: 20000170 .word 0x20000170
8000890: 20000174 .word 0x20000174
8000894: 20000178 .word 0x20000178
08000898 <afe_check_faults>:
{
}
void afe_check_faults()
{
8000898: b580 push {r7, lr}
800089a: b082 sub sp, #8
800089c: af00 add r7, sp, #0
uint32_t faultflags = 0;
800089e: 2300 movs r3, #0
80008a0: 607b str r3, [r7, #4]
BQ_Read_Register(FAULT_SUM, FAULT_SUM_SIZE, &faultflags);
80008a2: 1d3b adds r3, r7, #4
80008a4: 461a mov r2, r3
80008a6: 2102 movs r1, #2
80008a8: 2052 movs r0, #82 ; 0x52
80008aa: f000 f98a bl 8000bc2 <BQ_Read_Register>
if(faultflags != 0)
80008ae: 687b ldr r3, [r7, #4]
80008b0: 2b00 cmp r3, #0
80008b2: d002 beq.n 80008ba <afe_check_faults+0x22>
{
bq_status = BQ_ERROR;
80008b4: 4b03 ldr r3, [pc, #12] ; (80008c4 <afe_check_faults+0x2c>)
80008b6: 2204 movs r2, #4
80008b8: 701a strb r2, [r3, #0]
}
}
80008ba: bf00 nop
80008bc: 3708 adds r7, #8
80008be: 46bd mov sp, r7
80008c0: bd80 pop {r7, pc}
80008c2: bf00 nop
80008c4: 20000174 .word 0x20000174
080008c8 <afe_clear_all_faults>:
void afe_clear_all_faults()
{
80008c8: b580 push {r7, lr}
80008ca: af00 add r7, sp, #0
BQ_Write_Register(FAULT_SUM, FAULT_SUM_SIZE, 0xFFC0); //Clear all Faults
80008cc: f64f 72c0 movw r2, #65472 ; 0xffc0
80008d0: 2102 movs r1, #2
80008d2: 2052 movs r0, #82 ; 0x52
80008d4: f000 f920 bl 8000b18 <BQ_Write_Register>
bq_status = BQ_STDBY;
80008d8: 4b08 ldr r3, [pc, #32] ; (80008fc <afe_clear_all_faults+0x34>)
80008da: 2202 movs r2, #2
80008dc: 701a strb r2, [r3, #0]
HAL_Delay(1);
80008de: 2001 movs r0, #1
80008e0: f001 face bl 8001e80 <HAL_Delay>
afe_check_faults();
80008e4: f7ff ffd8 bl 8000898 <afe_check_faults>
if(bq_status == BQ_STDBY)
80008e8: 4b04 ldr r3, [pc, #16] ; (80008fc <afe_clear_all_faults+0x34>)
80008ea: 781b ldrb r3, [r3, #0]
80008ec: 2b02 cmp r3, #2
80008ee: d102 bne.n 80008f6 <afe_clear_all_faults+0x2e>
{
bq_status = BQ_RDY;
80008f0: 4b02 ldr r3, [pc, #8] ; (80008fc <afe_clear_all_faults+0x34>)
80008f2: 2201 movs r2, #1
80008f4: 701a strb r2, [r3, #0]
}
}
80008f6: bf00 nop
80008f8: bd80 pop {r7, pc}
80008fa: bf00 nop
80008fc: 20000174 .word 0x20000174
08000900 <afe_init_fault_thresholds>:
void afe_init_fault_thresholds()
{
8000900: b580 push {r7, lr}
8000902: af00 add r7, sp, #0
BQ_Write_Register(FO_CTRL, FO_CTRL_SIZE, 0xC3C0); //Include UV Fault OV Fault COMM SYS CHIP GPI Faults to Fault Output
8000904: f24c 32c0 movw r2, #50112 ; 0xc3c0
8000908: 2102 movs r1, #2
800090a: 206e movs r0, #110 ; 0x6e
800090c: f000 f904 bl 8000b18 <BQ_Write_Register>
BQ_Write_Register(CELL_UV, CELL_UV_SIZE, (CELL_UV_THRESHOLD & 0x03));
8000910: 2200 movs r2, #0
8000912: 2102 movs r1, #2
8000914: 208e movs r0, #142 ; 0x8e
8000916: f000 f8ff bl 8000b18 <BQ_Write_Register>
BQ_Write_Register(CELL_OV,CELL_OV_SIZE,(CELL_OV_THRESHOLD & 0x03));
800091a: 2200 movs r2, #0
800091c: 2102 movs r1, #2
800091e: 2090 movs r0, #144 ; 0x90
8000920: f000 f8fa bl 8000b18 <BQ_Write_Register>
}
8000924: bf00 nop
8000926: bd80 pop {r7, pc}
08000928 <afe_update_Checksum>:
void afe_update_Checksum()
{
8000928: b580 push {r7, lr}
800092a: b082 sub sp, #8
800092c: af00 add r7, sp, #0
uint32_t checksum = 0;
800092e: 2300 movs r3, #0
8000930: 607b str r3, [r7, #4]
BQ_Read_Register(CSUM_RSLT, CSUM_RSLT_SIZE, &checksum);
8000932: 1d3b adds r3, r7, #4
8000934: 461a mov r2, r3
8000936: 2104 movs r1, #4
8000938: 20f4 movs r0, #244 ; 0xf4
800093a: f000 f942 bl 8000bc2 <BQ_Read_Register>
BQ_Write_Register(CSUM, CSUM_SIZE, checksum);
800093e: 687b ldr r3, [r7, #4]
8000940: 461a mov r2, r3
8000942: 2104 movs r1, #4
8000944: 20f0 movs r0, #240 ; 0xf0
8000946: f000 f8e7 bl 8000b18 <BQ_Write_Register>
}
800094a: bf00 nop
800094c: 3708 adds r7, #8
800094e: 46bd mov sp, r7
8000950: bd80 pop {r7, pc}
...
08000954 <afe_config_measurement_channels>:
void afe_config_measurement_channels()
{
8000954: b580 push {r7, lr}
8000956: b084 sub sp, #16
8000958: af00 add r7, sp, #0
uint16_t cellmask = 0b1111111111;
800095a: f240 33ff movw r3, #1023 ; 0x3ff
800095e: 81fb strh r3, [r7, #14]
uint32_t channelmask = cellmask<<16;
8000960: 89fb ldrh r3, [r7, #14]
8000962: 041b lsls r3, r3, #16
8000964: 60bb str r3, [r7, #8]
BQ_Write_Register(NCHAN, NCHAN_SIZE, N_CELLS);
8000966: 220a movs r2, #10
8000968: 2101 movs r1, #1
800096a: 200d movs r0, #13
800096c: f000 f8d4 bl 8000b18 <BQ_Write_Register>
uint32_t channels = 0b1111111111 << 16;
8000970: 4b07 ldr r3, [pc, #28] ; (8000990 <afe_config_measurement_channels+0x3c>)
8000972: 607b str r3, [r7, #4]
BQ_Write_Register(CHANNELS, CHANNELS_SIZE, channels);
8000974: 687a ldr r2, [r7, #4]
8000976: 2104 movs r1, #4
8000978: 2003 movs r0, #3
800097a: f000 f8cd bl 8000b18 <BQ_Write_Register>
BQ_Write_Register(OVERSMPL, OVERSMPL_SIZE, 0xFA); //Oversampling enabled with 4 samples as average
800097e: 22fa movs r2, #250 ; 0xfa
8000980: 2101 movs r1, #1
8000982: 2007 movs r0, #7
8000984: f000 f8c8 bl 8000b18 <BQ_Write_Register>
}
8000988: bf00 nop
800098a: 3710 adds r7, #16
800098c: 46bd mov sp, r7
800098e: bd80 pop {r7, pc}
8000990: 03ff0000 .word 0x03ff0000
08000994 <afe_config_communication>:
void afe_config_communication()
{
8000994: b580 push {r7, lr}
8000996: af00 add r7, sp, #0
BQ_Write_Register(COMCONFIG, COMCONFIG_SIZE, (1 << 12) | (1 << 7)); //Enables UART Transceiver Diables Differential UART
8000998: f44f 5284 mov.w r2, #4224 ; 0x1080
800099c: 2102 movs r1, #2
800099e: 2010 movs r0, #16
80009a0: f000 f8ba bl 8000b18 <BQ_Write_Register>
}
80009a4: bf00 nop
80009a6: bd80 pop {r7, pc}
080009a8 <afe_config_gpios>:
void afe_config_gpios()
{
80009a8: b580 push {r7, lr}
80009aa: af00 add r7, sp, #0
BQ_Write_Register(GPIO_DIR, GPIO_DIR_SIZE, 0x01);
80009ac: 2201 movs r2, #1
80009ae: 2101 movs r1, #1
80009b0: 2078 movs r0, #120 ; 0x78
80009b2: f000 f8b1 bl 8000b18 <BQ_Write_Register>
}
80009b6: bf00 nop
80009b8: bd80 pop {r7, pc}
080009ba <afe_activate_LED>:
void afe_activate_LED()
{
80009ba: b580 push {r7, lr}
80009bc: af00 add r7, sp, #0
BQ_Write_Register(GPIO_OUT, GPIO_OUT_SIZE, 0x01);
80009be: 2201 movs r2, #1
80009c0: 2101 movs r1, #1
80009c2: 2079 movs r0, #121 ; 0x79
80009c4: f000 f8a8 bl 8000b18 <BQ_Write_Register>
}
80009c8: bf00 nop
80009ca: bd80 pop {r7, pc}
080009cc <init_BQCom>:
* Always use the Init Routine before using any other function of the Libary
*
*
*/
void init_BQCom(UART_HandleTypeDef* uarthandle)
{
80009cc: b480 push {r7}
80009ce: b083 sub sp, #12
80009d0: af00 add r7, sp, #0
80009d2: 6078 str r0, [r7, #4]
bq_uart = uarthandle;
80009d4: 4a04 ldr r2, [pc, #16] ; (80009e8 <init_BQCom+0x1c>)
80009d6: 687b ldr r3, [r7, #4]
80009d8: 6013 str r3, [r2, #0]
}
80009da: bf00 nop
80009dc: 370c adds r7, #12
80009de: 46bd mov sp, r7
80009e0: f85d 7b04 ldr.w r7, [sp], #4
80009e4: 4770 bx lr
80009e6: bf00 nop
80009e8: 2000018c .word 0x2000018c
080009ec <Calculate_CRC>:
*
* Returns 1 if the Function was successfull
*
*/
uint16_t Calculate_CRC(uint8_t* message_buffer, uint16_t bufferlength)
{
80009ec: b480 push {r7}
80009ee: b085 sub sp, #20
80009f0: af00 add r7, sp, #0
80009f2: 6078 str r0, [r7, #4]
80009f4: 460b mov r3, r1
80009f6: 807b strh r3, [r7, #2]
uint16_t wCRC = 0;
80009f8: 2300 movs r3, #0
80009fa: 81fb strh r3, [r7, #14]
if(bufferlength < 3)
80009fc: 887b ldrh r3, [r7, #2]
80009fe: 2b02 cmp r3, #2
8000a00: d801 bhi.n 8000a06 <Calculate_CRC+0x1a>
{
return 0;
8000a02: 2300 movs r3, #0
8000a04: e02e b.n 8000a64 <Calculate_CRC+0x78>
}
for (uint32_t i = 0; i < (bufferlength-2); i++)
8000a06: 2300 movs r3, #0
8000a08: 60bb str r3, [r7, #8]
8000a0a: e014 b.n 8000a36 <Calculate_CRC+0x4a>
{
wCRC ^= (message_buffer[i]) & 0x00FF;
8000a0c: 687a ldr r2, [r7, #4]
8000a0e: 68bb ldr r3, [r7, #8]
8000a10: 4413 add r3, r2
8000a12: 781b ldrb r3, [r3, #0]
8000a14: b29a uxth r2, r3
8000a16: 89fb ldrh r3, [r7, #14]
8000a18: 4053 eors r3, r2
8000a1a: 81fb strh r3, [r7, #14]
wCRC = crc16_table[wCRC & 0x00FF] ^ (wCRC >> 8);
8000a1c: 89fb ldrh r3, [r7, #14]
8000a1e: b2db uxtb r3, r3
8000a20: 4a13 ldr r2, [pc, #76] ; (8000a70 <Calculate_CRC+0x84>)
8000a22: f832 2013 ldrh.w r2, [r2, r3, lsl #1]
8000a26: 89fb ldrh r3, [r7, #14]
8000a28: 0a1b lsrs r3, r3, #8
8000a2a: b29b uxth r3, r3
8000a2c: 4053 eors r3, r2
8000a2e: 81fb strh r3, [r7, #14]
for (uint32_t i = 0; i < (bufferlength-2); i++)
8000a30: 68bb ldr r3, [r7, #8]
8000a32: 3301 adds r3, #1
8000a34: 60bb str r3, [r7, #8]
8000a36: 887b ldrh r3, [r7, #2]
8000a38: 3b02 subs r3, #2
8000a3a: 461a mov r2, r3
8000a3c: 68bb ldr r3, [r7, #8]
8000a3e: 4293 cmp r3, r2
8000a40: d3e4 bcc.n 8000a0c <Calculate_CRC+0x20>
}
message_buffer[bufferlength - 1] = (wCRC>>8) & 0xFF; //Upper CRC Byte is LSB of CRC
8000a42: 89fb ldrh r3, [r7, #14]
8000a44: 0a1b lsrs r3, r3, #8
8000a46: b299 uxth r1, r3
8000a48: 887b ldrh r3, [r7, #2]
8000a4a: 3b01 subs r3, #1
8000a4c: 687a ldr r2, [r7, #4]
8000a4e: 4413 add r3, r2
8000a50: b2ca uxtb r2, r1
8000a52: 701a strb r2, [r3, #0]
message_buffer[bufferlength - 2] = (wCRC) & 0xFF; //Lower CRC Byte is MSB of CRC
8000a54: 887b ldrh r3, [r7, #2]
8000a56: 3b02 subs r3, #2
8000a58: 687a ldr r2, [r7, #4]
8000a5a: 4413 add r3, r2
8000a5c: 89fa ldrh r2, [r7, #14]
8000a5e: b2d2 uxtb r2, r2
8000a60: 701a strb r2, [r3, #0]
return 1;
8000a62: 2301 movs r3, #1
}
8000a64: 4618 mov r0, r3
8000a66: 3714 adds r7, #20
8000a68: 46bd mov sp, r7
8000a6a: f85d 7b04 ldr.w r7, [sp], #4
8000a6e: 4770 bx lr
8000a70: 080050dc .word 0x080050dc
08000a74 <Check_CRC>:
*
* Returns 1 if the CRC is correct
*/
uint16_t Check_CRC(uint8_t* message_buffer, uint16_t bufferlength)
{
8000a74: b480 push {r7}
8000a76: b085 sub sp, #20
8000a78: af00 add r7, sp, #0
8000a7a: 6078 str r0, [r7, #4]
8000a7c: 460b mov r3, r1
8000a7e: 807b strh r3, [r7, #2]
uint16_t wCRC = 0;
8000a80: 2300 movs r3, #0
8000a82: 81fb strh r3, [r7, #14]
if(bufferlength < 3)
8000a84: 887b ldrh r3, [r7, #2]
8000a86: 2b02 cmp r3, #2
8000a88: d801 bhi.n 8000a8e <Check_CRC+0x1a>
{
return 0;
8000a8a: 2300 movs r3, #0
8000a8c: e03c b.n 8000b08 <Check_CRC+0x94>
}
for (uint32_t i = 0; i < bufferlength; i++)
8000a8e: 2300 movs r3, #0
8000a90: 60bb str r3, [r7, #8]
8000a92: e014 b.n 8000abe <Check_CRC+0x4a>
{
wCRC ^= (message_buffer[i]) & 0x00FF;
8000a94: 687a ldr r2, [r7, #4]
8000a96: 68bb ldr r3, [r7, #8]
8000a98: 4413 add r3, r2
8000a9a: 781b ldrb r3, [r3, #0]
8000a9c: b29a uxth r2, r3
8000a9e: 89fb ldrh r3, [r7, #14]
8000aa0: 4053 eors r3, r2
8000aa2: 81fb strh r3, [r7, #14]
wCRC = crc16_table[wCRC & 0x00FF] ^ (wCRC >> 8);
8000aa4: 89fb ldrh r3, [r7, #14]
8000aa6: b2db uxtb r3, r3
8000aa8: 4a1a ldr r2, [pc, #104] ; (8000b14 <Check_CRC+0xa0>)
8000aaa: f832 2013 ldrh.w r2, [r2, r3, lsl #1]
8000aae: 89fb ldrh r3, [r7, #14]
8000ab0: 0a1b lsrs r3, r3, #8
8000ab2: b29b uxth r3, r3
8000ab4: 4053 eors r3, r2
8000ab6: 81fb strh r3, [r7, #14]
for (uint32_t i = 0; i < bufferlength; i++)
8000ab8: 68bb ldr r3, [r7, #8]
8000aba: 3301 adds r3, #1
8000abc: 60bb str r3, [r7, #8]
8000abe: 887b ldrh r3, [r7, #2]
8000ac0: 68ba ldr r2, [r7, #8]
8000ac2: 429a cmp r2, r3
8000ac4: d3e6 bcc.n 8000a94 <Check_CRC+0x20>
}
message_buffer[bufferlength - 1] = (wCRC>>8) & 0xFF; //Upper CRC Byte is LSB of CRC
8000ac6: 89fb ldrh r3, [r7, #14]
8000ac8: 0a1b lsrs r3, r3, #8
8000aca: b299 uxth r1, r3
8000acc: 887b ldrh r3, [r7, #2]
8000ace: 3b01 subs r3, #1
8000ad0: 687a ldr r2, [r7, #4]
8000ad2: 4413 add r3, r2
8000ad4: b2ca uxtb r2, r1
8000ad6: 701a strb r2, [r3, #0]
message_buffer[bufferlength - 2] = (wCRC) & 0xFF; //Lower CRC Byte is MSB of CRC
8000ad8: 887b ldrh r3, [r7, #2]
8000ada: 3b02 subs r3, #2
8000adc: 687a ldr r2, [r7, #4]
8000ade: 4413 add r3, r2
8000ae0: 89fa ldrh r2, [r7, #14]
8000ae2: b2d2 uxtb r2, r2
8000ae4: 701a strb r2, [r3, #0]
if((message_buffer[bufferlength - 1] == 0) && (message_buffer[bufferlength - 2] == 0))
8000ae6: 887b ldrh r3, [r7, #2]
8000ae8: 3b01 subs r3, #1
8000aea: 687a ldr r2, [r7, #4]
8000aec: 4413 add r3, r2
8000aee: 781b ldrb r3, [r3, #0]
8000af0: 2b00 cmp r3, #0
8000af2: d108 bne.n 8000b06 <Check_CRC+0x92>
8000af4: 887b ldrh r3, [r7, #2]
8000af6: 3b02 subs r3, #2
8000af8: 687a ldr r2, [r7, #4]
8000afa: 4413 add r3, r2
8000afc: 781b ldrb r3, [r3, #0]
8000afe: 2b00 cmp r3, #0
8000b00: d101 bne.n 8000b06 <Check_CRC+0x92>
{
return 1;
8000b02: 2301 movs r3, #1
8000b04: e000 b.n 8000b08 <Check_CRC+0x94>
}
else
{
return 0;
8000b06: 2300 movs r3, #0
}
}
8000b08: 4618 mov r0, r3
8000b0a: 3714 adds r7, #20
8000b0c: 46bd mov sp, r7
8000b0e: f85d 7b04 ldr.w r7, [sp], #4
8000b12: 4770 bx lr
8000b14: 080050dc .word 0x080050dc
08000b18 <BQ_Write_Register>:
* data defines the data written to the BQ
*
*/
uint32_t BQ_Write_Register(uint8_t registeraddress, uint8_t registersize, uint32_t data)
{
8000b18: b580 push {r7, lr}
8000b1a: b086 sub sp, #24
8000b1c: af00 add r7, sp, #0
8000b1e: 4603 mov r3, r0
8000b20: 603a str r2, [r7, #0]
8000b22: 71fb strb r3, [r7, #7]
8000b24: 460b mov r3, r1
8000b26: 71bb strb r3, [r7, #6]
uint8_t* message = (uint8_t*) calloc(registersize+5,sizeof(uint8_t));
8000b28: 79bb ldrb r3, [r7, #6]
8000b2a: 3305 adds r3, #5
8000b2c: 2101 movs r1, #1
8000b2e: 4618 mov r0, r3
8000b30: f004 f992 bl 8004e58 <calloc>
8000b34: 4603 mov r3, r0
8000b36: 613b str r3, [r7, #16]
message[0] = FRM_WRT_NR | (registersize & 0x07);
8000b38: f997 3006 ldrsb.w r3, [r7, #6]
8000b3c: f003 0307 and.w r3, r3, #7
8000b40: b25b sxtb r3, r3
8000b42: f063 036f orn r3, r3, #111 ; 0x6f
8000b46: b25b sxtb r3, r3
8000b48: b2da uxtb r2, r3
8000b4a: 693b ldr r3, [r7, #16]
8000b4c: 701a strb r2, [r3, #0]
message[1] = 0x00;
8000b4e: 693b ldr r3, [r7, #16]
8000b50: 3301 adds r3, #1
8000b52: 2200 movs r2, #0
8000b54: 701a strb r2, [r3, #0]
message[2] = registeraddress;
8000b56: 693b ldr r3, [r7, #16]
8000b58: 3302 adds r3, #2
8000b5a: 79fa ldrb r2, [r7, #7]
8000b5c: 701a strb r2, [r3, #0]
for(int i = 0; i < registersize;i++)
8000b5e: 2300 movs r3, #0
8000b60: 617b str r3, [r7, #20]
8000b62: e012 b.n 8000b8a <BQ_Write_Register+0x72>
{
int shift_amount = 8 * (registersize - i - 1);
8000b64: 79ba ldrb r2, [r7, #6]
8000b66: 697b ldr r3, [r7, #20]
8000b68: 1ad3 subs r3, r2, r3
8000b6a: 3b01 subs r3, #1
8000b6c: 00db lsls r3, r3, #3
8000b6e: 60fb str r3, [r7, #12]
message[3+i] = (data>>shift_amount) & 0xFF;
8000b70: 683a ldr r2, [r7, #0]
8000b72: 68fb ldr r3, [r7, #12]
8000b74: 40da lsrs r2, r3
8000b76: 697b ldr r3, [r7, #20]
8000b78: 3303 adds r3, #3
8000b7a: 4619 mov r1, r3
8000b7c: 693b ldr r3, [r7, #16]
8000b7e: 440b add r3, r1
8000b80: b2d2 uxtb r2, r2
8000b82: 701a strb r2, [r3, #0]
for(int i = 0; i < registersize;i++)
8000b84: 697b ldr r3, [r7, #20]
8000b86: 3301 adds r3, #1
8000b88: 617b str r3, [r7, #20]
8000b8a: 79bb ldrb r3, [r7, #6]
8000b8c: 697a ldr r2, [r7, #20]
8000b8e: 429a cmp r2, r3
8000b90: dbe8 blt.n 8000b64 <BQ_Write_Register+0x4c>
}
Calculate_CRC(message, registersize+5);
8000b92: 79bb ldrb r3, [r7, #6]
8000b94: b29b uxth r3, r3
8000b96: 3305 adds r3, #5
8000b98: b29b uxth r3, r3
8000b9a: 4619 mov r1, r3
8000b9c: 6938 ldr r0, [r7, #16]
8000b9e: f7ff ff25 bl 80009ec <Calculate_CRC>
BQ_UART_Transmit(message, registersize+5);
8000ba2: 79bb ldrb r3, [r7, #6]
8000ba4: b29b uxth r3, r3
8000ba6: 3305 adds r3, #5
8000ba8: b29b uxth r3, r3
8000baa: 4619 mov r1, r3
8000bac: 6938 ldr r0, [r7, #16]
8000bae: f000 f8d9 bl 8000d64 <BQ_UART_Transmit>
free(message);
8000bb2: 6938 ldr r0, [r7, #16]
8000bb4: f004 f982 bl 8004ebc <free>
return 1;
8000bb8: 2301 movs r3, #1
}
8000bba: 4618 mov r0, r3
8000bbc: 3718 adds r7, #24
8000bbe: 46bd mov sp, r7
8000bc0: bd80 pop {r7, pc}
08000bc2 <BQ_Read_Register>:
*
* registersize defines the register size in bytes
*/
uint8_t BQ_Read_Register(uint8_t registeraddress, uint8_t registersize, uint32_t* data)
{
8000bc2: b580 push {r7, lr}
8000bc4: b086 sub sp, #24
8000bc6: af00 add r7, sp, #0
8000bc8: 4603 mov r3, r0
8000bca: 603a str r2, [r7, #0]
8000bcc: 71fb strb r3, [r7, #7]
8000bce: 460b mov r3, r1
8000bd0: 71bb strb r3, [r7, #6]
uint8_t message[6] = {0};
8000bd2: 2300 movs r3, #0
8000bd4: 60bb str r3, [r7, #8]
8000bd6: 2300 movs r3, #0
8000bd8: 81bb strh r3, [r7, #12]
message[0] = FRM_WRT_R;
8000bda: 2381 movs r3, #129 ; 0x81
8000bdc: 723b strb r3, [r7, #8]
message[1] = 0;
8000bde: 2300 movs r3, #0
8000be0: 727b strb r3, [r7, #9]
message[2] = registeraddress;
8000be2: 79fb ldrb r3, [r7, #7]
8000be4: 72bb strb r3, [r7, #10]
message[3] = registersize-1;
8000be6: 79bb ldrb r3, [r7, #6]
8000be8: 3b01 subs r3, #1
8000bea: b2db uxtb r3, r3
8000bec: 72fb strb r3, [r7, #11]
Calculate_CRC(message, 6);
8000bee: f107 0308 add.w r3, r7, #8
8000bf2: 2106 movs r1, #6
8000bf4: 4618 mov r0, r3
8000bf6: f7ff fef9 bl 80009ec <Calculate_CRC>
BQ_UART_Transmit(message, 6);
8000bfa: f107 0308 add.w r3, r7, #8
8000bfe: 2106 movs r1, #6
8000c00: 4618 mov r0, r3
8000c02: f000 f8af bl 8000d64 <BQ_UART_Transmit>
uint8_t* recv_message = (uint8_t*) calloc(registersize+3,sizeof(uint8_t));
8000c06: 79bb ldrb r3, [r7, #6]
8000c08: 3303 adds r3, #3
8000c0a: 2101 movs r1, #1
8000c0c: 4618 mov r0, r3
8000c0e: f004 f923 bl 8004e58 <calloc>
8000c12: 4603 mov r3, r0
8000c14: 613b str r3, [r7, #16]
BQ_UART_Receive(recv_message, registersize+3);
8000c16: 79bb ldrb r3, [r7, #6]
8000c18: b29b uxth r3, r3
8000c1a: 3303 adds r3, #3
8000c1c: b29b uxth r3, r3
8000c1e: 4619 mov r1, r3
8000c20: 6938 ldr r0, [r7, #16]
8000c22: f000 f8b5 bl 8000d90 <BQ_UART_Receive>
uint16_t crccheck = Check_CRC(recv_message, registersize+3);
8000c26: 79bb ldrb r3, [r7, #6]
8000c28: b29b uxth r3, r3
8000c2a: 3303 adds r3, #3
8000c2c: b29b uxth r3, r3
8000c2e: 4619 mov r1, r3
8000c30: 6938 ldr r0, [r7, #16]
8000c32: f7ff ff1f bl 8000a74 <Check_CRC>
8000c36: 4603 mov r3, r0
8000c38: 81fb strh r3, [r7, #14]
if(crccheck == 0)
8000c3a: 89fb ldrh r3, [r7, #14]
8000c3c: 2b00 cmp r3, #0
8000c3e: d104 bne.n 8000c4a <BQ_Read_Register+0x88>
{
free(recv_message);
8000c40: 6938 ldr r0, [r7, #16]
8000c42: f004 f93b bl 8004ebc <free>
return 0;
8000c46: 2300 movs r3, #0
8000c48: e025 b.n 8000c96 <BQ_Read_Register+0xd4>
}
data[0] = 0;
8000c4a: 683b ldr r3, [r7, #0]
8000c4c: 2200 movs r2, #0
8000c4e: 601a str r2, [r3, #0]
if(registersize > 4)
8000c50: 79bb ldrb r3, [r7, #6]
8000c52: 2b04 cmp r3, #4
8000c54: d901 bls.n 8000c5a <BQ_Read_Register+0x98>
registersize = 4;
8000c56: 2304 movs r3, #4
8000c58: 71bb strb r3, [r7, #6]
for(int n = 0; n < registersize; n++)
8000c5a: 2300 movs r3, #0
8000c5c: 617b str r3, [r7, #20]
8000c5e: e012 b.n 8000c86 <BQ_Read_Register+0xc4>
{
data[0] |= recv_message[1+n]>>(8*n);
8000c60: 683b ldr r3, [r7, #0]
8000c62: 681b ldr r3, [r3, #0]
8000c64: 697a ldr r2, [r7, #20]
8000c66: 3201 adds r2, #1
8000c68: 4611 mov r1, r2
8000c6a: 693a ldr r2, [r7, #16]
8000c6c: 440a add r2, r1
8000c6e: 7812 ldrb r2, [r2, #0]
8000c70: 4611 mov r1, r2
8000c72: 697a ldr r2, [r7, #20]
8000c74: 00d2 lsls r2, r2, #3
8000c76: fa41 f202 asr.w r2, r1, r2
8000c7a: 431a orrs r2, r3
8000c7c: 683b ldr r3, [r7, #0]
8000c7e: 601a str r2, [r3, #0]
for(int n = 0; n < registersize; n++)
8000c80: 697b ldr r3, [r7, #20]
8000c82: 3301 adds r3, #1
8000c84: 617b str r3, [r7, #20]
8000c86: 79bb ldrb r3, [r7, #6]
8000c88: 697a ldr r2, [r7, #20]
8000c8a: 429a cmp r2, r3
8000c8c: dbe8 blt.n 8000c60 <BQ_Read_Register+0x9e>
}
free(recv_message);
8000c8e: 6938 ldr r0, [r7, #16]
8000c90: f004 f914 bl 8004ebc <free>
return 1;
8000c94: 2301 movs r3, #1
}
8000c96: 4618 mov r0, r3
8000c98: 3718 adds r7, #24
8000c9a: 46bd mov sp, r7
8000c9c: bd80 pop {r7, pc}
...
08000ca0 <BQ_ReadMeasurements>:
* Result are Written into the Buffer
* Buffer size should be 2xMeasured Voltages
*
*/
uint32_t BQ_ReadMeasurements(uint8_t* buffer, uint8_t bufferlength)
{
8000ca0: b580 push {r7, lr}
8000ca2: b086 sub sp, #24
8000ca4: af00 add r7, sp, #0
8000ca6: 6078 str r0, [r7, #4]
8000ca8: 460b mov r3, r1
8000caa: 70fb strb r3, [r7, #3]
uint8_t message[6] = {};
8000cac: 2300 movs r3, #0
8000cae: 60bb str r3, [r7, #8]
8000cb0: 2300 movs r3, #0
8000cb2: 81bb strh r3, [r7, #12]
message[0] = FRM_WRT_R;
8000cb4: 2381 movs r3, #129 ; 0x81
8000cb6: 723b strb r3, [r7, #8]
message[1] = 0x00;
8000cb8: 2300 movs r3, #0
8000cba: 727b strb r3, [r7, #9]
message[2] = 0x02;
8000cbc: 2302 movs r3, #2
8000cbe: 72bb strb r3, [r7, #10]
message[3] = 0x00;
8000cc0: 2300 movs r3, #0
8000cc2: 72fb strb r3, [r7, #11]
Calculate_CRC(message, 6);
8000cc4: f107 0308 add.w r3, r7, #8
8000cc8: 2106 movs r1, #6
8000cca: 4618 mov r0, r3
8000ccc: f7ff fe8e bl 80009ec <Calculate_CRC>
BQ_UART_Transmit(message, 6);
8000cd0: f107 0308 add.w r3, r7, #8
8000cd4: 2106 movs r1, #6
8000cd6: 4618 mov r0, r3
8000cd8: f000 f844 bl 8000d64 <BQ_UART_Transmit>
uint16_t recv_len = 2*(numofcells+numofdietemps)+3;
8000cdc: 4b1f ldr r3, [pc, #124] ; (8000d5c <BQ_ReadMeasurements+0xbc>)
8000cde: 781b ldrb r3, [r3, #0]
8000ce0: 461a mov r2, r3
8000ce2: 4b1f ldr r3, [pc, #124] ; (8000d60 <BQ_ReadMeasurements+0xc0>)
8000ce4: 781b ldrb r3, [r3, #0]
8000ce6: 4413 add r3, r2
8000ce8: b29b uxth r3, r3
8000cea: 005b lsls r3, r3, #1
8000cec: b29b uxth r3, r3
8000cee: 3303 adds r3, #3
8000cf0: 82fb strh r3, [r7, #22]
uint8_t* recv_buf = (uint8_t*) calloc(recv_len,sizeof(uint8_t));
8000cf2: 8afb ldrh r3, [r7, #22]
8000cf4: 2101 movs r1, #1
8000cf6: 4618 mov r0, r3
8000cf8: f004 f8ae bl 8004e58 <calloc>
8000cfc: 4603 mov r3, r0
8000cfe: 613b str r3, [r7, #16]
uint8_t uartstat = BQ_UART_Receive(recv_buf, recv_len);
8000d00: 8afb ldrh r3, [r7, #22]
8000d02: 4619 mov r1, r3
8000d04: 6938 ldr r0, [r7, #16]
8000d06: f000 f843 bl 8000d90 <BQ_UART_Receive>
8000d0a: 4603 mov r3, r0
8000d0c: 73fb strb r3, [r7, #15]
if(Check_CRC(recv_buf, recv_len) == 0)
8000d0e: 8afb ldrh r3, [r7, #22]
8000d10: 4619 mov r1, r3
8000d12: 6938 ldr r0, [r7, #16]
8000d14: f7ff feae bl 8000a74 <Check_CRC>
8000d18: 4603 mov r3, r0
8000d1a: 2b00 cmp r3, #0
8000d1c: d104 bne.n 8000d28 <BQ_ReadMeasurements+0x88>
{
free(recv_buf);
8000d1e: 6938 ldr r0, [r7, #16]
8000d20: f004 f8cc bl 8004ebc <free>
return 0;
8000d24: 2300 movs r3, #0
8000d26: e014 b.n 8000d52 <BQ_ReadMeasurements+0xb2>
}
if(bufferlength <= 2*(numofcells+numofdietemps))
8000d28: 78fa ldrb r2, [r7, #3]
8000d2a: 4b0c ldr r3, [pc, #48] ; (8000d5c <BQ_ReadMeasurements+0xbc>)
8000d2c: 781b ldrb r3, [r3, #0]
8000d2e: 4619 mov r1, r3
8000d30: 4b0b ldr r3, [pc, #44] ; (8000d60 <BQ_ReadMeasurements+0xc0>)
8000d32: 781b ldrb r3, [r3, #0]
8000d34: 440b add r3, r1
8000d36: 005b lsls r3, r3, #1
8000d38: 429a cmp r2, r3
8000d3a: dc06 bgt.n 8000d4a <BQ_ReadMeasurements+0xaa>
{
memcpy(buffer,&recv_buf[1], bufferlength);
8000d3c: 693b ldr r3, [r7, #16]
8000d3e: 3301 adds r3, #1
8000d40: 78fa ldrb r2, [r7, #3]
8000d42: 4619 mov r1, r3
8000d44: 6878 ldr r0, [r7, #4]
8000d46: f004 f8cf bl 8004ee8 <memcpy>
}
free(recv_buf);
8000d4a: 6938 ldr r0, [r7, #16]
8000d4c: f004 f8b6 bl 8004ebc <free>
return 1;
8000d50: 2301 movs r3, #1
}
8000d52: 4618 mov r0, r3
8000d54: 3718 adds r7, #24
8000d56: 46bd mov sp, r7
8000d58: bd80 pop {r7, pc}
8000d5a: bf00 nop
8000d5c: 20000000 .word 0x20000000
8000d60: 200000e4 .word 0x200000e4
08000d64 <BQ_UART_Transmit>:
/* Hardware Layer Implementation of the UART Transmit
*
*/
uint8_t BQ_UART_Transmit(uint8_t* message_buffer, uint16_t bufferlength)
{
8000d64: b580 push {r7, lr}
8000d66: b084 sub sp, #16
8000d68: af00 add r7, sp, #0
8000d6a: 6078 str r0, [r7, #4]
8000d6c: 460b mov r3, r1
8000d6e: 807b strh r3, [r7, #2]
HAL_StatusTypeDef uartstate = HAL_UART_Transmit(bq_uart, message_buffer, bufferlength, BQUARTTIMEOUT);
8000d70: 4b06 ldr r3, [pc, #24] ; (8000d8c <BQ_UART_Transmit+0x28>)
8000d72: 6818 ldr r0, [r3, #0]
8000d74: 887a ldrh r2, [r7, #2]
8000d76: 23c8 movs r3, #200 ; 0xc8
8000d78: 6879 ldr r1, [r7, #4]
8000d7a: f003 f850 bl 8003e1e <HAL_UART_Transmit>
8000d7e: 4603 mov r3, r0
8000d80: 73fb strb r3, [r7, #15]
return (uint8_t) uartstate;
8000d82: 7bfb ldrb r3, [r7, #15]
}
8000d84: 4618 mov r0, r3
8000d86: 3710 adds r7, #16
8000d88: 46bd mov sp, r7
8000d8a: bd80 pop {r7, pc}
8000d8c: 2000018c .word 0x2000018c
08000d90 <BQ_UART_Receive>:
/* Hardware Layer Implementation of the UART Receive
*
*/
uint8_t BQ_UART_Receive(uint8_t* message_buffer, uint16_t bufferlength)
{
8000d90: b580 push {r7, lr}
8000d92: b084 sub sp, #16
8000d94: af00 add r7, sp, #0
8000d96: 6078 str r0, [r7, #4]
8000d98: 460b mov r3, r1
8000d9a: 807b strh r3, [r7, #2]
HAL_StatusTypeDef uartstate = HAL_UART_Receive(bq_uart, message_buffer, bufferlength, BQUARTTIMEOUT);
8000d9c: 4b06 ldr r3, [pc, #24] ; (8000db8 <BQ_UART_Receive+0x28>)
8000d9e: 6818 ldr r0, [r3, #0]
8000da0: 887a ldrh r2, [r7, #2]
8000da2: 23c8 movs r3, #200 ; 0xc8
8000da4: 6879 ldr r1, [r7, #4]
8000da6: f003 f8cc bl 8003f42 <HAL_UART_Receive>
8000daa: 4603 mov r3, r0
8000dac: 73fb strb r3, [r7, #15]
return (uint8_t) uartstate;
8000dae: 7bfb ldrb r3, [r7, #15]
}
8000db0: 4618 mov r0, r3
8000db2: 3710 adds r7, #16
8000db4: 46bd mov sp, r7
8000db6: bd80 pop {r7, pc}
8000db8: 2000018c .word 0x2000018c
08000dbc <tmp144_init>:
static volatile TMP144Bus bus_busbar;
static volatile TMP144Bus bus_other;
#define CHECK_STATUS(s) {HAL_StatusTypeDef _s = s; if (_s != HAL_OK) return _s;}
HAL_StatusTypeDef tmp144_init(UART_HandleTypeDef* busbar_side, UART_HandleTypeDef* other_side) {
8000dbc: b580 push {r7, lr}
8000dbe: b084 sub sp, #16
8000dc0: af00 add r7, sp, #0
8000dc2: 6078 str r0, [r7, #4]
8000dc4: 6039 str r1, [r7, #0]
bus_busbar.handle = busbar_side;
8000dc6: 4a45 ldr r2, [pc, #276] ; (8000edc <tmp144_init+0x120>)
8000dc8: 687b ldr r3, [r7, #4]
8000dca: 6013 str r3, [r2, #0]
bus_other.handle = other_side;
8000dcc: 4a44 ldr r2, [pc, #272] ; (8000ee0 <tmp144_init+0x124>)
8000dce: 683b ldr r3, [r7, #0]
8000dd0: 6013 str r3, [r2, #0]
bus_busbar.state = TMP144_IDLE;
8000dd2: 4b42 ldr r3, [pc, #264] ; (8000edc <tmp144_init+0x120>)
8000dd4: 2200 movs r2, #0
8000dd6: 711a strb r2, [r3, #4]
bus_other.state = TMP144_IDLE;
8000dd8: 4b41 ldr r3, [pc, #260] ; (8000ee0 <tmp144_init+0x124>)
8000dda: 2200 movs r2, #0
8000ddc: 711a strb r2, [r3, #4]
// TODO: Configure this in EEPROM
bus_busbar.n_sensors = 11;
8000dde: 4b3f ldr r3, [pc, #252] ; (8000edc <tmp144_init+0x120>)
8000de0: 220b movs r2, #11
8000de2: 629a str r2, [r3, #40] ; 0x28
bus_busbar.sensor_mappings[0] = 8;
8000de4: 4b3d ldr r3, [pc, #244] ; (8000edc <tmp144_init+0x120>)
8000de6: 2208 movs r2, #8
8000de8: f883 202c strb.w r2, [r3, #44] ; 0x2c
bus_busbar.sensor_mappings[1] = 8;
8000dec: 4b3b ldr r3, [pc, #236] ; (8000edc <tmp144_init+0x120>)
8000dee: 2208 movs r2, #8
8000df0: f883 202d strb.w r2, [r3, #45] ; 0x2d
bus_busbar.sensor_mappings[2] = 8;
8000df4: 4b39 ldr r3, [pc, #228] ; (8000edc <tmp144_init+0x120>)
8000df6: 2208 movs r2, #8
8000df8: f883 202e strb.w r2, [r3, #46] ; 0x2e
bus_busbar.sensor_mappings[3] = 6;
8000dfc: 4b37 ldr r3, [pc, #220] ; (8000edc <tmp144_init+0x120>)
8000dfe: 2206 movs r2, #6
8000e00: f883 202f strb.w r2, [r3, #47] ; 0x2f
bus_busbar.sensor_mappings[4] = 6;
8000e04: 4b35 ldr r3, [pc, #212] ; (8000edc <tmp144_init+0x120>)
8000e06: 2206 movs r2, #6
8000e08: f883 2030 strb.w r2, [r3, #48] ; 0x30
bus_busbar.sensor_mappings[5] = 4;
8000e0c: 4b33 ldr r3, [pc, #204] ; (8000edc <tmp144_init+0x120>)
8000e0e: 2204 movs r2, #4
8000e10: f883 2031 strb.w r2, [r3, #49] ; 0x31
bus_busbar.sensor_mappings[6] = 4;
8000e14: 4b31 ldr r3, [pc, #196] ; (8000edc <tmp144_init+0x120>)
8000e16: 2204 movs r2, #4
8000e18: f883 2032 strb.w r2, [r3, #50] ; 0x32
bus_busbar.sensor_mappings[7] = 4;
8000e1c: 4b2f ldr r3, [pc, #188] ; (8000edc <tmp144_init+0x120>)
8000e1e: 2204 movs r2, #4
8000e20: f883 2033 strb.w r2, [r3, #51] ; 0x33
bus_busbar.sensor_mappings[8] = 2;
8000e24: 4b2d ldr r3, [pc, #180] ; (8000edc <tmp144_init+0x120>)
8000e26: 2202 movs r2, #2
8000e28: f883 2034 strb.w r2, [r3, #52] ; 0x34
bus_busbar.sensor_mappings[9] = 2;
8000e2c: 4b2b ldr r3, [pc, #172] ; (8000edc <tmp144_init+0x120>)
8000e2e: 2202 movs r2, #2
8000e30: f883 2035 strb.w r2, [r3, #53] ; 0x35
bus_busbar.sensor_mappings[10] = 2;
8000e34: 4b29 ldr r3, [pc, #164] ; (8000edc <tmp144_init+0x120>)
8000e36: 2202 movs r2, #2
8000e38: f883 2036 strb.w r2, [r3, #54] ; 0x36
bus_other.n_sensors = 13;
8000e3c: 4b28 ldr r3, [pc, #160] ; (8000ee0 <tmp144_init+0x124>)
8000e3e: 220d movs r2, #13
8000e40: 629a str r2, [r3, #40] ; 0x28
bus_other.sensor_mappings[0] = 1;
8000e42: 4b27 ldr r3, [pc, #156] ; (8000ee0 <tmp144_init+0x124>)
8000e44: 2201 movs r2, #1
8000e46: f883 202c strb.w r2, [r3, #44] ; 0x2c
bus_other.sensor_mappings[1] = 1;
8000e4a: 4b25 ldr r3, [pc, #148] ; (8000ee0 <tmp144_init+0x124>)
8000e4c: 2201 movs r2, #1
8000e4e: f883 202d strb.w r2, [r3, #45] ; 0x2d
bus_other.sensor_mappings[2] = 1;
8000e52: 4b23 ldr r3, [pc, #140] ; (8000ee0 <tmp144_init+0x124>)
8000e54: 2201 movs r2, #1
8000e56: f883 202e strb.w r2, [r3, #46] ; 0x2e
bus_other.sensor_mappings[3] = 3;
8000e5a: 4b21 ldr r3, [pc, #132] ; (8000ee0 <tmp144_init+0x124>)
8000e5c: 2203 movs r2, #3
8000e5e: f883 202f strb.w r2, [r3, #47] ; 0x2f
bus_other.sensor_mappings[4] = 3;
8000e62: 4b1f ldr r3, [pc, #124] ; (8000ee0 <tmp144_init+0x124>)
8000e64: 2203 movs r2, #3
8000e66: f883 2030 strb.w r2, [r3, #48] ; 0x30
bus_other.sensor_mappings[5] = 5;
8000e6a: 4b1d ldr r3, [pc, #116] ; (8000ee0 <tmp144_init+0x124>)
8000e6c: 2205 movs r2, #5
8000e6e: f883 2031 strb.w r2, [r3, #49] ; 0x31
bus_other.sensor_mappings[6] = 5;
8000e72: 4b1b ldr r3, [pc, #108] ; (8000ee0 <tmp144_init+0x124>)
8000e74: 2205 movs r2, #5
8000e76: f883 2032 strb.w r2, [r3, #50] ; 0x32
bus_other.sensor_mappings[7] = 5;
8000e7a: 4b19 ldr r3, [pc, #100] ; (8000ee0 <tmp144_init+0x124>)
8000e7c: 2205 movs r2, #5
8000e7e: f883 2033 strb.w r2, [r3, #51] ; 0x33
bus_other.sensor_mappings[8] = 5;
8000e82: 4b17 ldr r3, [pc, #92] ; (8000ee0 <tmp144_init+0x124>)
8000e84: 2205 movs r2, #5
8000e86: f883 2034 strb.w r2, [r3, #52] ; 0x34
bus_other.sensor_mappings[9] = 7;
8000e8a: 4b15 ldr r3, [pc, #84] ; (8000ee0 <tmp144_init+0x124>)
8000e8c: 2207 movs r2, #7
8000e8e: f883 2035 strb.w r2, [r3, #53] ; 0x35
bus_other.sensor_mappings[10] = 7;
8000e92: 4b13 ldr r3, [pc, #76] ; (8000ee0 <tmp144_init+0x124>)
8000e94: 2207 movs r2, #7
8000e96: f883 2036 strb.w r2, [r3, #54] ; 0x36
bus_other.sensor_mappings[11] = 9;
8000e9a: 4b11 ldr r3, [pc, #68] ; (8000ee0 <tmp144_init+0x124>)
8000e9c: 2209 movs r2, #9
8000e9e: f883 2037 strb.w r2, [r3, #55] ; 0x37
bus_other.sensor_mappings[12] = 9;
8000ea2: 4b0f ldr r3, [pc, #60] ; (8000ee0 <tmp144_init+0x124>)
8000ea4: 2209 movs r2, #9
8000ea6: f883 2038 strb.w r2, [r3, #56] ; 0x38
CHECK_STATUS(tmp144_init_reset(&bus_busbar));
8000eaa: 480c ldr r0, [pc, #48] ; (8000edc <tmp144_init+0x120>)
8000eac: f000 f81a bl 8000ee4 <tmp144_init_reset>
8000eb0: 4603 mov r3, r0
8000eb2: 73fb strb r3, [r7, #15]
8000eb4: 7bfb ldrb r3, [r7, #15]
8000eb6: 2b00 cmp r3, #0
8000eb8: d001 beq.n 8000ebe <tmp144_init+0x102>
8000eba: 7bfb ldrb r3, [r7, #15]
8000ebc: e00a b.n 8000ed4 <tmp144_init+0x118>
CHECK_STATUS(tmp144_init_reset(&bus_other));
8000ebe: 4808 ldr r0, [pc, #32] ; (8000ee0 <tmp144_init+0x124>)
8000ec0: f000 f810 bl 8000ee4 <tmp144_init_reset>
8000ec4: 4603 mov r3, r0
8000ec6: 73bb strb r3, [r7, #14]
8000ec8: 7bbb ldrb r3, [r7, #14]
8000eca: 2b00 cmp r3, #0
8000ecc: d001 beq.n 8000ed2 <tmp144_init+0x116>
8000ece: 7bbb ldrb r3, [r7, #14]
8000ed0: e000 b.n 8000ed4 <tmp144_init+0x118>
return HAL_OK;
8000ed2: 2300 movs r3, #0
}
8000ed4: 4618 mov r0, r3
8000ed6: 3710 adds r7, #16
8000ed8: 46bd mov sp, r7
8000eda: bd80 pop {r7, pc}
8000edc: 200000e8 .word 0x200000e8
8000ee0: 20000124 .word 0x20000124
08000ee4 <tmp144_init_reset>:
HAL_StatusTypeDef tmp144_init_reset(TMP144Bus* bus) {
8000ee4: b580 push {r7, lr}
8000ee6: b084 sub sp, #16
8000ee8: af00 add r7, sp, #0
8000eea: 6078 str r0, [r7, #4]
if (bus->state != TMP144_IDLE) {
8000eec: 687b ldr r3, [r7, #4]
8000eee: 791b ldrb r3, [r3, #4]
8000ef0: 2b00 cmp r3, #0
8000ef2: d001 beq.n 8000ef8 <tmp144_init_reset+0x14>
return HAL_ERROR;
8000ef4: 2301 movs r3, #1
8000ef6: e051 b.n 8000f9c <tmp144_init_reset+0xb8>
}
bus->state = TMP144_RESETTING;
8000ef8: 687b ldr r3, [r7, #4]
8000efa: 2201 movs r2, #1
8000efc: 711a strb r2, [r3, #4]
CHECK_STATUS(HAL_UART_Receive_IT(bus->handle, bus->rxbuf, 2));
8000efe: 687b ldr r3, [r7, #4]
8000f00: 6818 ldr r0, [r3, #0]
8000f02: 687b ldr r3, [r7, #4]
8000f04: 3305 adds r3, #5
8000f06: 2202 movs r2, #2
8000f08: 4619 mov r1, r3
8000f0a: f003 f8bc bl 8004086 <HAL_UART_Receive_IT>
8000f0e: 4603 mov r3, r0
8000f10: 72fb strb r3, [r7, #11]
8000f12: 7afb ldrb r3, [r7, #11]
8000f14: 2b00 cmp r3, #0
8000f16: d001 beq.n 8000f1c <tmp144_init_reset+0x38>
8000f18: 7afb ldrb r3, [r7, #11]
8000f1a: e03f b.n 8000f9c <tmp144_init_reset+0xb8>
// Keep sending Global Software Reset until it echoes back (as per 7.5.2)
int tries = 0;
8000f1c: 2300 movs r3, #0
8000f1e: 60fb str r3, [r7, #12]
do {
if (tries > 10) {
8000f20: 68fb ldr r3, [r7, #12]
8000f22: 2b0a cmp r3, #10
8000f24: dd01 ble.n 8000f2a <tmp144_init_reset+0x46>
return HAL_TIMEOUT;
8000f26: 2303 movs r3, #3
8000f28: e038 b.n 8000f9c <tmp144_init_reset+0xb8>
}
CHECK_STATUS(HAL_UART_Transmit(bus->handle, TMP144_SEQ_RESET, sizeof(TMP144_SEQ_RESET), 100));
8000f2a: 687b ldr r3, [r7, #4]
8000f2c: 6818 ldr r0, [r3, #0]
8000f2e: 2364 movs r3, #100 ; 0x64
8000f30: 2202 movs r2, #2
8000f32: 491c ldr r1, [pc, #112] ; (8000fa4 <tmp144_init_reset+0xc0>)
8000f34: f002 ff73 bl 8003e1e <HAL_UART_Transmit>
8000f38: 4603 mov r3, r0
8000f3a: 72bb strb r3, [r7, #10]
8000f3c: 7abb ldrb r3, [r7, #10]
8000f3e: 2b00 cmp r3, #0
8000f40: d001 beq.n 8000f46 <tmp144_init_reset+0x62>
8000f42: 7abb ldrb r3, [r7, #10]
8000f44: e02a b.n 8000f9c <tmp144_init_reset+0xb8>
HAL_Delay(100);
8000f46: 2064 movs r0, #100 ; 0x64
8000f48: f000 ff9a bl 8001e80 <HAL_Delay>
tries++;
8000f4c: 68fb ldr r3, [r7, #12]
8000f4e: 3301 adds r3, #1
8000f50: 60fb str r3, [r7, #12]
} while (bus->state == TMP144_RESETTING);
8000f52: 687b ldr r3, [r7, #4]
8000f54: 791b ldrb r3, [r3, #4]
8000f56: 2b01 cmp r3, #1
8000f58: d0e2 beq.n 8000f20 <tmp144_init_reset+0x3c>
bus->state = TMP144_INITIALIZING;
8000f5a: 687b ldr r3, [r7, #4]
8000f5c: 2202 movs r2, #2
8000f5e: 711a strb r2, [r3, #4]
CHECK_STATUS(HAL_UART_Receive_IT(bus->handle, bus->rxbuf, 3));
8000f60: 687b ldr r3, [r7, #4]
8000f62: 6818 ldr r0, [r3, #0]
8000f64: 687b ldr r3, [r7, #4]
8000f66: 3305 adds r3, #5
8000f68: 2203 movs r2, #3
8000f6a: 4619 mov r1, r3
8000f6c: f003 f88b bl 8004086 <HAL_UART_Receive_IT>
8000f70: 4603 mov r3, r0
8000f72: 727b strb r3, [r7, #9]
8000f74: 7a7b ldrb r3, [r7, #9]
8000f76: 2b00 cmp r3, #0
8000f78: d001 beq.n 8000f7e <tmp144_init_reset+0x9a>
8000f7a: 7a7b ldrb r3, [r7, #9]
8000f7c: e00e b.n 8000f9c <tmp144_init_reset+0xb8>
CHECK_STATUS(HAL_UART_Transmit(bus->handle, TMP144_SEQ_ADDR, sizeof(TMP144_SEQ_ADDR), 100));
8000f7e: 687b ldr r3, [r7, #4]
8000f80: 6818 ldr r0, [r3, #0]
8000f82: 2364 movs r3, #100 ; 0x64
8000f84: 2203 movs r2, #3
8000f86: 4908 ldr r1, [pc, #32] ; (8000fa8 <tmp144_init_reset+0xc4>)
8000f88: f002 ff49 bl 8003e1e <HAL_UART_Transmit>
8000f8c: 4603 mov r3, r0
8000f8e: 723b strb r3, [r7, #8]
8000f90: 7a3b ldrb r3, [r7, #8]
8000f92: 2b00 cmp r3, #0
8000f94: d001 beq.n 8000f9a <tmp144_init_reset+0xb6>
8000f96: 7a3b ldrb r3, [r7, #8]
8000f98: e000 b.n 8000f9c <tmp144_init_reset+0xb8>
return HAL_OK;
8000f9a: 2300 movs r3, #0
}
8000f9c: 4618 mov r0, r3
8000f9e: 3710 adds r7, #16
8000fa0: 46bd mov sp, r7
8000fa2: bd80 pop {r7, pc}
8000fa4: 080052dc .word 0x080052dc
8000fa8: 080052e0 .word 0x080052e0
08000fac <tmp144_init_post_reset>:
HAL_StatusTypeDef tmp144_init_post_reset(TMP144Bus* bus) {
8000fac: b580 push {r7, lr}
8000fae: b082 sub sp, #8
8000fb0: af00 add r7, sp, #0
8000fb2: 6078 str r0, [r7, #4]
if (bus->state != TMP144_RESETTING || memcmp(bus->rxbuf, TMP144_SEQ_RESET, sizeof(TMP144_SEQ_RESET)) != 0) {
8000fb4: 687b ldr r3, [r7, #4]
8000fb6: 791b ldrb r3, [r3, #4]
8000fb8: 2b01 cmp r3, #1
8000fba: d109 bne.n 8000fd0 <tmp144_init_post_reset+0x24>
8000fbc: 687b ldr r3, [r7, #4]
8000fbe: 3305 adds r3, #5
8000fc0: 2202 movs r2, #2
8000fc2: 4908 ldr r1, [pc, #32] ; (8000fe4 <tmp144_init_post_reset+0x38>)
8000fc4: 4618 mov r0, r3
8000fc6: f003 ff81 bl 8004ecc <memcmp>
8000fca: 4603 mov r3, r0
8000fcc: 2b00 cmp r3, #0
8000fce: d001 beq.n 8000fd4 <tmp144_init_post_reset+0x28>
return HAL_ERROR;
8000fd0: 2301 movs r3, #1
8000fd2: e003 b.n 8000fdc <tmp144_init_post_reset+0x30>
}
bus->state = TMP144_IDLE;
8000fd4: 687b ldr r3, [r7, #4]
8000fd6: 2200 movs r2, #0
8000fd8: 711a strb r2, [r3, #4]
return HAL_OK;
8000fda: 2300 movs r3, #0
}
8000fdc: 4618 mov r0, r3
8000fde: 3708 adds r7, #8
8000fe0: 46bd mov sp, r7
8000fe2: bd80 pop {r7, pc}
8000fe4: 080052dc .word 0x080052dc
08000fe8 <tmp144_init_post_addr>:
HAL_StatusTypeDef tmp144_init_post_addr(TMP144Bus* bus) {
8000fe8: b580 push {r7, lr}
8000fea: b084 sub sp, #16
8000fec: af00 add r7, sp, #0
8000fee: 6078 str r0, [r7, #4]
size_t idx_response = sizeof(TMP144_SEQ_ADDR) - 1;
8000ff0: 2302 movs r3, #2
8000ff2: 60fb str r3, [r7, #12]
if (bus->state != TMP144_INITIALIZING || memcmp(bus->rxbuf, TMP144_SEQ_ADDR, idx_response) != 0) {
8000ff4: 687b ldr r3, [r7, #4]
8000ff6: 791b ldrb r3, [r3, #4]
8000ff8: 2b02 cmp r3, #2
8000ffa: d109 bne.n 8001010 <tmp144_init_post_addr+0x28>
8000ffc: 687b ldr r3, [r7, #4]
8000ffe: 3305 adds r3, #5
8001000: 68fa ldr r2, [r7, #12]
8001002: 4911 ldr r1, [pc, #68] ; (8001048 <tmp144_init_post_addr+0x60>)
8001004: 4618 mov r0, r3
8001006: f003 ff61 bl 8004ecc <memcmp>
800100a: 4603 mov r3, r0
800100c: 2b00 cmp r3, #0
800100e: d001 beq.n 8001014 <tmp144_init_post_addr+0x2c>
return HAL_ERROR;
8001010: 2301 movs r3, #1
8001012: e015 b.n 8001040 <tmp144_init_post_addr+0x58>
}
uint8_t n_sensors = bus->rxbuf[idx_response] - TMP144_SEQ_ADDR[idx_response];
8001014: 687a ldr r2, [r7, #4]
8001016: 68fb ldr r3, [r7, #12]
8001018: 4413 add r3, r2
800101a: 3305 adds r3, #5
800101c: 781a ldrb r2, [r3, #0]
800101e: 490a ldr r1, [pc, #40] ; (8001048 <tmp144_init_post_addr+0x60>)
8001020: 68fb ldr r3, [r7, #12]
8001022: 440b add r3, r1
8001024: 781b ldrb r3, [r3, #0]
8001026: 1ad3 subs r3, r2, r3
8001028: 72fb strb r3, [r7, #11]
if (n_sensors != bus->n_sensors) {
800102a: 7afa ldrb r2, [r7, #11]
800102c: 687b ldr r3, [r7, #4]
800102e: 6a9b ldr r3, [r3, #40] ; 0x28
8001030: 429a cmp r2, r3
8001032: d001 beq.n 8001038 <tmp144_init_post_addr+0x50>
return HAL_ERROR;
8001034: 2301 movs r3, #1
8001036: e003 b.n 8001040 <tmp144_init_post_addr+0x58>
}
bus->state = TMP144_IDLE;
8001038: 687b ldr r3, [r7, #4]
800103a: 2200 movs r2, #0
800103c: 711a strb r2, [r3, #4]
return HAL_OK;
800103e: 2300 movs r3, #0
}
8001040: 4618 mov r0, r3
8001042: 3710 adds r7, #16
8001044: 46bd mov sp, r7
8001046: bd80 pop {r7, pc}
8001048: 080052e0 .word 0x080052e0
0800104c <tmp144_read_temps>:
HAL_StatusTypeDef tmp144_read_temps() {
800104c: b580 push {r7, lr}
800104e: b082 sub sp, #8
8001050: af00 add r7, sp, #0
CHECK_STATUS(tmp144_send_read_temps(&bus_busbar));
8001052: 480c ldr r0, [pc, #48] ; (8001084 <tmp144_read_temps+0x38>)
8001054: f000 f81a bl 800108c <tmp144_send_read_temps>
8001058: 4603 mov r3, r0
800105a: 71fb strb r3, [r7, #7]
800105c: 79fb ldrb r3, [r7, #7]
800105e: 2b00 cmp r3, #0
8001060: d001 beq.n 8001066 <tmp144_read_temps+0x1a>
8001062: 79fb ldrb r3, [r7, #7]
8001064: e00a b.n 800107c <tmp144_read_temps+0x30>
CHECK_STATUS(tmp144_send_read_temps(&bus_other));
8001066: 4808 ldr r0, [pc, #32] ; (8001088 <tmp144_read_temps+0x3c>)
8001068: f000 f810 bl 800108c <tmp144_send_read_temps>
800106c: 4603 mov r3, r0
800106e: 71bb strb r3, [r7, #6]
8001070: 79bb ldrb r3, [r7, #6]
8001072: 2b00 cmp r3, #0
8001074: d001 beq.n 800107a <tmp144_read_temps+0x2e>
8001076: 79bb ldrb r3, [r7, #6]
8001078: e000 b.n 800107c <tmp144_read_temps+0x30>
return HAL_OK;
800107a: 2300 movs r3, #0
}
800107c: 4618 mov r0, r3
800107e: 3708 adds r7, #8
8001080: 46bd mov sp, r7
8001082: bd80 pop {r7, pc}
8001084: 200000e8 .word 0x200000e8
8001088: 20000124 .word 0x20000124
0800108c <tmp144_send_read_temps>:
HAL_StatusTypeDef tmp144_send_read_temps(TMP144Bus* bus) {
800108c: b580 push {r7, lr}
800108e: b084 sub sp, #16
8001090: af00 add r7, sp, #0
8001092: 6078 str r0, [r7, #4]
if (bus->state != TMP144_IDLE) {
8001094: 687b ldr r3, [r7, #4]
8001096: 791b ldrb r3, [r3, #4]
8001098: 2b00 cmp r3, #0
800109a: d001 beq.n 80010a0 <tmp144_send_read_temps+0x14>
return HAL_ERROR;
800109c: 2301 movs r3, #1
800109e: e025 b.n 80010ec <tmp144_send_read_temps+0x60>
}
bus->state = TMP144_READING_TEMP;
80010a0: 687b ldr r3, [r7, #4]
80010a2: 2203 movs r2, #3
80010a4: 711a strb r2, [r3, #4]
// HAL_UART_Receive_IT(bus->handle, bus->rxbuf, sizeof(TMP144_SEQ_READ_TEMPS) + 2 * bus->n_sensors);
CHECK_STATUS(HAL_UART_Receive_IT(bus->handle, bus->rxbuf, sizeof(TMP144_SEQ_READ_TEMPS) + 2 * bus->n_sensors));
80010a6: 687b ldr r3, [r7, #4]
80010a8: 6818 ldr r0, [r3, #0]
80010aa: 687b ldr r3, [r7, #4]
80010ac: 1d59 adds r1, r3, #5
80010ae: 687b ldr r3, [r7, #4]
80010b0: 6a9b ldr r3, [r3, #40] ; 0x28
80010b2: 3301 adds r3, #1
80010b4: b29b uxth r3, r3
80010b6: 005b lsls r3, r3, #1
80010b8: b29b uxth r3, r3
80010ba: 461a mov r2, r3
80010bc: f002 ffe3 bl 8004086 <HAL_UART_Receive_IT>
80010c0: 4603 mov r3, r0
80010c2: 73fb strb r3, [r7, #15]
80010c4: 7bfb ldrb r3, [r7, #15]
80010c6: 2b00 cmp r3, #0
80010c8: d001 beq.n 80010ce <tmp144_send_read_temps+0x42>
80010ca: 7bfb ldrb r3, [r7, #15]
80010cc: e00e b.n 80010ec <tmp144_send_read_temps+0x60>
CHECK_STATUS(HAL_UART_Transmit(bus->handle, TMP144_SEQ_READ_TEMPS, sizeof(TMP144_SEQ_READ_TEMPS), 100));
80010ce: 687b ldr r3, [r7, #4]
80010d0: 6818 ldr r0, [r3, #0]
80010d2: 2364 movs r3, #100 ; 0x64
80010d4: 2202 movs r2, #2
80010d6: 4907 ldr r1, [pc, #28] ; (80010f4 <tmp144_send_read_temps+0x68>)
80010d8: f002 fea1 bl 8003e1e <HAL_UART_Transmit>
80010dc: 4603 mov r3, r0
80010de: 73bb strb r3, [r7, #14]
80010e0: 7bbb ldrb r3, [r7, #14]
80010e2: 2b00 cmp r3, #0
80010e4: d001 beq.n 80010ea <tmp144_send_read_temps+0x5e>
80010e6: 7bbb ldrb r3, [r7, #14]
80010e8: e000 b.n 80010ec <tmp144_send_read_temps+0x60>
return HAL_OK;
80010ea: 2300 movs r3, #0
}
80010ec: 4618 mov r0, r3
80010ee: 3710 adds r7, #16
80010f0: 46bd mov sp, r7
80010f2: bd80 pop {r7, pc}
80010f4: 080052e4 .word 0x080052e4
080010f8 <tmp144_recv_temps>:
HAL_StatusTypeDef tmp144_recv_temps(TMP144Bus* bus) {
80010f8: b580 push {r7, lr}
80010fa: b088 sub sp, #32
80010fc: af00 add r7, sp, #0
80010fe: 6078 str r0, [r7, #4]
if (bus->state != TMP144_READING_TEMP) {
8001100: 687b ldr r3, [r7, #4]
8001102: 791b ldrb r3, [r3, #4]
8001104: 2b03 cmp r3, #3
8001106: d001 beq.n 800110c <tmp144_recv_temps+0x14>
return HAL_ERROR;
8001108: 2301 movs r3, #1
800110a: e057 b.n 80011bc <tmp144_recv_temps+0xc4>
}
bus->state = TMP144_IDLE;
800110c: 687b ldr r3, [r7, #4]
800110e: 2200 movs r2, #0
8001110: 711a strb r2, [r3, #4]
size_t headerlen = sizeof(TMP144_SEQ_READ_TEMPS);
8001112: 2302 movs r3, #2
8001114: 617b str r3, [r7, #20]
if (memcmp(bus->rxbuf, TMP144_SEQ_READ_TEMPS, headerlen) != 0) {
8001116: 687b ldr r3, [r7, #4]
8001118: 3305 adds r3, #5
800111a: 697a ldr r2, [r7, #20]
800111c: 4929 ldr r1, [pc, #164] ; (80011c4 <tmp144_recv_temps+0xcc>)
800111e: 4618 mov r0, r3
8001120: f003 fed4 bl 8004ecc <memcmp>
8001124: 4603 mov r3, r0
8001126: 2b00 cmp r3, #0
8001128: d001 beq.n 800112e <tmp144_recv_temps+0x36>
return HAL_ERROR;
800112a: 2301 movs r3, #1
800112c: e046 b.n 80011bc <tmp144_recv_temps+0xc4>
}
// Find max temperature for each cell
uint8_t current_cell = bus->sensor_mappings[0];
800112e: 687b ldr r3, [r7, #4]
8001130: f893 302c ldrb.w r3, [r3, #44] ; 0x2c
8001134: 77fb strb r3, [r7, #31]
uint16_t max_temp = 0;
8001136: 2300 movs r3, #0
8001138: 83bb strh r3, [r7, #28]
for (size_t i = 0; i < bus->n_sensors; i++) {
800113a: 2300 movs r3, #0
800113c: 61bb str r3, [r7, #24]
800113e: e032 b.n 80011a6 <tmp144_recv_temps+0xae>
uint8_t cell = bus->sensor_mappings[i];
8001140: 687a ldr r2, [r7, #4]
8001142: 69bb ldr r3, [r7, #24]
8001144: 4413 add r3, r2
8001146: 332c adds r3, #44 ; 0x2c
8001148: 781b ldrb r3, [r3, #0]
800114a: 74fb strb r3, [r7, #19]
if (cell != current_cell) {
800114c: 7cfa ldrb r2, [r7, #19]
800114e: 7ffb ldrb r3, [r7, #31]
8001150: 429a cmp r2, r3
8001152: d008 beq.n 8001166 <tmp144_recv_temps+0x6e>
temperatures[current_cell] = max_temp;
8001154: 7ffb ldrb r3, [r7, #31]
8001156: 491c ldr r1, [pc, #112] ; (80011c8 <tmp144_recv_temps+0xd0>)
8001158: 8bba ldrh r2, [r7, #28]
800115a: f821 2013 strh.w r2, [r1, r3, lsl #1]
current_cell = cell;
800115e: 7cfb ldrb r3, [r7, #19]
8001160: 77fb strb r3, [r7, #31]
max_temp = 0;
8001162: 2300 movs r3, #0
8001164: 83bb strh r3, [r7, #28]
}
size_t buf_offset = headerlen + 2 * i;
8001166: 69bb ldr r3, [r7, #24]
8001168: 005b lsls r3, r3, #1
800116a: 697a ldr r2, [r7, #20]
800116c: 4413 add r3, r2
800116e: 60fb str r3, [r7, #12]
uint16_t temp = (bus->rxbuf[buf_offset] >> 4) | (bus->rxbuf[buf_offset + 1] << 4);
8001170: 687a ldr r2, [r7, #4]
8001172: 68fb ldr r3, [r7, #12]
8001174: 4413 add r3, r2
8001176: 3305 adds r3, #5
8001178: 781b ldrb r3, [r3, #0]
800117a: 091b lsrs r3, r3, #4
800117c: b2db uxtb r3, r3
800117e: b21a sxth r2, r3
8001180: 68fb ldr r3, [r7, #12]
8001182: 3301 adds r3, #1
8001184: 6879 ldr r1, [r7, #4]
8001186: 440b add r3, r1
8001188: 795b ldrb r3, [r3, #5]
800118a: 011b lsls r3, r3, #4
800118c: b21b sxth r3, r3
800118e: 4313 orrs r3, r2
8001190: b21b sxth r3, r3
8001192: 817b strh r3, [r7, #10]
if (temp > max_temp) {
8001194: 897a ldrh r2, [r7, #10]
8001196: 8bbb ldrh r3, [r7, #28]
8001198: 429a cmp r2, r3
800119a: d901 bls.n 80011a0 <tmp144_recv_temps+0xa8>
max_temp = temp;
800119c: 897b ldrh r3, [r7, #10]
800119e: 83bb strh r3, [r7, #28]
for (size_t i = 0; i < bus->n_sensors; i++) {
80011a0: 69bb ldr r3, [r7, #24]
80011a2: 3301 adds r3, #1
80011a4: 61bb str r3, [r7, #24]
80011a6: 687b ldr r3, [r7, #4]
80011a8: 6a9b ldr r3, [r3, #40] ; 0x28
80011aa: 69ba ldr r2, [r7, #24]
80011ac: 429a cmp r2, r3
80011ae: d3c7 bcc.n 8001140 <tmp144_recv_temps+0x48>
}
}
temperatures[current_cell] = max_temp;
80011b0: 7ffb ldrb r3, [r7, #31]
80011b2: 4905 ldr r1, [pc, #20] ; (80011c8 <tmp144_recv_temps+0xd0>)
80011b4: 8bba ldrh r2, [r7, #28]
80011b6: f821 2013 strh.w r2, [r1, r3, lsl #1]
return HAL_OK;
80011ba: 2300 movs r3, #0
}
80011bc: 4618 mov r0, r3
80011be: 3720 adds r7, #32
80011c0: 46bd mov sp, r7
80011c2: bd80 pop {r7, pc}
80011c4: 080052e4 .word 0x080052e4
80011c8: 20000194 .word 0x20000194
080011cc <HAL_UART_RxCpltCallback>:
void HAL_UART_RxCpltCallback(UART_HandleTypeDef* handle) {
80011cc: b580 push {r7, lr}
80011ce: b084 sub sp, #16
80011d0: af00 add r7, sp, #0
80011d2: 6078 str r0, [r7, #4]
TMP144Bus* bus;
if (handle == bus_busbar.handle) {
80011d4: 4b1b ldr r3, [pc, #108] ; (8001244 <HAL_UART_RxCpltCallback+0x78>)
80011d6: 681b ldr r3, [r3, #0]
80011d8: 687a ldr r2, [r7, #4]
80011da: 429a cmp r2, r3
80011dc: d102 bne.n 80011e4 <HAL_UART_RxCpltCallback+0x18>
bus = &bus_busbar;
80011de: 4b19 ldr r3, [pc, #100] ; (8001244 <HAL_UART_RxCpltCallback+0x78>)
80011e0: 60fb str r3, [r7, #12]
80011e2: e009 b.n 80011f8 <HAL_UART_RxCpltCallback+0x2c>
} else if (handle == bus_other.handle) {
80011e4: 4b18 ldr r3, [pc, #96] ; (8001248 <HAL_UART_RxCpltCallback+0x7c>)
80011e6: 681b ldr r3, [r3, #0]
80011e8: 687a ldr r2, [r7, #4]
80011ea: 429a cmp r2, r3
80011ec: d102 bne.n 80011f4 <HAL_UART_RxCpltCallback+0x28>
bus = &bus_other;
80011ee: 4b16 ldr r3, [pc, #88] ; (8001248 <HAL_UART_RxCpltCallback+0x7c>)
80011f0: 60fb str r3, [r7, #12]
80011f2: e001 b.n 80011f8 <HAL_UART_RxCpltCallback+0x2c>
} else {
// TODO
Error_Handler();
80011f4: f000 fa94 bl 8001720 <Error_Handler>
}
switch (bus->state) {
80011f8: 68fb ldr r3, [r7, #12]
80011fa: 791b ldrb r3, [r3, #4]
80011fc: 2b03 cmp r3, #3
80011fe: d819 bhi.n 8001234 <HAL_UART_RxCpltCallback+0x68>
8001200: a201 add r2, pc, #4 ; (adr r2, 8001208 <HAL_UART_RxCpltCallback+0x3c>)
8001202: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8001206: bf00 nop
8001208: 08001219 .word 0x08001219
800120c: 0800121d .word 0x0800121d
8001210: 08001225 .word 0x08001225
8001214: 0800122d .word 0x0800122d
case TMP144_IDLE:
// TODO
Error_Handler();
8001218: f000 fa82 bl 8001720 <Error_Handler>
case TMP144_RESETTING:
tmp144_init_post_reset(bus);
800121c: 68f8 ldr r0, [r7, #12]
800121e: f7ff fec5 bl 8000fac <tmp144_init_post_reset>
break;
8001222: e00a b.n 800123a <HAL_UART_RxCpltCallback+0x6e>
case TMP144_INITIALIZING:
tmp144_init_post_addr(bus);
8001224: 68f8 ldr r0, [r7, #12]
8001226: f7ff fedf bl 8000fe8 <tmp144_init_post_addr>
break;
800122a: e006 b.n 800123a <HAL_UART_RxCpltCallback+0x6e>
case TMP144_READING_TEMP:
tmp144_recv_temps(bus);
800122c: 68f8 ldr r0, [r7, #12]
800122e: f7ff ff63 bl 80010f8 <tmp144_recv_temps>
break;
8001232: e002 b.n 800123a <HAL_UART_RxCpltCallback+0x6e>
default:
// TODO
Error_Handler();
8001234: f000 fa74 bl 8001720 <Error_Handler>
}
}
8001238: bf00 nop
800123a: bf00 nop
800123c: 3710 adds r7, #16
800123e: 46bd mov sp, r7
8001240: bd80 pop {r7, pc}
8001242: bf00 nop
8001244: 200000e8 .word 0x200000e8
8001248: 20000124 .word 0x20000124
0800124c <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
800124c: b580 push {r7, lr}
800124e: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
8001250: f000 fda4 bl 8001d9c <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
8001254: f000 f840 bl 80012d8 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
8001258: f000 f9de bl 8001618 <MX_GPIO_Init>
MX_CAN1_Init();
800125c: f000 f89a bl 8001394 <MX_CAN1_Init>
MX_CAN2_Init();
8001260: f000 f8ce bl 8001400 <MX_CAN2_Init>
MX_I2C1_Init();
8001264: f000 f902 bl 800146c <MX_I2C1_Init>
MX_USART1_UART_Init();
8001268: f000 f92e bl 80014c8 <MX_USART1_UART_Init>
MX_USART2_UART_Init();
800126c: f000 f956 bl 800151c <MX_USART2_UART_Init>
MX_USART3_UART_Init();
8001270: f000 f97e bl 8001570 <MX_USART3_UART_Init>
MX_USART6_UART_Init();
8001274: f000 f9a6 bl 80015c4 <MX_USART6_UART_Init>
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
HAL_GPIO_WritePin(BQ_POWER_ACTIVATE_GPIO_Port, BQ_POWER_ACTIVATE_Pin, GPIO_PIN_SET);
8001278: 2201 movs r2, #1
800127a: 2101 movs r1, #1
800127c: 4810 ldr r0, [pc, #64] ; (80012c0 <main+0x74>)
800127e: f001 ffa5 bl 80031cc <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(BQ_VIO_ACTICATE_GPIO_Port, BQ_VIO_ACTICATE_Pin, GPIO_PIN_SET);
8001282: 2201 movs r2, #1
8001284: 2102 movs r1, #2
8001286: 480e ldr r0, [pc, #56] ; (80012c0 <main+0x74>)
8001288: f001 ffa0 bl 80031cc <HAL_GPIO_WritePin>
afe_init(&huart2);
800128c: 480d ldr r0, [pc, #52] ; (80012c4 <main+0x78>)
800128e: f7ff fa6b bl 8000768 <afe_init>
ams_can_init(&hcan1, &hcan2);
8001292: 490d ldr r1, [pc, #52] ; (80012c8 <main+0x7c>)
8001294: 480d ldr r0, [pc, #52] ; (80012cc <main+0x80>)
8001296: f7ff f931 bl 80004fc <ams_can_init>
if (tmp144_init(&huart3, &huart1) != HAL_OK) {
800129a: 490d ldr r1, [pc, #52] ; (80012d0 <main+0x84>)
800129c: 480d ldr r0, [pc, #52] ; (80012d4 <main+0x88>)
800129e: f7ff fd8d bl 8000dbc <tmp144_init>
80012a2: 4603 mov r3, r0
80012a4: 2b00 cmp r3, #0
80012a6: d001 beq.n 80012ac <main+0x60>
Error_Handler();
80012a8: f000 fa3a bl 8001720 <Error_Handler>
while (1)
{
/* USER CODE END WHILE */
/* USER CODE BEGIN 3 */
afe_measure();
80012ac: f7ff fab0 bl 8000810 <afe_measure>
if (tmp144_read_temps() != HAL_OK) {
80012b0: f7ff fecc bl 800104c <tmp144_read_temps>
// Error_Handler();
}
ams_can_send_heartbeat();
80012b4: f7ff f9d0 bl 8000658 <ams_can_send_heartbeat>
HAL_Delay(100);
80012b8: 2064 movs r0, #100 ; 0x64
80012ba: f000 fde1 bl 8001e80 <HAL_Delay>
afe_measure();
80012be: e7f5 b.n 80012ac <main+0x60>
80012c0: 40020400 .word 0x40020400
80012c4: 200002f0 .word 0x200002f0
80012c8: 20000240 .word 0x20000240
80012cc: 20000334 .word 0x20000334
80012d0: 20000268 .word 0x20000268
80012d4: 200001a8 .word 0x200001a8
080012d8 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
80012d8: b580 push {r7, lr}
80012da: b094 sub sp, #80 ; 0x50
80012dc: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
80012de: f107 031c add.w r3, r7, #28
80012e2: 2234 movs r2, #52 ; 0x34
80012e4: 2100 movs r1, #0
80012e6: 4618 mov r0, r3
80012e8: f003 fe0c bl 8004f04 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
80012ec: f107 0308 add.w r3, r7, #8
80012f0: 2200 movs r2, #0
80012f2: 601a str r2, [r3, #0]
80012f4: 605a str r2, [r3, #4]
80012f6: 609a str r2, [r3, #8]
80012f8: 60da str r2, [r3, #12]
80012fa: 611a str r2, [r3, #16]
/** Configure the main internal regulator output voltage
*/
__HAL_RCC_PWR_CLK_ENABLE();
80012fc: 2300 movs r3, #0
80012fe: 607b str r3, [r7, #4]
8001300: 4b22 ldr r3, [pc, #136] ; (800138c <SystemClock_Config+0xb4>)
8001302: 6c1b ldr r3, [r3, #64] ; 0x40
8001304: 4a21 ldr r2, [pc, #132] ; (800138c <SystemClock_Config+0xb4>)
8001306: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
800130a: 6413 str r3, [r2, #64] ; 0x40
800130c: 4b1f ldr r3, [pc, #124] ; (800138c <SystemClock_Config+0xb4>)
800130e: 6c1b ldr r3, [r3, #64] ; 0x40
8001310: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8001314: 607b str r3, [r7, #4]
8001316: 687b ldr r3, [r7, #4]
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
8001318: 2300 movs r3, #0
800131a: 603b str r3, [r7, #0]
800131c: 4b1c ldr r3, [pc, #112] ; (8001390 <SystemClock_Config+0xb8>)
800131e: 681b ldr r3, [r3, #0]
8001320: 4a1b ldr r2, [pc, #108] ; (8001390 <SystemClock_Config+0xb8>)
8001322: f443 4340 orr.w r3, r3, #49152 ; 0xc000
8001326: 6013 str r3, [r2, #0]
8001328: 4b19 ldr r3, [pc, #100] ; (8001390 <SystemClock_Config+0xb8>)
800132a: 681b ldr r3, [r3, #0]
800132c: f403 4340 and.w r3, r3, #49152 ; 0xc000
8001330: 603b str r3, [r7, #0]
8001332: 683b ldr r3, [r7, #0]
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
8001334: 2302 movs r3, #2
8001336: 61fb str r3, [r7, #28]
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
8001338: 2301 movs r3, #1
800133a: 62bb str r3, [r7, #40] ; 0x28
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
800133c: 2310 movs r3, #16
800133e: 62fb str r3, [r7, #44] ; 0x2c
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
8001340: 2300 movs r3, #0
8001342: 637b str r3, [r7, #52] ; 0x34
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
8001344: f107 031c add.w r3, r7, #28
8001348: 4618 mov r0, r3
800134a: f002 fa97 bl 800387c <HAL_RCC_OscConfig>
800134e: 4603 mov r3, r0
8001350: 2b00 cmp r3, #0
8001352: d001 beq.n 8001358 <SystemClock_Config+0x80>
{
Error_Handler();
8001354: f000 f9e4 bl 8001720 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
8001358: 230f movs r3, #15
800135a: 60bb str r3, [r7, #8]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
800135c: 2300 movs r3, #0
800135e: 60fb str r3, [r7, #12]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
8001360: 2300 movs r3, #0
8001362: 613b str r3, [r7, #16]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
8001364: 2300 movs r3, #0
8001366: 617b str r3, [r7, #20]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
8001368: 2300 movs r3, #0
800136a: 61bb str r3, [r7, #24]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
800136c: f107 0308 add.w r3, r7, #8
8001370: 2100 movs r1, #0
8001372: 4618 mov r0, r3
8001374: f002 f888 bl 8003488 <HAL_RCC_ClockConfig>
8001378: 4603 mov r3, r0
800137a: 2b00 cmp r3, #0
800137c: d001 beq.n 8001382 <SystemClock_Config+0xaa>
{
Error_Handler();
800137e: f000 f9cf bl 8001720 <Error_Handler>
}
}
8001382: bf00 nop
8001384: 3750 adds r7, #80 ; 0x50
8001386: 46bd mov sp, r7
8001388: bd80 pop {r7, pc}
800138a: bf00 nop
800138c: 40023800 .word 0x40023800
8001390: 40007000 .word 0x40007000
08001394 <MX_CAN1_Init>:
* @brief CAN1 Initialization Function
* @param None
* @retval None
*/
static void MX_CAN1_Init(void)
{
8001394: b580 push {r7, lr}
8001396: af00 add r7, sp, #0
/* USER CODE END CAN1_Init 0 */
/* USER CODE BEGIN CAN1_Init 1 */
/* USER CODE END CAN1_Init 1 */
hcan1.Instance = CAN1;
8001398: 4b17 ldr r3, [pc, #92] ; (80013f8 <MX_CAN1_Init+0x64>)
800139a: 4a18 ldr r2, [pc, #96] ; (80013fc <MX_CAN1_Init+0x68>)
800139c: 601a str r2, [r3, #0]
hcan1.Init.Prescaler = 5;
800139e: 4b16 ldr r3, [pc, #88] ; (80013f8 <MX_CAN1_Init+0x64>)
80013a0: 2205 movs r2, #5
80013a2: 605a str r2, [r3, #4]
hcan1.Init.Mode = CAN_MODE_NORMAL;
80013a4: 4b14 ldr r3, [pc, #80] ; (80013f8 <MX_CAN1_Init+0x64>)
80013a6: 2200 movs r2, #0
80013a8: 609a str r2, [r3, #8]
hcan1.Init.SyncJumpWidth = CAN_SJW_1TQ;
80013aa: 4b13 ldr r3, [pc, #76] ; (80013f8 <MX_CAN1_Init+0x64>)
80013ac: 2200 movs r2, #0
80013ae: 60da str r2, [r3, #12]
hcan1.Init.TimeSeg1 = CAN_BS1_6TQ;
80013b0: 4b11 ldr r3, [pc, #68] ; (80013f8 <MX_CAN1_Init+0x64>)
80013b2: f44f 22a0 mov.w r2, #327680 ; 0x50000
80013b6: 611a str r2, [r3, #16]
hcan1.Init.TimeSeg2 = CAN_BS2_2TQ;
80013b8: 4b0f ldr r3, [pc, #60] ; (80013f8 <MX_CAN1_Init+0x64>)
80013ba: f44f 1280 mov.w r2, #1048576 ; 0x100000
80013be: 615a str r2, [r3, #20]
hcan1.Init.TimeTriggeredMode = DISABLE;
80013c0: 4b0d ldr r3, [pc, #52] ; (80013f8 <MX_CAN1_Init+0x64>)
80013c2: 2200 movs r2, #0
80013c4: 761a strb r2, [r3, #24]
hcan1.Init.AutoBusOff = DISABLE;
80013c6: 4b0c ldr r3, [pc, #48] ; (80013f8 <MX_CAN1_Init+0x64>)
80013c8: 2200 movs r2, #0
80013ca: 765a strb r2, [r3, #25]
hcan1.Init.AutoWakeUp = DISABLE;
80013cc: 4b0a ldr r3, [pc, #40] ; (80013f8 <MX_CAN1_Init+0x64>)
80013ce: 2200 movs r2, #0
80013d0: 769a strb r2, [r3, #26]
hcan1.Init.AutoRetransmission = ENABLE;
80013d2: 4b09 ldr r3, [pc, #36] ; (80013f8 <MX_CAN1_Init+0x64>)
80013d4: 2201 movs r2, #1
80013d6: 76da strb r2, [r3, #27]
hcan1.Init.ReceiveFifoLocked = DISABLE;
80013d8: 4b07 ldr r3, [pc, #28] ; (80013f8 <MX_CAN1_Init+0x64>)
80013da: 2200 movs r2, #0
80013dc: 771a strb r2, [r3, #28]
hcan1.Init.TransmitFifoPriority = DISABLE;
80013de: 4b06 ldr r3, [pc, #24] ; (80013f8 <MX_CAN1_Init+0x64>)
80013e0: 2200 movs r2, #0
80013e2: 775a strb r2, [r3, #29]
if (HAL_CAN_Init(&hcan1) != HAL_OK)
80013e4: 4804 ldr r0, [pc, #16] ; (80013f8 <MX_CAN1_Init+0x64>)
80013e6: f000 fd6f bl 8001ec8 <HAL_CAN_Init>
80013ea: 4603 mov r3, r0
80013ec: 2b00 cmp r3, #0
80013ee: d001 beq.n 80013f4 <MX_CAN1_Init+0x60>
{
Error_Handler();
80013f0: f000 f996 bl 8001720 <Error_Handler>
}
/* USER CODE BEGIN CAN1_Init 2 */
/* USER CODE END CAN1_Init 2 */
}
80013f4: bf00 nop
80013f6: bd80 pop {r7, pc}
80013f8: 20000334 .word 0x20000334
80013fc: 40006400 .word 0x40006400
08001400 <MX_CAN2_Init>:
* @brief CAN2 Initialization Function
* @param None
* @retval None
*/
static void MX_CAN2_Init(void)
{
8001400: b580 push {r7, lr}
8001402: af00 add r7, sp, #0
/* USER CODE END CAN2_Init 0 */
/* USER CODE BEGIN CAN2_Init 1 */
/* USER CODE END CAN2_Init 1 */
hcan2.Instance = CAN2;
8001404: 4b17 ldr r3, [pc, #92] ; (8001464 <MX_CAN2_Init+0x64>)
8001406: 4a18 ldr r2, [pc, #96] ; (8001468 <MX_CAN2_Init+0x68>)
8001408: 601a str r2, [r3, #0]
hcan2.Init.Prescaler = 5;
800140a: 4b16 ldr r3, [pc, #88] ; (8001464 <MX_CAN2_Init+0x64>)
800140c: 2205 movs r2, #5
800140e: 605a str r2, [r3, #4]
hcan2.Init.Mode = CAN_MODE_NORMAL;
8001410: 4b14 ldr r3, [pc, #80] ; (8001464 <MX_CAN2_Init+0x64>)
8001412: 2200 movs r2, #0
8001414: 609a str r2, [r3, #8]
hcan2.Init.SyncJumpWidth = CAN_SJW_1TQ;
8001416: 4b13 ldr r3, [pc, #76] ; (8001464 <MX_CAN2_Init+0x64>)
8001418: 2200 movs r2, #0
800141a: 60da str r2, [r3, #12]
hcan2.Init.TimeSeg1 = CAN_BS1_6TQ;
800141c: 4b11 ldr r3, [pc, #68] ; (8001464 <MX_CAN2_Init+0x64>)
800141e: f44f 22a0 mov.w r2, #327680 ; 0x50000
8001422: 611a str r2, [r3, #16]
hcan2.Init.TimeSeg2 = CAN_BS2_2TQ;
8001424: 4b0f ldr r3, [pc, #60] ; (8001464 <MX_CAN2_Init+0x64>)
8001426: f44f 1280 mov.w r2, #1048576 ; 0x100000
800142a: 615a str r2, [r3, #20]
hcan2.Init.TimeTriggeredMode = DISABLE;
800142c: 4b0d ldr r3, [pc, #52] ; (8001464 <MX_CAN2_Init+0x64>)
800142e: 2200 movs r2, #0
8001430: 761a strb r2, [r3, #24]
hcan2.Init.AutoBusOff = DISABLE;
8001432: 4b0c ldr r3, [pc, #48] ; (8001464 <MX_CAN2_Init+0x64>)
8001434: 2200 movs r2, #0
8001436: 765a strb r2, [r3, #25]
hcan2.Init.AutoWakeUp = DISABLE;
8001438: 4b0a ldr r3, [pc, #40] ; (8001464 <MX_CAN2_Init+0x64>)
800143a: 2200 movs r2, #0
800143c: 769a strb r2, [r3, #26]
hcan2.Init.AutoRetransmission = DISABLE;
800143e: 4b09 ldr r3, [pc, #36] ; (8001464 <MX_CAN2_Init+0x64>)
8001440: 2200 movs r2, #0
8001442: 76da strb r2, [r3, #27]
hcan2.Init.ReceiveFifoLocked = DISABLE;
8001444: 4b07 ldr r3, [pc, #28] ; (8001464 <MX_CAN2_Init+0x64>)
8001446: 2200 movs r2, #0
8001448: 771a strb r2, [r3, #28]
hcan2.Init.TransmitFifoPriority = DISABLE;
800144a: 4b06 ldr r3, [pc, #24] ; (8001464 <MX_CAN2_Init+0x64>)
800144c: 2200 movs r2, #0
800144e: 775a strb r2, [r3, #29]
if (HAL_CAN_Init(&hcan2) != HAL_OK)
8001450: 4804 ldr r0, [pc, #16] ; (8001464 <MX_CAN2_Init+0x64>)
8001452: f000 fd39 bl 8001ec8 <HAL_CAN_Init>
8001456: 4603 mov r3, r0
8001458: 2b00 cmp r3, #0
800145a: d001 beq.n 8001460 <MX_CAN2_Init+0x60>
{
Error_Handler();
800145c: f000 f960 bl 8001720 <Error_Handler>
}
/* USER CODE BEGIN CAN2_Init 2 */
/* USER CODE END CAN2_Init 2 */
}
8001460: bf00 nop
8001462: bd80 pop {r7, pc}
8001464: 20000240 .word 0x20000240
8001468: 40006800 .word 0x40006800
0800146c <MX_I2C1_Init>:
* @brief I2C1 Initialization Function
* @param None
* @retval None
*/
static void MX_I2C1_Init(void)
{
800146c: b580 push {r7, lr}
800146e: af00 add r7, sp, #0
/* USER CODE END I2C1_Init 0 */
/* USER CODE BEGIN I2C1_Init 1 */
/* USER CODE END I2C1_Init 1 */
hi2c1.Instance = I2C1;
8001470: 4b12 ldr r3, [pc, #72] ; (80014bc <MX_I2C1_Init+0x50>)
8001472: 4a13 ldr r2, [pc, #76] ; (80014c0 <MX_I2C1_Init+0x54>)
8001474: 601a str r2, [r3, #0]
hi2c1.Init.ClockSpeed = 100000;
8001476: 4b11 ldr r3, [pc, #68] ; (80014bc <MX_I2C1_Init+0x50>)
8001478: 4a12 ldr r2, [pc, #72] ; (80014c4 <MX_I2C1_Init+0x58>)
800147a: 605a str r2, [r3, #4]
hi2c1.Init.DutyCycle = I2C_DUTYCYCLE_2;
800147c: 4b0f ldr r3, [pc, #60] ; (80014bc <MX_I2C1_Init+0x50>)
800147e: 2200 movs r2, #0
8001480: 609a str r2, [r3, #8]
hi2c1.Init.OwnAddress1 = 0;
8001482: 4b0e ldr r3, [pc, #56] ; (80014bc <MX_I2C1_Init+0x50>)
8001484: 2200 movs r2, #0
8001486: 60da str r2, [r3, #12]
hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
8001488: 4b0c ldr r3, [pc, #48] ; (80014bc <MX_I2C1_Init+0x50>)
800148a: f44f 4280 mov.w r2, #16384 ; 0x4000
800148e: 611a str r2, [r3, #16]
hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
8001490: 4b0a ldr r3, [pc, #40] ; (80014bc <MX_I2C1_Init+0x50>)
8001492: 2200 movs r2, #0
8001494: 615a str r2, [r3, #20]
hi2c1.Init.OwnAddress2 = 0;
8001496: 4b09 ldr r3, [pc, #36] ; (80014bc <MX_I2C1_Init+0x50>)
8001498: 2200 movs r2, #0
800149a: 619a str r2, [r3, #24]
hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
800149c: 4b07 ldr r3, [pc, #28] ; (80014bc <MX_I2C1_Init+0x50>)
800149e: 2200 movs r2, #0
80014a0: 61da str r2, [r3, #28]
hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
80014a2: 4b06 ldr r3, [pc, #24] ; (80014bc <MX_I2C1_Init+0x50>)
80014a4: 2200 movs r2, #0
80014a6: 621a str r2, [r3, #32]
if (HAL_I2C_Init(&hi2c1) != HAL_OK)
80014a8: 4804 ldr r0, [pc, #16] ; (80014bc <MX_I2C1_Init+0x50>)
80014aa: f001 fea9 bl 8003200 <HAL_I2C_Init>
80014ae: 4603 mov r3, r0
80014b0: 2b00 cmp r3, #0
80014b2: d001 beq.n 80014b8 <MX_I2C1_Init+0x4c>
{
Error_Handler();
80014b4: f000 f934 bl 8001720 <Error_Handler>
}
/* USER CODE BEGIN I2C1_Init 2 */
/* USER CODE END I2C1_Init 2 */
}
80014b8: bf00 nop
80014ba: bd80 pop {r7, pc}
80014bc: 200001ec .word 0x200001ec
80014c0: 40005400 .word 0x40005400
80014c4: 000186a0 .word 0x000186a0
080014c8 <MX_USART1_UART_Init>:
* @brief USART1 Initialization Function
* @param None
* @retval None
*/
static void MX_USART1_UART_Init(void)
{
80014c8: b580 push {r7, lr}
80014ca: af00 add r7, sp, #0
/* USER CODE END USART1_Init 0 */
/* USER CODE BEGIN USART1_Init 1 */
/* USER CODE END USART1_Init 1 */
huart1.Instance = USART1;
80014cc: 4b11 ldr r3, [pc, #68] ; (8001514 <MX_USART1_UART_Init+0x4c>)
80014ce: 4a12 ldr r2, [pc, #72] ; (8001518 <MX_USART1_UART_Init+0x50>)
80014d0: 601a str r2, [r3, #0]
huart1.Init.BaudRate = 115200;
80014d2: 4b10 ldr r3, [pc, #64] ; (8001514 <MX_USART1_UART_Init+0x4c>)
80014d4: f44f 32e1 mov.w r2, #115200 ; 0x1c200
80014d8: 605a str r2, [r3, #4]
huart1.Init.WordLength = UART_WORDLENGTH_8B;
80014da: 4b0e ldr r3, [pc, #56] ; (8001514 <MX_USART1_UART_Init+0x4c>)
80014dc: 2200 movs r2, #0
80014de: 609a str r2, [r3, #8]
huart1.Init.StopBits = UART_STOPBITS_1;
80014e0: 4b0c ldr r3, [pc, #48] ; (8001514 <MX_USART1_UART_Init+0x4c>)
80014e2: 2200 movs r2, #0
80014e4: 60da str r2, [r3, #12]
huart1.Init.Parity = UART_PARITY_NONE;
80014e6: 4b0b ldr r3, [pc, #44] ; (8001514 <MX_USART1_UART_Init+0x4c>)
80014e8: 2200 movs r2, #0
80014ea: 611a str r2, [r3, #16]
huart1.Init.Mode = UART_MODE_TX_RX;
80014ec: 4b09 ldr r3, [pc, #36] ; (8001514 <MX_USART1_UART_Init+0x4c>)
80014ee: 220c movs r2, #12
80014f0: 615a str r2, [r3, #20]
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
80014f2: 4b08 ldr r3, [pc, #32] ; (8001514 <MX_USART1_UART_Init+0x4c>)
80014f4: 2200 movs r2, #0
80014f6: 619a str r2, [r3, #24]
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
80014f8: 4b06 ldr r3, [pc, #24] ; (8001514 <MX_USART1_UART_Init+0x4c>)
80014fa: 2200 movs r2, #0
80014fc: 61da str r2, [r3, #28]
if (HAL_UART_Init(&huart1) != HAL_OK)
80014fe: 4805 ldr r0, [pc, #20] ; (8001514 <MX_USART1_UART_Init+0x4c>)
8001500: f002 fc40 bl 8003d84 <HAL_UART_Init>
8001504: 4603 mov r3, r0
8001506: 2b00 cmp r3, #0
8001508: d001 beq.n 800150e <MX_USART1_UART_Init+0x46>
{
Error_Handler();
800150a: f000 f909 bl 8001720 <Error_Handler>
}
/* USER CODE BEGIN USART1_Init 2 */
/* USER CODE END USART1_Init 2 */
}
800150e: bf00 nop
8001510: bd80 pop {r7, pc}
8001512: bf00 nop
8001514: 20000268 .word 0x20000268
8001518: 40011000 .word 0x40011000
0800151c <MX_USART2_UART_Init>:
* @brief USART2 Initialization Function
* @param None
* @retval None
*/
static void MX_USART2_UART_Init(void)
{
800151c: b580 push {r7, lr}
800151e: af00 add r7, sp, #0
/* USER CODE END USART2_Init 0 */
/* USER CODE BEGIN USART2_Init 1 */
/* USER CODE END USART2_Init 1 */
huart2.Instance = USART2;
8001520: 4b10 ldr r3, [pc, #64] ; (8001564 <MX_USART2_UART_Init+0x48>)
8001522: 4a11 ldr r2, [pc, #68] ; (8001568 <MX_USART2_UART_Init+0x4c>)
8001524: 601a str r2, [r3, #0]
huart2.Init.BaudRate = 250000;
8001526: 4b0f ldr r3, [pc, #60] ; (8001564 <MX_USART2_UART_Init+0x48>)
8001528: 4a10 ldr r2, [pc, #64] ; (800156c <MX_USART2_UART_Init+0x50>)
800152a: 605a str r2, [r3, #4]
huart2.Init.WordLength = UART_WORDLENGTH_8B;
800152c: 4b0d ldr r3, [pc, #52] ; (8001564 <MX_USART2_UART_Init+0x48>)
800152e: 2200 movs r2, #0
8001530: 609a str r2, [r3, #8]
huart2.Init.StopBits = UART_STOPBITS_1;
8001532: 4b0c ldr r3, [pc, #48] ; (8001564 <MX_USART2_UART_Init+0x48>)
8001534: 2200 movs r2, #0
8001536: 60da str r2, [r3, #12]
huart2.Init.Parity = UART_PARITY_NONE;
8001538: 4b0a ldr r3, [pc, #40] ; (8001564 <MX_USART2_UART_Init+0x48>)
800153a: 2200 movs r2, #0
800153c: 611a str r2, [r3, #16]
huart2.Init.Mode = UART_MODE_TX_RX;
800153e: 4b09 ldr r3, [pc, #36] ; (8001564 <MX_USART2_UART_Init+0x48>)
8001540: 220c movs r2, #12
8001542: 615a str r2, [r3, #20]
huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
8001544: 4b07 ldr r3, [pc, #28] ; (8001564 <MX_USART2_UART_Init+0x48>)
8001546: 2200 movs r2, #0
8001548: 619a str r2, [r3, #24]
huart2.Init.OverSampling = UART_OVERSAMPLING_16;
800154a: 4b06 ldr r3, [pc, #24] ; (8001564 <MX_USART2_UART_Init+0x48>)
800154c: 2200 movs r2, #0
800154e: 61da str r2, [r3, #28]
if (HAL_UART_Init(&huart2) != HAL_OK)
8001550: 4804 ldr r0, [pc, #16] ; (8001564 <MX_USART2_UART_Init+0x48>)
8001552: f002 fc17 bl 8003d84 <HAL_UART_Init>
8001556: 4603 mov r3, r0
8001558: 2b00 cmp r3, #0
800155a: d001 beq.n 8001560 <MX_USART2_UART_Init+0x44>
{
Error_Handler();
800155c: f000 f8e0 bl 8001720 <Error_Handler>
}
/* USER CODE BEGIN USART2_Init 2 */
/* USER CODE END USART2_Init 2 */
}
8001560: bf00 nop
8001562: bd80 pop {r7, pc}
8001564: 200002f0 .word 0x200002f0
8001568: 40004400 .word 0x40004400
800156c: 0003d090 .word 0x0003d090
08001570 <MX_USART3_UART_Init>:
* @brief USART3 Initialization Function
* @param None
* @retval None
*/
static void MX_USART3_UART_Init(void)
{
8001570: b580 push {r7, lr}
8001572: af00 add r7, sp, #0
/* USER CODE END USART3_Init 0 */
/* USER CODE BEGIN USART3_Init 1 */
/* USER CODE END USART3_Init 1 */
huart3.Instance = USART3;
8001574: 4b11 ldr r3, [pc, #68] ; (80015bc <MX_USART3_UART_Init+0x4c>)
8001576: 4a12 ldr r2, [pc, #72] ; (80015c0 <MX_USART3_UART_Init+0x50>)
8001578: 601a str r2, [r3, #0]
huart3.Init.BaudRate = 115200;
800157a: 4b10 ldr r3, [pc, #64] ; (80015bc <MX_USART3_UART_Init+0x4c>)
800157c: f44f 32e1 mov.w r2, #115200 ; 0x1c200
8001580: 605a str r2, [r3, #4]
huart3.Init.WordLength = UART_WORDLENGTH_8B;
8001582: 4b0e ldr r3, [pc, #56] ; (80015bc <MX_USART3_UART_Init+0x4c>)
8001584: 2200 movs r2, #0
8001586: 609a str r2, [r3, #8]
huart3.Init.StopBits = UART_STOPBITS_1;
8001588: 4b0c ldr r3, [pc, #48] ; (80015bc <MX_USART3_UART_Init+0x4c>)
800158a: 2200 movs r2, #0
800158c: 60da str r2, [r3, #12]
huart3.Init.Parity = UART_PARITY_NONE;
800158e: 4b0b ldr r3, [pc, #44] ; (80015bc <MX_USART3_UART_Init+0x4c>)
8001590: 2200 movs r2, #0
8001592: 611a str r2, [r3, #16]
huart3.Init.Mode = UART_MODE_TX_RX;
8001594: 4b09 ldr r3, [pc, #36] ; (80015bc <MX_USART3_UART_Init+0x4c>)
8001596: 220c movs r2, #12
8001598: 615a str r2, [r3, #20]
huart3.Init.HwFlowCtl = UART_HWCONTROL_NONE;
800159a: 4b08 ldr r3, [pc, #32] ; (80015bc <MX_USART3_UART_Init+0x4c>)
800159c: 2200 movs r2, #0
800159e: 619a str r2, [r3, #24]
huart3.Init.OverSampling = UART_OVERSAMPLING_16;
80015a0: 4b06 ldr r3, [pc, #24] ; (80015bc <MX_USART3_UART_Init+0x4c>)
80015a2: 2200 movs r2, #0
80015a4: 61da str r2, [r3, #28]
if (HAL_UART_Init(&huart3) != HAL_OK)
80015a6: 4805 ldr r0, [pc, #20] ; (80015bc <MX_USART3_UART_Init+0x4c>)
80015a8: f002 fbec bl 8003d84 <HAL_UART_Init>
80015ac: 4603 mov r3, r0
80015ae: 2b00 cmp r3, #0
80015b0: d001 beq.n 80015b6 <MX_USART3_UART_Init+0x46>
{
Error_Handler();
80015b2: f000 f8b5 bl 8001720 <Error_Handler>
}
/* USER CODE BEGIN USART3_Init 2 */
/* USER CODE END USART3_Init 2 */
}
80015b6: bf00 nop
80015b8: bd80 pop {r7, pc}
80015ba: bf00 nop
80015bc: 200001a8 .word 0x200001a8
80015c0: 40004800 .word 0x40004800
080015c4 <MX_USART6_UART_Init>:
* @brief USART6 Initialization Function
* @param None
* @retval None
*/
static void MX_USART6_UART_Init(void)
{
80015c4: b580 push {r7, lr}
80015c6: af00 add r7, sp, #0
/* USER CODE END USART6_Init 0 */
/* USER CODE BEGIN USART6_Init 1 */
/* USER CODE END USART6_Init 1 */
huart6.Instance = USART6;
80015c8: 4b11 ldr r3, [pc, #68] ; (8001610 <MX_USART6_UART_Init+0x4c>)
80015ca: 4a12 ldr r2, [pc, #72] ; (8001614 <MX_USART6_UART_Init+0x50>)
80015cc: 601a str r2, [r3, #0]
huart6.Init.BaudRate = 115200;
80015ce: 4b10 ldr r3, [pc, #64] ; (8001610 <MX_USART6_UART_Init+0x4c>)
80015d0: f44f 32e1 mov.w r2, #115200 ; 0x1c200
80015d4: 605a str r2, [r3, #4]
huart6.Init.WordLength = UART_WORDLENGTH_8B;
80015d6: 4b0e ldr r3, [pc, #56] ; (8001610 <MX_USART6_UART_Init+0x4c>)
80015d8: 2200 movs r2, #0
80015da: 609a str r2, [r3, #8]
huart6.Init.StopBits = UART_STOPBITS_1;
80015dc: 4b0c ldr r3, [pc, #48] ; (8001610 <MX_USART6_UART_Init+0x4c>)
80015de: 2200 movs r2, #0
80015e0: 60da str r2, [r3, #12]
huart6.Init.Parity = UART_PARITY_NONE;
80015e2: 4b0b ldr r3, [pc, #44] ; (8001610 <MX_USART6_UART_Init+0x4c>)
80015e4: 2200 movs r2, #0
80015e6: 611a str r2, [r3, #16]
huart6.Init.Mode = UART_MODE_TX_RX;
80015e8: 4b09 ldr r3, [pc, #36] ; (8001610 <MX_USART6_UART_Init+0x4c>)
80015ea: 220c movs r2, #12
80015ec: 615a str r2, [r3, #20]
huart6.Init.HwFlowCtl = UART_HWCONTROL_NONE;
80015ee: 4b08 ldr r3, [pc, #32] ; (8001610 <MX_USART6_UART_Init+0x4c>)
80015f0: 2200 movs r2, #0
80015f2: 619a str r2, [r3, #24]
huart6.Init.OverSampling = UART_OVERSAMPLING_16;
80015f4: 4b06 ldr r3, [pc, #24] ; (8001610 <MX_USART6_UART_Init+0x4c>)
80015f6: 2200 movs r2, #0
80015f8: 61da str r2, [r3, #28]
if (HAL_UART_Init(&huart6) != HAL_OK)
80015fa: 4805 ldr r0, [pc, #20] ; (8001610 <MX_USART6_UART_Init+0x4c>)
80015fc: f002 fbc2 bl 8003d84 <HAL_UART_Init>
8001600: 4603 mov r3, r0
8001602: 2b00 cmp r3, #0
8001604: d001 beq.n 800160a <MX_USART6_UART_Init+0x46>
{
Error_Handler();
8001606: f000 f88b bl 8001720 <Error_Handler>
}
/* USER CODE BEGIN USART6_Init 2 */
/* USER CODE END USART6_Init 2 */
}
800160a: bf00 nop
800160c: bd80 pop {r7, pc}
800160e: bf00 nop
8001610: 200002ac .word 0x200002ac
8001614: 40011400 .word 0x40011400
08001618 <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
8001618: b580 push {r7, lr}
800161a: b08a sub sp, #40 ; 0x28
800161c: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
800161e: f107 0314 add.w r3, r7, #20
8001622: 2200 movs r2, #0
8001624: 601a str r2, [r3, #0]
8001626: 605a str r2, [r3, #4]
8001628: 609a str r2, [r3, #8]
800162a: 60da str r2, [r3, #12]
800162c: 611a str r2, [r3, #16]
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOC_CLK_ENABLE();
800162e: 2300 movs r3, #0
8001630: 613b str r3, [r7, #16]
8001632: 4b37 ldr r3, [pc, #220] ; (8001710 <MX_GPIO_Init+0xf8>)
8001634: 6b1b ldr r3, [r3, #48] ; 0x30
8001636: 4a36 ldr r2, [pc, #216] ; (8001710 <MX_GPIO_Init+0xf8>)
8001638: f043 0304 orr.w r3, r3, #4
800163c: 6313 str r3, [r2, #48] ; 0x30
800163e: 4b34 ldr r3, [pc, #208] ; (8001710 <MX_GPIO_Init+0xf8>)
8001640: 6b1b ldr r3, [r3, #48] ; 0x30
8001642: f003 0304 and.w r3, r3, #4
8001646: 613b str r3, [r7, #16]
8001648: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
800164a: 2300 movs r3, #0
800164c: 60fb str r3, [r7, #12]
800164e: 4b30 ldr r3, [pc, #192] ; (8001710 <MX_GPIO_Init+0xf8>)
8001650: 6b1b ldr r3, [r3, #48] ; 0x30
8001652: 4a2f ldr r2, [pc, #188] ; (8001710 <MX_GPIO_Init+0xf8>)
8001654: f043 0301 orr.w r3, r3, #1
8001658: 6313 str r3, [r2, #48] ; 0x30
800165a: 4b2d ldr r3, [pc, #180] ; (8001710 <MX_GPIO_Init+0xf8>)
800165c: 6b1b ldr r3, [r3, #48] ; 0x30
800165e: f003 0301 and.w r3, r3, #1
8001662: 60fb str r3, [r7, #12]
8001664: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOB_CLK_ENABLE();
8001666: 2300 movs r3, #0
8001668: 60bb str r3, [r7, #8]
800166a: 4b29 ldr r3, [pc, #164] ; (8001710 <MX_GPIO_Init+0xf8>)
800166c: 6b1b ldr r3, [r3, #48] ; 0x30
800166e: 4a28 ldr r2, [pc, #160] ; (8001710 <MX_GPIO_Init+0xf8>)
8001670: f043 0302 orr.w r3, r3, #2
8001674: 6313 str r3, [r2, #48] ; 0x30
8001676: 4b26 ldr r3, [pc, #152] ; (8001710 <MX_GPIO_Init+0xf8>)
8001678: 6b1b ldr r3, [r3, #48] ; 0x30
800167a: f003 0302 and.w r3, r3, #2
800167e: 60bb str r3, [r7, #8]
8001680: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOD_CLK_ENABLE();
8001682: 2300 movs r3, #0
8001684: 607b str r3, [r7, #4]
8001686: 4b22 ldr r3, [pc, #136] ; (8001710 <MX_GPIO_Init+0xf8>)
8001688: 6b1b ldr r3, [r3, #48] ; 0x30
800168a: 4a21 ldr r2, [pc, #132] ; (8001710 <MX_GPIO_Init+0xf8>)
800168c: f043 0308 orr.w r3, r3, #8
8001690: 6313 str r3, [r2, #48] ; 0x30
8001692: 4b1f ldr r3, [pc, #124] ; (8001710 <MX_GPIO_Init+0xf8>)
8001694: 6b1b ldr r3, [r3, #48] ; 0x30
8001696: f003 0308 and.w r3, r3, #8
800169a: 607b str r3, [r7, #4]
800169c: 687b ldr r3, [r7, #4]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOC, STAT_LED1_Pin|STAT_LED2_Pin|STAT_LED3_Pin|STAT_LED4_Pin
800169e: 2200 movs r2, #0
80016a0: f240 210f movw r1, #527 ; 0x20f
80016a4: 481b ldr r0, [pc, #108] ; (8001714 <MX_GPIO_Init+0xfc>)
80016a6: f001 fd91 bl 80031cc <HAL_GPIO_WritePin>
|FAN_CONTROL_Pin, GPIO_PIN_RESET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOB, BQ_POWER_ACTIVATE_Pin|BQ_VIO_ACTICATE_Pin|BQ_Wakeup_Pin, GPIO_PIN_RESET);
80016aa: 2200 movs r2, #0
80016ac: 2113 movs r1, #19
80016ae: 481a ldr r0, [pc, #104] ; (8001718 <MX_GPIO_Init+0x100>)
80016b0: f001 fd8c bl 80031cc <HAL_GPIO_WritePin>
/*Configure GPIO pins : STAT_LED1_Pin STAT_LED2_Pin STAT_LED3_Pin STAT_LED4_Pin
FAN_CONTROL_Pin */
GPIO_InitStruct.Pin = STAT_LED1_Pin|STAT_LED2_Pin|STAT_LED3_Pin|STAT_LED4_Pin
80016b4: f240 230f movw r3, #527 ; 0x20f
80016b8: 617b str r3, [r7, #20]
|FAN_CONTROL_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
80016ba: 2301 movs r3, #1
80016bc: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80016be: 2300 movs r3, #0
80016c0: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80016c2: 2300 movs r3, #0
80016c4: 623b str r3, [r7, #32]
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
80016c6: f107 0314 add.w r3, r7, #20
80016ca: 4619 mov r1, r3
80016cc: 4811 ldr r0, [pc, #68] ; (8001714 <MX_GPIO_Init+0xfc>)
80016ce: f001 fc01 bl 8002ed4 <HAL_GPIO_Init>
/*Configure GPIO pins : BQ_POWER_ACTIVATE_Pin BQ_VIO_ACTICATE_Pin BQ_Wakeup_Pin */
GPIO_InitStruct.Pin = BQ_POWER_ACTIVATE_Pin|BQ_VIO_ACTICATE_Pin|BQ_Wakeup_Pin;
80016d2: 2313 movs r3, #19
80016d4: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
80016d6: 2301 movs r3, #1
80016d8: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80016da: 2300 movs r3, #0
80016dc: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80016de: 2300 movs r3, #0
80016e0: 623b str r3, [r7, #32]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80016e2: f107 0314 add.w r3, r7, #20
80016e6: 4619 mov r1, r3
80016e8: 480b ldr r0, [pc, #44] ; (8001718 <MX_GPIO_Init+0x100>)
80016ea: f001 fbf3 bl 8002ed4 <HAL_GPIO_Init>
/*Configure GPIO pin : PD2 */
GPIO_InitStruct.Pin = GPIO_PIN_2;
80016ee: 2304 movs r3, #4
80016f0: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
80016f2: 2300 movs r3, #0
80016f4: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80016f6: 2300 movs r3, #0
80016f8: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
80016fa: f107 0314 add.w r3, r7, #20
80016fe: 4619 mov r1, r3
8001700: 4806 ldr r0, [pc, #24] ; (800171c <MX_GPIO_Init+0x104>)
8001702: f001 fbe7 bl 8002ed4 <HAL_GPIO_Init>
}
8001706: bf00 nop
8001708: 3728 adds r7, #40 ; 0x28
800170a: 46bd mov sp, r7
800170c: bd80 pop {r7, pc}
800170e: bf00 nop
8001710: 40023800 .word 0x40023800
8001714: 40020800 .word 0x40020800
8001718: 40020400 .word 0x40020400
800171c: 40020c00 .word 0x40020c00
08001720 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
8001720: b480 push {r7}
8001722: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
8001724: b672 cpsid i
}
8001726: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
8001728: e7fe b.n 8001728 <Error_Handler+0x8>
...
0800172c <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
800172c: b580 push {r7, lr}
800172e: b082 sub sp, #8
8001730: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8001732: 2300 movs r3, #0
8001734: 607b str r3, [r7, #4]
8001736: 4b12 ldr r3, [pc, #72] ; (8001780 <HAL_MspInit+0x54>)
8001738: 6c5b ldr r3, [r3, #68] ; 0x44
800173a: 4a11 ldr r2, [pc, #68] ; (8001780 <HAL_MspInit+0x54>)
800173c: f443 4380 orr.w r3, r3, #16384 ; 0x4000
8001740: 6453 str r3, [r2, #68] ; 0x44
8001742: 4b0f ldr r3, [pc, #60] ; (8001780 <HAL_MspInit+0x54>)
8001744: 6c5b ldr r3, [r3, #68] ; 0x44
8001746: f403 4380 and.w r3, r3, #16384 ; 0x4000
800174a: 607b str r3, [r7, #4]
800174c: 687b ldr r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
800174e: 2300 movs r3, #0
8001750: 603b str r3, [r7, #0]
8001752: 4b0b ldr r3, [pc, #44] ; (8001780 <HAL_MspInit+0x54>)
8001754: 6c1b ldr r3, [r3, #64] ; 0x40
8001756: 4a0a ldr r2, [pc, #40] ; (8001780 <HAL_MspInit+0x54>)
8001758: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
800175c: 6413 str r3, [r2, #64] ; 0x40
800175e: 4b08 ldr r3, [pc, #32] ; (8001780 <HAL_MspInit+0x54>)
8001760: 6c1b ldr r3, [r3, #64] ; 0x40
8001762: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8001766: 603b str r3, [r7, #0]
8001768: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/* DebugMonitor_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DebugMonitor_IRQn, 1, 0);
800176a: 2200 movs r2, #0
800176c: 2101 movs r1, #1
800176e: f06f 0003 mvn.w r0, #3
8001772: f001 fae6 bl 8002d42 <HAL_NVIC_SetPriority>
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
8001776: bf00 nop
8001778: 3708 adds r7, #8
800177a: 46bd mov sp, r7
800177c: bd80 pop {r7, pc}
800177e: bf00 nop
8001780: 40023800 .word 0x40023800
08001784 <HAL_CAN_MspInit>:
* This function configures the hardware resources used in this example
* @param hcan: CAN handle pointer
* @retval None
*/
void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
{
8001784: b580 push {r7, lr}
8001786: b08c sub sp, #48 ; 0x30
8001788: af00 add r7, sp, #0
800178a: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
800178c: f107 031c add.w r3, r7, #28
8001790: 2200 movs r2, #0
8001792: 601a str r2, [r3, #0]
8001794: 605a str r2, [r3, #4]
8001796: 609a str r2, [r3, #8]
8001798: 60da str r2, [r3, #12]
800179a: 611a str r2, [r3, #16]
if(hcan->Instance==CAN1)
800179c: 687b ldr r3, [r7, #4]
800179e: 681b ldr r3, [r3, #0]
80017a0: 4a57 ldr r2, [pc, #348] ; (8001900 <HAL_CAN_MspInit+0x17c>)
80017a2: 4293 cmp r3, r2
80017a4: d146 bne.n 8001834 <HAL_CAN_MspInit+0xb0>
{
/* USER CODE BEGIN CAN1_MspInit 0 */
/* USER CODE END CAN1_MspInit 0 */
/* Peripheral clock enable */
HAL_RCC_CAN1_CLK_ENABLED++;
80017a6: 4b57 ldr r3, [pc, #348] ; (8001904 <HAL_CAN_MspInit+0x180>)
80017a8: 681b ldr r3, [r3, #0]
80017aa: 3301 adds r3, #1
80017ac: 4a55 ldr r2, [pc, #340] ; (8001904 <HAL_CAN_MspInit+0x180>)
80017ae: 6013 str r3, [r2, #0]
if(HAL_RCC_CAN1_CLK_ENABLED==1){
80017b0: 4b54 ldr r3, [pc, #336] ; (8001904 <HAL_CAN_MspInit+0x180>)
80017b2: 681b ldr r3, [r3, #0]
80017b4: 2b01 cmp r3, #1
80017b6: d10d bne.n 80017d4 <HAL_CAN_MspInit+0x50>
__HAL_RCC_CAN1_CLK_ENABLE();
80017b8: 2300 movs r3, #0
80017ba: 61bb str r3, [r7, #24]
80017bc: 4b52 ldr r3, [pc, #328] ; (8001908 <HAL_CAN_MspInit+0x184>)
80017be: 6c1b ldr r3, [r3, #64] ; 0x40
80017c0: 4a51 ldr r2, [pc, #324] ; (8001908 <HAL_CAN_MspInit+0x184>)
80017c2: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000
80017c6: 6413 str r3, [r2, #64] ; 0x40
80017c8: 4b4f ldr r3, [pc, #316] ; (8001908 <HAL_CAN_MspInit+0x184>)
80017ca: 6c1b ldr r3, [r3, #64] ; 0x40
80017cc: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
80017d0: 61bb str r3, [r7, #24]
80017d2: 69bb ldr r3, [r7, #24]
}
__HAL_RCC_GPIOA_CLK_ENABLE();
80017d4: 2300 movs r3, #0
80017d6: 617b str r3, [r7, #20]
80017d8: 4b4b ldr r3, [pc, #300] ; (8001908 <HAL_CAN_MspInit+0x184>)
80017da: 6b1b ldr r3, [r3, #48] ; 0x30
80017dc: 4a4a ldr r2, [pc, #296] ; (8001908 <HAL_CAN_MspInit+0x184>)
80017de: f043 0301 orr.w r3, r3, #1
80017e2: 6313 str r3, [r2, #48] ; 0x30
80017e4: 4b48 ldr r3, [pc, #288] ; (8001908 <HAL_CAN_MspInit+0x184>)
80017e6: 6b1b ldr r3, [r3, #48] ; 0x30
80017e8: f003 0301 and.w r3, r3, #1
80017ec: 617b str r3, [r7, #20]
80017ee: 697b ldr r3, [r7, #20]
/**CAN1 GPIO Configuration
PA11 ------> CAN1_RX
PA12 ------> CAN1_TX
*/
GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12;
80017f0: f44f 53c0 mov.w r3, #6144 ; 0x1800
80017f4: 61fb str r3, [r7, #28]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80017f6: 2302 movs r3, #2
80017f8: 623b str r3, [r7, #32]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80017fa: 2300 movs r3, #0
80017fc: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
80017fe: 2303 movs r3, #3
8001800: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Alternate = GPIO_AF9_CAN1;
8001802: 2309 movs r3, #9
8001804: 62fb str r3, [r7, #44] ; 0x2c
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001806: f107 031c add.w r3, r7, #28
800180a: 4619 mov r1, r3
800180c: 483f ldr r0, [pc, #252] ; (800190c <HAL_CAN_MspInit+0x188>)
800180e: f001 fb61 bl 8002ed4 <HAL_GPIO_Init>
/* CAN1 interrupt Init */
HAL_NVIC_SetPriority(CAN1_RX0_IRQn, 0, 0);
8001812: 2200 movs r2, #0
8001814: 2100 movs r1, #0
8001816: 2014 movs r0, #20
8001818: f001 fa93 bl 8002d42 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(CAN1_RX0_IRQn);
800181c: 2014 movs r0, #20
800181e: f001 faac bl 8002d7a <HAL_NVIC_EnableIRQ>
HAL_NVIC_SetPriority(CAN1_RX1_IRQn, 0, 0);
8001822: 2200 movs r2, #0
8001824: 2100 movs r1, #0
8001826: 2015 movs r0, #21
8001828: f001 fa8b bl 8002d42 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(CAN1_RX1_IRQn);
800182c: 2015 movs r0, #21
800182e: f001 faa4 bl 8002d7a <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN CAN2_MspInit 1 */
/* USER CODE END CAN2_MspInit 1 */
}
}
8001832: e060 b.n 80018f6 <HAL_CAN_MspInit+0x172>
else if(hcan->Instance==CAN2)
8001834: 687b ldr r3, [r7, #4]
8001836: 681b ldr r3, [r3, #0]
8001838: 4a35 ldr r2, [pc, #212] ; (8001910 <HAL_CAN_MspInit+0x18c>)
800183a: 4293 cmp r3, r2
800183c: d15b bne.n 80018f6 <HAL_CAN_MspInit+0x172>
HAL_RCC_CAN1_CLK_ENABLED++;
800183e: 4b31 ldr r3, [pc, #196] ; (8001904 <HAL_CAN_MspInit+0x180>)
8001840: 681b ldr r3, [r3, #0]
8001842: 3301 adds r3, #1
8001844: 4a2f ldr r2, [pc, #188] ; (8001904 <HAL_CAN_MspInit+0x180>)
8001846: 6013 str r3, [r2, #0]
if(HAL_RCC_CAN1_CLK_ENABLED==1){
8001848: 4b2e ldr r3, [pc, #184] ; (8001904 <HAL_CAN_MspInit+0x180>)
800184a: 681b ldr r3, [r3, #0]
800184c: 2b01 cmp r3, #1
800184e: d10d bne.n 800186c <HAL_CAN_MspInit+0xe8>
__HAL_RCC_CAN1_CLK_ENABLE();
8001850: 2300 movs r3, #0
8001852: 613b str r3, [r7, #16]
8001854: 4b2c ldr r3, [pc, #176] ; (8001908 <HAL_CAN_MspInit+0x184>)
8001856: 6c1b ldr r3, [r3, #64] ; 0x40
8001858: 4a2b ldr r2, [pc, #172] ; (8001908 <HAL_CAN_MspInit+0x184>)
800185a: f043 7300 orr.w r3, r3, #33554432 ; 0x2000000
800185e: 6413 str r3, [r2, #64] ; 0x40
8001860: 4b29 ldr r3, [pc, #164] ; (8001908 <HAL_CAN_MspInit+0x184>)
8001862: 6c1b ldr r3, [r3, #64] ; 0x40
8001864: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8001868: 613b str r3, [r7, #16]
800186a: 693b ldr r3, [r7, #16]
__HAL_RCC_CAN2_CLK_ENABLE();
800186c: 2300 movs r3, #0
800186e: 60fb str r3, [r7, #12]
8001870: 4b25 ldr r3, [pc, #148] ; (8001908 <HAL_CAN_MspInit+0x184>)
8001872: 6c1b ldr r3, [r3, #64] ; 0x40
8001874: 4a24 ldr r2, [pc, #144] ; (8001908 <HAL_CAN_MspInit+0x184>)
8001876: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000
800187a: 6413 str r3, [r2, #64] ; 0x40
800187c: 4b22 ldr r3, [pc, #136] ; (8001908 <HAL_CAN_MspInit+0x184>)
800187e: 6c1b ldr r3, [r3, #64] ; 0x40
8001880: f003 6380 and.w r3, r3, #67108864 ; 0x4000000
8001884: 60fb str r3, [r7, #12]
8001886: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOB_CLK_ENABLE();
8001888: 2300 movs r3, #0
800188a: 60bb str r3, [r7, #8]
800188c: 4b1e ldr r3, [pc, #120] ; (8001908 <HAL_CAN_MspInit+0x184>)
800188e: 6b1b ldr r3, [r3, #48] ; 0x30
8001890: 4a1d ldr r2, [pc, #116] ; (8001908 <HAL_CAN_MspInit+0x184>)
8001892: f043 0302 orr.w r3, r3, #2
8001896: 6313 str r3, [r2, #48] ; 0x30
8001898: 4b1b ldr r3, [pc, #108] ; (8001908 <HAL_CAN_MspInit+0x184>)
800189a: 6b1b ldr r3, [r3, #48] ; 0x30
800189c: f003 0302 and.w r3, r3, #2
80018a0: 60bb str r3, [r7, #8]
80018a2: 68bb ldr r3, [r7, #8]
GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_5;
80018a4: f242 0320 movw r3, #8224 ; 0x2020
80018a8: 61fb str r3, [r7, #28]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80018aa: 2302 movs r3, #2
80018ac: 623b str r3, [r7, #32]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80018ae: 2300 movs r3, #0
80018b0: 627b str r3, [r7, #36] ; 0x24
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
80018b2: 2303 movs r3, #3
80018b4: 62bb str r3, [r7, #40] ; 0x28
GPIO_InitStruct.Alternate = GPIO_AF9_CAN2;
80018b6: 2309 movs r3, #9
80018b8: 62fb str r3, [r7, #44] ; 0x2c
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80018ba: f107 031c add.w r3, r7, #28
80018be: 4619 mov r1, r3
80018c0: 4814 ldr r0, [pc, #80] ; (8001914 <HAL_CAN_MspInit+0x190>)
80018c2: f001 fb07 bl 8002ed4 <HAL_GPIO_Init>
HAL_NVIC_SetPriority(CAN2_RX0_IRQn, 0, 0);
80018c6: 2200 movs r2, #0
80018c8: 2100 movs r1, #0
80018ca: 2040 movs r0, #64 ; 0x40
80018cc: f001 fa39 bl 8002d42 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(CAN2_RX0_IRQn);
80018d0: 2040 movs r0, #64 ; 0x40
80018d2: f001 fa52 bl 8002d7a <HAL_NVIC_EnableIRQ>
HAL_NVIC_SetPriority(CAN2_RX1_IRQn, 0, 0);
80018d6: 2200 movs r2, #0
80018d8: 2100 movs r1, #0
80018da: 2041 movs r0, #65 ; 0x41
80018dc: f001 fa31 bl 8002d42 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(CAN2_RX1_IRQn);
80018e0: 2041 movs r0, #65 ; 0x41
80018e2: f001 fa4a bl 8002d7a <HAL_NVIC_EnableIRQ>
HAL_NVIC_SetPriority(CAN2_SCE_IRQn, 0, 0);
80018e6: 2200 movs r2, #0
80018e8: 2100 movs r1, #0
80018ea: 2042 movs r0, #66 ; 0x42
80018ec: f001 fa29 bl 8002d42 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(CAN2_SCE_IRQn);
80018f0: 2042 movs r0, #66 ; 0x42
80018f2: f001 fa42 bl 8002d7a <HAL_NVIC_EnableIRQ>
}
80018f6: bf00 nop
80018f8: 3730 adds r7, #48 ; 0x30
80018fa: 46bd mov sp, r7
80018fc: bd80 pop {r7, pc}
80018fe: bf00 nop
8001900: 40006400 .word 0x40006400
8001904: 20000160 .word 0x20000160
8001908: 40023800 .word 0x40023800
800190c: 40020000 .word 0x40020000
8001910: 40006800 .word 0x40006800
8001914: 40020400 .word 0x40020400
08001918 <HAL_I2C_MspInit>:
* This function configures the hardware resources used in this example
* @param hi2c: I2C handle pointer
* @retval None
*/
void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
{
8001918: b580 push {r7, lr}
800191a: b08a sub sp, #40 ; 0x28
800191c: af00 add r7, sp, #0
800191e: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001920: f107 0314 add.w r3, r7, #20
8001924: 2200 movs r2, #0
8001926: 601a str r2, [r3, #0]
8001928: 605a str r2, [r3, #4]
800192a: 609a str r2, [r3, #8]
800192c: 60da str r2, [r3, #12]
800192e: 611a str r2, [r3, #16]
if(hi2c->Instance==I2C1)
8001930: 687b ldr r3, [r7, #4]
8001932: 681b ldr r3, [r3, #0]
8001934: 4a19 ldr r2, [pc, #100] ; (800199c <HAL_I2C_MspInit+0x84>)
8001936: 4293 cmp r3, r2
8001938: d12b bne.n 8001992 <HAL_I2C_MspInit+0x7a>
{
/* USER CODE BEGIN I2C1_MspInit 0 */
/* USER CODE END I2C1_MspInit 0 */
__HAL_RCC_GPIOB_CLK_ENABLE();
800193a: 2300 movs r3, #0
800193c: 613b str r3, [r7, #16]
800193e: 4b18 ldr r3, [pc, #96] ; (80019a0 <HAL_I2C_MspInit+0x88>)
8001940: 6b1b ldr r3, [r3, #48] ; 0x30
8001942: 4a17 ldr r2, [pc, #92] ; (80019a0 <HAL_I2C_MspInit+0x88>)
8001944: f043 0302 orr.w r3, r3, #2
8001948: 6313 str r3, [r2, #48] ; 0x30
800194a: 4b15 ldr r3, [pc, #84] ; (80019a0 <HAL_I2C_MspInit+0x88>)
800194c: 6b1b ldr r3, [r3, #48] ; 0x30
800194e: f003 0302 and.w r3, r3, #2
8001952: 613b str r3, [r7, #16]
8001954: 693b ldr r3, [r7, #16]
/**I2C1 GPIO Configuration
PB6 ------> I2C1_SCL
PB7 ------> I2C1_SDA
*/
GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
8001956: 23c0 movs r3, #192 ; 0xc0
8001958: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
800195a: 2312 movs r3, #18
800195c: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_PULLUP;
800195e: 2301 movs r3, #1
8001960: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001962: 2303 movs r3, #3
8001964: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;
8001966: 2304 movs r3, #4
8001968: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
800196a: f107 0314 add.w r3, r7, #20
800196e: 4619 mov r1, r3
8001970: 480c ldr r0, [pc, #48] ; (80019a4 <HAL_I2C_MspInit+0x8c>)
8001972: f001 faaf bl 8002ed4 <HAL_GPIO_Init>
/* Peripheral clock enable */
__HAL_RCC_I2C1_CLK_ENABLE();
8001976: 2300 movs r3, #0
8001978: 60fb str r3, [r7, #12]
800197a: 4b09 ldr r3, [pc, #36] ; (80019a0 <HAL_I2C_MspInit+0x88>)
800197c: 6c1b ldr r3, [r3, #64] ; 0x40
800197e: 4a08 ldr r2, [pc, #32] ; (80019a0 <HAL_I2C_MspInit+0x88>)
8001980: f443 1300 orr.w r3, r3, #2097152 ; 0x200000
8001984: 6413 str r3, [r2, #64] ; 0x40
8001986: 4b06 ldr r3, [pc, #24] ; (80019a0 <HAL_I2C_MspInit+0x88>)
8001988: 6c1b ldr r3, [r3, #64] ; 0x40
800198a: f403 1300 and.w r3, r3, #2097152 ; 0x200000
800198e: 60fb str r3, [r7, #12]
8001990: 68fb ldr r3, [r7, #12]
/* USER CODE BEGIN I2C1_MspInit 1 */
/* USER CODE END I2C1_MspInit 1 */
}
}
8001992: bf00 nop
8001994: 3728 adds r7, #40 ; 0x28
8001996: 46bd mov sp, r7
8001998: bd80 pop {r7, pc}
800199a: bf00 nop
800199c: 40005400 .word 0x40005400
80019a0: 40023800 .word 0x40023800
80019a4: 40020400 .word 0x40020400
080019a8 <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
80019a8: b580 push {r7, lr}
80019aa: b090 sub sp, #64 ; 0x40
80019ac: af00 add r7, sp, #0
80019ae: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
80019b0: f107 032c add.w r3, r7, #44 ; 0x2c
80019b4: 2200 movs r2, #0
80019b6: 601a str r2, [r3, #0]
80019b8: 605a str r2, [r3, #4]
80019ba: 609a str r2, [r3, #8]
80019bc: 60da str r2, [r3, #12]
80019be: 611a str r2, [r3, #16]
if(huart->Instance==USART1)
80019c0: 687b ldr r3, [r7, #4]
80019c2: 681b ldr r3, [r3, #0]
80019c4: 4a7c ldr r2, [pc, #496] ; (8001bb8 <HAL_UART_MspInit+0x210>)
80019c6: 4293 cmp r3, r2
80019c8: d135 bne.n 8001a36 <HAL_UART_MspInit+0x8e>
{
/* USER CODE BEGIN USART1_MspInit 0 */
/* USER CODE END USART1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_USART1_CLK_ENABLE();
80019ca: 2300 movs r3, #0
80019cc: 62bb str r3, [r7, #40] ; 0x28
80019ce: 4b7b ldr r3, [pc, #492] ; (8001bbc <HAL_UART_MspInit+0x214>)
80019d0: 6c5b ldr r3, [r3, #68] ; 0x44
80019d2: 4a7a ldr r2, [pc, #488] ; (8001bbc <HAL_UART_MspInit+0x214>)
80019d4: f043 0310 orr.w r3, r3, #16
80019d8: 6453 str r3, [r2, #68] ; 0x44
80019da: 4b78 ldr r3, [pc, #480] ; (8001bbc <HAL_UART_MspInit+0x214>)
80019dc: 6c5b ldr r3, [r3, #68] ; 0x44
80019de: f003 0310 and.w r3, r3, #16
80019e2: 62bb str r3, [r7, #40] ; 0x28
80019e4: 6abb ldr r3, [r7, #40] ; 0x28
__HAL_RCC_GPIOA_CLK_ENABLE();
80019e6: 2300 movs r3, #0
80019e8: 627b str r3, [r7, #36] ; 0x24
80019ea: 4b74 ldr r3, [pc, #464] ; (8001bbc <HAL_UART_MspInit+0x214>)
80019ec: 6b1b ldr r3, [r3, #48] ; 0x30
80019ee: 4a73 ldr r2, [pc, #460] ; (8001bbc <HAL_UART_MspInit+0x214>)
80019f0: f043 0301 orr.w r3, r3, #1
80019f4: 6313 str r3, [r2, #48] ; 0x30
80019f6: 4b71 ldr r3, [pc, #452] ; (8001bbc <HAL_UART_MspInit+0x214>)
80019f8: 6b1b ldr r3, [r3, #48] ; 0x30
80019fa: f003 0301 and.w r3, r3, #1
80019fe: 627b str r3, [r7, #36] ; 0x24
8001a00: 6a7b ldr r3, [r7, #36] ; 0x24
/**USART1 GPIO Configuration
PA10 ------> USART1_RX
PA15 ------> USART1_TX
*/
GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_15;
8001a02: f44f 4304 mov.w r3, #33792 ; 0x8400
8001a06: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001a08: 2302 movs r3, #2
8001a0a: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001a0c: 2300 movs r3, #0
8001a0e: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001a10: 2303 movs r3, #3
8001a12: 63bb str r3, [r7, #56] ; 0x38
GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
8001a14: 2307 movs r3, #7
8001a16: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001a18: f107 032c add.w r3, r7, #44 ; 0x2c
8001a1c: 4619 mov r1, r3
8001a1e: 4868 ldr r0, [pc, #416] ; (8001bc0 <HAL_UART_MspInit+0x218>)
8001a20: f001 fa58 bl 8002ed4 <HAL_GPIO_Init>
/* USART1 interrupt Init */
HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
8001a24: 2200 movs r2, #0
8001a26: 2100 movs r1, #0
8001a28: 2025 movs r0, #37 ; 0x25
8001a2a: f001 f98a bl 8002d42 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(USART1_IRQn);
8001a2e: 2025 movs r0, #37 ; 0x25
8001a30: f001 f9a3 bl 8002d7a <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN USART6_MspInit 1 */
/* USER CODE END USART6_MspInit 1 */
}
}
8001a34: e0bb b.n 8001bae <HAL_UART_MspInit+0x206>
else if(huart->Instance==USART2)
8001a36: 687b ldr r3, [r7, #4]
8001a38: 681b ldr r3, [r3, #0]
8001a3a: 4a62 ldr r2, [pc, #392] ; (8001bc4 <HAL_UART_MspInit+0x21c>)
8001a3c: 4293 cmp r3, r2
8001a3e: d12c bne.n 8001a9a <HAL_UART_MspInit+0xf2>
__HAL_RCC_USART2_CLK_ENABLE();
8001a40: 2300 movs r3, #0
8001a42: 623b str r3, [r7, #32]
8001a44: 4b5d ldr r3, [pc, #372] ; (8001bbc <HAL_UART_MspInit+0x214>)
8001a46: 6c1b ldr r3, [r3, #64] ; 0x40
8001a48: 4a5c ldr r2, [pc, #368] ; (8001bbc <HAL_UART_MspInit+0x214>)
8001a4a: f443 3300 orr.w r3, r3, #131072 ; 0x20000
8001a4e: 6413 str r3, [r2, #64] ; 0x40
8001a50: 4b5a ldr r3, [pc, #360] ; (8001bbc <HAL_UART_MspInit+0x214>)
8001a52: 6c1b ldr r3, [r3, #64] ; 0x40
8001a54: f403 3300 and.w r3, r3, #131072 ; 0x20000
8001a58: 623b str r3, [r7, #32]
8001a5a: 6a3b ldr r3, [r7, #32]
__HAL_RCC_GPIOA_CLK_ENABLE();
8001a5c: 2300 movs r3, #0
8001a5e: 61fb str r3, [r7, #28]
8001a60: 4b56 ldr r3, [pc, #344] ; (8001bbc <HAL_UART_MspInit+0x214>)
8001a62: 6b1b ldr r3, [r3, #48] ; 0x30
8001a64: 4a55 ldr r2, [pc, #340] ; (8001bbc <HAL_UART_MspInit+0x214>)
8001a66: f043 0301 orr.w r3, r3, #1
8001a6a: 6313 str r3, [r2, #48] ; 0x30
8001a6c: 4b53 ldr r3, [pc, #332] ; (8001bbc <HAL_UART_MspInit+0x214>)
8001a6e: 6b1b ldr r3, [r3, #48] ; 0x30
8001a70: f003 0301 and.w r3, r3, #1
8001a74: 61fb str r3, [r7, #28]
8001a76: 69fb ldr r3, [r7, #28]
GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3;
8001a78: 230c movs r3, #12
8001a7a: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001a7c: 2302 movs r3, #2
8001a7e: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001a80: 2300 movs r3, #0
8001a82: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001a84: 2303 movs r3, #3
8001a86: 63bb str r3, [r7, #56] ; 0x38
GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
8001a88: 2307 movs r3, #7
8001a8a: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001a8c: f107 032c add.w r3, r7, #44 ; 0x2c
8001a90: 4619 mov r1, r3
8001a92: 484b ldr r0, [pc, #300] ; (8001bc0 <HAL_UART_MspInit+0x218>)
8001a94: f001 fa1e bl 8002ed4 <HAL_GPIO_Init>
}
8001a98: e089 b.n 8001bae <HAL_UART_MspInit+0x206>
else if(huart->Instance==USART3)
8001a9a: 687b ldr r3, [r7, #4]
8001a9c: 681b ldr r3, [r3, #0]
8001a9e: 4a4a ldr r2, [pc, #296] ; (8001bc8 <HAL_UART_MspInit+0x220>)
8001aa0: 4293 cmp r3, r2
8001aa2: d153 bne.n 8001b4c <HAL_UART_MspInit+0x1a4>
__HAL_RCC_USART3_CLK_ENABLE();
8001aa4: 2300 movs r3, #0
8001aa6: 61bb str r3, [r7, #24]
8001aa8: 4b44 ldr r3, [pc, #272] ; (8001bbc <HAL_UART_MspInit+0x214>)
8001aaa: 6c1b ldr r3, [r3, #64] ; 0x40
8001aac: 4a43 ldr r2, [pc, #268] ; (8001bbc <HAL_UART_MspInit+0x214>)
8001aae: f443 2380 orr.w r3, r3, #262144 ; 0x40000
8001ab2: 6413 str r3, [r2, #64] ; 0x40
8001ab4: 4b41 ldr r3, [pc, #260] ; (8001bbc <HAL_UART_MspInit+0x214>)
8001ab6: 6c1b ldr r3, [r3, #64] ; 0x40
8001ab8: f403 2380 and.w r3, r3, #262144 ; 0x40000
8001abc: 61bb str r3, [r7, #24]
8001abe: 69bb ldr r3, [r7, #24]
__HAL_RCC_GPIOC_CLK_ENABLE();
8001ac0: 2300 movs r3, #0
8001ac2: 617b str r3, [r7, #20]
8001ac4: 4b3d ldr r3, [pc, #244] ; (8001bbc <HAL_UART_MspInit+0x214>)
8001ac6: 6b1b ldr r3, [r3, #48] ; 0x30
8001ac8: 4a3c ldr r2, [pc, #240] ; (8001bbc <HAL_UART_MspInit+0x214>)
8001aca: f043 0304 orr.w r3, r3, #4
8001ace: 6313 str r3, [r2, #48] ; 0x30
8001ad0: 4b3a ldr r3, [pc, #232] ; (8001bbc <HAL_UART_MspInit+0x214>)
8001ad2: 6b1b ldr r3, [r3, #48] ; 0x30
8001ad4: f003 0304 and.w r3, r3, #4
8001ad8: 617b str r3, [r7, #20]
8001ada: 697b ldr r3, [r7, #20]
__HAL_RCC_GPIOB_CLK_ENABLE();
8001adc: 2300 movs r3, #0
8001ade: 613b str r3, [r7, #16]
8001ae0: 4b36 ldr r3, [pc, #216] ; (8001bbc <HAL_UART_MspInit+0x214>)
8001ae2: 6b1b ldr r3, [r3, #48] ; 0x30
8001ae4: 4a35 ldr r2, [pc, #212] ; (8001bbc <HAL_UART_MspInit+0x214>)
8001ae6: f043 0302 orr.w r3, r3, #2
8001aea: 6313 str r3, [r2, #48] ; 0x30
8001aec: 4b33 ldr r3, [pc, #204] ; (8001bbc <HAL_UART_MspInit+0x214>)
8001aee: 6b1b ldr r3, [r3, #48] ; 0x30
8001af0: f003 0302 and.w r3, r3, #2
8001af4: 613b str r3, [r7, #16]
8001af6: 693b ldr r3, [r7, #16]
GPIO_InitStruct.Pin = GPIO_PIN_5;
8001af8: 2320 movs r3, #32
8001afa: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001afc: 2302 movs r3, #2
8001afe: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001b00: 2300 movs r3, #0
8001b02: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001b04: 2303 movs r3, #3
8001b06: 63bb str r3, [r7, #56] ; 0x38
GPIO_InitStruct.Alternate = GPIO_AF7_USART3;
8001b08: 2307 movs r3, #7
8001b0a: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8001b0c: f107 032c add.w r3, r7, #44 ; 0x2c
8001b10: 4619 mov r1, r3
8001b12: 482e ldr r0, [pc, #184] ; (8001bcc <HAL_UART_MspInit+0x224>)
8001b14: f001 f9de bl 8002ed4 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_10;
8001b18: f44f 6380 mov.w r3, #1024 ; 0x400
8001b1c: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001b1e: 2302 movs r3, #2
8001b20: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001b22: 2300 movs r3, #0
8001b24: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001b26: 2303 movs r3, #3
8001b28: 63bb str r3, [r7, #56] ; 0x38
GPIO_InitStruct.Alternate = GPIO_AF7_USART3;
8001b2a: 2307 movs r3, #7
8001b2c: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8001b2e: f107 032c add.w r3, r7, #44 ; 0x2c
8001b32: 4619 mov r1, r3
8001b34: 4826 ldr r0, [pc, #152] ; (8001bd0 <HAL_UART_MspInit+0x228>)
8001b36: f001 f9cd bl 8002ed4 <HAL_GPIO_Init>
HAL_NVIC_SetPriority(USART3_IRQn, 0, 0);
8001b3a: 2200 movs r2, #0
8001b3c: 2100 movs r1, #0
8001b3e: 2027 movs r0, #39 ; 0x27
8001b40: f001 f8ff bl 8002d42 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(USART3_IRQn);
8001b44: 2027 movs r0, #39 ; 0x27
8001b46: f001 f918 bl 8002d7a <HAL_NVIC_EnableIRQ>
}
8001b4a: e030 b.n 8001bae <HAL_UART_MspInit+0x206>
else if(huart->Instance==USART6)
8001b4c: 687b ldr r3, [r7, #4]
8001b4e: 681b ldr r3, [r3, #0]
8001b50: 4a20 ldr r2, [pc, #128] ; (8001bd4 <HAL_UART_MspInit+0x22c>)
8001b52: 4293 cmp r3, r2
8001b54: d12b bne.n 8001bae <HAL_UART_MspInit+0x206>
__HAL_RCC_USART6_CLK_ENABLE();
8001b56: 2300 movs r3, #0
8001b58: 60fb str r3, [r7, #12]
8001b5a: 4b18 ldr r3, [pc, #96] ; (8001bbc <HAL_UART_MspInit+0x214>)
8001b5c: 6c5b ldr r3, [r3, #68] ; 0x44
8001b5e: 4a17 ldr r2, [pc, #92] ; (8001bbc <HAL_UART_MspInit+0x214>)
8001b60: f043 0320 orr.w r3, r3, #32
8001b64: 6453 str r3, [r2, #68] ; 0x44
8001b66: 4b15 ldr r3, [pc, #84] ; (8001bbc <HAL_UART_MspInit+0x214>)
8001b68: 6c5b ldr r3, [r3, #68] ; 0x44
8001b6a: f003 0320 and.w r3, r3, #32
8001b6e: 60fb str r3, [r7, #12]
8001b70: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOC_CLK_ENABLE();
8001b72: 2300 movs r3, #0
8001b74: 60bb str r3, [r7, #8]
8001b76: 4b11 ldr r3, [pc, #68] ; (8001bbc <HAL_UART_MspInit+0x214>)
8001b78: 6b1b ldr r3, [r3, #48] ; 0x30
8001b7a: 4a10 ldr r2, [pc, #64] ; (8001bbc <HAL_UART_MspInit+0x214>)
8001b7c: f043 0304 orr.w r3, r3, #4
8001b80: 6313 str r3, [r2, #48] ; 0x30
8001b82: 4b0e ldr r3, [pc, #56] ; (8001bbc <HAL_UART_MspInit+0x214>)
8001b84: 6b1b ldr r3, [r3, #48] ; 0x30
8001b86: f003 0304 and.w r3, r3, #4
8001b8a: 60bb str r3, [r7, #8]
8001b8c: 68bb ldr r3, [r7, #8]
GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
8001b8e: 23c0 movs r3, #192 ; 0xc0
8001b90: 62fb str r3, [r7, #44] ; 0x2c
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001b92: 2302 movs r3, #2
8001b94: 633b str r3, [r7, #48] ; 0x30
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001b96: 2300 movs r3, #0
8001b98: 637b str r3, [r7, #52] ; 0x34
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001b9a: 2303 movs r3, #3
8001b9c: 63bb str r3, [r7, #56] ; 0x38
GPIO_InitStruct.Alternate = GPIO_AF8_USART6;
8001b9e: 2308 movs r3, #8
8001ba0: 63fb str r3, [r7, #60] ; 0x3c
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8001ba2: f107 032c add.w r3, r7, #44 ; 0x2c
8001ba6: 4619 mov r1, r3
8001ba8: 4808 ldr r0, [pc, #32] ; (8001bcc <HAL_UART_MspInit+0x224>)
8001baa: f001 f993 bl 8002ed4 <HAL_GPIO_Init>
}
8001bae: bf00 nop
8001bb0: 3740 adds r7, #64 ; 0x40
8001bb2: 46bd mov sp, r7
8001bb4: bd80 pop {r7, pc}
8001bb6: bf00 nop
8001bb8: 40011000 .word 0x40011000
8001bbc: 40023800 .word 0x40023800
8001bc0: 40020000 .word 0x40020000
8001bc4: 40004400 .word 0x40004400
8001bc8: 40004800 .word 0x40004800
8001bcc: 40020800 .word 0x40020800
8001bd0: 40020400 .word 0x40020400
8001bd4: 40011400 .word 0x40011400
08001bd8 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8001bd8: b480 push {r7}
8001bda: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8001bdc: e7fe b.n 8001bdc <NMI_Handler+0x4>
08001bde <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
8001bde: b480 push {r7}
8001be0: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8001be2: e7fe b.n 8001be2 <HardFault_Handler+0x4>
08001be4 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
8001be4: b480 push {r7}
8001be6: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
8001be8: e7fe b.n 8001be8 <MemManage_Handler+0x4>
08001bea <BusFault_Handler>:
/**
* @brief This function handles Pre-fetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
8001bea: b480 push {r7}
8001bec: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
8001bee: e7fe b.n 8001bee <BusFault_Handler+0x4>
08001bf0 <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
8001bf0: b480 push {r7}
8001bf2: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
8001bf4: e7fe b.n 8001bf4 <UsageFault_Handler+0x4>
08001bf6 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
8001bf6: b480 push {r7}
8001bf8: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
8001bfa: bf00 nop
8001bfc: 46bd mov sp, r7
8001bfe: f85d 7b04 ldr.w r7, [sp], #4
8001c02: 4770 bx lr
08001c04 <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
8001c04: b480 push {r7}
8001c06: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
8001c08: bf00 nop
8001c0a: 46bd mov sp, r7
8001c0c: f85d 7b04 ldr.w r7, [sp], #4
8001c10: 4770 bx lr
08001c12 <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
8001c12: b480 push {r7}
8001c14: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
8001c16: bf00 nop
8001c18: 46bd mov sp, r7
8001c1a: f85d 7b04 ldr.w r7, [sp], #4
8001c1e: 4770 bx lr
08001c20 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
8001c20: b580 push {r7, lr}
8001c22: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
8001c24: f000 f90c bl 8001e40 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
8001c28: bf00 nop
8001c2a: bd80 pop {r7, pc}
08001c2c <CAN1_RX0_IRQHandler>:
/**
* @brief This function handles CAN1 RX0 interrupts.
*/
void CAN1_RX0_IRQHandler(void)
{
8001c2c: b580 push {r7, lr}
8001c2e: af00 add r7, sp, #0
/* USER CODE BEGIN CAN1_RX0_IRQn 0 */
/* USER CODE END CAN1_RX0_IRQn 0 */
HAL_CAN_IRQHandler(&hcan1);
8001c30: 4802 ldr r0, [pc, #8] ; (8001c3c <CAN1_RX0_IRQHandler+0x10>)
8001c32: f000 fd7c bl 800272e <HAL_CAN_IRQHandler>
/* USER CODE BEGIN CAN1_RX0_IRQn 1 */
/* USER CODE END CAN1_RX0_IRQn 1 */
}
8001c36: bf00 nop
8001c38: bd80 pop {r7, pc}
8001c3a: bf00 nop
8001c3c: 20000334 .word 0x20000334
08001c40 <CAN1_RX1_IRQHandler>:
/**
* @brief This function handles CAN1 RX1 interrupt.
*/
void CAN1_RX1_IRQHandler(void)
{
8001c40: b580 push {r7, lr}
8001c42: af00 add r7, sp, #0
/* USER CODE BEGIN CAN1_RX1_IRQn 0 */
/* USER CODE END CAN1_RX1_IRQn 0 */
HAL_CAN_IRQHandler(&hcan1);
8001c44: 4802 ldr r0, [pc, #8] ; (8001c50 <CAN1_RX1_IRQHandler+0x10>)
8001c46: f000 fd72 bl 800272e <HAL_CAN_IRQHandler>
/* USER CODE BEGIN CAN1_RX1_IRQn 1 */
/* USER CODE END CAN1_RX1_IRQn 1 */
}
8001c4a: bf00 nop
8001c4c: bd80 pop {r7, pc}
8001c4e: bf00 nop
8001c50: 20000334 .word 0x20000334
08001c54 <USART1_IRQHandler>:
/**
* @brief This function handles USART1 global interrupt.
*/
void USART1_IRQHandler(void)
{
8001c54: b580 push {r7, lr}
8001c56: af00 add r7, sp, #0
/* USER CODE BEGIN USART1_IRQn 0 */
/* USER CODE END USART1_IRQn 0 */
HAL_UART_IRQHandler(&huart1);
8001c58: 4802 ldr r0, [pc, #8] ; (8001c64 <USART1_IRQHandler+0x10>)
8001c5a: f002 fa45 bl 80040e8 <HAL_UART_IRQHandler>
/* USER CODE BEGIN USART1_IRQn 1 */
/* USER CODE END USART1_IRQn 1 */
}
8001c5e: bf00 nop
8001c60: bd80 pop {r7, pc}
8001c62: bf00 nop
8001c64: 20000268 .word 0x20000268
08001c68 <USART3_IRQHandler>:
/**
* @brief This function handles USART3 global interrupt.
*/
void USART3_IRQHandler(void)
{
8001c68: b580 push {r7, lr}
8001c6a: af00 add r7, sp, #0
/* USER CODE BEGIN USART3_IRQn 0 */
/* USER CODE END USART3_IRQn 0 */
HAL_UART_IRQHandler(&huart3);
8001c6c: 4802 ldr r0, [pc, #8] ; (8001c78 <USART3_IRQHandler+0x10>)
8001c6e: f002 fa3b bl 80040e8 <HAL_UART_IRQHandler>
/* USER CODE BEGIN USART3_IRQn 1 */
/* USER CODE END USART3_IRQn 1 */
}
8001c72: bf00 nop
8001c74: bd80 pop {r7, pc}
8001c76: bf00 nop
8001c78: 200001a8 .word 0x200001a8
08001c7c <CAN2_RX0_IRQHandler>:
/**
* @brief This function handles CAN2 RX0 interrupts.
*/
void CAN2_RX0_IRQHandler(void)
{
8001c7c: b580 push {r7, lr}
8001c7e: af00 add r7, sp, #0
/* USER CODE BEGIN CAN2_RX0_IRQn 0 */
/* USER CODE END CAN2_RX0_IRQn 0 */
HAL_CAN_IRQHandler(&hcan2);
8001c80: 4802 ldr r0, [pc, #8] ; (8001c8c <CAN2_RX0_IRQHandler+0x10>)
8001c82: f000 fd54 bl 800272e <HAL_CAN_IRQHandler>
/* USER CODE BEGIN CAN2_RX0_IRQn 1 */
/* USER CODE END CAN2_RX0_IRQn 1 */
}
8001c86: bf00 nop
8001c88: bd80 pop {r7, pc}
8001c8a: bf00 nop
8001c8c: 20000240 .word 0x20000240
08001c90 <CAN2_RX1_IRQHandler>:
/**
* @brief This function handles CAN2 RX1 interrupt.
*/
void CAN2_RX1_IRQHandler(void)
{
8001c90: b580 push {r7, lr}
8001c92: af00 add r7, sp, #0
/* USER CODE BEGIN CAN2_RX1_IRQn 0 */
/* USER CODE END CAN2_RX1_IRQn 0 */
HAL_CAN_IRQHandler(&hcan2);
8001c94: 4802 ldr r0, [pc, #8] ; (8001ca0 <CAN2_RX1_IRQHandler+0x10>)
8001c96: f000 fd4a bl 800272e <HAL_CAN_IRQHandler>
/* USER CODE BEGIN CAN2_RX1_IRQn 1 */
/* USER CODE END CAN2_RX1_IRQn 1 */
}
8001c9a: bf00 nop
8001c9c: bd80 pop {r7, pc}
8001c9e: bf00 nop
8001ca0: 20000240 .word 0x20000240
08001ca4 <CAN2_SCE_IRQHandler>:
/**
* @brief This function handles CAN2 SCE interrupt.
*/
void CAN2_SCE_IRQHandler(void)
{
8001ca4: b580 push {r7, lr}
8001ca6: af00 add r7, sp, #0
/* USER CODE BEGIN CAN2_SCE_IRQn 0 */
/* USER CODE END CAN2_SCE_IRQn 0 */
HAL_CAN_IRQHandler(&hcan2);
8001ca8: 4802 ldr r0, [pc, #8] ; (8001cb4 <CAN2_SCE_IRQHandler+0x10>)
8001caa: f000 fd40 bl 800272e <HAL_CAN_IRQHandler>
/* USER CODE BEGIN CAN2_SCE_IRQn 1 */
/* USER CODE END CAN2_SCE_IRQn 1 */
}
8001cae: bf00 nop
8001cb0: bd80 pop {r7, pc}
8001cb2: bf00 nop
8001cb4: 20000240 .word 0x20000240
08001cb8 <_sbrk>:
*
* @param incr Memory size
* @return Pointer to allocated memory
*/
void *_sbrk(ptrdiff_t incr)
{
8001cb8: b580 push {r7, lr}
8001cba: b086 sub sp, #24
8001cbc: af00 add r7, sp, #0
8001cbe: 6078 str r0, [r7, #4]
extern uint8_t _end; /* Symbol defined in the linker script */
extern uint8_t _estack; /* Symbol defined in the linker script */
extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
8001cc0: 4a14 ldr r2, [pc, #80] ; (8001d14 <_sbrk+0x5c>)
8001cc2: 4b15 ldr r3, [pc, #84] ; (8001d18 <_sbrk+0x60>)
8001cc4: 1ad3 subs r3, r2, r3
8001cc6: 617b str r3, [r7, #20]
const uint8_t *max_heap = (uint8_t *)stack_limit;
8001cc8: 697b ldr r3, [r7, #20]
8001cca: 613b str r3, [r7, #16]
uint8_t *prev_heap_end;
/* Initialize heap end at first call */
if (NULL == __sbrk_heap_end)
8001ccc: 4b13 ldr r3, [pc, #76] ; (8001d1c <_sbrk+0x64>)
8001cce: 681b ldr r3, [r3, #0]
8001cd0: 2b00 cmp r3, #0
8001cd2: d102 bne.n 8001cda <_sbrk+0x22>
{
__sbrk_heap_end = &_end;
8001cd4: 4b11 ldr r3, [pc, #68] ; (8001d1c <_sbrk+0x64>)
8001cd6: 4a12 ldr r2, [pc, #72] ; (8001d20 <_sbrk+0x68>)
8001cd8: 601a str r2, [r3, #0]
}
/* Protect heap from growing into the reserved MSP stack */
if (__sbrk_heap_end + incr > max_heap)
8001cda: 4b10 ldr r3, [pc, #64] ; (8001d1c <_sbrk+0x64>)
8001cdc: 681a ldr r2, [r3, #0]
8001cde: 687b ldr r3, [r7, #4]
8001ce0: 4413 add r3, r2
8001ce2: 693a ldr r2, [r7, #16]
8001ce4: 429a cmp r2, r3
8001ce6: d207 bcs.n 8001cf8 <_sbrk+0x40>
{
errno = ENOMEM;
8001ce8: f003 f8be bl 8004e68 <__errno>
8001cec: 4603 mov r3, r0
8001cee: 220c movs r2, #12
8001cf0: 601a str r2, [r3, #0]
return (void *)-1;
8001cf2: f04f 33ff mov.w r3, #4294967295
8001cf6: e009 b.n 8001d0c <_sbrk+0x54>
}
prev_heap_end = __sbrk_heap_end;
8001cf8: 4b08 ldr r3, [pc, #32] ; (8001d1c <_sbrk+0x64>)
8001cfa: 681b ldr r3, [r3, #0]
8001cfc: 60fb str r3, [r7, #12]
__sbrk_heap_end += incr;
8001cfe: 4b07 ldr r3, [pc, #28] ; (8001d1c <_sbrk+0x64>)
8001d00: 681a ldr r2, [r3, #0]
8001d02: 687b ldr r3, [r7, #4]
8001d04: 4413 add r3, r2
8001d06: 4a05 ldr r2, [pc, #20] ; (8001d1c <_sbrk+0x64>)
8001d08: 6013 str r3, [r2, #0]
return (void *)prev_heap_end;
8001d0a: 68fb ldr r3, [r7, #12]
}
8001d0c: 4618 mov r0, r3
8001d0e: 3718 adds r7, #24
8001d10: 46bd mov sp, r7
8001d12: bd80 pop {r7, pc}
8001d14: 20040000 .word 0x20040000
8001d18: 00000400 .word 0x00000400
8001d1c: 20000164 .word 0x20000164
8001d20: 20000370 .word 0x20000370
08001d24 <SystemInit>:
* configuration.
* @param None
* @retval None
*/
void SystemInit(void)
{
8001d24: b480 push {r7}
8001d26: af00 add r7, sp, #0
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
8001d28: 4b06 ldr r3, [pc, #24] ; (8001d44 <SystemInit+0x20>)
8001d2a: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
8001d2e: 4a05 ldr r2, [pc, #20] ; (8001d44 <SystemInit+0x20>)
8001d30: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
8001d34: f8c2 3088 str.w r3, [r2, #136] ; 0x88
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
}
8001d38: bf00 nop
8001d3a: 46bd mov sp, r7
8001d3c: f85d 7b04 ldr.w r7, [sp], #4
8001d40: 4770 bx lr
8001d42: bf00 nop
8001d44: e000ed00 .word 0xe000ed00
08001d48 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
8001d48: f8df d034 ldr.w sp, [pc, #52] ; 8001d80 <LoopFillZerobss+0x12>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
8001d4c: 480d ldr r0, [pc, #52] ; (8001d84 <LoopFillZerobss+0x16>)
ldr r1, =_edata
8001d4e: 490e ldr r1, [pc, #56] ; (8001d88 <LoopFillZerobss+0x1a>)
ldr r2, =_sidata
8001d50: 4a0e ldr r2, [pc, #56] ; (8001d8c <LoopFillZerobss+0x1e>)
movs r3, #0
8001d52: 2300 movs r3, #0
b LoopCopyDataInit
8001d54: e002 b.n 8001d5c <LoopCopyDataInit>
08001d56 <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
8001d56: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
8001d58: 50c4 str r4, [r0, r3]
adds r3, r3, #4
8001d5a: 3304 adds r3, #4
08001d5c <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
8001d5c: 18c4 adds r4, r0, r3
cmp r4, r1
8001d5e: 428c cmp r4, r1
bcc CopyDataInit
8001d60: d3f9 bcc.n 8001d56 <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
8001d62: 4a0b ldr r2, [pc, #44] ; (8001d90 <LoopFillZerobss+0x22>)
ldr r4, =_ebss
8001d64: 4c0b ldr r4, [pc, #44] ; (8001d94 <LoopFillZerobss+0x26>)
movs r3, #0
8001d66: 2300 movs r3, #0
b LoopFillZerobss
8001d68: e001 b.n 8001d6e <LoopFillZerobss>
08001d6a <FillZerobss>:
FillZerobss:
str r3, [r2]
8001d6a: 6013 str r3, [r2, #0]
adds r2, r2, #4
8001d6c: 3204 adds r2, #4
08001d6e <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
8001d6e: 42a2 cmp r2, r4
bcc FillZerobss
8001d70: d3fb bcc.n 8001d6a <FillZerobss>
/* Call the clock system intitialization function.*/
bl SystemInit
8001d72: f7ff ffd7 bl 8001d24 <SystemInit>
/* Call static constructors */
bl __libc_init_array
8001d76: f003 f87d bl 8004e74 <__libc_init_array>
/* Call the application's entry point.*/
bl main
8001d7a: f7ff fa67 bl 800124c <main>
bx lr
8001d7e: 4770 bx lr
ldr sp, =_estack /* set stack pointer */
8001d80: 20040000 .word 0x20040000
ldr r0, =_sdata
8001d84: 20000000 .word 0x20000000
ldr r1, =_edata
8001d88: 20000074 .word 0x20000074
ldr r2, =_sidata
8001d8c: 08005310 .word 0x08005310
ldr r2, =_sbss
8001d90: 20000074 .word 0x20000074
ldr r4, =_ebss
8001d94: 20000370 .word 0x20000370
08001d98 <ADC_IRQHandler>:
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8001d98: e7fe b.n 8001d98 <ADC_IRQHandler>
...
08001d9c <HAL_Init>:
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
8001d9c: b580 push {r7, lr}
8001d9e: af00 add r7, sp, #0
/* Configure Flash prefetch, Instruction cache, Data cache */
#if (INSTRUCTION_CACHE_ENABLE != 0U)
__HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
8001da0: 4b0e ldr r3, [pc, #56] ; (8001ddc <HAL_Init+0x40>)
8001da2: 681b ldr r3, [r3, #0]
8001da4: 4a0d ldr r2, [pc, #52] ; (8001ddc <HAL_Init+0x40>)
8001da6: f443 7300 orr.w r3, r3, #512 ; 0x200
8001daa: 6013 str r3, [r2, #0]
#endif /* INSTRUCTION_CACHE_ENABLE */
#if (DATA_CACHE_ENABLE != 0U)
__HAL_FLASH_DATA_CACHE_ENABLE();
8001dac: 4b0b ldr r3, [pc, #44] ; (8001ddc <HAL_Init+0x40>)
8001dae: 681b ldr r3, [r3, #0]
8001db0: 4a0a ldr r2, [pc, #40] ; (8001ddc <HAL_Init+0x40>)
8001db2: f443 6380 orr.w r3, r3, #1024 ; 0x400
8001db6: 6013 str r3, [r2, #0]
#endif /* DATA_CACHE_ENABLE */
#if (PREFETCH_ENABLE != 0U)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
8001db8: 4b08 ldr r3, [pc, #32] ; (8001ddc <HAL_Init+0x40>)
8001dba: 681b ldr r3, [r3, #0]
8001dbc: 4a07 ldr r2, [pc, #28] ; (8001ddc <HAL_Init+0x40>)
8001dbe: f443 7380 orr.w r3, r3, #256 ; 0x100
8001dc2: 6013 str r3, [r2, #0]
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
8001dc4: 2003 movs r0, #3
8001dc6: f000 ffb1 bl 8002d2c <HAL_NVIC_SetPriorityGrouping>
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
8001dca: 2000 movs r0, #0
8001dcc: f000 f808 bl 8001de0 <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
8001dd0: f7ff fcac bl 800172c <HAL_MspInit>
/* Return function status */
return HAL_OK;
8001dd4: 2300 movs r3, #0
}
8001dd6: 4618 mov r0, r3
8001dd8: bd80 pop {r7, pc}
8001dda: bf00 nop
8001ddc: 40023c00 .word 0x40023c00
08001de0 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8001de0: b580 push {r7, lr}
8001de2: b082 sub sp, #8
8001de4: af00 add r7, sp, #0
8001de6: 6078 str r0, [r7, #4]
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
8001de8: 4b12 ldr r3, [pc, #72] ; (8001e34 <HAL_InitTick+0x54>)
8001dea: 681a ldr r2, [r3, #0]
8001dec: 4b12 ldr r3, [pc, #72] ; (8001e38 <HAL_InitTick+0x58>)
8001dee: 781b ldrb r3, [r3, #0]
8001df0: 4619 mov r1, r3
8001df2: f44f 737a mov.w r3, #1000 ; 0x3e8
8001df6: fbb3 f3f1 udiv r3, r3, r1
8001dfa: fbb2 f3f3 udiv r3, r2, r3
8001dfe: 4618 mov r0, r3
8001e00: f000 ffc9 bl 8002d96 <HAL_SYSTICK_Config>
8001e04: 4603 mov r3, r0
8001e06: 2b00 cmp r3, #0
8001e08: d001 beq.n 8001e0e <HAL_InitTick+0x2e>
{
return HAL_ERROR;
8001e0a: 2301 movs r3, #1
8001e0c: e00e b.n 8001e2c <HAL_InitTick+0x4c>
}
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8001e0e: 687b ldr r3, [r7, #4]
8001e10: 2b0f cmp r3, #15
8001e12: d80a bhi.n 8001e2a <HAL_InitTick+0x4a>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
8001e14: 2200 movs r2, #0
8001e16: 6879 ldr r1, [r7, #4]
8001e18: f04f 30ff mov.w r0, #4294967295
8001e1c: f000 ff91 bl 8002d42 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8001e20: 4a06 ldr r2, [pc, #24] ; (8001e3c <HAL_InitTick+0x5c>)
8001e22: 687b ldr r3, [r7, #4]
8001e24: 6013 str r3, [r2, #0]
{
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
8001e26: 2300 movs r3, #0
8001e28: e000 b.n 8001e2c <HAL_InitTick+0x4c>
return HAL_ERROR;
8001e2a: 2301 movs r3, #1
}
8001e2c: 4618 mov r0, r3
8001e2e: 3708 adds r7, #8
8001e30: 46bd mov sp, r7
8001e32: bd80 pop {r7, pc}
8001e34: 20000004 .word 0x20000004
8001e38: 2000000c .word 0x2000000c
8001e3c: 20000008 .word 0x20000008
08001e40 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8001e40: b480 push {r7}
8001e42: af00 add r7, sp, #0
uwTick += uwTickFreq;
8001e44: 4b06 ldr r3, [pc, #24] ; (8001e60 <HAL_IncTick+0x20>)
8001e46: 781b ldrb r3, [r3, #0]
8001e48: 461a mov r2, r3
8001e4a: 4b06 ldr r3, [pc, #24] ; (8001e64 <HAL_IncTick+0x24>)
8001e4c: 681b ldr r3, [r3, #0]
8001e4e: 4413 add r3, r2
8001e50: 4a04 ldr r2, [pc, #16] ; (8001e64 <HAL_IncTick+0x24>)
8001e52: 6013 str r3, [r2, #0]
}
8001e54: bf00 nop
8001e56: 46bd mov sp, r7
8001e58: f85d 7b04 ldr.w r7, [sp], #4
8001e5c: 4770 bx lr
8001e5e: bf00 nop
8001e60: 2000000c .word 0x2000000c
8001e64: 2000035c .word 0x2000035c
08001e68 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
8001e68: b480 push {r7}
8001e6a: af00 add r7, sp, #0
return uwTick;
8001e6c: 4b03 ldr r3, [pc, #12] ; (8001e7c <HAL_GetTick+0x14>)
8001e6e: 681b ldr r3, [r3, #0]
}
8001e70: 4618 mov r0, r3
8001e72: 46bd mov sp, r7
8001e74: f85d 7b04 ldr.w r7, [sp], #4
8001e78: 4770 bx lr
8001e7a: bf00 nop
8001e7c: 2000035c .word 0x2000035c
08001e80 <HAL_Delay>:
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
8001e80: b580 push {r7, lr}
8001e82: b084 sub sp, #16
8001e84: af00 add r7, sp, #0
8001e86: 6078 str r0, [r7, #4]
uint32_t tickstart = HAL_GetTick();
8001e88: f7ff ffee bl 8001e68 <HAL_GetTick>
8001e8c: 60b8 str r0, [r7, #8]
uint32_t wait = Delay;
8001e8e: 687b ldr r3, [r7, #4]
8001e90: 60fb str r3, [r7, #12]
/* Add a freq to guarantee minimum wait */
if (wait < HAL_MAX_DELAY)
8001e92: 68fb ldr r3, [r7, #12]
8001e94: f1b3 3fff cmp.w r3, #4294967295
8001e98: d005 beq.n 8001ea6 <HAL_Delay+0x26>
{
wait += (uint32_t)(uwTickFreq);
8001e9a: 4b0a ldr r3, [pc, #40] ; (8001ec4 <HAL_Delay+0x44>)
8001e9c: 781b ldrb r3, [r3, #0]
8001e9e: 461a mov r2, r3
8001ea0: 68fb ldr r3, [r7, #12]
8001ea2: 4413 add r3, r2
8001ea4: 60fb str r3, [r7, #12]
}
while((HAL_GetTick() - tickstart) < wait)
8001ea6: bf00 nop
8001ea8: f7ff ffde bl 8001e68 <HAL_GetTick>
8001eac: 4602 mov r2, r0
8001eae: 68bb ldr r3, [r7, #8]
8001eb0: 1ad3 subs r3, r2, r3
8001eb2: 68fa ldr r2, [r7, #12]
8001eb4: 429a cmp r2, r3
8001eb6: d8f7 bhi.n 8001ea8 <HAL_Delay+0x28>
{
}
}
8001eb8: bf00 nop
8001eba: bf00 nop
8001ebc: 3710 adds r7, #16
8001ebe: 46bd mov sp, r7
8001ec0: bd80 pop {r7, pc}
8001ec2: bf00 nop
8001ec4: 2000000c .word 0x2000000c
08001ec8 <HAL_CAN_Init>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan)
{
8001ec8: b580 push {r7, lr}
8001eca: b084 sub sp, #16
8001ecc: af00 add r7, sp, #0
8001ece: 6078 str r0, [r7, #4]
uint32_t tickstart;
/* Check CAN handle */
if (hcan == NULL)
8001ed0: 687b ldr r3, [r7, #4]
8001ed2: 2b00 cmp r3, #0
8001ed4: d101 bne.n 8001eda <HAL_CAN_Init+0x12>
{
return HAL_ERROR;
8001ed6: 2301 movs r3, #1
8001ed8: e0ed b.n 80020b6 <HAL_CAN_Init+0x1ee>
/* Init the low level hardware: CLOCK, NVIC */
hcan->MspInitCallback(hcan);
}
#else
if (hcan->State == HAL_CAN_STATE_RESET)
8001eda: 687b ldr r3, [r7, #4]
8001edc: f893 3020 ldrb.w r3, [r3, #32]
8001ee0: b2db uxtb r3, r3
8001ee2: 2b00 cmp r3, #0
8001ee4: d102 bne.n 8001eec <HAL_CAN_Init+0x24>
{
/* Init the low level hardware: CLOCK, NVIC */
HAL_CAN_MspInit(hcan);
8001ee6: 6878 ldr r0, [r7, #4]
8001ee8: f7ff fc4c bl 8001784 <HAL_CAN_MspInit>
}
#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
/* Request initialisation */
SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
8001eec: 687b ldr r3, [r7, #4]
8001eee: 681b ldr r3, [r3, #0]
8001ef0: 681a ldr r2, [r3, #0]
8001ef2: 687b ldr r3, [r7, #4]
8001ef4: 681b ldr r3, [r3, #0]
8001ef6: f042 0201 orr.w r2, r2, #1
8001efa: 601a str r2, [r3, #0]
/* Get tick */
tickstart = HAL_GetTick();
8001efc: f7ff ffb4 bl 8001e68 <HAL_GetTick>
8001f00: 60f8 str r0, [r7, #12]
/* Wait initialisation acknowledge */
while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U)
8001f02: e012 b.n 8001f2a <HAL_CAN_Init+0x62>
{
if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
8001f04: f7ff ffb0 bl 8001e68 <HAL_GetTick>
8001f08: 4602 mov r2, r0
8001f0a: 68fb ldr r3, [r7, #12]
8001f0c: 1ad3 subs r3, r2, r3
8001f0e: 2b0a cmp r3, #10
8001f10: d90b bls.n 8001f2a <HAL_CAN_Init+0x62>
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
8001f12: 687b ldr r3, [r7, #4]
8001f14: 6a5b ldr r3, [r3, #36] ; 0x24
8001f16: f443 3200 orr.w r2, r3, #131072 ; 0x20000
8001f1a: 687b ldr r3, [r7, #4]
8001f1c: 625a str r2, [r3, #36] ; 0x24
/* Change CAN state */
hcan->State = HAL_CAN_STATE_ERROR;
8001f1e: 687b ldr r3, [r7, #4]
8001f20: 2205 movs r2, #5
8001f22: f883 2020 strb.w r2, [r3, #32]
return HAL_ERROR;
8001f26: 2301 movs r3, #1
8001f28: e0c5 b.n 80020b6 <HAL_CAN_Init+0x1ee>
while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U)
8001f2a: 687b ldr r3, [r7, #4]
8001f2c: 681b ldr r3, [r3, #0]
8001f2e: 685b ldr r3, [r3, #4]
8001f30: f003 0301 and.w r3, r3, #1
8001f34: 2b00 cmp r3, #0
8001f36: d0e5 beq.n 8001f04 <HAL_CAN_Init+0x3c>
}
}
/* Exit from sleep mode */
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
8001f38: 687b ldr r3, [r7, #4]
8001f3a: 681b ldr r3, [r3, #0]
8001f3c: 681a ldr r2, [r3, #0]
8001f3e: 687b ldr r3, [r7, #4]
8001f40: 681b ldr r3, [r3, #0]
8001f42: f022 0202 bic.w r2, r2, #2
8001f46: 601a str r2, [r3, #0]
/* Get tick */
tickstart = HAL_GetTick();
8001f48: f7ff ff8e bl 8001e68 <HAL_GetTick>
8001f4c: 60f8 str r0, [r7, #12]
/* Check Sleep mode leave acknowledge */
while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
8001f4e: e012 b.n 8001f76 <HAL_CAN_Init+0xae>
{
if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
8001f50: f7ff ff8a bl 8001e68 <HAL_GetTick>
8001f54: 4602 mov r2, r0
8001f56: 68fb ldr r3, [r7, #12]
8001f58: 1ad3 subs r3, r2, r3
8001f5a: 2b0a cmp r3, #10
8001f5c: d90b bls.n 8001f76 <HAL_CAN_Init+0xae>
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
8001f5e: 687b ldr r3, [r7, #4]
8001f60: 6a5b ldr r3, [r3, #36] ; 0x24
8001f62: f443 3200 orr.w r2, r3, #131072 ; 0x20000
8001f66: 687b ldr r3, [r7, #4]
8001f68: 625a str r2, [r3, #36] ; 0x24
/* Change CAN state */
hcan->State = HAL_CAN_STATE_ERROR;
8001f6a: 687b ldr r3, [r7, #4]
8001f6c: 2205 movs r2, #5
8001f6e: f883 2020 strb.w r2, [r3, #32]
return HAL_ERROR;
8001f72: 2301 movs r3, #1
8001f74: e09f b.n 80020b6 <HAL_CAN_Init+0x1ee>
while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
8001f76: 687b ldr r3, [r7, #4]
8001f78: 681b ldr r3, [r3, #0]
8001f7a: 685b ldr r3, [r3, #4]
8001f7c: f003 0302 and.w r3, r3, #2
8001f80: 2b00 cmp r3, #0
8001f82: d1e5 bne.n 8001f50 <HAL_CAN_Init+0x88>
}
}
/* Set the time triggered communication mode */
if (hcan->Init.TimeTriggeredMode == ENABLE)
8001f84: 687b ldr r3, [r7, #4]
8001f86: 7e1b ldrb r3, [r3, #24]
8001f88: 2b01 cmp r3, #1
8001f8a: d108 bne.n 8001f9e <HAL_CAN_Init+0xd6>
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
8001f8c: 687b ldr r3, [r7, #4]
8001f8e: 681b ldr r3, [r3, #0]
8001f90: 681a ldr r2, [r3, #0]
8001f92: 687b ldr r3, [r7, #4]
8001f94: 681b ldr r3, [r3, #0]
8001f96: f042 0280 orr.w r2, r2, #128 ; 0x80
8001f9a: 601a str r2, [r3, #0]
8001f9c: e007 b.n 8001fae <HAL_CAN_Init+0xe6>
}
else
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
8001f9e: 687b ldr r3, [r7, #4]
8001fa0: 681b ldr r3, [r3, #0]
8001fa2: 681a ldr r2, [r3, #0]
8001fa4: 687b ldr r3, [r7, #4]
8001fa6: 681b ldr r3, [r3, #0]
8001fa8: f022 0280 bic.w r2, r2, #128 ; 0x80
8001fac: 601a str r2, [r3, #0]
}
/* Set the automatic bus-off management */
if (hcan->Init.AutoBusOff == ENABLE)
8001fae: 687b ldr r3, [r7, #4]
8001fb0: 7e5b ldrb r3, [r3, #25]
8001fb2: 2b01 cmp r3, #1
8001fb4: d108 bne.n 8001fc8 <HAL_CAN_Init+0x100>
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
8001fb6: 687b ldr r3, [r7, #4]
8001fb8: 681b ldr r3, [r3, #0]
8001fba: 681a ldr r2, [r3, #0]
8001fbc: 687b ldr r3, [r7, #4]
8001fbe: 681b ldr r3, [r3, #0]
8001fc0: f042 0240 orr.w r2, r2, #64 ; 0x40
8001fc4: 601a str r2, [r3, #0]
8001fc6: e007 b.n 8001fd8 <HAL_CAN_Init+0x110>
}
else
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
8001fc8: 687b ldr r3, [r7, #4]
8001fca: 681b ldr r3, [r3, #0]
8001fcc: 681a ldr r2, [r3, #0]
8001fce: 687b ldr r3, [r7, #4]
8001fd0: 681b ldr r3, [r3, #0]
8001fd2: f022 0240 bic.w r2, r2, #64 ; 0x40
8001fd6: 601a str r2, [r3, #0]
}
/* Set the automatic wake-up mode */
if (hcan->Init.AutoWakeUp == ENABLE)
8001fd8: 687b ldr r3, [r7, #4]
8001fda: 7e9b ldrb r3, [r3, #26]
8001fdc: 2b01 cmp r3, #1
8001fde: d108 bne.n 8001ff2 <HAL_CAN_Init+0x12a>
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
8001fe0: 687b ldr r3, [r7, #4]
8001fe2: 681b ldr r3, [r3, #0]
8001fe4: 681a ldr r2, [r3, #0]
8001fe6: 687b ldr r3, [r7, #4]
8001fe8: 681b ldr r3, [r3, #0]
8001fea: f042 0220 orr.w r2, r2, #32
8001fee: 601a str r2, [r3, #0]
8001ff0: e007 b.n 8002002 <HAL_CAN_Init+0x13a>
}
else
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
8001ff2: 687b ldr r3, [r7, #4]
8001ff4: 681b ldr r3, [r3, #0]
8001ff6: 681a ldr r2, [r3, #0]
8001ff8: 687b ldr r3, [r7, #4]
8001ffa: 681b ldr r3, [r3, #0]
8001ffc: f022 0220 bic.w r2, r2, #32
8002000: 601a str r2, [r3, #0]
}
/* Set the automatic retransmission */
if (hcan->Init.AutoRetransmission == ENABLE)
8002002: 687b ldr r3, [r7, #4]
8002004: 7edb ldrb r3, [r3, #27]
8002006: 2b01 cmp r3, #1
8002008: d108 bne.n 800201c <HAL_CAN_Init+0x154>
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART);
800200a: 687b ldr r3, [r7, #4]
800200c: 681b ldr r3, [r3, #0]
800200e: 681a ldr r2, [r3, #0]
8002010: 687b ldr r3, [r7, #4]
8002012: 681b ldr r3, [r3, #0]
8002014: f022 0210 bic.w r2, r2, #16
8002018: 601a str r2, [r3, #0]
800201a: e007 b.n 800202c <HAL_CAN_Init+0x164>
}
else
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_NART);
800201c: 687b ldr r3, [r7, #4]
800201e: 681b ldr r3, [r3, #0]
8002020: 681a ldr r2, [r3, #0]
8002022: 687b ldr r3, [r7, #4]
8002024: 681b ldr r3, [r3, #0]
8002026: f042 0210 orr.w r2, r2, #16
800202a: 601a str r2, [r3, #0]
}
/* Set the receive FIFO locked mode */
if (hcan->Init.ReceiveFifoLocked == ENABLE)
800202c: 687b ldr r3, [r7, #4]
800202e: 7f1b ldrb r3, [r3, #28]
8002030: 2b01 cmp r3, #1
8002032: d108 bne.n 8002046 <HAL_CAN_Init+0x17e>
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
8002034: 687b ldr r3, [r7, #4]
8002036: 681b ldr r3, [r3, #0]
8002038: 681a ldr r2, [r3, #0]
800203a: 687b ldr r3, [r7, #4]
800203c: 681b ldr r3, [r3, #0]
800203e: f042 0208 orr.w r2, r2, #8
8002042: 601a str r2, [r3, #0]
8002044: e007 b.n 8002056 <HAL_CAN_Init+0x18e>
}
else
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
8002046: 687b ldr r3, [r7, #4]
8002048: 681b ldr r3, [r3, #0]
800204a: 681a ldr r2, [r3, #0]
800204c: 687b ldr r3, [r7, #4]
800204e: 681b ldr r3, [r3, #0]
8002050: f022 0208 bic.w r2, r2, #8
8002054: 601a str r2, [r3, #0]
}
/* Set the transmit FIFO priority */
if (hcan->Init.TransmitFifoPriority == ENABLE)
8002056: 687b ldr r3, [r7, #4]
8002058: 7f5b ldrb r3, [r3, #29]
800205a: 2b01 cmp r3, #1
800205c: d108 bne.n 8002070 <HAL_CAN_Init+0x1a8>
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
800205e: 687b ldr r3, [r7, #4]
8002060: 681b ldr r3, [r3, #0]
8002062: 681a ldr r2, [r3, #0]
8002064: 687b ldr r3, [r7, #4]
8002066: 681b ldr r3, [r3, #0]
8002068: f042 0204 orr.w r2, r2, #4
800206c: 601a str r2, [r3, #0]
800206e: e007 b.n 8002080 <HAL_CAN_Init+0x1b8>
}
else
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
8002070: 687b ldr r3, [r7, #4]
8002072: 681b ldr r3, [r3, #0]
8002074: 681a ldr r2, [r3, #0]
8002076: 687b ldr r3, [r7, #4]
8002078: 681b ldr r3, [r3, #0]
800207a: f022 0204 bic.w r2, r2, #4
800207e: 601a str r2, [r3, #0]
}
/* Set the bit timing register */
WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode |
8002080: 687b ldr r3, [r7, #4]
8002082: 689a ldr r2, [r3, #8]
8002084: 687b ldr r3, [r7, #4]
8002086: 68db ldr r3, [r3, #12]
8002088: 431a orrs r2, r3
800208a: 687b ldr r3, [r7, #4]
800208c: 691b ldr r3, [r3, #16]
800208e: 431a orrs r2, r3
8002090: 687b ldr r3, [r7, #4]
8002092: 695b ldr r3, [r3, #20]
8002094: ea42 0103 orr.w r1, r2, r3
8002098: 687b ldr r3, [r7, #4]
800209a: 685b ldr r3, [r3, #4]
800209c: 1e5a subs r2, r3, #1
800209e: 687b ldr r3, [r7, #4]
80020a0: 681b ldr r3, [r3, #0]
80020a2: 430a orrs r2, r1
80020a4: 61da str r2, [r3, #28]
hcan->Init.TimeSeg1 |
hcan->Init.TimeSeg2 |
(hcan->Init.Prescaler - 1U)));
/* Initialize the error code */
hcan->ErrorCode = HAL_CAN_ERROR_NONE;
80020a6: 687b ldr r3, [r7, #4]
80020a8: 2200 movs r2, #0
80020aa: 625a str r2, [r3, #36] ; 0x24
/* Initialize the CAN state */
hcan->State = HAL_CAN_STATE_READY;
80020ac: 687b ldr r3, [r7, #4]
80020ae: 2201 movs r2, #1
80020b0: f883 2020 strb.w r2, [r3, #32]
/* Return function status */
return HAL_OK;
80020b4: 2300 movs r3, #0
}
80020b6: 4618 mov r0, r3
80020b8: 3710 adds r7, #16
80020ba: 46bd mov sp, r7
80020bc: bd80 pop {r7, pc}
...
080020c0 <HAL_CAN_ConfigFilter>:
* @param sFilterConfig pointer to a CAN_FilterTypeDef structure that
* contains the filter configuration information.
* @retval None
*/
HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig)
{
80020c0: b480 push {r7}
80020c2: b087 sub sp, #28
80020c4: af00 add r7, sp, #0
80020c6: 6078 str r0, [r7, #4]
80020c8: 6039 str r1, [r7, #0]
uint32_t filternbrbitpos;
CAN_TypeDef *can_ip = hcan->Instance;
80020ca: 687b ldr r3, [r7, #4]
80020cc: 681b ldr r3, [r3, #0]
80020ce: 617b str r3, [r7, #20]
HAL_CAN_StateTypeDef state = hcan->State;
80020d0: 687b ldr r3, [r7, #4]
80020d2: f893 3020 ldrb.w r3, [r3, #32]
80020d6: 74fb strb r3, [r7, #19]
if ((state == HAL_CAN_STATE_READY) ||
80020d8: 7cfb ldrb r3, [r7, #19]
80020da: 2b01 cmp r3, #1
80020dc: d003 beq.n 80020e6 <HAL_CAN_ConfigFilter+0x26>
80020de: 7cfb ldrb r3, [r7, #19]
80020e0: 2b02 cmp r3, #2
80020e2: f040 80be bne.w 8002262 <HAL_CAN_ConfigFilter+0x1a2>
assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->SlaveStartFilterBank));
}
#elif defined(CAN2)
/* CAN1 and CAN2 are dual instances with 28 common filters banks */
/* Select master instance to access the filter banks */
can_ip = CAN1;
80020e6: 4b65 ldr r3, [pc, #404] ; (800227c <HAL_CAN_ConfigFilter+0x1bc>)
80020e8: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank));
#endif
/* Initialisation mode for the filter */
SET_BIT(can_ip->FMR, CAN_FMR_FINIT);
80020ea: 697b ldr r3, [r7, #20]
80020ec: f8d3 3200 ldr.w r3, [r3, #512] ; 0x200
80020f0: f043 0201 orr.w r2, r3, #1
80020f4: 697b ldr r3, [r7, #20]
80020f6: f8c3 2200 str.w r2, [r3, #512] ; 0x200
SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos);
}
#elif defined(CAN2)
/* Select the start filter number of CAN2 slave instance */
CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB);
80020fa: 697b ldr r3, [r7, #20]
80020fc: f8d3 3200 ldr.w r3, [r3, #512] ; 0x200
8002100: f423 527c bic.w r2, r3, #16128 ; 0x3f00
8002104: 697b ldr r3, [r7, #20]
8002106: f8c3 2200 str.w r2, [r3, #512] ; 0x200
SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos);
800210a: 697b ldr r3, [r7, #20]
800210c: f8d3 2200 ldr.w r2, [r3, #512] ; 0x200
8002110: 683b ldr r3, [r7, #0]
8002112: 6a5b ldr r3, [r3, #36] ; 0x24
8002114: 021b lsls r3, r3, #8
8002116: 431a orrs r2, r3
8002118: 697b ldr r3, [r7, #20]
800211a: f8c3 2200 str.w r2, [r3, #512] ; 0x200
#endif
/* Convert filter number into bit position */
filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU);
800211e: 683b ldr r3, [r7, #0]
8002120: 695b ldr r3, [r3, #20]
8002122: f003 031f and.w r3, r3, #31
8002126: 2201 movs r2, #1
8002128: fa02 f303 lsl.w r3, r2, r3
800212c: 60fb str r3, [r7, #12]
/* Filter Deactivation */
CLEAR_BIT(can_ip->FA1R, filternbrbitpos);
800212e: 697b ldr r3, [r7, #20]
8002130: f8d3 221c ldr.w r2, [r3, #540] ; 0x21c
8002134: 68fb ldr r3, [r7, #12]
8002136: 43db mvns r3, r3
8002138: 401a ands r2, r3
800213a: 697b ldr r3, [r7, #20]
800213c: f8c3 221c str.w r2, [r3, #540] ; 0x21c
/* Filter Scale */
if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
8002140: 683b ldr r3, [r7, #0]
8002142: 69db ldr r3, [r3, #28]
8002144: 2b00 cmp r3, #0
8002146: d123 bne.n 8002190 <HAL_CAN_ConfigFilter+0xd0>
{
/* 16-bit scale for the filter */
CLEAR_BIT(can_ip->FS1R, filternbrbitpos);
8002148: 697b ldr r3, [r7, #20]
800214a: f8d3 220c ldr.w r2, [r3, #524] ; 0x20c
800214e: 68fb ldr r3, [r7, #12]
8002150: 43db mvns r3, r3
8002152: 401a ands r2, r3
8002154: 697b ldr r3, [r7, #20]
8002156: f8c3 220c str.w r2, [r3, #524] ; 0x20c
/* First 16-bit identifier and First 16-bit mask */
/* Or First 16-bit identifier and Second 16-bit identifier */
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
800215a: 683b ldr r3, [r7, #0]
800215c: 68db ldr r3, [r3, #12]
800215e: 0419 lsls r1, r3, #16
(0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
8002160: 683b ldr r3, [r7, #0]
8002162: 685b ldr r3, [r3, #4]
8002164: b29b uxth r3, r3
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
8002166: 683a ldr r2, [r7, #0]
8002168: 6952 ldr r2, [r2, #20]
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
800216a: 4319 orrs r1, r3
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
800216c: 697b ldr r3, [r7, #20]
800216e: 3248 adds r2, #72 ; 0x48
8002170: f843 1032 str.w r1, [r3, r2, lsl #3]
/* Second 16-bit identifier and Second 16-bit mask */
/* Or Third 16-bit identifier and Fourth 16-bit identifier */
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
8002174: 683b ldr r3, [r7, #0]
8002176: 689b ldr r3, [r3, #8]
8002178: 0419 lsls r1, r3, #16
(0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh);
800217a: 683b ldr r3, [r7, #0]
800217c: 681b ldr r3, [r3, #0]
800217e: b29a uxth r2, r3
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
8002180: 683b ldr r3, [r7, #0]
8002182: 695b ldr r3, [r3, #20]
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
8002184: 430a orrs r2, r1
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
8002186: 6979 ldr r1, [r7, #20]
8002188: 3348 adds r3, #72 ; 0x48
800218a: 00db lsls r3, r3, #3
800218c: 440b add r3, r1
800218e: 605a str r2, [r3, #4]
}
if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
8002190: 683b ldr r3, [r7, #0]
8002192: 69db ldr r3, [r3, #28]
8002194: 2b01 cmp r3, #1
8002196: d122 bne.n 80021de <HAL_CAN_ConfigFilter+0x11e>
{
/* 32-bit scale for the filter */
SET_BIT(can_ip->FS1R, filternbrbitpos);
8002198: 697b ldr r3, [r7, #20]
800219a: f8d3 220c ldr.w r2, [r3, #524] ; 0x20c
800219e: 68fb ldr r3, [r7, #12]
80021a0: 431a orrs r2, r3
80021a2: 697b ldr r3, [r7, #20]
80021a4: f8c3 220c str.w r2, [r3, #524] ; 0x20c
/* 32-bit identifier or First 32-bit identifier */
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
80021a8: 683b ldr r3, [r7, #0]
80021aa: 681b ldr r3, [r3, #0]
80021ac: 0419 lsls r1, r3, #16
(0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
80021ae: 683b ldr r3, [r7, #0]
80021b0: 685b ldr r3, [r3, #4]
80021b2: b29b uxth r3, r3
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
80021b4: 683a ldr r2, [r7, #0]
80021b6: 6952 ldr r2, [r2, #20]
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
80021b8: 4319 orrs r1, r3
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
80021ba: 697b ldr r3, [r7, #20]
80021bc: 3248 adds r2, #72 ; 0x48
80021be: f843 1032 str.w r1, [r3, r2, lsl #3]
/* 32-bit mask or Second 32-bit identifier */
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
80021c2: 683b ldr r3, [r7, #0]
80021c4: 689b ldr r3, [r3, #8]
80021c6: 0419 lsls r1, r3, #16
(0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow);
80021c8: 683b ldr r3, [r7, #0]
80021ca: 68db ldr r3, [r3, #12]
80021cc: b29a uxth r2, r3
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
80021ce: 683b ldr r3, [r7, #0]
80021d0: 695b ldr r3, [r3, #20]
((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
80021d2: 430a orrs r2, r1
can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
80021d4: 6979 ldr r1, [r7, #20]
80021d6: 3348 adds r3, #72 ; 0x48
80021d8: 00db lsls r3, r3, #3
80021da: 440b add r3, r1
80021dc: 605a str r2, [r3, #4]
}
/* Filter Mode */
if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
80021de: 683b ldr r3, [r7, #0]
80021e0: 699b ldr r3, [r3, #24]
80021e2: 2b00 cmp r3, #0
80021e4: d109 bne.n 80021fa <HAL_CAN_ConfigFilter+0x13a>
{
/* Id/Mask mode for the filter*/
CLEAR_BIT(can_ip->FM1R, filternbrbitpos);
80021e6: 697b ldr r3, [r7, #20]
80021e8: f8d3 2204 ldr.w r2, [r3, #516] ; 0x204
80021ec: 68fb ldr r3, [r7, #12]
80021ee: 43db mvns r3, r3
80021f0: 401a ands r2, r3
80021f2: 697b ldr r3, [r7, #20]
80021f4: f8c3 2204 str.w r2, [r3, #516] ; 0x204
80021f8: e007 b.n 800220a <HAL_CAN_ConfigFilter+0x14a>
}
else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
{
/* Identifier list mode for the filter*/
SET_BIT(can_ip->FM1R, filternbrbitpos);
80021fa: 697b ldr r3, [r7, #20]
80021fc: f8d3 2204 ldr.w r2, [r3, #516] ; 0x204
8002200: 68fb ldr r3, [r7, #12]
8002202: 431a orrs r2, r3
8002204: 697b ldr r3, [r7, #20]
8002206: f8c3 2204 str.w r2, [r3, #516] ; 0x204
}
/* Filter FIFO assignment */
if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
800220a: 683b ldr r3, [r7, #0]
800220c: 691b ldr r3, [r3, #16]
800220e: 2b00 cmp r3, #0
8002210: d109 bne.n 8002226 <HAL_CAN_ConfigFilter+0x166>
{
/* FIFO 0 assignation for the filter */
CLEAR_BIT(can_ip->FFA1R, filternbrbitpos);
8002212: 697b ldr r3, [r7, #20]
8002214: f8d3 2214 ldr.w r2, [r3, #532] ; 0x214
8002218: 68fb ldr r3, [r7, #12]
800221a: 43db mvns r3, r3
800221c: 401a ands r2, r3
800221e: 697b ldr r3, [r7, #20]
8002220: f8c3 2214 str.w r2, [r3, #532] ; 0x214
8002224: e007 b.n 8002236 <HAL_CAN_ConfigFilter+0x176>
}
else
{
/* FIFO 1 assignation for the filter */
SET_BIT(can_ip->FFA1R, filternbrbitpos);
8002226: 697b ldr r3, [r7, #20]
8002228: f8d3 2214 ldr.w r2, [r3, #532] ; 0x214
800222c: 68fb ldr r3, [r7, #12]
800222e: 431a orrs r2, r3
8002230: 697b ldr r3, [r7, #20]
8002232: f8c3 2214 str.w r2, [r3, #532] ; 0x214
}
/* Filter activation */
if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE)
8002236: 683b ldr r3, [r7, #0]
8002238: 6a1b ldr r3, [r3, #32]
800223a: 2b01 cmp r3, #1
800223c: d107 bne.n 800224e <HAL_CAN_ConfigFilter+0x18e>
{
SET_BIT(can_ip->FA1R, filternbrbitpos);
800223e: 697b ldr r3, [r7, #20]
8002240: f8d3 221c ldr.w r2, [r3, #540] ; 0x21c
8002244: 68fb ldr r3, [r7, #12]
8002246: 431a orrs r2, r3
8002248: 697b ldr r3, [r7, #20]
800224a: f8c3 221c str.w r2, [r3, #540] ; 0x21c
}
/* Leave the initialisation mode for the filter */
CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT);
800224e: 697b ldr r3, [r7, #20]
8002250: f8d3 3200 ldr.w r3, [r3, #512] ; 0x200
8002254: f023 0201 bic.w r2, r3, #1
8002258: 697b ldr r3, [r7, #20]
800225a: f8c3 2200 str.w r2, [r3, #512] ; 0x200
/* Return function status */
return HAL_OK;
800225e: 2300 movs r3, #0
8002260: e006 b.n 8002270 <HAL_CAN_ConfigFilter+0x1b0>
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
8002262: 687b ldr r3, [r7, #4]
8002264: 6a5b ldr r3, [r3, #36] ; 0x24
8002266: f443 2280 orr.w r2, r3, #262144 ; 0x40000
800226a: 687b ldr r3, [r7, #4]
800226c: 625a str r2, [r3, #36] ; 0x24
return HAL_ERROR;
800226e: 2301 movs r3, #1
}
}
8002270: 4618 mov r0, r3
8002272: 371c adds r7, #28
8002274: 46bd mov sp, r7
8002276: f85d 7b04 ldr.w r7, [sp], #4
800227a: 4770 bx lr
800227c: 40006400 .word 0x40006400
08002280 <HAL_CAN_Start>:
* @param hcan pointer to an CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan)
{
8002280: b580 push {r7, lr}
8002282: b084 sub sp, #16
8002284: af00 add r7, sp, #0
8002286: 6078 str r0, [r7, #4]
uint32_t tickstart;
if (hcan->State == HAL_CAN_STATE_READY)
8002288: 687b ldr r3, [r7, #4]
800228a: f893 3020 ldrb.w r3, [r3, #32]
800228e: b2db uxtb r3, r3
8002290: 2b01 cmp r3, #1
8002292: d12e bne.n 80022f2 <HAL_CAN_Start+0x72>
{
/* Change CAN peripheral state */
hcan->State = HAL_CAN_STATE_LISTENING;
8002294: 687b ldr r3, [r7, #4]
8002296: 2202 movs r2, #2
8002298: f883 2020 strb.w r2, [r3, #32]
/* Request leave initialisation */
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
800229c: 687b ldr r3, [r7, #4]
800229e: 681b ldr r3, [r3, #0]
80022a0: 681a ldr r2, [r3, #0]
80022a2: 687b ldr r3, [r7, #4]
80022a4: 681b ldr r3, [r3, #0]
80022a6: f022 0201 bic.w r2, r2, #1
80022aa: 601a str r2, [r3, #0]
/* Get tick */
tickstart = HAL_GetTick();
80022ac: f7ff fddc bl 8001e68 <HAL_GetTick>
80022b0: 60f8 str r0, [r7, #12]
/* Wait the acknowledge */
while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U)
80022b2: e012 b.n 80022da <HAL_CAN_Start+0x5a>
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
80022b4: f7ff fdd8 bl 8001e68 <HAL_GetTick>
80022b8: 4602 mov r2, r0
80022ba: 68fb ldr r3, [r7, #12]
80022bc: 1ad3 subs r3, r2, r3
80022be: 2b0a cmp r3, #10
80022c0: d90b bls.n 80022da <HAL_CAN_Start+0x5a>
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
80022c2: 687b ldr r3, [r7, #4]
80022c4: 6a5b ldr r3, [r3, #36] ; 0x24
80022c6: f443 3200 orr.w r2, r3, #131072 ; 0x20000
80022ca: 687b ldr r3, [r7, #4]
80022cc: 625a str r2, [r3, #36] ; 0x24
/* Change CAN state */
hcan->State = HAL_CAN_STATE_ERROR;
80022ce: 687b ldr r3, [r7, #4]
80022d0: 2205 movs r2, #5
80022d2: f883 2020 strb.w r2, [r3, #32]
return HAL_ERROR;
80022d6: 2301 movs r3, #1
80022d8: e012 b.n 8002300 <HAL_CAN_Start+0x80>
while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U)
80022da: 687b ldr r3, [r7, #4]
80022dc: 681b ldr r3, [r3, #0]
80022de: 685b ldr r3, [r3, #4]
80022e0: f003 0301 and.w r3, r3, #1
80022e4: 2b00 cmp r3, #0
80022e6: d1e5 bne.n 80022b4 <HAL_CAN_Start+0x34>
}
}
/* Reset the CAN ErrorCode */
hcan->ErrorCode = HAL_CAN_ERROR_NONE;
80022e8: 687b ldr r3, [r7, #4]
80022ea: 2200 movs r2, #0
80022ec: 625a str r2, [r3, #36] ; 0x24
/* Return function status */
return HAL_OK;
80022ee: 2300 movs r3, #0
80022f0: e006 b.n 8002300 <HAL_CAN_Start+0x80>
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY;
80022f2: 687b ldr r3, [r7, #4]
80022f4: 6a5b ldr r3, [r3, #36] ; 0x24
80022f6: f443 2200 orr.w r2, r3, #524288 ; 0x80000
80022fa: 687b ldr r3, [r7, #4]
80022fc: 625a str r2, [r3, #36] ; 0x24
return HAL_ERROR;
80022fe: 2301 movs r3, #1
}
}
8002300: 4618 mov r0, r3
8002302: 3710 adds r7, #16
8002304: 46bd mov sp, r7
8002306: bd80 pop {r7, pc}
08002308 <HAL_CAN_AddTxMessage>:
* the TxMailbox used to store the Tx message.
* This parameter can be a value of @arg CAN_Tx_Mailboxes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox)
{
8002308: b480 push {r7}
800230a: b089 sub sp, #36 ; 0x24
800230c: af00 add r7, sp, #0
800230e: 60f8 str r0, [r7, #12]
8002310: 60b9 str r1, [r7, #8]
8002312: 607a str r2, [r7, #4]
8002314: 603b str r3, [r7, #0]
uint32_t transmitmailbox;
HAL_CAN_StateTypeDef state = hcan->State;
8002316: 68fb ldr r3, [r7, #12]
8002318: f893 3020 ldrb.w r3, [r3, #32]
800231c: 77fb strb r3, [r7, #31]
uint32_t tsr = READ_REG(hcan->Instance->TSR);
800231e: 68fb ldr r3, [r7, #12]
8002320: 681b ldr r3, [r3, #0]
8002322: 689b ldr r3, [r3, #8]
8002324: 61bb str r3, [r7, #24]
{
assert_param(IS_CAN_EXTID(pHeader->ExtId));
}
assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime));
if ((state == HAL_CAN_STATE_READY) ||
8002326: 7ffb ldrb r3, [r7, #31]
8002328: 2b01 cmp r3, #1
800232a: d003 beq.n 8002334 <HAL_CAN_AddTxMessage+0x2c>
800232c: 7ffb ldrb r3, [r7, #31]
800232e: 2b02 cmp r3, #2
8002330: f040 80b8 bne.w 80024a4 <HAL_CAN_AddTxMessage+0x19c>
(state == HAL_CAN_STATE_LISTENING))
{
/* Check that all the Tx mailboxes are not full */
if (((tsr & CAN_TSR_TME0) != 0U) ||
8002334: 69bb ldr r3, [r7, #24]
8002336: f003 6380 and.w r3, r3, #67108864 ; 0x4000000
800233a: 2b00 cmp r3, #0
800233c: d10a bne.n 8002354 <HAL_CAN_AddTxMessage+0x4c>
((tsr & CAN_TSR_TME1) != 0U) ||
800233e: 69bb ldr r3, [r7, #24]
8002340: f003 6300 and.w r3, r3, #134217728 ; 0x8000000
if (((tsr & CAN_TSR_TME0) != 0U) ||
8002344: 2b00 cmp r3, #0
8002346: d105 bne.n 8002354 <HAL_CAN_AddTxMessage+0x4c>
((tsr & CAN_TSR_TME2) != 0U))
8002348: 69bb ldr r3, [r7, #24]
800234a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
((tsr & CAN_TSR_TME1) != 0U) ||
800234e: 2b00 cmp r3, #0
8002350: f000 80a0 beq.w 8002494 <HAL_CAN_AddTxMessage+0x18c>
{
/* Select an empty transmit mailbox */
transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos;
8002354: 69bb ldr r3, [r7, #24]
8002356: 0e1b lsrs r3, r3, #24
8002358: f003 0303 and.w r3, r3, #3
800235c: 617b str r3, [r7, #20]
/* Check transmit mailbox value */
if (transmitmailbox > 2U)
800235e: 697b ldr r3, [r7, #20]
8002360: 2b02 cmp r3, #2
8002362: d907 bls.n 8002374 <HAL_CAN_AddTxMessage+0x6c>
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_INTERNAL;
8002364: 68fb ldr r3, [r7, #12]
8002366: 6a5b ldr r3, [r3, #36] ; 0x24
8002368: f443 0200 orr.w r2, r3, #8388608 ; 0x800000
800236c: 68fb ldr r3, [r7, #12]
800236e: 625a str r2, [r3, #36] ; 0x24
return HAL_ERROR;
8002370: 2301 movs r3, #1
8002372: e09e b.n 80024b2 <HAL_CAN_AddTxMessage+0x1aa>
}
/* Store the Tx mailbox */
*pTxMailbox = (uint32_t)1 << transmitmailbox;
8002374: 2201 movs r2, #1
8002376: 697b ldr r3, [r7, #20]
8002378: 409a lsls r2, r3
800237a: 683b ldr r3, [r7, #0]
800237c: 601a str r2, [r3, #0]
/* Set up the Id */
if (pHeader->IDE == CAN_ID_STD)
800237e: 68bb ldr r3, [r7, #8]
8002380: 689b ldr r3, [r3, #8]
8002382: 2b00 cmp r3, #0
8002384: d10d bne.n 80023a2 <HAL_CAN_AddTxMessage+0x9a>
{
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) |
8002386: 68bb ldr r3, [r7, #8]
8002388: 681b ldr r3, [r3, #0]
800238a: 055a lsls r2, r3, #21
pHeader->RTR);
800238c: 68bb ldr r3, [r7, #8]
800238e: 68db ldr r3, [r3, #12]
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) |
8002390: 68f9 ldr r1, [r7, #12]
8002392: 6809 ldr r1, [r1, #0]
8002394: 431a orrs r2, r3
8002396: 697b ldr r3, [r7, #20]
8002398: 3318 adds r3, #24
800239a: 011b lsls r3, r3, #4
800239c: 440b add r3, r1
800239e: 601a str r2, [r3, #0]
80023a0: e00f b.n 80023c2 <HAL_CAN_AddTxMessage+0xba>
}
else
{
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
80023a2: 68bb ldr r3, [r7, #8]
80023a4: 685b ldr r3, [r3, #4]
80023a6: 00da lsls r2, r3, #3
pHeader->IDE |
80023a8: 68bb ldr r3, [r7, #8]
80023aa: 689b ldr r3, [r3, #8]
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
80023ac: 431a orrs r2, r3
pHeader->RTR);
80023ae: 68bb ldr r3, [r7, #8]
80023b0: 68db ldr r3, [r3, #12]
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
80023b2: 68f9 ldr r1, [r7, #12]
80023b4: 6809 ldr r1, [r1, #0]
pHeader->IDE |
80023b6: 431a orrs r2, r3
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
80023b8: 697b ldr r3, [r7, #20]
80023ba: 3318 adds r3, #24
80023bc: 011b lsls r3, r3, #4
80023be: 440b add r3, r1
80023c0: 601a str r2, [r3, #0]
}
/* Set up the DLC */
hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC);
80023c2: 68fb ldr r3, [r7, #12]
80023c4: 6819 ldr r1, [r3, #0]
80023c6: 68bb ldr r3, [r7, #8]
80023c8: 691a ldr r2, [r3, #16]
80023ca: 697b ldr r3, [r7, #20]
80023cc: 3318 adds r3, #24
80023ce: 011b lsls r3, r3, #4
80023d0: 440b add r3, r1
80023d2: 3304 adds r3, #4
80023d4: 601a str r2, [r3, #0]
/* Set up the Transmit Global Time mode */
if (pHeader->TransmitGlobalTime == ENABLE)
80023d6: 68bb ldr r3, [r7, #8]
80023d8: 7d1b ldrb r3, [r3, #20]
80023da: 2b01 cmp r3, #1
80023dc: d111 bne.n 8002402 <HAL_CAN_AddTxMessage+0xfa>
{
SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT);
80023de: 68fb ldr r3, [r7, #12]
80023e0: 681a ldr r2, [r3, #0]
80023e2: 697b ldr r3, [r7, #20]
80023e4: 3318 adds r3, #24
80023e6: 011b lsls r3, r3, #4
80023e8: 4413 add r3, r2
80023ea: 3304 adds r3, #4
80023ec: 681b ldr r3, [r3, #0]
80023ee: 68fa ldr r2, [r7, #12]
80023f0: 6811 ldr r1, [r2, #0]
80023f2: f443 7280 orr.w r2, r3, #256 ; 0x100
80023f6: 697b ldr r3, [r7, #20]
80023f8: 3318 adds r3, #24
80023fa: 011b lsls r3, r3, #4
80023fc: 440b add r3, r1
80023fe: 3304 adds r3, #4
8002400: 601a str r2, [r3, #0]
}
/* Set up the data field */
WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR,
8002402: 687b ldr r3, [r7, #4]
8002404: 3307 adds r3, #7
8002406: 781b ldrb r3, [r3, #0]
8002408: 061a lsls r2, r3, #24
800240a: 687b ldr r3, [r7, #4]
800240c: 3306 adds r3, #6
800240e: 781b ldrb r3, [r3, #0]
8002410: 041b lsls r3, r3, #16
8002412: 431a orrs r2, r3
8002414: 687b ldr r3, [r7, #4]
8002416: 3305 adds r3, #5
8002418: 781b ldrb r3, [r3, #0]
800241a: 021b lsls r3, r3, #8
800241c: 4313 orrs r3, r2
800241e: 687a ldr r2, [r7, #4]
8002420: 3204 adds r2, #4
8002422: 7812 ldrb r2, [r2, #0]
8002424: 4610 mov r0, r2
8002426: 68fa ldr r2, [r7, #12]
8002428: 6811 ldr r1, [r2, #0]
800242a: ea43 0200 orr.w r2, r3, r0
800242e: 697b ldr r3, [r7, #20]
8002430: 011b lsls r3, r3, #4
8002432: 440b add r3, r1
8002434: f503 73c6 add.w r3, r3, #396 ; 0x18c
8002438: 601a str r2, [r3, #0]
((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) |
((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) |
((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) |
((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos));
WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR,
800243a: 687b ldr r3, [r7, #4]
800243c: 3303 adds r3, #3
800243e: 781b ldrb r3, [r3, #0]
8002440: 061a lsls r2, r3, #24
8002442: 687b ldr r3, [r7, #4]
8002444: 3302 adds r3, #2
8002446: 781b ldrb r3, [r3, #0]
8002448: 041b lsls r3, r3, #16
800244a: 431a orrs r2, r3
800244c: 687b ldr r3, [r7, #4]
800244e: 3301 adds r3, #1
8002450: 781b ldrb r3, [r3, #0]
8002452: 021b lsls r3, r3, #8
8002454: 4313 orrs r3, r2
8002456: 687a ldr r2, [r7, #4]
8002458: 7812 ldrb r2, [r2, #0]
800245a: 4610 mov r0, r2
800245c: 68fa ldr r2, [r7, #12]
800245e: 6811 ldr r1, [r2, #0]
8002460: ea43 0200 orr.w r2, r3, r0
8002464: 697b ldr r3, [r7, #20]
8002466: 011b lsls r3, r3, #4
8002468: 440b add r3, r1
800246a: f503 73c4 add.w r3, r3, #392 ; 0x188
800246e: 601a str r2, [r3, #0]
((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) |
((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) |
((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos));
/* Request transmission */
SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ);
8002470: 68fb ldr r3, [r7, #12]
8002472: 681a ldr r2, [r3, #0]
8002474: 697b ldr r3, [r7, #20]
8002476: 3318 adds r3, #24
8002478: 011b lsls r3, r3, #4
800247a: 4413 add r3, r2
800247c: 681b ldr r3, [r3, #0]
800247e: 68fa ldr r2, [r7, #12]
8002480: 6811 ldr r1, [r2, #0]
8002482: f043 0201 orr.w r2, r3, #1
8002486: 697b ldr r3, [r7, #20]
8002488: 3318 adds r3, #24
800248a: 011b lsls r3, r3, #4
800248c: 440b add r3, r1
800248e: 601a str r2, [r3, #0]
/* Return function status */
return HAL_OK;
8002490: 2300 movs r3, #0
8002492: e00e b.n 80024b2 <HAL_CAN_AddTxMessage+0x1aa>
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
8002494: 68fb ldr r3, [r7, #12]
8002496: 6a5b ldr r3, [r3, #36] ; 0x24
8002498: f443 1200 orr.w r2, r3, #2097152 ; 0x200000
800249c: 68fb ldr r3, [r7, #12]
800249e: 625a str r2, [r3, #36] ; 0x24
return HAL_ERROR;
80024a0: 2301 movs r3, #1
80024a2: e006 b.n 80024b2 <HAL_CAN_AddTxMessage+0x1aa>
}
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
80024a4: 68fb ldr r3, [r7, #12]
80024a6: 6a5b ldr r3, [r3, #36] ; 0x24
80024a8: f443 2280 orr.w r2, r3, #262144 ; 0x40000
80024ac: 68fb ldr r3, [r7, #12]
80024ae: 625a str r2, [r3, #36] ; 0x24
return HAL_ERROR;
80024b0: 2301 movs r3, #1
}
}
80024b2: 4618 mov r0, r3
80024b4: 3724 adds r7, #36 ; 0x24
80024b6: 46bd mov sp, r7
80024b8: f85d 7b04 ldr.w r7, [sp], #4
80024bc: 4770 bx lr
080024be <HAL_CAN_GetRxMessage>:
* of the Rx frame will be stored.
* @param aData array where the payload of the Rx frame will be stored.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[])
{
80024be: b480 push {r7}
80024c0: b087 sub sp, #28
80024c2: af00 add r7, sp, #0
80024c4: 60f8 str r0, [r7, #12]
80024c6: 60b9 str r1, [r7, #8]
80024c8: 607a str r2, [r7, #4]
80024ca: 603b str r3, [r7, #0]
HAL_CAN_StateTypeDef state = hcan->State;
80024cc: 68fb ldr r3, [r7, #12]
80024ce: f893 3020 ldrb.w r3, [r3, #32]
80024d2: 75fb strb r3, [r7, #23]
assert_param(IS_CAN_RX_FIFO(RxFifo));
if ((state == HAL_CAN_STATE_READY) ||
80024d4: 7dfb ldrb r3, [r7, #23]
80024d6: 2b01 cmp r3, #1
80024d8: d003 beq.n 80024e2 <HAL_CAN_GetRxMessage+0x24>
80024da: 7dfb ldrb r3, [r7, #23]
80024dc: 2b02 cmp r3, #2
80024de: f040 80f3 bne.w 80026c8 <HAL_CAN_GetRxMessage+0x20a>
(state == HAL_CAN_STATE_LISTENING))
{
/* Check the Rx FIFO */
if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */
80024e2: 68bb ldr r3, [r7, #8]
80024e4: 2b00 cmp r3, #0
80024e6: d10e bne.n 8002506 <HAL_CAN_GetRxMessage+0x48>
{
/* Check that the Rx FIFO 0 is not empty */
if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U)
80024e8: 68fb ldr r3, [r7, #12]
80024ea: 681b ldr r3, [r3, #0]
80024ec: 68db ldr r3, [r3, #12]
80024ee: f003 0303 and.w r3, r3, #3
80024f2: 2b00 cmp r3, #0
80024f4: d116 bne.n 8002524 <HAL_CAN_GetRxMessage+0x66>
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
80024f6: 68fb ldr r3, [r7, #12]
80024f8: 6a5b ldr r3, [r3, #36] ; 0x24
80024fa: f443 1200 orr.w r2, r3, #2097152 ; 0x200000
80024fe: 68fb ldr r3, [r7, #12]
8002500: 625a str r2, [r3, #36] ; 0x24
return HAL_ERROR;
8002502: 2301 movs r3, #1
8002504: e0e7 b.n 80026d6 <HAL_CAN_GetRxMessage+0x218>
}
}
else /* Rx element is assigned to Rx FIFO 1 */
{
/* Check that the Rx FIFO 1 is not empty */
if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U)
8002506: 68fb ldr r3, [r7, #12]
8002508: 681b ldr r3, [r3, #0]
800250a: 691b ldr r3, [r3, #16]
800250c: f003 0303 and.w r3, r3, #3
8002510: 2b00 cmp r3, #0
8002512: d107 bne.n 8002524 <HAL_CAN_GetRxMessage+0x66>
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
8002514: 68fb ldr r3, [r7, #12]
8002516: 6a5b ldr r3, [r3, #36] ; 0x24
8002518: f443 1200 orr.w r2, r3, #2097152 ; 0x200000
800251c: 68fb ldr r3, [r7, #12]
800251e: 625a str r2, [r3, #36] ; 0x24
return HAL_ERROR;
8002520: 2301 movs r3, #1
8002522: e0d8 b.n 80026d6 <HAL_CAN_GetRxMessage+0x218>
}
}
/* Get the header */
pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR;
8002524: 68fb ldr r3, [r7, #12]
8002526: 681a ldr r2, [r3, #0]
8002528: 68bb ldr r3, [r7, #8]
800252a: 331b adds r3, #27
800252c: 011b lsls r3, r3, #4
800252e: 4413 add r3, r2
8002530: 681b ldr r3, [r3, #0]
8002532: f003 0204 and.w r2, r3, #4
8002536: 687b ldr r3, [r7, #4]
8002538: 609a str r2, [r3, #8]
if (pHeader->IDE == CAN_ID_STD)
800253a: 687b ldr r3, [r7, #4]
800253c: 689b ldr r3, [r3, #8]
800253e: 2b00 cmp r3, #0
8002540: d10c bne.n 800255c <HAL_CAN_GetRxMessage+0x9e>
{
pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos;
8002542: 68fb ldr r3, [r7, #12]
8002544: 681a ldr r2, [r3, #0]
8002546: 68bb ldr r3, [r7, #8]
8002548: 331b adds r3, #27
800254a: 011b lsls r3, r3, #4
800254c: 4413 add r3, r2
800254e: 681b ldr r3, [r3, #0]
8002550: 0d5b lsrs r3, r3, #21
8002552: f3c3 020a ubfx r2, r3, #0, #11
8002556: 687b ldr r3, [r7, #4]
8002558: 601a str r2, [r3, #0]
800255a: e00b b.n 8002574 <HAL_CAN_GetRxMessage+0xb6>
}
else
{
pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos;
800255c: 68fb ldr r3, [r7, #12]
800255e: 681a ldr r2, [r3, #0]
8002560: 68bb ldr r3, [r7, #8]
8002562: 331b adds r3, #27
8002564: 011b lsls r3, r3, #4
8002566: 4413 add r3, r2
8002568: 681b ldr r3, [r3, #0]
800256a: 08db lsrs r3, r3, #3
800256c: f023 4260 bic.w r2, r3, #3758096384 ; 0xe0000000
8002570: 687b ldr r3, [r7, #4]
8002572: 605a str r2, [r3, #4]
}
pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR);
8002574: 68fb ldr r3, [r7, #12]
8002576: 681a ldr r2, [r3, #0]
8002578: 68bb ldr r3, [r7, #8]
800257a: 331b adds r3, #27
800257c: 011b lsls r3, r3, #4
800257e: 4413 add r3, r2
8002580: 681b ldr r3, [r3, #0]
8002582: f003 0202 and.w r2, r3, #2
8002586: 687b ldr r3, [r7, #4]
8002588: 60da str r2, [r3, #12]
pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos;
800258a: 68fb ldr r3, [r7, #12]
800258c: 681a ldr r2, [r3, #0]
800258e: 68bb ldr r3, [r7, #8]
8002590: 331b adds r3, #27
8002592: 011b lsls r3, r3, #4
8002594: 4413 add r3, r2
8002596: 3304 adds r3, #4
8002598: 681b ldr r3, [r3, #0]
800259a: f003 020f and.w r2, r3, #15
800259e: 687b ldr r3, [r7, #4]
80025a0: 611a str r2, [r3, #16]
pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos;
80025a2: 68fb ldr r3, [r7, #12]
80025a4: 681a ldr r2, [r3, #0]
80025a6: 68bb ldr r3, [r7, #8]
80025a8: 331b adds r3, #27
80025aa: 011b lsls r3, r3, #4
80025ac: 4413 add r3, r2
80025ae: 3304 adds r3, #4
80025b0: 681b ldr r3, [r3, #0]
80025b2: 0a1b lsrs r3, r3, #8
80025b4: b2da uxtb r2, r3
80025b6: 687b ldr r3, [r7, #4]
80025b8: 619a str r2, [r3, #24]
pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos;
80025ba: 68fb ldr r3, [r7, #12]
80025bc: 681a ldr r2, [r3, #0]
80025be: 68bb ldr r3, [r7, #8]
80025c0: 331b adds r3, #27
80025c2: 011b lsls r3, r3, #4
80025c4: 4413 add r3, r2
80025c6: 3304 adds r3, #4
80025c8: 681b ldr r3, [r3, #0]
80025ca: 0c1b lsrs r3, r3, #16
80025cc: b29a uxth r2, r3
80025ce: 687b ldr r3, [r7, #4]
80025d0: 615a str r2, [r3, #20]
/* Get the data */
aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos);
80025d2: 68fb ldr r3, [r7, #12]
80025d4: 681a ldr r2, [r3, #0]
80025d6: 68bb ldr r3, [r7, #8]
80025d8: 011b lsls r3, r3, #4
80025da: 4413 add r3, r2
80025dc: f503 73dc add.w r3, r3, #440 ; 0x1b8
80025e0: 681b ldr r3, [r3, #0]
80025e2: b2da uxtb r2, r3
80025e4: 683b ldr r3, [r7, #0]
80025e6: 701a strb r2, [r3, #0]
aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos);
80025e8: 68fb ldr r3, [r7, #12]
80025ea: 681a ldr r2, [r3, #0]
80025ec: 68bb ldr r3, [r7, #8]
80025ee: 011b lsls r3, r3, #4
80025f0: 4413 add r3, r2
80025f2: f503 73dc add.w r3, r3, #440 ; 0x1b8
80025f6: 681b ldr r3, [r3, #0]
80025f8: 0a1a lsrs r2, r3, #8
80025fa: 683b ldr r3, [r7, #0]
80025fc: 3301 adds r3, #1
80025fe: b2d2 uxtb r2, r2
8002600: 701a strb r2, [r3, #0]
aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos);
8002602: 68fb ldr r3, [r7, #12]
8002604: 681a ldr r2, [r3, #0]
8002606: 68bb ldr r3, [r7, #8]
8002608: 011b lsls r3, r3, #4
800260a: 4413 add r3, r2
800260c: f503 73dc add.w r3, r3, #440 ; 0x1b8
8002610: 681b ldr r3, [r3, #0]
8002612: 0c1a lsrs r2, r3, #16
8002614: 683b ldr r3, [r7, #0]
8002616: 3302 adds r3, #2
8002618: b2d2 uxtb r2, r2
800261a: 701a strb r2, [r3, #0]
aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos);
800261c: 68fb ldr r3, [r7, #12]
800261e: 681a ldr r2, [r3, #0]
8002620: 68bb ldr r3, [r7, #8]
8002622: 011b lsls r3, r3, #4
8002624: 4413 add r3, r2
8002626: f503 73dc add.w r3, r3, #440 ; 0x1b8
800262a: 681b ldr r3, [r3, #0]
800262c: 0e1a lsrs r2, r3, #24
800262e: 683b ldr r3, [r7, #0]
8002630: 3303 adds r3, #3
8002632: b2d2 uxtb r2, r2
8002634: 701a strb r2, [r3, #0]
aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos);
8002636: 68fb ldr r3, [r7, #12]
8002638: 681a ldr r2, [r3, #0]
800263a: 68bb ldr r3, [r7, #8]
800263c: 011b lsls r3, r3, #4
800263e: 4413 add r3, r2
8002640: f503 73de add.w r3, r3, #444 ; 0x1bc
8002644: 681a ldr r2, [r3, #0]
8002646: 683b ldr r3, [r7, #0]
8002648: 3304 adds r3, #4
800264a: b2d2 uxtb r2, r2
800264c: 701a strb r2, [r3, #0]
aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos);
800264e: 68fb ldr r3, [r7, #12]
8002650: 681a ldr r2, [r3, #0]
8002652: 68bb ldr r3, [r7, #8]
8002654: 011b lsls r3, r3, #4
8002656: 4413 add r3, r2
8002658: f503 73de add.w r3, r3, #444 ; 0x1bc
800265c: 681b ldr r3, [r3, #0]
800265e: 0a1a lsrs r2, r3, #8
8002660: 683b ldr r3, [r7, #0]
8002662: 3305 adds r3, #5
8002664: b2d2 uxtb r2, r2
8002666: 701a strb r2, [r3, #0]
aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos);
8002668: 68fb ldr r3, [r7, #12]
800266a: 681a ldr r2, [r3, #0]
800266c: 68bb ldr r3, [r7, #8]
800266e: 011b lsls r3, r3, #4
8002670: 4413 add r3, r2
8002672: f503 73de add.w r3, r3, #444 ; 0x1bc
8002676: 681b ldr r3, [r3, #0]
8002678: 0c1a lsrs r2, r3, #16
800267a: 683b ldr r3, [r7, #0]
800267c: 3306 adds r3, #6
800267e: b2d2 uxtb r2, r2
8002680: 701a strb r2, [r3, #0]
aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos);
8002682: 68fb ldr r3, [r7, #12]
8002684: 681a ldr r2, [r3, #0]
8002686: 68bb ldr r3, [r7, #8]
8002688: 011b lsls r3, r3, #4
800268a: 4413 add r3, r2
800268c: f503 73de add.w r3, r3, #444 ; 0x1bc
8002690: 681b ldr r3, [r3, #0]
8002692: 0e1a lsrs r2, r3, #24
8002694: 683b ldr r3, [r7, #0]
8002696: 3307 adds r3, #7
8002698: b2d2 uxtb r2, r2
800269a: 701a strb r2, [r3, #0]
/* Release the FIFO */
if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */
800269c: 68bb ldr r3, [r7, #8]
800269e: 2b00 cmp r3, #0
80026a0: d108 bne.n 80026b4 <HAL_CAN_GetRxMessage+0x1f6>
{
/* Release RX FIFO 0 */
SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0);
80026a2: 68fb ldr r3, [r7, #12]
80026a4: 681b ldr r3, [r3, #0]
80026a6: 68da ldr r2, [r3, #12]
80026a8: 68fb ldr r3, [r7, #12]
80026aa: 681b ldr r3, [r3, #0]
80026ac: f042 0220 orr.w r2, r2, #32
80026b0: 60da str r2, [r3, #12]
80026b2: e007 b.n 80026c4 <HAL_CAN_GetRxMessage+0x206>
}
else /* Rx element is assigned to Rx FIFO 1 */
{
/* Release RX FIFO 1 */
SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1);
80026b4: 68fb ldr r3, [r7, #12]
80026b6: 681b ldr r3, [r3, #0]
80026b8: 691a ldr r2, [r3, #16]
80026ba: 68fb ldr r3, [r7, #12]
80026bc: 681b ldr r3, [r3, #0]
80026be: f042 0220 orr.w r2, r2, #32
80026c2: 611a str r2, [r3, #16]
}
/* Return function status */
return HAL_OK;
80026c4: 2300 movs r3, #0
80026c6: e006 b.n 80026d6 <HAL_CAN_GetRxMessage+0x218>
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
80026c8: 68fb ldr r3, [r7, #12]
80026ca: 6a5b ldr r3, [r3, #36] ; 0x24
80026cc: f443 2280 orr.w r2, r3, #262144 ; 0x40000
80026d0: 68fb ldr r3, [r7, #12]
80026d2: 625a str r2, [r3, #36] ; 0x24
return HAL_ERROR;
80026d4: 2301 movs r3, #1
}
}
80026d6: 4618 mov r0, r3
80026d8: 371c adds r7, #28
80026da: 46bd mov sp, r7
80026dc: f85d 7b04 ldr.w r7, [sp], #4
80026e0: 4770 bx lr
080026e2 <HAL_CAN_ActivateNotification>:
* @param ActiveITs indicates which interrupts will be enabled.
* This parameter can be any combination of @arg CAN_Interrupts.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs)
{
80026e2: b480 push {r7}
80026e4: b085 sub sp, #20
80026e6: af00 add r7, sp, #0
80026e8: 6078 str r0, [r7, #4]
80026ea: 6039 str r1, [r7, #0]
HAL_CAN_StateTypeDef state = hcan->State;
80026ec: 687b ldr r3, [r7, #4]
80026ee: f893 3020 ldrb.w r3, [r3, #32]
80026f2: 73fb strb r3, [r7, #15]
/* Check function parameters */
assert_param(IS_CAN_IT(ActiveITs));
if ((state == HAL_CAN_STATE_READY) ||
80026f4: 7bfb ldrb r3, [r7, #15]
80026f6: 2b01 cmp r3, #1
80026f8: d002 beq.n 8002700 <HAL_CAN_ActivateNotification+0x1e>
80026fa: 7bfb ldrb r3, [r7, #15]
80026fc: 2b02 cmp r3, #2
80026fe: d109 bne.n 8002714 <HAL_CAN_ActivateNotification+0x32>
(state == HAL_CAN_STATE_LISTENING))
{
/* Enable the selected interrupts */
__HAL_CAN_ENABLE_IT(hcan, ActiveITs);
8002700: 687b ldr r3, [r7, #4]
8002702: 681b ldr r3, [r3, #0]
8002704: 6959 ldr r1, [r3, #20]
8002706: 687b ldr r3, [r7, #4]
8002708: 681b ldr r3, [r3, #0]
800270a: 683a ldr r2, [r7, #0]
800270c: 430a orrs r2, r1
800270e: 615a str r2, [r3, #20]
/* Return function status */
return HAL_OK;
8002710: 2300 movs r3, #0
8002712: e006 b.n 8002722 <HAL_CAN_ActivateNotification+0x40>
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
8002714: 687b ldr r3, [r7, #4]
8002716: 6a5b ldr r3, [r3, #36] ; 0x24
8002718: f443 2280 orr.w r2, r3, #262144 ; 0x40000
800271c: 687b ldr r3, [r7, #4]
800271e: 625a str r2, [r3, #36] ; 0x24
return HAL_ERROR;
8002720: 2301 movs r3, #1
}
}
8002722: 4618 mov r0, r3
8002724: 3714 adds r7, #20
8002726: 46bd mov sp, r7
8002728: f85d 7b04 ldr.w r7, [sp], #4
800272c: 4770 bx lr
0800272e <HAL_CAN_IRQHandler>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
{
800272e: b580 push {r7, lr}
8002730: b08a sub sp, #40 ; 0x28
8002732: af00 add r7, sp, #0
8002734: 6078 str r0, [r7, #4]
uint32_t errorcode = HAL_CAN_ERROR_NONE;
8002736: 2300 movs r3, #0
8002738: 627b str r3, [r7, #36] ; 0x24
uint32_t interrupts = READ_REG(hcan->Instance->IER);
800273a: 687b ldr r3, [r7, #4]
800273c: 681b ldr r3, [r3, #0]
800273e: 695b ldr r3, [r3, #20]
8002740: 623b str r3, [r7, #32]
uint32_t msrflags = READ_REG(hcan->Instance->MSR);
8002742: 687b ldr r3, [r7, #4]
8002744: 681b ldr r3, [r3, #0]
8002746: 685b ldr r3, [r3, #4]
8002748: 61fb str r3, [r7, #28]
uint32_t tsrflags = READ_REG(hcan->Instance->TSR);
800274a: 687b ldr r3, [r7, #4]
800274c: 681b ldr r3, [r3, #0]
800274e: 689b ldr r3, [r3, #8]
8002750: 61bb str r3, [r7, #24]
uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R);
8002752: 687b ldr r3, [r7, #4]
8002754: 681b ldr r3, [r3, #0]
8002756: 68db ldr r3, [r3, #12]
8002758: 617b str r3, [r7, #20]
uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R);
800275a: 687b ldr r3, [r7, #4]
800275c: 681b ldr r3, [r3, #0]
800275e: 691b ldr r3, [r3, #16]
8002760: 613b str r3, [r7, #16]
uint32_t esrflags = READ_REG(hcan->Instance->ESR);
8002762: 687b ldr r3, [r7, #4]
8002764: 681b ldr r3, [r3, #0]
8002766: 699b ldr r3, [r3, #24]
8002768: 60fb str r3, [r7, #12]
/* Transmit Mailbox empty interrupt management *****************************/
if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U)
800276a: 6a3b ldr r3, [r7, #32]
800276c: f003 0301 and.w r3, r3, #1
8002770: 2b00 cmp r3, #0
8002772: d07c beq.n 800286e <HAL_CAN_IRQHandler+0x140>
{
/* Transmit Mailbox 0 management *****************************************/
if ((tsrflags & CAN_TSR_RQCP0) != 0U)
8002774: 69bb ldr r3, [r7, #24]
8002776: f003 0301 and.w r3, r3, #1
800277a: 2b00 cmp r3, #0
800277c: d023 beq.n 80027c6 <HAL_CAN_IRQHandler+0x98>
{
/* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0);
800277e: 687b ldr r3, [r7, #4]
8002780: 681b ldr r3, [r3, #0]
8002782: 2201 movs r2, #1
8002784: 609a str r2, [r3, #8]
if ((tsrflags & CAN_TSR_TXOK0) != 0U)
8002786: 69bb ldr r3, [r7, #24]
8002788: f003 0302 and.w r3, r3, #2
800278c: 2b00 cmp r3, #0
800278e: d003 beq.n 8002798 <HAL_CAN_IRQHandler+0x6a>
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->TxMailbox0CompleteCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox0CompleteCallback(hcan);
8002790: 6878 ldr r0, [r7, #4]
8002792: f000 f983 bl 8002a9c <HAL_CAN_TxMailbox0CompleteCallback>
8002796: e016 b.n 80027c6 <HAL_CAN_IRQHandler+0x98>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
else
{
if ((tsrflags & CAN_TSR_ALST0) != 0U)
8002798: 69bb ldr r3, [r7, #24]
800279a: f003 0304 and.w r3, r3, #4
800279e: 2b00 cmp r3, #0
80027a0: d004 beq.n 80027ac <HAL_CAN_IRQHandler+0x7e>
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_ALST0;
80027a2: 6a7b ldr r3, [r7, #36] ; 0x24
80027a4: f443 6300 orr.w r3, r3, #2048 ; 0x800
80027a8: 627b str r3, [r7, #36] ; 0x24
80027aa: e00c b.n 80027c6 <HAL_CAN_IRQHandler+0x98>
}
else if ((tsrflags & CAN_TSR_TERR0) != 0U)
80027ac: 69bb ldr r3, [r7, #24]
80027ae: f003 0308 and.w r3, r3, #8
80027b2: 2b00 cmp r3, #0
80027b4: d004 beq.n 80027c0 <HAL_CAN_IRQHandler+0x92>
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_TERR0;
80027b6: 6a7b ldr r3, [r7, #36] ; 0x24
80027b8: f443 5380 orr.w r3, r3, #4096 ; 0x1000
80027bc: 627b str r3, [r7, #36] ; 0x24
80027be: e002 b.n 80027c6 <HAL_CAN_IRQHandler+0x98>
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->TxMailbox0AbortCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox0AbortCallback(hcan);
80027c0: 6878 ldr r0, [r7, #4]
80027c2: f000 f989 bl 8002ad8 <HAL_CAN_TxMailbox0AbortCallback>
}
}
}
/* Transmit Mailbox 1 management *****************************************/
if ((tsrflags & CAN_TSR_RQCP1) != 0U)
80027c6: 69bb ldr r3, [r7, #24]
80027c8: f403 7380 and.w r3, r3, #256 ; 0x100
80027cc: 2b00 cmp r3, #0
80027ce: d024 beq.n 800281a <HAL_CAN_IRQHandler+0xec>
{
/* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1);
80027d0: 687b ldr r3, [r7, #4]
80027d2: 681b ldr r3, [r3, #0]
80027d4: f44f 7280 mov.w r2, #256 ; 0x100
80027d8: 609a str r2, [r3, #8]
if ((tsrflags & CAN_TSR_TXOK1) != 0U)
80027da: 69bb ldr r3, [r7, #24]
80027dc: f403 7300 and.w r3, r3, #512 ; 0x200
80027e0: 2b00 cmp r3, #0
80027e2: d003 beq.n 80027ec <HAL_CAN_IRQHandler+0xbe>
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->TxMailbox1CompleteCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox1CompleteCallback(hcan);
80027e4: 6878 ldr r0, [r7, #4]
80027e6: f000 f963 bl 8002ab0 <HAL_CAN_TxMailbox1CompleteCallback>
80027ea: e016 b.n 800281a <HAL_CAN_IRQHandler+0xec>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
else
{
if ((tsrflags & CAN_TSR_ALST1) != 0U)
80027ec: 69bb ldr r3, [r7, #24]
80027ee: f403 6380 and.w r3, r3, #1024 ; 0x400
80027f2: 2b00 cmp r3, #0
80027f4: d004 beq.n 8002800 <HAL_CAN_IRQHandler+0xd2>
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_ALST1;
80027f6: 6a7b ldr r3, [r7, #36] ; 0x24
80027f8: f443 5300 orr.w r3, r3, #8192 ; 0x2000
80027fc: 627b str r3, [r7, #36] ; 0x24
80027fe: e00c b.n 800281a <HAL_CAN_IRQHandler+0xec>
}
else if ((tsrflags & CAN_TSR_TERR1) != 0U)
8002800: 69bb ldr r3, [r7, #24]
8002802: f403 6300 and.w r3, r3, #2048 ; 0x800
8002806: 2b00 cmp r3, #0
8002808: d004 beq.n 8002814 <HAL_CAN_IRQHandler+0xe6>
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_TERR1;
800280a: 6a7b ldr r3, [r7, #36] ; 0x24
800280c: f443 4380 orr.w r3, r3, #16384 ; 0x4000
8002810: 627b str r3, [r7, #36] ; 0x24
8002812: e002 b.n 800281a <HAL_CAN_IRQHandler+0xec>
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->TxMailbox1AbortCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox1AbortCallback(hcan);
8002814: 6878 ldr r0, [r7, #4]
8002816: f000 f969 bl 8002aec <HAL_CAN_TxMailbox1AbortCallback>
}
}
}
/* Transmit Mailbox 2 management *****************************************/
if ((tsrflags & CAN_TSR_RQCP2) != 0U)
800281a: 69bb ldr r3, [r7, #24]
800281c: f403 3380 and.w r3, r3, #65536 ; 0x10000
8002820: 2b00 cmp r3, #0
8002822: d024 beq.n 800286e <HAL_CAN_IRQHandler+0x140>
{
/* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2);
8002824: 687b ldr r3, [r7, #4]
8002826: 681b ldr r3, [r3, #0]
8002828: f44f 3280 mov.w r2, #65536 ; 0x10000
800282c: 609a str r2, [r3, #8]
if ((tsrflags & CAN_TSR_TXOK2) != 0U)
800282e: 69bb ldr r3, [r7, #24]
8002830: f403 3300 and.w r3, r3, #131072 ; 0x20000
8002834: 2b00 cmp r3, #0
8002836: d003 beq.n 8002840 <HAL_CAN_IRQHandler+0x112>
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->TxMailbox2CompleteCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox2CompleteCallback(hcan);
8002838: 6878 ldr r0, [r7, #4]
800283a: f000 f943 bl 8002ac4 <HAL_CAN_TxMailbox2CompleteCallback>
800283e: e016 b.n 800286e <HAL_CAN_IRQHandler+0x140>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
else
{
if ((tsrflags & CAN_TSR_ALST2) != 0U)
8002840: 69bb ldr r3, [r7, #24]
8002842: f403 2380 and.w r3, r3, #262144 ; 0x40000
8002846: 2b00 cmp r3, #0
8002848: d004 beq.n 8002854 <HAL_CAN_IRQHandler+0x126>
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_ALST2;
800284a: 6a7b ldr r3, [r7, #36] ; 0x24
800284c: f443 4300 orr.w r3, r3, #32768 ; 0x8000
8002850: 627b str r3, [r7, #36] ; 0x24
8002852: e00c b.n 800286e <HAL_CAN_IRQHandler+0x140>
}
else if ((tsrflags & CAN_TSR_TERR2) != 0U)
8002854: 69bb ldr r3, [r7, #24]
8002856: f403 2300 and.w r3, r3, #524288 ; 0x80000
800285a: 2b00 cmp r3, #0
800285c: d004 beq.n 8002868 <HAL_CAN_IRQHandler+0x13a>
{
/* Update error code */
errorcode |= HAL_CAN_ERROR_TX_TERR2;
800285e: 6a7b ldr r3, [r7, #36] ; 0x24
8002860: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8002864: 627b str r3, [r7, #36] ; 0x24
8002866: e002 b.n 800286e <HAL_CAN_IRQHandler+0x140>
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->TxMailbox2AbortCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_TxMailbox2AbortCallback(hcan);
8002868: 6878 ldr r0, [r7, #4]
800286a: f000 f949 bl 8002b00 <HAL_CAN_TxMailbox2AbortCallback>
}
}
}
/* Receive FIFO 0 overrun interrupt management *****************************/
if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U)
800286e: 6a3b ldr r3, [r7, #32]
8002870: f003 0308 and.w r3, r3, #8
8002874: 2b00 cmp r3, #0
8002876: d00c beq.n 8002892 <HAL_CAN_IRQHandler+0x164>
{
if ((rf0rflags & CAN_RF0R_FOVR0) != 0U)
8002878: 697b ldr r3, [r7, #20]
800287a: f003 0310 and.w r3, r3, #16
800287e: 2b00 cmp r3, #0
8002880: d007 beq.n 8002892 <HAL_CAN_IRQHandler+0x164>
{
/* Set CAN error code to Rx Fifo 0 overrun error */
errorcode |= HAL_CAN_ERROR_RX_FOV0;
8002882: 6a7b ldr r3, [r7, #36] ; 0x24
8002884: f443 7300 orr.w r3, r3, #512 ; 0x200
8002888: 627b str r3, [r7, #36] ; 0x24
/* Clear FIFO0 Overrun Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0);
800288a: 687b ldr r3, [r7, #4]
800288c: 681b ldr r3, [r3, #0]
800288e: 2210 movs r2, #16
8002890: 60da str r2, [r3, #12]
}
}
/* Receive FIFO 0 full interrupt management ********************************/
if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U)
8002892: 6a3b ldr r3, [r7, #32]
8002894: f003 0304 and.w r3, r3, #4
8002898: 2b00 cmp r3, #0
800289a: d00b beq.n 80028b4 <HAL_CAN_IRQHandler+0x186>
{
if ((rf0rflags & CAN_RF0R_FULL0) != 0U)
800289c: 697b ldr r3, [r7, #20]
800289e: f003 0308 and.w r3, r3, #8
80028a2: 2b00 cmp r3, #0
80028a4: d006 beq.n 80028b4 <HAL_CAN_IRQHandler+0x186>
{
/* Clear FIFO 0 full Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0);
80028a6: 687b ldr r3, [r7, #4]
80028a8: 681b ldr r3, [r3, #0]
80028aa: 2208 movs r2, #8
80028ac: 60da str r2, [r3, #12]
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->RxFifo0FullCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_RxFifo0FullCallback(hcan);
80028ae: 6878 ldr r0, [r7, #4]
80028b0: f000 f930 bl 8002b14 <HAL_CAN_RxFifo0FullCallback>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* Receive FIFO 0 message pending interrupt management *********************/
if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U)
80028b4: 6a3b ldr r3, [r7, #32]
80028b6: f003 0302 and.w r3, r3, #2
80028ba: 2b00 cmp r3, #0
80028bc: d009 beq.n 80028d2 <HAL_CAN_IRQHandler+0x1a4>
{
/* Check if message is still pending */
if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U)
80028be: 687b ldr r3, [r7, #4]
80028c0: 681b ldr r3, [r3, #0]
80028c2: 68db ldr r3, [r3, #12]
80028c4: f003 0303 and.w r3, r3, #3
80028c8: 2b00 cmp r3, #0
80028ca: d002 beq.n 80028d2 <HAL_CAN_IRQHandler+0x1a4>
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->RxFifo0MsgPendingCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_RxFifo0MsgPendingCallback(hcan);
80028cc: 6878 ldr r0, [r7, #4]
80028ce: f7fd fe77 bl 80005c0 <HAL_CAN_RxFifo0MsgPendingCallback>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* Receive FIFO 1 overrun interrupt management *****************************/
if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U)
80028d2: 6a3b ldr r3, [r7, #32]
80028d4: f003 0340 and.w r3, r3, #64 ; 0x40
80028d8: 2b00 cmp r3, #0
80028da: d00c beq.n 80028f6 <HAL_CAN_IRQHandler+0x1c8>
{
if ((rf1rflags & CAN_RF1R_FOVR1) != 0U)
80028dc: 693b ldr r3, [r7, #16]
80028de: f003 0310 and.w r3, r3, #16
80028e2: 2b00 cmp r3, #0
80028e4: d007 beq.n 80028f6 <HAL_CAN_IRQHandler+0x1c8>
{
/* Set CAN error code to Rx Fifo 1 overrun error */
errorcode |= HAL_CAN_ERROR_RX_FOV1;
80028e6: 6a7b ldr r3, [r7, #36] ; 0x24
80028e8: f443 6380 orr.w r3, r3, #1024 ; 0x400
80028ec: 627b str r3, [r7, #36] ; 0x24
/* Clear FIFO1 Overrun Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1);
80028ee: 687b ldr r3, [r7, #4]
80028f0: 681b ldr r3, [r3, #0]
80028f2: 2210 movs r2, #16
80028f4: 611a str r2, [r3, #16]
}
}
/* Receive FIFO 1 full interrupt management ********************************/
if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U)
80028f6: 6a3b ldr r3, [r7, #32]
80028f8: f003 0320 and.w r3, r3, #32
80028fc: 2b00 cmp r3, #0
80028fe: d00b beq.n 8002918 <HAL_CAN_IRQHandler+0x1ea>
{
if ((rf1rflags & CAN_RF1R_FULL1) != 0U)
8002900: 693b ldr r3, [r7, #16]
8002902: f003 0308 and.w r3, r3, #8
8002906: 2b00 cmp r3, #0
8002908: d006 beq.n 8002918 <HAL_CAN_IRQHandler+0x1ea>
{
/* Clear FIFO 1 full Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1);
800290a: 687b ldr r3, [r7, #4]
800290c: 681b ldr r3, [r3, #0]
800290e: 2208 movs r2, #8
8002910: 611a str r2, [r3, #16]
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->RxFifo1FullCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_RxFifo1FullCallback(hcan);
8002912: 6878 ldr r0, [r7, #4]
8002914: f000 f912 bl 8002b3c <HAL_CAN_RxFifo1FullCallback>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* Receive FIFO 1 message pending interrupt management *********************/
if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U)
8002918: 6a3b ldr r3, [r7, #32]
800291a: f003 0310 and.w r3, r3, #16
800291e: 2b00 cmp r3, #0
8002920: d009 beq.n 8002936 <HAL_CAN_IRQHandler+0x208>
{
/* Check if message is still pending */
if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U)
8002922: 687b ldr r3, [r7, #4]
8002924: 681b ldr r3, [r3, #0]
8002926: 691b ldr r3, [r3, #16]
8002928: f003 0303 and.w r3, r3, #3
800292c: 2b00 cmp r3, #0
800292e: d002 beq.n 8002936 <HAL_CAN_IRQHandler+0x208>
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->RxFifo1MsgPendingCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_RxFifo1MsgPendingCallback(hcan);
8002930: 6878 ldr r0, [r7, #4]
8002932: f000 f8f9 bl 8002b28 <HAL_CAN_RxFifo1MsgPendingCallback>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* Sleep interrupt management *********************************************/
if ((interrupts & CAN_IT_SLEEP_ACK) != 0U)
8002936: 6a3b ldr r3, [r7, #32]
8002938: f403 3300 and.w r3, r3, #131072 ; 0x20000
800293c: 2b00 cmp r3, #0
800293e: d00b beq.n 8002958 <HAL_CAN_IRQHandler+0x22a>
{
if ((msrflags & CAN_MSR_SLAKI) != 0U)
8002940: 69fb ldr r3, [r7, #28]
8002942: f003 0310 and.w r3, r3, #16
8002946: 2b00 cmp r3, #0
8002948: d006 beq.n 8002958 <HAL_CAN_IRQHandler+0x22a>
{
/* Clear Sleep interrupt Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI);
800294a: 687b ldr r3, [r7, #4]
800294c: 681b ldr r3, [r3, #0]
800294e: 2210 movs r2, #16
8002950: 605a str r2, [r3, #4]
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->SleepCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_SleepCallback(hcan);
8002952: 6878 ldr r0, [r7, #4]
8002954: f000 f8fc bl 8002b50 <HAL_CAN_SleepCallback>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* WakeUp interrupt management *********************************************/
if ((interrupts & CAN_IT_WAKEUP) != 0U)
8002958: 6a3b ldr r3, [r7, #32]
800295a: f403 3380 and.w r3, r3, #65536 ; 0x10000
800295e: 2b00 cmp r3, #0
8002960: d00b beq.n 800297a <HAL_CAN_IRQHandler+0x24c>
{
if ((msrflags & CAN_MSR_WKUI) != 0U)
8002962: 69fb ldr r3, [r7, #28]
8002964: f003 0308 and.w r3, r3, #8
8002968: 2b00 cmp r3, #0
800296a: d006 beq.n 800297a <HAL_CAN_IRQHandler+0x24c>
{
/* Clear WakeUp Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU);
800296c: 687b ldr r3, [r7, #4]
800296e: 681b ldr r3, [r3, #0]
8002970: 2208 movs r2, #8
8002972: 605a str r2, [r3, #4]
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->WakeUpFromRxMsgCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_WakeUpFromRxMsgCallback(hcan);
8002974: 6878 ldr r0, [r7, #4]
8002976: f000 f8f5 bl 8002b64 <HAL_CAN_WakeUpFromRxMsgCallback>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
/* Error interrupts management *********************************************/
if ((interrupts & CAN_IT_ERROR) != 0U)
800297a: 6a3b ldr r3, [r7, #32]
800297c: f403 4300 and.w r3, r3, #32768 ; 0x8000
8002980: 2b00 cmp r3, #0
8002982: d07b beq.n 8002a7c <HAL_CAN_IRQHandler+0x34e>
{
if ((msrflags & CAN_MSR_ERRI) != 0U)
8002984: 69fb ldr r3, [r7, #28]
8002986: f003 0304 and.w r3, r3, #4
800298a: 2b00 cmp r3, #0
800298c: d072 beq.n 8002a74 <HAL_CAN_IRQHandler+0x346>
{
/* Check Error Warning Flag */
if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) &&
800298e: 6a3b ldr r3, [r7, #32]
8002990: f403 7380 and.w r3, r3, #256 ; 0x100
8002994: 2b00 cmp r3, #0
8002996: d008 beq.n 80029aa <HAL_CAN_IRQHandler+0x27c>
((esrflags & CAN_ESR_EWGF) != 0U))
8002998: 68fb ldr r3, [r7, #12]
800299a: f003 0301 and.w r3, r3, #1
if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) &&
800299e: 2b00 cmp r3, #0
80029a0: d003 beq.n 80029aa <HAL_CAN_IRQHandler+0x27c>
{
/* Set CAN error code to Error Warning */
errorcode |= HAL_CAN_ERROR_EWG;
80029a2: 6a7b ldr r3, [r7, #36] ; 0x24
80029a4: f043 0301 orr.w r3, r3, #1
80029a8: 627b str r3, [r7, #36] ; 0x24
/* No need for clear of Error Warning Flag as read-only */
}
/* Check Error Passive Flag */
if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) &&
80029aa: 6a3b ldr r3, [r7, #32]
80029ac: f403 7300 and.w r3, r3, #512 ; 0x200
80029b0: 2b00 cmp r3, #0
80029b2: d008 beq.n 80029c6 <HAL_CAN_IRQHandler+0x298>
((esrflags & CAN_ESR_EPVF) != 0U))
80029b4: 68fb ldr r3, [r7, #12]
80029b6: f003 0302 and.w r3, r3, #2
if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) &&
80029ba: 2b00 cmp r3, #0
80029bc: d003 beq.n 80029c6 <HAL_CAN_IRQHandler+0x298>
{
/* Set CAN error code to Error Passive */
errorcode |= HAL_CAN_ERROR_EPV;
80029be: 6a7b ldr r3, [r7, #36] ; 0x24
80029c0: f043 0302 orr.w r3, r3, #2
80029c4: 627b str r3, [r7, #36] ; 0x24
/* No need for clear of Error Passive Flag as read-only */
}
/* Check Bus-off Flag */
if (((interrupts & CAN_IT_BUSOFF) != 0U) &&
80029c6: 6a3b ldr r3, [r7, #32]
80029c8: f403 6380 and.w r3, r3, #1024 ; 0x400
80029cc: 2b00 cmp r3, #0
80029ce: d008 beq.n 80029e2 <HAL_CAN_IRQHandler+0x2b4>
((esrflags & CAN_ESR_BOFF) != 0U))
80029d0: 68fb ldr r3, [r7, #12]
80029d2: f003 0304 and.w r3, r3, #4
if (((interrupts & CAN_IT_BUSOFF) != 0U) &&
80029d6: 2b00 cmp r3, #0
80029d8: d003 beq.n 80029e2 <HAL_CAN_IRQHandler+0x2b4>
{
/* Set CAN error code to Bus-Off */
errorcode |= HAL_CAN_ERROR_BOF;
80029da: 6a7b ldr r3, [r7, #36] ; 0x24
80029dc: f043 0304 orr.w r3, r3, #4
80029e0: 627b str r3, [r7, #36] ; 0x24
/* No need for clear of Error Bus-Off as read-only */
}
/* Check Last Error Code Flag */
if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) &&
80029e2: 6a3b ldr r3, [r7, #32]
80029e4: f403 6300 and.w r3, r3, #2048 ; 0x800
80029e8: 2b00 cmp r3, #0
80029ea: d043 beq.n 8002a74 <HAL_CAN_IRQHandler+0x346>
((esrflags & CAN_ESR_LEC) != 0U))
80029ec: 68fb ldr r3, [r7, #12]
80029ee: f003 0370 and.w r3, r3, #112 ; 0x70
if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) &&
80029f2: 2b00 cmp r3, #0
80029f4: d03e beq.n 8002a74 <HAL_CAN_IRQHandler+0x346>
{
switch (esrflags & CAN_ESR_LEC)
80029f6: 68fb ldr r3, [r7, #12]
80029f8: f003 0370 and.w r3, r3, #112 ; 0x70
80029fc: 2b60 cmp r3, #96 ; 0x60
80029fe: d02b beq.n 8002a58 <HAL_CAN_IRQHandler+0x32a>
8002a00: 2b60 cmp r3, #96 ; 0x60
8002a02: d82e bhi.n 8002a62 <HAL_CAN_IRQHandler+0x334>
8002a04: 2b50 cmp r3, #80 ; 0x50
8002a06: d022 beq.n 8002a4e <HAL_CAN_IRQHandler+0x320>
8002a08: 2b50 cmp r3, #80 ; 0x50
8002a0a: d82a bhi.n 8002a62 <HAL_CAN_IRQHandler+0x334>
8002a0c: 2b40 cmp r3, #64 ; 0x40
8002a0e: d019 beq.n 8002a44 <HAL_CAN_IRQHandler+0x316>
8002a10: 2b40 cmp r3, #64 ; 0x40
8002a12: d826 bhi.n 8002a62 <HAL_CAN_IRQHandler+0x334>
8002a14: 2b30 cmp r3, #48 ; 0x30
8002a16: d010 beq.n 8002a3a <HAL_CAN_IRQHandler+0x30c>
8002a18: 2b30 cmp r3, #48 ; 0x30
8002a1a: d822 bhi.n 8002a62 <HAL_CAN_IRQHandler+0x334>
8002a1c: 2b10 cmp r3, #16
8002a1e: d002 beq.n 8002a26 <HAL_CAN_IRQHandler+0x2f8>
8002a20: 2b20 cmp r3, #32
8002a22: d005 beq.n 8002a30 <HAL_CAN_IRQHandler+0x302>
case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
/* Set CAN error code to CRC error */
errorcode |= HAL_CAN_ERROR_CRC;
break;
default:
break;
8002a24: e01d b.n 8002a62 <HAL_CAN_IRQHandler+0x334>
errorcode |= HAL_CAN_ERROR_STF;
8002a26: 6a7b ldr r3, [r7, #36] ; 0x24
8002a28: f043 0308 orr.w r3, r3, #8
8002a2c: 627b str r3, [r7, #36] ; 0x24
break;
8002a2e: e019 b.n 8002a64 <HAL_CAN_IRQHandler+0x336>
errorcode |= HAL_CAN_ERROR_FOR;
8002a30: 6a7b ldr r3, [r7, #36] ; 0x24
8002a32: f043 0310 orr.w r3, r3, #16
8002a36: 627b str r3, [r7, #36] ; 0x24
break;
8002a38: e014 b.n 8002a64 <HAL_CAN_IRQHandler+0x336>
errorcode |= HAL_CAN_ERROR_ACK;
8002a3a: 6a7b ldr r3, [r7, #36] ; 0x24
8002a3c: f043 0320 orr.w r3, r3, #32
8002a40: 627b str r3, [r7, #36] ; 0x24
break;
8002a42: e00f b.n 8002a64 <HAL_CAN_IRQHandler+0x336>
errorcode |= HAL_CAN_ERROR_BR;
8002a44: 6a7b ldr r3, [r7, #36] ; 0x24
8002a46: f043 0340 orr.w r3, r3, #64 ; 0x40
8002a4a: 627b str r3, [r7, #36] ; 0x24
break;
8002a4c: e00a b.n 8002a64 <HAL_CAN_IRQHandler+0x336>
errorcode |= HAL_CAN_ERROR_BD;
8002a4e: 6a7b ldr r3, [r7, #36] ; 0x24
8002a50: f043 0380 orr.w r3, r3, #128 ; 0x80
8002a54: 627b str r3, [r7, #36] ; 0x24
break;
8002a56: e005 b.n 8002a64 <HAL_CAN_IRQHandler+0x336>
errorcode |= HAL_CAN_ERROR_CRC;
8002a58: 6a7b ldr r3, [r7, #36] ; 0x24
8002a5a: f443 7380 orr.w r3, r3, #256 ; 0x100
8002a5e: 627b str r3, [r7, #36] ; 0x24
break;
8002a60: e000 b.n 8002a64 <HAL_CAN_IRQHandler+0x336>
break;
8002a62: bf00 nop
}
/* Clear Last error code Flag */
CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC);
8002a64: 687b ldr r3, [r7, #4]
8002a66: 681b ldr r3, [r3, #0]
8002a68: 699a ldr r2, [r3, #24]
8002a6a: 687b ldr r3, [r7, #4]
8002a6c: 681b ldr r3, [r3, #0]
8002a6e: f022 0270 bic.w r2, r2, #112 ; 0x70
8002a72: 619a str r2, [r3, #24]
}
}
/* Clear ERRI Flag */
__HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI);
8002a74: 687b ldr r3, [r7, #4]
8002a76: 681b ldr r3, [r3, #0]
8002a78: 2204 movs r2, #4
8002a7a: 605a str r2, [r3, #4]
}
/* Call the Error call Back in case of Errors */
if (errorcode != HAL_CAN_ERROR_NONE)
8002a7c: 6a7b ldr r3, [r7, #36] ; 0x24
8002a7e: 2b00 cmp r3, #0
8002a80: d008 beq.n 8002a94 <HAL_CAN_IRQHandler+0x366>
{
/* Update error code in handle */
hcan->ErrorCode |= errorcode;
8002a82: 687b ldr r3, [r7, #4]
8002a84: 6a5a ldr r2, [r3, #36] ; 0x24
8002a86: 6a7b ldr r3, [r7, #36] ; 0x24
8002a88: 431a orrs r2, r3
8002a8a: 687b ldr r3, [r7, #4]
8002a8c: 625a str r2, [r3, #36] ; 0x24
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Call registered callback*/
hcan->ErrorCallback(hcan);
#else
/* Call weak (surcharged) callback */
HAL_CAN_ErrorCallback(hcan);
8002a8e: 6878 ldr r0, [r7, #4]
8002a90: f000 f872 bl 8002b78 <HAL_CAN_ErrorCallback>
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
}
}
8002a94: bf00 nop
8002a96: 3728 adds r7, #40 ; 0x28
8002a98: 46bd mov sp, r7
8002a9a: bd80 pop {r7, pc}
08002a9c <HAL_CAN_TxMailbox0CompleteCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan)
{
8002a9c: b480 push {r7}
8002a9e: b083 sub sp, #12
8002aa0: af00 add r7, sp, #0
8002aa2: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the
user file
*/
}
8002aa4: bf00 nop
8002aa6: 370c adds r7, #12
8002aa8: 46bd mov sp, r7
8002aaa: f85d 7b04 ldr.w r7, [sp], #4
8002aae: 4770 bx lr
08002ab0 <HAL_CAN_TxMailbox1CompleteCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan)
{
8002ab0: b480 push {r7}
8002ab2: b083 sub sp, #12
8002ab4: af00 add r7, sp, #0
8002ab6: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the
user file
*/
}
8002ab8: bf00 nop
8002aba: 370c adds r7, #12
8002abc: 46bd mov sp, r7
8002abe: f85d 7b04 ldr.w r7, [sp], #4
8002ac2: 4770 bx lr
08002ac4 <HAL_CAN_TxMailbox2CompleteCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan)
{
8002ac4: b480 push {r7}
8002ac6: b083 sub sp, #12
8002ac8: af00 add r7, sp, #0
8002aca: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the
user file
*/
}
8002acc: bf00 nop
8002ace: 370c adds r7, #12
8002ad0: 46bd mov sp, r7
8002ad2: f85d 7b04 ldr.w r7, [sp], #4
8002ad6: 4770 bx lr
08002ad8 <HAL_CAN_TxMailbox0AbortCallback>:
* @param hcan pointer to an CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan)
{
8002ad8: b480 push {r7}
8002ada: b083 sub sp, #12
8002adc: af00 add r7, sp, #0
8002ade: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_TxMailbox0AbortCallback could be implemented in the
user file
*/
}
8002ae0: bf00 nop
8002ae2: 370c adds r7, #12
8002ae4: 46bd mov sp, r7
8002ae6: f85d 7b04 ldr.w r7, [sp], #4
8002aea: 4770 bx lr
08002aec <HAL_CAN_TxMailbox1AbortCallback>:
* @param hcan pointer to an CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan)
{
8002aec: b480 push {r7}
8002aee: b083 sub sp, #12
8002af0: af00 add r7, sp, #0
8002af2: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_TxMailbox1AbortCallback could be implemented in the
user file
*/
}
8002af4: bf00 nop
8002af6: 370c adds r7, #12
8002af8: 46bd mov sp, r7
8002afa: f85d 7b04 ldr.w r7, [sp], #4
8002afe: 4770 bx lr
08002b00 <HAL_CAN_TxMailbox2AbortCallback>:
* @param hcan pointer to an CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan)
{
8002b00: b480 push {r7}
8002b02: b083 sub sp, #12
8002b04: af00 add r7, sp, #0
8002b06: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_TxMailbox2AbortCallback could be implemented in the
user file
*/
}
8002b08: bf00 nop
8002b0a: 370c adds r7, #12
8002b0c: 46bd mov sp, r7
8002b0e: f85d 7b04 ldr.w r7, [sp], #4
8002b12: 4770 bx lr
08002b14 <HAL_CAN_RxFifo0FullCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan)
{
8002b14: b480 push {r7}
8002b16: b083 sub sp, #12
8002b18: af00 add r7, sp, #0
8002b1a: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_RxFifo0FullCallback could be implemented in the user
file
*/
}
8002b1c: bf00 nop
8002b1e: 370c adds r7, #12
8002b20: 46bd mov sp, r7
8002b22: f85d 7b04 ldr.w r7, [sp], #4
8002b26: 4770 bx lr
08002b28 <HAL_CAN_RxFifo1MsgPendingCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan)
{
8002b28: b480 push {r7}
8002b2a: b083 sub sp, #12
8002b2c: af00 add r7, sp, #0
8002b2e: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_RxFifo1MsgPendingCallback could be implemented in the
user file
*/
}
8002b30: bf00 nop
8002b32: 370c adds r7, #12
8002b34: 46bd mov sp, r7
8002b36: f85d 7b04 ldr.w r7, [sp], #4
8002b3a: 4770 bx lr
08002b3c <HAL_CAN_RxFifo1FullCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan)
{
8002b3c: b480 push {r7}
8002b3e: b083 sub sp, #12
8002b40: af00 add r7, sp, #0
8002b42: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_RxFifo1FullCallback could be implemented in the user
file
*/
}
8002b44: bf00 nop
8002b46: 370c adds r7, #12
8002b48: 46bd mov sp, r7
8002b4a: f85d 7b04 ldr.w r7, [sp], #4
8002b4e: 4770 bx lr
08002b50 <HAL_CAN_SleepCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan)
{
8002b50: b480 push {r7}
8002b52: b083 sub sp, #12
8002b54: af00 add r7, sp, #0
8002b56: 6078 str r0, [r7, #4]
UNUSED(hcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_SleepCallback could be implemented in the user file
*/
}
8002b58: bf00 nop
8002b5a: 370c adds r7, #12
8002b5c: 46bd mov sp, r7
8002b5e: f85d 7b04 ldr.w r7, [sp], #4
8002b62: 4770 bx lr
08002b64 <HAL_CAN_WakeUpFromRxMsgCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan)
{
8002b64: b480 push {r7}
8002b66: b083 sub sp, #12
8002b68: af00 add r7, sp, #0
8002b6a: 6078 str r0, [r7, #4]
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the
user file
*/
}
8002b6c: bf00 nop
8002b6e: 370c adds r7, #12
8002b70: 46bd mov sp, r7
8002b72: f85d 7b04 ldr.w r7, [sp], #4
8002b76: 4770 bx lr
08002b78 <HAL_CAN_ErrorCallback>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
{
8002b78: b480 push {r7}
8002b7a: b083 sub sp, #12
8002b7c: af00 add r7, sp, #0
8002b7e: 6078 str r0, [r7, #4]
UNUSED(hcan);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_ErrorCallback could be implemented in the user file
*/
}
8002b80: bf00 nop
8002b82: 370c adds r7, #12
8002b84: 46bd mov sp, r7
8002b86: f85d 7b04 ldr.w r7, [sp], #4
8002b8a: 4770 bx lr
08002b8c <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8002b8c: b480 push {r7}
8002b8e: b085 sub sp, #20
8002b90: af00 add r7, sp, #0
8002b92: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8002b94: 687b ldr r3, [r7, #4]
8002b96: f003 0307 and.w r3, r3, #7
8002b9a: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
8002b9c: 4b0c ldr r3, [pc, #48] ; (8002bd0 <__NVIC_SetPriorityGrouping+0x44>)
8002b9e: 68db ldr r3, [r3, #12]
8002ba0: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
8002ba2: 68ba ldr r2, [r7, #8]
8002ba4: f64f 03ff movw r3, #63743 ; 0xf8ff
8002ba8: 4013 ands r3, r2
8002baa: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
8002bac: 68fb ldr r3, [r7, #12]
8002bae: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
8002bb0: 68bb ldr r3, [r7, #8]
8002bb2: 4313 orrs r3, r2
reg_value = (reg_value |
8002bb4: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000
8002bb8: f443 3300 orr.w r3, r3, #131072 ; 0x20000
8002bbc: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
8002bbe: 4a04 ldr r2, [pc, #16] ; (8002bd0 <__NVIC_SetPriorityGrouping+0x44>)
8002bc0: 68bb ldr r3, [r7, #8]
8002bc2: 60d3 str r3, [r2, #12]
}
8002bc4: bf00 nop
8002bc6: 3714 adds r7, #20
8002bc8: 46bd mov sp, r7
8002bca: f85d 7b04 ldr.w r7, [sp], #4
8002bce: 4770 bx lr
8002bd0: e000ed00 .word 0xe000ed00
08002bd4 <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
8002bd4: b480 push {r7}
8002bd6: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
8002bd8: 4b04 ldr r3, [pc, #16] ; (8002bec <__NVIC_GetPriorityGrouping+0x18>)
8002bda: 68db ldr r3, [r3, #12]
8002bdc: 0a1b lsrs r3, r3, #8
8002bde: f003 0307 and.w r3, r3, #7
}
8002be2: 4618 mov r0, r3
8002be4: 46bd mov sp, r7
8002be6: f85d 7b04 ldr.w r7, [sp], #4
8002bea: 4770 bx lr
8002bec: e000ed00 .word 0xe000ed00
08002bf0 <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
8002bf0: b480 push {r7}
8002bf2: b083 sub sp, #12
8002bf4: af00 add r7, sp, #0
8002bf6: 4603 mov r3, r0
8002bf8: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8002bfa: f997 3007 ldrsb.w r3, [r7, #7]
8002bfe: 2b00 cmp r3, #0
8002c00: db0b blt.n 8002c1a <__NVIC_EnableIRQ+0x2a>
{
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
8002c02: 79fb ldrb r3, [r7, #7]
8002c04: f003 021f and.w r2, r3, #31
8002c08: 4907 ldr r1, [pc, #28] ; (8002c28 <__NVIC_EnableIRQ+0x38>)
8002c0a: f997 3007 ldrsb.w r3, [r7, #7]
8002c0e: 095b lsrs r3, r3, #5
8002c10: 2001 movs r0, #1
8002c12: fa00 f202 lsl.w r2, r0, r2
8002c16: f841 2023 str.w r2, [r1, r3, lsl #2]
}
}
8002c1a: bf00 nop
8002c1c: 370c adds r7, #12
8002c1e: 46bd mov sp, r7
8002c20: f85d 7b04 ldr.w r7, [sp], #4
8002c24: 4770 bx lr
8002c26: bf00 nop
8002c28: e000e100 .word 0xe000e100
08002c2c <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8002c2c: b480 push {r7}
8002c2e: b083 sub sp, #12
8002c30: af00 add r7, sp, #0
8002c32: 4603 mov r3, r0
8002c34: 6039 str r1, [r7, #0]
8002c36: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8002c38: f997 3007 ldrsb.w r3, [r7, #7]
8002c3c: 2b00 cmp r3, #0
8002c3e: db0a blt.n 8002c56 <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8002c40: 683b ldr r3, [r7, #0]
8002c42: b2da uxtb r2, r3
8002c44: 490c ldr r1, [pc, #48] ; (8002c78 <__NVIC_SetPriority+0x4c>)
8002c46: f997 3007 ldrsb.w r3, [r7, #7]
8002c4a: 0112 lsls r2, r2, #4
8002c4c: b2d2 uxtb r2, r2
8002c4e: 440b add r3, r1
8002c50: f883 2300 strb.w r2, [r3, #768] ; 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
8002c54: e00a b.n 8002c6c <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8002c56: 683b ldr r3, [r7, #0]
8002c58: b2da uxtb r2, r3
8002c5a: 4908 ldr r1, [pc, #32] ; (8002c7c <__NVIC_SetPriority+0x50>)
8002c5c: 79fb ldrb r3, [r7, #7]
8002c5e: f003 030f and.w r3, r3, #15
8002c62: 3b04 subs r3, #4
8002c64: 0112 lsls r2, r2, #4
8002c66: b2d2 uxtb r2, r2
8002c68: 440b add r3, r1
8002c6a: 761a strb r2, [r3, #24]
}
8002c6c: bf00 nop
8002c6e: 370c adds r7, #12
8002c70: 46bd mov sp, r7
8002c72: f85d 7b04 ldr.w r7, [sp], #4
8002c76: 4770 bx lr
8002c78: e000e100 .word 0xe000e100
8002c7c: e000ed00 .word 0xe000ed00
08002c80 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
8002c80: b480 push {r7}
8002c82: b089 sub sp, #36 ; 0x24
8002c84: af00 add r7, sp, #0
8002c86: 60f8 str r0, [r7, #12]
8002c88: 60b9 str r1, [r7, #8]
8002c8a: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8002c8c: 68fb ldr r3, [r7, #12]
8002c8e: f003 0307 and.w r3, r3, #7
8002c92: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
8002c94: 69fb ldr r3, [r7, #28]
8002c96: f1c3 0307 rsb r3, r3, #7
8002c9a: 2b04 cmp r3, #4
8002c9c: bf28 it cs
8002c9e: 2304 movcs r3, #4
8002ca0: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
8002ca2: 69fb ldr r3, [r7, #28]
8002ca4: 3304 adds r3, #4
8002ca6: 2b06 cmp r3, #6
8002ca8: d902 bls.n 8002cb0 <NVIC_EncodePriority+0x30>
8002caa: 69fb ldr r3, [r7, #28]
8002cac: 3b03 subs r3, #3
8002cae: e000 b.n 8002cb2 <NVIC_EncodePriority+0x32>
8002cb0: 2300 movs r3, #0
8002cb2: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8002cb4: f04f 32ff mov.w r2, #4294967295
8002cb8: 69bb ldr r3, [r7, #24]
8002cba: fa02 f303 lsl.w r3, r2, r3
8002cbe: 43da mvns r2, r3
8002cc0: 68bb ldr r3, [r7, #8]
8002cc2: 401a ands r2, r3
8002cc4: 697b ldr r3, [r7, #20]
8002cc6: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
8002cc8: f04f 31ff mov.w r1, #4294967295
8002ccc: 697b ldr r3, [r7, #20]
8002cce: fa01 f303 lsl.w r3, r1, r3
8002cd2: 43d9 mvns r1, r3
8002cd4: 687b ldr r3, [r7, #4]
8002cd6: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8002cd8: 4313 orrs r3, r2
);
}
8002cda: 4618 mov r0, r3
8002cdc: 3724 adds r7, #36 ; 0x24
8002cde: 46bd mov sp, r7
8002ce0: f85d 7b04 ldr.w r7, [sp], #4
8002ce4: 4770 bx lr
...
08002ce8 <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
8002ce8: b580 push {r7, lr}
8002cea: b082 sub sp, #8
8002cec: af00 add r7, sp, #0
8002cee: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
8002cf0: 687b ldr r3, [r7, #4]
8002cf2: 3b01 subs r3, #1
8002cf4: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
8002cf8: d301 bcc.n 8002cfe <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
8002cfa: 2301 movs r3, #1
8002cfc: e00f b.n 8002d1e <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
8002cfe: 4a0a ldr r2, [pc, #40] ; (8002d28 <SysTick_Config+0x40>)
8002d00: 687b ldr r3, [r7, #4]
8002d02: 3b01 subs r3, #1
8002d04: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
8002d06: 210f movs r1, #15
8002d08: f04f 30ff mov.w r0, #4294967295
8002d0c: f7ff ff8e bl 8002c2c <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
8002d10: 4b05 ldr r3, [pc, #20] ; (8002d28 <SysTick_Config+0x40>)
8002d12: 2200 movs r2, #0
8002d14: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
8002d16: 4b04 ldr r3, [pc, #16] ; (8002d28 <SysTick_Config+0x40>)
8002d18: 2207 movs r2, #7
8002d1a: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
8002d1c: 2300 movs r3, #0
}
8002d1e: 4618 mov r0, r3
8002d20: 3708 adds r7, #8
8002d22: 46bd mov sp, r7
8002d24: bd80 pop {r7, pc}
8002d26: bf00 nop
8002d28: e000e010 .word 0xe000e010
08002d2c <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8002d2c: b580 push {r7, lr}
8002d2e: b082 sub sp, #8
8002d30: af00 add r7, sp, #0
8002d32: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
8002d34: 6878 ldr r0, [r7, #4]
8002d36: f7ff ff29 bl 8002b8c <__NVIC_SetPriorityGrouping>
}
8002d3a: bf00 nop
8002d3c: 3708 adds r7, #8
8002d3e: 46bd mov sp, r7
8002d40: bd80 pop {r7, pc}
08002d42 <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8002d42: b580 push {r7, lr}
8002d44: b086 sub sp, #24
8002d46: af00 add r7, sp, #0
8002d48: 4603 mov r3, r0
8002d4a: 60b9 str r1, [r7, #8]
8002d4c: 607a str r2, [r7, #4]
8002d4e: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00U;
8002d50: 2300 movs r3, #0
8002d52: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
8002d54: f7ff ff3e bl 8002bd4 <__NVIC_GetPriorityGrouping>
8002d58: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
8002d5a: 687a ldr r2, [r7, #4]
8002d5c: 68b9 ldr r1, [r7, #8]
8002d5e: 6978 ldr r0, [r7, #20]
8002d60: f7ff ff8e bl 8002c80 <NVIC_EncodePriority>
8002d64: 4602 mov r2, r0
8002d66: f997 300f ldrsb.w r3, [r7, #15]
8002d6a: 4611 mov r1, r2
8002d6c: 4618 mov r0, r3
8002d6e: f7ff ff5d bl 8002c2c <__NVIC_SetPriority>
}
8002d72: bf00 nop
8002d74: 3718 adds r7, #24
8002d76: 46bd mov sp, r7
8002d78: bd80 pop {r7, pc}
08002d7a <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
8002d7a: b580 push {r7, lr}
8002d7c: b082 sub sp, #8
8002d7e: af00 add r7, sp, #0
8002d80: 4603 mov r3, r0
8002d82: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
8002d84: f997 3007 ldrsb.w r3, [r7, #7]
8002d88: 4618 mov r0, r3
8002d8a: f7ff ff31 bl 8002bf0 <__NVIC_EnableIRQ>
}
8002d8e: bf00 nop
8002d90: 3708 adds r7, #8
8002d92: 46bd mov sp, r7
8002d94: bd80 pop {r7, pc}
08002d96 <HAL_SYSTICK_Config>:
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
8002d96: b580 push {r7, lr}
8002d98: b082 sub sp, #8
8002d9a: af00 add r7, sp, #0
8002d9c: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
8002d9e: 6878 ldr r0, [r7, #4]
8002da0: f7ff ffa2 bl 8002ce8 <SysTick_Config>
8002da4: 4603 mov r3, r0
}
8002da6: 4618 mov r0, r3
8002da8: 3708 adds r7, #8
8002daa: 46bd mov sp, r7
8002dac: bd80 pop {r7, pc}
08002dae <HAL_DMA_Abort>:
* and the Stream will be effectively disabled only after the transfer of
* this single data is finished.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
{
8002dae: b580 push {r7, lr}
8002db0: b084 sub sp, #16
8002db2: af00 add r7, sp, #0
8002db4: 6078 str r0, [r7, #4]
/* calculate DMA base and stream number */
DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
8002db6: 687b ldr r3, [r7, #4]
8002db8: 6d9b ldr r3, [r3, #88] ; 0x58
8002dba: 60fb str r3, [r7, #12]
uint32_t tickstart = HAL_GetTick();
8002dbc: f7ff f854 bl 8001e68 <HAL_GetTick>
8002dc0: 60b8 str r0, [r7, #8]
if(hdma->State != HAL_DMA_STATE_BUSY)
8002dc2: 687b ldr r3, [r7, #4]
8002dc4: f893 3035 ldrb.w r3, [r3, #53] ; 0x35
8002dc8: b2db uxtb r3, r3
8002dca: 2b02 cmp r3, #2
8002dcc: d008 beq.n 8002de0 <HAL_DMA_Abort+0x32>
{
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
8002dce: 687b ldr r3, [r7, #4]
8002dd0: 2280 movs r2, #128 ; 0x80
8002dd2: 655a str r2, [r3, #84] ; 0x54
/* Process Unlocked */
__HAL_UNLOCK(hdma);
8002dd4: 687b ldr r3, [r7, #4]
8002dd6: 2200 movs r2, #0
8002dd8: f883 2034 strb.w r2, [r3, #52] ; 0x34
return HAL_ERROR;
8002ddc: 2301 movs r3, #1
8002dde: e052 b.n 8002e86 <HAL_DMA_Abort+0xd8>
}
else
{
/* Disable all the transfer interrupts */
hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
8002de0: 687b ldr r3, [r7, #4]
8002de2: 681b ldr r3, [r3, #0]
8002de4: 681a ldr r2, [r3, #0]
8002de6: 687b ldr r3, [r7, #4]
8002de8: 681b ldr r3, [r3, #0]
8002dea: f022 0216 bic.w r2, r2, #22
8002dee: 601a str r2, [r3, #0]
hdma->Instance->FCR &= ~(DMA_IT_FE);
8002df0: 687b ldr r3, [r7, #4]
8002df2: 681b ldr r3, [r3, #0]
8002df4: 695a ldr r2, [r3, #20]
8002df6: 687b ldr r3, [r7, #4]
8002df8: 681b ldr r3, [r3, #0]
8002dfa: f022 0280 bic.w r2, r2, #128 ; 0x80
8002dfe: 615a str r2, [r3, #20]
if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
8002e00: 687b ldr r3, [r7, #4]
8002e02: 6c1b ldr r3, [r3, #64] ; 0x40
8002e04: 2b00 cmp r3, #0
8002e06: d103 bne.n 8002e10 <HAL_DMA_Abort+0x62>
8002e08: 687b ldr r3, [r7, #4]
8002e0a: 6c9b ldr r3, [r3, #72] ; 0x48
8002e0c: 2b00 cmp r3, #0
8002e0e: d007 beq.n 8002e20 <HAL_DMA_Abort+0x72>
{
hdma->Instance->CR &= ~(DMA_IT_HT);
8002e10: 687b ldr r3, [r7, #4]
8002e12: 681b ldr r3, [r3, #0]
8002e14: 681a ldr r2, [r3, #0]
8002e16: 687b ldr r3, [r7, #4]
8002e18: 681b ldr r3, [r3, #0]
8002e1a: f022 0208 bic.w r2, r2, #8
8002e1e: 601a str r2, [r3, #0]
}
/* Disable the stream */
__HAL_DMA_DISABLE(hdma);
8002e20: 687b ldr r3, [r7, #4]
8002e22: 681b ldr r3, [r3, #0]
8002e24: 681a ldr r2, [r3, #0]
8002e26: 687b ldr r3, [r7, #4]
8002e28: 681b ldr r3, [r3, #0]
8002e2a: f022 0201 bic.w r2, r2, #1
8002e2e: 601a str r2, [r3, #0]
/* Check if the DMA Stream is effectively disabled */
while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
8002e30: e013 b.n 8002e5a <HAL_DMA_Abort+0xac>
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
8002e32: f7ff f819 bl 8001e68 <HAL_GetTick>
8002e36: 4602 mov r2, r0
8002e38: 68bb ldr r3, [r7, #8]
8002e3a: 1ad3 subs r3, r2, r3
8002e3c: 2b05 cmp r3, #5
8002e3e: d90c bls.n 8002e5a <HAL_DMA_Abort+0xac>
{
/* Update error code */
hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
8002e40: 687b ldr r3, [r7, #4]
8002e42: 2220 movs r2, #32
8002e44: 655a str r2, [r3, #84] ; 0x54
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_TIMEOUT;
8002e46: 687b ldr r3, [r7, #4]
8002e48: 2203 movs r2, #3
8002e4a: f883 2035 strb.w r2, [r3, #53] ; 0x35
/* Process Unlocked */
__HAL_UNLOCK(hdma);
8002e4e: 687b ldr r3, [r7, #4]
8002e50: 2200 movs r2, #0
8002e52: f883 2034 strb.w r2, [r3, #52] ; 0x34
return HAL_TIMEOUT;
8002e56: 2303 movs r3, #3
8002e58: e015 b.n 8002e86 <HAL_DMA_Abort+0xd8>
while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
8002e5a: 687b ldr r3, [r7, #4]
8002e5c: 681b ldr r3, [r3, #0]
8002e5e: 681b ldr r3, [r3, #0]
8002e60: f003 0301 and.w r3, r3, #1
8002e64: 2b00 cmp r3, #0
8002e66: d1e4 bne.n 8002e32 <HAL_DMA_Abort+0x84>
}
}
/* Clear all interrupt flags at correct offset within the register */
regs->IFCR = 0x3FU << hdma->StreamIndex;
8002e68: 687b ldr r3, [r7, #4]
8002e6a: 6ddb ldr r3, [r3, #92] ; 0x5c
8002e6c: 223f movs r2, #63 ; 0x3f
8002e6e: 409a lsls r2, r3
8002e70: 68fb ldr r3, [r7, #12]
8002e72: 609a str r2, [r3, #8]
/* Change the DMA state*/
hdma->State = HAL_DMA_STATE_READY;
8002e74: 687b ldr r3, [r7, #4]
8002e76: 2201 movs r2, #1
8002e78: f883 2035 strb.w r2, [r3, #53] ; 0x35
/* Process Unlocked */
__HAL_UNLOCK(hdma);
8002e7c: 687b ldr r3, [r7, #4]
8002e7e: 2200 movs r2, #0
8002e80: f883 2034 strb.w r2, [r3, #52] ; 0x34
}
return HAL_OK;
8002e84: 2300 movs r3, #0
}
8002e86: 4618 mov r0, r3
8002e88: 3710 adds r7, #16
8002e8a: 46bd mov sp, r7
8002e8c: bd80 pop {r7, pc}
08002e8e <HAL_DMA_Abort_IT>:
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
{
8002e8e: b480 push {r7}
8002e90: b083 sub sp, #12
8002e92: af00 add r7, sp, #0
8002e94: 6078 str r0, [r7, #4]
if(hdma->State != HAL_DMA_STATE_BUSY)
8002e96: 687b ldr r3, [r7, #4]
8002e98: f893 3035 ldrb.w r3, [r3, #53] ; 0x35
8002e9c: b2db uxtb r3, r3
8002e9e: 2b02 cmp r3, #2
8002ea0: d004 beq.n 8002eac <HAL_DMA_Abort_IT+0x1e>
{
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
8002ea2: 687b ldr r3, [r7, #4]
8002ea4: 2280 movs r2, #128 ; 0x80
8002ea6: 655a str r2, [r3, #84] ; 0x54
return HAL_ERROR;
8002ea8: 2301 movs r3, #1
8002eaa: e00c b.n 8002ec6 <HAL_DMA_Abort_IT+0x38>
}
else
{
/* Set Abort State */
hdma->State = HAL_DMA_STATE_ABORT;
8002eac: 687b ldr r3, [r7, #4]
8002eae: 2205 movs r2, #5
8002eb0: f883 2035 strb.w r2, [r3, #53] ; 0x35
/* Disable the stream */
__HAL_DMA_DISABLE(hdma);
8002eb4: 687b ldr r3, [r7, #4]
8002eb6: 681b ldr r3, [r3, #0]
8002eb8: 681a ldr r2, [r3, #0]
8002eba: 687b ldr r3, [r7, #4]
8002ebc: 681b ldr r3, [r3, #0]
8002ebe: f022 0201 bic.w r2, r2, #1
8002ec2: 601a str r2, [r3, #0]
}
return HAL_OK;
8002ec4: 2300 movs r3, #0
}
8002ec6: 4618 mov r0, r3
8002ec8: 370c adds r7, #12
8002eca: 46bd mov sp, r7
8002ecc: f85d 7b04 ldr.w r7, [sp], #4
8002ed0: 4770 bx lr
...
08002ed4 <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
8002ed4: b480 push {r7}
8002ed6: b089 sub sp, #36 ; 0x24
8002ed8: af00 add r7, sp, #0
8002eda: 6078 str r0, [r7, #4]
8002edc: 6039 str r1, [r7, #0]
uint32_t position;
uint32_t ioposition = 0x00U;
8002ede: 2300 movs r3, #0
8002ee0: 617b str r3, [r7, #20]
uint32_t iocurrent = 0x00U;
8002ee2: 2300 movs r3, #0
8002ee4: 613b str r3, [r7, #16]
uint32_t temp = 0x00U;
8002ee6: 2300 movs r3, #0
8002ee8: 61bb str r3, [r7, #24]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
for(position = 0U; position < GPIO_NUMBER; position++)
8002eea: 2300 movs r3, #0
8002eec: 61fb str r3, [r7, #28]
8002eee: e153 b.n 8003198 <HAL_GPIO_Init+0x2c4>
{
/* Get the IO position */
ioposition = 0x01U << position;
8002ef0: 2201 movs r2, #1
8002ef2: 69fb ldr r3, [r7, #28]
8002ef4: fa02 f303 lsl.w r3, r2, r3
8002ef8: 617b str r3, [r7, #20]
/* Get the current IO position */
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
8002efa: 683b ldr r3, [r7, #0]
8002efc: 681b ldr r3, [r3, #0]
8002efe: 697a ldr r2, [r7, #20]
8002f00: 4013 ands r3, r2
8002f02: 613b str r3, [r7, #16]
if(iocurrent == ioposition)
8002f04: 693a ldr r2, [r7, #16]
8002f06: 697b ldr r3, [r7, #20]
8002f08: 429a cmp r2, r3
8002f0a: f040 8142 bne.w 8003192 <HAL_GPIO_Init+0x2be>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
8002f0e: 683b ldr r3, [r7, #0]
8002f10: 685b ldr r3, [r3, #4]
8002f12: f003 0303 and.w r3, r3, #3
8002f16: 2b01 cmp r3, #1
8002f18: d005 beq.n 8002f26 <HAL_GPIO_Init+0x52>
(GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
8002f1a: 683b ldr r3, [r7, #0]
8002f1c: 685b ldr r3, [r3, #4]
8002f1e: f003 0303 and.w r3, r3, #3
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
8002f22: 2b02 cmp r3, #2
8002f24: d130 bne.n 8002f88 <HAL_GPIO_Init+0xb4>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
8002f26: 687b ldr r3, [r7, #4]
8002f28: 689b ldr r3, [r3, #8]
8002f2a: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
8002f2c: 69fb ldr r3, [r7, #28]
8002f2e: 005b lsls r3, r3, #1
8002f30: 2203 movs r2, #3
8002f32: fa02 f303 lsl.w r3, r2, r3
8002f36: 43db mvns r3, r3
8002f38: 69ba ldr r2, [r7, #24]
8002f3a: 4013 ands r3, r2
8002f3c: 61bb str r3, [r7, #24]
temp |= (GPIO_Init->Speed << (position * 2U));
8002f3e: 683b ldr r3, [r7, #0]
8002f40: 68da ldr r2, [r3, #12]
8002f42: 69fb ldr r3, [r7, #28]
8002f44: 005b lsls r3, r3, #1
8002f46: fa02 f303 lsl.w r3, r2, r3
8002f4a: 69ba ldr r2, [r7, #24]
8002f4c: 4313 orrs r3, r2
8002f4e: 61bb str r3, [r7, #24]
GPIOx->OSPEEDR = temp;
8002f50: 687b ldr r3, [r7, #4]
8002f52: 69ba ldr r2, [r7, #24]
8002f54: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
8002f56: 687b ldr r3, [r7, #4]
8002f58: 685b ldr r3, [r3, #4]
8002f5a: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
8002f5c: 2201 movs r2, #1
8002f5e: 69fb ldr r3, [r7, #28]
8002f60: fa02 f303 lsl.w r3, r2, r3
8002f64: 43db mvns r3, r3
8002f66: 69ba ldr r2, [r7, #24]
8002f68: 4013 ands r3, r2
8002f6a: 61bb str r3, [r7, #24]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
8002f6c: 683b ldr r3, [r7, #0]
8002f6e: 685b ldr r3, [r3, #4]
8002f70: 091b lsrs r3, r3, #4
8002f72: f003 0201 and.w r2, r3, #1
8002f76: 69fb ldr r3, [r7, #28]
8002f78: fa02 f303 lsl.w r3, r2, r3
8002f7c: 69ba ldr r2, [r7, #24]
8002f7e: 4313 orrs r3, r2
8002f80: 61bb str r3, [r7, #24]
GPIOx->OTYPER = temp;
8002f82: 687b ldr r3, [r7, #4]
8002f84: 69ba ldr r2, [r7, #24]
8002f86: 605a str r2, [r3, #4]
}
if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
8002f88: 683b ldr r3, [r7, #0]
8002f8a: 685b ldr r3, [r3, #4]
8002f8c: f003 0303 and.w r3, r3, #3
8002f90: 2b03 cmp r3, #3
8002f92: d017 beq.n 8002fc4 <HAL_GPIO_Init+0xf0>
{
/* Check the parameters */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
8002f94: 687b ldr r3, [r7, #4]
8002f96: 68db ldr r3, [r3, #12]
8002f98: 61bb str r3, [r7, #24]
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
8002f9a: 69fb ldr r3, [r7, #28]
8002f9c: 005b lsls r3, r3, #1
8002f9e: 2203 movs r2, #3
8002fa0: fa02 f303 lsl.w r3, r2, r3
8002fa4: 43db mvns r3, r3
8002fa6: 69ba ldr r2, [r7, #24]
8002fa8: 4013 ands r3, r2
8002faa: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Pull) << (position * 2U));
8002fac: 683b ldr r3, [r7, #0]
8002fae: 689a ldr r2, [r3, #8]
8002fb0: 69fb ldr r3, [r7, #28]
8002fb2: 005b lsls r3, r3, #1
8002fb4: fa02 f303 lsl.w r3, r2, r3
8002fb8: 69ba ldr r2, [r7, #24]
8002fba: 4313 orrs r3, r2
8002fbc: 61bb str r3, [r7, #24]
GPIOx->PUPDR = temp;
8002fbe: 687b ldr r3, [r7, #4]
8002fc0: 69ba ldr r2, [r7, #24]
8002fc2: 60da str r2, [r3, #12]
}
/* In case of Alternate function mode selection */
if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
8002fc4: 683b ldr r3, [r7, #0]
8002fc6: 685b ldr r3, [r3, #4]
8002fc8: f003 0303 and.w r3, r3, #3
8002fcc: 2b02 cmp r3, #2
8002fce: d123 bne.n 8003018 <HAL_GPIO_Init+0x144>
{
/* Check the Alternate function parameter */
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3U];
8002fd0: 69fb ldr r3, [r7, #28]
8002fd2: 08da lsrs r2, r3, #3
8002fd4: 687b ldr r3, [r7, #4]
8002fd6: 3208 adds r2, #8
8002fd8: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8002fdc: 61bb str r3, [r7, #24]
temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
8002fde: 69fb ldr r3, [r7, #28]
8002fe0: f003 0307 and.w r3, r3, #7
8002fe4: 009b lsls r3, r3, #2
8002fe6: 220f movs r2, #15
8002fe8: fa02 f303 lsl.w r3, r2, r3
8002fec: 43db mvns r3, r3
8002fee: 69ba ldr r2, [r7, #24]
8002ff0: 4013 ands r3, r2
8002ff2: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
8002ff4: 683b ldr r3, [r7, #0]
8002ff6: 691a ldr r2, [r3, #16]
8002ff8: 69fb ldr r3, [r7, #28]
8002ffa: f003 0307 and.w r3, r3, #7
8002ffe: 009b lsls r3, r3, #2
8003000: fa02 f303 lsl.w r3, r2, r3
8003004: 69ba ldr r2, [r7, #24]
8003006: 4313 orrs r3, r2
8003008: 61bb str r3, [r7, #24]
GPIOx->AFR[position >> 3U] = temp;
800300a: 69fb ldr r3, [r7, #28]
800300c: 08da lsrs r2, r3, #3
800300e: 687b ldr r3, [r7, #4]
8003010: 3208 adds r2, #8
8003012: 69b9 ldr r1, [r7, #24]
8003014: f843 1022 str.w r1, [r3, r2, lsl #2]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
8003018: 687b ldr r3, [r7, #4]
800301a: 681b ldr r3, [r3, #0]
800301c: 61bb str r3, [r7, #24]
temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
800301e: 69fb ldr r3, [r7, #28]
8003020: 005b lsls r3, r3, #1
8003022: 2203 movs r2, #3
8003024: fa02 f303 lsl.w r3, r2, r3
8003028: 43db mvns r3, r3
800302a: 69ba ldr r2, [r7, #24]
800302c: 4013 ands r3, r2
800302e: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
8003030: 683b ldr r3, [r7, #0]
8003032: 685b ldr r3, [r3, #4]
8003034: f003 0203 and.w r2, r3, #3
8003038: 69fb ldr r3, [r7, #28]
800303a: 005b lsls r3, r3, #1
800303c: fa02 f303 lsl.w r3, r2, r3
8003040: 69ba ldr r2, [r7, #24]
8003042: 4313 orrs r3, r2
8003044: 61bb str r3, [r7, #24]
GPIOx->MODER = temp;
8003046: 687b ldr r3, [r7, #4]
8003048: 69ba ldr r2, [r7, #24]
800304a: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
800304c: 683b ldr r3, [r7, #0]
800304e: 685b ldr r3, [r3, #4]
8003050: f403 3340 and.w r3, r3, #196608 ; 0x30000
8003054: 2b00 cmp r3, #0
8003056: f000 809c beq.w 8003192 <HAL_GPIO_Init+0x2be>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
800305a: 2300 movs r3, #0
800305c: 60fb str r3, [r7, #12]
800305e: 4b54 ldr r3, [pc, #336] ; (80031b0 <HAL_GPIO_Init+0x2dc>)
8003060: 6c5b ldr r3, [r3, #68] ; 0x44
8003062: 4a53 ldr r2, [pc, #332] ; (80031b0 <HAL_GPIO_Init+0x2dc>)
8003064: f443 4380 orr.w r3, r3, #16384 ; 0x4000
8003068: 6453 str r3, [r2, #68] ; 0x44
800306a: 4b51 ldr r3, [pc, #324] ; (80031b0 <HAL_GPIO_Init+0x2dc>)
800306c: 6c5b ldr r3, [r3, #68] ; 0x44
800306e: f403 4380 and.w r3, r3, #16384 ; 0x4000
8003072: 60fb str r3, [r7, #12]
8003074: 68fb ldr r3, [r7, #12]
temp = SYSCFG->EXTICR[position >> 2U];
8003076: 4a4f ldr r2, [pc, #316] ; (80031b4 <HAL_GPIO_Init+0x2e0>)
8003078: 69fb ldr r3, [r7, #28]
800307a: 089b lsrs r3, r3, #2
800307c: 3302 adds r3, #2
800307e: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8003082: 61bb str r3, [r7, #24]
temp &= ~(0x0FU << (4U * (position & 0x03U)));
8003084: 69fb ldr r3, [r7, #28]
8003086: f003 0303 and.w r3, r3, #3
800308a: 009b lsls r3, r3, #2
800308c: 220f movs r2, #15
800308e: fa02 f303 lsl.w r3, r2, r3
8003092: 43db mvns r3, r3
8003094: 69ba ldr r2, [r7, #24]
8003096: 4013 ands r3, r2
8003098: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
800309a: 687b ldr r3, [r7, #4]
800309c: 4a46 ldr r2, [pc, #280] ; (80031b8 <HAL_GPIO_Init+0x2e4>)
800309e: 4293 cmp r3, r2
80030a0: d013 beq.n 80030ca <HAL_GPIO_Init+0x1f6>
80030a2: 687b ldr r3, [r7, #4]
80030a4: 4a45 ldr r2, [pc, #276] ; (80031bc <HAL_GPIO_Init+0x2e8>)
80030a6: 4293 cmp r3, r2
80030a8: d00d beq.n 80030c6 <HAL_GPIO_Init+0x1f2>
80030aa: 687b ldr r3, [r7, #4]
80030ac: 4a44 ldr r2, [pc, #272] ; (80031c0 <HAL_GPIO_Init+0x2ec>)
80030ae: 4293 cmp r3, r2
80030b0: d007 beq.n 80030c2 <HAL_GPIO_Init+0x1ee>
80030b2: 687b ldr r3, [r7, #4]
80030b4: 4a43 ldr r2, [pc, #268] ; (80031c4 <HAL_GPIO_Init+0x2f0>)
80030b6: 4293 cmp r3, r2
80030b8: d101 bne.n 80030be <HAL_GPIO_Init+0x1ea>
80030ba: 2303 movs r3, #3
80030bc: e006 b.n 80030cc <HAL_GPIO_Init+0x1f8>
80030be: 2307 movs r3, #7
80030c0: e004 b.n 80030cc <HAL_GPIO_Init+0x1f8>
80030c2: 2302 movs r3, #2
80030c4: e002 b.n 80030cc <HAL_GPIO_Init+0x1f8>
80030c6: 2301 movs r3, #1
80030c8: e000 b.n 80030cc <HAL_GPIO_Init+0x1f8>
80030ca: 2300 movs r3, #0
80030cc: 69fa ldr r2, [r7, #28]
80030ce: f002 0203 and.w r2, r2, #3
80030d2: 0092 lsls r2, r2, #2
80030d4: 4093 lsls r3, r2
80030d6: 69ba ldr r2, [r7, #24]
80030d8: 4313 orrs r3, r2
80030da: 61bb str r3, [r7, #24]
SYSCFG->EXTICR[position >> 2U] = temp;
80030dc: 4935 ldr r1, [pc, #212] ; (80031b4 <HAL_GPIO_Init+0x2e0>)
80030de: 69fb ldr r3, [r7, #28]
80030e0: 089b lsrs r3, r3, #2
80030e2: 3302 adds r3, #2
80030e4: 69ba ldr r2, [r7, #24]
80030e6: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Clear EXTI line configuration */
temp = EXTI->IMR;
80030ea: 4b37 ldr r3, [pc, #220] ; (80031c8 <HAL_GPIO_Init+0x2f4>)
80030ec: 681b ldr r3, [r3, #0]
80030ee: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
80030f0: 693b ldr r3, [r7, #16]
80030f2: 43db mvns r3, r3
80030f4: 69ba ldr r2, [r7, #24]
80030f6: 4013 ands r3, r2
80030f8: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & EXTI_IT) != 0x00U)
80030fa: 683b ldr r3, [r7, #0]
80030fc: 685b ldr r3, [r3, #4]
80030fe: f403 3380 and.w r3, r3, #65536 ; 0x10000
8003102: 2b00 cmp r3, #0
8003104: d003 beq.n 800310e <HAL_GPIO_Init+0x23a>
{
temp |= iocurrent;
8003106: 69ba ldr r2, [r7, #24]
8003108: 693b ldr r3, [r7, #16]
800310a: 4313 orrs r3, r2
800310c: 61bb str r3, [r7, #24]
}
EXTI->IMR = temp;
800310e: 4a2e ldr r2, [pc, #184] ; (80031c8 <HAL_GPIO_Init+0x2f4>)
8003110: 69bb ldr r3, [r7, #24]
8003112: 6013 str r3, [r2, #0]
temp = EXTI->EMR;
8003114: 4b2c ldr r3, [pc, #176] ; (80031c8 <HAL_GPIO_Init+0x2f4>)
8003116: 685b ldr r3, [r3, #4]
8003118: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
800311a: 693b ldr r3, [r7, #16]
800311c: 43db mvns r3, r3
800311e: 69ba ldr r2, [r7, #24]
8003120: 4013 ands r3, r2
8003122: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
8003124: 683b ldr r3, [r7, #0]
8003126: 685b ldr r3, [r3, #4]
8003128: f403 3300 and.w r3, r3, #131072 ; 0x20000
800312c: 2b00 cmp r3, #0
800312e: d003 beq.n 8003138 <HAL_GPIO_Init+0x264>
{
temp |= iocurrent;
8003130: 69ba ldr r2, [r7, #24]
8003132: 693b ldr r3, [r7, #16]
8003134: 4313 orrs r3, r2
8003136: 61bb str r3, [r7, #24]
}
EXTI->EMR = temp;
8003138: 4a23 ldr r2, [pc, #140] ; (80031c8 <HAL_GPIO_Init+0x2f4>)
800313a: 69bb ldr r3, [r7, #24]
800313c: 6053 str r3, [r2, #4]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
800313e: 4b22 ldr r3, [pc, #136] ; (80031c8 <HAL_GPIO_Init+0x2f4>)
8003140: 689b ldr r3, [r3, #8]
8003142: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8003144: 693b ldr r3, [r7, #16]
8003146: 43db mvns r3, r3
8003148: 69ba ldr r2, [r7, #24]
800314a: 4013 ands r3, r2
800314c: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
800314e: 683b ldr r3, [r7, #0]
8003150: 685b ldr r3, [r3, #4]
8003152: f403 1380 and.w r3, r3, #1048576 ; 0x100000
8003156: 2b00 cmp r3, #0
8003158: d003 beq.n 8003162 <HAL_GPIO_Init+0x28e>
{
temp |= iocurrent;
800315a: 69ba ldr r2, [r7, #24]
800315c: 693b ldr r3, [r7, #16]
800315e: 4313 orrs r3, r2
8003160: 61bb str r3, [r7, #24]
}
EXTI->RTSR = temp;
8003162: 4a19 ldr r2, [pc, #100] ; (80031c8 <HAL_GPIO_Init+0x2f4>)
8003164: 69bb ldr r3, [r7, #24]
8003166: 6093 str r3, [r2, #8]
temp = EXTI->FTSR;
8003168: 4b17 ldr r3, [pc, #92] ; (80031c8 <HAL_GPIO_Init+0x2f4>)
800316a: 68db ldr r3, [r3, #12]
800316c: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
800316e: 693b ldr r3, [r7, #16]
8003170: 43db mvns r3, r3
8003172: 69ba ldr r2, [r7, #24]
8003174: 4013 ands r3, r2
8003176: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
8003178: 683b ldr r3, [r7, #0]
800317a: 685b ldr r3, [r3, #4]
800317c: f403 1300 and.w r3, r3, #2097152 ; 0x200000
8003180: 2b00 cmp r3, #0
8003182: d003 beq.n 800318c <HAL_GPIO_Init+0x2b8>
{
temp |= iocurrent;
8003184: 69ba ldr r2, [r7, #24]
8003186: 693b ldr r3, [r7, #16]
8003188: 4313 orrs r3, r2
800318a: 61bb str r3, [r7, #24]
}
EXTI->FTSR = temp;
800318c: 4a0e ldr r2, [pc, #56] ; (80031c8 <HAL_GPIO_Init+0x2f4>)
800318e: 69bb ldr r3, [r7, #24]
8003190: 60d3 str r3, [r2, #12]
for(position = 0U; position < GPIO_NUMBER; position++)
8003192: 69fb ldr r3, [r7, #28]
8003194: 3301 adds r3, #1
8003196: 61fb str r3, [r7, #28]
8003198: 69fb ldr r3, [r7, #28]
800319a: 2b0f cmp r3, #15
800319c: f67f aea8 bls.w 8002ef0 <HAL_GPIO_Init+0x1c>
}
}
}
}
80031a0: bf00 nop
80031a2: bf00 nop
80031a4: 3724 adds r7, #36 ; 0x24
80031a6: 46bd mov sp, r7
80031a8: f85d 7b04 ldr.w r7, [sp], #4
80031ac: 4770 bx lr
80031ae: bf00 nop
80031b0: 40023800 .word 0x40023800
80031b4: 40013800 .word 0x40013800
80031b8: 40020000 .word 0x40020000
80031bc: 40020400 .word 0x40020400
80031c0: 40020800 .word 0x40020800
80031c4: 40020c00 .word 0x40020c00
80031c8: 40013c00 .word 0x40013c00
080031cc <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
80031cc: b480 push {r7}
80031ce: b083 sub sp, #12
80031d0: af00 add r7, sp, #0
80031d2: 6078 str r0, [r7, #4]
80031d4: 460b mov r3, r1
80031d6: 807b strh r3, [r7, #2]
80031d8: 4613 mov r3, r2
80031da: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if(PinState != GPIO_PIN_RESET)
80031dc: 787b ldrb r3, [r7, #1]
80031de: 2b00 cmp r3, #0
80031e0: d003 beq.n 80031ea <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = GPIO_Pin;
80031e2: 887a ldrh r2, [r7, #2]
80031e4: 687b ldr r3, [r7, #4]
80031e6: 619a str r2, [r3, #24]
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
}
}
80031e8: e003 b.n 80031f2 <HAL_GPIO_WritePin+0x26>
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
80031ea: 887b ldrh r3, [r7, #2]
80031ec: 041a lsls r2, r3, #16
80031ee: 687b ldr r3, [r7, #4]
80031f0: 619a str r2, [r3, #24]
}
80031f2: bf00 nop
80031f4: 370c adds r7, #12
80031f6: 46bd mov sp, r7
80031f8: f85d 7b04 ldr.w r7, [sp], #4
80031fc: 4770 bx lr
...
08003200 <HAL_I2C_Init>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
{
8003200: b580 push {r7, lr}
8003202: b084 sub sp, #16
8003204: af00 add r7, sp, #0
8003206: 6078 str r0, [r7, #4]
uint32_t freqrange;
uint32_t pclk1;
/* Check the I2C handle allocation */
if (hi2c == NULL)
8003208: 687b ldr r3, [r7, #4]
800320a: 2b00 cmp r3, #0
800320c: d101 bne.n 8003212 <HAL_I2C_Init+0x12>
{
return HAL_ERROR;
800320e: 2301 movs r3, #1
8003210: e12b b.n 800346a <HAL_I2C_Init+0x26a>
assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
if (hi2c->State == HAL_I2C_STATE_RESET)
8003212: 687b ldr r3, [r7, #4]
8003214: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
8003218: b2db uxtb r3, r3
800321a: 2b00 cmp r3, #0
800321c: d106 bne.n 800322c <HAL_I2C_Init+0x2c>
{
/* Allocate lock resource and initialize it */
hi2c->Lock = HAL_UNLOCKED;
800321e: 687b ldr r3, [r7, #4]
8003220: 2200 movs r2, #0
8003222: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Init the low level hardware : GPIO, CLOCK, NVIC */
hi2c->MspInitCallback(hi2c);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_I2C_MspInit(hi2c);
8003226: 6878 ldr r0, [r7, #4]
8003228: f7fe fb76 bl 8001918 <HAL_I2C_MspInit>
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
hi2c->State = HAL_I2C_STATE_BUSY;
800322c: 687b ldr r3, [r7, #4]
800322e: 2224 movs r2, #36 ; 0x24
8003230: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
8003234: 687b ldr r3, [r7, #4]
8003236: 681b ldr r3, [r3, #0]
8003238: 681a ldr r2, [r3, #0]
800323a: 687b ldr r3, [r7, #4]
800323c: 681b ldr r3, [r3, #0]
800323e: f022 0201 bic.w r2, r2, #1
8003242: 601a str r2, [r3, #0]
/*Reset I2C*/
hi2c->Instance->CR1 |= I2C_CR1_SWRST;
8003244: 687b ldr r3, [r7, #4]
8003246: 681b ldr r3, [r3, #0]
8003248: 681a ldr r2, [r3, #0]
800324a: 687b ldr r3, [r7, #4]
800324c: 681b ldr r3, [r3, #0]
800324e: f442 4200 orr.w r2, r2, #32768 ; 0x8000
8003252: 601a str r2, [r3, #0]
hi2c->Instance->CR1 &= ~I2C_CR1_SWRST;
8003254: 687b ldr r3, [r7, #4]
8003256: 681b ldr r3, [r3, #0]
8003258: 681a ldr r2, [r3, #0]
800325a: 687b ldr r3, [r7, #4]
800325c: 681b ldr r3, [r3, #0]
800325e: f422 4200 bic.w r2, r2, #32768 ; 0x8000
8003262: 601a str r2, [r3, #0]
/* Get PCLK1 frequency */
pclk1 = HAL_RCC_GetPCLK1Freq();
8003264: f000 fae2 bl 800382c <HAL_RCC_GetPCLK1Freq>
8003268: 60f8 str r0, [r7, #12]
/* Check the minimum allowed PCLK1 frequency */
if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U)
800326a: 687b ldr r3, [r7, #4]
800326c: 685b ldr r3, [r3, #4]
800326e: 4a81 ldr r2, [pc, #516] ; (8003474 <HAL_I2C_Init+0x274>)
8003270: 4293 cmp r3, r2
8003272: d807 bhi.n 8003284 <HAL_I2C_Init+0x84>
8003274: 68fb ldr r3, [r7, #12]
8003276: 4a80 ldr r2, [pc, #512] ; (8003478 <HAL_I2C_Init+0x278>)
8003278: 4293 cmp r3, r2
800327a: bf94 ite ls
800327c: 2301 movls r3, #1
800327e: 2300 movhi r3, #0
8003280: b2db uxtb r3, r3
8003282: e006 b.n 8003292 <HAL_I2C_Init+0x92>
8003284: 68fb ldr r3, [r7, #12]
8003286: 4a7d ldr r2, [pc, #500] ; (800347c <HAL_I2C_Init+0x27c>)
8003288: 4293 cmp r3, r2
800328a: bf94 ite ls
800328c: 2301 movls r3, #1
800328e: 2300 movhi r3, #0
8003290: b2db uxtb r3, r3
8003292: 2b00 cmp r3, #0
8003294: d001 beq.n 800329a <HAL_I2C_Init+0x9a>
{
return HAL_ERROR;
8003296: 2301 movs r3, #1
8003298: e0e7 b.n 800346a <HAL_I2C_Init+0x26a>
}
/* Calculate frequency range */
freqrange = I2C_FREQRANGE(pclk1);
800329a: 68fb ldr r3, [r7, #12]
800329c: 4a78 ldr r2, [pc, #480] ; (8003480 <HAL_I2C_Init+0x280>)
800329e: fba2 2303 umull r2, r3, r2, r3
80032a2: 0c9b lsrs r3, r3, #18
80032a4: 60bb str r3, [r7, #8]
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
/* Configure I2Cx: Frequency range */
MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange);
80032a6: 687b ldr r3, [r7, #4]
80032a8: 681b ldr r3, [r3, #0]
80032aa: 685b ldr r3, [r3, #4]
80032ac: f023 013f bic.w r1, r3, #63 ; 0x3f
80032b0: 687b ldr r3, [r7, #4]
80032b2: 681b ldr r3, [r3, #0]
80032b4: 68ba ldr r2, [r7, #8]
80032b6: 430a orrs r2, r1
80032b8: 605a str r2, [r3, #4]
/*---------------------------- I2Cx TRISE Configuration --------------------*/
/* Configure I2Cx: Rise Time */
MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed));
80032ba: 687b ldr r3, [r7, #4]
80032bc: 681b ldr r3, [r3, #0]
80032be: 6a1b ldr r3, [r3, #32]
80032c0: f023 013f bic.w r1, r3, #63 ; 0x3f
80032c4: 687b ldr r3, [r7, #4]
80032c6: 685b ldr r3, [r3, #4]
80032c8: 4a6a ldr r2, [pc, #424] ; (8003474 <HAL_I2C_Init+0x274>)
80032ca: 4293 cmp r3, r2
80032cc: d802 bhi.n 80032d4 <HAL_I2C_Init+0xd4>
80032ce: 68bb ldr r3, [r7, #8]
80032d0: 3301 adds r3, #1
80032d2: e009 b.n 80032e8 <HAL_I2C_Init+0xe8>
80032d4: 68bb ldr r3, [r7, #8]
80032d6: f44f 7296 mov.w r2, #300 ; 0x12c
80032da: fb02 f303 mul.w r3, r2, r3
80032de: 4a69 ldr r2, [pc, #420] ; (8003484 <HAL_I2C_Init+0x284>)
80032e0: fba2 2303 umull r2, r3, r2, r3
80032e4: 099b lsrs r3, r3, #6
80032e6: 3301 adds r3, #1
80032e8: 687a ldr r2, [r7, #4]
80032ea: 6812 ldr r2, [r2, #0]
80032ec: 430b orrs r3, r1
80032ee: 6213 str r3, [r2, #32]
/*---------------------------- I2Cx CCR Configuration ----------------------*/
/* Configure I2Cx: Speed */
MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle));
80032f0: 687b ldr r3, [r7, #4]
80032f2: 681b ldr r3, [r3, #0]
80032f4: 69db ldr r3, [r3, #28]
80032f6: f423 424f bic.w r2, r3, #52992 ; 0xcf00
80032fa: f022 02ff bic.w r2, r2, #255 ; 0xff
80032fe: 687b ldr r3, [r7, #4]
8003300: 685b ldr r3, [r3, #4]
8003302: 495c ldr r1, [pc, #368] ; (8003474 <HAL_I2C_Init+0x274>)
8003304: 428b cmp r3, r1
8003306: d819 bhi.n 800333c <HAL_I2C_Init+0x13c>
8003308: 68fb ldr r3, [r7, #12]
800330a: 1e59 subs r1, r3, #1
800330c: 687b ldr r3, [r7, #4]
800330e: 685b ldr r3, [r3, #4]
8003310: 005b lsls r3, r3, #1
8003312: fbb1 f3f3 udiv r3, r1, r3
8003316: 1c59 adds r1, r3, #1
8003318: f640 73fc movw r3, #4092 ; 0xffc
800331c: 400b ands r3, r1
800331e: 2b00 cmp r3, #0
8003320: d00a beq.n 8003338 <HAL_I2C_Init+0x138>
8003322: 68fb ldr r3, [r7, #12]
8003324: 1e59 subs r1, r3, #1
8003326: 687b ldr r3, [r7, #4]
8003328: 685b ldr r3, [r3, #4]
800332a: 005b lsls r3, r3, #1
800332c: fbb1 f3f3 udiv r3, r1, r3
8003330: 3301 adds r3, #1
8003332: f3c3 030b ubfx r3, r3, #0, #12
8003336: e051 b.n 80033dc <HAL_I2C_Init+0x1dc>
8003338: 2304 movs r3, #4
800333a: e04f b.n 80033dc <HAL_I2C_Init+0x1dc>
800333c: 687b ldr r3, [r7, #4]
800333e: 689b ldr r3, [r3, #8]
8003340: 2b00 cmp r3, #0
8003342: d111 bne.n 8003368 <HAL_I2C_Init+0x168>
8003344: 68fb ldr r3, [r7, #12]
8003346: 1e58 subs r0, r3, #1
8003348: 687b ldr r3, [r7, #4]
800334a: 6859 ldr r1, [r3, #4]
800334c: 460b mov r3, r1
800334e: 005b lsls r3, r3, #1
8003350: 440b add r3, r1
8003352: fbb0 f3f3 udiv r3, r0, r3
8003356: 3301 adds r3, #1
8003358: f3c3 030b ubfx r3, r3, #0, #12
800335c: 2b00 cmp r3, #0
800335e: bf0c ite eq
8003360: 2301 moveq r3, #1
8003362: 2300 movne r3, #0
8003364: b2db uxtb r3, r3
8003366: e012 b.n 800338e <HAL_I2C_Init+0x18e>
8003368: 68fb ldr r3, [r7, #12]
800336a: 1e58 subs r0, r3, #1
800336c: 687b ldr r3, [r7, #4]
800336e: 6859 ldr r1, [r3, #4]
8003370: 460b mov r3, r1
8003372: 009b lsls r3, r3, #2
8003374: 440b add r3, r1
8003376: 0099 lsls r1, r3, #2
8003378: 440b add r3, r1
800337a: fbb0 f3f3 udiv r3, r0, r3
800337e: 3301 adds r3, #1
8003380: f3c3 030b ubfx r3, r3, #0, #12
8003384: 2b00 cmp r3, #0
8003386: bf0c ite eq
8003388: 2301 moveq r3, #1
800338a: 2300 movne r3, #0
800338c: b2db uxtb r3, r3
800338e: 2b00 cmp r3, #0
8003390: d001 beq.n 8003396 <HAL_I2C_Init+0x196>
8003392: 2301 movs r3, #1
8003394: e022 b.n 80033dc <HAL_I2C_Init+0x1dc>
8003396: 687b ldr r3, [r7, #4]
8003398: 689b ldr r3, [r3, #8]
800339a: 2b00 cmp r3, #0
800339c: d10e bne.n 80033bc <HAL_I2C_Init+0x1bc>
800339e: 68fb ldr r3, [r7, #12]
80033a0: 1e58 subs r0, r3, #1
80033a2: 687b ldr r3, [r7, #4]
80033a4: 6859 ldr r1, [r3, #4]
80033a6: 460b mov r3, r1
80033a8: 005b lsls r3, r3, #1
80033aa: 440b add r3, r1
80033ac: fbb0 f3f3 udiv r3, r0, r3
80033b0: 3301 adds r3, #1
80033b2: f3c3 030b ubfx r3, r3, #0, #12
80033b6: f443 4300 orr.w r3, r3, #32768 ; 0x8000
80033ba: e00f b.n 80033dc <HAL_I2C_Init+0x1dc>
80033bc: 68fb ldr r3, [r7, #12]
80033be: 1e58 subs r0, r3, #1
80033c0: 687b ldr r3, [r7, #4]
80033c2: 6859 ldr r1, [r3, #4]
80033c4: 460b mov r3, r1
80033c6: 009b lsls r3, r3, #2
80033c8: 440b add r3, r1
80033ca: 0099 lsls r1, r3, #2
80033cc: 440b add r3, r1
80033ce: fbb0 f3f3 udiv r3, r0, r3
80033d2: 3301 adds r3, #1
80033d4: f3c3 030b ubfx r3, r3, #0, #12
80033d8: f443 4340 orr.w r3, r3, #49152 ; 0xc000
80033dc: 6879 ldr r1, [r7, #4]
80033de: 6809 ldr r1, [r1, #0]
80033e0: 4313 orrs r3, r2
80033e2: 61cb str r3, [r1, #28]
/*---------------------------- I2Cx CR1 Configuration ----------------------*/
/* Configure I2Cx: Generalcall and NoStretch mode */
MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode));
80033e4: 687b ldr r3, [r7, #4]
80033e6: 681b ldr r3, [r3, #0]
80033e8: 681b ldr r3, [r3, #0]
80033ea: f023 01c0 bic.w r1, r3, #192 ; 0xc0
80033ee: 687b ldr r3, [r7, #4]
80033f0: 69da ldr r2, [r3, #28]
80033f2: 687b ldr r3, [r7, #4]
80033f4: 6a1b ldr r3, [r3, #32]
80033f6: 431a orrs r2, r3
80033f8: 687b ldr r3, [r7, #4]
80033fa: 681b ldr r3, [r3, #0]
80033fc: 430a orrs r2, r1
80033fe: 601a str r2, [r3, #0]
/*---------------------------- I2Cx OAR1 Configuration ---------------------*/
/* Configure I2Cx: Own Address1 and addressing mode */
MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1));
8003400: 687b ldr r3, [r7, #4]
8003402: 681b ldr r3, [r3, #0]
8003404: 689b ldr r3, [r3, #8]
8003406: f423 4303 bic.w r3, r3, #33536 ; 0x8300
800340a: f023 03ff bic.w r3, r3, #255 ; 0xff
800340e: 687a ldr r2, [r7, #4]
8003410: 6911 ldr r1, [r2, #16]
8003412: 687a ldr r2, [r7, #4]
8003414: 68d2 ldr r2, [r2, #12]
8003416: 4311 orrs r1, r2
8003418: 687a ldr r2, [r7, #4]
800341a: 6812 ldr r2, [r2, #0]
800341c: 430b orrs r3, r1
800341e: 6093 str r3, [r2, #8]
/*---------------------------- I2Cx OAR2 Configuration ---------------------*/
/* Configure I2Cx: Dual mode and Own Address2 */
MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2));
8003420: 687b ldr r3, [r7, #4]
8003422: 681b ldr r3, [r3, #0]
8003424: 68db ldr r3, [r3, #12]
8003426: f023 01ff bic.w r1, r3, #255 ; 0xff
800342a: 687b ldr r3, [r7, #4]
800342c: 695a ldr r2, [r3, #20]
800342e: 687b ldr r3, [r7, #4]
8003430: 699b ldr r3, [r3, #24]
8003432: 431a orrs r2, r3
8003434: 687b ldr r3, [r7, #4]
8003436: 681b ldr r3, [r3, #0]
8003438: 430a orrs r2, r1
800343a: 60da str r2, [r3, #12]
/* Enable the selected I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
800343c: 687b ldr r3, [r7, #4]
800343e: 681b ldr r3, [r3, #0]
8003440: 681a ldr r2, [r3, #0]
8003442: 687b ldr r3, [r7, #4]
8003444: 681b ldr r3, [r3, #0]
8003446: f042 0201 orr.w r2, r2, #1
800344a: 601a str r2, [r3, #0]
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
800344c: 687b ldr r3, [r7, #4]
800344e: 2200 movs r2, #0
8003450: 641a str r2, [r3, #64] ; 0x40
hi2c->State = HAL_I2C_STATE_READY;
8003452: 687b ldr r3, [r7, #4]
8003454: 2220 movs r2, #32
8003456: f883 203d strb.w r2, [r3, #61] ; 0x3d
hi2c->PreviousState = I2C_STATE_NONE;
800345a: 687b ldr r3, [r7, #4]
800345c: 2200 movs r2, #0
800345e: 631a str r2, [r3, #48] ; 0x30
hi2c->Mode = HAL_I2C_MODE_NONE;
8003460: 687b ldr r3, [r7, #4]
8003462: 2200 movs r2, #0
8003464: f883 203e strb.w r2, [r3, #62] ; 0x3e
return HAL_OK;
8003468: 2300 movs r3, #0
}
800346a: 4618 mov r0, r3
800346c: 3710 adds r7, #16
800346e: 46bd mov sp, r7
8003470: bd80 pop {r7, pc}
8003472: bf00 nop
8003474: 000186a0 .word 0x000186a0
8003478: 001e847f .word 0x001e847f
800347c: 003d08ff .word 0x003d08ff
8003480: 431bde83 .word 0x431bde83
8003484: 10624dd3 .word 0x10624dd3
08003488 <HAL_RCC_ClockConfig>:
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval None
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8003488: b580 push {r7, lr}
800348a: b084 sub sp, #16
800348c: af00 add r7, sp, #0
800348e: 6078 str r0, [r7, #4]
8003490: 6039 str r1, [r7, #0]
uint32_t tickstart;
/* Check Null pointer */
if(RCC_ClkInitStruct == NULL)
8003492: 687b ldr r3, [r7, #4]
8003494: 2b00 cmp r3, #0
8003496: d101 bne.n 800349c <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
8003498: 2301 movs r3, #1
800349a: e0cc b.n 8003636 <HAL_RCC_ClockConfig+0x1ae>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if(FLatency > __HAL_FLASH_GET_LATENCY())
800349c: 4b68 ldr r3, [pc, #416] ; (8003640 <HAL_RCC_ClockConfig+0x1b8>)
800349e: 681b ldr r3, [r3, #0]
80034a0: f003 0307 and.w r3, r3, #7
80034a4: 683a ldr r2, [r7, #0]
80034a6: 429a cmp r2, r3
80034a8: d90c bls.n 80034c4 <HAL_RCC_ClockConfig+0x3c>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
80034aa: 4b65 ldr r3, [pc, #404] ; (8003640 <HAL_RCC_ClockConfig+0x1b8>)
80034ac: 683a ldr r2, [r7, #0]
80034ae: b2d2 uxtb r2, r2
80034b0: 701a strb r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
80034b2: 4b63 ldr r3, [pc, #396] ; (8003640 <HAL_RCC_ClockConfig+0x1b8>)
80034b4: 681b ldr r3, [r3, #0]
80034b6: f003 0307 and.w r3, r3, #7
80034ba: 683a ldr r2, [r7, #0]
80034bc: 429a cmp r2, r3
80034be: d001 beq.n 80034c4 <HAL_RCC_ClockConfig+0x3c>
{
return HAL_ERROR;
80034c0: 2301 movs r3, #1
80034c2: e0b8 b.n 8003636 <HAL_RCC_ClockConfig+0x1ae>
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
80034c4: 687b ldr r3, [r7, #4]
80034c6: 681b ldr r3, [r3, #0]
80034c8: f003 0302 and.w r3, r3, #2
80034cc: 2b00 cmp r3, #0
80034ce: d020 beq.n 8003512 <HAL_RCC_ClockConfig+0x8a>
{
/* Set the highest APBx dividers in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
80034d0: 687b ldr r3, [r7, #4]
80034d2: 681b ldr r3, [r3, #0]
80034d4: f003 0304 and.w r3, r3, #4
80034d8: 2b00 cmp r3, #0
80034da: d005 beq.n 80034e8 <HAL_RCC_ClockConfig+0x60>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
80034dc: 4b59 ldr r3, [pc, #356] ; (8003644 <HAL_RCC_ClockConfig+0x1bc>)
80034de: 689b ldr r3, [r3, #8]
80034e0: 4a58 ldr r2, [pc, #352] ; (8003644 <HAL_RCC_ClockConfig+0x1bc>)
80034e2: f443 53e0 orr.w r3, r3, #7168 ; 0x1c00
80034e6: 6093 str r3, [r2, #8]
}
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
80034e8: 687b ldr r3, [r7, #4]
80034ea: 681b ldr r3, [r3, #0]
80034ec: f003 0308 and.w r3, r3, #8
80034f0: 2b00 cmp r3, #0
80034f2: d005 beq.n 8003500 <HAL_RCC_ClockConfig+0x78>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
80034f4: 4b53 ldr r3, [pc, #332] ; (8003644 <HAL_RCC_ClockConfig+0x1bc>)
80034f6: 689b ldr r3, [r3, #8]
80034f8: 4a52 ldr r2, [pc, #328] ; (8003644 <HAL_RCC_ClockConfig+0x1bc>)
80034fa: f443 4360 orr.w r3, r3, #57344 ; 0xe000
80034fe: 6093 str r3, [r2, #8]
}
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8003500: 4b50 ldr r3, [pc, #320] ; (8003644 <HAL_RCC_ClockConfig+0x1bc>)
8003502: 689b ldr r3, [r3, #8]
8003504: f023 02f0 bic.w r2, r3, #240 ; 0xf0
8003508: 687b ldr r3, [r7, #4]
800350a: 689b ldr r3, [r3, #8]
800350c: 494d ldr r1, [pc, #308] ; (8003644 <HAL_RCC_ClockConfig+0x1bc>)
800350e: 4313 orrs r3, r2
8003510: 608b str r3, [r1, #8]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8003512: 687b ldr r3, [r7, #4]
8003514: 681b ldr r3, [r3, #0]
8003516: f003 0301 and.w r3, r3, #1
800351a: 2b00 cmp r3, #0
800351c: d044 beq.n 80035a8 <HAL_RCC_ClockConfig+0x120>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
800351e: 687b ldr r3, [r7, #4]
8003520: 685b ldr r3, [r3, #4]
8003522: 2b01 cmp r3, #1
8003524: d107 bne.n 8003536 <HAL_RCC_ClockConfig+0xae>
{
/* Check the HSE ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8003526: 4b47 ldr r3, [pc, #284] ; (8003644 <HAL_RCC_ClockConfig+0x1bc>)
8003528: 681b ldr r3, [r3, #0]
800352a: f403 3300 and.w r3, r3, #131072 ; 0x20000
800352e: 2b00 cmp r3, #0
8003530: d119 bne.n 8003566 <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8003532: 2301 movs r3, #1
8003534: e07f b.n 8003636 <HAL_RCC_ClockConfig+0x1ae>
}
}
/* PLL is selected as System Clock Source */
else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
8003536: 687b ldr r3, [r7, #4]
8003538: 685b ldr r3, [r3, #4]
800353a: 2b02 cmp r3, #2
800353c: d003 beq.n 8003546 <HAL_RCC_ClockConfig+0xbe>
(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
800353e: 687b ldr r3, [r7, #4]
8003540: 685b ldr r3, [r3, #4]
else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
8003542: 2b03 cmp r3, #3
8003544: d107 bne.n 8003556 <HAL_RCC_ClockConfig+0xce>
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8003546: 4b3f ldr r3, [pc, #252] ; (8003644 <HAL_RCC_ClockConfig+0x1bc>)
8003548: 681b ldr r3, [r3, #0]
800354a: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
800354e: 2b00 cmp r3, #0
8003550: d109 bne.n 8003566 <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8003552: 2301 movs r3, #1
8003554: e06f b.n 8003636 <HAL_RCC_ClockConfig+0x1ae>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8003556: 4b3b ldr r3, [pc, #236] ; (8003644 <HAL_RCC_ClockConfig+0x1bc>)
8003558: 681b ldr r3, [r3, #0]
800355a: f003 0302 and.w r3, r3, #2
800355e: 2b00 cmp r3, #0
8003560: d101 bne.n 8003566 <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8003562: 2301 movs r3, #1
8003564: e067 b.n 8003636 <HAL_RCC_ClockConfig+0x1ae>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
8003566: 4b37 ldr r3, [pc, #220] ; (8003644 <HAL_RCC_ClockConfig+0x1bc>)
8003568: 689b ldr r3, [r3, #8]
800356a: f023 0203 bic.w r2, r3, #3
800356e: 687b ldr r3, [r7, #4]
8003570: 685b ldr r3, [r3, #4]
8003572: 4934 ldr r1, [pc, #208] ; (8003644 <HAL_RCC_ClockConfig+0x1bc>)
8003574: 4313 orrs r3, r2
8003576: 608b str r3, [r1, #8]
/* Get Start Tick */
tickstart = HAL_GetTick();
8003578: f7fe fc76 bl 8001e68 <HAL_GetTick>
800357c: 60f8 str r0, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
800357e: e00a b.n 8003596 <HAL_RCC_ClockConfig+0x10e>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8003580: f7fe fc72 bl 8001e68 <HAL_GetTick>
8003584: 4602 mov r2, r0
8003586: 68fb ldr r3, [r7, #12]
8003588: 1ad3 subs r3, r2, r3
800358a: f241 3288 movw r2, #5000 ; 0x1388
800358e: 4293 cmp r3, r2
8003590: d901 bls.n 8003596 <HAL_RCC_ClockConfig+0x10e>
{
return HAL_TIMEOUT;
8003592: 2303 movs r3, #3
8003594: e04f b.n 8003636 <HAL_RCC_ClockConfig+0x1ae>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8003596: 4b2b ldr r3, [pc, #172] ; (8003644 <HAL_RCC_ClockConfig+0x1bc>)
8003598: 689b ldr r3, [r3, #8]
800359a: f003 020c and.w r2, r3, #12
800359e: 687b ldr r3, [r7, #4]
80035a0: 685b ldr r3, [r3, #4]
80035a2: 009b lsls r3, r3, #2
80035a4: 429a cmp r2, r3
80035a6: d1eb bne.n 8003580 <HAL_RCC_ClockConfig+0xf8>
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if(FLatency < __HAL_FLASH_GET_LATENCY())
80035a8: 4b25 ldr r3, [pc, #148] ; (8003640 <HAL_RCC_ClockConfig+0x1b8>)
80035aa: 681b ldr r3, [r3, #0]
80035ac: f003 0307 and.w r3, r3, #7
80035b0: 683a ldr r2, [r7, #0]
80035b2: 429a cmp r2, r3
80035b4: d20c bcs.n 80035d0 <HAL_RCC_ClockConfig+0x148>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
80035b6: 4b22 ldr r3, [pc, #136] ; (8003640 <HAL_RCC_ClockConfig+0x1b8>)
80035b8: 683a ldr r2, [r7, #0]
80035ba: b2d2 uxtb r2, r2
80035bc: 701a strb r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
80035be: 4b20 ldr r3, [pc, #128] ; (8003640 <HAL_RCC_ClockConfig+0x1b8>)
80035c0: 681b ldr r3, [r3, #0]
80035c2: f003 0307 and.w r3, r3, #7
80035c6: 683a ldr r2, [r7, #0]
80035c8: 429a cmp r2, r3
80035ca: d001 beq.n 80035d0 <HAL_RCC_ClockConfig+0x148>
{
return HAL_ERROR;
80035cc: 2301 movs r3, #1
80035ce: e032 b.n 8003636 <HAL_RCC_ClockConfig+0x1ae>
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
80035d0: 687b ldr r3, [r7, #4]
80035d2: 681b ldr r3, [r3, #0]
80035d4: f003 0304 and.w r3, r3, #4
80035d8: 2b00 cmp r3, #0
80035da: d008 beq.n 80035ee <HAL_RCC_ClockConfig+0x166>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
80035dc: 4b19 ldr r3, [pc, #100] ; (8003644 <HAL_RCC_ClockConfig+0x1bc>)
80035de: 689b ldr r3, [r3, #8]
80035e0: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00
80035e4: 687b ldr r3, [r7, #4]
80035e6: 68db ldr r3, [r3, #12]
80035e8: 4916 ldr r1, [pc, #88] ; (8003644 <HAL_RCC_ClockConfig+0x1bc>)
80035ea: 4313 orrs r3, r2
80035ec: 608b str r3, [r1, #8]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
80035ee: 687b ldr r3, [r7, #4]
80035f0: 681b ldr r3, [r3, #0]
80035f2: f003 0308 and.w r3, r3, #8
80035f6: 2b00 cmp r3, #0
80035f8: d009 beq.n 800360e <HAL_RCC_ClockConfig+0x186>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
80035fa: 4b12 ldr r3, [pc, #72] ; (8003644 <HAL_RCC_ClockConfig+0x1bc>)
80035fc: 689b ldr r3, [r3, #8]
80035fe: f423 4260 bic.w r2, r3, #57344 ; 0xe000
8003602: 687b ldr r3, [r7, #4]
8003604: 691b ldr r3, [r3, #16]
8003606: 00db lsls r3, r3, #3
8003608: 490e ldr r1, [pc, #56] ; (8003644 <HAL_RCC_ClockConfig+0x1bc>)
800360a: 4313 orrs r3, r2
800360c: 608b str r3, [r1, #8]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
800360e: f000 f821 bl 8003654 <HAL_RCC_GetSysClockFreq>
8003612: 4602 mov r2, r0
8003614: 4b0b ldr r3, [pc, #44] ; (8003644 <HAL_RCC_ClockConfig+0x1bc>)
8003616: 689b ldr r3, [r3, #8]
8003618: 091b lsrs r3, r3, #4
800361a: f003 030f and.w r3, r3, #15
800361e: 490a ldr r1, [pc, #40] ; (8003648 <HAL_RCC_ClockConfig+0x1c0>)
8003620: 5ccb ldrb r3, [r1, r3]
8003622: fa22 f303 lsr.w r3, r2, r3
8003626: 4a09 ldr r2, [pc, #36] ; (800364c <HAL_RCC_ClockConfig+0x1c4>)
8003628: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings */
HAL_InitTick (uwTickPrio);
800362a: 4b09 ldr r3, [pc, #36] ; (8003650 <HAL_RCC_ClockConfig+0x1c8>)
800362c: 681b ldr r3, [r3, #0]
800362e: 4618 mov r0, r3
8003630: f7fe fbd6 bl 8001de0 <HAL_InitTick>
return HAL_OK;
8003634: 2300 movs r3, #0
}
8003636: 4618 mov r0, r3
8003638: 3710 adds r7, #16
800363a: 46bd mov sp, r7
800363c: bd80 pop {r7, pc}
800363e: bf00 nop
8003640: 40023c00 .word 0x40023c00
8003644: 40023800 .word 0x40023800
8003648: 080052e8 .word 0x080052e8
800364c: 20000004 .word 0x20000004
8003650: 20000008 .word 0x20000008
08003654 <HAL_RCC_GetSysClockFreq>:
*
*
* @retval SYSCLK frequency
*/
__weak uint32_t HAL_RCC_GetSysClockFreq(void)
{
8003654: e92d 43b0 stmdb sp!, {r4, r5, r7, r8, r9, lr}
8003658: b084 sub sp, #16
800365a: af00 add r7, sp, #0
uint32_t pllm = 0U, pllvco = 0U, pllp = 0U;
800365c: 2300 movs r3, #0
800365e: 607b str r3, [r7, #4]
8003660: 2300 movs r3, #0
8003662: 60fb str r3, [r7, #12]
8003664: 2300 movs r3, #0
8003666: 603b str r3, [r7, #0]
uint32_t sysclockfreq = 0U;
8003668: 2300 movs r3, #0
800366a: 60bb str r3, [r7, #8]
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
800366c: 4b67 ldr r3, [pc, #412] ; (800380c <HAL_RCC_GetSysClockFreq+0x1b8>)
800366e: 689b ldr r3, [r3, #8]
8003670: f003 030c and.w r3, r3, #12
8003674: 2b08 cmp r3, #8
8003676: d00d beq.n 8003694 <HAL_RCC_GetSysClockFreq+0x40>
8003678: 2b08 cmp r3, #8
800367a: f200 80bd bhi.w 80037f8 <HAL_RCC_GetSysClockFreq+0x1a4>
800367e: 2b00 cmp r3, #0
8003680: d002 beq.n 8003688 <HAL_RCC_GetSysClockFreq+0x34>
8003682: 2b04 cmp r3, #4
8003684: d003 beq.n 800368e <HAL_RCC_GetSysClockFreq+0x3a>
8003686: e0b7 b.n 80037f8 <HAL_RCC_GetSysClockFreq+0x1a4>
{
case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
{
sysclockfreq = HSI_VALUE;
8003688: 4b61 ldr r3, [pc, #388] ; (8003810 <HAL_RCC_GetSysClockFreq+0x1bc>)
800368a: 60bb str r3, [r7, #8]
break;
800368c: e0b7 b.n 80037fe <HAL_RCC_GetSysClockFreq+0x1aa>
}
case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
{
sysclockfreq = HSE_VALUE;
800368e: 4b60 ldr r3, [pc, #384] ; (8003810 <HAL_RCC_GetSysClockFreq+0x1bc>)
8003690: 60bb str r3, [r7, #8]
break;
8003692: e0b4 b.n 80037fe <HAL_RCC_GetSysClockFreq+0x1aa>
}
case RCC_CFGR_SWS_PLL: /* PLL used as system clock source */
{
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
SYSCLK = PLL_VCO / PLLP */
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
8003694: 4b5d ldr r3, [pc, #372] ; (800380c <HAL_RCC_GetSysClockFreq+0x1b8>)
8003696: 685b ldr r3, [r3, #4]
8003698: f003 033f and.w r3, r3, #63 ; 0x3f
800369c: 607b str r3, [r7, #4]
if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
800369e: 4b5b ldr r3, [pc, #364] ; (800380c <HAL_RCC_GetSysClockFreq+0x1b8>)
80036a0: 685b ldr r3, [r3, #4]
80036a2: f403 0380 and.w r3, r3, #4194304 ; 0x400000
80036a6: 2b00 cmp r3, #0
80036a8: d04d beq.n 8003746 <HAL_RCC_GetSysClockFreq+0xf2>
{
/* HSE used as PLL clock source */
pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
80036aa: 4b58 ldr r3, [pc, #352] ; (800380c <HAL_RCC_GetSysClockFreq+0x1b8>)
80036ac: 685b ldr r3, [r3, #4]
80036ae: 099b lsrs r3, r3, #6
80036b0: 461a mov r2, r3
80036b2: f04f 0300 mov.w r3, #0
80036b6: f240 10ff movw r0, #511 ; 0x1ff
80036ba: f04f 0100 mov.w r1, #0
80036be: ea02 0800 and.w r8, r2, r0
80036c2: ea03 0901 and.w r9, r3, r1
80036c6: 4640 mov r0, r8
80036c8: 4649 mov r1, r9
80036ca: f04f 0200 mov.w r2, #0
80036ce: f04f 0300 mov.w r3, #0
80036d2: 014b lsls r3, r1, #5
80036d4: ea43 63d0 orr.w r3, r3, r0, lsr #27
80036d8: 0142 lsls r2, r0, #5
80036da: 4610 mov r0, r2
80036dc: 4619 mov r1, r3
80036de: ebb0 0008 subs.w r0, r0, r8
80036e2: eb61 0109 sbc.w r1, r1, r9
80036e6: f04f 0200 mov.w r2, #0
80036ea: f04f 0300 mov.w r3, #0
80036ee: 018b lsls r3, r1, #6
80036f0: ea43 6390 orr.w r3, r3, r0, lsr #26
80036f4: 0182 lsls r2, r0, #6
80036f6: 1a12 subs r2, r2, r0
80036f8: eb63 0301 sbc.w r3, r3, r1
80036fc: f04f 0000 mov.w r0, #0
8003700: f04f 0100 mov.w r1, #0
8003704: 00d9 lsls r1, r3, #3
8003706: ea41 7152 orr.w r1, r1, r2, lsr #29
800370a: 00d0 lsls r0, r2, #3
800370c: 4602 mov r2, r0
800370e: 460b mov r3, r1
8003710: eb12 0208 adds.w r2, r2, r8
8003714: eb43 0309 adc.w r3, r3, r9
8003718: f04f 0000 mov.w r0, #0
800371c: f04f 0100 mov.w r1, #0
8003720: 0299 lsls r1, r3, #10
8003722: ea41 5192 orr.w r1, r1, r2, lsr #22
8003726: 0290 lsls r0, r2, #10
8003728: 4602 mov r2, r0
800372a: 460b mov r3, r1
800372c: 4610 mov r0, r2
800372e: 4619 mov r1, r3
8003730: 687b ldr r3, [r7, #4]
8003732: 461a mov r2, r3
8003734: f04f 0300 mov.w r3, #0
8003738: f7fc fd64 bl 8000204 <__aeabi_uldivmod>
800373c: 4602 mov r2, r0
800373e: 460b mov r3, r1
8003740: 4613 mov r3, r2
8003742: 60fb str r3, [r7, #12]
8003744: e04a b.n 80037dc <HAL_RCC_GetSysClockFreq+0x188>
}
else
{
/* HSI used as PLL clock source */
pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
8003746: 4b31 ldr r3, [pc, #196] ; (800380c <HAL_RCC_GetSysClockFreq+0x1b8>)
8003748: 685b ldr r3, [r3, #4]
800374a: 099b lsrs r3, r3, #6
800374c: 461a mov r2, r3
800374e: f04f 0300 mov.w r3, #0
8003752: f240 10ff movw r0, #511 ; 0x1ff
8003756: f04f 0100 mov.w r1, #0
800375a: ea02 0400 and.w r4, r2, r0
800375e: ea03 0501 and.w r5, r3, r1
8003762: 4620 mov r0, r4
8003764: 4629 mov r1, r5
8003766: f04f 0200 mov.w r2, #0
800376a: f04f 0300 mov.w r3, #0
800376e: 014b lsls r3, r1, #5
8003770: ea43 63d0 orr.w r3, r3, r0, lsr #27
8003774: 0142 lsls r2, r0, #5
8003776: 4610 mov r0, r2
8003778: 4619 mov r1, r3
800377a: 1b00 subs r0, r0, r4
800377c: eb61 0105 sbc.w r1, r1, r5
8003780: f04f 0200 mov.w r2, #0
8003784: f04f 0300 mov.w r3, #0
8003788: 018b lsls r3, r1, #6
800378a: ea43 6390 orr.w r3, r3, r0, lsr #26
800378e: 0182 lsls r2, r0, #6
8003790: 1a12 subs r2, r2, r0
8003792: eb63 0301 sbc.w r3, r3, r1
8003796: f04f 0000 mov.w r0, #0
800379a: f04f 0100 mov.w r1, #0
800379e: 00d9 lsls r1, r3, #3
80037a0: ea41 7152 orr.w r1, r1, r2, lsr #29
80037a4: 00d0 lsls r0, r2, #3
80037a6: 4602 mov r2, r0
80037a8: 460b mov r3, r1
80037aa: 1912 adds r2, r2, r4
80037ac: eb45 0303 adc.w r3, r5, r3
80037b0: f04f 0000 mov.w r0, #0
80037b4: f04f 0100 mov.w r1, #0
80037b8: 0299 lsls r1, r3, #10
80037ba: ea41 5192 orr.w r1, r1, r2, lsr #22
80037be: 0290 lsls r0, r2, #10
80037c0: 4602 mov r2, r0
80037c2: 460b mov r3, r1
80037c4: 4610 mov r0, r2
80037c6: 4619 mov r1, r3
80037c8: 687b ldr r3, [r7, #4]
80037ca: 461a mov r2, r3
80037cc: f04f 0300 mov.w r3, #0
80037d0: f7fc fd18 bl 8000204 <__aeabi_uldivmod>
80037d4: 4602 mov r2, r0
80037d6: 460b mov r3, r1
80037d8: 4613 mov r3, r2
80037da: 60fb str r3, [r7, #12]
}
pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U);
80037dc: 4b0b ldr r3, [pc, #44] ; (800380c <HAL_RCC_GetSysClockFreq+0x1b8>)
80037de: 685b ldr r3, [r3, #4]
80037e0: 0c1b lsrs r3, r3, #16
80037e2: f003 0303 and.w r3, r3, #3
80037e6: 3301 adds r3, #1
80037e8: 005b lsls r3, r3, #1
80037ea: 603b str r3, [r7, #0]
sysclockfreq = pllvco/pllp;
80037ec: 68fa ldr r2, [r7, #12]
80037ee: 683b ldr r3, [r7, #0]
80037f0: fbb2 f3f3 udiv r3, r2, r3
80037f4: 60bb str r3, [r7, #8]
break;
80037f6: e002 b.n 80037fe <HAL_RCC_GetSysClockFreq+0x1aa>
}
default:
{
sysclockfreq = HSI_VALUE;
80037f8: 4b05 ldr r3, [pc, #20] ; (8003810 <HAL_RCC_GetSysClockFreq+0x1bc>)
80037fa: 60bb str r3, [r7, #8]
break;
80037fc: bf00 nop
}
}
return sysclockfreq;
80037fe: 68bb ldr r3, [r7, #8]
}
8003800: 4618 mov r0, r3
8003802: 3710 adds r7, #16
8003804: 46bd mov sp, r7
8003806: e8bd 83b0 ldmia.w sp!, {r4, r5, r7, r8, r9, pc}
800380a: bf00 nop
800380c: 40023800 .word 0x40023800
8003810: 00f42400 .word 0x00f42400
08003814 <HAL_RCC_GetHCLKFreq>:
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
* and updated within this function
* @retval HCLK frequency
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
8003814: b480 push {r7}
8003816: af00 add r7, sp, #0
return SystemCoreClock;
8003818: 4b03 ldr r3, [pc, #12] ; (8003828 <HAL_RCC_GetHCLKFreq+0x14>)
800381a: 681b ldr r3, [r3, #0]
}
800381c: 4618 mov r0, r3
800381e: 46bd mov sp, r7
8003820: f85d 7b04 ldr.w r7, [sp], #4
8003824: 4770 bx lr
8003826: bf00 nop
8003828: 20000004 .word 0x20000004
0800382c <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
800382c: b580 push {r7, lr}
800382e: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]);
8003830: f7ff fff0 bl 8003814 <HAL_RCC_GetHCLKFreq>
8003834: 4602 mov r2, r0
8003836: 4b05 ldr r3, [pc, #20] ; (800384c <HAL_RCC_GetPCLK1Freq+0x20>)
8003838: 689b ldr r3, [r3, #8]
800383a: 0a9b lsrs r3, r3, #10
800383c: f003 0307 and.w r3, r3, #7
8003840: 4903 ldr r1, [pc, #12] ; (8003850 <HAL_RCC_GetPCLK1Freq+0x24>)
8003842: 5ccb ldrb r3, [r1, r3]
8003844: fa22 f303 lsr.w r3, r2, r3
}
8003848: 4618 mov r0, r3
800384a: bd80 pop {r7, pc}
800384c: 40023800 .word 0x40023800
8003850: 080052f8 .word 0x080052f8
08003854 <HAL_RCC_GetPCLK2Freq>:
* @note Each time PCLK2 changes, this function must be called to update the
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK2 frequency
*/
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
8003854: b580 push {r7, lr}
8003856: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]);
8003858: f7ff ffdc bl 8003814 <HAL_RCC_GetHCLKFreq>
800385c: 4602 mov r2, r0
800385e: 4b05 ldr r3, [pc, #20] ; (8003874 <HAL_RCC_GetPCLK2Freq+0x20>)
8003860: 689b ldr r3, [r3, #8]
8003862: 0b5b lsrs r3, r3, #13
8003864: f003 0307 and.w r3, r3, #7
8003868: 4903 ldr r1, [pc, #12] ; (8003878 <HAL_RCC_GetPCLK2Freq+0x24>)
800386a: 5ccb ldrb r3, [r1, r3]
800386c: fa22 f303 lsr.w r3, r2, r3
}
8003870: 4618 mov r0, r3
8003872: bd80 pop {r7, pc}
8003874: 40023800 .word 0x40023800
8003878: 080052f8 .word 0x080052f8
0800387c <HAL_RCC_OscConfig>:
* @note This function add the PLL/PLLR factor management during PLL configuration this feature
* is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
800387c: b580 push {r7, lr}
800387e: b086 sub sp, #24
8003880: af00 add r7, sp, #0
8003882: 6078 str r0, [r7, #4]
uint32_t tickstart, pll_config;
/* Check Null pointer */
if(RCC_OscInitStruct == NULL)
8003884: 687b ldr r3, [r7, #4]
8003886: 2b00 cmp r3, #0
8003888: d101 bne.n 800388e <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
800388a: 2301 movs r3, #1
800388c: e270 b.n 8003d70 <HAL_RCC_OscConfig+0x4f4>
}
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
800388e: 687b ldr r3, [r7, #4]
8003890: 681b ldr r3, [r3, #0]
8003892: f003 0301 and.w r3, r3, #1
8003896: 2b00 cmp r3, #0
8003898: d075 beq.n 8003986 <HAL_RCC_OscConfig+0x10a>
#if defined(STM32F446xx)
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) ||\
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
#else
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
800389a: 4ba3 ldr r3, [pc, #652] ; (8003b28 <HAL_RCC_OscConfig+0x2ac>)
800389c: 689b ldr r3, [r3, #8]
800389e: f003 030c and.w r3, r3, #12
80038a2: 2b04 cmp r3, #4
80038a4: d00c beq.n 80038c0 <HAL_RCC_OscConfig+0x44>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
80038a6: 4ba0 ldr r3, [pc, #640] ; (8003b28 <HAL_RCC_OscConfig+0x2ac>)
80038a8: 689b ldr r3, [r3, #8]
80038aa: f003 030c and.w r3, r3, #12
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
80038ae: 2b08 cmp r3, #8
80038b0: d112 bne.n 80038d8 <HAL_RCC_OscConfig+0x5c>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
80038b2: 4b9d ldr r3, [pc, #628] ; (8003b28 <HAL_RCC_OscConfig+0x2ac>)
80038b4: 685b ldr r3, [r3, #4]
80038b6: f403 0380 and.w r3, r3, #4194304 ; 0x400000
80038ba: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
80038be: d10b bne.n 80038d8 <HAL_RCC_OscConfig+0x5c>
#endif /* STM32F446xx */
{
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
80038c0: 4b99 ldr r3, [pc, #612] ; (8003b28 <HAL_RCC_OscConfig+0x2ac>)
80038c2: 681b ldr r3, [r3, #0]
80038c4: f403 3300 and.w r3, r3, #131072 ; 0x20000
80038c8: 2b00 cmp r3, #0
80038ca: d05b beq.n 8003984 <HAL_RCC_OscConfig+0x108>
80038cc: 687b ldr r3, [r7, #4]
80038ce: 685b ldr r3, [r3, #4]
80038d0: 2b00 cmp r3, #0
80038d2: d157 bne.n 8003984 <HAL_RCC_OscConfig+0x108>
{
return HAL_ERROR;
80038d4: 2301 movs r3, #1
80038d6: e24b b.n 8003d70 <HAL_RCC_OscConfig+0x4f4>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
80038d8: 687b ldr r3, [r7, #4]
80038da: 685b ldr r3, [r3, #4]
80038dc: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
80038e0: d106 bne.n 80038f0 <HAL_RCC_OscConfig+0x74>
80038e2: 4b91 ldr r3, [pc, #580] ; (8003b28 <HAL_RCC_OscConfig+0x2ac>)
80038e4: 681b ldr r3, [r3, #0]
80038e6: 4a90 ldr r2, [pc, #576] ; (8003b28 <HAL_RCC_OscConfig+0x2ac>)
80038e8: f443 3380 orr.w r3, r3, #65536 ; 0x10000
80038ec: 6013 str r3, [r2, #0]
80038ee: e01d b.n 800392c <HAL_RCC_OscConfig+0xb0>
80038f0: 687b ldr r3, [r7, #4]
80038f2: 685b ldr r3, [r3, #4]
80038f4: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
80038f8: d10c bne.n 8003914 <HAL_RCC_OscConfig+0x98>
80038fa: 4b8b ldr r3, [pc, #556] ; (8003b28 <HAL_RCC_OscConfig+0x2ac>)
80038fc: 681b ldr r3, [r3, #0]
80038fe: 4a8a ldr r2, [pc, #552] ; (8003b28 <HAL_RCC_OscConfig+0x2ac>)
8003900: f443 2380 orr.w r3, r3, #262144 ; 0x40000
8003904: 6013 str r3, [r2, #0]
8003906: 4b88 ldr r3, [pc, #544] ; (8003b28 <HAL_RCC_OscConfig+0x2ac>)
8003908: 681b ldr r3, [r3, #0]
800390a: 4a87 ldr r2, [pc, #540] ; (8003b28 <HAL_RCC_OscConfig+0x2ac>)
800390c: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8003910: 6013 str r3, [r2, #0]
8003912: e00b b.n 800392c <HAL_RCC_OscConfig+0xb0>
8003914: 4b84 ldr r3, [pc, #528] ; (8003b28 <HAL_RCC_OscConfig+0x2ac>)
8003916: 681b ldr r3, [r3, #0]
8003918: 4a83 ldr r2, [pc, #524] ; (8003b28 <HAL_RCC_OscConfig+0x2ac>)
800391a: f423 3380 bic.w r3, r3, #65536 ; 0x10000
800391e: 6013 str r3, [r2, #0]
8003920: 4b81 ldr r3, [pc, #516] ; (8003b28 <HAL_RCC_OscConfig+0x2ac>)
8003922: 681b ldr r3, [r3, #0]
8003924: 4a80 ldr r2, [pc, #512] ; (8003b28 <HAL_RCC_OscConfig+0x2ac>)
8003926: f423 2380 bic.w r3, r3, #262144 ; 0x40000
800392a: 6013 str r3, [r2, #0]
/* Check the HSE State */
if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
800392c: 687b ldr r3, [r7, #4]
800392e: 685b ldr r3, [r3, #4]
8003930: 2b00 cmp r3, #0
8003932: d013 beq.n 800395c <HAL_RCC_OscConfig+0xe0>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003934: f7fe fa98 bl 8001e68 <HAL_GetTick>
8003938: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
800393a: e008 b.n 800394e <HAL_RCC_OscConfig+0xd2>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
800393c: f7fe fa94 bl 8001e68 <HAL_GetTick>
8003940: 4602 mov r2, r0
8003942: 693b ldr r3, [r7, #16]
8003944: 1ad3 subs r3, r2, r3
8003946: 2b64 cmp r3, #100 ; 0x64
8003948: d901 bls.n 800394e <HAL_RCC_OscConfig+0xd2>
{
return HAL_TIMEOUT;
800394a: 2303 movs r3, #3
800394c: e210 b.n 8003d70 <HAL_RCC_OscConfig+0x4f4>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
800394e: 4b76 ldr r3, [pc, #472] ; (8003b28 <HAL_RCC_OscConfig+0x2ac>)
8003950: 681b ldr r3, [r3, #0]
8003952: f403 3300 and.w r3, r3, #131072 ; 0x20000
8003956: 2b00 cmp r3, #0
8003958: d0f0 beq.n 800393c <HAL_RCC_OscConfig+0xc0>
800395a: e014 b.n 8003986 <HAL_RCC_OscConfig+0x10a>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
800395c: f7fe fa84 bl 8001e68 <HAL_GetTick>
8003960: 6138 str r0, [r7, #16]
/* Wait till HSE is bypassed or disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8003962: e008 b.n 8003976 <HAL_RCC_OscConfig+0xfa>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
8003964: f7fe fa80 bl 8001e68 <HAL_GetTick>
8003968: 4602 mov r2, r0
800396a: 693b ldr r3, [r7, #16]
800396c: 1ad3 subs r3, r2, r3
800396e: 2b64 cmp r3, #100 ; 0x64
8003970: d901 bls.n 8003976 <HAL_RCC_OscConfig+0xfa>
{
return HAL_TIMEOUT;
8003972: 2303 movs r3, #3
8003974: e1fc b.n 8003d70 <HAL_RCC_OscConfig+0x4f4>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8003976: 4b6c ldr r3, [pc, #432] ; (8003b28 <HAL_RCC_OscConfig+0x2ac>)
8003978: 681b ldr r3, [r3, #0]
800397a: f403 3300 and.w r3, r3, #131072 ; 0x20000
800397e: 2b00 cmp r3, #0
8003980: d1f0 bne.n 8003964 <HAL_RCC_OscConfig+0xe8>
8003982: e000 b.n 8003986 <HAL_RCC_OscConfig+0x10a>
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8003984: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
8003986: 687b ldr r3, [r7, #4]
8003988: 681b ldr r3, [r3, #0]
800398a: f003 0302 and.w r3, r3, #2
800398e: 2b00 cmp r3, #0
8003990: d063 beq.n 8003a5a <HAL_RCC_OscConfig+0x1de>
#if defined(STM32F446xx)
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) ||\
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
#else
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
8003992: 4b65 ldr r3, [pc, #404] ; (8003b28 <HAL_RCC_OscConfig+0x2ac>)
8003994: 689b ldr r3, [r3, #8]
8003996: f003 030c and.w r3, r3, #12
800399a: 2b00 cmp r3, #0
800399c: d00b beq.n 80039b6 <HAL_RCC_OscConfig+0x13a>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
800399e: 4b62 ldr r3, [pc, #392] ; (8003b28 <HAL_RCC_OscConfig+0x2ac>)
80039a0: 689b ldr r3, [r3, #8]
80039a2: f003 030c and.w r3, r3, #12
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
80039a6: 2b08 cmp r3, #8
80039a8: d11c bne.n 80039e4 <HAL_RCC_OscConfig+0x168>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
80039aa: 4b5f ldr r3, [pc, #380] ; (8003b28 <HAL_RCC_OscConfig+0x2ac>)
80039ac: 685b ldr r3, [r3, #4]
80039ae: f403 0380 and.w r3, r3, #4194304 ; 0x400000
80039b2: 2b00 cmp r3, #0
80039b4: d116 bne.n 80039e4 <HAL_RCC_OscConfig+0x168>
#endif /* STM32F446xx */
{
/* When HSI is used as system clock it will not disabled */
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
80039b6: 4b5c ldr r3, [pc, #368] ; (8003b28 <HAL_RCC_OscConfig+0x2ac>)
80039b8: 681b ldr r3, [r3, #0]
80039ba: f003 0302 and.w r3, r3, #2
80039be: 2b00 cmp r3, #0
80039c0: d005 beq.n 80039ce <HAL_RCC_OscConfig+0x152>
80039c2: 687b ldr r3, [r7, #4]
80039c4: 68db ldr r3, [r3, #12]
80039c6: 2b01 cmp r3, #1
80039c8: d001 beq.n 80039ce <HAL_RCC_OscConfig+0x152>
{
return HAL_ERROR;
80039ca: 2301 movs r3, #1
80039cc: e1d0 b.n 8003d70 <HAL_RCC_OscConfig+0x4f4>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
80039ce: 4b56 ldr r3, [pc, #344] ; (8003b28 <HAL_RCC_OscConfig+0x2ac>)
80039d0: 681b ldr r3, [r3, #0]
80039d2: f023 02f8 bic.w r2, r3, #248 ; 0xf8
80039d6: 687b ldr r3, [r7, #4]
80039d8: 691b ldr r3, [r3, #16]
80039da: 00db lsls r3, r3, #3
80039dc: 4952 ldr r1, [pc, #328] ; (8003b28 <HAL_RCC_OscConfig+0x2ac>)
80039de: 4313 orrs r3, r2
80039e0: 600b str r3, [r1, #0]
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
80039e2: e03a b.n 8003a5a <HAL_RCC_OscConfig+0x1de>
}
}
else
{
/* Check the HSI State */
if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
80039e4: 687b ldr r3, [r7, #4]
80039e6: 68db ldr r3, [r3, #12]
80039e8: 2b00 cmp r3, #0
80039ea: d020 beq.n 8003a2e <HAL_RCC_OscConfig+0x1b2>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
80039ec: 4b4f ldr r3, [pc, #316] ; (8003b2c <HAL_RCC_OscConfig+0x2b0>)
80039ee: 2201 movs r2, #1
80039f0: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80039f2: f7fe fa39 bl 8001e68 <HAL_GetTick>
80039f6: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
80039f8: e008 b.n 8003a0c <HAL_RCC_OscConfig+0x190>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
80039fa: f7fe fa35 bl 8001e68 <HAL_GetTick>
80039fe: 4602 mov r2, r0
8003a00: 693b ldr r3, [r7, #16]
8003a02: 1ad3 subs r3, r2, r3
8003a04: 2b02 cmp r3, #2
8003a06: d901 bls.n 8003a0c <HAL_RCC_OscConfig+0x190>
{
return HAL_TIMEOUT;
8003a08: 2303 movs r3, #3
8003a0a: e1b1 b.n 8003d70 <HAL_RCC_OscConfig+0x4f4>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8003a0c: 4b46 ldr r3, [pc, #280] ; (8003b28 <HAL_RCC_OscConfig+0x2ac>)
8003a0e: 681b ldr r3, [r3, #0]
8003a10: f003 0302 and.w r3, r3, #2
8003a14: 2b00 cmp r3, #0
8003a16: d0f0 beq.n 80039fa <HAL_RCC_OscConfig+0x17e>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8003a18: 4b43 ldr r3, [pc, #268] ; (8003b28 <HAL_RCC_OscConfig+0x2ac>)
8003a1a: 681b ldr r3, [r3, #0]
8003a1c: f023 02f8 bic.w r2, r3, #248 ; 0xf8
8003a20: 687b ldr r3, [r7, #4]
8003a22: 691b ldr r3, [r3, #16]
8003a24: 00db lsls r3, r3, #3
8003a26: 4940 ldr r1, [pc, #256] ; (8003b28 <HAL_RCC_OscConfig+0x2ac>)
8003a28: 4313 orrs r3, r2
8003a2a: 600b str r3, [r1, #0]
8003a2c: e015 b.n 8003a5a <HAL_RCC_OscConfig+0x1de>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
8003a2e: 4b3f ldr r3, [pc, #252] ; (8003b2c <HAL_RCC_OscConfig+0x2b0>)
8003a30: 2200 movs r2, #0
8003a32: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003a34: f7fe fa18 bl 8001e68 <HAL_GetTick>
8003a38: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8003a3a: e008 b.n 8003a4e <HAL_RCC_OscConfig+0x1d2>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
8003a3c: f7fe fa14 bl 8001e68 <HAL_GetTick>
8003a40: 4602 mov r2, r0
8003a42: 693b ldr r3, [r7, #16]
8003a44: 1ad3 subs r3, r2, r3
8003a46: 2b02 cmp r3, #2
8003a48: d901 bls.n 8003a4e <HAL_RCC_OscConfig+0x1d2>
{
return HAL_TIMEOUT;
8003a4a: 2303 movs r3, #3
8003a4c: e190 b.n 8003d70 <HAL_RCC_OscConfig+0x4f4>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8003a4e: 4b36 ldr r3, [pc, #216] ; (8003b28 <HAL_RCC_OscConfig+0x2ac>)
8003a50: 681b ldr r3, [r3, #0]
8003a52: f003 0302 and.w r3, r3, #2
8003a56: 2b00 cmp r3, #0
8003a58: d1f0 bne.n 8003a3c <HAL_RCC_OscConfig+0x1c0>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
8003a5a: 687b ldr r3, [r7, #4]
8003a5c: 681b ldr r3, [r3, #0]
8003a5e: f003 0308 and.w r3, r3, #8
8003a62: 2b00 cmp r3, #0
8003a64: d030 beq.n 8003ac8 <HAL_RCC_OscConfig+0x24c>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
8003a66: 687b ldr r3, [r7, #4]
8003a68: 695b ldr r3, [r3, #20]
8003a6a: 2b00 cmp r3, #0
8003a6c: d016 beq.n 8003a9c <HAL_RCC_OscConfig+0x220>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
8003a6e: 4b30 ldr r3, [pc, #192] ; (8003b30 <HAL_RCC_OscConfig+0x2b4>)
8003a70: 2201 movs r2, #1
8003a72: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003a74: f7fe f9f8 bl 8001e68 <HAL_GetTick>
8003a78: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8003a7a: e008 b.n 8003a8e <HAL_RCC_OscConfig+0x212>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
8003a7c: f7fe f9f4 bl 8001e68 <HAL_GetTick>
8003a80: 4602 mov r2, r0
8003a82: 693b ldr r3, [r7, #16]
8003a84: 1ad3 subs r3, r2, r3
8003a86: 2b02 cmp r3, #2
8003a88: d901 bls.n 8003a8e <HAL_RCC_OscConfig+0x212>
{
return HAL_TIMEOUT;
8003a8a: 2303 movs r3, #3
8003a8c: e170 b.n 8003d70 <HAL_RCC_OscConfig+0x4f4>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8003a8e: 4b26 ldr r3, [pc, #152] ; (8003b28 <HAL_RCC_OscConfig+0x2ac>)
8003a90: 6f5b ldr r3, [r3, #116] ; 0x74
8003a92: f003 0302 and.w r3, r3, #2
8003a96: 2b00 cmp r3, #0
8003a98: d0f0 beq.n 8003a7c <HAL_RCC_OscConfig+0x200>
8003a9a: e015 b.n 8003ac8 <HAL_RCC_OscConfig+0x24c>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8003a9c: 4b24 ldr r3, [pc, #144] ; (8003b30 <HAL_RCC_OscConfig+0x2b4>)
8003a9e: 2200 movs r2, #0
8003aa0: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003aa2: f7fe f9e1 bl 8001e68 <HAL_GetTick>
8003aa6: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8003aa8: e008 b.n 8003abc <HAL_RCC_OscConfig+0x240>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
8003aaa: f7fe f9dd bl 8001e68 <HAL_GetTick>
8003aae: 4602 mov r2, r0
8003ab0: 693b ldr r3, [r7, #16]
8003ab2: 1ad3 subs r3, r2, r3
8003ab4: 2b02 cmp r3, #2
8003ab6: d901 bls.n 8003abc <HAL_RCC_OscConfig+0x240>
{
return HAL_TIMEOUT;
8003ab8: 2303 movs r3, #3
8003aba: e159 b.n 8003d70 <HAL_RCC_OscConfig+0x4f4>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8003abc: 4b1a ldr r3, [pc, #104] ; (8003b28 <HAL_RCC_OscConfig+0x2ac>)
8003abe: 6f5b ldr r3, [r3, #116] ; 0x74
8003ac0: f003 0302 and.w r3, r3, #2
8003ac4: 2b00 cmp r3, #0
8003ac6: d1f0 bne.n 8003aaa <HAL_RCC_OscConfig+0x22e>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8003ac8: 687b ldr r3, [r7, #4]
8003aca: 681b ldr r3, [r3, #0]
8003acc: f003 0304 and.w r3, r3, #4
8003ad0: 2b00 cmp r3, #0
8003ad2: f000 80a0 beq.w 8003c16 <HAL_RCC_OscConfig+0x39a>
{
FlagStatus pwrclkchanged = RESET;
8003ad6: 2300 movs r3, #0
8003ad8: 75fb strb r3, [r7, #23]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
8003ada: 4b13 ldr r3, [pc, #76] ; (8003b28 <HAL_RCC_OscConfig+0x2ac>)
8003adc: 6c1b ldr r3, [r3, #64] ; 0x40
8003ade: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8003ae2: 2b00 cmp r3, #0
8003ae4: d10f bne.n 8003b06 <HAL_RCC_OscConfig+0x28a>
{
__HAL_RCC_PWR_CLK_ENABLE();
8003ae6: 2300 movs r3, #0
8003ae8: 60bb str r3, [r7, #8]
8003aea: 4b0f ldr r3, [pc, #60] ; (8003b28 <HAL_RCC_OscConfig+0x2ac>)
8003aec: 6c1b ldr r3, [r3, #64] ; 0x40
8003aee: 4a0e ldr r2, [pc, #56] ; (8003b28 <HAL_RCC_OscConfig+0x2ac>)
8003af0: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8003af4: 6413 str r3, [r2, #64] ; 0x40
8003af6: 4b0c ldr r3, [pc, #48] ; (8003b28 <HAL_RCC_OscConfig+0x2ac>)
8003af8: 6c1b ldr r3, [r3, #64] ; 0x40
8003afa: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8003afe: 60bb str r3, [r7, #8]
8003b00: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8003b02: 2301 movs r3, #1
8003b04: 75fb strb r3, [r7, #23]
}
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8003b06: 4b0b ldr r3, [pc, #44] ; (8003b34 <HAL_RCC_OscConfig+0x2b8>)
8003b08: 681b ldr r3, [r3, #0]
8003b0a: f403 7380 and.w r3, r3, #256 ; 0x100
8003b0e: 2b00 cmp r3, #0
8003b10: d121 bne.n 8003b56 <HAL_RCC_OscConfig+0x2da>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
8003b12: 4b08 ldr r3, [pc, #32] ; (8003b34 <HAL_RCC_OscConfig+0x2b8>)
8003b14: 681b ldr r3, [r3, #0]
8003b16: 4a07 ldr r2, [pc, #28] ; (8003b34 <HAL_RCC_OscConfig+0x2b8>)
8003b18: f443 7380 orr.w r3, r3, #256 ; 0x100
8003b1c: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8003b1e: f7fe f9a3 bl 8001e68 <HAL_GetTick>
8003b22: 6138 str r0, [r7, #16]
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8003b24: e011 b.n 8003b4a <HAL_RCC_OscConfig+0x2ce>
8003b26: bf00 nop
8003b28: 40023800 .word 0x40023800
8003b2c: 42470000 .word 0x42470000
8003b30: 42470e80 .word 0x42470e80
8003b34: 40007000 .word 0x40007000
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8003b38: f7fe f996 bl 8001e68 <HAL_GetTick>
8003b3c: 4602 mov r2, r0
8003b3e: 693b ldr r3, [r7, #16]
8003b40: 1ad3 subs r3, r2, r3
8003b42: 2b02 cmp r3, #2
8003b44: d901 bls.n 8003b4a <HAL_RCC_OscConfig+0x2ce>
{
return HAL_TIMEOUT;
8003b46: 2303 movs r3, #3
8003b48: e112 b.n 8003d70 <HAL_RCC_OscConfig+0x4f4>
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8003b4a: 4b8b ldr r3, [pc, #556] ; (8003d78 <HAL_RCC_OscConfig+0x4fc>)
8003b4c: 681b ldr r3, [r3, #0]
8003b4e: f403 7380 and.w r3, r3, #256 ; 0x100
8003b52: 2b00 cmp r3, #0
8003b54: d0f0 beq.n 8003b38 <HAL_RCC_OscConfig+0x2bc>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8003b56: 687b ldr r3, [r7, #4]
8003b58: 689b ldr r3, [r3, #8]
8003b5a: 2b01 cmp r3, #1
8003b5c: d106 bne.n 8003b6c <HAL_RCC_OscConfig+0x2f0>
8003b5e: 4b87 ldr r3, [pc, #540] ; (8003d7c <HAL_RCC_OscConfig+0x500>)
8003b60: 6f1b ldr r3, [r3, #112] ; 0x70
8003b62: 4a86 ldr r2, [pc, #536] ; (8003d7c <HAL_RCC_OscConfig+0x500>)
8003b64: f043 0301 orr.w r3, r3, #1
8003b68: 6713 str r3, [r2, #112] ; 0x70
8003b6a: e01c b.n 8003ba6 <HAL_RCC_OscConfig+0x32a>
8003b6c: 687b ldr r3, [r7, #4]
8003b6e: 689b ldr r3, [r3, #8]
8003b70: 2b05 cmp r3, #5
8003b72: d10c bne.n 8003b8e <HAL_RCC_OscConfig+0x312>
8003b74: 4b81 ldr r3, [pc, #516] ; (8003d7c <HAL_RCC_OscConfig+0x500>)
8003b76: 6f1b ldr r3, [r3, #112] ; 0x70
8003b78: 4a80 ldr r2, [pc, #512] ; (8003d7c <HAL_RCC_OscConfig+0x500>)
8003b7a: f043 0304 orr.w r3, r3, #4
8003b7e: 6713 str r3, [r2, #112] ; 0x70
8003b80: 4b7e ldr r3, [pc, #504] ; (8003d7c <HAL_RCC_OscConfig+0x500>)
8003b82: 6f1b ldr r3, [r3, #112] ; 0x70
8003b84: 4a7d ldr r2, [pc, #500] ; (8003d7c <HAL_RCC_OscConfig+0x500>)
8003b86: f043 0301 orr.w r3, r3, #1
8003b8a: 6713 str r3, [r2, #112] ; 0x70
8003b8c: e00b b.n 8003ba6 <HAL_RCC_OscConfig+0x32a>
8003b8e: 4b7b ldr r3, [pc, #492] ; (8003d7c <HAL_RCC_OscConfig+0x500>)
8003b90: 6f1b ldr r3, [r3, #112] ; 0x70
8003b92: 4a7a ldr r2, [pc, #488] ; (8003d7c <HAL_RCC_OscConfig+0x500>)
8003b94: f023 0301 bic.w r3, r3, #1
8003b98: 6713 str r3, [r2, #112] ; 0x70
8003b9a: 4b78 ldr r3, [pc, #480] ; (8003d7c <HAL_RCC_OscConfig+0x500>)
8003b9c: 6f1b ldr r3, [r3, #112] ; 0x70
8003b9e: 4a77 ldr r2, [pc, #476] ; (8003d7c <HAL_RCC_OscConfig+0x500>)
8003ba0: f023 0304 bic.w r3, r3, #4
8003ba4: 6713 str r3, [r2, #112] ; 0x70
/* Check the LSE State */
if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
8003ba6: 687b ldr r3, [r7, #4]
8003ba8: 689b ldr r3, [r3, #8]
8003baa: 2b00 cmp r3, #0
8003bac: d015 beq.n 8003bda <HAL_RCC_OscConfig+0x35e>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003bae: f7fe f95b bl 8001e68 <HAL_GetTick>
8003bb2: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8003bb4: e00a b.n 8003bcc <HAL_RCC_OscConfig+0x350>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
8003bb6: f7fe f957 bl 8001e68 <HAL_GetTick>
8003bba: 4602 mov r2, r0
8003bbc: 693b ldr r3, [r7, #16]
8003bbe: 1ad3 subs r3, r2, r3
8003bc0: f241 3288 movw r2, #5000 ; 0x1388
8003bc4: 4293 cmp r3, r2
8003bc6: d901 bls.n 8003bcc <HAL_RCC_OscConfig+0x350>
{
return HAL_TIMEOUT;
8003bc8: 2303 movs r3, #3
8003bca: e0d1 b.n 8003d70 <HAL_RCC_OscConfig+0x4f4>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8003bcc: 4b6b ldr r3, [pc, #428] ; (8003d7c <HAL_RCC_OscConfig+0x500>)
8003bce: 6f1b ldr r3, [r3, #112] ; 0x70
8003bd0: f003 0302 and.w r3, r3, #2
8003bd4: 2b00 cmp r3, #0
8003bd6: d0ee beq.n 8003bb6 <HAL_RCC_OscConfig+0x33a>
8003bd8: e014 b.n 8003c04 <HAL_RCC_OscConfig+0x388>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003bda: f7fe f945 bl 8001e68 <HAL_GetTick>
8003bde: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8003be0: e00a b.n 8003bf8 <HAL_RCC_OscConfig+0x37c>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
8003be2: f7fe f941 bl 8001e68 <HAL_GetTick>
8003be6: 4602 mov r2, r0
8003be8: 693b ldr r3, [r7, #16]
8003bea: 1ad3 subs r3, r2, r3
8003bec: f241 3288 movw r2, #5000 ; 0x1388
8003bf0: 4293 cmp r3, r2
8003bf2: d901 bls.n 8003bf8 <HAL_RCC_OscConfig+0x37c>
{
return HAL_TIMEOUT;
8003bf4: 2303 movs r3, #3
8003bf6: e0bb b.n 8003d70 <HAL_RCC_OscConfig+0x4f4>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8003bf8: 4b60 ldr r3, [pc, #384] ; (8003d7c <HAL_RCC_OscConfig+0x500>)
8003bfa: 6f1b ldr r3, [r3, #112] ; 0x70
8003bfc: f003 0302 and.w r3, r3, #2
8003c00: 2b00 cmp r3, #0
8003c02: d1ee bne.n 8003be2 <HAL_RCC_OscConfig+0x366>
}
}
}
/* Restore clock configuration if changed */
if(pwrclkchanged == SET)
8003c04: 7dfb ldrb r3, [r7, #23]
8003c06: 2b01 cmp r3, #1
8003c08: d105 bne.n 8003c16 <HAL_RCC_OscConfig+0x39a>
{
__HAL_RCC_PWR_CLK_DISABLE();
8003c0a: 4b5c ldr r3, [pc, #368] ; (8003d7c <HAL_RCC_OscConfig+0x500>)
8003c0c: 6c1b ldr r3, [r3, #64] ; 0x40
8003c0e: 4a5b ldr r2, [pc, #364] ; (8003d7c <HAL_RCC_OscConfig+0x500>)
8003c10: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
8003c14: 6413 str r3, [r2, #64] ; 0x40
}
}
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
8003c16: 687b ldr r3, [r7, #4]
8003c18: 699b ldr r3, [r3, #24]
8003c1a: 2b00 cmp r3, #0
8003c1c: f000 80a7 beq.w 8003d6e <HAL_RCC_OscConfig+0x4f2>
{
/* Check if the PLL is used as system clock or not */
if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
8003c20: 4b56 ldr r3, [pc, #344] ; (8003d7c <HAL_RCC_OscConfig+0x500>)
8003c22: 689b ldr r3, [r3, #8]
8003c24: f003 030c and.w r3, r3, #12
8003c28: 2b08 cmp r3, #8
8003c2a: d060 beq.n 8003cee <HAL_RCC_OscConfig+0x472>
{
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
8003c2c: 687b ldr r3, [r7, #4]
8003c2e: 699b ldr r3, [r3, #24]
8003c30: 2b02 cmp r3, #2
8003c32: d145 bne.n 8003cc0 <HAL_RCC_OscConfig+0x444>
assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8003c34: 4b52 ldr r3, [pc, #328] ; (8003d80 <HAL_RCC_OscConfig+0x504>)
8003c36: 2200 movs r2, #0
8003c38: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003c3a: f7fe f915 bl 8001e68 <HAL_GetTick>
8003c3e: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8003c40: e008 b.n 8003c54 <HAL_RCC_OscConfig+0x3d8>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8003c42: f7fe f911 bl 8001e68 <HAL_GetTick>
8003c46: 4602 mov r2, r0
8003c48: 693b ldr r3, [r7, #16]
8003c4a: 1ad3 subs r3, r2, r3
8003c4c: 2b02 cmp r3, #2
8003c4e: d901 bls.n 8003c54 <HAL_RCC_OscConfig+0x3d8>
{
return HAL_TIMEOUT;
8003c50: 2303 movs r3, #3
8003c52: e08d b.n 8003d70 <HAL_RCC_OscConfig+0x4f4>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8003c54: 4b49 ldr r3, [pc, #292] ; (8003d7c <HAL_RCC_OscConfig+0x500>)
8003c56: 681b ldr r3, [r3, #0]
8003c58: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8003c5c: 2b00 cmp r3, #0
8003c5e: d1f0 bne.n 8003c42 <HAL_RCC_OscConfig+0x3c6>
}
}
/* Configure the main PLL clock source, multiplication and division factors. */
WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \
8003c60: 687b ldr r3, [r7, #4]
8003c62: 69da ldr r2, [r3, #28]
8003c64: 687b ldr r3, [r7, #4]
8003c66: 6a1b ldr r3, [r3, #32]
8003c68: 431a orrs r2, r3
8003c6a: 687b ldr r3, [r7, #4]
8003c6c: 6a5b ldr r3, [r3, #36] ; 0x24
8003c6e: 019b lsls r3, r3, #6
8003c70: 431a orrs r2, r3
8003c72: 687b ldr r3, [r7, #4]
8003c74: 6a9b ldr r3, [r3, #40] ; 0x28
8003c76: 085b lsrs r3, r3, #1
8003c78: 3b01 subs r3, #1
8003c7a: 041b lsls r3, r3, #16
8003c7c: 431a orrs r2, r3
8003c7e: 687b ldr r3, [r7, #4]
8003c80: 6adb ldr r3, [r3, #44] ; 0x2c
8003c82: 061b lsls r3, r3, #24
8003c84: 431a orrs r2, r3
8003c86: 687b ldr r3, [r7, #4]
8003c88: 6b1b ldr r3, [r3, #48] ; 0x30
8003c8a: 071b lsls r3, r3, #28
8003c8c: 493b ldr r1, [pc, #236] ; (8003d7c <HAL_RCC_OscConfig+0x500>)
8003c8e: 4313 orrs r3, r2
8003c90: 604b str r3, [r1, #4]
(RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \
(((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \
(RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos) | \
(RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)));
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8003c92: 4b3b ldr r3, [pc, #236] ; (8003d80 <HAL_RCC_OscConfig+0x504>)
8003c94: 2201 movs r2, #1
8003c96: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003c98: f7fe f8e6 bl 8001e68 <HAL_GetTick>
8003c9c: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8003c9e: e008 b.n 8003cb2 <HAL_RCC_OscConfig+0x436>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8003ca0: f7fe f8e2 bl 8001e68 <HAL_GetTick>
8003ca4: 4602 mov r2, r0
8003ca6: 693b ldr r3, [r7, #16]
8003ca8: 1ad3 subs r3, r2, r3
8003caa: 2b02 cmp r3, #2
8003cac: d901 bls.n 8003cb2 <HAL_RCC_OscConfig+0x436>
{
return HAL_TIMEOUT;
8003cae: 2303 movs r3, #3
8003cb0: e05e b.n 8003d70 <HAL_RCC_OscConfig+0x4f4>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8003cb2: 4b32 ldr r3, [pc, #200] ; (8003d7c <HAL_RCC_OscConfig+0x500>)
8003cb4: 681b ldr r3, [r3, #0]
8003cb6: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8003cba: 2b00 cmp r3, #0
8003cbc: d0f0 beq.n 8003ca0 <HAL_RCC_OscConfig+0x424>
8003cbe: e056 b.n 8003d6e <HAL_RCC_OscConfig+0x4f2>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8003cc0: 4b2f ldr r3, [pc, #188] ; (8003d80 <HAL_RCC_OscConfig+0x504>)
8003cc2: 2200 movs r2, #0
8003cc4: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003cc6: f7fe f8cf bl 8001e68 <HAL_GetTick>
8003cca: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8003ccc: e008 b.n 8003ce0 <HAL_RCC_OscConfig+0x464>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8003cce: f7fe f8cb bl 8001e68 <HAL_GetTick>
8003cd2: 4602 mov r2, r0
8003cd4: 693b ldr r3, [r7, #16]
8003cd6: 1ad3 subs r3, r2, r3
8003cd8: 2b02 cmp r3, #2
8003cda: d901 bls.n 8003ce0 <HAL_RCC_OscConfig+0x464>
{
return HAL_TIMEOUT;
8003cdc: 2303 movs r3, #3
8003cde: e047 b.n 8003d70 <HAL_RCC_OscConfig+0x4f4>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8003ce0: 4b26 ldr r3, [pc, #152] ; (8003d7c <HAL_RCC_OscConfig+0x500>)
8003ce2: 681b ldr r3, [r3, #0]
8003ce4: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8003ce8: 2b00 cmp r3, #0
8003cea: d1f0 bne.n 8003cce <HAL_RCC_OscConfig+0x452>
8003cec: e03f b.n 8003d6e <HAL_RCC_OscConfig+0x4f2>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
8003cee: 687b ldr r3, [r7, #4]
8003cf0: 699b ldr r3, [r3, #24]
8003cf2: 2b01 cmp r3, #1
8003cf4: d101 bne.n 8003cfa <HAL_RCC_OscConfig+0x47e>
{
return HAL_ERROR;
8003cf6: 2301 movs r3, #1
8003cf8: e03a b.n 8003d70 <HAL_RCC_OscConfig+0x4f4>
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->PLLCFGR;
8003cfa: 4b20 ldr r3, [pc, #128] ; (8003d7c <HAL_RCC_OscConfig+0x500>)
8003cfc: 685b ldr r3, [r3, #4]
8003cfe: 60fb str r3, [r7, #12]
#if defined (RCC_PLLCFGR_PLLR)
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
8003d00: 687b ldr r3, [r7, #4]
8003d02: 699b ldr r3, [r3, #24]
8003d04: 2b01 cmp r3, #1
8003d06: d030 beq.n 8003d6a <HAL_RCC_OscConfig+0x4ee>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8003d08: 68fb ldr r3, [r7, #12]
8003d0a: f403 0280 and.w r2, r3, #4194304 ; 0x400000
8003d0e: 687b ldr r3, [r7, #4]
8003d10: 69db ldr r3, [r3, #28]
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
8003d12: 429a cmp r2, r3
8003d14: d129 bne.n 8003d6a <HAL_RCC_OscConfig+0x4ee>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
8003d16: 68fb ldr r3, [r7, #12]
8003d18: f003 023f and.w r2, r3, #63 ; 0x3f
8003d1c: 687b ldr r3, [r7, #4]
8003d1e: 6a1b ldr r3, [r3, #32]
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8003d20: 429a cmp r2, r3
8003d22: d122 bne.n 8003d6a <HAL_RCC_OscConfig+0x4ee>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
8003d24: 68fa ldr r2, [r7, #12]
8003d26: f647 73c0 movw r3, #32704 ; 0x7fc0
8003d2a: 4013 ands r3, r2
8003d2c: 687a ldr r2, [r7, #4]
8003d2e: 6a52 ldr r2, [r2, #36] ; 0x24
8003d30: 0192 lsls r2, r2, #6
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
8003d32: 4293 cmp r3, r2
8003d34: d119 bne.n 8003d6a <HAL_RCC_OscConfig+0x4ee>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
8003d36: 68fb ldr r3, [r7, #12]
8003d38: f403 3240 and.w r2, r3, #196608 ; 0x30000
8003d3c: 687b ldr r3, [r7, #4]
8003d3e: 6a9b ldr r3, [r3, #40] ; 0x28
8003d40: 085b lsrs r3, r3, #1
8003d42: 3b01 subs r3, #1
8003d44: 041b lsls r3, r3, #16
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
8003d46: 429a cmp r2, r3
8003d48: d10f bne.n 8003d6a <HAL_RCC_OscConfig+0x4ee>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
8003d4a: 68fb ldr r3, [r7, #12]
8003d4c: f003 6270 and.w r2, r3, #251658240 ; 0xf000000
8003d50: 687b ldr r3, [r7, #4]
8003d52: 6adb ldr r3, [r3, #44] ; 0x2c
8003d54: 061b lsls r3, r3, #24
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
8003d56: 429a cmp r2, r3
8003d58: d107 bne.n 8003d6a <HAL_RCC_OscConfig+0x4ee>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
8003d5a: 68fb ldr r3, [r7, #12]
8003d5c: f003 42e0 and.w r2, r3, #1879048192 ; 0x70000000
8003d60: 687b ldr r3, [r7, #4]
8003d62: 6b1b ldr r3, [r3, #48] ; 0x30
8003d64: 071b lsls r3, r3, #28
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
8003d66: 429a cmp r2, r3
8003d68: d001 beq.n 8003d6e <HAL_RCC_OscConfig+0x4f2>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
#endif
{
return HAL_ERROR;
8003d6a: 2301 movs r3, #1
8003d6c: e000 b.n 8003d70 <HAL_RCC_OscConfig+0x4f4>
}
}
}
}
return HAL_OK;
8003d6e: 2300 movs r3, #0
}
8003d70: 4618 mov r0, r3
8003d72: 3718 adds r7, #24
8003d74: 46bd mov sp, r7
8003d76: bd80 pop {r7, pc}
8003d78: 40007000 .word 0x40007000
8003d7c: 40023800 .word 0x40023800
8003d80: 42470060 .word 0x42470060
08003d84 <HAL_UART_Init>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
8003d84: b580 push {r7, lr}
8003d86: b082 sub sp, #8
8003d88: af00 add r7, sp, #0
8003d8a: 6078 str r0, [r7, #4]
/* Check the UART handle allocation */
if (huart == NULL)
8003d8c: 687b ldr r3, [r7, #4]
8003d8e: 2b00 cmp r3, #0
8003d90: d101 bne.n 8003d96 <HAL_UART_Init+0x12>
{
return HAL_ERROR;
8003d92: 2301 movs r3, #1
8003d94: e03f b.n 8003e16 <HAL_UART_Init+0x92>
assert_param(IS_UART_INSTANCE(huart->Instance));
}
assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
if (huart->gState == HAL_UART_STATE_RESET)
8003d96: 687b ldr r3, [r7, #4]
8003d98: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
8003d9c: b2db uxtb r3, r3
8003d9e: 2b00 cmp r3, #0
8003da0: d106 bne.n 8003db0 <HAL_UART_Init+0x2c>
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
8003da2: 687b ldr r3, [r7, #4]
8003da4: 2200 movs r2, #0
8003da6: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Init the low level hardware */
huart->MspInitCallback(huart);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
8003daa: 6878 ldr r0, [r7, #4]
8003dac: f7fd fdfc bl 80019a8 <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
8003db0: 687b ldr r3, [r7, #4]
8003db2: 2224 movs r2, #36 ; 0x24
8003db4: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Disable the peripheral */
__HAL_UART_DISABLE(huart);
8003db8: 687b ldr r3, [r7, #4]
8003dba: 681b ldr r3, [r3, #0]
8003dbc: 68da ldr r2, [r3, #12]
8003dbe: 687b ldr r3, [r7, #4]
8003dc0: 681b ldr r3, [r3, #0]
8003dc2: f422 5200 bic.w r2, r2, #8192 ; 0x2000
8003dc6: 60da str r2, [r3, #12]
/* Set the UART Communication parameters */
UART_SetConfig(huart);
8003dc8: 6878 ldr r0, [r7, #4]
8003dca: f000 fe7d bl 8004ac8 <UART_SetConfig>
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
8003dce: 687b ldr r3, [r7, #4]
8003dd0: 681b ldr r3, [r3, #0]
8003dd2: 691a ldr r2, [r3, #16]
8003dd4: 687b ldr r3, [r7, #4]
8003dd6: 681b ldr r3, [r3, #0]
8003dd8: f422 4290 bic.w r2, r2, #18432 ; 0x4800
8003ddc: 611a str r2, [r3, #16]
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
8003dde: 687b ldr r3, [r7, #4]
8003de0: 681b ldr r3, [r3, #0]
8003de2: 695a ldr r2, [r3, #20]
8003de4: 687b ldr r3, [r7, #4]
8003de6: 681b ldr r3, [r3, #0]
8003de8: f022 022a bic.w r2, r2, #42 ; 0x2a
8003dec: 615a str r2, [r3, #20]
/* Enable the peripheral */
__HAL_UART_ENABLE(huart);
8003dee: 687b ldr r3, [r7, #4]
8003df0: 681b ldr r3, [r3, #0]
8003df2: 68da ldr r2, [r3, #12]
8003df4: 687b ldr r3, [r7, #4]
8003df6: 681b ldr r3, [r3, #0]
8003df8: f442 5200 orr.w r2, r2, #8192 ; 0x2000
8003dfc: 60da str r2, [r3, #12]
/* Initialize the UART state */
huart->ErrorCode = HAL_UART_ERROR_NONE;
8003dfe: 687b ldr r3, [r7, #4]
8003e00: 2200 movs r2, #0
8003e02: 641a str r2, [r3, #64] ; 0x40
huart->gState = HAL_UART_STATE_READY;
8003e04: 687b ldr r3, [r7, #4]
8003e06: 2220 movs r2, #32
8003e08: f883 203d strb.w r2, [r3, #61] ; 0x3d
huart->RxState = HAL_UART_STATE_READY;
8003e0c: 687b ldr r3, [r7, #4]
8003e0e: 2220 movs r2, #32
8003e10: f883 203e strb.w r2, [r3, #62] ; 0x3e
return HAL_OK;
8003e14: 2300 movs r3, #0
}
8003e16: 4618 mov r0, r3
8003e18: 3708 adds r7, #8
8003e1a: 46bd mov sp, r7
8003e1c: bd80 pop {r7, pc}
08003e1e <HAL_UART_Transmit>:
* @param Size Amount of data elements (u8 or u16) to be sent
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
8003e1e: b580 push {r7, lr}
8003e20: b08a sub sp, #40 ; 0x28
8003e22: af02 add r7, sp, #8
8003e24: 60f8 str r0, [r7, #12]
8003e26: 60b9 str r1, [r7, #8]
8003e28: 603b str r3, [r7, #0]
8003e2a: 4613 mov r3, r2
8003e2c: 80fb strh r3, [r7, #6]
uint8_t *pdata8bits;
uint16_t *pdata16bits;
uint32_t tickstart = 0U;
8003e2e: 2300 movs r3, #0
8003e30: 617b str r3, [r7, #20]
/* Check that a Tx process is not already ongoing */
if (huart->gState == HAL_UART_STATE_READY)
8003e32: 68fb ldr r3, [r7, #12]
8003e34: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
8003e38: b2db uxtb r3, r3
8003e3a: 2b20 cmp r3, #32
8003e3c: d17c bne.n 8003f38 <HAL_UART_Transmit+0x11a>
{
if ((pData == NULL) || (Size == 0U))
8003e3e: 68bb ldr r3, [r7, #8]
8003e40: 2b00 cmp r3, #0
8003e42: d002 beq.n 8003e4a <HAL_UART_Transmit+0x2c>
8003e44: 88fb ldrh r3, [r7, #6]
8003e46: 2b00 cmp r3, #0
8003e48: d101 bne.n 8003e4e <HAL_UART_Transmit+0x30>
{
return HAL_ERROR;
8003e4a: 2301 movs r3, #1
8003e4c: e075 b.n 8003f3a <HAL_UART_Transmit+0x11c>
}
/* Process Locked */
__HAL_LOCK(huart);
8003e4e: 68fb ldr r3, [r7, #12]
8003e50: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
8003e54: 2b01 cmp r3, #1
8003e56: d101 bne.n 8003e5c <HAL_UART_Transmit+0x3e>
8003e58: 2302 movs r3, #2
8003e5a: e06e b.n 8003f3a <HAL_UART_Transmit+0x11c>
8003e5c: 68fb ldr r3, [r7, #12]
8003e5e: 2201 movs r2, #1
8003e60: f883 203c strb.w r2, [r3, #60] ; 0x3c
huart->ErrorCode = HAL_UART_ERROR_NONE;
8003e64: 68fb ldr r3, [r7, #12]
8003e66: 2200 movs r2, #0
8003e68: 641a str r2, [r3, #64] ; 0x40
huart->gState = HAL_UART_STATE_BUSY_TX;
8003e6a: 68fb ldr r3, [r7, #12]
8003e6c: 2221 movs r2, #33 ; 0x21
8003e6e: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
8003e72: f7fd fff9 bl 8001e68 <HAL_GetTick>
8003e76: 6178 str r0, [r7, #20]
huart->TxXferSize = Size;
8003e78: 68fb ldr r3, [r7, #12]
8003e7a: 88fa ldrh r2, [r7, #6]
8003e7c: 849a strh r2, [r3, #36] ; 0x24
huart->TxXferCount = Size;
8003e7e: 68fb ldr r3, [r7, #12]
8003e80: 88fa ldrh r2, [r7, #6]
8003e82: 84da strh r2, [r3, #38] ; 0x26
/* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
8003e84: 68fb ldr r3, [r7, #12]
8003e86: 689b ldr r3, [r3, #8]
8003e88: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
8003e8c: d108 bne.n 8003ea0 <HAL_UART_Transmit+0x82>
8003e8e: 68fb ldr r3, [r7, #12]
8003e90: 691b ldr r3, [r3, #16]
8003e92: 2b00 cmp r3, #0
8003e94: d104 bne.n 8003ea0 <HAL_UART_Transmit+0x82>
{
pdata8bits = NULL;
8003e96: 2300 movs r3, #0
8003e98: 61fb str r3, [r7, #28]
pdata16bits = (uint16_t *) pData;
8003e9a: 68bb ldr r3, [r7, #8]
8003e9c: 61bb str r3, [r7, #24]
8003e9e: e003 b.n 8003ea8 <HAL_UART_Transmit+0x8a>
}
else
{
pdata8bits = pData;
8003ea0: 68bb ldr r3, [r7, #8]
8003ea2: 61fb str r3, [r7, #28]
pdata16bits = NULL;
8003ea4: 2300 movs r3, #0
8003ea6: 61bb str r3, [r7, #24]
}
/* Process Unlocked */
__HAL_UNLOCK(huart);
8003ea8: 68fb ldr r3, [r7, #12]
8003eaa: 2200 movs r2, #0
8003eac: f883 203c strb.w r2, [r3, #60] ; 0x3c
while (huart->TxXferCount > 0U)
8003eb0: e02a b.n 8003f08 <HAL_UART_Transmit+0xea>
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
8003eb2: 683b ldr r3, [r7, #0]
8003eb4: 9300 str r3, [sp, #0]
8003eb6: 697b ldr r3, [r7, #20]
8003eb8: 2200 movs r2, #0
8003eba: 2180 movs r1, #128 ; 0x80
8003ebc: 68f8 ldr r0, [r7, #12]
8003ebe: f000 fbc1 bl 8004644 <UART_WaitOnFlagUntilTimeout>
8003ec2: 4603 mov r3, r0
8003ec4: 2b00 cmp r3, #0
8003ec6: d001 beq.n 8003ecc <HAL_UART_Transmit+0xae>
{
return HAL_TIMEOUT;
8003ec8: 2303 movs r3, #3
8003eca: e036 b.n 8003f3a <HAL_UART_Transmit+0x11c>
}
if (pdata8bits == NULL)
8003ecc: 69fb ldr r3, [r7, #28]
8003ece: 2b00 cmp r3, #0
8003ed0: d10b bne.n 8003eea <HAL_UART_Transmit+0xcc>
{
huart->Instance->DR = (uint16_t)(*pdata16bits & 0x01FFU);
8003ed2: 69bb ldr r3, [r7, #24]
8003ed4: 881b ldrh r3, [r3, #0]
8003ed6: 461a mov r2, r3
8003ed8: 68fb ldr r3, [r7, #12]
8003eda: 681b ldr r3, [r3, #0]
8003edc: f3c2 0208 ubfx r2, r2, #0, #9
8003ee0: 605a str r2, [r3, #4]
pdata16bits++;
8003ee2: 69bb ldr r3, [r7, #24]
8003ee4: 3302 adds r3, #2
8003ee6: 61bb str r3, [r7, #24]
8003ee8: e007 b.n 8003efa <HAL_UART_Transmit+0xdc>
}
else
{
huart->Instance->DR = (uint8_t)(*pdata8bits & 0xFFU);
8003eea: 69fb ldr r3, [r7, #28]
8003eec: 781a ldrb r2, [r3, #0]
8003eee: 68fb ldr r3, [r7, #12]
8003ef0: 681b ldr r3, [r3, #0]
8003ef2: 605a str r2, [r3, #4]
pdata8bits++;
8003ef4: 69fb ldr r3, [r7, #28]
8003ef6: 3301 adds r3, #1
8003ef8: 61fb str r3, [r7, #28]
}
huart->TxXferCount--;
8003efa: 68fb ldr r3, [r7, #12]
8003efc: 8cdb ldrh r3, [r3, #38] ; 0x26
8003efe: b29b uxth r3, r3
8003f00: 3b01 subs r3, #1
8003f02: b29a uxth r2, r3
8003f04: 68fb ldr r3, [r7, #12]
8003f06: 84da strh r2, [r3, #38] ; 0x26
while (huart->TxXferCount > 0U)
8003f08: 68fb ldr r3, [r7, #12]
8003f0a: 8cdb ldrh r3, [r3, #38] ; 0x26
8003f0c: b29b uxth r3, r3
8003f0e: 2b00 cmp r3, #0
8003f10: d1cf bne.n 8003eb2 <HAL_UART_Transmit+0x94>
}
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
8003f12: 683b ldr r3, [r7, #0]
8003f14: 9300 str r3, [sp, #0]
8003f16: 697b ldr r3, [r7, #20]
8003f18: 2200 movs r2, #0
8003f1a: 2140 movs r1, #64 ; 0x40
8003f1c: 68f8 ldr r0, [r7, #12]
8003f1e: f000 fb91 bl 8004644 <UART_WaitOnFlagUntilTimeout>
8003f22: 4603 mov r3, r0
8003f24: 2b00 cmp r3, #0
8003f26: d001 beq.n 8003f2c <HAL_UART_Transmit+0x10e>
{
return HAL_TIMEOUT;
8003f28: 2303 movs r3, #3
8003f2a: e006 b.n 8003f3a <HAL_UART_Transmit+0x11c>
}
/* At end of Tx process, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
8003f2c: 68fb ldr r3, [r7, #12]
8003f2e: 2220 movs r2, #32
8003f30: f883 203d strb.w r2, [r3, #61] ; 0x3d
return HAL_OK;
8003f34: 2300 movs r3, #0
8003f36: e000 b.n 8003f3a <HAL_UART_Transmit+0x11c>
}
else
{
return HAL_BUSY;
8003f38: 2302 movs r3, #2
}
}
8003f3a: 4618 mov r0, r3
8003f3c: 3720 adds r7, #32
8003f3e: 46bd mov sp, r7
8003f40: bd80 pop {r7, pc}
08003f42 <HAL_UART_Receive>:
* @param Size Amount of data elements (u8 or u16) to be received.
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
8003f42: b580 push {r7, lr}
8003f44: b08a sub sp, #40 ; 0x28
8003f46: af02 add r7, sp, #8
8003f48: 60f8 str r0, [r7, #12]
8003f4a: 60b9 str r1, [r7, #8]
8003f4c: 603b str r3, [r7, #0]
8003f4e: 4613 mov r3, r2
8003f50: 80fb strh r3, [r7, #6]
uint8_t *pdata8bits;
uint16_t *pdata16bits;
uint32_t tickstart = 0U;
8003f52: 2300 movs r3, #0
8003f54: 617b str r3, [r7, #20]
/* Check that a Rx process is not already ongoing */
if (huart->RxState == HAL_UART_STATE_READY)
8003f56: 68fb ldr r3, [r7, #12]
8003f58: f893 303e ldrb.w r3, [r3, #62] ; 0x3e
8003f5c: b2db uxtb r3, r3
8003f5e: 2b20 cmp r3, #32
8003f60: f040 808c bne.w 800407c <HAL_UART_Receive+0x13a>
{
if ((pData == NULL) || (Size == 0U))
8003f64: 68bb ldr r3, [r7, #8]
8003f66: 2b00 cmp r3, #0
8003f68: d002 beq.n 8003f70 <HAL_UART_Receive+0x2e>
8003f6a: 88fb ldrh r3, [r7, #6]
8003f6c: 2b00 cmp r3, #0
8003f6e: d101 bne.n 8003f74 <HAL_UART_Receive+0x32>
{
return HAL_ERROR;
8003f70: 2301 movs r3, #1
8003f72: e084 b.n 800407e <HAL_UART_Receive+0x13c>
}
/* Process Locked */
__HAL_LOCK(huart);
8003f74: 68fb ldr r3, [r7, #12]
8003f76: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
8003f7a: 2b01 cmp r3, #1
8003f7c: d101 bne.n 8003f82 <HAL_UART_Receive+0x40>
8003f7e: 2302 movs r3, #2
8003f80: e07d b.n 800407e <HAL_UART_Receive+0x13c>
8003f82: 68fb ldr r3, [r7, #12]
8003f84: 2201 movs r2, #1
8003f86: f883 203c strb.w r2, [r3, #60] ; 0x3c
huart->ErrorCode = HAL_UART_ERROR_NONE;
8003f8a: 68fb ldr r3, [r7, #12]
8003f8c: 2200 movs r2, #0
8003f8e: 641a str r2, [r3, #64] ; 0x40
huart->RxState = HAL_UART_STATE_BUSY_RX;
8003f90: 68fb ldr r3, [r7, #12]
8003f92: 2222 movs r2, #34 ; 0x22
8003f94: f883 203e strb.w r2, [r3, #62] ; 0x3e
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8003f98: 68fb ldr r3, [r7, #12]
8003f9a: 2200 movs r2, #0
8003f9c: 631a str r2, [r3, #48] ; 0x30
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
8003f9e: f7fd ff63 bl 8001e68 <HAL_GetTick>
8003fa2: 6178 str r0, [r7, #20]
huart->RxXferSize = Size;
8003fa4: 68fb ldr r3, [r7, #12]
8003fa6: 88fa ldrh r2, [r7, #6]
8003fa8: 859a strh r2, [r3, #44] ; 0x2c
huart->RxXferCount = Size;
8003faa: 68fb ldr r3, [r7, #12]
8003fac: 88fa ldrh r2, [r7, #6]
8003fae: 85da strh r2, [r3, #46] ; 0x2e
/* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
8003fb0: 68fb ldr r3, [r7, #12]
8003fb2: 689b ldr r3, [r3, #8]
8003fb4: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
8003fb8: d108 bne.n 8003fcc <HAL_UART_Receive+0x8a>
8003fba: 68fb ldr r3, [r7, #12]
8003fbc: 691b ldr r3, [r3, #16]
8003fbe: 2b00 cmp r3, #0
8003fc0: d104 bne.n 8003fcc <HAL_UART_Receive+0x8a>
{
pdata8bits = NULL;
8003fc2: 2300 movs r3, #0
8003fc4: 61fb str r3, [r7, #28]
pdata16bits = (uint16_t *) pData;
8003fc6: 68bb ldr r3, [r7, #8]
8003fc8: 61bb str r3, [r7, #24]
8003fca: e003 b.n 8003fd4 <HAL_UART_Receive+0x92>
}
else
{
pdata8bits = pData;
8003fcc: 68bb ldr r3, [r7, #8]
8003fce: 61fb str r3, [r7, #28]
pdata16bits = NULL;
8003fd0: 2300 movs r3, #0
8003fd2: 61bb str r3, [r7, #24]
}
/* Process Unlocked */
__HAL_UNLOCK(huart);
8003fd4: 68fb ldr r3, [r7, #12]
8003fd6: 2200 movs r2, #0
8003fd8: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Check the remain data to be received */
while (huart->RxXferCount > 0U)
8003fdc: e043 b.n 8004066 <HAL_UART_Receive+0x124>
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
8003fde: 683b ldr r3, [r7, #0]
8003fe0: 9300 str r3, [sp, #0]
8003fe2: 697b ldr r3, [r7, #20]
8003fe4: 2200 movs r2, #0
8003fe6: 2120 movs r1, #32
8003fe8: 68f8 ldr r0, [r7, #12]
8003fea: f000 fb2b bl 8004644 <UART_WaitOnFlagUntilTimeout>
8003fee: 4603 mov r3, r0
8003ff0: 2b00 cmp r3, #0
8003ff2: d001 beq.n 8003ff8 <HAL_UART_Receive+0xb6>
{
return HAL_TIMEOUT;
8003ff4: 2303 movs r3, #3
8003ff6: e042 b.n 800407e <HAL_UART_Receive+0x13c>
}
if (pdata8bits == NULL)
8003ff8: 69fb ldr r3, [r7, #28]
8003ffa: 2b00 cmp r3, #0
8003ffc: d10c bne.n 8004018 <HAL_UART_Receive+0xd6>
{
*pdata16bits = (uint16_t)(huart->Instance->DR & 0x01FF);
8003ffe: 68fb ldr r3, [r7, #12]
8004000: 681b ldr r3, [r3, #0]
8004002: 685b ldr r3, [r3, #4]
8004004: b29b uxth r3, r3
8004006: f3c3 0308 ubfx r3, r3, #0, #9
800400a: b29a uxth r2, r3
800400c: 69bb ldr r3, [r7, #24]
800400e: 801a strh r2, [r3, #0]
pdata16bits++;
8004010: 69bb ldr r3, [r7, #24]
8004012: 3302 adds r3, #2
8004014: 61bb str r3, [r7, #24]
8004016: e01f b.n 8004058 <HAL_UART_Receive+0x116>
}
else
{
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE)))
8004018: 68fb ldr r3, [r7, #12]
800401a: 689b ldr r3, [r3, #8]
800401c: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
8004020: d007 beq.n 8004032 <HAL_UART_Receive+0xf0>
8004022: 68fb ldr r3, [r7, #12]
8004024: 689b ldr r3, [r3, #8]
8004026: 2b00 cmp r3, #0
8004028: d10a bne.n 8004040 <HAL_UART_Receive+0xfe>
800402a: 68fb ldr r3, [r7, #12]
800402c: 691b ldr r3, [r3, #16]
800402e: 2b00 cmp r3, #0
8004030: d106 bne.n 8004040 <HAL_UART_Receive+0xfe>
{
*pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
8004032: 68fb ldr r3, [r7, #12]
8004034: 681b ldr r3, [r3, #0]
8004036: 685b ldr r3, [r3, #4]
8004038: b2da uxtb r2, r3
800403a: 69fb ldr r3, [r7, #28]
800403c: 701a strb r2, [r3, #0]
800403e: e008 b.n 8004052 <HAL_UART_Receive+0x110>
}
else
{
*pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
8004040: 68fb ldr r3, [r7, #12]
8004042: 681b ldr r3, [r3, #0]
8004044: 685b ldr r3, [r3, #4]
8004046: b2db uxtb r3, r3
8004048: f003 037f and.w r3, r3, #127 ; 0x7f
800404c: b2da uxtb r2, r3
800404e: 69fb ldr r3, [r7, #28]
8004050: 701a strb r2, [r3, #0]
}
pdata8bits++;
8004052: 69fb ldr r3, [r7, #28]
8004054: 3301 adds r3, #1
8004056: 61fb str r3, [r7, #28]
}
huart->RxXferCount--;
8004058: 68fb ldr r3, [r7, #12]
800405a: 8ddb ldrh r3, [r3, #46] ; 0x2e
800405c: b29b uxth r3, r3
800405e: 3b01 subs r3, #1
8004060: b29a uxth r2, r3
8004062: 68fb ldr r3, [r7, #12]
8004064: 85da strh r2, [r3, #46] ; 0x2e
while (huart->RxXferCount > 0U)
8004066: 68fb ldr r3, [r7, #12]
8004068: 8ddb ldrh r3, [r3, #46] ; 0x2e
800406a: b29b uxth r3, r3
800406c: 2b00 cmp r3, #0
800406e: d1b6 bne.n 8003fde <HAL_UART_Receive+0x9c>
}
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8004070: 68fb ldr r3, [r7, #12]
8004072: 2220 movs r2, #32
8004074: f883 203e strb.w r2, [r3, #62] ; 0x3e
return HAL_OK;
8004078: 2300 movs r3, #0
800407a: e000 b.n 800407e <HAL_UART_Receive+0x13c>
}
else
{
return HAL_BUSY;
800407c: 2302 movs r3, #2
}
}
800407e: 4618 mov r0, r3
8004080: 3720 adds r7, #32
8004082: 46bd mov sp, r7
8004084: bd80 pop {r7, pc}
08004086 <HAL_UART_Receive_IT>:
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
8004086: b580 push {r7, lr}
8004088: b084 sub sp, #16
800408a: af00 add r7, sp, #0
800408c: 60f8 str r0, [r7, #12]
800408e: 60b9 str r1, [r7, #8]
8004090: 4613 mov r3, r2
8004092: 80fb strh r3, [r7, #6]
/* Check that a Rx process is not already ongoing */
if (huart->RxState == HAL_UART_STATE_READY)
8004094: 68fb ldr r3, [r7, #12]
8004096: f893 303e ldrb.w r3, [r3, #62] ; 0x3e
800409a: b2db uxtb r3, r3
800409c: 2b20 cmp r3, #32
800409e: d11d bne.n 80040dc <HAL_UART_Receive_IT+0x56>
{
if ((pData == NULL) || (Size == 0U))
80040a0: 68bb ldr r3, [r7, #8]
80040a2: 2b00 cmp r3, #0
80040a4: d002 beq.n 80040ac <HAL_UART_Receive_IT+0x26>
80040a6: 88fb ldrh r3, [r7, #6]
80040a8: 2b00 cmp r3, #0
80040aa: d101 bne.n 80040b0 <HAL_UART_Receive_IT+0x2a>
{
return HAL_ERROR;
80040ac: 2301 movs r3, #1
80040ae: e016 b.n 80040de <HAL_UART_Receive_IT+0x58>
}
/* Process Locked */
__HAL_LOCK(huart);
80040b0: 68fb ldr r3, [r7, #12]
80040b2: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
80040b6: 2b01 cmp r3, #1
80040b8: d101 bne.n 80040be <HAL_UART_Receive_IT+0x38>
80040ba: 2302 movs r3, #2
80040bc: e00f b.n 80040de <HAL_UART_Receive_IT+0x58>
80040be: 68fb ldr r3, [r7, #12]
80040c0: 2201 movs r2, #1
80040c2: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Set Reception type to Standard reception */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
80040c6: 68fb ldr r3, [r7, #12]
80040c8: 2200 movs r2, #0
80040ca: 631a str r2, [r3, #48] ; 0x30
return (UART_Start_Receive_IT(huart, pData, Size));
80040cc: 88fb ldrh r3, [r7, #6]
80040ce: 461a mov r2, r3
80040d0: 68b9 ldr r1, [r7, #8]
80040d2: 68f8 ldr r0, [r7, #12]
80040d4: f000 fb24 bl 8004720 <UART_Start_Receive_IT>
80040d8: 4603 mov r3, r0
80040da: e000 b.n 80040de <HAL_UART_Receive_IT+0x58>
}
else
{
return HAL_BUSY;
80040dc: 2302 movs r3, #2
}
}
80040de: 4618 mov r0, r3
80040e0: 3710 adds r7, #16
80040e2: 46bd mov sp, r7
80040e4: bd80 pop {r7, pc}
...
080040e8 <HAL_UART_IRQHandler>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
{
80040e8: b580 push {r7, lr}
80040ea: b0ba sub sp, #232 ; 0xe8
80040ec: af00 add r7, sp, #0
80040ee: 6078 str r0, [r7, #4]
uint32_t isrflags = READ_REG(huart->Instance->SR);
80040f0: 687b ldr r3, [r7, #4]
80040f2: 681b ldr r3, [r3, #0]
80040f4: 681b ldr r3, [r3, #0]
80040f6: f8c7 30e4 str.w r3, [r7, #228] ; 0xe4
uint32_t cr1its = READ_REG(huart->Instance->CR1);
80040fa: 687b ldr r3, [r7, #4]
80040fc: 681b ldr r3, [r3, #0]
80040fe: 68db ldr r3, [r3, #12]
8004100: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0
uint32_t cr3its = READ_REG(huart->Instance->CR3);
8004104: 687b ldr r3, [r7, #4]
8004106: 681b ldr r3, [r3, #0]
8004108: 695b ldr r3, [r3, #20]
800410a: f8c7 30dc str.w r3, [r7, #220] ; 0xdc
uint32_t errorflags = 0x00U;
800410e: 2300 movs r3, #0
8004110: f8c7 30d8 str.w r3, [r7, #216] ; 0xd8
uint32_t dmarequest = 0x00U;
8004114: 2300 movs r3, #0
8004116: f8c7 30d4 str.w r3, [r7, #212] ; 0xd4
/* If no error occurs */
errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
800411a: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4
800411e: f003 030f and.w r3, r3, #15
8004122: f8c7 30d8 str.w r3, [r7, #216] ; 0xd8
if (errorflags == RESET)
8004126: f8d7 30d8 ldr.w r3, [r7, #216] ; 0xd8
800412a: 2b00 cmp r3, #0
800412c: d10f bne.n 800414e <HAL_UART_IRQHandler+0x66>
{
/* UART in mode Receiver -------------------------------------------------*/
if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
800412e: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4
8004132: f003 0320 and.w r3, r3, #32
8004136: 2b00 cmp r3, #0
8004138: d009 beq.n 800414e <HAL_UART_IRQHandler+0x66>
800413a: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0
800413e: f003 0320 and.w r3, r3, #32
8004142: 2b00 cmp r3, #0
8004144: d003 beq.n 800414e <HAL_UART_IRQHandler+0x66>
{
UART_Receive_IT(huart);
8004146: 6878 ldr r0, [r7, #4]
8004148: f000 fc03 bl 8004952 <UART_Receive_IT>
return;
800414c: e256 b.n 80045fc <HAL_UART_IRQHandler+0x514>
}
}
/* If some errors occur */
if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET)
800414e: f8d7 30d8 ldr.w r3, [r7, #216] ; 0xd8
8004152: 2b00 cmp r3, #0
8004154: f000 80de beq.w 8004314 <HAL_UART_IRQHandler+0x22c>
8004158: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc
800415c: f003 0301 and.w r3, r3, #1
8004160: 2b00 cmp r3, #0
8004162: d106 bne.n 8004172 <HAL_UART_IRQHandler+0x8a>
|| ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
8004164: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0
8004168: f403 7390 and.w r3, r3, #288 ; 0x120
800416c: 2b00 cmp r3, #0
800416e: f000 80d1 beq.w 8004314 <HAL_UART_IRQHandler+0x22c>
{
/* UART parity error interrupt occurred ----------------------------------*/
if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
8004172: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4
8004176: f003 0301 and.w r3, r3, #1
800417a: 2b00 cmp r3, #0
800417c: d00b beq.n 8004196 <HAL_UART_IRQHandler+0xae>
800417e: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0
8004182: f403 7380 and.w r3, r3, #256 ; 0x100
8004186: 2b00 cmp r3, #0
8004188: d005 beq.n 8004196 <HAL_UART_IRQHandler+0xae>
{
huart->ErrorCode |= HAL_UART_ERROR_PE;
800418a: 687b ldr r3, [r7, #4]
800418c: 6c1b ldr r3, [r3, #64] ; 0x40
800418e: f043 0201 orr.w r2, r3, #1
8004192: 687b ldr r3, [r7, #4]
8004194: 641a str r2, [r3, #64] ; 0x40
}
/* UART noise error interrupt occurred -----------------------------------*/
if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
8004196: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4
800419a: f003 0304 and.w r3, r3, #4
800419e: 2b00 cmp r3, #0
80041a0: d00b beq.n 80041ba <HAL_UART_IRQHandler+0xd2>
80041a2: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc
80041a6: f003 0301 and.w r3, r3, #1
80041aa: 2b00 cmp r3, #0
80041ac: d005 beq.n 80041ba <HAL_UART_IRQHandler+0xd2>
{
huart->ErrorCode |= HAL_UART_ERROR_NE;
80041ae: 687b ldr r3, [r7, #4]
80041b0: 6c1b ldr r3, [r3, #64] ; 0x40
80041b2: f043 0202 orr.w r2, r3, #2
80041b6: 687b ldr r3, [r7, #4]
80041b8: 641a str r2, [r3, #64] ; 0x40
}
/* UART frame error interrupt occurred -----------------------------------*/
if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
80041ba: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4
80041be: f003 0302 and.w r3, r3, #2
80041c2: 2b00 cmp r3, #0
80041c4: d00b beq.n 80041de <HAL_UART_IRQHandler+0xf6>
80041c6: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc
80041ca: f003 0301 and.w r3, r3, #1
80041ce: 2b00 cmp r3, #0
80041d0: d005 beq.n 80041de <HAL_UART_IRQHandler+0xf6>
{
huart->ErrorCode |= HAL_UART_ERROR_FE;
80041d2: 687b ldr r3, [r7, #4]
80041d4: 6c1b ldr r3, [r3, #64] ; 0x40
80041d6: f043 0204 orr.w r2, r3, #4
80041da: 687b ldr r3, [r7, #4]
80041dc: 641a str r2, [r3, #64] ; 0x40
}
/* UART Over-Run interrupt occurred --------------------------------------*/
if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET)
80041de: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4
80041e2: f003 0308 and.w r3, r3, #8
80041e6: 2b00 cmp r3, #0
80041e8: d011 beq.n 800420e <HAL_UART_IRQHandler+0x126>
80041ea: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0
80041ee: f003 0320 and.w r3, r3, #32
80041f2: 2b00 cmp r3, #0
80041f4: d105 bne.n 8004202 <HAL_UART_IRQHandler+0x11a>
|| ((cr3its & USART_CR3_EIE) != RESET)))
80041f6: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc
80041fa: f003 0301 and.w r3, r3, #1
80041fe: 2b00 cmp r3, #0
8004200: d005 beq.n 800420e <HAL_UART_IRQHandler+0x126>
{
huart->ErrorCode |= HAL_UART_ERROR_ORE;
8004202: 687b ldr r3, [r7, #4]
8004204: 6c1b ldr r3, [r3, #64] ; 0x40
8004206: f043 0208 orr.w r2, r3, #8
800420a: 687b ldr r3, [r7, #4]
800420c: 641a str r2, [r3, #64] ; 0x40
}
/* Call UART Error Call back function if need be --------------------------*/
if (huart->ErrorCode != HAL_UART_ERROR_NONE)
800420e: 687b ldr r3, [r7, #4]
8004210: 6c1b ldr r3, [r3, #64] ; 0x40
8004212: 2b00 cmp r3, #0
8004214: f000 81ed beq.w 80045f2 <HAL_UART_IRQHandler+0x50a>
{
/* UART in mode Receiver -----------------------------------------------*/
if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
8004218: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4
800421c: f003 0320 and.w r3, r3, #32
8004220: 2b00 cmp r3, #0
8004222: d008 beq.n 8004236 <HAL_UART_IRQHandler+0x14e>
8004224: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0
8004228: f003 0320 and.w r3, r3, #32
800422c: 2b00 cmp r3, #0
800422e: d002 beq.n 8004236 <HAL_UART_IRQHandler+0x14e>
{
UART_Receive_IT(huart);
8004230: 6878 ldr r0, [r7, #4]
8004232: f000 fb8e bl 8004952 <UART_Receive_IT>
}
/* If Overrun error occurs, or if any error occurs in DMA mode reception,
consider error as blocking */
dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
8004236: 687b ldr r3, [r7, #4]
8004238: 681b ldr r3, [r3, #0]
800423a: 695b ldr r3, [r3, #20]
800423c: f003 0340 and.w r3, r3, #64 ; 0x40
8004240: 2b40 cmp r3, #64 ; 0x40
8004242: bf0c ite eq
8004244: 2301 moveq r3, #1
8004246: 2300 movne r3, #0
8004248: b2db uxtb r3, r3
800424a: f8c7 30d4 str.w r3, [r7, #212] ; 0xd4
if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest)
800424e: 687b ldr r3, [r7, #4]
8004250: 6c1b ldr r3, [r3, #64] ; 0x40
8004252: f003 0308 and.w r3, r3, #8
8004256: 2b00 cmp r3, #0
8004258: d103 bne.n 8004262 <HAL_UART_IRQHandler+0x17a>
800425a: f8d7 30d4 ldr.w r3, [r7, #212] ; 0xd4
800425e: 2b00 cmp r3, #0
8004260: d04f beq.n 8004302 <HAL_UART_IRQHandler+0x21a>
{
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
UART_EndRxTransfer(huart);
8004262: 6878 ldr r0, [r7, #4]
8004264: f000 fa96 bl 8004794 <UART_EndRxTransfer>
/* Disable the UART DMA Rx request if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
8004268: 687b ldr r3, [r7, #4]
800426a: 681b ldr r3, [r3, #0]
800426c: 695b ldr r3, [r3, #20]
800426e: f003 0340 and.w r3, r3, #64 ; 0x40
8004272: 2b40 cmp r3, #64 ; 0x40
8004274: d141 bne.n 80042fa <HAL_UART_IRQHandler+0x212>
{
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
8004276: 687b ldr r3, [r7, #4]
8004278: 681b ldr r3, [r3, #0]
800427a: 3314 adds r3, #20
800427c: f8c7 309c str.w r3, [r7, #156] ; 0x9c
*/
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004280: f8d7 309c ldr.w r3, [r7, #156] ; 0x9c
8004284: e853 3f00 ldrex r3, [r3]
8004288: f8c7 3098 str.w r3, [r7, #152] ; 0x98
return(result);
800428c: f8d7 3098 ldr.w r3, [r7, #152] ; 0x98
8004290: f023 0340 bic.w r3, r3, #64 ; 0x40
8004294: f8c7 30d0 str.w r3, [r7, #208] ; 0xd0
8004298: 687b ldr r3, [r7, #4]
800429a: 681b ldr r3, [r3, #0]
800429c: 3314 adds r3, #20
800429e: f8d7 20d0 ldr.w r2, [r7, #208] ; 0xd0
80042a2: f8c7 20a8 str.w r2, [r7, #168] ; 0xa8
80042a6: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4
*/
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80042aa: f8d7 10a4 ldr.w r1, [r7, #164] ; 0xa4
80042ae: f8d7 20a8 ldr.w r2, [r7, #168] ; 0xa8
80042b2: e841 2300 strex r3, r2, [r1]
80042b6: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0
return(result);
80042ba: f8d7 30a0 ldr.w r3, [r7, #160] ; 0xa0
80042be: 2b00 cmp r3, #0
80042c0: d1d9 bne.n 8004276 <HAL_UART_IRQHandler+0x18e>
/* Abort the UART DMA Rx stream */
if (huart->hdmarx != NULL)
80042c2: 687b ldr r3, [r7, #4]
80042c4: 6b9b ldr r3, [r3, #56] ; 0x38
80042c6: 2b00 cmp r3, #0
80042c8: d013 beq.n 80042f2 <HAL_UART_IRQHandler+0x20a>
{
/* Set the UART DMA Abort callback :
will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
80042ca: 687b ldr r3, [r7, #4]
80042cc: 6b9b ldr r3, [r3, #56] ; 0x38
80042ce: 4a7d ldr r2, [pc, #500] ; (80044c4 <HAL_UART_IRQHandler+0x3dc>)
80042d0: 651a str r2, [r3, #80] ; 0x50
if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
80042d2: 687b ldr r3, [r7, #4]
80042d4: 6b9b ldr r3, [r3, #56] ; 0x38
80042d6: 4618 mov r0, r3
80042d8: f7fe fdd9 bl 8002e8e <HAL_DMA_Abort_IT>
80042dc: 4603 mov r3, r0
80042de: 2b00 cmp r3, #0
80042e0: d016 beq.n 8004310 <HAL_UART_IRQHandler+0x228>
{
/* Call Directly XferAbortCallback function in case of error */
huart->hdmarx->XferAbortCallback(huart->hdmarx);
80042e2: 687b ldr r3, [r7, #4]
80042e4: 6b9b ldr r3, [r3, #56] ; 0x38
80042e6: 6d1b ldr r3, [r3, #80] ; 0x50
80042e8: 687a ldr r2, [r7, #4]
80042ea: 6b92 ldr r2, [r2, #56] ; 0x38
80042ec: 4610 mov r0, r2
80042ee: 4798 blx r3
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
80042f0: e00e b.n 8004310 <HAL_UART_IRQHandler+0x228>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
80042f2: 6878 ldr r0, [r7, #4]
80042f4: f000 f990 bl 8004618 <HAL_UART_ErrorCallback>
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
80042f8: e00a b.n 8004310 <HAL_UART_IRQHandler+0x228>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
80042fa: 6878 ldr r0, [r7, #4]
80042fc: f000 f98c bl 8004618 <HAL_UART_ErrorCallback>
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
8004300: e006 b.n 8004310 <HAL_UART_IRQHandler+0x228>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
8004302: 6878 ldr r0, [r7, #4]
8004304: f000 f988 bl 8004618 <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
huart->ErrorCode = HAL_UART_ERROR_NONE;
8004308: 687b ldr r3, [r7, #4]
800430a: 2200 movs r2, #0
800430c: 641a str r2, [r3, #64] ; 0x40
}
}
return;
800430e: e170 b.n 80045f2 <HAL_UART_IRQHandler+0x50a>
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
8004310: bf00 nop
return;
8004312: e16e b.n 80045f2 <HAL_UART_IRQHandler+0x50a>
} /* End if some error occurs */
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8004314: 687b ldr r3, [r7, #4]
8004316: 6b1b ldr r3, [r3, #48] ; 0x30
8004318: 2b01 cmp r3, #1
800431a: f040 814a bne.w 80045b2 <HAL_UART_IRQHandler+0x4ca>
&& ((isrflags & USART_SR_IDLE) != 0U)
800431e: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4
8004322: f003 0310 and.w r3, r3, #16
8004326: 2b00 cmp r3, #0
8004328: f000 8143 beq.w 80045b2 <HAL_UART_IRQHandler+0x4ca>
&& ((cr1its & USART_SR_IDLE) != 0U))
800432c: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0
8004330: f003 0310 and.w r3, r3, #16
8004334: 2b00 cmp r3, #0
8004336: f000 813c beq.w 80045b2 <HAL_UART_IRQHandler+0x4ca>
{
__HAL_UART_CLEAR_IDLEFLAG(huart);
800433a: 2300 movs r3, #0
800433c: 60bb str r3, [r7, #8]
800433e: 687b ldr r3, [r7, #4]
8004340: 681b ldr r3, [r3, #0]
8004342: 681b ldr r3, [r3, #0]
8004344: 60bb str r3, [r7, #8]
8004346: 687b ldr r3, [r7, #4]
8004348: 681b ldr r3, [r3, #0]
800434a: 685b ldr r3, [r3, #4]
800434c: 60bb str r3, [r7, #8]
800434e: 68bb ldr r3, [r7, #8]
/* Check if DMA mode is enabled in UART */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
8004350: 687b ldr r3, [r7, #4]
8004352: 681b ldr r3, [r3, #0]
8004354: 695b ldr r3, [r3, #20]
8004356: f003 0340 and.w r3, r3, #64 ; 0x40
800435a: 2b40 cmp r3, #64 ; 0x40
800435c: f040 80b4 bne.w 80044c8 <HAL_UART_IRQHandler+0x3e0>
{
/* DMA mode enabled */
/* Check received length : If all expected data are received, do nothing,
(DMA cplt callback will be called).
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
8004360: 687b ldr r3, [r7, #4]
8004362: 6b9b ldr r3, [r3, #56] ; 0x38
8004364: 681b ldr r3, [r3, #0]
8004366: 685b ldr r3, [r3, #4]
8004368: f8a7 30be strh.w r3, [r7, #190] ; 0xbe
if ((nb_remaining_rx_data > 0U)
800436c: f8b7 30be ldrh.w r3, [r7, #190] ; 0xbe
8004370: 2b00 cmp r3, #0
8004372: f000 8140 beq.w 80045f6 <HAL_UART_IRQHandler+0x50e>
&& (nb_remaining_rx_data < huart->RxXferSize))
8004376: 687b ldr r3, [r7, #4]
8004378: 8d9b ldrh r3, [r3, #44] ; 0x2c
800437a: f8b7 20be ldrh.w r2, [r7, #190] ; 0xbe
800437e: 429a cmp r2, r3
8004380: f080 8139 bcs.w 80045f6 <HAL_UART_IRQHandler+0x50e>
{
/* Reception is not complete */
huart->RxXferCount = nb_remaining_rx_data;
8004384: 687b ldr r3, [r7, #4]
8004386: f8b7 20be ldrh.w r2, [r7, #190] ; 0xbe
800438a: 85da strh r2, [r3, #46] ; 0x2e
/* In Normal mode, end DMA xfer and HAL UART Rx process*/
if (huart->hdmarx->Init.Mode != DMA_CIRCULAR)
800438c: 687b ldr r3, [r7, #4]
800438e: 6b9b ldr r3, [r3, #56] ; 0x38
8004390: 69db ldr r3, [r3, #28]
8004392: f5b3 7f80 cmp.w r3, #256 ; 0x100
8004396: f000 8088 beq.w 80044aa <HAL_UART_IRQHandler+0x3c2>
{
/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
800439a: 687b ldr r3, [r7, #4]
800439c: 681b ldr r3, [r3, #0]
800439e: 330c adds r3, #12
80043a0: f8c7 3088 str.w r3, [r7, #136] ; 0x88
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80043a4: f8d7 3088 ldr.w r3, [r7, #136] ; 0x88
80043a8: e853 3f00 ldrex r3, [r3]
80043ac: f8c7 3084 str.w r3, [r7, #132] ; 0x84
return(result);
80043b0: f8d7 3084 ldr.w r3, [r7, #132] ; 0x84
80043b4: f423 7380 bic.w r3, r3, #256 ; 0x100
80043b8: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8
80043bc: 687b ldr r3, [r7, #4]
80043be: 681b ldr r3, [r3, #0]
80043c0: 330c adds r3, #12
80043c2: f8d7 20b8 ldr.w r2, [r7, #184] ; 0xb8
80043c6: f8c7 2094 str.w r2, [r7, #148] ; 0x94
80043ca: f8c7 3090 str.w r3, [r7, #144] ; 0x90
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80043ce: f8d7 1090 ldr.w r1, [r7, #144] ; 0x90
80043d2: f8d7 2094 ldr.w r2, [r7, #148] ; 0x94
80043d6: e841 2300 strex r3, r2, [r1]
80043da: f8c7 308c str.w r3, [r7, #140] ; 0x8c
return(result);
80043de: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c
80043e2: 2b00 cmp r3, #0
80043e4: d1d9 bne.n 800439a <HAL_UART_IRQHandler+0x2b2>
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
80043e6: 687b ldr r3, [r7, #4]
80043e8: 681b ldr r3, [r3, #0]
80043ea: 3314 adds r3, #20
80043ec: 677b str r3, [r7, #116] ; 0x74
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80043ee: 6f7b ldr r3, [r7, #116] ; 0x74
80043f0: e853 3f00 ldrex r3, [r3]
80043f4: 673b str r3, [r7, #112] ; 0x70
return(result);
80043f6: 6f3b ldr r3, [r7, #112] ; 0x70
80043f8: f023 0301 bic.w r3, r3, #1
80043fc: f8c7 30b4 str.w r3, [r7, #180] ; 0xb4
8004400: 687b ldr r3, [r7, #4]
8004402: 681b ldr r3, [r3, #0]
8004404: 3314 adds r3, #20
8004406: f8d7 20b4 ldr.w r2, [r7, #180] ; 0xb4
800440a: f8c7 2080 str.w r2, [r7, #128] ; 0x80
800440e: 67fb str r3, [r7, #124] ; 0x7c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004410: 6ff9 ldr r1, [r7, #124] ; 0x7c
8004412: f8d7 2080 ldr.w r2, [r7, #128] ; 0x80
8004416: e841 2300 strex r3, r2, [r1]
800441a: 67bb str r3, [r7, #120] ; 0x78
return(result);
800441c: 6fbb ldr r3, [r7, #120] ; 0x78
800441e: 2b00 cmp r3, #0
8004420: d1e1 bne.n 80043e6 <HAL_UART_IRQHandler+0x2fe>
/* Disable the DMA transfer for the receiver request by resetting the DMAR bit
in the UART CR3 register */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
8004422: 687b ldr r3, [r7, #4]
8004424: 681b ldr r3, [r3, #0]
8004426: 3314 adds r3, #20
8004428: 663b str r3, [r7, #96] ; 0x60
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
800442a: 6e3b ldr r3, [r7, #96] ; 0x60
800442c: e853 3f00 ldrex r3, [r3]
8004430: 65fb str r3, [r7, #92] ; 0x5c
return(result);
8004432: 6dfb ldr r3, [r7, #92] ; 0x5c
8004434: f023 0340 bic.w r3, r3, #64 ; 0x40
8004438: f8c7 30b0 str.w r3, [r7, #176] ; 0xb0
800443c: 687b ldr r3, [r7, #4]
800443e: 681b ldr r3, [r3, #0]
8004440: 3314 adds r3, #20
8004442: f8d7 20b0 ldr.w r2, [r7, #176] ; 0xb0
8004446: 66fa str r2, [r7, #108] ; 0x6c
8004448: 66bb str r3, [r7, #104] ; 0x68
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
800444a: 6eb9 ldr r1, [r7, #104] ; 0x68
800444c: 6efa ldr r2, [r7, #108] ; 0x6c
800444e: e841 2300 strex r3, r2, [r1]
8004452: 667b str r3, [r7, #100] ; 0x64
return(result);
8004454: 6e7b ldr r3, [r7, #100] ; 0x64
8004456: 2b00 cmp r3, #0
8004458: d1e3 bne.n 8004422 <HAL_UART_IRQHandler+0x33a>
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
800445a: 687b ldr r3, [r7, #4]
800445c: 2220 movs r2, #32
800445e: f883 203e strb.w r2, [r3, #62] ; 0x3e
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8004462: 687b ldr r3, [r7, #4]
8004464: 2200 movs r2, #0
8004466: 631a str r2, [r3, #48] ; 0x30
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8004468: 687b ldr r3, [r7, #4]
800446a: 681b ldr r3, [r3, #0]
800446c: 330c adds r3, #12
800446e: 64fb str r3, [r7, #76] ; 0x4c
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004470: 6cfb ldr r3, [r7, #76] ; 0x4c
8004472: e853 3f00 ldrex r3, [r3]
8004476: 64bb str r3, [r7, #72] ; 0x48
return(result);
8004478: 6cbb ldr r3, [r7, #72] ; 0x48
800447a: f023 0310 bic.w r3, r3, #16
800447e: f8c7 30ac str.w r3, [r7, #172] ; 0xac
8004482: 687b ldr r3, [r7, #4]
8004484: 681b ldr r3, [r3, #0]
8004486: 330c adds r3, #12
8004488: f8d7 20ac ldr.w r2, [r7, #172] ; 0xac
800448c: 65ba str r2, [r7, #88] ; 0x58
800448e: 657b str r3, [r7, #84] ; 0x54
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004490: 6d79 ldr r1, [r7, #84] ; 0x54
8004492: 6dba ldr r2, [r7, #88] ; 0x58
8004494: e841 2300 strex r3, r2, [r1]
8004498: 653b str r3, [r7, #80] ; 0x50
return(result);
800449a: 6d3b ldr r3, [r7, #80] ; 0x50
800449c: 2b00 cmp r3, #0
800449e: d1e3 bne.n 8004468 <HAL_UART_IRQHandler+0x380>
/* Last bytes received, so no need as the abort is immediate */
(void)HAL_DMA_Abort(huart->hdmarx);
80044a0: 687b ldr r3, [r7, #4]
80044a2: 6b9b ldr r3, [r3, #56] ; 0x38
80044a4: 4618 mov r0, r3
80044a6: f7fe fc82 bl 8002dae <HAL_DMA_Abort>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
80044aa: 687b ldr r3, [r7, #4]
80044ac: 8d9a ldrh r2, [r3, #44] ; 0x2c
80044ae: 687b ldr r3, [r7, #4]
80044b0: 8ddb ldrh r3, [r3, #46] ; 0x2e
80044b2: b29b uxth r3, r3
80044b4: 1ad3 subs r3, r2, r3
80044b6: b29b uxth r3, r3
80044b8: 4619 mov r1, r3
80044ba: 6878 ldr r0, [r7, #4]
80044bc: f000 f8b6 bl 800462c <HAL_UARTEx_RxEventCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
return;
80044c0: e099 b.n 80045f6 <HAL_UART_IRQHandler+0x50e>
80044c2: bf00 nop
80044c4: 0800485b .word 0x0800485b
else
{
/* DMA mode not enabled */
/* Check received length : If all expected data are received, do nothing.
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
80044c8: 687b ldr r3, [r7, #4]
80044ca: 8d9a ldrh r2, [r3, #44] ; 0x2c
80044cc: 687b ldr r3, [r7, #4]
80044ce: 8ddb ldrh r3, [r3, #46] ; 0x2e
80044d0: b29b uxth r3, r3
80044d2: 1ad3 subs r3, r2, r3
80044d4: f8a7 30ce strh.w r3, [r7, #206] ; 0xce
if ((huart->RxXferCount > 0U)
80044d8: 687b ldr r3, [r7, #4]
80044da: 8ddb ldrh r3, [r3, #46] ; 0x2e
80044dc: b29b uxth r3, r3
80044de: 2b00 cmp r3, #0
80044e0: f000 808b beq.w 80045fa <HAL_UART_IRQHandler+0x512>
&& (nb_rx_data > 0U))
80044e4: f8b7 30ce ldrh.w r3, [r7, #206] ; 0xce
80044e8: 2b00 cmp r3, #0
80044ea: f000 8086 beq.w 80045fa <HAL_UART_IRQHandler+0x512>
{
/* Disable the UART Parity Error Interrupt and RXNE interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
80044ee: 687b ldr r3, [r7, #4]
80044f0: 681b ldr r3, [r3, #0]
80044f2: 330c adds r3, #12
80044f4: 63bb str r3, [r7, #56] ; 0x38
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80044f6: 6bbb ldr r3, [r7, #56] ; 0x38
80044f8: e853 3f00 ldrex r3, [r3]
80044fc: 637b str r3, [r7, #52] ; 0x34
return(result);
80044fe: 6b7b ldr r3, [r7, #52] ; 0x34
8004500: f423 7390 bic.w r3, r3, #288 ; 0x120
8004504: f8c7 30c8 str.w r3, [r7, #200] ; 0xc8
8004508: 687b ldr r3, [r7, #4]
800450a: 681b ldr r3, [r3, #0]
800450c: 330c adds r3, #12
800450e: f8d7 20c8 ldr.w r2, [r7, #200] ; 0xc8
8004512: 647a str r2, [r7, #68] ; 0x44
8004514: 643b str r3, [r7, #64] ; 0x40
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004516: 6c39 ldr r1, [r7, #64] ; 0x40
8004518: 6c7a ldr r2, [r7, #68] ; 0x44
800451a: e841 2300 strex r3, r2, [r1]
800451e: 63fb str r3, [r7, #60] ; 0x3c
return(result);
8004520: 6bfb ldr r3, [r7, #60] ; 0x3c
8004522: 2b00 cmp r3, #0
8004524: d1e3 bne.n 80044ee <HAL_UART_IRQHandler+0x406>
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8004526: 687b ldr r3, [r7, #4]
8004528: 681b ldr r3, [r3, #0]
800452a: 3314 adds r3, #20
800452c: 627b str r3, [r7, #36] ; 0x24
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
800452e: 6a7b ldr r3, [r7, #36] ; 0x24
8004530: e853 3f00 ldrex r3, [r3]
8004534: 623b str r3, [r7, #32]
return(result);
8004536: 6a3b ldr r3, [r7, #32]
8004538: f023 0301 bic.w r3, r3, #1
800453c: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4
8004540: 687b ldr r3, [r7, #4]
8004542: 681b ldr r3, [r3, #0]
8004544: 3314 adds r3, #20
8004546: f8d7 20c4 ldr.w r2, [r7, #196] ; 0xc4
800454a: 633a str r2, [r7, #48] ; 0x30
800454c: 62fb str r3, [r7, #44] ; 0x2c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
800454e: 6af9 ldr r1, [r7, #44] ; 0x2c
8004550: 6b3a ldr r2, [r7, #48] ; 0x30
8004552: e841 2300 strex r3, r2, [r1]
8004556: 62bb str r3, [r7, #40] ; 0x28
return(result);
8004558: 6abb ldr r3, [r7, #40] ; 0x28
800455a: 2b00 cmp r3, #0
800455c: d1e3 bne.n 8004526 <HAL_UART_IRQHandler+0x43e>
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
800455e: 687b ldr r3, [r7, #4]
8004560: 2220 movs r2, #32
8004562: f883 203e strb.w r2, [r3, #62] ; 0x3e
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8004566: 687b ldr r3, [r7, #4]
8004568: 2200 movs r2, #0
800456a: 631a str r2, [r3, #48] ; 0x30
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
800456c: 687b ldr r3, [r7, #4]
800456e: 681b ldr r3, [r3, #0]
8004570: 330c adds r3, #12
8004572: 613b str r3, [r7, #16]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004574: 693b ldr r3, [r7, #16]
8004576: e853 3f00 ldrex r3, [r3]
800457a: 60fb str r3, [r7, #12]
return(result);
800457c: 68fb ldr r3, [r7, #12]
800457e: f023 0310 bic.w r3, r3, #16
8004582: f8c7 30c0 str.w r3, [r7, #192] ; 0xc0
8004586: 687b ldr r3, [r7, #4]
8004588: 681b ldr r3, [r3, #0]
800458a: 330c adds r3, #12
800458c: f8d7 20c0 ldr.w r2, [r7, #192] ; 0xc0
8004590: 61fa str r2, [r7, #28]
8004592: 61bb str r3, [r7, #24]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004594: 69b9 ldr r1, [r7, #24]
8004596: 69fa ldr r2, [r7, #28]
8004598: e841 2300 strex r3, r2, [r1]
800459c: 617b str r3, [r7, #20]
return(result);
800459e: 697b ldr r3, [r7, #20]
80045a0: 2b00 cmp r3, #0
80045a2: d1e3 bne.n 800456c <HAL_UART_IRQHandler+0x484>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx complete callback*/
huart->RxEventCallback(huart, nb_rx_data);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
80045a4: f8b7 30ce ldrh.w r3, [r7, #206] ; 0xce
80045a8: 4619 mov r1, r3
80045aa: 6878 ldr r0, [r7, #4]
80045ac: f000 f83e bl 800462c <HAL_UARTEx_RxEventCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
return;
80045b0: e023 b.n 80045fa <HAL_UART_IRQHandler+0x512>
}
}
/* UART in mode Transmitter ------------------------------------------------*/
if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
80045b2: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4
80045b6: f003 0380 and.w r3, r3, #128 ; 0x80
80045ba: 2b00 cmp r3, #0
80045bc: d009 beq.n 80045d2 <HAL_UART_IRQHandler+0x4ea>
80045be: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0
80045c2: f003 0380 and.w r3, r3, #128 ; 0x80
80045c6: 2b00 cmp r3, #0
80045c8: d003 beq.n 80045d2 <HAL_UART_IRQHandler+0x4ea>
{
UART_Transmit_IT(huart);
80045ca: 6878 ldr r0, [r7, #4]
80045cc: f000 f959 bl 8004882 <UART_Transmit_IT>
return;
80045d0: e014 b.n 80045fc <HAL_UART_IRQHandler+0x514>
}
/* UART in mode Transmitter end --------------------------------------------*/
if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
80045d2: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4
80045d6: f003 0340 and.w r3, r3, #64 ; 0x40
80045da: 2b00 cmp r3, #0
80045dc: d00e beq.n 80045fc <HAL_UART_IRQHandler+0x514>
80045de: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0
80045e2: f003 0340 and.w r3, r3, #64 ; 0x40
80045e6: 2b00 cmp r3, #0
80045e8: d008 beq.n 80045fc <HAL_UART_IRQHandler+0x514>
{
UART_EndTransmit_IT(huart);
80045ea: 6878 ldr r0, [r7, #4]
80045ec: f000 f999 bl 8004922 <UART_EndTransmit_IT>
return;
80045f0: e004 b.n 80045fc <HAL_UART_IRQHandler+0x514>
return;
80045f2: bf00 nop
80045f4: e002 b.n 80045fc <HAL_UART_IRQHandler+0x514>
return;
80045f6: bf00 nop
80045f8: e000 b.n 80045fc <HAL_UART_IRQHandler+0x514>
return;
80045fa: bf00 nop
}
}
80045fc: 37e8 adds r7, #232 ; 0xe8
80045fe: 46bd mov sp, r7
8004600: bd80 pop {r7, pc}
8004602: bf00 nop
08004604 <HAL_UART_TxCpltCallback>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
{
8004604: b480 push {r7}
8004606: b083 sub sp, #12
8004608: af00 add r7, sp, #0
800460a: 6078 str r0, [r7, #4]
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_UART_TxCpltCallback could be implemented in the user file
*/
}
800460c: bf00 nop
800460e: 370c adds r7, #12
8004610: 46bd mov sp, r7
8004612: f85d 7b04 ldr.w r7, [sp], #4
8004616: 4770 bx lr
08004618 <HAL_UART_ErrorCallback>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
{
8004618: b480 push {r7}
800461a: b083 sub sp, #12
800461c: af00 add r7, sp, #0
800461e: 6078 str r0, [r7, #4]
/* Prevent unused argument(s) compilation warning */
UNUSED(huart);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_UART_ErrorCallback could be implemented in the user file
*/
}
8004620: bf00 nop
8004622: 370c adds r7, #12
8004624: 46bd mov sp, r7
8004626: f85d 7b04 ldr.w r7, [sp], #4
800462a: 4770 bx lr
0800462c <HAL_UARTEx_RxEventCallback>:
* @param Size Number of data available in application reception buffer (indicates a position in
* reception buffer until which, data are available)
* @retval None
*/
__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
{
800462c: b480 push {r7}
800462e: b083 sub sp, #12
8004630: af00 add r7, sp, #0
8004632: 6078 str r0, [r7, #4]
8004634: 460b mov r3, r1
8004636: 807b strh r3, [r7, #2]
UNUSED(Size);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_UARTEx_RxEventCallback can be implemented in the user file.
*/
}
8004638: bf00 nop
800463a: 370c adds r7, #12
800463c: 46bd mov sp, r7
800463e: f85d 7b04 ldr.w r7, [sp], #4
8004642: 4770 bx lr
08004644 <UART_WaitOnFlagUntilTimeout>:
* @param Timeout Timeout duration
* @retval HAL status
*/
static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout)
{
8004644: b580 push {r7, lr}
8004646: b090 sub sp, #64 ; 0x40
8004648: af00 add r7, sp, #0
800464a: 60f8 str r0, [r7, #12]
800464c: 60b9 str r1, [r7, #8]
800464e: 603b str r3, [r7, #0]
8004650: 4613 mov r3, r2
8004652: 71fb strb r3, [r7, #7]
/* Wait until flag is set */
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
8004654: e050 b.n 80046f8 <UART_WaitOnFlagUntilTimeout+0xb4>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
8004656: 6cbb ldr r3, [r7, #72] ; 0x48
8004658: f1b3 3fff cmp.w r3, #4294967295
800465c: d04c beq.n 80046f8 <UART_WaitOnFlagUntilTimeout+0xb4>
{
if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
800465e: 6cbb ldr r3, [r7, #72] ; 0x48
8004660: 2b00 cmp r3, #0
8004662: d007 beq.n 8004674 <UART_WaitOnFlagUntilTimeout+0x30>
8004664: f7fd fc00 bl 8001e68 <HAL_GetTick>
8004668: 4602 mov r2, r0
800466a: 683b ldr r3, [r7, #0]
800466c: 1ad3 subs r3, r2, r3
800466e: 6cba ldr r2, [r7, #72] ; 0x48
8004670: 429a cmp r2, r3
8004672: d241 bcs.n 80046f8 <UART_WaitOnFlagUntilTimeout+0xb4>
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
8004674: 68fb ldr r3, [r7, #12]
8004676: 681b ldr r3, [r3, #0]
8004678: 330c adds r3, #12
800467a: 62bb str r3, [r7, #40] ; 0x28
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
800467c: 6abb ldr r3, [r7, #40] ; 0x28
800467e: e853 3f00 ldrex r3, [r3]
8004682: 627b str r3, [r7, #36] ; 0x24
return(result);
8004684: 6a7b ldr r3, [r7, #36] ; 0x24
8004686: f423 73d0 bic.w r3, r3, #416 ; 0x1a0
800468a: 63fb str r3, [r7, #60] ; 0x3c
800468c: 68fb ldr r3, [r7, #12]
800468e: 681b ldr r3, [r3, #0]
8004690: 330c adds r3, #12
8004692: 6bfa ldr r2, [r7, #60] ; 0x3c
8004694: 637a str r2, [r7, #52] ; 0x34
8004696: 633b str r3, [r7, #48] ; 0x30
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004698: 6b39 ldr r1, [r7, #48] ; 0x30
800469a: 6b7a ldr r2, [r7, #52] ; 0x34
800469c: e841 2300 strex r3, r2, [r1]
80046a0: 62fb str r3, [r7, #44] ; 0x2c
return(result);
80046a2: 6afb ldr r3, [r7, #44] ; 0x2c
80046a4: 2b00 cmp r3, #0
80046a6: d1e5 bne.n 8004674 <UART_WaitOnFlagUntilTimeout+0x30>
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
80046a8: 68fb ldr r3, [r7, #12]
80046aa: 681b ldr r3, [r3, #0]
80046ac: 3314 adds r3, #20
80046ae: 617b str r3, [r7, #20]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80046b0: 697b ldr r3, [r7, #20]
80046b2: e853 3f00 ldrex r3, [r3]
80046b6: 613b str r3, [r7, #16]
return(result);
80046b8: 693b ldr r3, [r7, #16]
80046ba: f023 0301 bic.w r3, r3, #1
80046be: 63bb str r3, [r7, #56] ; 0x38
80046c0: 68fb ldr r3, [r7, #12]
80046c2: 681b ldr r3, [r3, #0]
80046c4: 3314 adds r3, #20
80046c6: 6bba ldr r2, [r7, #56] ; 0x38
80046c8: 623a str r2, [r7, #32]
80046ca: 61fb str r3, [r7, #28]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80046cc: 69f9 ldr r1, [r7, #28]
80046ce: 6a3a ldr r2, [r7, #32]
80046d0: e841 2300 strex r3, r2, [r1]
80046d4: 61bb str r3, [r7, #24]
return(result);
80046d6: 69bb ldr r3, [r7, #24]
80046d8: 2b00 cmp r3, #0
80046da: d1e5 bne.n 80046a8 <UART_WaitOnFlagUntilTimeout+0x64>
huart->gState = HAL_UART_STATE_READY;
80046dc: 68fb ldr r3, [r7, #12]
80046de: 2220 movs r2, #32
80046e0: f883 203d strb.w r2, [r3, #61] ; 0x3d
huart->RxState = HAL_UART_STATE_READY;
80046e4: 68fb ldr r3, [r7, #12]
80046e6: 2220 movs r2, #32
80046e8: f883 203e strb.w r2, [r3, #62] ; 0x3e
/* Process Unlocked */
__HAL_UNLOCK(huart);
80046ec: 68fb ldr r3, [r7, #12]
80046ee: 2200 movs r2, #0
80046f0: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_TIMEOUT;
80046f4: 2303 movs r3, #3
80046f6: e00f b.n 8004718 <UART_WaitOnFlagUntilTimeout+0xd4>
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
80046f8: 68fb ldr r3, [r7, #12]
80046fa: 681b ldr r3, [r3, #0]
80046fc: 681a ldr r2, [r3, #0]
80046fe: 68bb ldr r3, [r7, #8]
8004700: 4013 ands r3, r2
8004702: 68ba ldr r2, [r7, #8]
8004704: 429a cmp r2, r3
8004706: bf0c ite eq
8004708: 2301 moveq r3, #1
800470a: 2300 movne r3, #0
800470c: b2db uxtb r3, r3
800470e: 461a mov r2, r3
8004710: 79fb ldrb r3, [r7, #7]
8004712: 429a cmp r2, r3
8004714: d09f beq.n 8004656 <UART_WaitOnFlagUntilTimeout+0x12>
}
}
}
return HAL_OK;
8004716: 2300 movs r3, #0
}
8004718: 4618 mov r0, r3
800471a: 3740 adds r7, #64 ; 0x40
800471c: 46bd mov sp, r7
800471e: bd80 pop {r7, pc}
08004720 <UART_Start_Receive_IT>:
* @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data elements (u8 or u16) to be received.
* @retval HAL status
*/
HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
{
8004720: b480 push {r7}
8004722: b085 sub sp, #20
8004724: af00 add r7, sp, #0
8004726: 60f8 str r0, [r7, #12]
8004728: 60b9 str r1, [r7, #8]
800472a: 4613 mov r3, r2
800472c: 80fb strh r3, [r7, #6]
huart->pRxBuffPtr = pData;
800472e: 68fb ldr r3, [r7, #12]
8004730: 68ba ldr r2, [r7, #8]
8004732: 629a str r2, [r3, #40] ; 0x28
huart->RxXferSize = Size;
8004734: 68fb ldr r3, [r7, #12]
8004736: 88fa ldrh r2, [r7, #6]
8004738: 859a strh r2, [r3, #44] ; 0x2c
huart->RxXferCount = Size;
800473a: 68fb ldr r3, [r7, #12]
800473c: 88fa ldrh r2, [r7, #6]
800473e: 85da strh r2, [r3, #46] ; 0x2e
huart->ErrorCode = HAL_UART_ERROR_NONE;
8004740: 68fb ldr r3, [r7, #12]
8004742: 2200 movs r2, #0
8004744: 641a str r2, [r3, #64] ; 0x40
huart->RxState = HAL_UART_STATE_BUSY_RX;
8004746: 68fb ldr r3, [r7, #12]
8004748: 2222 movs r2, #34 ; 0x22
800474a: f883 203e strb.w r2, [r3, #62] ; 0x3e
/* Process Unlocked */
__HAL_UNLOCK(huart);
800474e: 68fb ldr r3, [r7, #12]
8004750: 2200 movs r2, #0
8004752: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Enable the UART Parity Error Interrupt */
__HAL_UART_ENABLE_IT(huart, UART_IT_PE);
8004756: 68fb ldr r3, [r7, #12]
8004758: 681b ldr r3, [r3, #0]
800475a: 68da ldr r2, [r3, #12]
800475c: 68fb ldr r3, [r7, #12]
800475e: 681b ldr r3, [r3, #0]
8004760: f442 7280 orr.w r2, r2, #256 ; 0x100
8004764: 60da str r2, [r3, #12]
/* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
__HAL_UART_ENABLE_IT(huart, UART_IT_ERR);
8004766: 68fb ldr r3, [r7, #12]
8004768: 681b ldr r3, [r3, #0]
800476a: 695a ldr r2, [r3, #20]
800476c: 68fb ldr r3, [r7, #12]
800476e: 681b ldr r3, [r3, #0]
8004770: f042 0201 orr.w r2, r2, #1
8004774: 615a str r2, [r3, #20]
/* Enable the UART Data Register not empty Interrupt */
__HAL_UART_ENABLE_IT(huart, UART_IT_RXNE);
8004776: 68fb ldr r3, [r7, #12]
8004778: 681b ldr r3, [r3, #0]
800477a: 68da ldr r2, [r3, #12]
800477c: 68fb ldr r3, [r7, #12]
800477e: 681b ldr r3, [r3, #0]
8004780: f042 0220 orr.w r2, r2, #32
8004784: 60da str r2, [r3, #12]
return HAL_OK;
8004786: 2300 movs r3, #0
}
8004788: 4618 mov r0, r3
800478a: 3714 adds r7, #20
800478c: 46bd mov sp, r7
800478e: f85d 7b04 ldr.w r7, [sp], #4
8004792: 4770 bx lr
08004794 <UART_EndRxTransfer>:
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
* @param huart UART handle.
* @retval None
*/
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
{
8004794: b480 push {r7}
8004796: b095 sub sp, #84 ; 0x54
8004798: af00 add r7, sp, #0
800479a: 6078 str r0, [r7, #4]
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
800479c: 687b ldr r3, [r7, #4]
800479e: 681b ldr r3, [r3, #0]
80047a0: 330c adds r3, #12
80047a2: 637b str r3, [r7, #52] ; 0x34
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80047a4: 6b7b ldr r3, [r7, #52] ; 0x34
80047a6: e853 3f00 ldrex r3, [r3]
80047aa: 633b str r3, [r7, #48] ; 0x30
return(result);
80047ac: 6b3b ldr r3, [r7, #48] ; 0x30
80047ae: f423 7390 bic.w r3, r3, #288 ; 0x120
80047b2: 64fb str r3, [r7, #76] ; 0x4c
80047b4: 687b ldr r3, [r7, #4]
80047b6: 681b ldr r3, [r3, #0]
80047b8: 330c adds r3, #12
80047ba: 6cfa ldr r2, [r7, #76] ; 0x4c
80047bc: 643a str r2, [r7, #64] ; 0x40
80047be: 63fb str r3, [r7, #60] ; 0x3c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80047c0: 6bf9 ldr r1, [r7, #60] ; 0x3c
80047c2: 6c3a ldr r2, [r7, #64] ; 0x40
80047c4: e841 2300 strex r3, r2, [r1]
80047c8: 63bb str r3, [r7, #56] ; 0x38
return(result);
80047ca: 6bbb ldr r3, [r7, #56] ; 0x38
80047cc: 2b00 cmp r3, #0
80047ce: d1e5 bne.n 800479c <UART_EndRxTransfer+0x8>
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
80047d0: 687b ldr r3, [r7, #4]
80047d2: 681b ldr r3, [r3, #0]
80047d4: 3314 adds r3, #20
80047d6: 623b str r3, [r7, #32]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80047d8: 6a3b ldr r3, [r7, #32]
80047da: e853 3f00 ldrex r3, [r3]
80047de: 61fb str r3, [r7, #28]
return(result);
80047e0: 69fb ldr r3, [r7, #28]
80047e2: f023 0301 bic.w r3, r3, #1
80047e6: 64bb str r3, [r7, #72] ; 0x48
80047e8: 687b ldr r3, [r7, #4]
80047ea: 681b ldr r3, [r3, #0]
80047ec: 3314 adds r3, #20
80047ee: 6cba ldr r2, [r7, #72] ; 0x48
80047f0: 62fa str r2, [r7, #44] ; 0x2c
80047f2: 62bb str r3, [r7, #40] ; 0x28
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80047f4: 6ab9 ldr r1, [r7, #40] ; 0x28
80047f6: 6afa ldr r2, [r7, #44] ; 0x2c
80047f8: e841 2300 strex r3, r2, [r1]
80047fc: 627b str r3, [r7, #36] ; 0x24
return(result);
80047fe: 6a7b ldr r3, [r7, #36] ; 0x24
8004800: 2b00 cmp r3, #0
8004802: d1e5 bne.n 80047d0 <UART_EndRxTransfer+0x3c>
/* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8004804: 687b ldr r3, [r7, #4]
8004806: 6b1b ldr r3, [r3, #48] ; 0x30
8004808: 2b01 cmp r3, #1
800480a: d119 bne.n 8004840 <UART_EndRxTransfer+0xac>
{
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
800480c: 687b ldr r3, [r7, #4]
800480e: 681b ldr r3, [r3, #0]
8004810: 330c adds r3, #12
8004812: 60fb str r3, [r7, #12]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004814: 68fb ldr r3, [r7, #12]
8004816: e853 3f00 ldrex r3, [r3]
800481a: 60bb str r3, [r7, #8]
return(result);
800481c: 68bb ldr r3, [r7, #8]
800481e: f023 0310 bic.w r3, r3, #16
8004822: 647b str r3, [r7, #68] ; 0x44
8004824: 687b ldr r3, [r7, #4]
8004826: 681b ldr r3, [r3, #0]
8004828: 330c adds r3, #12
800482a: 6c7a ldr r2, [r7, #68] ; 0x44
800482c: 61ba str r2, [r7, #24]
800482e: 617b str r3, [r7, #20]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004830: 6979 ldr r1, [r7, #20]
8004832: 69ba ldr r2, [r7, #24]
8004834: e841 2300 strex r3, r2, [r1]
8004838: 613b str r3, [r7, #16]
return(result);
800483a: 693b ldr r3, [r7, #16]
800483c: 2b00 cmp r3, #0
800483e: d1e5 bne.n 800480c <UART_EndRxTransfer+0x78>
}
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8004840: 687b ldr r3, [r7, #4]
8004842: 2220 movs r2, #32
8004844: f883 203e strb.w r2, [r3, #62] ; 0x3e
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8004848: 687b ldr r3, [r7, #4]
800484a: 2200 movs r2, #0
800484c: 631a str r2, [r3, #48] ; 0x30
}
800484e: bf00 nop
8004850: 3754 adds r7, #84 ; 0x54
8004852: 46bd mov sp, r7
8004854: f85d 7b04 ldr.w r7, [sp], #4
8004858: 4770 bx lr
0800485a <UART_DMAAbortOnError>:
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
800485a: b580 push {r7, lr}
800485c: b084 sub sp, #16
800485e: af00 add r7, sp, #0
8004860: 6078 str r0, [r7, #4]
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
8004862: 687b ldr r3, [r7, #4]
8004864: 6b9b ldr r3, [r3, #56] ; 0x38
8004866: 60fb str r3, [r7, #12]
huart->RxXferCount = 0x00U;
8004868: 68fb ldr r3, [r7, #12]
800486a: 2200 movs r2, #0
800486c: 85da strh r2, [r3, #46] ; 0x2e
huart->TxXferCount = 0x00U;
800486e: 68fb ldr r3, [r7, #12]
8004870: 2200 movs r2, #0
8004872: 84da strh r2, [r3, #38] ; 0x26
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
8004874: 68f8 ldr r0, [r7, #12]
8004876: f7ff fecf bl 8004618 <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
800487a: bf00 nop
800487c: 3710 adds r7, #16
800487e: 46bd mov sp, r7
8004880: bd80 pop {r7, pc}
08004882 <UART_Transmit_IT>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
{
8004882: b480 push {r7}
8004884: b085 sub sp, #20
8004886: af00 add r7, sp, #0
8004888: 6078 str r0, [r7, #4]
uint16_t *tmp;
/* Check that a Tx process is ongoing */
if (huart->gState == HAL_UART_STATE_BUSY_TX)
800488a: 687b ldr r3, [r7, #4]
800488c: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
8004890: b2db uxtb r3, r3
8004892: 2b21 cmp r3, #33 ; 0x21
8004894: d13e bne.n 8004914 <UART_Transmit_IT+0x92>
{
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
8004896: 687b ldr r3, [r7, #4]
8004898: 689b ldr r3, [r3, #8]
800489a: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
800489e: d114 bne.n 80048ca <UART_Transmit_IT+0x48>
80048a0: 687b ldr r3, [r7, #4]
80048a2: 691b ldr r3, [r3, #16]
80048a4: 2b00 cmp r3, #0
80048a6: d110 bne.n 80048ca <UART_Transmit_IT+0x48>
{
tmp = (uint16_t *) huart->pTxBuffPtr;
80048a8: 687b ldr r3, [r7, #4]
80048aa: 6a1b ldr r3, [r3, #32]
80048ac: 60fb str r3, [r7, #12]
huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
80048ae: 68fb ldr r3, [r7, #12]
80048b0: 881b ldrh r3, [r3, #0]
80048b2: 461a mov r2, r3
80048b4: 687b ldr r3, [r7, #4]
80048b6: 681b ldr r3, [r3, #0]
80048b8: f3c2 0208 ubfx r2, r2, #0, #9
80048bc: 605a str r2, [r3, #4]
huart->pTxBuffPtr += 2U;
80048be: 687b ldr r3, [r7, #4]
80048c0: 6a1b ldr r3, [r3, #32]
80048c2: 1c9a adds r2, r3, #2
80048c4: 687b ldr r3, [r7, #4]
80048c6: 621a str r2, [r3, #32]
80048c8: e008 b.n 80048dc <UART_Transmit_IT+0x5a>
}
else
{
huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF);
80048ca: 687b ldr r3, [r7, #4]
80048cc: 6a1b ldr r3, [r3, #32]
80048ce: 1c59 adds r1, r3, #1
80048d0: 687a ldr r2, [r7, #4]
80048d2: 6211 str r1, [r2, #32]
80048d4: 781a ldrb r2, [r3, #0]
80048d6: 687b ldr r3, [r7, #4]
80048d8: 681b ldr r3, [r3, #0]
80048da: 605a str r2, [r3, #4]
}
if (--huart->TxXferCount == 0U)
80048dc: 687b ldr r3, [r7, #4]
80048de: 8cdb ldrh r3, [r3, #38] ; 0x26
80048e0: b29b uxth r3, r3
80048e2: 3b01 subs r3, #1
80048e4: b29b uxth r3, r3
80048e6: 687a ldr r2, [r7, #4]
80048e8: 4619 mov r1, r3
80048ea: 84d1 strh r1, [r2, #38] ; 0x26
80048ec: 2b00 cmp r3, #0
80048ee: d10f bne.n 8004910 <UART_Transmit_IT+0x8e>
{
/* Disable the UART Transmit Complete Interrupt */
__HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
80048f0: 687b ldr r3, [r7, #4]
80048f2: 681b ldr r3, [r3, #0]
80048f4: 68da ldr r2, [r3, #12]
80048f6: 687b ldr r3, [r7, #4]
80048f8: 681b ldr r3, [r3, #0]
80048fa: f022 0280 bic.w r2, r2, #128 ; 0x80
80048fe: 60da str r2, [r3, #12]
/* Enable the UART Transmit Complete Interrupt */
__HAL_UART_ENABLE_IT(huart, UART_IT_TC);
8004900: 687b ldr r3, [r7, #4]
8004902: 681b ldr r3, [r3, #0]
8004904: 68da ldr r2, [r3, #12]
8004906: 687b ldr r3, [r7, #4]
8004908: 681b ldr r3, [r3, #0]
800490a: f042 0240 orr.w r2, r2, #64 ; 0x40
800490e: 60da str r2, [r3, #12]
}
return HAL_OK;
8004910: 2300 movs r3, #0
8004912: e000 b.n 8004916 <UART_Transmit_IT+0x94>
}
else
{
return HAL_BUSY;
8004914: 2302 movs r3, #2
}
}
8004916: 4618 mov r0, r3
8004918: 3714 adds r7, #20
800491a: 46bd mov sp, r7
800491c: f85d 7b04 ldr.w r7, [sp], #4
8004920: 4770 bx lr
08004922 <UART_EndTransmit_IT>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
{
8004922: b580 push {r7, lr}
8004924: b082 sub sp, #8
8004926: af00 add r7, sp, #0
8004928: 6078 str r0, [r7, #4]
/* Disable the UART Transmit Complete Interrupt */
__HAL_UART_DISABLE_IT(huart, UART_IT_TC);
800492a: 687b ldr r3, [r7, #4]
800492c: 681b ldr r3, [r3, #0]
800492e: 68da ldr r2, [r3, #12]
8004930: 687b ldr r3, [r7, #4]
8004932: 681b ldr r3, [r3, #0]
8004934: f022 0240 bic.w r2, r2, #64 ; 0x40
8004938: 60da str r2, [r3, #12]
/* Tx process is ended, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
800493a: 687b ldr r3, [r7, #4]
800493c: 2220 movs r2, #32
800493e: f883 203d strb.w r2, [r3, #61] ; 0x3d
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Tx complete callback*/
huart->TxCpltCallback(huart);
#else
/*Call legacy weak Tx complete callback*/
HAL_UART_TxCpltCallback(huart);
8004942: 6878 ldr r0, [r7, #4]
8004944: f7ff fe5e bl 8004604 <HAL_UART_TxCpltCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
return HAL_OK;
8004948: 2300 movs r3, #0
}
800494a: 4618 mov r0, r3
800494c: 3708 adds r7, #8
800494e: 46bd mov sp, r7
8004950: bd80 pop {r7, pc}
08004952 <UART_Receive_IT>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
{
8004952: b580 push {r7, lr}
8004954: b08c sub sp, #48 ; 0x30
8004956: af00 add r7, sp, #0
8004958: 6078 str r0, [r7, #4]
uint8_t *pdata8bits;
uint16_t *pdata16bits;
/* Check that a Rx process is ongoing */
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
800495a: 687b ldr r3, [r7, #4]
800495c: f893 303e ldrb.w r3, [r3, #62] ; 0x3e
8004960: b2db uxtb r3, r3
8004962: 2b22 cmp r3, #34 ; 0x22
8004964: f040 80ab bne.w 8004abe <UART_Receive_IT+0x16c>
{
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
8004968: 687b ldr r3, [r7, #4]
800496a: 689b ldr r3, [r3, #8]
800496c: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
8004970: d117 bne.n 80049a2 <UART_Receive_IT+0x50>
8004972: 687b ldr r3, [r7, #4]
8004974: 691b ldr r3, [r3, #16]
8004976: 2b00 cmp r3, #0
8004978: d113 bne.n 80049a2 <UART_Receive_IT+0x50>
{
pdata8bits = NULL;
800497a: 2300 movs r3, #0
800497c: 62fb str r3, [r7, #44] ; 0x2c
pdata16bits = (uint16_t *) huart->pRxBuffPtr;
800497e: 687b ldr r3, [r7, #4]
8004980: 6a9b ldr r3, [r3, #40] ; 0x28
8004982: 62bb str r3, [r7, #40] ; 0x28
*pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
8004984: 687b ldr r3, [r7, #4]
8004986: 681b ldr r3, [r3, #0]
8004988: 685b ldr r3, [r3, #4]
800498a: b29b uxth r3, r3
800498c: f3c3 0308 ubfx r3, r3, #0, #9
8004990: b29a uxth r2, r3
8004992: 6abb ldr r3, [r7, #40] ; 0x28
8004994: 801a strh r2, [r3, #0]
huart->pRxBuffPtr += 2U;
8004996: 687b ldr r3, [r7, #4]
8004998: 6a9b ldr r3, [r3, #40] ; 0x28
800499a: 1c9a adds r2, r3, #2
800499c: 687b ldr r3, [r7, #4]
800499e: 629a str r2, [r3, #40] ; 0x28
80049a0: e026 b.n 80049f0 <UART_Receive_IT+0x9e>
}
else
{
pdata8bits = (uint8_t *) huart->pRxBuffPtr;
80049a2: 687b ldr r3, [r7, #4]
80049a4: 6a9b ldr r3, [r3, #40] ; 0x28
80049a6: 62fb str r3, [r7, #44] ; 0x2c
pdata16bits = NULL;
80049a8: 2300 movs r3, #0
80049aa: 62bb str r3, [r7, #40] ; 0x28
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE)))
80049ac: 687b ldr r3, [r7, #4]
80049ae: 689b ldr r3, [r3, #8]
80049b0: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
80049b4: d007 beq.n 80049c6 <UART_Receive_IT+0x74>
80049b6: 687b ldr r3, [r7, #4]
80049b8: 689b ldr r3, [r3, #8]
80049ba: 2b00 cmp r3, #0
80049bc: d10a bne.n 80049d4 <UART_Receive_IT+0x82>
80049be: 687b ldr r3, [r7, #4]
80049c0: 691b ldr r3, [r3, #16]
80049c2: 2b00 cmp r3, #0
80049c4: d106 bne.n 80049d4 <UART_Receive_IT+0x82>
{
*pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
80049c6: 687b ldr r3, [r7, #4]
80049c8: 681b ldr r3, [r3, #0]
80049ca: 685b ldr r3, [r3, #4]
80049cc: b2da uxtb r2, r3
80049ce: 6afb ldr r3, [r7, #44] ; 0x2c
80049d0: 701a strb r2, [r3, #0]
80049d2: e008 b.n 80049e6 <UART_Receive_IT+0x94>
}
else
{
*pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
80049d4: 687b ldr r3, [r7, #4]
80049d6: 681b ldr r3, [r3, #0]
80049d8: 685b ldr r3, [r3, #4]
80049da: b2db uxtb r3, r3
80049dc: f003 037f and.w r3, r3, #127 ; 0x7f
80049e0: b2da uxtb r2, r3
80049e2: 6afb ldr r3, [r7, #44] ; 0x2c
80049e4: 701a strb r2, [r3, #0]
}
huart->pRxBuffPtr += 1U;
80049e6: 687b ldr r3, [r7, #4]
80049e8: 6a9b ldr r3, [r3, #40] ; 0x28
80049ea: 1c5a adds r2, r3, #1
80049ec: 687b ldr r3, [r7, #4]
80049ee: 629a str r2, [r3, #40] ; 0x28
}
if (--huart->RxXferCount == 0U)
80049f0: 687b ldr r3, [r7, #4]
80049f2: 8ddb ldrh r3, [r3, #46] ; 0x2e
80049f4: b29b uxth r3, r3
80049f6: 3b01 subs r3, #1
80049f8: b29b uxth r3, r3
80049fa: 687a ldr r2, [r7, #4]
80049fc: 4619 mov r1, r3
80049fe: 85d1 strh r1, [r2, #46] ; 0x2e
8004a00: 2b00 cmp r3, #0
8004a02: d15a bne.n 8004aba <UART_Receive_IT+0x168>
{
/* Disable the UART Data Register not empty Interrupt */
__HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
8004a04: 687b ldr r3, [r7, #4]
8004a06: 681b ldr r3, [r3, #0]
8004a08: 68da ldr r2, [r3, #12]
8004a0a: 687b ldr r3, [r7, #4]
8004a0c: 681b ldr r3, [r3, #0]
8004a0e: f022 0220 bic.w r2, r2, #32
8004a12: 60da str r2, [r3, #12]
/* Disable the UART Parity Error Interrupt */
__HAL_UART_DISABLE_IT(huart, UART_IT_PE);
8004a14: 687b ldr r3, [r7, #4]
8004a16: 681b ldr r3, [r3, #0]
8004a18: 68da ldr r2, [r3, #12]
8004a1a: 687b ldr r3, [r7, #4]
8004a1c: 681b ldr r3, [r3, #0]
8004a1e: f422 7280 bic.w r2, r2, #256 ; 0x100
8004a22: 60da str r2, [r3, #12]
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
__HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
8004a24: 687b ldr r3, [r7, #4]
8004a26: 681b ldr r3, [r3, #0]
8004a28: 695a ldr r2, [r3, #20]
8004a2a: 687b ldr r3, [r7, #4]
8004a2c: 681b ldr r3, [r3, #0]
8004a2e: f022 0201 bic.w r2, r2, #1
8004a32: 615a str r2, [r3, #20]
/* Rx process is completed, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8004a34: 687b ldr r3, [r7, #4]
8004a36: 2220 movs r2, #32
8004a38: f883 203e strb.w r2, [r3, #62] ; 0x3e
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
8004a3c: 687b ldr r3, [r7, #4]
8004a3e: 6b1b ldr r3, [r3, #48] ; 0x30
8004a40: 2b01 cmp r3, #1
8004a42: d135 bne.n 8004ab0 <UART_Receive_IT+0x15e>
{
/* Set reception type to Standard */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8004a44: 687b ldr r3, [r7, #4]
8004a46: 2200 movs r2, #0
8004a48: 631a str r2, [r3, #48] ; 0x30
/* Disable IDLE interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8004a4a: 687b ldr r3, [r7, #4]
8004a4c: 681b ldr r3, [r3, #0]
8004a4e: 330c adds r3, #12
8004a50: 617b str r3, [r7, #20]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8004a52: 697b ldr r3, [r7, #20]
8004a54: e853 3f00 ldrex r3, [r3]
8004a58: 613b str r3, [r7, #16]
return(result);
8004a5a: 693b ldr r3, [r7, #16]
8004a5c: f023 0310 bic.w r3, r3, #16
8004a60: 627b str r3, [r7, #36] ; 0x24
8004a62: 687b ldr r3, [r7, #4]
8004a64: 681b ldr r3, [r3, #0]
8004a66: 330c adds r3, #12
8004a68: 6a7a ldr r2, [r7, #36] ; 0x24
8004a6a: 623a str r2, [r7, #32]
8004a6c: 61fb str r3, [r7, #28]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8004a6e: 69f9 ldr r1, [r7, #28]
8004a70: 6a3a ldr r2, [r7, #32]
8004a72: e841 2300 strex r3, r2, [r1]
8004a76: 61bb str r3, [r7, #24]
return(result);
8004a78: 69bb ldr r3, [r7, #24]
8004a7a: 2b00 cmp r3, #0
8004a7c: d1e5 bne.n 8004a4a <UART_Receive_IT+0xf8>
/* Check if IDLE flag is set */
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE))
8004a7e: 687b ldr r3, [r7, #4]
8004a80: 681b ldr r3, [r3, #0]
8004a82: 681b ldr r3, [r3, #0]
8004a84: f003 0310 and.w r3, r3, #16
8004a88: 2b10 cmp r3, #16
8004a8a: d10a bne.n 8004aa2 <UART_Receive_IT+0x150>
{
/* Clear IDLE flag in ISR */
__HAL_UART_CLEAR_IDLEFLAG(huart);
8004a8c: 2300 movs r3, #0
8004a8e: 60fb str r3, [r7, #12]
8004a90: 687b ldr r3, [r7, #4]
8004a92: 681b ldr r3, [r3, #0]
8004a94: 681b ldr r3, [r3, #0]
8004a96: 60fb str r3, [r7, #12]
8004a98: 687b ldr r3, [r7, #4]
8004a9a: 681b ldr r3, [r3, #0]
8004a9c: 685b ldr r3, [r3, #4]
8004a9e: 60fb str r3, [r7, #12]
8004aa0: 68fb ldr r3, [r7, #12]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
8004aa2: 687b ldr r3, [r7, #4]
8004aa4: 8d9b ldrh r3, [r3, #44] ; 0x2c
8004aa6: 4619 mov r1, r3
8004aa8: 6878 ldr r0, [r7, #4]
8004aaa: f7ff fdbf bl 800462c <HAL_UARTEx_RxEventCallback>
8004aae: e002 b.n 8004ab6 <UART_Receive_IT+0x164>
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx complete callback*/
huart->RxCpltCallback(huart);
#else
/*Call legacy weak Rx complete callback*/
HAL_UART_RxCpltCallback(huart);
8004ab0: 6878 ldr r0, [r7, #4]
8004ab2: f7fc fb8b bl 80011cc <HAL_UART_RxCpltCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
return HAL_OK;
8004ab6: 2300 movs r3, #0
8004ab8: e002 b.n 8004ac0 <UART_Receive_IT+0x16e>
}
return HAL_OK;
8004aba: 2300 movs r3, #0
8004abc: e000 b.n 8004ac0 <UART_Receive_IT+0x16e>
}
else
{
return HAL_BUSY;
8004abe: 2302 movs r3, #2
}
}
8004ac0: 4618 mov r0, r3
8004ac2: 3730 adds r7, #48 ; 0x30
8004ac4: 46bd mov sp, r7
8004ac6: bd80 pop {r7, pc}
08004ac8 <UART_SetConfig>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
static void UART_SetConfig(UART_HandleTypeDef *huart)
{
8004ac8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
8004acc: b09f sub sp, #124 ; 0x7c
8004ace: af00 add r7, sp, #0
8004ad0: 66f8 str r0, [r7, #108] ; 0x6c
assert_param(IS_UART_MODE(huart->Init.Mode));
/*-------------------------- USART CR2 Configuration -----------------------*/
/* Configure the UART Stop Bits: Set STOP[13:12] bits
according to huart->Init.StopBits value */
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
8004ad2: 6efb ldr r3, [r7, #108] ; 0x6c
8004ad4: 681b ldr r3, [r3, #0]
8004ad6: 691b ldr r3, [r3, #16]
8004ad8: f423 5040 bic.w r0, r3, #12288 ; 0x3000
8004adc: 6efb ldr r3, [r7, #108] ; 0x6c
8004ade: 68d9 ldr r1, [r3, #12]
8004ae0: 6efb ldr r3, [r7, #108] ; 0x6c
8004ae2: 681a ldr r2, [r3, #0]
8004ae4: ea40 0301 orr.w r3, r0, r1
8004ae8: 6113 str r3, [r2, #16]
Set the M bits according to huart->Init.WordLength value
Set PCE and PS bits according to huart->Init.Parity value
Set TE and RE bits according to huart->Init.Mode value
Set OVER8 bit according to huart->Init.OverSampling value */
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
8004aea: 6efb ldr r3, [r7, #108] ; 0x6c
8004aec: 689a ldr r2, [r3, #8]
8004aee: 6efb ldr r3, [r7, #108] ; 0x6c
8004af0: 691b ldr r3, [r3, #16]
8004af2: 431a orrs r2, r3
8004af4: 6efb ldr r3, [r7, #108] ; 0x6c
8004af6: 695b ldr r3, [r3, #20]
8004af8: 431a orrs r2, r3
8004afa: 6efb ldr r3, [r7, #108] ; 0x6c
8004afc: 69db ldr r3, [r3, #28]
8004afe: 4313 orrs r3, r2
8004b00: 673b str r3, [r7, #112] ; 0x70
MODIFY_REG(huart->Instance->CR1,
8004b02: 6efb ldr r3, [r7, #108] ; 0x6c
8004b04: 681b ldr r3, [r3, #0]
8004b06: 68db ldr r3, [r3, #12]
8004b08: f423 4116 bic.w r1, r3, #38400 ; 0x9600
8004b0c: f021 010c bic.w r1, r1, #12
8004b10: 6efb ldr r3, [r7, #108] ; 0x6c
8004b12: 681a ldr r2, [r3, #0]
8004b14: 6f3b ldr r3, [r7, #112] ; 0x70
8004b16: 430b orrs r3, r1
8004b18: 60d3 str r3, [r2, #12]
(uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
tmpreg);
/*-------------------------- USART CR3 Configuration -----------------------*/
/* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
8004b1a: 6efb ldr r3, [r7, #108] ; 0x6c
8004b1c: 681b ldr r3, [r3, #0]
8004b1e: 695b ldr r3, [r3, #20]
8004b20: f423 7040 bic.w r0, r3, #768 ; 0x300
8004b24: 6efb ldr r3, [r7, #108] ; 0x6c
8004b26: 6999 ldr r1, [r3, #24]
8004b28: 6efb ldr r3, [r7, #108] ; 0x6c
8004b2a: 681a ldr r2, [r3, #0]
8004b2c: ea40 0301 orr.w r3, r0, r1
8004b30: 6153 str r3, [r2, #20]
if ((huart->Instance == USART1) || (huart->Instance == USART6) || (huart->Instance == UART9) || (huart->Instance == UART10))
{
pclk = HAL_RCC_GetPCLK2Freq();
}
#elif defined(USART6)
if ((huart->Instance == USART1) || (huart->Instance == USART6))
8004b32: 6efb ldr r3, [r7, #108] ; 0x6c
8004b34: 681a ldr r2, [r3, #0]
8004b36: 4bc5 ldr r3, [pc, #788] ; (8004e4c <UART_SetConfig+0x384>)
8004b38: 429a cmp r2, r3
8004b3a: d004 beq.n 8004b46 <UART_SetConfig+0x7e>
8004b3c: 6efb ldr r3, [r7, #108] ; 0x6c
8004b3e: 681a ldr r2, [r3, #0]
8004b40: 4bc3 ldr r3, [pc, #780] ; (8004e50 <UART_SetConfig+0x388>)
8004b42: 429a cmp r2, r3
8004b44: d103 bne.n 8004b4e <UART_SetConfig+0x86>
{
pclk = HAL_RCC_GetPCLK2Freq();
8004b46: f7fe fe85 bl 8003854 <HAL_RCC_GetPCLK2Freq>
8004b4a: 6778 str r0, [r7, #116] ; 0x74
8004b4c: e002 b.n 8004b54 <UART_SetConfig+0x8c>
pclk = HAL_RCC_GetPCLK2Freq();
}
#endif /* USART6 */
else
{
pclk = HAL_RCC_GetPCLK1Freq();
8004b4e: f7fe fe6d bl 800382c <HAL_RCC_GetPCLK1Freq>
8004b52: 6778 str r0, [r7, #116] ; 0x74
}
/*-------------------------- USART BRR Configuration ---------------------*/
if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
8004b54: 6efb ldr r3, [r7, #108] ; 0x6c
8004b56: 69db ldr r3, [r3, #28]
8004b58: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
8004b5c: f040 80b6 bne.w 8004ccc <UART_SetConfig+0x204>
{
huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);
8004b60: 6f7b ldr r3, [r7, #116] ; 0x74
8004b62: 461c mov r4, r3
8004b64: f04f 0500 mov.w r5, #0
8004b68: 4622 mov r2, r4
8004b6a: 462b mov r3, r5
8004b6c: 1891 adds r1, r2, r2
8004b6e: 6439 str r1, [r7, #64] ; 0x40
8004b70: 415b adcs r3, r3
8004b72: 647b str r3, [r7, #68] ; 0x44
8004b74: e9d7 2310 ldrd r2, r3, [r7, #64] ; 0x40
8004b78: 1912 adds r2, r2, r4
8004b7a: eb45 0303 adc.w r3, r5, r3
8004b7e: f04f 0000 mov.w r0, #0
8004b82: f04f 0100 mov.w r1, #0
8004b86: 00d9 lsls r1, r3, #3
8004b88: ea41 7152 orr.w r1, r1, r2, lsr #29
8004b8c: 00d0 lsls r0, r2, #3
8004b8e: 4602 mov r2, r0
8004b90: 460b mov r3, r1
8004b92: 1911 adds r1, r2, r4
8004b94: 6639 str r1, [r7, #96] ; 0x60
8004b96: 416b adcs r3, r5
8004b98: 667b str r3, [r7, #100] ; 0x64
8004b9a: 6efb ldr r3, [r7, #108] ; 0x6c
8004b9c: 685b ldr r3, [r3, #4]
8004b9e: 461a mov r2, r3
8004ba0: f04f 0300 mov.w r3, #0
8004ba4: 1891 adds r1, r2, r2
8004ba6: 63b9 str r1, [r7, #56] ; 0x38
8004ba8: 415b adcs r3, r3
8004baa: 63fb str r3, [r7, #60] ; 0x3c
8004bac: e9d7 230e ldrd r2, r3, [r7, #56] ; 0x38
8004bb0: e9d7 0118 ldrd r0, r1, [r7, #96] ; 0x60
8004bb4: f7fb fb26 bl 8000204 <__aeabi_uldivmod>
8004bb8: 4602 mov r2, r0
8004bba: 460b mov r3, r1
8004bbc: 4ba5 ldr r3, [pc, #660] ; (8004e54 <UART_SetConfig+0x38c>)
8004bbe: fba3 2302 umull r2, r3, r3, r2
8004bc2: 095b lsrs r3, r3, #5
8004bc4: 011e lsls r6, r3, #4
8004bc6: 6f7b ldr r3, [r7, #116] ; 0x74
8004bc8: 461c mov r4, r3
8004bca: f04f 0500 mov.w r5, #0
8004bce: 4622 mov r2, r4
8004bd0: 462b mov r3, r5
8004bd2: 1891 adds r1, r2, r2
8004bd4: 6339 str r1, [r7, #48] ; 0x30
8004bd6: 415b adcs r3, r3
8004bd8: 637b str r3, [r7, #52] ; 0x34
8004bda: e9d7 230c ldrd r2, r3, [r7, #48] ; 0x30
8004bde: 1912 adds r2, r2, r4
8004be0: eb45 0303 adc.w r3, r5, r3
8004be4: f04f 0000 mov.w r0, #0
8004be8: f04f 0100 mov.w r1, #0
8004bec: 00d9 lsls r1, r3, #3
8004bee: ea41 7152 orr.w r1, r1, r2, lsr #29
8004bf2: 00d0 lsls r0, r2, #3
8004bf4: 4602 mov r2, r0
8004bf6: 460b mov r3, r1
8004bf8: 1911 adds r1, r2, r4
8004bfa: 65b9 str r1, [r7, #88] ; 0x58
8004bfc: 416b adcs r3, r5
8004bfe: 65fb str r3, [r7, #92] ; 0x5c
8004c00: 6efb ldr r3, [r7, #108] ; 0x6c
8004c02: 685b ldr r3, [r3, #4]
8004c04: 461a mov r2, r3
8004c06: f04f 0300 mov.w r3, #0
8004c0a: 1891 adds r1, r2, r2
8004c0c: 62b9 str r1, [r7, #40] ; 0x28
8004c0e: 415b adcs r3, r3
8004c10: 62fb str r3, [r7, #44] ; 0x2c
8004c12: e9d7 230a ldrd r2, r3, [r7, #40] ; 0x28
8004c16: e9d7 0116 ldrd r0, r1, [r7, #88] ; 0x58
8004c1a: f7fb faf3 bl 8000204 <__aeabi_uldivmod>
8004c1e: 4602 mov r2, r0
8004c20: 460b mov r3, r1
8004c22: 4b8c ldr r3, [pc, #560] ; (8004e54 <UART_SetConfig+0x38c>)
8004c24: fba3 1302 umull r1, r3, r3, r2
8004c28: 095b lsrs r3, r3, #5
8004c2a: 2164 movs r1, #100 ; 0x64
8004c2c: fb01 f303 mul.w r3, r1, r3
8004c30: 1ad3 subs r3, r2, r3
8004c32: 00db lsls r3, r3, #3
8004c34: 3332 adds r3, #50 ; 0x32
8004c36: 4a87 ldr r2, [pc, #540] ; (8004e54 <UART_SetConfig+0x38c>)
8004c38: fba2 2303 umull r2, r3, r2, r3
8004c3c: 095b lsrs r3, r3, #5
8004c3e: 005b lsls r3, r3, #1
8004c40: f403 73f8 and.w r3, r3, #496 ; 0x1f0
8004c44: 441e add r6, r3
8004c46: 6f7b ldr r3, [r7, #116] ; 0x74
8004c48: 4618 mov r0, r3
8004c4a: f04f 0100 mov.w r1, #0
8004c4e: 4602 mov r2, r0
8004c50: 460b mov r3, r1
8004c52: 1894 adds r4, r2, r2
8004c54: 623c str r4, [r7, #32]
8004c56: 415b adcs r3, r3
8004c58: 627b str r3, [r7, #36] ; 0x24
8004c5a: e9d7 2308 ldrd r2, r3, [r7, #32]
8004c5e: 1812 adds r2, r2, r0
8004c60: eb41 0303 adc.w r3, r1, r3
8004c64: f04f 0400 mov.w r4, #0
8004c68: f04f 0500 mov.w r5, #0
8004c6c: 00dd lsls r5, r3, #3
8004c6e: ea45 7552 orr.w r5, r5, r2, lsr #29
8004c72: 00d4 lsls r4, r2, #3
8004c74: 4622 mov r2, r4
8004c76: 462b mov r3, r5
8004c78: 1814 adds r4, r2, r0
8004c7a: 653c str r4, [r7, #80] ; 0x50
8004c7c: 414b adcs r3, r1
8004c7e: 657b str r3, [r7, #84] ; 0x54
8004c80: 6efb ldr r3, [r7, #108] ; 0x6c
8004c82: 685b ldr r3, [r3, #4]
8004c84: 461a mov r2, r3
8004c86: f04f 0300 mov.w r3, #0
8004c8a: 1891 adds r1, r2, r2
8004c8c: 61b9 str r1, [r7, #24]
8004c8e: 415b adcs r3, r3
8004c90: 61fb str r3, [r7, #28]
8004c92: e9d7 2306 ldrd r2, r3, [r7, #24]
8004c96: e9d7 0114 ldrd r0, r1, [r7, #80] ; 0x50
8004c9a: f7fb fab3 bl 8000204 <__aeabi_uldivmod>
8004c9e: 4602 mov r2, r0
8004ca0: 460b mov r3, r1
8004ca2: 4b6c ldr r3, [pc, #432] ; (8004e54 <UART_SetConfig+0x38c>)
8004ca4: fba3 1302 umull r1, r3, r3, r2
8004ca8: 095b lsrs r3, r3, #5
8004caa: 2164 movs r1, #100 ; 0x64
8004cac: fb01 f303 mul.w r3, r1, r3
8004cb0: 1ad3 subs r3, r2, r3
8004cb2: 00db lsls r3, r3, #3
8004cb4: 3332 adds r3, #50 ; 0x32
8004cb6: 4a67 ldr r2, [pc, #412] ; (8004e54 <UART_SetConfig+0x38c>)
8004cb8: fba2 2303 umull r2, r3, r2, r3
8004cbc: 095b lsrs r3, r3, #5
8004cbe: f003 0207 and.w r2, r3, #7
8004cc2: 6efb ldr r3, [r7, #108] ; 0x6c
8004cc4: 681b ldr r3, [r3, #0]
8004cc6: 4432 add r2, r6
8004cc8: 609a str r2, [r3, #8]
}
else
{
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
}
}
8004cca: e0b9 b.n 8004e40 <UART_SetConfig+0x378>
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
8004ccc: 6f7b ldr r3, [r7, #116] ; 0x74
8004cce: 461c mov r4, r3
8004cd0: f04f 0500 mov.w r5, #0
8004cd4: 4622 mov r2, r4
8004cd6: 462b mov r3, r5
8004cd8: 1891 adds r1, r2, r2
8004cda: 6139 str r1, [r7, #16]
8004cdc: 415b adcs r3, r3
8004cde: 617b str r3, [r7, #20]
8004ce0: e9d7 2304 ldrd r2, r3, [r7, #16]
8004ce4: 1912 adds r2, r2, r4
8004ce6: eb45 0303 adc.w r3, r5, r3
8004cea: f04f 0000 mov.w r0, #0
8004cee: f04f 0100 mov.w r1, #0
8004cf2: 00d9 lsls r1, r3, #3
8004cf4: ea41 7152 orr.w r1, r1, r2, lsr #29
8004cf8: 00d0 lsls r0, r2, #3
8004cfa: 4602 mov r2, r0
8004cfc: 460b mov r3, r1
8004cfe: eb12 0804 adds.w r8, r2, r4
8004d02: eb43 0905 adc.w r9, r3, r5
8004d06: 6efb ldr r3, [r7, #108] ; 0x6c
8004d08: 685b ldr r3, [r3, #4]
8004d0a: 4618 mov r0, r3
8004d0c: f04f 0100 mov.w r1, #0
8004d10: f04f 0200 mov.w r2, #0
8004d14: f04f 0300 mov.w r3, #0
8004d18: 008b lsls r3, r1, #2
8004d1a: ea43 7390 orr.w r3, r3, r0, lsr #30
8004d1e: 0082 lsls r2, r0, #2
8004d20: 4640 mov r0, r8
8004d22: 4649 mov r1, r9
8004d24: f7fb fa6e bl 8000204 <__aeabi_uldivmod>
8004d28: 4602 mov r2, r0
8004d2a: 460b mov r3, r1
8004d2c: 4b49 ldr r3, [pc, #292] ; (8004e54 <UART_SetConfig+0x38c>)
8004d2e: fba3 2302 umull r2, r3, r3, r2
8004d32: 095b lsrs r3, r3, #5
8004d34: 011e lsls r6, r3, #4
8004d36: 6f7b ldr r3, [r7, #116] ; 0x74
8004d38: 4618 mov r0, r3
8004d3a: f04f 0100 mov.w r1, #0
8004d3e: 4602 mov r2, r0
8004d40: 460b mov r3, r1
8004d42: 1894 adds r4, r2, r2
8004d44: 60bc str r4, [r7, #8]
8004d46: 415b adcs r3, r3
8004d48: 60fb str r3, [r7, #12]
8004d4a: e9d7 2302 ldrd r2, r3, [r7, #8]
8004d4e: 1812 adds r2, r2, r0
8004d50: eb41 0303 adc.w r3, r1, r3
8004d54: f04f 0400 mov.w r4, #0
8004d58: f04f 0500 mov.w r5, #0
8004d5c: 00dd lsls r5, r3, #3
8004d5e: ea45 7552 orr.w r5, r5, r2, lsr #29
8004d62: 00d4 lsls r4, r2, #3
8004d64: 4622 mov r2, r4
8004d66: 462b mov r3, r5
8004d68: 1814 adds r4, r2, r0
8004d6a: 64bc str r4, [r7, #72] ; 0x48
8004d6c: 414b adcs r3, r1
8004d6e: 64fb str r3, [r7, #76] ; 0x4c
8004d70: 6efb ldr r3, [r7, #108] ; 0x6c
8004d72: 685b ldr r3, [r3, #4]
8004d74: 4618 mov r0, r3
8004d76: f04f 0100 mov.w r1, #0
8004d7a: f04f 0200 mov.w r2, #0
8004d7e: f04f 0300 mov.w r3, #0
8004d82: 008b lsls r3, r1, #2
8004d84: ea43 7390 orr.w r3, r3, r0, lsr #30
8004d88: 0082 lsls r2, r0, #2
8004d8a: e9d7 0112 ldrd r0, r1, [r7, #72] ; 0x48
8004d8e: f7fb fa39 bl 8000204 <__aeabi_uldivmod>
8004d92: 4602 mov r2, r0
8004d94: 460b mov r3, r1
8004d96: 4b2f ldr r3, [pc, #188] ; (8004e54 <UART_SetConfig+0x38c>)
8004d98: fba3 1302 umull r1, r3, r3, r2
8004d9c: 095b lsrs r3, r3, #5
8004d9e: 2164 movs r1, #100 ; 0x64
8004da0: fb01 f303 mul.w r3, r1, r3
8004da4: 1ad3 subs r3, r2, r3
8004da6: 011b lsls r3, r3, #4
8004da8: 3332 adds r3, #50 ; 0x32
8004daa: 4a2a ldr r2, [pc, #168] ; (8004e54 <UART_SetConfig+0x38c>)
8004dac: fba2 2303 umull r2, r3, r2, r3
8004db0: 095b lsrs r3, r3, #5
8004db2: f003 03f0 and.w r3, r3, #240 ; 0xf0
8004db6: 441e add r6, r3
8004db8: 6f7b ldr r3, [r7, #116] ; 0x74
8004dba: 4618 mov r0, r3
8004dbc: f04f 0100 mov.w r1, #0
8004dc0: 4602 mov r2, r0
8004dc2: 460b mov r3, r1
8004dc4: 1894 adds r4, r2, r2
8004dc6: 603c str r4, [r7, #0]
8004dc8: 415b adcs r3, r3
8004dca: 607b str r3, [r7, #4]
8004dcc: e9d7 2300 ldrd r2, r3, [r7]
8004dd0: 1812 adds r2, r2, r0
8004dd2: eb41 0303 adc.w r3, r1, r3
8004dd6: f04f 0400 mov.w r4, #0
8004dda: f04f 0500 mov.w r5, #0
8004dde: 00dd lsls r5, r3, #3
8004de0: ea45 7552 orr.w r5, r5, r2, lsr #29
8004de4: 00d4 lsls r4, r2, #3
8004de6: 4622 mov r2, r4
8004de8: 462b mov r3, r5
8004dea: eb12 0a00 adds.w sl, r2, r0
8004dee: eb43 0b01 adc.w fp, r3, r1
8004df2: 6efb ldr r3, [r7, #108] ; 0x6c
8004df4: 685b ldr r3, [r3, #4]
8004df6: 4618 mov r0, r3
8004df8: f04f 0100 mov.w r1, #0
8004dfc: f04f 0200 mov.w r2, #0
8004e00: f04f 0300 mov.w r3, #0
8004e04: 008b lsls r3, r1, #2
8004e06: ea43 7390 orr.w r3, r3, r0, lsr #30
8004e0a: 0082 lsls r2, r0, #2
8004e0c: 4650 mov r0, sl
8004e0e: 4659 mov r1, fp
8004e10: f7fb f9f8 bl 8000204 <__aeabi_uldivmod>
8004e14: 4602 mov r2, r0
8004e16: 460b mov r3, r1
8004e18: 4b0e ldr r3, [pc, #56] ; (8004e54 <UART_SetConfig+0x38c>)
8004e1a: fba3 1302 umull r1, r3, r3, r2
8004e1e: 095b lsrs r3, r3, #5
8004e20: 2164 movs r1, #100 ; 0x64
8004e22: fb01 f303 mul.w r3, r1, r3
8004e26: 1ad3 subs r3, r2, r3
8004e28: 011b lsls r3, r3, #4
8004e2a: 3332 adds r3, #50 ; 0x32
8004e2c: 4a09 ldr r2, [pc, #36] ; (8004e54 <UART_SetConfig+0x38c>)
8004e2e: fba2 2303 umull r2, r3, r2, r3
8004e32: 095b lsrs r3, r3, #5
8004e34: f003 020f and.w r2, r3, #15
8004e38: 6efb ldr r3, [r7, #108] ; 0x6c
8004e3a: 681b ldr r3, [r3, #0]
8004e3c: 4432 add r2, r6
8004e3e: 609a str r2, [r3, #8]
}
8004e40: bf00 nop
8004e42: 377c adds r7, #124 ; 0x7c
8004e44: 46bd mov sp, r7
8004e46: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
8004e4a: bf00 nop
8004e4c: 40011000 .word 0x40011000
8004e50: 40011400 .word 0x40011400
8004e54: 51eb851f .word 0x51eb851f
08004e58 <calloc>:
8004e58: 4b02 ldr r3, [pc, #8] ; (8004e64 <calloc+0xc>)
8004e5a: 460a mov r2, r1
8004e5c: 4601 mov r1, r0
8004e5e: 6818 ldr r0, [r3, #0]
8004e60: f000 b858 b.w 8004f14 <_calloc_r>
8004e64: 20000010 .word 0x20000010
08004e68 <__errno>:
8004e68: 4b01 ldr r3, [pc, #4] ; (8004e70 <__errno+0x8>)
8004e6a: 6818 ldr r0, [r3, #0]
8004e6c: 4770 bx lr
8004e6e: bf00 nop
8004e70: 20000010 .word 0x20000010
08004e74 <__libc_init_array>:
8004e74: b570 push {r4, r5, r6, lr}
8004e76: 4d0d ldr r5, [pc, #52] ; (8004eac <__libc_init_array+0x38>)
8004e78: 4c0d ldr r4, [pc, #52] ; (8004eb0 <__libc_init_array+0x3c>)
8004e7a: 1b64 subs r4, r4, r5
8004e7c: 10a4 asrs r4, r4, #2
8004e7e: 2600 movs r6, #0
8004e80: 42a6 cmp r6, r4
8004e82: d109 bne.n 8004e98 <__libc_init_array+0x24>
8004e84: 4d0b ldr r5, [pc, #44] ; (8004eb4 <__libc_init_array+0x40>)
8004e86: 4c0c ldr r4, [pc, #48] ; (8004eb8 <__libc_init_array+0x44>)
8004e88: f000 f91c bl 80050c4 <_init>
8004e8c: 1b64 subs r4, r4, r5
8004e8e: 10a4 asrs r4, r4, #2
8004e90: 2600 movs r6, #0
8004e92: 42a6 cmp r6, r4
8004e94: d105 bne.n 8004ea2 <__libc_init_array+0x2e>
8004e96: bd70 pop {r4, r5, r6, pc}
8004e98: f855 3b04 ldr.w r3, [r5], #4
8004e9c: 4798 blx r3
8004e9e: 3601 adds r6, #1
8004ea0: e7ee b.n 8004e80 <__libc_init_array+0xc>
8004ea2: f855 3b04 ldr.w r3, [r5], #4
8004ea6: 4798 blx r3
8004ea8: 3601 adds r6, #1
8004eaa: e7f2 b.n 8004e92 <__libc_init_array+0x1e>
8004eac: 08005308 .word 0x08005308
8004eb0: 08005308 .word 0x08005308
8004eb4: 08005308 .word 0x08005308
8004eb8: 0800530c .word 0x0800530c
08004ebc <free>:
8004ebc: 4b02 ldr r3, [pc, #8] ; (8004ec8 <free+0xc>)
8004ebe: 4601 mov r1, r0
8004ec0: 6818 ldr r0, [r3, #0]
8004ec2: f000 b837 b.w 8004f34 <_free_r>
8004ec6: bf00 nop
8004ec8: 20000010 .word 0x20000010
08004ecc <memcmp>:
8004ecc: b530 push {r4, r5, lr}
8004ece: 3901 subs r1, #1
8004ed0: 2400 movs r4, #0
8004ed2: 42a2 cmp r2, r4
8004ed4: d101 bne.n 8004eda <memcmp+0xe>
8004ed6: 2000 movs r0, #0
8004ed8: e005 b.n 8004ee6 <memcmp+0x1a>
8004eda: 5d03 ldrb r3, [r0, r4]
8004edc: 3401 adds r4, #1
8004ede: 5d0d ldrb r5, [r1, r4]
8004ee0: 42ab cmp r3, r5
8004ee2: d0f6 beq.n 8004ed2 <memcmp+0x6>
8004ee4: 1b58 subs r0, r3, r5
8004ee6: bd30 pop {r4, r5, pc}
08004ee8 <memcpy>:
8004ee8: 440a add r2, r1
8004eea: 4291 cmp r1, r2
8004eec: f100 33ff add.w r3, r0, #4294967295
8004ef0: d100 bne.n 8004ef4 <memcpy+0xc>
8004ef2: 4770 bx lr
8004ef4: b510 push {r4, lr}
8004ef6: f811 4b01 ldrb.w r4, [r1], #1
8004efa: f803 4f01 strb.w r4, [r3, #1]!
8004efe: 4291 cmp r1, r2
8004f00: d1f9 bne.n 8004ef6 <memcpy+0xe>
8004f02: bd10 pop {r4, pc}
08004f04 <memset>:
8004f04: 4402 add r2, r0
8004f06: 4603 mov r3, r0
8004f08: 4293 cmp r3, r2
8004f0a: d100 bne.n 8004f0e <memset+0xa>
8004f0c: 4770 bx lr
8004f0e: f803 1b01 strb.w r1, [r3], #1
8004f12: e7f9 b.n 8004f08 <memset+0x4>
08004f14 <_calloc_r>:
8004f14: b513 push {r0, r1, r4, lr}
8004f16: 434a muls r2, r1
8004f18: 4611 mov r1, r2
8004f1a: 9201 str r2, [sp, #4]
8004f1c: f000 f85a bl 8004fd4 <_malloc_r>
8004f20: 4604 mov r4, r0
8004f22: b118 cbz r0, 8004f2c <_calloc_r+0x18>
8004f24: 9a01 ldr r2, [sp, #4]
8004f26: 2100 movs r1, #0
8004f28: f7ff ffec bl 8004f04 <memset>
8004f2c: 4620 mov r0, r4
8004f2e: b002 add sp, #8
8004f30: bd10 pop {r4, pc}
...
08004f34 <_free_r>:
8004f34: b537 push {r0, r1, r2, r4, r5, lr}
8004f36: 2900 cmp r1, #0
8004f38: d048 beq.n 8004fcc <_free_r+0x98>
8004f3a: f851 3c04 ldr.w r3, [r1, #-4]
8004f3e: 9001 str r0, [sp, #4]
8004f40: 2b00 cmp r3, #0
8004f42: f1a1 0404 sub.w r4, r1, #4
8004f46: bfb8 it lt
8004f48: 18e4 addlt r4, r4, r3
8004f4a: f000 f8ad bl 80050a8 <__malloc_lock>
8004f4e: 4a20 ldr r2, [pc, #128] ; (8004fd0 <_free_r+0x9c>)
8004f50: 9801 ldr r0, [sp, #4]
8004f52: 6813 ldr r3, [r2, #0]
8004f54: 4615 mov r5, r2
8004f56: b933 cbnz r3, 8004f66 <_free_r+0x32>
8004f58: 6063 str r3, [r4, #4]
8004f5a: 6014 str r4, [r2, #0]
8004f5c: b003 add sp, #12
8004f5e: e8bd 4030 ldmia.w sp!, {r4, r5, lr}
8004f62: f000 b8a7 b.w 80050b4 <__malloc_unlock>
8004f66: 42a3 cmp r3, r4
8004f68: d90b bls.n 8004f82 <_free_r+0x4e>
8004f6a: 6821 ldr r1, [r4, #0]
8004f6c: 1862 adds r2, r4, r1
8004f6e: 4293 cmp r3, r2
8004f70: bf04 itt eq
8004f72: 681a ldreq r2, [r3, #0]
8004f74: 685b ldreq r3, [r3, #4]
8004f76: 6063 str r3, [r4, #4]
8004f78: bf04 itt eq
8004f7a: 1852 addeq r2, r2, r1
8004f7c: 6022 streq r2, [r4, #0]
8004f7e: 602c str r4, [r5, #0]
8004f80: e7ec b.n 8004f5c <_free_r+0x28>
8004f82: 461a mov r2, r3
8004f84: 685b ldr r3, [r3, #4]
8004f86: b10b cbz r3, 8004f8c <_free_r+0x58>
8004f88: 42a3 cmp r3, r4
8004f8a: d9fa bls.n 8004f82 <_free_r+0x4e>
8004f8c: 6811 ldr r1, [r2, #0]
8004f8e: 1855 adds r5, r2, r1
8004f90: 42a5 cmp r5, r4
8004f92: d10b bne.n 8004fac <_free_r+0x78>
8004f94: 6824 ldr r4, [r4, #0]
8004f96: 4421 add r1, r4
8004f98: 1854 adds r4, r2, r1
8004f9a: 42a3 cmp r3, r4
8004f9c: 6011 str r1, [r2, #0]
8004f9e: d1dd bne.n 8004f5c <_free_r+0x28>
8004fa0: 681c ldr r4, [r3, #0]
8004fa2: 685b ldr r3, [r3, #4]
8004fa4: 6053 str r3, [r2, #4]
8004fa6: 4421 add r1, r4
8004fa8: 6011 str r1, [r2, #0]
8004faa: e7d7 b.n 8004f5c <_free_r+0x28>
8004fac: d902 bls.n 8004fb4 <_free_r+0x80>
8004fae: 230c movs r3, #12
8004fb0: 6003 str r3, [r0, #0]
8004fb2: e7d3 b.n 8004f5c <_free_r+0x28>
8004fb4: 6825 ldr r5, [r4, #0]
8004fb6: 1961 adds r1, r4, r5
8004fb8: 428b cmp r3, r1
8004fba: bf04 itt eq
8004fbc: 6819 ldreq r1, [r3, #0]
8004fbe: 685b ldreq r3, [r3, #4]
8004fc0: 6063 str r3, [r4, #4]
8004fc2: bf04 itt eq
8004fc4: 1949 addeq r1, r1, r5
8004fc6: 6021 streq r1, [r4, #0]
8004fc8: 6054 str r4, [r2, #4]
8004fca: e7c7 b.n 8004f5c <_free_r+0x28>
8004fcc: b003 add sp, #12
8004fce: bd30 pop {r4, r5, pc}
8004fd0: 20000168 .word 0x20000168
08004fd4 <_malloc_r>:
8004fd4: b5f8 push {r3, r4, r5, r6, r7, lr}
8004fd6: 1ccd adds r5, r1, #3
8004fd8: f025 0503 bic.w r5, r5, #3
8004fdc: 3508 adds r5, #8
8004fde: 2d0c cmp r5, #12
8004fe0: bf38 it cc
8004fe2: 250c movcc r5, #12
8004fe4: 2d00 cmp r5, #0
8004fe6: 4606 mov r6, r0
8004fe8: db01 blt.n 8004fee <_malloc_r+0x1a>
8004fea: 42a9 cmp r1, r5
8004fec: d903 bls.n 8004ff6 <_malloc_r+0x22>
8004fee: 230c movs r3, #12
8004ff0: 6033 str r3, [r6, #0]
8004ff2: 2000 movs r0, #0
8004ff4: bdf8 pop {r3, r4, r5, r6, r7, pc}
8004ff6: f000 f857 bl 80050a8 <__malloc_lock>
8004ffa: 4921 ldr r1, [pc, #132] ; (8005080 <_malloc_r+0xac>)
8004ffc: 680a ldr r2, [r1, #0]
8004ffe: 4614 mov r4, r2
8005000: b99c cbnz r4, 800502a <_malloc_r+0x56>
8005002: 4f20 ldr r7, [pc, #128] ; (8005084 <_malloc_r+0xb0>)
8005004: 683b ldr r3, [r7, #0]
8005006: b923 cbnz r3, 8005012 <_malloc_r+0x3e>
8005008: 4621 mov r1, r4
800500a: 4630 mov r0, r6
800500c: f000 f83c bl 8005088 <_sbrk_r>
8005010: 6038 str r0, [r7, #0]
8005012: 4629 mov r1, r5
8005014: 4630 mov r0, r6
8005016: f000 f837 bl 8005088 <_sbrk_r>
800501a: 1c43 adds r3, r0, #1
800501c: d123 bne.n 8005066 <_malloc_r+0x92>
800501e: 230c movs r3, #12
8005020: 6033 str r3, [r6, #0]
8005022: 4630 mov r0, r6
8005024: f000 f846 bl 80050b4 <__malloc_unlock>
8005028: e7e3 b.n 8004ff2 <_malloc_r+0x1e>
800502a: 6823 ldr r3, [r4, #0]
800502c: 1b5b subs r3, r3, r5
800502e: d417 bmi.n 8005060 <_malloc_r+0x8c>
8005030: 2b0b cmp r3, #11
8005032: d903 bls.n 800503c <_malloc_r+0x68>
8005034: 6023 str r3, [r4, #0]
8005036: 441c add r4, r3
8005038: 6025 str r5, [r4, #0]
800503a: e004 b.n 8005046 <_malloc_r+0x72>
800503c: 6863 ldr r3, [r4, #4]
800503e: 42a2 cmp r2, r4
8005040: bf0c ite eq
8005042: 600b streq r3, [r1, #0]
8005044: 6053 strne r3, [r2, #4]
8005046: 4630 mov r0, r6
8005048: f000 f834 bl 80050b4 <__malloc_unlock>
800504c: f104 000b add.w r0, r4, #11
8005050: 1d23 adds r3, r4, #4
8005052: f020 0007 bic.w r0, r0, #7
8005056: 1ac2 subs r2, r0, r3
8005058: d0cc beq.n 8004ff4 <_malloc_r+0x20>
800505a: 1a1b subs r3, r3, r0
800505c: 50a3 str r3, [r4, r2]
800505e: e7c9 b.n 8004ff4 <_malloc_r+0x20>
8005060: 4622 mov r2, r4
8005062: 6864 ldr r4, [r4, #4]
8005064: e7cc b.n 8005000 <_malloc_r+0x2c>
8005066: 1cc4 adds r4, r0, #3
8005068: f024 0403 bic.w r4, r4, #3
800506c: 42a0 cmp r0, r4
800506e: d0e3 beq.n 8005038 <_malloc_r+0x64>
8005070: 1a21 subs r1, r4, r0
8005072: 4630 mov r0, r6
8005074: f000 f808 bl 8005088 <_sbrk_r>
8005078: 3001 adds r0, #1
800507a: d1dd bne.n 8005038 <_malloc_r+0x64>
800507c: e7cf b.n 800501e <_malloc_r+0x4a>
800507e: bf00 nop
8005080: 20000168 .word 0x20000168
8005084: 2000016c .word 0x2000016c
08005088 <_sbrk_r>:
8005088: b538 push {r3, r4, r5, lr}
800508a: 4d06 ldr r5, [pc, #24] ; (80050a4 <_sbrk_r+0x1c>)
800508c: 2300 movs r3, #0
800508e: 4604 mov r4, r0
8005090: 4608 mov r0, r1
8005092: 602b str r3, [r5, #0]
8005094: f7fc fe10 bl 8001cb8 <_sbrk>
8005098: 1c43 adds r3, r0, #1
800509a: d102 bne.n 80050a2 <_sbrk_r+0x1a>
800509c: 682b ldr r3, [r5, #0]
800509e: b103 cbz r3, 80050a2 <_sbrk_r+0x1a>
80050a0: 6023 str r3, [r4, #0]
80050a2: bd38 pop {r3, r4, r5, pc}
80050a4: 20000360 .word 0x20000360
080050a8 <__malloc_lock>:
80050a8: 4801 ldr r0, [pc, #4] ; (80050b0 <__malloc_lock+0x8>)
80050aa: f000 b809 b.w 80050c0 <__retarget_lock_acquire_recursive>
80050ae: bf00 nop
80050b0: 20000368 .word 0x20000368
080050b4 <__malloc_unlock>:
80050b4: 4801 ldr r0, [pc, #4] ; (80050bc <__malloc_unlock+0x8>)
80050b6: f000 b804 b.w 80050c2 <__retarget_lock_release_recursive>
80050ba: bf00 nop
80050bc: 20000368 .word 0x20000368
080050c0 <__retarget_lock_acquire_recursive>:
80050c0: 4770 bx lr
080050c2 <__retarget_lock_release_recursive>:
80050c2: 4770 bx lr
080050c4 <_init>:
80050c4: b5f8 push {r3, r4, r5, r6, r7, lr}
80050c6: bf00 nop
80050c8: bcf8 pop {r3, r4, r5, r6, r7}
80050ca: bc08 pop {r3}
80050cc: 469e mov lr, r3
80050ce: 4770 bx lr
080050d0 <_fini>:
80050d0: b5f8 push {r3, r4, r5, r6, r7, lr}
80050d2: bf00 nop
80050d4: bcf8 pop {r3, r4, r5, r6, r7}
80050d6: bc08 pop {r3}
80050d8: 469e mov lr, r3
80050da: 4770 bx lr
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