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ams-master/Software/build/debug/Master_FT25.lss
LeneMarquardt a1510c1a69 gerber and software test in main
2025-03-21 15:35:07 +01:00

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build/debug/Master_FT25.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 000002ac 08000000 08000000 00001000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00004af4 080002ac 080002ac 000012ac 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 0000005c 08004da0 08004da0 00005da0 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08004dfc 08004dfc 00006010 2**0
CONTENTS, READONLY
4 .ARM 00000000 08004dfc 08004dfc 00006010 2**0
CONTENTS, READONLY
5 .preinit_array 00000000 08004dfc 08004dfc 00006010 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 08004dfc 08004dfc 00005dfc 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
7 .fini_array 00000004 08004e00 08004e00 00005e00 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
8 .data 00000010 20000000 08004e04 00006000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 000002e8 20000010 08004e14 00006010 2**2
ALLOC
10 ._user_heap_stack 00000600 200002f8 08004e14 000062f8 2**0
ALLOC
11 .ARM.attributes 0000002e 00000000 00000000 00006010 2**0
CONTENTS, READONLY
12 .comment 00000039 00000000 00000000 0000603e 2**0
CONTENTS, READONLY
13 .debug_info 0001e5b9 00000000 00000000 00006077 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_abbrev 00002a77 00000000 00000000 00024630 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_aranges 00001410 00000000 00000000 000270a8 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_rnglists 000011f1 00000000 00000000 000284b8 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 000182df 00000000 00000000 000296a9 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 0000827b 00000000 00000000 00041988 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .debug_frame 0000341c 00000000 00000000 00049c04 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
20 .debug_loclists 0000ef9e 00000000 00000000 0004d020 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
21 .debug_line_str 00000047 00000000 00000000 0005bfbe 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
080002ac <__do_global_dtors_aux>:
80002ac: b510 push {r4, lr}
80002ae: 4c05 ldr r4, [pc, #20] @ (80002c4 <__do_global_dtors_aux+0x18>)
80002b0: 7823 ldrb r3, [r4, #0]
80002b2: b933 cbnz r3, 80002c2 <__do_global_dtors_aux+0x16>
80002b4: 4b04 ldr r3, [pc, #16] @ (80002c8 <__do_global_dtors_aux+0x1c>)
80002b6: b113 cbz r3, 80002be <__do_global_dtors_aux+0x12>
80002b8: 4804 ldr r0, [pc, #16] @ (80002cc <__do_global_dtors_aux+0x20>)
80002ba: f3af 8000 nop.w
80002be: 2301 movs r3, #1
80002c0: 7023 strb r3, [r4, #0]
80002c2: bd10 pop {r4, pc}
80002c4: 20000010 .word 0x20000010
80002c8: 00000000 .word 0x00000000
80002cc: 08004d88 .word 0x08004d88
080002d0 <frame_dummy>:
80002d0: b508 push {r3, lr}
80002d2: 4b03 ldr r3, [pc, #12] @ (80002e0 <frame_dummy+0x10>)
80002d4: b11b cbz r3, 80002de <frame_dummy+0xe>
80002d6: 4903 ldr r1, [pc, #12] @ (80002e4 <frame_dummy+0x14>)
80002d8: 4803 ldr r0, [pc, #12] @ (80002e8 <frame_dummy+0x18>)
80002da: f3af 8000 nop.w
80002de: bd08 pop {r3, pc}
80002e0: 00000000 .word 0x00000000
80002e4: 20000014 .word 0x20000014
80002e8: 08004d88 .word 0x08004d88
080002ec <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
80002ec: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr}
80002f0: b08b sub sp, #44 @ 0x2c
GPIO_InitTypeDef GPIO_InitStruct = {0};
80002f2: ad05 add r5, sp, #20
80002f4: 2400 movs r4, #0
80002f6: 9405 str r4, [sp, #20]
80002f8: 9406 str r4, [sp, #24]
80002fa: 9407 str r4, [sp, #28]
80002fc: 9408 str r4, [sp, #32]
80002fe: 9409 str r4, [sp, #36] @ 0x24
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOH_CLK_ENABLE();
8000300: 4b41 ldr r3, [pc, #260] @ (8000408 <MX_GPIO_Init+0x11c>)
8000302: f8d3 2140 ldr.w r2, [r3, #320] @ 0x140
8000306: f042 0280 orr.w r2, r2, #128 @ 0x80
800030a: f8c3 2140 str.w r2, [r3, #320] @ 0x140
800030e: f8d3 2140 ldr.w r2, [r3, #320] @ 0x140
8000312: f002 0280 and.w r2, r2, #128 @ 0x80
8000316: 9201 str r2, [sp, #4]
8000318: 9a01 ldr r2, [sp, #4]
__HAL_RCC_GPIOC_CLK_ENABLE();
800031a: f8d3 2140 ldr.w r2, [r3, #320] @ 0x140
800031e: f042 0204 orr.w r2, r2, #4
8000322: f8c3 2140 str.w r2, [r3, #320] @ 0x140
8000326: f8d3 2140 ldr.w r2, [r3, #320] @ 0x140
800032a: f002 0204 and.w r2, r2, #4
800032e: 9202 str r2, [sp, #8]
8000330: 9a02 ldr r2, [sp, #8]
__HAL_RCC_GPIOA_CLK_ENABLE();
8000332: f8d3 2140 ldr.w r2, [r3, #320] @ 0x140
8000336: f042 0201 orr.w r2, r2, #1
800033a: f8c3 2140 str.w r2, [r3, #320] @ 0x140
800033e: f8d3 2140 ldr.w r2, [r3, #320] @ 0x140
8000342: f002 0201 and.w r2, r2, #1
8000346: 9203 str r2, [sp, #12]
8000348: 9a03 ldr r2, [sp, #12]
__HAL_RCC_GPIOB_CLK_ENABLE();
800034a: f8d3 2140 ldr.w r2, [r3, #320] @ 0x140
800034e: f042 0202 orr.w r2, r2, #2
8000352: f8c3 2140 str.w r2, [r3, #320] @ 0x140
8000356: f8d3 3140 ldr.w r3, [r3, #320] @ 0x140
800035a: f003 0302 and.w r3, r3, #2
800035e: 9304 str r3, [sp, #16]
8000360: 9b04 ldr r3, [sp, #16]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOC, STATUS_LED_B_Pin|MSTR1_Pin|MSTR2_Pin|POS_AIR_CTRL_Pin
8000362: f8df 80ac ldr.w r8, [pc, #172] @ 8000410 <MX_GPIO_Init+0x124>
8000366: 4622 mov r2, r4
8000368: 21f4 movs r1, #244 @ 0xf4
800036a: 4640 mov r0, r8
800036c: f001 fc66 bl 8001c3c <HAL_GPIO_WritePin>
|NEG_AIR_CTRL_Pin, GPIO_PIN_RESET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOB, IMD_POWER_Pin|STATUS_LED_R_Pin, GPIO_PIN_RESET);
8000370: f8df 90a0 ldr.w r9, [pc, #160] @ 8000414 <MX_GPIO_Init+0x128>
8000374: 4622 mov r2, r4
8000376: f248 0104 movw r1, #32772 @ 0x8004
800037a: 4648 mov r0, r9
800037c: f001 fc5e bl 8001c3c <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOA, PRECHARGE_CTRL_Pin|AMS_NERROR_Pin|STATUS_LED_G_Pin, GPIO_PIN_RESET);
8000380: 4e22 ldr r6, [pc, #136] @ (800040c <MX_GPIO_Init+0x120>)
8000382: 4622 mov r2, r4
8000384: f44f 4109 mov.w r1, #35072 @ 0x8900
8000388: 4630 mov r0, r6
800038a: f001 fc57 bl 8001c3c <HAL_GPIO_WritePin>
/*Configure GPIO pins : STATUS_LED_B_Pin MSTR1_Pin MSTR2_Pin POS_AIR_CTRL_Pin
NEG_AIR_CTRL_Pin */
GPIO_InitStruct.Pin = STATUS_LED_B_Pin|MSTR1_Pin|MSTR2_Pin|POS_AIR_CTRL_Pin
800038e: 23f4 movs r3, #244 @ 0xf4
8000390: 9305 str r3, [sp, #20]
|NEG_AIR_CTRL_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000392: 2701 movs r7, #1
8000394: 9706 str r7, [sp, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000396: 9407 str r4, [sp, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000398: 9408 str r4, [sp, #32]
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
800039a: 4629 mov r1, r5
800039c: 4640 mov r0, r8
800039e: f001 fb3d bl 8001a1c <HAL_GPIO_Init>
/*Configure GPIO pins : TS_ERROR_Pin HV_ACTIVE_Pin IMD_OK_Pin NEG_AIR_CLOSED_Pin
POS_AIR_CLOSED_Pin INTR1_Pin WAKE1_Pin */
GPIO_InitStruct.Pin = TS_ERROR_Pin|HV_ACTIVE_Pin|IMD_OK_Pin|NEG_AIR_CLOSED_Pin
80003a2: f240 63cb movw r3, #1739 @ 0x6cb
80003a6: 9305 str r3, [sp, #20]
|POS_AIR_CLOSED_Pin|INTR1_Pin|WAKE1_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
80003a8: 9406 str r4, [sp, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80003aa: 9407 str r4, [sp, #28]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
80003ac: 4629 mov r1, r5
80003ae: 4630 mov r0, r6
80003b0: f001 fb34 bl 8001a1c <HAL_GPIO_Init>
/*Configure GPIO pins : PRE_and_AIR__open_Pin SDC_VOLTAGE_Pin IMD_ERROR_LED_Pin AMS_ERROR_LED_Pin
INTR2_Pin WAKE2_Pin */
GPIO_InitStruct.Pin = PRE_and_AIR__open_Pin|SDC_VOLTAGE_Pin|IMD_ERROR_LED_Pin|AMS_ERROR_LED_Pin
80003b4: f242 43c3 movw r3, #9411 @ 0x24c3
80003b8: 9305 str r3, [sp, #20]
|INTR2_Pin|WAKE2_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
80003ba: 9406 str r4, [sp, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80003bc: 9407 str r4, [sp, #28]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80003be: 4629 mov r1, r5
80003c0: 4648 mov r0, r9
80003c2: f001 fb2b bl 8001a1c <HAL_GPIO_Init>
/*Configure GPIO pins : IMD_POWER_Pin STATUS_LED_R_Pin */
GPIO_InitStruct.Pin = IMD_POWER_Pin|STATUS_LED_R_Pin;
80003c6: f248 0304 movw r3, #32772 @ 0x8004
80003ca: 9305 str r3, [sp, #20]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
80003cc: 9706 str r7, [sp, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80003ce: 9407 str r4, [sp, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80003d0: 9408 str r4, [sp, #32]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80003d2: 4629 mov r1, r5
80003d4: 4648 mov r0, r9
80003d6: f001 fb21 bl 8001a1c <HAL_GPIO_Init>
/*Configure GPIO pin : TSAL_GREEN_Pin */
GPIO_InitStruct.Pin = TSAL_GREEN_Pin;
80003da: f44f 7300 mov.w r3, #512 @ 0x200
80003de: 9305 str r3, [sp, #20]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
80003e0: 9406 str r4, [sp, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80003e2: 9407 str r4, [sp, #28]
HAL_GPIO_Init(TSAL_GREEN_GPIO_Port, &GPIO_InitStruct);
80003e4: 4629 mov r1, r5
80003e6: 4640 mov r0, r8
80003e8: f001 fb18 bl 8001a1c <HAL_GPIO_Init>
/*Configure GPIO pins : PRECHARGE_CTRL_Pin AMS_NERROR_Pin STATUS_LED_G_Pin */
GPIO_InitStruct.Pin = PRECHARGE_CTRL_Pin|AMS_NERROR_Pin|STATUS_LED_G_Pin;
80003ec: f44f 4309 mov.w r3, #35072 @ 0x8900
80003f0: 9305 str r3, [sp, #20]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
80003f2: 9706 str r7, [sp, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
80003f4: 9407 str r4, [sp, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
80003f6: 9408 str r4, [sp, #32]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
80003f8: 4629 mov r1, r5
80003fa: 4630 mov r0, r6
80003fc: f001 fb0e bl 8001a1c <HAL_GPIO_Init>
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
8000400: b00b add sp, #44 @ 0x2c
8000402: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc}
8000406: bf00 nop
8000408: 58024400 .word 0x58024400
800040c: 58020000 .word 0x58020000
8000410: 58020800 .word 0x58020800
8000414: 58020400 .word 0x58020400
08000418 <Error_Handler>:
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
8000418: b672 cpsid i
void Error_Handler(void)
{
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
800041a: e7fe b.n 800041a <Error_Handler+0x2>
0800041c <MX_FDCAN1_Init>:
{
800041c: b508 push {r3, lr}
hfdcan1.Instance = FDCAN1;
800041e: 4816 ldr r0, [pc, #88] @ (8000478 <MX_FDCAN1_Init+0x5c>)
8000420: 4b16 ldr r3, [pc, #88] @ (800047c <MX_FDCAN1_Init+0x60>)
8000422: 6003 str r3, [r0, #0]
hfdcan1.Init.FrameFormat = FDCAN_FRAME_CLASSIC;
8000424: 2300 movs r3, #0
8000426: 6083 str r3, [r0, #8]
hfdcan1.Init.Mode = FDCAN_MODE_NORMAL;
8000428: 60c3 str r3, [r0, #12]
hfdcan1.Init.AutoRetransmission = DISABLE;
800042a: 7403 strb r3, [r0, #16]
hfdcan1.Init.TransmitPause = DISABLE;
800042c: 7443 strb r3, [r0, #17]
hfdcan1.Init.ProtocolException = DISABLE;
800042e: 7483 strb r3, [r0, #18]
hfdcan1.Init.NominalPrescaler = 2;
8000430: 2202 movs r2, #2
8000432: 6142 str r2, [r0, #20]
hfdcan1.Init.NominalSyncJumpWidth = 1;
8000434: 2201 movs r2, #1
8000436: 6182 str r2, [r0, #24]
hfdcan1.Init.NominalTimeSeg1 = 31;
8000438: 211f movs r1, #31
800043a: 61c1 str r1, [r0, #28]
hfdcan1.Init.NominalTimeSeg2 = 8;
800043c: 2108 movs r1, #8
800043e: 6201 str r1, [r0, #32]
hfdcan1.Init.DataPrescaler = 1;
8000440: 6242 str r2, [r0, #36] @ 0x24
hfdcan1.Init.DataSyncJumpWidth = 1;
8000442: 6282 str r2, [r0, #40] @ 0x28
hfdcan1.Init.DataTimeSeg1 = 1;
8000444: 62c2 str r2, [r0, #44] @ 0x2c
hfdcan1.Init.DataTimeSeg2 = 1;
8000446: 6302 str r2, [r0, #48] @ 0x30
hfdcan1.Init.MessageRAMOffset = 0;
8000448: 6343 str r3, [r0, #52] @ 0x34
hfdcan1.Init.StdFiltersNbr = 32;
800044a: 2120 movs r1, #32
800044c: 6381 str r1, [r0, #56] @ 0x38
hfdcan1.Init.ExtFiltersNbr = 0;
800044e: 63c3 str r3, [r0, #60] @ 0x3c
hfdcan1.Init.RxFifo0ElmtsNbr = 16;
8000450: 2210 movs r2, #16
8000452: 6402 str r2, [r0, #64] @ 0x40
hfdcan1.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_8;
8000454: 2204 movs r2, #4
8000456: 6442 str r2, [r0, #68] @ 0x44
hfdcan1.Init.RxFifo1ElmtsNbr = 0;
8000458: 6483 str r3, [r0, #72] @ 0x48
hfdcan1.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_8;
800045a: 64c2 str r2, [r0, #76] @ 0x4c
hfdcan1.Init.RxBuffersNbr = 0;
800045c: 6503 str r3, [r0, #80] @ 0x50
hfdcan1.Init.RxBufferSize = FDCAN_DATA_BYTES_8;
800045e: 6542 str r2, [r0, #84] @ 0x54
hfdcan1.Init.TxEventsNbr = 0;
8000460: 6583 str r3, [r0, #88] @ 0x58
hfdcan1.Init.TxBuffersNbr = 0;
8000462: 65c3 str r3, [r0, #92] @ 0x5c
hfdcan1.Init.TxFifoQueueElmtsNbr = 32;
8000464: 6601 str r1, [r0, #96] @ 0x60
hfdcan1.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION;
8000466: 6643 str r3, [r0, #100] @ 0x64
hfdcan1.Init.TxElmtSize = FDCAN_DATA_BYTES_8;
8000468: 6682 str r2, [r0, #104] @ 0x68
if (HAL_FDCAN_Init(&hfdcan1) != HAL_OK)
800046a: f000 ffeb bl 8001444 <HAL_FDCAN_Init>
800046e: b900 cbnz r0, 8000472 <MX_FDCAN1_Init+0x56>
}
8000470: bd08 pop {r3, pc}
Error_Handler();
8000472: f7ff ffd1 bl 8000418 <Error_Handler>
8000476: bf00 nop
8000478: 20000188 .word 0x20000188
800047c: 4000a000 .word 0x4000a000
08000480 <MX_TIM15_Init>:
{
8000480: b500 push {lr}
8000482: b08d sub sp, #52 @ 0x34
TIM_SlaveConfigTypeDef sSlaveConfig = {0};
8000484: 2300 movs r3, #0
8000486: 9307 str r3, [sp, #28]
8000488: 9308 str r3, [sp, #32]
800048a: 9309 str r3, [sp, #36] @ 0x24
800048c: 930a str r3, [sp, #40] @ 0x28
800048e: 930b str r3, [sp, #44] @ 0x2c
TIM_IC_InitTypeDef sConfigIC = {0};
8000490: 9303 str r3, [sp, #12]
8000492: 9304 str r3, [sp, #16]
8000494: 9305 str r3, [sp, #20]
8000496: 9306 str r3, [sp, #24]
TIM_MasterConfigTypeDef sMasterConfig = {0};
8000498: 9300 str r3, [sp, #0]
800049a: 9301 str r3, [sp, #4]
800049c: 9302 str r3, [sp, #8]
htim15.Instance = TIM15;
800049e: 4823 ldr r0, [pc, #140] @ (800052c <MX_TIM15_Init+0xac>)
80004a0: 4a23 ldr r2, [pc, #140] @ (8000530 <MX_TIM15_Init+0xb0>)
80004a2: 6002 str r2, [r0, #0]
htim15.Init.Prescaler = 16000-1;
80004a4: f643 627f movw r2, #15999 @ 0x3e7f
80004a8: 6042 str r2, [r0, #4]
htim15.Init.CounterMode = TIM_COUNTERMODE_UP;
80004aa: 6083 str r3, [r0, #8]
htim15.Init.Period = 65535;
80004ac: f64f 72ff movw r2, #65535 @ 0xffff
80004b0: 60c2 str r2, [r0, #12]
htim15.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
80004b2: 6103 str r3, [r0, #16]
htim15.Init.RepetitionCounter = 0;
80004b4: 6143 str r3, [r0, #20]
htim15.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
80004b6: 6183 str r3, [r0, #24]
if (HAL_TIM_IC_Init(&htim15) != HAL_OK)
80004b8: f004 f988 bl 80047cc <HAL_TIM_IC_Init>
80004bc: 2800 cmp r0, #0
80004be: d12b bne.n 8000518 <MX_TIM15_Init+0x98>
sSlaveConfig.SlaveMode = TIM_SLAVEMODE_RESET;
80004c0: 2304 movs r3, #4
80004c2: 9307 str r3, [sp, #28]
sSlaveConfig.InputTrigger = TIM_TS_TI1FP1;
80004c4: 2350 movs r3, #80 @ 0x50
80004c6: 9308 str r3, [sp, #32]
sSlaveConfig.TriggerPolarity = TIM_INPUTCHANNELPOLARITY_RISING;
80004c8: 2300 movs r3, #0
80004ca: 9309 str r3, [sp, #36] @ 0x24
sSlaveConfig.TriggerPrescaler = TIM_ICPSC_DIV1;
80004cc: 930a str r3, [sp, #40] @ 0x28
sSlaveConfig.TriggerFilter = 0;
80004ce: 930b str r3, [sp, #44] @ 0x2c
if (HAL_TIM_SlaveConfigSynchro(&htim15, &sSlaveConfig) != HAL_OK)
80004d0: a907 add r1, sp, #28
80004d2: 4816 ldr r0, [pc, #88] @ (800052c <MX_TIM15_Init+0xac>)
80004d4: f004 fb10 bl 8004af8 <HAL_TIM_SlaveConfigSynchro>
80004d8: bb00 cbnz r0, 800051c <MX_TIM15_Init+0x9c>
sConfigIC.ICPolarity = TIM_INPUTCHANNELPOLARITY_RISING;
80004da: 2200 movs r2, #0
80004dc: 9203 str r2, [sp, #12]
sConfigIC.ICSelection = TIM_ICSELECTION_DIRECTTI;
80004de: 2301 movs r3, #1
80004e0: 9304 str r3, [sp, #16]
sConfigIC.ICPrescaler = TIM_ICPSC_DIV1;
80004e2: 9205 str r2, [sp, #20]
sConfigIC.ICFilter = 0;
80004e4: 9206 str r2, [sp, #24]
if (HAL_TIM_IC_ConfigChannel(&htim15, &sConfigIC, TIM_CHANNEL_1) != HAL_OK)
80004e6: a903 add r1, sp, #12
80004e8: 4810 ldr r0, [pc, #64] @ (800052c <MX_TIM15_Init+0xac>)
80004ea: f004 f9e9 bl 80048c0 <HAL_TIM_IC_ConfigChannel>
80004ee: b9b8 cbnz r0, 8000520 <MX_TIM15_Init+0xa0>
sConfigIC.ICPolarity = TIM_INPUTCHANNELPOLARITY_FALLING;
80004f0: 2302 movs r3, #2
80004f2: 9303 str r3, [sp, #12]
sConfigIC.ICSelection = TIM_ICSELECTION_INDIRECTTI;
80004f4: 9304 str r3, [sp, #16]
if (HAL_TIM_IC_ConfigChannel(&htim15, &sConfigIC, TIM_CHANNEL_2) != HAL_OK)
80004f6: 2204 movs r2, #4
80004f8: a903 add r1, sp, #12
80004fa: 480c ldr r0, [pc, #48] @ (800052c <MX_TIM15_Init+0xac>)
80004fc: f004 f9e0 bl 80048c0 <HAL_TIM_IC_ConfigChannel>
8000500: b980 cbnz r0, 8000524 <MX_TIM15_Init+0xa4>
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
8000502: 2300 movs r3, #0
8000504: 9300 str r3, [sp, #0]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
8000506: 9302 str r3, [sp, #8]
if (HAL_TIMEx_MasterConfigSynchronization(&htim15, &sMasterConfig) != HAL_OK)
8000508: 4669 mov r1, sp
800050a: 4808 ldr r0, [pc, #32] @ (800052c <MX_TIM15_Init+0xac>)
800050c: f004 fb1e bl 8004b4c <HAL_TIMEx_MasterConfigSynchronization>
8000510: b950 cbnz r0, 8000528 <MX_TIM15_Init+0xa8>
}
8000512: b00d add sp, #52 @ 0x34
8000514: f85d fb04 ldr.w pc, [sp], #4
Error_Handler();
8000518: f7ff ff7e bl 8000418 <Error_Handler>
Error_Handler();
800051c: f7ff ff7c bl 8000418 <Error_Handler>
Error_Handler();
8000520: f7ff ff7a bl 8000418 <Error_Handler>
Error_Handler();
8000524: f7ff ff78 bl 8000418 <Error_Handler>
Error_Handler();
8000528: f7ff ff76 bl 8000418 <Error_Handler>
800052c: 2000002c .word 0x2000002c
8000530: 40014000 .word 0x40014000
08000534 <MX_SPI1_Init>:
{
8000534: b508 push {r3, lr}
hspi1.Instance = SPI1;
8000536: 4813 ldr r0, [pc, #76] @ (8000584 <MX_SPI1_Init+0x50>)
8000538: 4b13 ldr r3, [pc, #76] @ (8000588 <MX_SPI1_Init+0x54>)
800053a: 6003 str r3, [r0, #0]
hspi1.Init.Mode = SPI_MODE_MASTER;
800053c: f44f 0380 mov.w r3, #4194304 @ 0x400000
8000540: 6043 str r3, [r0, #4]
hspi1.Init.Direction = SPI_DIRECTION_2LINES;
8000542: 2300 movs r3, #0
8000544: 6083 str r3, [r0, #8]
hspi1.Init.DataSize = SPI_DATASIZE_4BIT;
8000546: 2203 movs r2, #3
8000548: 60c2 str r2, [r0, #12]
hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;
800054a: 6103 str r3, [r0, #16]
hspi1.Init.CLKPhase = SPI_PHASE_1EDGE;
800054c: 6143 str r3, [r0, #20]
hspi1.Init.NSS = SPI_NSS_HARD_OUTPUT;
800054e: f04f 5200 mov.w r2, #536870912 @ 0x20000000
8000552: 6182 str r2, [r0, #24]
hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
8000554: 61c3 str r3, [r0, #28]
hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
8000556: 6203 str r3, [r0, #32]
hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
8000558: 6243 str r3, [r0, #36] @ 0x24
hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
800055a: 6283 str r3, [r0, #40] @ 0x28
hspi1.Init.CRCPolynomial = 0x0;
800055c: 62c3 str r3, [r0, #44] @ 0x2c
hspi1.Init.NSSPMode = SPI_NSS_PULSE_ENABLE;
800055e: f04f 4280 mov.w r2, #1073741824 @ 0x40000000
8000562: 6342 str r2, [r0, #52] @ 0x34
hspi1.Init.NSSPolarity = SPI_NSS_POLARITY_LOW;
8000564: 6383 str r3, [r0, #56] @ 0x38
hspi1.Init.FifoThreshold = SPI_FIFO_THRESHOLD_01DATA;
8000566: 63c3 str r3, [r0, #60] @ 0x3c
hspi1.Init.TxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN;
8000568: 6403 str r3, [r0, #64] @ 0x40
hspi1.Init.RxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN;
800056a: 6443 str r3, [r0, #68] @ 0x44
hspi1.Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE;
800056c: 6483 str r3, [r0, #72] @ 0x48
hspi1.Init.MasterInterDataIdleness = SPI_MASTER_INTERDATA_IDLENESS_00CYCLE;
800056e: 64c3 str r3, [r0, #76] @ 0x4c
hspi1.Init.MasterReceiverAutoSusp = SPI_MASTER_RX_AUTOSUSP_DISABLE;
8000570: 6503 str r3, [r0, #80] @ 0x50
hspi1.Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_DISABLE;
8000572: 6543 str r3, [r0, #84] @ 0x54
hspi1.Init.IOSwap = SPI_IO_SWAP_DISABLE;
8000574: 6583 str r3, [r0, #88] @ 0x58
if (HAL_SPI_Init(&hspi1) != HAL_OK)
8000576: f003 ff5f bl 8004438 <HAL_SPI_Init>
800057a: b900 cbnz r0, 800057e <MX_SPI1_Init+0x4a>
}
800057c: bd08 pop {r3, pc}
Error_Handler();
800057e: f7ff ff4b bl 8000418 <Error_Handler>
8000582: bf00 nop
8000584: 20000100 .word 0x20000100
8000588: 40013000 .word 0x40013000
0800058c <MX_SPI2_Init>:
{
800058c: b508 push {r3, lr}
hspi2.Instance = SPI2;
800058e: 4812 ldr r0, [pc, #72] @ (80005d8 <MX_SPI2_Init+0x4c>)
8000590: 4b12 ldr r3, [pc, #72] @ (80005dc <MX_SPI2_Init+0x50>)
8000592: 6003 str r3, [r0, #0]
hspi2.Init.Mode = SPI_MODE_MASTER;
8000594: f44f 0380 mov.w r3, #4194304 @ 0x400000
8000598: 6043 str r3, [r0, #4]
hspi2.Init.Direction = SPI_DIRECTION_2LINES;
800059a: 2300 movs r3, #0
800059c: 6083 str r3, [r0, #8]
hspi2.Init.DataSize = SPI_DATASIZE_4BIT;
800059e: 2203 movs r2, #3
80005a0: 60c2 str r2, [r0, #12]
hspi2.Init.CLKPolarity = SPI_POLARITY_LOW;
80005a2: 6103 str r3, [r0, #16]
hspi2.Init.CLKPhase = SPI_PHASE_1EDGE;
80005a4: 6143 str r3, [r0, #20]
hspi2.Init.NSS = SPI_NSS_HARD_INPUT;
80005a6: 6183 str r3, [r0, #24]
hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
80005a8: 61c3 str r3, [r0, #28]
hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB;
80005aa: 6203 str r3, [r0, #32]
hspi2.Init.TIMode = SPI_TIMODE_DISABLE;
80005ac: 6243 str r3, [r0, #36] @ 0x24
hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
80005ae: 6283 str r3, [r0, #40] @ 0x28
hspi2.Init.CRCPolynomial = 0x0;
80005b0: 62c3 str r3, [r0, #44] @ 0x2c
hspi2.Init.NSSPMode = SPI_NSS_PULSE_ENABLE;
80005b2: f04f 4280 mov.w r2, #1073741824 @ 0x40000000
80005b6: 6342 str r2, [r0, #52] @ 0x34
hspi2.Init.NSSPolarity = SPI_NSS_POLARITY_LOW;
80005b8: 6383 str r3, [r0, #56] @ 0x38
hspi2.Init.FifoThreshold = SPI_FIFO_THRESHOLD_01DATA;
80005ba: 63c3 str r3, [r0, #60] @ 0x3c
hspi2.Init.TxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN;
80005bc: 6403 str r3, [r0, #64] @ 0x40
hspi2.Init.RxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN;
80005be: 6443 str r3, [r0, #68] @ 0x44
hspi2.Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE;
80005c0: 6483 str r3, [r0, #72] @ 0x48
hspi2.Init.MasterInterDataIdleness = SPI_MASTER_INTERDATA_IDLENESS_00CYCLE;
80005c2: 64c3 str r3, [r0, #76] @ 0x4c
hspi2.Init.MasterReceiverAutoSusp = SPI_MASTER_RX_AUTOSUSP_DISABLE;
80005c4: 6503 str r3, [r0, #80] @ 0x50
hspi2.Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_DISABLE;
80005c6: 6543 str r3, [r0, #84] @ 0x54
hspi2.Init.IOSwap = SPI_IO_SWAP_DISABLE;
80005c8: 6583 str r3, [r0, #88] @ 0x58
if (HAL_SPI_Init(&hspi2) != HAL_OK)
80005ca: f003 ff35 bl 8004438 <HAL_SPI_Init>
80005ce: b900 cbnz r0, 80005d2 <MX_SPI2_Init+0x46>
}
80005d0: bd08 pop {r3, pc}
Error_Handler();
80005d2: f7ff ff21 bl 8000418 <Error_Handler>
80005d6: bf00 nop
80005d8: 20000078 .word 0x20000078
80005dc: 40003800 .word 0x40003800
080005e0 <MX_ADC1_Init>:
{
80005e0: b500 push {lr}
80005e2: b08b sub sp, #44 @ 0x2c
ADC_MultiModeTypeDef multimode = {0};
80005e4: 2300 movs r3, #0
80005e6: 9307 str r3, [sp, #28]
80005e8: 9308 str r3, [sp, #32]
80005ea: 9309 str r3, [sp, #36] @ 0x24
ADC_ChannelConfTypeDef sConfig = {0};
80005ec: 9300 str r3, [sp, #0]
80005ee: 9301 str r3, [sp, #4]
80005f0: 9302 str r3, [sp, #8]
80005f2: 9303 str r3, [sp, #12]
80005f4: 9304 str r3, [sp, #16]
80005f6: 9305 str r3, [sp, #20]
80005f8: 9306 str r3, [sp, #24]
hadc1.Instance = ADC1;
80005fa: 481d ldr r0, [pc, #116] @ (8000670 <MX_ADC1_Init+0x90>)
80005fc: 4a1d ldr r2, [pc, #116] @ (8000674 <MX_ADC1_Init+0x94>)
80005fe: 6002 str r2, [r0, #0]
hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1;
8000600: 6043 str r3, [r0, #4]
hadc1.Init.Resolution = ADC_RESOLUTION_16B;
8000602: 6083 str r3, [r0, #8]
hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
8000604: 60c3 str r3, [r0, #12]
hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
8000606: 2204 movs r2, #4
8000608: 6102 str r2, [r0, #16]
hadc1.Init.LowPowerAutoWait = DISABLE;
800060a: 7503 strb r3, [r0, #20]
hadc1.Init.ContinuousConvMode = DISABLE;
800060c: 7543 strb r3, [r0, #21]
hadc1.Init.NbrOfConversion = 1;
800060e: 2201 movs r2, #1
8000610: 6182 str r2, [r0, #24]
hadc1.Init.DiscontinuousConvMode = DISABLE;
8000612: 7703 strb r3, [r0, #28]
hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
8000614: 6243 str r3, [r0, #36] @ 0x24
hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
8000616: 6283 str r3, [r0, #40] @ 0x28
hadc1.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR;
8000618: 62c3 str r3, [r0, #44] @ 0x2c
hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED;
800061a: 6303 str r3, [r0, #48] @ 0x30
hadc1.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE;
800061c: 6343 str r3, [r0, #52] @ 0x34
hadc1.Init.OversamplingMode = DISABLE;
800061e: f880 3038 strb.w r3, [r0, #56] @ 0x38
if (HAL_ADC_Init(&hadc1) != HAL_OK)
8000622: f000 fc29 bl 8000e78 <HAL_ADC_Init>
8000626: b9e0 cbnz r0, 8000662 <MX_ADC1_Init+0x82>
multimode.Mode = ADC_MODE_INDEPENDENT;
8000628: 2300 movs r3, #0
800062a: 9307 str r3, [sp, #28]
if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK)
800062c: a907 add r1, sp, #28
800062e: 4810 ldr r0, [pc, #64] @ (8000670 <MX_ADC1_Init+0x90>)
8000630: f000 fd1e bl 8001070 <HAL_ADCEx_MultiModeConfigChannel>
8000634: b9b8 cbnz r0, 8000666 <MX_ADC1_Init+0x86>
sConfig.Channel = ADC_CHANNEL_10;
8000636: 4b10 ldr r3, [pc, #64] @ (8000678 <MX_ADC1_Init+0x98>)
8000638: 9300 str r3, [sp, #0]
sConfig.Rank = ADC_REGULAR_RANK_1;
800063a: 2306 movs r3, #6
800063c: 9301 str r3, [sp, #4]
sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
800063e: 2300 movs r3, #0
8000640: 9302 str r3, [sp, #8]
sConfig.SingleDiff = ADC_SINGLE_ENDED;
8000642: f240 72ff movw r2, #2047 @ 0x7ff
8000646: 9203 str r2, [sp, #12]
sConfig.OffsetNumber = ADC_OFFSET_NONE;
8000648: 2204 movs r2, #4
800064a: 9204 str r2, [sp, #16]
sConfig.Offset = 0;
800064c: 9305 str r3, [sp, #20]
sConfig.OffsetSignedSaturation = DISABLE;
800064e: f88d 3019 strb.w r3, [sp, #25]
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
8000652: 4669 mov r1, sp
8000654: 4806 ldr r0, [pc, #24] @ (8000670 <MX_ADC1_Init+0x90>)
8000656: f000 f97b bl 8000950 <HAL_ADC_ConfigChannel>
800065a: b930 cbnz r0, 800066a <MX_ADC1_Init+0x8a>
}
800065c: b00b add sp, #44 @ 0x2c
800065e: f85d fb04 ldr.w pc, [sp], #4
Error_Handler();
8000662: f7ff fed9 bl 8000418 <Error_Handler>
Error_Handler();
8000666: f7ff fed7 bl 8000418 <Error_Handler>
Error_Handler();
800066a: f7ff fed5 bl 8000418 <Error_Handler>
800066e: bf00 nop
8000670: 2000028c .word 0x2000028c
8000674: 40022000 .word 0x40022000
8000678: 2a000400 .word 0x2a000400
0800067c <MX_ADC2_Init>:
{
800067c: b500 push {lr}
800067e: b089 sub sp, #36 @ 0x24
ADC_ChannelConfTypeDef sConfig = {0};
8000680: 2300 movs r3, #0
8000682: 9301 str r3, [sp, #4]
8000684: 9302 str r3, [sp, #8]
8000686: 9303 str r3, [sp, #12]
8000688: 9304 str r3, [sp, #16]
800068a: 9305 str r3, [sp, #20]
800068c: 9306 str r3, [sp, #24]
800068e: 9307 str r3, [sp, #28]
hadc2.Instance = ADC2;
8000690: 4818 ldr r0, [pc, #96] @ (80006f4 <MX_ADC2_Init+0x78>)
8000692: 4a19 ldr r2, [pc, #100] @ (80006f8 <MX_ADC2_Init+0x7c>)
8000694: 6002 str r2, [r0, #0]
hadc2.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1;
8000696: 6043 str r3, [r0, #4]
hadc2.Init.Resolution = ADC_RESOLUTION_16B;
8000698: 6083 str r3, [r0, #8]
hadc2.Init.ScanConvMode = ADC_SCAN_DISABLE;
800069a: 60c3 str r3, [r0, #12]
hadc2.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
800069c: 2204 movs r2, #4
800069e: 6102 str r2, [r0, #16]
hadc2.Init.LowPowerAutoWait = DISABLE;
80006a0: 7503 strb r3, [r0, #20]
hadc2.Init.ContinuousConvMode = DISABLE;
80006a2: 7543 strb r3, [r0, #21]
hadc2.Init.NbrOfConversion = 1;
80006a4: 2201 movs r2, #1
80006a6: 6182 str r2, [r0, #24]
hadc2.Init.DiscontinuousConvMode = DISABLE;
80006a8: 7703 strb r3, [r0, #28]
hadc2.Init.ExternalTrigConv = ADC_SOFTWARE_START;
80006aa: 6243 str r3, [r0, #36] @ 0x24
hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
80006ac: 6283 str r3, [r0, #40] @ 0x28
hadc2.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR;
80006ae: 62c3 str r3, [r0, #44] @ 0x2c
hadc2.Init.Overrun = ADC_OVR_DATA_PRESERVED;
80006b0: 6303 str r3, [r0, #48] @ 0x30
hadc2.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE;
80006b2: 6343 str r3, [r0, #52] @ 0x34
hadc2.Init.OversamplingMode = DISABLE;
80006b4: f880 3038 strb.w r3, [r0, #56] @ 0x38
if (HAL_ADC_Init(&hadc2) != HAL_OK)
80006b8: f000 fbde bl 8000e78 <HAL_ADC_Init>
80006bc: b9a8 cbnz r0, 80006ea <MX_ADC2_Init+0x6e>
sConfig.Channel = ADC_CHANNEL_10;
80006be: 4b0f ldr r3, [pc, #60] @ (80006fc <MX_ADC2_Init+0x80>)
80006c0: 9301 str r3, [sp, #4]
sConfig.Rank = ADC_REGULAR_RANK_1;
80006c2: 2306 movs r3, #6
80006c4: 9302 str r3, [sp, #8]
sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
80006c6: 2300 movs r3, #0
80006c8: 9303 str r3, [sp, #12]
sConfig.SingleDiff = ADC_DIFFERENTIAL_ENDED;
80006ca: 4a0d ldr r2, [pc, #52] @ (8000700 <MX_ADC2_Init+0x84>)
80006cc: 9204 str r2, [sp, #16]
sConfig.OffsetNumber = ADC_OFFSET_NONE;
80006ce: 2204 movs r2, #4
80006d0: 9205 str r2, [sp, #20]
sConfig.Offset = 0;
80006d2: 9306 str r3, [sp, #24]
sConfig.OffsetSignedSaturation = DISABLE;
80006d4: f88d 301d strb.w r3, [sp, #29]
if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
80006d8: eb0d 0102 add.w r1, sp, r2
80006dc: 4805 ldr r0, [pc, #20] @ (80006f4 <MX_ADC2_Init+0x78>)
80006de: f000 f937 bl 8000950 <HAL_ADC_ConfigChannel>
80006e2: b920 cbnz r0, 80006ee <MX_ADC2_Init+0x72>
}
80006e4: b009 add sp, #36 @ 0x24
80006e6: f85d fb04 ldr.w pc, [sp], #4
Error_Handler();
80006ea: f7ff fe95 bl 8000418 <Error_Handler>
Error_Handler();
80006ee: f7ff fe93 bl 8000418 <Error_Handler>
80006f2: bf00 nop
80006f4: 20000228 .word 0x20000228
80006f8: 40022100 .word 0x40022100
80006fc: 2a000400 .word 0x2a000400
8000700: 47ff0000 .word 0x47ff0000
08000704 <SystemClock_Config>:
{
8000704: b500 push {lr}
8000706: b09d sub sp, #116 @ 0x74
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
8000708: 224c movs r2, #76 @ 0x4c
800070a: 2100 movs r1, #0
800070c: a809 add r0, sp, #36 @ 0x24
800070e: f004 fb00 bl 8004d12 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
8000712: 2220 movs r2, #32
8000714: 2100 movs r1, #0
8000716: a801 add r0, sp, #4
8000718: f004 fafb bl 8004d12 <memset>
RCC->CKGAENR = 0xFFFFFFFF;
800071c: 4b23 ldr r3, [pc, #140] @ (80007ac <SystemClock_Config+0xa8>)
800071e: f04f 32ff mov.w r2, #4294967295
8000722: f8c3 20b0 str.w r2, [r3, #176] @ 0xb0
HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
8000726: 2002 movs r0, #2
8000728: f001 fc5e bl 8001fe8 <HAL_PWREx_ConfigSupply>
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
800072c: 2300 movs r3, #0
800072e: 9300 str r3, [sp, #0]
8000730: 4b1f ldr r3, [pc, #124] @ (80007b0 <SystemClock_Config+0xac>)
8000732: 699a ldr r2, [r3, #24]
8000734: f422 4240 bic.w r2, r2, #49152 @ 0xc000
8000738: 619a str r2, [r3, #24]
800073a: 699b ldr r3, [r3, #24]
800073c: f403 4340 and.w r3, r3, #49152 @ 0xc000
8000740: 9300 str r3, [sp, #0]
8000742: 9b00 ldr r3, [sp, #0]
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
8000744: 4b1a ldr r3, [pc, #104] @ (80007b0 <SystemClock_Config+0xac>)
8000746: 699b ldr r3, [r3, #24]
8000748: f413 5f00 tst.w r3, #8192 @ 0x2000
800074c: d0fa beq.n 8000744 <SystemClock_Config+0x40>
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
800074e: 2201 movs r2, #1
8000750: 9209 str r2, [sp, #36] @ 0x24
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
8000752: f44f 3380 mov.w r3, #65536 @ 0x10000
8000756: 930a str r3, [sp, #40] @ 0x28
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
8000758: 2302 movs r3, #2
800075a: 9312 str r3, [sp, #72] @ 0x48
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
800075c: 9313 str r3, [sp, #76] @ 0x4c
RCC_OscInitStruct.PLL.PLLM = 1;
800075e: 9214 str r2, [sp, #80] @ 0x50
RCC_OscInitStruct.PLL.PLLN = 8;
8000760: 2208 movs r2, #8
8000762: 9215 str r2, [sp, #84] @ 0x54
RCC_OscInitStruct.PLL.PLLP = 2;
8000764: 9316 str r3, [sp, #88] @ 0x58
RCC_OscInitStruct.PLL.PLLQ = 2;
8000766: 9317 str r3, [sp, #92] @ 0x5c
RCC_OscInitStruct.PLL.PLLR = 2;
8000768: 9318 str r3, [sp, #96] @ 0x60
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3;
800076a: 230c movs r3, #12
800076c: 9319 str r3, [sp, #100] @ 0x64
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
800076e: 2300 movs r3, #0
8000770: 931a str r3, [sp, #104] @ 0x68
RCC_OscInitStruct.PLL.PLLFRACN = 0;
8000772: 931b str r3, [sp, #108] @ 0x6c
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
8000774: a809 add r0, sp, #36 @ 0x24
8000776: f001 fc61 bl 800203c <HAL_RCC_OscConfig>
800077a: b990 cbnz r0, 80007a2 <SystemClock_Config+0x9e>
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
800077c: 233f movs r3, #63 @ 0x3f
800077e: 9301 str r3, [sp, #4]
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
8000780: 2303 movs r3, #3
8000782: 9302 str r3, [sp, #8]
RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
8000784: 2300 movs r3, #0
8000786: 9303 str r3, [sp, #12]
RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV1;
8000788: 9304 str r3, [sp, #16]
RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV1;
800078a: 9305 str r3, [sp, #20]
RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV1;
800078c: 9306 str r3, [sp, #24]
RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV1;
800078e: 9307 str r3, [sp, #28]
RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV1;
8000790: 9308 str r3, [sp, #32]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
8000792: 2102 movs r1, #2
8000794: a801 add r0, sp, #4
8000796: f002 f87d bl 8002894 <HAL_RCC_ClockConfig>
800079a: b920 cbnz r0, 80007a6 <SystemClock_Config+0xa2>
}
800079c: b01d add sp, #116 @ 0x74
800079e: f85d fb04 ldr.w pc, [sp], #4
Error_Handler();
80007a2: f7ff fe39 bl 8000418 <Error_Handler>
Error_Handler();
80007a6: f7ff fe37 bl 8000418 <Error_Handler>
80007aa: bf00 nop
80007ac: 58024400 .word 0x58024400
80007b0: 58024800 .word 0x58024800
080007b4 <PeriphCommonClock_Config>:
{
80007b4: b530 push {r4, r5, lr}
80007b6: b0b1 sub sp, #196 @ 0xc4
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
80007b8: 25c0 movs r5, #192 @ 0xc0
80007ba: 462a mov r2, r5
80007bc: 2100 movs r1, #0
80007be: 4668 mov r0, sp
80007c0: f004 faa7 bl 8004d12 <memset>
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADC|RCC_PERIPHCLK_FDCAN;
80007c4: f44f 2208 mov.w r2, #557056 @ 0x88000
80007c8: 2300 movs r3, #0
80007ca: e9cd 2300 strd r2, r3, [sp]
PeriphClkInitStruct.PLL2.PLL2M = 1;
80007ce: 2301 movs r3, #1
80007d0: 9302 str r3, [sp, #8]
PeriphClkInitStruct.PLL2.PLL2N = 8;
80007d2: 2308 movs r3, #8
80007d4: 9303 str r3, [sp, #12]
PeriphClkInitStruct.PLL2.PLL2P = 3;
80007d6: 2303 movs r3, #3
80007d8: 9304 str r3, [sp, #16]
PeriphClkInitStruct.PLL2.PLL2Q = 3;
80007da: 9305 str r3, [sp, #20]
PeriphClkInitStruct.PLL2.PLL2R = 2;
80007dc: 2302 movs r3, #2
80007de: 9306 str r3, [sp, #24]
PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_3;
80007e0: 9507 str r5, [sp, #28]
PeriphClkInitStruct.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL2;
80007e2: f04f 5300 mov.w r3, #536870912 @ 0x20000000
80007e6: 931e str r3, [sp, #120] @ 0x78
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
80007e8: 4668 mov r0, sp
80007ea: f002 fad9 bl 8002da0 <HAL_RCCEx_PeriphCLKConfig>
80007ee: b908 cbnz r0, 80007f4 <PeriphCommonClock_Config+0x40>
}
80007f0: b031 add sp, #196 @ 0xc4
80007f2: bd30 pop {r4, r5, pc}
Error_Handler();
80007f4: f7ff fe10 bl 8000418 <Error_Handler>
080007f8 <main>:
{
80007f8: b508 push {r3, lr}
HAL_Init();
80007fa: f000 f83b bl 8000874 <HAL_Init>
SystemClock_Config();
80007fe: f7ff ff81 bl 8000704 <SystemClock_Config>
PeriphCommonClock_Config();
8000802: f7ff ffd7 bl 80007b4 <PeriphCommonClock_Config>
MX_GPIO_Init();
8000806: f7ff fd71 bl 80002ec <MX_GPIO_Init>
MX_FDCAN1_Init();
800080a: f7ff fe07 bl 800041c <MX_FDCAN1_Init>
MX_TIM15_Init();
800080e: f7ff fe37 bl 8000480 <MX_TIM15_Init>
MX_SPI1_Init();
8000812: f7ff fe8f bl 8000534 <MX_SPI1_Init>
MX_SPI2_Init();
8000816: f7ff feb9 bl 800058c <MX_SPI2_Init>
MX_ADC1_Init();
800081a: f7ff fee1 bl 80005e0 <MX_ADC1_Init>
MX_ADC2_Init();
800081e: f7ff ff2d bl 800067c <MX_ADC2_Init>
while (1)
8000822: e7fe b.n 8000822 <main+0x2a>
08000824 <HAL_InitTick>:
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
/* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that don't take the value zero)*/
if((uint32_t)uwTickFreq == 0UL)
8000824: 4b10 ldr r3, [pc, #64] @ (8000868 <HAL_InitTick+0x44>)
8000826: 781b ldrb r3, [r3, #0]
8000828: b90b cbnz r3, 800082e <HAL_InitTick+0xa>
{
return HAL_ERROR;
800082a: 2001 movs r0, #1
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
}
800082c: 4770 bx lr
{
800082e: b510 push {r4, lr}
8000830: 4604 mov r4, r0
if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) > 0U)
8000832: f44f 707a mov.w r0, #1000 @ 0x3e8
8000836: fbb0 f3f3 udiv r3, r0, r3
800083a: 4a0c ldr r2, [pc, #48] @ (800086c <HAL_InitTick+0x48>)
800083c: 6810 ldr r0, [r2, #0]
800083e: fbb0 f0f3 udiv r0, r0, r3
8000842: f000 fd01 bl 8001248 <HAL_SYSTICK_Config>
8000846: b968 cbnz r0, 8000864 <HAL_InitTick+0x40>
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8000848: 2c0f cmp r4, #15
800084a: d901 bls.n 8000850 <HAL_InitTick+0x2c>
return HAL_ERROR;
800084c: 2001 movs r0, #1
800084e: e00a b.n 8000866 <HAL_InitTick+0x42>
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
8000850: 2200 movs r2, #0
8000852: 4621 mov r1, r4
8000854: f04f 30ff mov.w r0, #4294967295
8000858: f000 fce2 bl 8001220 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
800085c: 4b04 ldr r3, [pc, #16] @ (8000870 <HAL_InitTick+0x4c>)
800085e: 601c str r4, [r3, #0]
return HAL_OK;
8000860: 2000 movs r0, #0
8000862: e000 b.n 8000866 <HAL_InitTick+0x42>
return HAL_ERROR;
8000864: 2001 movs r0, #1
}
8000866: bd10 pop {r4, pc}
8000868: 20000000 .word 0x20000000
800086c: 2000000c .word 0x2000000c
8000870: 20000004 .word 0x20000004
08000874 <HAL_Init>:
{
8000874: b510 push {r4, lr}
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
8000876: 2003 movs r0, #3
8000878: f000 fcc0 bl 80011fc <HAL_NVIC_SetPriorityGrouping>
common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU);
800087c: f001 ff0e bl 800269c <HAL_RCC_GetSysClockFreq>
8000880: 490f ldr r1, [pc, #60] @ (80008c0 <HAL_Init+0x4c>)
8000882: 698b ldr r3, [r1, #24]
8000884: f3c3 2303 ubfx r3, r3, #8, #4
8000888: 4a0e ldr r2, [pc, #56] @ (80008c4 <HAL_Init+0x50>)
800088a: 5cd3 ldrb r3, [r2, r3]
800088c: f003 031f and.w r3, r3, #31
8000890: 40d8 lsrs r0, r3
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
8000892: 698b ldr r3, [r1, #24]
8000894: f003 030f and.w r3, r3, #15
8000898: 5cd3 ldrb r3, [r2, r3]
800089a: f003 031f and.w r3, r3, #31
800089e: fa20 f303 lsr.w r3, r0, r3
80008a2: 4a09 ldr r2, [pc, #36] @ (80008c8 <HAL_Init+0x54>)
80008a4: 6013 str r3, [r2, #0]
SystemCoreClock = common_system_clock;
80008a6: 4b09 ldr r3, [pc, #36] @ (80008cc <HAL_Init+0x58>)
80008a8: 6018 str r0, [r3, #0]
if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
80008aa: 200f movs r0, #15
80008ac: f7ff ffba bl 8000824 <HAL_InitTick>
80008b0: b110 cbz r0, 80008b8 <HAL_Init+0x44>
return HAL_ERROR;
80008b2: 2401 movs r4, #1
}
80008b4: 4620 mov r0, r4
80008b6: bd10 pop {r4, pc}
80008b8: 4604 mov r4, r0
HAL_MspInit();
80008ba: f001 f9c5 bl 8001c48 <HAL_MspInit>
return HAL_OK;
80008be: e7f9 b.n 80008b4 <HAL_Init+0x40>
80008c0: 58024400 .word 0x58024400
80008c4: 08004dec .word 0x08004dec
80008c8: 20000008 .word 0x20000008
80008cc: 2000000c .word 0x2000000c
080008d0 <HAL_IncTick>:
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
uwTick += (uint32_t)uwTickFreq;
80008d0: 4b03 ldr r3, [pc, #12] @ (80008e0 <HAL_IncTick+0x10>)
80008d2: 781b ldrb r3, [r3, #0]
80008d4: 4a03 ldr r2, [pc, #12] @ (80008e4 <HAL_IncTick+0x14>)
80008d6: 6811 ldr r1, [r2, #0]
80008d8: 440b add r3, r1
80008da: 6013 str r3, [r2, #0]
}
80008dc: 4770 bx lr
80008de: bf00 nop
80008e0: 20000000 .word 0x20000000
80008e4: 200002f0 .word 0x200002f0
080008e8 <HAL_GetTick>:
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
return uwTick;
80008e8: 4b01 ldr r3, [pc, #4] @ (80008f0 <HAL_GetTick+0x8>)
80008ea: 6818 ldr r0, [r3, #0]
}
80008ec: 4770 bx lr
80008ee: bf00 nop
80008f0: 200002f0 .word 0x200002f0
080008f4 <LL_ADC_REG_SetSequencerRanks>:
* (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
* Other channels are slow channels (conversion rate: refer to reference manual).
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
{
80008f4: b410 push {r4}
/* Set bits with content of parameter "Channel" with bits position */
/* in register and register position depending on parameter "Rank". */
/* Parameters "Rank" and "Channel" are used with masks because containing */
/* other bits reserved for other purpose. */
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
80008f6: 3030 adds r0, #48 @ 0x30
80008f8: 0a0b lsrs r3, r1, #8
80008fa: 009b lsls r3, r3, #2
80008fc: f003 030c and.w r3, r3, #12
MODIFY_REG(*preg,
8000900: 58c4 ldr r4, [r0, r3]
8000902: f001 011f and.w r1, r1, #31
8000906: f04f 0c1f mov.w ip, #31
800090a: fa0c fc01 lsl.w ip, ip, r1
800090e: ea24 0c0c bic.w ip, r4, ip
8000912: f3c2 6284 ubfx r2, r2, #26, #5
8000916: 408a lsls r2, r1
8000918: ea4c 0202 orr.w r2, ip, r2
800091c: 50c2 str r2, [r0, r3]
ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
}
800091e: f85d 4b04 ldr.w r4, [sp], #4
8000922: 4770 bx lr
08000924 <LL_ADC_SetChannelSamplingTime>:
* @arg @ref LL_ADC_SAMPLINGTIME_387CYCLES_5
* @arg @ref LL_ADC_SAMPLINGTIME_810CYCLES_5
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
{
8000924: b410 push {r4}
/* Set bits with content of parameter "SamplingTime" with bits position */
/* in register and register position depending on parameter "Channel". */
/* Parameter "Channel" is used with masks because containing */
/* other bits reserved for other purpose. */
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
8000926: 3014 adds r0, #20
8000928: 0e4b lsrs r3, r1, #25
800092a: 009b lsls r3, r3, #2
800092c: f003 0304 and.w r3, r3, #4
MODIFY_REG(*preg,
8000930: 58c4 ldr r4, [r0, r3]
8000932: f3c1 5104 ubfx r1, r1, #20, #5
8000936: f04f 0c07 mov.w ip, #7
800093a: fa0c fc01 lsl.w ip, ip, r1
800093e: ea24 0c0c bic.w ip, r4, ip
8000942: 408a lsls r2, r1
8000944: ea4c 0202 orr.w r2, ip, r2
8000948: 50c2 str r2, [r0, r3]
ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS),
SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS));
}
800094a: f85d 4b04 ldr.w r4, [sp], #4
800094e: 4770 bx lr
08000950 <HAL_ADC_ConfigChannel>:
* @param hadc ADC handle
* @param sConfig Structure of ADC channel assigned to ADC group regular.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
{
8000950: b5f0 push {r4, r5, r6, r7, lr}
8000952: b083 sub sp, #12
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
uint32_t tmpOffsetShifted;
uint32_t tmp_config_internal_channel;
__IO uint32_t wait_loop_index = 0;
8000954: 2300 movs r3, #0
8000956: 9301 str r3, [sp, #4]
}
#endif
}
/* Process locked */
__HAL_LOCK(hadc);
8000958: f890 3050 ldrb.w r3, [r0, #80] @ 0x50
800095c: 2b01 cmp r3, #1
800095e: f000 81fa beq.w 8000d56 <HAL_ADC_ConfigChannel+0x406>
8000962: 4604 mov r4, r0
8000964: 460d mov r5, r1
8000966: 2301 movs r3, #1
8000968: f880 3050 strb.w r3, [r0, #80] @ 0x50
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated when ADC is disabled or enabled without */
/* conversion on going on regular group: */
/* - Channel number */
/* - Channel rank */
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
800096c: 6802 ldr r2, [r0, #0]
* @param ADCx ADC instance
* @retval 0: no conversion is on going on ADC group regular.
*/
__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
800096e: 6893 ldr r3, [r2, #8]
8000970: f013 0f04 tst.w r3, #4
8000974: d009 beq.n 800098a <HAL_ADC_ConfigChannel+0x3a>
/* channel could be done on neither of the channel configuration structure */
/* parameters. */
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8000976: 6d43 ldr r3, [r0, #84] @ 0x54
8000978: f043 0320 orr.w r3, r3, #32
800097c: 6543 str r3, [r0, #84] @ 0x54
tmp_hal_status = HAL_ERROR;
800097e: 2001 movs r0, #1
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
8000980: 2300 movs r3, #0
8000982: f884 3050 strb.w r3, [r4, #80] @ 0x50
/* Return function status */
return tmp_hal_status;
}
8000986: b003 add sp, #12
8000988: bdf0 pop {r4, r5, r6, r7, pc}
if (!(__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)))
800098a: 680b ldr r3, [r1, #0]
800098c: 2b00 cmp r3, #0
800098e: db0a blt.n 80009a6 <HAL_ADC_ConfigChannel+0x56>
hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL));
8000990: f3c3 0113 ubfx r1, r3, #0, #20
8000994: 2900 cmp r1, #0
8000996: d139 bne.n 8000a0c <HAL_ADC_ConfigChannel+0xbc>
8000998: f3c3 6384 ubfx r3, r3, #26, #5
800099c: 2101 movs r1, #1
800099e: 4099 lsls r1, r3
80009a0: 69d3 ldr r3, [r2, #28]
80009a2: 430b orrs r3, r1
80009a4: 61d3 str r3, [r2, #28]
LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel);
80009a6: 682a ldr r2, [r5, #0]
80009a8: 6869 ldr r1, [r5, #4]
80009aa: 6820 ldr r0, [r4, #0]
80009ac: f7ff ffa2 bl 80008f4 <LL_ADC_REG_SetSequencerRanks>
tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
80009b0: 6820 ldr r0, [r4, #0]
80009b2: 6886 ldr r6, [r0, #8]
80009b4: f016 0604 ands.w r6, r6, #4
80009b8: d000 beq.n 80009bc <HAL_ADC_ConfigChannel+0x6c>
80009ba: 2601 movs r6, #1
* @param ADCx ADC instance
* @retval 0: no conversion is on going on ADC group injected.
*/
__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
80009bc: 6883 ldr r3, [r0, #8]
80009be: f013 0f08 tst.w r3, #8
80009c2: d100 bne.n 80009c6 <HAL_ADC_ConfigChannel+0x76>
if ((tmp_adc_is_conversion_on_going_regular == 0UL)
80009c4: b376 cbz r6, 8000a24 <HAL_ADC_ConfigChannel+0xd4>
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
80009c6: 6821 ldr r1, [r4, #0]
return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
80009c8: 688b ldr r3, [r1, #8]
80009ca: f013 0f01 tst.w r3, #1
80009ce: f040 81be bne.w 8000d4e <HAL_ADC_ConfigChannel+0x3fe>
LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfig->Channel, sConfig->SingleDiff);
80009d2: 682b ldr r3, [r5, #0]
80009d4: 68e8 ldr r0, [r5, #12]
MODIFY_REG(ADCx->DIFSEL,
80009d6: f8d1 20c0 ldr.w r2, [r1, #192] @ 0xc0
80009da: f3c3 0613 ubfx r6, r3, #0, #20
80009de: ea22 0206 bic.w r2, r2, r6
80009e2: f000 0618 and.w r6, r0, #24
80009e6: 48a1 ldr r0, [pc, #644] @ (8000c6c <HAL_ADC_ConfigChannel+0x31c>)
80009e8: 40f0 lsrs r0, r6
80009ea: 4003 ands r3, r0
80009ec: f3c3 0313 ubfx r3, r3, #0, #20
80009f0: 4313 orrs r3, r2
80009f2: f8c1 30c0 str.w r3, [r1, #192] @ 0xc0
if (sConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED)
80009f6: 68ea ldr r2, [r5, #12]
80009f8: 4b9d ldr r3, [pc, #628] @ (8000c70 <HAL_ADC_ConfigChannel+0x320>)
80009fa: 429a cmp r2, r3
80009fc: f000 808f beq.w 8000b1e <HAL_ADC_ConfigChannel+0x1ce>
if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
8000a00: 682b ldr r3, [r5, #0]
8000a02: 2b00 cmp r3, #0
8000a04: f2c0 8136 blt.w 8000c74 <HAL_ADC_ConfigChannel+0x324>
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
8000a08: 2000 movs r0, #0
8000a0a: e7b9 b.n 8000980 <HAL_ADC_ConfigChannel+0x30>
uint32_t result;
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8000a0c: fa93 f3a3 rbit r3, r3
optimisations using the logic "value was passed to __builtin_clz, so it
is non-zero".
ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
single CLZ instruction.
*/
if (value == 0U)
8000a10: b133 cbz r3, 8000a20 <HAL_ADC_ConfigChannel+0xd0>
{
return 32U;
}
return __builtin_clz(value);
8000a12: fab3 f383 clz r3, r3
hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) & 0x1FUL));
8000a16: f003 031f and.w r3, r3, #31
8000a1a: 2101 movs r1, #1
8000a1c: 4099 lsls r1, r3
8000a1e: e7bf b.n 80009a0 <HAL_ADC_ConfigChannel+0x50>
return 32U;
8000a20: 2320 movs r3, #32
8000a22: e7f8 b.n 8000a16 <HAL_ADC_ConfigChannel+0xc6>
LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime);
8000a24: 68aa ldr r2, [r5, #8]
8000a26: 6829 ldr r1, [r5, #0]
8000a28: f7ff ff7c bl 8000924 <LL_ADC_SetChannelSamplingTime>
tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset);
8000a2c: 6823 ldr r3, [r4, #0]
8000a2e: 68da ldr r2, [r3, #12]
8000a30: f012 0f10 tst.w r2, #16
8000a34: d131 bne.n 8000a9a <HAL_ADC_ConfigChannel+0x14a>
8000a36: 696a ldr r2, [r5, #20]
8000a38: 68d9 ldr r1, [r3, #12]
8000a3a: f3c1 0182 ubfx r1, r1, #2, #3
8000a3e: 0049 lsls r1, r1, #1
8000a40: 408a lsls r2, r1
if (sConfig->OffsetNumber != ADC_OFFSET_NONE)
8000a42: 692f ldr r7, [r5, #16]
8000a44: 2f04 cmp r7, #4
8000a46: d036 beq.n 8000ab6 <HAL_ADC_ConfigChannel+0x166>
LL_ADC_SetOffset(hadc->Instance, sConfig->OffsetNumber, sConfig->Channel, tmpOffsetShifted);
8000a48: 6828 ldr r0, [r5, #0]
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
8000a4a: 3360 adds r3, #96 @ 0x60
MODIFY_REG(*preg,
8000a4c: f853 1027 ldr.w r1, [r3, r7, lsl #2]
8000a50: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
8000a54: f000 40f8 and.w r0, r0, #2080374784 @ 0x7c000000
8000a58: 4302 orrs r2, r0
8000a5a: 430a orrs r2, r1
8000a5c: f843 2027 str.w r2, [r3, r7, lsl #2]
LL_ADC_SetOffsetSignedSaturation(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetSignedSaturation == ENABLE) ? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE : LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
8000a60: 6823 ldr r3, [r4, #0]
8000a62: 6928 ldr r0, [r5, #16]
8000a64: 7e6a ldrb r2, [r5, #25]
8000a66: 2a01 cmp r2, #1
8000a68: d01f beq.n 8000aaa <HAL_ADC_ConfigChannel+0x15a>
8000a6a: 4632 mov r2, r6
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
8000a6c: 3360 adds r3, #96 @ 0x60
MODIFY_REG(*preg, ADC_OFR1_SSATE, OffsetSignedSaturation);
8000a6e: f853 1020 ldr.w r1, [r3, r0, lsl #2]
8000a72: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000
8000a76: 430a orrs r2, r1
8000a78: f843 2020 str.w r2, [r3, r0, lsl #2]
LL_ADC_SetDataRightShift(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetRightShift == ENABLE) ? LL_ADC_OFFSET_RSHIFT_ENABLE : LL_ADC_OFFSET_RSHIFT_DISABLE);
8000a7c: 6820 ldr r0, [r4, #0]
8000a7e: 6929 ldr r1, [r5, #16]
8000a80: 7e2b ldrb r3, [r5, #24]
8000a82: 2b01 cmp r3, #1
8000a84: d014 beq.n 8000ab0 <HAL_ADC_ConfigChannel+0x160>
MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_RSHIFT1 | ADC_CFGR2_RSHIFT2 | ADC_CFGR2_RSHIFT3 | ADC_CFGR2_RSHIFT4), RigthShift << (Offsety & 0x1FUL));
8000a86: 6902 ldr r2, [r0, #16]
8000a88: f422 42f0 bic.w r2, r2, #30720 @ 0x7800
8000a8c: f001 031f and.w r3, r1, #31
8000a90: fa06 f303 lsl.w r3, r6, r3
8000a94: 4313 orrs r3, r2
8000a96: 6103 str r3, [r0, #16]
}
8000a98: e795 b.n 80009c6 <HAL_ADC_ConfigChannel+0x76>
tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset);
8000a9a: 696a ldr r2, [r5, #20]
8000a9c: 68d9 ldr r1, [r3, #12]
8000a9e: 0889 lsrs r1, r1, #2
8000aa0: f001 0104 and.w r1, r1, #4
8000aa4: 0049 lsls r1, r1, #1
8000aa6: 408a lsls r2, r1
8000aa8: e7cb b.n 8000a42 <HAL_ADC_ConfigChannel+0xf2>
LL_ADC_SetOffsetSignedSaturation(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetSignedSaturation == ENABLE) ? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE : LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
8000aaa: f04f 4200 mov.w r2, #2147483648 @ 0x80000000
8000aae: e7dd b.n 8000a6c <HAL_ADC_ConfigChannel+0x11c>
LL_ADC_SetDataRightShift(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetRightShift == ENABLE) ? LL_ADC_OFFSET_RSHIFT_ENABLE : LL_ADC_OFFSET_RSHIFT_DISABLE);
8000ab0: f44f 6600 mov.w r6, #2048 @ 0x800
8000ab4: e7e7 b.n 8000a86 <HAL_ADC_ConfigChannel+0x136>
if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
8000ab6: 6e1a ldr r2, [r3, #96] @ 0x60
8000ab8: f002 42f8 and.w r2, r2, #2080374784 @ 0x7c000000
8000abc: 6829 ldr r1, [r5, #0]
8000abe: ebb2 6f81 cmp.w r2, r1, lsl #26
8000ac2: d01d beq.n 8000b00 <HAL_ADC_ConfigChannel+0x1b0>
if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
8000ac4: 6822 ldr r2, [r4, #0]
8000ac6: 6e53 ldr r3, [r2, #100] @ 0x64
8000ac8: f003 43f8 and.w r3, r3, #2080374784 @ 0x7c000000
8000acc: 6829 ldr r1, [r5, #0]
8000ace: ebb3 6f81 cmp.w r3, r1, lsl #26
8000ad2: d01a beq.n 8000b0a <HAL_ADC_ConfigChannel+0x1ba>
if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
8000ad4: 6822 ldr r2, [r4, #0]
8000ad6: 6e93 ldr r3, [r2, #104] @ 0x68
8000ad8: f003 43f8 and.w r3, r3, #2080374784 @ 0x7c000000
8000adc: 6829 ldr r1, [r5, #0]
8000ade: ebb3 6f81 cmp.w r3, r1, lsl #26
8000ae2: d017 beq.n 8000b14 <HAL_ADC_ConfigChannel+0x1c4>
if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
8000ae4: 6822 ldr r2, [r4, #0]
8000ae6: 6ed3 ldr r3, [r2, #108] @ 0x6c
8000ae8: f003 43f8 and.w r3, r3, #2080374784 @ 0x7c000000
8000aec: 6829 ldr r1, [r5, #0]
8000aee: ebb3 6f81 cmp.w r3, r1, lsl #26
8000af2: f47f af68 bne.w 80009c6 <HAL_ADC_ConfigChannel+0x76>
CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_SSATE);
8000af6: 6ed3 ldr r3, [r2, #108] @ 0x6c
8000af8: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
8000afc: 66d3 str r3, [r2, #108] @ 0x6c
8000afe: e762 b.n 80009c6 <HAL_ADC_ConfigChannel+0x76>
CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_SSATE);
8000b00: 6e1a ldr r2, [r3, #96] @ 0x60
8000b02: f022 4200 bic.w r2, r2, #2147483648 @ 0x80000000
8000b06: 661a str r2, [r3, #96] @ 0x60
8000b08: e7dc b.n 8000ac4 <HAL_ADC_ConfigChannel+0x174>
CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_SSATE);
8000b0a: 6e53 ldr r3, [r2, #100] @ 0x64
8000b0c: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
8000b10: 6653 str r3, [r2, #100] @ 0x64
8000b12: e7df b.n 8000ad4 <HAL_ADC_ConfigChannel+0x184>
CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_SSATE);
8000b14: 6e93 ldr r3, [r2, #104] @ 0x68
8000b16: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
8000b1a: 6693 str r3, [r2, #104] @ 0x68
8000b1c: e7e2 b.n 8000ae4 <HAL_ADC_ConfigChannel+0x194>
LL_ADC_SetChannelSamplingTime(hadc->Instance,
8000b1e: 6820 ldr r0, [r4, #0]
(uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)),
8000b20: 682b ldr r3, [r5, #0]
8000b22: f3c3 0613 ubfx r6, r3, #0, #20
8000b26: bb26 cbnz r6, 8000b72 <HAL_ADC_ConfigChannel+0x222>
8000b28: 0e9a lsrs r2, r3, #26
8000b2a: 3201 adds r2, #1
8000b2c: f002 021f and.w r2, r2, #31
8000b30: 2a09 cmp r2, #9
8000b32: bf8c ite hi
8000b34: 2200 movhi r2, #0
8000b36: 2201 movls r2, #1
LL_ADC_SetChannelSamplingTime(hadc->Instance,
8000b38: 2a00 cmp r2, #0
8000b3a: d051 beq.n 8000be0 <HAL_ADC_ConfigChannel+0x290>
(uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)),
8000b3c: bb46 cbnz r6, 8000b90 <HAL_ADC_ConfigChannel+0x240>
8000b3e: 0e99 lsrs r1, r3, #26
8000b40: 3101 adds r1, #1
8000b42: 0689 lsls r1, r1, #26
8000b44: f001 41f8 and.w r1, r1, #2080374784 @ 0x7c000000
8000b48: bb76 cbnz r6, 8000ba8 <HAL_ADC_ConfigChannel+0x258>
8000b4a: 0e9f lsrs r7, r3, #26
8000b4c: 3701 adds r7, #1
8000b4e: f007 071f and.w r7, r7, #31
8000b52: 2201 movs r2, #1
8000b54: 40ba lsls r2, r7
8000b56: 4311 orrs r1, r2
8000b58: bba6 cbnz r6, 8000bc4 <HAL_ADC_ConfigChannel+0x274>
8000b5a: 0e9b lsrs r3, r3, #26
8000b5c: 3301 adds r3, #1
8000b5e: f003 031f and.w r3, r3, #31
8000b62: eb03 0343 add.w r3, r3, r3, lsl #1
8000b66: 051b lsls r3, r3, #20
LL_ADC_SetChannelSamplingTime(hadc->Instance,
8000b68: 4319 orrs r1, r3
8000b6a: 68aa ldr r2, [r5, #8]
8000b6c: f7ff feda bl 8000924 <LL_ADC_SetChannelSamplingTime>
8000b70: e746 b.n 8000a00 <HAL_ADC_ConfigChannel+0xb0>
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8000b72: fa93 f2a3 rbit r2, r3
if (value == 0U)
8000b76: b14a cbz r2, 8000b8c <HAL_ADC_ConfigChannel+0x23c>
return __builtin_clz(value);
8000b78: fab2 f282 clz r2, r2
(uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)),
8000b7c: 3201 adds r2, #1
8000b7e: f002 021f and.w r2, r2, #31
8000b82: 2a09 cmp r2, #9
8000b84: bf8c ite hi
8000b86: 2200 movhi r2, #0
8000b88: 2201 movls r2, #1
8000b8a: e7d5 b.n 8000b38 <HAL_ADC_ConfigChannel+0x1e8>
return 32U;
8000b8c: 2220 movs r2, #32
8000b8e: e7f5 b.n 8000b7c <HAL_ADC_ConfigChannel+0x22c>
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8000b90: fa93 f1a3 rbit r1, r3
if (value == 0U)
8000b94: b131 cbz r1, 8000ba4 <HAL_ADC_ConfigChannel+0x254>
return __builtin_clz(value);
8000b96: fab1 f181 clz r1, r1
8000b9a: 3101 adds r1, #1
8000b9c: 0689 lsls r1, r1, #26
8000b9e: f001 41f8 and.w r1, r1, #2080374784 @ 0x7c000000
8000ba2: e7d1 b.n 8000b48 <HAL_ADC_ConfigChannel+0x1f8>
return 32U;
8000ba4: 2120 movs r1, #32
8000ba6: e7f8 b.n 8000b9a <HAL_ADC_ConfigChannel+0x24a>
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8000ba8: fa93 f2a3 rbit r2, r3
if (value == 0U)
8000bac: b142 cbz r2, 8000bc0 <HAL_ADC_ConfigChannel+0x270>
return __builtin_clz(value);
8000bae: fab2 f282 clz r2, r2
8000bb2: 3201 adds r2, #1
8000bb4: f002 021f and.w r2, r2, #31
8000bb8: 2701 movs r7, #1
8000bba: fa07 f202 lsl.w r2, r7, r2
8000bbe: e7ca b.n 8000b56 <HAL_ADC_ConfigChannel+0x206>
return 32U;
8000bc0: 2220 movs r2, #32
8000bc2: e7f6 b.n 8000bb2 <HAL_ADC_ConfigChannel+0x262>
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8000bc4: fa93 f3a3 rbit r3, r3
if (value == 0U)
8000bc8: b143 cbz r3, 8000bdc <HAL_ADC_ConfigChannel+0x28c>
return __builtin_clz(value);
8000bca: fab3 f383 clz r3, r3
8000bce: 3301 adds r3, #1
8000bd0: f003 031f and.w r3, r3, #31
8000bd4: eb03 0343 add.w r3, r3, r3, lsl #1
8000bd8: 051b lsls r3, r3, #20
8000bda: e7c5 b.n 8000b68 <HAL_ADC_ConfigChannel+0x218>
return 32U;
8000bdc: 2320 movs r3, #32
8000bde: e7f6 b.n 8000bce <HAL_ADC_ConfigChannel+0x27e>
8000be0: b9ce cbnz r6, 8000c16 <HAL_ADC_ConfigChannel+0x2c6>
8000be2: 0e99 lsrs r1, r3, #26
8000be4: 3101 adds r1, #1
8000be6: 0689 lsls r1, r1, #26
8000be8: f001 41f8 and.w r1, r1, #2080374784 @ 0x7c000000
8000bec: b9fe cbnz r6, 8000c2e <HAL_ADC_ConfigChannel+0x2de>
8000bee: 0e9f lsrs r7, r3, #26
8000bf0: 3701 adds r7, #1
8000bf2: f007 071f and.w r7, r7, #31
8000bf6: 2201 movs r2, #1
8000bf8: 40ba lsls r2, r7
8000bfa: 4311 orrs r1, r2
8000bfc: bb2e cbnz r6, 8000c4a <HAL_ADC_ConfigChannel+0x2fa>
8000bfe: 0e9b lsrs r3, r3, #26
8000c00: 3301 adds r3, #1
8000c02: f003 031f and.w r3, r3, #31
8000c06: eb03 0343 add.w r3, r3, r3, lsl #1
8000c0a: 3b1e subs r3, #30
8000c0c: 051b lsls r3, r3, #20
8000c0e: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000
LL_ADC_SetChannelSamplingTime(hadc->Instance,
8000c12: 4319 orrs r1, r3
8000c14: e7a9 b.n 8000b6a <HAL_ADC_ConfigChannel+0x21a>
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8000c16: fa93 f1a3 rbit r1, r3
if (value == 0U)
8000c1a: b131 cbz r1, 8000c2a <HAL_ADC_ConfigChannel+0x2da>
return __builtin_clz(value);
8000c1c: fab1 f181 clz r1, r1
(uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)),
8000c20: 3101 adds r1, #1
8000c22: 0689 lsls r1, r1, #26
8000c24: f001 41f8 and.w r1, r1, #2080374784 @ 0x7c000000
8000c28: e7e0 b.n 8000bec <HAL_ADC_ConfigChannel+0x29c>
return 32U;
8000c2a: 2120 movs r1, #32
8000c2c: e7f8 b.n 8000c20 <HAL_ADC_ConfigChannel+0x2d0>
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8000c2e: fa93 f2a3 rbit r2, r3
if (value == 0U)
8000c32: b142 cbz r2, 8000c46 <HAL_ADC_ConfigChannel+0x2f6>
return __builtin_clz(value);
8000c34: fab2 f282 clz r2, r2
8000c38: 3201 adds r2, #1
8000c3a: f002 021f and.w r2, r2, #31
8000c3e: 2701 movs r7, #1
8000c40: fa07 f202 lsl.w r2, r7, r2
8000c44: e7d9 b.n 8000bfa <HAL_ADC_ConfigChannel+0x2aa>
return 32U;
8000c46: 2220 movs r2, #32
8000c48: e7f6 b.n 8000c38 <HAL_ADC_ConfigChannel+0x2e8>
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8000c4a: fa93 f3a3 rbit r3, r3
if (value == 0U)
8000c4e: b15b cbz r3, 8000c68 <HAL_ADC_ConfigChannel+0x318>
return __builtin_clz(value);
8000c50: fab3 f383 clz r3, r3
8000c54: 3301 adds r3, #1
8000c56: f003 031f and.w r3, r3, #31
8000c5a: eb03 0343 add.w r3, r3, r3, lsl #1
8000c5e: 3b1e subs r3, #30
8000c60: 051b lsls r3, r3, #20
8000c62: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000
8000c66: e7d4 b.n 8000c12 <HAL_ADC_ConfigChannel+0x2c2>
return 32U;
8000c68: 2320 movs r3, #32
8000c6a: e7f3 b.n 8000c54 <HAL_ADC_ConfigChannel+0x304>
8000c6c: 000fffff .word 0x000fffff
8000c70: 47ff0000 .word 0x47ff0000
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
8000c74: 4a39 ldr r2, [pc, #228] @ (8000d5c <HAL_ADC_ConfigChannel+0x40c>)
8000c76: 6891 ldr r1, [r2, #8]
8000c78: f001 75e0 and.w r5, r1, #29360128 @ 0x1c00000
return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
8000c7c: f5a2 7240 sub.w r2, r2, #768 @ 0x300
8000c80: 6892 ldr r2, [r2, #8]
8000c82: f012 0201 ands.w r2, r2, #1
8000c86: d000 beq.n 8000c8a <HAL_ADC_ConfigChannel+0x33a>
8000c88: 2201 movs r2, #1
8000c8a: 4835 ldr r0, [pc, #212] @ (8000d60 <HAL_ADC_ConfigChannel+0x410>)
8000c8c: 6880 ldr r0, [r0, #8]
8000c8e: f010 0f01 tst.w r0, #1
8000c92: d156 bne.n 8000d42 <HAL_ADC_ConfigChannel+0x3f2>
if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
8000c94: 2a00 cmp r2, #0
8000c96: d154 bne.n 8000d42 <HAL_ADC_ConfigChannel+0x3f2>
if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
8000c98: 4a32 ldr r2, [pc, #200] @ (8000d64 <HAL_ADC_ConfigChannel+0x414>)
8000c9a: 4293 cmp r3, r2
8000c9c: d007 beq.n 8000cae <HAL_ADC_ConfigChannel+0x35e>
else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
8000c9e: 4a32 ldr r2, [pc, #200] @ (8000d68 <HAL_ADC_ConfigChannel+0x418>)
8000ca0: 4293 cmp r3, r2
8000ca2: d028 beq.n 8000cf6 <HAL_ADC_ConfigChannel+0x3a6>
else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
8000ca4: 4a31 ldr r2, [pc, #196] @ (8000d6c <HAL_ADC_ConfigChannel+0x41c>)
8000ca6: 4293 cmp r3, r2
8000ca8: d038 beq.n 8000d1c <HAL_ADC_ConfigChannel+0x3cc>
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
8000caa: 2000 movs r0, #0
8000cac: e668 b.n 8000980 <HAL_ADC_ConfigChannel+0x30>
if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
8000cae: f411 0f00 tst.w r1, #8388608 @ 0x800000
8000cb2: d1f4 bne.n 8000c9e <HAL_ADC_ConfigChannel+0x34e>
if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
8000cb4: 6822 ldr r2, [r4, #0]
8000cb6: 4b2a ldr r3, [pc, #168] @ (8000d60 <HAL_ADC_ConfigChannel+0x410>)
8000cb8: 429a cmp r2, r3
8000cba: d001 beq.n 8000cc0 <HAL_ADC_ConfigChannel+0x370>
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
8000cbc: 2000 movs r0, #0
8000cbe: e65f b.n 8000980 <HAL_ADC_ConfigChannel+0x30>
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel);
8000cc0: f445 0300 orr.w r3, r5, #8388608 @ 0x800000
MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal);
8000cc4: 4925 ldr r1, [pc, #148] @ (8000d5c <HAL_ADC_ConfigChannel+0x40c>)
8000cc6: 688a ldr r2, [r1, #8]
8000cc8: f022 72e0 bic.w r2, r2, #29360128 @ 0x1c00000
8000ccc: 4313 orrs r3, r2
8000cce: 608b str r3, [r1, #8]
wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
8000cd0: 4b27 ldr r3, [pc, #156] @ (8000d70 <HAL_ADC_ConfigChannel+0x420>)
8000cd2: 681b ldr r3, [r3, #0]
8000cd4: 099b lsrs r3, r3, #6
8000cd6: 4a27 ldr r2, [pc, #156] @ (8000d74 <HAL_ADC_ConfigChannel+0x424>)
8000cd8: fba2 2303 umull r2, r3, r2, r3
8000cdc: 099b lsrs r3, r3, #6
8000cde: 3301 adds r3, #1
8000ce0: 005b lsls r3, r3, #1
8000ce2: 9301 str r3, [sp, #4]
while (wait_loop_index != 0UL)
8000ce4: e002 b.n 8000cec <HAL_ADC_ConfigChannel+0x39c>
wait_loop_index--;
8000ce6: 9b01 ldr r3, [sp, #4]
8000ce8: 3b01 subs r3, #1
8000cea: 9301 str r3, [sp, #4]
while (wait_loop_index != 0UL)
8000cec: 9b01 ldr r3, [sp, #4]
8000cee: 2b00 cmp r3, #0
8000cf0: d1f9 bne.n 8000ce6 <HAL_ADC_ConfigChannel+0x396>
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
8000cf2: 2000 movs r0, #0
8000cf4: e644 b.n 8000980 <HAL_ADC_ConfigChannel+0x30>
else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
8000cf6: f011 7f80 tst.w r1, #16777216 @ 0x1000000
8000cfa: d1d3 bne.n 8000ca4 <HAL_ADC_ConfigChannel+0x354>
if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
8000cfc: 6822 ldr r2, [r4, #0]
8000cfe: 4b18 ldr r3, [pc, #96] @ (8000d60 <HAL_ADC_ConfigChannel+0x410>)
8000d00: 429a cmp r2, r3
8000d02: d001 beq.n 8000d08 <HAL_ADC_ConfigChannel+0x3b8>
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
8000d04: 2000 movs r0, #0
8000d06: e63b b.n 8000980 <HAL_ADC_ConfigChannel+0x30>
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
8000d08: f045 7380 orr.w r3, r5, #16777216 @ 0x1000000
8000d0c: 4913 ldr r1, [pc, #76] @ (8000d5c <HAL_ADC_ConfigChannel+0x40c>)
8000d0e: 688a ldr r2, [r1, #8]
8000d10: f022 72e0 bic.w r2, r2, #29360128 @ 0x1c00000
8000d14: 4313 orrs r3, r2
8000d16: 608b str r3, [r1, #8]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
8000d18: 2000 movs r0, #0
}
8000d1a: e631 b.n 8000980 <HAL_ADC_ConfigChannel+0x30>
else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
8000d1c: f411 0f80 tst.w r1, #4194304 @ 0x400000
8000d20: d117 bne.n 8000d52 <HAL_ADC_ConfigChannel+0x402>
if (ADC_VREFINT_INSTANCE(hadc))
8000d22: 6822 ldr r2, [r4, #0]
8000d24: 4b0e ldr r3, [pc, #56] @ (8000d60 <HAL_ADC_ConfigChannel+0x410>)
8000d26: 429a cmp r2, r3
8000d28: d001 beq.n 8000d2e <HAL_ADC_ConfigChannel+0x3de>
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
8000d2a: 2000 movs r0, #0
8000d2c: e628 b.n 8000980 <HAL_ADC_ConfigChannel+0x30>
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel);
8000d2e: f445 0380 orr.w r3, r5, #4194304 @ 0x400000
MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal);
8000d32: 490a ldr r1, [pc, #40] @ (8000d5c <HAL_ADC_ConfigChannel+0x40c>)
8000d34: 688a ldr r2, [r1, #8]
8000d36: f022 72e0 bic.w r2, r2, #29360128 @ 0x1c00000
8000d3a: 4313 orrs r3, r2
8000d3c: 608b str r3, [r1, #8]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
8000d3e: 2000 movs r0, #0
}
8000d40: e61e b.n 8000980 <HAL_ADC_ConfigChannel+0x30>
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8000d42: 6d63 ldr r3, [r4, #84] @ 0x54
8000d44: f043 0320 orr.w r3, r3, #32
8000d48: 6563 str r3, [r4, #84] @ 0x54
tmp_hal_status = HAL_ERROR;
8000d4a: 2001 movs r0, #1
8000d4c: e618 b.n 8000980 <HAL_ADC_ConfigChannel+0x30>
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
8000d4e: 2000 movs r0, #0
8000d50: e616 b.n 8000980 <HAL_ADC_ConfigChannel+0x30>
8000d52: 2000 movs r0, #0
8000d54: e614 b.n 8000980 <HAL_ADC_ConfigChannel+0x30>
__HAL_LOCK(hadc);
8000d56: 2002 movs r0, #2
8000d58: e615 b.n 8000986 <HAL_ADC_ConfigChannel+0x36>
8000d5a: bf00 nop
8000d5c: 40022300 .word 0x40022300
8000d60: 40022100 .word 0x40022100
8000d64: cb840000 .word 0xcb840000
8000d68: bac04000 .word 0xbac04000
8000d6c: cfb80000 .word 0xcfb80000
8000d70: 2000000c .word 0x2000000c
8000d74: 053e2d63 .word 0x053e2d63
08000d78 <ADC_ConfigureBoostMode>:
* stopped.
* @param hadc ADC handle
* @retval None.
*/
void ADC_ConfigureBoostMode(ADC_HandleTypeDef *hadc)
{
8000d78: b510 push {r4, lr}
8000d7a: 4604 mov r4, r0
uint32_t freq;
if (ADC_IS_SYNCHRONOUS_CLOCK_MODE(hadc))
8000d7c: 4b3a ldr r3, [pc, #232] @ (8000e68 <ADC_ConfigureBoostMode+0xf0>)
8000d7e: 689b ldr r3, [r3, #8]
8000d80: f413 3f40 tst.w r3, #196608 @ 0x30000
8000d84: d019 beq.n 8000dba <ADC_ConfigureBoostMode+0x42>
{
freq = HAL_RCC_GetHCLKFreq();
8000d86: f001 fecf bl 8002b28 <HAL_RCC_GetHCLKFreq>
switch (hadc->Init.ClockPrescaler)
8000d8a: 6863 ldr r3, [r4, #4]
8000d8c: f5b3 3f00 cmp.w r3, #131072 @ 0x20000
8000d90: d005 beq.n 8000d9e <ADC_ConfigureBoostMode+0x26>
8000d92: f5b3 3f40 cmp.w r3, #196608 @ 0x30000
8000d96: d00e beq.n 8000db6 <ADC_ConfigureBoostMode+0x3e>
8000d98: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8000d9c: d102 bne.n 8000da4 <ADC_ConfigureBoostMode+0x2c>
{
case ADC_CLOCK_SYNC_PCLK_DIV1:
case ADC_CLOCK_SYNC_PCLK_DIV2:
freq /= (hadc->Init.ClockPrescaler >> ADC_CCR_CKMODE_Pos);
8000d9e: 0c1b lsrs r3, r3, #16
8000da0: fbb0 f0f3 udiv r0, r0, r3
}
}
#if defined(ADC_VER_V5_3) || defined(ADC_VER_V5_V90)
freq /= 2U;
if (freq <= 6250000UL)
8000da4: 4b31 ldr r3, [pc, #196] @ (8000e6c <ADC_ConfigureBoostMode+0xf4>)
8000da6: 4298 cmp r0, r3
8000da8: d841 bhi.n 8000e2e <ADC_ConfigureBoostMode+0xb6>
{
MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, 0UL);
8000daa: 6822 ldr r2, [r4, #0]
8000dac: 6893 ldr r3, [r2, #8]
8000dae: f423 7340 bic.w r3, r3, #768 @ 0x300
8000db2: 6093 str r3, [r2, #8]
{
MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0);
}
}
#endif /* ADC_VER_V5_3 */
}
8000db4: bd10 pop {r4, pc}
freq /= 4UL;
8000db6: 0880 lsrs r0, r0, #2
break;
8000db8: e7f4 b.n 8000da4 <ADC_ConfigureBoostMode+0x2c>
freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC);
8000dba: f44f 2000 mov.w r0, #524288 @ 0x80000
8000dbe: 2100 movs r1, #0
8000dc0: f003 f82a bl 8003e18 <HAL_RCCEx_GetPeriphCLKFreq>
switch (hadc->Init.ClockPrescaler)
8000dc4: 6863 ldr r3, [r4, #4]
8000dc6: f5b3 1f10 cmp.w r3, #2359296 @ 0x240000
8000dca: d02c beq.n 8000e26 <ADC_ConfigureBoostMode+0xae>
8000dcc: d821 bhi.n 8000e12 <ADC_ConfigureBoostMode+0x9a>
8000dce: f5b3 1fe0 cmp.w r3, #1835008 @ 0x1c0000
8000dd2: d026 beq.n 8000e22 <ADC_ConfigureBoostMode+0xaa>
8000dd4: d904 bls.n 8000de0 <ADC_ConfigureBoostMode+0x68>
8000dd6: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000
8000dda: d1e3 bne.n 8000da4 <ADC_ConfigureBoostMode+0x2c>
freq /= 32UL;
8000ddc: 0940 lsrs r0, r0, #5
break;
8000dde: e7e1 b.n 8000da4 <ADC_ConfigureBoostMode+0x2c>
switch (hadc->Init.ClockPrescaler)
8000de0: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
8000de4: d010 beq.n 8000e08 <ADC_ConfigureBoostMode+0x90>
8000de6: d809 bhi.n 8000dfc <ADC_ConfigureBoostMode+0x84>
8000de8: f5b3 2f00 cmp.w r3, #524288 @ 0x80000
8000dec: d00c beq.n 8000e08 <ADC_ConfigureBoostMode+0x90>
8000dee: f5b3 2f40 cmp.w r3, #786432 @ 0xc0000
8000df2: d009 beq.n 8000e08 <ADC_ConfigureBoostMode+0x90>
8000df4: f5b3 2f80 cmp.w r3, #262144 @ 0x40000
8000df8: d006 beq.n 8000e08 <ADC_ConfigureBoostMode+0x90>
8000dfa: e7d3 b.n 8000da4 <ADC_ConfigureBoostMode+0x2c>
8000dfc: f5b3 1fa0 cmp.w r3, #1310720 @ 0x140000
8000e00: d002 beq.n 8000e08 <ADC_ConfigureBoostMode+0x90>
8000e02: f5b3 1fc0 cmp.w r3, #1572864 @ 0x180000
8000e06: d1cd bne.n 8000da4 <ADC_ConfigureBoostMode+0x2c>
freq /= ((hadc->Init.ClockPrescaler >> ADC_CCR_PRESC_Pos) << 1UL);
8000e08: 0c9b lsrs r3, r3, #18
8000e0a: 005b lsls r3, r3, #1
8000e0c: fbb0 f0f3 udiv r0, r0, r3
break;
8000e10: e7c8 b.n 8000da4 <ADC_ConfigureBoostMode+0x2c>
switch (hadc->Init.ClockPrescaler)
8000e12: f5b3 1f20 cmp.w r3, #2621440 @ 0x280000
8000e16: d008 beq.n 8000e2a <ADC_ConfigureBoostMode+0xb2>
8000e18: f5b3 1f30 cmp.w r3, #2883584 @ 0x2c0000
8000e1c: d1c2 bne.n 8000da4 <ADC_ConfigureBoostMode+0x2c>
freq /= 256UL;
8000e1e: 0a00 lsrs r0, r0, #8
break;
8000e20: e7c0 b.n 8000da4 <ADC_ConfigureBoostMode+0x2c>
freq /= 16UL;
8000e22: 0900 lsrs r0, r0, #4
break;
8000e24: e7be b.n 8000da4 <ADC_ConfigureBoostMode+0x2c>
freq /= 64UL;
8000e26: 0980 lsrs r0, r0, #6
break;
8000e28: e7bc b.n 8000da4 <ADC_ConfigureBoostMode+0x2c>
freq /= 128UL;
8000e2a: 09c0 lsrs r0, r0, #7
break;
8000e2c: e7ba b.n 8000da4 <ADC_ConfigureBoostMode+0x2c>
else if (freq <= 12500000UL)
8000e2e: 4b10 ldr r3, [pc, #64] @ (8000e70 <ADC_ConfigureBoostMode+0xf8>)
8000e30: 4298 cmp r0, r3
8000e32: d807 bhi.n 8000e44 <ADC_ConfigureBoostMode+0xcc>
MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_0);
8000e34: 6822 ldr r2, [r4, #0]
8000e36: 6893 ldr r3, [r2, #8]
8000e38: f423 7340 bic.w r3, r3, #768 @ 0x300
8000e3c: f443 7380 orr.w r3, r3, #256 @ 0x100
8000e40: 6093 str r3, [r2, #8]
8000e42: e7b7 b.n 8000db4 <ADC_ConfigureBoostMode+0x3c>
else if (freq <= 25000000UL)
8000e44: 4b0b ldr r3, [pc, #44] @ (8000e74 <ADC_ConfigureBoostMode+0xfc>)
8000e46: 4298 cmp r0, r3
8000e48: d807 bhi.n 8000e5a <ADC_ConfigureBoostMode+0xe2>
MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1);
8000e4a: 6822 ldr r2, [r4, #0]
8000e4c: 6893 ldr r3, [r2, #8]
8000e4e: f423 7340 bic.w r3, r3, #768 @ 0x300
8000e52: f443 7300 orr.w r3, r3, #512 @ 0x200
8000e56: 6093 str r3, [r2, #8]
8000e58: e7ac b.n 8000db4 <ADC_ConfigureBoostMode+0x3c>
MODIFY_REG(hadc->Instance->CR, ADC_CR_BOOST, ADC_CR_BOOST_1 | ADC_CR_BOOST_0);
8000e5a: 6822 ldr r2, [r4, #0]
8000e5c: 6893 ldr r3, [r2, #8]
8000e5e: f443 7340 orr.w r3, r3, #768 @ 0x300
8000e62: 6093 str r3, [r2, #8]
}
8000e64: e7a6 b.n 8000db4 <ADC_ConfigureBoostMode+0x3c>
8000e66: bf00 nop
8000e68: 40022300 .word 0x40022300
8000e6c: 00bebc21 .word 0x00bebc21
8000e70: 017d7841 .word 0x017d7841
8000e74: 02faf081 .word 0x02faf081
08000e78 <HAL_ADC_Init>:
{
8000e78: b530 push {r4, r5, lr}
8000e7a: b083 sub sp, #12
__IO uint32_t wait_loop_index = 0UL;
8000e7c: 2300 movs r3, #0
8000e7e: 9301 str r3, [sp, #4]
if (hadc == NULL)
8000e80: 2800 cmp r0, #0
8000e82: f000 80df beq.w 8001044 <HAL_ADC_Init+0x1cc>
8000e86: 4604 mov r4, r0
if (hadc->State == HAL_ADC_STATE_RESET)
8000e88: 6d43 ldr r3, [r0, #84] @ 0x54
8000e8a: b1eb cbz r3, 8000ec8 <HAL_ADC_Init+0x50>
if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL)
8000e8c: 6823 ldr r3, [r4, #0]
return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);
8000e8e: 689a ldr r2, [r3, #8]
8000e90: f012 5f00 tst.w r2, #536870912 @ 0x20000000
8000e94: d003 beq.n 8000e9e <HAL_ADC_Init+0x26>
CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));
8000e96: 6899 ldr r1, [r3, #8]
8000e98: 4a6b ldr r2, [pc, #428] @ (8001048 <HAL_ADC_Init+0x1d0>)
8000e9a: 400a ands r2, r1
8000e9c: 609a str r2, [r3, #8]
if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
8000e9e: 6823 ldr r3, [r4, #0]
return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
8000ea0: 689a ldr r2, [r3, #8]
8000ea2: f012 5f80 tst.w r2, #268435456 @ 0x10000000
8000ea6: d11c bne.n 8000ee2 <HAL_ADC_Init+0x6a>
MODIFY_REG(ADCx->CR,
8000ea8: 6899 ldr r1, [r3, #8]
8000eaa: 4a68 ldr r2, [pc, #416] @ (800104c <HAL_ADC_Init+0x1d4>)
8000eac: 400a ands r2, r1
8000eae: f042 5280 orr.w r2, r2, #268435456 @ 0x10000000
8000eb2: 609a str r2, [r3, #8]
wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
8000eb4: 4b66 ldr r3, [pc, #408] @ (8001050 <HAL_ADC_Init+0x1d8>)
8000eb6: 681b ldr r3, [r3, #0]
8000eb8: 099b lsrs r3, r3, #6
8000eba: 4a66 ldr r2, [pc, #408] @ (8001054 <HAL_ADC_Init+0x1dc>)
8000ebc: fba2 2303 umull r2, r3, r2, r3
8000ec0: 099b lsrs r3, r3, #6
8000ec2: 3301 adds r3, #1
8000ec4: 9301 str r3, [sp, #4]
while (wait_loop_index != 0UL)
8000ec6: e009 b.n 8000edc <HAL_ADC_Init+0x64>
HAL_ADC_MspInit(hadc);
8000ec8: f000 fed0 bl 8001c6c <HAL_ADC_MspInit>
ADC_CLEAR_ERRORCODE(hadc);
8000ecc: 2300 movs r3, #0
8000ece: 65a3 str r3, [r4, #88] @ 0x58
hadc->Lock = HAL_UNLOCKED;
8000ed0: f884 3050 strb.w r3, [r4, #80] @ 0x50
8000ed4: e7da b.n 8000e8c <HAL_ADC_Init+0x14>
wait_loop_index--;
8000ed6: 9b01 ldr r3, [sp, #4]
8000ed8: 3b01 subs r3, #1
8000eda: 9301 str r3, [sp, #4]
while (wait_loop_index != 0UL)
8000edc: 9b01 ldr r3, [sp, #4]
8000ede: 2b00 cmp r3, #0
8000ee0: d1f9 bne.n 8000ed6 <HAL_ADC_Init+0x5e>
if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
8000ee2: 6822 ldr r2, [r4, #0]
return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
8000ee4: 6893 ldr r3, [r2, #8]
8000ee6: f013 5f80 tst.w r3, #268435456 @ 0x10000000
8000eea: f040 8081 bne.w 8000ff0 <HAL_ADC_Init+0x178>
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8000eee: 6d63 ldr r3, [r4, #84] @ 0x54
8000ef0: f043 0310 orr.w r3, r3, #16
8000ef4: 6563 str r3, [r4, #84] @ 0x54
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8000ef6: 6da3 ldr r3, [r4, #88] @ 0x58
8000ef8: f043 0301 orr.w r3, r3, #1
8000efc: 65a3 str r3, [r4, #88] @ 0x58
tmp_hal_status = HAL_ERROR;
8000efe: 2501 movs r5, #1
return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
8000f00: 6893 ldr r3, [r2, #8]
8000f02: f013 0304 ands.w r3, r3, #4
8000f06: d000 beq.n 8000f0a <HAL_ADC_Init+0x92>
8000f08: 2301 movs r3, #1
if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
8000f0a: 6d61 ldr r1, [r4, #84] @ 0x54
8000f0c: f011 0f10 tst.w r1, #16
8000f10: f040 8090 bne.w 8001034 <HAL_ADC_Init+0x1bc>
&& (tmp_adc_reg_is_conversion_on_going == 0UL)
8000f14: 2b00 cmp r3, #0
8000f16: f040 808d bne.w 8001034 <HAL_ADC_Init+0x1bc>
ADC_STATE_CLR_SET(hadc->State,
8000f1a: 6d63 ldr r3, [r4, #84] @ 0x54
8000f1c: f423 7381 bic.w r3, r3, #258 @ 0x102
8000f20: f043 0302 orr.w r3, r3, #2
8000f24: 6563 str r3, [r4, #84] @ 0x54
return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
8000f26: 6893 ldr r3, [r2, #8]
8000f28: f013 0f01 tst.w r3, #1
8000f2c: d112 bne.n 8000f54 <HAL_ADC_Init+0xdc>
8000f2e: 4b4a ldr r3, [pc, #296] @ (8001058 <HAL_ADC_Init+0x1e0>)
8000f30: 689b ldr r3, [r3, #8]
8000f32: f013 0301 ands.w r3, r3, #1
8000f36: d000 beq.n 8000f3a <HAL_ADC_Init+0xc2>
8000f38: 2301 movs r3, #1
8000f3a: 4a48 ldr r2, [pc, #288] @ (800105c <HAL_ADC_Init+0x1e4>)
8000f3c: 6892 ldr r2, [r2, #8]
8000f3e: f012 0f01 tst.w r2, #1
8000f42: d107 bne.n 8000f54 <HAL_ADC_Init+0xdc>
if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
8000f44: b933 cbnz r3, 8000f54 <HAL_ADC_Init+0xdc>
LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler);
8000f46: 6863 ldr r3, [r4, #4]
MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);
8000f48: 4945 ldr r1, [pc, #276] @ (8001060 <HAL_ADC_Init+0x1e8>)
8000f4a: 688a ldr r2, [r1, #8]
8000f4c: f422 127c bic.w r2, r2, #4128768 @ 0x3f0000
8000f50: 4313 orrs r3, r2
8000f52: 608b str r3, [r1, #8]
tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
8000f54: 7d62 ldrb r2, [r4, #21]
hadc->Init.Overrun |
8000f56: 6b23 ldr r3, [r4, #48] @ 0x30
tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
8000f58: ea43 3342 orr.w r3, r3, r2, lsl #13
hadc->Init.Resolution |
8000f5c: 68a2 ldr r2, [r4, #8]
hadc->Init.Overrun |
8000f5e: 4313 orrs r3, r2
ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode));
8000f60: 7f22 ldrb r2, [r4, #28]
tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
8000f62: ea43 4302 orr.w r3, r3, r2, lsl #16
if (hadc->Init.DiscontinuousConvMode == ENABLE)
8000f66: 2a01 cmp r2, #1
8000f68: d044 beq.n 8000ff4 <HAL_ADC_Init+0x17c>
if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
8000f6a: 6a62 ldr r2, [r4, #36] @ 0x24
8000f6c: b122 cbz r2, 8000f78 <HAL_ADC_Init+0x100>
tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL)
8000f6e: f402 7278 and.w r2, r2, #992 @ 0x3e0
| hadc->Init.ExternalTrigConvEdge
8000f72: 6aa1 ldr r1, [r4, #40] @ 0x28
8000f74: 430a orrs r2, r1
tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL)
8000f76: 4313 orrs r3, r2
MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR);
8000f78: 6821 ldr r1, [r4, #0]
8000f7a: 68c8 ldr r0, [r1, #12]
8000f7c: 4a39 ldr r2, [pc, #228] @ (8001064 <HAL_ADC_Init+0x1ec>)
8000f7e: 4002 ands r2, r0
8000f80: 431a orrs r2, r3
8000f82: 60ca str r2, [r1, #12]
tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
8000f84: 6822 ldr r2, [r4, #0]
return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
8000f86: 6893 ldr r3, [r2, #8]
8000f88: f013 0304 ands.w r3, r3, #4
8000f8c: d000 beq.n 8000f90 <HAL_ADC_Init+0x118>
8000f8e: 2301 movs r3, #1
return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
8000f90: 6891 ldr r1, [r2, #8]
8000f92: f011 0f08 tst.w r1, #8
8000f96: d11c bne.n 8000fd2 <HAL_ADC_Init+0x15a>
if ((tmp_adc_is_conversion_on_going_regular == 0UL)
8000f98: b9db cbnz r3, 8000fd2 <HAL_ADC_Init+0x15a>
ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
8000f9a: 7d21 ldrb r1, [r4, #20]
ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.ConversionDataManagement));
8000f9c: 6ae3 ldr r3, [r4, #44] @ 0x2c
tmpCFGR = (
8000f9e: ea43 3181 orr.w r1, r3, r1, lsl #14
MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR);
8000fa2: 68d0 ldr r0, [r2, #12]
8000fa4: 4b30 ldr r3, [pc, #192] @ (8001068 <HAL_ADC_Init+0x1f0>)
8000fa6: 4003 ands r3, r0
8000fa8: 430b orrs r3, r1
8000faa: 60d3 str r3, [r2, #12]
if (hadc->Init.OversamplingMode == ENABLE)
8000fac: f894 3038 ldrb.w r3, [r4, #56] @ 0x38
8000fb0: 2b01 cmp r3, #1
8000fb2: d024 beq.n 8000ffe <HAL_ADC_Init+0x186>
CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE);
8000fb4: 6822 ldr r2, [r4, #0]
8000fb6: 6913 ldr r3, [r2, #16]
8000fb8: f023 0301 bic.w r3, r3, #1
8000fbc: 6113 str r3, [r2, #16]
MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_LSHIFT, hadc->Init.LeftBitShift);
8000fbe: 6822 ldr r2, [r4, #0]
8000fc0: 6913 ldr r3, [r2, #16]
8000fc2: f023 4370 bic.w r3, r3, #4026531840 @ 0xf0000000
8000fc6: 6b61 ldr r1, [r4, #52] @ 0x34
8000fc8: 430b orrs r3, r1
8000fca: 6113 str r3, [r2, #16]
ADC_ConfigureBoostMode(hadc);
8000fcc: 4620 mov r0, r4
8000fce: f7ff fed3 bl 8000d78 <ADC_ConfigureBoostMode>
if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
8000fd2: 68e3 ldr r3, [r4, #12]
8000fd4: 2b01 cmp r3, #1
8000fd6: d024 beq.n 8001022 <HAL_ADC_Init+0x1aa>
CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L);
8000fd8: 6822 ldr r2, [r4, #0]
8000fda: 6b13 ldr r3, [r2, #48] @ 0x30
8000fdc: f023 030f bic.w r3, r3, #15
8000fe0: 6313 str r3, [r2, #48] @ 0x30
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
8000fe2: 6d63 ldr r3, [r4, #84] @ 0x54
8000fe4: f023 0303 bic.w r3, r3, #3
8000fe8: f043 0301 orr.w r3, r3, #1
8000fec: 6563 str r3, [r4, #84] @ 0x54
8000fee: e026 b.n 800103e <HAL_ADC_Init+0x1c6>
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
8000ff0: 2500 movs r5, #0
8000ff2: e785 b.n 8000f00 <HAL_ADC_Init+0x88>
tmpCFGR |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion);
8000ff4: 6a22 ldr r2, [r4, #32]
8000ff6: 3a01 subs r2, #1
8000ff8: ea43 4342 orr.w r3, r3, r2, lsl #17
8000ffc: e7b5 b.n 8000f6a <HAL_ADC_Init+0xf2>
MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_FIELDS,
8000ffe: 6820 ldr r0, [r4, #0]
8001000: 6902 ldr r2, [r0, #16]
8001002: 4b1a ldr r3, [pc, #104] @ (800106c <HAL_ADC_Init+0x1f4>)
8001004: 4013 ands r3, r2
8001006: 6be2 ldr r2, [r4, #60] @ 0x3c
8001008: 1e51 subs r1, r2, #1
800100a: 6c22 ldr r2, [r4, #64] @ 0x40
800100c: ea42 4201 orr.w r2, r2, r1, lsl #16
8001010: 6c61 ldr r1, [r4, #68] @ 0x44
8001012: 430a orrs r2, r1
8001014: 6ca1 ldr r1, [r4, #72] @ 0x48
8001016: 430a orrs r2, r1
8001018: 4313 orrs r3, r2
800101a: f043 0301 orr.w r3, r3, #1
800101e: 6103 str r3, [r0, #16]
8001020: e7cd b.n 8000fbe <HAL_ADC_Init+0x146>
MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1));
8001022: 6821 ldr r1, [r4, #0]
8001024: 6b0b ldr r3, [r1, #48] @ 0x30
8001026: f023 030f bic.w r3, r3, #15
800102a: 69a2 ldr r2, [r4, #24]
800102c: 3a01 subs r2, #1
800102e: 4313 orrs r3, r2
8001030: 630b str r3, [r1, #48] @ 0x30
8001032: e7d6 b.n 8000fe2 <HAL_ADC_Init+0x16a>
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8001034: 6d63 ldr r3, [r4, #84] @ 0x54
8001036: f043 0310 orr.w r3, r3, #16
800103a: 6563 str r3, [r4, #84] @ 0x54
tmp_hal_status = HAL_ERROR;
800103c: 2501 movs r5, #1
}
800103e: 4628 mov r0, r5
8001040: b003 add sp, #12
8001042: bd30 pop {r4, r5, pc}
return HAL_ERROR;
8001044: 2501 movs r5, #1
8001046: e7fa b.n 800103e <HAL_ADC_Init+0x1c6>
8001048: 5fffffc0 .word 0x5fffffc0
800104c: 6fffffc0 .word 0x6fffffc0
8001050: 2000000c .word 0x2000000c
8001054: 053e2d63 .word 0x053e2d63
8001058: 40022000 .word 0x40022000
800105c: 40022100 .word 0x40022100
8001060: 40022300 .word 0x40022300
8001064: fff0c003 .word 0xfff0c003
8001068: ffffbffc .word 0xffffbffc
800106c: fc00f81e .word 0xfc00f81e
08001070 <HAL_ADCEx_MultiModeConfigChannel>:
assert_param(IS_ADC_DUAL_DATA_MODE(multimode->DualModeData));
assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));
}
/* Process locked */
__HAL_LOCK(hadc);
8001070: f890 2050 ldrb.w r2, [r0, #80] @ 0x50
8001074: 2a01 cmp r2, #1
8001076: d078 beq.n 800116a <HAL_ADCEx_MultiModeConfigChannel+0xfa>
{
8001078: b410 push {r4}
800107a: b09b sub sp, #108 @ 0x6c
800107c: 4603 mov r3, r0
__HAL_LOCK(hadc);
800107e: 2201 movs r2, #1
8001080: f880 2050 strb.w r2, [r0, #80] @ 0x50
tmphadcSlave.State = HAL_ADC_STATE_RESET;
8001084: 2200 movs r2, #0
8001086: 9216 str r2, [sp, #88] @ 0x58
tmphadcSlave.ErrorCode = HAL_ADC_ERROR_NONE;
8001088: 9217 str r2, [sp, #92] @ 0x5c
ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
800108a: 6800 ldr r0, [r0, #0]
800108c: 4a38 ldr r2, [pc, #224] @ (8001170 <HAL_ADCEx_MultiModeConfigChannel+0x100>)
800108e: 4290 cmp r0, r2
8001090: d031 beq.n 80010f6 <HAL_ADCEx_MultiModeConfigChannel+0x86>
8001092: 2200 movs r2, #0
8001094: 9201 str r2, [sp, #4]
if (tmphadcSlave.Instance == NULL)
8001096: 9a01 ldr r2, [sp, #4]
8001098: 2a00 cmp r2, #0
800109a: d030 beq.n 80010fe <HAL_ADCEx_MultiModeConfigChannel+0x8e>
return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
800109c: 6892 ldr r2, [r2, #8]
800109e: f012 0204 ands.w r2, r2, #4
80010a2: d000 beq.n 80010a6 <HAL_ADCEx_MultiModeConfigChannel+0x36>
80010a4: 2201 movs r2, #1
80010a6: 6880 ldr r0, [r0, #8]
80010a8: f010 0f04 tst.w r0, #4
80010ac: d149 bne.n 8001142 <HAL_ADCEx_MultiModeConfigChannel+0xd2>
/* Parameters that can be updated when ADC is disabled or enabled without */
/* conversion on going on regular group: */
/* - Multimode DATA Format configuration */
tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance);
if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
&& (tmphadcSlave_conversion_on_going == 0UL))
80010ae: 2a00 cmp r2, #0
80010b0: d147 bne.n 8001142 <HAL_ADCEx_MultiModeConfigChannel+0xd2>
tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
/* If multimode is selected, configure all multimode parameters. */
/* Otherwise, reset multimode parameters (can be used in case of */
/* transition from multimode to independent mode). */
if (multimode->Mode != ADC_MODE_INDEPENDENT)
80010b2: 680a ldr r2, [r1, #0]
80010b4: b362 cbz r2, 8001110 <HAL_ADCEx_MultiModeConfigChannel+0xa0>
{
MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_DAMDF, multimode->DualModeData);
80010b6: 482f ldr r0, [pc, #188] @ (8001174 <HAL_ADCEx_MultiModeConfigChannel+0x104>)
80010b8: 6882 ldr r2, [r0, #8]
80010ba: f422 4240 bic.w r2, r2, #49152 @ 0xc000
80010be: 684c ldr r4, [r1, #4]
80010c0: 4322 orrs r2, r4
80010c2: 6082 str r2, [r0, #8]
return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
80010c4: 4a2a ldr r2, [pc, #168] @ (8001170 <HAL_ADCEx_MultiModeConfigChannel+0x100>)
80010c6: 6892 ldr r2, [r2, #8]
80010c8: f012 0201 ands.w r2, r2, #1
80010cc: d000 beq.n 80010d0 <HAL_ADCEx_MultiModeConfigChannel+0x60>
80010ce: 2201 movs r2, #1
80010d0: 4829 ldr r0, [pc, #164] @ (8001178 <HAL_ADCEx_MultiModeConfigChannel+0x108>)
80010d2: 6880 ldr r0, [r0, #8]
80010d4: f010 0f01 tst.w r0, #1
80010d8: d13f bne.n 800115a <HAL_ADCEx_MultiModeConfigChannel+0xea>
/* from 1 to 8 clock cycles for 12 bits */
/* from 1 to 6 clock cycles for 10 and 8 bits */
/* If a higher delay is selected, it will be clipped to maximum delay */
/* range */
if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
80010da: 2a00 cmp r2, #0
80010dc: d13f bne.n 800115e <HAL_ADCEx_MultiModeConfigChannel+0xee>
{
MODIFY_REG(tmpADC_Common->CCR,
80010de: 4c25 ldr r4, [pc, #148] @ (8001174 <HAL_ADCEx_MultiModeConfigChannel+0x104>)
80010e0: 68a0 ldr r0, [r4, #8]
80010e2: f5a2 6272 sub.w r2, r2, #3872 @ 0xf20
80010e6: 4002 ands r2, r0
80010e8: 6808 ldr r0, [r1, #0]
80010ea: 6889 ldr r1, [r1, #8]
80010ec: 4301 orrs r1, r0
80010ee: 430a orrs r2, r1
80010f0: 60a2 str r2, [r4, #8]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
80010f2: 2000 movs r0, #0
80010f4: e02a b.n 800114c <HAL_ADCEx_MultiModeConfigChannel+0xdc>
ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
80010f6: f502 7280 add.w r2, r2, #256 @ 0x100
80010fa: 9201 str r2, [sp, #4]
80010fc: e7cb b.n 8001096 <HAL_ADCEx_MultiModeConfigChannel+0x26>
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
80010fe: 6d5a ldr r2, [r3, #84] @ 0x54
8001100: f042 0220 orr.w r2, r2, #32
8001104: 655a str r2, [r3, #84] @ 0x54
__HAL_UNLOCK(hadc);
8001106: 2200 movs r2, #0
8001108: f883 2050 strb.w r2, [r3, #80] @ 0x50
return HAL_ERROR;
800110c: 2001 movs r0, #1
800110e: e020 b.n 8001152 <HAL_ADCEx_MultiModeConfigChannel+0xe2>
);
}
}
else /* ADC_MODE_INDEPENDENT */
{
CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DAMDF);
8001110: 4918 ldr r1, [pc, #96] @ (8001174 <HAL_ADCEx_MultiModeConfigChannel+0x104>)
8001112: 688a ldr r2, [r1, #8]
8001114: f422 4240 bic.w r2, r2, #49152 @ 0xc000
8001118: 608a str r2, [r1, #8]
800111a: 4a15 ldr r2, [pc, #84] @ (8001170 <HAL_ADCEx_MultiModeConfigChannel+0x100>)
800111c: 6892 ldr r2, [r2, #8]
800111e: f012 0201 ands.w r2, r2, #1
8001122: d000 beq.n 8001126 <HAL_ADCEx_MultiModeConfigChannel+0xb6>
8001124: 2201 movs r2, #1
8001126: 4914 ldr r1, [pc, #80] @ (8001178 <HAL_ADCEx_MultiModeConfigChannel+0x108>)
8001128: 6889 ldr r1, [r1, #8]
800112a: f011 0f01 tst.w r1, #1
800112e: d118 bne.n 8001162 <HAL_ADCEx_MultiModeConfigChannel+0xf2>
/* Parameters that can be updated only when ADC is disabled: */
/* - Multimode mode selection */
/* - Multimode delay */
if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
8001130: b9ca cbnz r2, 8001166 <HAL_ADCEx_MultiModeConfigChannel+0xf6>
{
CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY);
8001132: 4910 ldr r1, [pc, #64] @ (8001174 <HAL_ADCEx_MultiModeConfigChannel+0x104>)
8001134: 6888 ldr r0, [r1, #8]
8001136: f5a2 6272 sub.w r2, r2, #3872 @ 0xf20
800113a: 4002 ands r2, r0
800113c: 608a str r2, [r1, #8]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
800113e: 2000 movs r0, #0
8001140: e004 b.n 800114c <HAL_ADCEx_MultiModeConfigChannel+0xdc>
/* If one of the ADC sharing the same common group is enabled, no update */
/* could be done on neither of the multimode structure parameters. */
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8001142: 6d5a ldr r2, [r3, #84] @ 0x54
8001144: f042 0220 orr.w r2, r2, #32
8001148: 655a str r2, [r3, #84] @ 0x54
tmp_hal_status = HAL_ERROR;
800114a: 2001 movs r0, #1
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
800114c: 2200 movs r2, #0
800114e: f883 2050 strb.w r2, [r3, #80] @ 0x50
/* Return function status */
return tmp_hal_status;
}
8001152: b01b add sp, #108 @ 0x6c
8001154: f85d 4b04 ldr.w r4, [sp], #4
8001158: 4770 bx lr
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
800115a: 2000 movs r0, #0
800115c: e7f6 b.n 800114c <HAL_ADCEx_MultiModeConfigChannel+0xdc>
800115e: 2000 movs r0, #0
8001160: e7f4 b.n 800114c <HAL_ADCEx_MultiModeConfigChannel+0xdc>
8001162: 2000 movs r0, #0
8001164: e7f2 b.n 800114c <HAL_ADCEx_MultiModeConfigChannel+0xdc>
8001166: 2000 movs r0, #0
8001168: e7f0 b.n 800114c <HAL_ADCEx_MultiModeConfigChannel+0xdc>
__HAL_LOCK(hadc);
800116a: 2002 movs r0, #2
}
800116c: 4770 bx lr
800116e: bf00 nop
8001170: 40022000 .word 0x40022000
8001174: 40022300 .word 0x40022300
8001178: 40022100 .word 0x40022100
0800117c <__NVIC_EnableIRQ>:
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
800117c: 2800 cmp r0, #0
800117e: db07 blt.n 8001190 <__NVIC_EnableIRQ+0x14>
{
__COMPILER_BARRIER();
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
8001180: f000 021f and.w r2, r0, #31
8001184: 0940 lsrs r0, r0, #5
8001186: 2301 movs r3, #1
8001188: 4093 lsls r3, r2
800118a: 4a02 ldr r2, [pc, #8] @ (8001194 <__NVIC_EnableIRQ+0x18>)
800118c: f842 3020 str.w r3, [r2, r0, lsl #2]
__COMPILER_BARRIER();
}
}
8001190: 4770 bx lr
8001192: bf00 nop
8001194: e000e100 .word 0xe000e100
08001198 <__NVIC_SetPriority>:
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
8001198: 2800 cmp r0, #0
800119a: db04 blt.n 80011a6 <__NVIC_SetPriority+0xe>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
800119c: 0109 lsls r1, r1, #4
800119e: b2c9 uxtb r1, r1
80011a0: 4b04 ldr r3, [pc, #16] @ (80011b4 <__NVIC_SetPriority+0x1c>)
80011a2: 5419 strb r1, [r3, r0]
80011a4: 4770 bx lr
}
else
{
SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
80011a6: f000 000f and.w r0, r0, #15
80011aa: 0109 lsls r1, r1, #4
80011ac: b2c9 uxtb r1, r1
80011ae: 4b02 ldr r3, [pc, #8] @ (80011b8 <__NVIC_SetPriority+0x20>)
80011b0: 5419 strb r1, [r3, r0]
}
}
80011b2: 4770 bx lr
80011b4: e000e400 .word 0xe000e400
80011b8: e000ed14 .word 0xe000ed14
080011bc <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
80011bc: b500 push {lr}
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
80011be: f000 0007 and.w r0, r0, #7
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
80011c2: f1c0 0c07 rsb ip, r0, #7
80011c6: f1bc 0f04 cmp.w ip, #4
80011ca: bf28 it cs
80011cc: f04f 0c04 movcs.w ip, #4
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
80011d0: 1d03 adds r3, r0, #4
80011d2: 2b06 cmp r3, #6
80011d4: d90f bls.n 80011f6 <NVIC_EncodePriority+0x3a>
80011d6: 1ec3 subs r3, r0, #3
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
80011d8: f04f 3eff mov.w lr, #4294967295
80011dc: fa0e f00c lsl.w r0, lr, ip
80011e0: ea21 0100 bic.w r1, r1, r0
80011e4: 4099 lsls r1, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
80011e6: fa0e fe03 lsl.w lr, lr, r3
80011ea: ea22 020e bic.w r2, r2, lr
);
}
80011ee: ea41 0002 orr.w r0, r1, r2
80011f2: f85d fb04 ldr.w pc, [sp], #4
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
80011f6: 2300 movs r3, #0
80011f8: e7ee b.n 80011d8 <NVIC_EncodePriority+0x1c>
...
080011fc <HAL_NVIC_SetPriorityGrouping>:
reg_value = SCB->AIRCR; /* read old register configuration */
80011fc: 4906 ldr r1, [pc, #24] @ (8001218 <HAL_NVIC_SetPriorityGrouping+0x1c>)
80011fe: 68cb ldr r3, [r1, #12]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
8001200: f423 63e0 bic.w r3, r3, #1792 @ 0x700
8001204: 041b lsls r3, r3, #16
8001206: 0c1b lsrs r3, r3, #16
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
8001208: 0200 lsls r0, r0, #8
800120a: f400 60e0 and.w r0, r0, #1792 @ 0x700
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
800120e: 4303 orrs r3, r0
reg_value = (reg_value |
8001210: 4a02 ldr r2, [pc, #8] @ (800121c <HAL_NVIC_SetPriorityGrouping+0x20>)
8001212: 431a orrs r2, r3
SCB->AIRCR = reg_value;
8001214: 60ca str r2, [r1, #12]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
}
8001216: 4770 bx lr
8001218: e000ed00 .word 0xe000ed00
800121c: 05fa0000 .word 0x05fa0000
08001220 <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8001220: b510 push {r4, lr}
8001222: 4604 mov r4, r0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
8001224: 4b05 ldr r3, [pc, #20] @ (800123c <HAL_NVIC_SetPriority+0x1c>)
8001226: 68d8 ldr r0, [r3, #12]
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
8001228: f3c0 2002 ubfx r0, r0, #8, #3
800122c: f7ff ffc6 bl 80011bc <NVIC_EncodePriority>
8001230: 4601 mov r1, r0
8001232: 4620 mov r0, r4
8001234: f7ff ffb0 bl 8001198 <__NVIC_SetPriority>
}
8001238: bd10 pop {r4, pc}
800123a: bf00 nop
800123c: e000ed00 .word 0xe000ed00
08001240 <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32h7xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
8001240: b508 push {r3, lr}
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
8001242: f7ff ff9b bl 800117c <__NVIC_EnableIRQ>
}
8001246: bd08 pop {r3, pc}
08001248 <HAL_SYSTICK_Config>:
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
8001248: 3801 subs r0, #1
800124a: f1b0 7f80 cmp.w r0, #16777216 @ 0x1000000
800124e: d20b bcs.n 8001268 <HAL_SYSTICK_Config+0x20>
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
8001250: f04f 23e0 mov.w r3, #3758153728 @ 0xe000e000
8001254: 6158 str r0, [r3, #20]
SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8001256: 4a05 ldr r2, [pc, #20] @ (800126c <HAL_SYSTICK_Config+0x24>)
8001258: 21f0 movs r1, #240 @ 0xf0
800125a: f882 1023 strb.w r1, [r2, #35] @ 0x23
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
800125e: 2000 movs r0, #0
8001260: 6198 str r0, [r3, #24]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
8001262: 2207 movs r2, #7
8001264: 611a str r2, [r3, #16]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
8001266: 4770 bx lr
return (1UL); /* Reload value impossible */
8001268: 2001 movs r0, #1
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
return SysTick_Config(TicksNumb);
}
800126a: 4770 bx lr
800126c: e000ed00 .word 0xe000ed00
08001270 <FDCAN_CalcultateRamBlockAddresses>:
* @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains
* the configuration information for the specified FDCAN.
* @retval HAL status
*/
static HAL_StatusTypeDef FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan)
{
8001270: b430 push {r4, r5}
uint32_t RAMcounter;
uint32_t StartAddress;
StartAddress = hfdcan->Init.MessageRAMOffset;
8001272: 6b41 ldr r1, [r0, #52] @ 0x34
/* Standard filter list start address */
MODIFY_REG(hfdcan->Instance->SIDFC, FDCAN_SIDFC_FLSSA, (StartAddress << FDCAN_SIDFC_FLSSA_Pos));
8001274: 6804 ldr r4, [r0, #0]
8001276: f8d4 3084 ldr.w r3, [r4, #132] @ 0x84
800127a: 4a6f ldr r2, [pc, #444] @ (8001438 <FDCAN_CalcultateRamBlockAddresses+0x1c8>)
800127c: 4013 ands r3, r2
800127e: ea43 0381 orr.w r3, r3, r1, lsl #2
8001282: f8c4 3084 str.w r3, [r4, #132] @ 0x84
/* Standard filter elements number */
MODIFY_REG(hfdcan->Instance->SIDFC, FDCAN_SIDFC_LSS, (hfdcan->Init.StdFiltersNbr << FDCAN_SIDFC_LSS_Pos));
8001286: 6804 ldr r4, [r0, #0]
8001288: f8d4 3084 ldr.w r3, [r4, #132] @ 0x84
800128c: f423 037f bic.w r3, r3, #16711680 @ 0xff0000
8001290: 6b85 ldr r5, [r0, #56] @ 0x38
8001292: ea43 4305 orr.w r3, r3, r5, lsl #16
8001296: f8c4 3084 str.w r3, [r4, #132] @ 0x84
/* Extended filter list start address */
StartAddress += hfdcan->Init.StdFiltersNbr;
800129a: 6b83 ldr r3, [r0, #56] @ 0x38
800129c: 440b add r3, r1
MODIFY_REG(hfdcan->Instance->XIDFC, FDCAN_XIDFC_FLESA, (StartAddress << FDCAN_XIDFC_FLESA_Pos));
800129e: 6804 ldr r4, [r0, #0]
80012a0: f8d4 1088 ldr.w r1, [r4, #136] @ 0x88
80012a4: 4011 ands r1, r2
80012a6: ea41 0183 orr.w r1, r1, r3, lsl #2
80012aa: f8c4 1088 str.w r1, [r4, #136] @ 0x88
/* Extended filter elements number */
MODIFY_REG(hfdcan->Instance->XIDFC, FDCAN_XIDFC_LSE, (hfdcan->Init.ExtFiltersNbr << FDCAN_XIDFC_LSE_Pos));
80012ae: 6804 ldr r4, [r0, #0]
80012b0: f8d4 1088 ldr.w r1, [r4, #136] @ 0x88
80012b4: f421 01fe bic.w r1, r1, #8323072 @ 0x7f0000
80012b8: 6bc5 ldr r5, [r0, #60] @ 0x3c
80012ba: ea41 4105 orr.w r1, r1, r5, lsl #16
80012be: f8c4 1088 str.w r1, [r4, #136] @ 0x88
/* Rx FIFO 0 start address */
StartAddress += (hfdcan->Init.ExtFiltersNbr * 2U);
80012c2: 6bc1 ldr r1, [r0, #60] @ 0x3c
80012c4: eb03 0341 add.w r3, r3, r1, lsl #1
MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0SA, (StartAddress << FDCAN_RXF0C_F0SA_Pos));
80012c8: 6804 ldr r4, [r0, #0]
80012ca: f8d4 10a0 ldr.w r1, [r4, #160] @ 0xa0
80012ce: 4011 ands r1, r2
80012d0: ea41 0183 orr.w r1, r1, r3, lsl #2
80012d4: f8c4 10a0 str.w r1, [r4, #160] @ 0xa0
/* Rx FIFO 0 elements number */
MODIFY_REG(hfdcan->Instance->RXF0C, FDCAN_RXF0C_F0S, (hfdcan->Init.RxFifo0ElmtsNbr << FDCAN_RXF0C_F0S_Pos));
80012d8: 6804 ldr r4, [r0, #0]
80012da: f8d4 10a0 ldr.w r1, [r4, #160] @ 0xa0
80012de: f421 01fe bic.w r1, r1, #8323072 @ 0x7f0000
80012e2: 6c05 ldr r5, [r0, #64] @ 0x40
80012e4: ea41 4105 orr.w r1, r1, r5, lsl #16
80012e8: f8c4 10a0 str.w r1, [r4, #160] @ 0xa0
/* Rx FIFO 1 start address */
StartAddress += (hfdcan->Init.RxFifo0ElmtsNbr * hfdcan->Init.RxFifo0ElmtSize);
80012ec: 6c01 ldr r1, [r0, #64] @ 0x40
80012ee: 6c44 ldr r4, [r0, #68] @ 0x44
80012f0: fb04 3301 mla r3, r4, r1, r3
MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1SA, (StartAddress << FDCAN_RXF1C_F1SA_Pos));
80012f4: 6804 ldr r4, [r0, #0]
80012f6: f8d4 10b0 ldr.w r1, [r4, #176] @ 0xb0
80012fa: 4011 ands r1, r2
80012fc: ea41 0183 orr.w r1, r1, r3, lsl #2
8001300: f8c4 10b0 str.w r1, [r4, #176] @ 0xb0
/* Rx FIFO 1 elements number */
MODIFY_REG(hfdcan->Instance->RXF1C, FDCAN_RXF1C_F1S, (hfdcan->Init.RxFifo1ElmtsNbr << FDCAN_RXF1C_F1S_Pos));
8001304: 6804 ldr r4, [r0, #0]
8001306: f8d4 10b0 ldr.w r1, [r4, #176] @ 0xb0
800130a: f421 01fe bic.w r1, r1, #8323072 @ 0x7f0000
800130e: 6c85 ldr r5, [r0, #72] @ 0x48
8001310: ea41 4105 orr.w r1, r1, r5, lsl #16
8001314: f8c4 10b0 str.w r1, [r4, #176] @ 0xb0
/* Rx buffer list start address */
StartAddress += (hfdcan->Init.RxFifo1ElmtsNbr * hfdcan->Init.RxFifo1ElmtSize);
8001318: 6c81 ldr r1, [r0, #72] @ 0x48
800131a: 6cc4 ldr r4, [r0, #76] @ 0x4c
800131c: fb04 3301 mla r3, r4, r1, r3
MODIFY_REG(hfdcan->Instance->RXBC, FDCAN_RXBC_RBSA, (StartAddress << FDCAN_RXBC_RBSA_Pos));
8001320: 6804 ldr r4, [r0, #0]
8001322: f8d4 10ac ldr.w r1, [r4, #172] @ 0xac
8001326: 4011 ands r1, r2
8001328: ea41 0183 orr.w r1, r1, r3, lsl #2
800132c: f8c4 10ac str.w r1, [r4, #172] @ 0xac
/* Tx event FIFO start address */
StartAddress += (hfdcan->Init.RxBuffersNbr * hfdcan->Init.RxBufferSize);
8001330: 6d01 ldr r1, [r0, #80] @ 0x50
8001332: 6d44 ldr r4, [r0, #84] @ 0x54
8001334: fb04 3301 mla r3, r4, r1, r3
MODIFY_REG(hfdcan->Instance->TXEFC, FDCAN_TXEFC_EFSA, (StartAddress << FDCAN_TXEFC_EFSA_Pos));
8001338: 6804 ldr r4, [r0, #0]
800133a: f8d4 10f0 ldr.w r1, [r4, #240] @ 0xf0
800133e: 4011 ands r1, r2
8001340: ea41 0183 orr.w r1, r1, r3, lsl #2
8001344: f8c4 10f0 str.w r1, [r4, #240] @ 0xf0
/* Tx event FIFO elements number */
MODIFY_REG(hfdcan->Instance->TXEFC, FDCAN_TXEFC_EFS, (hfdcan->Init.TxEventsNbr << FDCAN_TXEFC_EFS_Pos));
8001348: 6804 ldr r4, [r0, #0]
800134a: f8d4 10f0 ldr.w r1, [r4, #240] @ 0xf0
800134e: f421 117c bic.w r1, r1, #4128768 @ 0x3f0000
8001352: 6d85 ldr r5, [r0, #88] @ 0x58
8001354: ea41 4105 orr.w r1, r1, r5, lsl #16
8001358: f8c4 10f0 str.w r1, [r4, #240] @ 0xf0
/* Tx buffer list start address */
StartAddress += (hfdcan->Init.TxEventsNbr * 2U);
800135c: 6d81 ldr r1, [r0, #88] @ 0x58
800135e: eb03 0341 add.w r3, r3, r1, lsl #1
MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_TBSA, (StartAddress << FDCAN_TXBC_TBSA_Pos));
8001362: 6804 ldr r4, [r0, #0]
8001364: f8d4 10c0 ldr.w r1, [r4, #192] @ 0xc0
8001368: 400a ands r2, r1
800136a: ea42 0383 orr.w r3, r2, r3, lsl #2
800136e: f8c4 30c0 str.w r3, [r4, #192] @ 0xc0
/* Dedicated Tx buffers number */
MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_NDTB, (hfdcan->Init.TxBuffersNbr << FDCAN_TXBC_NDTB_Pos));
8001372: 6802 ldr r2, [r0, #0]
8001374: f8d2 30c0 ldr.w r3, [r2, #192] @ 0xc0
8001378: f423 137c bic.w r3, r3, #4128768 @ 0x3f0000
800137c: 6dc1 ldr r1, [r0, #92] @ 0x5c
800137e: ea43 4301 orr.w r3, r3, r1, lsl #16
8001382: f8c2 30c0 str.w r3, [r2, #192] @ 0xc0
/* Tx FIFO/queue elements number */
MODIFY_REG(hfdcan->Instance->TXBC, FDCAN_TXBC_TFQS, (hfdcan->Init.TxFifoQueueElmtsNbr << FDCAN_TXBC_TFQS_Pos));
8001386: 6802 ldr r2, [r0, #0]
8001388: f8d2 30c0 ldr.w r3, [r2, #192] @ 0xc0
800138c: f023 537c bic.w r3, r3, #1056964608 @ 0x3f000000
8001390: 6e01 ldr r1, [r0, #96] @ 0x60
8001392: ea43 6301 orr.w r3, r3, r1, lsl #24
8001396: f8c2 30c0 str.w r3, [r2, #192] @ 0xc0
hfdcan->msgRam.StandardFilterSA = SRAMCAN_BASE + (hfdcan->Init.MessageRAMOffset * 4U);
800139a: 6b43 ldr r3, [r0, #52] @ 0x34
800139c: 4a27 ldr r2, [pc, #156] @ (800143c <FDCAN_CalcultateRamBlockAddresses+0x1cc>)
800139e: 441a add r2, r3
80013a0: 0092 lsls r2, r2, #2
80013a2: 66c2 str r2, [r0, #108] @ 0x6c
hfdcan->msgRam.ExtendedFilterSA = hfdcan->msgRam.StandardFilterSA + (hfdcan->Init.StdFiltersNbr * 4U);
80013a4: 6b83 ldr r3, [r0, #56] @ 0x38
80013a6: eb02 0383 add.w r3, r2, r3, lsl #2
80013aa: 6703 str r3, [r0, #112] @ 0x70
hfdcan->msgRam.RxFIFO0SA = hfdcan->msgRam.ExtendedFilterSA + (hfdcan->Init.ExtFiltersNbr * 2U * 4U);
80013ac: 6bc1 ldr r1, [r0, #60] @ 0x3c
80013ae: eb03 03c1 add.w r3, r3, r1, lsl #3
80013b2: 6743 str r3, [r0, #116] @ 0x74
hfdcan->msgRam.RxFIFO1SA = hfdcan->msgRam.RxFIFO0SA +
(hfdcan->Init.RxFifo0ElmtsNbr * hfdcan->Init.RxFifo0ElmtSize * 4U);
80013b4: 6c01 ldr r1, [r0, #64] @ 0x40
80013b6: 6c44 ldr r4, [r0, #68] @ 0x44
80013b8: fb04 f101 mul.w r1, r4, r1
hfdcan->msgRam.RxFIFO1SA = hfdcan->msgRam.RxFIFO0SA +
80013bc: eb03 0381 add.w r3, r3, r1, lsl #2
80013c0: 6783 str r3, [r0, #120] @ 0x78
hfdcan->msgRam.RxBufferSA = hfdcan->msgRam.RxFIFO1SA +
(hfdcan->Init.RxFifo1ElmtsNbr * hfdcan->Init.RxFifo1ElmtSize * 4U);
80013c2: 6c81 ldr r1, [r0, #72] @ 0x48
80013c4: 6cc4 ldr r4, [r0, #76] @ 0x4c
80013c6: fb04 f101 mul.w r1, r4, r1
hfdcan->msgRam.RxBufferSA = hfdcan->msgRam.RxFIFO1SA +
80013ca: eb03 0381 add.w r3, r3, r1, lsl #2
80013ce: 67c3 str r3, [r0, #124] @ 0x7c
hfdcan->msgRam.TxEventFIFOSA = hfdcan->msgRam.RxBufferSA +
(hfdcan->Init.RxBuffersNbr * hfdcan->Init.RxBufferSize * 4U);
80013d0: 6d01 ldr r1, [r0, #80] @ 0x50
80013d2: 6d44 ldr r4, [r0, #84] @ 0x54
80013d4: fb04 f101 mul.w r1, r4, r1
hfdcan->msgRam.TxEventFIFOSA = hfdcan->msgRam.RxBufferSA +
80013d8: eb03 0381 add.w r3, r3, r1, lsl #2
80013dc: f8c0 3080 str.w r3, [r0, #128] @ 0x80
hfdcan->msgRam.TxBufferSA = hfdcan->msgRam.TxEventFIFOSA + (hfdcan->Init.TxEventsNbr * 2U * 4U);
80013e0: 6d81 ldr r1, [r0, #88] @ 0x58
80013e2: eb03 03c1 add.w r3, r3, r1, lsl #3
80013e6: f8c0 3084 str.w r3, [r0, #132] @ 0x84
hfdcan->msgRam.TxFIFOQSA = hfdcan->msgRam.TxBufferSA + (hfdcan->Init.TxBuffersNbr * hfdcan->Init.TxElmtSize * 4U);
80013ea: 6e81 ldr r1, [r0, #104] @ 0x68
80013ec: 6dc4 ldr r4, [r0, #92] @ 0x5c
80013ee: fb01 fc04 mul.w ip, r1, r4
80013f2: eb03 038c add.w r3, r3, ip, lsl #2
80013f6: f8c0 3088 str.w r3, [r0, #136] @ 0x88
hfdcan->msgRam.EndAddress = hfdcan->msgRam.TxFIFOQSA +
(hfdcan->Init.TxFifoQueueElmtsNbr * hfdcan->Init.TxElmtSize * 4U);
80013fa: 6e04 ldr r4, [r0, #96] @ 0x60
80013fc: fb04 f101 mul.w r1, r4, r1
hfdcan->msgRam.EndAddress = hfdcan->msgRam.TxFIFOQSA +
8001400: eb03 0381 add.w r3, r3, r1, lsl #2
8001404: f8c0 3090 str.w r3, [r0, #144] @ 0x90
if (hfdcan->msgRam.EndAddress > FDCAN_MESSAGE_RAM_END_ADDRESS) /* Last address of the Message RAM */
8001408: 490d ldr r1, [pc, #52] @ (8001440 <FDCAN_CalcultateRamBlockAddresses+0x1d0>)
800140a: 428b cmp r3, r1
800140c: d90d bls.n 800142a <FDCAN_CalcultateRamBlockAddresses+0x1ba>
{
/* Update error code.
Message RAM overflow */
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_PARAM;
800140e: f8d0 309c ldr.w r3, [r0, #156] @ 0x9c
8001412: f043 0320 orr.w r3, r3, #32
8001416: f8c0 309c str.w r3, [r0, #156] @ 0x9c
/* Change FDCAN state */
hfdcan->State = HAL_FDCAN_STATE_ERROR;
800141a: 2303 movs r3, #3
800141c: f880 3098 strb.w r3, [r0, #152] @ 0x98
return HAL_ERROR;
8001420: 2001 movs r0, #1
8001422: e007 b.n 8001434 <FDCAN_CalcultateRamBlockAddresses+0x1c4>
else
{
/* Flush the allocated Message RAM area */
for (RAMcounter = hfdcan->msgRam.StandardFilterSA; RAMcounter < hfdcan->msgRam.EndAddress; RAMcounter += 4U)
{
*(uint32_t *)(RAMcounter) = 0x00000000;
8001424: 2300 movs r3, #0
8001426: f842 3b04 str.w r3, [r2], #4
for (RAMcounter = hfdcan->msgRam.StandardFilterSA; RAMcounter < hfdcan->msgRam.EndAddress; RAMcounter += 4U)
800142a: f8d0 3090 ldr.w r3, [r0, #144] @ 0x90
800142e: 4293 cmp r3, r2
8001430: d8f8 bhi.n 8001424 <FDCAN_CalcultateRamBlockAddresses+0x1b4>
}
}
/* Return function status */
return HAL_OK;
8001432: 2000 movs r0, #0
}
8001434: bc30 pop {r4, r5}
8001436: 4770 bx lr
8001438: ffff0003 .word 0xffff0003
800143c: 10002b00 .word 0x10002b00
8001440: 4000d3fc .word 0x4000d3fc
08001444 <HAL_FDCAN_Init>:
{
8001444: b530 push {r4, r5, lr}
8001446: b095 sub sp, #84 @ 0x54
8001448: 4604 mov r4, r0
const uint32_t CvtEltSize[] = {0, 0, 0, 0, 0, 1, 2, 3, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0, 7};
800144a: 224c movs r2, #76 @ 0x4c
800144c: 49a0 ldr r1, [pc, #640] @ (80016d0 <HAL_FDCAN_Init+0x28c>)
800144e: a801 add r0, sp, #4
8001450: f003 fc8c bl 8004d6c <memcpy>
if (hfdcan == NULL)
8001454: 2c00 cmp r4, #0
8001456: f000 8138 beq.w 80016ca <HAL_FDCAN_Init+0x286>
if (hfdcan->Instance == FDCAN1)
800145a: 6823 ldr r3, [r4, #0]
800145c: 4a9d ldr r2, [pc, #628] @ (80016d4 <HAL_FDCAN_Init+0x290>)
800145e: 4293 cmp r3, r2
8001460: d020 beq.n 80014a4 <HAL_FDCAN_Init+0x60>
if (hfdcan->State == HAL_FDCAN_STATE_RESET)
8001462: f894 3098 ldrb.w r3, [r4, #152] @ 0x98
8001466: b30b cbz r3, 80014ac <HAL_FDCAN_Init+0x68>
CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CSR);
8001468: 6822 ldr r2, [r4, #0]
800146a: 6993 ldr r3, [r2, #24]
800146c: f023 0310 bic.w r3, r3, #16
8001470: 6193 str r3, [r2, #24]
tickstart = HAL_GetTick();
8001472: f7ff fa39 bl 80008e8 <HAL_GetTick>
8001476: 4605 mov r5, r0
while ((hfdcan->Instance->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA)
8001478: 6823 ldr r3, [r4, #0]
800147a: 699a ldr r2, [r3, #24]
800147c: f012 0f08 tst.w r2, #8
8001480: d01a beq.n 80014b8 <HAL_FDCAN_Init+0x74>
if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
8001482: f7ff fa31 bl 80008e8 <HAL_GetTick>
8001486: 1b43 subs r3, r0, r5
8001488: 2b0a cmp r3, #10
800148a: d9f5 bls.n 8001478 <HAL_FDCAN_Init+0x34>
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
800148c: f8d4 309c ldr.w r3, [r4, #156] @ 0x9c
8001490: f043 0301 orr.w r3, r3, #1
8001494: f8c4 309c str.w r3, [r4, #156] @ 0x9c
hfdcan->State = HAL_FDCAN_STATE_ERROR;
8001498: 2303 movs r3, #3
800149a: f884 3098 strb.w r3, [r4, #152] @ 0x98
return HAL_ERROR;
800149e: 2001 movs r0, #1
}
80014a0: b015 add sp, #84 @ 0x54
80014a2: bd30 pop {r4, r5, pc}
hfdcan->ttcan = (TTCAN_TypeDef *)((uint32_t)hfdcan->Instance + 0x100U);
80014a4: f503 7380 add.w r3, r3, #256 @ 0x100
80014a8: 6063 str r3, [r4, #4]
80014aa: e7da b.n 8001462 <HAL_FDCAN_Init+0x1e>
hfdcan->Lock = HAL_UNLOCKED;
80014ac: f884 3099 strb.w r3, [r4, #153] @ 0x99
HAL_FDCAN_MspInit(hfdcan);
80014b0: 4620 mov r0, r4
80014b2: f000 fc4b bl 8001d4c <HAL_FDCAN_MspInit>
80014b6: e7d7 b.n 8001468 <HAL_FDCAN_Init+0x24>
SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_INIT);
80014b8: 699a ldr r2, [r3, #24]
80014ba: f042 0201 orr.w r2, r2, #1
80014be: 619a str r2, [r3, #24]
tickstart = HAL_GetTick();
80014c0: f7ff fa12 bl 80008e8 <HAL_GetTick>
80014c4: 4605 mov r5, r0
while ((hfdcan->Instance->CCCR & FDCAN_CCCR_INIT) == 0U)
80014c6: 6823 ldr r3, [r4, #0]
80014c8: 699a ldr r2, [r3, #24]
80014ca: f012 0f01 tst.w r2, #1
80014ce: d10f bne.n 80014f0 <HAL_FDCAN_Init+0xac>
if ((HAL_GetTick() - tickstart) > FDCAN_TIMEOUT_VALUE)
80014d0: f7ff fa0a bl 80008e8 <HAL_GetTick>
80014d4: 1b40 subs r0, r0, r5
80014d6: 280a cmp r0, #10
80014d8: d9f5 bls.n 80014c6 <HAL_FDCAN_Init+0x82>
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_TIMEOUT;
80014da: f8d4 309c ldr.w r3, [r4, #156] @ 0x9c
80014de: f043 0301 orr.w r3, r3, #1
80014e2: f8c4 309c str.w r3, [r4, #156] @ 0x9c
hfdcan->State = HAL_FDCAN_STATE_ERROR;
80014e6: 2303 movs r3, #3
80014e8: f884 3098 strb.w r3, [r4, #152] @ 0x98
return HAL_ERROR;
80014ec: 2001 movs r0, #1
80014ee: e7d7 b.n 80014a0 <HAL_FDCAN_Init+0x5c>
SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_CCE);
80014f0: 699a ldr r2, [r3, #24]
80014f2: f042 0202 orr.w r2, r2, #2
80014f6: 619a str r2, [r3, #24]
if (hfdcan->Init.AutoRetransmission == ENABLE)
80014f8: 7c23 ldrb r3, [r4, #16]
80014fa: 2b01 cmp r3, #1
80014fc: d040 beq.n 8001580 <HAL_FDCAN_Init+0x13c>
SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR);
80014fe: 6822 ldr r2, [r4, #0]
8001500: 6993 ldr r3, [r2, #24]
8001502: f043 0340 orr.w r3, r3, #64 @ 0x40
8001506: 6193 str r3, [r2, #24]
if (hfdcan->Init.TransmitPause == ENABLE)
8001508: 7c63 ldrb r3, [r4, #17]
800150a: 2b01 cmp r3, #1
800150c: d03e beq.n 800158c <HAL_FDCAN_Init+0x148>
CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP);
800150e: 6822 ldr r2, [r4, #0]
8001510: 6993 ldr r3, [r2, #24]
8001512: f423 4380 bic.w r3, r3, #16384 @ 0x4000
8001516: 6193 str r3, [r2, #24]
if (hfdcan->Init.ProtocolException == ENABLE)
8001518: 7ca3 ldrb r3, [r4, #18]
800151a: 2b01 cmp r3, #1
800151c: d03c beq.n 8001598 <HAL_FDCAN_Init+0x154>
SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD);
800151e: 6822 ldr r2, [r4, #0]
8001520: 6993 ldr r3, [r2, #24]
8001522: f443 5380 orr.w r3, r3, #4096 @ 0x1000
8001526: 6193 str r3, [r2, #24]
MODIFY_REG(hfdcan->Instance->CCCR, FDCAN_FRAME_FD_BRS, hfdcan->Init.FrameFormat);
8001528: 6822 ldr r2, [r4, #0]
800152a: 6993 ldr r3, [r2, #24]
800152c: f423 7340 bic.w r3, r3, #768 @ 0x300
8001530: 68a1 ldr r1, [r4, #8]
8001532: 430b orrs r3, r1
8001534: 6193 str r3, [r2, #24]
CLEAR_BIT(hfdcan->Instance->CCCR, (FDCAN_CCCR_TEST | FDCAN_CCCR_MON | FDCAN_CCCR_ASM));
8001536: 6822 ldr r2, [r4, #0]
8001538: 6993 ldr r3, [r2, #24]
800153a: f023 03a4 bic.w r3, r3, #164 @ 0xa4
800153e: 6193 str r3, [r2, #24]
CLEAR_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK);
8001540: 6822 ldr r2, [r4, #0]
8001542: 6913 ldr r3, [r2, #16]
8001544: f023 0310 bic.w r3, r3, #16
8001548: 6113 str r3, [r2, #16]
if (hfdcan->Init.Mode == FDCAN_MODE_RESTRICTED_OPERATION)
800154a: 68e3 ldr r3, [r4, #12]
800154c: 2b01 cmp r3, #1
800154e: d029 beq.n 80015a4 <HAL_FDCAN_Init+0x160>
else if (hfdcan->Init.Mode != FDCAN_MODE_NORMAL)
8001550: 2b00 cmp r3, #0
8001552: d02c beq.n 80015ae <HAL_FDCAN_Init+0x16a>
if (hfdcan->Init.Mode != FDCAN_MODE_BUS_MONITORING)
8001554: 2b02 cmp r3, #2
8001556: f000 809b beq.w 8001690 <HAL_FDCAN_Init+0x24c>
SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TEST);
800155a: 6822 ldr r2, [r4, #0]
800155c: 6993 ldr r3, [r2, #24]
800155e: f043 0380 orr.w r3, r3, #128 @ 0x80
8001562: 6193 str r3, [r2, #24]
SET_BIT(hfdcan->Instance->TEST, FDCAN_TEST_LBCK);
8001564: 6822 ldr r2, [r4, #0]
8001566: 6913 ldr r3, [r2, #16]
8001568: f043 0310 orr.w r3, r3, #16
800156c: 6113 str r3, [r2, #16]
if (hfdcan->Init.Mode == FDCAN_MODE_INTERNAL_LOOPBACK)
800156e: 68e3 ldr r3, [r4, #12]
8001570: 2b03 cmp r3, #3
8001572: d11c bne.n 80015ae <HAL_FDCAN_Init+0x16a>
SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON);
8001574: 6822 ldr r2, [r4, #0]
8001576: 6993 ldr r3, [r2, #24]
8001578: f043 0320 orr.w r3, r3, #32
800157c: 6193 str r3, [r2, #24]
800157e: e016 b.n 80015ae <HAL_FDCAN_Init+0x16a>
CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_DAR);
8001580: 6822 ldr r2, [r4, #0]
8001582: 6993 ldr r3, [r2, #24]
8001584: f023 0340 bic.w r3, r3, #64 @ 0x40
8001588: 6193 str r3, [r2, #24]
800158a: e7bd b.n 8001508 <HAL_FDCAN_Init+0xc4>
SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_TXP);
800158c: 6822 ldr r2, [r4, #0]
800158e: 6993 ldr r3, [r2, #24]
8001590: f443 4380 orr.w r3, r3, #16384 @ 0x4000
8001594: 6193 str r3, [r2, #24]
8001596: e7bf b.n 8001518 <HAL_FDCAN_Init+0xd4>
CLEAR_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_PXHD);
8001598: 6822 ldr r2, [r4, #0]
800159a: 6993 ldr r3, [r2, #24]
800159c: f423 5380 bic.w r3, r3, #4096 @ 0x1000
80015a0: 6193 str r3, [r2, #24]
80015a2: e7c1 b.n 8001528 <HAL_FDCAN_Init+0xe4>
SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_ASM);
80015a4: 6822 ldr r2, [r4, #0]
80015a6: 6993 ldr r3, [r2, #24]
80015a8: f043 0304 orr.w r3, r3, #4
80015ac: 6193 str r3, [r2, #24]
hfdcan->Instance->NBTP = ((((uint32_t)hfdcan->Init.NominalSyncJumpWidth - 1U) << FDCAN_NBTP_NSJW_Pos) | \
80015ae: 69a3 ldr r3, [r4, #24]
80015b0: 1e5a subs r2, r3, #1
(((uint32_t)hfdcan->Init.NominalTimeSeg1 - 1U) << FDCAN_NBTP_NTSEG1_Pos) | \
80015b2: 69e3 ldr r3, [r4, #28]
80015b4: 3b01 subs r3, #1
80015b6: 021b lsls r3, r3, #8
hfdcan->Instance->NBTP = ((((uint32_t)hfdcan->Init.NominalSyncJumpWidth - 1U) << FDCAN_NBTP_NSJW_Pos) | \
80015b8: ea43 6342 orr.w r3, r3, r2, lsl #25
(((uint32_t)hfdcan->Init.NominalTimeSeg2 - 1U) << FDCAN_NBTP_NTSEG2_Pos) | \
80015bc: 6a22 ldr r2, [r4, #32]
80015be: 3a01 subs r2, #1
(((uint32_t)hfdcan->Init.NominalTimeSeg1 - 1U) << FDCAN_NBTP_NTSEG1_Pos) | \
80015c0: 4313 orrs r3, r2
(((uint32_t)hfdcan->Init.NominalPrescaler - 1U) << FDCAN_NBTP_NBRP_Pos));
80015c2: 6962 ldr r2, [r4, #20]
80015c4: 3a01 subs r2, #1
hfdcan->Instance->NBTP = ((((uint32_t)hfdcan->Init.NominalSyncJumpWidth - 1U) << FDCAN_NBTP_NSJW_Pos) | \
80015c6: 6821 ldr r1, [r4, #0]
(((uint32_t)hfdcan->Init.NominalTimeSeg2 - 1U) << FDCAN_NBTP_NTSEG2_Pos) | \
80015c8: ea43 4302 orr.w r3, r3, r2, lsl #16
hfdcan->Instance->NBTP = ((((uint32_t)hfdcan->Init.NominalSyncJumpWidth - 1U) << FDCAN_NBTP_NSJW_Pos) | \
80015cc: 61cb str r3, [r1, #28]
if (hfdcan->Init.FrameFormat == FDCAN_FRAME_FD_BRS)
80015ce: 68a3 ldr r3, [r4, #8]
80015d0: f5b3 7f40 cmp.w r3, #768 @ 0x300
80015d4: d062 beq.n 800169c <HAL_FDCAN_Init+0x258>
if (hfdcan->Init.TxFifoQueueElmtsNbr > 0U)
80015d6: 6e23 ldr r3, [r4, #96] @ 0x60
80015d8: b133 cbz r3, 80015e8 <HAL_FDCAN_Init+0x1a4>
SET_BIT(hfdcan->Instance->TXBC, hfdcan->Init.TxFifoQueueMode);
80015da: 6822 ldr r2, [r4, #0]
80015dc: f8d2 30c0 ldr.w r3, [r2, #192] @ 0xc0
80015e0: 6e61 ldr r1, [r4, #100] @ 0x64
80015e2: 430b orrs r3, r1
80015e4: f8c2 30c0 str.w r3, [r2, #192] @ 0xc0
if ((hfdcan->Init.TxBuffersNbr + hfdcan->Init.TxFifoQueueElmtsNbr) > 0U)
80015e8: 6de3 ldr r3, [r4, #92] @ 0x5c
80015ea: 6e22 ldr r2, [r4, #96] @ 0x60
80015ec: 42d3 cmn r3, r2
80015ee: d00d beq.n 800160c <HAL_FDCAN_Init+0x1c8>
MODIFY_REG(hfdcan->Instance->TXESC, FDCAN_TXESC_TBDS, CvtEltSize[hfdcan->Init.TxElmtSize]);
80015f0: 6821 ldr r1, [r4, #0]
80015f2: f8d1 30c8 ldr.w r3, [r1, #200] @ 0xc8
80015f6: f023 0307 bic.w r3, r3, #7
80015fa: 6ea2 ldr r2, [r4, #104] @ 0x68
80015fc: a814 add r0, sp, #80 @ 0x50
80015fe: eb00 0282 add.w r2, r0, r2, lsl #2
8001602: f852 2c4c ldr.w r2, [r2, #-76]
8001606: 4313 orrs r3, r2
8001608: f8c1 30c8 str.w r3, [r1, #200] @ 0xc8
if (hfdcan->Init.RxFifo0ElmtsNbr > 0U)
800160c: 6c23 ldr r3, [r4, #64] @ 0x40
800160e: b16b cbz r3, 800162c <HAL_FDCAN_Init+0x1e8>
MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_F0DS,
8001610: 6821 ldr r1, [r4, #0]
8001612: f8d1 30bc ldr.w r3, [r1, #188] @ 0xbc
8001616: f023 0307 bic.w r3, r3, #7
800161a: 6c62 ldr r2, [r4, #68] @ 0x44
800161c: a814 add r0, sp, #80 @ 0x50
800161e: eb00 0282 add.w r2, r0, r2, lsl #2
8001622: f852 2c4c ldr.w r2, [r2, #-76]
8001626: 4313 orrs r3, r2
8001628: f8c1 30bc str.w r3, [r1, #188] @ 0xbc
if (hfdcan->Init.RxFifo1ElmtsNbr > 0U)
800162c: 6ca3 ldr r3, [r4, #72] @ 0x48
800162e: b173 cbz r3, 800164e <HAL_FDCAN_Init+0x20a>
MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_F1DS,
8001630: 6821 ldr r1, [r4, #0]
8001632: f8d1 30bc ldr.w r3, [r1, #188] @ 0xbc
8001636: f023 0370 bic.w r3, r3, #112 @ 0x70
800163a: 6ce2 ldr r2, [r4, #76] @ 0x4c
800163c: a814 add r0, sp, #80 @ 0x50
800163e: eb00 0282 add.w r2, r0, r2, lsl #2
8001642: f852 2c4c ldr.w r2, [r2, #-76]
8001646: ea43 1302 orr.w r3, r3, r2, lsl #4
800164a: f8c1 30bc str.w r3, [r1, #188] @ 0xbc
if (hfdcan->Init.RxBuffersNbr > 0U)
800164e: 6d23 ldr r3, [r4, #80] @ 0x50
8001650: b173 cbz r3, 8001670 <HAL_FDCAN_Init+0x22c>
MODIFY_REG(hfdcan->Instance->RXESC, FDCAN_RXESC_RBDS,
8001652: 6821 ldr r1, [r4, #0]
8001654: f8d1 30bc ldr.w r3, [r1, #188] @ 0xbc
8001658: f423 63e0 bic.w r3, r3, #1792 @ 0x700
800165c: 6d62 ldr r2, [r4, #84] @ 0x54
800165e: a814 add r0, sp, #80 @ 0x50
8001660: eb00 0282 add.w r2, r0, r2, lsl #2
8001664: f852 2c4c ldr.w r2, [r2, #-76]
8001668: ea43 2302 orr.w r3, r3, r2, lsl #8
800166c: f8c1 30bc str.w r3, [r1, #188] @ 0xbc
if (hfdcan->Instance == FDCAN1)
8001670: 6822 ldr r2, [r4, #0]
8001672: 4b18 ldr r3, [pc, #96] @ (80016d4 <HAL_FDCAN_Init+0x290>)
8001674: 429a cmp r2, r3
8001676: d022 beq.n 80016be <HAL_FDCAN_Init+0x27a>
hfdcan->LatestTxFifoQRequest = 0U;
8001678: 2300 movs r3, #0
800167a: f8c4 3094 str.w r3, [r4, #148] @ 0x94
hfdcan->ErrorCode = HAL_FDCAN_ERROR_NONE;
800167e: f8c4 309c str.w r3, [r4, #156] @ 0x9c
hfdcan->State = HAL_FDCAN_STATE_READY;
8001682: 2301 movs r3, #1
8001684: f884 3098 strb.w r3, [r4, #152] @ 0x98
status = FDCAN_CalcultateRamBlockAddresses(hfdcan);
8001688: 4620 mov r0, r4
800168a: f7ff fdf1 bl 8001270 <FDCAN_CalcultateRamBlockAddresses>
return status;
800168e: e707 b.n 80014a0 <HAL_FDCAN_Init+0x5c>
SET_BIT(hfdcan->Instance->CCCR, FDCAN_CCCR_MON);
8001690: 6822 ldr r2, [r4, #0]
8001692: 6993 ldr r3, [r2, #24]
8001694: f043 0320 orr.w r3, r3, #32
8001698: 6193 str r3, [r2, #24]
800169a: e788 b.n 80015ae <HAL_FDCAN_Init+0x16a>
hfdcan->Instance->DBTP = ((((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1U) << FDCAN_DBTP_DSJW_Pos) | \
800169c: 6aa3 ldr r3, [r4, #40] @ 0x28
800169e: 3b01 subs r3, #1
(((uint32_t)hfdcan->Init.DataTimeSeg1 - 1U) << FDCAN_DBTP_DTSEG1_Pos) | \
80016a0: 6ae2 ldr r2, [r4, #44] @ 0x2c
80016a2: 3a01 subs r2, #1
hfdcan->Instance->DBTP = ((((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1U) << FDCAN_DBTP_DSJW_Pos) | \
80016a4: ea43 2302 orr.w r3, r3, r2, lsl #8
(((uint32_t)hfdcan->Init.DataTimeSeg2 - 1U) << FDCAN_DBTP_DTSEG2_Pos) | \
80016a8: 6b22 ldr r2, [r4, #48] @ 0x30
80016aa: 3a01 subs r2, #1
(((uint32_t)hfdcan->Init.DataTimeSeg1 - 1U) << FDCAN_DBTP_DTSEG1_Pos) | \
80016ac: ea43 1302 orr.w r3, r3, r2, lsl #4
(((uint32_t)hfdcan->Init.DataPrescaler - 1U) << FDCAN_DBTP_DBRP_Pos));
80016b0: 6a62 ldr r2, [r4, #36] @ 0x24
80016b2: 3a01 subs r2, #1
hfdcan->Instance->DBTP = ((((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1U) << FDCAN_DBTP_DSJW_Pos) | \
80016b4: 6821 ldr r1, [r4, #0]
(((uint32_t)hfdcan->Init.DataTimeSeg2 - 1U) << FDCAN_DBTP_DTSEG2_Pos) | \
80016b6: ea43 4302 orr.w r3, r3, r2, lsl #16
hfdcan->Instance->DBTP = ((((uint32_t)hfdcan->Init.DataSyncJumpWidth - 1U) << FDCAN_DBTP_DSJW_Pos) | \
80016ba: 60cb str r3, [r1, #12]
80016bc: e78b b.n 80015d6 <HAL_FDCAN_Init+0x192>
CLEAR_BIT(hfdcan->ttcan->TTOCF, FDCAN_TTOCF_OM);
80016be: 6862 ldr r2, [r4, #4]
80016c0: 6893 ldr r3, [r2, #8]
80016c2: f023 0303 bic.w r3, r3, #3
80016c6: 6093 str r3, [r2, #8]
80016c8: e7d6 b.n 8001678 <HAL_FDCAN_Init+0x234>
return HAL_ERROR;
80016ca: 2001 movs r0, #1
80016cc: e6e8 b.n 80014a0 <HAL_FDCAN_Init+0x5c>
80016ce: bf00 nop
80016d0: 08004da0 .word 0x08004da0
80016d4: 4000a000 .word 0x4000a000
080016d8 <HAL_FDCAN_ClockCalibrationCallback>:
}
80016d8: 4770 bx lr
080016da <HAL_FDCAN_TxEventFifoCallback>:
}
80016da: 4770 bx lr
080016dc <HAL_FDCAN_RxFifo0Callback>:
}
80016dc: 4770 bx lr
080016de <HAL_FDCAN_RxFifo1Callback>:
}
80016de: 4770 bx lr
080016e0 <HAL_FDCAN_TxFifoEmptyCallback>:
}
80016e0: 4770 bx lr
080016e2 <HAL_FDCAN_TxBufferCompleteCallback>:
}
80016e2: 4770 bx lr
080016e4 <HAL_FDCAN_TxBufferAbortCallback>:
}
80016e4: 4770 bx lr
080016e6 <HAL_FDCAN_RxBufferNewMessageCallback>:
}
80016e6: 4770 bx lr
080016e8 <HAL_FDCAN_TimestampWraparoundCallback>:
}
80016e8: 4770 bx lr
080016ea <HAL_FDCAN_TimeoutOccurredCallback>:
}
80016ea: 4770 bx lr
080016ec <HAL_FDCAN_HighPriorityMessageCallback>:
}
80016ec: 4770 bx lr
080016ee <HAL_FDCAN_ErrorCallback>:
}
80016ee: 4770 bx lr
080016f0 <HAL_FDCAN_ErrorStatusCallback>:
}
80016f0: 4770 bx lr
080016f2 <HAL_FDCAN_TT_ScheduleSyncCallback>:
}
80016f2: 4770 bx lr
080016f4 <HAL_FDCAN_TT_TimeMarkCallback>:
}
80016f4: 4770 bx lr
080016f6 <HAL_FDCAN_TT_StopWatchCallback>:
}
80016f6: 4770 bx lr
080016f8 <HAL_FDCAN_TT_GlobalTimeCallback>:
}
80016f8: 4770 bx lr
...
080016fc <HAL_FDCAN_IRQHandler>:
{
80016fc: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
8001700: b083 sub sp, #12
8001702: 4604 mov r4, r0
ClkCalibrationITs = (FDCAN_CCU->IR << 30);
8001704: 4b90 ldr r3, [pc, #576] @ (8001948 <HAL_FDCAN_IRQHandler+0x24c>)
8001706: 691a ldr r2, [r3, #16]
ClkCalibrationITs &= (FDCAN_CCU->IE << 30);
8001708: 695b ldr r3, [r3, #20]
800170a: 4013 ands r3, r2
800170c: 9301 str r3, [sp, #4]
800170e: 079b lsls r3, r3, #30
8001710: 9300 str r3, [sp, #0]
TxEventFifoITs = hfdcan->Instance->IR & FDCAN_TX_EVENT_FIFO_MASK;
8001712: 6803 ldr r3, [r0, #0]
8001714: 6d1a ldr r2, [r3, #80] @ 0x50
8001716: f402 4a70 and.w sl, r2, #61440 @ 0xf000
TxEventFifoITs &= hfdcan->Instance->IE;
800171a: 6d5a ldr r2, [r3, #84] @ 0x54
800171c: ea0a 0a02 and.w sl, sl, r2
RxFifo0ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO0_MASK;
8001720: 6d1a ldr r2, [r3, #80] @ 0x50
8001722: f002 090f and.w r9, r2, #15
RxFifo0ITs &= hfdcan->Instance->IE;
8001726: 6d5a ldr r2, [r3, #84] @ 0x54
8001728: ea09 0902 and.w r9, r9, r2
RxFifo1ITs = hfdcan->Instance->IR & FDCAN_RX_FIFO1_MASK;
800172c: 6d1a ldr r2, [r3, #80] @ 0x50
800172e: f002 08f0 and.w r8, r2, #240 @ 0xf0
RxFifo1ITs &= hfdcan->Instance->IE;
8001732: 6d5a ldr r2, [r3, #84] @ 0x54
8001734: ea08 0802 and.w r8, r8, r2
Errors = hfdcan->Instance->IR & FDCAN_ERROR_MASK;
8001738: 6d1e ldr r6, [r3, #80] @ 0x50
800173a: f006 5671 and.w r6, r6, #1010827264 @ 0x3c400000
Errors &= hfdcan->Instance->IE;
800173e: 6d5a ldr r2, [r3, #84] @ 0x54
8001740: 4016 ands r6, r2
ErrorStatusITs = hfdcan->Instance->IR & FDCAN_ERROR_STATUS_MASK;
8001742: 6d1f ldr r7, [r3, #80] @ 0x50
8001744: f007 7760 and.w r7, r7, #58720256 @ 0x3800000
ErrorStatusITs &= hfdcan->Instance->IE;
8001748: 6d5a ldr r2, [r3, #84] @ 0x54
800174a: 4017 ands r7, r2
itsourceIE = hfdcan->Instance->IE;
800174c: 6d5d ldr r5, [r3, #84] @ 0x54
itflagIR = hfdcan->Instance->IR;
800174e: f8d3 b050 ldr.w fp, [r3, #80] @ 0x50
if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_RX_HIGH_PRIORITY_MSG) != RESET)
8001752: f415 7f80 tst.w r5, #256 @ 0x100
8001756: d002 beq.n 800175e <HAL_FDCAN_IRQHandler+0x62>
if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG) != RESET)
8001758: f41b 7f80 tst.w fp, #256 @ 0x100
800175c: d164 bne.n 8001828 <HAL_FDCAN_IRQHandler+0x12c>
if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TX_ABORT_COMPLETE) != RESET)
800175e: f415 6f80 tst.w r5, #1024 @ 0x400
8001762: d002 beq.n 800176a <HAL_FDCAN_IRQHandler+0x6e>
if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TX_ABORT_COMPLETE) != RESET)
8001764: f41b 6f80 tst.w fp, #1024 @ 0x400
8001768: d167 bne.n 800183a <HAL_FDCAN_IRQHandler+0x13e>
if (ClkCalibrationITs != 0U)
800176a: 9b00 ldr r3, [sp, #0]
800176c: 2b00 cmp r3, #0
800176e: d174 bne.n 800185a <HAL_FDCAN_IRQHandler+0x15e>
if (TxEventFifoITs != 0U)
8001770: f1ba 0f00 cmp.w sl, #0
8001774: d17e bne.n 8001874 <HAL_FDCAN_IRQHandler+0x178>
if (RxFifo0ITs != 0U)
8001776: f1b9 0f00 cmp.w r9, #0
800177a: f040 8087 bne.w 800188c <HAL_FDCAN_IRQHandler+0x190>
if (RxFifo1ITs != 0U)
800177e: f1b8 0f00 cmp.w r8, #0
8001782: f040 808f bne.w 80018a4 <HAL_FDCAN_IRQHandler+0x1a8>
if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TX_FIFO_EMPTY) != RESET)
8001786: f415 6f00 tst.w r5, #2048 @ 0x800
800178a: d003 beq.n 8001794 <HAL_FDCAN_IRQHandler+0x98>
if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TX_FIFO_EMPTY) != RESET)
800178c: f41b 6f00 tst.w fp, #2048 @ 0x800
8001790: f040 8094 bne.w 80018bc <HAL_FDCAN_IRQHandler+0x1c0>
if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TX_COMPLETE) != RESET)
8001794: f415 7f00 tst.w r5, #512 @ 0x200
8001798: d003 beq.n 80017a2 <HAL_FDCAN_IRQHandler+0xa6>
if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TX_COMPLETE) != RESET)
800179a: f41b 7f00 tst.w fp, #512 @ 0x200
800179e: f040 8098 bne.w 80018d2 <HAL_FDCAN_IRQHandler+0x1d6>
if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_RX_BUFFER_NEW_MESSAGE) != RESET)
80017a2: f415 2f00 tst.w r5, #524288 @ 0x80000
80017a6: d003 beq.n 80017b0 <HAL_FDCAN_IRQHandler+0xb4>
if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE) != RESET)
80017a8: f41b 2f00 tst.w fp, #524288 @ 0x80000
80017ac: f040 80a1 bne.w 80018f2 <HAL_FDCAN_IRQHandler+0x1f6>
if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TIMESTAMP_WRAPAROUND) != RESET)
80017b0: f415 3f80 tst.w r5, #65536 @ 0x10000
80017b4: d003 beq.n 80017be <HAL_FDCAN_IRQHandler+0xc2>
if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TIMESTAMP_WRAPAROUND) != RESET)
80017b6: f41b 3f80 tst.w fp, #65536 @ 0x10000
80017ba: f040 80a5 bne.w 8001908 <HAL_FDCAN_IRQHandler+0x20c>
if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_TIMEOUT_OCCURRED) != RESET)
80017be: f415 2f80 tst.w r5, #262144 @ 0x40000
80017c2: d003 beq.n 80017cc <HAL_FDCAN_IRQHandler+0xd0>
if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_TIMEOUT_OCCURRED) != RESET)
80017c4: f41b 2f80 tst.w fp, #262144 @ 0x40000
80017c8: f040 80a9 bne.w 800191e <HAL_FDCAN_IRQHandler+0x222>
if (FDCAN_CHECK_IT_SOURCE(itsourceIE, FDCAN_IT_RAM_ACCESS_FAILURE) != RESET)
80017cc: f415 3f00 tst.w r5, #131072 @ 0x20000
80017d0: d00f beq.n 80017f2 <HAL_FDCAN_IRQHandler+0xf6>
if (FDCAN_CHECK_FLAG(itflagIR, FDCAN_FLAG_RAM_ACCESS_FAILURE) != RESET)
80017d2: f41b 3f00 tst.w fp, #131072 @ 0x20000
80017d6: d00c beq.n 80017f2 <HAL_FDCAN_IRQHandler+0xf6>
__HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RAM_ACCESS_FAILURE);
80017d8: 6823 ldr r3, [r4, #0]
80017da: f44f 3200 mov.w r2, #131072 @ 0x20000
80017de: 651a str r2, [r3, #80] @ 0x50
80017e0: 4b59 ldr r3, [pc, #356] @ (8001948 <HAL_FDCAN_IRQHandler+0x24c>)
80017e2: 2200 movs r2, #0
80017e4: 611a str r2, [r3, #16]
hfdcan->ErrorCode |= HAL_FDCAN_ERROR_RAM_ACCESS;
80017e6: f8d4 309c ldr.w r3, [r4, #156] @ 0x9c
80017ea: f043 0380 orr.w r3, r3, #128 @ 0x80
80017ee: f8c4 309c str.w r3, [r4, #156] @ 0x9c
if (ErrorStatusITs != 0U)
80017f2: 2f00 cmp r7, #0
80017f4: f040 809e bne.w 8001934 <HAL_FDCAN_IRQHandler+0x238>
if (Errors != 0U)
80017f8: b14e cbz r6, 800180e <HAL_FDCAN_IRQHandler+0x112>
__HAL_FDCAN_CLEAR_FLAG(hfdcan, Errors);
80017fa: 6823 ldr r3, [r4, #0]
80017fc: 651e str r6, [r3, #80] @ 0x50
80017fe: 0fb2 lsrs r2, r6, #30
8001800: 4b51 ldr r3, [pc, #324] @ (8001948 <HAL_FDCAN_IRQHandler+0x24c>)
8001802: 611a str r2, [r3, #16]
hfdcan->ErrorCode |= Errors;
8001804: f8d4 309c ldr.w r3, [r4, #156] @ 0x9c
8001808: 4333 orrs r3, r6
800180a: f8c4 309c str.w r3, [r4, #156] @ 0x9c
if (hfdcan->Instance == FDCAN1)
800180e: 6822 ldr r2, [r4, #0]
8001810: 4b4e ldr r3, [pc, #312] @ (800194c <HAL_FDCAN_IRQHandler+0x250>)
8001812: 429a cmp r2, r3
8001814: f000 809c beq.w 8001950 <HAL_FDCAN_IRQHandler+0x254>
if (hfdcan->ErrorCode != HAL_FDCAN_ERROR_NONE)
8001818: f8d4 309c ldr.w r3, [r4, #156] @ 0x9c
800181c: 2b00 cmp r3, #0
800181e: f040 80f9 bne.w 8001a14 <HAL_FDCAN_IRQHandler+0x318>
}
8001822: b003 add sp, #12
8001824: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
__HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_HIGH_PRIORITY_MSG);
8001828: f44f 7280 mov.w r2, #256 @ 0x100
800182c: 651a str r2, [r3, #80] @ 0x50
800182e: 4b46 ldr r3, [pc, #280] @ (8001948 <HAL_FDCAN_IRQHandler+0x24c>)
8001830: 2200 movs r2, #0
8001832: 611a str r2, [r3, #16]
HAL_FDCAN_HighPriorityMessageCallback(hfdcan);
8001834: f7ff ff5a bl 80016ec <HAL_FDCAN_HighPriorityMessageCallback>
8001838: e791 b.n 800175e <HAL_FDCAN_IRQHandler+0x62>
AbortedBuffers = hfdcan->Instance->TXBCF;
800183a: 6823 ldr r3, [r4, #0]
800183c: f8d3 10dc ldr.w r1, [r3, #220] @ 0xdc
AbortedBuffers &= hfdcan->Instance->TXBCIE;
8001840: f8d3 20e4 ldr.w r2, [r3, #228] @ 0xe4
__HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_ABORT_COMPLETE);
8001844: f44f 6080 mov.w r0, #1024 @ 0x400
8001848: 6518 str r0, [r3, #80] @ 0x50
800184a: 4b3f ldr r3, [pc, #252] @ (8001948 <HAL_FDCAN_IRQHandler+0x24c>)
800184c: 2000 movs r0, #0
800184e: 6118 str r0, [r3, #16]
HAL_FDCAN_TxBufferAbortCallback(hfdcan, AbortedBuffers);
8001850: 4011 ands r1, r2
8001852: 4620 mov r0, r4
8001854: f7ff ff46 bl 80016e4 <HAL_FDCAN_TxBufferAbortCallback>
8001858: e787 b.n 800176a <HAL_FDCAN_IRQHandler+0x6e>
__HAL_FDCAN_CLEAR_FLAG(hfdcan, ClkCalibrationITs);
800185a: 6823 ldr r3, [r4, #0]
800185c: 2200 movs r2, #0
800185e: 651a str r2, [r3, #80] @ 0x50
8001860: 9b01 ldr r3, [sp, #4]
8001862: f003 0303 and.w r3, r3, #3
8001866: 4a38 ldr r2, [pc, #224] @ (8001948 <HAL_FDCAN_IRQHandler+0x24c>)
8001868: 6113 str r3, [r2, #16]
HAL_FDCAN_ClockCalibrationCallback(hfdcan, ClkCalibrationITs);
800186a: 9900 ldr r1, [sp, #0]
800186c: 4620 mov r0, r4
800186e: f7ff ff33 bl 80016d8 <HAL_FDCAN_ClockCalibrationCallback>
8001872: e77d b.n 8001770 <HAL_FDCAN_IRQHandler+0x74>
__HAL_FDCAN_CLEAR_FLAG(hfdcan, TxEventFifoITs);
8001874: 6823 ldr r3, [r4, #0]
8001876: f8c3 a050 str.w sl, [r3, #80] @ 0x50
800187a: ea4f 729a mov.w r2, sl, lsr #30
800187e: 4b32 ldr r3, [pc, #200] @ (8001948 <HAL_FDCAN_IRQHandler+0x24c>)
8001880: 611a str r2, [r3, #16]
HAL_FDCAN_TxEventFifoCallback(hfdcan, TxEventFifoITs);
8001882: 4651 mov r1, sl
8001884: 4620 mov r0, r4
8001886: f7ff ff28 bl 80016da <HAL_FDCAN_TxEventFifoCallback>
800188a: e774 b.n 8001776 <HAL_FDCAN_IRQHandler+0x7a>
__HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo0ITs);
800188c: 6823 ldr r3, [r4, #0]
800188e: f8c3 9050 str.w r9, [r3, #80] @ 0x50
8001892: ea4f 7299 mov.w r2, r9, lsr #30
8001896: 4b2c ldr r3, [pc, #176] @ (8001948 <HAL_FDCAN_IRQHandler+0x24c>)
8001898: 611a str r2, [r3, #16]
HAL_FDCAN_RxFifo0Callback(hfdcan, RxFifo0ITs);
800189a: 4649 mov r1, r9
800189c: 4620 mov r0, r4
800189e: f7ff ff1d bl 80016dc <HAL_FDCAN_RxFifo0Callback>
80018a2: e76c b.n 800177e <HAL_FDCAN_IRQHandler+0x82>
__HAL_FDCAN_CLEAR_FLAG(hfdcan, RxFifo1ITs);
80018a4: 6823 ldr r3, [r4, #0]
80018a6: f8c3 8050 str.w r8, [r3, #80] @ 0x50
80018aa: ea4f 7298 mov.w r2, r8, lsr #30
80018ae: 4b26 ldr r3, [pc, #152] @ (8001948 <HAL_FDCAN_IRQHandler+0x24c>)
80018b0: 611a str r2, [r3, #16]
HAL_FDCAN_RxFifo1Callback(hfdcan, RxFifo1ITs);
80018b2: 4641 mov r1, r8
80018b4: 4620 mov r0, r4
80018b6: f7ff ff12 bl 80016de <HAL_FDCAN_RxFifo1Callback>
80018ba: e764 b.n 8001786 <HAL_FDCAN_IRQHandler+0x8a>
__HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_FIFO_EMPTY);
80018bc: 6823 ldr r3, [r4, #0]
80018be: f44f 6200 mov.w r2, #2048 @ 0x800
80018c2: 651a str r2, [r3, #80] @ 0x50
80018c4: 4b20 ldr r3, [pc, #128] @ (8001948 <HAL_FDCAN_IRQHandler+0x24c>)
80018c6: 2200 movs r2, #0
80018c8: 611a str r2, [r3, #16]
HAL_FDCAN_TxFifoEmptyCallback(hfdcan);
80018ca: 4620 mov r0, r4
80018cc: f7ff ff08 bl 80016e0 <HAL_FDCAN_TxFifoEmptyCallback>
80018d0: e760 b.n 8001794 <HAL_FDCAN_IRQHandler+0x98>
TransmittedBuffers = hfdcan->Instance->TXBTO;
80018d2: 6823 ldr r3, [r4, #0]
80018d4: f8d3 10d8 ldr.w r1, [r3, #216] @ 0xd8
TransmittedBuffers &= hfdcan->Instance->TXBTIE;
80018d8: f8d3 20e0 ldr.w r2, [r3, #224] @ 0xe0
__HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TX_COMPLETE);
80018dc: f44f 7000 mov.w r0, #512 @ 0x200
80018e0: 6518 str r0, [r3, #80] @ 0x50
80018e2: 4b19 ldr r3, [pc, #100] @ (8001948 <HAL_FDCAN_IRQHandler+0x24c>)
80018e4: 2000 movs r0, #0
80018e6: 6118 str r0, [r3, #16]
HAL_FDCAN_TxBufferCompleteCallback(hfdcan, TransmittedBuffers);
80018e8: 4011 ands r1, r2
80018ea: 4620 mov r0, r4
80018ec: f7ff fef9 bl 80016e2 <HAL_FDCAN_TxBufferCompleteCallback>
80018f0: e757 b.n 80017a2 <HAL_FDCAN_IRQHandler+0xa6>
__HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE);
80018f2: 6823 ldr r3, [r4, #0]
80018f4: f44f 2200 mov.w r2, #524288 @ 0x80000
80018f8: 651a str r2, [r3, #80] @ 0x50
80018fa: 4b13 ldr r3, [pc, #76] @ (8001948 <HAL_FDCAN_IRQHandler+0x24c>)
80018fc: 2200 movs r2, #0
80018fe: 611a str r2, [r3, #16]
HAL_FDCAN_RxBufferNewMessageCallback(hfdcan);
8001900: 4620 mov r0, r4
8001902: f7ff fef0 bl 80016e6 <HAL_FDCAN_RxBufferNewMessageCallback>
8001906: e753 b.n 80017b0 <HAL_FDCAN_IRQHandler+0xb4>
__HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMESTAMP_WRAPAROUND);
8001908: 6823 ldr r3, [r4, #0]
800190a: f44f 3280 mov.w r2, #65536 @ 0x10000
800190e: 651a str r2, [r3, #80] @ 0x50
8001910: 4b0d ldr r3, [pc, #52] @ (8001948 <HAL_FDCAN_IRQHandler+0x24c>)
8001912: 2200 movs r2, #0
8001914: 611a str r2, [r3, #16]
HAL_FDCAN_TimestampWraparoundCallback(hfdcan);
8001916: 4620 mov r0, r4
8001918: f7ff fee6 bl 80016e8 <HAL_FDCAN_TimestampWraparoundCallback>
800191c: e74f b.n 80017be <HAL_FDCAN_IRQHandler+0xc2>
__HAL_FDCAN_CLEAR_FLAG(hfdcan, FDCAN_FLAG_TIMEOUT_OCCURRED);
800191e: 6823 ldr r3, [r4, #0]
8001920: f44f 2280 mov.w r2, #262144 @ 0x40000
8001924: 651a str r2, [r3, #80] @ 0x50
8001926: 4b08 ldr r3, [pc, #32] @ (8001948 <HAL_FDCAN_IRQHandler+0x24c>)
8001928: 2200 movs r2, #0
800192a: 611a str r2, [r3, #16]
HAL_FDCAN_TimeoutOccurredCallback(hfdcan);
800192c: 4620 mov r0, r4
800192e: f7ff fedc bl 80016ea <HAL_FDCAN_TimeoutOccurredCallback>
8001932: e74b b.n 80017cc <HAL_FDCAN_IRQHandler+0xd0>
__HAL_FDCAN_CLEAR_FLAG(hfdcan, ErrorStatusITs);
8001934: 6823 ldr r3, [r4, #0]
8001936: 651f str r7, [r3, #80] @ 0x50
8001938: 0fba lsrs r2, r7, #30
800193a: 4b03 ldr r3, [pc, #12] @ (8001948 <HAL_FDCAN_IRQHandler+0x24c>)
800193c: 611a str r2, [r3, #16]
HAL_FDCAN_ErrorStatusCallback(hfdcan, ErrorStatusITs);
800193e: 4639 mov r1, r7
8001940: 4620 mov r0, r4
8001942: f7ff fed5 bl 80016f0 <HAL_FDCAN_ErrorStatusCallback>
8001946: e757 b.n 80017f8 <HAL_FDCAN_IRQHandler+0xfc>
8001948: 4000a800 .word 0x4000a800
800194c: 4000a000 .word 0x4000a000
if ((hfdcan->ttcan->TTOCF & FDCAN_TTOCF_OM) != 0U)
8001950: 6863 ldr r3, [r4, #4]
8001952: 689a ldr r2, [r3, #8]
8001954: f012 0f03 tst.w r2, #3
8001958: f43f af5e beq.w 8001818 <HAL_FDCAN_IRQHandler+0x11c>
TTSchedSyncITs = hfdcan->ttcan->TTIR & FDCAN_TT_SCHEDULE_SYNC_MASK;
800195c: 6a19 ldr r1, [r3, #32]
800195e: f001 010f and.w r1, r1, #15
TTSchedSyncITs &= hfdcan->ttcan->TTIE;
8001962: 6a5a ldr r2, [r3, #36] @ 0x24
TTTimeMarkITs = hfdcan->ttcan->TTIR & FDCAN_TT_TIME_MARK_MASK;
8001964: 6a18 ldr r0, [r3, #32]
8001966: f000 0830 and.w r8, r0, #48 @ 0x30
TTTimeMarkITs &= hfdcan->ttcan->TTIE;
800196a: 6a58 ldr r0, [r3, #36] @ 0x24
800196c: ea08 0800 and.w r8, r8, r0
TTGlobTimeITs = hfdcan->ttcan->TTIR & FDCAN_TT_GLOBAL_TIME_MASK;
8001970: 6a1f ldr r7, [r3, #32]
8001972: f407 77c0 and.w r7, r7, #384 @ 0x180
TTGlobTimeITs &= hfdcan->ttcan->TTIE;
8001976: 6a58 ldr r0, [r3, #36] @ 0x24
8001978: 4007 ands r7, r0
TTDistErrors = hfdcan->ttcan->TTIR & FDCAN_TT_DISTURBING_ERROR_MASK;
800197a: 6a1e ldr r6, [r3, #32]
800197c: f406 46fc and.w r6, r6, #32256 @ 0x7e00
TTDistErrors &= hfdcan->ttcan->TTIE;
8001980: 6a58 ldr r0, [r3, #36] @ 0x24
8001982: 4006 ands r6, r0
TTFatalErrors = hfdcan->ttcan->TTIR & FDCAN_TT_FATAL_ERROR_MASK;
8001984: 6a1d ldr r5, [r3, #32]
8001986: f405 25f0 and.w r5, r5, #491520 @ 0x78000
TTFatalErrors &= hfdcan->ttcan->TTIE;
800198a: 6a58 ldr r0, [r3, #36] @ 0x24
800198c: 4005 ands r5, r0
itsourceTTIE = hfdcan->ttcan->TTIE;
800198e: f8d3 9024 ldr.w r9, [r3, #36] @ 0x24
itflagTTIR = hfdcan->ttcan->TTIR;
8001992: f8d3 a020 ldr.w sl, [r3, #32]
if (TTSchedSyncITs != 0U)
8001996: 4011 ands r1, r2
8001998: d11c bne.n 80019d4 <HAL_FDCAN_IRQHandler+0x2d8>
if (TTTimeMarkITs != 0U)
800199a: f1b8 0f00 cmp.w r8, #0
800199e: d11e bne.n 80019de <HAL_FDCAN_IRQHandler+0x2e2>
if (FDCAN_CHECK_IT_SOURCE(itsourceTTIE, FDCAN_TT_IT_STOP_WATCH) != RESET)
80019a0: f019 0f40 tst.w r9, #64 @ 0x40
80019a4: d002 beq.n 80019ac <HAL_FDCAN_IRQHandler+0x2b0>
if (FDCAN_CHECK_FLAG(itflagTTIR, FDCAN_TT_FLAG_STOP_WATCH) != RESET)
80019a6: f01a 0f40 tst.w sl, #64 @ 0x40
80019aa: d120 bne.n 80019ee <HAL_FDCAN_IRQHandler+0x2f2>
if (TTGlobTimeITs != 0U)
80019ac: bb5f cbnz r7, 8001a06 <HAL_FDCAN_IRQHandler+0x30a>
if (TTDistErrors != 0U)
80019ae: b136 cbz r6, 80019be <HAL_FDCAN_IRQHandler+0x2c2>
__HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTDistErrors);
80019b0: 6863 ldr r3, [r4, #4]
80019b2: 621e str r6, [r3, #32]
hfdcan->ErrorCode |= TTDistErrors;
80019b4: f8d4 309c ldr.w r3, [r4, #156] @ 0x9c
80019b8: 4333 orrs r3, r6
80019ba: f8c4 309c str.w r3, [r4, #156] @ 0x9c
if (TTFatalErrors != 0U)
80019be: 2d00 cmp r5, #0
80019c0: f43f af2a beq.w 8001818 <HAL_FDCAN_IRQHandler+0x11c>
__HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTFatalErrors);
80019c4: 6863 ldr r3, [r4, #4]
80019c6: 621d str r5, [r3, #32]
hfdcan->ErrorCode |= TTFatalErrors;
80019c8: f8d4 309c ldr.w r3, [r4, #156] @ 0x9c
80019cc: 432b orrs r3, r5
80019ce: f8c4 309c str.w r3, [r4, #156] @ 0x9c
80019d2: e721 b.n 8001818 <HAL_FDCAN_IRQHandler+0x11c>
__HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTSchedSyncITs);
80019d4: 6219 str r1, [r3, #32]
HAL_FDCAN_TT_ScheduleSyncCallback(hfdcan, TTSchedSyncITs);
80019d6: 4620 mov r0, r4
80019d8: f7ff fe8b bl 80016f2 <HAL_FDCAN_TT_ScheduleSyncCallback>
80019dc: e7dd b.n 800199a <HAL_FDCAN_IRQHandler+0x29e>
__HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTTimeMarkITs);
80019de: 6863 ldr r3, [r4, #4]
80019e0: f8c3 8020 str.w r8, [r3, #32]
HAL_FDCAN_TT_TimeMarkCallback(hfdcan, TTTimeMarkITs);
80019e4: 4641 mov r1, r8
80019e6: 4620 mov r0, r4
80019e8: f7ff fe84 bl 80016f4 <HAL_FDCAN_TT_TimeMarkCallback>
80019ec: e7d8 b.n 80019a0 <HAL_FDCAN_IRQHandler+0x2a4>
SWTime = ((hfdcan->ttcan->TTCPT & FDCAN_TTCPT_SWV) >> FDCAN_TTCPT_SWV_Pos);
80019ee: 6863 ldr r3, [r4, #4]
80019f0: 6bd9 ldr r1, [r3, #60] @ 0x3c
SWCycleCount = ((hfdcan->ttcan->TTCPT & FDCAN_TTCPT_CCV) >> FDCAN_TTCPT_CCV_Pos);
80019f2: 6bda ldr r2, [r3, #60] @ 0x3c
__HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, FDCAN_TT_FLAG_STOP_WATCH);
80019f4: 2040 movs r0, #64 @ 0x40
80019f6: 6218 str r0, [r3, #32]
HAL_FDCAN_TT_StopWatchCallback(hfdcan, SWTime, SWCycleCount);
80019f8: f002 023f and.w r2, r2, #63 @ 0x3f
80019fc: 0c09 lsrs r1, r1, #16
80019fe: 4620 mov r0, r4
8001a00: f7ff fe79 bl 80016f6 <HAL_FDCAN_TT_StopWatchCallback>
8001a04: e7d2 b.n 80019ac <HAL_FDCAN_IRQHandler+0x2b0>
__HAL_FDCAN_TT_CLEAR_FLAG(hfdcan, TTGlobTimeITs);
8001a06: 6863 ldr r3, [r4, #4]
8001a08: 621f str r7, [r3, #32]
HAL_FDCAN_TT_GlobalTimeCallback(hfdcan, TTGlobTimeITs);
8001a0a: 4639 mov r1, r7
8001a0c: 4620 mov r0, r4
8001a0e: f7ff fe73 bl 80016f8 <HAL_FDCAN_TT_GlobalTimeCallback>
8001a12: e7cc b.n 80019ae <HAL_FDCAN_IRQHandler+0x2b2>
HAL_FDCAN_ErrorCallback(hfdcan);
8001a14: 4620 mov r0, r4
8001a16: f7ff fe6a bl 80016ee <HAL_FDCAN_ErrorCallback>
}
8001a1a: e702 b.n 8001822 <HAL_FDCAN_IRQHandler+0x126>
08001a1c <HAL_GPIO_Init>:
* @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
8001a1c: b5f0 push {r4, r5, r6, r7, lr}
8001a1e: b083 sub sp, #12
uint32_t position = 0x00U;
8001a20: 2300 movs r3, #0
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0x00U)
8001a22: e06b b.n 8001afc <HAL_GPIO_Init+0xe0>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
8001a24: 6885 ldr r5, [r0, #8]
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
8001a26: 005e lsls r6, r3, #1
8001a28: 2403 movs r4, #3
8001a2a: 40b4 lsls r4, r6
8001a2c: ea25 0504 bic.w r5, r5, r4
temp |= (GPIO_Init->Speed << (position * 2U));
8001a30: 68cc ldr r4, [r1, #12]
8001a32: 40b4 lsls r4, r6
8001a34: 432c orrs r4, r5
GPIOx->OSPEEDR = temp;
8001a36: 6084 str r4, [r0, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
8001a38: 6845 ldr r5, [r0, #4]
temp &= ~(GPIO_OTYPER_OT0 << position) ;
8001a3a: ea25 050c bic.w r5, r5, ip
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
8001a3e: 684c ldr r4, [r1, #4]
8001a40: f3c4 1400 ubfx r4, r4, #4, #1
8001a44: 409c lsls r4, r3
8001a46: 432c orrs r4, r5
GPIOx->OTYPER = temp;
8001a48: 6044 str r4, [r0, #4]
8001a4a: e069 b.n 8001b20 <HAL_GPIO_Init+0x104>
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3U];
8001a4c: 08dd lsrs r5, r3, #3
8001a4e: 3508 adds r5, #8
8001a50: f850 4025 ldr.w r4, [r0, r5, lsl #2]
temp &= ~(0xFU << ((position & 0x07U) * 4U));
8001a54: f003 0c07 and.w ip, r3, #7
8001a58: ea4f 0c8c mov.w ip, ip, lsl #2
8001a5c: f04f 0e0f mov.w lr, #15
8001a60: fa0e fe0c lsl.w lr, lr, ip
8001a64: ea24 0e0e bic.w lr, r4, lr
temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
8001a68: 690c ldr r4, [r1, #16]
8001a6a: fa04 f40c lsl.w r4, r4, ip
8001a6e: ea44 040e orr.w r4, r4, lr
GPIOx->AFR[position >> 3U] = temp;
8001a72: f840 4025 str.w r4, [r0, r5, lsl #2]
8001a76: e06b b.n 8001b50 <HAL_GPIO_Init+0x134>
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
temp = SYSCFG->EXTICR[position >> 2U];
temp &= ~(0x0FUL << (4U * (position & 0x03U)));
temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
8001a78: 2409 movs r4, #9
8001a7a: e000 b.n 8001a7e <HAL_GPIO_Init+0x62>
8001a7c: 2400 movs r4, #0
8001a7e: fa04 f40e lsl.w r4, r4, lr
8001a82: 432c orrs r4, r5
SYSCFG->EXTICR[position >> 2U] = temp;
8001a84: f10c 0c02 add.w ip, ip, #2
8001a88: 4d69 ldr r5, [pc, #420] @ (8001c30 <HAL_GPIO_Init+0x214>)
8001a8a: f845 402c str.w r4, [r5, ip, lsl #2]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR1;
8001a8e: f04f 44b0 mov.w r4, #1476395008 @ 0x58000000
8001a92: 6825 ldr r5, [r4, #0]
temp &= ~(iocurrent);
8001a94: 43d4 mvns r4, r2
8001a96: ea25 0602 bic.w r6, r5, r2
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
8001a9a: 684f ldr r7, [r1, #4]
8001a9c: f417 1f80 tst.w r7, #1048576 @ 0x100000
8001aa0: d001 beq.n 8001aa6 <HAL_GPIO_Init+0x8a>
{
temp |= iocurrent;
8001aa2: ea42 0605 orr.w r6, r2, r5
}
EXTI->RTSR1 = temp;
8001aa6: f04f 45b0 mov.w r5, #1476395008 @ 0x58000000
8001aaa: 602e str r6, [r5, #0]
temp = EXTI->FTSR1;
8001aac: 686d ldr r5, [r5, #4]
temp &= ~(iocurrent);
8001aae: ea04 0605 and.w r6, r4, r5
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
8001ab2: 684f ldr r7, [r1, #4]
8001ab4: f417 1f00 tst.w r7, #2097152 @ 0x200000
8001ab8: d001 beq.n 8001abe <HAL_GPIO_Init+0xa2>
{
temp |= iocurrent;
8001aba: ea42 0605 orr.w r6, r2, r5
}
EXTI->FTSR1 = temp;
8001abe: f04f 45b0 mov.w r5, #1476395008 @ 0x58000000
8001ac2: 606e str r6, [r5, #4]
temp = EXTI_CurrentCPU->EMR1;
8001ac4: f8d5 5084 ldr.w r5, [r5, #132] @ 0x84
temp &= ~(iocurrent);
8001ac8: ea04 0605 and.w r6, r4, r5
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
8001acc: 684f ldr r7, [r1, #4]
8001ace: f417 3f00 tst.w r7, #131072 @ 0x20000
8001ad2: d001 beq.n 8001ad8 <HAL_GPIO_Init+0xbc>
{
temp |= iocurrent;
8001ad4: ea42 0605 orr.w r6, r2, r5
}
EXTI_CurrentCPU->EMR1 = temp;
8001ad8: f04f 45b0 mov.w r5, #1476395008 @ 0x58000000
8001adc: f8c5 6084 str.w r6, [r5, #132] @ 0x84
/* Clear EXTI line configuration */
temp = EXTI_CurrentCPU->IMR1;
8001ae0: f8d5 5080 ldr.w r5, [r5, #128] @ 0x80
temp &= ~(iocurrent);
8001ae4: 402c ands r4, r5
if ((GPIO_Init->Mode & EXTI_IT) != 0x00U)
8001ae6: 684e ldr r6, [r1, #4]
8001ae8: f416 3f80 tst.w r6, #65536 @ 0x10000
8001aec: d001 beq.n 8001af2 <HAL_GPIO_Init+0xd6>
{
temp |= iocurrent;
8001aee: ea42 0405 orr.w r4, r2, r5
}
EXTI_CurrentCPU->IMR1 = temp;
8001af2: f04f 42b0 mov.w r2, #1476395008 @ 0x58000000
8001af6: f8c2 4080 str.w r4, [r2, #128] @ 0x80
}
}
position++;
8001afa: 3301 adds r3, #1
while (((GPIO_Init->Pin) >> position) != 0x00U)
8001afc: 680a ldr r2, [r1, #0]
8001afe: fa32 f403 lsrs.w r4, r2, r3
8001b02: f000 8092 beq.w 8001c2a <HAL_GPIO_Init+0x20e>
iocurrent = (GPIO_Init->Pin) & (1UL << position);
8001b06: f04f 0c01 mov.w ip, #1
8001b0a: fa0c fc03 lsl.w ip, ip, r3
if (iocurrent != 0x00U)
8001b0e: ea1c 0202 ands.w r2, ip, r2
8001b12: d0f2 beq.n 8001afa <HAL_GPIO_Init+0xde>
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
8001b14: 684c ldr r4, [r1, #4]
8001b16: f004 0403 and.w r4, r4, #3
8001b1a: 3c01 subs r4, #1
8001b1c: 2c01 cmp r4, #1
8001b1e: d981 bls.n 8001a24 <HAL_GPIO_Init+0x8>
if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
8001b20: 684c ldr r4, [r1, #4]
8001b22: f004 0403 and.w r4, r4, #3
8001b26: 2c03 cmp r4, #3
8001b28: d00c beq.n 8001b44 <HAL_GPIO_Init+0x128>
temp = GPIOx->PUPDR;
8001b2a: 68c4 ldr r4, [r0, #12]
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
8001b2c: 005d lsls r5, r3, #1
8001b2e: f04f 0c03 mov.w ip, #3
8001b32: fa0c fc05 lsl.w ip, ip, r5
8001b36: ea24 0c0c bic.w ip, r4, ip
temp |= ((GPIO_Init->Pull) << (position * 2U));
8001b3a: 688c ldr r4, [r1, #8]
8001b3c: 40ac lsls r4, r5
8001b3e: ea44 040c orr.w r4, r4, ip
GPIOx->PUPDR = temp;
8001b42: 60c4 str r4, [r0, #12]
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
8001b44: 684c ldr r4, [r1, #4]
8001b46: f004 0403 and.w r4, r4, #3
8001b4a: 2c02 cmp r4, #2
8001b4c: f43f af7e beq.w 8001a4c <HAL_GPIO_Init+0x30>
temp = GPIOx->MODER;
8001b50: 6804 ldr r4, [r0, #0]
temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
8001b52: ea4f 0e43 mov.w lr, r3, lsl #1
8001b56: f04f 0c03 mov.w ip, #3
8001b5a: fa0c fc0e lsl.w ip, ip, lr
8001b5e: ea24 0c0c bic.w ip, r4, ip
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
8001b62: 684c ldr r4, [r1, #4]
8001b64: f004 0403 and.w r4, r4, #3
8001b68: fa04 f40e lsl.w r4, r4, lr
8001b6c: ea44 040c orr.w r4, r4, ip
GPIOx->MODER = temp;
8001b70: 6004 str r4, [r0, #0]
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
8001b72: 684c ldr r4, [r1, #4]
8001b74: f414 3f40 tst.w r4, #196608 @ 0x30000
8001b78: d0bf beq.n 8001afa <HAL_GPIO_Init+0xde>
__HAL_RCC_SYSCFG_CLK_ENABLE();
8001b7a: 4c2e ldr r4, [pc, #184] @ (8001c34 <HAL_GPIO_Init+0x218>)
8001b7c: f8d4 5154 ldr.w r5, [r4, #340] @ 0x154
8001b80: f045 0502 orr.w r5, r5, #2
8001b84: f8c4 5154 str.w r5, [r4, #340] @ 0x154
8001b88: f8d4 4154 ldr.w r4, [r4, #340] @ 0x154
8001b8c: f004 0402 and.w r4, r4, #2
8001b90: 9401 str r4, [sp, #4]
8001b92: 9c01 ldr r4, [sp, #4]
temp = SYSCFG->EXTICR[position >> 2U];
8001b94: ea4f 0c93 mov.w ip, r3, lsr #2
8001b98: f10c 0502 add.w r5, ip, #2
8001b9c: 4c24 ldr r4, [pc, #144] @ (8001c30 <HAL_GPIO_Init+0x214>)
8001b9e: f854 5025 ldr.w r5, [r4, r5, lsl #2]
temp &= ~(0x0FUL << (4U * (position & 0x03U)));
8001ba2: f003 0e03 and.w lr, r3, #3
8001ba6: ea4f 0e8e mov.w lr, lr, lsl #2
8001baa: 240f movs r4, #15
8001bac: fa04 f40e lsl.w r4, r4, lr
8001bb0: ea25 0504 bic.w r5, r5, r4
temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
8001bb4: 4c20 ldr r4, [pc, #128] @ (8001c38 <HAL_GPIO_Init+0x21c>)
8001bb6: 42a0 cmp r0, r4
8001bb8: f43f af60 beq.w 8001a7c <HAL_GPIO_Init+0x60>
8001bbc: f504 6480 add.w r4, r4, #1024 @ 0x400
8001bc0: 42a0 cmp r0, r4
8001bc2: d022 beq.n 8001c0a <HAL_GPIO_Init+0x1ee>
8001bc4: f504 6480 add.w r4, r4, #1024 @ 0x400
8001bc8: 42a0 cmp r0, r4
8001bca: d020 beq.n 8001c0e <HAL_GPIO_Init+0x1f2>
8001bcc: f504 6480 add.w r4, r4, #1024 @ 0x400
8001bd0: 42a0 cmp r0, r4
8001bd2: d01e beq.n 8001c12 <HAL_GPIO_Init+0x1f6>
8001bd4: f504 6480 add.w r4, r4, #1024 @ 0x400
8001bd8: 42a0 cmp r0, r4
8001bda: d01c beq.n 8001c16 <HAL_GPIO_Init+0x1fa>
8001bdc: f504 6480 add.w r4, r4, #1024 @ 0x400
8001be0: 42a0 cmp r0, r4
8001be2: d01a beq.n 8001c1a <HAL_GPIO_Init+0x1fe>
8001be4: f504 6480 add.w r4, r4, #1024 @ 0x400
8001be8: 42a0 cmp r0, r4
8001bea: d018 beq.n 8001c1e <HAL_GPIO_Init+0x202>
8001bec: f504 6480 add.w r4, r4, #1024 @ 0x400
8001bf0: 42a0 cmp r0, r4
8001bf2: d016 beq.n 8001c22 <HAL_GPIO_Init+0x206>
8001bf4: f504 6480 add.w r4, r4, #1024 @ 0x400
8001bf8: 42a0 cmp r0, r4
8001bfa: d014 beq.n 8001c26 <HAL_GPIO_Init+0x20a>
8001bfc: f504 6480 add.w r4, r4, #1024 @ 0x400
8001c00: 42a0 cmp r0, r4
8001c02: f43f af39 beq.w 8001a78 <HAL_GPIO_Init+0x5c>
8001c06: 240a movs r4, #10
8001c08: e739 b.n 8001a7e <HAL_GPIO_Init+0x62>
8001c0a: 2401 movs r4, #1
8001c0c: e737 b.n 8001a7e <HAL_GPIO_Init+0x62>
8001c0e: 2402 movs r4, #2
8001c10: e735 b.n 8001a7e <HAL_GPIO_Init+0x62>
8001c12: 2403 movs r4, #3
8001c14: e733 b.n 8001a7e <HAL_GPIO_Init+0x62>
8001c16: 2404 movs r4, #4
8001c18: e731 b.n 8001a7e <HAL_GPIO_Init+0x62>
8001c1a: 2405 movs r4, #5
8001c1c: e72f b.n 8001a7e <HAL_GPIO_Init+0x62>
8001c1e: 2406 movs r4, #6
8001c20: e72d b.n 8001a7e <HAL_GPIO_Init+0x62>
8001c22: 2407 movs r4, #7
8001c24: e72b b.n 8001a7e <HAL_GPIO_Init+0x62>
8001c26: 2408 movs r4, #8
8001c28: e729 b.n 8001a7e <HAL_GPIO_Init+0x62>
}
}
8001c2a: b003 add sp, #12
8001c2c: bdf0 pop {r4, r5, r6, r7, pc}
8001c2e: bf00 nop
8001c30: 58000400 .word 0x58000400
8001c34: 58024400 .word 0x58024400
8001c38: 58020000 .word 0x58020000
08001c3c <HAL_GPIO_WritePin>:
{
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if (PinState != GPIO_PIN_RESET)
8001c3c: b10a cbz r2, 8001c42 <HAL_GPIO_WritePin+0x6>
{
GPIOx->BSRR = GPIO_Pin;
8001c3e: 6181 str r1, [r0, #24]
8001c40: 4770 bx lr
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;
8001c42: 0409 lsls r1, r1, #16
8001c44: 6181 str r1, [r0, #24]
}
}
8001c46: 4770 bx lr
08001c48 <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8001c48: b082 sub sp, #8
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8001c4a: 4b07 ldr r3, [pc, #28] @ (8001c68 <HAL_MspInit+0x20>)
8001c4c: f8d3 2154 ldr.w r2, [r3, #340] @ 0x154
8001c50: f042 0202 orr.w r2, r2, #2
8001c54: f8c3 2154 str.w r2, [r3, #340] @ 0x154
8001c58: f8d3 3154 ldr.w r3, [r3, #340] @ 0x154
8001c5c: f003 0302 and.w r3, r3, #2
8001c60: 9301 str r3, [sp, #4]
8001c62: 9b01 ldr r3, [sp, #4]
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
8001c64: b002 add sp, #8
8001c66: 4770 bx lr
8001c68: 58024400 .word 0x58024400
08001c6c <HAL_ADC_MspInit>:
* This function configures the hardware resources used in this example
* @param hadc: ADC handle pointer
* @retval None
*/
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
{
8001c6c: b500 push {lr}
8001c6e: b08b sub sp, #44 @ 0x2c
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001c70: 2300 movs r3, #0
8001c72: 9305 str r3, [sp, #20]
8001c74: 9306 str r3, [sp, #24]
8001c76: 9307 str r3, [sp, #28]
8001c78: 9308 str r3, [sp, #32]
8001c7a: 9309 str r3, [sp, #36] @ 0x24
if(hadc->Instance==ADC1)
8001c7c: 6803 ldr r3, [r0, #0]
8001c7e: 4a2e ldr r2, [pc, #184] @ (8001d38 <HAL_ADC_MspInit+0xcc>)
8001c80: 4293 cmp r3, r2
8001c82: d005 beq.n 8001c90 <HAL_ADC_MspInit+0x24>
/* USER CODE BEGIN ADC1_MspInit 1 */
/* USER CODE END ADC1_MspInit 1 */
}
else if(hadc->Instance==ADC2)
8001c84: 4a2d ldr r2, [pc, #180] @ (8001d3c <HAL_ADC_MspInit+0xd0>)
8001c86: 4293 cmp r3, r2
8001c88: d02c beq.n 8001ce4 <HAL_ADC_MspInit+0x78>
/* USER CODE BEGIN ADC2_MspInit 1 */
/* USER CODE END ADC2_MspInit 1 */
}
}
8001c8a: b00b add sp, #44 @ 0x2c
8001c8c: f85d fb04 ldr.w pc, [sp], #4
HAL_RCC_ADC12_CLK_ENABLED++;
8001c90: 4a2b ldr r2, [pc, #172] @ (8001d40 <HAL_ADC_MspInit+0xd4>)
8001c92: 6813 ldr r3, [r2, #0]
8001c94: 3301 adds r3, #1
8001c96: 6013 str r3, [r2, #0]
if(HAL_RCC_ADC12_CLK_ENABLED==1){
8001c98: 2b01 cmp r3, #1
8001c9a: d015 beq.n 8001cc8 <HAL_ADC_MspInit+0x5c>
__HAL_RCC_GPIOC_CLK_ENABLE();
8001c9c: 4b29 ldr r3, [pc, #164] @ (8001d44 <HAL_ADC_MspInit+0xd8>)
8001c9e: f8d3 2140 ldr.w r2, [r3, #320] @ 0x140
8001ca2: f042 0204 orr.w r2, r2, #4
8001ca6: f8c3 2140 str.w r2, [r3, #320] @ 0x140
8001caa: f8d3 3140 ldr.w r3, [r3, #320] @ 0x140
8001cae: f003 0304 and.w r3, r3, #4
8001cb2: 9302 str r3, [sp, #8]
8001cb4: 9b02 ldr r3, [sp, #8]
GPIO_InitStruct.Pin = LV_I_measure_Pin;
8001cb6: 2301 movs r3, #1
8001cb8: 9305 str r3, [sp, #20]
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8001cba: 2303 movs r3, #3
8001cbc: 9306 str r3, [sp, #24]
HAL_GPIO_Init(LV_I_measure_GPIO_Port, &GPIO_InitStruct);
8001cbe: a905 add r1, sp, #20
8001cc0: 4821 ldr r0, [pc, #132] @ (8001d48 <HAL_ADC_MspInit+0xdc>)
8001cc2: f7ff feab bl 8001a1c <HAL_GPIO_Init>
8001cc6: e7e0 b.n 8001c8a <HAL_ADC_MspInit+0x1e>
__HAL_RCC_ADC12_CLK_ENABLE();
8001cc8: 4b1e ldr r3, [pc, #120] @ (8001d44 <HAL_ADC_MspInit+0xd8>)
8001cca: f8d3 2138 ldr.w r2, [r3, #312] @ 0x138
8001cce: f042 0220 orr.w r2, r2, #32
8001cd2: f8c3 2138 str.w r2, [r3, #312] @ 0x138
8001cd6: f8d3 3138 ldr.w r3, [r3, #312] @ 0x138
8001cda: f003 0320 and.w r3, r3, #32
8001cde: 9301 str r3, [sp, #4]
8001ce0: 9b01 ldr r3, [sp, #4]
8001ce2: e7db b.n 8001c9c <HAL_ADC_MspInit+0x30>
HAL_RCC_ADC12_CLK_ENABLED++;
8001ce4: 4a16 ldr r2, [pc, #88] @ (8001d40 <HAL_ADC_MspInit+0xd4>)
8001ce6: 6813 ldr r3, [r2, #0]
8001ce8: 3301 adds r3, #1
8001cea: 6013 str r3, [r2, #0]
if(HAL_RCC_ADC12_CLK_ENABLED==1){
8001cec: 2b01 cmp r3, #1
8001cee: d014 beq.n 8001d1a <HAL_ADC_MspInit+0xae>
__HAL_RCC_GPIOC_CLK_ENABLE();
8001cf0: 4b14 ldr r3, [pc, #80] @ (8001d44 <HAL_ADC_MspInit+0xd8>)
8001cf2: f8d3 2140 ldr.w r2, [r3, #320] @ 0x140
8001cf6: f042 0204 orr.w r2, r2, #4
8001cfa: f8c3 2140 str.w r2, [r3, #320] @ 0x140
8001cfe: f8d3 3140 ldr.w r3, [r3, #320] @ 0x140
8001d02: f003 0304 and.w r3, r3, #4
8001d06: 9304 str r3, [sp, #16]
8001d08: 9b04 ldr r3, [sp, #16]
GPIO_InitStruct.Pin = LV_I_measure_Pin|TEMP_TSDCDC_Pin;
8001d0a: 2303 movs r3, #3
8001d0c: 9305 str r3, [sp, #20]
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8001d0e: 9306 str r3, [sp, #24]
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8001d10: a905 add r1, sp, #20
8001d12: 480d ldr r0, [pc, #52] @ (8001d48 <HAL_ADC_MspInit+0xdc>)
8001d14: f7ff fe82 bl 8001a1c <HAL_GPIO_Init>
}
8001d18: e7b7 b.n 8001c8a <HAL_ADC_MspInit+0x1e>
__HAL_RCC_ADC12_CLK_ENABLE();
8001d1a: 4b0a ldr r3, [pc, #40] @ (8001d44 <HAL_ADC_MspInit+0xd8>)
8001d1c: f8d3 2138 ldr.w r2, [r3, #312] @ 0x138
8001d20: f042 0220 orr.w r2, r2, #32
8001d24: f8c3 2138 str.w r2, [r3, #312] @ 0x138
8001d28: f8d3 3138 ldr.w r3, [r3, #312] @ 0x138
8001d2c: f003 0320 and.w r3, r3, #32
8001d30: 9303 str r3, [sp, #12]
8001d32: 9b03 ldr r3, [sp, #12]
8001d34: e7dc b.n 8001cf0 <HAL_ADC_MspInit+0x84>
8001d36: bf00 nop
8001d38: 40022000 .word 0x40022000
8001d3c: 40022100 .word 0x40022100
8001d40: 200002f4 .word 0x200002f4
8001d44: 58024400 .word 0x58024400
8001d48: 58020800 .word 0x58020800
08001d4c <HAL_FDCAN_MspInit>:
* This function configures the hardware resources used in this example
* @param hfdcan: FDCAN handle pointer
* @retval None
*/
void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef* hfdcan)
{
8001d4c: b500 push {lr}
8001d4e: b089 sub sp, #36 @ 0x24
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001d50: 2300 movs r3, #0
8001d52: 9303 str r3, [sp, #12]
8001d54: 9304 str r3, [sp, #16]
8001d56: 9305 str r3, [sp, #20]
8001d58: 9306 str r3, [sp, #24]
8001d5a: 9307 str r3, [sp, #28]
if(hfdcan->Instance==FDCAN1)
8001d5c: 6802 ldr r2, [r0, #0]
8001d5e: 4b19 ldr r3, [pc, #100] @ (8001dc4 <HAL_FDCAN_MspInit+0x78>)
8001d60: 429a cmp r2, r3
8001d62: d002 beq.n 8001d6a <HAL_FDCAN_MspInit+0x1e>
/* USER CODE BEGIN FDCAN1_MspInit 1 */
/* USER CODE END FDCAN1_MspInit 1 */
}
}
8001d64: b009 add sp, #36 @ 0x24
8001d66: f85d fb04 ldr.w pc, [sp], #4
__HAL_RCC_FDCAN_CLK_ENABLE();
8001d6a: 4b17 ldr r3, [pc, #92] @ (8001dc8 <HAL_FDCAN_MspInit+0x7c>)
8001d6c: f8d3 214c ldr.w r2, [r3, #332] @ 0x14c
8001d70: f442 7280 orr.w r2, r2, #256 @ 0x100
8001d74: f8c3 214c str.w r2, [r3, #332] @ 0x14c
8001d78: f8d3 214c ldr.w r2, [r3, #332] @ 0x14c
8001d7c: f402 7280 and.w r2, r2, #256 @ 0x100
8001d80: 9201 str r2, [sp, #4]
8001d82: 9a01 ldr r2, [sp, #4]
__HAL_RCC_GPIOB_CLK_ENABLE();
8001d84: f8d3 2140 ldr.w r2, [r3, #320] @ 0x140
8001d88: f042 0202 orr.w r2, r2, #2
8001d8c: f8c3 2140 str.w r2, [r3, #320] @ 0x140
8001d90: f8d3 3140 ldr.w r3, [r3, #320] @ 0x140
8001d94: f003 0302 and.w r3, r3, #2
8001d98: 9302 str r3, [sp, #8]
8001d9a: 9b02 ldr r3, [sp, #8]
GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9;
8001d9c: f44f 7340 mov.w r3, #768 @ 0x300
8001da0: 9303 str r3, [sp, #12]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001da2: 2302 movs r3, #2
8001da4: 9304 str r3, [sp, #16]
GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN1;
8001da6: 2309 movs r3, #9
8001da8: 9307 str r3, [sp, #28]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8001daa: a903 add r1, sp, #12
8001dac: 4807 ldr r0, [pc, #28] @ (8001dcc <HAL_FDCAN_MspInit+0x80>)
8001dae: f7ff fe35 bl 8001a1c <HAL_GPIO_Init>
HAL_NVIC_SetPriority(FDCAN1_IT0_IRQn, 0, 0);
8001db2: 2200 movs r2, #0
8001db4: 4611 mov r1, r2
8001db6: 2013 movs r0, #19
8001db8: f7ff fa32 bl 8001220 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(FDCAN1_IT0_IRQn);
8001dbc: 2013 movs r0, #19
8001dbe: f7ff fa3f bl 8001240 <HAL_NVIC_EnableIRQ>
}
8001dc2: e7cf b.n 8001d64 <HAL_FDCAN_MspInit+0x18>
8001dc4: 4000a000 .word 0x4000a000
8001dc8: 58024400 .word 0x58024400
8001dcc: 58020400 .word 0x58020400
08001dd0 <HAL_SPI_MspInit>:
* This function configures the hardware resources used in this example
* @param hspi: SPI handle pointer
* @retval None
*/
void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
{
8001dd0: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
8001dd4: b0be sub sp, #248 @ 0xf8
8001dd6: 4604 mov r4, r0
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001dd8: 2100 movs r1, #0
8001dda: 9139 str r1, [sp, #228] @ 0xe4
8001ddc: 913a str r1, [sp, #232] @ 0xe8
8001dde: 913b str r1, [sp, #236] @ 0xec
8001de0: 913c str r1, [sp, #240] @ 0xf0
8001de2: 913d str r1, [sp, #244] @ 0xf4
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
8001de4: 22c0 movs r2, #192 @ 0xc0
8001de6: a808 add r0, sp, #32
8001de8: f002 ff93 bl 8004d12 <memset>
if(hspi->Instance==SPI1)
8001dec: 6823 ldr r3, [r4, #0]
8001dee: 4a5c ldr r2, [pc, #368] @ (8001f60 <HAL_SPI_MspInit+0x190>)
8001df0: 4293 cmp r3, r2
8001df2: d005 beq.n 8001e00 <HAL_SPI_MspInit+0x30>
/* USER CODE BEGIN SPI1_MspInit 1 */
/* USER CODE END SPI1_MspInit 1 */
}
else if(hspi->Instance==SPI2)
8001df4: 4a5b ldr r2, [pc, #364] @ (8001f64 <HAL_SPI_MspInit+0x194>)
8001df6: 4293 cmp r3, r2
8001df8: d04f beq.n 8001e9a <HAL_SPI_MspInit+0xca>
/* USER CODE BEGIN SPI2_MspInit 1 */
/* USER CODE END SPI2_MspInit 1 */
}
}
8001dfa: b03e add sp, #248 @ 0xf8
8001dfc: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SPI1;
8001e00: f44f 5280 mov.w r2, #4096 @ 0x1000
8001e04: 2300 movs r3, #0
8001e06: e9cd 2308 strd r2, r3, [sp, #32]
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
8001e0a: a808 add r0, sp, #32
8001e0c: f000 ffc8 bl 8002da0 <HAL_RCCEx_PeriphCLKConfig>
8001e10: 2800 cmp r0, #0
8001e12: d13f bne.n 8001e94 <HAL_SPI_MspInit+0xc4>
__HAL_RCC_SPI1_CLK_ENABLE();
8001e14: 4b54 ldr r3, [pc, #336] @ (8001f68 <HAL_SPI_MspInit+0x198>)
8001e16: f8d3 2150 ldr.w r2, [r3, #336] @ 0x150
8001e1a: f442 5280 orr.w r2, r2, #4096 @ 0x1000
8001e1e: f8c3 2150 str.w r2, [r3, #336] @ 0x150
8001e22: f8d3 2150 ldr.w r2, [r3, #336] @ 0x150
8001e26: f402 5280 and.w r2, r2, #4096 @ 0x1000
8001e2a: 9201 str r2, [sp, #4]
8001e2c: 9a01 ldr r2, [sp, #4]
__HAL_RCC_GPIOA_CLK_ENABLE();
8001e2e: f8d3 2140 ldr.w r2, [r3, #320] @ 0x140
8001e32: f042 0201 orr.w r2, r2, #1
8001e36: f8c3 2140 str.w r2, [r3, #320] @ 0x140
8001e3a: f8d3 2140 ldr.w r2, [r3, #320] @ 0x140
8001e3e: f002 0201 and.w r2, r2, #1
8001e42: 9202 str r2, [sp, #8]
8001e44: 9a02 ldr r2, [sp, #8]
__HAL_RCC_GPIOB_CLK_ENABLE();
8001e46: f8d3 2140 ldr.w r2, [r3, #320] @ 0x140
8001e4a: f042 0202 orr.w r2, r2, #2
8001e4e: f8c3 2140 str.w r2, [r3, #320] @ 0x140
8001e52: f8d3 3140 ldr.w r3, [r3, #320] @ 0x140
8001e56: f003 0302 and.w r3, r3, #2
8001e5a: 9303 str r3, [sp, #12]
8001e5c: 9b03 ldr r3, [sp, #12]
GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5;
8001e5e: f04f 0830 mov.w r8, #48 @ 0x30
8001e62: f8cd 80e4 str.w r8, [sp, #228] @ 0xe4
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001e66: 2702 movs r7, #2
8001e68: 973a str r7, [sp, #232] @ 0xe8
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001e6a: 2400 movs r4, #0
8001e6c: 943b str r4, [sp, #236] @ 0xec
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001e6e: 943c str r4, [sp, #240] @ 0xf0
GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
8001e70: 2605 movs r6, #5
8001e72: 963d str r6, [sp, #244] @ 0xf4
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001e74: ad39 add r5, sp, #228 @ 0xe4
8001e76: 4629 mov r1, r5
8001e78: 483c ldr r0, [pc, #240] @ (8001f6c <HAL_SPI_MspInit+0x19c>)
8001e7a: f7ff fdcf bl 8001a1c <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5;
8001e7e: f8cd 80e4 str.w r8, [sp, #228] @ 0xe4
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001e82: 973a str r7, [sp, #232] @ 0xe8
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001e84: 943b str r4, [sp, #236] @ 0xec
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001e86: 943c str r4, [sp, #240] @ 0xf0
GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
8001e88: 963d str r6, [sp, #244] @ 0xf4
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8001e8a: 4629 mov r1, r5
8001e8c: 4838 ldr r0, [pc, #224] @ (8001f70 <HAL_SPI_MspInit+0x1a0>)
8001e8e: f7ff fdc5 bl 8001a1c <HAL_GPIO_Init>
8001e92: e7b2 b.n 8001dfa <HAL_SPI_MspInit+0x2a>
Error_Handler();
8001e94: f7fe fac0 bl 8000418 <Error_Handler>
8001e98: e7bc b.n 8001e14 <HAL_SPI_MspInit+0x44>
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SPI2;
8001e9a: f44f 5280 mov.w r2, #4096 @ 0x1000
8001e9e: 2300 movs r3, #0
8001ea0: e9cd 2308 strd r2, r3, [sp, #32]
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
8001ea4: a808 add r0, sp, #32
8001ea6: f000 ff7b bl 8002da0 <HAL_RCCEx_PeriphCLKConfig>
8001eaa: 2800 cmp r0, #0
8001eac: d155 bne.n 8001f5a <HAL_SPI_MspInit+0x18a>
__HAL_RCC_SPI2_CLK_ENABLE();
8001eae: 4b2e ldr r3, [pc, #184] @ (8001f68 <HAL_SPI_MspInit+0x198>)
8001eb0: f8d3 2148 ldr.w r2, [r3, #328] @ 0x148
8001eb4: f442 4280 orr.w r2, r2, #16384 @ 0x4000
8001eb8: f8c3 2148 str.w r2, [r3, #328] @ 0x148
8001ebc: f8d3 2148 ldr.w r2, [r3, #328] @ 0x148
8001ec0: f402 4280 and.w r2, r2, #16384 @ 0x4000
8001ec4: 9204 str r2, [sp, #16]
8001ec6: 9a04 ldr r2, [sp, #16]
__HAL_RCC_GPIOC_CLK_ENABLE();
8001ec8: f8d3 2140 ldr.w r2, [r3, #320] @ 0x140
8001ecc: f042 0204 orr.w r2, r2, #4
8001ed0: f8c3 2140 str.w r2, [r3, #320] @ 0x140
8001ed4: f8d3 2140 ldr.w r2, [r3, #320] @ 0x140
8001ed8: f002 0204 and.w r2, r2, #4
8001edc: 9205 str r2, [sp, #20]
8001ede: 9a05 ldr r2, [sp, #20]
__HAL_RCC_GPIOB_CLK_ENABLE();
8001ee0: f8d3 2140 ldr.w r2, [r3, #320] @ 0x140
8001ee4: f042 0202 orr.w r2, r2, #2
8001ee8: f8c3 2140 str.w r2, [r3, #320] @ 0x140
8001eec: f8d3 2140 ldr.w r2, [r3, #320] @ 0x140
8001ef0: f002 0202 and.w r2, r2, #2
8001ef4: 9206 str r2, [sp, #24]
8001ef6: 9a06 ldr r2, [sp, #24]
__HAL_RCC_GPIOA_CLK_ENABLE();
8001ef8: f8d3 2140 ldr.w r2, [r3, #320] @ 0x140
8001efc: f042 0201 orr.w r2, r2, #1
8001f00: f8c3 2140 str.w r2, [r3, #320] @ 0x140
8001f04: f8d3 3140 ldr.w r3, [r3, #320] @ 0x140
8001f08: f003 0301 and.w r3, r3, #1
8001f0c: 9307 str r3, [sp, #28]
8001f0e: 9b07 ldr r3, [sp, #28]
GPIO_InitStruct.Pin = GPIO_PIN_3;
8001f10: 2308 movs r3, #8
8001f12: 9339 str r3, [sp, #228] @ 0xe4
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001f14: 2702 movs r7, #2
8001f16: 973a str r7, [sp, #232] @ 0xe8
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001f18: 2400 movs r4, #0
8001f1a: 943b str r4, [sp, #236] @ 0xec
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001f1c: 943c str r4, [sp, #240] @ 0xf0
GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
8001f1e: 2605 movs r6, #5
8001f20: 963d str r6, [sp, #244] @ 0xf4
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8001f22: ad39 add r5, sp, #228 @ 0xe4
8001f24: 4629 mov r1, r5
8001f26: 4813 ldr r0, [pc, #76] @ (8001f74 <HAL_SPI_MspInit+0x1a4>)
8001f28: f7ff fd78 bl 8001a1c <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_14;
8001f2c: f44f 43a0 mov.w r3, #20480 @ 0x5000
8001f30: 9339 str r3, [sp, #228] @ 0xe4
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001f32: 973a str r7, [sp, #232] @ 0xe8
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001f34: 943b str r4, [sp, #236] @ 0xec
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001f36: 943c str r4, [sp, #240] @ 0xf0
GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
8001f38: 963d str r6, [sp, #244] @ 0xf4
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8001f3a: 4629 mov r1, r5
8001f3c: 480c ldr r0, [pc, #48] @ (8001f70 <HAL_SPI_MspInit+0x1a0>)
8001f3e: f7ff fd6d bl 8001a1c <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_12;
8001f42: f44f 5380 mov.w r3, #4096 @ 0x1000
8001f46: 9339 str r3, [sp, #228] @ 0xe4
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001f48: 973a str r7, [sp, #232] @ 0xe8
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001f4a: 943b str r4, [sp, #236] @ 0xec
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001f4c: 943c str r4, [sp, #240] @ 0xf0
GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
8001f4e: 963d str r6, [sp, #244] @ 0xf4
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001f50: 4629 mov r1, r5
8001f52: 4806 ldr r0, [pc, #24] @ (8001f6c <HAL_SPI_MspInit+0x19c>)
8001f54: f7ff fd62 bl 8001a1c <HAL_GPIO_Init>
}
8001f58: e74f b.n 8001dfa <HAL_SPI_MspInit+0x2a>
Error_Handler();
8001f5a: f7fe fa5d bl 8000418 <Error_Handler>
8001f5e: e7a6 b.n 8001eae <HAL_SPI_MspInit+0xde>
8001f60: 40013000 .word 0x40013000
8001f64: 40003800 .word 0x40003800
8001f68: 58024400 .word 0x58024400
8001f6c: 58020000 .word 0x58020000
8001f70: 58020400 .word 0x58020400
8001f74: 58020800 .word 0x58020800
08001f78 <HAL_TIM_IC_MspInit>:
* This function configures the hardware resources used in this example
* @param htim_ic: TIM_IC handle pointer
* @retval None
*/
void HAL_TIM_IC_MspInit(TIM_HandleTypeDef* htim_ic)
{
8001f78: b500 push {lr}
8001f7a: b089 sub sp, #36 @ 0x24
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001f7c: 2300 movs r3, #0
8001f7e: 9303 str r3, [sp, #12]
8001f80: 9304 str r3, [sp, #16]
8001f82: 9305 str r3, [sp, #20]
8001f84: 9306 str r3, [sp, #24]
8001f86: 9307 str r3, [sp, #28]
if(htim_ic->Instance==TIM15)
8001f88: 6802 ldr r2, [r0, #0]
8001f8a: 4b14 ldr r3, [pc, #80] @ (8001fdc <HAL_TIM_IC_MspInit+0x64>)
8001f8c: 429a cmp r2, r3
8001f8e: d002 beq.n 8001f96 <HAL_TIM_IC_MspInit+0x1e>
/* USER CODE BEGIN TIM15_MspInit 1 */
/* USER CODE END TIM15_MspInit 1 */
}
}
8001f90: b009 add sp, #36 @ 0x24
8001f92: f85d fb04 ldr.w pc, [sp], #4
__HAL_RCC_TIM15_CLK_ENABLE();
8001f96: 4b12 ldr r3, [pc, #72] @ (8001fe0 <HAL_TIM_IC_MspInit+0x68>)
8001f98: f8d3 2150 ldr.w r2, [r3, #336] @ 0x150
8001f9c: f442 3280 orr.w r2, r2, #65536 @ 0x10000
8001fa0: f8c3 2150 str.w r2, [r3, #336] @ 0x150
8001fa4: f8d3 2150 ldr.w r2, [r3, #336] @ 0x150
8001fa8: f402 3280 and.w r2, r2, #65536 @ 0x10000
8001fac: 9201 str r2, [sp, #4]
8001fae: 9a01 ldr r2, [sp, #4]
__HAL_RCC_GPIOA_CLK_ENABLE();
8001fb0: f8d3 2140 ldr.w r2, [r3, #320] @ 0x140
8001fb4: f042 0201 orr.w r2, r2, #1
8001fb8: f8c3 2140 str.w r2, [r3, #320] @ 0x140
8001fbc: f8d3 3140 ldr.w r3, [r3, #320] @ 0x140
8001fc0: f003 0301 and.w r3, r3, #1
8001fc4: 9302 str r3, [sp, #8]
8001fc6: 9b02 ldr r3, [sp, #8]
GPIO_InitStruct.Pin = IMD_M_Pin;
8001fc8: 2304 movs r3, #4
8001fca: 9303 str r3, [sp, #12]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001fcc: 2202 movs r2, #2
8001fce: 9204 str r2, [sp, #16]
GPIO_InitStruct.Alternate = GPIO_AF4_TIM15;
8001fd0: 9307 str r3, [sp, #28]
HAL_GPIO_Init(IMD_M_GPIO_Port, &GPIO_InitStruct);
8001fd2: a903 add r1, sp, #12
8001fd4: 4803 ldr r0, [pc, #12] @ (8001fe4 <HAL_TIM_IC_MspInit+0x6c>)
8001fd6: f7ff fd21 bl 8001a1c <HAL_GPIO_Init>
}
8001fda: e7d9 b.n 8001f90 <HAL_TIM_IC_MspInit+0x18>
8001fdc: 40014000 .word 0x40014000
8001fe0: 58024400 .word 0x58024400
8001fe4: 58020000 .word 0x58020000
08001fe8 <HAL_PWREx_ConfigSupply>:
/* Check the parameters */
assert_param (IS_PWR_SUPPLY (SupplySource));
/* Check if supply source was configured */
#if defined (PWR_FLAG_SCUEN)
if (__HAL_PWR_GET_FLAG (PWR_FLAG_SCUEN) == 0U)
8001fe8: 4b13 ldr r3, [pc, #76] @ (8002038 <HAL_PWREx_ConfigSupply+0x50>)
8001fea: 68db ldr r3, [r3, #12]
8001fec: f013 0f04 tst.w r3, #4
8001ff0: d107 bne.n 8002002 <HAL_PWREx_ConfigSupply+0x1a>
#else
if ((PWR->CR3 & (PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)) != (PWR_CR3_SMPSEN | PWR_CR3_LDOEN))
#endif /* defined (PWR_FLAG_SCUEN) */
{
/* Check supply configuration */
if ((PWR->CR3 & PWR_SUPPLY_CONFIG_MASK) != SupplySource)
8001ff2: 4b11 ldr r3, [pc, #68] @ (8002038 <HAL_PWREx_ConfigSupply+0x50>)
8001ff4: 68db ldr r3, [r3, #12]
8001ff6: f003 0307 and.w r3, r3, #7
8001ffa: 4283 cmp r3, r0
8001ffc: d01a beq.n 8002034 <HAL_PWREx_ConfigSupply+0x4c>
{
/* Supply configuration update locked, can't apply a new supply config */
return HAL_ERROR;
8001ffe: 2001 movs r0, #1
8002000: 4770 bx lr
{
8002002: b510 push {r4, lr}
return HAL_OK;
}
}
/* Set the power supply configuration */
MODIFY_REG (PWR->CR3, PWR_SUPPLY_CONFIG_MASK, SupplySource);
8002004: 4a0c ldr r2, [pc, #48] @ (8002038 <HAL_PWREx_ConfigSupply+0x50>)
8002006: 68d3 ldr r3, [r2, #12]
8002008: f023 0307 bic.w r3, r3, #7
800200c: 4303 orrs r3, r0
800200e: 60d3 str r3, [r2, #12]
/* Get tick */
tickstart = HAL_GetTick ();
8002010: f7fe fc6a bl 80008e8 <HAL_GetTick>
8002014: 4604 mov r4, r0
/* Wait till voltage level flag is set */
while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U)
8002016: 4b08 ldr r3, [pc, #32] @ (8002038 <HAL_PWREx_ConfigSupply+0x50>)
8002018: 685b ldr r3, [r3, #4]
800201a: f413 5f00 tst.w r3, #8192 @ 0x2000
800201e: d107 bne.n 8002030 <HAL_PWREx_ConfigSupply+0x48>
{
if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY)
8002020: f7fe fc62 bl 80008e8 <HAL_GetTick>
8002024: 1b00 subs r0, r0, r4
8002026: f5b0 7f7a cmp.w r0, #1000 @ 0x3e8
800202a: d9f4 bls.n 8002016 <HAL_PWREx_ConfigSupply+0x2e>
{
return HAL_ERROR;
800202c: 2001 movs r0, #1
800202e: e000 b.n 8002032 <HAL_PWREx_ConfigSupply+0x4a>
}
}
}
#endif /* defined (SMPS) */
return HAL_OK;
8002030: 2000 movs r0, #0
}
8002032: bd10 pop {r4, pc}
return HAL_OK;
8002034: 2000 movs r0, #0
}
8002036: 4770 bx lr
8002038: 58024800 .word 0x58024800
0800203c <HAL_RCC_OscConfig>:
{
uint32_t tickstart;
uint32_t temp1_pllckcfg, temp2_pllckcfg;
/* Check Null pointer */
if (RCC_OscInitStruct == NULL)
800203c: 2800 cmp r0, #0
800203e: f000 8311 beq.w 8002664 <HAL_RCC_OscConfig+0x628>
{
8002042: b538 push {r3, r4, r5, lr}
8002044: 4604 mov r4, r0
}
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
8002046: 6803 ldr r3, [r0, #0]
8002048: f013 0f01 tst.w r3, #1
800204c: d029 beq.n 80020a2 <HAL_RCC_OscConfig+0x66>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
800204e: 4aa1 ldr r2, [pc, #644] @ (80022d4 <HAL_RCC_OscConfig+0x298>)
8002050: 6913 ldr r3, [r2, #16]
8002052: f003 0338 and.w r3, r3, #56 @ 0x38
const uint32_t temp_pllckselr = RCC->PLLCKSELR;
8002056: 6a92 ldr r2, [r2, #40] @ 0x28
/* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
if ((temp_sysclksrc == RCC_CFGR_SWS_HSE) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSE)))
8002058: 2b10 cmp r3, #16
800205a: d019 beq.n 8002090 <HAL_RCC_OscConfig+0x54>
800205c: 2b18 cmp r3, #24
800205e: d013 beq.n 8002088 <HAL_RCC_OscConfig+0x4c>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
8002060: 6863 ldr r3, [r4, #4]
8002062: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8002066: d043 beq.n 80020f0 <HAL_RCC_OscConfig+0xb4>
8002068: 2b00 cmp r3, #0
800206a: d158 bne.n 800211e <HAL_RCC_OscConfig+0xe2>
800206c: 4b99 ldr r3, [pc, #612] @ (80022d4 <HAL_RCC_OscConfig+0x298>)
800206e: 681a ldr r2, [r3, #0]
8002070: f422 3280 bic.w r2, r2, #65536 @ 0x10000
8002074: 601a str r2, [r3, #0]
8002076: 681a ldr r2, [r3, #0]
8002078: f422 1280 bic.w r2, r2, #1048576 @ 0x100000
800207c: 601a str r2, [r3, #0]
800207e: 681a ldr r2, [r3, #0]
8002080: f422 2280 bic.w r2, r2, #262144 @ 0x40000
8002084: 601a str r2, [r3, #0]
8002086: e038 b.n 80020fa <HAL_RCC_OscConfig+0xbe>
if ((temp_sysclksrc == RCC_CFGR_SWS_HSE) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSE)))
8002088: f002 0203 and.w r2, r2, #3
800208c: 2a02 cmp r2, #2
800208e: d1e7 bne.n 8002060 <HAL_RCC_OscConfig+0x24>
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8002090: 4b90 ldr r3, [pc, #576] @ (80022d4 <HAL_RCC_OscConfig+0x298>)
8002092: 681b ldr r3, [r3, #0]
8002094: f413 3f00 tst.w r3, #131072 @ 0x20000
8002098: d003 beq.n 80020a2 <HAL_RCC_OscConfig+0x66>
800209a: 6863 ldr r3, [r4, #4]
800209c: 2b00 cmp r3, #0
800209e: f000 82e3 beq.w 8002668 <HAL_RCC_OscConfig+0x62c>
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
80020a2: 6823 ldr r3, [r4, #0]
80020a4: f013 0f02 tst.w r3, #2
80020a8: f000 80a2 beq.w 80021f0 <HAL_RCC_OscConfig+0x1b4>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_HSICALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* When the HSI is used as system clock it will not be disabled */
const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
80020ac: 4a89 ldr r2, [pc, #548] @ (80022d4 <HAL_RCC_OscConfig+0x298>)
80020ae: 6913 ldr r3, [r2, #16]
const uint32_t temp_pllckselr = RCC->PLLCKSELR;
80020b0: 6a92 ldr r2, [r2, #40] @ 0x28
if ((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI)))
80020b2: f013 0338 ands.w r3, r3, #56 @ 0x38
80020b6: d074 beq.n 80021a2 <HAL_RCC_OscConfig+0x166>
80020b8: 2b18 cmp r3, #24
80020ba: d06f beq.n 800219c <HAL_RCC_OscConfig+0x160>
}
else
{
/* Check the HSI State */
if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF)
80020bc: 68e3 ldr r3, [r4, #12]
80020be: 2b00 cmp r3, #0
80020c0: f000 80c3 beq.w 800224a <HAL_RCC_OscConfig+0x20e>
{
/* Enable the Internal High Speed oscillator (HSI, HSIDIV2,HSIDIV4, or HSIDIV8) */
__HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState);
80020c4: 4983 ldr r1, [pc, #524] @ (80022d4 <HAL_RCC_OscConfig+0x298>)
80020c6: 680a ldr r2, [r1, #0]
80020c8: f022 0219 bic.w r2, r2, #25
80020cc: 4313 orrs r3, r2
80020ce: 600b str r3, [r1, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80020d0: f7fe fc0a bl 80008e8 <HAL_GetTick>
80020d4: 4605 mov r5, r0
/* Wait till HSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
80020d6: 4b7f ldr r3, [pc, #508] @ (80022d4 <HAL_RCC_OscConfig+0x298>)
80020d8: 681b ldr r3, [r3, #0]
80020da: f013 0f04 tst.w r3, #4
80020de: f040 80ab bne.w 8002238 <HAL_RCC_OscConfig+0x1fc>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
80020e2: f7fe fc01 bl 80008e8 <HAL_GetTick>
80020e6: 1b40 subs r0, r0, r5
80020e8: 2802 cmp r0, #2
80020ea: d9f4 bls.n 80020d6 <HAL_RCC_OscConfig+0x9a>
{
return HAL_TIMEOUT;
80020ec: 2003 movs r0, #3
80020ee: e2c2 b.n 8002676 <HAL_RCC_OscConfig+0x63a>
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
80020f0: 4a78 ldr r2, [pc, #480] @ (80022d4 <HAL_RCC_OscConfig+0x298>)
80020f2: 6813 ldr r3, [r2, #0]
80020f4: f443 3380 orr.w r3, r3, #65536 @ 0x10000
80020f8: 6013 str r3, [r2, #0]
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
80020fa: 6863 ldr r3, [r4, #4]
80020fc: 2b00 cmp r3, #0
80020fe: d03e beq.n 800217e <HAL_RCC_OscConfig+0x142>
tickstart = HAL_GetTick();
8002100: f7fe fbf2 bl 80008e8 <HAL_GetTick>
8002104: 4605 mov r5, r0
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
8002106: 4b73 ldr r3, [pc, #460] @ (80022d4 <HAL_RCC_OscConfig+0x298>)
8002108: 681b ldr r3, [r3, #0]
800210a: f413 3f00 tst.w r3, #131072 @ 0x20000
800210e: d1c8 bne.n 80020a2 <HAL_RCC_OscConfig+0x66>
if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
8002110: f7fe fbea bl 80008e8 <HAL_GetTick>
8002114: 1b40 subs r0, r0, r5
8002116: 2864 cmp r0, #100 @ 0x64
8002118: d9f5 bls.n 8002106 <HAL_RCC_OscConfig+0xca>
return HAL_TIMEOUT;
800211a: 2003 movs r0, #3
800211c: e2ab b.n 8002676 <HAL_RCC_OscConfig+0x63a>
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
800211e: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
8002122: d010 beq.n 8002146 <HAL_RCC_OscConfig+0x10a>
8002124: f5b3 1fa8 cmp.w r3, #1376256 @ 0x150000
8002128: d01b beq.n 8002162 <HAL_RCC_OscConfig+0x126>
800212a: 4b6a ldr r3, [pc, #424] @ (80022d4 <HAL_RCC_OscConfig+0x298>)
800212c: 681a ldr r2, [r3, #0]
800212e: f422 3280 bic.w r2, r2, #65536 @ 0x10000
8002132: 601a str r2, [r3, #0]
8002134: 681a ldr r2, [r3, #0]
8002136: f422 2280 bic.w r2, r2, #262144 @ 0x40000
800213a: 601a str r2, [r3, #0]
800213c: 681a ldr r2, [r3, #0]
800213e: f422 1280 bic.w r2, r2, #1048576 @ 0x100000
8002142: 601a str r2, [r3, #0]
8002144: e7d9 b.n 80020fa <HAL_RCC_OscConfig+0xbe>
8002146: 4b63 ldr r3, [pc, #396] @ (80022d4 <HAL_RCC_OscConfig+0x298>)
8002148: 681a ldr r2, [r3, #0]
800214a: f442 2280 orr.w r2, r2, #262144 @ 0x40000
800214e: 601a str r2, [r3, #0]
8002150: 681a ldr r2, [r3, #0]
8002152: f422 1280 bic.w r2, r2, #1048576 @ 0x100000
8002156: 601a str r2, [r3, #0]
8002158: 681a ldr r2, [r3, #0]
800215a: f442 3280 orr.w r2, r2, #65536 @ 0x10000
800215e: 601a str r2, [r3, #0]
8002160: e7cb b.n 80020fa <HAL_RCC_OscConfig+0xbe>
8002162: 4b5c ldr r3, [pc, #368] @ (80022d4 <HAL_RCC_OscConfig+0x298>)
8002164: 681a ldr r2, [r3, #0]
8002166: f442 2280 orr.w r2, r2, #262144 @ 0x40000
800216a: 601a str r2, [r3, #0]
800216c: 681a ldr r2, [r3, #0]
800216e: f442 1280 orr.w r2, r2, #1048576 @ 0x100000
8002172: 601a str r2, [r3, #0]
8002174: 681a ldr r2, [r3, #0]
8002176: f442 3280 orr.w r2, r2, #65536 @ 0x10000
800217a: 601a str r2, [r3, #0]
800217c: e7bd b.n 80020fa <HAL_RCC_OscConfig+0xbe>
tickstart = HAL_GetTick();
800217e: f7fe fbb3 bl 80008e8 <HAL_GetTick>
8002182: 4605 mov r5, r0
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
8002184: 4b53 ldr r3, [pc, #332] @ (80022d4 <HAL_RCC_OscConfig+0x298>)
8002186: 681b ldr r3, [r3, #0]
8002188: f413 3f00 tst.w r3, #131072 @ 0x20000
800218c: d089 beq.n 80020a2 <HAL_RCC_OscConfig+0x66>
if ((uint32_t)(HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
800218e: f7fe fbab bl 80008e8 <HAL_GetTick>
8002192: 1b40 subs r0, r0, r5
8002194: 2864 cmp r0, #100 @ 0x64
8002196: d9f5 bls.n 8002184 <HAL_RCC_OscConfig+0x148>
return HAL_TIMEOUT;
8002198: 2003 movs r0, #3
800219a: e26c b.n 8002676 <HAL_RCC_OscConfig+0x63a>
if ((temp_sysclksrc == RCC_CFGR_SWS_HSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSI)))
800219c: f012 0f03 tst.w r2, #3
80021a0: d18c bne.n 80020bc <HAL_RCC_OscConfig+0x80>
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
80021a2: 4b4c ldr r3, [pc, #304] @ (80022d4 <HAL_RCC_OscConfig+0x298>)
80021a4: 681b ldr r3, [r3, #0]
80021a6: f013 0f04 tst.w r3, #4
80021aa: d003 beq.n 80021b4 <HAL_RCC_OscConfig+0x178>
80021ac: 68e3 ldr r3, [r4, #12]
80021ae: 2b00 cmp r3, #0
80021b0: f000 825c beq.w 800266c <HAL_RCC_OscConfig+0x630>
__HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIState);
80021b4: 4a47 ldr r2, [pc, #284] @ (80022d4 <HAL_RCC_OscConfig+0x298>)
80021b6: 6813 ldr r3, [r2, #0]
80021b8: f023 0319 bic.w r3, r3, #25
80021bc: 68e1 ldr r1, [r4, #12]
80021be: 430b orrs r3, r1
80021c0: 6013 str r3, [r2, #0]
tickstart = HAL_GetTick();
80021c2: f7fe fb91 bl 80008e8 <HAL_GetTick>
80021c6: 4605 mov r5, r0
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
80021c8: 4b42 ldr r3, [pc, #264] @ (80022d4 <HAL_RCC_OscConfig+0x298>)
80021ca: 681b ldr r3, [r3, #0]
80021cc: f013 0f04 tst.w r3, #4
80021d0: d106 bne.n 80021e0 <HAL_RCC_OscConfig+0x1a4>
if ((uint32_t)(HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
80021d2: f7fe fb89 bl 80008e8 <HAL_GetTick>
80021d6: 1b40 subs r0, r0, r5
80021d8: 2802 cmp r0, #2
80021da: d9f5 bls.n 80021c8 <HAL_RCC_OscConfig+0x18c>
return HAL_TIMEOUT;
80021dc: 2003 movs r0, #3
80021de: e24a b.n 8002676 <HAL_RCC_OscConfig+0x63a>
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
80021e0: 4a3c ldr r2, [pc, #240] @ (80022d4 <HAL_RCC_OscConfig+0x298>)
80021e2: 6853 ldr r3, [r2, #4]
80021e4: f023 43fe bic.w r3, r3, #2130706432 @ 0x7f000000
80021e8: 6921 ldr r1, [r4, #16]
80021ea: ea43 6301 orr.w r3, r3, r1, lsl #24
80021ee: 6053 str r3, [r2, #4]
}
}
}
}
/*----------------------------- CSI Configuration --------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI)
80021f0: 6823 ldr r3, [r4, #0]
80021f2: f013 0f10 tst.w r3, #16
80021f6: d051 beq.n 800229c <HAL_RCC_OscConfig+0x260>
/* Check the parameters */
assert_param(IS_RCC_CSI(RCC_OscInitStruct->CSIState));
assert_param(IS_RCC_CSICALIBRATION_VALUE(RCC_OscInitStruct->CSICalibrationValue));
/* When the CSI is used as system clock it will not disabled */
const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
80021f8: 4a36 ldr r2, [pc, #216] @ (80022d4 <HAL_RCC_OscConfig+0x298>)
80021fa: 6913 ldr r3, [r2, #16]
80021fc: f003 0338 and.w r3, r3, #56 @ 0x38
const uint32_t temp_pllckselr = RCC->PLLCKSELR;
8002200: 6a92 ldr r2, [r2, #40] @ 0x28
if ((temp_sysclksrc == RCC_CFGR_SWS_CSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_CSI)))
8002202: 2b08 cmp r3, #8
8002204: d039 beq.n 800227a <HAL_RCC_OscConfig+0x23e>
8002206: 2b18 cmp r3, #24
8002208: d033 beq.n 8002272 <HAL_RCC_OscConfig+0x236>
}
}
else
{
/* Check the CSI State */
if ((RCC_OscInitStruct->CSIState) != RCC_CSI_OFF)
800220a: 69e3 ldr r3, [r4, #28]
800220c: 2b00 cmp r3, #0
800220e: d06c beq.n 80022ea <HAL_RCC_OscConfig+0x2ae>
{
/* Enable the Internal High Speed oscillator (CSI). */
__HAL_RCC_CSI_ENABLE();
8002210: 4a30 ldr r2, [pc, #192] @ (80022d4 <HAL_RCC_OscConfig+0x298>)
8002212: 6813 ldr r3, [r2, #0]
8002214: f043 0380 orr.w r3, r3, #128 @ 0x80
8002218: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
800221a: f7fe fb65 bl 80008e8 <HAL_GetTick>
800221e: 4605 mov r5, r0
/* Wait till CSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U)
8002220: 4b2c ldr r3, [pc, #176] @ (80022d4 <HAL_RCC_OscConfig+0x298>)
8002222: 681b ldr r3, [r3, #0]
8002224: f413 7f80 tst.w r3, #256 @ 0x100
8002228: d156 bne.n 80022d8 <HAL_RCC_OscConfig+0x29c>
{
if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE)
800222a: f7fe fb5d bl 80008e8 <HAL_GetTick>
800222e: 1b40 subs r0, r0, r5
8002230: 2802 cmp r0, #2
8002232: d9f5 bls.n 8002220 <HAL_RCC_OscConfig+0x1e4>
{
return HAL_TIMEOUT;
8002234: 2003 movs r0, #3
8002236: e21e b.n 8002676 <HAL_RCC_OscConfig+0x63a>
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8002238: 4a26 ldr r2, [pc, #152] @ (80022d4 <HAL_RCC_OscConfig+0x298>)
800223a: 6853 ldr r3, [r2, #4]
800223c: f023 43fe bic.w r3, r3, #2130706432 @ 0x7f000000
8002240: 6921 ldr r1, [r4, #16]
8002242: ea43 6301 orr.w r3, r3, r1, lsl #24
8002246: 6053 str r3, [r2, #4]
8002248: e7d2 b.n 80021f0 <HAL_RCC_OscConfig+0x1b4>
__HAL_RCC_HSI_DISABLE();
800224a: 4a22 ldr r2, [pc, #136] @ (80022d4 <HAL_RCC_OscConfig+0x298>)
800224c: 6813 ldr r3, [r2, #0]
800224e: f023 0301 bic.w r3, r3, #1
8002252: 6013 str r3, [r2, #0]
tickstart = HAL_GetTick();
8002254: f7fe fb48 bl 80008e8 <HAL_GetTick>
8002258: 4605 mov r5, r0
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
800225a: 4b1e ldr r3, [pc, #120] @ (80022d4 <HAL_RCC_OscConfig+0x298>)
800225c: 681b ldr r3, [r3, #0]
800225e: f013 0f04 tst.w r3, #4
8002262: d0c5 beq.n 80021f0 <HAL_RCC_OscConfig+0x1b4>
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8002264: f7fe fb40 bl 80008e8 <HAL_GetTick>
8002268: 1b40 subs r0, r0, r5
800226a: 2802 cmp r0, #2
800226c: d9f5 bls.n 800225a <HAL_RCC_OscConfig+0x21e>
return HAL_TIMEOUT;
800226e: 2003 movs r0, #3
8002270: e201 b.n 8002676 <HAL_RCC_OscConfig+0x63a>
if ((temp_sysclksrc == RCC_CFGR_SWS_CSI) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_CSI)))
8002272: f002 0203 and.w r2, r2, #3
8002276: 2a01 cmp r2, #1
8002278: d1c7 bne.n 800220a <HAL_RCC_OscConfig+0x1ce>
if ((__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U) && (RCC_OscInitStruct->CSIState != RCC_CSI_ON))
800227a: 4b16 ldr r3, [pc, #88] @ (80022d4 <HAL_RCC_OscConfig+0x298>)
800227c: 681b ldr r3, [r3, #0]
800227e: f413 7f80 tst.w r3, #256 @ 0x100
8002282: d003 beq.n 800228c <HAL_RCC_OscConfig+0x250>
8002284: 69e3 ldr r3, [r4, #28]
8002286: 2b80 cmp r3, #128 @ 0x80
8002288: f040 81f2 bne.w 8002670 <HAL_RCC_OscConfig+0x634>
__HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
800228c: 4a11 ldr r2, [pc, #68] @ (80022d4 <HAL_RCC_OscConfig+0x298>)
800228e: 68d3 ldr r3, [r2, #12]
8002290: f023 537c bic.w r3, r3, #1056964608 @ 0x3f000000
8002294: 6a21 ldr r1, [r4, #32]
8002296: ea43 6301 orr.w r3, r3, r1, lsl #24
800229a: 60d3 str r3, [r2, #12]
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
800229c: 6823 ldr r3, [r4, #0]
800229e: f013 0f08 tst.w r3, #8
80022a2: d04a beq.n 800233a <HAL_RCC_OscConfig+0x2fe>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF)
80022a4: 6963 ldr r3, [r4, #20]
80022a6: 2b00 cmp r3, #0
80022a8: d033 beq.n 8002312 <HAL_RCC_OscConfig+0x2d6>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
80022aa: 4a0a ldr r2, [pc, #40] @ (80022d4 <HAL_RCC_OscConfig+0x298>)
80022ac: 6f53 ldr r3, [r2, #116] @ 0x74
80022ae: f043 0301 orr.w r3, r3, #1
80022b2: 6753 str r3, [r2, #116] @ 0x74
/* Get Start Tick*/
tickstart = HAL_GetTick();
80022b4: f7fe fb18 bl 80008e8 <HAL_GetTick>
80022b8: 4605 mov r5, r0
/* Wait till LSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
80022ba: 4b06 ldr r3, [pc, #24] @ (80022d4 <HAL_RCC_OscConfig+0x298>)
80022bc: 6f5b ldr r3, [r3, #116] @ 0x74
80022be: f013 0f02 tst.w r3, #2
80022c2: d13a bne.n 800233a <HAL_RCC_OscConfig+0x2fe>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
80022c4: f7fe fb10 bl 80008e8 <HAL_GetTick>
80022c8: 1b40 subs r0, r0, r5
80022ca: 2802 cmp r0, #2
80022cc: d9f5 bls.n 80022ba <HAL_RCC_OscConfig+0x27e>
{
return HAL_TIMEOUT;
80022ce: 2003 movs r0, #3
80022d0: e1d1 b.n 8002676 <HAL_RCC_OscConfig+0x63a>
80022d2: bf00 nop
80022d4: 58024400 .word 0x58024400
__HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->CSICalibrationValue);
80022d8: 4a8c ldr r2, [pc, #560] @ (800250c <HAL_RCC_OscConfig+0x4d0>)
80022da: 68d3 ldr r3, [r2, #12]
80022dc: f023 537c bic.w r3, r3, #1056964608 @ 0x3f000000
80022e0: 6a21 ldr r1, [r4, #32]
80022e2: ea43 6301 orr.w r3, r3, r1, lsl #24
80022e6: 60d3 str r3, [r2, #12]
80022e8: e7d8 b.n 800229c <HAL_RCC_OscConfig+0x260>
__HAL_RCC_CSI_DISABLE();
80022ea: 4a88 ldr r2, [pc, #544] @ (800250c <HAL_RCC_OscConfig+0x4d0>)
80022ec: 6813 ldr r3, [r2, #0]
80022ee: f023 0380 bic.w r3, r3, #128 @ 0x80
80022f2: 6013 str r3, [r2, #0]
tickstart = HAL_GetTick();
80022f4: f7fe faf8 bl 80008e8 <HAL_GetTick>
80022f8: 4605 mov r5, r0
while (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) != 0U)
80022fa: 4b84 ldr r3, [pc, #528] @ (800250c <HAL_RCC_OscConfig+0x4d0>)
80022fc: 681b ldr r3, [r3, #0]
80022fe: f413 7f80 tst.w r3, #256 @ 0x100
8002302: d0cb beq.n 800229c <HAL_RCC_OscConfig+0x260>
if ((HAL_GetTick() - tickstart) > CSI_TIMEOUT_VALUE)
8002304: f7fe faf0 bl 80008e8 <HAL_GetTick>
8002308: 1b40 subs r0, r0, r5
800230a: 2802 cmp r0, #2
800230c: d9f5 bls.n 80022fa <HAL_RCC_OscConfig+0x2be>
return HAL_TIMEOUT;
800230e: 2003 movs r0, #3
8002310: e1b1 b.n 8002676 <HAL_RCC_OscConfig+0x63a>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8002312: 4a7e ldr r2, [pc, #504] @ (800250c <HAL_RCC_OscConfig+0x4d0>)
8002314: 6f53 ldr r3, [r2, #116] @ 0x74
8002316: f023 0301 bic.w r3, r3, #1
800231a: 6753 str r3, [r2, #116] @ 0x74
/* Get Start Tick*/
tickstart = HAL_GetTick();
800231c: f7fe fae4 bl 80008e8 <HAL_GetTick>
8002320: 4605 mov r5, r0
/* Wait till LSI is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
8002322: 4b7a ldr r3, [pc, #488] @ (800250c <HAL_RCC_OscConfig+0x4d0>)
8002324: 6f5b ldr r3, [r3, #116] @ 0x74
8002326: f013 0f02 tst.w r3, #2
800232a: d006 beq.n 800233a <HAL_RCC_OscConfig+0x2fe>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
800232c: f7fe fadc bl 80008e8 <HAL_GetTick>
8002330: 1b40 subs r0, r0, r5
8002332: 2802 cmp r0, #2
8002334: d9f5 bls.n 8002322 <HAL_RCC_OscConfig+0x2e6>
{
return HAL_TIMEOUT;
8002336: 2003 movs r0, #3
8002338: e19d b.n 8002676 <HAL_RCC_OscConfig+0x63a>
}
}
}
/*------------------------------ HSI48 Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
800233a: 6823 ldr r3, [r4, #0]
800233c: f013 0f20 tst.w r3, #32
8002340: d029 beq.n 8002396 <HAL_RCC_OscConfig+0x35a>
{
/* Check the parameters */
assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
/* Check the HSI48 State */
if ((RCC_OscInitStruct->HSI48State) != RCC_HSI48_OFF)
8002342: 69a3 ldr r3, [r4, #24]
8002344: b19b cbz r3, 800236e <HAL_RCC_OscConfig+0x332>
{
/* Enable the Internal Low Speed oscillator (HSI48). */
__HAL_RCC_HSI48_ENABLE();
8002346: 4a71 ldr r2, [pc, #452] @ (800250c <HAL_RCC_OscConfig+0x4d0>)
8002348: 6813 ldr r3, [r2, #0]
800234a: f443 5380 orr.w r3, r3, #4096 @ 0x1000
800234e: 6013 str r3, [r2, #0]
/* Get time-out */
tickstart = HAL_GetTick();
8002350: f7fe faca bl 80008e8 <HAL_GetTick>
8002354: 4605 mov r5, r0
/* Wait till HSI48 is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == 0U)
8002356: 4b6d ldr r3, [pc, #436] @ (800250c <HAL_RCC_OscConfig+0x4d0>)
8002358: 681b ldr r3, [r3, #0]
800235a: f413 5f00 tst.w r3, #8192 @ 0x2000
800235e: d11a bne.n 8002396 <HAL_RCC_OscConfig+0x35a>
{
if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
8002360: f7fe fac2 bl 80008e8 <HAL_GetTick>
8002364: 1b40 subs r0, r0, r5
8002366: 2802 cmp r0, #2
8002368: d9f5 bls.n 8002356 <HAL_RCC_OscConfig+0x31a>
{
return HAL_TIMEOUT;
800236a: 2003 movs r0, #3
800236c: e183 b.n 8002676 <HAL_RCC_OscConfig+0x63a>
}
}
else
{
/* Disable the Internal Low Speed oscillator (HSI48). */
__HAL_RCC_HSI48_DISABLE();
800236e: 4a67 ldr r2, [pc, #412] @ (800250c <HAL_RCC_OscConfig+0x4d0>)
8002370: 6813 ldr r3, [r2, #0]
8002372: f423 5380 bic.w r3, r3, #4096 @ 0x1000
8002376: 6013 str r3, [r2, #0]
/* Get time-out */
tickstart = HAL_GetTick();
8002378: f7fe fab6 bl 80008e8 <HAL_GetTick>
800237c: 4605 mov r5, r0
/* Wait till HSI48 is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != 0U)
800237e: 4b63 ldr r3, [pc, #396] @ (800250c <HAL_RCC_OscConfig+0x4d0>)
8002380: 681b ldr r3, [r3, #0]
8002382: f413 5f00 tst.w r3, #8192 @ 0x2000
8002386: d006 beq.n 8002396 <HAL_RCC_OscConfig+0x35a>
{
if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
8002388: f7fe faae bl 80008e8 <HAL_GetTick>
800238c: 1b40 subs r0, r0, r5
800238e: 2802 cmp r0, #2
8002390: d9f5 bls.n 800237e <HAL_RCC_OscConfig+0x342>
{
return HAL_TIMEOUT;
8002392: 2003 movs r0, #3
8002394: e16f b.n 8002676 <HAL_RCC_OscConfig+0x63a>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8002396: 6823 ldr r3, [r4, #0]
8002398: f013 0f04 tst.w r3, #4
800239c: d122 bne.n 80023e4 <HAL_RCC_OscConfig+0x3a8>
}
}
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
800239e: 6a63 ldr r3, [r4, #36] @ 0x24
80023a0: 2b00 cmp r3, #0
80023a2: f000 8167 beq.w 8002674 <HAL_RCC_OscConfig+0x638>
{
/* Check if the PLL is used as system clock or not */
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1)
80023a6: 4a59 ldr r2, [pc, #356] @ (800250c <HAL_RCC_OscConfig+0x4d0>)
80023a8: 6912 ldr r2, [r2, #16]
80023aa: f002 0238 and.w r2, r2, #56 @ 0x38
80023ae: 2a18 cmp r2, #24
80023b0: f000 810e beq.w 80025d0 <HAL_RCC_OscConfig+0x594>
{
if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
80023b4: 2b02 cmp r3, #2
80023b6: f000 8094 beq.w 80024e2 <HAL_RCC_OscConfig+0x4a6>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
80023ba: 4a54 ldr r2, [pc, #336] @ (800250c <HAL_RCC_OscConfig+0x4d0>)
80023bc: 6813 ldr r3, [r2, #0]
80023be: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
80023c2: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80023c4: f7fe fa90 bl 80008e8 <HAL_GetTick>
80023c8: 4604 mov r4, r0
/* Wait till PLL is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
80023ca: 4b50 ldr r3, [pc, #320] @ (800250c <HAL_RCC_OscConfig+0x4d0>)
80023cc: 681b ldr r3, [r3, #0]
80023ce: f013 7f00 tst.w r3, #33554432 @ 0x2000000
80023d2: f000 80fb beq.w 80025cc <HAL_RCC_OscConfig+0x590>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
80023d6: f7fe fa87 bl 80008e8 <HAL_GetTick>
80023da: 1b00 subs r0, r0, r4
80023dc: 2802 cmp r0, #2
80023de: d9f4 bls.n 80023ca <HAL_RCC_OscConfig+0x38e>
{
return HAL_TIMEOUT;
80023e0: 2003 movs r0, #3
80023e2: e148 b.n 8002676 <HAL_RCC_OscConfig+0x63a>
PWR->CR1 |= PWR_CR1_DBP;
80023e4: 4a4a ldr r2, [pc, #296] @ (8002510 <HAL_RCC_OscConfig+0x4d4>)
80023e6: 6813 ldr r3, [r2, #0]
80023e8: f443 7380 orr.w r3, r3, #256 @ 0x100
80023ec: 6013 str r3, [r2, #0]
tickstart = HAL_GetTick();
80023ee: f7fe fa7b bl 80008e8 <HAL_GetTick>
80023f2: 4605 mov r5, r0
while ((PWR->CR1 & PWR_CR1_DBP) == 0U)
80023f4: 4b46 ldr r3, [pc, #280] @ (8002510 <HAL_RCC_OscConfig+0x4d4>)
80023f6: 681b ldr r3, [r3, #0]
80023f8: f413 7f80 tst.w r3, #256 @ 0x100
80023fc: d106 bne.n 800240c <HAL_RCC_OscConfig+0x3d0>
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
80023fe: f7fe fa73 bl 80008e8 <HAL_GetTick>
8002402: 1b40 subs r0, r0, r5
8002404: 2864 cmp r0, #100 @ 0x64
8002406: d9f5 bls.n 80023f4 <HAL_RCC_OscConfig+0x3b8>
return HAL_TIMEOUT;
8002408: 2003 movs r0, #3
800240a: e134 b.n 8002676 <HAL_RCC_OscConfig+0x63a>
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
800240c: 68a3 ldr r3, [r4, #8]
800240e: 2b01 cmp r3, #1
8002410: d00e beq.n 8002430 <HAL_RCC_OscConfig+0x3f4>
8002412: bb33 cbnz r3, 8002462 <HAL_RCC_OscConfig+0x426>
8002414: 4b3d ldr r3, [pc, #244] @ (800250c <HAL_RCC_OscConfig+0x4d0>)
8002416: 6f1a ldr r2, [r3, #112] @ 0x70
8002418: f022 0201 bic.w r2, r2, #1
800241c: 671a str r2, [r3, #112] @ 0x70
800241e: 6f1a ldr r2, [r3, #112] @ 0x70
8002420: f022 0280 bic.w r2, r2, #128 @ 0x80
8002424: 671a str r2, [r3, #112] @ 0x70
8002426: 6f1a ldr r2, [r3, #112] @ 0x70
8002428: f022 0204 bic.w r2, r2, #4
800242c: 671a str r2, [r3, #112] @ 0x70
800242e: e004 b.n 800243a <HAL_RCC_OscConfig+0x3fe>
8002430: 4a36 ldr r2, [pc, #216] @ (800250c <HAL_RCC_OscConfig+0x4d0>)
8002432: 6f13 ldr r3, [r2, #112] @ 0x70
8002434: f043 0301 orr.w r3, r3, #1
8002438: 6713 str r3, [r2, #112] @ 0x70
if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
800243a: 68a3 ldr r3, [r4, #8]
800243c: 2b00 cmp r3, #0
800243e: d03e beq.n 80024be <HAL_RCC_OscConfig+0x482>
tickstart = HAL_GetTick();
8002440: f7fe fa52 bl 80008e8 <HAL_GetTick>
8002444: 4605 mov r5, r0
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
8002446: 4b31 ldr r3, [pc, #196] @ (800250c <HAL_RCC_OscConfig+0x4d0>)
8002448: 6f1b ldr r3, [r3, #112] @ 0x70
800244a: f013 0f02 tst.w r3, #2
800244e: d1a6 bne.n 800239e <HAL_RCC_OscConfig+0x362>
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8002450: f7fe fa4a bl 80008e8 <HAL_GetTick>
8002454: 1b40 subs r0, r0, r5
8002456: f241 3388 movw r3, #5000 @ 0x1388
800245a: 4298 cmp r0, r3
800245c: d9f3 bls.n 8002446 <HAL_RCC_OscConfig+0x40a>
return HAL_TIMEOUT;
800245e: 2003 movs r0, #3
8002460: e109 b.n 8002676 <HAL_RCC_OscConfig+0x63a>
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8002462: 2b05 cmp r3, #5
8002464: d00f beq.n 8002486 <HAL_RCC_OscConfig+0x44a>
8002466: 2b85 cmp r3, #133 @ 0x85
8002468: d01b beq.n 80024a2 <HAL_RCC_OscConfig+0x466>
800246a: 4b28 ldr r3, [pc, #160] @ (800250c <HAL_RCC_OscConfig+0x4d0>)
800246c: 6f1a ldr r2, [r3, #112] @ 0x70
800246e: f022 0201 bic.w r2, r2, #1
8002472: 671a str r2, [r3, #112] @ 0x70
8002474: 6f1a ldr r2, [r3, #112] @ 0x70
8002476: f022 0204 bic.w r2, r2, #4
800247a: 671a str r2, [r3, #112] @ 0x70
800247c: 6f1a ldr r2, [r3, #112] @ 0x70
800247e: f022 0280 bic.w r2, r2, #128 @ 0x80
8002482: 671a str r2, [r3, #112] @ 0x70
8002484: e7d9 b.n 800243a <HAL_RCC_OscConfig+0x3fe>
8002486: 4b21 ldr r3, [pc, #132] @ (800250c <HAL_RCC_OscConfig+0x4d0>)
8002488: 6f1a ldr r2, [r3, #112] @ 0x70
800248a: f042 0204 orr.w r2, r2, #4
800248e: 671a str r2, [r3, #112] @ 0x70
8002490: 6f1a ldr r2, [r3, #112] @ 0x70
8002492: f022 0280 bic.w r2, r2, #128 @ 0x80
8002496: 671a str r2, [r3, #112] @ 0x70
8002498: 6f1a ldr r2, [r3, #112] @ 0x70
800249a: f042 0201 orr.w r2, r2, #1
800249e: 671a str r2, [r3, #112] @ 0x70
80024a0: e7cb b.n 800243a <HAL_RCC_OscConfig+0x3fe>
80024a2: 4b1a ldr r3, [pc, #104] @ (800250c <HAL_RCC_OscConfig+0x4d0>)
80024a4: 6f1a ldr r2, [r3, #112] @ 0x70
80024a6: f042 0204 orr.w r2, r2, #4
80024aa: 671a str r2, [r3, #112] @ 0x70
80024ac: 6f1a ldr r2, [r3, #112] @ 0x70
80024ae: f042 0280 orr.w r2, r2, #128 @ 0x80
80024b2: 671a str r2, [r3, #112] @ 0x70
80024b4: 6f1a ldr r2, [r3, #112] @ 0x70
80024b6: f042 0201 orr.w r2, r2, #1
80024ba: 671a str r2, [r3, #112] @ 0x70
80024bc: e7bd b.n 800243a <HAL_RCC_OscConfig+0x3fe>
tickstart = HAL_GetTick();
80024be: f7fe fa13 bl 80008e8 <HAL_GetTick>
80024c2: 4605 mov r5, r0
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
80024c4: 4b11 ldr r3, [pc, #68] @ (800250c <HAL_RCC_OscConfig+0x4d0>)
80024c6: 6f1b ldr r3, [r3, #112] @ 0x70
80024c8: f013 0f02 tst.w r3, #2
80024cc: f43f af67 beq.w 800239e <HAL_RCC_OscConfig+0x362>
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
80024d0: f7fe fa0a bl 80008e8 <HAL_GetTick>
80024d4: 1b40 subs r0, r0, r5
80024d6: f241 3388 movw r3, #5000 @ 0x1388
80024da: 4298 cmp r0, r3
80024dc: d9f2 bls.n 80024c4 <HAL_RCC_OscConfig+0x488>
return HAL_TIMEOUT;
80024de: 2003 movs r0, #3
80024e0: e0c9 b.n 8002676 <HAL_RCC_OscConfig+0x63a>
__HAL_RCC_PLL_DISABLE();
80024e2: 4a0a ldr r2, [pc, #40] @ (800250c <HAL_RCC_OscConfig+0x4d0>)
80024e4: 6813 ldr r3, [r2, #0]
80024e6: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
80024ea: 6013 str r3, [r2, #0]
tickstart = HAL_GetTick();
80024ec: f7fe f9fc bl 80008e8 <HAL_GetTick>
80024f0: 4605 mov r5, r0
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
80024f2: 4b06 ldr r3, [pc, #24] @ (800250c <HAL_RCC_OscConfig+0x4d0>)
80024f4: 681b ldr r3, [r3, #0]
80024f6: f013 7f00 tst.w r3, #33554432 @ 0x2000000
80024fa: d00b beq.n 8002514 <HAL_RCC_OscConfig+0x4d8>
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
80024fc: f7fe f9f4 bl 80008e8 <HAL_GetTick>
8002500: 1b40 subs r0, r0, r5
8002502: 2802 cmp r0, #2
8002504: d9f5 bls.n 80024f2 <HAL_RCC_OscConfig+0x4b6>
return HAL_TIMEOUT;
8002506: 2003 movs r0, #3
8002508: e0b5 b.n 8002676 <HAL_RCC_OscConfig+0x63a>
800250a: bf00 nop
800250c: 58024400 .word 0x58024400
8002510: 58024800 .word 0x58024800
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
8002514: 4b5f ldr r3, [pc, #380] @ (8002694 <HAL_RCC_OscConfig+0x658>)
8002516: 6a99 ldr r1, [r3, #40] @ 0x28
8002518: 4a5f ldr r2, [pc, #380] @ (8002698 <HAL_RCC_OscConfig+0x65c>)
800251a: 400a ands r2, r1
800251c: 6aa1 ldr r1, [r4, #40] @ 0x28
800251e: 6ae0 ldr r0, [r4, #44] @ 0x2c
8002520: ea41 1100 orr.w r1, r1, r0, lsl #4
8002524: 430a orrs r2, r1
8002526: 629a str r2, [r3, #40] @ 0x28
8002528: 6b22 ldr r2, [r4, #48] @ 0x30
800252a: 3a01 subs r2, #1
800252c: f3c2 0208 ubfx r2, r2, #0, #9
8002530: 6b61 ldr r1, [r4, #52] @ 0x34
8002532: 3901 subs r1, #1
8002534: 0249 lsls r1, r1, #9
8002536: b289 uxth r1, r1
8002538: 430a orrs r2, r1
800253a: 6ba1 ldr r1, [r4, #56] @ 0x38
800253c: 3901 subs r1, #1
800253e: 0409 lsls r1, r1, #16
8002540: f401 01fe and.w r1, r1, #8323072 @ 0x7f0000
8002544: 430a orrs r2, r1
8002546: 6be1 ldr r1, [r4, #60] @ 0x3c
8002548: 3901 subs r1, #1
800254a: 0609 lsls r1, r1, #24
800254c: f001 41fe and.w r1, r1, #2130706432 @ 0x7f000000
8002550: 430a orrs r2, r1
8002552: 631a str r2, [r3, #48] @ 0x30
__HAL_RCC_PLLFRACN_DISABLE();
8002554: 6ada ldr r2, [r3, #44] @ 0x2c
8002556: f022 0201 bic.w r2, r2, #1
800255a: 62da str r2, [r3, #44] @ 0x2c
__HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN);
800255c: 6b5a ldr r2, [r3, #52] @ 0x34
800255e: f36f 02cf bfc r2, #3, #13
8002562: 6ca1 ldr r1, [r4, #72] @ 0x48
8002564: ea42 02c1 orr.w r2, r2, r1, lsl #3
8002568: 635a str r2, [r3, #52] @ 0x34
__HAL_RCC_PLL_VCIRANGE(RCC_OscInitStruct->PLL.PLLRGE) ;
800256a: 6ada ldr r2, [r3, #44] @ 0x2c
800256c: f022 020c bic.w r2, r2, #12
8002570: 6c21 ldr r1, [r4, #64] @ 0x40
8002572: 430a orrs r2, r1
8002574: 62da str r2, [r3, #44] @ 0x2c
__HAL_RCC_PLL_VCORANGE(RCC_OscInitStruct->PLL.PLLVCOSEL) ;
8002576: 6ada ldr r2, [r3, #44] @ 0x2c
8002578: f022 0202 bic.w r2, r2, #2
800257c: 6c61 ldr r1, [r4, #68] @ 0x44
800257e: 430a orrs r2, r1
8002580: 62da str r2, [r3, #44] @ 0x2c
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP);
8002582: 6ada ldr r2, [r3, #44] @ 0x2c
8002584: f442 3280 orr.w r2, r2, #65536 @ 0x10000
8002588: 62da str r2, [r3, #44] @ 0x2c
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
800258a: 6ada ldr r2, [r3, #44] @ 0x2c
800258c: f442 3200 orr.w r2, r2, #131072 @ 0x20000
8002590: 62da str r2, [r3, #44] @ 0x2c
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR);
8002592: 6ada ldr r2, [r3, #44] @ 0x2c
8002594: f442 2280 orr.w r2, r2, #262144 @ 0x40000
8002598: 62da str r2, [r3, #44] @ 0x2c
__HAL_RCC_PLLFRACN_ENABLE();
800259a: 6ada ldr r2, [r3, #44] @ 0x2c
800259c: f042 0201 orr.w r2, r2, #1
80025a0: 62da str r2, [r3, #44] @ 0x2c
__HAL_RCC_PLL_ENABLE();
80025a2: 681a ldr r2, [r3, #0]
80025a4: f042 7280 orr.w r2, r2, #16777216 @ 0x1000000
80025a8: 601a str r2, [r3, #0]
tickstart = HAL_GetTick();
80025aa: f7fe f99d bl 80008e8 <HAL_GetTick>
80025ae: 4604 mov r4, r0
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
80025b0: 4b38 ldr r3, [pc, #224] @ (8002694 <HAL_RCC_OscConfig+0x658>)
80025b2: 681b ldr r3, [r3, #0]
80025b4: f013 7f00 tst.w r3, #33554432 @ 0x2000000
80025b8: d106 bne.n 80025c8 <HAL_RCC_OscConfig+0x58c>
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
80025ba: f7fe f995 bl 80008e8 <HAL_GetTick>
80025be: 1b00 subs r0, r0, r4
80025c0: 2802 cmp r0, #2
80025c2: d9f5 bls.n 80025b0 <HAL_RCC_OscConfig+0x574>
return HAL_TIMEOUT;
80025c4: 2003 movs r0, #3
80025c6: e056 b.n 8002676 <HAL_RCC_OscConfig+0x63a>
__HAL_RCC_PLLFRACN_ENABLE();
}
}
}
}
return HAL_OK;
80025c8: 2000 movs r0, #0
80025ca: e054 b.n 8002676 <HAL_RCC_OscConfig+0x63a>
80025cc: 2000 movs r0, #0
80025ce: e052 b.n 8002676 <HAL_RCC_OscConfig+0x63a>
temp1_pllckcfg = RCC->PLLCKSELR;
80025d0: 4930 ldr r1, [pc, #192] @ (8002694 <HAL_RCC_OscConfig+0x658>)
80025d2: 6a8a ldr r2, [r1, #40] @ 0x28
temp2_pllckcfg = RCC->PLL1DIVR;
80025d4: 6b08 ldr r0, [r1, #48] @ 0x30
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
80025d6: 2b01 cmp r3, #1
80025d8: d04e beq.n 8002678 <HAL_RCC_OscConfig+0x63c>
(READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
80025da: f002 0303 and.w r3, r2, #3
80025de: 6aa1 ldr r1, [r4, #40] @ 0x28
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
80025e0: 428b cmp r3, r1
80025e2: d14b bne.n 800267c <HAL_RCC_OscConfig+0x640>
((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) ||
80025e4: f3c2 1205 ubfx r2, r2, #4, #6
80025e8: 6ae3 ldr r3, [r4, #44] @ 0x2c
(READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
80025ea: 429a cmp r2, r3
80025ec: d148 bne.n 8002680 <HAL_RCC_OscConfig+0x644>
(READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) ||
80025ee: f3c0 0208 ubfx r2, r0, #0, #9
80025f2: 6b23 ldr r3, [r4, #48] @ 0x30
80025f4: 3b01 subs r3, #1
((READ_BIT(temp1_pllckcfg, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos) != RCC_OscInitStruct->PLL.PLLM) ||
80025f6: 429a cmp r2, r3
80025f8: d144 bne.n 8002684 <HAL_RCC_OscConfig+0x648>
((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) ||
80025fa: f3c0 2246 ubfx r2, r0, #9, #7
80025fe: 6b63 ldr r3, [r4, #52] @ 0x34
8002600: 3b01 subs r3, #1
(READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_N1) != (RCC_OscInitStruct->PLL.PLLN - 1U)) ||
8002602: 429a cmp r2, r3
8002604: d140 bne.n 8002688 <HAL_RCC_OscConfig+0x64c>
((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) ||
8002606: f3c0 4206 ubfx r2, r0, #16, #7
800260a: 6ba3 ldr r3, [r4, #56] @ 0x38
800260c: 3b01 subs r3, #1
((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) != (RCC_OscInitStruct->PLL.PLLP - 1U)) ||
800260e: 429a cmp r2, r3
8002610: d13c bne.n 800268c <HAL_RCC_OscConfig+0x650>
((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) != (RCC_OscInitStruct->PLL.PLLR - 1U)))
8002612: f3c0 6006 ubfx r0, r0, #24, #7
8002616: 6be3 ldr r3, [r4, #60] @ 0x3c
8002618: 3b01 subs r3, #1
((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) != (RCC_OscInitStruct->PLL.PLLQ - 1U)) ||
800261a: 4298 cmp r0, r3
800261c: d138 bne.n 8002690 <HAL_RCC_OscConfig+0x654>
temp1_pllckcfg = ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos);
800261e: 4b1d ldr r3, [pc, #116] @ (8002694 <HAL_RCC_OscConfig+0x658>)
8002620: 6b5b ldr r3, [r3, #52] @ 0x34
8002622: f3c3 03cc ubfx r3, r3, #3, #13
if (RCC_OscInitStruct->PLL.PLLFRACN != temp1_pllckcfg)
8002626: 6ca2 ldr r2, [r4, #72] @ 0x48
8002628: 429a cmp r2, r3
800262a: d101 bne.n 8002630 <HAL_RCC_OscConfig+0x5f4>
return HAL_OK;
800262c: 2000 movs r0, #0
800262e: e022 b.n 8002676 <HAL_RCC_OscConfig+0x63a>
__HAL_RCC_PLLFRACN_DISABLE();
8002630: 4a18 ldr r2, [pc, #96] @ (8002694 <HAL_RCC_OscConfig+0x658>)
8002632: 6ad3 ldr r3, [r2, #44] @ 0x2c
8002634: f023 0301 bic.w r3, r3, #1
8002638: 62d3 str r3, [r2, #44] @ 0x2c
tickstart = HAL_GetTick();
800263a: f7fe f955 bl 80008e8 <HAL_GetTick>
800263e: 4605 mov r5, r0
while ((HAL_GetTick() - tickstart) < PLL_FRAC_TIMEOUT_VALUE)
8002640: f7fe f952 bl 80008e8 <HAL_GetTick>
8002644: 42a8 cmp r0, r5
8002646: d0fb beq.n 8002640 <HAL_RCC_OscConfig+0x604>
__HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN);
8002648: 4a12 ldr r2, [pc, #72] @ (8002694 <HAL_RCC_OscConfig+0x658>)
800264a: 6b53 ldr r3, [r2, #52] @ 0x34
800264c: f36f 03cf bfc r3, #3, #13
8002650: 6ca1 ldr r1, [r4, #72] @ 0x48
8002652: ea43 03c1 orr.w r3, r3, r1, lsl #3
8002656: 6353 str r3, [r2, #52] @ 0x34
__HAL_RCC_PLLFRACN_ENABLE();
8002658: 6ad3 ldr r3, [r2, #44] @ 0x2c
800265a: f043 0301 orr.w r3, r3, #1
800265e: 62d3 str r3, [r2, #44] @ 0x2c
return HAL_OK;
8002660: 2000 movs r0, #0
8002662: e008 b.n 8002676 <HAL_RCC_OscConfig+0x63a>
return HAL_ERROR;
8002664: 2001 movs r0, #1
}
8002666: 4770 bx lr
return HAL_ERROR;
8002668: 2001 movs r0, #1
800266a: e004 b.n 8002676 <HAL_RCC_OscConfig+0x63a>
return HAL_ERROR;
800266c: 2001 movs r0, #1
800266e: e002 b.n 8002676 <HAL_RCC_OscConfig+0x63a>
return HAL_ERROR;
8002670: 2001 movs r0, #1
8002672: e000 b.n 8002676 <HAL_RCC_OscConfig+0x63a>
return HAL_OK;
8002674: 2000 movs r0, #0
}
8002676: bd38 pop {r3, r4, r5, pc}
return HAL_ERROR;
8002678: 2001 movs r0, #1
800267a: e7fc b.n 8002676 <HAL_RCC_OscConfig+0x63a>
800267c: 2001 movs r0, #1
800267e: e7fa b.n 8002676 <HAL_RCC_OscConfig+0x63a>
8002680: 2001 movs r0, #1
8002682: e7f8 b.n 8002676 <HAL_RCC_OscConfig+0x63a>
8002684: 2001 movs r0, #1
8002686: e7f6 b.n 8002676 <HAL_RCC_OscConfig+0x63a>
8002688: 2001 movs r0, #1
800268a: e7f4 b.n 8002676 <HAL_RCC_OscConfig+0x63a>
800268c: 2001 movs r0, #1
800268e: e7f2 b.n 8002676 <HAL_RCC_OscConfig+0x63a>
8002690: 2001 movs r0, #1
8002692: e7f0 b.n 8002676 <HAL_RCC_OscConfig+0x63a>
8002694: 58024400 .word 0x58024400
8002698: fffffc0c .word 0xfffffc0c
0800269c <HAL_RCC_GetSysClockFreq>:
float_t fracn1, pllvco;
uint32_t sysclockfreq;
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
800269c: 4b75 ldr r3, [pc, #468] @ (8002874 <HAL_RCC_GetSysClockFreq+0x1d8>)
800269e: 691b ldr r3, [r3, #16]
80026a0: f003 0338 and.w r3, r3, #56 @ 0x38
80026a4: 2b10 cmp r3, #16
80026a6: f000 80de beq.w 8002866 <HAL_RCC_GetSysClockFreq+0x1ca>
80026aa: 2b18 cmp r3, #24
80026ac: d00f beq.n 80026ce <HAL_RCC_GetSysClockFreq+0x32>
80026ae: 2b00 cmp r3, #0
80026b0: f040 80db bne.w 800286a <HAL_RCC_GetSysClockFreq+0x1ce>
{
case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
80026b4: 4b6f ldr r3, [pc, #444] @ (8002874 <HAL_RCC_GetSysClockFreq+0x1d8>)
80026b6: 681b ldr r3, [r3, #0]
80026b8: f013 0f20 tst.w r3, #32
80026bc: f000 80d7 beq.w 800286e <HAL_RCC_GetSysClockFreq+0x1d2>
{
sysclockfreq = (uint32_t)(HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
80026c0: 4b6c ldr r3, [pc, #432] @ (8002874 <HAL_RCC_GetSysClockFreq+0x1d8>)
80026c2: 681b ldr r3, [r3, #0]
80026c4: f3c3 03c1 ubfx r3, r3, #3, #2
80026c8: 486b ldr r0, [pc, #428] @ (8002878 <HAL_RCC_GetSysClockFreq+0x1dc>)
80026ca: 40d8 lsrs r0, r3
80026cc: 4770 bx lr
{
80026ce: b410 push {r4}
case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
SYSCLK = PLL_VCO / PLLR
*/
pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
80026d0: 4b68 ldr r3, [pc, #416] @ (8002874 <HAL_RCC_GetSysClockFreq+0x1d8>)
80026d2: 6a9a ldr r2, [r3, #40] @ 0x28
80026d4: f002 0203 and.w r2, r2, #3
pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4) ;
80026d8: 6a9c ldr r4, [r3, #40] @ 0x28
80026da: f3c4 1005 ubfx r0, r4, #4, #6
pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos);
80026de: 6ad9 ldr r1, [r3, #44] @ 0x2c
80026e0: f001 0101 and.w r1, r1, #1
fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3));
80026e4: 6b5b ldr r3, [r3, #52] @ 0x34
80026e6: f3c3 03cc ubfx r3, r3, #3, #13
80026ea: fb01 f303 mul.w r3, r1, r3
80026ee: ee07 3a90 vmov s15, r3
80026f2: eef8 7a67 vcvt.f32.u32 s15, s15
if (pllm != 0U)
80026f6: f414 7f7c tst.w r4, #1008 @ 0x3f0
80026fa: d077 beq.n 80027ec <HAL_RCC_GetSysClockFreq+0x150>
{
switch (pllsource)
80026fc: 2a01 cmp r2, #1
80026fe: d04a beq.n 8002796 <HAL_RCC_GetSysClockFreq+0xfa>
8002700: 2a02 cmp r2, #2
8002702: d076 beq.n 80027f2 <HAL_RCC_GetSysClockFreq+0x156>
8002704: 2a00 cmp r2, #0
8002706: f040 8091 bne.w 800282c <HAL_RCC_GetSysClockFreq+0x190>
{
case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
800270a: 4b5a ldr r3, [pc, #360] @ (8002874 <HAL_RCC_GetSysClockFreq+0x1d8>)
800270c: 681b ldr r3, [r3, #0]
800270e: f013 0f20 tst.w r3, #32
8002712: d023 beq.n 800275c <HAL_RCC_GetSysClockFreq+0xc0>
{
hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
8002714: 4957 ldr r1, [pc, #348] @ (8002874 <HAL_RCC_GetSysClockFreq+0x1d8>)
8002716: 680a ldr r2, [r1, #0]
8002718: f3c2 02c1 ubfx r2, r2, #3, #2
800271c: 4b56 ldr r3, [pc, #344] @ (8002878 <HAL_RCC_GetSysClockFreq+0x1dc>)
800271e: 40d3 lsrs r3, r2
pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
8002720: ee07 3a10 vmov s14, r3
8002724: eef8 6a47 vcvt.f32.u32 s13, s14
8002728: ee07 0a10 vmov s14, r0
800272c: eeb8 6a47 vcvt.f32.u32 s12, s14
8002730: ee86 7a86 vdiv.f32 s14, s13, s12
8002734: 6b0b ldr r3, [r1, #48] @ 0x30
8002736: f3c3 0308 ubfx r3, r3, #0, #9
800273a: ee06 3a90 vmov s13, r3
800273e: eef8 6a66 vcvt.f32.u32 s13, s13
8002742: ed9f 6a4e vldr s12, [pc, #312] @ 800287c <HAL_RCC_GetSysClockFreq+0x1e0>
8002746: ee67 7a86 vmul.f32 s15, s15, s12
800274a: ee76 7aa7 vadd.f32 s15, s13, s15
800274e: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0
8002752: ee77 7aa6 vadd.f32 s15, s15, s13
8002756: ee27 7a27 vmul.f32 s14, s14, s15
800275a: e038 b.n 80027ce <HAL_RCC_GetSysClockFreq+0x132>
}
else
{
pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
800275c: ee07 0a10 vmov s14, r0
8002760: eef8 6a47 vcvt.f32.u32 s13, s14
8002764: ed9f 6a46 vldr s12, [pc, #280] @ 8002880 <HAL_RCC_GetSysClockFreq+0x1e4>
8002768: ee86 7a26 vdiv.f32 s14, s12, s13
800276c: 4b41 ldr r3, [pc, #260] @ (8002874 <HAL_RCC_GetSysClockFreq+0x1d8>)
800276e: 6b1b ldr r3, [r3, #48] @ 0x30
8002770: f3c3 0308 ubfx r3, r3, #0, #9
8002774: ee06 3a90 vmov s13, r3
8002778: eef8 6a66 vcvt.f32.u32 s13, s13
800277c: ed9f 6a3f vldr s12, [pc, #252] @ 800287c <HAL_RCC_GetSysClockFreq+0x1e0>
8002780: ee67 7a86 vmul.f32 s15, s15, s12
8002784: ee76 7aa7 vadd.f32 s15, s13, s15
8002788: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0
800278c: ee77 7aa6 vadd.f32 s15, s15, s13
8002790: ee27 7a27 vmul.f32 s14, s14, s15
8002794: e01b b.n 80027ce <HAL_RCC_GetSysClockFreq+0x132>
}
break;
case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */
pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
8002796: ee07 0a10 vmov s14, r0
800279a: eef8 6a47 vcvt.f32.u32 s13, s14
800279e: ed9f 6a39 vldr s12, [pc, #228] @ 8002884 <HAL_RCC_GetSysClockFreq+0x1e8>
80027a2: ee86 7a26 vdiv.f32 s14, s12, s13
80027a6: 4b33 ldr r3, [pc, #204] @ (8002874 <HAL_RCC_GetSysClockFreq+0x1d8>)
80027a8: 6b1b ldr r3, [r3, #48] @ 0x30
80027aa: f3c3 0308 ubfx r3, r3, #0, #9
80027ae: ee06 3a90 vmov s13, r3
80027b2: eef8 6a66 vcvt.f32.u32 s13, s13
80027b6: ed9f 6a31 vldr s12, [pc, #196] @ 800287c <HAL_RCC_GetSysClockFreq+0x1e0>
80027ba: ee67 7a86 vmul.f32 s15, s15, s12
80027be: ee76 7aa7 vadd.f32 s15, s13, s15
80027c2: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0
80027c6: ee77 7aa6 vadd.f32 s15, s15, s13
80027ca: ee27 7a27 vmul.f32 s14, s14, s15
default:
pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
break;
}
pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + 1U) ;
80027ce: 4b29 ldr r3, [pc, #164] @ (8002874 <HAL_RCC_GetSysClockFreq+0x1d8>)
80027d0: 6b1b ldr r3, [r3, #48] @ 0x30
80027d2: f3c3 2346 ubfx r3, r3, #9, #7
80027d6: 3301 adds r3, #1
sysclockfreq = (uint32_t)(float_t)(pllvco / (float_t)pllp);
80027d8: ee07 3a90 vmov s15, r3
80027dc: eef8 7a67 vcvt.f32.u32 s15, s15
80027e0: eec7 6a27 vdiv.f32 s13, s14, s15
80027e4: eefc 7ae6 vcvt.u32.f32 s15, s13
80027e8: ee17 0a90 vmov r0, s15
sysclockfreq = CSI_VALUE;
break;
}
return sysclockfreq;
}
80027ec: f85d 4b04 ldr.w r4, [sp], #4
80027f0: 4770 bx lr
pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
80027f2: ee07 0a10 vmov s14, r0
80027f6: eef8 6a47 vcvt.f32.u32 s13, s14
80027fa: ed9f 6a23 vldr s12, [pc, #140] @ 8002888 <HAL_RCC_GetSysClockFreq+0x1ec>
80027fe: ee86 7a26 vdiv.f32 s14, s12, s13
8002802: 4b1c ldr r3, [pc, #112] @ (8002874 <HAL_RCC_GetSysClockFreq+0x1d8>)
8002804: 6b1b ldr r3, [r3, #48] @ 0x30
8002806: f3c3 0308 ubfx r3, r3, #0, #9
800280a: ee06 3a90 vmov s13, r3
800280e: eef8 6a66 vcvt.f32.u32 s13, s13
8002812: ed9f 6a1a vldr s12, [pc, #104] @ 800287c <HAL_RCC_GetSysClockFreq+0x1e0>
8002816: ee67 7a86 vmul.f32 s15, s15, s12
800281a: ee76 7aa7 vadd.f32 s15, s13, s15
800281e: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0
8002822: ee77 7aa6 vadd.f32 s15, s15, s13
8002826: ee27 7a27 vmul.f32 s14, s14, s15
break;
800282a: e7d0 b.n 80027ce <HAL_RCC_GetSysClockFreq+0x132>
pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
800282c: ee07 0a10 vmov s14, r0
8002830: eef8 6a47 vcvt.f32.u32 s13, s14
8002834: ed9f 6a13 vldr s12, [pc, #76] @ 8002884 <HAL_RCC_GetSysClockFreq+0x1e8>
8002838: ee86 7a26 vdiv.f32 s14, s12, s13
800283c: 4b0d ldr r3, [pc, #52] @ (8002874 <HAL_RCC_GetSysClockFreq+0x1d8>)
800283e: 6b1b ldr r3, [r3, #48] @ 0x30
8002840: f3c3 0308 ubfx r3, r3, #0, #9
8002844: ee06 3a90 vmov s13, r3
8002848: eef8 6a66 vcvt.f32.u32 s13, s13
800284c: ed9f 6a0b vldr s12, [pc, #44] @ 800287c <HAL_RCC_GetSysClockFreq+0x1e0>
8002850: ee67 7a86 vmul.f32 s15, s15, s12
8002854: ee76 7aa7 vadd.f32 s15, s13, s15
8002858: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0
800285c: ee77 7aa6 vadd.f32 s15, s15, s13
8002860: ee27 7a27 vmul.f32 s14, s14, s15
break;
8002864: e7b3 b.n 80027ce <HAL_RCC_GetSysClockFreq+0x132>
sysclockfreq = HSE_VALUE;
8002866: 4809 ldr r0, [pc, #36] @ (800288c <HAL_RCC_GetSysClockFreq+0x1f0>)
8002868: 4770 bx lr
switch (RCC->CFGR & RCC_CFGR_SWS)
800286a: 4809 ldr r0, [pc, #36] @ (8002890 <HAL_RCC_GetSysClockFreq+0x1f4>)
800286c: 4770 bx lr
sysclockfreq = (uint32_t) HSI_VALUE;
800286e: 4802 ldr r0, [pc, #8] @ (8002878 <HAL_RCC_GetSysClockFreq+0x1dc>)
}
8002870: 4770 bx lr
8002872: bf00 nop
8002874: 58024400 .word 0x58024400
8002878: 03d09000 .word 0x03d09000
800287c: 39000000 .word 0x39000000
8002880: 4c742400 .word 0x4c742400
8002884: 4a742400 .word 0x4a742400
8002888: 4b742400 .word 0x4b742400
800288c: 00f42400 .word 0x00f42400
8002890: 003d0900 .word 0x003d0900
08002894 <HAL_RCC_ClockConfig>:
if (RCC_ClkInitStruct == NULL)
8002894: 2800 cmp r0, #0
8002896: f000 8132 beq.w 8002afe <HAL_RCC_ClockConfig+0x26a>
{
800289a: b570 push {r4, r5, r6, lr}
800289c: 460d mov r5, r1
800289e: 4604 mov r4, r0
if (FLatency > __HAL_FLASH_GET_LATENCY())
80028a0: 4b9b ldr r3, [pc, #620] @ (8002b10 <HAL_RCC_ClockConfig+0x27c>)
80028a2: 681b ldr r3, [r3, #0]
80028a4: f003 030f and.w r3, r3, #15
80028a8: 428b cmp r3, r1
80028aa: d20b bcs.n 80028c4 <HAL_RCC_ClockConfig+0x30>
__HAL_FLASH_SET_LATENCY(FLatency);
80028ac: 4a98 ldr r2, [pc, #608] @ (8002b10 <HAL_RCC_ClockConfig+0x27c>)
80028ae: 6813 ldr r3, [r2, #0]
80028b0: f023 030f bic.w r3, r3, #15
80028b4: 430b orrs r3, r1
80028b6: 6013 str r3, [r2, #0]
if (__HAL_FLASH_GET_LATENCY() != FLatency)
80028b8: 6813 ldr r3, [r2, #0]
80028ba: f003 030f and.w r3, r3, #15
80028be: 428b cmp r3, r1
80028c0: f040 811f bne.w 8002b02 <HAL_RCC_ClockConfig+0x26e>
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1)
80028c4: 6823 ldr r3, [r4, #0]
80028c6: f013 0f04 tst.w r3, #4
80028ca: d00c beq.n 80028e6 <HAL_RCC_ClockConfig+0x52>
if ((RCC_ClkInitStruct->APB3CLKDivider) > (RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE))
80028cc: 6922 ldr r2, [r4, #16]
80028ce: 4b91 ldr r3, [pc, #580] @ (8002b14 <HAL_RCC_ClockConfig+0x280>)
80028d0: 699b ldr r3, [r3, #24]
80028d2: f003 0370 and.w r3, r3, #112 @ 0x70
80028d6: 429a cmp r2, r3
80028d8: d905 bls.n 80028e6 <HAL_RCC_ClockConfig+0x52>
MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, RCC_ClkInitStruct->APB3CLKDivider);
80028da: 498e ldr r1, [pc, #568] @ (8002b14 <HAL_RCC_ClockConfig+0x280>)
80028dc: 698b ldr r3, [r1, #24]
80028de: f023 0370 bic.w r3, r3, #112 @ 0x70
80028e2: 431a orrs r2, r3
80028e4: 618a str r2, [r1, #24]
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
80028e6: 6823 ldr r3, [r4, #0]
80028e8: f013 0f08 tst.w r3, #8
80028ec: d00c beq.n 8002908 <HAL_RCC_ClockConfig+0x74>
if ((RCC_ClkInitStruct->APB1CLKDivider) > (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1))
80028ee: 6962 ldr r2, [r4, #20]
80028f0: 4b88 ldr r3, [pc, #544] @ (8002b14 <HAL_RCC_ClockConfig+0x280>)
80028f2: 69db ldr r3, [r3, #28]
80028f4: f003 0370 and.w r3, r3, #112 @ 0x70
80028f8: 429a cmp r2, r3
80028fa: d905 bls.n 8002908 <HAL_RCC_ClockConfig+0x74>
MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
80028fc: 4985 ldr r1, [pc, #532] @ (8002b14 <HAL_RCC_ClockConfig+0x280>)
80028fe: 69cb ldr r3, [r1, #28]
8002900: f023 0370 bic.w r3, r3, #112 @ 0x70
8002904: 431a orrs r2, r3
8002906: 61ca str r2, [r1, #28]
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8002908: 6823 ldr r3, [r4, #0]
800290a: f013 0f10 tst.w r3, #16
800290e: d00c beq.n 800292a <HAL_RCC_ClockConfig+0x96>
if ((RCC_ClkInitStruct->APB2CLKDivider) > (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2))
8002910: 69a2 ldr r2, [r4, #24]
8002912: 4b80 ldr r3, [pc, #512] @ (8002b14 <HAL_RCC_ClockConfig+0x280>)
8002914: 69db ldr r3, [r3, #28]
8002916: f403 63e0 and.w r3, r3, #1792 @ 0x700
800291a: 429a cmp r2, r3
800291c: d905 bls.n 800292a <HAL_RCC_ClockConfig+0x96>
MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
800291e: 497d ldr r1, [pc, #500] @ (8002b14 <HAL_RCC_ClockConfig+0x280>)
8002920: 69cb ldr r3, [r1, #28]
8002922: f423 63e0 bic.w r3, r3, #1792 @ 0x700
8002926: 431a orrs r2, r3
8002928: 61ca str r2, [r1, #28]
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1)
800292a: 6823 ldr r3, [r4, #0]
800292c: f013 0f20 tst.w r3, #32
8002930: d00c beq.n 800294c <HAL_RCC_ClockConfig+0xb8>
if ((RCC_ClkInitStruct->APB4CLKDivider) > (RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE))
8002932: 69e2 ldr r2, [r4, #28]
8002934: 4b77 ldr r3, [pc, #476] @ (8002b14 <HAL_RCC_ClockConfig+0x280>)
8002936: 6a1b ldr r3, [r3, #32]
8002938: f003 0370 and.w r3, r3, #112 @ 0x70
800293c: 429a cmp r2, r3
800293e: d905 bls.n 800294c <HAL_RCC_ClockConfig+0xb8>
MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, (RCC_ClkInitStruct->APB4CLKDivider));
8002940: 4974 ldr r1, [pc, #464] @ (8002b14 <HAL_RCC_ClockConfig+0x280>)
8002942: 6a0b ldr r3, [r1, #32]
8002944: f023 0370 bic.w r3, r3, #112 @ 0x70
8002948: 431a orrs r2, r3
800294a: 620a str r2, [r1, #32]
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
800294c: 6823 ldr r3, [r4, #0]
800294e: f013 0f02 tst.w r3, #2
8002952: d00c beq.n 800296e <HAL_RCC_ClockConfig+0xda>
if ((RCC_ClkInitStruct->AHBCLKDivider) > (RCC->CDCFGR1 & RCC_CDCFGR1_HPRE))
8002954: 68e2 ldr r2, [r4, #12]
8002956: 4b6f ldr r3, [pc, #444] @ (8002b14 <HAL_RCC_ClockConfig+0x280>)
8002958: 699b ldr r3, [r3, #24]
800295a: f003 030f and.w r3, r3, #15
800295e: 429a cmp r2, r3
8002960: d905 bls.n 800296e <HAL_RCC_ClockConfig+0xda>
MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8002962: 496c ldr r1, [pc, #432] @ (8002b14 <HAL_RCC_ClockConfig+0x280>)
8002964: 698b ldr r3, [r1, #24]
8002966: f023 030f bic.w r3, r3, #15
800296a: 431a orrs r2, r3
800296c: 618a str r2, [r1, #24]
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
800296e: 6823 ldr r3, [r4, #0]
8002970: f013 0f01 tst.w r3, #1
8002974: d041 beq.n 80029fa <HAL_RCC_ClockConfig+0x166>
MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, RCC_ClkInitStruct->SYSCLKDivider);
8002976: 4a67 ldr r2, [pc, #412] @ (8002b14 <HAL_RCC_ClockConfig+0x280>)
8002978: 6993 ldr r3, [r2, #24]
800297a: f423 6370 bic.w r3, r3, #3840 @ 0xf00
800297e: 68a1 ldr r1, [r4, #8]
8002980: 430b orrs r3, r1
8002982: 6193 str r3, [r2, #24]
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8002984: 6863 ldr r3, [r4, #4]
8002986: 2b02 cmp r3, #2
8002988: d00a beq.n 80029a0 <HAL_RCC_ClockConfig+0x10c>
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
800298a: 2b03 cmp r3, #3
800298c: d027 beq.n 80029de <HAL_RCC_ClockConfig+0x14a>
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI)
800298e: 2b01 cmp r3, #1
8002990: d02c beq.n 80029ec <HAL_RCC_ClockConfig+0x158>
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
8002992: 4a60 ldr r2, [pc, #384] @ (8002b14 <HAL_RCC_ClockConfig+0x280>)
8002994: 6812 ldr r2, [r2, #0]
8002996: f012 0f04 tst.w r2, #4
800299a: d106 bne.n 80029aa <HAL_RCC_ClockConfig+0x116>
return HAL_ERROR;
800299c: 2001 movs r0, #1
800299e: e0ad b.n 8002afc <HAL_RCC_ClockConfig+0x268>
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
80029a0: 6812 ldr r2, [r2, #0]
80029a2: f412 3f00 tst.w r2, #131072 @ 0x20000
80029a6: f000 80ae beq.w 8002b06 <HAL_RCC_ClockConfig+0x272>
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
80029aa: 495a ldr r1, [pc, #360] @ (8002b14 <HAL_RCC_ClockConfig+0x280>)
80029ac: 690a ldr r2, [r1, #16]
80029ae: f022 0207 bic.w r2, r2, #7
80029b2: 4313 orrs r3, r2
80029b4: 610b str r3, [r1, #16]
tickstart = HAL_GetTick();
80029b6: f7fd ff97 bl 80008e8 <HAL_GetTick>
80029ba: 4606 mov r6, r0
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
80029bc: 4b55 ldr r3, [pc, #340] @ (8002b14 <HAL_RCC_ClockConfig+0x280>)
80029be: 691b ldr r3, [r3, #16]
80029c0: f003 0338 and.w r3, r3, #56 @ 0x38
80029c4: 6862 ldr r2, [r4, #4]
80029c6: ebb3 0fc2 cmp.w r3, r2, lsl #3
80029ca: d016 beq.n 80029fa <HAL_RCC_ClockConfig+0x166>
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
80029cc: f7fd ff8c bl 80008e8 <HAL_GetTick>
80029d0: 1b80 subs r0, r0, r6
80029d2: f241 3388 movw r3, #5000 @ 0x1388
80029d6: 4298 cmp r0, r3
80029d8: d9f0 bls.n 80029bc <HAL_RCC_ClockConfig+0x128>
return HAL_TIMEOUT;
80029da: 2003 movs r0, #3
80029dc: e08e b.n 8002afc <HAL_RCC_ClockConfig+0x268>
if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
80029de: 4a4d ldr r2, [pc, #308] @ (8002b14 <HAL_RCC_ClockConfig+0x280>)
80029e0: 6812 ldr r2, [r2, #0]
80029e2: f012 7f00 tst.w r2, #33554432 @ 0x2000000
80029e6: d1e0 bne.n 80029aa <HAL_RCC_ClockConfig+0x116>
return HAL_ERROR;
80029e8: 2001 movs r0, #1
80029ea: e087 b.n 8002afc <HAL_RCC_ClockConfig+0x268>
if (__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == 0U)
80029ec: 4a49 ldr r2, [pc, #292] @ (8002b14 <HAL_RCC_ClockConfig+0x280>)
80029ee: 6812 ldr r2, [r2, #0]
80029f0: f412 7f80 tst.w r2, #256 @ 0x100
80029f4: d1d9 bne.n 80029aa <HAL_RCC_ClockConfig+0x116>
return HAL_ERROR;
80029f6: 2001 movs r0, #1
80029f8: e080 b.n 8002afc <HAL_RCC_ClockConfig+0x268>
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
80029fa: 6823 ldr r3, [r4, #0]
80029fc: f013 0f02 tst.w r3, #2
8002a00: d00c beq.n 8002a1c <HAL_RCC_ClockConfig+0x188>
if ((RCC_ClkInitStruct->AHBCLKDivider) < (RCC->CDCFGR1 & RCC_CDCFGR1_HPRE))
8002a02: 68e2 ldr r2, [r4, #12]
8002a04: 4b43 ldr r3, [pc, #268] @ (8002b14 <HAL_RCC_ClockConfig+0x280>)
8002a06: 699b ldr r3, [r3, #24]
8002a08: f003 030f and.w r3, r3, #15
8002a0c: 429a cmp r2, r3
8002a0e: d205 bcs.n 8002a1c <HAL_RCC_ClockConfig+0x188>
MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8002a10: 4940 ldr r1, [pc, #256] @ (8002b14 <HAL_RCC_ClockConfig+0x280>)
8002a12: 698b ldr r3, [r1, #24]
8002a14: f023 030f bic.w r3, r3, #15
8002a18: 431a orrs r2, r3
8002a1a: 618a str r2, [r1, #24]
if (FLatency < __HAL_FLASH_GET_LATENCY())
8002a1c: 4b3c ldr r3, [pc, #240] @ (8002b10 <HAL_RCC_ClockConfig+0x27c>)
8002a1e: 681b ldr r3, [r3, #0]
8002a20: f003 030f and.w r3, r3, #15
8002a24: 42ab cmp r3, r5
8002a26: d90a bls.n 8002a3e <HAL_RCC_ClockConfig+0x1aa>
__HAL_FLASH_SET_LATENCY(FLatency);
8002a28: 4a39 ldr r2, [pc, #228] @ (8002b10 <HAL_RCC_ClockConfig+0x27c>)
8002a2a: 6813 ldr r3, [r2, #0]
8002a2c: f023 030f bic.w r3, r3, #15
8002a30: 432b orrs r3, r5
8002a32: 6013 str r3, [r2, #0]
if (__HAL_FLASH_GET_LATENCY() != FLatency)
8002a34: 6813 ldr r3, [r2, #0]
8002a36: f003 030f and.w r3, r3, #15
8002a3a: 42ab cmp r3, r5
8002a3c: d165 bne.n 8002b0a <HAL_RCC_ClockConfig+0x276>
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1)
8002a3e: 6823 ldr r3, [r4, #0]
8002a40: f013 0f04 tst.w r3, #4
8002a44: d00c beq.n 8002a60 <HAL_RCC_ClockConfig+0x1cc>
if ((RCC_ClkInitStruct->APB3CLKDivider) < (RCC->CDCFGR1 & RCC_CDCFGR1_CDPPRE))
8002a46: 6922 ldr r2, [r4, #16]
8002a48: 4b32 ldr r3, [pc, #200] @ (8002b14 <HAL_RCC_ClockConfig+0x280>)
8002a4a: 699b ldr r3, [r3, #24]
8002a4c: f003 0370 and.w r3, r3, #112 @ 0x70
8002a50: 429a cmp r2, r3
8002a52: d205 bcs.n 8002a60 <HAL_RCC_ClockConfig+0x1cc>
MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, RCC_ClkInitStruct->APB3CLKDivider);
8002a54: 492f ldr r1, [pc, #188] @ (8002b14 <HAL_RCC_ClockConfig+0x280>)
8002a56: 698b ldr r3, [r1, #24]
8002a58: f023 0370 bic.w r3, r3, #112 @ 0x70
8002a5c: 431a orrs r2, r3
8002a5e: 618a str r2, [r1, #24]
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8002a60: 6823 ldr r3, [r4, #0]
8002a62: f013 0f08 tst.w r3, #8
8002a66: d00c beq.n 8002a82 <HAL_RCC_ClockConfig+0x1ee>
if ((RCC_ClkInitStruct->APB1CLKDivider) < (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1))
8002a68: 6962 ldr r2, [r4, #20]
8002a6a: 4b2a ldr r3, [pc, #168] @ (8002b14 <HAL_RCC_ClockConfig+0x280>)
8002a6c: 69db ldr r3, [r3, #28]
8002a6e: f003 0370 and.w r3, r3, #112 @ 0x70
8002a72: 429a cmp r2, r3
8002a74: d205 bcs.n 8002a82 <HAL_RCC_ClockConfig+0x1ee>
MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
8002a76: 4927 ldr r1, [pc, #156] @ (8002b14 <HAL_RCC_ClockConfig+0x280>)
8002a78: 69cb ldr r3, [r1, #28]
8002a7a: f023 0370 bic.w r3, r3, #112 @ 0x70
8002a7e: 431a orrs r2, r3
8002a80: 61ca str r2, [r1, #28]
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8002a82: 6823 ldr r3, [r4, #0]
8002a84: f013 0f10 tst.w r3, #16
8002a88: d00c beq.n 8002aa4 <HAL_RCC_ClockConfig+0x210>
if ((RCC_ClkInitStruct->APB2CLKDivider) < (RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2))
8002a8a: 69a2 ldr r2, [r4, #24]
8002a8c: 4b21 ldr r3, [pc, #132] @ (8002b14 <HAL_RCC_ClockConfig+0x280>)
8002a8e: 69db ldr r3, [r3, #28]
8002a90: f403 63e0 and.w r3, r3, #1792 @ 0x700
8002a94: 429a cmp r2, r3
8002a96: d205 bcs.n 8002aa4 <HAL_RCC_ClockConfig+0x210>
MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
8002a98: 491e ldr r1, [pc, #120] @ (8002b14 <HAL_RCC_ClockConfig+0x280>)
8002a9a: 69cb ldr r3, [r1, #28]
8002a9c: f423 63e0 bic.w r3, r3, #1792 @ 0x700
8002aa0: 431a orrs r2, r3
8002aa2: 61ca str r2, [r1, #28]
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1)
8002aa4: 6823 ldr r3, [r4, #0]
8002aa6: f013 0f20 tst.w r3, #32
8002aaa: d00c beq.n 8002ac6 <HAL_RCC_ClockConfig+0x232>
if ((RCC_ClkInitStruct->APB4CLKDivider) < (RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE))
8002aac: 69e2 ldr r2, [r4, #28]
8002aae: 4b19 ldr r3, [pc, #100] @ (8002b14 <HAL_RCC_ClockConfig+0x280>)
8002ab0: 6a1b ldr r3, [r3, #32]
8002ab2: f003 0370 and.w r3, r3, #112 @ 0x70
8002ab6: 429a cmp r2, r3
8002ab8: d205 bcs.n 8002ac6 <HAL_RCC_ClockConfig+0x232>
MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, (RCC_ClkInitStruct->APB4CLKDivider));
8002aba: 4916 ldr r1, [pc, #88] @ (8002b14 <HAL_RCC_ClockConfig+0x280>)
8002abc: 6a0b ldr r3, [r1, #32]
8002abe: f023 0370 bic.w r3, r3, #112 @ 0x70
8002ac2: 431a orrs r2, r3
8002ac4: 620a str r2, [r1, #32]
common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU);
8002ac6: f7ff fde9 bl 800269c <HAL_RCC_GetSysClockFreq>
8002aca: 4912 ldr r1, [pc, #72] @ (8002b14 <HAL_RCC_ClockConfig+0x280>)
8002acc: 698b ldr r3, [r1, #24]
8002ace: f3c3 2303 ubfx r3, r3, #8, #4
8002ad2: 4a11 ldr r2, [pc, #68] @ (8002b18 <HAL_RCC_ClockConfig+0x284>)
8002ad4: 5cd3 ldrb r3, [r2, r3]
8002ad6: f003 031f and.w r3, r3, #31
8002ada: 40d8 lsrs r0, r3
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
8002adc: 698b ldr r3, [r1, #24]
8002ade: f003 030f and.w r3, r3, #15
8002ae2: 5cd3 ldrb r3, [r2, r3]
8002ae4: f003 031f and.w r3, r3, #31
8002ae8: fa20 f303 lsr.w r3, r0, r3
8002aec: 4a0b ldr r2, [pc, #44] @ (8002b1c <HAL_RCC_ClockConfig+0x288>)
8002aee: 6013 str r3, [r2, #0]
SystemCoreClock = common_system_clock;
8002af0: 4b0b ldr r3, [pc, #44] @ (8002b20 <HAL_RCC_ClockConfig+0x28c>)
8002af2: 6018 str r0, [r3, #0]
halstatus = HAL_InitTick(uwTickPrio);
8002af4: 4b0b ldr r3, [pc, #44] @ (8002b24 <HAL_RCC_ClockConfig+0x290>)
8002af6: 6818 ldr r0, [r3, #0]
8002af8: f7fd fe94 bl 8000824 <HAL_InitTick>
}
8002afc: bd70 pop {r4, r5, r6, pc}
return HAL_ERROR;
8002afe: 2001 movs r0, #1
}
8002b00: 4770 bx lr
return HAL_ERROR;
8002b02: 2001 movs r0, #1
8002b04: e7fa b.n 8002afc <HAL_RCC_ClockConfig+0x268>
return HAL_ERROR;
8002b06: 2001 movs r0, #1
8002b08: e7f8 b.n 8002afc <HAL_RCC_ClockConfig+0x268>
return HAL_ERROR;
8002b0a: 2001 movs r0, #1
8002b0c: e7f6 b.n 8002afc <HAL_RCC_ClockConfig+0x268>
8002b0e: bf00 nop
8002b10: 52002000 .word 0x52002000
8002b14: 58024400 .word 0x58024400
8002b18: 08004dec .word 0x08004dec
8002b1c: 20000008 .word 0x20000008
8002b20: 2000000c .word 0x2000000c
8002b24: 20000004 .word 0x20000004
08002b28 <HAL_RCC_GetHCLKFreq>:
* @note The SystemD2Clock CMSIS variable is used to store System domain2 Clock Frequency
* and updated within this function
* @retval HCLK frequency
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
8002b28: b508 push {r3, lr}
uint32_t common_system_clock;
#if defined(RCC_D1CFGR_D1CPRE)
common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos] & 0x1FU);
#else
common_system_clock = HAL_RCC_GetSysClockFreq() >> (D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos] & 0x1FU);
8002b2a: f7ff fdb7 bl 800269c <HAL_RCC_GetSysClockFreq>
8002b2e: 4a0b ldr r2, [pc, #44] @ (8002b5c <HAL_RCC_GetHCLKFreq+0x34>)
8002b30: 6993 ldr r3, [r2, #24]
8002b32: f3c3 2303 ubfx r3, r3, #8, #4
8002b36: 490a ldr r1, [pc, #40] @ (8002b60 <HAL_RCC_GetHCLKFreq+0x38>)
8002b38: 5ccb ldrb r3, [r1, r3]
8002b3a: f003 031f and.w r3, r3, #31
8002b3e: fa20 f303 lsr.w r3, r0, r3
#endif
#if defined(RCC_D1CFGR_HPRE)
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
#else
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
8002b42: 6992 ldr r2, [r2, #24]
8002b44: f002 020f and.w r2, r2, #15
8002b48: 5c88 ldrb r0, [r1, r2]
8002b4a: f000 001f and.w r0, r0, #31
8002b4e: fa23 f000 lsr.w r0, r3, r0
8002b52: 4a04 ldr r2, [pc, #16] @ (8002b64 <HAL_RCC_GetHCLKFreq+0x3c>)
8002b54: 6010 str r0, [r2, #0]
#endif
#if defined(DUAL_CORE) && defined(CORE_CM4)
SystemCoreClock = SystemD2Clock;
#else
SystemCoreClock = common_system_clock;
8002b56: 4a04 ldr r2, [pc, #16] @ (8002b68 <HAL_RCC_GetHCLKFreq+0x40>)
8002b58: 6013 str r3, [r2, #0]
#endif /* DUAL_CORE && CORE_CM4 */
return SystemD2Clock;
}
8002b5a: bd08 pop {r3, pc}
8002b5c: 58024400 .word 0x58024400
8002b60: 08004dec .word 0x08004dec
8002b64: 20000008 .word 0x20000008
8002b68: 2000000c .word 0x2000000c
08002b6c <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
8002b6c: b508 push {r3, lr}
#if defined (RCC_D2CFGR_D2PPRE1)
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1) >> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU));
#else
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> ((D1CorePrescTable[(RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE1) >> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU));
8002b6e: f7ff ffdb bl 8002b28 <HAL_RCC_GetHCLKFreq>
8002b72: 4b05 ldr r3, [pc, #20] @ (8002b88 <HAL_RCC_GetPCLK1Freq+0x1c>)
8002b74: 69db ldr r3, [r3, #28]
8002b76: f3c3 1302 ubfx r3, r3, #4, #3
8002b7a: 4a04 ldr r2, [pc, #16] @ (8002b8c <HAL_RCC_GetPCLK1Freq+0x20>)
8002b7c: 5cd3 ldrb r3, [r2, r3]
8002b7e: f003 031f and.w r3, r3, #31
#endif
}
8002b82: 40d8 lsrs r0, r3
8002b84: bd08 pop {r3, pc}
8002b86: bf00 nop
8002b88: 58024400 .word 0x58024400
8002b8c: 08004dec .word 0x08004dec
08002b90 <RCCEx_PLL2_Config>:
assert_param(IS_RCC_PLL2RGE_VALUE(pll2->PLL2RGE));
assert_param(IS_RCC_PLL2VCO_VALUE(pll2->PLL2VCOSEL));
assert_param(IS_RCC_PLLFRACN_VALUE(pll2->PLL2FRACN));
/* Check that PLL2 OSC clock source is already set */
if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
8002b90: 4b40 ldr r3, [pc, #256] @ (8002c94 <RCCEx_PLL2_Config+0x104>)
8002b92: 6a9b ldr r3, [r3, #40] @ 0x28
8002b94: f003 0303 and.w r3, r3, #3
8002b98: 2b03 cmp r3, #3
8002b9a: d079 beq.n 8002c90 <RCCEx_PLL2_Config+0x100>
{
8002b9c: b570 push {r4, r5, r6, lr}
8002b9e: 4605 mov r5, r0
8002ba0: 460e mov r6, r1
else
{
/* Disable PLL2. */
__HAL_RCC_PLL2_DISABLE();
8002ba2: 4a3c ldr r2, [pc, #240] @ (8002c94 <RCCEx_PLL2_Config+0x104>)
8002ba4: 6813 ldr r3, [r2, #0]
8002ba6: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000
8002baa: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002bac: f7fd fe9c bl 80008e8 <HAL_GetTick>
8002bb0: 4604 mov r4, r0
/* Wait till PLL is disabled */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U)
8002bb2: 4b38 ldr r3, [pc, #224] @ (8002c94 <RCCEx_PLL2_Config+0x104>)
8002bb4: 681b ldr r3, [r3, #0]
8002bb6: f013 6f00 tst.w r3, #134217728 @ 0x8000000
8002bba: d006 beq.n 8002bca <RCCEx_PLL2_Config+0x3a>
{
if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
8002bbc: f7fd fe94 bl 80008e8 <HAL_GetTick>
8002bc0: 1b03 subs r3, r0, r4
8002bc2: 2b02 cmp r3, #2
8002bc4: d9f5 bls.n 8002bb2 <RCCEx_PLL2_Config+0x22>
{
return HAL_TIMEOUT;
8002bc6: 2003 movs r0, #3
}
return status;
}
8002bc8: bd70 pop {r4, r5, r6, pc}
__HAL_RCC_PLL2_CONFIG(pll2->PLL2M,
8002bca: 4b32 ldr r3, [pc, #200] @ (8002c94 <RCCEx_PLL2_Config+0x104>)
8002bcc: 6a9a ldr r2, [r3, #40] @ 0x28
8002bce: f422 327c bic.w r2, r2, #258048 @ 0x3f000
8002bd2: 6829 ldr r1, [r5, #0]
8002bd4: ea42 3201 orr.w r2, r2, r1, lsl #12
8002bd8: 629a str r2, [r3, #40] @ 0x28
8002bda: 686a ldr r2, [r5, #4]
8002bdc: 3a01 subs r2, #1
8002bde: f3c2 0208 ubfx r2, r2, #0, #9
8002be2: 68a9 ldr r1, [r5, #8]
8002be4: 3901 subs r1, #1
8002be6: 0249 lsls r1, r1, #9
8002be8: b289 uxth r1, r1
8002bea: 430a orrs r2, r1
8002bec: 68e9 ldr r1, [r5, #12]
8002bee: 3901 subs r1, #1
8002bf0: 0409 lsls r1, r1, #16
8002bf2: f401 01fe and.w r1, r1, #8323072 @ 0x7f0000
8002bf6: 430a orrs r2, r1
8002bf8: 6929 ldr r1, [r5, #16]
8002bfa: 3901 subs r1, #1
8002bfc: 0609 lsls r1, r1, #24
8002bfe: f001 41fe and.w r1, r1, #2130706432 @ 0x7f000000
8002c02: 430a orrs r2, r1
8002c04: 639a str r2, [r3, #56] @ 0x38
__HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE) ;
8002c06: 6ada ldr r2, [r3, #44] @ 0x2c
8002c08: f022 02c0 bic.w r2, r2, #192 @ 0xc0
8002c0c: 6969 ldr r1, [r5, #20]
8002c0e: 430a orrs r2, r1
8002c10: 62da str r2, [r3, #44] @ 0x2c
__HAL_RCC_PLL2_VCORANGE(pll2->PLL2VCOSEL) ;
8002c12: 6ada ldr r2, [r3, #44] @ 0x2c
8002c14: f022 0220 bic.w r2, r2, #32
8002c18: 69a9 ldr r1, [r5, #24]
8002c1a: 430a orrs r2, r1
8002c1c: 62da str r2, [r3, #44] @ 0x2c
__HAL_RCC_PLL2FRACN_DISABLE();
8002c1e: 6ada ldr r2, [r3, #44] @ 0x2c
8002c20: f022 0210 bic.w r2, r2, #16
8002c24: 62da str r2, [r3, #44] @ 0x2c
__HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN);
8002c26: 6bda ldr r2, [r3, #60] @ 0x3c
8002c28: f36f 02cf bfc r2, #3, #13
8002c2c: 69e9 ldr r1, [r5, #28]
8002c2e: ea42 02c1 orr.w r2, r2, r1, lsl #3
8002c32: 63da str r2, [r3, #60] @ 0x3c
__HAL_RCC_PLL2FRACN_ENABLE();
8002c34: 6ada ldr r2, [r3, #44] @ 0x2c
8002c36: f042 0210 orr.w r2, r2, #16
8002c3a: 62da str r2, [r3, #44] @ 0x2c
if (Divider == DIVIDER_P_UPDATE)
8002c3c: b9c6 cbnz r6, 8002c70 <RCCEx_PLL2_Config+0xe0>
__HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVP);
8002c3e: 461a mov r2, r3
8002c40: 6adb ldr r3, [r3, #44] @ 0x2c
8002c42: f443 2300 orr.w r3, r3, #524288 @ 0x80000
8002c46: 62d3 str r3, [r2, #44] @ 0x2c
__HAL_RCC_PLL2_ENABLE();
8002c48: 4a12 ldr r2, [pc, #72] @ (8002c94 <RCCEx_PLL2_Config+0x104>)
8002c4a: 6813 ldr r3, [r2, #0]
8002c4c: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000
8002c50: 6013 str r3, [r2, #0]
tickstart = HAL_GetTick();
8002c52: f7fd fe49 bl 80008e8 <HAL_GetTick>
8002c56: 4604 mov r4, r0
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U)
8002c58: 4b0e ldr r3, [pc, #56] @ (8002c94 <RCCEx_PLL2_Config+0x104>)
8002c5a: 681b ldr r3, [r3, #0]
8002c5c: f013 6f00 tst.w r3, #134217728 @ 0x8000000
8002c60: d114 bne.n 8002c8c <RCCEx_PLL2_Config+0xfc>
if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE)
8002c62: f7fd fe41 bl 80008e8 <HAL_GetTick>
8002c66: 1b00 subs r0, r0, r4
8002c68: 2802 cmp r0, #2
8002c6a: d9f5 bls.n 8002c58 <RCCEx_PLL2_Config+0xc8>
return HAL_TIMEOUT;
8002c6c: 2003 movs r0, #3
8002c6e: e7ab b.n 8002bc8 <RCCEx_PLL2_Config+0x38>
else if (Divider == DIVIDER_Q_UPDATE)
8002c70: 2e01 cmp r6, #1
8002c72: d005 beq.n 8002c80 <RCCEx_PLL2_Config+0xf0>
__HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVR);
8002c74: 4a07 ldr r2, [pc, #28] @ (8002c94 <RCCEx_PLL2_Config+0x104>)
8002c76: 6ad3 ldr r3, [r2, #44] @ 0x2c
8002c78: f443 1300 orr.w r3, r3, #2097152 @ 0x200000
8002c7c: 62d3 str r3, [r2, #44] @ 0x2c
8002c7e: e7e3 b.n 8002c48 <RCCEx_PLL2_Config+0xb8>
__HAL_RCC_PLL2CLKOUT_ENABLE(RCC_PLL2_DIVQ);
8002c80: 4a04 ldr r2, [pc, #16] @ (8002c94 <RCCEx_PLL2_Config+0x104>)
8002c82: 6ad3 ldr r3, [r2, #44] @ 0x2c
8002c84: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
8002c88: 62d3 str r3, [r2, #44] @ 0x2c
8002c8a: e7dd b.n 8002c48 <RCCEx_PLL2_Config+0xb8>
return status;
8002c8c: 2000 movs r0, #0
8002c8e: e79b b.n 8002bc8 <RCCEx_PLL2_Config+0x38>
return HAL_ERROR;
8002c90: 2001 movs r0, #1
}
8002c92: 4770 bx lr
8002c94: 58024400 .word 0x58024400
08002c98 <RCCEx_PLL3_Config>:
assert_param(IS_RCC_PLL3RGE_VALUE(pll3->PLL3RGE));
assert_param(IS_RCC_PLL3VCO_VALUE(pll3->PLL3VCOSEL));
assert_param(IS_RCC_PLLFRACN_VALUE(pll3->PLL3FRACN));
/* Check that PLL3 OSC clock source is already set */
if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_NONE)
8002c98: 4b40 ldr r3, [pc, #256] @ (8002d9c <RCCEx_PLL3_Config+0x104>)
8002c9a: 6a9b ldr r3, [r3, #40] @ 0x28
8002c9c: f003 0303 and.w r3, r3, #3
8002ca0: 2b03 cmp r3, #3
8002ca2: d079 beq.n 8002d98 <RCCEx_PLL3_Config+0x100>
{
8002ca4: b570 push {r4, r5, r6, lr}
8002ca6: 4605 mov r5, r0
8002ca8: 460e mov r6, r1
else
{
/* Disable PLL3. */
__HAL_RCC_PLL3_DISABLE();
8002caa: 4a3c ldr r2, [pc, #240] @ (8002d9c <RCCEx_PLL3_Config+0x104>)
8002cac: 6813 ldr r3, [r2, #0]
8002cae: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8002cb2: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8002cb4: f7fd fe18 bl 80008e8 <HAL_GetTick>
8002cb8: 4604 mov r4, r0
/* Wait till PLL3 is ready */
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U)
8002cba: 4b38 ldr r3, [pc, #224] @ (8002d9c <RCCEx_PLL3_Config+0x104>)
8002cbc: 681b ldr r3, [r3, #0]
8002cbe: f013 5f00 tst.w r3, #536870912 @ 0x20000000
8002cc2: d006 beq.n 8002cd2 <RCCEx_PLL3_Config+0x3a>
{
if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
8002cc4: f7fd fe10 bl 80008e8 <HAL_GetTick>
8002cc8: 1b03 subs r3, r0, r4
8002cca: 2b02 cmp r3, #2
8002ccc: d9f5 bls.n 8002cba <RCCEx_PLL3_Config+0x22>
{
return HAL_TIMEOUT;
8002cce: 2003 movs r0, #3
}
return status;
}
8002cd0: bd70 pop {r4, r5, r6, pc}
__HAL_RCC_PLL3_CONFIG(pll3->PLL3M,
8002cd2: 4b32 ldr r3, [pc, #200] @ (8002d9c <RCCEx_PLL3_Config+0x104>)
8002cd4: 6a9a ldr r2, [r3, #40] @ 0x28
8002cd6: f022 727c bic.w r2, r2, #66060288 @ 0x3f00000
8002cda: 6829 ldr r1, [r5, #0]
8002cdc: ea42 5201 orr.w r2, r2, r1, lsl #20
8002ce0: 629a str r2, [r3, #40] @ 0x28
8002ce2: 686a ldr r2, [r5, #4]
8002ce4: 3a01 subs r2, #1
8002ce6: f3c2 0208 ubfx r2, r2, #0, #9
8002cea: 68a9 ldr r1, [r5, #8]
8002cec: 3901 subs r1, #1
8002cee: 0249 lsls r1, r1, #9
8002cf0: b289 uxth r1, r1
8002cf2: 430a orrs r2, r1
8002cf4: 68e9 ldr r1, [r5, #12]
8002cf6: 3901 subs r1, #1
8002cf8: 0409 lsls r1, r1, #16
8002cfa: f401 01fe and.w r1, r1, #8323072 @ 0x7f0000
8002cfe: 430a orrs r2, r1
8002d00: 6929 ldr r1, [r5, #16]
8002d02: 3901 subs r1, #1
8002d04: 0609 lsls r1, r1, #24
8002d06: f001 41fe and.w r1, r1, #2130706432 @ 0x7f000000
8002d0a: 430a orrs r2, r1
8002d0c: 641a str r2, [r3, #64] @ 0x40
__HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE) ;
8002d0e: 6ada ldr r2, [r3, #44] @ 0x2c
8002d10: f422 6240 bic.w r2, r2, #3072 @ 0xc00
8002d14: 6969 ldr r1, [r5, #20]
8002d16: 430a orrs r2, r1
8002d18: 62da str r2, [r3, #44] @ 0x2c
__HAL_RCC_PLL3_VCORANGE(pll3->PLL3VCOSEL) ;
8002d1a: 6ada ldr r2, [r3, #44] @ 0x2c
8002d1c: f422 7200 bic.w r2, r2, #512 @ 0x200
8002d20: 69a9 ldr r1, [r5, #24]
8002d22: 430a orrs r2, r1
8002d24: 62da str r2, [r3, #44] @ 0x2c
__HAL_RCC_PLL3FRACN_DISABLE();
8002d26: 6ada ldr r2, [r3, #44] @ 0x2c
8002d28: f422 7280 bic.w r2, r2, #256 @ 0x100
8002d2c: 62da str r2, [r3, #44] @ 0x2c
__HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN);
8002d2e: 6c5a ldr r2, [r3, #68] @ 0x44
8002d30: f36f 02cf bfc r2, #3, #13
8002d34: 69e9 ldr r1, [r5, #28]
8002d36: ea42 02c1 orr.w r2, r2, r1, lsl #3
8002d3a: 645a str r2, [r3, #68] @ 0x44
__HAL_RCC_PLL3FRACN_ENABLE();
8002d3c: 6ada ldr r2, [r3, #44] @ 0x2c
8002d3e: f442 7280 orr.w r2, r2, #256 @ 0x100
8002d42: 62da str r2, [r3, #44] @ 0x2c
if (Divider == DIVIDER_P_UPDATE)
8002d44: b9c6 cbnz r6, 8002d78 <RCCEx_PLL3_Config+0xe0>
__HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVP);
8002d46: 461a mov r2, r3
8002d48: 6adb ldr r3, [r3, #44] @ 0x2c
8002d4a: f443 0380 orr.w r3, r3, #4194304 @ 0x400000
8002d4e: 62d3 str r3, [r2, #44] @ 0x2c
__HAL_RCC_PLL3_ENABLE();
8002d50: 4a12 ldr r2, [pc, #72] @ (8002d9c <RCCEx_PLL3_Config+0x104>)
8002d52: 6813 ldr r3, [r2, #0]
8002d54: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8002d58: 6013 str r3, [r2, #0]
tickstart = HAL_GetTick();
8002d5a: f7fd fdc5 bl 80008e8 <HAL_GetTick>
8002d5e: 4604 mov r4, r0
while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U)
8002d60: 4b0e ldr r3, [pc, #56] @ (8002d9c <RCCEx_PLL3_Config+0x104>)
8002d62: 681b ldr r3, [r3, #0]
8002d64: f013 5f00 tst.w r3, #536870912 @ 0x20000000
8002d68: d114 bne.n 8002d94 <RCCEx_PLL3_Config+0xfc>
if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE)
8002d6a: f7fd fdbd bl 80008e8 <HAL_GetTick>
8002d6e: 1b00 subs r0, r0, r4
8002d70: 2802 cmp r0, #2
8002d72: d9f5 bls.n 8002d60 <RCCEx_PLL3_Config+0xc8>
return HAL_TIMEOUT;
8002d74: 2003 movs r0, #3
8002d76: e7ab b.n 8002cd0 <RCCEx_PLL3_Config+0x38>
else if (Divider == DIVIDER_Q_UPDATE)
8002d78: 2e01 cmp r6, #1
8002d7a: d005 beq.n 8002d88 <RCCEx_PLL3_Config+0xf0>
__HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVR);
8002d7c: 4a07 ldr r2, [pc, #28] @ (8002d9c <RCCEx_PLL3_Config+0x104>)
8002d7e: 6ad3 ldr r3, [r2, #44] @ 0x2c
8002d80: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
8002d84: 62d3 str r3, [r2, #44] @ 0x2c
8002d86: e7e3 b.n 8002d50 <RCCEx_PLL3_Config+0xb8>
__HAL_RCC_PLL3CLKOUT_ENABLE(RCC_PLL3_DIVQ);
8002d88: 4a04 ldr r2, [pc, #16] @ (8002d9c <RCCEx_PLL3_Config+0x104>)
8002d8a: 6ad3 ldr r3, [r2, #44] @ 0x2c
8002d8c: f443 0300 orr.w r3, r3, #8388608 @ 0x800000
8002d90: 62d3 str r3, [r2, #44] @ 0x2c
8002d92: e7dd b.n 8002d50 <RCCEx_PLL3_Config+0xb8>
return status;
8002d94: 2000 movs r0, #0
8002d96: e79b b.n 8002cd0 <RCCEx_PLL3_Config+0x38>
return HAL_ERROR;
8002d98: 2001 movs r0, #1
}
8002d9a: 4770 bx lr
8002d9c: 58024400 .word 0x58024400
08002da0 <HAL_RCCEx_PeriphCLKConfig>:
{
8002da0: b5f8 push {r3, r4, r5, r6, r7, lr}
8002da2: 4604 mov r4, r0
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
8002da4: 6803 ldr r3, [r0, #0]
8002da6: f013 6f00 tst.w r3, #134217728 @ 0x8000000
8002daa: d030 beq.n 8002e0e <HAL_RCCEx_PeriphCLKConfig+0x6e>
switch (PeriphClkInit->SpdifrxClockSelection)
8002dac: 6ec3 ldr r3, [r0, #108] @ 0x6c
8002dae: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000
8002db2: d026 beq.n 8002e02 <HAL_RCCEx_PeriphCLKConfig+0x62>
8002db4: d80e bhi.n 8002dd4 <HAL_RCCEx_PeriphCLKConfig+0x34>
8002db6: b1ab cbz r3, 8002de4 <HAL_RCCEx_PeriphCLKConfig+0x44>
8002db8: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
8002dbc: d107 bne.n 8002dce <HAL_RCCEx_PeriphCLKConfig+0x2e>
ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE);
8002dbe: 2102 movs r1, #2
8002dc0: 3008 adds r0, #8
8002dc2: f7ff fee5 bl 8002b90 <RCCEx_PLL2_Config>
8002dc6: 4605 mov r5, r0
if (ret == HAL_OK)
8002dc8: b195 cbz r5, 8002df0 <HAL_RCCEx_PeriphCLKConfig+0x50>
status = ret;
8002dca: 462e mov r6, r5
8002dcc: e021 b.n 8002e12 <HAL_RCCEx_PeriphCLKConfig+0x72>
switch (PeriphClkInit->SpdifrxClockSelection)
8002dce: 2601 movs r6, #1
8002dd0: 4635 mov r5, r6
8002dd2: e01e b.n 8002e12 <HAL_RCCEx_PeriphCLKConfig+0x72>
8002dd4: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000
8002dd8: d101 bne.n 8002dde <HAL_RCCEx_PeriphCLKConfig+0x3e>
8002dda: 2500 movs r5, #0
8002ddc: e008 b.n 8002df0 <HAL_RCCEx_PeriphCLKConfig+0x50>
8002dde: 2601 movs r6, #1
8002de0: 4635 mov r5, r6
8002de2: e016 b.n 8002e12 <HAL_RCCEx_PeriphCLKConfig+0x72>
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
8002de4: 4a97 ldr r2, [pc, #604] @ (8003044 <HAL_RCCEx_PeriphCLKConfig+0x2a4>)
8002de6: 6ad3 ldr r3, [r2, #44] @ 0x2c
8002de8: f443 3300 orr.w r3, r3, #131072 @ 0x20000
8002dec: 62d3 str r3, [r2, #44] @ 0x2c
HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
8002dee: 2500 movs r5, #0
__HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifrxClockSelection);
8002df0: 4a94 ldr r2, [pc, #592] @ (8003044 <HAL_RCCEx_PeriphCLKConfig+0x2a4>)
8002df2: 6d13 ldr r3, [r2, #80] @ 0x50
8002df4: f423 1340 bic.w r3, r3, #3145728 @ 0x300000
8002df8: 6ee1 ldr r1, [r4, #108] @ 0x6c
8002dfa: 430b orrs r3, r1
8002dfc: 6513 str r3, [r2, #80] @ 0x50
HAL_StatusTypeDef status = HAL_OK; /* Final status */
8002dfe: 2600 movs r6, #0
8002e00: e007 b.n 8002e12 <HAL_RCCEx_PeriphCLKConfig+0x72>
ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE);
8002e02: 2102 movs r1, #2
8002e04: 3028 adds r0, #40 @ 0x28
8002e06: f7ff ff47 bl 8002c98 <RCCEx_PLL3_Config>
8002e0a: 4605 mov r5, r0
break;
8002e0c: e7dc b.n 8002dc8 <HAL_RCCEx_PeriphCLKConfig+0x28>
HAL_StatusTypeDef status = HAL_OK; /* Final status */
8002e0e: 2600 movs r6, #0
HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
8002e10: 4635 mov r5, r6
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
8002e12: 6823 ldr r3, [r4, #0]
8002e14: f413 7f80 tst.w r3, #256 @ 0x100
8002e18: d014 beq.n 8002e44 <HAL_RCCEx_PeriphCLKConfig+0xa4>
switch (PeriphClkInit->Sai1ClockSelection)
8002e1a: 6da3 ldr r3, [r4, #88] @ 0x58
8002e1c: 2b04 cmp r3, #4
8002e1e: d831 bhi.n 8002e84 <HAL_RCCEx_PeriphCLKConfig+0xe4>
8002e20: e8df f003 tbb [pc, r3]
8002e24: 08292203 .word 0x08292203
8002e28: 08 .byte 0x08
8002e29: 00 .byte 0x00
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
8002e2a: 4a86 ldr r2, [pc, #536] @ (8003044 <HAL_RCCEx_PeriphCLKConfig+0x2a4>)
8002e2c: 6ad3 ldr r3, [r2, #44] @ 0x2c
8002e2e: f443 3300 orr.w r3, r3, #131072 @ 0x20000
8002e32: 62d3 str r3, [r2, #44] @ 0x2c
if (ret == HAL_OK)
8002e34: bb4d cbnz r5, 8002e8a <HAL_RCCEx_PeriphCLKConfig+0xea>
__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
8002e36: 4a83 ldr r2, [pc, #524] @ (8003044 <HAL_RCCEx_PeriphCLKConfig+0x2a4>)
8002e38: 6d13 ldr r3, [r2, #80] @ 0x50
8002e3a: f023 0307 bic.w r3, r3, #7
8002e3e: 6da1 ldr r1, [r4, #88] @ 0x58
8002e40: 430b orrs r3, r1
8002e42: 6513 str r3, [r2, #80] @ 0x50
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2A) == RCC_PERIPHCLK_SAI2A)
8002e44: 6823 ldr r3, [r4, #0]
8002e46: f413 7f00 tst.w r3, #512 @ 0x200
8002e4a: d042 beq.n 8002ed2 <HAL_RCCEx_PeriphCLKConfig+0x132>
switch (PeriphClkInit->Sai2AClockSelection)
8002e4c: 6de3 ldr r3, [r4, #92] @ 0x5c
8002e4e: 2b80 cmp r3, #128 @ 0x80
8002e50: d031 beq.n 8002eb6 <HAL_RCCEx_PeriphCLKConfig+0x116>
8002e52: d81f bhi.n 8002e94 <HAL_RCCEx_PeriphCLKConfig+0xf4>
8002e54: b34b cbz r3, 8002eaa <HAL_RCCEx_PeriphCLKConfig+0x10a>
8002e56: 2b40 cmp r3, #64 @ 0x40
8002e58: d119 bne.n 8002e8e <HAL_RCCEx_PeriphCLKConfig+0xee>
ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
8002e5a: 2100 movs r1, #0
8002e5c: f104 0008 add.w r0, r4, #8
8002e60: f7ff fe96 bl 8002b90 <RCCEx_PLL2_Config>
8002e64: 4605 mov r5, r0
break;
8002e66: e02c b.n 8002ec2 <HAL_RCCEx_PeriphCLKConfig+0x122>
ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
8002e68: 2100 movs r1, #0
8002e6a: f104 0008 add.w r0, r4, #8
8002e6e: f7ff fe8f bl 8002b90 <RCCEx_PLL2_Config>
8002e72: 4605 mov r5, r0
break;
8002e74: e7de b.n 8002e34 <HAL_RCCEx_PeriphCLKConfig+0x94>
ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
8002e76: 2100 movs r1, #0
8002e78: f104 0028 add.w r0, r4, #40 @ 0x28
8002e7c: f7ff ff0c bl 8002c98 <RCCEx_PLL3_Config>
8002e80: 4605 mov r5, r0
break;
8002e82: e7d7 b.n 8002e34 <HAL_RCCEx_PeriphCLKConfig+0x94>
switch (PeriphClkInit->Sai1ClockSelection)
8002e84: 2601 movs r6, #1
8002e86: 4635 mov r5, r6
8002e88: e7dc b.n 8002e44 <HAL_RCCEx_PeriphCLKConfig+0xa4>
status = ret;
8002e8a: 462e mov r6, r5
8002e8c: e7da b.n 8002e44 <HAL_RCCEx_PeriphCLKConfig+0xa4>
switch (PeriphClkInit->Sai2AClockSelection)
8002e8e: 2601 movs r6, #1
8002e90: 4635 mov r5, r6
8002e92: e01e b.n 8002ed2 <HAL_RCCEx_PeriphCLKConfig+0x132>
8002e94: f5b3 7f80 cmp.w r3, #256 @ 0x100
8002e98: d013 beq.n 8002ec2 <HAL_RCCEx_PeriphCLKConfig+0x122>
8002e9a: f5b3 7fa0 cmp.w r3, #320 @ 0x140
8002e9e: d010 beq.n 8002ec2 <HAL_RCCEx_PeriphCLKConfig+0x122>
8002ea0: 2bc0 cmp r3, #192 @ 0xc0
8002ea2: d00e beq.n 8002ec2 <HAL_RCCEx_PeriphCLKConfig+0x122>
8002ea4: 2601 movs r6, #1
8002ea6: 4635 mov r5, r6
8002ea8: e013 b.n 8002ed2 <HAL_RCCEx_PeriphCLKConfig+0x132>
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
8002eaa: 4a66 ldr r2, [pc, #408] @ (8003044 <HAL_RCCEx_PeriphCLKConfig+0x2a4>)
8002eac: 6ad3 ldr r3, [r2, #44] @ 0x2c
8002eae: f443 3300 orr.w r3, r3, #131072 @ 0x20000
8002eb2: 62d3 str r3, [r2, #44] @ 0x2c
break;
8002eb4: e005 b.n 8002ec2 <HAL_RCCEx_PeriphCLKConfig+0x122>
ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
8002eb6: 2100 movs r1, #0
8002eb8: f104 0028 add.w r0, r4, #40 @ 0x28
8002ebc: f7ff feec bl 8002c98 <RCCEx_PLL3_Config>
8002ec0: 4605 mov r5, r0
if (ret == HAL_OK)
8002ec2: b9d5 cbnz r5, 8002efa <HAL_RCCEx_PeriphCLKConfig+0x15a>
__HAL_RCC_SAI2A_CONFIG(PeriphClkInit->Sai2AClockSelection);
8002ec4: 4a5f ldr r2, [pc, #380] @ (8003044 <HAL_RCCEx_PeriphCLKConfig+0x2a4>)
8002ec6: 6d13 ldr r3, [r2, #80] @ 0x50
8002ec8: f423 73e0 bic.w r3, r3, #448 @ 0x1c0
8002ecc: 6de1 ldr r1, [r4, #92] @ 0x5c
8002ece: 430b orrs r3, r1
8002ed0: 6513 str r3, [r2, #80] @ 0x50
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2B) == RCC_PERIPHCLK_SAI2B)
8002ed2: 6823 ldr r3, [r4, #0]
8002ed4: f413 6f80 tst.w r3, #1024 @ 0x400
8002ed8: d034 beq.n 8002f44 <HAL_RCCEx_PeriphCLKConfig+0x1a4>
switch (PeriphClkInit->Sai2BClockSelection)
8002eda: 6e23 ldr r3, [r4, #96] @ 0x60
8002edc: f5b3 6f80 cmp.w r3, #1024 @ 0x400
8002ee0: d022 beq.n 8002f28 <HAL_RCCEx_PeriphCLKConfig+0x188>
8002ee2: d80f bhi.n 8002f04 <HAL_RCCEx_PeriphCLKConfig+0x164>
8002ee4: b1d3 cbz r3, 8002f1c <HAL_RCCEx_PeriphCLKConfig+0x17c>
8002ee6: f5b3 7f00 cmp.w r3, #512 @ 0x200
8002eea: d108 bne.n 8002efe <HAL_RCCEx_PeriphCLKConfig+0x15e>
ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
8002eec: 2100 movs r1, #0
8002eee: f104 0008 add.w r0, r4, #8
8002ef2: f7ff fe4d bl 8002b90 <RCCEx_PLL2_Config>
8002ef6: 4605 mov r5, r0
break;
8002ef8: e01c b.n 8002f34 <HAL_RCCEx_PeriphCLKConfig+0x194>
status = ret;
8002efa: 462e mov r6, r5
8002efc: e7e9 b.n 8002ed2 <HAL_RCCEx_PeriphCLKConfig+0x132>
switch (PeriphClkInit->Sai2BClockSelection)
8002efe: 2601 movs r6, #1
8002f00: 4635 mov r5, r6
8002f02: e01f b.n 8002f44 <HAL_RCCEx_PeriphCLKConfig+0x1a4>
8002f04: f5b3 6f00 cmp.w r3, #2048 @ 0x800
8002f08: d014 beq.n 8002f34 <HAL_RCCEx_PeriphCLKConfig+0x194>
8002f0a: f5b3 6f20 cmp.w r3, #2560 @ 0xa00
8002f0e: d011 beq.n 8002f34 <HAL_RCCEx_PeriphCLKConfig+0x194>
8002f10: f5b3 6fc0 cmp.w r3, #1536 @ 0x600
8002f14: d00e beq.n 8002f34 <HAL_RCCEx_PeriphCLKConfig+0x194>
8002f16: 2601 movs r6, #1
8002f18: 4635 mov r5, r6
8002f1a: e013 b.n 8002f44 <HAL_RCCEx_PeriphCLKConfig+0x1a4>
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
8002f1c: 4a49 ldr r2, [pc, #292] @ (8003044 <HAL_RCCEx_PeriphCLKConfig+0x2a4>)
8002f1e: 6ad3 ldr r3, [r2, #44] @ 0x2c
8002f20: f443 3300 orr.w r3, r3, #131072 @ 0x20000
8002f24: 62d3 str r3, [r2, #44] @ 0x2c
break;
8002f26: e005 b.n 8002f34 <HAL_RCCEx_PeriphCLKConfig+0x194>
ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
8002f28: 2100 movs r1, #0
8002f2a: f104 0028 add.w r0, r4, #40 @ 0x28
8002f2e: f7ff feb3 bl 8002c98 <RCCEx_PLL3_Config>
8002f32: 4605 mov r5, r0
if (ret == HAL_OK)
8002f34: b9bd cbnz r5, 8002f66 <HAL_RCCEx_PeriphCLKConfig+0x1c6>
__HAL_RCC_SAI2B_CONFIG(PeriphClkInit->Sai2BClockSelection);
8002f36: 4a43 ldr r2, [pc, #268] @ (8003044 <HAL_RCCEx_PeriphCLKConfig+0x2a4>)
8002f38: 6d13 ldr r3, [r2, #80] @ 0x50
8002f3a: f423 6360 bic.w r3, r3, #3584 @ 0xe00
8002f3e: 6e21 ldr r1, [r4, #96] @ 0x60
8002f40: 430b orrs r3, r1
8002f42: 6513 str r3, [r2, #80] @ 0x50
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI)
8002f44: 6823 ldr r3, [r4, #0]
8002f46: f013 7f00 tst.w r3, #33554432 @ 0x2000000
8002f4a: d024 beq.n 8002f96 <HAL_RCCEx_PeriphCLKConfig+0x1f6>
switch (PeriphClkInit->OspiClockSelection)
8002f4c: 6ce3 ldr r3, [r4, #76] @ 0x4c
8002f4e: 2b20 cmp r3, #32
8002f50: d013 beq.n 8002f7a <HAL_RCCEx_PeriphCLKConfig+0x1da>
8002f52: d80d bhi.n 8002f70 <HAL_RCCEx_PeriphCLKConfig+0x1d0>
8002f54: b1bb cbz r3, 8002f86 <HAL_RCCEx_PeriphCLKConfig+0x1e6>
8002f56: 2b10 cmp r3, #16
8002f58: d107 bne.n 8002f6a <HAL_RCCEx_PeriphCLKConfig+0x1ca>
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
8002f5a: 4a3a ldr r2, [pc, #232] @ (8003044 <HAL_RCCEx_PeriphCLKConfig+0x2a4>)
8002f5c: 6ad3 ldr r3, [r2, #44] @ 0x2c
8002f5e: f443 3300 orr.w r3, r3, #131072 @ 0x20000
8002f62: 62d3 str r3, [r2, #44] @ 0x2c
break;
8002f64: e00f b.n 8002f86 <HAL_RCCEx_PeriphCLKConfig+0x1e6>
status = ret;
8002f66: 462e mov r6, r5
8002f68: e7ec b.n 8002f44 <HAL_RCCEx_PeriphCLKConfig+0x1a4>
switch (PeriphClkInit->OspiClockSelection)
8002f6a: 2601 movs r6, #1
8002f6c: 4635 mov r5, r6
8002f6e: e012 b.n 8002f96 <HAL_RCCEx_PeriphCLKConfig+0x1f6>
8002f70: 2b30 cmp r3, #48 @ 0x30
8002f72: d008 beq.n 8002f86 <HAL_RCCEx_PeriphCLKConfig+0x1e6>
8002f74: 2601 movs r6, #1
8002f76: 4635 mov r5, r6
8002f78: e00d b.n 8002f96 <HAL_RCCEx_PeriphCLKConfig+0x1f6>
ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE);
8002f7a: 2102 movs r1, #2
8002f7c: f104 0008 add.w r0, r4, #8
8002f80: f7ff fe06 bl 8002b90 <RCCEx_PLL2_Config>
8002f84: 4605 mov r5, r0
if (ret == HAL_OK)
8002f86: b9d5 cbnz r5, 8002fbe <HAL_RCCEx_PeriphCLKConfig+0x21e>
__HAL_RCC_OSPI_CONFIG(PeriphClkInit->OspiClockSelection);
8002f88: 4a2e ldr r2, [pc, #184] @ (8003044 <HAL_RCCEx_PeriphCLKConfig+0x2a4>)
8002f8a: 6cd3 ldr r3, [r2, #76] @ 0x4c
8002f8c: f023 0330 bic.w r3, r3, #48 @ 0x30
8002f90: 6ce1 ldr r1, [r4, #76] @ 0x4c
8002f92: 430b orrs r3, r1
8002f94: 64d3 str r3, [r2, #76] @ 0x4c
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI123) == RCC_PERIPHCLK_SPI123)
8002f96: 6823 ldr r3, [r4, #0]
8002f98: f413 5f80 tst.w r3, #4096 @ 0x1000
8002f9c: d031 beq.n 8003002 <HAL_RCCEx_PeriphCLKConfig+0x262>
switch (PeriphClkInit->Spi123ClockSelection)
8002f9e: 6e63 ldr r3, [r4, #100] @ 0x64
8002fa0: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
8002fa4: d01f beq.n 8002fe6 <HAL_RCCEx_PeriphCLKConfig+0x246>
8002fa6: d80f bhi.n 8002fc8 <HAL_RCCEx_PeriphCLKConfig+0x228>
8002fa8: b1bb cbz r3, 8002fda <HAL_RCCEx_PeriphCLKConfig+0x23a>
8002faa: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
8002fae: d108 bne.n 8002fc2 <HAL_RCCEx_PeriphCLKConfig+0x222>
ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
8002fb0: 2100 movs r1, #0
8002fb2: f104 0008 add.w r0, r4, #8
8002fb6: f7ff fdeb bl 8002b90 <RCCEx_PLL2_Config>
8002fba: 4605 mov r5, r0
break;
8002fbc: e019 b.n 8002ff2 <HAL_RCCEx_PeriphCLKConfig+0x252>
status = ret;
8002fbe: 462e mov r6, r5
8002fc0: e7e9 b.n 8002f96 <HAL_RCCEx_PeriphCLKConfig+0x1f6>
switch (PeriphClkInit->Spi123ClockSelection)
8002fc2: 2601 movs r6, #1
8002fc4: 4635 mov r5, r6
8002fc6: e01c b.n 8003002 <HAL_RCCEx_PeriphCLKConfig+0x262>
8002fc8: f5b3 5f40 cmp.w r3, #12288 @ 0x3000
8002fcc: d011 beq.n 8002ff2 <HAL_RCCEx_PeriphCLKConfig+0x252>
8002fce: f5b3 4f80 cmp.w r3, #16384 @ 0x4000
8002fd2: d00e beq.n 8002ff2 <HAL_RCCEx_PeriphCLKConfig+0x252>
8002fd4: 2601 movs r6, #1
8002fd6: 4635 mov r5, r6
8002fd8: e013 b.n 8003002 <HAL_RCCEx_PeriphCLKConfig+0x262>
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
8002fda: 4a1a ldr r2, [pc, #104] @ (8003044 <HAL_RCCEx_PeriphCLKConfig+0x2a4>)
8002fdc: 6ad3 ldr r3, [r2, #44] @ 0x2c
8002fde: f443 3300 orr.w r3, r3, #131072 @ 0x20000
8002fe2: 62d3 str r3, [r2, #44] @ 0x2c
break;
8002fe4: e005 b.n 8002ff2 <HAL_RCCEx_PeriphCLKConfig+0x252>
ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
8002fe6: 2100 movs r1, #0
8002fe8: f104 0028 add.w r0, r4, #40 @ 0x28
8002fec: f7ff fe54 bl 8002c98 <RCCEx_PLL3_Config>
8002ff0: 4605 mov r5, r0
if (ret == HAL_OK)
8002ff2: bb15 cbnz r5, 800303a <HAL_RCCEx_PeriphCLKConfig+0x29a>
__HAL_RCC_SPI123_CONFIG(PeriphClkInit->Spi123ClockSelection);
8002ff4: 4a13 ldr r2, [pc, #76] @ (8003044 <HAL_RCCEx_PeriphCLKConfig+0x2a4>)
8002ff6: 6d13 ldr r3, [r2, #80] @ 0x50
8002ff8: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8002ffc: 6e61 ldr r1, [r4, #100] @ 0x64
8002ffe: 430b orrs r3, r1
8003000: 6513 str r3, [r2, #80] @ 0x50
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI45) == RCC_PERIPHCLK_SPI45)
8003002: 6823 ldr r3, [r4, #0]
8003004: f413 5f00 tst.w r3, #8192 @ 0x2000
8003008: d032 beq.n 8003070 <HAL_RCCEx_PeriphCLKConfig+0x2d0>
switch (PeriphClkInit->Spi45ClockSelection)
800300a: 6ea3 ldr r3, [r4, #104] @ 0x68
800300c: f5b3 3f00 cmp.w r3, #131072 @ 0x20000
8003010: d026 beq.n 8003060 <HAL_RCCEx_PeriphCLKConfig+0x2c0>
8003012: d819 bhi.n 8003048 <HAL_RCCEx_PeriphCLKConfig+0x2a8>
8003014: b143 cbz r3, 8003028 <HAL_RCCEx_PeriphCLKConfig+0x288>
8003016: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
800301a: d110 bne.n 800303e <HAL_RCCEx_PeriphCLKConfig+0x29e>
ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
800301c: 2101 movs r1, #1
800301e: f104 0008 add.w r0, r4, #8
8003022: f7ff fdb5 bl 8002b90 <RCCEx_PLL2_Config>
8003026: 4605 mov r5, r0
if (ret == HAL_OK)
8003028: bb0d cbnz r5, 800306e <HAL_RCCEx_PeriphCLKConfig+0x2ce>
__HAL_RCC_SPI45_CONFIG(PeriphClkInit->Spi45ClockSelection);
800302a: 4a06 ldr r2, [pc, #24] @ (8003044 <HAL_RCCEx_PeriphCLKConfig+0x2a4>)
800302c: 6d13 ldr r3, [r2, #80] @ 0x50
800302e: f423 23e0 bic.w r3, r3, #458752 @ 0x70000
8003032: 6ea1 ldr r1, [r4, #104] @ 0x68
8003034: 430b orrs r3, r1
8003036: 6513 str r3, [r2, #80] @ 0x50
8003038: e01a b.n 8003070 <HAL_RCCEx_PeriphCLKConfig+0x2d0>
status = ret;
800303a: 462e mov r6, r5
800303c: e7e1 b.n 8003002 <HAL_RCCEx_PeriphCLKConfig+0x262>
switch (PeriphClkInit->Spi45ClockSelection)
800303e: 2601 movs r6, #1
8003040: 4635 mov r5, r6
8003042: e015 b.n 8003070 <HAL_RCCEx_PeriphCLKConfig+0x2d0>
8003044: 58024400 .word 0x58024400
8003048: f5b3 2f80 cmp.w r3, #262144 @ 0x40000
800304c: d0ec beq.n 8003028 <HAL_RCCEx_PeriphCLKConfig+0x288>
800304e: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
8003052: d0e9 beq.n 8003028 <HAL_RCCEx_PeriphCLKConfig+0x288>
8003054: f5b3 3f40 cmp.w r3, #196608 @ 0x30000
8003058: d0e6 beq.n 8003028 <HAL_RCCEx_PeriphCLKConfig+0x288>
800305a: 2601 movs r6, #1
800305c: 4635 mov r5, r6
800305e: e007 b.n 8003070 <HAL_RCCEx_PeriphCLKConfig+0x2d0>
ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
8003060: 2101 movs r1, #1
8003062: f104 0028 add.w r0, r4, #40 @ 0x28
8003066: f7ff fe17 bl 8002c98 <RCCEx_PLL3_Config>
800306a: 4605 mov r5, r0
break;
800306c: e7dc b.n 8003028 <HAL_RCCEx_PeriphCLKConfig+0x288>
status = ret;
800306e: 462e mov r6, r5
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI6) == RCC_PERIPHCLK_SPI6)
8003070: 6823 ldr r3, [r4, #0]
8003072: f413 4f80 tst.w r3, #16384 @ 0x4000
8003076: d018 beq.n 80030aa <HAL_RCCEx_PeriphCLKConfig+0x30a>
switch (PeriphClkInit->Spi6ClockSelection)
8003078: f8d4 30b0 ldr.w r3, [r4, #176] @ 0xb0
800307c: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
8003080: d038 beq.n 80030f4 <HAL_RCCEx_PeriphCLKConfig+0x354>
8003082: d824 bhi.n 80030ce <HAL_RCCEx_PeriphCLKConfig+0x32e>
8003084: b143 cbz r3, 8003098 <HAL_RCCEx_PeriphCLKConfig+0x2f8>
8003086: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
800308a: d11d bne.n 80030c8 <HAL_RCCEx_PeriphCLKConfig+0x328>
ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
800308c: 2101 movs r1, #1
800308e: f104 0008 add.w r0, r4, #8
8003092: f7ff fd7d bl 8002b90 <RCCEx_PLL2_Config>
8003096: 4605 mov r5, r0
if (ret == HAL_OK)
8003098: bb9d cbnz r5, 8003102 <HAL_RCCEx_PeriphCLKConfig+0x362>
__HAL_RCC_SPI6_CONFIG(PeriphClkInit->Spi6ClockSelection);
800309a: 4a90 ldr r2, [pc, #576] @ (80032dc <HAL_RCCEx_PeriphCLKConfig+0x53c>)
800309c: 6d93 ldr r3, [r2, #88] @ 0x58
800309e: f023 43e0 bic.w r3, r3, #1879048192 @ 0x70000000
80030a2: f8d4 10b0 ldr.w r1, [r4, #176] @ 0xb0
80030a6: 430b orrs r3, r1
80030a8: 6593 str r3, [r2, #88] @ 0x58
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN)
80030aa: 6823 ldr r3, [r4, #0]
80030ac: f413 4f00 tst.w r3, #32768 @ 0x8000
80030b0: d03f beq.n 8003132 <HAL_RCCEx_PeriphCLKConfig+0x392>
switch (PeriphClkInit->FdcanClockSelection)
80030b2: 6fa3 ldr r3, [r4, #120] @ 0x78
80030b4: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
80030b8: d025 beq.n 8003106 <HAL_RCCEx_PeriphCLKConfig+0x366>
80030ba: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
80030be: d030 beq.n 8003122 <HAL_RCCEx_PeriphCLKConfig+0x382>
80030c0: b333 cbz r3, 8003110 <HAL_RCCEx_PeriphCLKConfig+0x370>
80030c2: 2601 movs r6, #1
80030c4: 4635 mov r5, r6
80030c6: e034 b.n 8003132 <HAL_RCCEx_PeriphCLKConfig+0x392>
switch (PeriphClkInit->Spi6ClockSelection)
80030c8: 2601 movs r6, #1
80030ca: 4635 mov r5, r6
80030cc: e7ed b.n 80030aa <HAL_RCCEx_PeriphCLKConfig+0x30a>
80030ce: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
80030d2: d0e1 beq.n 8003098 <HAL_RCCEx_PeriphCLKConfig+0x2f8>
80030d4: d808 bhi.n 80030e8 <HAL_RCCEx_PeriphCLKConfig+0x348>
80030d6: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000
80030da: d0dd beq.n 8003098 <HAL_RCCEx_PeriphCLKConfig+0x2f8>
80030dc: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
80030e0: d0da beq.n 8003098 <HAL_RCCEx_PeriphCLKConfig+0x2f8>
80030e2: 2601 movs r6, #1
80030e4: 4635 mov r5, r6
80030e6: e7e0 b.n 80030aa <HAL_RCCEx_PeriphCLKConfig+0x30a>
80030e8: f1b3 4fc0 cmp.w r3, #1610612736 @ 0x60000000
80030ec: d0d4 beq.n 8003098 <HAL_RCCEx_PeriphCLKConfig+0x2f8>
80030ee: 2601 movs r6, #1
80030f0: 4635 mov r5, r6
80030f2: e7da b.n 80030aa <HAL_RCCEx_PeriphCLKConfig+0x30a>
ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
80030f4: 2101 movs r1, #1
80030f6: f104 0028 add.w r0, r4, #40 @ 0x28
80030fa: f7ff fdcd bl 8002c98 <RCCEx_PLL3_Config>
80030fe: 4605 mov r5, r0
break;
8003100: e7ca b.n 8003098 <HAL_RCCEx_PeriphCLKConfig+0x2f8>
status = ret;
8003102: 462e mov r6, r5
8003104: e7d1 b.n 80030aa <HAL_RCCEx_PeriphCLKConfig+0x30a>
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
8003106: 4a75 ldr r2, [pc, #468] @ (80032dc <HAL_RCCEx_PeriphCLKConfig+0x53c>)
8003108: 6ad3 ldr r3, [r2, #44] @ 0x2c
800310a: f443 3300 orr.w r3, r3, #131072 @ 0x20000
800310e: 62d3 str r3, [r2, #44] @ 0x2c
if (ret == HAL_OK)
8003110: b975 cbnz r5, 8003130 <HAL_RCCEx_PeriphCLKConfig+0x390>
__HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection);
8003112: 4a72 ldr r2, [pc, #456] @ (80032dc <HAL_RCCEx_PeriphCLKConfig+0x53c>)
8003114: 6d13 ldr r3, [r2, #80] @ 0x50
8003116: f023 5340 bic.w r3, r3, #805306368 @ 0x30000000
800311a: 6fa1 ldr r1, [r4, #120] @ 0x78
800311c: 430b orrs r3, r1
800311e: 6513 str r3, [r2, #80] @ 0x50
8003120: e007 b.n 8003132 <HAL_RCCEx_PeriphCLKConfig+0x392>
ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
8003122: 2101 movs r1, #1
8003124: f104 0008 add.w r0, r4, #8
8003128: f7ff fd32 bl 8002b90 <RCCEx_PLL2_Config>
800312c: 4605 mov r5, r0
break;
800312e: e7ef b.n 8003110 <HAL_RCCEx_PeriphCLKConfig+0x370>
status = ret;
8003130: 462e mov r6, r5
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMC) == RCC_PERIPHCLK_FMC)
8003132: 6823 ldr r3, [r4, #0]
8003134: f013 7f80 tst.w r3, #16777216 @ 0x1000000
8003138: d013 beq.n 8003162 <HAL_RCCEx_PeriphCLKConfig+0x3c2>
switch (PeriphClkInit->FmcClockSelection)
800313a: 6ca3 ldr r3, [r4, #72] @ 0x48
800313c: 2b03 cmp r3, #3
800313e: d83c bhi.n 80031ba <HAL_RCCEx_PeriphCLKConfig+0x41a>
8003140: e8df f003 tbb [pc, r3]
8003144: 07340207 .word 0x07340207
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
8003148: 4a64 ldr r2, [pc, #400] @ (80032dc <HAL_RCCEx_PeriphCLKConfig+0x53c>)
800314a: 6ad3 ldr r3, [r2, #44] @ 0x2c
800314c: f443 3300 orr.w r3, r3, #131072 @ 0x20000
8003150: 62d3 str r3, [r2, #44] @ 0x2c
if (ret == HAL_OK)
8003152: bbad cbnz r5, 80031c0 <HAL_RCCEx_PeriphCLKConfig+0x420>
__HAL_RCC_FMC_CONFIG(PeriphClkInit->FmcClockSelection);
8003154: 4a61 ldr r2, [pc, #388] @ (80032dc <HAL_RCCEx_PeriphCLKConfig+0x53c>)
8003156: 6cd3 ldr r3, [r2, #76] @ 0x4c
8003158: f023 0303 bic.w r3, r3, #3
800315c: 6ca1 ldr r1, [r4, #72] @ 0x48
800315e: 430b orrs r3, r1
8003160: 64d3 str r3, [r2, #76] @ 0x4c
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
8003162: 6823 ldr r3, [r4, #0]
8003164: f413 0f80 tst.w r3, #4194304 @ 0x400000
8003168: d12c bne.n 80031c4 <HAL_RCCEx_PeriphCLKConfig+0x424>
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART16) == RCC_PERIPHCLK_USART16)
800316a: 6823 ldr r3, [r4, #0]
800316c: f013 0f01 tst.w r3, #1
8003170: f000 80a5 beq.w 80032be <HAL_RCCEx_PeriphCLKConfig+0x51e>
switch (PeriphClkInit->Usart16ClockSelection)
8003174: f8d4 3084 ldr.w r3, [r4, #132] @ 0x84
8003178: 2b28 cmp r3, #40 @ 0x28
800317a: f200 809e bhi.w 80032ba <HAL_RCCEx_PeriphCLKConfig+0x51a>
800317e: e8df f003 tbb [pc, r3]
8003182: 9c8b .short 0x9c8b
8003184: 9c9c9c9c .word 0x9c9c9c9c
8003188: 9c859c9c .word 0x9c859c9c
800318c: 9c9c9c9c .word 0x9c9c9c9c
8003190: 9c959c9c .word 0x9c959c9c
8003194: 9c9c9c9c .word 0x9c9c9c9c
8003198: 9c8b9c9c .word 0x9c8b9c9c
800319c: 9c9c9c9c .word 0x9c9c9c9c
80031a0: 9c8b9c9c .word 0x9c8b9c9c
80031a4: 9c9c9c9c .word 0x9c9c9c9c
80031a8: 9c9c .short 0x9c9c
80031aa: 8b .byte 0x8b
80031ab: 00 .byte 0x00
ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE);
80031ac: 2102 movs r1, #2
80031ae: f104 0008 add.w r0, r4, #8
80031b2: f7ff fced bl 8002b90 <RCCEx_PLL2_Config>
80031b6: 4605 mov r5, r0
break;
80031b8: e7cb b.n 8003152 <HAL_RCCEx_PeriphCLKConfig+0x3b2>
switch (PeriphClkInit->FmcClockSelection)
80031ba: 2601 movs r6, #1
80031bc: 4635 mov r5, r6
80031be: e7d0 b.n 8003162 <HAL_RCCEx_PeriphCLKConfig+0x3c2>
status = ret;
80031c0: 462e mov r6, r5
80031c2: e7ce b.n 8003162 <HAL_RCCEx_PeriphCLKConfig+0x3c2>
SET_BIT(PWR->CR1, PWR_CR1_DBP);
80031c4: 4a46 ldr r2, [pc, #280] @ (80032e0 <HAL_RCCEx_PeriphCLKConfig+0x540>)
80031c6: 6813 ldr r3, [r2, #0]
80031c8: f443 7380 orr.w r3, r3, #256 @ 0x100
80031cc: 6013 str r3, [r2, #0]
tickstart = HAL_GetTick();
80031ce: f7fd fb8b bl 80008e8 <HAL_GetTick>
80031d2: 4607 mov r7, r0
while ((PWR->CR1 & PWR_CR1_DBP) == 0U)
80031d4: 4b42 ldr r3, [pc, #264] @ (80032e0 <HAL_RCCEx_PeriphCLKConfig+0x540>)
80031d6: 681b ldr r3, [r3, #0]
80031d8: f413 7f80 tst.w r3, #256 @ 0x100
80031dc: d105 bne.n 80031ea <HAL_RCCEx_PeriphCLKConfig+0x44a>
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
80031de: f7fd fb83 bl 80008e8 <HAL_GetTick>
80031e2: 1bc0 subs r0, r0, r7
80031e4: 2864 cmp r0, #100 @ 0x64
80031e6: d9f5 bls.n 80031d4 <HAL_RCCEx_PeriphCLKConfig+0x434>
ret = HAL_TIMEOUT;
80031e8: 2503 movs r5, #3
if (ret == HAL_OK)
80031ea: 2d00 cmp r5, #0
80031ec: d14a bne.n 8003284 <HAL_RCCEx_PeriphCLKConfig+0x4e4>
if ((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
80031ee: 4b3b ldr r3, [pc, #236] @ (80032dc <HAL_RCCEx_PeriphCLKConfig+0x53c>)
80031f0: 6f1b ldr r3, [r3, #112] @ 0x70
80031f2: f8d4 20b4 ldr.w r2, [r4, #180] @ 0xb4
80031f6: 4053 eors r3, r2
80031f8: f413 7f40 tst.w r3, #768 @ 0x300
80031fc: d00c beq.n 8003218 <HAL_RCCEx_PeriphCLKConfig+0x478>
tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
80031fe: 4b37 ldr r3, [pc, #220] @ (80032dc <HAL_RCCEx_PeriphCLKConfig+0x53c>)
8003200: 6f1a ldr r2, [r3, #112] @ 0x70
8003202: f422 7240 bic.w r2, r2, #768 @ 0x300
__HAL_RCC_BACKUPRESET_FORCE();
8003206: 6f19 ldr r1, [r3, #112] @ 0x70
8003208: f441 3180 orr.w r1, r1, #65536 @ 0x10000
800320c: 6719 str r1, [r3, #112] @ 0x70
__HAL_RCC_BACKUPRESET_RELEASE();
800320e: 6f19 ldr r1, [r3, #112] @ 0x70
8003210: f421 3180 bic.w r1, r1, #65536 @ 0x10000
8003214: 6719 str r1, [r3, #112] @ 0x70
RCC->BDCR = tmpreg;
8003216: 671a str r2, [r3, #112] @ 0x70
if (PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
8003218: f8d4 30b4 ldr.w r3, [r4, #180] @ 0xb4
800321c: f5b3 7f80 cmp.w r3, #256 @ 0x100
8003220: d015 beq.n 800324e <HAL_RCCEx_PeriphCLKConfig+0x4ae>
if (ret == HAL_OK)
8003222: bb8d cbnz r5, 8003288 <HAL_RCCEx_PeriphCLKConfig+0x4e8>
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
8003224: f8d4 30b4 ldr.w r3, [r4, #180] @ 0xb4
8003228: f403 7240 and.w r2, r3, #768 @ 0x300
800322c: f5b2 7f40 cmp.w r2, #768 @ 0x300
8003230: d01e beq.n 8003270 <HAL_RCCEx_PeriphCLKConfig+0x4d0>
8003232: 4a2a ldr r2, [pc, #168] @ (80032dc <HAL_RCCEx_PeriphCLKConfig+0x53c>)
8003234: 6913 ldr r3, [r2, #16]
8003236: f423 537c bic.w r3, r3, #16128 @ 0x3f00
800323a: 6113 str r3, [r2, #16]
800323c: 4927 ldr r1, [pc, #156] @ (80032dc <HAL_RCCEx_PeriphCLKConfig+0x53c>)
800323e: 6f0b ldr r3, [r1, #112] @ 0x70
8003240: f8d4 20b4 ldr.w r2, [r4, #180] @ 0xb4
8003244: f3c2 020b ubfx r2, r2, #0, #12
8003248: 4313 orrs r3, r2
800324a: 670b str r3, [r1, #112] @ 0x70
800324c: e78d b.n 800316a <HAL_RCCEx_PeriphCLKConfig+0x3ca>
tickstart = HAL_GetTick();
800324e: f7fd fb4b bl 80008e8 <HAL_GetTick>
8003252: 4607 mov r7, r0
while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
8003254: 4b21 ldr r3, [pc, #132] @ (80032dc <HAL_RCCEx_PeriphCLKConfig+0x53c>)
8003256: 6f1b ldr r3, [r3, #112] @ 0x70
8003258: f013 0f02 tst.w r3, #2
800325c: d1e1 bne.n 8003222 <HAL_RCCEx_PeriphCLKConfig+0x482>
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
800325e: f7fd fb43 bl 80008e8 <HAL_GetTick>
8003262: 1bc0 subs r0, r0, r7
8003264: f241 3388 movw r3, #5000 @ 0x1388
8003268: 4298 cmp r0, r3
800326a: d9f3 bls.n 8003254 <HAL_RCCEx_PeriphCLKConfig+0x4b4>
ret = HAL_TIMEOUT;
800326c: 2503 movs r5, #3
800326e: e7d8 b.n 8003222 <HAL_RCCEx_PeriphCLKConfig+0x482>
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
8003270: 481a ldr r0, [pc, #104] @ (80032dc <HAL_RCCEx_PeriphCLKConfig+0x53c>)
8003272: 6902 ldr r2, [r0, #16]
8003274: f422 527c bic.w r2, r2, #16128 @ 0x3f00
8003278: 491a ldr r1, [pc, #104] @ (80032e4 <HAL_RCCEx_PeriphCLKConfig+0x544>)
800327a: ea01 1313 and.w r3, r1, r3, lsr #4
800327e: 4313 orrs r3, r2
8003280: 6103 str r3, [r0, #16]
8003282: e7db b.n 800323c <HAL_RCCEx_PeriphCLKConfig+0x49c>
status = ret;
8003284: 462e mov r6, r5
8003286: e770 b.n 800316a <HAL_RCCEx_PeriphCLKConfig+0x3ca>
status = ret;
8003288: 462e mov r6, r5
800328a: e76e b.n 800316a <HAL_RCCEx_PeriphCLKConfig+0x3ca>
ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
800328c: 2101 movs r1, #1
800328e: f104 0008 add.w r0, r4, #8
8003292: f7ff fc7d bl 8002b90 <RCCEx_PLL2_Config>
8003296: 4605 mov r5, r0
if (ret == HAL_OK)
8003298: b9f5 cbnz r5, 80032d8 <HAL_RCCEx_PeriphCLKConfig+0x538>
__HAL_RCC_USART16_CONFIG(PeriphClkInit->Usart16ClockSelection);
800329a: 4a10 ldr r2, [pc, #64] @ (80032dc <HAL_RCCEx_PeriphCLKConfig+0x53c>)
800329c: 6d53 ldr r3, [r2, #84] @ 0x54
800329e: f023 0338 bic.w r3, r3, #56 @ 0x38
80032a2: f8d4 1084 ldr.w r1, [r4, #132] @ 0x84
80032a6: 430b orrs r3, r1
80032a8: 6553 str r3, [r2, #84] @ 0x54
80032aa: e008 b.n 80032be <HAL_RCCEx_PeriphCLKConfig+0x51e>
ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
80032ac: 2101 movs r1, #1
80032ae: f104 0028 add.w r0, r4, #40 @ 0x28
80032b2: f7ff fcf1 bl 8002c98 <RCCEx_PLL3_Config>
80032b6: 4605 mov r5, r0
break;
80032b8: e7ee b.n 8003298 <HAL_RCCEx_PeriphCLKConfig+0x4f8>
switch (PeriphClkInit->Usart16ClockSelection)
80032ba: 2601 movs r6, #1
80032bc: 4635 mov r5, r6
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART234578) == RCC_PERIPHCLK_USART234578)
80032be: 6823 ldr r3, [r4, #0]
80032c0: f013 0f02 tst.w r3, #2
80032c4: d01f beq.n 8003306 <HAL_RCCEx_PeriphCLKConfig+0x566>
switch (PeriphClkInit->Usart234578ClockSelection)
80032c6: f8d4 3080 ldr.w r3, [r4, #128] @ 0x80
80032ca: 2b05 cmp r3, #5
80032cc: d833 bhi.n 8003336 <HAL_RCCEx_PeriphCLKConfig+0x596>
80032ce: e8df f003 tbb [pc, r3]
80032d2: 0b11 .short 0x0b11
80032d4: 1111112b .word 0x1111112b
status = ret;
80032d8: 462e mov r6, r5
80032da: e7f0 b.n 80032be <HAL_RCCEx_PeriphCLKConfig+0x51e>
80032dc: 58024400 .word 0x58024400
80032e0: 58024800 .word 0x58024800
80032e4: 00ffffcf .word 0x00ffffcf
ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
80032e8: 2101 movs r1, #1
80032ea: f104 0008 add.w r0, r4, #8
80032ee: f7ff fc4f bl 8002b90 <RCCEx_PLL2_Config>
80032f2: 4605 mov r5, r0
if (ret == HAL_OK)
80032f4: bb15 cbnz r5, 800333c <HAL_RCCEx_PeriphCLKConfig+0x59c>
__HAL_RCC_USART234578_CONFIG(PeriphClkInit->Usart234578ClockSelection);
80032f6: 4ab7 ldr r2, [pc, #732] @ (80035d4 <HAL_RCCEx_PeriphCLKConfig+0x834>)
80032f8: 6d53 ldr r3, [r2, #84] @ 0x54
80032fa: f023 0307 bic.w r3, r3, #7
80032fe: f8d4 1080 ldr.w r1, [r4, #128] @ 0x80
8003302: 430b orrs r3, r1
8003304: 6553 str r3, [r2, #84] @ 0x54
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
8003306: 6823 ldr r3, [r4, #0]
8003308: f013 0f04 tst.w r3, #4
800330c: d029 beq.n 8003362 <HAL_RCCEx_PeriphCLKConfig+0x5c2>
switch (PeriphClkInit->Lpuart1ClockSelection)
800330e: f8d4 309c ldr.w r3, [r4, #156] @ 0x9c
8003312: 2b05 cmp r3, #5
8003314: f200 8108 bhi.w 8003528 <HAL_RCCEx_PeriphCLKConfig+0x788>
8003318: e8df f013 tbh [pc, r3, lsl #1]
800331c: 00120018 .word 0x00120018
8003320: 001800ff .word 0x001800ff
8003324: 00180018 .word 0x00180018
ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
8003328: 2101 movs r1, #1
800332a: f104 0028 add.w r0, r4, #40 @ 0x28
800332e: f7ff fcb3 bl 8002c98 <RCCEx_PLL3_Config>
8003332: 4605 mov r5, r0
break;
8003334: e7de b.n 80032f4 <HAL_RCCEx_PeriphCLKConfig+0x554>
switch (PeriphClkInit->Usart234578ClockSelection)
8003336: 2601 movs r6, #1
8003338: 4635 mov r5, r6
800333a: e7e4 b.n 8003306 <HAL_RCCEx_PeriphCLKConfig+0x566>
status = ret;
800333c: 462e mov r6, r5
800333e: e7e2 b.n 8003306 <HAL_RCCEx_PeriphCLKConfig+0x566>
ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
8003340: 2101 movs r1, #1
8003342: f104 0008 add.w r0, r4, #8
8003346: f7ff fc23 bl 8002b90 <RCCEx_PLL2_Config>
800334a: 4605 mov r5, r0
if (ret == HAL_OK)
800334c: 2d00 cmp r5, #0
800334e: f040 80ee bne.w 800352e <HAL_RCCEx_PeriphCLKConfig+0x78e>
__HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
8003352: 4aa0 ldr r2, [pc, #640] @ (80035d4 <HAL_RCCEx_PeriphCLKConfig+0x834>)
8003354: 6d93 ldr r3, [r2, #88] @ 0x58
8003356: f023 0307 bic.w r3, r3, #7
800335a: f8d4 109c ldr.w r1, [r4, #156] @ 0x9c
800335e: 430b orrs r3, r1
8003360: 6593 str r3, [r2, #88] @ 0x58
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
8003362: 6823 ldr r3, [r4, #0]
8003364: f013 0f20 tst.w r3, #32
8003368: d01d beq.n 80033a6 <HAL_RCCEx_PeriphCLKConfig+0x606>
switch (PeriphClkInit->Lptim1ClockSelection)
800336a: f8d4 3098 ldr.w r3, [r4, #152] @ 0x98
800336e: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
8003372: f000 80f0 beq.w 8003556 <HAL_RCCEx_PeriphCLKConfig+0x7b6>
8003376: f200 80df bhi.w 8003538 <HAL_RCCEx_PeriphCLKConfig+0x798>
800337a: b14b cbz r3, 8003390 <HAL_RCCEx_PeriphCLKConfig+0x5f0>
800337c: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
8003380: f040 80d7 bne.w 8003532 <HAL_RCCEx_PeriphCLKConfig+0x792>
ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
8003384: 2100 movs r1, #0
8003386: f104 0008 add.w r0, r4, #8
800338a: f7ff fc01 bl 8002b90 <RCCEx_PLL2_Config>
800338e: 4605 mov r5, r0
if (ret == HAL_OK)
8003390: 2d00 cmp r5, #0
8003392: f040 80e7 bne.w 8003564 <HAL_RCCEx_PeriphCLKConfig+0x7c4>
__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
8003396: 4a8f ldr r2, [pc, #572] @ (80035d4 <HAL_RCCEx_PeriphCLKConfig+0x834>)
8003398: 6d53 ldr r3, [r2, #84] @ 0x54
800339a: f023 43e0 bic.w r3, r3, #1879048192 @ 0x70000000
800339e: f8d4 1098 ldr.w r1, [r4, #152] @ 0x98
80033a2: 430b orrs r3, r1
80033a4: 6553 str r3, [r2, #84] @ 0x54
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2)
80033a6: 6823 ldr r3, [r4, #0]
80033a8: f013 0f40 tst.w r3, #64 @ 0x40
80033ac: d01d beq.n 80033ea <HAL_RCCEx_PeriphCLKConfig+0x64a>
switch (PeriphClkInit->Lptim2ClockSelection)
80033ae: f8d4 30a4 ldr.w r3, [r4, #164] @ 0xa4
80033b2: f5b3 6f00 cmp.w r3, #2048 @ 0x800
80033b6: f000 80e9 beq.w 800358c <HAL_RCCEx_PeriphCLKConfig+0x7ec>
80033ba: f200 80d8 bhi.w 800356e <HAL_RCCEx_PeriphCLKConfig+0x7ce>
80033be: b14b cbz r3, 80033d4 <HAL_RCCEx_PeriphCLKConfig+0x634>
80033c0: f5b3 6f80 cmp.w r3, #1024 @ 0x400
80033c4: f040 80d0 bne.w 8003568 <HAL_RCCEx_PeriphCLKConfig+0x7c8>
ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
80033c8: 2100 movs r1, #0
80033ca: f104 0008 add.w r0, r4, #8
80033ce: f7ff fbdf bl 8002b90 <RCCEx_PLL2_Config>
80033d2: 4605 mov r5, r0
if (ret == HAL_OK)
80033d4: 2d00 cmp r5, #0
80033d6: f040 80e0 bne.w 800359a <HAL_RCCEx_PeriphCLKConfig+0x7fa>
__HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
80033da: 4a7e ldr r2, [pc, #504] @ (80035d4 <HAL_RCCEx_PeriphCLKConfig+0x834>)
80033dc: 6d93 ldr r3, [r2, #88] @ 0x58
80033de: f423 53e0 bic.w r3, r3, #7168 @ 0x1c00
80033e2: f8d4 10a4 ldr.w r1, [r4, #164] @ 0xa4
80033e6: 430b orrs r3, r1
80033e8: 6593 str r3, [r2, #88] @ 0x58
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM345) == RCC_PERIPHCLK_LPTIM345)
80033ea: 6823 ldr r3, [r4, #0]
80033ec: f013 0f80 tst.w r3, #128 @ 0x80
80033f0: d01d beq.n 800342e <HAL_RCCEx_PeriphCLKConfig+0x68e>
switch (PeriphClkInit->Lptim345ClockSelection)
80033f2: f8d4 30a8 ldr.w r3, [r4, #168] @ 0xa8
80033f6: f5b3 4f80 cmp.w r3, #16384 @ 0x4000
80033fa: f000 80e2 beq.w 80035c2 <HAL_RCCEx_PeriphCLKConfig+0x822>
80033fe: f200 80d1 bhi.w 80035a4 <HAL_RCCEx_PeriphCLKConfig+0x804>
8003402: b14b cbz r3, 8003418 <HAL_RCCEx_PeriphCLKConfig+0x678>
8003404: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
8003408: f040 80c9 bne.w 800359e <HAL_RCCEx_PeriphCLKConfig+0x7fe>
ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
800340c: 2100 movs r1, #0
800340e: f104 0008 add.w r0, r4, #8
8003412: f7ff fbbd bl 8002b90 <RCCEx_PLL2_Config>
8003416: 4605 mov r5, r0
if (ret == HAL_OK)
8003418: 2d00 cmp r5, #0
800341a: f040 80d9 bne.w 80035d0 <HAL_RCCEx_PeriphCLKConfig+0x830>
__HAL_RCC_LPTIM345_CONFIG(PeriphClkInit->Lptim345ClockSelection);
800341e: 4a6d ldr r2, [pc, #436] @ (80035d4 <HAL_RCCEx_PeriphCLKConfig+0x834>)
8003420: 6d93 ldr r3, [r2, #88] @ 0x58
8003422: f423 4360 bic.w r3, r3, #57344 @ 0xe000
8003426: f8d4 10a8 ldr.w r1, [r4, #168] @ 0xa8
800342a: 430b orrs r3, r1
800342c: 6593 str r3, [r2, #88] @ 0x58
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C123) == RCC_PERIPHCLK_I2C123)
800342e: 6823 ldr r3, [r4, #0]
8003430: f013 0f08 tst.w r3, #8
8003434: d00d beq.n 8003452 <HAL_RCCEx_PeriphCLKConfig+0x6b2>
if ((PeriphClkInit->I2c123ClockSelection) == RCC_I2C123CLKSOURCE_PLL3)
8003436: f8d4 308c ldr.w r3, [r4, #140] @ 0x8c
800343a: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
800343e: f000 80cb beq.w 80035d8 <HAL_RCCEx_PeriphCLKConfig+0x838>
__HAL_RCC_I2C123_CONFIG(PeriphClkInit->I2c123ClockSelection);
8003442: 4a64 ldr r2, [pc, #400] @ (80035d4 <HAL_RCCEx_PeriphCLKConfig+0x834>)
8003444: 6d53 ldr r3, [r2, #84] @ 0x54
8003446: f423 5340 bic.w r3, r3, #12288 @ 0x3000
800344a: f8d4 108c ldr.w r1, [r4, #140] @ 0x8c
800344e: 430b orrs r3, r1
8003450: 6553 str r3, [r2, #84] @ 0x54
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
8003452: 6823 ldr r3, [r4, #0]
8003454: f013 0f10 tst.w r3, #16
8003458: d00d beq.n 8003476 <HAL_RCCEx_PeriphCLKConfig+0x6d6>
if ((PeriphClkInit->I2c4ClockSelection) == RCC_I2C4CLKSOURCE_PLL3)
800345a: f8d4 30a0 ldr.w r3, [r4, #160] @ 0xa0
800345e: f5b3 7f80 cmp.w r3, #256 @ 0x100
8003462: f000 80c3 beq.w 80035ec <HAL_RCCEx_PeriphCLKConfig+0x84c>
__HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
8003466: 4a5b ldr r2, [pc, #364] @ (80035d4 <HAL_RCCEx_PeriphCLKConfig+0x834>)
8003468: 6d93 ldr r3, [r2, #88] @ 0x58
800346a: f423 7340 bic.w r3, r3, #768 @ 0x300
800346e: f8d4 10a0 ldr.w r1, [r4, #160] @ 0xa0
8003472: 430b orrs r3, r1
8003474: 6593 str r3, [r2, #88] @ 0x58
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
8003476: 6823 ldr r3, [r4, #0]
8003478: f413 2f00 tst.w r3, #524288 @ 0x80000
800347c: d01c beq.n 80034b8 <HAL_RCCEx_PeriphCLKConfig+0x718>
switch (PeriphClkInit->AdcClockSelection)
800347e: f8d4 30ac ldr.w r3, [r4, #172] @ 0xac
8003482: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8003486: f000 80bb beq.w 8003600 <HAL_RCCEx_PeriphCLKConfig+0x860>
800348a: f5b3 3f00 cmp.w r3, #131072 @ 0x20000
800348e: d008 beq.n 80034a2 <HAL_RCCEx_PeriphCLKConfig+0x702>
8003490: 2b00 cmp r3, #0
8003492: f040 80bc bne.w 800360e <HAL_RCCEx_PeriphCLKConfig+0x86e>
ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
8003496: 2100 movs r1, #0
8003498: f104 0008 add.w r0, r4, #8
800349c: f7ff fb78 bl 8002b90 <RCCEx_PLL2_Config>
80034a0: 4605 mov r5, r0
if (ret == HAL_OK)
80034a2: 2d00 cmp r5, #0
80034a4: f040 80b6 bne.w 8003614 <HAL_RCCEx_PeriphCLKConfig+0x874>
__HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
80034a8: 4a4a ldr r2, [pc, #296] @ (80035d4 <HAL_RCCEx_PeriphCLKConfig+0x834>)
80034aa: 6d93 ldr r3, [r2, #88] @ 0x58
80034ac: f423 3340 bic.w r3, r3, #196608 @ 0x30000
80034b0: f8d4 10ac ldr.w r1, [r4, #172] @ 0xac
80034b4: 430b orrs r3, r1
80034b6: 6593 str r3, [r2, #88] @ 0x58
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
80034b8: 6823 ldr r3, [r4, #0]
80034ba: f413 2f80 tst.w r3, #262144 @ 0x40000
80034be: d01c beq.n 80034fa <HAL_RCCEx_PeriphCLKConfig+0x75a>
switch (PeriphClkInit->UsbClockSelection)
80034c0: f8d4 3090 ldr.w r3, [r4, #144] @ 0x90
80034c4: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000
80034c8: f000 80a6 beq.w 8003618 <HAL_RCCEx_PeriphCLKConfig+0x878>
80034cc: f5b3 1f40 cmp.w r3, #3145728 @ 0x300000
80034d0: d008 beq.n 80034e4 <HAL_RCCEx_PeriphCLKConfig+0x744>
80034d2: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
80034d6: f040 80a6 bne.w 8003626 <HAL_RCCEx_PeriphCLKConfig+0x886>
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
80034da: 4a3e ldr r2, [pc, #248] @ (80035d4 <HAL_RCCEx_PeriphCLKConfig+0x834>)
80034dc: 6ad3 ldr r3, [r2, #44] @ 0x2c
80034de: f443 3300 orr.w r3, r3, #131072 @ 0x20000
80034e2: 62d3 str r3, [r2, #44] @ 0x2c
if (ret == HAL_OK)
80034e4: 2d00 cmp r5, #0
80034e6: f040 80a1 bne.w 800362c <HAL_RCCEx_PeriphCLKConfig+0x88c>
__HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
80034ea: 4a3a ldr r2, [pc, #232] @ (80035d4 <HAL_RCCEx_PeriphCLKConfig+0x834>)
80034ec: 6d53 ldr r3, [r2, #84] @ 0x54
80034ee: f423 1340 bic.w r3, r3, #3145728 @ 0x300000
80034f2: f8d4 1090 ldr.w r1, [r4, #144] @ 0x90
80034f6: 430b orrs r3, r1
80034f8: 6553 str r3, [r2, #84] @ 0x54
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == RCC_PERIPHCLK_SDMMC)
80034fa: 6823 ldr r3, [r4, #0]
80034fc: f413 3f80 tst.w r3, #65536 @ 0x10000
8003500: f000 80ac beq.w 800365c <HAL_RCCEx_PeriphCLKConfig+0x8bc>
switch (PeriphClkInit->SdmmcClockSelection)
8003504: 6d23 ldr r3, [r4, #80] @ 0x50
8003506: 2b00 cmp r3, #0
8003508: f000 8092 beq.w 8003630 <HAL_RCCEx_PeriphCLKConfig+0x890>
800350c: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8003510: f000 809c beq.w 800364c <HAL_RCCEx_PeriphCLKConfig+0x8ac>
8003514: 2601 movs r6, #1
8003516: 4635 mov r5, r6
8003518: e0a0 b.n 800365c <HAL_RCCEx_PeriphCLKConfig+0x8bc>
ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
800351a: 2101 movs r1, #1
800351c: f104 0028 add.w r0, r4, #40 @ 0x28
8003520: f7ff fbba bl 8002c98 <RCCEx_PLL3_Config>
8003524: 4605 mov r5, r0
break;
8003526: e711 b.n 800334c <HAL_RCCEx_PeriphCLKConfig+0x5ac>
switch (PeriphClkInit->Lpuart1ClockSelection)
8003528: 2601 movs r6, #1
800352a: 4635 mov r5, r6
800352c: e719 b.n 8003362 <HAL_RCCEx_PeriphCLKConfig+0x5c2>
status = ret;
800352e: 462e mov r6, r5
8003530: e717 b.n 8003362 <HAL_RCCEx_PeriphCLKConfig+0x5c2>
switch (PeriphClkInit->Lptim1ClockSelection)
8003532: 2601 movs r6, #1
8003534: 4635 mov r5, r6
8003536: e736 b.n 80033a6 <HAL_RCCEx_PeriphCLKConfig+0x606>
8003538: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
800353c: f43f af28 beq.w 8003390 <HAL_RCCEx_PeriphCLKConfig+0x5f0>
8003540: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
8003544: f43f af24 beq.w 8003390 <HAL_RCCEx_PeriphCLKConfig+0x5f0>
8003548: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000
800354c: f43f af20 beq.w 8003390 <HAL_RCCEx_PeriphCLKConfig+0x5f0>
8003550: 2601 movs r6, #1
8003552: 4635 mov r5, r6
8003554: e727 b.n 80033a6 <HAL_RCCEx_PeriphCLKConfig+0x606>
ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE);
8003556: 2102 movs r1, #2
8003558: f104 0028 add.w r0, r4, #40 @ 0x28
800355c: f7ff fb9c bl 8002c98 <RCCEx_PLL3_Config>
8003560: 4605 mov r5, r0
break;
8003562: e715 b.n 8003390 <HAL_RCCEx_PeriphCLKConfig+0x5f0>
status = ret;
8003564: 462e mov r6, r5
8003566: e71e b.n 80033a6 <HAL_RCCEx_PeriphCLKConfig+0x606>
switch (PeriphClkInit->Lptim2ClockSelection)
8003568: 2601 movs r6, #1
800356a: 4635 mov r5, r6
800356c: e73d b.n 80033ea <HAL_RCCEx_PeriphCLKConfig+0x64a>
800356e: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
8003572: f43f af2f beq.w 80033d4 <HAL_RCCEx_PeriphCLKConfig+0x634>
8003576: f5b3 5fa0 cmp.w r3, #5120 @ 0x1400
800357a: f43f af2b beq.w 80033d4 <HAL_RCCEx_PeriphCLKConfig+0x634>
800357e: f5b3 6f40 cmp.w r3, #3072 @ 0xc00
8003582: f43f af27 beq.w 80033d4 <HAL_RCCEx_PeriphCLKConfig+0x634>
8003586: 2601 movs r6, #1
8003588: 4635 mov r5, r6
800358a: e72e b.n 80033ea <HAL_RCCEx_PeriphCLKConfig+0x64a>
ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE);
800358c: 2102 movs r1, #2
800358e: f104 0028 add.w r0, r4, #40 @ 0x28
8003592: f7ff fb81 bl 8002c98 <RCCEx_PLL3_Config>
8003596: 4605 mov r5, r0
break;
8003598: e71c b.n 80033d4 <HAL_RCCEx_PeriphCLKConfig+0x634>
status = ret;
800359a: 462e mov r6, r5
800359c: e725 b.n 80033ea <HAL_RCCEx_PeriphCLKConfig+0x64a>
switch (PeriphClkInit->Lptim345ClockSelection)
800359e: 2601 movs r6, #1
80035a0: 4635 mov r5, r6
80035a2: e744 b.n 800342e <HAL_RCCEx_PeriphCLKConfig+0x68e>
80035a4: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
80035a8: f43f af36 beq.w 8003418 <HAL_RCCEx_PeriphCLKConfig+0x678>
80035ac: f5b3 4f20 cmp.w r3, #40960 @ 0xa000
80035b0: f43f af32 beq.w 8003418 <HAL_RCCEx_PeriphCLKConfig+0x678>
80035b4: f5b3 4fc0 cmp.w r3, #24576 @ 0x6000
80035b8: f43f af2e beq.w 8003418 <HAL_RCCEx_PeriphCLKConfig+0x678>
80035bc: 2601 movs r6, #1
80035be: 4635 mov r5, r6
80035c0: e735 b.n 800342e <HAL_RCCEx_PeriphCLKConfig+0x68e>
ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE);
80035c2: 2102 movs r1, #2
80035c4: f104 0028 add.w r0, r4, #40 @ 0x28
80035c8: f7ff fb66 bl 8002c98 <RCCEx_PLL3_Config>
80035cc: 4605 mov r5, r0
break;
80035ce: e723 b.n 8003418 <HAL_RCCEx_PeriphCLKConfig+0x678>
status = ret;
80035d0: 462e mov r6, r5
80035d2: e72c b.n 800342e <HAL_RCCEx_PeriphCLKConfig+0x68e>
80035d4: 58024400 .word 0x58024400
if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK)
80035d8: 2102 movs r1, #2
80035da: f104 0028 add.w r0, r4, #40 @ 0x28
80035de: f7ff fb5b bl 8002c98 <RCCEx_PLL3_Config>
80035e2: 2800 cmp r0, #0
80035e4: f43f af2d beq.w 8003442 <HAL_RCCEx_PeriphCLKConfig+0x6a2>
status = HAL_ERROR;
80035e8: 2601 movs r6, #1
80035ea: e72a b.n 8003442 <HAL_RCCEx_PeriphCLKConfig+0x6a2>
if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK)
80035ec: 2102 movs r1, #2
80035ee: f104 0028 add.w r0, r4, #40 @ 0x28
80035f2: f7ff fb51 bl 8002c98 <RCCEx_PLL3_Config>
80035f6: 2800 cmp r0, #0
80035f8: f43f af35 beq.w 8003466 <HAL_RCCEx_PeriphCLKConfig+0x6c6>
status = HAL_ERROR;
80035fc: 2601 movs r6, #1
80035fe: e732 b.n 8003466 <HAL_RCCEx_PeriphCLKConfig+0x6c6>
ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE);
8003600: 2102 movs r1, #2
8003602: f104 0028 add.w r0, r4, #40 @ 0x28
8003606: f7ff fb47 bl 8002c98 <RCCEx_PLL3_Config>
800360a: 4605 mov r5, r0
break;
800360c: e749 b.n 80034a2 <HAL_RCCEx_PeriphCLKConfig+0x702>
switch (PeriphClkInit->AdcClockSelection)
800360e: 2601 movs r6, #1
8003610: 4635 mov r5, r6
8003612: e751 b.n 80034b8 <HAL_RCCEx_PeriphCLKConfig+0x718>
status = ret;
8003614: 462e mov r6, r5
8003616: e74f b.n 80034b8 <HAL_RCCEx_PeriphCLKConfig+0x718>
ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
8003618: 2101 movs r1, #1
800361a: f104 0028 add.w r0, r4, #40 @ 0x28
800361e: f7ff fb3b bl 8002c98 <RCCEx_PLL3_Config>
8003622: 4605 mov r5, r0
break;
8003624: e75e b.n 80034e4 <HAL_RCCEx_PeriphCLKConfig+0x744>
switch (PeriphClkInit->UsbClockSelection)
8003626: 2601 movs r6, #1
8003628: 4635 mov r5, r6
800362a: e766 b.n 80034fa <HAL_RCCEx_PeriphCLKConfig+0x75a>
status = ret;
800362c: 462e mov r6, r5
800362e: e764 b.n 80034fa <HAL_RCCEx_PeriphCLKConfig+0x75a>
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
8003630: 4a6f ldr r2, [pc, #444] @ (80037f0 <HAL_RCCEx_PeriphCLKConfig+0xa50>)
8003632: 6ad3 ldr r3, [r2, #44] @ 0x2c
8003634: f443 3300 orr.w r3, r3, #131072 @ 0x20000
8003638: 62d3 str r3, [r2, #44] @ 0x2c
if (ret == HAL_OK)
800363a: b975 cbnz r5, 800365a <HAL_RCCEx_PeriphCLKConfig+0x8ba>
__HAL_RCC_SDMMC_CONFIG(PeriphClkInit->SdmmcClockSelection);
800363c: 4a6c ldr r2, [pc, #432] @ (80037f0 <HAL_RCCEx_PeriphCLKConfig+0xa50>)
800363e: 6cd3 ldr r3, [r2, #76] @ 0x4c
8003640: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8003644: 6d21 ldr r1, [r4, #80] @ 0x50
8003646: 430b orrs r3, r1
8003648: 64d3 str r3, [r2, #76] @ 0x4c
800364a: e007 b.n 800365c <HAL_RCCEx_PeriphCLKConfig+0x8bc>
ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE);
800364c: 2102 movs r1, #2
800364e: f104 0008 add.w r0, r4, #8
8003652: f7ff fa9d bl 8002b90 <RCCEx_PLL2_Config>
8003656: 4605 mov r5, r0
break;
8003658: e7ef b.n 800363a <HAL_RCCEx_PeriphCLKConfig+0x89a>
status = ret;
800365a: 462e mov r6, r5
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
800365c: 6823 ldr r3, [r4, #0]
800365e: f013 5f00 tst.w r3, #536870912 @ 0x20000000
8003662: d111 bne.n 8003688 <HAL_RCCEx_PeriphCLKConfig+0x8e8>
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG)
8003664: 6823 ldr r3, [r4, #0]
8003666: f413 3f00 tst.w r3, #131072 @ 0x20000
800366a: d028 beq.n 80036be <HAL_RCCEx_PeriphCLKConfig+0x91e>
switch (PeriphClkInit->RngClockSelection)
800366c: f8d4 3088 ldr.w r3, [r4, #136] @ 0x88
8003670: f5b3 7f80 cmp.w r3, #256 @ 0x100
8003674: d014 beq.n 80036a0 <HAL_RCCEx_PeriphCLKConfig+0x900>
8003676: d910 bls.n 800369a <HAL_RCCEx_PeriphCLKConfig+0x8fa>
8003678: f5b3 7f00 cmp.w r3, #512 @ 0x200
800367c: d015 beq.n 80036aa <HAL_RCCEx_PeriphCLKConfig+0x90a>
800367e: f5b3 7f40 cmp.w r3, #768 @ 0x300
8003682: d012 beq.n 80036aa <HAL_RCCEx_PeriphCLKConfig+0x90a>
8003684: 2601 movs r6, #1
8003686: e01a b.n 80036be <HAL_RCCEx_PeriphCLKConfig+0x91e>
if (RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE) != HAL_OK)
8003688: 2102 movs r1, #2
800368a: f104 0028 add.w r0, r4, #40 @ 0x28
800368e: f7ff fb03 bl 8002c98 <RCCEx_PLL3_Config>
8003692: 2800 cmp r0, #0
8003694: d0e6 beq.n 8003664 <HAL_RCCEx_PeriphCLKConfig+0x8c4>
status = HAL_ERROR;
8003696: 2601 movs r6, #1
8003698: e7e4 b.n 8003664 <HAL_RCCEx_PeriphCLKConfig+0x8c4>
switch (PeriphClkInit->RngClockSelection)
800369a: b133 cbz r3, 80036aa <HAL_RCCEx_PeriphCLKConfig+0x90a>
800369c: 2601 movs r6, #1
800369e: e00e b.n 80036be <HAL_RCCEx_PeriphCLKConfig+0x91e>
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
80036a0: 4a53 ldr r2, [pc, #332] @ (80037f0 <HAL_RCCEx_PeriphCLKConfig+0xa50>)
80036a2: 6ad3 ldr r3, [r2, #44] @ 0x2c
80036a4: f443 3300 orr.w r3, r3, #131072 @ 0x20000
80036a8: 62d3 str r3, [r2, #44] @ 0x2c
if (ret == HAL_OK)
80036aa: 2d00 cmp r5, #0
80036ac: d168 bne.n 8003780 <HAL_RCCEx_PeriphCLKConfig+0x9e0>
__HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
80036ae: 4a50 ldr r2, [pc, #320] @ (80037f0 <HAL_RCCEx_PeriphCLKConfig+0xa50>)
80036b0: 6d53 ldr r3, [r2, #84] @ 0x54
80036b2: f423 7340 bic.w r3, r3, #768 @ 0x300
80036b6: f8d4 1088 ldr.w r1, [r4, #136] @ 0x88
80036ba: 430b orrs r3, r1
80036bc: 6553 str r3, [r2, #84] @ 0x54
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1)
80036be: 6823 ldr r3, [r4, #0]
80036c0: f413 1f80 tst.w r3, #1048576 @ 0x100000
80036c4: d006 beq.n 80036d4 <HAL_RCCEx_PeriphCLKConfig+0x934>
__HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection);
80036c6: 4a4a ldr r2, [pc, #296] @ (80037f0 <HAL_RCCEx_PeriphCLKConfig+0xa50>)
80036c8: 6d13 ldr r3, [r2, #80] @ 0x50
80036ca: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
80036ce: 6fe1 ldr r1, [r4, #124] @ 0x7c
80036d0: 430b orrs r3, r1
80036d2: 6513 str r3, [r2, #80] @ 0x50
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
80036d4: 6823 ldr r3, [r4, #0]
80036d6: f413 1f00 tst.w r3, #2097152 @ 0x200000
80036da: d006 beq.n 80036ea <HAL_RCCEx_PeriphCLKConfig+0x94a>
__HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
80036dc: 4a44 ldr r2, [pc, #272] @ (80037f0 <HAL_RCCEx_PeriphCLKConfig+0xa50>)
80036de: 6d13 ldr r3, [r2, #80] @ 0x50
80036e0: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
80036e4: 6f21 ldr r1, [r4, #112] @ 0x70
80036e6: 430b orrs r3, r1
80036e8: 6513 str r3, [r2, #80] @ 0x50
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2) == RCC_PERIPHCLK_DFSDM2)
80036ea: 6823 ldr r3, [r4, #0]
80036ec: f413 6f00 tst.w r3, #2048 @ 0x800
80036f0: d006 beq.n 8003700 <HAL_RCCEx_PeriphCLKConfig+0x960>
__HAL_RCC_DFSDM2_CONFIG(PeriphClkInit->Dfsdm2ClockSelection);
80036f2: 4a3f ldr r2, [pc, #252] @ (80037f0 <HAL_RCCEx_PeriphCLKConfig+0xa50>)
80036f4: 6d93 ldr r3, [r2, #88] @ 0x58
80036f6: f023 6300 bic.w r3, r3, #134217728 @ 0x8000000
80036fa: 6f61 ldr r1, [r4, #116] @ 0x74
80036fc: 430b orrs r3, r1
80036fe: 6593 str r3, [r2, #88] @ 0x58
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM)
8003700: 6823 ldr r3, [r4, #0]
8003702: f013 4f80 tst.w r3, #1073741824 @ 0x40000000
8003706: d009 beq.n 800371c <HAL_RCCEx_PeriphCLKConfig+0x97c>
__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
8003708: 4b39 ldr r3, [pc, #228] @ (80037f0 <HAL_RCCEx_PeriphCLKConfig+0xa50>)
800370a: 691a ldr r2, [r3, #16]
800370c: f422 4200 bic.w r2, r2, #32768 @ 0x8000
8003710: 611a str r2, [r3, #16]
8003712: 691a ldr r2, [r3, #16]
8003714: f8d4 10b8 ldr.w r1, [r4, #184] @ 0xb8
8003718: 430a orrs r2, r1
800371a: 611a str r2, [r3, #16]
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CKPER) == RCC_PERIPHCLK_CKPER)
800371c: 6823 ldr r3, [r4, #0]
800371e: 2b00 cmp r3, #0
8003720: da06 bge.n 8003730 <HAL_RCCEx_PeriphCLKConfig+0x990>
__HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection);
8003722: 4a33 ldr r2, [pc, #204] @ (80037f0 <HAL_RCCEx_PeriphCLKConfig+0xa50>)
8003724: 6cd3 ldr r3, [r2, #76] @ 0x4c
8003726: f023 5340 bic.w r3, r3, #805306368 @ 0x30000000
800372a: 6d61 ldr r1, [r4, #84] @ 0x54
800372c: 430b orrs r3, r1
800372e: 64d3 str r3, [r2, #76] @ 0x4c
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
8003730: 6823 ldr r3, [r4, #0]
8003732: f413 0f00 tst.w r3, #8388608 @ 0x800000
8003736: d007 beq.n 8003748 <HAL_RCCEx_PeriphCLKConfig+0x9a8>
__HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
8003738: 4a2d ldr r2, [pc, #180] @ (80037f0 <HAL_RCCEx_PeriphCLKConfig+0xa50>)
800373a: 6d53 ldr r3, [r2, #84] @ 0x54
800373c: f423 0340 bic.w r3, r3, #12582912 @ 0xc00000
8003740: f8d4 1094 ldr.w r1, [r4, #148] @ 0x94
8003744: 430b orrs r3, r1
8003746: 6553 str r3, [r2, #84] @ 0x54
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVP) == RCC_PERIPHCLK_PLL2_DIVP)
8003748: 6863 ldr r3, [r4, #4]
800374a: f013 0f01 tst.w r3, #1
800374e: d119 bne.n 8003784 <HAL_RCCEx_PeriphCLKConfig+0x9e4>
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVQ) == RCC_PERIPHCLK_PLL2_DIVQ)
8003750: 6863 ldr r3, [r4, #4]
8003752: f013 0f02 tst.w r3, #2
8003756: d11e bne.n 8003796 <HAL_RCCEx_PeriphCLKConfig+0x9f6>
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL2_DIVR) == RCC_PERIPHCLK_PLL2_DIVR)
8003758: 6863 ldr r3, [r4, #4]
800375a: f013 0f04 tst.w r3, #4
800375e: d123 bne.n 80037a8 <HAL_RCCEx_PeriphCLKConfig+0xa08>
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVP) == RCC_PERIPHCLK_PLL3_DIVP)
8003760: 6863 ldr r3, [r4, #4]
8003762: f013 0f08 tst.w r3, #8
8003766: d128 bne.n 80037ba <HAL_RCCEx_PeriphCLKConfig+0xa1a>
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVQ) == RCC_PERIPHCLK_PLL3_DIVQ)
8003768: 6863 ldr r3, [r4, #4]
800376a: f013 0f10 tst.w r3, #16
800376e: d12d bne.n 80037cc <HAL_RCCEx_PeriphCLKConfig+0xa2c>
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLL3_DIVR) == RCC_PERIPHCLK_PLL3_DIVR)
8003770: 6863 ldr r3, [r4, #4]
8003772: f013 0f20 tst.w r3, #32
8003776: d132 bne.n 80037de <HAL_RCCEx_PeriphCLKConfig+0xa3e>
if (status == HAL_OK)
8003778: b106 cbz r6, 800377c <HAL_RCCEx_PeriphCLKConfig+0x9dc>
return HAL_ERROR;
800377a: 2601 movs r6, #1
}
800377c: 4630 mov r0, r6
800377e: bdf8 pop {r3, r4, r5, r6, r7, pc}
status = ret;
8003780: 462e mov r6, r5
8003782: e79c b.n 80036be <HAL_RCCEx_PeriphCLKConfig+0x91e>
ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_P_UPDATE);
8003784: 2100 movs r1, #0
8003786: f104 0008 add.w r0, r4, #8
800378a: f7ff fa01 bl 8002b90 <RCCEx_PLL2_Config>
if (ret == HAL_OK)
800378e: 2800 cmp r0, #0
8003790: d0de beq.n 8003750 <HAL_RCCEx_PeriphCLKConfig+0x9b0>
status = ret;
8003792: 4606 mov r6, r0
8003794: e7dc b.n 8003750 <HAL_RCCEx_PeriphCLKConfig+0x9b0>
ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_Q_UPDATE);
8003796: 2101 movs r1, #1
8003798: f104 0008 add.w r0, r4, #8
800379c: f7ff f9f8 bl 8002b90 <RCCEx_PLL2_Config>
if (ret == HAL_OK)
80037a0: 2800 cmp r0, #0
80037a2: d0d9 beq.n 8003758 <HAL_RCCEx_PeriphCLKConfig+0x9b8>
status = ret;
80037a4: 4606 mov r6, r0
80037a6: e7d7 b.n 8003758 <HAL_RCCEx_PeriphCLKConfig+0x9b8>
ret = RCCEx_PLL2_Config(&(PeriphClkInit->PLL2), DIVIDER_R_UPDATE);
80037a8: 2102 movs r1, #2
80037aa: f104 0008 add.w r0, r4, #8
80037ae: f7ff f9ef bl 8002b90 <RCCEx_PLL2_Config>
if (ret == HAL_OK)
80037b2: 2800 cmp r0, #0
80037b4: d0d4 beq.n 8003760 <HAL_RCCEx_PeriphCLKConfig+0x9c0>
status = ret;
80037b6: 4606 mov r6, r0
80037b8: e7d2 b.n 8003760 <HAL_RCCEx_PeriphCLKConfig+0x9c0>
ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_P_UPDATE);
80037ba: 2100 movs r1, #0
80037bc: f104 0028 add.w r0, r4, #40 @ 0x28
80037c0: f7ff fa6a bl 8002c98 <RCCEx_PLL3_Config>
if (ret == HAL_OK)
80037c4: 2800 cmp r0, #0
80037c6: d0cf beq.n 8003768 <HAL_RCCEx_PeriphCLKConfig+0x9c8>
status = ret;
80037c8: 4606 mov r6, r0
80037ca: e7cd b.n 8003768 <HAL_RCCEx_PeriphCLKConfig+0x9c8>
ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_Q_UPDATE);
80037cc: 2101 movs r1, #1
80037ce: f104 0028 add.w r0, r4, #40 @ 0x28
80037d2: f7ff fa61 bl 8002c98 <RCCEx_PLL3_Config>
if (ret == HAL_OK)
80037d6: 2800 cmp r0, #0
80037d8: d0ca beq.n 8003770 <HAL_RCCEx_PeriphCLKConfig+0x9d0>
status = ret;
80037da: 4606 mov r6, r0
80037dc: e7c8 b.n 8003770 <HAL_RCCEx_PeriphCLKConfig+0x9d0>
ret = RCCEx_PLL3_Config(&(PeriphClkInit->PLL3), DIVIDER_R_UPDATE);
80037de: 2102 movs r1, #2
80037e0: f104 0028 add.w r0, r4, #40 @ 0x28
80037e4: f7ff fa58 bl 8002c98 <RCCEx_PLL3_Config>
if (ret == HAL_OK)
80037e8: 2800 cmp r0, #0
80037ea: d0c5 beq.n 8003778 <HAL_RCCEx_PeriphCLKConfig+0x9d8>
return HAL_ERROR;
80037ec: 2601 movs r6, #1
80037ee: e7c5 b.n 800377c <HAL_RCCEx_PeriphCLKConfig+0x9dc>
80037f0: 58024400 .word 0x58024400
080037f4 <HAL_RCCEx_GetD3PCLK1Freq>:
{
80037f4: b508 push {r3, lr}
return (HAL_RCC_GetHCLKFreq() >> (D1CorePrescTable[(RCC->SRDCFGR & RCC_SRDCFGR_SRDPPRE) >> RCC_SRDCFGR_SRDPPRE_Pos] & 0x1FU));
80037f6: f7ff f997 bl 8002b28 <HAL_RCC_GetHCLKFreq>
80037fa: 4b05 ldr r3, [pc, #20] @ (8003810 <HAL_RCCEx_GetD3PCLK1Freq+0x1c>)
80037fc: 6a1b ldr r3, [r3, #32]
80037fe: f3c3 1302 ubfx r3, r3, #4, #3
8003802: 4a04 ldr r2, [pc, #16] @ (8003814 <HAL_RCCEx_GetD3PCLK1Freq+0x20>)
8003804: 5cd3 ldrb r3, [r2, r3]
8003806: f003 031f and.w r3, r3, #31
}
800380a: 40d8 lsrs r0, r3
800380c: bd08 pop {r3, pc}
800380e: bf00 nop
8003810: 58024400 .word 0x58024400
8003814: 08004dec .word 0x08004dec
08003818 <HAL_RCCEx_GetPLL2ClockFreq>:
{
8003818: b410 push {r4}
pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
800381a: 4b79 ldr r3, [pc, #484] @ (8003a00 <HAL_RCCEx_GetPLL2ClockFreq+0x1e8>)
800381c: 6a9a ldr r2, [r3, #40] @ 0x28
pll2m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM2) >> 12);
800381e: 6a9c ldr r4, [r3, #40] @ 0x28
8003820: f3c4 3c05 ubfx ip, r4, #12, #6
pll2fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL2FRACEN) >> RCC_PLLCFGR_PLL2FRACEN_Pos;
8003824: 6ad9 ldr r1, [r3, #44] @ 0x2c
8003826: f3c1 1100 ubfx r1, r1, #4, #1
fracn2 = (float_t)(uint32_t)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_FRACN2) >> 3));
800382a: 6bdb ldr r3, [r3, #60] @ 0x3c
800382c: f3c3 03cc ubfx r3, r3, #3, #13
8003830: fb01 f303 mul.w r3, r1, r3
if (pll2m != 0U)
8003834: f414 3f7c tst.w r4, #258048 @ 0x3f000
8003838: f000 80dd beq.w 80039f6 <HAL_RCCEx_GetPLL2ClockFreq+0x1de>
800383c: f002 0203 and.w r2, r2, #3
8003840: ee07 3a90 vmov s15, r3
8003844: eef8 7a67 vcvt.f32.u32 s15, s15
switch (pllsource)
8003848: 2a01 cmp r2, #1
800384a: d04b beq.n 80038e4 <HAL_RCCEx_GetPLL2ClockFreq+0xcc>
800384c: 2a02 cmp r2, #2
800384e: f000 8098 beq.w 8003982 <HAL_RCCEx_GetPLL2ClockFreq+0x16a>
8003852: 2a00 cmp r2, #0
8003854: f040 80b2 bne.w 80039bc <HAL_RCCEx_GetPLL2ClockFreq+0x1a4>
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
8003858: 4b69 ldr r3, [pc, #420] @ (8003a00 <HAL_RCCEx_GetPLL2ClockFreq+0x1e8>)
800385a: 681b ldr r3, [r3, #0]
800385c: f013 0f20 tst.w r3, #32
8003860: d023 beq.n 80038aa <HAL_RCCEx_GetPLL2ClockFreq+0x92>
hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
8003862: 4967 ldr r1, [pc, #412] @ (8003a00 <HAL_RCCEx_GetPLL2ClockFreq+0x1e8>)
8003864: 680a ldr r2, [r1, #0]
8003866: f3c2 02c1 ubfx r2, r2, #3, #2
800386a: 4b66 ldr r3, [pc, #408] @ (8003a04 <HAL_RCCEx_GetPLL2ClockFreq+0x1ec>)
800386c: 40d3 lsrs r3, r2
pll2vco = ((float_t)hsivalue / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
800386e: ee07 3a10 vmov s14, r3
8003872: eef8 6a47 vcvt.f32.u32 s13, s14
8003876: ee07 ca10 vmov s14, ip
800387a: eeb8 6a47 vcvt.f32.u32 s12, s14
800387e: ee86 7a86 vdiv.f32 s14, s13, s12
8003882: 6b8b ldr r3, [r1, #56] @ 0x38
8003884: f3c3 0308 ubfx r3, r3, #0, #9
8003888: ee06 3a90 vmov s13, r3
800388c: eef8 6a66 vcvt.f32.u32 s13, s13
8003890: ed9f 6a5d vldr s12, [pc, #372] @ 8003a08 <HAL_RCCEx_GetPLL2ClockFreq+0x1f0>
8003894: ee67 7a86 vmul.f32 s15, s15, s12
8003898: ee76 7aa7 vadd.f32 s15, s13, s15
800389c: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0
80038a0: ee77 7aa6 vadd.f32 s15, s15, s13
80038a4: ee27 7a27 vmul.f32 s14, s14, s15
80038a8: e038 b.n 800391c <HAL_RCCEx_GetPLL2ClockFreq+0x104>
pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
80038aa: ee07 ca10 vmov s14, ip
80038ae: eef8 6a47 vcvt.f32.u32 s13, s14
80038b2: ed9f 6a56 vldr s12, [pc, #344] @ 8003a0c <HAL_RCCEx_GetPLL2ClockFreq+0x1f4>
80038b6: ee86 7a26 vdiv.f32 s14, s12, s13
80038ba: 4b51 ldr r3, [pc, #324] @ (8003a00 <HAL_RCCEx_GetPLL2ClockFreq+0x1e8>)
80038bc: 6b9b ldr r3, [r3, #56] @ 0x38
80038be: f3c3 0308 ubfx r3, r3, #0, #9
80038c2: ee06 3a90 vmov s13, r3
80038c6: eef8 6a66 vcvt.f32.u32 s13, s13
80038ca: ed9f 6a4f vldr s12, [pc, #316] @ 8003a08 <HAL_RCCEx_GetPLL2ClockFreq+0x1f0>
80038ce: ee67 7a86 vmul.f32 s15, s15, s12
80038d2: ee76 7aa7 vadd.f32 s15, s13, s15
80038d6: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0
80038da: ee77 7aa6 vadd.f32 s15, s15, s13
80038de: ee27 7a27 vmul.f32 s14, s14, s15
80038e2: e01b b.n 800391c <HAL_RCCEx_GetPLL2ClockFreq+0x104>
pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
80038e4: ee07 ca10 vmov s14, ip
80038e8: eef8 6a47 vcvt.f32.u32 s13, s14
80038ec: ed9f 6a48 vldr s12, [pc, #288] @ 8003a10 <HAL_RCCEx_GetPLL2ClockFreq+0x1f8>
80038f0: ee86 7a26 vdiv.f32 s14, s12, s13
80038f4: 4b42 ldr r3, [pc, #264] @ (8003a00 <HAL_RCCEx_GetPLL2ClockFreq+0x1e8>)
80038f6: 6b9b ldr r3, [r3, #56] @ 0x38
80038f8: f3c3 0308 ubfx r3, r3, #0, #9
80038fc: ee06 3a90 vmov s13, r3
8003900: eef8 6a66 vcvt.f32.u32 s13, s13
8003904: ed9f 6a40 vldr s12, [pc, #256] @ 8003a08 <HAL_RCCEx_GetPLL2ClockFreq+0x1f0>
8003908: ee67 7a86 vmul.f32 s15, s15, s12
800390c: ee76 7aa7 vadd.f32 s15, s13, s15
8003910: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0
8003914: ee77 7aa6 vadd.f32 s15, s15, s13
8003918: ee27 7a27 vmul.f32 s14, s14, s15
PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_P2) >> 9) + (float_t)1)) ;
800391c: 4a38 ldr r2, [pc, #224] @ (8003a00 <HAL_RCCEx_GetPLL2ClockFreq+0x1e8>)
800391e: 6b93 ldr r3, [r2, #56] @ 0x38
8003920: f3c3 2346 ubfx r3, r3, #9, #7
8003924: ee07 3a90 vmov s15, r3
8003928: eef8 7a67 vcvt.f32.u32 s15, s15
800392c: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0
8003930: ee77 7aa6 vadd.f32 s15, s15, s13
8003934: ee87 6a27 vdiv.f32 s12, s14, s15
8003938: eebc 6ac6 vcvt.u32.f32 s12, s12
800393c: ed80 6a00 vstr s12, [r0]
PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_Q2) >> 16) + (float_t)1)) ;
8003940: 6b93 ldr r3, [r2, #56] @ 0x38
8003942: f3c3 4306 ubfx r3, r3, #16, #7
8003946: ee07 3a90 vmov s15, r3
800394a: eef8 7a67 vcvt.f32.u32 s15, s15
800394e: ee77 7aa6 vadd.f32 s15, s15, s13
8003952: ee87 6a27 vdiv.f32 s12, s14, s15
8003956: eebc 6ac6 vcvt.u32.f32 s12, s12
800395a: ed80 6a01 vstr s12, [r0, #4]
PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_R2) >> 24) + (float_t)1)) ;
800395e: 6b93 ldr r3, [r2, #56] @ 0x38
8003960: f3c3 6306 ubfx r3, r3, #24, #7
8003964: ee07 3a90 vmov s15, r3
8003968: eef8 7a67 vcvt.f32.u32 s15, s15
800396c: ee77 7aa6 vadd.f32 s15, s15, s13
8003970: eec7 6a27 vdiv.f32 s13, s14, s15
8003974: eefc 6ae6 vcvt.u32.f32 s13, s13
8003978: edc0 6a02 vstr s13, [r0, #8]
}
800397c: f85d 4b04 ldr.w r4, [sp], #4
8003980: 4770 bx lr
pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
8003982: ee07 ca10 vmov s14, ip
8003986: eef8 6a47 vcvt.f32.u32 s13, s14
800398a: ed9f 6a22 vldr s12, [pc, #136] @ 8003a14 <HAL_RCCEx_GetPLL2ClockFreq+0x1fc>
800398e: ee86 7a26 vdiv.f32 s14, s12, s13
8003992: 4b1b ldr r3, [pc, #108] @ (8003a00 <HAL_RCCEx_GetPLL2ClockFreq+0x1e8>)
8003994: 6b9b ldr r3, [r3, #56] @ 0x38
8003996: f3c3 0308 ubfx r3, r3, #0, #9
800399a: ee06 3a90 vmov s13, r3
800399e: eef8 6a66 vcvt.f32.u32 s13, s13
80039a2: ed9f 6a19 vldr s12, [pc, #100] @ 8003a08 <HAL_RCCEx_GetPLL2ClockFreq+0x1f0>
80039a6: ee67 7a86 vmul.f32 s15, s15, s12
80039aa: ee76 7aa7 vadd.f32 s15, s13, s15
80039ae: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0
80039b2: ee77 7aa6 vadd.f32 s15, s15, s13
80039b6: ee27 7a27 vmul.f32 s14, s14, s15
break;
80039ba: e7af b.n 800391c <HAL_RCCEx_GetPLL2ClockFreq+0x104>
pll2vco = ((float_t)CSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_N2) + (fracn2 / (float_t)0x2000) + (float_t)1);
80039bc: ee07 ca10 vmov s14, ip
80039c0: eef8 6a47 vcvt.f32.u32 s13, s14
80039c4: ed9f 6a12 vldr s12, [pc, #72] @ 8003a10 <HAL_RCCEx_GetPLL2ClockFreq+0x1f8>
80039c8: ee86 7a26 vdiv.f32 s14, s12, s13
80039cc: 4b0c ldr r3, [pc, #48] @ (8003a00 <HAL_RCCEx_GetPLL2ClockFreq+0x1e8>)
80039ce: 6b9b ldr r3, [r3, #56] @ 0x38
80039d0: f3c3 0308 ubfx r3, r3, #0, #9
80039d4: ee06 3a90 vmov s13, r3
80039d8: eef8 6a66 vcvt.f32.u32 s13, s13
80039dc: ed9f 6a0a vldr s12, [pc, #40] @ 8003a08 <HAL_RCCEx_GetPLL2ClockFreq+0x1f0>
80039e0: ee67 7a86 vmul.f32 s15, s15, s12
80039e4: ee76 7aa7 vadd.f32 s15, s13, s15
80039e8: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0
80039ec: ee77 7aa6 vadd.f32 s15, s15, s13
80039f0: ee27 7a27 vmul.f32 s14, s14, s15
break;
80039f4: e792 b.n 800391c <HAL_RCCEx_GetPLL2ClockFreq+0x104>
PLL2_Clocks->PLL2_P_Frequency = 0U;
80039f6: 2300 movs r3, #0
80039f8: 6003 str r3, [r0, #0]
PLL2_Clocks->PLL2_Q_Frequency = 0U;
80039fa: 6043 str r3, [r0, #4]
PLL2_Clocks->PLL2_R_Frequency = 0U;
80039fc: 6083 str r3, [r0, #8]
}
80039fe: e7bd b.n 800397c <HAL_RCCEx_GetPLL2ClockFreq+0x164>
8003a00: 58024400 .word 0x58024400
8003a04: 03d09000 .word 0x03d09000
8003a08: 39000000 .word 0x39000000
8003a0c: 4c742400 .word 0x4c742400
8003a10: 4a742400 .word 0x4a742400
8003a14: 4b742400 .word 0x4b742400
08003a18 <HAL_RCCEx_GetPLL3ClockFreq>:
{
8003a18: b410 push {r4}
pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
8003a1a: 4b79 ldr r3, [pc, #484] @ (8003c00 <HAL_RCCEx_GetPLL3ClockFreq+0x1e8>)
8003a1c: 6a9a ldr r2, [r3, #40] @ 0x28
pll3m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM3) >> 20) ;
8003a1e: 6a9c ldr r4, [r3, #40] @ 0x28
8003a20: f3c4 5c05 ubfx ip, r4, #20, #6
pll3fracen = (RCC->PLLCFGR & RCC_PLLCFGR_PLL3FRACEN) >> RCC_PLLCFGR_PLL3FRACEN_Pos;
8003a24: 6ad9 ldr r1, [r3, #44] @ 0x2c
8003a26: f3c1 2100 ubfx r1, r1, #8, #1
fracn3 = (float_t)(uint32_t)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACN3) >> 3));
8003a2a: 6c5b ldr r3, [r3, #68] @ 0x44
8003a2c: f3c3 03cc ubfx r3, r3, #3, #13
8003a30: fb01 f303 mul.w r3, r1, r3
if (pll3m != 0U)
8003a34: f014 7f7c tst.w r4, #66060288 @ 0x3f00000
8003a38: f000 80dd beq.w 8003bf6 <HAL_RCCEx_GetPLL3ClockFreq+0x1de>
8003a3c: f002 0203 and.w r2, r2, #3
8003a40: ee07 3a90 vmov s15, r3
8003a44: eef8 7a67 vcvt.f32.u32 s15, s15
switch (pllsource)
8003a48: 2a01 cmp r2, #1
8003a4a: d04b beq.n 8003ae4 <HAL_RCCEx_GetPLL3ClockFreq+0xcc>
8003a4c: 2a02 cmp r2, #2
8003a4e: f000 8098 beq.w 8003b82 <HAL_RCCEx_GetPLL3ClockFreq+0x16a>
8003a52: 2a00 cmp r2, #0
8003a54: f040 80b2 bne.w 8003bbc <HAL_RCCEx_GetPLL3ClockFreq+0x1a4>
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
8003a58: 4b69 ldr r3, [pc, #420] @ (8003c00 <HAL_RCCEx_GetPLL3ClockFreq+0x1e8>)
8003a5a: 681b ldr r3, [r3, #0]
8003a5c: f013 0f20 tst.w r3, #32
8003a60: d023 beq.n 8003aaa <HAL_RCCEx_GetPLL3ClockFreq+0x92>
hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
8003a62: 4967 ldr r1, [pc, #412] @ (8003c00 <HAL_RCCEx_GetPLL3ClockFreq+0x1e8>)
8003a64: 680a ldr r2, [r1, #0]
8003a66: f3c2 02c1 ubfx r2, r2, #3, #2
8003a6a: 4b66 ldr r3, [pc, #408] @ (8003c04 <HAL_RCCEx_GetPLL3ClockFreq+0x1ec>)
8003a6c: 40d3 lsrs r3, r2
pll3vco = ((float_t)hsivalue / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
8003a6e: ee07 3a10 vmov s14, r3
8003a72: eef8 6a47 vcvt.f32.u32 s13, s14
8003a76: ee07 ca10 vmov s14, ip
8003a7a: eeb8 6a47 vcvt.f32.u32 s12, s14
8003a7e: ee86 7a86 vdiv.f32 s14, s13, s12
8003a82: 6c0b ldr r3, [r1, #64] @ 0x40
8003a84: f3c3 0308 ubfx r3, r3, #0, #9
8003a88: ee06 3a90 vmov s13, r3
8003a8c: eef8 6a66 vcvt.f32.u32 s13, s13
8003a90: ed9f 6a5d vldr s12, [pc, #372] @ 8003c08 <HAL_RCCEx_GetPLL3ClockFreq+0x1f0>
8003a94: ee67 7a86 vmul.f32 s15, s15, s12
8003a98: ee76 7aa7 vadd.f32 s15, s13, s15
8003a9c: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0
8003aa0: ee77 7aa6 vadd.f32 s15, s15, s13
8003aa4: ee27 7a27 vmul.f32 s14, s14, s15
8003aa8: e038 b.n 8003b1c <HAL_RCCEx_GetPLL3ClockFreq+0x104>
pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
8003aaa: ee07 ca10 vmov s14, ip
8003aae: eef8 6a47 vcvt.f32.u32 s13, s14
8003ab2: ed9f 6a56 vldr s12, [pc, #344] @ 8003c0c <HAL_RCCEx_GetPLL3ClockFreq+0x1f4>
8003ab6: ee86 7a26 vdiv.f32 s14, s12, s13
8003aba: 4b51 ldr r3, [pc, #324] @ (8003c00 <HAL_RCCEx_GetPLL3ClockFreq+0x1e8>)
8003abc: 6c1b ldr r3, [r3, #64] @ 0x40
8003abe: f3c3 0308 ubfx r3, r3, #0, #9
8003ac2: ee06 3a90 vmov s13, r3
8003ac6: eef8 6a66 vcvt.f32.u32 s13, s13
8003aca: ed9f 6a4f vldr s12, [pc, #316] @ 8003c08 <HAL_RCCEx_GetPLL3ClockFreq+0x1f0>
8003ace: ee67 7a86 vmul.f32 s15, s15, s12
8003ad2: ee76 7aa7 vadd.f32 s15, s13, s15
8003ad6: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0
8003ada: ee77 7aa6 vadd.f32 s15, s15, s13
8003ade: ee27 7a27 vmul.f32 s14, s14, s15
8003ae2: e01b b.n 8003b1c <HAL_RCCEx_GetPLL3ClockFreq+0x104>
pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
8003ae4: ee07 ca10 vmov s14, ip
8003ae8: eef8 6a47 vcvt.f32.u32 s13, s14
8003aec: ed9f 6a48 vldr s12, [pc, #288] @ 8003c10 <HAL_RCCEx_GetPLL3ClockFreq+0x1f8>
8003af0: ee86 7a26 vdiv.f32 s14, s12, s13
8003af4: 4b42 ldr r3, [pc, #264] @ (8003c00 <HAL_RCCEx_GetPLL3ClockFreq+0x1e8>)
8003af6: 6c1b ldr r3, [r3, #64] @ 0x40
8003af8: f3c3 0308 ubfx r3, r3, #0, #9
8003afc: ee06 3a90 vmov s13, r3
8003b00: eef8 6a66 vcvt.f32.u32 s13, s13
8003b04: ed9f 6a40 vldr s12, [pc, #256] @ 8003c08 <HAL_RCCEx_GetPLL3ClockFreq+0x1f0>
8003b08: ee67 7a86 vmul.f32 s15, s15, s12
8003b0c: ee76 7aa7 vadd.f32 s15, s13, s15
8003b10: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0
8003b14: ee77 7aa6 vadd.f32 s15, s15, s13
8003b18: ee27 7a27 vmul.f32 s14, s14, s15
PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_P3) >> 9) + (float_t)1)) ;
8003b1c: 4a38 ldr r2, [pc, #224] @ (8003c00 <HAL_RCCEx_GetPLL3ClockFreq+0x1e8>)
8003b1e: 6c13 ldr r3, [r2, #64] @ 0x40
8003b20: f3c3 2346 ubfx r3, r3, #9, #7
8003b24: ee07 3a90 vmov s15, r3
8003b28: eef8 7a67 vcvt.f32.u32 s15, s15
8003b2c: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0
8003b30: ee77 7aa6 vadd.f32 s15, s15, s13
8003b34: ee87 6a27 vdiv.f32 s12, s14, s15
8003b38: eebc 6ac6 vcvt.u32.f32 s12, s12
8003b3c: ed80 6a00 vstr s12, [r0]
PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_Q3) >> 16) + (float_t)1)) ;
8003b40: 6c13 ldr r3, [r2, #64] @ 0x40
8003b42: f3c3 4306 ubfx r3, r3, #16, #7
8003b46: ee07 3a90 vmov s15, r3
8003b4a: eef8 7a67 vcvt.f32.u32 s15, s15
8003b4e: ee77 7aa6 vadd.f32 s15, s15, s13
8003b52: ee87 6a27 vdiv.f32 s12, s14, s15
8003b56: eebc 6ac6 vcvt.u32.f32 s12, s12
8003b5a: ed80 6a01 vstr s12, [r0, #4]
PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_R3) >> 24) + (float_t)1)) ;
8003b5e: 6c13 ldr r3, [r2, #64] @ 0x40
8003b60: f3c3 6306 ubfx r3, r3, #24, #7
8003b64: ee07 3a90 vmov s15, r3
8003b68: eef8 7a67 vcvt.f32.u32 s15, s15
8003b6c: ee77 7aa6 vadd.f32 s15, s15, s13
8003b70: eec7 6a27 vdiv.f32 s13, s14, s15
8003b74: eefc 6ae6 vcvt.u32.f32 s13, s13
8003b78: edc0 6a02 vstr s13, [r0, #8]
}
8003b7c: f85d 4b04 ldr.w r4, [sp], #4
8003b80: 4770 bx lr
pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
8003b82: ee07 ca10 vmov s14, ip
8003b86: eef8 6a47 vcvt.f32.u32 s13, s14
8003b8a: ed9f 6a22 vldr s12, [pc, #136] @ 8003c14 <HAL_RCCEx_GetPLL3ClockFreq+0x1fc>
8003b8e: ee86 7a26 vdiv.f32 s14, s12, s13
8003b92: 4b1b ldr r3, [pc, #108] @ (8003c00 <HAL_RCCEx_GetPLL3ClockFreq+0x1e8>)
8003b94: 6c1b ldr r3, [r3, #64] @ 0x40
8003b96: f3c3 0308 ubfx r3, r3, #0, #9
8003b9a: ee06 3a90 vmov s13, r3
8003b9e: eef8 6a66 vcvt.f32.u32 s13, s13
8003ba2: ed9f 6a19 vldr s12, [pc, #100] @ 8003c08 <HAL_RCCEx_GetPLL3ClockFreq+0x1f0>
8003ba6: ee67 7a86 vmul.f32 s15, s15, s12
8003baa: ee76 7aa7 vadd.f32 s15, s13, s15
8003bae: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0
8003bb2: ee77 7aa6 vadd.f32 s15, s15, s13
8003bb6: ee27 7a27 vmul.f32 s14, s14, s15
break;
8003bba: e7af b.n 8003b1c <HAL_RCCEx_GetPLL3ClockFreq+0x104>
pll3vco = ((float_t)CSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_N3) + (fracn3 / (float_t)0x2000) + (float_t)1);
8003bbc: ee07 ca10 vmov s14, ip
8003bc0: eef8 6a47 vcvt.f32.u32 s13, s14
8003bc4: ed9f 6a12 vldr s12, [pc, #72] @ 8003c10 <HAL_RCCEx_GetPLL3ClockFreq+0x1f8>
8003bc8: ee86 7a26 vdiv.f32 s14, s12, s13
8003bcc: 4b0c ldr r3, [pc, #48] @ (8003c00 <HAL_RCCEx_GetPLL3ClockFreq+0x1e8>)
8003bce: 6c1b ldr r3, [r3, #64] @ 0x40
8003bd0: f3c3 0308 ubfx r3, r3, #0, #9
8003bd4: ee06 3a90 vmov s13, r3
8003bd8: eef8 6a66 vcvt.f32.u32 s13, s13
8003bdc: ed9f 6a0a vldr s12, [pc, #40] @ 8003c08 <HAL_RCCEx_GetPLL3ClockFreq+0x1f0>
8003be0: ee67 7a86 vmul.f32 s15, s15, s12
8003be4: ee76 7aa7 vadd.f32 s15, s13, s15
8003be8: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0
8003bec: ee77 7aa6 vadd.f32 s15, s15, s13
8003bf0: ee27 7a27 vmul.f32 s14, s14, s15
break;
8003bf4: e792 b.n 8003b1c <HAL_RCCEx_GetPLL3ClockFreq+0x104>
PLL3_Clocks->PLL3_P_Frequency = 0U;
8003bf6: 2300 movs r3, #0
8003bf8: 6003 str r3, [r0, #0]
PLL3_Clocks->PLL3_Q_Frequency = 0U;
8003bfa: 6043 str r3, [r0, #4]
PLL3_Clocks->PLL3_R_Frequency = 0U;
8003bfc: 6083 str r3, [r0, #8]
}
8003bfe: e7bd b.n 8003b7c <HAL_RCCEx_GetPLL3ClockFreq+0x164>
8003c00: 58024400 .word 0x58024400
8003c04: 03d09000 .word 0x03d09000
8003c08: 39000000 .word 0x39000000
8003c0c: 4c742400 .word 0x4c742400
8003c10: 4a742400 .word 0x4a742400
8003c14: 4b742400 .word 0x4b742400
08003c18 <HAL_RCCEx_GetPLL1ClockFreq>:
{
8003c18: b410 push {r4}
pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
8003c1a: 4b79 ldr r3, [pc, #484] @ (8003e00 <HAL_RCCEx_GetPLL1ClockFreq+0x1e8>)
8003c1c: 6a9a ldr r2, [r3, #40] @ 0x28
pll1m = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4);
8003c1e: 6a9c ldr r4, [r3, #40] @ 0x28
8003c20: f3c4 1c05 ubfx ip, r4, #4, #6
pll1fracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN;
8003c24: 6ad9 ldr r1, [r3, #44] @ 0x2c
8003c26: f001 0101 and.w r1, r1, #1
fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3));
8003c2a: 6b5b ldr r3, [r3, #52] @ 0x34
8003c2c: f3c3 03cc ubfx r3, r3, #3, #13
8003c30: fb01 f303 mul.w r3, r1, r3
if (pll1m != 0U)
8003c34: f414 7f7c tst.w r4, #1008 @ 0x3f0
8003c38: f000 80dd beq.w 8003df6 <HAL_RCCEx_GetPLL1ClockFreq+0x1de>
8003c3c: f002 0203 and.w r2, r2, #3
8003c40: ee07 3a90 vmov s15, r3
8003c44: eef8 7a67 vcvt.f32.u32 s15, s15
switch (pllsource)
8003c48: 2a01 cmp r2, #1
8003c4a: d04b beq.n 8003ce4 <HAL_RCCEx_GetPLL1ClockFreq+0xcc>
8003c4c: 2a02 cmp r2, #2
8003c4e: f000 8098 beq.w 8003d82 <HAL_RCCEx_GetPLL1ClockFreq+0x16a>
8003c52: 2a00 cmp r2, #0
8003c54: f040 80b2 bne.w 8003dbc <HAL_RCCEx_GetPLL1ClockFreq+0x1a4>
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
8003c58: 4b69 ldr r3, [pc, #420] @ (8003e00 <HAL_RCCEx_GetPLL1ClockFreq+0x1e8>)
8003c5a: 681b ldr r3, [r3, #0]
8003c5c: f013 0f20 tst.w r3, #32
8003c60: d023 beq.n 8003caa <HAL_RCCEx_GetPLL1ClockFreq+0x92>
hsivalue = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
8003c62: 4967 ldr r1, [pc, #412] @ (8003e00 <HAL_RCCEx_GetPLL1ClockFreq+0x1e8>)
8003c64: 680a ldr r2, [r1, #0]
8003c66: f3c2 02c1 ubfx r2, r2, #3, #2
8003c6a: 4b66 ldr r3, [pc, #408] @ (8003e04 <HAL_RCCEx_GetPLL1ClockFreq+0x1ec>)
8003c6c: 40d3 lsrs r3, r2
pll1vco = ((float_t)hsivalue / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
8003c6e: ee07 3a10 vmov s14, r3
8003c72: eef8 6a47 vcvt.f32.u32 s13, s14
8003c76: ee07 ca10 vmov s14, ip
8003c7a: eeb8 6a47 vcvt.f32.u32 s12, s14
8003c7e: ee86 7a86 vdiv.f32 s14, s13, s12
8003c82: 6b0b ldr r3, [r1, #48] @ 0x30
8003c84: f3c3 0308 ubfx r3, r3, #0, #9
8003c88: ee06 3a90 vmov s13, r3
8003c8c: eef8 6a66 vcvt.f32.u32 s13, s13
8003c90: ed9f 6a5d vldr s12, [pc, #372] @ 8003e08 <HAL_RCCEx_GetPLL1ClockFreq+0x1f0>
8003c94: ee67 7a86 vmul.f32 s15, s15, s12
8003c98: ee76 7aa7 vadd.f32 s15, s13, s15
8003c9c: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0
8003ca0: ee77 7aa6 vadd.f32 s15, s15, s13
8003ca4: ee27 7a27 vmul.f32 s14, s14, s15
8003ca8: e038 b.n 8003d1c <HAL_RCCEx_GetPLL1ClockFreq+0x104>
pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
8003caa: ee07 ca10 vmov s14, ip
8003cae: eef8 6a47 vcvt.f32.u32 s13, s14
8003cb2: ed9f 6a56 vldr s12, [pc, #344] @ 8003e0c <HAL_RCCEx_GetPLL1ClockFreq+0x1f4>
8003cb6: ee86 7a26 vdiv.f32 s14, s12, s13
8003cba: 4b51 ldr r3, [pc, #324] @ (8003e00 <HAL_RCCEx_GetPLL1ClockFreq+0x1e8>)
8003cbc: 6b1b ldr r3, [r3, #48] @ 0x30
8003cbe: f3c3 0308 ubfx r3, r3, #0, #9
8003cc2: ee06 3a90 vmov s13, r3
8003cc6: eef8 6a66 vcvt.f32.u32 s13, s13
8003cca: ed9f 6a4f vldr s12, [pc, #316] @ 8003e08 <HAL_RCCEx_GetPLL1ClockFreq+0x1f0>
8003cce: ee67 7a86 vmul.f32 s15, s15, s12
8003cd2: ee76 7aa7 vadd.f32 s15, s13, s15
8003cd6: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0
8003cda: ee77 7aa6 vadd.f32 s15, s15, s13
8003cde: ee27 7a27 vmul.f32 s14, s14, s15
8003ce2: e01b b.n 8003d1c <HAL_RCCEx_GetPLL1ClockFreq+0x104>
pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
8003ce4: ee07 ca10 vmov s14, ip
8003ce8: eef8 6a47 vcvt.f32.u32 s13, s14
8003cec: ed9f 6a48 vldr s12, [pc, #288] @ 8003e10 <HAL_RCCEx_GetPLL1ClockFreq+0x1f8>
8003cf0: ee86 7a26 vdiv.f32 s14, s12, s13
8003cf4: 4b42 ldr r3, [pc, #264] @ (8003e00 <HAL_RCCEx_GetPLL1ClockFreq+0x1e8>)
8003cf6: 6b1b ldr r3, [r3, #48] @ 0x30
8003cf8: f3c3 0308 ubfx r3, r3, #0, #9
8003cfc: ee06 3a90 vmov s13, r3
8003d00: eef8 6a66 vcvt.f32.u32 s13, s13
8003d04: ed9f 6a40 vldr s12, [pc, #256] @ 8003e08 <HAL_RCCEx_GetPLL1ClockFreq+0x1f0>
8003d08: ee67 7a86 vmul.f32 s15, s15, s12
8003d0c: ee76 7aa7 vadd.f32 s15, s13, s15
8003d10: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0
8003d14: ee77 7aa6 vadd.f32 s15, s15, s13
8003d18: ee27 7a27 vmul.f32 s14, s14, s15
PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + (float_t)1)) ;
8003d1c: 4a38 ldr r2, [pc, #224] @ (8003e00 <HAL_RCCEx_GetPLL1ClockFreq+0x1e8>)
8003d1e: 6b13 ldr r3, [r2, #48] @ 0x30
8003d20: f3c3 2346 ubfx r3, r3, #9, #7
8003d24: ee07 3a90 vmov s15, r3
8003d28: eef8 7a67 vcvt.f32.u32 s15, s15
8003d2c: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0
8003d30: ee77 7aa6 vadd.f32 s15, s15, s13
8003d34: ee87 6a27 vdiv.f32 s12, s14, s15
8003d38: eebc 6ac6 vcvt.u32.f32 s12, s12
8003d3c: ed80 6a00 vstr s12, [r0]
PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_Q1) >> 16) + (float_t)1)) ;
8003d40: 6b13 ldr r3, [r2, #48] @ 0x30
8003d42: f3c3 4306 ubfx r3, r3, #16, #7
8003d46: ee07 3a90 vmov s15, r3
8003d4a: eef8 7a67 vcvt.f32.u32 s15, s15
8003d4e: ee77 7aa6 vadd.f32 s15, s15, s13
8003d52: ee87 6a27 vdiv.f32 s12, s14, s15
8003d56: eebc 6ac6 vcvt.u32.f32 s12, s12
8003d5a: ed80 6a01 vstr s12, [r0, #4]
PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & RCC_PLL1DIVR_R1) >> 24) + (float_t)1)) ;
8003d5e: 6b13 ldr r3, [r2, #48] @ 0x30
8003d60: f3c3 6306 ubfx r3, r3, #24, #7
8003d64: ee07 3a90 vmov s15, r3
8003d68: eef8 7a67 vcvt.f32.u32 s15, s15
8003d6c: ee77 7aa6 vadd.f32 s15, s15, s13
8003d70: eec7 6a27 vdiv.f32 s13, s14, s15
8003d74: eefc 6ae6 vcvt.u32.f32 s13, s13
8003d78: edc0 6a02 vstr s13, [r0, #8]
}
8003d7c: f85d 4b04 ldr.w r4, [sp], #4
8003d80: 4770 bx lr
pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
8003d82: ee07 ca10 vmov s14, ip
8003d86: eef8 6a47 vcvt.f32.u32 s13, s14
8003d8a: ed9f 6a22 vldr s12, [pc, #136] @ 8003e14 <HAL_RCCEx_GetPLL1ClockFreq+0x1fc>
8003d8e: ee86 7a26 vdiv.f32 s14, s12, s13
8003d92: 4b1b ldr r3, [pc, #108] @ (8003e00 <HAL_RCCEx_GetPLL1ClockFreq+0x1e8>)
8003d94: 6b1b ldr r3, [r3, #48] @ 0x30
8003d96: f3c3 0308 ubfx r3, r3, #0, #9
8003d9a: ee06 3a90 vmov s13, r3
8003d9e: eef8 6a66 vcvt.f32.u32 s13, s13
8003da2: ed9f 6a19 vldr s12, [pc, #100] @ 8003e08 <HAL_RCCEx_GetPLL1ClockFreq+0x1f0>
8003da6: ee67 7a86 vmul.f32 s15, s15, s12
8003daa: ee76 7aa7 vadd.f32 s15, s13, s15
8003dae: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0
8003db2: ee77 7aa6 vadd.f32 s15, s15, s13
8003db6: ee27 7a27 vmul.f32 s14, s14, s15
break;
8003dba: e7af b.n 8003d1c <HAL_RCCEx_GetPLL1ClockFreq+0x104>
pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1 / (float_t)0x2000) + (float_t)1);
8003dbc: ee07 ca10 vmov s14, ip
8003dc0: eef8 6a47 vcvt.f32.u32 s13, s14
8003dc4: ed9f 6a11 vldr s12, [pc, #68] @ 8003e0c <HAL_RCCEx_GetPLL1ClockFreq+0x1f4>
8003dc8: ee86 7a26 vdiv.f32 s14, s12, s13
8003dcc: 4b0c ldr r3, [pc, #48] @ (8003e00 <HAL_RCCEx_GetPLL1ClockFreq+0x1e8>)
8003dce: 6b1b ldr r3, [r3, #48] @ 0x30
8003dd0: f3c3 0308 ubfx r3, r3, #0, #9
8003dd4: ee06 3a90 vmov s13, r3
8003dd8: eef8 6a66 vcvt.f32.u32 s13, s13
8003ddc: ed9f 6a0a vldr s12, [pc, #40] @ 8003e08 <HAL_RCCEx_GetPLL1ClockFreq+0x1f0>
8003de0: ee67 7a86 vmul.f32 s15, s15, s12
8003de4: ee76 7aa7 vadd.f32 s15, s13, s15
8003de8: eef7 6a00 vmov.f32 s13, #112 @ 0x3f800000 1.0
8003dec: ee77 7aa6 vadd.f32 s15, s15, s13
8003df0: ee27 7a27 vmul.f32 s14, s14, s15
break;
8003df4: e792 b.n 8003d1c <HAL_RCCEx_GetPLL1ClockFreq+0x104>
PLL1_Clocks->PLL1_P_Frequency = 0U;
8003df6: 2300 movs r3, #0
8003df8: 6003 str r3, [r0, #0]
PLL1_Clocks->PLL1_Q_Frequency = 0U;
8003dfa: 6043 str r3, [r0, #4]
PLL1_Clocks->PLL1_R_Frequency = 0U;
8003dfc: 6083 str r3, [r0, #8]
}
8003dfe: e7bd b.n 8003d7c <HAL_RCCEx_GetPLL1ClockFreq+0x164>
8003e00: 58024400 .word 0x58024400
8003e04: 03d09000 .word 0x03d09000
8003e08: 39000000 .word 0x39000000
8003e0c: 4c742400 .word 0x4c742400
8003e10: 4a742400 .word 0x4a742400
8003e14: 4b742400 .word 0x4b742400
08003e18 <HAL_RCCEx_GetPeriphCLKFreq>:
{
8003e18: b500 push {lr}
8003e1a: b08b sub sp, #44 @ 0x2c
if (PeriphClk == RCC_PERIPHCLK_SAI1)
8003e1c: f5a0 7380 sub.w r3, r0, #256 @ 0x100
8003e20: 430b orrs r3, r1
8003e22: d028 beq.n 8003e76 <HAL_RCCEx_GetPeriphCLKFreq+0x5e>
else if (PeriphClk == RCC_PERIPHCLK_SAI2A)
8003e24: f5a0 7300 sub.w r3, r0, #512 @ 0x200
8003e28: 430b orrs r3, r1
8003e2a: d077 beq.n 8003f1c <HAL_RCCEx_GetPeriphCLKFreq+0x104>
else if (PeriphClk == RCC_PERIPHCLK_SAI2B)
8003e2c: f5a0 6380 sub.w r3, r0, #1024 @ 0x400
8003e30: 430b orrs r3, r1
8003e32: f000 80cb beq.w 8003fcc <HAL_RCCEx_GetPeriphCLKFreq+0x1b4>
else if (PeriphClk == RCC_PERIPHCLK_SPI123)
8003e36: f5a0 5380 sub.w r3, r0, #4096 @ 0x1000
8003e3a: 430b orrs r3, r1
8003e3c: f000 8123 beq.w 8004086 <HAL_RCCEx_GetPeriphCLKFreq+0x26e>
else if (PeriphClk == RCC_PERIPHCLK_SPI45)
8003e40: f5a0 5300 sub.w r3, r0, #8192 @ 0x2000
8003e44: 430b orrs r3, r1
8003e46: f000 8183 beq.w 8004150 <HAL_RCCEx_GetPeriphCLKFreq+0x338>
else if (PeriphClk == RCC_PERIPHCLK_ADC)
8003e4a: f5a0 2300 sub.w r3, r0, #524288 @ 0x80000
8003e4e: 430b orrs r3, r1
8003e50: f000 81cc beq.w 80041ec <HAL_RCCEx_GetPeriphCLKFreq+0x3d4>
else if (PeriphClk == RCC_PERIPHCLK_SDMMC)
8003e54: f5a0 3380 sub.w r3, r0, #65536 @ 0x10000
8003e58: 430b orrs r3, r1
8003e5a: f000 820f beq.w 800427c <HAL_RCCEx_GetPeriphCLKFreq+0x464>
else if (PeriphClk == RCC_PERIPHCLK_SPI6)
8003e5e: f5a0 4380 sub.w r3, r0, #16384 @ 0x4000
8003e62: 430b orrs r3, r1
8003e64: f000 8228 beq.w 80042b8 <HAL_RCCEx_GetPeriphCLKFreq+0x4a0>
else if (PeriphClk == RCC_PERIPHCLK_FDCAN)
8003e68: f5a0 4000 sub.w r0, r0, #32768 @ 0x8000
8003e6c: 4308 orrs r0, r1
8003e6e: f000 827d beq.w 800436c <HAL_RCCEx_GetPeriphCLKFreq+0x554>
frequency = 0;
8003e72: 2000 movs r0, #0
8003e74: e00c b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
saiclocksource = __HAL_RCC_GET_SAI1_SOURCE();
8003e76: 4b94 ldr r3, [pc, #592] @ (80040c8 <HAL_RCCEx_GetPeriphCLKFreq+0x2b0>)
8003e78: 6d1b ldr r3, [r3, #80] @ 0x50
8003e7a: f003 0307 and.w r3, r3, #7
switch (saiclocksource)
8003e7e: 2b04 cmp r3, #4
8003e80: f200 829e bhi.w 80043c0 <HAL_RCCEx_GetPeriphCLKFreq+0x5a8>
8003e84: e8df f003 tbb [pc, r3]
8003e88: 031b1107 .word 0x031b1107
8003e8c: 25 .byte 0x25
8003e8d: 00 .byte 0x00
8003e8e: 488f ldr r0, [pc, #572] @ (80040cc <HAL_RCCEx_GetPeriphCLKFreq+0x2b4>)
}
8003e90: b00b add sp, #44 @ 0x2c
8003e92: f85d fb04 ldr.w pc, [sp], #4
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
8003e96: 4b8c ldr r3, [pc, #560] @ (80040c8 <HAL_RCCEx_GetPeriphCLKFreq+0x2b0>)
8003e98: 6818 ldr r0, [r3, #0]
8003e9a: f010 7000 ands.w r0, r0, #33554432 @ 0x2000000
8003e9e: d0f7 beq.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
8003ea0: a807 add r0, sp, #28
8003ea2: f7ff feb9 bl 8003c18 <HAL_RCCEx_GetPLL1ClockFreq>
frequency = pll1_clocks.PLL1_Q_Frequency;
8003ea6: 9808 ldr r0, [sp, #32]
8003ea8: e7f2 b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
8003eaa: 4b87 ldr r3, [pc, #540] @ (80040c8 <HAL_RCCEx_GetPeriphCLKFreq+0x2b0>)
8003eac: 6818 ldr r0, [r3, #0]
8003eae: f010 6000 ands.w r0, r0, #134217728 @ 0x8000000
8003eb2: d0ed beq.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
8003eb4: a804 add r0, sp, #16
8003eb6: f7ff fcaf bl 8003818 <HAL_RCCEx_GetPLL2ClockFreq>
frequency = pll2_clocks.PLL2_P_Frequency;
8003eba: 9804 ldr r0, [sp, #16]
8003ebc: e7e8 b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
8003ebe: 4b82 ldr r3, [pc, #520] @ (80040c8 <HAL_RCCEx_GetPeriphCLKFreq+0x2b0>)
8003ec0: 6818 ldr r0, [r3, #0]
8003ec2: f010 5000 ands.w r0, r0, #536870912 @ 0x20000000
8003ec6: d0e3 beq.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
8003ec8: a801 add r0, sp, #4
8003eca: f7ff fda5 bl 8003a18 <HAL_RCCEx_GetPLL3ClockFreq>
frequency = pll3_clocks.PLL3_P_Frequency;
8003ece: 9801 ldr r0, [sp, #4]
8003ed0: e7de b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
8003ed2: 4a7d ldr r2, [pc, #500] @ (80040c8 <HAL_RCCEx_GetPeriphCLKFreq+0x2b0>)
8003ed4: 6cd3 ldr r3, [r2, #76] @ 0x4c
8003ed6: f003 5340 and.w r3, r3, #805306368 @ 0x30000000
if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
8003eda: 6812 ldr r2, [r2, #0]
8003edc: f012 0f04 tst.w r2, #4
8003ee0: d007 beq.n 8003ef2 <HAL_RCCEx_GetPeriphCLKFreq+0xda>
8003ee2: b933 cbnz r3, 8003ef2 <HAL_RCCEx_GetPeriphCLKFreq+0xda>
frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
8003ee4: 4b78 ldr r3, [pc, #480] @ (80040c8 <HAL_RCCEx_GetPeriphCLKFreq+0x2b0>)
8003ee6: 681b ldr r3, [r3, #0]
8003ee8: f3c3 03c1 ubfx r3, r3, #3, #2
8003eec: 4878 ldr r0, [pc, #480] @ (80040d0 <HAL_RCCEx_GetPeriphCLKFreq+0x2b8>)
8003eee: 40d8 lsrs r0, r3
8003ef0: e7ce b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
8003ef2: 4a75 ldr r2, [pc, #468] @ (80040c8 <HAL_RCCEx_GetPeriphCLKFreq+0x2b0>)
8003ef4: 6812 ldr r2, [r2, #0]
8003ef6: f412 7f80 tst.w r2, #256 @ 0x100
8003efa: d003 beq.n 8003f04 <HAL_RCCEx_GetPeriphCLKFreq+0xec>
8003efc: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
8003f00: f000 8260 beq.w 80043c4 <HAL_RCCEx_GetPeriphCLKFreq+0x5ac>
else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
8003f04: 4a70 ldr r2, [pc, #448] @ (80040c8 <HAL_RCCEx_GetPeriphCLKFreq+0x2b0>)
8003f06: 6812 ldr r2, [r2, #0]
8003f08: f412 3f00 tst.w r2, #131072 @ 0x20000
8003f0c: f000 825c beq.w 80043c8 <HAL_RCCEx_GetPeriphCLKFreq+0x5b0>
8003f10: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
8003f14: f000 825a beq.w 80043cc <HAL_RCCEx_GetPeriphCLKFreq+0x5b4>
frequency = 0;
8003f18: 2000 movs r0, #0
8003f1a: e7b9 b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
saiclocksource = __HAL_RCC_GET_SAI2A_SOURCE();
8003f1c: 4b6a ldr r3, [pc, #424] @ (80040c8 <HAL_RCCEx_GetPeriphCLKFreq+0x2b0>)
8003f1e: 6d1b ldr r3, [r3, #80] @ 0x50
8003f20: f403 73e0 and.w r3, r3, #448 @ 0x1c0
switch (saiclocksource)
8003f24: 2b80 cmp r3, #128 @ 0x80
8003f26: d031 beq.n 8003f8c <HAL_RCCEx_GetPeriphCLKFreq+0x174>
8003f28: d915 bls.n 8003f56 <HAL_RCCEx_GetPeriphCLKFreq+0x13e>
8003f2a: 2bc0 cmp r3, #192 @ 0xc0
8003f2c: f000 8250 beq.w 80043d0 <HAL_RCCEx_GetPeriphCLKFreq+0x5b8>
8003f30: f5b3 7f80 cmp.w r3, #256 @ 0x100
8003f34: d11e bne.n 8003f74 <HAL_RCCEx_GetPeriphCLKFreq+0x15c>
ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
8003f36: 4a64 ldr r2, [pc, #400] @ (80040c8 <HAL_RCCEx_GetPeriphCLKFreq+0x2b0>)
8003f38: 6cd3 ldr r3, [r2, #76] @ 0x4c
8003f3a: f003 5340 and.w r3, r3, #805306368 @ 0x30000000
if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
8003f3e: 6812 ldr r2, [r2, #0]
8003f40: f012 0f04 tst.w r2, #4
8003f44: d02d beq.n 8003fa2 <HAL_RCCEx_GetPeriphCLKFreq+0x18a>
8003f46: bb63 cbnz r3, 8003fa2 <HAL_RCCEx_GetPeriphCLKFreq+0x18a>
frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
8003f48: 4b5f ldr r3, [pc, #380] @ (80040c8 <HAL_RCCEx_GetPeriphCLKFreq+0x2b0>)
8003f4a: 681b ldr r3, [r3, #0]
8003f4c: f3c3 03c1 ubfx r3, r3, #3, #2
8003f50: 485f ldr r0, [pc, #380] @ (80040d0 <HAL_RCCEx_GetPeriphCLKFreq+0x2b8>)
8003f52: 40d8 lsrs r0, r3
8003f54: e79c b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
switch (saiclocksource)
8003f56: b17b cbz r3, 8003f78 <HAL_RCCEx_GetPeriphCLKFreq+0x160>
8003f58: 2b40 cmp r3, #64 @ 0x40
8003f5a: d109 bne.n 8003f70 <HAL_RCCEx_GetPeriphCLKFreq+0x158>
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
8003f5c: 4b5a ldr r3, [pc, #360] @ (80040c8 <HAL_RCCEx_GetPeriphCLKFreq+0x2b0>)
8003f5e: 6818 ldr r0, [r3, #0]
8003f60: f010 6000 ands.w r0, r0, #134217728 @ 0x8000000
8003f64: d094 beq.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
8003f66: a804 add r0, sp, #16
8003f68: f7ff fc56 bl 8003818 <HAL_RCCEx_GetPLL2ClockFreq>
frequency = pll2_clocks.PLL2_P_Frequency;
8003f6c: 9804 ldr r0, [sp, #16]
8003f6e: e78f b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
frequency = 0;
8003f70: 2000 movs r0, #0
8003f72: e78d b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
8003f74: 2000 movs r0, #0
8003f76: e78b b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
8003f78: 4b53 ldr r3, [pc, #332] @ (80040c8 <HAL_RCCEx_GetPeriphCLKFreq+0x2b0>)
8003f7a: 6818 ldr r0, [r3, #0]
8003f7c: f010 7000 ands.w r0, r0, #33554432 @ 0x2000000
8003f80: d086 beq.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
8003f82: a807 add r0, sp, #28
8003f84: f7ff fe48 bl 8003c18 <HAL_RCCEx_GetPLL1ClockFreq>
frequency = pll1_clocks.PLL1_Q_Frequency;
8003f88: 9808 ldr r0, [sp, #32]
8003f8a: e781 b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
8003f8c: 4b4e ldr r3, [pc, #312] @ (80040c8 <HAL_RCCEx_GetPeriphCLKFreq+0x2b0>)
8003f8e: 6818 ldr r0, [r3, #0]
8003f90: f010 5000 ands.w r0, r0, #536870912 @ 0x20000000
8003f94: f43f af7c beq.w 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
8003f98: a801 add r0, sp, #4
8003f9a: f7ff fd3d bl 8003a18 <HAL_RCCEx_GetPLL3ClockFreq>
frequency = pll3_clocks.PLL3_P_Frequency;
8003f9e: 9801 ldr r0, [sp, #4]
8003fa0: e776 b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
8003fa2: 4a49 ldr r2, [pc, #292] @ (80040c8 <HAL_RCCEx_GetPeriphCLKFreq+0x2b0>)
8003fa4: 6812 ldr r2, [r2, #0]
8003fa6: f412 7f80 tst.w r2, #256 @ 0x100
8003faa: d003 beq.n 8003fb4 <HAL_RCCEx_GetPeriphCLKFreq+0x19c>
8003fac: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
8003fb0: f000 8210 beq.w 80043d4 <HAL_RCCEx_GetPeriphCLKFreq+0x5bc>
else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
8003fb4: 4a44 ldr r2, [pc, #272] @ (80040c8 <HAL_RCCEx_GetPeriphCLKFreq+0x2b0>)
8003fb6: 6812 ldr r2, [r2, #0]
8003fb8: f412 3f00 tst.w r2, #131072 @ 0x20000
8003fbc: f000 820c beq.w 80043d8 <HAL_RCCEx_GetPeriphCLKFreq+0x5c0>
8003fc0: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
8003fc4: f000 820a beq.w 80043dc <HAL_RCCEx_GetPeriphCLKFreq+0x5c4>
frequency = 0;
8003fc8: 2000 movs r0, #0
8003fca: e761 b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
saiclocksource = __HAL_RCC_GET_SAI2B_SOURCE();
8003fcc: 4b3e ldr r3, [pc, #248] @ (80040c8 <HAL_RCCEx_GetPeriphCLKFreq+0x2b0>)
8003fce: 6d1b ldr r3, [r3, #80] @ 0x50
8003fd0: f403 6360 and.w r3, r3, #3584 @ 0xe00
switch (saiclocksource)
8003fd4: f5b3 6f80 cmp.w r3, #1024 @ 0x400
8003fd8: d035 beq.n 8004046 <HAL_RCCEx_GetPeriphCLKFreq+0x22e>
8003fda: d916 bls.n 800400a <HAL_RCCEx_GetPeriphCLKFreq+0x1f2>
8003fdc: f5b3 6fc0 cmp.w r3, #1536 @ 0x600
8003fe0: f000 81fe beq.w 80043e0 <HAL_RCCEx_GetPeriphCLKFreq+0x5c8>
8003fe4: f5b3 6f00 cmp.w r3, #2048 @ 0x800
8003fe8: d120 bne.n 800402c <HAL_RCCEx_GetPeriphCLKFreq+0x214>
ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
8003fea: 4a37 ldr r2, [pc, #220] @ (80040c8 <HAL_RCCEx_GetPeriphCLKFreq+0x2b0>)
8003fec: 6cd3 ldr r3, [r2, #76] @ 0x4c
8003fee: f003 5340 and.w r3, r3, #805306368 @ 0x30000000
if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
8003ff2: 6812 ldr r2, [r2, #0]
8003ff4: f012 0f04 tst.w r2, #4
8003ff8: d030 beq.n 800405c <HAL_RCCEx_GetPeriphCLKFreq+0x244>
8003ffa: bb7b cbnz r3, 800405c <HAL_RCCEx_GetPeriphCLKFreq+0x244>
frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
8003ffc: 4b32 ldr r3, [pc, #200] @ (80040c8 <HAL_RCCEx_GetPeriphCLKFreq+0x2b0>)
8003ffe: 681b ldr r3, [r3, #0]
8004000: f3c3 03c1 ubfx r3, r3, #3, #2
8004004: 4832 ldr r0, [pc, #200] @ (80040d0 <HAL_RCCEx_GetPeriphCLKFreq+0x2b8>)
8004006: 40d8 lsrs r0, r3
8004008: e742 b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
switch (saiclocksource)
800400a: b18b cbz r3, 8004030 <HAL_RCCEx_GetPeriphCLKFreq+0x218>
800400c: f5b3 7f00 cmp.w r3, #512 @ 0x200
8004010: d10a bne.n 8004028 <HAL_RCCEx_GetPeriphCLKFreq+0x210>
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
8004012: 4b2d ldr r3, [pc, #180] @ (80040c8 <HAL_RCCEx_GetPeriphCLKFreq+0x2b0>)
8004014: 6818 ldr r0, [r3, #0]
8004016: f010 6000 ands.w r0, r0, #134217728 @ 0x8000000
800401a: f43f af39 beq.w 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
800401e: a804 add r0, sp, #16
8004020: f7ff fbfa bl 8003818 <HAL_RCCEx_GetPLL2ClockFreq>
frequency = pll2_clocks.PLL2_P_Frequency;
8004024: 9804 ldr r0, [sp, #16]
8004026: e733 b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
frequency = 0;
8004028: 2000 movs r0, #0
800402a: e731 b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
800402c: 2000 movs r0, #0
800402e: e72f b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
8004030: 4b25 ldr r3, [pc, #148] @ (80040c8 <HAL_RCCEx_GetPeriphCLKFreq+0x2b0>)
8004032: 6818 ldr r0, [r3, #0]
8004034: f010 7000 ands.w r0, r0, #33554432 @ 0x2000000
8004038: f43f af2a beq.w 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
800403c: a807 add r0, sp, #28
800403e: f7ff fdeb bl 8003c18 <HAL_RCCEx_GetPLL1ClockFreq>
frequency = pll1_clocks.PLL1_Q_Frequency;
8004042: 9808 ldr r0, [sp, #32]
8004044: e724 b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
8004046: 4b20 ldr r3, [pc, #128] @ (80040c8 <HAL_RCCEx_GetPeriphCLKFreq+0x2b0>)
8004048: 6818 ldr r0, [r3, #0]
800404a: f010 5000 ands.w r0, r0, #536870912 @ 0x20000000
800404e: f43f af1f beq.w 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
8004052: a801 add r0, sp, #4
8004054: f7ff fce0 bl 8003a18 <HAL_RCCEx_GetPLL3ClockFreq>
frequency = pll3_clocks.PLL3_P_Frequency;
8004058: 9801 ldr r0, [sp, #4]
800405a: e719 b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
800405c: 4a1a ldr r2, [pc, #104] @ (80040c8 <HAL_RCCEx_GetPeriphCLKFreq+0x2b0>)
800405e: 6812 ldr r2, [r2, #0]
8004060: f412 7f80 tst.w r2, #256 @ 0x100
8004064: d003 beq.n 800406e <HAL_RCCEx_GetPeriphCLKFreq+0x256>
8004066: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
800406a: f000 81bb beq.w 80043e4 <HAL_RCCEx_GetPeriphCLKFreq+0x5cc>
else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
800406e: 4a16 ldr r2, [pc, #88] @ (80040c8 <HAL_RCCEx_GetPeriphCLKFreq+0x2b0>)
8004070: 6812 ldr r2, [r2, #0]
8004072: f412 3f00 tst.w r2, #131072 @ 0x20000
8004076: f000 81b7 beq.w 80043e8 <HAL_RCCEx_GetPeriphCLKFreq+0x5d0>
800407a: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
800407e: f000 81b5 beq.w 80043ec <HAL_RCCEx_GetPeriphCLKFreq+0x5d4>
frequency = 0;
8004082: 2000 movs r0, #0
8004084: e704 b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
srcclk = __HAL_RCC_GET_SPI123_SOURCE();
8004086: 4b10 ldr r3, [pc, #64] @ (80040c8 <HAL_RCCEx_GetPeriphCLKFreq+0x2b0>)
8004088: 6d1b ldr r3, [r3, #80] @ 0x50
800408a: f403 43e0 and.w r3, r3, #28672 @ 0x7000
switch (srcclk)
800408e: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
8004092: d03d beq.n 8004110 <HAL_RCCEx_GetPeriphCLKFreq+0x2f8>
8004094: d91e bls.n 80040d4 <HAL_RCCEx_GetPeriphCLKFreq+0x2bc>
8004096: f5b3 5f40 cmp.w r3, #12288 @ 0x3000
800409a: f000 81a9 beq.w 80043f0 <HAL_RCCEx_GetPeriphCLKFreq+0x5d8>
800409e: f5b3 4f80 cmp.w r3, #16384 @ 0x4000
80040a2: d128 bne.n 80040f6 <HAL_RCCEx_GetPeriphCLKFreq+0x2de>
ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
80040a4: 4a08 ldr r2, [pc, #32] @ (80040c8 <HAL_RCCEx_GetPeriphCLKFreq+0x2b0>)
80040a6: 6cd3 ldr r3, [r2, #76] @ 0x4c
80040a8: f003 5340 and.w r3, r3, #805306368 @ 0x30000000
if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
80040ac: 6812 ldr r2, [r2, #0]
80040ae: f012 0f04 tst.w r2, #4
80040b2: d038 beq.n 8004126 <HAL_RCCEx_GetPeriphCLKFreq+0x30e>
80040b4: 2b00 cmp r3, #0
80040b6: d136 bne.n 8004126 <HAL_RCCEx_GetPeriphCLKFreq+0x30e>
frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
80040b8: 4b03 ldr r3, [pc, #12] @ (80040c8 <HAL_RCCEx_GetPeriphCLKFreq+0x2b0>)
80040ba: 681b ldr r3, [r3, #0]
80040bc: f3c3 03c1 ubfx r3, r3, #3, #2
80040c0: 4803 ldr r0, [pc, #12] @ (80040d0 <HAL_RCCEx_GetPeriphCLKFreq+0x2b8>)
80040c2: 40d8 lsrs r0, r3
80040c4: e6e4 b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
80040c6: bf00 nop
80040c8: 58024400 .word 0x58024400
80040cc: 00bb8000 .word 0x00bb8000
80040d0: 03d09000 .word 0x03d09000
switch (srcclk)
80040d4: b18b cbz r3, 80040fa <HAL_RCCEx_GetPeriphCLKFreq+0x2e2>
80040d6: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
80040da: d10a bne.n 80040f2 <HAL_RCCEx_GetPeriphCLKFreq+0x2da>
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
80040dc: 4b9f ldr r3, [pc, #636] @ (800435c <HAL_RCCEx_GetPeriphCLKFreq+0x544>)
80040de: 6818 ldr r0, [r3, #0]
80040e0: f010 6000 ands.w r0, r0, #134217728 @ 0x8000000
80040e4: f43f aed4 beq.w 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
80040e8: a804 add r0, sp, #16
80040ea: f7ff fb95 bl 8003818 <HAL_RCCEx_GetPLL2ClockFreq>
frequency = pll2_clocks.PLL2_P_Frequency;
80040ee: 9804 ldr r0, [sp, #16]
80040f0: e6ce b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
frequency = 0;
80040f2: 2000 movs r0, #0
80040f4: e6cc b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
80040f6: 2000 movs r0, #0
80040f8: e6ca b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
80040fa: 4b98 ldr r3, [pc, #608] @ (800435c <HAL_RCCEx_GetPeriphCLKFreq+0x544>)
80040fc: 6818 ldr r0, [r3, #0]
80040fe: f010 7000 ands.w r0, r0, #33554432 @ 0x2000000
8004102: f43f aec5 beq.w 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
8004106: a807 add r0, sp, #28
8004108: f7ff fd86 bl 8003c18 <HAL_RCCEx_GetPLL1ClockFreq>
frequency = pll1_clocks.PLL1_Q_Frequency;
800410c: 9808 ldr r0, [sp, #32]
800410e: e6bf b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
8004110: 4b92 ldr r3, [pc, #584] @ (800435c <HAL_RCCEx_GetPeriphCLKFreq+0x544>)
8004112: 6818 ldr r0, [r3, #0]
8004114: f010 5000 ands.w r0, r0, #536870912 @ 0x20000000
8004118: f43f aeba beq.w 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
800411c: a801 add r0, sp, #4
800411e: f7ff fc7b bl 8003a18 <HAL_RCCEx_GetPLL3ClockFreq>
frequency = pll3_clocks.PLL3_P_Frequency;
8004122: 9801 ldr r0, [sp, #4]
8004124: e6b4 b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
8004126: 4a8d ldr r2, [pc, #564] @ (800435c <HAL_RCCEx_GetPeriphCLKFreq+0x544>)
8004128: 6812 ldr r2, [r2, #0]
800412a: f412 7f80 tst.w r2, #256 @ 0x100
800412e: d003 beq.n 8004138 <HAL_RCCEx_GetPeriphCLKFreq+0x320>
8004130: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
8004134: f000 815e beq.w 80043f4 <HAL_RCCEx_GetPeriphCLKFreq+0x5dc>
else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
8004138: 4a88 ldr r2, [pc, #544] @ (800435c <HAL_RCCEx_GetPeriphCLKFreq+0x544>)
800413a: 6812 ldr r2, [r2, #0]
800413c: f412 3f00 tst.w r2, #131072 @ 0x20000
8004140: f000 815a beq.w 80043f8 <HAL_RCCEx_GetPeriphCLKFreq+0x5e0>
8004144: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
8004148: f000 8158 beq.w 80043fc <HAL_RCCEx_GetPeriphCLKFreq+0x5e4>
frequency = 0;
800414c: 2000 movs r0, #0
800414e: e69f b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
srcclk = __HAL_RCC_GET_SPI45_SOURCE();
8004150: 4b82 ldr r3, [pc, #520] @ (800435c <HAL_RCCEx_GetPeriphCLKFreq+0x544>)
8004152: 6d1b ldr r3, [r3, #80] @ 0x50
8004154: f403 23e0 and.w r3, r3, #458752 @ 0x70000
switch (srcclk)
8004158: f5b3 3f40 cmp.w r3, #196608 @ 0x30000
800415c: d032 beq.n 80041c4 <HAL_RCCEx_GetPeriphCLKFreq+0x3ac>
800415e: d80b bhi.n 8004178 <HAL_RCCEx_GetPeriphCLKFreq+0x360>
8004160: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8004164: d018 beq.n 8004198 <HAL_RCCEx_GetPeriphCLKFreq+0x380>
8004166: f5b3 3f00 cmp.w r3, #131072 @ 0x20000
800416a: d020 beq.n 80041ae <HAL_RCCEx_GetPeriphCLKFreq+0x396>
800416c: b913 cbnz r3, 8004174 <HAL_RCCEx_GetPeriphCLKFreq+0x35c>
frequency = HAL_RCC_GetPCLK1Freq();
800416e: f7fe fcfd bl 8002b6c <HAL_RCC_GetPCLK1Freq>
break;
8004172: e68d b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
switch (srcclk)
8004174: 2000 movs r0, #0
8004176: e68b b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
8004178: f5b3 2f80 cmp.w r3, #262144 @ 0x40000
800417c: d02e beq.n 80041dc <HAL_RCCEx_GetPeriphCLKFreq+0x3c4>
800417e: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
8004182: d107 bne.n 8004194 <HAL_RCCEx_GetPeriphCLKFreq+0x37c>
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
8004184: 4b75 ldr r3, [pc, #468] @ (800435c <HAL_RCCEx_GetPeriphCLKFreq+0x544>)
8004186: 6818 ldr r0, [r3, #0]
8004188: f410 3000 ands.w r0, r0, #131072 @ 0x20000
800418c: f43f ae80 beq.w 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
frequency = HSE_VALUE;
8004190: 4873 ldr r0, [pc, #460] @ (8004360 <HAL_RCCEx_GetPeriphCLKFreq+0x548>)
8004192: e67d b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
switch (srcclk)
8004194: 2000 movs r0, #0
8004196: e67b b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
8004198: 4b70 ldr r3, [pc, #448] @ (800435c <HAL_RCCEx_GetPeriphCLKFreq+0x544>)
800419a: 6818 ldr r0, [r3, #0]
800419c: f010 6000 ands.w r0, r0, #134217728 @ 0x8000000
80041a0: f43f ae76 beq.w 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
80041a4: a804 add r0, sp, #16
80041a6: f7ff fb37 bl 8003818 <HAL_RCCEx_GetPLL2ClockFreq>
frequency = pll2_clocks.PLL2_Q_Frequency;
80041aa: 9805 ldr r0, [sp, #20]
80041ac: e670 b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
80041ae: 4b6b ldr r3, [pc, #428] @ (800435c <HAL_RCCEx_GetPeriphCLKFreq+0x544>)
80041b0: 6818 ldr r0, [r3, #0]
80041b2: f010 5000 ands.w r0, r0, #536870912 @ 0x20000000
80041b6: f43f ae6b beq.w 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
80041ba: a801 add r0, sp, #4
80041bc: f7ff fc2c bl 8003a18 <HAL_RCCEx_GetPLL3ClockFreq>
frequency = pll3_clocks.PLL3_Q_Frequency;
80041c0: 9802 ldr r0, [sp, #8]
80041c2: e665 b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
80041c4: 4b65 ldr r3, [pc, #404] @ (800435c <HAL_RCCEx_GetPeriphCLKFreq+0x544>)
80041c6: 6818 ldr r0, [r3, #0]
80041c8: f010 0004 ands.w r0, r0, #4
80041cc: f43f ae60 beq.w 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
80041d0: 681b ldr r3, [r3, #0]
80041d2: f3c3 03c1 ubfx r3, r3, #3, #2
80041d6: 4863 ldr r0, [pc, #396] @ (8004364 <HAL_RCCEx_GetPeriphCLKFreq+0x54c>)
80041d8: 40d8 lsrs r0, r3
80041da: e659 b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY))
80041dc: 4b5f ldr r3, [pc, #380] @ (800435c <HAL_RCCEx_GetPeriphCLKFreq+0x544>)
80041de: 6818 ldr r0, [r3, #0]
80041e0: f410 7080 ands.w r0, r0, #256 @ 0x100
80041e4: f43f ae54 beq.w 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
frequency = CSI_VALUE;
80041e8: 485f ldr r0, [pc, #380] @ (8004368 <HAL_RCCEx_GetPeriphCLKFreq+0x550>)
80041ea: e651 b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
srcclk = __HAL_RCC_GET_ADC_SOURCE();
80041ec: 4b5b ldr r3, [pc, #364] @ (800435c <HAL_RCCEx_GetPeriphCLKFreq+0x544>)
80041ee: 6d9b ldr r3, [r3, #88] @ 0x58
80041f0: f403 3340 and.w r3, r3, #196608 @ 0x30000
switch (srcclk)
80041f4: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
80041f8: d010 beq.n 800421c <HAL_RCCEx_GetPeriphCLKFreq+0x404>
80041fa: f5b3 3f00 cmp.w r3, #131072 @ 0x20000
80041fe: d018 beq.n 8004232 <HAL_RCCEx_GetPeriphCLKFreq+0x41a>
8004200: 2b00 cmp r3, #0
8004202: f040 80fd bne.w 8004400 <HAL_RCCEx_GetPeriphCLKFreq+0x5e8>
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
8004206: 4b55 ldr r3, [pc, #340] @ (800435c <HAL_RCCEx_GetPeriphCLKFreq+0x544>)
8004208: 6818 ldr r0, [r3, #0]
800420a: f010 6000 ands.w r0, r0, #134217728 @ 0x8000000
800420e: f43f ae3f beq.w 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
8004212: a804 add r0, sp, #16
8004214: f7ff fb00 bl 8003818 <HAL_RCCEx_GetPLL2ClockFreq>
frequency = pll2_clocks.PLL2_P_Frequency;
8004218: 9804 ldr r0, [sp, #16]
800421a: e639 b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
800421c: 4b4f ldr r3, [pc, #316] @ (800435c <HAL_RCCEx_GetPeriphCLKFreq+0x544>)
800421e: 6818 ldr r0, [r3, #0]
8004220: f010 5000 ands.w r0, r0, #536870912 @ 0x20000000
8004224: f43f ae34 beq.w 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
8004228: a801 add r0, sp, #4
800422a: f7ff fbf5 bl 8003a18 <HAL_RCCEx_GetPLL3ClockFreq>
frequency = pll3_clocks.PLL3_R_Frequency;
800422e: 9803 ldr r0, [sp, #12]
8004230: e62e b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
ckpclocksource = __HAL_RCC_GET_CLKP_SOURCE();
8004232: 4a4a ldr r2, [pc, #296] @ (800435c <HAL_RCCEx_GetPeriphCLKFreq+0x544>)
8004234: 6cd3 ldr r3, [r2, #76] @ 0x4c
8004236: f003 5340 and.w r3, r3, #805306368 @ 0x30000000
if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI))
800423a: 6812 ldr r2, [r2, #0]
800423c: f012 0f04 tst.w r2, #4
8004240: d007 beq.n 8004252 <HAL_RCCEx_GetPeriphCLKFreq+0x43a>
8004242: b933 cbnz r3, 8004252 <HAL_RCCEx_GetPeriphCLKFreq+0x43a>
frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
8004244: 4b45 ldr r3, [pc, #276] @ (800435c <HAL_RCCEx_GetPeriphCLKFreq+0x544>)
8004246: 681b ldr r3, [r3, #0]
8004248: f3c3 03c1 ubfx r3, r3, #3, #2
800424c: 4845 ldr r0, [pc, #276] @ (8004364 <HAL_RCCEx_GetPeriphCLKFreq+0x54c>)
800424e: 40d8 lsrs r0, r3
8004250: e61e b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI))
8004252: 4a42 ldr r2, [pc, #264] @ (800435c <HAL_RCCEx_GetPeriphCLKFreq+0x544>)
8004254: 6812 ldr r2, [r2, #0]
8004256: f412 7f80 tst.w r2, #256 @ 0x100
800425a: d003 beq.n 8004264 <HAL_RCCEx_GetPeriphCLKFreq+0x44c>
800425c: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
8004260: f000 80d0 beq.w 8004404 <HAL_RCCEx_GetPeriphCLKFreq+0x5ec>
else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE))
8004264: 4a3d ldr r2, [pc, #244] @ (800435c <HAL_RCCEx_GetPeriphCLKFreq+0x544>)
8004266: 6812 ldr r2, [r2, #0]
8004268: f412 3f00 tst.w r2, #131072 @ 0x20000
800426c: f000 80cc beq.w 8004408 <HAL_RCCEx_GetPeriphCLKFreq+0x5f0>
8004270: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
8004274: f000 80ca beq.w 800440c <HAL_RCCEx_GetPeriphCLKFreq+0x5f4>
frequency = 0;
8004278: 2000 movs r0, #0
800427a: e609 b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
srcclk = __HAL_RCC_GET_SDMMC_SOURCE();
800427c: 4b37 ldr r3, [pc, #220] @ (800435c <HAL_RCCEx_GetPeriphCLKFreq+0x544>)
800427e: 6cdb ldr r3, [r3, #76] @ 0x4c
switch (srcclk)
8004280: f413 3380 ands.w r3, r3, #65536 @ 0x10000
8004284: d002 beq.n 800428c <HAL_RCCEx_GetPeriphCLKFreq+0x474>
8004286: b963 cbnz r3, 80042a2 <HAL_RCCEx_GetPeriphCLKFreq+0x48a>
8004288: 2000 movs r0, #0
800428a: e601 b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
800428c: 4b33 ldr r3, [pc, #204] @ (800435c <HAL_RCCEx_GetPeriphCLKFreq+0x544>)
800428e: 6818 ldr r0, [r3, #0]
8004290: f010 7000 ands.w r0, r0, #33554432 @ 0x2000000
8004294: f43f adfc beq.w 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
8004298: a807 add r0, sp, #28
800429a: f7ff fcbd bl 8003c18 <HAL_RCCEx_GetPLL1ClockFreq>
frequency = pll1_clocks.PLL1_Q_Frequency;
800429e: 9808 ldr r0, [sp, #32]
80042a0: e5f6 b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
80042a2: 4b2e ldr r3, [pc, #184] @ (800435c <HAL_RCCEx_GetPeriphCLKFreq+0x544>)
80042a4: 6818 ldr r0, [r3, #0]
80042a6: f010 6000 ands.w r0, r0, #134217728 @ 0x8000000
80042aa: f43f adf1 beq.w 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
80042ae: a804 add r0, sp, #16
80042b0: f7ff fab2 bl 8003818 <HAL_RCCEx_GetPLL2ClockFreq>
frequency = pll2_clocks.PLL2_R_Frequency;
80042b4: 9806 ldr r0, [sp, #24]
80042b6: e5eb b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
srcclk = __HAL_RCC_GET_SPI6_SOURCE();
80042b8: 4b28 ldr r3, [pc, #160] @ (800435c <HAL_RCCEx_GetPeriphCLKFreq+0x544>)
80042ba: 6d9b ldr r3, [r3, #88] @ 0x58
80042bc: f003 43e0 and.w r3, r3, #1879048192 @ 0x70000000
switch (srcclk)
80042c0: f1b3 5f40 cmp.w r3, #805306368 @ 0x30000000
80042c4: d036 beq.n 8004334 <HAL_RCCEx_GetPeriphCLKFreq+0x51c>
80042c6: d80b bhi.n 80042e0 <HAL_RCCEx_GetPeriphCLKFreq+0x4c8>
80042c8: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
80042cc: d01c beq.n 8004308 <HAL_RCCEx_GetPeriphCLKFreq+0x4f0>
80042ce: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
80042d2: d024 beq.n 800431e <HAL_RCCEx_GetPeriphCLKFreq+0x506>
80042d4: b913 cbnz r3, 80042dc <HAL_RCCEx_GetPeriphCLKFreq+0x4c4>
frequency = HAL_RCCEx_GetD3PCLK1Freq();
80042d6: f7ff fa8d bl 80037f4 <HAL_RCCEx_GetD3PCLK1Freq>
break;
80042da: e5d9 b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
frequency = 0;
80042dc: 2000 movs r0, #0
80042de: e5d7 b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
switch (srcclk)
80042e0: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
80042e4: d032 beq.n 800434c <HAL_RCCEx_GetPeriphCLKFreq+0x534>
80042e6: f1b3 4fc0 cmp.w r3, #1610612736 @ 0x60000000
80042ea: f000 8091 beq.w 8004410 <HAL_RCCEx_GetPeriphCLKFreq+0x5f8>
80042ee: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
80042f2: d107 bne.n 8004304 <HAL_RCCEx_GetPeriphCLKFreq+0x4ec>
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY))
80042f4: 4b19 ldr r3, [pc, #100] @ (800435c <HAL_RCCEx_GetPeriphCLKFreq+0x544>)
80042f6: 6818 ldr r0, [r3, #0]
80042f8: f410 7080 ands.w r0, r0, #256 @ 0x100
80042fc: f43f adc8 beq.w 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
frequency = CSI_VALUE;
8004300: 4819 ldr r0, [pc, #100] @ (8004368 <HAL_RCCEx_GetPeriphCLKFreq+0x550>)
8004302: e5c5 b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
frequency = 0;
8004304: 2000 movs r0, #0
8004306: e5c3 b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
8004308: 4b14 ldr r3, [pc, #80] @ (800435c <HAL_RCCEx_GetPeriphCLKFreq+0x544>)
800430a: 6818 ldr r0, [r3, #0]
800430c: f010 6000 ands.w r0, r0, #134217728 @ 0x8000000
8004310: f43f adbe beq.w 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
8004314: a804 add r0, sp, #16
8004316: f7ff fa7f bl 8003818 <HAL_RCCEx_GetPLL2ClockFreq>
frequency = pll2_clocks.PLL2_Q_Frequency;
800431a: 9805 ldr r0, [sp, #20]
800431c: e5b8 b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY))
800431e: 4b0f ldr r3, [pc, #60] @ (800435c <HAL_RCCEx_GetPeriphCLKFreq+0x544>)
8004320: 6818 ldr r0, [r3, #0]
8004322: f010 5000 ands.w r0, r0, #536870912 @ 0x20000000
8004326: f43f adb3 beq.w 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks);
800432a: a801 add r0, sp, #4
800432c: f7ff fb74 bl 8003a18 <HAL_RCCEx_GetPLL3ClockFreq>
frequency = pll3_clocks.PLL3_Q_Frequency;
8004330: 9802 ldr r0, [sp, #8]
8004332: e5ad b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY))
8004334: 4b09 ldr r3, [pc, #36] @ (800435c <HAL_RCCEx_GetPeriphCLKFreq+0x544>)
8004336: 6818 ldr r0, [r3, #0]
8004338: f010 0004 ands.w r0, r0, #4
800433c: f43f ada8 beq.w 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3));
8004340: 681b ldr r3, [r3, #0]
8004342: f3c3 03c1 ubfx r3, r3, #3, #2
8004346: 4807 ldr r0, [pc, #28] @ (8004364 <HAL_RCCEx_GetPeriphCLKFreq+0x54c>)
8004348: 40d8 lsrs r0, r3
800434a: e5a1 b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
800434c: 4b03 ldr r3, [pc, #12] @ (800435c <HAL_RCCEx_GetPeriphCLKFreq+0x544>)
800434e: 6818 ldr r0, [r3, #0]
8004350: f410 3000 ands.w r0, r0, #131072 @ 0x20000
8004354: f43f ad9c beq.w 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
frequency = HSE_VALUE;
8004358: 4801 ldr r0, [pc, #4] @ (8004360 <HAL_RCCEx_GetPeriphCLKFreq+0x548>)
800435a: e599 b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
800435c: 58024400 .word 0x58024400
8004360: 00f42400 .word 0x00f42400
8004364: 03d09000 .word 0x03d09000
8004368: 003d0900 .word 0x003d0900
srcclk = __HAL_RCC_GET_FDCAN_SOURCE();
800436c: 4b2a ldr r3, [pc, #168] @ (8004418 <HAL_RCCEx_GetPeriphCLKFreq+0x600>)
800436e: 6d1b ldr r3, [r3, #80] @ 0x50
8004370: f003 5340 and.w r3, r3, #805306368 @ 0x30000000
switch (srcclk)
8004374: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
8004378: d00c beq.n 8004394 <HAL_RCCEx_GetPeriphCLKFreq+0x57c>
800437a: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
800437e: d014 beq.n 80043aa <HAL_RCCEx_GetPeriphCLKFreq+0x592>
8004380: 2b00 cmp r3, #0
8004382: d147 bne.n 8004414 <HAL_RCCEx_GetPeriphCLKFreq+0x5fc>
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
8004384: 4b24 ldr r3, [pc, #144] @ (8004418 <HAL_RCCEx_GetPeriphCLKFreq+0x600>)
8004386: 6818 ldr r0, [r3, #0]
8004388: f410 3000 ands.w r0, r0, #131072 @ 0x20000
800438c: f43f ad80 beq.w 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
frequency = HSE_VALUE;
8004390: 4822 ldr r0, [pc, #136] @ (800441c <HAL_RCCEx_GetPeriphCLKFreq+0x604>)
8004392: e57d b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY))
8004394: 4b20 ldr r3, [pc, #128] @ (8004418 <HAL_RCCEx_GetPeriphCLKFreq+0x600>)
8004396: 6818 ldr r0, [r3, #0]
8004398: f010 7000 ands.w r0, r0, #33554432 @ 0x2000000
800439c: f43f ad78 beq.w 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks);
80043a0: a807 add r0, sp, #28
80043a2: f7ff fc39 bl 8003c18 <HAL_RCCEx_GetPLL1ClockFreq>
frequency = pll1_clocks.PLL1_Q_Frequency;
80043a6: 9808 ldr r0, [sp, #32]
80043a8: e572 b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY))
80043aa: 4b1b ldr r3, [pc, #108] @ (8004418 <HAL_RCCEx_GetPeriphCLKFreq+0x600>)
80043ac: 6818 ldr r0, [r3, #0]
80043ae: f010 6000 ands.w r0, r0, #134217728 @ 0x8000000
80043b2: f43f ad6d beq.w 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks);
80043b6: a804 add r0, sp, #16
80043b8: f7ff fa2e bl 8003818 <HAL_RCCEx_GetPLL2ClockFreq>
frequency = pll2_clocks.PLL2_Q_Frequency;
80043bc: 9805 ldr r0, [sp, #20]
80043be: e567 b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
frequency = 0;
80043c0: 2000 movs r0, #0
80043c2: e565 b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
frequency = CSI_VALUE;
80043c4: 4816 ldr r0, [pc, #88] @ (8004420 <HAL_RCCEx_GetPeriphCLKFreq+0x608>)
80043c6: e563 b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
frequency = 0;
80043c8: 2000 movs r0, #0
80043ca: e561 b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
frequency = HSE_VALUE;
80043cc: 4813 ldr r0, [pc, #76] @ (800441c <HAL_RCCEx_GetPeriphCLKFreq+0x604>)
80043ce: e55f b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
switch (saiclocksource)
80043d0: 4814 ldr r0, [pc, #80] @ (8004424 <HAL_RCCEx_GetPeriphCLKFreq+0x60c>)
80043d2: e55d b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
frequency = CSI_VALUE;
80043d4: 4812 ldr r0, [pc, #72] @ (8004420 <HAL_RCCEx_GetPeriphCLKFreq+0x608>)
80043d6: e55b b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
frequency = 0;
80043d8: 2000 movs r0, #0
80043da: e559 b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
frequency = HSE_VALUE;
80043dc: 480f ldr r0, [pc, #60] @ (800441c <HAL_RCCEx_GetPeriphCLKFreq+0x604>)
80043de: e557 b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
switch (saiclocksource)
80043e0: 4810 ldr r0, [pc, #64] @ (8004424 <HAL_RCCEx_GetPeriphCLKFreq+0x60c>)
80043e2: e555 b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
frequency = CSI_VALUE;
80043e4: 480e ldr r0, [pc, #56] @ (8004420 <HAL_RCCEx_GetPeriphCLKFreq+0x608>)
80043e6: e553 b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
frequency = 0;
80043e8: 2000 movs r0, #0
80043ea: e551 b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
frequency = HSE_VALUE;
80043ec: 480b ldr r0, [pc, #44] @ (800441c <HAL_RCCEx_GetPeriphCLKFreq+0x604>)
80043ee: e54f b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
switch (srcclk)
80043f0: 480c ldr r0, [pc, #48] @ (8004424 <HAL_RCCEx_GetPeriphCLKFreq+0x60c>)
80043f2: e54d b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
frequency = CSI_VALUE;
80043f4: 480a ldr r0, [pc, #40] @ (8004420 <HAL_RCCEx_GetPeriphCLKFreq+0x608>)
80043f6: e54b b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
frequency = 0;
80043f8: 2000 movs r0, #0
80043fa: e549 b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
frequency = HSE_VALUE;
80043fc: 4807 ldr r0, [pc, #28] @ (800441c <HAL_RCCEx_GetPeriphCLKFreq+0x604>)
80043fe: e547 b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
switch (srcclk)
8004400: 2000 movs r0, #0
8004402: e545 b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
frequency = CSI_VALUE;
8004404: 4806 ldr r0, [pc, #24] @ (8004420 <HAL_RCCEx_GetPeriphCLKFreq+0x608>)
8004406: e543 b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
frequency = 0;
8004408: 2000 movs r0, #0
800440a: e541 b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
frequency = HSE_VALUE;
800440c: 4803 ldr r0, [pc, #12] @ (800441c <HAL_RCCEx_GetPeriphCLKFreq+0x604>)
800440e: e53f b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
switch (srcclk)
8004410: 4804 ldr r0, [pc, #16] @ (8004424 <HAL_RCCEx_GetPeriphCLKFreq+0x60c>)
8004412: e53d b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
switch (srcclk)
8004414: 2000 movs r0, #0
return frequency;
8004416: e53b b.n 8003e90 <HAL_RCCEx_GetPeriphCLKFreq+0x78>
8004418: 58024400 .word 0x58024400
800441c: 00f42400 .word 0x00f42400
8004420: 003d0900 .word 0x003d0900
8004424: 00bb8000 .word 0x00bb8000
08004428 <SPI_GetPacketSize>:
* the configuration information for SPI module.
* @retval Packet size occupied in the fifo
*/
static uint32_t SPI_GetPacketSize(const SPI_HandleTypeDef *hspi)
{
uint32_t fifo_threashold = (hspi->Init.FifoThreshold >> SPI_CFG1_FTHLV_Pos) + 1UL;
8004428: 6bc3 ldr r3, [r0, #60] @ 0x3c
800442a: 095b lsrs r3, r3, #5
uint32_t data_size = (hspi->Init.DataSize >> SPI_CFG1_DSIZE_Pos) + 1UL;
800442c: 68c0 ldr r0, [r0, #12]
/* Convert data size to Byte */
data_size = (data_size + 7UL) / 8UL;
800442e: 3008 adds r0, #8
8004430: 08c0 lsrs r0, r0, #3
return data_size * fifo_threashold;
}
8004432: fb03 0000 mla r0, r3, r0, r0
8004436: 4770 bx lr
08004438 <HAL_SPI_Init>:
if (hspi == NULL)
8004438: 2800 cmp r0, #0
800443a: f000 80b7 beq.w 80045ac <HAL_SPI_Init+0x174>
{
800443e: b570 push {r4, r5, r6, lr}
8004440: 4604 mov r4, r0
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
8004442: 2300 movs r3, #0
8004444: 6283 str r3, [r0, #40] @ 0x28
if ((!IS_SPI_HIGHEND_INSTANCE(hspi->Instance)) && (hspi->Init.DataSize > SPI_DATASIZE_16BIT))
8004446: 6805 ldr r5, [r0, #0]
8004448: 4b5c ldr r3, [pc, #368] @ (80045bc <HAL_SPI_Init+0x184>)
800444a: 4e5d ldr r6, [pc, #372] @ (80045c0 <HAL_SPI_Init+0x188>)
800444c: 429d cmp r5, r3
800444e: bf18 it ne
8004450: 42b5 cmpne r5, r6
8004452: bf14 ite ne
8004454: 2601 movne r6, #1
8004456: 2600 moveq r6, #0
8004458: d007 beq.n 800446a <HAL_SPI_Init+0x32>
800445a: f5a3 4374 sub.w r3, r3, #62464 @ 0xf400
800445e: 429d cmp r5, r3
8004460: d003 beq.n 800446a <HAL_SPI_Init+0x32>
8004462: 68c3 ldr r3, [r0, #12]
8004464: 2b0f cmp r3, #15
8004466: f200 80a3 bhi.w 80045b0 <HAL_SPI_Init+0x178>
packet_length = SPI_GetPacketSize(hspi);
800446a: 4620 mov r0, r4
800446c: f7ff ffdc bl 8004428 <SPI_GetPacketSize>
if (((!IS_SPI_HIGHEND_INSTANCE(hspi->Instance)) && (packet_length > SPI_LOWEND_FIFO_SIZE)) ||
8004470: b12e cbz r6, 800447e <HAL_SPI_Init+0x46>
8004472: 4b54 ldr r3, [pc, #336] @ (80045c4 <HAL_SPI_Init+0x18c>)
8004474: 429d cmp r5, r3
8004476: d002 beq.n 800447e <HAL_SPI_Init+0x46>
8004478: 2808 cmp r0, #8
800447a: f200 809b bhi.w 80045b4 <HAL_SPI_Init+0x17c>
800447e: 4a4f ldr r2, [pc, #316] @ (80045bc <HAL_SPI_Init+0x184>)
8004480: 4b4f ldr r3, [pc, #316] @ (80045c0 <HAL_SPI_Init+0x188>)
8004482: 429d cmp r5, r3
8004484: bf18 it ne
8004486: 4295 cmpne r5, r2
8004488: d003 beq.n 8004492 <HAL_SPI_Init+0x5a>
((IS_SPI_HIGHEND_INSTANCE(hspi->Instance)) && (packet_length > SPI_HIGHEND_FIFO_SIZE)))
800448a: f503 6380 add.w r3, r3, #1024 @ 0x400
800448e: 429d cmp r5, r3
8004490: d102 bne.n 8004498 <HAL_SPI_Init+0x60>
8004492: 2810 cmp r0, #16
8004494: f200 8090 bhi.w 80045b8 <HAL_SPI_Init+0x180>
if (hspi->State == HAL_SPI_STATE_RESET)
8004498: f894 3081 ldrb.w r3, [r4, #129] @ 0x81
800449c: b1f3 cbz r3, 80044dc <HAL_SPI_Init+0xa4>
hspi->State = HAL_SPI_STATE_BUSY;
800449e: 2302 movs r3, #2
80044a0: f884 3081 strb.w r3, [r4, #129] @ 0x81
__HAL_SPI_DISABLE(hspi);
80044a4: 6822 ldr r2, [r4, #0]
80044a6: 6813 ldr r3, [r2, #0]
80044a8: f023 0301 bic.w r3, r3, #1
80044ac: 6013 str r3, [r2, #0]
crc_length = hspi->Instance->CFG1 & SPI_CFG1_CRCSIZE;
80044ae: 6823 ldr r3, [r4, #0]
80044b0: 689a ldr r2, [r3, #8]
80044b2: f402 12f8 and.w r2, r2, #2031616 @ 0x1f0000
if ((hspi->Init.NSS == SPI_NSS_SOFT) && (((hspi->Init.Mode == SPI_MODE_MASTER) && \
80044b6: 69a1 ldr r1, [r4, #24]
80044b8: f1b1 6f80 cmp.w r1, #67108864 @ 0x4000000
80044bc: d014 beq.n 80044e8 <HAL_SPI_Init+0xb0>
if (((hspi->Init.Mode & SPI_MODE_MASTER) == SPI_MODE_MASTER) && (hspi->Init.DataSize >= SPI_DATASIZE_8BIT))
80044be: 6863 ldr r3, [r4, #4]
80044c0: f413 0f80 tst.w r3, #4194304 @ 0x400000
80044c4: d023 beq.n 800450e <HAL_SPI_Init+0xd6>
80044c6: 68e3 ldr r3, [r4, #12]
80044c8: 2b06 cmp r3, #6
80044ca: d920 bls.n 800450e <HAL_SPI_Init+0xd6>
MODIFY_REG(hspi->Instance->CR1, SPI_CR1_MASRX, hspi->Init.MasterReceiverAutoSusp);
80044cc: 6821 ldr r1, [r4, #0]
80044ce: 680b ldr r3, [r1, #0]
80044d0: f423 7380 bic.w r3, r3, #256 @ 0x100
80044d4: 6d20 ldr r0, [r4, #80] @ 0x50
80044d6: 4303 orrs r3, r0
80044d8: 600b str r3, [r1, #0]
80044da: e01d b.n 8004518 <HAL_SPI_Init+0xe0>
hspi->Lock = HAL_UNLOCKED;
80044dc: f884 3080 strb.w r3, [r4, #128] @ 0x80
HAL_SPI_MspInit(hspi);
80044e0: 4620 mov r0, r4
80044e2: f7fd fc75 bl 8001dd0 <HAL_SPI_MspInit>
80044e6: e7da b.n 800449e <HAL_SPI_Init+0x66>
if ((hspi->Init.NSS == SPI_NSS_SOFT) && (((hspi->Init.Mode == SPI_MODE_MASTER) && \
80044e8: 6861 ldr r1, [r4, #4]
80044ea: f5b1 0f80 cmp.w r1, #4194304 @ 0x400000
80044ee: d006 beq.n 80044fe <HAL_SPI_Init+0xc6>
(hspi->Init.NSSPolarity == SPI_NSS_POLARITY_LOW)) || \
80044f0: 2900 cmp r1, #0
80044f2: d1e4 bne.n 80044be <HAL_SPI_Init+0x86>
(hspi->Init.NSSPolarity == SPI_NSS_POLARITY_HIGH))))
80044f4: 6ba1 ldr r1, [r4, #56] @ 0x38
((hspi->Init.Mode == SPI_MODE_SLAVE) && \
80044f6: f1b1 5f80 cmp.w r1, #268435456 @ 0x10000000
80044fa: d1e0 bne.n 80044be <HAL_SPI_Init+0x86>
80044fc: e002 b.n 8004504 <HAL_SPI_Init+0xcc>
(hspi->Init.NSSPolarity == SPI_NSS_POLARITY_LOW)) || \
80044fe: 6ba0 ldr r0, [r4, #56] @ 0x38
if ((hspi->Init.NSS == SPI_NSS_SOFT) && (((hspi->Init.Mode == SPI_MODE_MASTER) && \
8004500: 2800 cmp r0, #0
8004502: d1f5 bne.n 80044f0 <HAL_SPI_Init+0xb8>
SET_BIT(hspi->Instance->CR1, SPI_CR1_SSI);
8004504: 6819 ldr r1, [r3, #0]
8004506: f441 5180 orr.w r1, r1, #4096 @ 0x1000
800450a: 6019 str r1, [r3, #0]
800450c: e7d7 b.n 80044be <HAL_SPI_Init+0x86>
CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_MASRX);
800450e: 6821 ldr r1, [r4, #0]
8004510: 680b ldr r3, [r1, #0]
8004512: f423 7380 bic.w r3, r3, #256 @ 0x100
8004516: 600b str r3, [r1, #0]
WRITE_REG(hspi->Instance->CFG1, (hspi->Init.BaudRatePrescaler | hspi->Init.CRCCalculation | crc_length |
8004518: 69e3 ldr r3, [r4, #28]
800451a: 6aa1 ldr r1, [r4, #40] @ 0x28
800451c: 430b orrs r3, r1
800451e: 4313 orrs r3, r2
8004520: 6be2 ldr r2, [r4, #60] @ 0x3c
8004522: 4313 orrs r3, r2
8004524: 68e1 ldr r1, [r4, #12]
8004526: 6822 ldr r2, [r4, #0]
8004528: 430b orrs r3, r1
800452a: 6093 str r3, [r2, #8]
WRITE_REG(hspi->Instance->CFG2, (hspi->Init.NSSPMode | hspi->Init.TIMode |
800452c: 6b63 ldr r3, [r4, #52] @ 0x34
800452e: 6a62 ldr r2, [r4, #36] @ 0x24
8004530: 4313 orrs r3, r2
8004532: 6ba2 ldr r2, [r4, #56] @ 0x38
8004534: 4313 orrs r3, r2
8004536: 69a2 ldr r2, [r4, #24]
8004538: 4313 orrs r3, r2
800453a: 6922 ldr r2, [r4, #16]
800453c: 4313 orrs r3, r2
800453e: 6962 ldr r2, [r4, #20]
8004540: 4313 orrs r3, r2
8004542: 6a22 ldr r2, [r4, #32]
8004544: 4313 orrs r3, r2
8004546: 6862 ldr r2, [r4, #4]
8004548: 4313 orrs r3, r2
800454a: 6ce2 ldr r2, [r4, #76] @ 0x4c
800454c: 4313 orrs r3, r2
800454e: 68a2 ldr r2, [r4, #8]
8004550: 4313 orrs r3, r2
8004552: 6ca2 ldr r2, [r4, #72] @ 0x48
8004554: 4313 orrs r3, r2
8004556: 6da1 ldr r1, [r4, #88] @ 0x58
8004558: 6822 ldr r2, [r4, #0]
800455a: 430b orrs r3, r1
800455c: 60d3 str r3, [r2, #12]
if (hspi->Init.Mode == SPI_MODE_SLAVE)
800455e: 6863 ldr r3, [r4, #4]
8004560: b96b cbnz r3, 800457e <HAL_SPI_Init+0x146>
MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRDET, SPI_CFG1_UDRDET_0);
8004562: 6822 ldr r2, [r4, #0]
8004564: 6893 ldr r3, [r2, #8]
8004566: f423 53c0 bic.w r3, r3, #6144 @ 0x1800
800456a: f443 6300 orr.w r3, r3, #2048 @ 0x800
800456e: 6093 str r3, [r2, #8]
MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, SPI_CFG1_UDRCFG_1);
8004570: 6822 ldr r2, [r4, #0]
8004572: 6893 ldr r3, [r2, #8]
8004574: f423 63c0 bic.w r3, r3, #1536 @ 0x600
8004578: f443 6380 orr.w r3, r3, #1024 @ 0x400
800457c: 6093 str r3, [r2, #8]
CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
800457e: 6822 ldr r2, [r4, #0]
8004580: 6d13 ldr r3, [r2, #80] @ 0x50
8004582: f023 0301 bic.w r3, r3, #1
8004586: 6513 str r3, [r2, #80] @ 0x50
if ((hspi->Init.Mode & SPI_MODE_MASTER) == SPI_MODE_MASTER)
8004588: 6863 ldr r3, [r4, #4]
800458a: f413 0f80 tst.w r3, #4194304 @ 0x400000
800458e: d006 beq.n 800459e <HAL_SPI_Init+0x166>
MODIFY_REG(hspi->Instance->CFG2, SPI_CFG2_AFCNTR, (hspi->Init.MasterKeepIOState));
8004590: 6822 ldr r2, [r4, #0]
8004592: 68d3 ldr r3, [r2, #12]
8004594: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
8004598: 6d61 ldr r1, [r4, #84] @ 0x54
800459a: 430b orrs r3, r1
800459c: 60d3 str r3, [r2, #12]
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
800459e: 2000 movs r0, #0
80045a0: f8c4 0084 str.w r0, [r4, #132] @ 0x84
hspi->State = HAL_SPI_STATE_READY;
80045a4: 2301 movs r3, #1
80045a6: f884 3081 strb.w r3, [r4, #129] @ 0x81
}
80045aa: bd70 pop {r4, r5, r6, pc}
return HAL_ERROR;
80045ac: 2001 movs r0, #1
}
80045ae: 4770 bx lr
return HAL_ERROR;
80045b0: 2001 movs r0, #1
80045b2: e7fa b.n 80045aa <HAL_SPI_Init+0x172>
return HAL_ERROR;
80045b4: 2001 movs r0, #1
80045b6: e7f8 b.n 80045aa <HAL_SPI_Init+0x172>
80045b8: 2001 movs r0, #1
80045ba: e7f6 b.n 80045aa <HAL_SPI_Init+0x172>
80045bc: 40013000 .word 0x40013000
80045c0: 40003800 .word 0x40003800
80045c4: 40003c00 .word 0x40003c00
080045c8 <TIM_TI1_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
80045c8: b410 push {r4}
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 1: Reset the CC1E Bit */
tmpccer = TIMx->CCER;
80045ca: 6a03 ldr r3, [r0, #32]
TIMx->CCER &= ~TIM_CCER_CC1E;
80045cc: 6a04 ldr r4, [r0, #32]
80045ce: f024 0401 bic.w r4, r4, #1
80045d2: 6204 str r4, [r0, #32]
tmpccmr1 = TIMx->CCMR1;
80045d4: 6984 ldr r4, [r0, #24]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC1F;
80045d6: f024 0cf0 bic.w ip, r4, #240 @ 0xf0
tmpccmr1 |= (TIM_ICFilter << 4U);
80045da: ea4c 1202 orr.w r2, ip, r2, lsl #4
/* Select the Polarity and set the CC1E Bit */
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
80045de: f023 030a bic.w r3, r3, #10
tmpccer |= TIM_ICPolarity;
80045e2: 430b orrs r3, r1
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1;
80045e4: 6182 str r2, [r0, #24]
TIMx->CCER = tmpccer;
80045e6: 6203 str r3, [r0, #32]
}
80045e8: f85d 4b04 ldr.w r4, [sp], #4
80045ec: 4770 bx lr
080045ee <TIM_TI2_SetConfig>:
* (on channel1 path) is used as the input signal. Therefore CCMR1 must be
* protected against un-initialized filter and polarity values.
*/
static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
uint32_t TIM_ICFilter)
{
80045ee: b430 push {r4, r5}
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 2: Reset the CC2E Bit */
tmpccer = TIMx->CCER;
80045f0: 6a05 ldr r5, [r0, #32]
TIMx->CCER &= ~TIM_CCER_CC2E;
80045f2: 6a04 ldr r4, [r0, #32]
80045f4: f024 0410 bic.w r4, r4, #16
80045f8: 6204 str r4, [r0, #32]
tmpccmr1 = TIMx->CCMR1;
80045fa: 6984 ldr r4, [r0, #24]
/* Select the Input */
tmpccmr1 &= ~TIM_CCMR1_CC2S;
80045fc: f424 7c40 bic.w ip, r4, #768 @ 0x300
tmpccmr1 |= (TIM_ICSelection << 8U);
8004600: ea4c 2c02 orr.w ip, ip, r2, lsl #8
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC2F;
8004604: f42c 4c70 bic.w ip, ip, #61440 @ 0xf000
tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
8004608: 031b lsls r3, r3, #12
800460a: b29b uxth r3, r3
800460c: ea43 030c orr.w r3, r3, ip
/* Select the Polarity and set the CC2E Bit */
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
8004610: f025 05a0 bic.w r5, r5, #160 @ 0xa0
tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
8004614: 0109 lsls r1, r1, #4
8004616: f001 01a0 and.w r1, r1, #160 @ 0xa0
800461a: 4329 orrs r1, r5
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1 ;
800461c: 6183 str r3, [r0, #24]
TIMx->CCER = tmpccer;
800461e: 6201 str r1, [r0, #32]
}
8004620: bc30 pop {r4, r5}
8004622: 4770 bx lr
08004624 <TIM_TI2_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
8004624: b410 push {r4}
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 2: Reset the CC2E Bit */
tmpccer = TIMx->CCER;
8004626: 6a03 ldr r3, [r0, #32]
TIMx->CCER &= ~TIM_CCER_CC2E;
8004628: 6a04 ldr r4, [r0, #32]
800462a: f024 0410 bic.w r4, r4, #16
800462e: 6204 str r4, [r0, #32]
tmpccmr1 = TIMx->CCMR1;
8004630: 6984 ldr r4, [r0, #24]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC2F;
8004632: f424 4c70 bic.w ip, r4, #61440 @ 0xf000
tmpccmr1 |= (TIM_ICFilter << 12U);
8004636: ea4c 3202 orr.w r2, ip, r2, lsl #12
/* Select the Polarity and set the CC2E Bit */
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
800463a: f023 03a0 bic.w r3, r3, #160 @ 0xa0
tmpccer |= (TIM_ICPolarity << 4U);
800463e: ea43 1301 orr.w r3, r3, r1, lsl #4
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1 ;
8004642: 6182 str r2, [r0, #24]
TIMx->CCER = tmpccer;
8004644: 6203 str r3, [r0, #32]
}
8004646: f85d 4b04 ldr.w r4, [sp], #4
800464a: 4770 bx lr
0800464c <TIM_TI3_SetConfig>:
* (on channel1 path) is used as the input signal. Therefore CCMR2 must be
* protected against un-initialized filter and polarity values.
*/
static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
uint32_t TIM_ICFilter)
{
800464c: b430 push {r4, r5}
uint32_t tmpccmr2;
uint32_t tmpccer;
/* Disable the Channel 3: Reset the CC3E Bit */
tmpccer = TIMx->CCER;
800464e: 6a05 ldr r5, [r0, #32]
TIMx->CCER &= ~TIM_CCER_CC3E;
8004650: 6a04 ldr r4, [r0, #32]
8004652: f424 7480 bic.w r4, r4, #256 @ 0x100
8004656: 6204 str r4, [r0, #32]
tmpccmr2 = TIMx->CCMR2;
8004658: 69c4 ldr r4, [r0, #28]
/* Select the Input */
tmpccmr2 &= ~TIM_CCMR2_CC3S;
800465a: f024 0c03 bic.w ip, r4, #3
tmpccmr2 |= TIM_ICSelection;
800465e: ea4c 0c02 orr.w ip, ip, r2
/* Set the filter */
tmpccmr2 &= ~TIM_CCMR2_IC3F;
8004662: f02c 0cf0 bic.w ip, ip, #240 @ 0xf0
tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
8004666: 011b lsls r3, r3, #4
8004668: b2db uxtb r3, r3
800466a: ea43 030c orr.w r3, r3, ip
/* Select the Polarity and set the CC3E Bit */
tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
800466e: f425 6520 bic.w r5, r5, #2560 @ 0xa00
tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
8004672: 0209 lsls r1, r1, #8
8004674: f401 6120 and.w r1, r1, #2560 @ 0xa00
8004678: 4329 orrs r1, r5
/* Write to TIMx CCMR2 and CCER registers */
TIMx->CCMR2 = tmpccmr2;
800467a: 61c3 str r3, [r0, #28]
TIMx->CCER = tmpccer;
800467c: 6201 str r1, [r0, #32]
}
800467e: bc30 pop {r4, r5}
8004680: 4770 bx lr
08004682 <TIM_TI4_SetConfig>:
* protected against un-initialized filter and polarity values.
* @retval None
*/
static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
uint32_t TIM_ICFilter)
{
8004682: b430 push {r4, r5}
uint32_t tmpccmr2;
uint32_t tmpccer;
/* Disable the Channel 4: Reset the CC4E Bit */
tmpccer = TIMx->CCER;
8004684: 6a05 ldr r5, [r0, #32]
TIMx->CCER &= ~TIM_CCER_CC4E;
8004686: 6a04 ldr r4, [r0, #32]
8004688: f424 5480 bic.w r4, r4, #4096 @ 0x1000
800468c: 6204 str r4, [r0, #32]
tmpccmr2 = TIMx->CCMR2;
800468e: 69c4 ldr r4, [r0, #28]
/* Select the Input */
tmpccmr2 &= ~TIM_CCMR2_CC4S;
8004690: f424 7c40 bic.w ip, r4, #768 @ 0x300
tmpccmr2 |= (TIM_ICSelection << 8U);
8004694: ea4c 2c02 orr.w ip, ip, r2, lsl #8
/* Set the filter */
tmpccmr2 &= ~TIM_CCMR2_IC4F;
8004698: f42c 4c70 bic.w ip, ip, #61440 @ 0xf000
tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
800469c: 031b lsls r3, r3, #12
800469e: b29b uxth r3, r3
80046a0: ea43 030c orr.w r3, r3, ip
/* Select the Polarity and set the CC4E Bit */
tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
80046a4: f425 4520 bic.w r5, r5, #40960 @ 0xa000
tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
80046a8: 0309 lsls r1, r1, #12
80046aa: f401 4120 and.w r1, r1, #40960 @ 0xa000
80046ae: 4329 orrs r1, r5
/* Write to TIMx CCMR2 and CCER registers */
TIMx->CCMR2 = tmpccmr2;
80046b0: 61c3 str r3, [r0, #28]
TIMx->CCER = tmpccer ;
80046b2: 6201 str r1, [r0, #32]
}
80046b4: bc30 pop {r4, r5}
80046b6: 4770 bx lr
080046b8 <TIM_Base_SetConfig>:
{
80046b8: b530 push {r4, r5, lr}
tmpcr1 = TIMx->CR1;
80046ba: 6803 ldr r3, [r0, #0]
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
80046bc: 4a3d ldr r2, [pc, #244] @ (80047b4 <TIM_Base_SetConfig+0xfc>)
80046be: 4290 cmp r0, r2
80046c0: bf14 ite ne
80046c2: f04f 0e00 movne.w lr, #0
80046c6: f04f 0e01 moveq.w lr, #1
80046ca: f1b0 4f80 cmp.w r0, #1073741824 @ 0x40000000
80046ce: bf14 ite ne
80046d0: 4672 movne r2, lr
80046d2: f04e 0201 orreq.w r2, lr, #1
80046d6: b9aa cbnz r2, 8004704 <TIM_Base_SetConfig+0x4c>
80046d8: 4c37 ldr r4, [pc, #220] @ (80047b8 <TIM_Base_SetConfig+0x100>)
80046da: 42a0 cmp r0, r4
80046dc: bf14 ite ne
80046de: 2400 movne r4, #0
80046e0: 2401 moveq r4, #1
80046e2: 4d36 ldr r5, [pc, #216] @ (80047bc <TIM_Base_SetConfig+0x104>)
80046e4: 42a8 cmp r0, r5
80046e6: d00d beq.n 8004704 <TIM_Base_SetConfig+0x4c>
80046e8: b964 cbnz r4, 8004704 <TIM_Base_SetConfig+0x4c>
80046ea: f104 4480 add.w r4, r4, #1073741824 @ 0x40000000
80046ee: f504 3482 add.w r4, r4, #66560 @ 0x10400
80046f2: 42a0 cmp r0, r4
80046f4: bf14 ite ne
80046f6: 2400 movne r4, #0
80046f8: 2401 moveq r4, #1
80046fa: f505 6500 add.w r5, r5, #2048 @ 0x800
80046fe: 42a8 cmp r0, r5
8004700: d000 beq.n 8004704 <TIM_Base_SetConfig+0x4c>
8004702: b11c cbz r4, 800470c <TIM_Base_SetConfig+0x54>
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
8004704: f023 0370 bic.w r3, r3, #112 @ 0x70
tmpcr1 |= Structure->CounterMode;
8004708: 684c ldr r4, [r1, #4]
800470a: 4323 orrs r3, r4
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
800470c: bb12 cbnz r2, 8004754 <TIM_Base_SetConfig+0x9c>
800470e: 4a2a ldr r2, [pc, #168] @ (80047b8 <TIM_Base_SetConfig+0x100>)
8004710: 4290 cmp r0, r2
8004712: bf14 ite ne
8004714: 2200 movne r2, #0
8004716: 2201 moveq r2, #1
8004718: 4c28 ldr r4, [pc, #160] @ (80047bc <TIM_Base_SetConfig+0x104>)
800471a: 42a0 cmp r0, r4
800471c: d01a beq.n 8004754 <TIM_Base_SetConfig+0x9c>
800471e: b9ca cbnz r2, 8004754 <TIM_Base_SetConfig+0x9c>
8004720: f102 4280 add.w r2, r2, #1073741824 @ 0x40000000
8004724: f502 3282 add.w r2, r2, #66560 @ 0x10400
8004728: 4290 cmp r0, r2
800472a: bf14 ite ne
800472c: 2200 movne r2, #0
800472e: 2201 moveq r2, #1
8004730: f504 6400 add.w r4, r4, #2048 @ 0x800
8004734: 42a0 cmp r0, r4
8004736: d00d beq.n 8004754 <TIM_Base_SetConfig+0x9c>
8004738: b962 cbnz r2, 8004754 <TIM_Base_SetConfig+0x9c>
800473a: 4a21 ldr r2, [pc, #132] @ (80047c0 <TIM_Base_SetConfig+0x108>)
800473c: 4290 cmp r0, r2
800473e: bf14 ite ne
8004740: 2200 movne r2, #0
8004742: 2201 moveq r2, #1
8004744: f504 349a add.w r4, r4, #78848 @ 0x13400
8004748: 42a0 cmp r0, r4
800474a: d003 beq.n 8004754 <TIM_Base_SetConfig+0x9c>
800474c: b912 cbnz r2, 8004754 <TIM_Base_SetConfig+0x9c>
800474e: 4a1d ldr r2, [pc, #116] @ (80047c4 <TIM_Base_SetConfig+0x10c>)
8004750: 4290 cmp r0, r2
8004752: d104 bne.n 800475e <TIM_Base_SetConfig+0xa6>
tmpcr1 &= ~TIM_CR1_CKD;
8004754: f423 7c40 bic.w ip, r3, #768 @ 0x300
tmpcr1 |= (uint32_t)Structure->ClockDivision;
8004758: 68cb ldr r3, [r1, #12]
800475a: ea43 030c orr.w r3, r3, ip
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
800475e: f023 0380 bic.w r3, r3, #128 @ 0x80
8004762: 694a ldr r2, [r1, #20]
8004764: 4313 orrs r3, r2
TIMx->CR1 = tmpcr1;
8004766: 6003 str r3, [r0, #0]
TIMx->ARR = (uint32_t)Structure->Period ;
8004768: 688a ldr r2, [r1, #8]
800476a: 62c2 str r2, [r0, #44] @ 0x2c
TIMx->PSC = Structure->Prescaler;
800476c: 680a ldr r2, [r1, #0]
800476e: 6282 str r2, [r0, #40] @ 0x28
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
8004770: 4a15 ldr r2, [pc, #84] @ (80047c8 <TIM_Base_SetConfig+0x110>)
8004772: 4290 cmp r0, r2
8004774: bf14 ite ne
8004776: 4673 movne r3, lr
8004778: f04e 0301 orreq.w r3, lr, #1
800477c: b963 cbnz r3, 8004798 <TIM_Base_SetConfig+0xe0>
800477e: 4b10 ldr r3, [pc, #64] @ (80047c0 <TIM_Base_SetConfig+0x108>)
8004780: 4298 cmp r0, r3
8004782: bf14 ite ne
8004784: 2300 movne r3, #0
8004786: 2301 moveq r3, #1
8004788: f502 5270 add.w r2, r2, #15360 @ 0x3c00
800478c: 4290 cmp r0, r2
800478e: d003 beq.n 8004798 <TIM_Base_SetConfig+0xe0>
8004790: b913 cbnz r3, 8004798 <TIM_Base_SetConfig+0xe0>
8004792: 4b0c ldr r3, [pc, #48] @ (80047c4 <TIM_Base_SetConfig+0x10c>)
8004794: 4298 cmp r0, r3
8004796: d101 bne.n 800479c <TIM_Base_SetConfig+0xe4>
TIMx->RCR = Structure->RepetitionCounter;
8004798: 690b ldr r3, [r1, #16]
800479a: 6303 str r3, [r0, #48] @ 0x30
TIMx->EGR = TIM_EGR_UG;
800479c: 2301 movs r3, #1
800479e: 6143 str r3, [r0, #20]
if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
80047a0: 6903 ldr r3, [r0, #16]
80047a2: f013 0f01 tst.w r3, #1
80047a6: d003 beq.n 80047b0 <TIM_Base_SetConfig+0xf8>
CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
80047a8: 6903 ldr r3, [r0, #16]
80047aa: f023 0301 bic.w r3, r3, #1
80047ae: 6103 str r3, [r0, #16]
}
80047b0: bd30 pop {r4, r5, pc}
80047b2: bf00 nop
80047b4: 40010000 .word 0x40010000
80047b8: 40000800 .word 0x40000800
80047bc: 40000400 .word 0x40000400
80047c0: 40014400 .word 0x40014400
80047c4: 40014800 .word 0x40014800
80047c8: 40010400 .word 0x40010400
080047cc <HAL_TIM_IC_Init>:
if (htim == NULL)
80047cc: b360 cbz r0, 8004828 <HAL_TIM_IC_Init+0x5c>
{
80047ce: b510 push {r4, lr}
80047d0: 4604 mov r4, r0
if (htim->State == HAL_TIM_STATE_RESET)
80047d2: f890 303d ldrb.w r3, [r0, #61] @ 0x3d
80047d6: b313 cbz r3, 800481e <HAL_TIM_IC_Init+0x52>
htim->State = HAL_TIM_STATE_BUSY;
80047d8: 2302 movs r3, #2
80047da: f884 303d strb.w r3, [r4, #61] @ 0x3d
TIM_Base_SetConfig(htim->Instance, &htim->Init);
80047de: 4621 mov r1, r4
80047e0: f851 0b04 ldr.w r0, [r1], #4
80047e4: f7ff ff68 bl 80046b8 <TIM_Base_SetConfig>
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
80047e8: 2301 movs r3, #1
80047ea: f884 3048 strb.w r3, [r4, #72] @ 0x48
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
80047ee: f884 303e strb.w r3, [r4, #62] @ 0x3e
80047f2: f884 303f strb.w r3, [r4, #63] @ 0x3f
80047f6: f884 3040 strb.w r3, [r4, #64] @ 0x40
80047fa: f884 3041 strb.w r3, [r4, #65] @ 0x41
80047fe: f884 3042 strb.w r3, [r4, #66] @ 0x42
8004802: f884 3043 strb.w r3, [r4, #67] @ 0x43
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8004806: f884 3044 strb.w r3, [r4, #68] @ 0x44
800480a: f884 3045 strb.w r3, [r4, #69] @ 0x45
800480e: f884 3046 strb.w r3, [r4, #70] @ 0x46
8004812: f884 3047 strb.w r3, [r4, #71] @ 0x47
htim->State = HAL_TIM_STATE_READY;
8004816: f884 303d strb.w r3, [r4, #61] @ 0x3d
return HAL_OK;
800481a: 2000 movs r0, #0
}
800481c: bd10 pop {r4, pc}
htim->Lock = HAL_UNLOCKED;
800481e: f880 303c strb.w r3, [r0, #60] @ 0x3c
HAL_TIM_IC_MspInit(htim);
8004822: f7fd fba9 bl 8001f78 <HAL_TIM_IC_MspInit>
8004826: e7d7 b.n 80047d8 <HAL_TIM_IC_Init+0xc>
return HAL_ERROR;
8004828: 2001 movs r0, #1
}
800482a: 4770 bx lr
0800482c <TIM_TI1_SetConfig>:
{
800482c: b470 push {r4, r5, r6}
800482e: 4694 mov ip, r2
tmpccer = TIMx->CCER;
8004830: 6a06 ldr r6, [r0, #32]
TIMx->CCER &= ~TIM_CCER_CC1E;
8004832: 6a04 ldr r4, [r0, #32]
8004834: f024 0401 bic.w r4, r4, #1
8004838: 6204 str r4, [r0, #32]
tmpccmr1 = TIMx->CCMR1;
800483a: 6984 ldr r4, [r0, #24]
if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
800483c: 4d1d ldr r5, [pc, #116] @ (80048b4 <TIM_TI1_SetConfig+0x88>)
800483e: f1b0 4f80 cmp.w r0, #1073741824 @ 0x40000000
8004842: bf18 it ne
8004844: 42a8 cmpne r0, r5
8004846: d023 beq.n 8004890 <TIM_TI1_SetConfig+0x64>
8004848: 4a1b ldr r2, [pc, #108] @ (80048b8 <TIM_TI1_SetConfig+0x8c>)
800484a: 4290 cmp r0, r2
800484c: bf14 ite ne
800484e: 2200 movne r2, #0
8004850: 2201 moveq r2, #1
8004852: f5a5 457c sub.w r5, r5, #64512 @ 0xfc00
8004856: 42a8 cmp r0, r5
8004858: d01a beq.n 8004890 <TIM_TI1_SetConfig+0x64>
800485a: b9ca cbnz r2, 8004890 <TIM_TI1_SetConfig+0x64>
800485c: f102 4280 add.w r2, r2, #1073741824 @ 0x40000000
8004860: f502 3282 add.w r2, r2, #66560 @ 0x10400
8004864: 4290 cmp r0, r2
8004866: bf14 ite ne
8004868: 2200 movne r2, #0
800486a: 2201 moveq r2, #1
800486c: f505 6500 add.w r5, r5, #2048 @ 0x800
8004870: 42a8 cmp r0, r5
8004872: d00d beq.n 8004890 <TIM_TI1_SetConfig+0x64>
8004874: b962 cbnz r2, 8004890 <TIM_TI1_SetConfig+0x64>
8004876: 4a11 ldr r2, [pc, #68] @ (80048bc <TIM_TI1_SetConfig+0x90>)
8004878: 4290 cmp r0, r2
800487a: bf14 ite ne
800487c: 2200 movne r2, #0
800487e: 2201 moveq r2, #1
8004880: f505 6540 add.w r5, r5, #3072 @ 0xc00
8004884: 42a8 cmp r0, r5
8004886: d003 beq.n 8004890 <TIM_TI1_SetConfig+0x64>
8004888: b912 cbnz r2, 8004890 <TIM_TI1_SetConfig+0x64>
tmpccmr1 |= TIM_CCMR1_CC1S_0;
800488a: f044 0201 orr.w r2, r4, #1
800488e: e003 b.n 8004898 <TIM_TI1_SetConfig+0x6c>
tmpccmr1 &= ~TIM_CCMR1_CC1S;
8004890: f024 0203 bic.w r2, r4, #3
tmpccmr1 |= TIM_ICSelection;
8004894: ea42 020c orr.w r2, r2, ip
tmpccmr1 &= ~TIM_CCMR1_IC1F;
8004898: f022 02f0 bic.w r2, r2, #240 @ 0xf0
tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
800489c: 011b lsls r3, r3, #4
800489e: b2db uxtb r3, r3
80048a0: 4313 orrs r3, r2
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
80048a2: f026 020a bic.w r2, r6, #10
tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
80048a6: f001 010a and.w r1, r1, #10
80048aa: 4311 orrs r1, r2
TIMx->CCMR1 = tmpccmr1;
80048ac: 6183 str r3, [r0, #24]
TIMx->CCER = tmpccer;
80048ae: 6201 str r1, [r0, #32]
}
80048b0: bc70 pop {r4, r5, r6}
80048b2: 4770 bx lr
80048b4: 40010000 .word 0x40010000
80048b8: 40000800 .word 0x40000800
80048bc: 40014000 .word 0x40014000
080048c0 <HAL_TIM_IC_ConfigChannel>:
{
80048c0: b538 push {r3, r4, r5, lr}
__HAL_LOCK(htim);
80048c2: f890 303c ldrb.w r3, [r0, #60] @ 0x3c
80048c6: 2b01 cmp r3, #1
80048c8: d05e beq.n 8004988 <HAL_TIM_IC_ConfigChannel+0xc8>
80048ca: 4604 mov r4, r0
80048cc: 460d mov r5, r1
80048ce: 2301 movs r3, #1
80048d0: f880 303c strb.w r3, [r0, #60] @ 0x3c
if (Channel == TIM_CHANNEL_1)
80048d4: 2a0c cmp r2, #12
80048d6: d852 bhi.n 800497e <HAL_TIM_IC_ConfigChannel+0xbe>
80048d8: e8df f002 tbb [pc, r2]
80048dc: 51515107 .word 0x51515107
80048e0: 51515119 .word 0x51515119
80048e4: 5151512c .word 0x5151512c
80048e8: 3e .byte 0x3e
80048e9: 00 .byte 0x00
TIM_TI1_SetConfig(htim->Instance,
80048ea: 68cb ldr r3, [r1, #12]
80048ec: 684a ldr r2, [r1, #4]
80048ee: 6809 ldr r1, [r1, #0]
80048f0: 6800 ldr r0, [r0, #0]
80048f2: f7ff ff9b bl 800482c <TIM_TI1_SetConfig>
htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
80048f6: 6822 ldr r2, [r4, #0]
80048f8: 6993 ldr r3, [r2, #24]
80048fa: f023 030c bic.w r3, r3, #12
80048fe: 6193 str r3, [r2, #24]
htim->Instance->CCMR1 |= sConfig->ICPrescaler;
8004900: 6822 ldr r2, [r4, #0]
8004902: 6993 ldr r3, [r2, #24]
8004904: 68a9 ldr r1, [r5, #8]
8004906: 430b orrs r3, r1
8004908: 6193 str r3, [r2, #24]
HAL_StatusTypeDef status = HAL_OK;
800490a: 2000 movs r0, #0
800490c: e038 b.n 8004980 <HAL_TIM_IC_ConfigChannel+0xc0>
TIM_TI2_SetConfig(htim->Instance,
800490e: 68cb ldr r3, [r1, #12]
8004910: 684a ldr r2, [r1, #4]
8004912: 6809 ldr r1, [r1, #0]
8004914: 6800 ldr r0, [r0, #0]
8004916: f7ff fe6a bl 80045ee <TIM_TI2_SetConfig>
htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
800491a: 6822 ldr r2, [r4, #0]
800491c: 6993 ldr r3, [r2, #24]
800491e: f423 6340 bic.w r3, r3, #3072 @ 0xc00
8004922: 6193 str r3, [r2, #24]
htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
8004924: 6822 ldr r2, [r4, #0]
8004926: 6993 ldr r3, [r2, #24]
8004928: 68a9 ldr r1, [r5, #8]
800492a: ea43 2301 orr.w r3, r3, r1, lsl #8
800492e: 6193 str r3, [r2, #24]
HAL_StatusTypeDef status = HAL_OK;
8004930: 2000 movs r0, #0
8004932: e025 b.n 8004980 <HAL_TIM_IC_ConfigChannel+0xc0>
TIM_TI3_SetConfig(htim->Instance,
8004934: 68cb ldr r3, [r1, #12]
8004936: 684a ldr r2, [r1, #4]
8004938: 6809 ldr r1, [r1, #0]
800493a: 6800 ldr r0, [r0, #0]
800493c: f7ff fe86 bl 800464c <TIM_TI3_SetConfig>
htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
8004940: 6822 ldr r2, [r4, #0]
8004942: 69d3 ldr r3, [r2, #28]
8004944: f023 030c bic.w r3, r3, #12
8004948: 61d3 str r3, [r2, #28]
htim->Instance->CCMR2 |= sConfig->ICPrescaler;
800494a: 6822 ldr r2, [r4, #0]
800494c: 69d3 ldr r3, [r2, #28]
800494e: 68a9 ldr r1, [r5, #8]
8004950: 430b orrs r3, r1
8004952: 61d3 str r3, [r2, #28]
HAL_StatusTypeDef status = HAL_OK;
8004954: 2000 movs r0, #0
8004956: e013 b.n 8004980 <HAL_TIM_IC_ConfigChannel+0xc0>
TIM_TI4_SetConfig(htim->Instance,
8004958: 68cb ldr r3, [r1, #12]
800495a: 684a ldr r2, [r1, #4]
800495c: 6809 ldr r1, [r1, #0]
800495e: 6800 ldr r0, [r0, #0]
8004960: f7ff fe8f bl 8004682 <TIM_TI4_SetConfig>
htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
8004964: 6822 ldr r2, [r4, #0]
8004966: 69d3 ldr r3, [r2, #28]
8004968: f423 6340 bic.w r3, r3, #3072 @ 0xc00
800496c: 61d3 str r3, [r2, #28]
htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
800496e: 6822 ldr r2, [r4, #0]
8004970: 69d3 ldr r3, [r2, #28]
8004972: 68a9 ldr r1, [r5, #8]
8004974: ea43 2301 orr.w r3, r3, r1, lsl #8
8004978: 61d3 str r3, [r2, #28]
HAL_StatusTypeDef status = HAL_OK;
800497a: 2000 movs r0, #0
800497c: e000 b.n 8004980 <HAL_TIM_IC_ConfigChannel+0xc0>
__HAL_LOCK(htim);
800497e: 2001 movs r0, #1
__HAL_UNLOCK(htim);
8004980: 2300 movs r3, #0
8004982: f884 303c strb.w r3, [r4, #60] @ 0x3c
}
8004986: bd38 pop {r3, r4, r5, pc}
__HAL_LOCK(htim);
8004988: 2002 movs r0, #2
800498a: e7fc b.n 8004986 <HAL_TIM_IC_ConfigChannel+0xc6>
0800498c <TIM_ETR_SetConfig>:
* This parameter must be a value between 0x00 and 0x0F
* @retval None
*/
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
{
800498c: b410 push {r4}
uint32_t tmpsmcr;
tmpsmcr = TIMx->SMCR;
800498e: 6884 ldr r4, [r0, #8]
/* Reset the ETR Bits */
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
8004990: f424 4c7f bic.w ip, r4, #65280 @ 0xff00
/* Set the Prescaler, the Filter value and the Polarity */
tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
8004994: ea42 2203 orr.w r2, r2, r3, lsl #8
8004998: 430a orrs r2, r1
800499a: ea42 020c orr.w r2, r2, ip
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
800499e: 6082 str r2, [r0, #8]
}
80049a0: f85d 4b04 ldr.w r4, [sp], #4
80049a4: 4770 bx lr
...
080049a8 <TIM_SlaveTimer_SetConfig>:
{
80049a8: b510 push {r4, lr}
tmpsmcr = htim->Instance->SMCR;
80049aa: 6804 ldr r4, [r0, #0]
80049ac: 68a3 ldr r3, [r4, #8]
tmpsmcr &= ~TIM_SMCR_TS;
80049ae: 4a4c ldr r2, [pc, #304] @ (8004ae0 <TIM_SlaveTimer_SetConfig+0x138>)
80049b0: 401a ands r2, r3
tmpsmcr |= sSlaveConfig->InputTrigger;
80049b2: 684b ldr r3, [r1, #4]
80049b4: 4313 orrs r3, r2
tmpsmcr &= ~TIM_SMCR_SMS;
80049b6: 4a4b ldr r2, [pc, #300] @ (8004ae4 <TIM_SlaveTimer_SetConfig+0x13c>)
80049b8: 401a ands r2, r3
tmpsmcr |= sSlaveConfig->SlaveMode;
80049ba: 680b ldr r3, [r1, #0]
80049bc: 4313 orrs r3, r2
htim->Instance->SMCR = tmpsmcr;
80049be: 60a3 str r3, [r4, #8]
switch (sSlaveConfig->InputTrigger)
80049c0: 684b ldr r3, [r1, #4]
80049c2: 2b60 cmp r3, #96 @ 0x60
80049c4: d068 beq.n 8004a98 <TIM_SlaveTimer_SetConfig+0xf0>
80049c6: d81e bhi.n 8004a06 <TIM_SlaveTimer_SetConfig+0x5e>
80049c8: 2b40 cmp r3, #64 @ 0x40
80049ca: d050 beq.n 8004a6e <TIM_SlaveTimer_SetConfig+0xc6>
80049cc: d908 bls.n 80049e0 <TIM_SlaveTimer_SetConfig+0x38>
80049ce: 2b50 cmp r3, #80 @ 0x50
80049d0: d117 bne.n 8004a02 <TIM_SlaveTimer_SetConfig+0x5a>
TIM_TI1_ConfigInputStage(htim->Instance,
80049d2: 690a ldr r2, [r1, #16]
80049d4: 6889 ldr r1, [r1, #8]
80049d6: 6800 ldr r0, [r0, #0]
80049d8: f7ff fdf6 bl 80045c8 <TIM_TI1_ConfigInputStage>
HAL_StatusTypeDef status = HAL_OK;
80049dc: 2000 movs r0, #0
break;
80049de: e045 b.n 8004a6c <TIM_SlaveTimer_SetConfig+0xc4>
switch (sSlaveConfig->InputTrigger)
80049e0: 2b20 cmp r3, #32
80049e2: d060 beq.n 8004aa6 <TIM_SlaveTimer_SetConfig+0xfe>
80049e4: d807 bhi.n 80049f6 <TIM_SlaveTimer_SetConfig+0x4e>
80049e6: 2b00 cmp r3, #0
80049e8: d05f beq.n 8004aaa <TIM_SlaveTimer_SetConfig+0x102>
80049ea: 2b10 cmp r3, #16
80049ec: d001 beq.n 80049f2 <TIM_SlaveTimer_SetConfig+0x4a>
status = HAL_ERROR;
80049ee: 2001 movs r0, #1
80049f0: e03c b.n 8004a6c <TIM_SlaveTimer_SetConfig+0xc4>
switch (sSlaveConfig->InputTrigger)
80049f2: 2000 movs r0, #0
80049f4: e03a b.n 8004a6c <TIM_SlaveTimer_SetConfig+0xc4>
80049f6: 2b30 cmp r3, #48 @ 0x30
80049f8: d001 beq.n 80049fe <TIM_SlaveTimer_SetConfig+0x56>
status = HAL_ERROR;
80049fa: 2001 movs r0, #1
80049fc: e036 b.n 8004a6c <TIM_SlaveTimer_SetConfig+0xc4>
switch (sSlaveConfig->InputTrigger)
80049fe: 2000 movs r0, #0
8004a00: e034 b.n 8004a6c <TIM_SlaveTimer_SetConfig+0xc4>
status = HAL_ERROR;
8004a02: 2001 movs r0, #1
8004a04: e032 b.n 8004a6c <TIM_SlaveTimer_SetConfig+0xc4>
switch (sSlaveConfig->InputTrigger)
8004a06: 2b70 cmp r3, #112 @ 0x70
8004a08: d029 beq.n 8004a5e <TIM_SlaveTimer_SetConfig+0xb6>
8004a0a: d350 bcc.n 8004aae <TIM_SlaveTimer_SetConfig+0x106>
8004a0c: 4a36 ldr r2, [pc, #216] @ (8004ae8 <TIM_SlaveTimer_SetConfig+0x140>)
8004a0e: 4293 cmp r3, r2
8004a10: d04f beq.n 8004ab2 <TIM_SlaveTimer_SetConfig+0x10a>
8004a12: d813 bhi.n 8004a3c <TIM_SlaveTimer_SetConfig+0x94>
8004a14: 3a30 subs r2, #48 @ 0x30
8004a16: 4293 cmp r3, r2
8004a18: d04d beq.n 8004ab6 <TIM_SlaveTimer_SetConfig+0x10e>
8004a1a: d907 bls.n 8004a2c <TIM_SlaveTimer_SetConfig+0x84>
8004a1c: 4a33 ldr r2, [pc, #204] @ (8004aec <TIM_SlaveTimer_SetConfig+0x144>)
8004a1e: 4293 cmp r3, r2
8004a20: d04f beq.n 8004ac2 <TIM_SlaveTimer_SetConfig+0x11a>
8004a22: 3210 adds r2, #16
8004a24: 4293 cmp r3, r2
8004a26: d14e bne.n 8004ac6 <TIM_SlaveTimer_SetConfig+0x11e>
8004a28: 2000 movs r0, #0
8004a2a: e01f b.n 8004a6c <TIM_SlaveTimer_SetConfig+0xc4>
8004a2c: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
8004a30: d043 beq.n 8004aba <TIM_SlaveTimer_SetConfig+0x112>
8004a32: f1b3 1f10 cmp.w r3, #1048592 @ 0x100010
8004a36: d142 bne.n 8004abe <TIM_SlaveTimer_SetConfig+0x116>
8004a38: 2000 movs r0, #0
8004a3a: e017 b.n 8004a6c <TIM_SlaveTimer_SetConfig+0xc4>
8004a3c: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000
8004a40: d043 beq.n 8004aca <TIM_SlaveTimer_SetConfig+0x122>
8004a42: d807 bhi.n 8004a54 <TIM_SlaveTimer_SetConfig+0xac>
8004a44: 4a2a ldr r2, [pc, #168] @ (8004af0 <TIM_SlaveTimer_SetConfig+0x148>)
8004a46: 4293 cmp r3, r2
8004a48: d041 beq.n 8004ace <TIM_SlaveTimer_SetConfig+0x126>
8004a4a: 3210 adds r2, #16
8004a4c: 4293 cmp r3, r2
8004a4e: d140 bne.n 8004ad2 <TIM_SlaveTimer_SetConfig+0x12a>
8004a50: 2000 movs r0, #0
8004a52: e00b b.n 8004a6c <TIM_SlaveTimer_SetConfig+0xc4>
8004a54: 4a27 ldr r2, [pc, #156] @ (8004af4 <TIM_SlaveTimer_SetConfig+0x14c>)
8004a56: 4293 cmp r3, r2
8004a58: d13d bne.n 8004ad6 <TIM_SlaveTimer_SetConfig+0x12e>
8004a5a: 2000 movs r0, #0
8004a5c: e006 b.n 8004a6c <TIM_SlaveTimer_SetConfig+0xc4>
TIM_ETR_SetConfig(htim->Instance,
8004a5e: 690b ldr r3, [r1, #16]
8004a60: 688a ldr r2, [r1, #8]
8004a62: 68c9 ldr r1, [r1, #12]
8004a64: 6800 ldr r0, [r0, #0]
8004a66: f7ff ff91 bl 800498c <TIM_ETR_SetConfig>
HAL_StatusTypeDef status = HAL_OK;
8004a6a: 2000 movs r0, #0
}
8004a6c: bd10 pop {r4, pc}
if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
8004a6e: 680b ldr r3, [r1, #0]
8004a70: 2b05 cmp r3, #5
8004a72: d032 beq.n 8004ada <TIM_SlaveTimer_SetConfig+0x132>
tmpccer = htim->Instance->CCER;
8004a74: 6803 ldr r3, [r0, #0]
8004a76: 6a1c ldr r4, [r3, #32]
htim->Instance->CCER &= ~TIM_CCER_CC1E;
8004a78: 6a1a ldr r2, [r3, #32]
8004a7a: f022 0201 bic.w r2, r2, #1
8004a7e: 621a str r2, [r3, #32]
tmpccmr1 = htim->Instance->CCMR1;
8004a80: 6802 ldr r2, [r0, #0]
8004a82: 6993 ldr r3, [r2, #24]
tmpccmr1 &= ~TIM_CCMR1_IC1F;
8004a84: f023 03f0 bic.w r3, r3, #240 @ 0xf0
tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
8004a88: 6909 ldr r1, [r1, #16]
8004a8a: ea43 1301 orr.w r3, r3, r1, lsl #4
htim->Instance->CCMR1 = tmpccmr1;
8004a8e: 6193 str r3, [r2, #24]
htim->Instance->CCER = tmpccer;
8004a90: 6803 ldr r3, [r0, #0]
8004a92: 621c str r4, [r3, #32]
HAL_StatusTypeDef status = HAL_OK;
8004a94: 2000 movs r0, #0
break;
8004a96: e7e9 b.n 8004a6c <TIM_SlaveTimer_SetConfig+0xc4>
TIM_TI2_ConfigInputStage(htim->Instance,
8004a98: 690a ldr r2, [r1, #16]
8004a9a: 6889 ldr r1, [r1, #8]
8004a9c: 6800 ldr r0, [r0, #0]
8004a9e: f7ff fdc1 bl 8004624 <TIM_TI2_ConfigInputStage>
HAL_StatusTypeDef status = HAL_OK;
8004aa2: 2000 movs r0, #0
break;
8004aa4: e7e2 b.n 8004a6c <TIM_SlaveTimer_SetConfig+0xc4>
switch (sSlaveConfig->InputTrigger)
8004aa6: 2000 movs r0, #0
8004aa8: e7e0 b.n 8004a6c <TIM_SlaveTimer_SetConfig+0xc4>
8004aaa: 2000 movs r0, #0
8004aac: e7de b.n 8004a6c <TIM_SlaveTimer_SetConfig+0xc4>
status = HAL_ERROR;
8004aae: 2001 movs r0, #1
8004ab0: e7dc b.n 8004a6c <TIM_SlaveTimer_SetConfig+0xc4>
switch (sSlaveConfig->InputTrigger)
8004ab2: 2000 movs r0, #0
8004ab4: e7da b.n 8004a6c <TIM_SlaveTimer_SetConfig+0xc4>
8004ab6: 2000 movs r0, #0
8004ab8: e7d8 b.n 8004a6c <TIM_SlaveTimer_SetConfig+0xc4>
8004aba: 2000 movs r0, #0
8004abc: e7d6 b.n 8004a6c <TIM_SlaveTimer_SetConfig+0xc4>
status = HAL_ERROR;
8004abe: 2001 movs r0, #1
8004ac0: e7d4 b.n 8004a6c <TIM_SlaveTimer_SetConfig+0xc4>
switch (sSlaveConfig->InputTrigger)
8004ac2: 2000 movs r0, #0
8004ac4: e7d2 b.n 8004a6c <TIM_SlaveTimer_SetConfig+0xc4>
status = HAL_ERROR;
8004ac6: 2001 movs r0, #1
8004ac8: e7d0 b.n 8004a6c <TIM_SlaveTimer_SetConfig+0xc4>
switch (sSlaveConfig->InputTrigger)
8004aca: 2000 movs r0, #0
8004acc: e7ce b.n 8004a6c <TIM_SlaveTimer_SetConfig+0xc4>
8004ace: 2000 movs r0, #0
8004ad0: e7cc b.n 8004a6c <TIM_SlaveTimer_SetConfig+0xc4>
status = HAL_ERROR;
8004ad2: 2001 movs r0, #1
8004ad4: e7ca b.n 8004a6c <TIM_SlaveTimer_SetConfig+0xc4>
8004ad6: 2001 movs r0, #1
8004ad8: e7c8 b.n 8004a6c <TIM_SlaveTimer_SetConfig+0xc4>
return HAL_ERROR;
8004ada: 2001 movs r0, #1
8004adc: e7c6 b.n 8004a6c <TIM_SlaveTimer_SetConfig+0xc4>
8004ade: bf00 nop
8004ae0: ffcfff8f .word 0xffcfff8f
8004ae4: fffefff8 .word 0xfffefff8
8004ae8: 00100050 .word 0x00100050
8004aec: 00100030 .word 0x00100030
8004af0: 00100060 .word 0x00100060
8004af4: 00200010 .word 0x00200010
08004af8 <HAL_TIM_SlaveConfigSynchro>:
__HAL_LOCK(htim);
8004af8: f890 303c ldrb.w r3, [r0, #60] @ 0x3c
8004afc: 2b01 cmp r3, #1
8004afe: d022 beq.n 8004b46 <HAL_TIM_SlaveConfigSynchro+0x4e>
{
8004b00: b510 push {r4, lr}
8004b02: 4604 mov r4, r0
__HAL_LOCK(htim);
8004b04: 2301 movs r3, #1
8004b06: f880 303c strb.w r3, [r0, #60] @ 0x3c
htim->State = HAL_TIM_STATE_BUSY;
8004b0a: 2302 movs r3, #2
8004b0c: f880 303d strb.w r3, [r0, #61] @ 0x3d
if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
8004b10: f7ff ff4a bl 80049a8 <TIM_SlaveTimer_SetConfig>
8004b14: b980 cbnz r0, 8004b38 <HAL_TIM_SlaveConfigSynchro+0x40>
__HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
8004b16: 6822 ldr r2, [r4, #0]
8004b18: 68d3 ldr r3, [r2, #12]
8004b1a: f023 0340 bic.w r3, r3, #64 @ 0x40
8004b1e: 60d3 str r3, [r2, #12]
__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
8004b20: 6822 ldr r2, [r4, #0]
8004b22: 68d3 ldr r3, [r2, #12]
8004b24: f423 4380 bic.w r3, r3, #16384 @ 0x4000
8004b28: 60d3 str r3, [r2, #12]
htim->State = HAL_TIM_STATE_READY;
8004b2a: 2301 movs r3, #1
8004b2c: f884 303d strb.w r3, [r4, #61] @ 0x3d
__HAL_UNLOCK(htim);
8004b30: 2300 movs r3, #0
8004b32: f884 303c strb.w r3, [r4, #60] @ 0x3c
}
8004b36: bd10 pop {r4, pc}
htim->State = HAL_TIM_STATE_READY;
8004b38: 2001 movs r0, #1
8004b3a: f884 003d strb.w r0, [r4, #61] @ 0x3d
__HAL_UNLOCK(htim);
8004b3e: 2300 movs r3, #0
8004b40: f884 303c strb.w r3, [r4, #60] @ 0x3c
return HAL_ERROR;
8004b44: e7f7 b.n 8004b36 <HAL_TIM_SlaveConfigSynchro+0x3e>
__HAL_LOCK(htim);
8004b46: 2002 movs r0, #2
}
8004b48: 4770 bx lr
...
08004b4c <HAL_TIMEx_MasterConfigSynchronization>:
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
/* Check input state */
__HAL_LOCK(htim);
8004b4c: f890 203c ldrb.w r2, [r0, #60] @ 0x3c
8004b50: 2a01 cmp r2, #1
8004b52: d045 beq.n 8004be0 <HAL_TIMEx_MasterConfigSynchronization+0x94>
{
8004b54: b470 push {r4, r5, r6}
8004b56: 4603 mov r3, r0
__HAL_LOCK(htim);
8004b58: 2201 movs r2, #1
8004b5a: f880 203c strb.w r2, [r0, #60] @ 0x3c
/* Change the handler state */
htim->State = HAL_TIM_STATE_BUSY;
8004b5e: 2202 movs r2, #2
8004b60: f880 203d strb.w r2, [r0, #61] @ 0x3d
/* Get the TIMx CR2 register value */
tmpcr2 = htim->Instance->CR2;
8004b64: 6802 ldr r2, [r0, #0]
8004b66: 6850 ldr r0, [r2, #4]
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
8004b68: 6894 ldr r4, [r2, #8]
/* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
8004b6a: 4e1e ldr r6, [pc, #120] @ (8004be4 <HAL_TIMEx_MasterConfigSynchronization+0x98>)
8004b6c: 4d1e ldr r5, [pc, #120] @ (8004be8 <HAL_TIMEx_MasterConfigSynchronization+0x9c>)
8004b6e: 42aa cmp r2, r5
8004b70: bf18 it ne
8004b72: 42b2 cmpne r2, r6
8004b74: d103 bne.n 8004b7e <HAL_TIMEx_MasterConfigSynchronization+0x32>
{
/* Check the parameters */
assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
/* Clear the MMS2 bits */
tmpcr2 &= ~TIM_CR2_MMS2;
8004b76: f420 0070 bic.w r0, r0, #15728640 @ 0xf00000
/* Select the TRGO2 source*/
tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
8004b7a: 684d ldr r5, [r1, #4]
8004b7c: 4328 orrs r0, r5
}
/* Reset the MMS Bits */
tmpcr2 &= ~TIM_CR2_MMS;
8004b7e: f020 0070 bic.w r0, r0, #112 @ 0x70
/* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
8004b82: 680d ldr r5, [r1, #0]
8004b84: 4328 orrs r0, r5
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
8004b86: 6050 str r0, [r2, #4]
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
8004b88: 681a ldr r2, [r3, #0]
8004b8a: 4816 ldr r0, [pc, #88] @ (8004be4 <HAL_TIMEx_MasterConfigSynchronization+0x98>)
8004b8c: f1b2 4f80 cmp.w r2, #1073741824 @ 0x40000000
8004b90: bf18 it ne
8004b92: 4282 cmpne r2, r0
8004b94: d017 beq.n 8004bc6 <HAL_TIMEx_MasterConfigSynchronization+0x7a>
8004b96: f5a0 407c sub.w r0, r0, #64512 @ 0xfc00
8004b9a: 4282 cmp r2, r0
8004b9c: d013 beq.n 8004bc6 <HAL_TIMEx_MasterConfigSynchronization+0x7a>
8004b9e: f500 6080 add.w r0, r0, #1024 @ 0x400
8004ba2: 4282 cmp r2, r0
8004ba4: d00f beq.n 8004bc6 <HAL_TIMEx_MasterConfigSynchronization+0x7a>
8004ba6: f500 6080 add.w r0, r0, #1024 @ 0x400
8004baa: 4282 cmp r2, r0
8004bac: d00b beq.n 8004bc6 <HAL_TIMEx_MasterConfigSynchronization+0x7a>
8004bae: f500 4078 add.w r0, r0, #63488 @ 0xf800
8004bb2: 4282 cmp r2, r0
8004bb4: d007 beq.n 8004bc6 <HAL_TIMEx_MasterConfigSynchronization+0x7a>
8004bb6: f5a0 406c sub.w r0, r0, #60416 @ 0xec00
8004bba: 4282 cmp r2, r0
8004bbc: d003 beq.n 8004bc6 <HAL_TIMEx_MasterConfigSynchronization+0x7a>
8004bbe: f500 3094 add.w r0, r0, #75776 @ 0x12800
8004bc2: 4282 cmp r2, r0
8004bc4: d104 bne.n 8004bd0 <HAL_TIMEx_MasterConfigSynchronization+0x84>
{
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
8004bc6: f024 0480 bic.w r4, r4, #128 @ 0x80
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
8004bca: 6889 ldr r1, [r1, #8]
8004bcc: 4321 orrs r1, r4
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
8004bce: 6091 str r1, [r2, #8]
}
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
8004bd0: 2201 movs r2, #1
8004bd2: f883 203d strb.w r2, [r3, #61] @ 0x3d
__HAL_UNLOCK(htim);
8004bd6: 2000 movs r0, #0
8004bd8: f883 003c strb.w r0, [r3, #60] @ 0x3c
return HAL_OK;
}
8004bdc: bc70 pop {r4, r5, r6}
8004bde: 4770 bx lr
__HAL_LOCK(htim);
8004be0: 2002 movs r0, #2
}
8004be2: 4770 bx lr
8004be4: 40010000 .word 0x40010000
8004be8: 40010400 .word 0x40010400
08004bec <NMI_Handler>:
{
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8004bec: e7fe b.n 8004bec <NMI_Handler>
08004bee <HardFault_Handler>:
void HardFault_Handler(void)
{
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8004bee: e7fe b.n 8004bee <HardFault_Handler>
08004bf0 <MemManage_Handler>:
void MemManage_Handler(void)
{
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
8004bf0: e7fe b.n 8004bf0 <MemManage_Handler>
08004bf2 <BusFault_Handler>:
void BusFault_Handler(void)
{
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
8004bf2: e7fe b.n 8004bf2 <BusFault_Handler>
08004bf4 <UsageFault_Handler>:
void UsageFault_Handler(void)
{
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
8004bf4: e7fe b.n 8004bf4 <UsageFault_Handler>
08004bf6 <SVC_Handler>:
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
8004bf6: 4770 bx lr
08004bf8 <DebugMon_Handler>:
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
8004bf8: 4770 bx lr
08004bfa <PendSV_Handler>:
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
8004bfa: 4770 bx lr
08004bfc <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
8004bfc: b508 push {r3, lr}
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
8004bfe: f7fb fe67 bl 80008d0 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
8004c02: bd08 pop {r3, pc}
08004c04 <FDCAN1_IT0_IRQHandler>:
/**
* @brief This function handles FDCAN1 interrupt 0.
*/
void FDCAN1_IT0_IRQHandler(void)
{
8004c04: b508 push {r3, lr}
/* USER CODE BEGIN FDCAN1_IT0_IRQn 0 */
/* USER CODE END FDCAN1_IT0_IRQn 0 */
HAL_FDCAN_IRQHandler(&hfdcan1);
8004c06: 4802 ldr r0, [pc, #8] @ (8004c10 <FDCAN1_IT0_IRQHandler+0xc>)
8004c08: f7fc fd78 bl 80016fc <HAL_FDCAN_IRQHandler>
/* USER CODE BEGIN FDCAN1_IT0_IRQn 1 */
/* USER CODE END FDCAN1_IT0_IRQn 1 */
}
8004c0c: bd08 pop {r3, pc}
8004c0e: bf00 nop
8004c10: 20000188 .word 0x20000188
08004c14 <SystemInit>:
__IO uint32_t tmpreg;
#endif /* DATA_IN_D2_SRAM */
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */
8004c14: 4a22 ldr r2, [pc, #136] @ (8004ca0 <SystemInit+0x8c>)
8004c16: f8d2 3088 ldr.w r3, [r2, #136] @ 0x88
8004c1a: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000
8004c1e: f8c2 3088 str.w r3, [r2, #136] @ 0x88
#endif
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Increasing the CPU frequency */
if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
8004c22: 4b20 ldr r3, [pc, #128] @ (8004ca4 <SystemInit+0x90>)
8004c24: 681b ldr r3, [r3, #0]
8004c26: f003 030f and.w r3, r3, #15
8004c2a: 2b02 cmp r3, #2
8004c2c: d806 bhi.n 8004c3c <SystemInit+0x28>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
8004c2e: 4a1d ldr r2, [pc, #116] @ (8004ca4 <SystemInit+0x90>)
8004c30: 6813 ldr r3, [r2, #0]
8004c32: f023 030f bic.w r3, r3, #15
8004c36: f043 0303 orr.w r3, r3, #3
8004c3a: 6013 str r3, [r2, #0]
}
/* Set HSION bit */
RCC->CR |= RCC_CR_HSION;
8004c3c: 4b1a ldr r3, [pc, #104] @ (8004ca8 <SystemInit+0x94>)
8004c3e: 681a ldr r2, [r3, #0]
8004c40: f042 0201 orr.w r2, r2, #1
8004c44: 601a str r2, [r3, #0]
/* Reset CFGR register */
RCC->CFGR = 0x00000000;
8004c46: 2200 movs r2, #0
8004c48: 611a str r2, [r3, #16]
/* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */
RCC->CR &= 0xEAF6ED7FU;
8004c4a: 6819 ldr r1, [r3, #0]
8004c4c: 4a17 ldr r2, [pc, #92] @ (8004cac <SystemInit+0x98>)
8004c4e: 400a ands r2, r1
8004c50: 601a str r2, [r3, #0]
/* Decreasing the number of wait states because of lower CPU frequency */
if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
8004c52: 4b14 ldr r3, [pc, #80] @ (8004ca4 <SystemInit+0x90>)
8004c54: 681b ldr r3, [r3, #0]
8004c56: f013 0f0c tst.w r3, #12
8004c5a: d006 beq.n 8004c6a <SystemInit+0x56>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
8004c5c: 4a11 ldr r2, [pc, #68] @ (8004ca4 <SystemInit+0x90>)
8004c5e: 6813 ldr r3, [r2, #0]
8004c60: f023 030f bic.w r3, r3, #15
8004c64: f043 0303 orr.w r3, r3, #3
8004c68: 6013 str r3, [r2, #0]
/* Reset D3CFGR register */
RCC->D3CFGR = 0x00000000;
#else
/* Reset CDCFGR1 register */
RCC->CDCFGR1 = 0x00000000;
8004c6a: 4b0f ldr r3, [pc, #60] @ (8004ca8 <SystemInit+0x94>)
8004c6c: 2200 movs r2, #0
8004c6e: 619a str r2, [r3, #24]
/* Reset CDCFGR2 register */
RCC->CDCFGR2 = 0x00000000;
8004c70: 61da str r2, [r3, #28]
/* Reset SRDCFGR register */
RCC->SRDCFGR = 0x00000000;
8004c72: 621a str r2, [r3, #32]
#endif
/* Reset PLLCKSELR register */
RCC->PLLCKSELR = 0x02020200;
8004c74: 490e ldr r1, [pc, #56] @ (8004cb0 <SystemInit+0x9c>)
8004c76: 6299 str r1, [r3, #40] @ 0x28
/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x01FF0000;
8004c78: 490e ldr r1, [pc, #56] @ (8004cb4 <SystemInit+0xa0>)
8004c7a: 62d9 str r1, [r3, #44] @ 0x2c
/* Reset PLL1DIVR register */
RCC->PLL1DIVR = 0x01010280;
8004c7c: 490e ldr r1, [pc, #56] @ (8004cb8 <SystemInit+0xa4>)
8004c7e: 6319 str r1, [r3, #48] @ 0x30
/* Reset PLL1FRACR register */
RCC->PLL1FRACR = 0x00000000;
8004c80: 635a str r2, [r3, #52] @ 0x34
/* Reset PLL2DIVR register */
RCC->PLL2DIVR = 0x01010280;
8004c82: 6399 str r1, [r3, #56] @ 0x38
/* Reset PLL2FRACR register */
RCC->PLL2FRACR = 0x00000000;
8004c84: 63da str r2, [r3, #60] @ 0x3c
/* Reset PLL3DIVR register */
RCC->PLL3DIVR = 0x01010280;
8004c86: 6419 str r1, [r3, #64] @ 0x40
/* Reset PLL3FRACR register */
RCC->PLL3FRACR = 0x00000000;
8004c88: 645a str r2, [r3, #68] @ 0x44
/* Reset HSEBYP bit */
RCC->CR &= 0xFFFBFFFFU;
8004c8a: 6819 ldr r1, [r3, #0]
8004c8c: f421 2180 bic.w r1, r1, #262144 @ 0x40000
8004c90: 6019 str r1, [r3, #0]
/* Disable all interrupts */
RCC->CIER = 0x00000000;
8004c92: 661a str r2, [r3, #96] @ 0x60
/*
* Disable the FMC bank1 (enabled after reset).
* This, prevents CPU speculation access on this bank which blocks the use of FMC during
* 24us. During this time the others FMC master (such as LTDC) cannot use it!
*/
FMC_Bank1_R->BTCR[0] = 0x000030D2;
8004c94: 4b09 ldr r3, [pc, #36] @ (8004cbc <SystemInit+0xa8>)
8004c96: f243 02d2 movw r2, #12498 @ 0x30d2
8004c9a: 601a str r2, [r3, #0]
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */
#endif /* USER_VECT_TAB_ADDRESS */
#endif /*DUAL_CORE && CORE_CM4*/
}
8004c9c: 4770 bx lr
8004c9e: bf00 nop
8004ca0: e000ed00 .word 0xe000ed00
8004ca4: 52002000 .word 0x52002000
8004ca8: 58024400 .word 0x58024400
8004cac: eaf6ed7f .word 0xeaf6ed7f
8004cb0: 02020200 .word 0x02020200
8004cb4: 01ff0000 .word 0x01ff0000
8004cb8: 01010280 .word 0x01010280
8004cbc: 52004000 .word 0x52004000
08004cc0 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
8004cc0: f8df d034 ldr.w sp, [pc, #52] @ 8004cf8 <LoopFillZerobss+0xe>
/* Call the clock system initialization function.*/
bl SystemInit
8004cc4: f7ff ffa6 bl 8004c14 <SystemInit>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
8004cc8: 480c ldr r0, [pc, #48] @ (8004cfc <LoopFillZerobss+0x12>)
ldr r1, =_edata
8004cca: 490d ldr r1, [pc, #52] @ (8004d00 <LoopFillZerobss+0x16>)
ldr r2, =_sidata
8004ccc: 4a0d ldr r2, [pc, #52] @ (8004d04 <LoopFillZerobss+0x1a>)
movs r3, #0
8004cce: 2300 movs r3, #0
b LoopCopyDataInit
8004cd0: e002 b.n 8004cd8 <LoopCopyDataInit>
08004cd2 <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
8004cd2: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
8004cd4: 50c4 str r4, [r0, r3]
adds r3, r3, #4
8004cd6: 3304 adds r3, #4
08004cd8 <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
8004cd8: 18c4 adds r4, r0, r3
cmp r4, r1
8004cda: 428c cmp r4, r1
bcc CopyDataInit
8004cdc: d3f9 bcc.n 8004cd2 <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
8004cde: 4a0a ldr r2, [pc, #40] @ (8004d08 <LoopFillZerobss+0x1e>)
ldr r4, =_ebss
8004ce0: 4c0a ldr r4, [pc, #40] @ (8004d0c <LoopFillZerobss+0x22>)
movs r3, #0
8004ce2: 2300 movs r3, #0
b LoopFillZerobss
8004ce4: e001 b.n 8004cea <LoopFillZerobss>
08004ce6 <FillZerobss>:
FillZerobss:
str r3, [r2]
8004ce6: 6013 str r3, [r2, #0]
adds r2, r2, #4
8004ce8: 3204 adds r2, #4
08004cea <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
8004cea: 42a2 cmp r2, r4
bcc FillZerobss
8004cec: d3fb bcc.n 8004ce6 <FillZerobss>
/* Call static constructors */
bl __libc_init_array
8004cee: f000 f819 bl 8004d24 <__libc_init_array>
/* Call the application's entry point.*/
bl main
8004cf2: f7fb fd81 bl 80007f8 <main>
bx lr
8004cf6: 4770 bx lr
ldr sp, =_estack /* set stack pointer */
8004cf8: 20020000 .word 0x20020000
ldr r0, =_sdata
8004cfc: 20000000 .word 0x20000000
ldr r1, =_edata
8004d00: 20000010 .word 0x20000010
ldr r2, =_sidata
8004d04: 08004e04 .word 0x08004e04
ldr r2, =_sbss
8004d08: 20000010 .word 0x20000010
ldr r4, =_ebss
8004d0c: 200002f8 .word 0x200002f8
08004d10 <ADC_IRQHandler>:
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8004d10: e7fe b.n 8004d10 <ADC_IRQHandler>
08004d12 <memset>:
8004d12: 4402 add r2, r0
8004d14: 4603 mov r3, r0
8004d16: 4293 cmp r3, r2
8004d18: d100 bne.n 8004d1c <memset+0xa>
8004d1a: 4770 bx lr
8004d1c: f803 1b01 strb.w r1, [r3], #1
8004d20: e7f9 b.n 8004d16 <memset+0x4>
...
08004d24 <__libc_init_array>:
8004d24: b570 push {r4, r5, r6, lr}
8004d26: 4b0d ldr r3, [pc, #52] @ (8004d5c <__libc_init_array+0x38>)
8004d28: 4d0d ldr r5, [pc, #52] @ (8004d60 <__libc_init_array+0x3c>)
8004d2a: 1b5b subs r3, r3, r5
8004d2c: 109c asrs r4, r3, #2
8004d2e: 2600 movs r6, #0
8004d30: 42a6 cmp r6, r4
8004d32: d109 bne.n 8004d48 <__libc_init_array+0x24>
8004d34: f000 f828 bl 8004d88 <_init>
8004d38: 4d0a ldr r5, [pc, #40] @ (8004d64 <__libc_init_array+0x40>)
8004d3a: 4b0b ldr r3, [pc, #44] @ (8004d68 <__libc_init_array+0x44>)
8004d3c: 1b5b subs r3, r3, r5
8004d3e: 109c asrs r4, r3, #2
8004d40: 2600 movs r6, #0
8004d42: 42a6 cmp r6, r4
8004d44: d105 bne.n 8004d52 <__libc_init_array+0x2e>
8004d46: bd70 pop {r4, r5, r6, pc}
8004d48: f855 3b04 ldr.w r3, [r5], #4
8004d4c: 4798 blx r3
8004d4e: 3601 adds r6, #1
8004d50: e7ee b.n 8004d30 <__libc_init_array+0xc>
8004d52: f855 3b04 ldr.w r3, [r5], #4
8004d56: 4798 blx r3
8004d58: 3601 adds r6, #1
8004d5a: e7f2 b.n 8004d42 <__libc_init_array+0x1e>
8004d5c: 08004dfc .word 0x08004dfc
8004d60: 08004dfc .word 0x08004dfc
8004d64: 08004dfc .word 0x08004dfc
8004d68: 08004e00 .word 0x08004e00
08004d6c <memcpy>:
8004d6c: 440a add r2, r1
8004d6e: 4291 cmp r1, r2
8004d70: f100 33ff add.w r3, r0, #4294967295
8004d74: d100 bne.n 8004d78 <memcpy+0xc>
8004d76: 4770 bx lr
8004d78: b510 push {r4, lr}
8004d7a: f811 4b01 ldrb.w r4, [r1], #1
8004d7e: f803 4f01 strb.w r4, [r3, #1]!
8004d82: 4291 cmp r1, r2
8004d84: d1f9 bne.n 8004d7a <memcpy+0xe>
8004d86: bd10 pop {r4, pc}
08004d88 <_init>:
8004d88: b5f8 push {r3, r4, r5, r6, r7, lr}
8004d8a: bf00 nop
8004d8c: bcf8 pop {r3, r4, r5, r6, r7}
8004d8e: bc08 pop {r3}
8004d90: 469e mov lr, r3
8004d92: 4770 bx lr
08004d94 <_fini>:
8004d94: b5f8 push {r3, r4, r5, r6, r7, lr}
8004d96: bf00 nop
8004d98: bcf8 pop {r3, r4, r5, r6, r7}
8004d9a: bc08 pop {r3}
8004d9c: 469e mov lr, r3
8004d9e: 4770 bx lr
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