ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 1 1 .cpu cortex-m7 2 .arch armv7e-m 3 .fpu fpv5-d16 4 .eabi_attribute 28, 1 5 .eabi_attribute 20, 1 6 .eabi_attribute 21, 1 7 .eabi_attribute 23, 3 8 .eabi_attribute 24, 1 9 .eabi_attribute 25, 1 10 .eabi_attribute 26, 1 11 .eabi_attribute 30, 1 12 .eabi_attribute 34, 1 13 .eabi_attribute 18, 4 14 .file "main.c" 15 .text 16 .Ltext0: 17 .cfi_sections .debug_frame 18 .file 1 "Core/Src/main.c" 19 .section .text.MX_GPIO_Init,"ax",%progbits 20 .align 1 21 .syntax unified 22 .thumb 23 .thumb_func 25 MX_GPIO_Init: 26 .LFB344: 1:Core/Src/main.c **** /* USER CODE BEGIN Header */ 2:Core/Src/main.c **** /** 3:Core/Src/main.c **** ****************************************************************************** 4:Core/Src/main.c **** * @file : main.c 5:Core/Src/main.c **** * @brief : Main program body 6:Core/Src/main.c **** ****************************************************************************** 7:Core/Src/main.c **** * @attention 8:Core/Src/main.c **** * 9:Core/Src/main.c **** * Copyright (c) 2025 STMicroelectronics. 10:Core/Src/main.c **** * All rights reserved. 11:Core/Src/main.c **** * 12:Core/Src/main.c **** * This software is licensed under terms that can be found in the LICENSE file 13:Core/Src/main.c **** * in the root directory of this software component. 14:Core/Src/main.c **** * If no LICENSE file comes with this software, it is provided AS-IS. 15:Core/Src/main.c **** * 16:Core/Src/main.c **** ****************************************************************************** 17:Core/Src/main.c **** */ 18:Core/Src/main.c **** /* USER CODE END Header */ 19:Core/Src/main.c **** /* Includes ------------------------------------------------------------------*/ 20:Core/Src/main.c **** #include "main.h" 21:Core/Src/main.c **** 22:Core/Src/main.c **** /* Private includes ----------------------------------------------------------*/ 23:Core/Src/main.c **** /* USER CODE BEGIN Includes */ 24:Core/Src/main.c **** 25:Core/Src/main.c **** /* USER CODE END Includes */ 26:Core/Src/main.c **** 27:Core/Src/main.c **** /* Private typedef -----------------------------------------------------------*/ 28:Core/Src/main.c **** /* USER CODE BEGIN PTD */ 29:Core/Src/main.c **** 30:Core/Src/main.c **** /* USER CODE END PTD */ 31:Core/Src/main.c **** 32:Core/Src/main.c **** /* Private define ------------------------------------------------------------*/ ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 2 33:Core/Src/main.c **** /* USER CODE BEGIN PD */ 34:Core/Src/main.c **** 35:Core/Src/main.c **** /* USER CODE END PD */ 36:Core/Src/main.c **** 37:Core/Src/main.c **** /* Private macro -------------------------------------------------------------*/ 38:Core/Src/main.c **** /* USER CODE BEGIN PM */ 39:Core/Src/main.c **** 40:Core/Src/main.c **** /* USER CODE END PM */ 41:Core/Src/main.c **** 42:Core/Src/main.c **** /* Private variables ---------------------------------------------------------*/ 43:Core/Src/main.c **** ADC_HandleTypeDef hadc1; 44:Core/Src/main.c **** ADC_HandleTypeDef hadc2; 45:Core/Src/main.c **** 46:Core/Src/main.c **** FDCAN_HandleTypeDef hfdcan1; 47:Core/Src/main.c **** 48:Core/Src/main.c **** SPI_HandleTypeDef hspi1; 49:Core/Src/main.c **** SPI_HandleTypeDef hspi2; 50:Core/Src/main.c **** 51:Core/Src/main.c **** TIM_HandleTypeDef htim15; 52:Core/Src/main.c **** 53:Core/Src/main.c **** /* USER CODE BEGIN PV */ 54:Core/Src/main.c **** 55:Core/Src/main.c **** /* USER CODE END PV */ 56:Core/Src/main.c **** 57:Core/Src/main.c **** /* Private function prototypes -----------------------------------------------*/ 58:Core/Src/main.c **** void SystemClock_Config(void); 59:Core/Src/main.c **** void PeriphCommonClock_Config(void); 60:Core/Src/main.c **** static void MX_GPIO_Init(void); 61:Core/Src/main.c **** static void MX_FDCAN1_Init(void); 62:Core/Src/main.c **** static void MX_TIM15_Init(void); 63:Core/Src/main.c **** static void MX_SPI1_Init(void); 64:Core/Src/main.c **** static void MX_SPI2_Init(void); 65:Core/Src/main.c **** static void MX_ADC1_Init(void); 66:Core/Src/main.c **** static void MX_ADC2_Init(void); 67:Core/Src/main.c **** /* USER CODE BEGIN PFP */ 68:Core/Src/main.c **** 69:Core/Src/main.c **** /* USER CODE END PFP */ 70:Core/Src/main.c **** 71:Core/Src/main.c **** /* Private user code ---------------------------------------------------------*/ 72:Core/Src/main.c **** /* USER CODE BEGIN 0 */ 73:Core/Src/main.c **** 74:Core/Src/main.c **** /* USER CODE END 0 */ 75:Core/Src/main.c **** 76:Core/Src/main.c **** /** 77:Core/Src/main.c **** * @brief The application entry point. 78:Core/Src/main.c **** * @retval int 79:Core/Src/main.c **** */ 80:Core/Src/main.c **** int main(void) 81:Core/Src/main.c **** { 82:Core/Src/main.c **** /* USER CODE BEGIN 1 */ 83:Core/Src/main.c **** 84:Core/Src/main.c **** /* USER CODE END 1 */ 85:Core/Src/main.c **** 86:Core/Src/main.c **** /* MCU Configuration--------------------------------------------------------*/ 87:Core/Src/main.c **** 88:Core/Src/main.c **** /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ 89:Core/Src/main.c **** HAL_Init(); ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 3 90:Core/Src/main.c **** 91:Core/Src/main.c **** /* USER CODE BEGIN Init */ 92:Core/Src/main.c **** 93:Core/Src/main.c **** /* USER CODE END Init */ 94:Core/Src/main.c **** 95:Core/Src/main.c **** /* Configure the system clock */ 96:Core/Src/main.c **** SystemClock_Config(); 97:Core/Src/main.c **** 98:Core/Src/main.c **** /* Configure the peripherals common clocks */ 99:Core/Src/main.c **** PeriphCommonClock_Config(); 100:Core/Src/main.c **** 101:Core/Src/main.c **** /* USER CODE BEGIN SysInit */ 102:Core/Src/main.c **** 103:Core/Src/main.c **** /* USER CODE END SysInit */ 104:Core/Src/main.c **** 105:Core/Src/main.c **** /* Initialize all configured peripherals */ 106:Core/Src/main.c **** MX_GPIO_Init(); 107:Core/Src/main.c **** MX_FDCAN1_Init(); 108:Core/Src/main.c **** MX_TIM15_Init(); 109:Core/Src/main.c **** MX_SPI1_Init(); 110:Core/Src/main.c **** MX_SPI2_Init(); 111:Core/Src/main.c **** MX_ADC1_Init(); 112:Core/Src/main.c **** MX_ADC2_Init(); 113:Core/Src/main.c **** /* USER CODE BEGIN 2 */ 114:Core/Src/main.c **** 115:Core/Src/main.c **** /* USER CODE END 2 */ 116:Core/Src/main.c **** 117:Core/Src/main.c **** /* Infinite loop */ 118:Core/Src/main.c **** /* USER CODE BEGIN WHILE */ 119:Core/Src/main.c **** while (1) 120:Core/Src/main.c **** { 121:Core/Src/main.c **** /* USER CODE END WHILE */ 122:Core/Src/main.c **** 123:Core/Src/main.c **** /* USER CODE BEGIN 3 */ 124:Core/Src/main.c **** } 125:Core/Src/main.c **** /* USER CODE END 3 */ 126:Core/Src/main.c **** } 127:Core/Src/main.c **** 128:Core/Src/main.c **** /** 129:Core/Src/main.c **** * @brief System Clock Configuration 130:Core/Src/main.c **** * @retval None 131:Core/Src/main.c **** */ 132:Core/Src/main.c **** void SystemClock_Config(void) 133:Core/Src/main.c **** { 134:Core/Src/main.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 135:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 136:Core/Src/main.c **** 137:Core/Src/main.c **** /*AXI clock gating */ 138:Core/Src/main.c **** RCC->CKGAENR = 0xFFFFFFFF; 139:Core/Src/main.c **** 140:Core/Src/main.c **** /** Supply configuration update enable 141:Core/Src/main.c **** */ 142:Core/Src/main.c **** HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); 143:Core/Src/main.c **** 144:Core/Src/main.c **** /** Configure the main internal regulator output voltage 145:Core/Src/main.c **** */ 146:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3); ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 4 147:Core/Src/main.c **** 148:Core/Src/main.c **** while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} 149:Core/Src/main.c **** 150:Core/Src/main.c **** /** Initializes the RCC Oscillators according to the specified parameters 151:Core/Src/main.c **** * in the RCC_OscInitTypeDef structure. 152:Core/Src/main.c **** */ 153:Core/Src/main.c **** RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 154:Core/Src/main.c **** RCC_OscInitStruct.HSEState = RCC_HSE_ON; 155:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 156:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 157:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLM = 1; 158:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 8; 159:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLP = 2; 160:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = 2; 161:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLR = 2; 162:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3; 163:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; 164:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLFRACN = 0; 165:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 166:Core/Src/main.c **** { 167:Core/Src/main.c **** Error_Handler(); 168:Core/Src/main.c **** } 169:Core/Src/main.c **** 170:Core/Src/main.c **** /** Initializes the CPU, AHB and APB buses clocks 171:Core/Src/main.c **** */ 172:Core/Src/main.c **** RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 173:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 174:Core/Src/main.c **** |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1; 175:Core/Src/main.c **** RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 176:Core/Src/main.c **** RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; 177:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV1; 178:Core/Src/main.c **** RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV1; 179:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV1; 180:Core/Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV1; 181:Core/Src/main.c **** RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV1; 182:Core/Src/main.c **** 183:Core/Src/main.c **** if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 184:Core/Src/main.c **** { 185:Core/Src/main.c **** Error_Handler(); 186:Core/Src/main.c **** } 187:Core/Src/main.c **** } 188:Core/Src/main.c **** 189:Core/Src/main.c **** /** 190:Core/Src/main.c **** * @brief Peripherals Common Clock Configuration 191:Core/Src/main.c **** * @retval None 192:Core/Src/main.c **** */ 193:Core/Src/main.c **** void PeriphCommonClock_Config(void) 194:Core/Src/main.c **** { 195:Core/Src/main.c **** RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 196:Core/Src/main.c **** 197:Core/Src/main.c **** /** Initializes the peripherals clock 198:Core/Src/main.c **** */ 199:Core/Src/main.c **** PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADC|RCC_PERIPHCLK_FDCAN; 200:Core/Src/main.c **** PeriphClkInitStruct.PLL2.PLL2M = 1; 201:Core/Src/main.c **** PeriphClkInitStruct.PLL2.PLL2N = 8; 202:Core/Src/main.c **** PeriphClkInitStruct.PLL2.PLL2P = 3; 203:Core/Src/main.c **** PeriphClkInitStruct.PLL2.PLL2Q = 3; ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 5 204:Core/Src/main.c **** PeriphClkInitStruct.PLL2.PLL2R = 2; 205:Core/Src/main.c **** PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_3; 206:Core/Src/main.c **** PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE; 207:Core/Src/main.c **** PeriphClkInitStruct.PLL2.PLL2FRACN = 0; 208:Core/Src/main.c **** PeriphClkInitStruct.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL2; 209:Core/Src/main.c **** PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLL2; 210:Core/Src/main.c **** if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 211:Core/Src/main.c **** { 212:Core/Src/main.c **** Error_Handler(); 213:Core/Src/main.c **** } 214:Core/Src/main.c **** } 215:Core/Src/main.c **** 216:Core/Src/main.c **** /** 217:Core/Src/main.c **** * @brief ADC1 Initialization Function 218:Core/Src/main.c **** * @param None 219:Core/Src/main.c **** * @retval None 220:Core/Src/main.c **** */ 221:Core/Src/main.c **** static void MX_ADC1_Init(void) 222:Core/Src/main.c **** { 223:Core/Src/main.c **** 224:Core/Src/main.c **** /* USER CODE BEGIN ADC1_Init 0 */ 225:Core/Src/main.c **** 226:Core/Src/main.c **** /* USER CODE END ADC1_Init 0 */ 227:Core/Src/main.c **** 228:Core/Src/main.c **** ADC_MultiModeTypeDef multimode = {0}; 229:Core/Src/main.c **** ADC_ChannelConfTypeDef sConfig = {0}; 230:Core/Src/main.c **** 231:Core/Src/main.c **** /* USER CODE BEGIN ADC1_Init 1 */ 232:Core/Src/main.c **** 233:Core/Src/main.c **** /* USER CODE END ADC1_Init 1 */ 234:Core/Src/main.c **** 235:Core/Src/main.c **** /** Common config 236:Core/Src/main.c **** */ 237:Core/Src/main.c **** hadc1.Instance = ADC1; 238:Core/Src/main.c **** hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; 239:Core/Src/main.c **** hadc1.Init.Resolution = ADC_RESOLUTION_16B; 240:Core/Src/main.c **** hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE; 241:Core/Src/main.c **** hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 242:Core/Src/main.c **** hadc1.Init.LowPowerAutoWait = DISABLE; 243:Core/Src/main.c **** hadc1.Init.ContinuousConvMode = DISABLE; 244:Core/Src/main.c **** hadc1.Init.NbrOfConversion = 1; 245:Core/Src/main.c **** hadc1.Init.DiscontinuousConvMode = DISABLE; 246:Core/Src/main.c **** hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; 247:Core/Src/main.c **** hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; 248:Core/Src/main.c **** hadc1.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR; 249:Core/Src/main.c **** hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED; 250:Core/Src/main.c **** hadc1.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE; 251:Core/Src/main.c **** hadc1.Init.OversamplingMode = DISABLE; 252:Core/Src/main.c **** if (HAL_ADC_Init(&hadc1) != HAL_OK) 253:Core/Src/main.c **** { 254:Core/Src/main.c **** Error_Handler(); 255:Core/Src/main.c **** } 256:Core/Src/main.c **** 257:Core/Src/main.c **** /** Configure the ADC multi-mode 258:Core/Src/main.c **** */ 259:Core/Src/main.c **** multimode.Mode = ADC_MODE_INDEPENDENT; 260:Core/Src/main.c **** if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK) ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 6 261:Core/Src/main.c **** { 262:Core/Src/main.c **** Error_Handler(); 263:Core/Src/main.c **** } 264:Core/Src/main.c **** 265:Core/Src/main.c **** /** Configure Regular Channel 266:Core/Src/main.c **** */ 267:Core/Src/main.c **** sConfig.Channel = ADC_CHANNEL_10; 268:Core/Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_1; 269:Core/Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5; 270:Core/Src/main.c **** sConfig.SingleDiff = ADC_SINGLE_ENDED; 271:Core/Src/main.c **** sConfig.OffsetNumber = ADC_OFFSET_NONE; 272:Core/Src/main.c **** sConfig.Offset = 0; 273:Core/Src/main.c **** sConfig.OffsetSignedSaturation = DISABLE; 274:Core/Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 275:Core/Src/main.c **** { 276:Core/Src/main.c **** Error_Handler(); 277:Core/Src/main.c **** } 278:Core/Src/main.c **** /* USER CODE BEGIN ADC1_Init 2 */ 279:Core/Src/main.c **** 280:Core/Src/main.c **** /* USER CODE END ADC1_Init 2 */ 281:Core/Src/main.c **** 282:Core/Src/main.c **** } 283:Core/Src/main.c **** 284:Core/Src/main.c **** /** 285:Core/Src/main.c **** * @brief ADC2 Initialization Function 286:Core/Src/main.c **** * @param None 287:Core/Src/main.c **** * @retval None 288:Core/Src/main.c **** */ 289:Core/Src/main.c **** static void MX_ADC2_Init(void) 290:Core/Src/main.c **** { 291:Core/Src/main.c **** 292:Core/Src/main.c **** /* USER CODE BEGIN ADC2_Init 0 */ 293:Core/Src/main.c **** 294:Core/Src/main.c **** /* USER CODE END ADC2_Init 0 */ 295:Core/Src/main.c **** 296:Core/Src/main.c **** ADC_ChannelConfTypeDef sConfig = {0}; 297:Core/Src/main.c **** 298:Core/Src/main.c **** /* USER CODE BEGIN ADC2_Init 1 */ 299:Core/Src/main.c **** 300:Core/Src/main.c **** /* USER CODE END ADC2_Init 1 */ 301:Core/Src/main.c **** 302:Core/Src/main.c **** /** Common config 303:Core/Src/main.c **** */ 304:Core/Src/main.c **** hadc2.Instance = ADC2; 305:Core/Src/main.c **** hadc2.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; 306:Core/Src/main.c **** hadc2.Init.Resolution = ADC_RESOLUTION_16B; 307:Core/Src/main.c **** hadc2.Init.ScanConvMode = ADC_SCAN_DISABLE; 308:Core/Src/main.c **** hadc2.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 309:Core/Src/main.c **** hadc2.Init.LowPowerAutoWait = DISABLE; 310:Core/Src/main.c **** hadc2.Init.ContinuousConvMode = DISABLE; 311:Core/Src/main.c **** hadc2.Init.NbrOfConversion = 1; 312:Core/Src/main.c **** hadc2.Init.DiscontinuousConvMode = DISABLE; 313:Core/Src/main.c **** hadc2.Init.ExternalTrigConv = ADC_SOFTWARE_START; 314:Core/Src/main.c **** hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; 315:Core/Src/main.c **** hadc2.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR; 316:Core/Src/main.c **** hadc2.Init.Overrun = ADC_OVR_DATA_PRESERVED; 317:Core/Src/main.c **** hadc2.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE; ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 7 318:Core/Src/main.c **** hadc2.Init.OversamplingMode = DISABLE; 319:Core/Src/main.c **** if (HAL_ADC_Init(&hadc2) != HAL_OK) 320:Core/Src/main.c **** { 321:Core/Src/main.c **** Error_Handler(); 322:Core/Src/main.c **** } 323:Core/Src/main.c **** 324:Core/Src/main.c **** /** Configure Regular Channel 325:Core/Src/main.c **** */ 326:Core/Src/main.c **** sConfig.Channel = ADC_CHANNEL_10; 327:Core/Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_1; 328:Core/Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5; 329:Core/Src/main.c **** sConfig.SingleDiff = ADC_DIFFERENTIAL_ENDED; 330:Core/Src/main.c **** sConfig.OffsetNumber = ADC_OFFSET_NONE; 331:Core/Src/main.c **** sConfig.Offset = 0; 332:Core/Src/main.c **** sConfig.OffsetSignedSaturation = DISABLE; 333:Core/Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 334:Core/Src/main.c **** { 335:Core/Src/main.c **** Error_Handler(); 336:Core/Src/main.c **** } 337:Core/Src/main.c **** /* USER CODE BEGIN ADC2_Init 2 */ 338:Core/Src/main.c **** 339:Core/Src/main.c **** /* USER CODE END ADC2_Init 2 */ 340:Core/Src/main.c **** 341:Core/Src/main.c **** } 342:Core/Src/main.c **** 343:Core/Src/main.c **** /** 344:Core/Src/main.c **** * @brief FDCAN1 Initialization Function 345:Core/Src/main.c **** * @param None 346:Core/Src/main.c **** * @retval None 347:Core/Src/main.c **** */ 348:Core/Src/main.c **** static void MX_FDCAN1_Init(void) 349:Core/Src/main.c **** { 350:Core/Src/main.c **** 351:Core/Src/main.c **** /* USER CODE BEGIN FDCAN1_Init 0 */ 352:Core/Src/main.c **** 353:Core/Src/main.c **** /* USER CODE END FDCAN1_Init 0 */ 354:Core/Src/main.c **** 355:Core/Src/main.c **** /* USER CODE BEGIN FDCAN1_Init 1 */ 356:Core/Src/main.c **** 357:Core/Src/main.c **** /* USER CODE END FDCAN1_Init 1 */ 358:Core/Src/main.c **** hfdcan1.Instance = FDCAN1; 359:Core/Src/main.c **** hfdcan1.Init.FrameFormat = FDCAN_FRAME_CLASSIC; 360:Core/Src/main.c **** hfdcan1.Init.Mode = FDCAN_MODE_NORMAL; 361:Core/Src/main.c **** hfdcan1.Init.AutoRetransmission = DISABLE; 362:Core/Src/main.c **** hfdcan1.Init.TransmitPause = DISABLE; 363:Core/Src/main.c **** hfdcan1.Init.ProtocolException = DISABLE; 364:Core/Src/main.c **** hfdcan1.Init.NominalPrescaler = 2; 365:Core/Src/main.c **** hfdcan1.Init.NominalSyncJumpWidth = 1; 366:Core/Src/main.c **** hfdcan1.Init.NominalTimeSeg1 = 31; 367:Core/Src/main.c **** hfdcan1.Init.NominalTimeSeg2 = 8; 368:Core/Src/main.c **** hfdcan1.Init.DataPrescaler = 1; 369:Core/Src/main.c **** hfdcan1.Init.DataSyncJumpWidth = 1; 370:Core/Src/main.c **** hfdcan1.Init.DataTimeSeg1 = 1; 371:Core/Src/main.c **** hfdcan1.Init.DataTimeSeg2 = 1; 372:Core/Src/main.c **** hfdcan1.Init.MessageRAMOffset = 0; 373:Core/Src/main.c **** hfdcan1.Init.StdFiltersNbr = 32; 374:Core/Src/main.c **** hfdcan1.Init.ExtFiltersNbr = 0; ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 8 375:Core/Src/main.c **** hfdcan1.Init.RxFifo0ElmtsNbr = 16; 376:Core/Src/main.c **** hfdcan1.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_8; 377:Core/Src/main.c **** hfdcan1.Init.RxFifo1ElmtsNbr = 0; 378:Core/Src/main.c **** hfdcan1.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_8; 379:Core/Src/main.c **** hfdcan1.Init.RxBuffersNbr = 0; 380:Core/Src/main.c **** hfdcan1.Init.RxBufferSize = FDCAN_DATA_BYTES_8; 381:Core/Src/main.c **** hfdcan1.Init.TxEventsNbr = 0; 382:Core/Src/main.c **** hfdcan1.Init.TxBuffersNbr = 0; 383:Core/Src/main.c **** hfdcan1.Init.TxFifoQueueElmtsNbr = 32; 384:Core/Src/main.c **** hfdcan1.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION; 385:Core/Src/main.c **** hfdcan1.Init.TxElmtSize = FDCAN_DATA_BYTES_8; 386:Core/Src/main.c **** if (HAL_FDCAN_Init(&hfdcan1) != HAL_OK) 387:Core/Src/main.c **** { 388:Core/Src/main.c **** Error_Handler(); 389:Core/Src/main.c **** } 390:Core/Src/main.c **** /* USER CODE BEGIN FDCAN1_Init 2 */ 391:Core/Src/main.c **** 392:Core/Src/main.c **** /* USER CODE END FDCAN1_Init 2 */ 393:Core/Src/main.c **** 394:Core/Src/main.c **** } 395:Core/Src/main.c **** 396:Core/Src/main.c **** /** 397:Core/Src/main.c **** * @brief SPI1 Initialization Function 398:Core/Src/main.c **** * @param None 399:Core/Src/main.c **** * @retval None 400:Core/Src/main.c **** */ 401:Core/Src/main.c **** static void MX_SPI1_Init(void) 402:Core/Src/main.c **** { 403:Core/Src/main.c **** 404:Core/Src/main.c **** /* USER CODE BEGIN SPI1_Init 0 */ 405:Core/Src/main.c **** 406:Core/Src/main.c **** /* USER CODE END SPI1_Init 0 */ 407:Core/Src/main.c **** 408:Core/Src/main.c **** /* USER CODE BEGIN SPI1_Init 1 */ 409:Core/Src/main.c **** 410:Core/Src/main.c **** /* USER CODE END SPI1_Init 1 */ 411:Core/Src/main.c **** /* SPI1 parameter configuration*/ 412:Core/Src/main.c **** hspi1.Instance = SPI1; 413:Core/Src/main.c **** hspi1.Init.Mode = SPI_MODE_MASTER; 414:Core/Src/main.c **** hspi1.Init.Direction = SPI_DIRECTION_2LINES; 415:Core/Src/main.c **** hspi1.Init.DataSize = SPI_DATASIZE_4BIT; 416:Core/Src/main.c **** hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; 417:Core/Src/main.c **** hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; 418:Core/Src/main.c **** hspi1.Init.NSS = SPI_NSS_HARD_OUTPUT; 419:Core/Src/main.c **** hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; 420:Core/Src/main.c **** hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; 421:Core/Src/main.c **** hspi1.Init.TIMode = SPI_TIMODE_DISABLE; 422:Core/Src/main.c **** hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 423:Core/Src/main.c **** hspi1.Init.CRCPolynomial = 0x0; 424:Core/Src/main.c **** hspi1.Init.NSSPMode = SPI_NSS_PULSE_ENABLE; 425:Core/Src/main.c **** hspi1.Init.NSSPolarity = SPI_NSS_POLARITY_LOW; 426:Core/Src/main.c **** hspi1.Init.FifoThreshold = SPI_FIFO_THRESHOLD_01DATA; 427:Core/Src/main.c **** hspi1.Init.TxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN; 428:Core/Src/main.c **** hspi1.Init.RxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN; 429:Core/Src/main.c **** hspi1.Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE; 430:Core/Src/main.c **** hspi1.Init.MasterInterDataIdleness = SPI_MASTER_INTERDATA_IDLENESS_00CYCLE; 431:Core/Src/main.c **** hspi1.Init.MasterReceiverAutoSusp = SPI_MASTER_RX_AUTOSUSP_DISABLE; ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 9 432:Core/Src/main.c **** hspi1.Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_DISABLE; 433:Core/Src/main.c **** hspi1.Init.IOSwap = SPI_IO_SWAP_DISABLE; 434:Core/Src/main.c **** if (HAL_SPI_Init(&hspi1) != HAL_OK) 435:Core/Src/main.c **** { 436:Core/Src/main.c **** Error_Handler(); 437:Core/Src/main.c **** } 438:Core/Src/main.c **** /* USER CODE BEGIN SPI1_Init 2 */ 439:Core/Src/main.c **** 440:Core/Src/main.c **** /* USER CODE END SPI1_Init 2 */ 441:Core/Src/main.c **** 442:Core/Src/main.c **** } 443:Core/Src/main.c **** 444:Core/Src/main.c **** /** 445:Core/Src/main.c **** * @brief SPI2 Initialization Function 446:Core/Src/main.c **** * @param None 447:Core/Src/main.c **** * @retval None 448:Core/Src/main.c **** */ 449:Core/Src/main.c **** static void MX_SPI2_Init(void) 450:Core/Src/main.c **** { 451:Core/Src/main.c **** 452:Core/Src/main.c **** /* USER CODE BEGIN SPI2_Init 0 */ 453:Core/Src/main.c **** 454:Core/Src/main.c **** /* USER CODE END SPI2_Init 0 */ 455:Core/Src/main.c **** 456:Core/Src/main.c **** /* USER CODE BEGIN SPI2_Init 1 */ 457:Core/Src/main.c **** 458:Core/Src/main.c **** /* USER CODE END SPI2_Init 1 */ 459:Core/Src/main.c **** /* SPI2 parameter configuration*/ 460:Core/Src/main.c **** hspi2.Instance = SPI2; 461:Core/Src/main.c **** hspi2.Init.Mode = SPI_MODE_MASTER; 462:Core/Src/main.c **** hspi2.Init.Direction = SPI_DIRECTION_2LINES; 463:Core/Src/main.c **** hspi2.Init.DataSize = SPI_DATASIZE_4BIT; 464:Core/Src/main.c **** hspi2.Init.CLKPolarity = SPI_POLARITY_LOW; 465:Core/Src/main.c **** hspi2.Init.CLKPhase = SPI_PHASE_1EDGE; 466:Core/Src/main.c **** hspi2.Init.NSS = SPI_NSS_HARD_INPUT; 467:Core/Src/main.c **** hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; 468:Core/Src/main.c **** hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB; 469:Core/Src/main.c **** hspi2.Init.TIMode = SPI_TIMODE_DISABLE; 470:Core/Src/main.c **** hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 471:Core/Src/main.c **** hspi2.Init.CRCPolynomial = 0x0; 472:Core/Src/main.c **** hspi2.Init.NSSPMode = SPI_NSS_PULSE_ENABLE; 473:Core/Src/main.c **** hspi2.Init.NSSPolarity = SPI_NSS_POLARITY_LOW; 474:Core/Src/main.c **** hspi2.Init.FifoThreshold = SPI_FIFO_THRESHOLD_01DATA; 475:Core/Src/main.c **** hspi2.Init.TxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN; 476:Core/Src/main.c **** hspi2.Init.RxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN; 477:Core/Src/main.c **** hspi2.Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE; 478:Core/Src/main.c **** hspi2.Init.MasterInterDataIdleness = SPI_MASTER_INTERDATA_IDLENESS_00CYCLE; 479:Core/Src/main.c **** hspi2.Init.MasterReceiverAutoSusp = SPI_MASTER_RX_AUTOSUSP_DISABLE; 480:Core/Src/main.c **** hspi2.Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_DISABLE; 481:Core/Src/main.c **** hspi2.Init.IOSwap = SPI_IO_SWAP_DISABLE; 482:Core/Src/main.c **** if (HAL_SPI_Init(&hspi2) != HAL_OK) 483:Core/Src/main.c **** { 484:Core/Src/main.c **** Error_Handler(); 485:Core/Src/main.c **** } 486:Core/Src/main.c **** /* USER CODE BEGIN SPI2_Init 2 */ 487:Core/Src/main.c **** 488:Core/Src/main.c **** /* USER CODE END SPI2_Init 2 */ ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 10 489:Core/Src/main.c **** 490:Core/Src/main.c **** } 491:Core/Src/main.c **** 492:Core/Src/main.c **** /** 493:Core/Src/main.c **** * @brief TIM15 Initialization Function 494:Core/Src/main.c **** * @param None 495:Core/Src/main.c **** * @retval None 496:Core/Src/main.c **** */ 497:Core/Src/main.c **** static void MX_TIM15_Init(void) 498:Core/Src/main.c **** { 499:Core/Src/main.c **** 500:Core/Src/main.c **** /* USER CODE BEGIN TIM15_Init 0 */ 501:Core/Src/main.c **** 502:Core/Src/main.c **** /* USER CODE END TIM15_Init 0 */ 503:Core/Src/main.c **** 504:Core/Src/main.c **** TIM_SlaveConfigTypeDef sSlaveConfig = {0}; 505:Core/Src/main.c **** TIM_IC_InitTypeDef sConfigIC = {0}; 506:Core/Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0}; 507:Core/Src/main.c **** 508:Core/Src/main.c **** /* USER CODE BEGIN TIM15_Init 1 */ 509:Core/Src/main.c **** 510:Core/Src/main.c **** /* USER CODE END TIM15_Init 1 */ 511:Core/Src/main.c **** htim15.Instance = TIM15; 512:Core/Src/main.c **** htim15.Init.Prescaler = 16000-1; 513:Core/Src/main.c **** htim15.Init.CounterMode = TIM_COUNTERMODE_UP; 514:Core/Src/main.c **** htim15.Init.Period = 65535; 515:Core/Src/main.c **** htim15.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 516:Core/Src/main.c **** htim15.Init.RepetitionCounter = 0; 517:Core/Src/main.c **** htim15.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 518:Core/Src/main.c **** if (HAL_TIM_IC_Init(&htim15) != HAL_OK) 519:Core/Src/main.c **** { 520:Core/Src/main.c **** Error_Handler(); 521:Core/Src/main.c **** } 522:Core/Src/main.c **** sSlaveConfig.SlaveMode = TIM_SLAVEMODE_RESET; 523:Core/Src/main.c **** sSlaveConfig.InputTrigger = TIM_TS_TI1FP1; 524:Core/Src/main.c **** sSlaveConfig.TriggerPolarity = TIM_INPUTCHANNELPOLARITY_RISING; 525:Core/Src/main.c **** sSlaveConfig.TriggerPrescaler = TIM_ICPSC_DIV1; 526:Core/Src/main.c **** sSlaveConfig.TriggerFilter = 0; 527:Core/Src/main.c **** if (HAL_TIM_SlaveConfigSynchro(&htim15, &sSlaveConfig) != HAL_OK) 528:Core/Src/main.c **** { 529:Core/Src/main.c **** Error_Handler(); 530:Core/Src/main.c **** } 531:Core/Src/main.c **** sConfigIC.ICPolarity = TIM_INPUTCHANNELPOLARITY_RISING; 532:Core/Src/main.c **** sConfigIC.ICSelection = TIM_ICSELECTION_DIRECTTI; 533:Core/Src/main.c **** sConfigIC.ICPrescaler = TIM_ICPSC_DIV1; 534:Core/Src/main.c **** sConfigIC.ICFilter = 0; 535:Core/Src/main.c **** if (HAL_TIM_IC_ConfigChannel(&htim15, &sConfigIC, TIM_CHANNEL_1) != HAL_OK) 536:Core/Src/main.c **** { 537:Core/Src/main.c **** Error_Handler(); 538:Core/Src/main.c **** } 539:Core/Src/main.c **** sConfigIC.ICPolarity = TIM_INPUTCHANNELPOLARITY_FALLING; 540:Core/Src/main.c **** sConfigIC.ICSelection = TIM_ICSELECTION_INDIRECTTI; 541:Core/Src/main.c **** if (HAL_TIM_IC_ConfigChannel(&htim15, &sConfigIC, TIM_CHANNEL_2) != HAL_OK) 542:Core/Src/main.c **** { 543:Core/Src/main.c **** Error_Handler(); 544:Core/Src/main.c **** } 545:Core/Src/main.c **** sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 11 546:Core/Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 547:Core/Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim15, &sMasterConfig) != HAL_OK) 548:Core/Src/main.c **** { 549:Core/Src/main.c **** Error_Handler(); 550:Core/Src/main.c **** } 551:Core/Src/main.c **** /* USER CODE BEGIN TIM15_Init 2 */ 552:Core/Src/main.c **** 553:Core/Src/main.c **** /* USER CODE END TIM15_Init 2 */ 554:Core/Src/main.c **** 555:Core/Src/main.c **** } 556:Core/Src/main.c **** 557:Core/Src/main.c **** /** 558:Core/Src/main.c **** * @brief GPIO Initialization Function 559:Core/Src/main.c **** * @param None 560:Core/Src/main.c **** * @retval None 561:Core/Src/main.c **** */ 562:Core/Src/main.c **** static void MX_GPIO_Init(void) 563:Core/Src/main.c **** { 27 .loc 1 563 1 view -0 28 .cfi_startproc 29 @ args = 0, pretend = 0, frame = 40 30 @ frame_needed = 0, uses_anonymous_args = 0 31 0000 2DE9F043 push {r4, r5, r6, r7, r8, r9, lr} 32 .cfi_def_cfa_offset 28 33 .cfi_offset 4, -28 34 .cfi_offset 5, -24 35 .cfi_offset 6, -20 36 .cfi_offset 7, -16 37 .cfi_offset 8, -12 38 .cfi_offset 9, -8 39 .cfi_offset 14, -4 40 0004 8BB0 sub sp, sp, #44 41 .cfi_def_cfa_offset 72 564:Core/Src/main.c **** GPIO_InitTypeDef GPIO_InitStruct = {0}; 42 .loc 1 564 3 view .LVU1 43 .loc 1 564 20 is_stmt 0 view .LVU2 44 0006 05AD add r5, sp, #20 45 0008 0024 movs r4, #0 46 000a 0594 str r4, [sp, #20] 47 000c 0694 str r4, [sp, #24] 48 000e 0794 str r4, [sp, #28] 49 0010 0894 str r4, [sp, #32] 50 0012 0994 str r4, [sp, #36] 565:Core/Src/main.c **** /* USER CODE BEGIN MX_GPIO_Init_1 */ 566:Core/Src/main.c **** /* USER CODE END MX_GPIO_Init_1 */ 567:Core/Src/main.c **** 568:Core/Src/main.c **** /* GPIO Ports Clock Enable */ 569:Core/Src/main.c **** __HAL_RCC_GPIOH_CLK_ENABLE(); 51 .loc 1 569 3 is_stmt 1 view .LVU3 52 .LBB4: 53 .loc 1 569 3 view .LVU4 54 .loc 1 569 3 view .LVU5 55 0014 414B ldr r3, .L3 56 0016 D3F84021 ldr r2, [r3, #320] 57 001a 42F08002 orr r2, r2, #128 58 001e C3F84021 str r2, [r3, #320] 59 .loc 1 569 3 view .LVU6 ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 12 60 0022 D3F84021 ldr r2, [r3, #320] 61 0026 02F08002 and r2, r2, #128 62 002a 0192 str r2, [sp, #4] 63 .loc 1 569 3 view .LVU7 64 002c 019A ldr r2, [sp, #4] 65 .LBE4: 66 .loc 1 569 3 view .LVU8 570:Core/Src/main.c **** __HAL_RCC_GPIOC_CLK_ENABLE(); 67 .loc 1 570 3 view .LVU9 68 .LBB5: 69 .loc 1 570 3 view .LVU10 70 .loc 1 570 3 view .LVU11 71 002e D3F84021 ldr r2, [r3, #320] 72 0032 42F00402 orr r2, r2, #4 73 0036 C3F84021 str r2, [r3, #320] 74 .loc 1 570 3 view .LVU12 75 003a D3F84021 ldr r2, [r3, #320] 76 003e 02F00402 and r2, r2, #4 77 0042 0292 str r2, [sp, #8] 78 .loc 1 570 3 view .LVU13 79 0044 029A ldr r2, [sp, #8] 80 .LBE5: 81 .loc 1 570 3 view .LVU14 571:Core/Src/main.c **** __HAL_RCC_GPIOA_CLK_ENABLE(); 82 .loc 1 571 3 view .LVU15 83 .LBB6: 84 .loc 1 571 3 view .LVU16 85 .loc 1 571 3 view .LVU17 86 0046 D3F84021 ldr r2, [r3, #320] 87 004a 42F00102 orr r2, r2, #1 88 004e C3F84021 str r2, [r3, #320] 89 .loc 1 571 3 view .LVU18 90 0052 D3F84021 ldr r2, [r3, #320] 91 0056 02F00102 and r2, r2, #1 92 005a 0392 str r2, [sp, #12] 93 .loc 1 571 3 view .LVU19 94 005c 039A ldr r2, [sp, #12] 95 .LBE6: 96 .loc 1 571 3 view .LVU20 572:Core/Src/main.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); 97 .loc 1 572 3 view .LVU21 98 .LBB7: 99 .loc 1 572 3 view .LVU22 100 .loc 1 572 3 view .LVU23 101 005e D3F84021 ldr r2, [r3, #320] 102 0062 42F00202 orr r2, r2, #2 103 0066 C3F84021 str r2, [r3, #320] 104 .loc 1 572 3 view .LVU24 105 006a D3F84031 ldr r3, [r3, #320] 106 006e 03F00203 and r3, r3, #2 107 0072 0493 str r3, [sp, #16] 108 .loc 1 572 3 view .LVU25 109 0074 049B ldr r3, [sp, #16] 110 .LBE7: 111 .loc 1 572 3 view .LVU26 573:Core/Src/main.c **** 574:Core/Src/main.c **** /*Configure GPIO pin Output Level */ ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 13 575:Core/Src/main.c **** HAL_GPIO_WritePin(GPIOC, STATUS_LED_B_Pin|MSTR1_Pin|MSTR2_Pin|POS_AIR_CTRL_Pin 112 .loc 1 575 3 view .LVU27 113 0076 DFF8AC80 ldr r8, .L3+8 114 007a 2246 mov r2, r4 115 007c F421 movs r1, #244 116 007e 4046 mov r0, r8 117 0080 FFF7FEFF bl HAL_GPIO_WritePin 118 .LVL0: 576:Core/Src/main.c **** |NEG_AIR_CTRL_Pin, GPIO_PIN_RESET); 577:Core/Src/main.c **** 578:Core/Src/main.c **** /*Configure GPIO pin Output Level */ 579:Core/Src/main.c **** HAL_GPIO_WritePin(GPIOB, IMD_POWER_Pin|STATUS_LED_R_Pin, GPIO_PIN_RESET); 119 .loc 1 579 3 view .LVU28 120 0084 DFF8A090 ldr r9, .L3+12 121 0088 2246 mov r2, r4 122 008a 48F20401 movw r1, #32772 123 008e 4846 mov r0, r9 124 0090 FFF7FEFF bl HAL_GPIO_WritePin 125 .LVL1: 580:Core/Src/main.c **** 581:Core/Src/main.c **** /*Configure GPIO pin Output Level */ 582:Core/Src/main.c **** HAL_GPIO_WritePin(GPIOA, PRECHARGE_CTRL_Pin|AMS_NERROR_Pin|STATUS_LED_G_Pin, GPIO_PIN_RESET); 126 .loc 1 582 3 view .LVU29 127 0094 224E ldr r6, .L3+4 128 0096 2246 mov r2, r4 129 0098 4FF40941 mov r1, #35072 130 009c 3046 mov r0, r6 131 009e FFF7FEFF bl HAL_GPIO_WritePin 132 .LVL2: 583:Core/Src/main.c **** 584:Core/Src/main.c **** /*Configure GPIO pins : STATUS_LED_B_Pin MSTR1_Pin MSTR2_Pin POS_AIR_CTRL_Pin 585:Core/Src/main.c **** NEG_AIR_CTRL_Pin */ 586:Core/Src/main.c **** GPIO_InitStruct.Pin = STATUS_LED_B_Pin|MSTR1_Pin|MSTR2_Pin|POS_AIR_CTRL_Pin 133 .loc 1 586 3 view .LVU30 134 .loc 1 586 23 is_stmt 0 view .LVU31 135 00a2 F423 movs r3, #244 136 00a4 0593 str r3, [sp, #20] 587:Core/Src/main.c **** |NEG_AIR_CTRL_Pin; 588:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 137 .loc 1 588 3 is_stmt 1 view .LVU32 138 .loc 1 588 24 is_stmt 0 view .LVU33 139 00a6 0127 movs r7, #1 140 00a8 0697 str r7, [sp, #24] 589:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 141 .loc 1 589 3 is_stmt 1 view .LVU34 142 .loc 1 589 24 is_stmt 0 view .LVU35 143 00aa 0794 str r4, [sp, #28] 590:Core/Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 144 .loc 1 590 3 is_stmt 1 view .LVU36 145 .loc 1 590 25 is_stmt 0 view .LVU37 146 00ac 0894 str r4, [sp, #32] 591:Core/Src/main.c **** HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 147 .loc 1 591 3 is_stmt 1 view .LVU38 148 00ae 2946 mov r1, r5 149 00b0 4046 mov r0, r8 150 00b2 FFF7FEFF bl HAL_GPIO_Init 151 .LVL3: ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 14 592:Core/Src/main.c **** 593:Core/Src/main.c **** /*Configure GPIO pins : TS_ERROR_Pin HV_ACTIVE_Pin IMD_OK_Pin NEG_AIR_CLOSED_Pin 594:Core/Src/main.c **** POS_AIR_CLOSED_Pin INTR1_Pin WAKE1_Pin */ 595:Core/Src/main.c **** GPIO_InitStruct.Pin = TS_ERROR_Pin|HV_ACTIVE_Pin|IMD_OK_Pin|NEG_AIR_CLOSED_Pin 152 .loc 1 595 3 view .LVU39 153 .loc 1 595 23 is_stmt 0 view .LVU40 154 00b6 40F2CB63 movw r3, #1739 155 00ba 0593 str r3, [sp, #20] 596:Core/Src/main.c **** |POS_AIR_CLOSED_Pin|INTR1_Pin|WAKE1_Pin; 597:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 156 .loc 1 597 3 is_stmt 1 view .LVU41 157 .loc 1 597 24 is_stmt 0 view .LVU42 158 00bc 0694 str r4, [sp, #24] 598:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 159 .loc 1 598 3 is_stmt 1 view .LVU43 160 .loc 1 598 24 is_stmt 0 view .LVU44 161 00be 0794 str r4, [sp, #28] 599:Core/Src/main.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 162 .loc 1 599 3 is_stmt 1 view .LVU45 163 00c0 2946 mov r1, r5 164 00c2 3046 mov r0, r6 165 00c4 FFF7FEFF bl HAL_GPIO_Init 166 .LVL4: 600:Core/Src/main.c **** 601:Core/Src/main.c **** /*Configure GPIO pins : PRE_and_AIR__open_Pin SDC_VOLTAGE_Pin IMD_ERROR_LED_Pin AMS_ERROR_LED_Pin 602:Core/Src/main.c **** INTR2_Pin WAKE2_Pin */ 603:Core/Src/main.c **** GPIO_InitStruct.Pin = PRE_and_AIR__open_Pin|SDC_VOLTAGE_Pin|IMD_ERROR_LED_Pin|AMS_ERROR_LED_Pin 167 .loc 1 603 3 view .LVU46 168 .loc 1 603 23 is_stmt 0 view .LVU47 169 00c8 42F2C343 movw r3, #9411 170 00cc 0593 str r3, [sp, #20] 604:Core/Src/main.c **** |INTR2_Pin|WAKE2_Pin; 605:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 171 .loc 1 605 3 is_stmt 1 view .LVU48 172 .loc 1 605 24 is_stmt 0 view .LVU49 173 00ce 0694 str r4, [sp, #24] 606:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 174 .loc 1 606 3 is_stmt 1 view .LVU50 175 .loc 1 606 24 is_stmt 0 view .LVU51 176 00d0 0794 str r4, [sp, #28] 607:Core/Src/main.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 177 .loc 1 607 3 is_stmt 1 view .LVU52 178 00d2 2946 mov r1, r5 179 00d4 4846 mov r0, r9 180 00d6 FFF7FEFF bl HAL_GPIO_Init 181 .LVL5: 608:Core/Src/main.c **** 609:Core/Src/main.c **** /*Configure GPIO pins : IMD_POWER_Pin STATUS_LED_R_Pin */ 610:Core/Src/main.c **** GPIO_InitStruct.Pin = IMD_POWER_Pin|STATUS_LED_R_Pin; 182 .loc 1 610 3 view .LVU53 183 .loc 1 610 23 is_stmt 0 view .LVU54 184 00da 48F20403 movw r3, #32772 185 00de 0593 str r3, [sp, #20] 611:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 186 .loc 1 611 3 is_stmt 1 view .LVU55 187 .loc 1 611 24 is_stmt 0 view .LVU56 188 00e0 0697 str r7, [sp, #24] ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 15 612:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 189 .loc 1 612 3 is_stmt 1 view .LVU57 190 .loc 1 612 24 is_stmt 0 view .LVU58 191 00e2 0794 str r4, [sp, #28] 613:Core/Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 192 .loc 1 613 3 is_stmt 1 view .LVU59 193 .loc 1 613 25 is_stmt 0 view .LVU60 194 00e4 0894 str r4, [sp, #32] 614:Core/Src/main.c **** HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 195 .loc 1 614 3 is_stmt 1 view .LVU61 196 00e6 2946 mov r1, r5 197 00e8 4846 mov r0, r9 198 00ea FFF7FEFF bl HAL_GPIO_Init 199 .LVL6: 615:Core/Src/main.c **** 616:Core/Src/main.c **** /*Configure GPIO pin : TSAL_GREEN_Pin */ 617:Core/Src/main.c **** GPIO_InitStruct.Pin = TSAL_GREEN_Pin; 200 .loc 1 617 3 view .LVU62 201 .loc 1 617 23 is_stmt 0 view .LVU63 202 00ee 4FF40073 mov r3, #512 203 00f2 0593 str r3, [sp, #20] 618:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 204 .loc 1 618 3 is_stmt 1 view .LVU64 205 .loc 1 618 24 is_stmt 0 view .LVU65 206 00f4 0694 str r4, [sp, #24] 619:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 207 .loc 1 619 3 is_stmt 1 view .LVU66 208 .loc 1 619 24 is_stmt 0 view .LVU67 209 00f6 0794 str r4, [sp, #28] 620:Core/Src/main.c **** HAL_GPIO_Init(TSAL_GREEN_GPIO_Port, &GPIO_InitStruct); 210 .loc 1 620 3 is_stmt 1 view .LVU68 211 00f8 2946 mov r1, r5 212 00fa 4046 mov r0, r8 213 00fc FFF7FEFF bl HAL_GPIO_Init 214 .LVL7: 621:Core/Src/main.c **** 622:Core/Src/main.c **** /*Configure GPIO pins : PRECHARGE_CTRL_Pin AMS_NERROR_Pin STATUS_LED_G_Pin */ 623:Core/Src/main.c **** GPIO_InitStruct.Pin = PRECHARGE_CTRL_Pin|AMS_NERROR_Pin|STATUS_LED_G_Pin; 215 .loc 1 623 3 view .LVU69 216 .loc 1 623 23 is_stmt 0 view .LVU70 217 0100 4FF40943 mov r3, #35072 218 0104 0593 str r3, [sp, #20] 624:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 219 .loc 1 624 3 is_stmt 1 view .LVU71 220 .loc 1 624 24 is_stmt 0 view .LVU72 221 0106 0697 str r7, [sp, #24] 625:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; 222 .loc 1 625 3 is_stmt 1 view .LVU73 223 .loc 1 625 24 is_stmt 0 view .LVU74 224 0108 0794 str r4, [sp, #28] 626:Core/Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 225 .loc 1 626 3 is_stmt 1 view .LVU75 226 .loc 1 626 25 is_stmt 0 view .LVU76 227 010a 0894 str r4, [sp, #32] 627:Core/Src/main.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 228 .loc 1 627 3 is_stmt 1 view .LVU77 229 010c 2946 mov r1, r5 ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 16 230 010e 3046 mov r0, r6 231 0110 FFF7FEFF bl HAL_GPIO_Init 232 .LVL8: 628:Core/Src/main.c **** 629:Core/Src/main.c **** /* USER CODE BEGIN MX_GPIO_Init_2 */ 630:Core/Src/main.c **** /* USER CODE END MX_GPIO_Init_2 */ 631:Core/Src/main.c **** } 233 .loc 1 631 1 is_stmt 0 view .LVU78 234 0114 0BB0 add sp, sp, #44 235 .cfi_def_cfa_offset 28 236 @ sp needed 237 0116 BDE8F083 pop {r4, r5, r6, r7, r8, r9, pc} 238 .L4: 239 011a 00BF .align 2 240 .L3: 241 011c 00440258 .word 1476543488 242 0120 00000258 .word 1476526080 243 0124 00080258 .word 1476528128 244 0128 00040258 .word 1476527104 245 .cfi_endproc 246 .LFE344: 248 .section .text.Error_Handler,"ax",%progbits 249 .align 1 250 .global Error_Handler 251 .syntax unified 252 .thumb 253 .thumb_func 255 Error_Handler: 256 .LFB345: 632:Core/Src/main.c **** 633:Core/Src/main.c **** /* USER CODE BEGIN 4 */ 634:Core/Src/main.c **** 635:Core/Src/main.c **** /* USER CODE END 4 */ 636:Core/Src/main.c **** 637:Core/Src/main.c **** /** 638:Core/Src/main.c **** * @brief This function is executed in case of error occurrence. 639:Core/Src/main.c **** * @retval None 640:Core/Src/main.c **** */ 641:Core/Src/main.c **** void Error_Handler(void) 642:Core/Src/main.c **** { 257 .loc 1 642 1 is_stmt 1 view -0 258 .cfi_startproc 259 @ Volatile: function does not return. 260 @ args = 0, pretend = 0, frame = 0 261 @ frame_needed = 0, uses_anonymous_args = 0 262 @ link register save eliminated. 643:Core/Src/main.c **** /* USER CODE BEGIN Error_Handler_Debug */ 644:Core/Src/main.c **** /* User can add his own implementation to report the HAL error return state */ 645:Core/Src/main.c **** __disable_irq(); 263 .loc 1 645 3 view .LVU80 264 .LBB8: 265 .LBI8: 266 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h" 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.2.0 ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 17 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 08. May 2019 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2019 Arm Limited. All rights reserved. 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 24:Drivers/CMSIS/Include/cmsis_gcc.h **** 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H 27:Drivers/CMSIS/Include/cmsis_gcc.h **** 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" 33:Drivers/CMSIS/Include/cmsis_gcc.h **** 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 38:Drivers/CMSIS/Include/cmsis_gcc.h **** 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 18 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 116:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __COMPILER_BARRIER 117:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __COMPILER_BARRIER() __ASM volatile("":::"memory") 118:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 19 119:Drivers/CMSIS/Include/cmsis_gcc.h **** 120:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ######################### Startup and Lowlevel Init ######################## */ 121:Drivers/CMSIS/Include/cmsis_gcc.h **** 122:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PROGRAM_START 123:Drivers/CMSIS/Include/cmsis_gcc.h **** 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Initializes data and bss sections 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details This default implementations initialized all data and additional bss 127:Drivers/CMSIS/Include/cmsis_gcc.h **** sections relying on .copy.table and .zero.table specified properly 128:Drivers/CMSIS/Include/cmsis_gcc.h **** in the used linker script. 129:Drivers/CMSIS/Include/cmsis_gcc.h **** 130:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) 132:Drivers/CMSIS/Include/cmsis_gcc.h **** { 133:Drivers/CMSIS/Include/cmsis_gcc.h **** extern void _start(void) __NO_RETURN; 134:Drivers/CMSIS/Include/cmsis_gcc.h **** 135:Drivers/CMSIS/Include/cmsis_gcc.h **** typedef struct { 136:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t const* src; 137:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t* dest; 138:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t wlen; 139:Drivers/CMSIS/Include/cmsis_gcc.h **** } __copy_table_t; 140:Drivers/CMSIS/Include/cmsis_gcc.h **** 141:Drivers/CMSIS/Include/cmsis_gcc.h **** typedef struct { 142:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t* dest; 143:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t wlen; 144:Drivers/CMSIS/Include/cmsis_gcc.h **** } __zero_table_t; 145:Drivers/CMSIS/Include/cmsis_gcc.h **** 146:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __copy_table_t __copy_table_start__; 147:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __copy_table_t __copy_table_end__; 148:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __zero_table_t __zero_table_start__; 149:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __zero_table_t __zero_table_end__; 150:Drivers/CMSIS/Include/cmsis_gcc.h **** 151:Drivers/CMSIS/Include/cmsis_gcc.h **** for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable 152:Drivers/CMSIS/Include/cmsis_gcc.h **** for(uint32_t i=0u; iwlen; ++i) { 153:Drivers/CMSIS/Include/cmsis_gcc.h **** pTable->dest[i] = pTable->src[i]; 154:Drivers/CMSIS/Include/cmsis_gcc.h **** } 155:Drivers/CMSIS/Include/cmsis_gcc.h **** } 156:Drivers/CMSIS/Include/cmsis_gcc.h **** 157:Drivers/CMSIS/Include/cmsis_gcc.h **** for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable 158:Drivers/CMSIS/Include/cmsis_gcc.h **** for(uint32_t i=0u; iwlen; ++i) { 159:Drivers/CMSIS/Include/cmsis_gcc.h **** pTable->dest[i] = 0u; 160:Drivers/CMSIS/Include/cmsis_gcc.h **** } 161:Drivers/CMSIS/Include/cmsis_gcc.h **** } 162:Drivers/CMSIS/Include/cmsis_gcc.h **** 163:Drivers/CMSIS/Include/cmsis_gcc.h **** _start(); 164:Drivers/CMSIS/Include/cmsis_gcc.h **** } 165:Drivers/CMSIS/Include/cmsis_gcc.h **** 166:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PROGRAM_START __cmsis_start 167:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 168:Drivers/CMSIS/Include/cmsis_gcc.h **** 169:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INITIAL_SP 170:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INITIAL_SP __StackTop 171:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 172:Drivers/CMSIS/Include/cmsis_gcc.h **** 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STACK_LIMIT 174:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STACK_LIMIT __StackLimit 175:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 20 176:Drivers/CMSIS/Include/cmsis_gcc.h **** 177:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE 178:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE __Vectors 179:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 180:Drivers/CMSIS/Include/cmsis_gcc.h **** 181:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE_ATTRIBUTE 182:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section(".vectors"))) 183:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 184:Drivers/CMSIS/Include/cmsis_gcc.h **** 185:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ 186:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface 187:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions 188:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ 189:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 190:Drivers/CMSIS/Include/cmsis_gcc.h **** 191:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 192:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts 193:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR. 194:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 195:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 196:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) 197:Drivers/CMSIS/Include/cmsis_gcc.h **** { 198:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); 199:Drivers/CMSIS/Include/cmsis_gcc.h **** } 200:Drivers/CMSIS/Include/cmsis_gcc.h **** 201:Drivers/CMSIS/Include/cmsis_gcc.h **** 202:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 203:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts 204:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR. 205:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 206:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 207:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) 267 .loc 2 207 27 view .LVU81 268 .LBB9: 208:Drivers/CMSIS/Include/cmsis_gcc.h **** { 209:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); 269 .loc 2 209 3 view .LVU82 270 .syntax unified 271 @ 209 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 272 0000 72B6 cpsid i 273 @ 0 "" 2 274 .thumb 275 .syntax unified 276 .L6: 277 .LBE9: 278 .LBE8: 646:Core/Src/main.c **** while (1) 279 .loc 1 646 3 view .LVU83 647:Core/Src/main.c **** { 648:Core/Src/main.c **** } 280 .loc 1 648 3 view .LVU84 646:Core/Src/main.c **** while (1) 281 .loc 1 646 9 view .LVU85 282 0002 FEE7 b .L6 283 .cfi_endproc 284 .LFE345: 286 .section .text.MX_FDCAN1_Init,"ax",%progbits ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 21 287 .align 1 288 .syntax unified 289 .thumb 290 .thumb_func 292 MX_FDCAN1_Init: 293 .LFB340: 349:Core/Src/main.c **** 294 .loc 1 349 1 view -0 295 .cfi_startproc 296 @ args = 0, pretend = 0, frame = 0 297 @ frame_needed = 0, uses_anonymous_args = 0 298 0000 08B5 push {r3, lr} 299 .cfi_def_cfa_offset 8 300 .cfi_offset 3, -8 301 .cfi_offset 14, -4 358:Core/Src/main.c **** hfdcan1.Init.FrameFormat = FDCAN_FRAME_CLASSIC; 302 .loc 1 358 3 view .LVU87 358:Core/Src/main.c **** hfdcan1.Init.FrameFormat = FDCAN_FRAME_CLASSIC; 303 .loc 1 358 20 is_stmt 0 view .LVU88 304 0002 1648 ldr r0, .L11 305 0004 164B ldr r3, .L11+4 306 0006 0360 str r3, [r0] 359:Core/Src/main.c **** hfdcan1.Init.Mode = FDCAN_MODE_NORMAL; 307 .loc 1 359 3 is_stmt 1 view .LVU89 359:Core/Src/main.c **** hfdcan1.Init.Mode = FDCAN_MODE_NORMAL; 308 .loc 1 359 28 is_stmt 0 view .LVU90 309 0008 0023 movs r3, #0 310 000a 8360 str r3, [r0, #8] 360:Core/Src/main.c **** hfdcan1.Init.AutoRetransmission = DISABLE; 311 .loc 1 360 3 is_stmt 1 view .LVU91 360:Core/Src/main.c **** hfdcan1.Init.AutoRetransmission = DISABLE; 312 .loc 1 360 21 is_stmt 0 view .LVU92 313 000c C360 str r3, [r0, #12] 361:Core/Src/main.c **** hfdcan1.Init.TransmitPause = DISABLE; 314 .loc 1 361 3 is_stmt 1 view .LVU93 361:Core/Src/main.c **** hfdcan1.Init.TransmitPause = DISABLE; 315 .loc 1 361 35 is_stmt 0 view .LVU94 316 000e 0374 strb r3, [r0, #16] 362:Core/Src/main.c **** hfdcan1.Init.ProtocolException = DISABLE; 317 .loc 1 362 3 is_stmt 1 view .LVU95 362:Core/Src/main.c **** hfdcan1.Init.ProtocolException = DISABLE; 318 .loc 1 362 30 is_stmt 0 view .LVU96 319 0010 4374 strb r3, [r0, #17] 363:Core/Src/main.c **** hfdcan1.Init.NominalPrescaler = 2; 320 .loc 1 363 3 is_stmt 1 view .LVU97 363:Core/Src/main.c **** hfdcan1.Init.NominalPrescaler = 2; 321 .loc 1 363 34 is_stmt 0 view .LVU98 322 0012 8374 strb r3, [r0, #18] 364:Core/Src/main.c **** hfdcan1.Init.NominalSyncJumpWidth = 1; 323 .loc 1 364 3 is_stmt 1 view .LVU99 364:Core/Src/main.c **** hfdcan1.Init.NominalSyncJumpWidth = 1; 324 .loc 1 364 33 is_stmt 0 view .LVU100 325 0014 0222 movs r2, #2 326 0016 4261 str r2, [r0, #20] 365:Core/Src/main.c **** hfdcan1.Init.NominalTimeSeg1 = 31; 327 .loc 1 365 3 is_stmt 1 view .LVU101 365:Core/Src/main.c **** hfdcan1.Init.NominalTimeSeg1 = 31; ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 22 328 .loc 1 365 37 is_stmt 0 view .LVU102 329 0018 0122 movs r2, #1 330 001a 8261 str r2, [r0, #24] 366:Core/Src/main.c **** hfdcan1.Init.NominalTimeSeg2 = 8; 331 .loc 1 366 3 is_stmt 1 view .LVU103 366:Core/Src/main.c **** hfdcan1.Init.NominalTimeSeg2 = 8; 332 .loc 1 366 32 is_stmt 0 view .LVU104 333 001c 1F21 movs r1, #31 334 001e C161 str r1, [r0, #28] 367:Core/Src/main.c **** hfdcan1.Init.DataPrescaler = 1; 335 .loc 1 367 3 is_stmt 1 view .LVU105 367:Core/Src/main.c **** hfdcan1.Init.DataPrescaler = 1; 336 .loc 1 367 32 is_stmt 0 view .LVU106 337 0020 0821 movs r1, #8 338 0022 0162 str r1, [r0, #32] 368:Core/Src/main.c **** hfdcan1.Init.DataSyncJumpWidth = 1; 339 .loc 1 368 3 is_stmt 1 view .LVU107 368:Core/Src/main.c **** hfdcan1.Init.DataSyncJumpWidth = 1; 340 .loc 1 368 30 is_stmt 0 view .LVU108 341 0024 4262 str r2, [r0, #36] 369:Core/Src/main.c **** hfdcan1.Init.DataTimeSeg1 = 1; 342 .loc 1 369 3 is_stmt 1 view .LVU109 369:Core/Src/main.c **** hfdcan1.Init.DataTimeSeg1 = 1; 343 .loc 1 369 34 is_stmt 0 view .LVU110 344 0026 8262 str r2, [r0, #40] 370:Core/Src/main.c **** hfdcan1.Init.DataTimeSeg2 = 1; 345 .loc 1 370 3 is_stmt 1 view .LVU111 370:Core/Src/main.c **** hfdcan1.Init.DataTimeSeg2 = 1; 346 .loc 1 370 29 is_stmt 0 view .LVU112 347 0028 C262 str r2, [r0, #44] 371:Core/Src/main.c **** hfdcan1.Init.MessageRAMOffset = 0; 348 .loc 1 371 3 is_stmt 1 view .LVU113 371:Core/Src/main.c **** hfdcan1.Init.MessageRAMOffset = 0; 349 .loc 1 371 29 is_stmt 0 view .LVU114 350 002a 0263 str r2, [r0, #48] 372:Core/Src/main.c **** hfdcan1.Init.StdFiltersNbr = 32; 351 .loc 1 372 3 is_stmt 1 view .LVU115 372:Core/Src/main.c **** hfdcan1.Init.StdFiltersNbr = 32; 352 .loc 1 372 33 is_stmt 0 view .LVU116 353 002c 4363 str r3, [r0, #52] 373:Core/Src/main.c **** hfdcan1.Init.ExtFiltersNbr = 0; 354 .loc 1 373 3 is_stmt 1 view .LVU117 373:Core/Src/main.c **** hfdcan1.Init.ExtFiltersNbr = 0; 355 .loc 1 373 30 is_stmt 0 view .LVU118 356 002e 2021 movs r1, #32 357 0030 8163 str r1, [r0, #56] 374:Core/Src/main.c **** hfdcan1.Init.RxFifo0ElmtsNbr = 16; 358 .loc 1 374 3 is_stmt 1 view .LVU119 374:Core/Src/main.c **** hfdcan1.Init.RxFifo0ElmtsNbr = 16; 359 .loc 1 374 30 is_stmt 0 view .LVU120 360 0032 C363 str r3, [r0, #60] 375:Core/Src/main.c **** hfdcan1.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_8; 361 .loc 1 375 3 is_stmt 1 view .LVU121 375:Core/Src/main.c **** hfdcan1.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_8; 362 .loc 1 375 32 is_stmt 0 view .LVU122 363 0034 1022 movs r2, #16 364 0036 0264 str r2, [r0, #64] ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 23 376:Core/Src/main.c **** hfdcan1.Init.RxFifo1ElmtsNbr = 0; 365 .loc 1 376 3 is_stmt 1 view .LVU123 376:Core/Src/main.c **** hfdcan1.Init.RxFifo1ElmtsNbr = 0; 366 .loc 1 376 32 is_stmt 0 view .LVU124 367 0038 0422 movs r2, #4 368 003a 4264 str r2, [r0, #68] 377:Core/Src/main.c **** hfdcan1.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_8; 369 .loc 1 377 3 is_stmt 1 view .LVU125 377:Core/Src/main.c **** hfdcan1.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_8; 370 .loc 1 377 32 is_stmt 0 view .LVU126 371 003c 8364 str r3, [r0, #72] 378:Core/Src/main.c **** hfdcan1.Init.RxBuffersNbr = 0; 372 .loc 1 378 3 is_stmt 1 view .LVU127 378:Core/Src/main.c **** hfdcan1.Init.RxBuffersNbr = 0; 373 .loc 1 378 32 is_stmt 0 view .LVU128 374 003e C264 str r2, [r0, #76] 379:Core/Src/main.c **** hfdcan1.Init.RxBufferSize = FDCAN_DATA_BYTES_8; 375 .loc 1 379 3 is_stmt 1 view .LVU129 379:Core/Src/main.c **** hfdcan1.Init.RxBufferSize = FDCAN_DATA_BYTES_8; 376 .loc 1 379 29 is_stmt 0 view .LVU130 377 0040 0365 str r3, [r0, #80] 380:Core/Src/main.c **** hfdcan1.Init.TxEventsNbr = 0; 378 .loc 1 380 3 is_stmt 1 view .LVU131 380:Core/Src/main.c **** hfdcan1.Init.TxEventsNbr = 0; 379 .loc 1 380 29 is_stmt 0 view .LVU132 380 0042 4265 str r2, [r0, #84] 381:Core/Src/main.c **** hfdcan1.Init.TxBuffersNbr = 0; 381 .loc 1 381 3 is_stmt 1 view .LVU133 381:Core/Src/main.c **** hfdcan1.Init.TxBuffersNbr = 0; 382 .loc 1 381 28 is_stmt 0 view .LVU134 383 0044 8365 str r3, [r0, #88] 382:Core/Src/main.c **** hfdcan1.Init.TxFifoQueueElmtsNbr = 32; 384 .loc 1 382 3 is_stmt 1 view .LVU135 382:Core/Src/main.c **** hfdcan1.Init.TxFifoQueueElmtsNbr = 32; 385 .loc 1 382 29 is_stmt 0 view .LVU136 386 0046 C365 str r3, [r0, #92] 383:Core/Src/main.c **** hfdcan1.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION; 387 .loc 1 383 3 is_stmt 1 view .LVU137 383:Core/Src/main.c **** hfdcan1.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION; 388 .loc 1 383 36 is_stmt 0 view .LVU138 389 0048 0166 str r1, [r0, #96] 384:Core/Src/main.c **** hfdcan1.Init.TxElmtSize = FDCAN_DATA_BYTES_8; 390 .loc 1 384 3 is_stmt 1 view .LVU139 384:Core/Src/main.c **** hfdcan1.Init.TxElmtSize = FDCAN_DATA_BYTES_8; 391 .loc 1 384 32 is_stmt 0 view .LVU140 392 004a 4366 str r3, [r0, #100] 385:Core/Src/main.c **** if (HAL_FDCAN_Init(&hfdcan1) != HAL_OK) 393 .loc 1 385 3 is_stmt 1 view .LVU141 385:Core/Src/main.c **** if (HAL_FDCAN_Init(&hfdcan1) != HAL_OK) 394 .loc 1 385 27 is_stmt 0 view .LVU142 395 004c 8266 str r2, [r0, #104] 386:Core/Src/main.c **** { 396 .loc 1 386 3 is_stmt 1 view .LVU143 386:Core/Src/main.c **** { 397 .loc 1 386 7 is_stmt 0 view .LVU144 398 004e FFF7FEFF bl HAL_FDCAN_Init 399 .LVL9: ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 24 386:Core/Src/main.c **** { 400 .loc 1 386 6 discriminator 1 view .LVU145 401 0052 00B9 cbnz r0, .L10 394:Core/Src/main.c **** 402 .loc 1 394 1 view .LVU146 403 0054 08BD pop {r3, pc} 404 .L10: 388:Core/Src/main.c **** } 405 .loc 1 388 5 is_stmt 1 view .LVU147 406 0056 FFF7FEFF bl Error_Handler 407 .LVL10: 408 .L12: 409 005a 00BF .align 2 410 .L11: 411 005c 00000000 .word hfdcan1 412 0060 00A00040 .word 1073782784 413 .cfi_endproc 414 .LFE340: 416 .section .text.MX_TIM15_Init,"ax",%progbits 417 .align 1 418 .syntax unified 419 .thumb 420 .thumb_func 422 MX_TIM15_Init: 423 .LFB343: 498:Core/Src/main.c **** 424 .loc 1 498 1 view -0 425 .cfi_startproc 426 @ args = 0, pretend = 0, frame = 48 427 @ frame_needed = 0, uses_anonymous_args = 0 428 0000 00B5 push {lr} 429 .cfi_def_cfa_offset 4 430 .cfi_offset 14, -4 431 0002 8DB0 sub sp, sp, #52 432 .cfi_def_cfa_offset 56 504:Core/Src/main.c **** TIM_IC_InitTypeDef sConfigIC = {0}; 433 .loc 1 504 3 view .LVU149 504:Core/Src/main.c **** TIM_IC_InitTypeDef sConfigIC = {0}; 434 .loc 1 504 26 is_stmt 0 view .LVU150 435 0004 0023 movs r3, #0 436 0006 0793 str r3, [sp, #28] 437 0008 0893 str r3, [sp, #32] 438 000a 0993 str r3, [sp, #36] 439 000c 0A93 str r3, [sp, #40] 440 000e 0B93 str r3, [sp, #44] 505:Core/Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0}; 441 .loc 1 505 3 is_stmt 1 view .LVU151 505:Core/Src/main.c **** TIM_MasterConfigTypeDef sMasterConfig = {0}; 442 .loc 1 505 22 is_stmt 0 view .LVU152 443 0010 0393 str r3, [sp, #12] 444 0012 0493 str r3, [sp, #16] 445 0014 0593 str r3, [sp, #20] 446 0016 0693 str r3, [sp, #24] 506:Core/Src/main.c **** 447 .loc 1 506 3 is_stmt 1 view .LVU153 506:Core/Src/main.c **** 448 .loc 1 506 27 is_stmt 0 view .LVU154 ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 25 449 0018 0093 str r3, [sp] 450 001a 0193 str r3, [sp, #4] 451 001c 0293 str r3, [sp, #8] 511:Core/Src/main.c **** htim15.Init.Prescaler = 16000-1; 452 .loc 1 511 3 is_stmt 1 view .LVU155 511:Core/Src/main.c **** htim15.Init.Prescaler = 16000-1; 453 .loc 1 511 19 is_stmt 0 view .LVU156 454 001e 2348 ldr r0, .L25 455 0020 234A ldr r2, .L25+4 456 0022 0260 str r2, [r0] 512:Core/Src/main.c **** htim15.Init.CounterMode = TIM_COUNTERMODE_UP; 457 .loc 1 512 3 is_stmt 1 view .LVU157 512:Core/Src/main.c **** htim15.Init.CounterMode = TIM_COUNTERMODE_UP; 458 .loc 1 512 25 is_stmt 0 view .LVU158 459 0024 43F67F62 movw r2, #15999 460 0028 4260 str r2, [r0, #4] 513:Core/Src/main.c **** htim15.Init.Period = 65535; 461 .loc 1 513 3 is_stmt 1 view .LVU159 513:Core/Src/main.c **** htim15.Init.Period = 65535; 462 .loc 1 513 27 is_stmt 0 view .LVU160 463 002a 8360 str r3, [r0, #8] 514:Core/Src/main.c **** htim15.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 464 .loc 1 514 3 is_stmt 1 view .LVU161 514:Core/Src/main.c **** htim15.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 465 .loc 1 514 22 is_stmt 0 view .LVU162 466 002c 4FF6FF72 movw r2, #65535 467 0030 C260 str r2, [r0, #12] 515:Core/Src/main.c **** htim15.Init.RepetitionCounter = 0; 468 .loc 1 515 3 is_stmt 1 view .LVU163 515:Core/Src/main.c **** htim15.Init.RepetitionCounter = 0; 469 .loc 1 515 29 is_stmt 0 view .LVU164 470 0032 0361 str r3, [r0, #16] 516:Core/Src/main.c **** htim15.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 471 .loc 1 516 3 is_stmt 1 view .LVU165 516:Core/Src/main.c **** htim15.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 472 .loc 1 516 33 is_stmt 0 view .LVU166 473 0034 4361 str r3, [r0, #20] 517:Core/Src/main.c **** if (HAL_TIM_IC_Init(&htim15) != HAL_OK) 474 .loc 1 517 3 is_stmt 1 view .LVU167 517:Core/Src/main.c **** if (HAL_TIM_IC_Init(&htim15) != HAL_OK) 475 .loc 1 517 33 is_stmt 0 view .LVU168 476 0036 8361 str r3, [r0, #24] 518:Core/Src/main.c **** { 477 .loc 1 518 3 is_stmt 1 view .LVU169 518:Core/Src/main.c **** { 478 .loc 1 518 7 is_stmt 0 view .LVU170 479 0038 FFF7FEFF bl HAL_TIM_IC_Init 480 .LVL11: 518:Core/Src/main.c **** { 481 .loc 1 518 6 discriminator 1 view .LVU171 482 003c 0028 cmp r0, #0 483 003e 2BD1 bne .L20 522:Core/Src/main.c **** sSlaveConfig.InputTrigger = TIM_TS_TI1FP1; 484 .loc 1 522 3 is_stmt 1 view .LVU172 522:Core/Src/main.c **** sSlaveConfig.InputTrigger = TIM_TS_TI1FP1; 485 .loc 1 522 26 is_stmt 0 view .LVU173 486 0040 0423 movs r3, #4 ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 26 487 0042 0793 str r3, [sp, #28] 523:Core/Src/main.c **** sSlaveConfig.TriggerPolarity = TIM_INPUTCHANNELPOLARITY_RISING; 488 .loc 1 523 3 is_stmt 1 view .LVU174 523:Core/Src/main.c **** sSlaveConfig.TriggerPolarity = TIM_INPUTCHANNELPOLARITY_RISING; 489 .loc 1 523 29 is_stmt 0 view .LVU175 490 0044 5023 movs r3, #80 491 0046 0893 str r3, [sp, #32] 524:Core/Src/main.c **** sSlaveConfig.TriggerPrescaler = TIM_ICPSC_DIV1; 492 .loc 1 524 3 is_stmt 1 view .LVU176 524:Core/Src/main.c **** sSlaveConfig.TriggerPrescaler = TIM_ICPSC_DIV1; 493 .loc 1 524 32 is_stmt 0 view .LVU177 494 0048 0023 movs r3, #0 495 004a 0993 str r3, [sp, #36] 525:Core/Src/main.c **** sSlaveConfig.TriggerFilter = 0; 496 .loc 1 525 3 is_stmt 1 view .LVU178 525:Core/Src/main.c **** sSlaveConfig.TriggerFilter = 0; 497 .loc 1 525 33 is_stmt 0 view .LVU179 498 004c 0A93 str r3, [sp, #40] 526:Core/Src/main.c **** if (HAL_TIM_SlaveConfigSynchro(&htim15, &sSlaveConfig) != HAL_OK) 499 .loc 1 526 3 is_stmt 1 view .LVU180 526:Core/Src/main.c **** if (HAL_TIM_SlaveConfigSynchro(&htim15, &sSlaveConfig) != HAL_OK) 500 .loc 1 526 30 is_stmt 0 view .LVU181 501 004e 0B93 str r3, [sp, #44] 527:Core/Src/main.c **** { 502 .loc 1 527 3 is_stmt 1 view .LVU182 527:Core/Src/main.c **** { 503 .loc 1 527 7 is_stmt 0 view .LVU183 504 0050 07A9 add r1, sp, #28 505 0052 1648 ldr r0, .L25 506 0054 FFF7FEFF bl HAL_TIM_SlaveConfigSynchro 507 .LVL12: 527:Core/Src/main.c **** { 508 .loc 1 527 6 discriminator 1 view .LVU184 509 0058 00BB cbnz r0, .L21 531:Core/Src/main.c **** sConfigIC.ICSelection = TIM_ICSELECTION_DIRECTTI; 510 .loc 1 531 3 is_stmt 1 view .LVU185 531:Core/Src/main.c **** sConfigIC.ICSelection = TIM_ICSELECTION_DIRECTTI; 511 .loc 1 531 24 is_stmt 0 view .LVU186 512 005a 0022 movs r2, #0 513 005c 0392 str r2, [sp, #12] 532:Core/Src/main.c **** sConfigIC.ICPrescaler = TIM_ICPSC_DIV1; 514 .loc 1 532 3 is_stmt 1 view .LVU187 532:Core/Src/main.c **** sConfigIC.ICPrescaler = TIM_ICPSC_DIV1; 515 .loc 1 532 25 is_stmt 0 view .LVU188 516 005e 0123 movs r3, #1 517 0060 0493 str r3, [sp, #16] 533:Core/Src/main.c **** sConfigIC.ICFilter = 0; 518 .loc 1 533 3 is_stmt 1 view .LVU189 533:Core/Src/main.c **** sConfigIC.ICFilter = 0; 519 .loc 1 533 25 is_stmt 0 view .LVU190 520 0062 0592 str r2, [sp, #20] 534:Core/Src/main.c **** if (HAL_TIM_IC_ConfigChannel(&htim15, &sConfigIC, TIM_CHANNEL_1) != HAL_OK) 521 .loc 1 534 3 is_stmt 1 view .LVU191 534:Core/Src/main.c **** if (HAL_TIM_IC_ConfigChannel(&htim15, &sConfigIC, TIM_CHANNEL_1) != HAL_OK) 522 .loc 1 534 22 is_stmt 0 view .LVU192 523 0064 0692 str r2, [sp, #24] 535:Core/Src/main.c **** { ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 27 524 .loc 1 535 3 is_stmt 1 view .LVU193 535:Core/Src/main.c **** { 525 .loc 1 535 7 is_stmt 0 view .LVU194 526 0066 03A9 add r1, sp, #12 527 0068 1048 ldr r0, .L25 528 006a FFF7FEFF bl HAL_TIM_IC_ConfigChannel 529 .LVL13: 535:Core/Src/main.c **** { 530 .loc 1 535 6 discriminator 1 view .LVU195 531 006e B8B9 cbnz r0, .L22 539:Core/Src/main.c **** sConfigIC.ICSelection = TIM_ICSELECTION_INDIRECTTI; 532 .loc 1 539 3 is_stmt 1 view .LVU196 539:Core/Src/main.c **** sConfigIC.ICSelection = TIM_ICSELECTION_INDIRECTTI; 533 .loc 1 539 24 is_stmt 0 view .LVU197 534 0070 0223 movs r3, #2 535 0072 0393 str r3, [sp, #12] 540:Core/Src/main.c **** if (HAL_TIM_IC_ConfigChannel(&htim15, &sConfigIC, TIM_CHANNEL_2) != HAL_OK) 536 .loc 1 540 3 is_stmt 1 view .LVU198 540:Core/Src/main.c **** if (HAL_TIM_IC_ConfigChannel(&htim15, &sConfigIC, TIM_CHANNEL_2) != HAL_OK) 537 .loc 1 540 25 is_stmt 0 view .LVU199 538 0074 0493 str r3, [sp, #16] 541:Core/Src/main.c **** { 539 .loc 1 541 3 is_stmt 1 view .LVU200 541:Core/Src/main.c **** { 540 .loc 1 541 7 is_stmt 0 view .LVU201 541 0076 0422 movs r2, #4 542 0078 03A9 add r1, sp, #12 543 007a 0C48 ldr r0, .L25 544 007c FFF7FEFF bl HAL_TIM_IC_ConfigChannel 545 .LVL14: 541:Core/Src/main.c **** { 546 .loc 1 541 6 discriminator 1 view .LVU202 547 0080 80B9 cbnz r0, .L23 545:Core/Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 548 .loc 1 545 3 is_stmt 1 view .LVU203 545:Core/Src/main.c **** sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 549 .loc 1 545 37 is_stmt 0 view .LVU204 550 0082 0023 movs r3, #0 551 0084 0093 str r3, [sp] 546:Core/Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim15, &sMasterConfig) != HAL_OK) 552 .loc 1 546 3 is_stmt 1 view .LVU205 546:Core/Src/main.c **** if (HAL_TIMEx_MasterConfigSynchronization(&htim15, &sMasterConfig) != HAL_OK) 553 .loc 1 546 33 is_stmt 0 view .LVU206 554 0086 0293 str r3, [sp, #8] 547:Core/Src/main.c **** { 555 .loc 1 547 3 is_stmt 1 view .LVU207 547:Core/Src/main.c **** { 556 .loc 1 547 7 is_stmt 0 view .LVU208 557 0088 6946 mov r1, sp 558 008a 0848 ldr r0, .L25 559 008c FFF7FEFF bl HAL_TIMEx_MasterConfigSynchronization 560 .LVL15: 547:Core/Src/main.c **** { 561 .loc 1 547 6 discriminator 1 view .LVU209 562 0090 50B9 cbnz r0, .L24 555:Core/Src/main.c **** 563 .loc 1 555 1 view .LVU210 ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 28 564 0092 0DB0 add sp, sp, #52 565 .cfi_remember_state 566 .cfi_def_cfa_offset 4 567 @ sp needed 568 0094 5DF804FB ldr pc, [sp], #4 569 .L20: 570 .cfi_restore_state 520:Core/Src/main.c **** } 571 .loc 1 520 5 is_stmt 1 view .LVU211 572 0098 FFF7FEFF bl Error_Handler 573 .LVL16: 574 .L21: 529:Core/Src/main.c **** } 575 .loc 1 529 5 view .LVU212 576 009c FFF7FEFF bl Error_Handler 577 .LVL17: 578 .L22: 537:Core/Src/main.c **** } 579 .loc 1 537 5 view .LVU213 580 00a0 FFF7FEFF bl Error_Handler 581 .LVL18: 582 .L23: 543:Core/Src/main.c **** } 583 .loc 1 543 5 view .LVU214 584 00a4 FFF7FEFF bl Error_Handler 585 .LVL19: 586 .L24: 549:Core/Src/main.c **** } 587 .loc 1 549 5 view .LVU215 588 00a8 FFF7FEFF bl Error_Handler 589 .LVL20: 590 .L26: 591 .align 2 592 .L25: 593 00ac 00000000 .word htim15 594 00b0 00400140 .word 1073823744 595 .cfi_endproc 596 .LFE343: 598 .section .text.MX_SPI1_Init,"ax",%progbits 599 .align 1 600 .syntax unified 601 .thumb 602 .thumb_func 604 MX_SPI1_Init: 605 .LFB341: 402:Core/Src/main.c **** 606 .loc 1 402 1 view -0 607 .cfi_startproc 608 @ args = 0, pretend = 0, frame = 0 609 @ frame_needed = 0, uses_anonymous_args = 0 610 0000 08B5 push {r3, lr} 611 .cfi_def_cfa_offset 8 612 .cfi_offset 3, -8 613 .cfi_offset 14, -4 412:Core/Src/main.c **** hspi1.Init.Mode = SPI_MODE_MASTER; 614 .loc 1 412 3 view .LVU217 412:Core/Src/main.c **** hspi1.Init.Mode = SPI_MODE_MASTER; ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 29 615 .loc 1 412 18 is_stmt 0 view .LVU218 616 0002 1348 ldr r0, .L31 617 0004 134B ldr r3, .L31+4 618 0006 0360 str r3, [r0] 413:Core/Src/main.c **** hspi1.Init.Direction = SPI_DIRECTION_2LINES; 619 .loc 1 413 3 is_stmt 1 view .LVU219 413:Core/Src/main.c **** hspi1.Init.Direction = SPI_DIRECTION_2LINES; 620 .loc 1 413 19 is_stmt 0 view .LVU220 621 0008 4FF48003 mov r3, #4194304 622 000c 4360 str r3, [r0, #4] 414:Core/Src/main.c **** hspi1.Init.DataSize = SPI_DATASIZE_4BIT; 623 .loc 1 414 3 is_stmt 1 view .LVU221 414:Core/Src/main.c **** hspi1.Init.DataSize = SPI_DATASIZE_4BIT; 624 .loc 1 414 24 is_stmt 0 view .LVU222 625 000e 0023 movs r3, #0 626 0010 8360 str r3, [r0, #8] 415:Core/Src/main.c **** hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; 627 .loc 1 415 3 is_stmt 1 view .LVU223 415:Core/Src/main.c **** hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; 628 .loc 1 415 23 is_stmt 0 view .LVU224 629 0012 0322 movs r2, #3 630 0014 C260 str r2, [r0, #12] 416:Core/Src/main.c **** hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; 631 .loc 1 416 3 is_stmt 1 view .LVU225 416:Core/Src/main.c **** hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; 632 .loc 1 416 26 is_stmt 0 view .LVU226 633 0016 0361 str r3, [r0, #16] 417:Core/Src/main.c **** hspi1.Init.NSS = SPI_NSS_HARD_OUTPUT; 634 .loc 1 417 3 is_stmt 1 view .LVU227 417:Core/Src/main.c **** hspi1.Init.NSS = SPI_NSS_HARD_OUTPUT; 635 .loc 1 417 23 is_stmt 0 view .LVU228 636 0018 4361 str r3, [r0, #20] 418:Core/Src/main.c **** hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; 637 .loc 1 418 3 is_stmt 1 view .LVU229 418:Core/Src/main.c **** hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; 638 .loc 1 418 18 is_stmt 0 view .LVU230 639 001a 4FF00052 mov r2, #536870912 640 001e 8261 str r2, [r0, #24] 419:Core/Src/main.c **** hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; 641 .loc 1 419 3 is_stmt 1 view .LVU231 419:Core/Src/main.c **** hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; 642 .loc 1 419 32 is_stmt 0 view .LVU232 643 0020 C361 str r3, [r0, #28] 420:Core/Src/main.c **** hspi1.Init.TIMode = SPI_TIMODE_DISABLE; 644 .loc 1 420 3 is_stmt 1 view .LVU233 420:Core/Src/main.c **** hspi1.Init.TIMode = SPI_TIMODE_DISABLE; 645 .loc 1 420 23 is_stmt 0 view .LVU234 646 0022 0362 str r3, [r0, #32] 421:Core/Src/main.c **** hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 647 .loc 1 421 3 is_stmt 1 view .LVU235 421:Core/Src/main.c **** hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 648 .loc 1 421 21 is_stmt 0 view .LVU236 649 0024 4362 str r3, [r0, #36] 422:Core/Src/main.c **** hspi1.Init.CRCPolynomial = 0x0; 650 .loc 1 422 3 is_stmt 1 view .LVU237 422:Core/Src/main.c **** hspi1.Init.CRCPolynomial = 0x0; 651 .loc 1 422 29 is_stmt 0 view .LVU238 ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 30 652 0026 8362 str r3, [r0, #40] 423:Core/Src/main.c **** hspi1.Init.NSSPMode = SPI_NSS_PULSE_ENABLE; 653 .loc 1 423 3 is_stmt 1 view .LVU239 423:Core/Src/main.c **** hspi1.Init.NSSPMode = SPI_NSS_PULSE_ENABLE; 654 .loc 1 423 28 is_stmt 0 view .LVU240 655 0028 C362 str r3, [r0, #44] 424:Core/Src/main.c **** hspi1.Init.NSSPolarity = SPI_NSS_POLARITY_LOW; 656 .loc 1 424 3 is_stmt 1 view .LVU241 424:Core/Src/main.c **** hspi1.Init.NSSPolarity = SPI_NSS_POLARITY_LOW; 657 .loc 1 424 23 is_stmt 0 view .LVU242 658 002a 4FF08042 mov r2, #1073741824 659 002e 4263 str r2, [r0, #52] 425:Core/Src/main.c **** hspi1.Init.FifoThreshold = SPI_FIFO_THRESHOLD_01DATA; 660 .loc 1 425 3 is_stmt 1 view .LVU243 425:Core/Src/main.c **** hspi1.Init.FifoThreshold = SPI_FIFO_THRESHOLD_01DATA; 661 .loc 1 425 26 is_stmt 0 view .LVU244 662 0030 8363 str r3, [r0, #56] 426:Core/Src/main.c **** hspi1.Init.TxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN; 663 .loc 1 426 3 is_stmt 1 view .LVU245 426:Core/Src/main.c **** hspi1.Init.TxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN; 664 .loc 1 426 28 is_stmt 0 view .LVU246 665 0032 C363 str r3, [r0, #60] 427:Core/Src/main.c **** hspi1.Init.RxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN; 666 .loc 1 427 3 is_stmt 1 view .LVU247 427:Core/Src/main.c **** hspi1.Init.RxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN; 667 .loc 1 427 41 is_stmt 0 view .LVU248 668 0034 0364 str r3, [r0, #64] 428:Core/Src/main.c **** hspi1.Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE; 669 .loc 1 428 3 is_stmt 1 view .LVU249 428:Core/Src/main.c **** hspi1.Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE; 670 .loc 1 428 41 is_stmt 0 view .LVU250 671 0036 4364 str r3, [r0, #68] 429:Core/Src/main.c **** hspi1.Init.MasterInterDataIdleness = SPI_MASTER_INTERDATA_IDLENESS_00CYCLE; 672 .loc 1 429 3 is_stmt 1 view .LVU251 429:Core/Src/main.c **** hspi1.Init.MasterInterDataIdleness = SPI_MASTER_INTERDATA_IDLENESS_00CYCLE; 673 .loc 1 429 31 is_stmt 0 view .LVU252 674 0038 8364 str r3, [r0, #72] 430:Core/Src/main.c **** hspi1.Init.MasterReceiverAutoSusp = SPI_MASTER_RX_AUTOSUSP_DISABLE; 675 .loc 1 430 3 is_stmt 1 view .LVU253 430:Core/Src/main.c **** hspi1.Init.MasterReceiverAutoSusp = SPI_MASTER_RX_AUTOSUSP_DISABLE; 676 .loc 1 430 38 is_stmt 0 view .LVU254 677 003a C364 str r3, [r0, #76] 431:Core/Src/main.c **** hspi1.Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_DISABLE; 678 .loc 1 431 3 is_stmt 1 view .LVU255 431:Core/Src/main.c **** hspi1.Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_DISABLE; 679 .loc 1 431 37 is_stmt 0 view .LVU256 680 003c 0365 str r3, [r0, #80] 432:Core/Src/main.c **** hspi1.Init.IOSwap = SPI_IO_SWAP_DISABLE; 681 .loc 1 432 3 is_stmt 1 view .LVU257 432:Core/Src/main.c **** hspi1.Init.IOSwap = SPI_IO_SWAP_DISABLE; 682 .loc 1 432 32 is_stmt 0 view .LVU258 683 003e 4365 str r3, [r0, #84] 433:Core/Src/main.c **** if (HAL_SPI_Init(&hspi1) != HAL_OK) 684 .loc 1 433 3 is_stmt 1 view .LVU259 433:Core/Src/main.c **** if (HAL_SPI_Init(&hspi1) != HAL_OK) 685 .loc 1 433 21 is_stmt 0 view .LVU260 686 0040 8365 str r3, [r0, #88] ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 31 434:Core/Src/main.c **** { 687 .loc 1 434 3 is_stmt 1 view .LVU261 434:Core/Src/main.c **** { 688 .loc 1 434 7 is_stmt 0 view .LVU262 689 0042 FFF7FEFF bl HAL_SPI_Init 690 .LVL21: 434:Core/Src/main.c **** { 691 .loc 1 434 6 discriminator 1 view .LVU263 692 0046 00B9 cbnz r0, .L30 442:Core/Src/main.c **** 693 .loc 1 442 1 view .LVU264 694 0048 08BD pop {r3, pc} 695 .L30: 436:Core/Src/main.c **** } 696 .loc 1 436 5 is_stmt 1 view .LVU265 697 004a FFF7FEFF bl Error_Handler 698 .LVL22: 699 .L32: 700 004e 00BF .align 2 701 .L31: 702 0050 00000000 .word hspi1 703 0054 00300140 .word 1073819648 704 .cfi_endproc 705 .LFE341: 707 .section .text.MX_SPI2_Init,"ax",%progbits 708 .align 1 709 .syntax unified 710 .thumb 711 .thumb_func 713 MX_SPI2_Init: 714 .LFB342: 450:Core/Src/main.c **** 715 .loc 1 450 1 view -0 716 .cfi_startproc 717 @ args = 0, pretend = 0, frame = 0 718 @ frame_needed = 0, uses_anonymous_args = 0 719 0000 08B5 push {r3, lr} 720 .cfi_def_cfa_offset 8 721 .cfi_offset 3, -8 722 .cfi_offset 14, -4 460:Core/Src/main.c **** hspi2.Init.Mode = SPI_MODE_MASTER; 723 .loc 1 460 3 view .LVU267 460:Core/Src/main.c **** hspi2.Init.Mode = SPI_MODE_MASTER; 724 .loc 1 460 18 is_stmt 0 view .LVU268 725 0002 1248 ldr r0, .L37 726 0004 124B ldr r3, .L37+4 727 0006 0360 str r3, [r0] 461:Core/Src/main.c **** hspi2.Init.Direction = SPI_DIRECTION_2LINES; 728 .loc 1 461 3 is_stmt 1 view .LVU269 461:Core/Src/main.c **** hspi2.Init.Direction = SPI_DIRECTION_2LINES; 729 .loc 1 461 19 is_stmt 0 view .LVU270 730 0008 4FF48003 mov r3, #4194304 731 000c 4360 str r3, [r0, #4] 462:Core/Src/main.c **** hspi2.Init.DataSize = SPI_DATASIZE_4BIT; 732 .loc 1 462 3 is_stmt 1 view .LVU271 462:Core/Src/main.c **** hspi2.Init.DataSize = SPI_DATASIZE_4BIT; 733 .loc 1 462 24 is_stmt 0 view .LVU272 ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 32 734 000e 0023 movs r3, #0 735 0010 8360 str r3, [r0, #8] 463:Core/Src/main.c **** hspi2.Init.CLKPolarity = SPI_POLARITY_LOW; 736 .loc 1 463 3 is_stmt 1 view .LVU273 463:Core/Src/main.c **** hspi2.Init.CLKPolarity = SPI_POLARITY_LOW; 737 .loc 1 463 23 is_stmt 0 view .LVU274 738 0012 0322 movs r2, #3 739 0014 C260 str r2, [r0, #12] 464:Core/Src/main.c **** hspi2.Init.CLKPhase = SPI_PHASE_1EDGE; 740 .loc 1 464 3 is_stmt 1 view .LVU275 464:Core/Src/main.c **** hspi2.Init.CLKPhase = SPI_PHASE_1EDGE; 741 .loc 1 464 26 is_stmt 0 view .LVU276 742 0016 0361 str r3, [r0, #16] 465:Core/Src/main.c **** hspi2.Init.NSS = SPI_NSS_HARD_INPUT; 743 .loc 1 465 3 is_stmt 1 view .LVU277 465:Core/Src/main.c **** hspi2.Init.NSS = SPI_NSS_HARD_INPUT; 744 .loc 1 465 23 is_stmt 0 view .LVU278 745 0018 4361 str r3, [r0, #20] 466:Core/Src/main.c **** hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; 746 .loc 1 466 3 is_stmt 1 view .LVU279 466:Core/Src/main.c **** hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; 747 .loc 1 466 18 is_stmt 0 view .LVU280 748 001a 8361 str r3, [r0, #24] 467:Core/Src/main.c **** hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB; 749 .loc 1 467 3 is_stmt 1 view .LVU281 467:Core/Src/main.c **** hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB; 750 .loc 1 467 32 is_stmt 0 view .LVU282 751 001c C361 str r3, [r0, #28] 468:Core/Src/main.c **** hspi2.Init.TIMode = SPI_TIMODE_DISABLE; 752 .loc 1 468 3 is_stmt 1 view .LVU283 468:Core/Src/main.c **** hspi2.Init.TIMode = SPI_TIMODE_DISABLE; 753 .loc 1 468 23 is_stmt 0 view .LVU284 754 001e 0362 str r3, [r0, #32] 469:Core/Src/main.c **** hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 755 .loc 1 469 3 is_stmt 1 view .LVU285 469:Core/Src/main.c **** hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; 756 .loc 1 469 21 is_stmt 0 view .LVU286 757 0020 4362 str r3, [r0, #36] 470:Core/Src/main.c **** hspi2.Init.CRCPolynomial = 0x0; 758 .loc 1 470 3 is_stmt 1 view .LVU287 470:Core/Src/main.c **** hspi2.Init.CRCPolynomial = 0x0; 759 .loc 1 470 29 is_stmt 0 view .LVU288 760 0022 8362 str r3, [r0, #40] 471:Core/Src/main.c **** hspi2.Init.NSSPMode = SPI_NSS_PULSE_ENABLE; 761 .loc 1 471 3 is_stmt 1 view .LVU289 471:Core/Src/main.c **** hspi2.Init.NSSPMode = SPI_NSS_PULSE_ENABLE; 762 .loc 1 471 28 is_stmt 0 view .LVU290 763 0024 C362 str r3, [r0, #44] 472:Core/Src/main.c **** hspi2.Init.NSSPolarity = SPI_NSS_POLARITY_LOW; 764 .loc 1 472 3 is_stmt 1 view .LVU291 472:Core/Src/main.c **** hspi2.Init.NSSPolarity = SPI_NSS_POLARITY_LOW; 765 .loc 1 472 23 is_stmt 0 view .LVU292 766 0026 4FF08042 mov r2, #1073741824 767 002a 4263 str r2, [r0, #52] 473:Core/Src/main.c **** hspi2.Init.FifoThreshold = SPI_FIFO_THRESHOLD_01DATA; 768 .loc 1 473 3 is_stmt 1 view .LVU293 473:Core/Src/main.c **** hspi2.Init.FifoThreshold = SPI_FIFO_THRESHOLD_01DATA; ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 33 769 .loc 1 473 26 is_stmt 0 view .LVU294 770 002c 8363 str r3, [r0, #56] 474:Core/Src/main.c **** hspi2.Init.TxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN; 771 .loc 1 474 3 is_stmt 1 view .LVU295 474:Core/Src/main.c **** hspi2.Init.TxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN; 772 .loc 1 474 28 is_stmt 0 view .LVU296 773 002e C363 str r3, [r0, #60] 475:Core/Src/main.c **** hspi2.Init.RxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN; 774 .loc 1 475 3 is_stmt 1 view .LVU297 475:Core/Src/main.c **** hspi2.Init.RxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN; 775 .loc 1 475 41 is_stmt 0 view .LVU298 776 0030 0364 str r3, [r0, #64] 476:Core/Src/main.c **** hspi2.Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE; 777 .loc 1 476 3 is_stmt 1 view .LVU299 476:Core/Src/main.c **** hspi2.Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE; 778 .loc 1 476 41 is_stmt 0 view .LVU300 779 0032 4364 str r3, [r0, #68] 477:Core/Src/main.c **** hspi2.Init.MasterInterDataIdleness = SPI_MASTER_INTERDATA_IDLENESS_00CYCLE; 780 .loc 1 477 3 is_stmt 1 view .LVU301 477:Core/Src/main.c **** hspi2.Init.MasterInterDataIdleness = SPI_MASTER_INTERDATA_IDLENESS_00CYCLE; 781 .loc 1 477 31 is_stmt 0 view .LVU302 782 0034 8364 str r3, [r0, #72] 478:Core/Src/main.c **** hspi2.Init.MasterReceiverAutoSusp = SPI_MASTER_RX_AUTOSUSP_DISABLE; 783 .loc 1 478 3 is_stmt 1 view .LVU303 478:Core/Src/main.c **** hspi2.Init.MasterReceiverAutoSusp = SPI_MASTER_RX_AUTOSUSP_DISABLE; 784 .loc 1 478 38 is_stmt 0 view .LVU304 785 0036 C364 str r3, [r0, #76] 479:Core/Src/main.c **** hspi2.Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_DISABLE; 786 .loc 1 479 3 is_stmt 1 view .LVU305 479:Core/Src/main.c **** hspi2.Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_DISABLE; 787 .loc 1 479 37 is_stmt 0 view .LVU306 788 0038 0365 str r3, [r0, #80] 480:Core/Src/main.c **** hspi2.Init.IOSwap = SPI_IO_SWAP_DISABLE; 789 .loc 1 480 3 is_stmt 1 view .LVU307 480:Core/Src/main.c **** hspi2.Init.IOSwap = SPI_IO_SWAP_DISABLE; 790 .loc 1 480 32 is_stmt 0 view .LVU308 791 003a 4365 str r3, [r0, #84] 481:Core/Src/main.c **** if (HAL_SPI_Init(&hspi2) != HAL_OK) 792 .loc 1 481 3 is_stmt 1 view .LVU309 481:Core/Src/main.c **** if (HAL_SPI_Init(&hspi2) != HAL_OK) 793 .loc 1 481 21 is_stmt 0 view .LVU310 794 003c 8365 str r3, [r0, #88] 482:Core/Src/main.c **** { 795 .loc 1 482 3 is_stmt 1 view .LVU311 482:Core/Src/main.c **** { 796 .loc 1 482 7 is_stmt 0 view .LVU312 797 003e FFF7FEFF bl HAL_SPI_Init 798 .LVL23: 482:Core/Src/main.c **** { 799 .loc 1 482 6 discriminator 1 view .LVU313 800 0042 00B9 cbnz r0, .L36 490:Core/Src/main.c **** 801 .loc 1 490 1 view .LVU314 802 0044 08BD pop {r3, pc} 803 .L36: 484:Core/Src/main.c **** } 804 .loc 1 484 5 is_stmt 1 view .LVU315 ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 34 805 0046 FFF7FEFF bl Error_Handler 806 .LVL24: 807 .L38: 808 004a 00BF .align 2 809 .L37: 810 004c 00000000 .word hspi2 811 0050 00380040 .word 1073756160 812 .cfi_endproc 813 .LFE342: 815 .section .text.MX_ADC1_Init,"ax",%progbits 816 .align 1 817 .syntax unified 818 .thumb 819 .thumb_func 821 MX_ADC1_Init: 822 .LFB338: 222:Core/Src/main.c **** 823 .loc 1 222 1 view -0 824 .cfi_startproc 825 @ args = 0, pretend = 0, frame = 40 826 @ frame_needed = 0, uses_anonymous_args = 0 827 0000 00B5 push {lr} 828 .cfi_def_cfa_offset 4 829 .cfi_offset 14, -4 830 0002 8BB0 sub sp, sp, #44 831 .cfi_def_cfa_offset 48 228:Core/Src/main.c **** ADC_ChannelConfTypeDef sConfig = {0}; 832 .loc 1 228 3 view .LVU317 228:Core/Src/main.c **** ADC_ChannelConfTypeDef sConfig = {0}; 833 .loc 1 228 24 is_stmt 0 view .LVU318 834 0004 0023 movs r3, #0 835 0006 0793 str r3, [sp, #28] 836 0008 0893 str r3, [sp, #32] 837 000a 0993 str r3, [sp, #36] 229:Core/Src/main.c **** 838 .loc 1 229 3 is_stmt 1 view .LVU319 229:Core/Src/main.c **** 839 .loc 1 229 26 is_stmt 0 view .LVU320 840 000c 0093 str r3, [sp] 841 000e 0193 str r3, [sp, #4] 842 0010 0293 str r3, [sp, #8] 843 0012 0393 str r3, [sp, #12] 844 0014 0493 str r3, [sp, #16] 845 0016 0593 str r3, [sp, #20] 846 0018 0693 str r3, [sp, #24] 237:Core/Src/main.c **** hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; 847 .loc 1 237 3 is_stmt 1 view .LVU321 237:Core/Src/main.c **** hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; 848 .loc 1 237 18 is_stmt 0 view .LVU322 849 001a 1D48 ldr r0, .L47 850 001c 1D4A ldr r2, .L47+4 851 001e 0260 str r2, [r0] 238:Core/Src/main.c **** hadc1.Init.Resolution = ADC_RESOLUTION_16B; 852 .loc 1 238 3 is_stmt 1 view .LVU323 238:Core/Src/main.c **** hadc1.Init.Resolution = ADC_RESOLUTION_16B; 853 .loc 1 238 29 is_stmt 0 view .LVU324 854 0020 4360 str r3, [r0, #4] ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 35 239:Core/Src/main.c **** hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE; 855 .loc 1 239 3 is_stmt 1 view .LVU325 239:Core/Src/main.c **** hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE; 856 .loc 1 239 25 is_stmt 0 view .LVU326 857 0022 8360 str r3, [r0, #8] 240:Core/Src/main.c **** hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 858 .loc 1 240 3 is_stmt 1 view .LVU327 240:Core/Src/main.c **** hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 859 .loc 1 240 27 is_stmt 0 view .LVU328 860 0024 C360 str r3, [r0, #12] 241:Core/Src/main.c **** hadc1.Init.LowPowerAutoWait = DISABLE; 861 .loc 1 241 3 is_stmt 1 view .LVU329 241:Core/Src/main.c **** hadc1.Init.LowPowerAutoWait = DISABLE; 862 .loc 1 241 27 is_stmt 0 view .LVU330 863 0026 0422 movs r2, #4 864 0028 0261 str r2, [r0, #16] 242:Core/Src/main.c **** hadc1.Init.ContinuousConvMode = DISABLE; 865 .loc 1 242 3 is_stmt 1 view .LVU331 242:Core/Src/main.c **** hadc1.Init.ContinuousConvMode = DISABLE; 866 .loc 1 242 31 is_stmt 0 view .LVU332 867 002a 0375 strb r3, [r0, #20] 243:Core/Src/main.c **** hadc1.Init.NbrOfConversion = 1; 868 .loc 1 243 3 is_stmt 1 view .LVU333 243:Core/Src/main.c **** hadc1.Init.NbrOfConversion = 1; 869 .loc 1 243 33 is_stmt 0 view .LVU334 870 002c 4375 strb r3, [r0, #21] 244:Core/Src/main.c **** hadc1.Init.DiscontinuousConvMode = DISABLE; 871 .loc 1 244 3 is_stmt 1 view .LVU335 244:Core/Src/main.c **** hadc1.Init.DiscontinuousConvMode = DISABLE; 872 .loc 1 244 30 is_stmt 0 view .LVU336 873 002e 0122 movs r2, #1 874 0030 8261 str r2, [r0, #24] 245:Core/Src/main.c **** hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; 875 .loc 1 245 3 is_stmt 1 view .LVU337 245:Core/Src/main.c **** hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; 876 .loc 1 245 36 is_stmt 0 view .LVU338 877 0032 0377 strb r3, [r0, #28] 246:Core/Src/main.c **** hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; 878 .loc 1 246 3 is_stmt 1 view .LVU339 246:Core/Src/main.c **** hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; 879 .loc 1 246 31 is_stmt 0 view .LVU340 880 0034 4362 str r3, [r0, #36] 247:Core/Src/main.c **** hadc1.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR; 881 .loc 1 247 3 is_stmt 1 view .LVU341 247:Core/Src/main.c **** hadc1.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR; 882 .loc 1 247 35 is_stmt 0 view .LVU342 883 0036 8362 str r3, [r0, #40] 248:Core/Src/main.c **** hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED; 884 .loc 1 248 3 is_stmt 1 view .LVU343 248:Core/Src/main.c **** hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED; 885 .loc 1 248 39 is_stmt 0 view .LVU344 886 0038 C362 str r3, [r0, #44] 249:Core/Src/main.c **** hadc1.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE; 887 .loc 1 249 3 is_stmt 1 view .LVU345 249:Core/Src/main.c **** hadc1.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE; 888 .loc 1 249 22 is_stmt 0 view .LVU346 889 003a 0363 str r3, [r0, #48] ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 36 250:Core/Src/main.c **** hadc1.Init.OversamplingMode = DISABLE; 890 .loc 1 250 3 is_stmt 1 view .LVU347 250:Core/Src/main.c **** hadc1.Init.OversamplingMode = DISABLE; 891 .loc 1 250 27 is_stmt 0 view .LVU348 892 003c 4363 str r3, [r0, #52] 251:Core/Src/main.c **** if (HAL_ADC_Init(&hadc1) != HAL_OK) 893 .loc 1 251 3 is_stmt 1 view .LVU349 251:Core/Src/main.c **** if (HAL_ADC_Init(&hadc1) != HAL_OK) 894 .loc 1 251 31 is_stmt 0 view .LVU350 895 003e 80F83830 strb r3, [r0, #56] 252:Core/Src/main.c **** { 896 .loc 1 252 3 is_stmt 1 view .LVU351 252:Core/Src/main.c **** { 897 .loc 1 252 7 is_stmt 0 view .LVU352 898 0042 FFF7FEFF bl HAL_ADC_Init 899 .LVL25: 252:Core/Src/main.c **** { 900 .loc 1 252 6 discriminator 1 view .LVU353 901 0046 E0B9 cbnz r0, .L44 259:Core/Src/main.c **** if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK) 902 .loc 1 259 3 is_stmt 1 view .LVU354 259:Core/Src/main.c **** if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK) 903 .loc 1 259 18 is_stmt 0 view .LVU355 904 0048 0023 movs r3, #0 905 004a 0793 str r3, [sp, #28] 260:Core/Src/main.c **** { 906 .loc 1 260 3 is_stmt 1 view .LVU356 260:Core/Src/main.c **** { 907 .loc 1 260 7 is_stmt 0 view .LVU357 908 004c 07A9 add r1, sp, #28 909 004e 1048 ldr r0, .L47 910 0050 FFF7FEFF bl HAL_ADCEx_MultiModeConfigChannel 911 .LVL26: 260:Core/Src/main.c **** { 912 .loc 1 260 6 discriminator 1 view .LVU358 913 0054 B8B9 cbnz r0, .L45 267:Core/Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_1; 914 .loc 1 267 3 is_stmt 1 view .LVU359 267:Core/Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_1; 915 .loc 1 267 19 is_stmt 0 view .LVU360 916 0056 104B ldr r3, .L47+8 917 0058 0093 str r3, [sp] 268:Core/Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5; 918 .loc 1 268 3 is_stmt 1 view .LVU361 268:Core/Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5; 919 .loc 1 268 16 is_stmt 0 view .LVU362 920 005a 0623 movs r3, #6 921 005c 0193 str r3, [sp, #4] 269:Core/Src/main.c **** sConfig.SingleDiff = ADC_SINGLE_ENDED; 922 .loc 1 269 3 is_stmt 1 view .LVU363 269:Core/Src/main.c **** sConfig.SingleDiff = ADC_SINGLE_ENDED; 923 .loc 1 269 24 is_stmt 0 view .LVU364 924 005e 0023 movs r3, #0 925 0060 0293 str r3, [sp, #8] 270:Core/Src/main.c **** sConfig.OffsetNumber = ADC_OFFSET_NONE; 926 .loc 1 270 3 is_stmt 1 view .LVU365 270:Core/Src/main.c **** sConfig.OffsetNumber = ADC_OFFSET_NONE; ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 37 927 .loc 1 270 22 is_stmt 0 view .LVU366 928 0062 40F2FF72 movw r2, #2047 929 0066 0392 str r2, [sp, #12] 271:Core/Src/main.c **** sConfig.Offset = 0; 930 .loc 1 271 3 is_stmt 1 view .LVU367 271:Core/Src/main.c **** sConfig.Offset = 0; 931 .loc 1 271 24 is_stmt 0 view .LVU368 932 0068 0422 movs r2, #4 933 006a 0492 str r2, [sp, #16] 272:Core/Src/main.c **** sConfig.OffsetSignedSaturation = DISABLE; 934 .loc 1 272 3 is_stmt 1 view .LVU369 272:Core/Src/main.c **** sConfig.OffsetSignedSaturation = DISABLE; 935 .loc 1 272 18 is_stmt 0 view .LVU370 936 006c 0593 str r3, [sp, #20] 273:Core/Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 937 .loc 1 273 3 is_stmt 1 view .LVU371 273:Core/Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) 938 .loc 1 273 34 is_stmt 0 view .LVU372 939 006e 8DF81930 strb r3, [sp, #25] 274:Core/Src/main.c **** { 940 .loc 1 274 3 is_stmt 1 view .LVU373 274:Core/Src/main.c **** { 941 .loc 1 274 7 is_stmt 0 view .LVU374 942 0072 6946 mov r1, sp 943 0074 0648 ldr r0, .L47 944 0076 FFF7FEFF bl HAL_ADC_ConfigChannel 945 .LVL27: 274:Core/Src/main.c **** { 946 .loc 1 274 6 discriminator 1 view .LVU375 947 007a 30B9 cbnz r0, .L46 282:Core/Src/main.c **** 948 .loc 1 282 1 view .LVU376 949 007c 0BB0 add sp, sp, #44 950 .cfi_remember_state 951 .cfi_def_cfa_offset 4 952 @ sp needed 953 007e 5DF804FB ldr pc, [sp], #4 954 .L44: 955 .cfi_restore_state 254:Core/Src/main.c **** } 956 .loc 1 254 5 is_stmt 1 view .LVU377 957 0082 FFF7FEFF bl Error_Handler 958 .LVL28: 959 .L45: 262:Core/Src/main.c **** } 960 .loc 1 262 5 view .LVU378 961 0086 FFF7FEFF bl Error_Handler 962 .LVL29: 963 .L46: 276:Core/Src/main.c **** } 964 .loc 1 276 5 view .LVU379 965 008a FFF7FEFF bl Error_Handler 966 .LVL30: 967 .L48: 968 008e 00BF .align 2 969 .L47: 970 0090 00000000 .word hadc1 ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 38 971 0094 00200240 .word 1073881088 972 0098 0004002A .word 704644096 973 .cfi_endproc 974 .LFE338: 976 .section .text.MX_ADC2_Init,"ax",%progbits 977 .align 1 978 .syntax unified 979 .thumb 980 .thumb_func 982 MX_ADC2_Init: 983 .LFB339: 290:Core/Src/main.c **** 984 .loc 1 290 1 view -0 985 .cfi_startproc 986 @ args = 0, pretend = 0, frame = 32 987 @ frame_needed = 0, uses_anonymous_args = 0 988 0000 00B5 push {lr} 989 .cfi_def_cfa_offset 4 990 .cfi_offset 14, -4 991 0002 89B0 sub sp, sp, #36 992 .cfi_def_cfa_offset 40 296:Core/Src/main.c **** 993 .loc 1 296 3 view .LVU381 296:Core/Src/main.c **** 994 .loc 1 296 26 is_stmt 0 view .LVU382 995 0004 0023 movs r3, #0 996 0006 0193 str r3, [sp, #4] 997 0008 0293 str r3, [sp, #8] 998 000a 0393 str r3, [sp, #12] 999 000c 0493 str r3, [sp, #16] 1000 000e 0593 str r3, [sp, #20] 1001 0010 0693 str r3, [sp, #24] 1002 0012 0793 str r3, [sp, #28] 304:Core/Src/main.c **** hadc2.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; 1003 .loc 1 304 3 is_stmt 1 view .LVU383 304:Core/Src/main.c **** hadc2.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1; 1004 .loc 1 304 18 is_stmt 0 view .LVU384 1005 0014 1848 ldr r0, .L55 1006 0016 194A ldr r2, .L55+4 1007 0018 0260 str r2, [r0] 305:Core/Src/main.c **** hadc2.Init.Resolution = ADC_RESOLUTION_16B; 1008 .loc 1 305 3 is_stmt 1 view .LVU385 305:Core/Src/main.c **** hadc2.Init.Resolution = ADC_RESOLUTION_16B; 1009 .loc 1 305 29 is_stmt 0 view .LVU386 1010 001a 4360 str r3, [r0, #4] 306:Core/Src/main.c **** hadc2.Init.ScanConvMode = ADC_SCAN_DISABLE; 1011 .loc 1 306 3 is_stmt 1 view .LVU387 306:Core/Src/main.c **** hadc2.Init.ScanConvMode = ADC_SCAN_DISABLE; 1012 .loc 1 306 25 is_stmt 0 view .LVU388 1013 001c 8360 str r3, [r0, #8] 307:Core/Src/main.c **** hadc2.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 1014 .loc 1 307 3 is_stmt 1 view .LVU389 307:Core/Src/main.c **** hadc2.Init.EOCSelection = ADC_EOC_SINGLE_CONV; 1015 .loc 1 307 27 is_stmt 0 view .LVU390 1016 001e C360 str r3, [r0, #12] 308:Core/Src/main.c **** hadc2.Init.LowPowerAutoWait = DISABLE; 1017 .loc 1 308 3 is_stmt 1 view .LVU391 ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 39 308:Core/Src/main.c **** hadc2.Init.LowPowerAutoWait = DISABLE; 1018 .loc 1 308 27 is_stmt 0 view .LVU392 1019 0020 0422 movs r2, #4 1020 0022 0261 str r2, [r0, #16] 309:Core/Src/main.c **** hadc2.Init.ContinuousConvMode = DISABLE; 1021 .loc 1 309 3 is_stmt 1 view .LVU393 309:Core/Src/main.c **** hadc2.Init.ContinuousConvMode = DISABLE; 1022 .loc 1 309 31 is_stmt 0 view .LVU394 1023 0024 0375 strb r3, [r0, #20] 310:Core/Src/main.c **** hadc2.Init.NbrOfConversion = 1; 1024 .loc 1 310 3 is_stmt 1 view .LVU395 310:Core/Src/main.c **** hadc2.Init.NbrOfConversion = 1; 1025 .loc 1 310 33 is_stmt 0 view .LVU396 1026 0026 4375 strb r3, [r0, #21] 311:Core/Src/main.c **** hadc2.Init.DiscontinuousConvMode = DISABLE; 1027 .loc 1 311 3 is_stmt 1 view .LVU397 311:Core/Src/main.c **** hadc2.Init.DiscontinuousConvMode = DISABLE; 1028 .loc 1 311 30 is_stmt 0 view .LVU398 1029 0028 0122 movs r2, #1 1030 002a 8261 str r2, [r0, #24] 312:Core/Src/main.c **** hadc2.Init.ExternalTrigConv = ADC_SOFTWARE_START; 1031 .loc 1 312 3 is_stmt 1 view .LVU399 312:Core/Src/main.c **** hadc2.Init.ExternalTrigConv = ADC_SOFTWARE_START; 1032 .loc 1 312 36 is_stmt 0 view .LVU400 1033 002c 0377 strb r3, [r0, #28] 313:Core/Src/main.c **** hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; 1034 .loc 1 313 3 is_stmt 1 view .LVU401 313:Core/Src/main.c **** hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; 1035 .loc 1 313 31 is_stmt 0 view .LVU402 1036 002e 4362 str r3, [r0, #36] 314:Core/Src/main.c **** hadc2.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR; 1037 .loc 1 314 3 is_stmt 1 view .LVU403 314:Core/Src/main.c **** hadc2.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR; 1038 .loc 1 314 35 is_stmt 0 view .LVU404 1039 0030 8362 str r3, [r0, #40] 315:Core/Src/main.c **** hadc2.Init.Overrun = ADC_OVR_DATA_PRESERVED; 1040 .loc 1 315 3 is_stmt 1 view .LVU405 315:Core/Src/main.c **** hadc2.Init.Overrun = ADC_OVR_DATA_PRESERVED; 1041 .loc 1 315 39 is_stmt 0 view .LVU406 1042 0032 C362 str r3, [r0, #44] 316:Core/Src/main.c **** hadc2.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE; 1043 .loc 1 316 3 is_stmt 1 view .LVU407 316:Core/Src/main.c **** hadc2.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE; 1044 .loc 1 316 22 is_stmt 0 view .LVU408 1045 0034 0363 str r3, [r0, #48] 317:Core/Src/main.c **** hadc2.Init.OversamplingMode = DISABLE; 1046 .loc 1 317 3 is_stmt 1 view .LVU409 317:Core/Src/main.c **** hadc2.Init.OversamplingMode = DISABLE; 1047 .loc 1 317 27 is_stmt 0 view .LVU410 1048 0036 4363 str r3, [r0, #52] 318:Core/Src/main.c **** if (HAL_ADC_Init(&hadc2) != HAL_OK) 1049 .loc 1 318 3 is_stmt 1 view .LVU411 318:Core/Src/main.c **** if (HAL_ADC_Init(&hadc2) != HAL_OK) 1050 .loc 1 318 31 is_stmt 0 view .LVU412 1051 0038 80F83830 strb r3, [r0, #56] 319:Core/Src/main.c **** { 1052 .loc 1 319 3 is_stmt 1 view .LVU413 ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 40 319:Core/Src/main.c **** { 1053 .loc 1 319 7 is_stmt 0 view .LVU414 1054 003c FFF7FEFF bl HAL_ADC_Init 1055 .LVL31: 319:Core/Src/main.c **** { 1056 .loc 1 319 6 discriminator 1 view .LVU415 1057 0040 A8B9 cbnz r0, .L53 326:Core/Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_1; 1058 .loc 1 326 3 is_stmt 1 view .LVU416 326:Core/Src/main.c **** sConfig.Rank = ADC_REGULAR_RANK_1; 1059 .loc 1 326 19 is_stmt 0 view .LVU417 1060 0042 0F4B ldr r3, .L55+8 1061 0044 0193 str r3, [sp, #4] 327:Core/Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5; 1062 .loc 1 327 3 is_stmt 1 view .LVU418 327:Core/Src/main.c **** sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5; 1063 .loc 1 327 16 is_stmt 0 view .LVU419 1064 0046 0623 movs r3, #6 1065 0048 0293 str r3, [sp, #8] 328:Core/Src/main.c **** sConfig.SingleDiff = ADC_DIFFERENTIAL_ENDED; 1066 .loc 1 328 3 is_stmt 1 view .LVU420 328:Core/Src/main.c **** sConfig.SingleDiff = ADC_DIFFERENTIAL_ENDED; 1067 .loc 1 328 24 is_stmt 0 view .LVU421 1068 004a 0023 movs r3, #0 1069 004c 0393 str r3, [sp, #12] 329:Core/Src/main.c **** sConfig.OffsetNumber = ADC_OFFSET_NONE; 1070 .loc 1 329 3 is_stmt 1 view .LVU422 329:Core/Src/main.c **** sConfig.OffsetNumber = ADC_OFFSET_NONE; 1071 .loc 1 329 22 is_stmt 0 view .LVU423 1072 004e 0D4A ldr r2, .L55+12 1073 0050 0492 str r2, [sp, #16] 330:Core/Src/main.c **** sConfig.Offset = 0; 1074 .loc 1 330 3 is_stmt 1 view .LVU424 330:Core/Src/main.c **** sConfig.Offset = 0; 1075 .loc 1 330 24 is_stmt 0 view .LVU425 1076 0052 0422 movs r2, #4 1077 0054 0592 str r2, [sp, #20] 331:Core/Src/main.c **** sConfig.OffsetSignedSaturation = DISABLE; 1078 .loc 1 331 3 is_stmt 1 view .LVU426 331:Core/Src/main.c **** sConfig.OffsetSignedSaturation = DISABLE; 1079 .loc 1 331 18 is_stmt 0 view .LVU427 1080 0056 0693 str r3, [sp, #24] 332:Core/Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 1081 .loc 1 332 3 is_stmt 1 view .LVU428 332:Core/Src/main.c **** if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) 1082 .loc 1 332 34 is_stmt 0 view .LVU429 1083 0058 8DF81D30 strb r3, [sp, #29] 333:Core/Src/main.c **** { 1084 .loc 1 333 3 is_stmt 1 view .LVU430 333:Core/Src/main.c **** { 1085 .loc 1 333 7 is_stmt 0 view .LVU431 1086 005c 0DEB0201 add r1, sp, r2 1087 0060 0548 ldr r0, .L55 1088 0062 FFF7FEFF bl HAL_ADC_ConfigChannel 1089 .LVL32: 333:Core/Src/main.c **** { 1090 .loc 1 333 6 discriminator 1 view .LVU432 ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 41 1091 0066 20B9 cbnz r0, .L54 341:Core/Src/main.c **** 1092 .loc 1 341 1 view .LVU433 1093 0068 09B0 add sp, sp, #36 1094 .cfi_remember_state 1095 .cfi_def_cfa_offset 4 1096 @ sp needed 1097 006a 5DF804FB ldr pc, [sp], #4 1098 .L53: 1099 .cfi_restore_state 321:Core/Src/main.c **** } 1100 .loc 1 321 5 is_stmt 1 view .LVU434 1101 006e FFF7FEFF bl Error_Handler 1102 .LVL33: 1103 .L54: 335:Core/Src/main.c **** } 1104 .loc 1 335 5 view .LVU435 1105 0072 FFF7FEFF bl Error_Handler 1106 .LVL34: 1107 .L56: 1108 0076 00BF .align 2 1109 .L55: 1110 0078 00000000 .word hadc2 1111 007c 00210240 .word 1073881344 1112 0080 0004002A .word 704644096 1113 0084 0000FF47 .word 1207894016 1114 .cfi_endproc 1115 .LFE339: 1117 .section .text.SystemClock_Config,"ax",%progbits 1118 .align 1 1119 .global SystemClock_Config 1120 .syntax unified 1121 .thumb 1122 .thumb_func 1124 SystemClock_Config: 1125 .LFB336: 133:Core/Src/main.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 1126 .loc 1 133 1 view -0 1127 .cfi_startproc 1128 @ args = 0, pretend = 0, frame = 112 1129 @ frame_needed = 0, uses_anonymous_args = 0 1130 0000 00B5 push {lr} 1131 .cfi_def_cfa_offset 4 1132 .cfi_offset 14, -4 1133 0002 9DB0 sub sp, sp, #116 1134 .cfi_def_cfa_offset 120 134:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 1135 .loc 1 134 3 view .LVU437 134:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 1136 .loc 1 134 22 is_stmt 0 view .LVU438 1137 0004 4C22 movs r2, #76 1138 0006 0021 movs r1, #0 1139 0008 09A8 add r0, sp, #36 1140 000a FFF7FEFF bl memset 1141 .LVL35: 135:Core/Src/main.c **** 1142 .loc 1 135 3 is_stmt 1 view .LVU439 ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 42 135:Core/Src/main.c **** 1143 .loc 1 135 22 is_stmt 0 view .LVU440 1144 000e 2022 movs r2, #32 1145 0010 0021 movs r1, #0 1146 0012 01A8 add r0, sp, #4 1147 0014 FFF7FEFF bl memset 1148 .LVL36: 138:Core/Src/main.c **** 1149 .loc 1 138 3 is_stmt 1 view .LVU441 138:Core/Src/main.c **** 1150 .loc 1 138 16 is_stmt 0 view .LVU442 1151 0018 234B ldr r3, .L64 1152 001a 4FF0FF32 mov r2, #-1 1153 001e C3F8B020 str r2, [r3, #176] 142:Core/Src/main.c **** 1154 .loc 1 142 3 is_stmt 1 view .LVU443 1155 0022 0220 movs r0, #2 1156 0024 FFF7FEFF bl HAL_PWREx_ConfigSupply 1157 .LVL37: 146:Core/Src/main.c **** 1158 .loc 1 146 3 view .LVU444 1159 .LBB10: 146:Core/Src/main.c **** 1160 .loc 1 146 3 view .LVU445 1161 0028 0023 movs r3, #0 1162 002a 0093 str r3, [sp] 146:Core/Src/main.c **** 1163 .loc 1 146 3 view .LVU446 1164 002c 1F4B ldr r3, .L64+4 1165 002e 9A69 ldr r2, [r3, #24] 1166 0030 22F44042 bic r2, r2, #49152 1167 0034 9A61 str r2, [r3, #24] 146:Core/Src/main.c **** 1168 .loc 1 146 3 view .LVU447 1169 0036 9B69 ldr r3, [r3, #24] 1170 0038 03F44043 and r3, r3, #49152 1171 003c 0093 str r3, [sp] 146:Core/Src/main.c **** 1172 .loc 1 146 3 view .LVU448 1173 003e 009B ldr r3, [sp] 1174 .LBE10: 146:Core/Src/main.c **** 1175 .loc 1 146 3 view .LVU449 148:Core/Src/main.c **** 1176 .loc 1 148 3 view .LVU450 1177 .L58: 148:Core/Src/main.c **** 1178 .loc 1 148 48 discriminator 1 view .LVU451 148:Core/Src/main.c **** 1179 .loc 1 148 9 discriminator 1 view .LVU452 148:Core/Src/main.c **** 1180 .loc 1 148 10 is_stmt 0 discriminator 1 view .LVU453 1181 0040 1A4B ldr r3, .L64+4 1182 0042 9B69 ldr r3, [r3, #24] 148:Core/Src/main.c **** 1183 .loc 1 148 9 discriminator 1 view .LVU454 1184 0044 13F4005F tst r3, #8192 ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 43 1185 0048 FAD0 beq .L58 153:Core/Src/main.c **** RCC_OscInitStruct.HSEState = RCC_HSE_ON; 1186 .loc 1 153 3 is_stmt 1 view .LVU455 153:Core/Src/main.c **** RCC_OscInitStruct.HSEState = RCC_HSE_ON; 1187 .loc 1 153 36 is_stmt 0 view .LVU456 1188 004a 0122 movs r2, #1 1189 004c 0992 str r2, [sp, #36] 154:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 1190 .loc 1 154 3 is_stmt 1 view .LVU457 154:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 1191 .loc 1 154 30 is_stmt 0 view .LVU458 1192 004e 4FF48033 mov r3, #65536 1193 0052 0A93 str r3, [sp, #40] 155:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 1194 .loc 1 155 3 is_stmt 1 view .LVU459 155:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 1195 .loc 1 155 34 is_stmt 0 view .LVU460 1196 0054 0223 movs r3, #2 1197 0056 1293 str r3, [sp, #72] 156:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLM = 1; 1198 .loc 1 156 3 is_stmt 1 view .LVU461 156:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLM = 1; 1199 .loc 1 156 35 is_stmt 0 view .LVU462 1200 0058 1393 str r3, [sp, #76] 157:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 8; 1201 .loc 1 157 3 is_stmt 1 view .LVU463 157:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 8; 1202 .loc 1 157 30 is_stmt 0 view .LVU464 1203 005a 1492 str r2, [sp, #80] 158:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLP = 2; 1204 .loc 1 158 3 is_stmt 1 view .LVU465 158:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLP = 2; 1205 .loc 1 158 30 is_stmt 0 view .LVU466 1206 005c 0822 movs r2, #8 1207 005e 1592 str r2, [sp, #84] 159:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = 2; 1208 .loc 1 159 3 is_stmt 1 view .LVU467 159:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = 2; 1209 .loc 1 159 30 is_stmt 0 view .LVU468 1210 0060 1693 str r3, [sp, #88] 160:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLR = 2; 1211 .loc 1 160 3 is_stmt 1 view .LVU469 160:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLR = 2; 1212 .loc 1 160 30 is_stmt 0 view .LVU470 1213 0062 1793 str r3, [sp, #92] 161:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3; 1214 .loc 1 161 3 is_stmt 1 view .LVU471 161:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3; 1215 .loc 1 161 30 is_stmt 0 view .LVU472 1216 0064 1893 str r3, [sp, #96] 162:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; 1217 .loc 1 162 3 is_stmt 1 view .LVU473 162:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; 1218 .loc 1 162 32 is_stmt 0 view .LVU474 1219 0066 0C23 movs r3, #12 1220 0068 1993 str r3, [sp, #100] 163:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLFRACN = 0; ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 44 1221 .loc 1 163 3 is_stmt 1 view .LVU475 163:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLFRACN = 0; 1222 .loc 1 163 35 is_stmt 0 view .LVU476 1223 006a 0023 movs r3, #0 1224 006c 1A93 str r3, [sp, #104] 164:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 1225 .loc 1 164 3 is_stmt 1 view .LVU477 164:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 1226 .loc 1 164 34 is_stmt 0 view .LVU478 1227 006e 1B93 str r3, [sp, #108] 165:Core/Src/main.c **** { 1228 .loc 1 165 3 is_stmt 1 view .LVU479 165:Core/Src/main.c **** { 1229 .loc 1 165 7 is_stmt 0 view .LVU480 1230 0070 09A8 add r0, sp, #36 1231 0072 FFF7FEFF bl HAL_RCC_OscConfig 1232 .LVL38: 165:Core/Src/main.c **** { 1233 .loc 1 165 6 discriminator 1 view .LVU481 1234 0076 90B9 cbnz r0, .L62 172:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 1235 .loc 1 172 3 is_stmt 1 view .LVU482 172:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 1236 .loc 1 172 31 is_stmt 0 view .LVU483 1237 0078 3F23 movs r3, #63 1238 007a 0193 str r3, [sp, #4] 175:Core/Src/main.c **** RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; 1239 .loc 1 175 3 is_stmt 1 view .LVU484 175:Core/Src/main.c **** RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; 1240 .loc 1 175 34 is_stmt 0 view .LVU485 1241 007c 0323 movs r3, #3 1242 007e 0293 str r3, [sp, #8] 176:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV1; 1243 .loc 1 176 3 is_stmt 1 view .LVU486 176:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV1; 1244 .loc 1 176 35 is_stmt 0 view .LVU487 1245 0080 0023 movs r3, #0 1246 0082 0393 str r3, [sp, #12] 177:Core/Src/main.c **** RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV1; 1247 .loc 1 177 3 is_stmt 1 view .LVU488 177:Core/Src/main.c **** RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV1; 1248 .loc 1 177 35 is_stmt 0 view .LVU489 1249 0084 0493 str r3, [sp, #16] 178:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV1; 1250 .loc 1 178 3 is_stmt 1 view .LVU490 178:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV1; 1251 .loc 1 178 36 is_stmt 0 view .LVU491 1252 0086 0593 str r3, [sp, #20] 179:Core/Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV1; 1253 .loc 1 179 3 is_stmt 1 view .LVU492 179:Core/Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV1; 1254 .loc 1 179 36 is_stmt 0 view .LVU493 1255 0088 0693 str r3, [sp, #24] 180:Core/Src/main.c **** RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV1; 1256 .loc 1 180 3 is_stmt 1 view .LVU494 180:Core/Src/main.c **** RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV1; 1257 .loc 1 180 36 is_stmt 0 view .LVU495 ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 45 1258 008a 0793 str r3, [sp, #28] 181:Core/Src/main.c **** 1259 .loc 1 181 3 is_stmt 1 view .LVU496 181:Core/Src/main.c **** 1260 .loc 1 181 36 is_stmt 0 view .LVU497 1261 008c 0893 str r3, [sp, #32] 183:Core/Src/main.c **** { 1262 .loc 1 183 3 is_stmt 1 view .LVU498 183:Core/Src/main.c **** { 1263 .loc 1 183 7 is_stmt 0 view .LVU499 1264 008e 0221 movs r1, #2 1265 0090 01A8 add r0, sp, #4 1266 0092 FFF7FEFF bl HAL_RCC_ClockConfig 1267 .LVL39: 183:Core/Src/main.c **** { 1268 .loc 1 183 6 discriminator 1 view .LVU500 1269 0096 20B9 cbnz r0, .L63 187:Core/Src/main.c **** 1270 .loc 1 187 1 view .LVU501 1271 0098 1DB0 add sp, sp, #116 1272 .cfi_remember_state 1273 .cfi_def_cfa_offset 4 1274 @ sp needed 1275 009a 5DF804FB ldr pc, [sp], #4 1276 .L62: 1277 .cfi_restore_state 167:Core/Src/main.c **** } 1278 .loc 1 167 5 is_stmt 1 view .LVU502 1279 009e FFF7FEFF bl Error_Handler 1280 .LVL40: 1281 .L63: 185:Core/Src/main.c **** } 1282 .loc 1 185 5 view .LVU503 1283 00a2 FFF7FEFF bl Error_Handler 1284 .LVL41: 1285 .L65: 1286 00a6 00BF .align 2 1287 .L64: 1288 00a8 00440258 .word 1476543488 1289 00ac 00480258 .word 1476544512 1290 .cfi_endproc 1291 .LFE336: 1293 .section .text.PeriphCommonClock_Config,"ax",%progbits 1294 .align 1 1295 .global PeriphCommonClock_Config 1296 .syntax unified 1297 .thumb 1298 .thumb_func 1300 PeriphCommonClock_Config: 1301 .LFB337: 194:Core/Src/main.c **** RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; 1302 .loc 1 194 1 view -0 1303 .cfi_startproc 1304 @ args = 0, pretend = 0, frame = 192 1305 @ frame_needed = 0, uses_anonymous_args = 0 1306 0000 30B5 push {r4, r5, lr} 1307 .cfi_def_cfa_offset 12 ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 46 1308 .cfi_offset 4, -12 1309 .cfi_offset 5, -8 1310 .cfi_offset 14, -4 1311 0002 B1B0 sub sp, sp, #196 1312 .cfi_def_cfa_offset 208 195:Core/Src/main.c **** 1313 .loc 1 195 3 view .LVU505 195:Core/Src/main.c **** 1314 .loc 1 195 28 is_stmt 0 view .LVU506 1315 0004 C025 movs r5, #192 1316 0006 2A46 mov r2, r5 1317 0008 0021 movs r1, #0 1318 000a 6846 mov r0, sp 1319 000c FFF7FEFF bl memset 1320 .LVL42: 199:Core/Src/main.c **** PeriphClkInitStruct.PLL2.PLL2M = 1; 1321 .loc 1 199 3 is_stmt 1 view .LVU507 199:Core/Src/main.c **** PeriphClkInitStruct.PLL2.PLL2M = 1; 1322 .loc 1 199 44 is_stmt 0 view .LVU508 1323 0010 4FF40822 mov r2, #557056 1324 0014 0023 movs r3, #0 1325 0016 CDE90023 strd r2, [sp] 200:Core/Src/main.c **** PeriphClkInitStruct.PLL2.PLL2N = 8; 1326 .loc 1 200 3 is_stmt 1 view .LVU509 200:Core/Src/main.c **** PeriphClkInitStruct.PLL2.PLL2N = 8; 1327 .loc 1 200 34 is_stmt 0 view .LVU510 1328 001a 0123 movs r3, #1 1329 001c 0293 str r3, [sp, #8] 201:Core/Src/main.c **** PeriphClkInitStruct.PLL2.PLL2P = 3; 1330 .loc 1 201 3 is_stmt 1 view .LVU511 201:Core/Src/main.c **** PeriphClkInitStruct.PLL2.PLL2P = 3; 1331 .loc 1 201 34 is_stmt 0 view .LVU512 1332 001e 0823 movs r3, #8 1333 0020 0393 str r3, [sp, #12] 202:Core/Src/main.c **** PeriphClkInitStruct.PLL2.PLL2Q = 3; 1334 .loc 1 202 3 is_stmt 1 view .LVU513 202:Core/Src/main.c **** PeriphClkInitStruct.PLL2.PLL2Q = 3; 1335 .loc 1 202 34 is_stmt 0 view .LVU514 1336 0022 0323 movs r3, #3 1337 0024 0493 str r3, [sp, #16] 203:Core/Src/main.c **** PeriphClkInitStruct.PLL2.PLL2R = 2; 1338 .loc 1 203 3 is_stmt 1 view .LVU515 203:Core/Src/main.c **** PeriphClkInitStruct.PLL2.PLL2R = 2; 1339 .loc 1 203 34 is_stmt 0 view .LVU516 1340 0026 0593 str r3, [sp, #20] 204:Core/Src/main.c **** PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_3; 1341 .loc 1 204 3 is_stmt 1 view .LVU517 204:Core/Src/main.c **** PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_3; 1342 .loc 1 204 34 is_stmt 0 view .LVU518 1343 0028 0223 movs r3, #2 1344 002a 0693 str r3, [sp, #24] 205:Core/Src/main.c **** PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE; 1345 .loc 1 205 3 is_stmt 1 view .LVU519 205:Core/Src/main.c **** PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE; 1346 .loc 1 205 36 is_stmt 0 view .LVU520 1347 002c 0795 str r5, [sp, #28] 206:Core/Src/main.c **** PeriphClkInitStruct.PLL2.PLL2FRACN = 0; ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 47 1348 .loc 1 206 3 is_stmt 1 view .LVU521 207:Core/Src/main.c **** PeriphClkInitStruct.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL2; 1349 .loc 1 207 3 view .LVU522 208:Core/Src/main.c **** PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLL2; 1350 .loc 1 208 3 view .LVU523 208:Core/Src/main.c **** PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLL2; 1351 .loc 1 208 43 is_stmt 0 view .LVU524 1352 002e 4FF00053 mov r3, #536870912 1353 0032 1E93 str r3, [sp, #120] 209:Core/Src/main.c **** if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) 1354 .loc 1 209 3 is_stmt 1 view .LVU525 210:Core/Src/main.c **** { 1355 .loc 1 210 3 view .LVU526 210:Core/Src/main.c **** { 1356 .loc 1 210 7 is_stmt 0 view .LVU527 1357 0034 6846 mov r0, sp 1358 0036 FFF7FEFF bl HAL_RCCEx_PeriphCLKConfig 1359 .LVL43: 210:Core/Src/main.c **** { 1360 .loc 1 210 6 discriminator 1 view .LVU528 1361 003a 08B9 cbnz r0, .L69 214:Core/Src/main.c **** 1362 .loc 1 214 1 view .LVU529 1363 003c 31B0 add sp, sp, #196 1364 .cfi_remember_state 1365 .cfi_def_cfa_offset 12 1366 @ sp needed 1367 003e 30BD pop {r4, r5, pc} 1368 .L69: 1369 .cfi_restore_state 212:Core/Src/main.c **** } 1370 .loc 1 212 5 is_stmt 1 view .LVU530 1371 0040 FFF7FEFF bl Error_Handler 1372 .LVL44: 1373 .cfi_endproc 1374 .LFE337: 1376 .section .text.main,"ax",%progbits 1377 .align 1 1378 .global main 1379 .syntax unified 1380 .thumb 1381 .thumb_func 1383 main: 1384 .LFB335: 81:Core/Src/main.c **** /* USER CODE BEGIN 1 */ 1385 .loc 1 81 1 view -0 1386 .cfi_startproc 1387 @ Volatile: function does not return. 1388 @ args = 0, pretend = 0, frame = 0 1389 @ frame_needed = 0, uses_anonymous_args = 0 1390 0000 08B5 push {r3, lr} 1391 .cfi_def_cfa_offset 8 1392 .cfi_offset 3, -8 1393 .cfi_offset 14, -4 89:Core/Src/main.c **** 1394 .loc 1 89 3 view .LVU532 1395 0002 FFF7FEFF bl HAL_Init ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 48 1396 .LVL45: 96:Core/Src/main.c **** 1397 .loc 1 96 3 view .LVU533 1398 0006 FFF7FEFF bl SystemClock_Config 1399 .LVL46: 99:Core/Src/main.c **** 1400 .loc 1 99 3 view .LVU534 1401 000a FFF7FEFF bl PeriphCommonClock_Config 1402 .LVL47: 106:Core/Src/main.c **** MX_FDCAN1_Init(); 1403 .loc 1 106 3 view .LVU535 1404 000e FFF7FEFF bl MX_GPIO_Init 1405 .LVL48: 107:Core/Src/main.c **** MX_TIM15_Init(); 1406 .loc 1 107 3 view .LVU536 1407 0012 FFF7FEFF bl MX_FDCAN1_Init 1408 .LVL49: 108:Core/Src/main.c **** MX_SPI1_Init(); 1409 .loc 1 108 3 view .LVU537 1410 0016 FFF7FEFF bl MX_TIM15_Init 1411 .LVL50: 109:Core/Src/main.c **** MX_SPI2_Init(); 1412 .loc 1 109 3 view .LVU538 1413 001a FFF7FEFF bl MX_SPI1_Init 1414 .LVL51: 110:Core/Src/main.c **** MX_ADC1_Init(); 1415 .loc 1 110 3 view .LVU539 1416 001e FFF7FEFF bl MX_SPI2_Init 1417 .LVL52: 111:Core/Src/main.c **** MX_ADC2_Init(); 1418 .loc 1 111 3 view .LVU540 1419 0022 FFF7FEFF bl MX_ADC1_Init 1420 .LVL53: 112:Core/Src/main.c **** /* USER CODE BEGIN 2 */ 1421 .loc 1 112 3 view .LVU541 1422 0026 FFF7FEFF bl MX_ADC2_Init 1423 .LVL54: 1424 .L71: 119:Core/Src/main.c **** { 1425 .loc 1 119 3 view .LVU542 124:Core/Src/main.c **** /* USER CODE END 3 */ 1426 .loc 1 124 3 view .LVU543 119:Core/Src/main.c **** { 1427 .loc 1 119 9 view .LVU544 1428 002a FEE7 b .L71 1429 .cfi_endproc 1430 .LFE335: 1432 .global htim15 1433 .section .bss.htim15,"aw",%nobits 1434 .align 2 1437 htim15: 1438 0000 00000000 .space 76 1438 00000000 1438 00000000 1438 00000000 1438 00000000 1439 .global hspi2 ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 49 1440 .section .bss.hspi2,"aw",%nobits 1441 .align 2 1444 hspi2: 1445 0000 00000000 .space 136 1445 00000000 1445 00000000 1445 00000000 1445 00000000 1446 .global hspi1 1447 .section .bss.hspi1,"aw",%nobits 1448 .align 2 1451 hspi1: 1452 0000 00000000 .space 136 1452 00000000 1452 00000000 1452 00000000 1452 00000000 1453 .global hfdcan1 1454 .section .bss.hfdcan1,"aw",%nobits 1455 .align 2 1458 hfdcan1: 1459 0000 00000000 .space 160 1459 00000000 1459 00000000 1459 00000000 1459 00000000 1460 .global hadc2 1461 .section .bss.hadc2,"aw",%nobits 1462 .align 2 1465 hadc2: 1466 0000 00000000 .space 100 1466 00000000 1466 00000000 1466 00000000 1466 00000000 1467 .global hadc1 1468 .section .bss.hadc1,"aw",%nobits 1469 .align 2 1472 hadc1: 1473 0000 00000000 .space 100 1473 00000000 1473 00000000 1473 00000000 1473 00000000 1474 .text 1475 .Letext0: 1476 .file 3 "C:/Users/lenex/AppData/Roaming/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-to 1477 .file 4 "C:/Users/lenex/AppData/Roaming/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-to 1478 .file 5 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7a3xx.h" 1479 .file 6 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h" 1480 .file 7 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h" 1481 .file 8 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h" 1482 .file 9 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h" 1483 .file 10 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h" 1484 .file 11 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h" 1485 .file 12 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h" 1486 .file 13 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h" ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 50 1487 .file 14 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h" 1488 .file 15 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_spi.h" 1489 .file 16 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h" 1490 .file 17 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h" 1491 .file 18 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h" 1492 .file 19 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h" 1493 .file 20 "" ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 51 DEFINED SYMBOLS *ABS*:00000000 main.c C:\Users\lenex\AppData\Local\Temp\ccDm094H.s:20 .text.MX_GPIO_Init:00000000 $t C:\Users\lenex\AppData\Local\Temp\ccDm094H.s:25 .text.MX_GPIO_Init:00000000 MX_GPIO_Init C:\Users\lenex\AppData\Local\Temp\ccDm094H.s:241 .text.MX_GPIO_Init:0000011c $d C:\Users\lenex\AppData\Local\Temp\ccDm094H.s:249 .text.Error_Handler:00000000 $t C:\Users\lenex\AppData\Local\Temp\ccDm094H.s:255 .text.Error_Handler:00000000 Error_Handler C:\Users\lenex\AppData\Local\Temp\ccDm094H.s:287 .text.MX_FDCAN1_Init:00000000 $t C:\Users\lenex\AppData\Local\Temp\ccDm094H.s:292 .text.MX_FDCAN1_Init:00000000 MX_FDCAN1_Init C:\Users\lenex\AppData\Local\Temp\ccDm094H.s:411 .text.MX_FDCAN1_Init:0000005c $d C:\Users\lenex\AppData\Local\Temp\ccDm094H.s:1458 .bss.hfdcan1:00000000 hfdcan1 C:\Users\lenex\AppData\Local\Temp\ccDm094H.s:417 .text.MX_TIM15_Init:00000000 $t C:\Users\lenex\AppData\Local\Temp\ccDm094H.s:422 .text.MX_TIM15_Init:00000000 MX_TIM15_Init C:\Users\lenex\AppData\Local\Temp\ccDm094H.s:593 .text.MX_TIM15_Init:000000ac $d C:\Users\lenex\AppData\Local\Temp\ccDm094H.s:1437 .bss.htim15:00000000 htim15 C:\Users\lenex\AppData\Local\Temp\ccDm094H.s:599 .text.MX_SPI1_Init:00000000 $t C:\Users\lenex\AppData\Local\Temp\ccDm094H.s:604 .text.MX_SPI1_Init:00000000 MX_SPI1_Init C:\Users\lenex\AppData\Local\Temp\ccDm094H.s:702 .text.MX_SPI1_Init:00000050 $d C:\Users\lenex\AppData\Local\Temp\ccDm094H.s:1451 .bss.hspi1:00000000 hspi1 C:\Users\lenex\AppData\Local\Temp\ccDm094H.s:708 .text.MX_SPI2_Init:00000000 $t C:\Users\lenex\AppData\Local\Temp\ccDm094H.s:713 .text.MX_SPI2_Init:00000000 MX_SPI2_Init C:\Users\lenex\AppData\Local\Temp\ccDm094H.s:810 .text.MX_SPI2_Init:0000004c $d C:\Users\lenex\AppData\Local\Temp\ccDm094H.s:1444 .bss.hspi2:00000000 hspi2 C:\Users\lenex\AppData\Local\Temp\ccDm094H.s:816 .text.MX_ADC1_Init:00000000 $t C:\Users\lenex\AppData\Local\Temp\ccDm094H.s:821 .text.MX_ADC1_Init:00000000 MX_ADC1_Init C:\Users\lenex\AppData\Local\Temp\ccDm094H.s:970 .text.MX_ADC1_Init:00000090 $d C:\Users\lenex\AppData\Local\Temp\ccDm094H.s:1472 .bss.hadc1:00000000 hadc1 C:\Users\lenex\AppData\Local\Temp\ccDm094H.s:977 .text.MX_ADC2_Init:00000000 $t C:\Users\lenex\AppData\Local\Temp\ccDm094H.s:982 .text.MX_ADC2_Init:00000000 MX_ADC2_Init C:\Users\lenex\AppData\Local\Temp\ccDm094H.s:1110 .text.MX_ADC2_Init:00000078 $d C:\Users\lenex\AppData\Local\Temp\ccDm094H.s:1465 .bss.hadc2:00000000 hadc2 C:\Users\lenex\AppData\Local\Temp\ccDm094H.s:1118 .text.SystemClock_Config:00000000 $t C:\Users\lenex\AppData\Local\Temp\ccDm094H.s:1124 .text.SystemClock_Config:00000000 SystemClock_Config C:\Users\lenex\AppData\Local\Temp\ccDm094H.s:1288 .text.SystemClock_Config:000000a8 $d C:\Users\lenex\AppData\Local\Temp\ccDm094H.s:1294 .text.PeriphCommonClock_Config:00000000 $t C:\Users\lenex\AppData\Local\Temp\ccDm094H.s:1300 .text.PeriphCommonClock_Config:00000000 PeriphCommonClock_Config C:\Users\lenex\AppData\Local\Temp\ccDm094H.s:1377 .text.main:00000000 $t C:\Users\lenex\AppData\Local\Temp\ccDm094H.s:1383 .text.main:00000000 main C:\Users\lenex\AppData\Local\Temp\ccDm094H.s:1434 .bss.htim15:00000000 $d C:\Users\lenex\AppData\Local\Temp\ccDm094H.s:1441 .bss.hspi2:00000000 $d C:\Users\lenex\AppData\Local\Temp\ccDm094H.s:1448 .bss.hspi1:00000000 $d C:\Users\lenex\AppData\Local\Temp\ccDm094H.s:1455 .bss.hfdcan1:00000000 $d C:\Users\lenex\AppData\Local\Temp\ccDm094H.s:1462 .bss.hadc2:00000000 $d C:\Users\lenex\AppData\Local\Temp\ccDm094H.s:1469 .bss.hadc1:00000000 $d UNDEFINED SYMBOLS HAL_GPIO_WritePin HAL_GPIO_Init HAL_FDCAN_Init HAL_TIM_IC_Init HAL_TIM_SlaveConfigSynchro HAL_TIM_IC_ConfigChannel HAL_TIMEx_MasterConfigSynchronization HAL_SPI_Init HAL_ADC_Init HAL_ADCEx_MultiModeConfigChannel HAL_ADC_ConfigChannel ARM GAS C:\Users\lenex\AppData\Local\Temp\ccDm094H.s page 52 memset HAL_PWREx_ConfigSupply HAL_RCC_OscConfig HAL_RCC_ClockConfig HAL_RCCEx_PeriphCLKConfig HAL_Init