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updated build

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This commit is contained in:
Moritz Ruffer 2025-03-26 18:59:27 +01:00
parent 1f163bb8b0
commit e5cb622b0d
104 changed files with 204086 additions and 156355 deletions
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78
AMS_Master_Code/Core/Inc/main.h
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@ -57,28 +57,62 @@ void Error_Handler(void);
/* USER CODE END EFP */ /* USER CODE END EFP */
/* Private defines -----------------------------------------------------------*/ /* Private defines -----------------------------------------------------------*/
#define B1_Pin GPIO_PIN_13 #define LV_I_measure_Pin GPIO_PIN_0
#define B1_GPIO_Port GPIOC #define LV_I_measure_GPIO_Port GPIOC
#define OSC32_IN_Pin GPIO_PIN_14 #define TEMP_TSDCDC_Pin GPIO_PIN_1
#define OSC32_IN_GPIO_Port GPIOC #define TEMP_TSDCDC_GPIO_Port GPIOC
#define OSC32_OUT_Pin GPIO_PIN_15 #define STATUS_LED_B_Pin GPIO_PIN_2
#define OSC32_OUT_GPIO_Port GPIOC #define STATUS_LED_B_GPIO_Port GPIOC
#define PH0_MCU_Pin GPIO_PIN_0 #define TS_ERROR_Pin GPIO_PIN_0
#define PH0_MCU_GPIO_Port GPIOH #define TS_ERROR_GPIO_Port GPIOA
#define PH1_MCU_Pin GPIO_PIN_1 #define HV_ACTIVE_Pin GPIO_PIN_1
#define PH1_MCU_GPIO_Port GPIOH #define HV_ACTIVE_GPIO_Port GPIOA
#define LD1_Pin GPIO_PIN_0 #define IMD_M_Pin GPIO_PIN_2
#define LD1_GPIO_Port GPIOB #define IMD_M_GPIO_Port GPIOA
#define LD3_Pin GPIO_PIN_14 #define IMD_OK_Pin GPIO_PIN_3
#define LD3_GPIO_Port GPIOB #define IMD_OK_GPIO_Port GPIOA
#define STLINK_RX_Pin GPIO_PIN_8 #define AMS_CS_Pin GPIO_PIN_4
#define STLINK_RX_GPIO_Port GPIOD #define AMS_CS_GPIO_Port GPIOA
#define STLINK_TX_Pin GPIO_PIN_9 #define NEG_AIR_CLOSED_Pin GPIO_PIN_6
#define STLINK_TX_GPIO_Port GPIOD #define NEG_AIR_CLOSED_GPIO_Port GPIOA
#define AMS_CS_Pin GPIO_PIN_14 #define POS_AIR_CLOSED_Pin GPIO_PIN_7
#define AMS_CS_GPIO_Port GPIOD #define POS_AIR_CLOSED_GPIO_Port GPIOA
#define LD2_Pin GPIO_PIN_1 #define MSTR1_Pin GPIO_PIN_4
#define LD2_GPIO_Port GPIOE #define MSTR1_GPIO_Port GPIOC
#define MSTR2_Pin GPIO_PIN_5
#define MSTR2_GPIO_Port GPIOC
#define PRE_and_AIR__open_Pin GPIO_PIN_0
#define PRE_and_AIR__open_GPIO_Port GPIOB
#define SDC_VOLTAGE_Pin GPIO_PIN_1
#define SDC_VOLTAGE_GPIO_Port GPIOB
#define IMD_POWER_Pin GPIO_PIN_2
#define IMD_POWER_GPIO_Port GPIOB
#define IMD_ERROR_LED_Pin GPIO_PIN_10
#define IMD_ERROR_LED_GPIO_Port GPIOB
#define AMS_ERROR_LED_Pin GPIO_PIN_13
#define AMS_ERROR_LED_GPIO_Port GPIOB
#define STATUS_LED_R_Pin GPIO_PIN_15
#define STATUS_LED_R_GPIO_Port GPIOB
#define POS_AIR_CTRL_Pin GPIO_PIN_6
#define POS_AIR_CTRL_GPIO_Port GPIOC
#define NEG_AIR_CTRL_Pin GPIO_PIN_7
#define NEG_AIR_CTRL_GPIO_Port GPIOC
#define TSAL_GREEN_Pin GPIO_PIN_9
#define TSAL_GREEN_GPIO_Port GPIOC
#define PRECHARGE_CTRL_Pin GPIO_PIN_8
#define PRECHARGE_CTRL_GPIO_Port GPIOA
#define INTR1_Pin GPIO_PIN_9
#define INTR1_GPIO_Port GPIOA
#define WAKE1_Pin GPIO_PIN_10
#define WAKE1_GPIO_Port GPIOA
#define AMS_NERROR_Pin GPIO_PIN_11
#define AMS_NERROR_GPIO_Port GPIOA
#define STATUS_LED_G_Pin GPIO_PIN_15
#define STATUS_LED_G_GPIO_Port GPIOA
#define INTR2_Pin GPIO_PIN_6
#define INTR2_GPIO_Port GPIOB
#define WAKE2_Pin GPIO_PIN_7
#define WAKE2_GPIO_Port GPIOB
/* USER CODE BEGIN Private defines */ /* USER CODE BEGIN Private defines */

11
AMS_Master_Code/Core/Inc/stm32h7xx_hal_conf.h
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@ -34,8 +34,8 @@
*/ */
#define HAL_MODULE_ENABLED #define HAL_MODULE_ENABLED
/* #define HAL_ADC_MODULE_ENABLED */ #define HAL_ADC_MODULE_ENABLED
/* #define HAL_FDCAN_MODULE_ENABLED */ #define HAL_FDCAN_MODULE_ENABLED
/* #define HAL_FMAC_MODULE_ENABLED */ /* #define HAL_FMAC_MODULE_ENABLED */
/* #define HAL_CEC_MODULE_ENABLED */ /* #define HAL_CEC_MODULE_ENABLED */
/* #define HAL_COMP_MODULE_ENABLED */ /* #define HAL_COMP_MODULE_ENABLED */
@ -59,6 +59,7 @@
/* #define HAL_JPEG_MODULE_ENABLED */ /* #define HAL_JPEG_MODULE_ENABLED */
/* #define HAL_OPAMP_MODULE_ENABLED */ /* #define HAL_OPAMP_MODULE_ENABLED */
/* #define HAL_OSPI_MODULE_ENABLED */ /* #define HAL_OSPI_MODULE_ENABLED */
/* #define HAL_OSPI_MODULE_ENABLED */
/* #define HAL_I2S_MODULE_ENABLED */ /* #define HAL_I2S_MODULE_ENABLED */
/* #define HAL_SMBUS_MODULE_ENABLED */ /* #define HAL_SMBUS_MODULE_ENABLED */
/* #define HAL_IWDG_MODULE_ENABLED */ /* #define HAL_IWDG_MODULE_ENABLED */
@ -74,7 +75,7 @@
/* #define HAL_SPDIFRX_MODULE_ENABLED */ /* #define HAL_SPDIFRX_MODULE_ENABLED */
#define HAL_SPI_MODULE_ENABLED #define HAL_SPI_MODULE_ENABLED
/* #define HAL_SWPMI_MODULE_ENABLED */ /* #define HAL_SWPMI_MODULE_ENABLED */
/* #define HAL_TIM_MODULE_ENABLED */ #define HAL_TIM_MODULE_ENABLED
/* #define HAL_UART_MODULE_ENABLED */ /* #define HAL_UART_MODULE_ENABLED */
/* #define HAL_USART_MODULE_ENABLED */ /* #define HAL_USART_MODULE_ENABLED */
/* #define HAL_IRDA_MODULE_ENABLED */ /* #define HAL_IRDA_MODULE_ENABLED */
@ -106,7 +107,7 @@
* (when HSE is used as system clock source, directly or through the PLL). * (when HSE is used as system clock source, directly or through the PLL).
*/ */
#if !defined (HSE_VALUE) #if !defined (HSE_VALUE)
#define HSE_VALUE (8000000UL) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */ #define HSE_VALUE (16000000UL) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */
#endif /* HSE_VALUE */ #endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT) #if !defined (HSE_STARTUP_TIMEOUT)
@ -165,7 +166,7 @@
* @brief This is the HAL system configuration section * @brief This is the HAL system configuration section
*/ */
#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */ #define VDD_VALUE (3300UL) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY (0UL) /*!< tick interrupt priority */ #define TICK_INT_PRIORITY (15UL) /*!< tick interrupt priority */
#define USE_RTOS 0 #define USE_RTOS 0
#define USE_SD_TRANSCEIVER 0U /*!< use uSD Transceiver */ #define USE_SD_TRANSCEIVER 0U /*!< use uSD Transceiver */
#define USE_SPI_CRC 0U /*!< use CRC in SPI */ #define USE_SPI_CRC 0U /*!< use CRC in SPI */

1
AMS_Master_Code/Core/Inc/stm32h7xx_it.h
View File

@ -55,6 +55,7 @@ void SVC_Handler(void);
void DebugMon_Handler(void); void DebugMon_Handler(void);
void PendSV_Handler(void); void PendSV_Handler(void);
void SysTick_Handler(void); void SysTick_Handler(void);
void FDCAN1_IT0_IRQHandler(void);
/* USER CODE BEGIN EFP */ /* USER CODE BEGIN EFP */
/* USER CODE END EFP */ /* USER CODE END EFP */

2
AMS_Master_Code/Core/Lib/ADBMS6830B_Driver/Core/Src/ADBMS_HighLevel.c
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@ -36,6 +36,8 @@ struct pollingTimes pollingTimes = {0, 0};
static constexpr ADBMS_DetailedStatus NO_ERROR = {ADBMS_NO_ERROR}; static constexpr ADBMS_DetailedStatus NO_ERROR = {ADBMS_NO_ERROR};
ADBMS_DetailedStatus AMS_Init(SPI_HandleTypeDef* hspi) { ADBMS_DetailedStatus AMS_Init(SPI_HandleTypeDef* hspi) {
// pull MSTR High for Microcontroller mode ADBMS6822
HAL_GPIO_WritePin(MSTR1_GPIO_Port, MSTR1_Pin, GPIO_PIN_SET);
debug_log(LOG_LEVEL_INFO, "ADBMS6830B HAL - configured for %d controllers and %d cells per controller...", N_BMS, debug_log(LOG_LEVEL_INFO, "ADBMS6830B HAL - configured for %d controllers and %d cells per controller...", N_BMS,
numberofCells); numberofCells);
if (initAMS(hspi) != HAL_OK) { if (initAMS(hspi) != HAL_OK) {

461
AMS_Master_Code/Core/Src/main.c
View File

@ -44,8 +44,15 @@
/* USER CODE END PM */ /* USER CODE END PM */
/* Private variables ---------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/
ADC_HandleTypeDef hadc1;
ADC_HandleTypeDef hadc2;
FDCAN_HandleTypeDef hfdcan1;
SPI_HandleTypeDef hspi1; SPI_HandleTypeDef hspi1;
SPI_HandleTypeDef hspi2;
TIM_HandleTypeDef htim15;
/* USER CODE BEGIN PV */ /* USER CODE BEGIN PV */
@ -53,9 +60,14 @@ SPI_HandleTypeDef hspi1;
/* Private function prototypes -----------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/
void SystemClock_Config(void); void SystemClock_Config(void);
static void MPU_Config(void); void PeriphCommonClock_Config(void);
static void MX_GPIO_Init(void); static void MX_GPIO_Init(void);
static void MX_FDCAN1_Init(void);
static void MX_TIM15_Init(void);
static void MX_SPI1_Init(void); static void MX_SPI1_Init(void);
static void MX_SPI2_Init(void);
static void MX_ADC1_Init(void);
static void MX_ADC2_Init(void);
/* USER CODE BEGIN PFP */ /* USER CODE BEGIN PFP */
/* USER CODE END PFP */ /* USER CODE END PFP */
@ -71,14 +83,10 @@ uint32_t volatile logging_mask = 0b11111; // no LOG_LEVEL_NOISY
*/ */
int main(void) int main(void)
{ {
/* USER CODE BEGIN 1 */ /* USER CODE BEGIN 1 */
/* USER CODE END 1 */ /* USER CODE END 1 */
/* MPU Configuration--------------------------------------------------------*/
MPU_Config();
/* MCU Configuration--------------------------------------------------------*/ /* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
@ -91,13 +99,21 @@ int main(void)
/* Configure the system clock */ /* Configure the system clock */
SystemClock_Config(); SystemClock_Config();
/* Configure the peripherals common clocks */
PeriphCommonClock_Config();
/* USER CODE BEGIN SysInit */ /* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */ /* USER CODE END SysInit */
/* Initialize all configured peripherals */ /* Initialize all configured peripherals */
MX_GPIO_Init(); MX_GPIO_Init();
MX_FDCAN1_Init();
MX_TIM15_Init();
MX_SPI1_Init(); MX_SPI1_Init();
MX_SPI2_Init();
MX_ADC1_Init();
MX_ADC2_Init();
/* USER CODE BEGIN 2 */ /* USER CODE BEGIN 2 */
debug_clear_console(); debug_clear_console();
debug_log(LOG_LEVEL_INFO, "AMS_Master on %s (%s), compiled at %s", COMMIT_BRANCH, COMMIT_HASH, COMPILE_DATE); debug_log(LOG_LEVEL_INFO, "AMS_Master on %s (%s), compiled at %s", COMMIT_BRANCH, COMMIT_HASH, COMPILE_DATE);
@ -281,26 +297,25 @@ void SystemClock_Config(void)
/** Supply configuration update enable /** Supply configuration update enable
*/ */
HAL_PWREx_ConfigSupply(PWR_DIRECT_SMPS_SUPPLY); HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
/** Configure the main internal regulator output voltage /** Configure the main internal regulator output voltage
*/ */
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
/** Initializes the RCC Oscillators according to the specified parameters /** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure. * in the RCC_OscInitTypeDef structure.
*/ */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSIState = RCC_HSI_DIV1; RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.HSICalibrationValue = 64;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = 4; RCC_OscInitStruct.PLL.PLLM = 1;
RCC_OscInitStruct.PLL.PLLN = 8; RCC_OscInitStruct.PLL.PLLN = 8;
RCC_OscInitStruct.PLL.PLLP = 2; RCC_OscInitStruct.PLL.PLLP = 2;
RCC_OscInitStruct.PLL.PLLQ = 4; RCC_OscInitStruct.PLL.PLLQ = 2;
RCC_OscInitStruct.PLL.PLLR = 2; RCC_OscInitStruct.PLL.PLLR = 2;
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3; RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3;
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
@ -323,12 +338,219 @@ void SystemClock_Config(void)
RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV1; RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV1;
RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV1; RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV1;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
{ {
Error_Handler(); Error_Handler();
} }
} }
/**
* @brief Peripherals Common Clock Configuration
* @retval None
*/
void PeriphCommonClock_Config(void)
{
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
/** Initializes the peripherals clock
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADC|RCC_PERIPHCLK_FDCAN;
PeriphClkInitStruct.PLL2.PLL2M = 1;
PeriphClkInitStruct.PLL2.PLL2N = 8;
PeriphClkInitStruct.PLL2.PLL2P = 3;
PeriphClkInitStruct.PLL2.PLL2Q = 3;
PeriphClkInitStruct.PLL2.PLL2R = 2;
PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_3;
PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE;
PeriphClkInitStruct.PLL2.PLL2FRACN = 0;
PeriphClkInitStruct.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL2;
PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLL2;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
Error_Handler();
}
}
/**
* @brief ADC1 Initialization Function
* @param None
* @retval None
*/
static void MX_ADC1_Init(void)
{
/* USER CODE BEGIN ADC1_Init 0 */
/* USER CODE END ADC1_Init 0 */
ADC_MultiModeTypeDef multimode = {0};
ADC_ChannelConfTypeDef sConfig = {0};
/* USER CODE BEGIN ADC1_Init 1 */
/* USER CODE END ADC1_Init 1 */
/** Common config
*/
hadc1.Instance = ADC1;
hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1;
hadc1.Init.Resolution = ADC_RESOLUTION_16B;
hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
hadc1.Init.LowPowerAutoWait = DISABLE;
hadc1.Init.ContinuousConvMode = DISABLE;
hadc1.Init.NbrOfConversion = 1;
hadc1.Init.DiscontinuousConvMode = DISABLE;
hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
hadc1.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR;
hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED;
hadc1.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE;
hadc1.Init.OversamplingMode = DISABLE;
if (HAL_ADC_Init(&hadc1) != HAL_OK)
{
Error_Handler();
}
/** Configure the ADC multi-mode
*/
multimode.Mode = ADC_MODE_INDEPENDENT;
if (HAL_ADCEx_MultiModeConfigChannel(&hadc1, &multimode) != HAL_OK)
{
Error_Handler();
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_10;
sConfig.Rank = ADC_REGULAR_RANK_1;
sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
sConfig.SingleDiff = ADC_SINGLE_ENDED;
sConfig.OffsetNumber = ADC_OFFSET_NONE;
sConfig.Offset = 0;
sConfig.OffsetSignedSaturation = DISABLE;
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN ADC1_Init 2 */
/* USER CODE END ADC1_Init 2 */
}
/**
* @brief ADC2 Initialization Function
* @param None
* @retval None
*/
static void MX_ADC2_Init(void)
{
/* USER CODE BEGIN ADC2_Init 0 */
/* USER CODE END ADC2_Init 0 */
ADC_ChannelConfTypeDef sConfig = {0};
/* USER CODE BEGIN ADC2_Init 1 */
/* USER CODE END ADC2_Init 1 */
/** Common config
*/
hadc2.Instance = ADC2;
hadc2.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1;
hadc2.Init.Resolution = ADC_RESOLUTION_16B;
hadc2.Init.ScanConvMode = ADC_SCAN_DISABLE;
hadc2.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
hadc2.Init.LowPowerAutoWait = DISABLE;
hadc2.Init.ContinuousConvMode = DISABLE;
hadc2.Init.NbrOfConversion = 1;
hadc2.Init.DiscontinuousConvMode = DISABLE;
hadc2.Init.ExternalTrigConv = ADC_SOFTWARE_START;
hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
hadc2.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR;
hadc2.Init.Overrun = ADC_OVR_DATA_PRESERVED;
hadc2.Init.LeftBitShift = ADC_LEFTBITSHIFT_NONE;
hadc2.Init.OversamplingMode = DISABLE;
if (HAL_ADC_Init(&hadc2) != HAL_OK)
{
Error_Handler();
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_10;
sConfig.Rank = ADC_REGULAR_RANK_1;
sConfig.SamplingTime = ADC_SAMPLETIME_1CYCLE_5;
sConfig.SingleDiff = ADC_DIFFERENTIAL_ENDED;
sConfig.OffsetNumber = ADC_OFFSET_NONE;
sConfig.Offset = 0;
sConfig.OffsetSignedSaturation = DISABLE;
if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN ADC2_Init 2 */
/* USER CODE END ADC2_Init 2 */
}
/**
* @brief FDCAN1 Initialization Function
* @param None
* @retval None
*/
static void MX_FDCAN1_Init(void)
{
/* USER CODE BEGIN FDCAN1_Init 0 */
/* USER CODE END FDCAN1_Init 0 */
/* USER CODE BEGIN FDCAN1_Init 1 */
/* USER CODE END FDCAN1_Init 1 */
hfdcan1.Instance = FDCAN1;
hfdcan1.Init.FrameFormat = FDCAN_FRAME_CLASSIC;
hfdcan1.Init.Mode = FDCAN_MODE_NORMAL;
hfdcan1.Init.AutoRetransmission = DISABLE;
hfdcan1.Init.TransmitPause = DISABLE;
hfdcan1.Init.ProtocolException = DISABLE;
hfdcan1.Init.NominalPrescaler = 2;
hfdcan1.Init.NominalSyncJumpWidth = 1;
hfdcan1.Init.NominalTimeSeg1 = 31;
hfdcan1.Init.NominalTimeSeg2 = 8;
hfdcan1.Init.DataPrescaler = 1;
hfdcan1.Init.DataSyncJumpWidth = 1;
hfdcan1.Init.DataTimeSeg1 = 1;
hfdcan1.Init.DataTimeSeg2 = 1;
hfdcan1.Init.MessageRAMOffset = 0;
hfdcan1.Init.StdFiltersNbr = 32;
hfdcan1.Init.ExtFiltersNbr = 0;
hfdcan1.Init.RxFifo0ElmtsNbr = 16;
hfdcan1.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_8;
hfdcan1.Init.RxFifo1ElmtsNbr = 0;
hfdcan1.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_8;
hfdcan1.Init.RxBuffersNbr = 0;
hfdcan1.Init.RxBufferSize = FDCAN_DATA_BYTES_8;
hfdcan1.Init.TxEventsNbr = 0;
hfdcan1.Init.TxBuffersNbr = 0;
hfdcan1.Init.TxFifoQueueElmtsNbr = 32;
hfdcan1.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION;
hfdcan1.Init.TxElmtSize = FDCAN_DATA_BYTES_8;
if (HAL_FDCAN_Init(&hfdcan1) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN FDCAN1_Init 2 */
/* USER CODE END FDCAN1_Init 2 */
}
/** /**
* @brief SPI1 Initialization Function * @brief SPI1 Initialization Function
* @param None * @param None
@ -348,11 +570,11 @@ static void MX_SPI1_Init(void)
hspi1.Instance = SPI1; hspi1.Instance = SPI1;
hspi1.Init.Mode = SPI_MODE_MASTER; hspi1.Init.Mode = SPI_MODE_MASTER;
hspi1.Init.Direction = SPI_DIRECTION_2LINES; hspi1.Init.Direction = SPI_DIRECTION_2LINES;
hspi1.Init.DataSize = SPI_DATASIZE_8BIT; hspi1.Init.DataSize = SPI_DATASIZE_4BIT;
hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;
hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; hspi1.Init.CLKPhase = SPI_PHASE_1EDGE;
hspi1.Init.NSS = SPI_NSS_SOFT; hspi1.Init.NSS = SPI_NSS_HARD_OUTPUT;
hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_32; hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
hspi1.Init.TIMode = SPI_TIMODE_DISABLE; hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
@ -377,6 +599,119 @@ static void MX_SPI1_Init(void)
} }
/**
* @brief SPI2 Initialization Function
* @param None
* @retval None
*/
static void MX_SPI2_Init(void)
{
/* USER CODE BEGIN SPI2_Init 0 */
/* USER CODE END SPI2_Init 0 */
/* USER CODE BEGIN SPI2_Init 1 */
/* USER CODE END SPI2_Init 1 */
/* SPI2 parameter configuration*/
hspi2.Instance = SPI2;
hspi2.Init.Mode = SPI_MODE_MASTER;
hspi2.Init.Direction = SPI_DIRECTION_2LINES;
hspi2.Init.DataSize = SPI_DATASIZE_4BIT;
hspi2.Init.CLKPolarity = SPI_POLARITY_LOW;
hspi2.Init.CLKPhase = SPI_PHASE_1EDGE;
hspi2.Init.NSS = SPI_NSS_HARD_INPUT;
hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB;
hspi2.Init.TIMode = SPI_TIMODE_DISABLE;
hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
hspi2.Init.CRCPolynomial = 0x0;
hspi2.Init.NSSPMode = SPI_NSS_PULSE_ENABLE;
hspi2.Init.NSSPolarity = SPI_NSS_POLARITY_LOW;
hspi2.Init.FifoThreshold = SPI_FIFO_THRESHOLD_01DATA;
hspi2.Init.TxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN;
hspi2.Init.RxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN;
hspi2.Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE;
hspi2.Init.MasterInterDataIdleness = SPI_MASTER_INTERDATA_IDLENESS_00CYCLE;
hspi2.Init.MasterReceiverAutoSusp = SPI_MASTER_RX_AUTOSUSP_DISABLE;
hspi2.Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_DISABLE;
hspi2.Init.IOSwap = SPI_IO_SWAP_DISABLE;
if (HAL_SPI_Init(&hspi2) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN SPI2_Init 2 */
/* USER CODE END SPI2_Init 2 */
}
/**
* @brief TIM15 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM15_Init(void)
{
/* USER CODE BEGIN TIM15_Init 0 */
/* USER CODE END TIM15_Init 0 */
TIM_SlaveConfigTypeDef sSlaveConfig = {0};
TIM_IC_InitTypeDef sConfigIC = {0};
TIM_MasterConfigTypeDef sMasterConfig = {0};
/* USER CODE BEGIN TIM15_Init 1 */
/* USER CODE END TIM15_Init 1 */
htim15.Instance = TIM15;
htim15.Init.Prescaler = 16000-1;
htim15.Init.CounterMode = TIM_COUNTERMODE_UP;
htim15.Init.Period = 65535;
htim15.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
htim15.Init.RepetitionCounter = 0;
htim15.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
if (HAL_TIM_IC_Init(&htim15) != HAL_OK)
{
Error_Handler();
}
sSlaveConfig.SlaveMode = TIM_SLAVEMODE_RESET;
sSlaveConfig.InputTrigger = TIM_TS_TI1FP1;
sSlaveConfig.TriggerPolarity = TIM_INPUTCHANNELPOLARITY_RISING;
sSlaveConfig.TriggerPrescaler = TIM_ICPSC_DIV1;
sSlaveConfig.TriggerFilter = 0;
if (HAL_TIM_SlaveConfigSynchro(&htim15, &sSlaveConfig) != HAL_OK)
{
Error_Handler();
}
sConfigIC.ICPolarity = TIM_INPUTCHANNELPOLARITY_RISING;
sConfigIC.ICSelection = TIM_ICSELECTION_DIRECTTI;
sConfigIC.ICPrescaler = TIM_ICPSC_DIV1;
sConfigIC.ICFilter = 0;
if (HAL_TIM_IC_ConfigChannel(&htim15, &sConfigIC, TIM_CHANNEL_1) != HAL_OK)
{
Error_Handler();
}
sConfigIC.ICPolarity = TIM_INPUTCHANNELPOLARITY_FALLING;
sConfigIC.ICSelection = TIM_ICSELECTION_INDIRECTTI;
if (HAL_TIM_IC_ConfigChannel(&htim15, &sConfigIC, TIM_CHANNEL_2) != HAL_OK)
{
Error_Handler();
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
if (HAL_TIMEx_MasterConfigSynchronization(&htim15, &sMasterConfig) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN TIM15_Init 2 */
/* USER CODE END TIM15_Init 2 */
}
/** /**
* @brief GPIO Initialization Function * @brief GPIO Initialization Function
* @param None * @param None
@ -389,56 +724,65 @@ static void MX_GPIO_Init(void)
/* USER CODE END MX_GPIO_Init_1 */ /* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */ /* GPIO Ports Clock Enable */
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOH_CLK_ENABLE(); __HAL_RCC_GPIOH_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOD_CLK_ENABLE();
__HAL_RCC_GPIOE_CLK_ENABLE();
/*Configure GPIO pin Output Level */ /*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOB, LD1_Pin|LD3_Pin, GPIO_PIN_RESET); HAL_GPIO_WritePin(GPIOC, STATUS_LED_B_Pin|MSTR1_Pin|MSTR2_Pin|POS_AIR_CTRL_Pin
|NEG_AIR_CTRL_Pin, GPIO_PIN_RESET);
/*Configure GPIO pin Output Level */ /*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(AMS_CS_GPIO_Port, AMS_CS_Pin, GPIO_PIN_RESET); HAL_GPIO_WritePin(GPIOB, IMD_POWER_Pin|STATUS_LED_R_Pin, GPIO_PIN_RESET);
/*Configure GPIO pin Output Level */ /*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET); HAL_GPIO_WritePin(GPIOA, PRECHARGE_CTRL_Pin|AMS_NERROR_Pin|STATUS_LED_G_Pin, GPIO_PIN_RESET);
/*Configure GPIO pin : B1_Pin */ /*Configure GPIO pins : STATUS_LED_B_Pin MSTR1_Pin MSTR2_Pin POS_AIR_CTRL_Pin
GPIO_InitStruct.Pin = B1_Pin; NEG_AIR_CTRL_Pin */
GPIO_InitStruct.Pin = STATUS_LED_B_Pin|MSTR1_Pin|MSTR2_Pin|POS_AIR_CTRL_Pin
|NEG_AIR_CTRL_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
/*Configure GPIO pins : TS_ERROR_Pin HV_ACTIVE_Pin IMD_OK_Pin NEG_AIR_CLOSED_Pin
POS_AIR_CLOSED_Pin INTR1_Pin WAKE1_Pin */
GPIO_InitStruct.Pin = TS_ERROR_Pin|HV_ACTIVE_Pin|IMD_OK_Pin|NEG_AIR_CLOSED_Pin
|POS_AIR_CLOSED_Pin|INTR1_Pin|WAKE1_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT; GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct); HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/*Configure GPIO pins : LD1_Pin LD3_Pin */ /*Configure GPIO pins : PRE_and_AIR__open_Pin SDC_VOLTAGE_Pin IMD_ERROR_LED_Pin AMS_ERROR_LED_Pin
GPIO_InitStruct.Pin = LD1_Pin|LD3_Pin; INTR2_Pin WAKE2_Pin */
GPIO_InitStruct.Pin = PRE_and_AIR__open_Pin|SDC_VOLTAGE_Pin|IMD_ERROR_LED_Pin|AMS_ERROR_LED_Pin
|INTR2_Pin|WAKE2_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/*Configure GPIO pins : IMD_POWER_Pin STATUS_LED_R_Pin */
GPIO_InitStruct.Pin = IMD_POWER_Pin|STATUS_LED_R_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/*Configure GPIO pins : STLINK_RX_Pin STLINK_TX_Pin */ /*Configure GPIO pin : TSAL_GREEN_Pin */
GPIO_InitStruct.Pin = STLINK_RX_Pin|STLINK_TX_Pin; GPIO_InitStruct.Pin = TSAL_GREEN_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; HAL_GPIO_Init(TSAL_GREEN_GPIO_Port, &GPIO_InitStruct);
GPIO_InitStruct.Alternate = GPIO_AF7_USART3;
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
/*Configure GPIO pin : AMS_CS_Pin */ /*Configure GPIO pins : PRECHARGE_CTRL_Pin AMS_NERROR_Pin STATUS_LED_G_Pin */
GPIO_InitStruct.Pin = AMS_CS_Pin; GPIO_InitStruct.Pin = PRECHARGE_CTRL_Pin|AMS_NERROR_Pin|STATUS_LED_G_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(AMS_CS_GPIO_Port, &GPIO_InitStruct); HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/*Configure GPIO pin : LD2_Pin */
GPIO_InitStruct.Pin = LD2_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(LD2_GPIO_Port, &GPIO_InitStruct);
/* USER CODE BEGIN MX_GPIO_Init_2 */ /* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */ /* USER CODE END MX_GPIO_Init_2 */
@ -448,35 +792,6 @@ static void MX_GPIO_Init(void)
/* USER CODE END 4 */ /* USER CODE END 4 */
/* MPU Configuration */
void MPU_Config(void)
{
MPU_Region_InitTypeDef MPU_InitStruct = {0};
/* Disables the MPU */
HAL_MPU_Disable();
/** Initializes and configures the Region and the memory to be protected
*/
MPU_InitStruct.Enable = MPU_REGION_ENABLE;
MPU_InitStruct.Number = MPU_REGION_NUMBER0;
MPU_InitStruct.BaseAddress = 0x0;
MPU_InitStruct.Size = MPU_REGION_SIZE_4GB;
MPU_InitStruct.SubRegionDisable = 0x87;
MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;
MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS;
MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;
MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;
MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;
HAL_MPU_ConfigRegion(&MPU_InitStruct);
/* Enables the MPU */
HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);
}
/** /**
* @brief This function is executed in case of error occurrence. * @brief This function is executed in case of error occurrence.
* @retval None * @retval None

351
AMS_Master_Code/Core/Src/stm32h7xx_hal_msp.c
View File

@ -20,6 +20,7 @@
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "main.h" #include "main.h"
/* USER CODE BEGIN Includes */ /* USER CODE BEGIN Includes */
/* USER CODE END Includes */ /* USER CODE END Includes */
@ -62,7 +63,6 @@
*/ */
void HAL_MspInit(void) void HAL_MspInit(void)
{ {
/* USER CODE BEGIN MspInit 0 */ /* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */ /* USER CODE END MspInit 0 */
@ -76,6 +76,193 @@ void HAL_MspInit(void)
/* USER CODE END MspInit 1 */ /* USER CODE END MspInit 1 */
} }
static uint32_t HAL_RCC_ADC12_CLK_ENABLED=0;
/**
* @brief ADC MSP Initialization
* This function configures the hardware resources used in this example
* @param hadc: ADC handle pointer
* @retval None
*/
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
if(hadc->Instance==ADC1)
{
/* USER CODE BEGIN ADC1_MspInit 0 */
/* USER CODE END ADC1_MspInit 0 */
/* Peripheral clock enable */
HAL_RCC_ADC12_CLK_ENABLED++;
if(HAL_RCC_ADC12_CLK_ENABLED==1){
__HAL_RCC_ADC12_CLK_ENABLE();
}
__HAL_RCC_GPIOC_CLK_ENABLE();
/**ADC1 GPIO Configuration
PC0 ------> ADC1_INP10
*/
GPIO_InitStruct.Pin = LV_I_measure_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(LV_I_measure_GPIO_Port, &GPIO_InitStruct);
/* USER CODE BEGIN ADC1_MspInit 1 */
/* USER CODE END ADC1_MspInit 1 */
}
else if(hadc->Instance==ADC2)
{
/* USER CODE BEGIN ADC2_MspInit 0 */
/* USER CODE END ADC2_MspInit 0 */
/* Peripheral clock enable */
HAL_RCC_ADC12_CLK_ENABLED++;
if(HAL_RCC_ADC12_CLK_ENABLED==1){
__HAL_RCC_ADC12_CLK_ENABLE();
}
__HAL_RCC_GPIOC_CLK_ENABLE();
/**ADC2 GPIO Configuration
PC0 ------> ADC2_INP10
PC1 ------> ADC2_INP11
PC1 ------> ADC2_INN10
*/
GPIO_InitStruct.Pin = LV_I_measure_Pin|TEMP_TSDCDC_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
/* USER CODE BEGIN ADC2_MspInit 1 */
/* USER CODE END ADC2_MspInit 1 */
}
}
/**
* @brief ADC MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hadc: ADC handle pointer
* @retval None
*/
void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
{
if(hadc->Instance==ADC1)
{
/* USER CODE BEGIN ADC1_MspDeInit 0 */
/* USER CODE END ADC1_MspDeInit 0 */
/* Peripheral clock disable */
HAL_RCC_ADC12_CLK_ENABLED--;
if(HAL_RCC_ADC12_CLK_ENABLED==0){
__HAL_RCC_ADC12_CLK_DISABLE();
}
/**ADC1 GPIO Configuration
PC0 ------> ADC1_INP10
*/
HAL_GPIO_DeInit(LV_I_measure_GPIO_Port, LV_I_measure_Pin);
/* USER CODE BEGIN ADC1_MspDeInit 1 */
/* USER CODE END ADC1_MspDeInit 1 */
}
else if(hadc->Instance==ADC2)
{
/* USER CODE BEGIN ADC2_MspDeInit 0 */
/* USER CODE END ADC2_MspDeInit 0 */
/* Peripheral clock disable */
HAL_RCC_ADC12_CLK_ENABLED--;
if(HAL_RCC_ADC12_CLK_ENABLED==0){
__HAL_RCC_ADC12_CLK_DISABLE();
}
/**ADC2 GPIO Configuration
PC0 ------> ADC2_INP10
PC1 ------> ADC2_INP11
PC1 ------> ADC2_INN10
*/
HAL_GPIO_DeInit(GPIOC, LV_I_measure_Pin|TEMP_TSDCDC_Pin);
/* USER CODE BEGIN ADC2_MspDeInit 1 */
/* USER CODE END ADC2_MspDeInit 1 */
}
}
/**
* @brief FDCAN MSP Initialization
* This function configures the hardware resources used in this example
* @param hfdcan: FDCAN handle pointer
* @retval None
*/
void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef* hfdcan)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
if(hfdcan->Instance==FDCAN1)
{
/* USER CODE BEGIN FDCAN1_MspInit 0 */
/* USER CODE END FDCAN1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_FDCAN_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
/**FDCAN1 GPIO Configuration
PB8 ------> FDCAN1_RX
PB9 ------> FDCAN1_TX
*/
GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF9_FDCAN1;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/* FDCAN1 interrupt Init */
HAL_NVIC_SetPriority(FDCAN1_IT0_IRQn, 0, 0);
HAL_NVIC_EnableIRQ(FDCAN1_IT0_IRQn);
/* USER CODE BEGIN FDCAN1_MspInit 1 */
/* USER CODE END FDCAN1_MspInit 1 */
}
}
/**
* @brief FDCAN MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hfdcan: FDCAN handle pointer
* @retval None
*/
void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef* hfdcan)
{
if(hfdcan->Instance==FDCAN1)
{
/* USER CODE BEGIN FDCAN1_MspDeInit 0 */
/* USER CODE END FDCAN1_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_FDCAN_CLK_DISABLE();
/**FDCAN1 GPIO Configuration
PB8 ------> FDCAN1_RX
PB9 ------> FDCAN1_TX
*/
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_8|GPIO_PIN_9);
/* FDCAN1 interrupt DeInit */
HAL_NVIC_DisableIRQ(FDCAN1_IT0_IRQn);
/* USER CODE BEGIN FDCAN1_MspDeInit 1 */
/* USER CODE END FDCAN1_MspDeInit 1 */
}
}
/** /**
* @brief SPI MSP Initialization * @brief SPI MSP Initialization
* This function configures the hardware resources used in this example * This function configures the hardware resources used in this example
@ -105,22 +292,82 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
__HAL_RCC_SPI1_CLK_ENABLE(); __HAL_RCC_SPI1_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
/**SPI1 GPIO Configuration /**SPI1 GPIO Configuration
PA4 ------> SPI1_NSS
PA5 ------> SPI1_SCK PA5 ------> SPI1_SCK
PA6 ------> SPI1_MISO PB4 ------> SPI1_MISO
PA7 ------> SPI1_MOSI PB5 ------> SPI1_MOSI
*/ */
GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; GPIO_InitStruct.Pin = AMS_CS_Pin|GPIO_PIN_5;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF5_SPI1; GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/* USER CODE BEGIN SPI1_MspInit 1 */ /* USER CODE BEGIN SPI1_MspInit 1 */
/* USER CODE END SPI1_MspInit 1 */ /* USER CODE END SPI1_MspInit 1 */
}
else if(hspi->Instance==SPI2)
{
/* USER CODE BEGIN SPI2_MspInit 0 */
/* USER CODE END SPI2_MspInit 0 */
/** Initializes the peripherals clock
*/
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SPI2;
PeriphClkInitStruct.Spi123ClockSelection = RCC_SPI123CLKSOURCE_PLL;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
Error_Handler();
}
/* Peripheral clock enable */
__HAL_RCC_SPI2_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
/**SPI2 GPIO Configuration
PC3 ------> SPI2_MOSI
PB12 ------> SPI2_NSS
PB14 ------> SPI2_MISO
PA12 ------> SPI2_SCK
*/
GPIO_InitStruct.Pin = GPIO_PIN_3;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_14;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
GPIO_InitStruct.Pin = GPIO_PIN_12;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/* USER CODE BEGIN SPI2_MspInit 1 */
/* USER CODE END SPI2_MspInit 1 */
} }
} }
@ -142,16 +389,106 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi)
__HAL_RCC_SPI1_CLK_DISABLE(); __HAL_RCC_SPI1_CLK_DISABLE();
/**SPI1 GPIO Configuration /**SPI1 GPIO Configuration
PA4 ------> SPI1_NSS
PA5 ------> SPI1_SCK PA5 ------> SPI1_SCK
PA6 ------> SPI1_MISO PB4 ------> SPI1_MISO
PA7 ------> SPI1_MOSI PB5 ------> SPI1_MOSI
*/ */
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7); HAL_GPIO_DeInit(GPIOA, AMS_CS_Pin|GPIO_PIN_5);
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_4|GPIO_PIN_5);
/* USER CODE BEGIN SPI1_MspDeInit 1 */ /* USER CODE BEGIN SPI1_MspDeInit 1 */
/* USER CODE END SPI1_MspDeInit 1 */ /* USER CODE END SPI1_MspDeInit 1 */
} }
else if(hspi->Instance==SPI2)
{
/* USER CODE BEGIN SPI2_MspDeInit 0 */
/* USER CODE END SPI2_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_SPI2_CLK_DISABLE();
/**SPI2 GPIO Configuration
PC3 ------> SPI2_MOSI
PB12 ------> SPI2_NSS
PB14 ------> SPI2_MISO
PA12 ------> SPI2_SCK
*/
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_3);
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_12|GPIO_PIN_14);
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_12);
/* USER CODE BEGIN SPI2_MspDeInit 1 */
/* USER CODE END SPI2_MspDeInit 1 */
}
}
/**
* @brief TIM_IC MSP Initialization
* This function configures the hardware resources used in this example
* @param htim_ic: TIM_IC handle pointer
* @retval None
*/
void HAL_TIM_IC_MspInit(TIM_HandleTypeDef* htim_ic)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
if(htim_ic->Instance==TIM15)
{
/* USER CODE BEGIN TIM15_MspInit 0 */
/* USER CODE END TIM15_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_TIM15_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
/**TIM15 GPIO Configuration
PA2 ------> TIM15_CH1
*/
GPIO_InitStruct.Pin = IMD_M_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF4_TIM15;
HAL_GPIO_Init(IMD_M_GPIO_Port, &GPIO_InitStruct);
/* USER CODE BEGIN TIM15_MspInit 1 */
/* USER CODE END TIM15_MspInit 1 */
}
}
/**
* @brief TIM_IC MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param htim_ic: TIM_IC handle pointer
* @retval None
*/
void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef* htim_ic)
{
if(htim_ic->Instance==TIM15)
{
/* USER CODE BEGIN TIM15_MspDeInit 0 */
/* USER CODE END TIM15_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_TIM15_CLK_DISABLE();
/**TIM15 GPIO Configuration
PA2 ------> TIM15_CH1
*/
HAL_GPIO_DeInit(IMD_M_GPIO_Port, IMD_M_Pin);
/* USER CODE BEGIN TIM15_MspDeInit 1 */
/* USER CODE END TIM15_MspDeInit 1 */
}
} }

16
AMS_Master_Code/Core/Src/stm32h7xx_it.c
View File

@ -55,7 +55,7 @@
/* USER CODE END 0 */ /* USER CODE END 0 */
/* External variables --------------------------------------------------------*/ /* External variables --------------------------------------------------------*/
extern FDCAN_HandleTypeDef hfdcan1;
/* USER CODE BEGIN EV */ /* USER CODE BEGIN EV */
/* USER CODE END EV */ /* USER CODE END EV */
@ -198,6 +198,20 @@ void SysTick_Handler(void)
/* please refer to the startup file (startup_stm32h7xx.s). */ /* please refer to the startup file (startup_stm32h7xx.s). */
/******************************************************************************/ /******************************************************************************/
/**
* @brief This function handles FDCAN1 interrupt 0.
*/
void FDCAN1_IT0_IRQHandler(void)
{
/* USER CODE BEGIN FDCAN1_IT0_IRQn 0 */
/* USER CODE END FDCAN1_IT0_IRQn 0 */
HAL_FDCAN_IRQHandler(&hfdcan1);
/* USER CODE BEGIN FDCAN1_IT0_IRQn 1 */
/* USER CODE END FDCAN1_IT0_IRQn 1 */
}
/* USER CODE BEGIN 1 */ /* USER CODE BEGIN 1 */
/* USER CODE END 1 */ /* USER CODE END 1 */

296
AMS_Master_Code/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7a3xxq.h → AMS_Master_Code/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7a3xx.h
View File

@ -1,8 +1,8 @@
/** /**
****************************************************************************** ******************************************************************************
* @file stm32h7a3xxq.h * @file stm32h7a3xx.h
* @author MCD Application Team * @author MCD Application Team
* @brief CMSIS STM32H7A3xxQ Device Peripheral Access Layer Header File. * @brief CMSIS STM32H7A3xx Device Peripheral Access Layer Header File.
* *
* This file contains: * This file contains:
* - Data structures and the address mapping for all peripherals * - Data structures and the address mapping for all peripherals
@ -26,12 +26,12 @@
* @{ * @{
*/ */
/** @addtogroup stm32h7a3xxq /** @addtogroup stm32h7a3xx
* @{ * @{
*/ */
#ifndef STM32H7A3xxQ_H #ifndef STM32H7A3xx_H
#define STM32H7A3xxQ_H #define STM32H7A3xx_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@ -202,7 +202,6 @@ typedef enum
* @{ * @{
*/ */
#define SMPS /*!< Switched mode power supply feature */
@ -9625,198 +9624,101 @@ typedef struct
/* */ /* */
/******************************************************************************/ /******************************************************************************/
/****************** Bits definition for GPIO_MODER register *****************/ /****************** Bits definition for GPIO_MODER register *****************/
#define GPIO_MODER_MODER0_Pos (0U) #define GPIO_MODER_MODE0_Pos (0U)
#define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */ #define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
#define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */ #define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
#define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */ #define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
#define GPIO_MODER_MODER1_Pos (2U) #define GPIO_MODER_MODE1_Pos (2U)
#define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */ #define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
#define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */ #define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
#define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */ #define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
#define GPIO_MODER_MODER2_Pos (4U) #define GPIO_MODER_MODE2_Pos (4U)
#define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */ #define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
#define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */ #define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
#define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */ #define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
#define GPIO_MODER_MODER3_Pos (6U) #define GPIO_MODER_MODE3_Pos (6U)
#define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */ #define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
#define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */ #define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
#define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */ #define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
#define GPIO_MODER_MODER4_Pos (8U) #define GPIO_MODER_MODE4_Pos (8U)
#define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */ #define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
#define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */ #define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
#define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */ #define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
#define GPIO_MODER_MODER5_Pos (10U) #define GPIO_MODER_MODE5_Pos (10U)
#define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */ #define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
#define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */ #define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
#define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */ #define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
#define GPIO_MODER_MODER6_Pos (12U) #define GPIO_MODER_MODE6_Pos (12U)
#define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */ #define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
#define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */ #define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
#define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */ #define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
#define GPIO_MODER_MODER7_Pos (14U) #define GPIO_MODER_MODE7_Pos (14U)
#define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */ #define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
#define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */ #define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
#define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */ #define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
#define GPIO_MODER_MODER8_Pos (16U) #define GPIO_MODER_MODE8_Pos (16U)
#define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */ #define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
#define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */ #define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
#define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */ #define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
#define GPIO_MODER_MODER9_Pos (18U) #define GPIO_MODER_MODE9_Pos (18U)
#define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */ #define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
#define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */ #define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
#define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */ #define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
#define GPIO_MODER_MODER10_Pos (20U) #define GPIO_MODER_MODE10_Pos (20U)
#define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */ #define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
#define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */ #define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
#define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */ #define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
#define GPIO_MODER_MODER11_Pos (22U) #define GPIO_MODER_MODE11_Pos (22U)
#define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */ #define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
#define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */ #define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
#define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */ #define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
#define GPIO_MODER_MODER12_Pos (24U) #define GPIO_MODER_MODE12_Pos (24U)
#define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */ #define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
#define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */ #define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
#define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */ #define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
#define GPIO_MODER_MODER13_Pos (26U) #define GPIO_MODER_MODE13_Pos (26U)
#define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */ #define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
#define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */ #define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
#define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */ #define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
#define GPIO_MODER_MODER14_Pos (28U) #define GPIO_MODER_MODE14_Pos (28U)
#define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */ #define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
#define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */ #define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
#define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */ #define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
#define GPIO_MODER_MODER15_Pos (30U) #define GPIO_MODER_MODE15_Pos (30U)
#define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */ #define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
#define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */ #define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
#define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */ #define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
/* Legacy Defines */
#define GPIO_MODER_MODE0_Pos GPIO_MODER_MODER0_Pos
#define GPIO_MODER_MODE0_Msk GPIO_MODER_MODER0_Msk
#define GPIO_MODER_MODE0 GPIO_MODER_MODER0
#define GPIO_MODER_MODE0_0 GPIO_MODER_MODER0_0
#define GPIO_MODER_MODE0_1 GPIO_MODER_MODER0_1
#define GPIO_MODER_MODE1_Pos GPIO_MODER_MODER1_Pos
#define GPIO_MODER_MODE1_Msk GPIO_MODER_MODER1_Msk
#define GPIO_MODER_MODE1 GPIO_MODER_MODER1
#define GPIO_MODER_MODE1_0 GPIO_MODER_MODER1_0
#define GPIO_MODER_MODE1_1 GPIO_MODER_MODER1_1
#define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_Pos
#define GPIO_MODER_MODE2_Msk GPIO_MODER_MODER2_Msk
#define GPIO_MODER_MODE2 GPIO_MODER_MODER2
#define GPIO_MODER_MODE2_0 GPIO_MODER_MODER2_0
#define GPIO_MODER_MODE2_1 GPIO_MODER_MODER2_1
#define GPIO_MODER_MODE3_Pos GPIO_MODER_MODER3_Pos
#define GPIO_MODER_MODE3_Msk GPIO_MODER_MODER3_Msk
#define GPIO_MODER_MODE3 GPIO_MODER_MODER3
#define GPIO_MODER_MODE3_0 GPIO_MODER_MODER3_0
#define GPIO_MODER_MODE3_1 GPIO_MODER_MODER3_1
#define GPIO_MODER_MODE4_Pos GPIO_MODER_MODER4_Pos
#define GPIO_MODER_MODE4_Msk GPIO_MODER_MODER4_Msk
#define GPIO_MODER_MODE4 GPIO_MODER_MODER4
#define GPIO_MODER_MODE4_0 GPIO_MODER_MODER4_0
#define GPIO_MODER_MODE4_1 GPIO_MODER_MODER4_1
#define GPIO_MODER_MODE5_Pos GPIO_MODER_MODER5_Pos
#define GPIO_MODER_MODE5_Msk GPIO_MODER_MODER5_Msk
#define GPIO_MODER_MODE5 GPIO_MODER_MODER5
#define GPIO_MODER_MODE5_0 GPIO_MODER_MODER5_0
#define GPIO_MODER_MODE5_1 GPIO_MODER_MODER5_1
#define GPIO_MODER_MODE6_Pos GPIO_MODER_MODER6_Pos
#define GPIO_MODER_MODE6_Msk GPIO_MODER_MODER6_Msk
#define GPIO_MODER_MODE6 GPIO_MODER_MODER6
#define GPIO_MODER_MODE6_0 GPIO_MODER_MODER6_0
#define GPIO_MODER_MODE6_1 GPIO_MODER_MODER6_1
#define GPIO_MODER_MODE7_Pos GPIO_MODER_MODER7_Pos
#define GPIO_MODER_MODE7_Msk GPIO_MODER_MODER7_Msk
#define GPIO_MODER_MODE7 GPIO_MODER_MODER7
#define GPIO_MODER_MODE7_0 GPIO_MODER_MODER7_0
#define GPIO_MODER_MODE7_1 GPIO_MODER_MODER7_1
#define GPIO_MODER_MODE8_Pos GPIO_MODER_MODER8_Pos
#define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER8_Msk
#define GPIO_MODER_MODE8 GPIO_MODER_MODER8
#define GPIO_MODER_MODE8_0 GPIO_MODER_MODER8_0
#define GPIO_MODER_MODE8_1 GPIO_MODER_MODER8_1
#define GPIO_MODER_MODE9_Pos GPIO_MODER_MODER9_Pos
#define GPIO_MODER_MODE9_Msk GPIO_MODER_MODER9_Msk
#define GPIO_MODER_MODE9 GPIO_MODER_MODER9
#define GPIO_MODER_MODE9_0 GPIO_MODER_MODER9_0
#define GPIO_MODER_MODE9_1 GPIO_MODER_MODER9_1
#define GPIO_MODER_MODE10_Pos GPIO_MODER_MODER10_Po
#define GPIO_MODER_MODE10_Msk GPIO_MODER_MODER10_Ms
#define GPIO_MODER_MODE10 GPIO_MODER_MODER10
#define GPIO_MODER_MODE10_0 GPIO_MODER_MODER10_0
#define GPIO_MODER_MODE10_1 GPIO_MODER_MODER10_1
#define GPIO_MODER_MODE11_Pos GPIO_MODER_MODER11_Po
#define GPIO_MODER_MODE11_Msk GPIO_MODER_MODER11_Ms
#define GPIO_MODER_MODE11 GPIO_MODER_MODER11
#define GPIO_MODER_MODE11_0 GPIO_MODER_MODER11_0
#define GPIO_MODER_MODE11_1 GPIO_MODER_MODER11_1
#define GPIO_MODER_MODE12_Pos GPIO_MODER_MODER12_Po
#define GPIO_MODER_MODE12_Msk GPIO_MODER_MODER12_Ms
#define GPIO_MODER_MODE12 GPIO_MODER_MODER12
#define GPIO_MODER_MODE12_0 GPIO_MODER_MODER12_0
#define GPIO_MODER_MODE12_1 GPIO_MODER_MODER12_1
#define GPIO_MODER_MODE13_Pos GPIO_MODER_MODER13_Po
#define GPIO_MODER_MODE13_Msk GPIO_MODER_MODER13_Ms
#define GPIO_MODER_MODE13 GPIO_MODER_MODER13
#define GPIO_MODER_MODE13_0 GPIO_MODER_MODER13_0
#define GPIO_MODER_MODE13_1 GPIO_MODER_MODER13_1
#define GPIO_MODER_MODE14_Pos GPIO_MODER_MODER14_Po
#define GPIO_MODER_MODE14_Msk GPIO_MODER_MODER14_Ms
#define GPIO_MODER_MODE14 GPIO_MODER_MODER14
#define GPIO_MODER_MODE14_0 GPIO_MODER_MODER14_0
#define GPIO_MODER_MODE14_1 GPIO_MODER_MODER14_1
#define GPIO_MODER_MODE15_Pos GPIO_MODER_MODER15_Po
#define GPIO_MODER_MODE15_Msk GPIO_MODER_MODER15_Ms
#define GPIO_MODER_MODE15 GPIO_MODER_MODER15
#define GPIO_MODER_MODE15_0 GPIO_MODER_MODER15_0
#define GPIO_MODER_MODE15_1 GPIO_MODER_MODER15_1
/****************** Bits definition for GPIO_OTYPER register ****************/ /****************** Bits definition for GPIO_OTYPER register ****************/
#define GPIO_OTYPER_OT0_Pos (0U) #define GPIO_OTYPER_OT0_Pos (0U)
@ -11432,10 +11334,10 @@ typedef struct
#define JPEG_SR_COF JPEG_SR_COF_Msk /*!<JPEG Codec operation on going flag */ #define JPEG_SR_COF JPEG_SR_COF_Msk /*!<JPEG Codec operation on going flag */
/******************** Bit definition for CFR register ********************/ /******************** Bit definition for CFR register ********************/
#define JPEG_CFR_CEOCF_Pos (5U) #define JPEG_CFR_CEOCF_Pos (4U)
#define JPEG_CFR_CEOCF_Msk (0x1UL << JPEG_CFR_CEOCF_Pos) /*!< 0x00000010 */ #define JPEG_CFR_CEOCF_Msk (0x1UL << JPEG_CFR_CEOCF_Pos) /*!< 0x00000010 */
#define JPEG_CFR_CEOCF JPEG_CFR_CEOCF_Msk /*!<Clear End of Conversion Flag */ #define JPEG_CFR_CEOCF JPEG_CFR_CEOCF_Msk /*!<Clear End of Conversion Flag */
#define JPEG_CFR_CHPDF_Pos (6U) #define JPEG_CFR_CHPDF_Pos (5U)
#define JPEG_CFR_CHPDF_Msk (0x1UL << JPEG_CFR_CHPDF_Pos) /*!< 0x00000020 */ #define JPEG_CFR_CHPDF_Msk (0x1UL << JPEG_CFR_CHPDF_Pos) /*!< 0x00000020 */
#define JPEG_CFR_CHPDF JPEG_CFR_CHPDF_Msk /*!<Clear Header Parsing Done Flag */ #define JPEG_CFR_CHPDF JPEG_CFR_CHPDF_Msk /*!<Clear Header Parsing Done Flag */
@ -12432,26 +12334,15 @@ typedef struct
#define PWR_CR3_USB33DEN_Pos (24U) #define PWR_CR3_USB33DEN_Pos (24U)
#define PWR_CR3_USB33DEN_Msk (0x1UL << PWR_CR3_USB33DEN_Pos) /*!< 0x01000000 */ #define PWR_CR3_USB33DEN_Msk (0x1UL << PWR_CR3_USB33DEN_Pos) /*!< 0x01000000 */
#define PWR_CR3_USB33DEN PWR_CR3_USB33DEN_Msk /*!< VDD33_USB voltage level detector enable */ #define PWR_CR3_USB33DEN PWR_CR3_USB33DEN_Msk /*!< VDD33_USB voltage level detector enable */
#define PWR_CR3_SMPSEXTRDY_Pos (16U)
#define PWR_CR3_SMPSEXTRDY_Msk (0x1UL << PWR_CR3_SMPSEXTRDY_Pos) /*!< 0x00010000 */
#define PWR_CR3_SMPSEXTRDY PWR_CR3_SMPSEXTRDY_Msk /*!< SMPS External supply ready */
#define PWR_CR3_VBRS_Pos (9U) #define PWR_CR3_VBRS_Pos (9U)
#define PWR_CR3_VBRS_Msk (0x1UL << PWR_CR3_VBRS_Pos) /*!< 0x00000200 */ #define PWR_CR3_VBRS_Msk (0x1UL << PWR_CR3_VBRS_Pos) /*!< 0x00000200 */
#define PWR_CR3_VBRS PWR_CR3_VBRS_Msk /*!< VBAT charging resistor selection */ #define PWR_CR3_VBRS PWR_CR3_VBRS_Msk /*!< VBAT charging resistor selection */
#define PWR_CR3_VBE_Pos (8U) #define PWR_CR3_VBE_Pos (8U)
#define PWR_CR3_VBE_Msk (0x1UL << PWR_CR3_VBE_Pos) /*!< 0x00000100 */ #define PWR_CR3_VBE_Msk (0x1UL << PWR_CR3_VBE_Pos) /*!< 0x00000100 */
#define PWR_CR3_VBE PWR_CR3_VBE_Msk /*!< VBAT charging enable */ #define PWR_CR3_VBE PWR_CR3_VBE_Msk /*!< VBAT charging enable */
#define PWR_CR3_SMPSLEVEL_Pos (4U) #define PWR_CR3_SCUEN_Pos (2U)
#define PWR_CR3_SMPSLEVEL_Msk (0x3UL << PWR_CR3_SMPSLEVEL_Pos) /*!< 0x00000030 */ #define PWR_CR3_SCUEN_Msk (0x1UL << PWR_CR3_SCUEN_Pos) /*!< 0x00000004 */
#define PWR_CR3_SMPSLEVEL PWR_CR3_SMPSLEVEL_Msk /*!< SMPS output Voltage */ #define PWR_CR3_SCUEN PWR_CR3_SCUEN_Msk /*!< Supply configuration update enable */
#define PWR_CR3_SMPSLEVEL_0 (0x1UL << PWR_CR3_SMPSLEVEL_Pos) /*!< 0x00000010 */
#define PWR_CR3_SMPSLEVEL_1 (0x2UL << PWR_CR3_SMPSLEVEL_Pos) /*!< 0x00000020 */
#define PWR_CR3_SMPSEXTHP_Pos (3U)
#define PWR_CR3_SMPSEXTHP_Msk (0x1UL << PWR_CR3_SMPSEXTHP_Pos) /*!< 0x00000008 */
#define PWR_CR3_SMPSEXTHP PWR_CR3_SMPSEXTHP_Msk /*!< SMPS forced ON and in High Power MR mode */
#define PWR_CR3_SMPSEN_Pos (2U)
#define PWR_CR3_SMPSEN_Msk (0x1UL << PWR_CR3_SMPSEN_Pos) /*!< 0x00000004 */
#define PWR_CR3_SMPSEN PWR_CR3_SMPSEN_Msk /*!< SMPS Enable */
#define PWR_CR3_LDOEN_Pos (1U) #define PWR_CR3_LDOEN_Pos (1U)
#define PWR_CR3_LDOEN_Msk (0x1UL << PWR_CR3_LDOEN_Pos) /*!< 0x00000002 */ #define PWR_CR3_LDOEN_Msk (0x1UL << PWR_CR3_LDOEN_Pos) /*!< 0x00000002 */
#define PWR_CR3_LDOEN PWR_CR3_LDOEN_Msk /*!< Low Drop Output regulator enable */ #define PWR_CR3_LDOEN PWR_CR3_LDOEN_Msk /*!< Low Drop Output regulator enable */
@ -14676,11 +14567,6 @@ typedef struct
/* Real-Time Clock (RTC) */ /* Real-Time Clock (RTC) */
/* */ /* */
/******************************************************************************/ /******************************************************************************/
#define RTC_TAMPER2_SUPPORT /*!<RTC TAMPER 2 support feature */
#define RTC_TAMPNOERASE_SUPPORT /*!<RTC BKP REG NO ERASE ON TAMPER support feature */
#define RTC_TAMPMASKFLAG_SUPPORT /*!<RTC TAMPER MASK FLAG support feature */
#define RTC_TAMPxIE_SUPPORT /*!<RTC TAMPERx INTERRUPT ENABLE support feature */
/******************** Bits definition for RTC_TR register *******************/ /******************** Bits definition for RTC_TR register *******************/
#define RTC_TR_PM_Pos (22U) #define RTC_TR_PM_Pos (22U)
#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */ #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
@ -22687,5 +22573,5 @@ typedef struct
} }
#endif /* __cplusplus */ #endif /* __cplusplus */
#endif /* STM32H7A3xxQ_H */ #endif /* STM32H7A3xx_H */

7
AMS_Master_Code/Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h
View File

@ -71,8 +71,7 @@
/* #define STM32H745xx */ /*!< STM32H745ZI, STM32H745II, STM32H745BI, STM32H745XI Devices */ /* #define STM32H745xx */ /*!< STM32H745ZI, STM32H745II, STM32H745BI, STM32H745XI Devices */
/* #define STM32H745xG */ /*!< STM32H745ZG, STM32H745IG, STM32H745BG, STM32H745XG Devices */ /* #define STM32H745xG */ /*!< STM32H745ZG, STM32H745IG, STM32H745BG, STM32H745XG Devices */
/* #define STM32H755xx */ /*!< STM32H755ZI, STM32H755II, STM32H755BI, STM32H755XI Devices */ /* #define STM32H755xx */ /*!< STM32H755ZI, STM32H755II, STM32H755BI, STM32H755XI Devices */
/* #define STM32H7B0xx */ /*!< STM32H7B0IBTx, STM32H7B0RBTx, STM32H7B0VBTx, STM32H7B0ZBTx Devices */ /* #define STM32H7B0xx */ /*!< STM32H7B0ABIxQ, STM32H7B0IBTx, STM32H7B0RBTx, STM32H7B0VBTx, STM32H7B0ZBTx, STM32H7B0IBKxQ */
/* #define STM32H7B0xxQ */ /*!< STM32H7B0ABIxQ, STM32H7B0IBKxQ Devices */
/* #define STM32H7A3xx */ /*!< STM32H7A3IIK6, STM32H7A3IIT6, STM32H7A3NIH6, STM32H7A3RIT6, STM32H7A3VIH6, STM32H7A3VIT6, STM32H7A3ZIT6 */ /* #define STM32H7A3xx */ /*!< STM32H7A3IIK6, STM32H7A3IIT6, STM32H7A3NIH6, STM32H7A3RIT6, STM32H7A3VIH6, STM32H7A3VIT6, STM32H7A3ZIT6 */
/* #define STM32H7A3xxQ */ /*!< STM32H7A3QIY6Q, STM32H7A3IIK6Q, STM32H7A3IIT6Q, STM32H7A3LIH6Q, STM32H7A3VIH6Q, STM32H7A3VIT6Q, STM32H7A3AII6Q, STM32H7A3ZIT6Q */ /* #define STM32H7A3xxQ */ /*!< STM32H7A3QIY6Q, STM32H7A3IIK6Q, STM32H7A3IIT6Q, STM32H7A3LIH6Q, STM32H7A3VIH6Q, STM32H7A3VIT6Q, STM32H7A3AII6Q, STM32H7A3ZIT6Q */
/* #define STM32H7B3xx */ /*!< STM32H7B3IIK6, STM32H7B3IIT6, STM32H7B3NIH6, STM32H7B3RIT6, STM32H7B3VIH6, STM32H7B3VIT6, STM32H7B3ZIT6 */ /* #define STM32H7B3xx */ /*!< STM32H7B3IIK6, STM32H7B3IIT6, STM32H7B3NIH6, STM32H7B3RIT6, STM32H7B3VIH6, STM32H7B3VIT6, STM32H7B3ZIT6 */
@ -103,11 +102,11 @@
#endif /* USE_HAL_DRIVER */ #endif /* USE_HAL_DRIVER */
/** /**
* @brief CMSIS Device version number V1.10.6 * @brief CMSIS Device version number V1.10.4
*/ */
#define __STM32H7xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */ #define __STM32H7xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x0A) /*!< [23:16] sub1 version */ #define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x0A) /*!< [23:16] sub1 version */
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x06) /*!< [15:8] sub2 version */ #define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x04) /*!< [15:8] sub2 version */
#define __STM32H7xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32H7xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32H7xx_CMSIS_DEVICE_VERSION ((__STM32H7xx_CMSIS_DEVICE_VERSION_MAIN << 24)\ #define __STM32H7xx_CMSIS_DEVICE_VERSION ((__STM32H7xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
|(__STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\ |(__STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\

1
AMS_Master_Code/Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h
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@ -84,7 +84,6 @@ extern const uint8_t D1CorePrescTable[16] ; /*!< D1CorePrescTable prescalers ta
extern void SystemInit(void); extern void SystemInit(void);
extern void SystemCoreClockUpdate(void); extern void SystemCoreClockUpdate(void);
extern void ExitRun0Mode(void);
/** /**
* @} * @}
*/ */

84
AMS_Master_Code/Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
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@ -472,9 +472,7 @@ extern "C" {
#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) && !defined(STM32H5)
#define PAGESIZE FLASH_PAGE_SIZE #define PAGESIZE FLASH_PAGE_SIZE
#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 && STM32H5 */
#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
@ -603,15 +601,6 @@ extern "C" {
#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
#endif /* STM32G4 */ #endif /* STM32G4 */
#if defined(STM32U5)
#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOAnalogBooster
#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOAnalogBooster
#define HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection HAL_SYSCFG_EnableIOAnalogVoltageSelection
#define HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection HAL_SYSCFG_DisableIOAnalogVoltageSelection
#endif /* STM32U5 */
#if defined(STM32H5) #if defined(STM32H5)
#define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC #define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC
#define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC #define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC
@ -817,21 +806,6 @@ extern "C" {
#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP #define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP
#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 #define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1
#endif /* STM32U5 */ #endif /* STM32U5 */
#if defined(STM32WBA)
#define GPIO_AF11_RF_ANTSW0 GPIO_AF11_RF
#define GPIO_AF11_RF_ANTSW1 GPIO_AF11_RF
#define GPIO_AF11_RF_ANTSW2 GPIO_AF11_RF
#define GPIO_AF11_RF_IO1 GPIO_AF11_RF
#define GPIO_AF11_RF_IO2 GPIO_AF11_RF
#define GPIO_AF11_RF_IO3 GPIO_AF11_RF
#define GPIO_AF11_RF_IO4 GPIO_AF11_RF
#define GPIO_AF11_RF_IO5 GPIO_AF11_RF
#define GPIO_AF11_RF_IO6 GPIO_AF11_RF
#define GPIO_AF11_RF_IO7 GPIO_AF11_RF
#define GPIO_AF11_RF_IO8 GPIO_AF11_RF
#define GPIO_AF11_RF_IO9 GPIO_AF11_RF
#endif /* STM32WBA */
/** /**
* @} * @}
*/ */
@ -886,10 +860,6 @@ extern "C" {
#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
#if defined(STM32F3) || defined(STM32G4) || defined(STM32H7)
#define HRTIMInterruptResquests HRTIMInterruptRequests
#endif /* STM32F3 || STM32G4 || STM32H7 */
#if defined(STM32G4) #if defined(STM32G4)
#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig #define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig
#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable #define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable
@ -1027,8 +997,8 @@ extern "C" {
#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) #define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0)
#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) #define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1)
#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) #define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
#endif /* STM32F3 */
#endif /* STM32F3 */
/** /**
* @} * @}
*/ */
@ -1279,10 +1249,10 @@ extern "C" {
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
#if defined(STM32H5) || defined(STM32H7RS) || defined(STM32N6) #if defined(STM32H5) || defined(STM32H7RS)
#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM #define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM
#endif /* STM32H5 || STM32H7RS || STM32N6 */ #endif /* STM32H5 || STM32H7RS */
#if defined(STM32WBA) #if defined(STM32WBA)
#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
@ -1294,10 +1264,10 @@ extern "C" {
#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL #define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL
#endif /* STM32WBA */ #endif /* STM32WBA */
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) #if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE
#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL #define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL
#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ #endif /* STM32H5 || STM32WBA || STM32H7RS */
#if defined(STM32F7) #if defined(STM32F7)
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK #define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK
@ -1847,7 +1817,7 @@ extern "C" {
#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE)? \ #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd == ENABLE)? \
HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \ HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \
HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
@ -2029,12 +1999,12 @@ extern "C" {
/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose /** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose
* @{ * @{
*/ */
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) #if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey #define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey
#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock #define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock
#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock #define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock
#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets #define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets
#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ #endif /* STM32H5 || STM32WBA || STM32H7RS */
/** /**
* @} * @}
@ -2761,12 +2731,6 @@ extern "C" {
#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
#if defined(STM32C0)
#define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET
#define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET
#define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET
#define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET
#endif /* STM32C0 */
#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
@ -3695,7 +3659,7 @@ extern "C" {
#endif #endif
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ #if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \
defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || defined(STM32U0) defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
#else #else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
@ -3946,8 +3910,7 @@ extern "C" {
*/ */
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ #if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \
defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32N6) || \ defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0)
defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3)
#else #else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif #endif
@ -4241,33 +4204,6 @@ extern "C" {
#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
#if defined(STM32U5)
#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSVLD
#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINTMSK
#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPC
#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_PSRST
#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_GONAKEFF
#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUPINT
#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM
#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_CHNUM
#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1RSMOK
#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFSIZ
#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MCNT
#define USB_OTG_HCCHAR_MC_0 USB_OTG_HCCHAR_MCNT_0
#define USB_OTG_HCCHAR_MC_1 USB_OTG_HCCHAR_MCNT_1
#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERRM
#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPNG
#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OUTPKTERRM
#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM
#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MCNT
#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM
#define USB_OTG_DOEPCTL_DPID USB_OTG_DOEPCTL_DPID_EONUM
#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_RXDPID
#define USB_OTG_DOEPTSIZ_STUPCNT_0 USB_OTG_DOEPTSIZ_RXDPID_0
#define USB_OTG_DOEPTSIZ_STUPCNT_1 USB_OTG_DOEPTSIZ_RXDPID_1
#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STPPCLK
#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATEHCLK
#endif
/** /**
* @} * @}
*/ */

6
AMS_Master_Code/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h
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@ -59,14 +59,8 @@ typedef enum
* @{ * @{
*/ */
#define REV_ID_Y ((uint32_t)0x1003) /*!< STM32H7 rev.Y */ #define REV_ID_Y ((uint32_t)0x1003) /*!< STM32H7 rev.Y */
#define REV_ID_Z ((uint32_t)0x1001) /*!< STM32H7 rev.Z */
#define REV_ID_A ((uint32_t)0x1000) /*!< STM32H7 rev.A */
#define REV_ID_B ((uint32_t)0x2000) /*!< STM32H7 rev.B */ #define REV_ID_B ((uint32_t)0x2000) /*!< STM32H7 rev.B */
#if (STM32H7_DEV_ID == 0x450UL)
#define REV_ID_X ((uint32_t)0x2001) /*!< STM32H7 rev.X */ #define REV_ID_X ((uint32_t)0x2001) /*!< STM32H7 rev.X */
#else
#define REV_ID_X ((uint32_t)0x1007) /*!< STM32H7 rev.X */
#endif /* STM32H7_DEV_ID */
#define REV_ID_V ((uint32_t)0x2003) /*!< STM32H7 rev.V */ #define REV_ID_V ((uint32_t)0x2003) /*!< STM32H7 rev.V */
/** /**

2034
AMS_Master_Code/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h Normal file
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File diff suppressed because it is too large Load Diff

1388
AMS_Master_Code/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h Normal file
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File diff suppressed because it is too large Load Diff

2
AMS_Master_Code/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h
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@ -309,7 +309,7 @@ void HAL_MPU_Enable(uint32_t MPU_Control);
void HAL_MPU_Disable(void); void HAL_MPU_Disable(void);
void HAL_MPU_EnableRegion(uint32_t RegionNumber); void HAL_MPU_EnableRegion(uint32_t RegionNumber);
void HAL_MPU_DisableRegion(uint32_t RegionNumber); void HAL_MPU_DisableRegion(uint32_t RegionNumber);
void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *MPU_Init); void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
#endif /* __MPU_PRESENT */ #endif /* __MPU_PRESENT */
uint32_t HAL_NVIC_GetPriorityGrouping(void); uint32_t HAL_NVIC_GetPriorityGrouping(void);
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);

4
AMS_Master_Code/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h
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@ -1211,8 +1211,8 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Ca
* @brief Peripheral State functions * @brief Peripheral State functions
* @{ * @{
*/ */
HAL_DMA_StateTypeDef HAL_DMA_GetState(const DMA_HandleTypeDef *hdma); HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
uint32_t HAL_DMA_GetError(const DMA_HandleTypeDef *hdma); uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
/** /**
* @} * @}
*/ */

10
AMS_Master_Code/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h
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@ -496,7 +496,7 @@ typedef struct
/* Configuration functions ****************************************************/ /* Configuration functions ****************************************************/
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(const EXTI_HandleTypeDef *hexti); HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)); HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine); HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
/** /**
@ -508,10 +508,10 @@ HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLin
* @{ * @{
*/ */
/* IO operation functions *****************************************************/ /* IO operation functions *****************************************************/
void HAL_EXTI_IRQHandler(const EXTI_HandleTypeDef *hexti); void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
uint32_t HAL_EXTI_GetPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge); uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
void HAL_EXTI_ClearPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge); void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
void HAL_EXTI_GenerateSWI(const EXTI_HandleTypeDef *hexti); void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
/** /**
* @} * @}

2464
AMS_Master_Code/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_fdcan.h Normal file
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File diff suppressed because it is too large Load Diff

4
AMS_Master_Code/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h
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@ -252,7 +252,7 @@ typedef enum
* @{ * @{
*/ */
/* Initialization and de-initialization functions *****************************/ /* Initialization and de-initialization functions *****************************/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *GPIO_Init); void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
/** /**
* @} * @}
@ -262,7 +262,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
* @{ * @{
*/ */
/* IO operation functions *****************************************************/ /* IO operation functions *****************************************************/
GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);

12
AMS_Master_Code/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h
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@ -57,7 +57,7 @@ extern "C" {
(HSEM->C1IER |= (__SEM_MASK__)) : \ (HSEM->C1IER |= (__SEM_MASK__)) : \
(HSEM->C2IER |= (__SEM_MASK__))) (HSEM->C2IER |= (__SEM_MASK__)))
#else #else
#define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) (HSEM->C1IER |= (__SEM_MASK__)) #define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) (HSEM->IER |= (__SEM_MASK__))
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */
/** /**
* @brief Disables the specified HSEM interrupts. * @brief Disables the specified HSEM interrupts.
@ -69,7 +69,7 @@ extern "C" {
(HSEM->C1IER &= ~(__SEM_MASK__)) : \ (HSEM->C1IER &= ~(__SEM_MASK__)) : \
(HSEM->C2IER &= ~(__SEM_MASK__))) (HSEM->C2IER &= ~(__SEM_MASK__)))
#else #else
#define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) (HSEM->C1IER &= ~(__SEM_MASK__)) #define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) (HSEM->IER &= ~(__SEM_MASK__))
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */
/** /**
@ -80,9 +80,9 @@ extern "C" {
#if defined(DUAL_CORE) #if defined(DUAL_CORE)
#define __HAL_HSEM_GET_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \ #define __HAL_HSEM_GET_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
((__SEM_MASK__) & HSEM->C1MISR) : \ ((__SEM_MASK__) & HSEM->C1MISR) : \
((__SEM_MASK__) & HSEM->C2MISR)) ((__SEM_MASK__) & HSEM->C2MISR1))
#else #else
#define __HAL_HSEM_GET_IT(__SEM_MASK__) ((__SEM_MASK__) & HSEM->C1MISR) #define __HAL_HSEM_GET_IT(__SEM_MASK__) ((__SEM_MASK__) & HSEM->MISR)
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */
/** /**
@ -95,7 +95,7 @@ extern "C" {
(__SEM_MASK__) & HSEM->C1ISR : \ (__SEM_MASK__) & HSEM->C1ISR : \
(__SEM_MASK__) & HSEM->C2ISR) (__SEM_MASK__) & HSEM->C2ISR)
#else #else
#define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((__SEM_MASK__) & HSEM->C1ISR) #define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((__SEM_MASK__) & HSEM->ISR)
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */
/** /**
@ -108,7 +108,7 @@ extern "C" {
(HSEM->C1ICR |= (__SEM_MASK__)) : \ (HSEM->C1ICR |= (__SEM_MASK__)) : \
(HSEM->C2ICR |= (__SEM_MASK__))) (HSEM->C2ICR |= (__SEM_MASK__)))
#else #else
#define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) (HSEM->C1ICR |= (__SEM_MASK__)) #define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) (HSEM->ICR |= (__SEM_MASK__))
#endif /* DUAL_CORE */ #endif /* DUAL_CORE */
/** /**

6
AMS_Master_Code/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h
View File

@ -655,7 +655,7 @@ HAL_StatusTypeDef HAL_MDMA_UnRegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDM
*/ */
HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MDMA_LinkNodeConfTypeDef *pNodeConfig); HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MDMA_LinkNodeConfTypeDef *pNodeConfig);
HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, const MDMA_LinkNodeTypeDef *pPrevNode); HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, MDMA_LinkNodeTypeDef *pPrevNode);
HAL_StatusTypeDef HAL_MDMA_LinkedList_RemoveNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNode); HAL_StatusTypeDef HAL_MDMA_LinkedList_RemoveNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNode);
HAL_StatusTypeDef HAL_MDMA_LinkedList_EnableCircularMode(MDMA_HandleTypeDef *hmdma); HAL_StatusTypeDef HAL_MDMA_LinkedList_EnableCircularMode(MDMA_HandleTypeDef *hmdma);
HAL_StatusTypeDef HAL_MDMA_LinkedList_DisableCircularMode(MDMA_HandleTypeDef *hmdma); HAL_StatusTypeDef HAL_MDMA_LinkedList_DisableCircularMode(MDMA_HandleTypeDef *hmdma);
@ -687,8 +687,8 @@ void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma);
* @brief Peripheral State functions * @brief Peripheral State functions
* @{ * @{
*/ */
HAL_MDMA_StateTypeDef HAL_MDMA_GetState(const MDMA_HandleTypeDef *hmdma); HAL_MDMA_StateTypeDef HAL_MDMA_GetState(MDMA_HandleTypeDef *hmdma);
uint32_t HAL_MDMA_GetError(const MDMA_HandleTypeDef *hmdma); uint32_t HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma);
/** /**
* @} * @}

2
AMS_Master_Code/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h
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@ -692,7 +692,7 @@ void HAL_PWR_DisableBkUpAccess (void);
*/ */
/* Peripheral Control functions **********************************************/ /* Peripheral Control functions **********************************************/
/* PVD configuration */ /* PVD configuration */
void HAL_PWR_ConfigPVD (const PWR_PVDTypeDef *sConfigPVD); void HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD);
void HAL_PWR_EnablePVD (void); void HAL_PWR_EnablePVD (void);
void HAL_PWR_DisablePVD (void); void HAL_PWR_DisablePVD (void);

4
AMS_Master_Code/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h
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@ -544,7 +544,7 @@ void HAL_PWREx_EnableMemoryShutOff (uint32_t MemoryBlock);
void HAL_PWREx_DisableMemoryShutOff (uint32_t MemoryBlock); void HAL_PWREx_DisableMemoryShutOff (uint32_t MemoryBlock);
#endif /* defined(PWR_CR1_SRDRAMSO) */ #endif /* defined(PWR_CR1_SRDRAMSO) */
/* Wakeup Pins control functions */ /* Wakeup Pins control functions */
void HAL_PWREx_EnableWakeUpPin (const PWREx_WakeupPinTypeDef *sPinParams); void HAL_PWREx_EnableWakeUpPin (PWREx_WakeupPinTypeDef *sPinParams);
void HAL_PWREx_DisableWakeUpPin (uint32_t WakeUpPin); void HAL_PWREx_DisableWakeUpPin (uint32_t WakeUpPin);
uint32_t HAL_PWREx_GetWakeupFlag (uint32_t WakeUpFlag); uint32_t HAL_PWREx_GetWakeupFlag (uint32_t WakeUpFlag);
HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag (uint32_t WakeUpFlag); HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag (uint32_t WakeUpFlag);
@ -599,7 +599,7 @@ uint32_t HAL_PWREx_GetVBATLevel (void);
PWREx_MMC_VoltageLevel HAL_PWREx_GetMMCVoltage (void); PWREx_MMC_VoltageLevel HAL_PWREx_GetMMCVoltage (void);
#endif /* PWR_CSR1_MMCVDO */ #endif /* PWR_CSR1_MMCVDO */
/* Power AVD configuration functions */ /* Power AVD configuration functions */
void HAL_PWREx_ConfigAVD (const PWREx_AVDTypeDef *sConfigAVD); void HAL_PWREx_ConfigAVD (PWREx_AVDTypeDef *sConfigAVD);
void HAL_PWREx_EnableAVD (void); void HAL_PWREx_EnableAVD (void);
void HAL_PWREx_DisableAVD (void); void HAL_PWREx_DisableAVD (void);
/* Power PVD/AVD IRQ Handler */ /* Power PVD/AVD IRQ Handler */

2
AMS_Master_Code/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h
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@ -7968,7 +7968,7 @@ typedef struct
/* Initialization and de-initialization functions ******************************/ /* Initialization and de-initialization functions ******************************/
HAL_StatusTypeDef HAL_RCC_DeInit(void); HAL_StatusTypeDef HAL_RCC_DeInit(void);
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
/** /**
* @} * @}

2
AMS_Master_Code/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc_ex.h
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@ -3936,7 +3936,7 @@ void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx);
* @{ * @{
*/ */
void HAL_RCCEx_CRSConfig(const RCC_CRSInitTypeDef *pInit); void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);

2466
AMS_Master_Code/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h Normal file
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533
AMS_Master_Code/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h Normal file
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@ -0,0 +1,533 @@
/**
******************************************************************************
* @file stm32h7xx_hal_tim_ex.h
* @author MCD Application Team
* @brief Header file of TIM HAL Extended module.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H7xx_HAL_TIM_EX_H
#define STM32H7xx_HAL_TIM_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup TIMEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
* @{
*/
/**
* @brief TIM Hall sensor Configuration Structure definition
*/
typedef struct
{
uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
uint32_t IC1Filter; /*!< Specifies the input capture filter.
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
} TIM_HallSensor_InitTypeDef;
#if defined(TIM_BREAK_INPUT_SUPPORT)
/**
* @brief TIM Break/Break2 input configuration
*/
typedef struct
{
uint32_t Source; /*!< Specifies the source of the timer break input.
This parameter can be a value of @ref TIMEx_Break_Input_Source */
uint32_t Enable; /*!< Specifies whether or not the break input source is enabled.
This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */
uint32_t Polarity; /*!< Specifies the break input source polarity.
This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity
Not relevant when analog watchdog output of the DFSDM1 used as break input source */
} TIMEx_BreakInputConfigTypeDef;
#endif /* TIM_BREAK_INPUT_SUPPORT */
/**
* @}
*/
/* End of exported types -----------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
* @{
*/
/** @defgroup TIMEx_Remap TIM Extended Remapping
* @{
*/
#define TIM_TIM1_ETR_GPIO 0x00000000U /*!< TIM1_ETR is connected to GPIO */
#define TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM1_ETR is connected to COMP1 OUT */
#define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< TIM1_ETR is connected to COMP2 OUT */
#define TIM_TIM1_ETR_ADC1_AWD1 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC1 AWD1 */
#define TIM_TIM1_ETR_ADC1_AWD2 (TIM1_AF1_ETRSEL_2) /*!< TIM1_ETR is connected to ADC1 AWD2 */
#define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC1 AWD3 */
#define TIM_TIM1_ETR_ADC3_AWD1 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM1_ETR is connected to ADC3 AWD1 */
#define TIM_TIM1_ETR_ADC3_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC3 AWD2 */
#define TIM_TIM1_ETR_ADC3_AWD3 TIM1_AF1_ETRSEL_3 /*!< TIM1_ETR is connected to ADC3 AWD3 */
#define TIM_TIM8_ETR_GPIO 0x00000000U /*!< TIM8_ETR is connected to GPIO */
#define TIM_TIM8_ETR_COMP1 TIM8_AF1_ETRSEL_0 /*!< TIM8_ETR is connected to COMP1 OUT */
#define TIM_TIM8_ETR_COMP2 TIM8_AF1_ETRSEL_1 /*!< TIM8_ETR is connected to COMP2 OUT */
#define TIM_TIM8_ETR_ADC2_AWD1 (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC2 AWD1 */
#define TIM_TIM8_ETR_ADC2_AWD2 (TIM8_AF1_ETRSEL_2) /*!< TIM8_ETR is connected to ADC2 AWD2 */
#define TIM_TIM8_ETR_ADC2_AWD3 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC2 AWD3 */
#define TIM_TIM8_ETR_ADC3_AWD1 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1) /*!< TIM8_ETR is connected to ADC3 AWD1 */
#define TIM_TIM8_ETR_ADC3_AWD2 (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC3 AWD2 */
#define TIM_TIM8_ETR_ADC3_AWD3 TIM8_AF1_ETRSEL_3 /*!< TIM8_ETR is connected to ADC3 AWD3 */
#define TIM_TIM2_ETR_GPIO 0x00000000U /*!< TIM2_ETR is connected to GPIO */
#define TIM_TIM2_ETR_COMP1 (TIM2_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to COMP1 OUT */
#define TIM_TIM2_ETR_COMP2 (TIM2_AF1_ETRSEL_1) /*!< TIM2_ETR is connected to COMP2 OUT */
#define TIM_TIM2_ETR_RCC_LSE (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to RCC LSE */
#define TIM_TIM2_ETR_SAI1_FSA TIM2_AF1_ETRSEL_2 /*!< TIM2_ETR is connected to SAI1 FS_A */
#define TIM_TIM2_ETR_SAI1_FSB (TIM2_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to SAI1 FS_B */
#define TIM_TIM3_ETR_GPIO 0x00000000U /*!< TIM3_ETR is connected to GPIO */
#define TIM_TIM3_ETR_COMP1 TIM3_AF1_ETRSEL_0 /*!< TIM3_ETR is connected to COMP1 OUT */
#define TIM_TIM5_ETR_GPIO 0x00000000U /*!< TIM5_ETR is connected to GPIO */
#define TIM_TIM5_ETR_SAI2_FSA TIM5_AF1_ETRSEL_0 /*!< TIM5_ETR is connected to SAI2 FS_A */
#define TIM_TIM5_ETR_SAI2_FSB TIM5_AF1_ETRSEL_1 /*!< TIM5_ETR is connected to SAI2 FS_B */
#define TIM_TIM5_ETR_SAI4_FSA TIM5_AF1_ETRSEL_0 /*!< TIM5_ETR is connected to SAI4 FS_A */
#define TIM_TIM5_ETR_SAI4_FSB TIM5_AF1_ETRSEL_1 /*!< TIM5_ETR is connected to SAI4 FS_B */
#define TIM_TIM23_ETR_GPIO 0x00000000U /*!< TIM23_ETR is connected to GPIO */
#define TIM_TIM23_ETR_COMP1 (TIM2_AF1_ETRSEL_0) /*!< TIM23_ETR is connected to COMP1 OUT */
#define TIM_TIM23_ETR_COMP2 (TIM2_AF1_ETRSEL_1) /*!< TIM23_ETR is connected to COMP2 OUT */
#define TIM_TIM24_ETR_GPIO 0x00000000U /*!< TIM24_ETR is connected to GPIO */
#define TIM_TIM24_ETR_SAI4_FSA TIM5_AF1_ETRSEL_0 /*!< TIM24_ETR is connected to SAI4 FS_A */
#define TIM_TIM24_ETR_SAI4_FSB TIM5_AF1_ETRSEL_1 /*!< TIM24_ETR is connected to SAI4 FS_B */
#define TIM_TIM24_ETR_SAI1_FSA (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /*!< TIM24_ETR is connected to SAI1 FS_A */
#define TIM_TIM24_ETR_SAI1_FSB TIM2_AF1_ETRSEL_2 /*!< TIM24_ETR is connected to SAI1 FS_B */
/**
* @}
*/
#if defined(TIM_BREAK_INPUT_SUPPORT)
/** @defgroup TIMEx_Break_Input TIM Extended Break input
* @{
*/
#define TIM_BREAKINPUT_BRK 0x00000001U /*!< Timer break input */
#define TIM_BREAKINPUT_BRK2 0x00000002U /*!< Timer break2 input */
/**
* @}
*/
/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source
* @{
*/
#define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /*!< An external source (GPIO) is connected to the BKIN pin */
#define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /*!< The COMP1 output is connected to the break input */
#define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /*!< The COMP2 output is connected to the break input */
#define TIM_BREAKINPUTSOURCE_DFSDM1 0x00000008U /*!< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */
/**
* @}
*/
/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling
* @{
*/
#define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /*!< Break input source is disabled */
#define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /*!< Break input source is enabled */
/**
* @}
*/
/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity
* @{
*/
#define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /*!< Break input source is active low */
#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /*!< Break input source is active_high */
/**
* @}
*/
#endif /* TIM_BREAK_INPUT_SUPPORT */
/** @defgroup TIMEx_Timer_Input_Selection TIM Extended Timer input selection
* @{
*/
#define TIM_TIM1_TI1_GPIO 0x00000000U /*!< TIM1_TI1 is connected to GPIO */
#define TIM_TIM1_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM1_TI1 is connected to COMP1 OUT */
#define TIM_TIM8_TI1_GPIO 0x00000000U /*!< TIM8_TI1 is connected to GPIO */
#define TIM_TIM8_TI1_COMP2 TIM_TISEL_TI1SEL_0 /*!< TIM8_TI1 is connected to COMP2 OUT */
#define TIM_TIM2_TI4_GPIO 0x00000000U /*!< TIM2_TI4 is connected to GPIO */
#define TIM_TIM2_TI4_COMP1 TIM_TISEL_TI4SEL_0 /*!< TIM2_TI4 is connected to COMP1 OUT */
#define TIM_TIM2_TI4_COMP2 TIM_TISEL_TI4SEL_1 /*!< TIM2_TI4 is connected to COMP2 OUT */
#define TIM_TIM2_TI4_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /*!< TIM2_TI4 is connected to COMP2 OUT OR COMP2 OUT */
#define TIM_TIM3_TI1_GPIO 0x00000000U /*!< TIM3_TI1 is connected to GPIO */
#define TIM_TIM3_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM3_TI1 is connected to COMP1 OUT */
#define TIM_TIM3_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM3_TI1 is connected to COMP2 OUT */
#define TIM_TIM3_TI1_COMP1_COMP2 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM3_TI1 is connected to COMP1 OUT or COMP2 OUT */
#define TIM_TIM5_TI1_GPIO 0x00000000U /*!< TIM5_TI1 is connected to GPIO */
#define TIM_TIM5_TI1_CAN_TMP TIM_TISEL_TI1SEL_0 /*!< TIM5_TI1 is connected to CAN TMP */
#define TIM_TIM5_TI1_CAN_RTP TIM_TISEL_TI1SEL_1 /*!< TIM5_TI1 is connected to CAN RTP */
#define TIM_TIM12_TI1_GPIO 0x00000000U /*!< TIM12 TI1 is connected to GPIO */
#define TIM_TIM12_TI1_SPDIF_FS TIM_TISEL_TI1SEL_0 /*!< TIM12 TI1 is connected to SPDIF FS */
#define TIM_TIM15_TI1_GPIO 0x00000000U /*!< TIM15_TI1 is connected to GPIO */
#define TIM_TIM15_TI1_TIM2_CH1 TIM_TISEL_TI1SEL_0 /*!< TIM15_TI1 is connected to TIM2 CH1 */
#define TIM_TIM15_TI1_TIM3_CH1 TIM_TISEL_TI1SEL_1 /*!< TIM15_TI1 is connected to TIM3 CH1 */
#define TIM_TIM15_TI1_TIM4_CH1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM15_TI1 is connected to TIM4 CH1 */
#define TIM_TIM15_TI1_RCC_LSE (TIM_TISEL_TI1SEL_2) /*!< TIM15_TI1 is connected to RCC LSE */
#define TIM_TIM15_TI1_RCC_CSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM15_TI1 is connected to RCC CSI */
#define TIM_TIM15_TI1_RCC_MCO2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM15_TI1 is connected to RCC MCO2 */
#define TIM_TIM15_TI2_GPIO 0x00000000U /*!< TIM15_TI2 is connected to GPIO */
#define TIM_TIM15_TI2_TIM2_CH2 (TIM_TISEL_TI2SEL_0) /*!< TIM15_TI2 is connected to TIM2 CH2 */
#define TIM_TIM15_TI2_TIM3_CH2 (TIM_TISEL_TI2SEL_1) /*!< TIM15_TI2 is connected to TIM3 CH2 */
#define TIM_TIM15_TI2_TIM4_CH2 (TIM_TISEL_TI2SEL_0 | TIM_TISEL_TI2SEL_1) /*!< TIM15_TI2 is connected to TIM4 CH2 */
#define TIM_TIM16_TI1_GPIO 0x00000000U /*!< TIM16 TI1 is connected to GPIO */
#define TIM_TIM16_TI1_RCC_LSI TIM_TISEL_TI1SEL_0 /*!< TIM16 TI1 is connected to RCC LSI */
#define TIM_TIM16_TI1_RCC_LSE TIM_TISEL_TI1SEL_1 /*!< TIM16 TI1 is connected to RCC LSE */
#define TIM_TIM16_TI1_WKUP_IT (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM16 TI1 is connected to WKUP_IT */
#define TIM_TIM17_TI1_GPIO 0x00000000U /*!< TIM17 TI1 is connected to GPIO */
#define TIM_TIM17_TI1_SPDIF_FS TIM_TISEL_TI1SEL_0 /*!< TIM17 TI1 is connected to SPDIF FS */
#define TIM_TIM17_TI1_RCC_HSE1MHZ TIM_TISEL_TI1SEL_1 /*!< TIM17 TI1 is connected to RCC HSE 1Mhz */
#define TIM_TIM17_TI1_RCC_MCO1 (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /*!< TIM17 TI1 is connected to RCC MCO1 */
#define TIM_TIM23_TI4_GPIO 0x00000000U /*!< TIM23_TI4 is connected to GPIO */
#define TIM_TIM23_TI4_COMP1 TIM_TISEL_TI4SEL_0 /*!< TIM23_TI4 is connected to COMP1 OUT */
#define TIM_TIM23_TI4_COMP2 TIM_TISEL_TI4SEL_1 /*!< TIM23_TI4 is connected to COMP2 OUT */
#define TIM_TIM23_TI4_COMP1_COMP2 (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /*!< TIM23_TI4 is connected to COMP1 OUT or COMP2 OUT */
#define TIM_TIM24_TI1_GPIO 0x00000000U /*!< TIM24_TI1 is connected to GPIO */
#define TIM_TIM24_TI1_CAN_TMP TIM_TISEL_TI1SEL_0 /*!< TIM24_TI1 is connected to CAN TMP */
#define TIM_TIM24_TI1_CAN_RTP TIM_TISEL_TI1SEL_1 /*!< TIM24_TI1 is connected to CAN RTP */
#define TIM_TIM24_TI1_CAN_SOC (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /*!< TIM24_TI1 is connected to CAN SOC */
/**
* @}
*/
/**
* @}
*/
/* End of exported constants -------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
* @{
*/
/**
* @}
*/
/* End of exported macro -----------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
* @{
*/
#define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \
((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))
#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \
((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \
((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM1))
#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \
((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))
#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \
((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))
#define IS_TIM_TISEL(__TISEL__) (((__TISEL__) == TIM_TIM1_TI1_GPIO) ||\
((__TISEL__) == TIM_TIM1_TI1_COMP1) ||\
((__TISEL__) == TIM_TIM8_TI1_GPIO) ||\
((__TISEL__) == TIM_TIM8_TI1_COMP2) ||\
((__TISEL__) == TIM_TIM2_TI4_GPIO) ||\
((__TISEL__) == TIM_TIM2_TI4_COMP1) ||\
((__TISEL__) == TIM_TIM2_TI4_COMP2) ||\
((__TISEL__) == TIM_TIM2_TI4_COMP1_COMP2) ||\
((__TISEL__) == TIM_TIM3_TI1_GPIO) ||\
((__TISEL__) == TIM_TIM3_TI1_COMP1) ||\
((__TISEL__) == TIM_TIM3_TI1_COMP2) ||\
((__TISEL__) == TIM_TIM3_TI1_COMP1_COMP2) ||\
((__TISEL__) == TIM_TIM5_TI1_GPIO) ||\
((__TISEL__) == TIM_TIM5_TI1_CAN_TMP) ||\
((__TISEL__) == TIM_TIM5_TI1_CAN_RTP) ||\
((__TISEL__) == TIM_TIM12_TI1_SPDIF_FS) ||\
((__TISEL__) == TIM_TIM12_TI1_GPIO) ||\
((__TISEL__) == TIM_TIM15_TI1_GPIO) ||\
((__TISEL__) == TIM_TIM15_TI1_TIM2_CH1) ||\
((__TISEL__) == TIM_TIM15_TI1_TIM3_CH1) ||\
((__TISEL__) == TIM_TIM15_TI1_TIM4_CH1) ||\
((__TISEL__) == TIM_TIM15_TI1_RCC_LSE) ||\
((__TISEL__) == TIM_TIM15_TI1_RCC_CSI) ||\
((__TISEL__) == TIM_TIM15_TI1_RCC_MCO2) ||\
((__TISEL__) == TIM_TIM15_TI2_GPIO) ||\
((__TISEL__) == TIM_TIM15_TI2_TIM2_CH2) ||\
((__TISEL__) == TIM_TIM15_TI2_TIM3_CH2) ||\
((__TISEL__) == TIM_TIM15_TI2_TIM4_CH2) ||\
((__TISEL__) == TIM_TIM16_TI1_GPIO) ||\
((__TISEL__) == TIM_TIM16_TI1_RCC_LSI) ||\
((__TISEL__) == TIM_TIM16_TI1_RCC_LSE) ||\
((__TISEL__) == TIM_TIM16_TI1_WKUP_IT) ||\
((__TISEL__) == TIM_TIM17_TI1_GPIO) ||\
((__TISEL__) == TIM_TIM17_TI1_SPDIF_FS) ||\
((__TISEL__) == TIM_TIM17_TI1_RCC_HSE1MHZ) ||\
((__TISEL__) == TIM_TIM17_TI1_RCC_MCO1) ||\
((__TISEL__) == TIM_TIM23_TI4_GPIO) ||\
((__TISEL__) == TIM_TIM23_TI4_COMP1) ||\
((__TISEL__) == TIM_TIM23_TI4_COMP2) ||\
((__TISEL__) == TIM_TIM23_TI4_COMP1_COMP2) ||\
((__TISEL__) == TIM_TIM24_TI1_GPIO) ||\
((__TISEL__) == TIM_TIM24_TI1_CAN_TMP) ||\
((__TISEL__) == TIM_TIM24_TI1_CAN_RTP) ||\
((__TISEL__) == TIM_TIM24_TI1_CAN_SOC))
#define IS_TIM_REMAP(__RREMAP__) (((__RREMAP__) == TIM_TIM1_ETR_GPIO) ||\
((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD1) ||\
((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD2) ||\
((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD3) ||\
((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD1) ||\
((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD2) ||\
((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD3) ||\
((__RREMAP__) == TIM_TIM1_ETR_COMP1) ||\
((__RREMAP__) == TIM_TIM1_ETR_COMP2) ||\
((__RREMAP__) == TIM_TIM8_ETR_GPIO) ||\
((__RREMAP__) == TIM_TIM8_ETR_ADC2_AWD1) ||\
((__RREMAP__) == TIM_TIM8_ETR_ADC2_AWD2) ||\
((__RREMAP__) == TIM_TIM8_ETR_ADC2_AWD3) ||\
((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD1) ||\
((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD2) ||\
((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD3) ||\
((__RREMAP__) == TIM_TIM8_ETR_COMP1) ||\
((__RREMAP__) == TIM_TIM8_ETR_COMP2) ||\
((__RREMAP__) == TIM_TIM2_ETR_GPIO) ||\
((__RREMAP__) == TIM_TIM2_ETR_COMP1) ||\
((__RREMAP__) == TIM_TIM2_ETR_COMP2) ||\
((__RREMAP__) == TIM_TIM2_ETR_RCC_LSE) ||\
((__RREMAP__) == TIM_TIM2_ETR_SAI1_FSA) ||\
((__RREMAP__) == TIM_TIM2_ETR_SAI1_FSB) ||\
((__RREMAP__) == TIM_TIM3_ETR_GPIO) ||\
((__RREMAP__) == TIM_TIM3_ETR_COMP1) ||\
((__RREMAP__) == TIM_TIM5_ETR_GPIO) ||\
((__RREMAP__) == TIM_TIM5_ETR_SAI2_FSA) ||\
((__RREMAP__) == TIM_TIM5_ETR_SAI2_FSB) ||\
((__RREMAP__) == TIM_TIM23_ETR_GPIO) ||\
((__RREMAP__) == TIM_TIM23_ETR_COMP1) ||\
((__RREMAP__) == TIM_TIM23_ETR_COMP2) ||\
((__RREMAP__) == TIM_TIM24_ETR_GPIO) ||\
((__RREMAP__) == TIM_TIM24_ETR_SAI4_FSA) ||\
((__RREMAP__) == TIM_TIM24_ETR_SAI4_FSB) ||\
((__RREMAP__) == TIM_TIM24_ETR_SAI1_FSA) ||\
((__RREMAP__) == TIM_TIM24_ETR_SAI1_FSB))
/**
* @}
*/
/* End of private macro ------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
* @{
*/
/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
* @brief Timer Hall Sensor functions
* @{
*/
/* Timer Hall Sensor functions **********************************************/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
/**
* @}
*/
/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
* @brief Timer Complementary Output Compare functions
* @{
*/
/* Timer Complementary Output Compare functions *****************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
uint16_t Length);
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
/**
* @}
*/
/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
* @brief Timer Complementary PWM functions
* @{
*/
/* Timer Complementary PWM functions ****************************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData,
uint16_t Length);
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
/**
* @}
*/
/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
* @brief Timer Complementary One Pulse functions
* @{
*/
/* Timer Complementary One Pulse functions **********************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
/**
* @}
*/
/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
* @brief Peripheral Control functions
* @{
*/
/* Extended Control functions ************************************************/
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
const TIM_MasterConfigTypeDef *sMasterConfig);
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
#if defined(TIM_BREAK_INPUT_SUPPORT)
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput,
const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
#endif /* TIM_BREAK_INPUT_SUPPORT */
HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel);
#if defined(TIM_BDTR_BKBID)
HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput);
HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim, uint32_t BreakInput);
#endif /* TIM_BDTR_BKBID */
/**
* @}
*/
/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
* @brief Extended Callbacks functions
* @{
*/
/* Extended Callback **********************************************************/
void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);
void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);
void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim);
/**
* @}
*/
/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
* @brief Extended Peripheral State functions
* @{
*/
/* Extended Peripheral State functions ***************************************/
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim);
HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN);
/**
* @}
*/
/**
* @}
*/
/* End of exported functions -------------------------------------------------*/
/* Private functions----------------------------------------------------------*/
/** @addtogroup TIMEx_Private_Functions TIM Extended Private Functions
* @{
*/
void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);
/**
* @}
*/
/* End of private functions --------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32H7xx_HAL_TIM_EX_H */

8412
AMS_Master_Code/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_adc.h Normal file
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216
AMS_Master_Code/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dma.h
View File

@ -140,7 +140,7 @@ typedef struct
This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */ This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
uint32_t PeriphRequest; /*!< Specifies the peripheral request. uint32_t PeriphRequest; /*!< Specifies the peripheral request.
This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST This parameter can be a value of @ref DMAMUX1_Request_selection
This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */ This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
@ -486,7 +486,7 @@ typedef struct
* @arg @ref LL_DMA_STREAM_7 * @arg @ref LL_DMA_STREAM_7
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMA_EnableStream(const DMA_TypeDef *DMAx, uint32_t Stream) __STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -508,7 +508,7 @@ __STATIC_INLINE void LL_DMA_EnableStream(const DMA_TypeDef *DMAx, uint32_t Strea
* @arg @ref LL_DMA_STREAM_7 * @arg @ref LL_DMA_STREAM_7
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMA_DisableStream(const DMA_TypeDef *DMAx, uint32_t Stream) __STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -530,7 +530,7 @@ __STATIC_INLINE void LL_DMA_DisableStream(const DMA_TypeDef *DMAx, uint32_t Stre
* @arg @ref LL_DMA_STREAM_7 * @arg @ref LL_DMA_STREAM_7
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(const DMA_TypeDef *DMAx, uint32_t Stream) __STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -571,7 +571,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(const DMA_TypeDef *DMAx, uint32_
* @arg @ref LL_DMA_CURRENTTARGETMEM0 or @ref LL_DMA_CURRENTTARGETMEM1 * @arg @ref LL_DMA_CURRENTTARGETMEM0 or @ref LL_DMA_CURRENTTARGETMEM1
*@retval None *@retval None
*/ */
__STATIC_INLINE void LL_DMA_ConfigTransfer(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration) __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -599,7 +599,7 @@ __STATIC_INLINE void LL_DMA_ConfigTransfer(const DMA_TypeDef *DMAx, uint32_t Str
* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMA_SetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction) __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -624,7 +624,7 @@ __STATIC_INLINE void LL_DMA_SetDataTransferDirection(const DMA_TypeDef *DMAx, ui
* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
*/ */
__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Stream) __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -651,7 +651,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(const DMA_TypeDef *DMAx
* @arg @ref LL_DMA_MODE_PFCTRL * @arg @ref LL_DMA_MODE_PFCTRL
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMA_SetMode(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode) __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -677,7 +677,7 @@ __STATIC_INLINE void LL_DMA_SetMode(const DMA_TypeDef *DMAx, uint32_t Stream, ui
* @arg @ref LL_DMA_MODE_CIRCULAR * @arg @ref LL_DMA_MODE_CIRCULAR
* @arg @ref LL_DMA_MODE_PFCTRL * @arg @ref LL_DMA_MODE_PFCTRL
*/ */
__STATIC_INLINE uint32_t LL_DMA_GetMode(const DMA_TypeDef *DMAx, uint32_t Stream) __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -702,7 +702,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMode(const DMA_TypeDef *DMAx, uint32_t Stream
* @arg @ref LL_DMA_PERIPH_INCREMENT * @arg @ref LL_DMA_PERIPH_INCREMENT
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMA_SetPeriphIncMode(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -726,7 +726,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphIncMode(const DMA_TypeDef *DMAx, uint32_t S
* @arg @ref LL_DMA_PERIPH_NOINCREMENT * @arg @ref LL_DMA_PERIPH_NOINCREMENT
* @arg @ref LL_DMA_PERIPH_INCREMENT * @arg @ref LL_DMA_PERIPH_INCREMENT
*/ */
__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(const DMA_TypeDef *DMAx, uint32_t Stream) __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -751,7 +751,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(const DMA_TypeDef *DMAx, uint32
* @arg @ref LL_DMA_MEMORY_INCREMENT * @arg @ref LL_DMA_MEMORY_INCREMENT
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMA_SetMemoryIncMode(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -775,7 +775,7 @@ __STATIC_INLINE void LL_DMA_SetMemoryIncMode(const DMA_TypeDef *DMAx, uint32_t S
* @arg @ref LL_DMA_MEMORY_NOINCREMENT * @arg @ref LL_DMA_MEMORY_NOINCREMENT
* @arg @ref LL_DMA_MEMORY_INCREMENT * @arg @ref LL_DMA_MEMORY_INCREMENT
*/ */
__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(const DMA_TypeDef *DMAx, uint32_t Stream) __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -801,7 +801,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(const DMA_TypeDef *DMAx, uint32
* @arg @ref LL_DMA_PDATAALIGN_WORD * @arg @ref LL_DMA_PDATAALIGN_WORD
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMA_SetPeriphSize(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -826,7 +826,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphSize(const DMA_TypeDef *DMAx, uint32_t Stre
* @arg @ref LL_DMA_PDATAALIGN_HALFWORD * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
* @arg @ref LL_DMA_PDATAALIGN_WORD * @arg @ref LL_DMA_PDATAALIGN_WORD
*/ */
__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(const DMA_TypeDef *DMAx, uint32_t Stream) __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -852,7 +852,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(const DMA_TypeDef *DMAx, uint32_t
* @arg @ref LL_DMA_MDATAALIGN_WORD * @arg @ref LL_DMA_MDATAALIGN_WORD
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMA_SetMemorySize(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -877,7 +877,7 @@ __STATIC_INLINE void LL_DMA_SetMemorySize(const DMA_TypeDef *DMAx, uint32_t Stre
* @arg @ref LL_DMA_MDATAALIGN_HALFWORD * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
* @arg @ref LL_DMA_MDATAALIGN_WORD * @arg @ref LL_DMA_MDATAALIGN_WORD
*/ */
__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(const DMA_TypeDef *DMAx, uint32_t Stream) __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -902,7 +902,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(const DMA_TypeDef *DMAx, uint32_t
* @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMA_SetIncOffsetSize(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize) __STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -926,7 +926,7 @@ __STATIC_INLINE void LL_DMA_SetIncOffsetSize(const DMA_TypeDef *DMAx, uint32_t S
* @arg @ref LL_DMA_OFFSETSIZE_PSIZE * @arg @ref LL_DMA_OFFSETSIZE_PSIZE
* @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
*/ */
__STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(const DMA_TypeDef *DMAx, uint32_t Stream) __STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -953,7 +953,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(const DMA_TypeDef *DMAx, uint32
* @arg @ref LL_DMA_PRIORITY_VERYHIGH * @arg @ref LL_DMA_PRIORITY_VERYHIGH
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority) __STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -979,7 +979,7 @@ __STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(const DMA_TypeDef *DMAx, uint
* @arg @ref LL_DMA_PRIORITY_HIGH * @arg @ref LL_DMA_PRIORITY_HIGH
* @arg @ref LL_DMA_PRIORITY_VERYHIGH * @arg @ref LL_DMA_PRIORITY_VERYHIGH
*/ */
__STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Stream) __STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -1001,7 +1001,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(const DMA_TypeDef *DMAx,
* @arg @ref LL_DMA_STREAM_7 * @arg @ref LL_DMA_STREAM_7
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMA_EnableBufferableTransfer(const DMA_TypeDef *DMAx, uint32_t Stream) __STATIC_INLINE void LL_DMA_EnableBufferableTransfer(DMA_TypeDef *DMAx, uint32_t Stream)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -1023,7 +1023,7 @@ __STATIC_INLINE void LL_DMA_EnableBufferableTransfer(const DMA_TypeDef *DMAx, ui
* @arg @ref LL_DMA_STREAM_7 * @arg @ref LL_DMA_STREAM_7
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMA_DisableBufferableTransfer(const DMA_TypeDef *DMAx, uint32_t Stream) __STATIC_INLINE void LL_DMA_DisableBufferableTransfer(DMA_TypeDef *DMAx, uint32_t Stream)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -1048,7 +1048,7 @@ __STATIC_INLINE void LL_DMA_DisableBufferableTransfer(const DMA_TypeDef *DMAx, u
* @param NbData Between 0 to 0xFFFFFFFF * @param NbData Between 0 to 0xFFFFFFFF
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMA_SetDataLength(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t NbData) __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t NbData)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -1072,7 +1072,7 @@ __STATIC_INLINE void LL_DMA_SetDataLength(const DMA_TypeDef *DMAx, uint32_t Stre
* @arg @ref LL_DMA_STREAM_7 * @arg @ref LL_DMA_STREAM_7
* @retval Between 0 to 0xFFFFFFFF * @retval Between 0 to 0xFFFFFFFF
*/ */
__STATIC_INLINE uint32_t LL_DMA_GetDataLength(const DMA_TypeDef *DMAx, uint32_t Stream) __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Stream)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -1396,7 +1396,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Stream,
* *
* @note (*) Availability depends on devices. * @note (*) Availability depends on devices.
*/ */
__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t Stream) __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Stream)
{ {
return (READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * (Stream)) + (uint32_t)(DMAMUX_CCR_SIZE * LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx)))))->CCR, DMAMUX_CxCR_DMAREQ_ID)); return (READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * (Stream)) + (uint32_t)(DMAMUX_CCR_SIZE * LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx)))))->CCR, DMAMUX_CxCR_DMAREQ_ID));
} }
@ -1421,7 +1421,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(const DMA_TypeDef *DMAx, uint3
* @arg @ref LL_DMA_MBURST_INC16 * @arg @ref LL_DMA_MBURST_INC16
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst) __STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -1447,7 +1447,7 @@ __STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(const DMA_TypeDef *DMAx, uint32_t
* @arg @ref LL_DMA_MBURST_INC8 * @arg @ref LL_DMA_MBURST_INC8
* @arg @ref LL_DMA_MBURST_INC16 * @arg @ref LL_DMA_MBURST_INC16
*/ */
__STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(const DMA_TypeDef *DMAx, uint32_t Stream) __STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -1474,7 +1474,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(const DMA_TypeDef *DMAx, uint
* @arg @ref LL_DMA_PBURST_INC16 * @arg @ref LL_DMA_PBURST_INC16
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst) __STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -1500,7 +1500,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(const DMA_TypeDef *DMAx, uint32_t
* @arg @ref LL_DMA_PBURST_INC8 * @arg @ref LL_DMA_PBURST_INC8
* @arg @ref LL_DMA_PBURST_INC16 * @arg @ref LL_DMA_PBURST_INC16
*/ */
__STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(const DMA_TypeDef *DMAx, uint32_t Stream) __STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -1525,7 +1525,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(const DMA_TypeDef *DMAx, uint
* @arg @ref LL_DMA_CURRENTTARGETMEM1 * @arg @ref LL_DMA_CURRENTTARGETMEM1
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMA_SetCurrentTargetMem(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory) __STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -1549,7 +1549,7 @@ __STATIC_INLINE void LL_DMA_SetCurrentTargetMem(const DMA_TypeDef *DMAx, uint32_
* @arg @ref LL_DMA_CURRENTTARGETMEM0 * @arg @ref LL_DMA_CURRENTTARGETMEM0
* @arg @ref LL_DMA_CURRENTTARGETMEM1 * @arg @ref LL_DMA_CURRENTTARGETMEM1
*/ */
__STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(const DMA_TypeDef *DMAx, uint32_t Stream) __STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -1571,7 +1571,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(const DMA_TypeDef *DMAx, uin
* @arg @ref LL_DMA_STREAM_7 * @arg @ref LL_DMA_STREAM_7
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(const DMA_TypeDef *DMAx, uint32_t Stream) __STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -1593,7 +1593,7 @@ __STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(const DMA_TypeDef *DMAx, uint
* @arg @ref LL_DMA_STREAM_7 * @arg @ref LL_DMA_STREAM_7
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(const DMA_TypeDef *DMAx, uint32_t Stream) __STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -1615,9 +1615,9 @@ __STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(const DMA_TypeDef *DMAx, uin
* @arg @ref LL_DMA_STREAM_7 * @arg @ref LL_DMA_STREAM_7
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMA_IsEnabledDoubleBufferMode(const DMA_TypeDef *DMAx, uint32_t Stream) __STATIC_INLINE uint32_t LL_DMA_IsEnabledDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; register uint32_t dma_base_addr = (uint32_t)DMAx;
return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM) == (DMA_SxCR_DBM)) ? 1UL : 0UL); return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM) == (DMA_SxCR_DBM)) ? 1UL : 0UL);
} }
@ -1643,7 +1643,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledDoubleBufferMode(const DMA_TypeDef *DMA
* @arg @ref LL_DMA_FIFOSTATUS_EMPTY * @arg @ref LL_DMA_FIFOSTATUS_EMPTY
* @arg @ref LL_DMA_FIFOSTATUS_FULL * @arg @ref LL_DMA_FIFOSTATUS_FULL
*/ */
__STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(const DMA_TypeDef *DMAx, uint32_t Stream) __STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -1665,7 +1665,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(const DMA_TypeDef *DMAx, uint32_t
* @arg @ref LL_DMA_STREAM_7 * @arg @ref LL_DMA_STREAM_7
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMA_DisableFifoMode(const DMA_TypeDef *DMAx, uint32_t Stream) __STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -1687,7 +1687,7 @@ __STATIC_INLINE void LL_DMA_DisableFifoMode(const DMA_TypeDef *DMAx, uint32_t St
* @arg @ref LL_DMA_STREAM_7 * @arg @ref LL_DMA_STREAM_7
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMA_EnableFifoMode(const DMA_TypeDef *DMAx, uint32_t Stream) __STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -1714,7 +1714,7 @@ __STATIC_INLINE void LL_DMA_EnableFifoMode(const DMA_TypeDef *DMAx, uint32_t Str
* @arg @ref LL_DMA_FIFOTHRESHOLD_FULL * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMA_SetFIFOThreshold(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold) __STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -1740,7 +1740,7 @@ __STATIC_INLINE void LL_DMA_SetFIFOThreshold(const DMA_TypeDef *DMAx, uint32_t S
* @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
* @arg @ref LL_DMA_FIFOTHRESHOLD_FULL * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
*/ */
__STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(const DMA_TypeDef *DMAx, uint32_t Stream) __STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -1771,7 +1771,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(const DMA_TypeDef *DMAx, uint32
* @arg @ref LL_DMA_FIFOTHRESHOLD_FULL * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMA_ConfigFifo(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold) __STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -1801,7 +1801,7 @@ __STATIC_INLINE void LL_DMA_ConfigFifo(const DMA_TypeDef *DMAx, uint32_t Stream,
* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMA_ConfigAddresses(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction) __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -1837,7 +1837,7 @@ __STATIC_INLINE void LL_DMA_ConfigAddresses(const DMA_TypeDef *DMAx, uint32_t St
* @param MemoryAddress Between 0 to 0xFFFFFFFF * @param MemoryAddress Between 0 to 0xFFFFFFFF
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMA_SetMemoryAddress(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress) __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -1862,7 +1862,7 @@ __STATIC_INLINE void LL_DMA_SetMemoryAddress(const DMA_TypeDef *DMAx, uint32_t S
* @param PeriphAddress Between 0 to 0xFFFFFFFF * @param PeriphAddress Between 0 to 0xFFFFFFFF
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMA_SetPeriphAddress(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t PeriphAddress) __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t PeriphAddress)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -1885,7 +1885,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphAddress(const DMA_TypeDef *DMAx, uint32_t S
* @arg @ref LL_DMA_STREAM_7 * @arg @ref LL_DMA_STREAM_7
* @retval Between 0 to 0xFFFFFFFF * @retval Between 0 to 0xFFFFFFFF
*/ */
__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(const DMA_TypeDef *DMAx, uint32_t Stream) __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Stream)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -1908,7 +1908,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(const DMA_TypeDef *DMAx, uint32
* @arg @ref LL_DMA_STREAM_7 * @arg @ref LL_DMA_STREAM_7
* @retval Between 0 to 0xFFFFFFFF * @retval Between 0 to 0xFFFFFFFF
*/ */
__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(const DMA_TypeDef *DMAx, uint32_t Stream) __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Stream)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -1933,7 +1933,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(const DMA_TypeDef *DMAx, uint32
* @param MemoryAddress Between 0 to 0xFFFFFFFF * @param MemoryAddress Between 0 to 0xFFFFFFFF
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress) __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -1958,7 +1958,7 @@ __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(const DMA_TypeDef *DMAx, uint32_t S
* @param MemoryAddress Between 0 to 0xFFFFFFFF * @param MemoryAddress Between 0 to 0xFFFFFFFF
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMA_SetM2MDstAddress(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress) __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -1981,7 +1981,7 @@ __STATIC_INLINE void LL_DMA_SetM2MDstAddress(const DMA_TypeDef *DMAx, uint32_t S
* @arg @ref LL_DMA_STREAM_7 * @arg @ref LL_DMA_STREAM_7
* @retval Between 0 to 0xFFFFFFFF * @retval Between 0 to 0xFFFFFFFF
*/ */
__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(const DMA_TypeDef *DMAx, uint32_t Stream) __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Stream)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -2004,7 +2004,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(const DMA_TypeDef *DMAx, uint32
* @arg @ref LL_DMA_STREAM_7 * @arg @ref LL_DMA_STREAM_7
* @retval Between 0 to 0xFFFFFFFF * @retval Between 0 to 0xFFFFFFFF
*/ */
__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(const DMA_TypeDef *DMAx, uint32_t Stream) __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Stream)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -2027,7 +2027,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(const DMA_TypeDef *DMAx, uint32
* @param Address Between 0 to 0xFFFFFFFF * @param Address Between 0 to 0xFFFFFFFF
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMA_SetMemory1Address(const DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address) __STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -2049,7 +2049,7 @@ __STATIC_INLINE void LL_DMA_SetMemory1Address(const DMA_TypeDef *DMAx, uint32_t
* @arg @ref LL_DMA_STREAM_7 * @arg @ref LL_DMA_STREAM_7
* @retval Between 0 to 0xFFFFFFFF * @retval Between 0 to 0xFFFFFFFF
*/ */
__STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(const DMA_TypeDef *DMAx, uint32_t Stream) __STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -2070,7 +2070,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(const DMA_TypeDef *DMAx, uint3
* @param DMAx DMAx Instance * @param DMAx DMAx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(const DMA_TypeDef *DMAx) __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx)
{ {
return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF0) == (DMA_LISR_HTIF0)) ? 1UL : 0UL); return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF0) == (DMA_LISR_HTIF0)) ? 1UL : 0UL);
} }
@ -2081,7 +2081,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(const DMA_TypeDef *DMAx)
* @param DMAx DMAx Instance * @param DMAx DMAx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(const DMA_TypeDef *DMAx) __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
{ {
return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF1) == (DMA_LISR_HTIF1)) ? 1UL : 0UL); return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF1) == (DMA_LISR_HTIF1)) ? 1UL : 0UL);
} }
@ -2092,7 +2092,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(const DMA_TypeDef *DMAx)
* @param DMAx DMAx Instance * @param DMAx DMAx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(const DMA_TypeDef *DMAx) __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
{ {
return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF2) == (DMA_LISR_HTIF2)) ? 1UL : 0UL); return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF2) == (DMA_LISR_HTIF2)) ? 1UL : 0UL);
} }
@ -2103,7 +2103,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(const DMA_TypeDef *DMAx)
* @param DMAx DMAx Instance * @param DMAx DMAx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(const DMA_TypeDef *DMAx) __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
{ {
return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF3) == (DMA_LISR_HTIF3)) ? 1UL : 0UL); return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF3) == (DMA_LISR_HTIF3)) ? 1UL : 0UL);
} }
@ -2114,7 +2114,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(const DMA_TypeDef *DMAx)
* @param DMAx DMAx Instance * @param DMAx DMAx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(const DMA_TypeDef *DMAx) __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
{ {
return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF4) == (DMA_HISR_HTIF4)) ? 1UL : 0UL); return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF4) == (DMA_HISR_HTIF4)) ? 1UL : 0UL);
} }
@ -2125,7 +2125,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(const DMA_TypeDef *DMAx)
* @param DMAx DMAx Instance * @param DMAx DMAx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(const DMA_TypeDef *DMAx) __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
{ {
return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF5) == (DMA_HISR_HTIF5)) ? 1UL : 0UL); return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF5) == (DMA_HISR_HTIF5)) ? 1UL : 0UL);
} }
@ -2136,7 +2136,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(const DMA_TypeDef *DMAx)
* @param DMAx DMAx Instance * @param DMAx DMAx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(const DMA_TypeDef *DMAx) __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
{ {
return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF6) == (DMA_HISR_HTIF6)) ? 1UL : 0UL); return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF6) == (DMA_HISR_HTIF6)) ? 1UL : 0UL);
} }
@ -2147,7 +2147,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(const DMA_TypeDef *DMAx)
* @param DMAx DMAx Instance * @param DMAx DMAx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(const DMA_TypeDef *DMAx) __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
{ {
return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF7) == (DMA_HISR_HTIF7)) ? 1UL : 0UL); return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF7) == (DMA_HISR_HTIF7)) ? 1UL : 0UL);
} }
@ -2158,7 +2158,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(const DMA_TypeDef *DMAx)
* @param DMAx DMAx Instance * @param DMAx DMAx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(const DMA_TypeDef *DMAx) __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx)
{ {
return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF0) == (DMA_LISR_TCIF0)) ? 1UL : 0UL); return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF0) == (DMA_LISR_TCIF0)) ? 1UL : 0UL);
} }
@ -2169,7 +2169,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(const DMA_TypeDef *DMAx)
* @param DMAx DMAx Instance * @param DMAx DMAx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(const DMA_TypeDef *DMAx) __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
{ {
return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF1) == (DMA_LISR_TCIF1)) ? 1UL : 0UL); return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF1) == (DMA_LISR_TCIF1)) ? 1UL : 0UL);
} }
@ -2180,7 +2180,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(const DMA_TypeDef *DMAx)
* @param DMAx DMAx Instance * @param DMAx DMAx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(const DMA_TypeDef *DMAx) __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
{ {
return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF2) == (DMA_LISR_TCIF2)) ? 1UL : 0UL); return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF2) == (DMA_LISR_TCIF2)) ? 1UL : 0UL);
} }
@ -2191,7 +2191,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(const DMA_TypeDef *DMAx)
* @param DMAx DMAx Instance * @param DMAx DMAx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(const DMA_TypeDef *DMAx) __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
{ {
return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF3) == (DMA_LISR_TCIF3)) ? 1UL : 0UL); return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF3) == (DMA_LISR_TCIF3)) ? 1UL : 0UL);
} }
@ -2202,7 +2202,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(const DMA_TypeDef *DMAx)
* @param DMAx DMAx Instance * @param DMAx DMAx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(const DMA_TypeDef *DMAx) __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
{ {
return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF4) == (DMA_HISR_TCIF4)) ? 1UL : 0UL); return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF4) == (DMA_HISR_TCIF4)) ? 1UL : 0UL);
} }
@ -2213,7 +2213,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(const DMA_TypeDef *DMAx)
* @param DMAx DMAx Instance * @param DMAx DMAx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(const DMA_TypeDef *DMAx) __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
{ {
return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF5) == (DMA_HISR_TCIF5)) ? 1UL : 0UL); return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF5) == (DMA_HISR_TCIF5)) ? 1UL : 0UL);
} }
@ -2224,7 +2224,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(const DMA_TypeDef *DMAx)
* @param DMAx DMAx Instance * @param DMAx DMAx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(const DMA_TypeDef *DMAx) __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
{ {
return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF6) == (DMA_HISR_TCIF6)) ? 1UL : 0UL); return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF6) == (DMA_HISR_TCIF6)) ? 1UL : 0UL);
} }
@ -2235,7 +2235,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(const DMA_TypeDef *DMAx)
* @param DMAx DMAx Instance * @param DMAx DMAx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(const DMA_TypeDef *DMAx) __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
{ {
return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF7) == (DMA_HISR_TCIF7)) ? 1UL : 0UL); return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF7) == (DMA_HISR_TCIF7)) ? 1UL : 0UL);
} }
@ -2246,7 +2246,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(const DMA_TypeDef *DMAx)
* @param DMAx DMAx Instance * @param DMAx DMAx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(const DMA_TypeDef *DMAx) __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx)
{ {
return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF0) == (DMA_LISR_TEIF0)) ? 1UL : 0UL); return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF0) == (DMA_LISR_TEIF0)) ? 1UL : 0UL);
} }
@ -2257,7 +2257,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(const DMA_TypeDef *DMAx)
* @param DMAx DMAx Instance * @param DMAx DMAx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(const DMA_TypeDef *DMAx) __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
{ {
return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF1) == (DMA_LISR_TEIF1)) ? 1UL : 0UL); return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF1) == (DMA_LISR_TEIF1)) ? 1UL : 0UL);
} }
@ -2268,7 +2268,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(const DMA_TypeDef *DMAx)
* @param DMAx DMAx Instance * @param DMAx DMAx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(const DMA_TypeDef *DMAx) __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
{ {
return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF2) == (DMA_LISR_TEIF2)) ? 1UL : 0UL); return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF2) == (DMA_LISR_TEIF2)) ? 1UL : 0UL);
} }
@ -2279,7 +2279,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(const DMA_TypeDef *DMAx)
* @param DMAx DMAx Instance * @param DMAx DMAx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(const DMA_TypeDef *DMAx) __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
{ {
return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF3) == (DMA_LISR_TEIF3)) ? 1UL : 0UL); return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF3) == (DMA_LISR_TEIF3)) ? 1UL : 0UL);
} }
@ -2290,7 +2290,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(const DMA_TypeDef *DMAx)
* @param DMAx DMAx Instance * @param DMAx DMAx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(const DMA_TypeDef *DMAx) __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
{ {
return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF4) == (DMA_HISR_TEIF4)) ? 1UL : 0UL); return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF4) == (DMA_HISR_TEIF4)) ? 1UL : 0UL);
} }
@ -2301,7 +2301,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(const DMA_TypeDef *DMAx)
* @param DMAx DMAx Instance * @param DMAx DMAx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(const DMA_TypeDef *DMAx) __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
{ {
return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF5) == (DMA_HISR_TEIF5)) ? 1UL : 0UL); return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF5) == (DMA_HISR_TEIF5)) ? 1UL : 0UL);
} }
@ -2312,7 +2312,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(const DMA_TypeDef *DMAx)
* @param DMAx DMAx Instance * @param DMAx DMAx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(const DMA_TypeDef *DMAx) __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
{ {
return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF6) == (DMA_HISR_TEIF6)) ? 1UL : 0UL); return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF6) == (DMA_HISR_TEIF6)) ? 1UL : 0UL);
} }
@ -2323,7 +2323,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(const DMA_TypeDef *DMAx)
* @param DMAx DMAx Instance * @param DMAx DMAx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(const DMA_TypeDef *DMAx) __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
{ {
return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF7) == (DMA_HISR_TEIF7)) ? 1UL : 0UL); return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF7) == (DMA_HISR_TEIF7)) ? 1UL : 0UL);
} }
@ -2334,7 +2334,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(const DMA_TypeDef *DMAx)
* @param DMAx DMAx Instance * @param DMAx DMAx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(const DMA_TypeDef *DMAx) __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx)
{ {
return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF0) == (DMA_LISR_DMEIF0)) ? 1UL : 0UL); return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF0) == (DMA_LISR_DMEIF0)) ? 1UL : 0UL);
} }
@ -2345,7 +2345,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(const DMA_TypeDef *DMAx)
* @param DMAx DMAx Instance * @param DMAx DMAx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(const DMA_TypeDef *DMAx) __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx)
{ {
return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF1) == (DMA_LISR_DMEIF1)) ? 1UL : 0UL); return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF1) == (DMA_LISR_DMEIF1)) ? 1UL : 0UL);
} }
@ -2356,7 +2356,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(const DMA_TypeDef *DMAx)
* @param DMAx DMAx Instance * @param DMAx DMAx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(const DMA_TypeDef *DMAx) __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx)
{ {
return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF2) == (DMA_LISR_DMEIF2)) ? 1UL : 0UL); return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF2) == (DMA_LISR_DMEIF2)) ? 1UL : 0UL);
} }
@ -2367,7 +2367,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(const DMA_TypeDef *DMAx)
* @param DMAx DMAx Instance * @param DMAx DMAx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(const DMA_TypeDef *DMAx) __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx)
{ {
return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF3) == (DMA_LISR_DMEIF3)) ? 1UL : 0UL); return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF3) == (DMA_LISR_DMEIF3)) ? 1UL : 0UL);
} }
@ -2378,7 +2378,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(const DMA_TypeDef *DMAx)
* @param DMAx DMAx Instance * @param DMAx DMAx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(const DMA_TypeDef *DMAx) __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx)
{ {
return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF4) == (DMA_HISR_DMEIF4)) ? 1UL : 0UL); return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF4) == (DMA_HISR_DMEIF4)) ? 1UL : 0UL);
} }
@ -2389,7 +2389,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(const DMA_TypeDef *DMAx)
* @param DMAx DMAx Instance * @param DMAx DMAx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(const DMA_TypeDef *DMAx) __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx)
{ {
return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF5) == (DMA_HISR_DMEIF5)) ? 1UL : 0UL); return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF5) == (DMA_HISR_DMEIF5)) ? 1UL : 0UL);
} }
@ -2400,7 +2400,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(const DMA_TypeDef *DMAx)
* @param DMAx DMAx Instance * @param DMAx DMAx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(const DMA_TypeDef *DMAx) __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx)
{ {
return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF6) == (DMA_HISR_DMEIF6)) ? 1UL : 0UL); return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF6) == (DMA_HISR_DMEIF6)) ? 1UL : 0UL);
} }
@ -2411,7 +2411,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(const DMA_TypeDef *DMAx)
* @param DMAx DMAx Instance * @param DMAx DMAx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(const DMA_TypeDef *DMAx) __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx)
{ {
return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF7) == (DMA_HISR_DMEIF7)) ? 1UL : 0UL); return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF7) == (DMA_HISR_DMEIF7)) ? 1UL : 0UL);
} }
@ -2422,7 +2422,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(const DMA_TypeDef *DMAx)
* @param DMAx DMAx Instance * @param DMAx DMAx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(const DMA_TypeDef *DMAx) __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx)
{ {
return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF0) == (DMA_LISR_FEIF0)) ? 1UL : 0UL); return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF0) == (DMA_LISR_FEIF0)) ? 1UL : 0UL);
} }
@ -2433,7 +2433,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(const DMA_TypeDef *DMAx)
* @param DMAx DMAx Instance * @param DMAx DMAx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(const DMA_TypeDef *DMAx) __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx)
{ {
return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF1) == (DMA_LISR_FEIF1)) ? 1UL : 0UL); return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF1) == (DMA_LISR_FEIF1)) ? 1UL : 0UL);
} }
@ -2444,7 +2444,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(const DMA_TypeDef *DMAx)
* @param DMAx DMAx Instance * @param DMAx DMAx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(const DMA_TypeDef *DMAx) __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx)
{ {
return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF2) == (DMA_LISR_FEIF2)) ? 1UL : 0UL); return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF2) == (DMA_LISR_FEIF2)) ? 1UL : 0UL);
} }
@ -2455,7 +2455,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(const DMA_TypeDef *DMAx)
* @param DMAx DMAx Instance * @param DMAx DMAx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(const DMA_TypeDef *DMAx) __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx)
{ {
return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF3) == (DMA_LISR_FEIF3)) ? 1UL : 0UL); return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF3) == (DMA_LISR_FEIF3)) ? 1UL : 0UL);
} }
@ -2466,7 +2466,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(const DMA_TypeDef *DMAx)
* @param DMAx DMAx Instance * @param DMAx DMAx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(const DMA_TypeDef *DMAx) __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx)
{ {
return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF4) == (DMA_HISR_FEIF4)) ? 1UL : 0UL); return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF4) == (DMA_HISR_FEIF4)) ? 1UL : 0UL);
} }
@ -2477,7 +2477,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(const DMA_TypeDef *DMAx)
* @param DMAx DMAx Instance * @param DMAx DMAx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(const DMA_TypeDef *DMAx) __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx)
{ {
return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF5) == (DMA_HISR_FEIF5)) ? 1UL : 0UL); return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF5) == (DMA_HISR_FEIF5)) ? 1UL : 0UL);
} }
@ -2488,7 +2488,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(const DMA_TypeDef *DMAx)
* @param DMAx DMAx Instance * @param DMAx DMAx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(const DMA_TypeDef *DMAx) __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx)
{ {
return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF6) == (DMA_HISR_FEIF6)) ? 1UL : 0UL); return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF6) == (DMA_HISR_FEIF6)) ? 1UL : 0UL);
} }
@ -2499,7 +2499,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(const DMA_TypeDef *DMAx)
* @param DMAx DMAx Instance * @param DMAx DMAx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(const DMA_TypeDef *DMAx) __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx)
{ {
return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF7) == (DMA_HISR_FEIF7)) ? 1UL : 0UL); return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF7) == (DMA_HISR_FEIF7)) ? 1UL : 0UL);
} }
@ -2967,7 +2967,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx)
* @arg @ref LL_DMA_STREAM_7 * @arg @ref LL_DMA_STREAM_7
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMA_EnableIT_HT(const DMA_TypeDef *DMAx, uint32_t Stream) __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -2989,7 +2989,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_HT(const DMA_TypeDef *DMAx, uint32_t Stream
* @arg @ref LL_DMA_STREAM_7 * @arg @ref LL_DMA_STREAM_7
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMA_EnableIT_TE(const DMA_TypeDef *DMAx, uint32_t Stream) __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -3011,7 +3011,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_TE(const DMA_TypeDef *DMAx, uint32_t Stream
* @arg @ref LL_DMA_STREAM_7 * @arg @ref LL_DMA_STREAM_7
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMA_EnableIT_TC(const DMA_TypeDef *DMAx, uint32_t Stream) __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -3033,7 +3033,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_TC(const DMA_TypeDef *DMAx, uint32_t Stream
* @arg @ref LL_DMA_STREAM_7 * @arg @ref LL_DMA_STREAM_7
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMA_EnableIT_DME(const DMA_TypeDef *DMAx, uint32_t Stream) __STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -3055,7 +3055,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_DME(const DMA_TypeDef *DMAx, uint32_t Strea
* @arg @ref LL_DMA_STREAM_7 * @arg @ref LL_DMA_STREAM_7
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMA_EnableIT_FE(const DMA_TypeDef *DMAx, uint32_t Stream) __STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -3077,7 +3077,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_FE(const DMA_TypeDef *DMAx, uint32_t Stream
* @arg @ref LL_DMA_STREAM_7 * @arg @ref LL_DMA_STREAM_7
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMA_DisableIT_HT(const DMA_TypeDef *DMAx, uint32_t Stream) __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -3099,7 +3099,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_HT(const DMA_TypeDef *DMAx, uint32_t Strea
* @arg @ref LL_DMA_STREAM_7 * @arg @ref LL_DMA_STREAM_7
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMA_DisableIT_TE(const DMA_TypeDef *DMAx, uint32_t Stream) __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -3121,7 +3121,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_TE(const DMA_TypeDef *DMAx, uint32_t Strea
* @arg @ref LL_DMA_STREAM_7 * @arg @ref LL_DMA_STREAM_7
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMA_DisableIT_TC(const DMA_TypeDef *DMAx, uint32_t Stream) __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -3143,7 +3143,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_TC(const DMA_TypeDef *DMAx, uint32_t Strea
* @arg @ref LL_DMA_STREAM_7 * @arg @ref LL_DMA_STREAM_7
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMA_DisableIT_DME(const DMA_TypeDef *DMAx, uint32_t Stream) __STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -3165,7 +3165,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_DME(const DMA_TypeDef *DMAx, uint32_t Stre
* @arg @ref LL_DMA_STREAM_7 * @arg @ref LL_DMA_STREAM_7
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMA_DisableIT_FE(const DMA_TypeDef *DMAx, uint32_t Stream) __STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -3187,7 +3187,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_FE(const DMA_TypeDef *DMAx, uint32_t Strea
* @arg @ref LL_DMA_STREAM_7 * @arg @ref LL_DMA_STREAM_7
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(const DMA_TypeDef *DMAx, uint32_t Stream) __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -3209,7 +3209,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(const DMA_TypeDef *DMAx, uint32_t
* @arg @ref LL_DMA_STREAM_7 * @arg @ref LL_DMA_STREAM_7
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(const DMA_TypeDef *DMAx, uint32_t Stream) __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -3231,7 +3231,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(const DMA_TypeDef *DMAx, uint32_t
* @arg @ref LL_DMA_STREAM_7 * @arg @ref LL_DMA_STREAM_7
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(const DMA_TypeDef *DMAx, uint32_t Stream) __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -3253,7 +3253,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(const DMA_TypeDef *DMAx, uint32_t
* @arg @ref LL_DMA_STREAM_7 * @arg @ref LL_DMA_STREAM_7
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(const DMA_TypeDef *DMAx, uint32_t Stream) __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;
@ -3275,7 +3275,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(const DMA_TypeDef *DMAx, uint32_
* @arg @ref LL_DMA_STREAM_7 * @arg @ref LL_DMA_STREAM_7
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(const DMA_TypeDef *DMAx, uint32_t Stream) __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
{ {
uint32_t dma_base_addr = (uint32_t)DMAx; uint32_t dma_base_addr = (uint32_t)DMAx;

154
AMS_Master_Code/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_dmamux.h
View File

@ -726,7 +726,7 @@ extern "C" {
* @note (*) Availability depends on devices. * @note (*) Availability depends on devices.
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMAMUX_SetRequestID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request) __STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -919,7 +919,7 @@ __STATIC_INLINE void LL_DMAMUX_SetRequestID(const DMAMUX_Channel_TypeDef *DMAMUX
* @note (*) Availability depends on devices. * @note (*) Availability depends on devices.
* @retval None * @retval None
*/ */
__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -950,7 +950,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(const DMAMUX_Channel_TypeDef *DM
* @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32. * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32.
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb) __STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -980,7 +980,7 @@ __STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(const DMAMUX_Channel_TypeDef *DM
* @arg @ref LL_DMAMUX_CHANNEL_15 * @arg @ref LL_DMAMUX_CHANNEL_15
* @retval Between Min_Data = 1 and Max_Data = 32 * @retval Between Min_Data = 1 and Max_Data = 32
*/ */
__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -1015,7 +1015,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(const DMAMUX_Channel_TypeDef
* @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity) __STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -1049,7 +1049,7 @@ __STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(const DMAMUX_Channel_TypeDef *DMA
* @arg @ref LL_DMAMUX_SYNC_POL_FALLING * @arg @ref LL_DMAMUX_SYNC_POL_FALLING
* @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING
*/ */
__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -1079,7 +1079,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(const DMAMUX_Channel_TypeDef
* @arg @ref LL_DMAMUX_CHANNEL_15 * @arg @ref LL_DMAMUX_CHANNEL_15
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) __STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -1109,7 +1109,7 @@ __STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(const DMAMUX_Channel_TypeDe
* @arg @ref LL_DMAMUX_CHANNEL_15 * @arg @ref LL_DMAMUX_CHANNEL_15
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) __STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -1139,7 +1139,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(const DMAMUX_Channel_TypeD
* @arg @ref LL_DMAMUX_CHANNEL_15 * @arg @ref LL_DMAMUX_CHANNEL_15
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -1169,7 +1169,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(const DMAMUX_Channel
* @arg @ref LL_DMAMUX_CHANNEL_15 * @arg @ref LL_DMAMUX_CHANNEL_15
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMAMUX_EnableSync(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) __STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -1199,7 +1199,7 @@ __STATIC_INLINE void LL_DMAMUX_EnableSync(const DMAMUX_Channel_TypeDef *DMAMUXx,
* @arg @ref LL_DMAMUX_CHANNEL_15 * @arg @ref LL_DMAMUX_CHANNEL_15
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMAMUX_DisableSync(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) __STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -1229,7 +1229,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableSync(const DMAMUX_Channel_TypeDef *DMAMUXx
* @arg @ref LL_DMAMUX_CHANNEL_15 * @arg @ref LL_DMAMUX_CHANNEL_15
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -1284,7 +1284,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(const DMAMUX_Channel_TypeDef *D
* @arg @ref LL_DMAMUX2_SYNC_EXTI2 * @arg @ref LL_DMAMUX2_SYNC_EXTI2
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMAMUX_SetSyncID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID) __STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -1338,7 +1338,7 @@ __STATIC_INLINE void LL_DMAMUX_SetSyncID(const DMAMUX_Channel_TypeDef *DMAMUXx,
* @arg @ref LL_DMAMUX2_SYNC_EXTI0 * @arg @ref LL_DMAMUX2_SYNC_EXTI0
* @arg @ref LL_DMAMUX2_SYNC_EXTI2 * @arg @ref LL_DMAMUX2_SYNC_EXTI2
*/ */
__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -1360,7 +1360,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(const DMAMUX_Channel_TypeDef *DMAMU
* @arg @ref LL_DMAMUX_REQ_GEN_7 * @arg @ref LL_DMAMUX_REQ_GEN_7
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMAMUX_EnableRequestGen(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) __STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -1378,7 +1378,7 @@ __STATIC_INLINE void LL_DMAMUX_EnableRequestGen(const DMAMUX_Channel_TypeDef *DM
* @arg @ref LL_DMAMUX_REQ_GEN_3 * @arg @ref LL_DMAMUX_REQ_GEN_3
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMAMUX_DisableRequestGen(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) __STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -1400,7 +1400,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableRequestGen(const DMAMUX_Channel_TypeDef *D
* @arg @ref LL_DMAMUX_REQ_GEN_7 * @arg @ref LL_DMAMUX_REQ_GEN_7
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -1427,7 +1427,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(const DMAMUX_Channel_Type
* @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity) __STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -1453,7 +1453,7 @@ __STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(const DMAMUX_Channel_TypeDe
* @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING
* @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
*/ */
__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -1477,7 +1477,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(const DMAMUX_Channel_Ty
* @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32. * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32.
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb) __STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -1499,7 +1499,7 @@ __STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(const DMAMUX_Channel_TypeDef *DMA
* @arg @ref LL_DMAMUX_REQ_GEN_7 * @arg @ref LL_DMAMUX_REQ_GEN_7
* @retval Between Min_Data = 1 and Max_Data = 32 * @retval Between Min_Data = 1 and Max_Data = 32
*/ */
__STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) __STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -1561,7 +1561,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(const DMAMUX_Channel_TypeDef
* @note (*) Availability depends on devices. * @note (*) Availability depends on devices.
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID) __STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -1607,7 +1607,7 @@ __STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(const DMAMUX_Channel_TypeDef *
* @arg @ref LL_DMAMUX2_SYNC_EXTI0 * @arg @ref LL_DMAMUX2_SYNC_EXTI0
* @arg @ref LL_DMAMUX2_SYNC_EXTI2 * @arg @ref LL_DMAMUX2_SYNC_EXTI2
*/ */
__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -1628,7 +1628,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(const DMAMUX_Channel_TypeD
* @param DMAMUXx DMAMUXx DMAMUXx Instance * @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(const DMAMUX_Channel_TypeDef *DMAMUXx) __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -1641,7 +1641,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(const DMAMUX_Channel_TypeDef
* @param DMAMUXx DMAMUXx DMAMUXx Instance * @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(const DMAMUX_Channel_TypeDef *DMAMUXx) __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -1654,7 +1654,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(const DMAMUX_Channel_TypeDef
* @param DMAMUXx DMAMUXx DMAMUXx Instance * @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(const DMAMUX_Channel_TypeDef *DMAMUXx) __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -1667,7 +1667,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(const DMAMUX_Channel_TypeDef
* @param DMAMUXx DMAMUXx DMAMUXx Instance * @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(const DMAMUX_Channel_TypeDef *DMAMUXx) __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -1680,7 +1680,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(const DMAMUX_Channel_TypeDef
* @param DMAMUXx DMAMUXx DMAMUXx Instance * @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(const DMAMUX_Channel_TypeDef *DMAMUXx) __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -1693,7 +1693,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(const DMAMUX_Channel_TypeDef
* @param DMAMUXx DMAMUXx DMAMUXx Instance * @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(const DMAMUX_Channel_TypeDef *DMAMUXx) __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -1706,7 +1706,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(const DMAMUX_Channel_TypeDef
* @param DMAMUXx DMAMUXx DMAMUXx Instance * @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(const DMAMUX_Channel_TypeDef *DMAMUXx) __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -1719,7 +1719,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(const DMAMUX_Channel_TypeDef
* @param DMAMUXx DMAMUXx DMAMUXx Instance * @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(const DMAMUX_Channel_TypeDef *DMAMUXx) __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -1732,7 +1732,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(const DMAMUX_Channel_TypeDef
* @param DMAMUXx DMAMUXx DMAMUXx Instance * @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(const DMAMUX_Channel_TypeDef *DMAMUXx) __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -1745,7 +1745,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(const DMAMUX_Channel_TypeDef
* @param DMAMUXx DMAMUXx DMAMUXx Instance * @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(const DMAMUX_Channel_TypeDef *DMAMUXx) __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -1758,7 +1758,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(const DMAMUX_Channel_TypeDef
* @param DMAMUXx DMAMUXx DMAMUXx Instance * @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(const DMAMUX_Channel_TypeDef *DMAMUXx) __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -1771,7 +1771,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(const DMAMUX_Channel_TypeDe
* @param DMAMUXx DMAMUXx DMAMUXx Instance * @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(const DMAMUX_Channel_TypeDef *DMAMUXx) __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -1784,7 +1784,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(const DMAMUX_Channel_TypeDe
* @param DMAMUXx DMAMUXx DMAMUXx Instance * @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(const DMAMUX_Channel_TypeDef *DMAMUXx) __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -1797,7 +1797,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(const DMAMUX_Channel_TypeDe
* @param DMAMUXx DMAMUXx DMAMUXx Instance * @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(const DMAMUX_Channel_TypeDef *DMAMUXx) __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -1810,7 +1810,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(const DMAMUX_Channel_TypeDe
* @param DMAMUXx DMAMUXx DMAMUXx Instance * @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO14(const DMAMUX_Channel_TypeDef *DMAMUXx) __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -1823,7 +1823,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO14(const DMAMUX_Channel_TypeDe
* @param DMAMUXx DMAMUXx DMAMUXx Instance * @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO15(const DMAMUX_Channel_TypeDef *DMAMUXx) __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -1836,7 +1836,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO15(const DMAMUX_Channel_TypeDe
* @param DMAMUXx DMAMUXx DMAMUXx Instance * @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(const DMAMUX_Channel_TypeDef *DMAMUXx) __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -1849,7 +1849,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(const DMAMUX_Channel_TypeDe
* @param DMAMUXx DMAMUXx DMAMUXx Instance * @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(const DMAMUX_Channel_TypeDef *DMAMUXx) __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -1862,7 +1862,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(const DMAMUX_Channel_TypeDe
* @param DMAMUXx DMAMUXx DMAMUXx Instance * @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(const DMAMUX_Channel_TypeDef *DMAMUXx) __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -1875,7 +1875,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(const DMAMUX_Channel_TypeDe
* @param DMAMUXx DMAMUXx DMAMUXx Instance * @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(const DMAMUX_Channel_TypeDef *DMAMUXx) __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -1888,7 +1888,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(const DMAMUX_Channel_TypeDe
* @param DMAMUXx DMAMUXx DMAMUXx Instance * @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO4(const DMAMUX_Channel_TypeDef *DMAMUXx) __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO4(DMAMUX_Channel_TypeDef *DMAMUXx)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -1901,7 +1901,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO4(const DMAMUX_Channel_TypeDe
* @param DMAMUXx DMAMUXx DMAMUXx Instance * @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO5(const DMAMUX_Channel_TypeDef *DMAMUXx) __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO5(DMAMUX_Channel_TypeDef *DMAMUXx)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -1914,7 +1914,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO5(const DMAMUX_Channel_TypeDe
* @param DMAMUXx DMAMUXx DMAMUXx Instance * @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO6(const DMAMUX_Channel_TypeDef *DMAMUXx) __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO6(DMAMUX_Channel_TypeDef *DMAMUXx)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -1927,7 +1927,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO6(const DMAMUX_Channel_TypeDe
* @param DMAMUXx DMAMUXx DMAMUXx Instance * @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO7(const DMAMUX_Channel_TypeDef *DMAMUXx) __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO7(DMAMUX_Channel_TypeDef *DMAMUXx)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -1940,7 +1940,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO7(const DMAMUX_Channel_TypeDe
* @param DMAMUXx DMAMUXx DMAMUXx Instance * @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(const DMAMUX_Channel_TypeDef *DMAMUXx) __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -1953,7 +1953,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(const DMAMUX_Channel_TypeDef *DMAMU
* @param DMAMUXx DMAMUXx DMAMUXx Instance * @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(const DMAMUX_Channel_TypeDef *DMAMUXx) __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -1966,7 +1966,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(const DMAMUX_Channel_TypeDef *DMAMU
* @param DMAMUXx DMAMUXx DMAMUXx Instance * @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(const DMAMUX_Channel_TypeDef *DMAMUXx) __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -1979,7 +1979,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(const DMAMUX_Channel_TypeDef *DMAMU
* @param DMAMUXx DMAMUXx DMAMUXx Instance * @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(const DMAMUX_Channel_TypeDef *DMAMUXx) __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -1992,7 +1992,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(const DMAMUX_Channel_TypeDef *DMAMU
* @param DMAMUXx DMAMUXx DMAMUXx Instance * @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(const DMAMUX_Channel_TypeDef *DMAMUXx) __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -2005,7 +2005,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(const DMAMUX_Channel_TypeDef *DMAMU
* @param DMAMUXx DMAMUXx DMAMUXx Instance * @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(const DMAMUX_Channel_TypeDef *DMAMUXx) __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -2018,7 +2018,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(const DMAMUX_Channel_TypeDef *DMAMU
* @param DMAMUXx DMAMUXx DMAMUXx Instance * @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(const DMAMUX_Channel_TypeDef *DMAMUXx) __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -2031,7 +2031,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(const DMAMUX_Channel_TypeDef *DMAMU
* @param DMAMUXx DMAMUXx DMAMUXx Instance * @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(const DMAMUX_Channel_TypeDef *DMAMUXx) __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -2044,7 +2044,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(const DMAMUX_Channel_TypeDef *DMAMU
* @param DMAMUXx DMAMUXx DMAMUXx Instance * @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(const DMAMUX_Channel_TypeDef *DMAMUXx) __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -2057,7 +2057,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(const DMAMUX_Channel_TypeDef *DMAMU
* @param DMAMUXx DMAMUXx DMAMUXx Instance * @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(const DMAMUX_Channel_TypeDef *DMAMUXx) __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -2070,7 +2070,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(const DMAMUX_Channel_TypeDef *DMAMU
* @param DMAMUXx DMAMUXx DMAMUXx Instance * @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(const DMAMUX_Channel_TypeDef *DMAMUXx) __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -2083,7 +2083,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(const DMAMUX_Channel_TypeDef *DMAM
* @param DMAMUXx DMAMUXx DMAMUXx Instance * @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(const DMAMUX_Channel_TypeDef *DMAMUXx) __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -2096,7 +2096,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(const DMAMUX_Channel_TypeDef *DMAM
* @param DMAMUXx DMAMUXx DMAMUXx Instance * @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(const DMAMUX_Channel_TypeDef *DMAMUXx) __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -2109,7 +2109,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(const DMAMUX_Channel_TypeDef *DMAM
* @param DMAMUXx DMAMUXx DMAMUXx Instance * @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(const DMAMUX_Channel_TypeDef *DMAMUXx) __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -2122,7 +2122,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(const DMAMUX_Channel_TypeDef *DMAM
* @param DMAMUXx DMAMUXx DMAMUXx Instance * @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO14(const DMAMUX_Channel_TypeDef *DMAMUXx) __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -2135,7 +2135,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO14(const DMAMUX_Channel_TypeDef *DMAM
* @param DMAMUXx DMAMUXx DMAMUXx Instance * @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO15(const DMAMUX_Channel_TypeDef *DMAMUXx) __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -2148,7 +2148,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO15(const DMAMUX_Channel_TypeDef *DMAM
* @param DMAMUXx DMAMUXx DMAMUXx Instance * @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(const DMAMUX_Channel_TypeDef *DMAMUXx) __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -2161,7 +2161,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(const DMAMUX_Channel_TypeDef *DMAM
* @param DMAMUXx DMAMUXx DMAMUXx Instance * @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(const DMAMUX_Channel_TypeDef *DMAMUXx) __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -2174,7 +2174,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(const DMAMUX_Channel_TypeDef *DMAM
* @param DMAMUXx DMAMUXx DMAMUXx Instance * @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(const DMAMUX_Channel_TypeDef *DMAMUXx) __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -2187,7 +2187,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(const DMAMUX_Channel_TypeDef *DMAM
* @param DMAMUXx DMAMUXx DMAMUXx Instance * @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(const DMAMUX_Channel_TypeDef *DMAMUXx) __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -2200,7 +2200,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(const DMAMUX_Channel_TypeDef *DMAM
* @param DMAMUXx DMAMUXx DMAMUXx Instance * @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO4(const DMAMUX_Channel_TypeDef *DMAMUXx) __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO4(DMAMUX_Channel_TypeDef *DMAMUXx)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -2213,7 +2213,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO4(const DMAMUX_Channel_TypeDef *DMAM
* @param DMAMUXx DMAMUXx DMAMUXx Instance * @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO5(const DMAMUX_Channel_TypeDef *DMAMUXx) __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO5(DMAMUX_Channel_TypeDef *DMAMUXx)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -2226,7 +2226,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO5(const DMAMUX_Channel_TypeDef *DMAM
* @param DMAMUXx DMAMUXx DMAMUXx Instance * @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO6(const DMAMUX_Channel_TypeDef *DMAMUXx) __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO6(DMAMUX_Channel_TypeDef *DMAMUXx)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -2239,7 +2239,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO6(const DMAMUX_Channel_TypeDef *DMAM
* @param DMAMUXx DMAMUXx DMAMUXx Instance * @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO7(const DMAMUX_Channel_TypeDef *DMAMUXx) __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO7(DMAMUX_Channel_TypeDef *DMAMUXx)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -2277,7 +2277,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO7(const DMAMUX_Channel_TypeDef *DMAM
* @arg @ref LL_DMAMUX_CHANNEL_15 * @arg @ref LL_DMAMUX_CHANNEL_15
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMAMUX_EnableIT_SO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) __STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -2307,7 +2307,7 @@ __STATIC_INLINE void LL_DMAMUX_EnableIT_SO(const DMAMUX_Channel_TypeDef *DMAMUXx
* @arg @ref LL_DMAMUX_CHANNEL_15 * @arg @ref LL_DMAMUX_CHANNEL_15
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMAMUX_DisableIT_SO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) __STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -2337,7 +2337,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableIT_SO(const DMAMUX_Channel_TypeDef *DMAMUX
* @arg @ref LL_DMAMUX_CHANNEL_15 * @arg @ref LL_DMAMUX_CHANNEL_15
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -2359,7 +2359,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(const DMAMUX_Channel_TypeDef *
* @arg @ref LL_DMAMUX_REQ_GEN_7 * @arg @ref LL_DMAMUX_REQ_GEN_7
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) __STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -2381,7 +2381,7 @@ __STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(const DMAMUX_Channel_TypeDef *DMAMUX
* @arg @ref LL_DMAMUX_REQ_GEN_7 * @arg @ref LL_DMAMUX_REQ_GEN_7
* @retval None * @retval None
*/ */
__STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) __STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
@ -2403,7 +2403,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(const DMAMUX_Channel_TypeDef *DMAMU
* @arg @ref LL_DMAMUX_REQ_GEN_7 * @arg @ref LL_DMAMUX_REQ_GEN_7
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
{ {
uint32_t dmamux_base_addr = (uint32_t)DMAMUXx; uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

26
AMS_Master_Code/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_gpio.h
View File

@ -309,7 +309,7 @@ __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint3
* @arg @ref LL_GPIO_MODE_ALTERNATE * @arg @ref LL_GPIO_MODE_ALTERNATE
* @arg @ref LL_GPIO_MODE_ANALOG * @arg @ref LL_GPIO_MODE_ANALOG
*/ */
__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(const GPIO_TypeDef *GPIOx, uint32_t Pin) __STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
{ {
return (uint32_t)(READ_BIT(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0)) / (Pin * Pin)); return (uint32_t)(READ_BIT(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0)) / (Pin * Pin));
} }
@ -377,7 +377,7 @@ __STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinM
* @arg @ref LL_GPIO_OUTPUT_PUSHPULL * @arg @ref LL_GPIO_OUTPUT_PUSHPULL
* @arg @ref LL_GPIO_OUTPUT_OPENDRAIN * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
*/ */
__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(const GPIO_TypeDef *GPIOx, uint32_t Pin) __STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
{ {
return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) / Pin); return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) / Pin);
} }
@ -450,7 +450,7 @@ __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint
* @arg @ref LL_GPIO_SPEED_FREQ_HIGH * @arg @ref LL_GPIO_SPEED_FREQ_HIGH
* @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
*/ */
__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(const GPIO_TypeDef *GPIOx, uint32_t Pin) __STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
{ {
return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEED0)) / (Pin * Pin)); return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEED0)) / (Pin * Pin));
} }
@ -515,7 +515,7 @@ __STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint3
* @arg @ref LL_GPIO_PULL_UP * @arg @ref LL_GPIO_PULL_UP
* @arg @ref LL_GPIO_PULL_DOWN * @arg @ref LL_GPIO_PULL_DOWN
*/ */
__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(const GPIO_TypeDef *GPIOx, uint32_t Pin) __STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)
{ {
return (uint32_t)(READ_BIT(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0)) / (Pin * Pin)); return (uint32_t)(READ_BIT(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0)) / (Pin * Pin));
} }
@ -591,7 +591,7 @@ __STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uin
* @arg @ref LL_GPIO_AF_14 * @arg @ref LL_GPIO_AF_14
* @arg @ref LL_GPIO_AF_15 * @arg @ref LL_GPIO_AF_15
*/ */
__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(const GPIO_TypeDef *GPIOx, uint32_t Pin) __STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin)
{ {
return (uint32_t)(READ_BIT(GPIOx->AFR[0], return (uint32_t)(READ_BIT(GPIOx->AFR[0],
((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0)) / (((Pin * Pin) * Pin) * Pin)); ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0)) / (((Pin * Pin) * Pin) * Pin));
@ -669,7 +669,7 @@ __STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, ui
* @arg @ref LL_GPIO_AF_14 * @arg @ref LL_GPIO_AF_14
* @arg @ref LL_GPIO_AF_15 * @arg @ref LL_GPIO_AF_15
*/ */
__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(const GPIO_TypeDef *GPIOx, uint32_t Pin) __STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin)
{ {
return (uint32_t)(READ_BIT(GPIOx->AFR[1], return (uint32_t)(READ_BIT(GPIOx->AFR[1],
(((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8)) / ((((Pin >> 8U) * (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8)) / ((((Pin >> 8U) *
@ -741,7 +741,7 @@ __STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
* @arg @ref LL_GPIO_PIN_ALL * @arg @ref LL_GPIO_PIN_ALL
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(const GPIO_TypeDef *GPIOx, uint32_t PinMask) __STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{ {
return ((READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)) ? 1UL : 0UL); return ((READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)) ? 1UL : 0UL);
} }
@ -752,7 +752,7 @@ __STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(const GPIO_TypeDef *GPIOx, uint32_t
* @param GPIOx GPIO Port * @param GPIOx GPIO Port
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(const GPIO_TypeDef *GPIOx) __STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)
{ {
return ((READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)) ? 1UL : 0UL); return ((READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)) ? 1UL : 0UL);
} }
@ -771,7 +771,7 @@ __STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(const GPIO_TypeDef *GPIOx)
* @param GPIOx GPIO Port * @param GPIOx GPIO Port
* @retval Input data register value of port * @retval Input data register value of port
*/ */
__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(const GPIO_TypeDef *GPIOx) __STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
{ {
return (uint32_t)(READ_REG(GPIOx->IDR)); return (uint32_t)(READ_REG(GPIOx->IDR));
} }
@ -800,7 +800,7 @@ __STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(const GPIO_TypeDef *GPIOx)
* @arg @ref LL_GPIO_PIN_ALL * @arg @ref LL_GPIO_PIN_ALL
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(const GPIO_TypeDef *GPIOx, uint32_t PinMask) __STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{ {
return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL); return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL);
} }
@ -823,7 +823,7 @@ __STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortV
* @param GPIOx GPIO Port * @param GPIOx GPIO Port
* @retval Output data register value of port * @retval Output data register value of port
*/ */
__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(const GPIO_TypeDef *GPIOx) __STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)
{ {
return (uint32_t)(READ_REG(GPIOx->ODR)); return (uint32_t)(READ_REG(GPIOx->ODR));
} }
@ -852,7 +852,7 @@ __STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(const GPIO_TypeDef *GPIOx)
* @arg @ref LL_GPIO_PIN_ALL * @arg @ref LL_GPIO_PIN_ALL
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(const GPIO_TypeDef *GPIOx, uint32_t PinMask) __STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{ {
return ((READ_BIT(GPIOx->ODR, PinMask) == (PinMask)) ? 1UL : 0UL); return ((READ_BIT(GPIOx->ODR, PinMask) == (PinMask)) ? 1UL : 0UL);
} }
@ -954,7 +954,7 @@ __STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
* @{ * @{
*/ */
ErrorStatus LL_GPIO_DeInit(const GPIO_TypeDef *GPIOx); ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);
ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct); ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct);
void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);

24
AMS_Master_Code/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_hsem.h
View File

@ -163,7 +163,7 @@ extern "C" {
* @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_HSEM_IsSemaphoreLocked(const HSEM_TypeDef *HSEMx, uint32_t Semaphore) __STATIC_INLINE uint32_t LL_HSEM_IsSemaphoreLocked(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
{ {
return ((READ_BIT(HSEMx->R[Semaphore], HSEM_R_LOCK) == (HSEM_R_LOCK_Msk)) ? 1UL : 0UL); return ((READ_BIT(HSEMx->R[Semaphore], HSEM_R_LOCK) == (HSEM_R_LOCK_Msk)) ? 1UL : 0UL);
} }
@ -178,7 +178,7 @@ __STATIC_INLINE uint32_t LL_HSEM_IsSemaphoreLocked(const HSEM_TypeDef *HSEMx, ui
* @arg @ref LL_HSEM_COREID_CPU1 * @arg @ref LL_HSEM_COREID_CPU1
* @arg @ref LL_HSEM_COREID_CPU2 * @arg @ref LL_HSEM_COREID_CPU2
*/ */
__STATIC_INLINE uint32_t LL_HSEM_GetCoreId(const HSEM_TypeDef *HSEMx, uint32_t Semaphore) __STATIC_INLINE uint32_t LL_HSEM_GetCoreId(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
{ {
return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_COREID_Msk)); return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_COREID_Msk));
} }
@ -190,7 +190,7 @@ __STATIC_INLINE uint32_t LL_HSEM_GetCoreId(const HSEM_TypeDef *HSEMx, uint32_t S
* @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
* @retval Process number. Value between Min_Data=0 and Max_Data=255 * @retval Process number. Value between Min_Data=0 and Max_Data=255
*/ */
__STATIC_INLINE uint32_t LL_HSEM_GetProcessId(const HSEM_TypeDef *HSEMx, uint32_t Semaphore) __STATIC_INLINE uint32_t LL_HSEM_GetProcessId(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
{ {
return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_PROCID_Msk)); return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_PROCID_Msk));
} }
@ -236,7 +236,7 @@ __STATIC_INLINE uint32_t LL_HSEM_2StepLock(HSEM_TypeDef *HSEMx, uint32_t Semapho
* @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
* @retval 1 lock fail, 0 lock successful or already locked by same core * @retval 1 lock fail, 0 lock successful or already locked by same core
*/ */
__STATIC_INLINE uint32_t LL_HSEM_1StepLock(const HSEM_TypeDef *HSEMx, uint32_t Semaphore) __STATIC_INLINE uint32_t LL_HSEM_1StepLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
{ {
return ((HSEMx->RLR[Semaphore] != (HSEM_RLR_LOCK | LL_HSEM_COREID)) ? 1UL : 0UL); return ((HSEMx->RLR[Semaphore] != (HSEM_RLR_LOCK | LL_HSEM_COREID)) ? 1UL : 0UL);
} }
@ -261,7 +261,7 @@ __STATIC_INLINE void LL_HSEM_ReleaseLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore
* @param HSEMx HSEM Instance. * @param HSEMx HSEM Instance.
* @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31
* @retval 0 semaphore is free, 1 semaphore is locked */ * @retval 0 semaphore is free, 1 semaphore is locked */
__STATIC_INLINE uint32_t LL_HSEM_GetStatus(const HSEM_TypeDef *HSEMx, uint32_t Semaphore) __STATIC_INLINE uint32_t LL_HSEM_GetStatus(HSEM_TypeDef *HSEMx, uint32_t Semaphore)
{ {
return ((HSEMx->R[Semaphore] != 0U) ? 1UL : 0UL); return ((HSEMx->R[Semaphore] != 0U) ? 1UL : 0UL);
} }
@ -284,7 +284,7 @@ __STATIC_INLINE void LL_HSEM_SetKey(HSEM_TypeDef *HSEMx, uint32_t key)
* @param HSEMx HSEM Instance. * @param HSEMx HSEM Instance.
* @retval key to unlock all semaphore from the same core * @retval key to unlock all semaphore from the same core
*/ */
__STATIC_INLINE uint32_t LL_HSEM_GetKey(const HSEM_TypeDef *HSEMx) __STATIC_INLINE uint32_t LL_HSEM_GetKey(HSEM_TypeDef *HSEMx)
{ {
return (uint32_t)(READ_BIT(HSEMx->KEYR, HSEM_KEYR_KEY) >> HSEM_KEYR_KEY_Pos); return (uint32_t)(READ_BIT(HSEMx->KEYR, HSEM_KEYR_KEY) >> HSEM_KEYR_KEY_Pos);
} }
@ -450,7 +450,7 @@ __STATIC_INLINE void LL_HSEM_DisableIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t Semap
* depends on devices. * depends on devices.
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C1IER(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) __STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
{ {
return ((READ_BIT(HSEMx->C1IER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); return ((READ_BIT(HSEMx->C1IER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
} }
@ -586,7 +586,7 @@ __STATIC_INLINE void LL_HSEM_DisableIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t Semap
* @arg @ref LL_HSEM_SEMAPHORE_ALL * @arg @ref LL_HSEM_SEMAPHORE_ALL
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C2IER(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) __STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
{ {
return ((READ_BIT(HSEMx->C2IER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); return ((READ_BIT(HSEMx->C2IER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
} }
@ -689,7 +689,7 @@ __STATIC_INLINE void LL_HSEM_ClearFlag_C1ICR(HSEM_TypeDef *HSEMx, uint32_t Semap
* depends on devices. * depends on devices.
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1ISR(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1ISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
{ {
return ((READ_BIT(HSEMx->C1ISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); return ((READ_BIT(HSEMx->C1ISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
} }
@ -736,7 +736,7 @@ __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1ISR(const HSEM_TypeDef *HSEMx, u
* depends on devices. * depends on devices.
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1MISR(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1MISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
{ {
return ((READ_BIT(HSEMx->C1MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); return ((READ_BIT(HSEMx->C1MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
} }
@ -827,7 +827,7 @@ __STATIC_INLINE void LL_HSEM_ClearFlag_C2ICR(HSEM_TypeDef *HSEMx, uint32_t Semap
* @arg @ref LL_HSEM_SEMAPHORE_ALL * @arg @ref LL_HSEM_SEMAPHORE_ALL
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2ISR(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2ISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
{ {
return ((READ_BIT(HSEMx->C2ISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); return ((READ_BIT(HSEMx->C2ISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
} }
@ -872,7 +872,7 @@ __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2ISR(const HSEM_TypeDef *HSEMx, u
* @arg @ref LL_HSEM_SEMAPHORE_ALL * @arg @ref LL_HSEM_SEMAPHORE_ALL
* @retval State of bit (1 or 0). * @retval State of bit (1 or 0).
*/ */
__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2MISR(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2MISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)
{ {
return ((READ_BIT(HSEMx->C2MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); return ((READ_BIT(HSEMx->C2MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);
} }

5213
AMS_Master_Code/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_tim.h Normal file
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2
AMS_Master_Code/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c
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@ -51,7 +51,7 @@
*/ */
#define __STM32H7xx_HAL_VERSION_MAIN (0x01UL) /*!< [31:24] main version */ #define __STM32H7xx_HAL_VERSION_MAIN (0x01UL) /*!< [31:24] main version */
#define __STM32H7xx_HAL_VERSION_SUB1 (0x0BUL) /*!< [23:16] sub1 version */ #define __STM32H7xx_HAL_VERSION_SUB1 (0x0BUL) /*!< [23:16] sub1 version */
#define __STM32H7xx_HAL_VERSION_SUB2 (0x05UL) /*!< [15:8] sub2 version */ #define __STM32H7xx_HAL_VERSION_SUB2 (0x03UL) /*!< [15:8] sub2 version */
#define __STM32H7xx_HAL_VERSION_RC (0x00UL) /*!< [7:0] release candidate */ #define __STM32H7xx_HAL_VERSION_RC (0x00UL) /*!< [7:0] release candidate */
#define __STM32H7xx_HAL_VERSION ((__STM32H7xx_HAL_VERSION_MAIN << 24)\ #define __STM32H7xx_HAL_VERSION ((__STM32H7xx_HAL_VERSION_MAIN << 24)\
|(__STM32H7xx_HAL_VERSION_SUB1 << 16)\ |(__STM32H7xx_HAL_VERSION_SUB1 << 16)\

4056
AMS_Master_Code/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c Normal file
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2659
AMS_Master_Code/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c Normal file
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2
AMS_Master_Code/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c
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@ -327,7 +327,7 @@ void HAL_MPU_DisableRegion(uint32_t RegionNumber)
* the initialization and configuration information. * the initialization and configuration information.
* @retval None * @retval None
*/ */
void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *MPU_Init) void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
{ {
/* Check the parameters */ /* Check the parameters */
assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));

8
AMS_Master_Code/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma.c
View File

@ -174,7 +174,7 @@ typedef struct
*/ */
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma); static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
static HAL_StatusTypeDef DMA_CheckFifoParam(const DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma);
static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma); static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma);
static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma); static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma);
@ -1733,7 +1733,7 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Ca
* the configuration information for the specified DMA Stream. * the configuration information for the specified DMA Stream.
* @retval HAL state * @retval HAL state
*/ */
HAL_DMA_StateTypeDef HAL_DMA_GetState(const DMA_HandleTypeDef *hdma) HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
{ {
return hdma->State; return hdma->State;
} }
@ -1744,7 +1744,7 @@ HAL_DMA_StateTypeDef HAL_DMA_GetState(const DMA_HandleTypeDef *hdma)
* the configuration information for the specified DMA Stream. * the configuration information for the specified DMA Stream.
* @retval DMA Error Code * @retval DMA Error Code
*/ */
uint32_t HAL_DMA_GetError(const DMA_HandleTypeDef *hdma) uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
{ {
return hdma->ErrorCode; return hdma->ErrorCode;
} }
@ -1893,7 +1893,7 @@ static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
* the configuration information for the specified DMA Stream. * the configuration information for the specified DMA Stream.
* @retval HAL status * @retval HAL status
*/ */
static HAL_StatusTypeDef DMA_CheckFifoParam(const DMA_HandleTypeDef *hdma) static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)
{ {
HAL_StatusTypeDef status = HAL_OK; HAL_StatusTypeDef status = HAL_OK;

12
AMS_Master_Code/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c
View File

@ -509,7 +509,7 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT
* @param hexti Exti handle. * @param hexti Exti handle.
* @retval HAL Status. * @retval HAL Status.
*/ */
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(const EXTI_HandleTypeDef *hexti) HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
{ {
__IO uint32_t *regaddr; __IO uint32_t *regaddr;
uint32_t regval; uint32_t regval;
@ -682,7 +682,7 @@ HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLin
* @param hexti Exti handle. * @param hexti Exti handle.
* @retval none. * @retval none.
*/ */
void HAL_EXTI_IRQHandler(const EXTI_HandleTypeDef *hexti) void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
{ {
__IO uint32_t *regaddr; __IO uint32_t *regaddr;
uint32_t regval; uint32_t regval;
@ -734,9 +734,9 @@ void HAL_EXTI_IRQHandler(const EXTI_HandleTypeDef *hexti)
* This parameter is kept for compatibility with other series. * This parameter is kept for compatibility with other series.
* @retval 1 if interrupt is pending else 0. * @retval 1 if interrupt is pending else 0.
*/ */
uint32_t HAL_EXTI_GetPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge) uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
{ {
const __IO uint32_t *regaddr; __IO uint32_t *regaddr;
uint32_t regval; uint32_t regval;
uint32_t linepos; uint32_t linepos;
uint32_t maskline; uint32_t maskline;
@ -785,7 +785,7 @@ uint32_t HAL_EXTI_GetPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge)
* This parameter is kept for compatibility with other series. * This parameter is kept for compatibility with other series.
* @retval None. * @retval None.
*/ */
void HAL_EXTI_ClearPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge) void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
{ {
__IO uint32_t *regaddr; __IO uint32_t *regaddr;
uint32_t maskline; uint32_t maskline;
@ -827,7 +827,7 @@ void HAL_EXTI_ClearPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge)
* @param hexti Exti handle. * @param hexti Exti handle.
* @retval None. * @retval None.
*/ */
void HAL_EXTI_GenerateSWI(const EXTI_HandleTypeDef *hexti) void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
{ {
__IO uint32_t *regaddr; __IO uint32_t *regaddr;
uint32_t maskline; uint32_t maskline;

6257
AMS_Master_Code/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c Normal file
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8
AMS_Master_Code/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash_ex.c
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@ -1020,26 +1020,26 @@ void HAL_FLASHEx_GetEccInfo(FLASH_EccInfoTypeDef *pData)
*/ */
void HAL_FLASHEx_BusFault_IRQHandler(void) void HAL_FLASHEx_BusFault_IRQHandler(void)
{ {
/* Check if the ECC double error occurred*/ /* Check if the ECC double error occured*/
if ((FLASH->SR1 & FLASH_FLAG_DBECCERR_BANK1) != 0) if ((FLASH->SR1 & FLASH_FLAG_DBECCERR_BANK1) != 0)
{ {
/* FLASH ECC detection user callback */ /* FLASH ECC detection user callback */
HAL_FLASHEx_EccDetectionCallback(); HAL_FLASHEx_EccDetectionCallback();
/* Clear Bank 1 ECC double detection error flag /* Clear Bank 1 ECC double detection error flag
note : this step will clear all the information related to the flash ECC detection note : this step will clear all the informations related to the flash ECC detection
*/ */
__HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_DBECCERR_BANK1); __HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_DBECCERR_BANK1);
} }
#if defined (DUAL_BANK) #if defined (DUAL_BANK)
/* Check if the ECC double error occurred*/ /* Check if the ECC double error occured*/
if ((FLASH->SR2 & FLASH_FLAG_DBECCERR_BANK2) != 0) if ((FLASH->SR2 & FLASH_FLAG_DBECCERR_BANK2) != 0)
{ {
/* FLASH ECC detection user callback */ /* FLASH ECC detection user callback */
HAL_FLASHEx_EccDetectionCallback(); HAL_FLASHEx_EccDetectionCallback();
/* Clear Bank 2 ECC double detection error flag /* Clear Bank 2 ECC double detection error flag
note : this step will clear all the information related to the flash ECC detection note : this step will clear all the informations related to the flash ECC detection
*/ */
__HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_DBECCERR_BANK2); __HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_DBECCERR_BANK2);
} }

4
AMS_Master_Code/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_gpio.c
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@ -162,7 +162,7 @@
* the configuration information for the specified GPIO peripheral. * the configuration information for the specified GPIO peripheral.
* @retval None * @retval None
*/ */
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *GPIO_Init) void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{ {
uint32_t position = 0x00U; uint32_t position = 0x00U;
uint32_t iocurrent; uint32_t iocurrent;
@ -386,7 +386,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
* This parameter can be GPIO_PIN_x where x can be (0..15). * This parameter can be GPIO_PIN_x where x can be (0..15).
* @retval The input port pin value. * @retval The input port pin value.
*/ */
GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{ {
GPIO_PinState bitstatus; GPIO_PinState bitstatus;

107
AMS_Master_Code/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c
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@ -90,7 +90,7 @@
add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
add their own code by customization of function pointer HAL_I2C_ErrorCallback() add their own code by customization of function pointer HAL_I2C_ErrorCallback()
(+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
(+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
(+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
@ -156,7 +156,7 @@
HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA() HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA()
(+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
(++) Abort a master or memory IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
(+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
(++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT()
@ -214,7 +214,7 @@
add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
add their own code by customization of function pointer HAL_I2C_ErrorCallback() add their own code by customization of function pointer HAL_I2C_ErrorCallback()
(+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
(+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
(+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
@ -1407,6 +1407,14 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
/* Enable Address Acknowledge */ /* Enable Address Acknowledge */
hi2c->Instance->CR2 &= ~I2C_CR2_NACK; hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
/* Wait until ADDR flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
return HAL_ERROR;
}
/* Preload TX data if no stretch enable */ /* Preload TX data if no stretch enable */
if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
{ {
@ -1420,18 +1428,6 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
hi2c->XferCount--; hi2c->XferCount--;
} }
/* Wait until ADDR flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
return HAL_ERROR;
}
/* Clear ADDR flag */ /* Clear ADDR flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
@ -1443,10 +1439,6 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
{ {
/* Disable Address Acknowledge */ /* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK; hi2c->Instance->CR2 |= I2C_CR2_NACK;
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
return HAL_ERROR; return HAL_ERROR;
} }
@ -1459,10 +1451,6 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
{ {
/* Disable Address Acknowledge */ /* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK; hi2c->Instance->CR2 |= I2C_CR2_NACK;
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
return HAL_ERROR; return HAL_ERROR;
} }
@ -3267,8 +3255,6 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
__IO uint32_t I2C_Trials = 0UL; __IO uint32_t I2C_Trials = 0UL;
HAL_StatusTypeDef status = HAL_OK;
FlagStatus tmp1; FlagStatus tmp1;
FlagStatus tmp2; FlagStatus tmp2;
@ -3326,64 +3312,37 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
/* Wait until STOPF flag is reset */ /* Wait until STOPF flag is reset */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
{ {
/* A non acknowledge appear during STOP Flag waiting process, a new trial must be performed */ return HAL_ERROR;
if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Reset the error code for next trial */
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
}
else
{
status = HAL_ERROR;
}
} }
else
{
/* A acknowledge appear during STOP Flag waiting process, this mean that device respond to its address */
/* Clear STOP Flag */ /* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Device is ready */ /* Device is ready */
hi2c->State = HAL_I2C_STATE_READY; hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */ /* Process Unlocked */
__HAL_UNLOCK(hi2c); __HAL_UNLOCK(hi2c);
return HAL_OK; return HAL_OK;
}
} }
else else
{ {
/* A non acknowledge is detected, this mean that device not respond to its address, /* Wait until STOPF flag is reset */
a new trial must be performed */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_ERROR;
}
/* Clear NACK Flag */ /* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
/* Wait until STOPF flag is reset */ /* Clear STOP Flag, auto generated with autoend*/
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
{
status = HAL_ERROR;
}
else
{
/* Clear STOP Flag, auto generated with autoend*/
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
}
} }
/* Increment Trials */ /* Increment Trials */
I2C_Trials++; I2C_Trials++;
if ((I2C_Trials < Trials) && (status == HAL_ERROR))
{
status = HAL_OK;
}
} while (I2C_Trials < Trials); } while (I2C_Trials < Trials);
/* Update I2C state */ /* Update I2C state */
@ -4593,7 +4552,7 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
} }
/** /**
* @brief Abort a master or memory I2C IT or DMA process communication with Interrupt. * @brief Abort a master I2C IT or DMA process communication with Interrupt.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C. * the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value * @param DevAddress Target device address: The device 7 bits address value
@ -4602,9 +4561,7 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
*/ */
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
{ {
HAL_I2C_ModeTypeDef tmp_mode = hi2c->Mode; if (hi2c->Mode == HAL_I2C_MODE_MASTER)
if ((tmp_mode == HAL_I2C_MODE_MASTER) || (tmp_mode == HAL_I2C_MODE_MEM))
{ {
/* Process Locked */ /* Process Locked */
__HAL_LOCK(hi2c); __HAL_LOCK(hi2c);
@ -7327,17 +7284,15 @@ static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t T
static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
uint32_t Request) uint32_t Request)
{ {
uint32_t tmp;
/* Check the parameters */ /* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_TRANSFER_MODE(Mode)); assert_param(IS_TRANSFER_MODE(Mode));
assert_param(IS_TRANSFER_REQUEST(Request)); assert_param(IS_TRANSFER_REQUEST(Request));
/* Declaration of tmp to prevent undefined behavior of volatile usage */ /* Declaration of tmp to prevent undefined behavior of volatile usage */
tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
(((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
(uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
/* update CR2 register */ /* update CR2 register */
MODIFY_REG(hi2c->Instance->CR2, \ MODIFY_REG(hi2c->Instance->CR2, \

6
AMS_Master_Code/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c
View File

@ -708,7 +708,7 @@ HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MD
* *
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, const MDMA_LinkNodeTypeDef *pPrevNode) HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, MDMA_LinkNodeTypeDef *pPrevNode)
{ {
MDMA_LinkNodeTypeDef *pNode; MDMA_LinkNodeTypeDef *pNode;
uint32_t counter = 0, nodeInserted = 0; uint32_t counter = 0, nodeInserted = 0;
@ -1719,7 +1719,7 @@ void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma)
* the configuration information for the specified MDMA Channel. * the configuration information for the specified MDMA Channel.
* @retval HAL state * @retval HAL state
*/ */
HAL_MDMA_StateTypeDef HAL_MDMA_GetState(const MDMA_HandleTypeDef *hmdma) HAL_MDMA_StateTypeDef HAL_MDMA_GetState(MDMA_HandleTypeDef *hmdma)
{ {
return hmdma->State; return hmdma->State;
} }
@ -1730,7 +1730,7 @@ HAL_MDMA_StateTypeDef HAL_MDMA_GetState(const MDMA_HandleTypeDef *hmdma)
* the configuration information for the specified MDMA Channel. * the configuration information for the specified MDMA Channel.
* @retval MDMA Error Code * @retval MDMA Error Code
*/ */
uint32_t HAL_MDMA_GetError(const MDMA_HandleTypeDef *hmdma) uint32_t HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma)
{ {
return hmdma->ErrorCode; return hmdma->ErrorCode;
} }

2
AMS_Master_Code/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c
View File

@ -412,7 +412,7 @@ void HAL_PWR_DisableBkUpAccess (void)
* only Cortex-M4 or wake up Cortex-M7 and Cortex-M4. * only Cortex-M4 or wake up Cortex-M7 and Cortex-M4.
* @retval None. * @retval None.
*/ */
void HAL_PWR_ConfigPVD (const PWR_PVDTypeDef *sConfigPVD) void HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD)
{ {
/* Check the PVD configuration parameter */ /* Check the PVD configuration parameter */
if (sConfigPVD == NULL) if (sConfigPVD == NULL)

8
AMS_Master_Code/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c
View File

@ -308,10 +308,6 @@
* PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO, PWR_SMPS_1V8_SUPPLIES_EXT and * PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO, PWR_SMPS_1V8_SUPPLIES_EXT and
* PWR_SMPS_2V5_SUPPLIES_EXT are used only for lines that supports SMPS * PWR_SMPS_2V5_SUPPLIES_EXT are used only for lines that supports SMPS
* regulator. * regulator.
* @note This API is deprecated and is kept only for backward compatibility's sake.
* The power supply configuration is handled as part of the system initialization
* process during startup.
* For more details, please refer to the power control chapter in the reference manual
* @retval HAL status. * @retval HAL status.
*/ */
HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource) HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource)
@ -1303,7 +1299,7 @@ void HAL_PWREx_DisableMemoryShutOff (uint32_t MemoryBlock)
* Cortex-M4. * Cortex-M4.
* @retval None. * @retval None.
*/ */
void HAL_PWREx_EnableWakeUpPin (const PWREx_WakeupPinTypeDef *sPinParams) void HAL_PWREx_EnableWakeUpPin (PWREx_WakeupPinTypeDef *sPinParams)
{ {
uint32_t pinConfig; uint32_t pinConfig;
uint32_t regMask; uint32_t regMask;
@ -1977,7 +1973,7 @@ PWREx_MMC_VoltageLevel HAL_PWREx_GetMMCVoltage (void)
* only Cortex-M4 and wake up Cortex-M7 and Cortex-M4. * only Cortex-M4 and wake up Cortex-M7 and Cortex-M4.
* @retval None. * @retval None.
*/ */
void HAL_PWREx_ConfigAVD (const PWREx_AVDTypeDef *sConfigAVD) void HAL_PWREx_ConfigAVD (PWREx_AVDTypeDef *sConfigAVD)
{ {
/* Check the parameters */ /* Check the parameters */
assert_param (IS_PWR_AVD_LEVEL (sConfigAVD->AVDLevel)); assert_param (IS_PWR_AVD_LEVEL (sConfigAVD->AVDLevel));

2
AMS_Master_Code/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c
View File

@ -919,7 +919,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc
* (for more details refer to section above "Initialization/de-initialization functions") * (for more details refer to section above "Initialization/de-initialization functions")
* @retval None * @retval None
*/ */
HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{ {
HAL_StatusTypeDef halstatus; HAL_StatusTypeDef halstatus;
uint32_t tickstart; uint32_t tickstart;

10
AMS_Master_Code/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c
View File

@ -58,8 +58,8 @@
/* Private variables ---------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/
static HAL_StatusTypeDef RCCEx_PLL2_Config(const RCC_PLL2InitTypeDef *pll2, uint32_t Divider); static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider);
static HAL_StatusTypeDef RCCEx_PLL3_Config(const RCC_PLL3InitTypeDef *pll3, uint32_t Divider); static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider);
/* Exported functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/
/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
@ -3379,7 +3379,7 @@ void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx)
* @param pInit Pointer on RCC_CRSInitTypeDef structure * @param pInit Pointer on RCC_CRSInitTypeDef structure
* @retval None * @retval None
*/ */
void HAL_RCCEx_CRSConfig(const RCC_CRSInitTypeDef *pInit) void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)
{ {
uint32_t value; uint32_t value;
@ -3690,7 +3690,7 @@ __weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)
* *
* @retval HAL status * @retval HAL status
*/ */
static HAL_StatusTypeDef RCCEx_PLL2_Config(const RCC_PLL2InitTypeDef *pll2, uint32_t Divider) static HAL_StatusTypeDef RCCEx_PLL2_Config(RCC_PLL2InitTypeDef *pll2, uint32_t Divider)
{ {
uint32_t tickstart; uint32_t tickstart;
@ -3795,7 +3795,7 @@ static HAL_StatusTypeDef RCCEx_PLL2_Config(const RCC_PLL2InitTypeDef *pll2, uint
* *
* @retval HAL status * @retval HAL status
*/ */
static HAL_StatusTypeDef RCCEx_PLL3_Config(const RCC_PLL3InitTypeDef *pll3, uint32_t Divider) static HAL_StatusTypeDef RCCEx_PLL3_Config(RCC_PLL3InitTypeDef *pll3, uint32_t Divider)
{ {
uint32_t tickstart; uint32_t tickstart;
HAL_StatusTypeDef status = HAL_OK; HAL_StatusTypeDef status = HAL_OK;

12
AMS_Master_Code/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi.c
View File

@ -2235,6 +2235,7 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
/* Check Direction parameter */ /* Check Direction parameter */
assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction));
if (hspi->State != HAL_SPI_STATE_READY) if (hspi->State != HAL_SPI_STATE_READY)
{ {
__HAL_UNLOCK(hspi); __HAL_UNLOCK(hspi);
@ -2417,14 +2418,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uin
CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN); CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN);
/* Packing mode management is enabled by the DMA settings */ /* Packing mode management is enabled by the DMA settings */
if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && \ if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD)) || \
((hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD) || \ ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && ((hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_HALFWORD) && \
(hspi->hdmatx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD))) || \ (hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD))))
((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && \
(((hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_HALFWORD) && \
(hspi->hdmarx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD)) || \
((hspi->hdmatx->Init.MemDataAlignment != DMA_MDATAALIGN_HALFWORD) && \
(hspi->hdmatx->Init.MemDataAlignment != DMA_MDATAALIGN_WORD)))))
{ {
/* Restriction the DMA data received is not allowed in this mode */ /* Restriction the DMA data received is not allowed in this mode */
/* Unlock the process */ /* Unlock the process */

1
AMS_Master_Code/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi_ex.c
View File

@ -57,6 +57,7 @@
data transfers. data transfers.
(#) SPIEx function: (#) SPIEx function:
(++) HAL_SPIEx_FlushRxFifo()
(++) HAL_SPIEx_FlushRxFifo() (++) HAL_SPIEx_FlushRxFifo()
(++) HAL_SPIEx_EnableLockConfiguration() (++) HAL_SPIEx_EnableLockConfiguration()
(++) HAL_SPIEx_ConfigureUnderrun() (++) HAL_SPIEx_ConfigureUnderrun()

7925
AMS_Master_Code/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c Normal file
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File diff suppressed because it is too large Load Diff

2921
AMS_Master_Code/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c Normal file
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File diff suppressed because it is too large Load Diff

22
AMS_Master_Code/Makefile
View File

@ -1,5 +1,5 @@
########################################################################################################################## ##########################################################################################################################
# File automatically-generated by tool: [projectgenerator] version: [4.6.0-B36] date: [Tue Mar 18 20:15:25 CET 2025] # File automatically-generated by tool: [projectgenerator] version: [4.5.0-RC5] date: [Wed Mar 26 18:44:11 CET 2025]
########################################################################################################################## ##########################################################################################################################
# ------------------------------------------------ # ------------------------------------------------
@ -13,7 +13,7 @@
###################################### ######################################
# target # target
###################################### ######################################
TARGET = AMS Master Nucleo TARGET = Master_FT25
###################################### ######################################
@ -39,7 +39,13 @@ C_SOURCES = \
Core/Src/main.c \ Core/Src/main.c \
Core/Src/stm32h7xx_it.c \ Core/Src/stm32h7xx_it.c \
Core/Src/stm32h7xx_hal_msp.c \ Core/Src/stm32h7xx_hal_msp.c \
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c \ Core/Src/sysmem.c \
Core/Src/syscalls.c \
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc.c \
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_adc_ex.c \
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_fdcan.c \
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim.c \
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_tim_ex.c \
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c \ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c \
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c \ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc_ex.c \
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c \ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_flash.c \
@ -51,15 +57,14 @@ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_dma_ex.c \
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c \ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_mdma.c \
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c \ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c \
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c \ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c \
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_cortex.c \
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c \ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal.c \
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c \ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c.c \
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c \ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_i2c_ex.c \
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c \ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_exti.c \
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi.c \ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi.c \
Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi_ex.c \ Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_spi_ex.c \
Core/Src/system_stm32h7xx.c \ Core/Src/system_stm32h7xx.c
Core/Src/sysmem.c \
Core/Src/syscalls.c
# ASM sources # ASM sources
ASM_SOURCES = \ ASM_SOURCES = \
@ -110,9 +115,8 @@ AS_DEFS =
# C defines # C defines
C_DEFS = \ C_DEFS = \
-DUSE_PWR_DIRECT_SMPS_SUPPLY \
-DUSE_HAL_DRIVER \ -DUSE_HAL_DRIVER \
-DSTM32H7A3xxQ -DSTM32H7A3xx
# AS includes # AS includes
@ -145,7 +149,7 @@ CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)"
# LDFLAGS # LDFLAGS
####################################### #######################################
# link script # link script
LDSCRIPT = STM32H7A3XX_FLASH.ld LDSCRIPT = stm32h7a3ritx_flash.ld
# libraries # libraries
LIBS = -lc -lm -lnosys LIBS = -lc -lm -lnosys

743
AMS_Master_Code/startup_stm32h7a3xx.s Normal file
View File

@ -0,0 +1,743 @@
/**
******************************************************************************
* @file startup_stm32h7a3xx.s
* @author MCD Application Team
* @brief STM32H7B3xx Devices vector table for GCC based toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m7
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
* @param None
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
*******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
/* External Interrupts */
.word WWDG_IRQHandler /* Window WatchDog */
.word PVD_PVM_IRQHandler /* PVD/PVM through EXTI Line detection */
.word RTC_TAMP_STAMP_CSS_LSE_IRQHandler /* Tamper and TimeStamps through the EXTI line */
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
.word FLASH_IRQHandler /* FLASH */
.word RCC_IRQHandler /* RCC */
.word EXTI0_IRQHandler /* EXTI Line0 */
.word EXTI1_IRQHandler /* EXTI Line1 */
.word EXTI2_IRQHandler /* EXTI Line2 */
.word EXTI3_IRQHandler /* EXTI Line3 */
.word EXTI4_IRQHandler /* EXTI Line4 */
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
.word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
.word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
.word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
.word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
.word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
.word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
.word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
.word TIM2_IRQHandler /* TIM2 */
.word TIM3_IRQHandler /* TIM3 */
.word TIM4_IRQHandler /* TIM4 */
.word I2C1_EV_IRQHandler /* I2C1 Event */
.word I2C1_ER_IRQHandler /* I2C1 Error */
.word I2C2_EV_IRQHandler /* I2C2 Event */
.word I2C2_ER_IRQHandler /* I2C2 Error */
.word SPI1_IRQHandler /* SPI1 */
.word SPI2_IRQHandler /* SPI2 */
.word USART1_IRQHandler /* USART1 */
.word USART2_IRQHandler /* USART2 */
.word USART3_IRQHandler /* USART3 */
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
.word DFSDM2_IRQHandler /* DFSDM2 Interrupt */
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
.word FMC_IRQHandler /* FMC */
.word SDMMC1_IRQHandler /* SDMMC1 */
.word TIM5_IRQHandler /* TIM5 */
.word SPI3_IRQHandler /* SPI3 */
.word UART4_IRQHandler /* UART4 */
.word UART5_IRQHandler /* UART5 */
.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
.word TIM7_IRQHandler /* TIM7 */
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/
.word DFSDM1_FLT4_IRQHandler /* DFSDM Filter4 Interrupt */
.word DFSDM1_FLT5_IRQHandler /* DFSDM Filter5 Interrupt */
.word DFSDM1_FLT6_IRQHandler /* DFSDM Filter6 Interrupt */
.word DFSDM1_FLT7_IRQHandler /* DFSDM Filter7 Interrupt */
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
.word USART6_IRQHandler /* USART6 */
.word I2C3_EV_IRQHandler /* I2C3 event */
.word I2C3_ER_IRQHandler /* I2C3 error */
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
.word OTG_HS_IRQHandler /* USB OTG HS */
.word DCMI_PSSI_IRQHandler /* DCMI, PSSI */
.word 0 /* Reserved */
.word RNG_IRQHandler /* RNG */
.word FPU_IRQHandler /* FPU */
.word UART7_IRQHandler /* UART7 */
.word UART8_IRQHandler /* UART8 */
.word SPI4_IRQHandler /* SPI4 */
.word SPI5_IRQHandler /* SPI5 */
.word SPI6_IRQHandler /* SPI6 */
.word SAI1_IRQHandler /* SAI1 */
.word LTDC_IRQHandler /* LTDC */
.word LTDC_ER_IRQHandler /* LTDC error */
.word DMA2D_IRQHandler /* DMA2D */
.word SAI2_IRQHandler /* SAI2 */
.word OCTOSPI1_IRQHandler /* OCTOSPI1 */
.word LPTIM1_IRQHandler /* LPTIM1 */
.word CEC_IRQHandler /* HDMI_CEC */
.word I2C4_EV_IRQHandler /* I2C4 Event */
.word I2C4_ER_IRQHandler /* I2C4 Error */
.word SPDIF_RX_IRQHandler /* SPDIF_RX */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
.word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
.word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
.word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
.word 0 /* Reserved */
.word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
.word TIM15_IRQHandler /* TIM15 global Interrupt */
.word TIM16_IRQHandler /* TIM16 global Interrupt */
.word TIM17_IRQHandler /* TIM17 global Interrupt */
.word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
.word MDIOS_IRQHandler /* MDIOS global Interrupt */
.word JPEG_IRQHandler /* JPEG global Interrupt */
.word MDMA_IRQHandler /* MDMA global Interrupt */
.word 0 /* Reserved */
.word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
.word HSEM1_IRQHandler /* HSEM1 global Interrupt */
.word 0 /* Reserved */
.word DAC2_IRQHandler /* DAC2 global Interrupt */
.word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
.word BDMA2_Channel0_IRQHandler /* BDMA2 Channel 0 global Interrupt */
.word BDMA2_Channel1_IRQHandler /* BDMA2 Channel 1 global Interrupt */
.word BDMA2_Channel2_IRQHandler /* BDMA2 Channel 2 global Interrupt */
.word BDMA2_Channel3_IRQHandler /* BDMA2 Channel 3 global Interrupt */
.word BDMA2_Channel4_IRQHandler /* BDMA2 Channel 4 global Interrupt */
.word BDMA2_Channel5_IRQHandler /* BDMA2 Channel 5 global Interrupt */
.word BDMA2_Channel6_IRQHandler /* BDMA2 Channel 6 global Interrupt */
.word BDMA2_Channel7_IRQHandler /* BDMA2 Channel 7 global Interrupt */
.word COMP_IRQHandler /* COMP global Interrupt */
.word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
.word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
.word UART9_IRQHandler /* UART9 global interrupt */
.word USART10_IRQHandler /* USART10 global interrupt */
.word LPUART1_IRQHandler /* LP UART1 interrupt */
.word 0 /* Reserved */
.word CRS_IRQHandler /* Clock Recovery Global Interrupt */
.word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
.word 0 /* Reserved */
.word DTS_IRQHandler /* DTS */
.word 0 /* Reserved */
.word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
.word OCTOSPI2_IRQHandler /* OCTOSPI2 */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word GFXMMU_IRQHandler /* GFXMMU */
.word BDMA1_IRQHandler /* BDMA1 */
.size g_pfnVectors, .-g_pfnVectors
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_PVM_IRQHandler
.thumb_set PVD_PVM_IRQHandler,Default_Handler
.weak RTC_TAMP_STAMP_CSS_LSE_IRQHandler
.thumb_set RTC_TAMP_STAMP_CSS_LSE_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Stream0_IRQHandler
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
.weak DMA1_Stream1_IRQHandler
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
.weak DMA1_Stream2_IRQHandler
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
.weak DMA1_Stream3_IRQHandler
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
.weak DMA1_Stream4_IRQHandler
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
.weak DMA1_Stream5_IRQHandler
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
.weak DMA1_Stream6_IRQHandler
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
.weak ADC_IRQHandler
.thumb_set ADC_IRQHandler,Default_Handler
.weak FDCAN1_IT0_IRQHandler
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
.weak FDCAN2_IT0_IRQHandler
.thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
.weak FDCAN1_IT1_IRQHandler
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
.weak FDCAN2_IT1_IRQHandler
.thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_IRQHandler
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
.weak TIM1_UP_IRQHandler
.thumb_set TIM1_UP_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_IRQHandler
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak DFSDM2_IRQHandler
.thumb_set DFSDM2_IRQHandler,Default_Handler
.weak TIM8_BRK_TIM12_IRQHandler
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
.weak TIM8_UP_TIM13_IRQHandler
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_TIM14_IRQHandler
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak DMA1_Stream7_IRQHandler
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
.weak FMC_IRQHandler
.thumb_set FMC_IRQHandler,Default_Handler
.weak SDMMC1_IRQHandler
.thumb_set SDMMC1_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Stream0_IRQHandler
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
.weak DMA2_Stream1_IRQHandler
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
.weak DMA2_Stream2_IRQHandler
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
.weak DMA2_Stream3_IRQHandler
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
.weak DMA2_Stream4_IRQHandler
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
.weak FDCAN_CAL_IRQHandler
.thumb_set FDCAN_CAL_IRQHandler,Default_Handler
.weak DFSDM1_FLT4_IRQHandler
.thumb_set DFSDM1_FLT4_IRQHandler,Default_Handler
.weak DFSDM1_FLT5_IRQHandler
.thumb_set DFSDM1_FLT5_IRQHandler,Default_Handler
.weak DFSDM1_FLT6_IRQHandler
.thumb_set DFSDM1_FLT6_IRQHandler,Default_Handler
.weak DFSDM1_FLT7_IRQHandler
.thumb_set DFSDM1_FLT7_IRQHandler,Default_Handler
.weak DMA2_Stream5_IRQHandler
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
.weak DMA2_Stream6_IRQHandler
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
.weak DMA2_Stream7_IRQHandler
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
.weak USART6_IRQHandler
.thumb_set USART6_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak OTG_HS_EP1_OUT_IRQHandler
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
.weak OTG_HS_EP1_IN_IRQHandler
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
.weak OTG_HS_WKUP_IRQHandler
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
.weak OTG_HS_IRQHandler
.thumb_set OTG_HS_IRQHandler,Default_Handler
.weak DCMI_PSSI_IRQHandler
.thumb_set DCMI_PSSI_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak UART7_IRQHandler
.thumb_set UART7_IRQHandler,Default_Handler
.weak UART8_IRQHandler
.thumb_set UART8_IRQHandler,Default_Handler
.weak SPI4_IRQHandler
.thumb_set SPI4_IRQHandler,Default_Handler
.weak SPI5_IRQHandler
.thumb_set SPI5_IRQHandler,Default_Handler
.weak SPI6_IRQHandler
.thumb_set SPI6_IRQHandler,Default_Handler
.weak SAI1_IRQHandler
.thumb_set SAI1_IRQHandler,Default_Handler
.weak LTDC_IRQHandler
.thumb_set LTDC_IRQHandler,Default_Handler
.weak LTDC_ER_IRQHandler
.thumb_set LTDC_ER_IRQHandler,Default_Handler
.weak DMA2D_IRQHandler
.thumb_set DMA2D_IRQHandler,Default_Handler
.weak SAI2_IRQHandler
.thumb_set SAI2_IRQHandler,Default_Handler
.weak OCTOSPI1_IRQHandler
.thumb_set OCTOSPI1_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak CEC_IRQHandler
.thumb_set CEC_IRQHandler,Default_Handler
.weak I2C4_EV_IRQHandler
.thumb_set I2C4_EV_IRQHandler,Default_Handler
.weak I2C4_ER_IRQHandler
.thumb_set I2C4_ER_IRQHandler,Default_Handler
.weak SPDIF_RX_IRQHandler
.thumb_set SPDIF_RX_IRQHandler,Default_Handler
.weak DMAMUX1_OVR_IRQHandler
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
.weak DFSDM1_FLT0_IRQHandler
.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
.weak DFSDM1_FLT1_IRQHandler
.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
.weak DFSDM1_FLT2_IRQHandler
.thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
.weak DFSDM1_FLT3_IRQHandler
.thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
.weak SWPMI1_IRQHandler
.thumb_set SWPMI1_IRQHandler,Default_Handler
.weak TIM15_IRQHandler
.thumb_set TIM15_IRQHandler,Default_Handler
.weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler
.weak TIM17_IRQHandler
.thumb_set TIM17_IRQHandler,Default_Handler
.weak MDIOS_WKUP_IRQHandler
.thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
.weak MDIOS_IRQHandler
.thumb_set MDIOS_IRQHandler,Default_Handler
.weak JPEG_IRQHandler
.thumb_set JPEG_IRQHandler,Default_Handler
.weak MDMA_IRQHandler
.thumb_set MDMA_IRQHandler,Default_Handler
.weak SDMMC2_IRQHandler
.thumb_set SDMMC2_IRQHandler,Default_Handler
.weak HSEM1_IRQHandler
.thumb_set HSEM1_IRQHandler,Default_Handler
.weak DAC2_IRQHandler
.thumb_set DAC2_IRQHandler,Default_Handler
.weak DMAMUX2_OVR_IRQHandler
.thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
.weak BDMA2_Channel0_IRQHandler
.thumb_set BDMA2_Channel0_IRQHandler,Default_Handler
.weak BDMA2_Channel1_IRQHandler
.thumb_set BDMA2_Channel1_IRQHandler,Default_Handler
.weak BDMA2_Channel2_IRQHandler
.thumb_set BDMA2_Channel2_IRQHandler,Default_Handler
.weak BDMA2_Channel3_IRQHandler
.thumb_set BDMA2_Channel3_IRQHandler,Default_Handler
.weak BDMA2_Channel4_IRQHandler
.thumb_set BDMA2_Channel4_IRQHandler,Default_Handler
.weak BDMA2_Channel5_IRQHandler
.thumb_set BDMA2_Channel5_IRQHandler,Default_Handler
.weak BDMA2_Channel6_IRQHandler
.thumb_set BDMA2_Channel6_IRQHandler,Default_Handler
.weak BDMA2_Channel7_IRQHandler
.thumb_set BDMA2_Channel7_IRQHandler,Default_Handler
.weak COMP_IRQHandler
.thumb_set COMP_IRQHandler,Default_Handler
.weak LPTIM2_IRQHandler
.thumb_set LPTIM2_IRQHandler,Default_Handler
.weak LPTIM3_IRQHandler
.thumb_set LPTIM3_IRQHandler,Default_Handler
.weak LPTIM4_IRQHandler
.thumb_set LPTIM4_IRQHandler,Default_Handler
.weak LPTIM5_IRQHandler
.thumb_set LPTIM5_IRQHandler,Default_Handler
.weak UART9_IRQHandler
.thumb_set UART9_IRQHandler,Default_Handler
.weak USART10_IRQHandler
.thumb_set USART10_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak CRS_IRQHandler
.thumb_set CRS_IRQHandler,Default_Handler
.weak ECC_IRQHandler
.thumb_set ECC_IRQHandler,Default_Handler
.weak DTS_IRQHandler
.thumb_set DTS_IRQHandler,Default_Handler
.weak WAKEUP_PIN_IRQHandler
.thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
.weak OCTOSPI2_IRQHandler
.thumb_set OCTOSPI2_IRQHandler,Default_Handler
.weak GFXMMU_IRQHandler
.thumb_set GFXMMU_IRQHandler,Default_Handler
.weak BDMA1_IRQHandler
.thumb_set BDMA1_IRQHandler,Default_Handler

190
AMS_Master_Code/stm32h7a3ritx_flash.ld Normal file
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/*
******************************************************************************
**
** File : LinkerScript.ld
**
** Author : STM32CubeMX
**
** Abstract : Linker script for STM32H7A3RITx series
** 2048Kbytes FLASH and 1216Kbytes RAM
**
** Set heap size, stack size and stack location according
** to application requirements.
**
** Set memory bank area and size if external memory is used.
**
** Target : STMicroelectronics STM32
**
** Distribution: The file is distributed “as is,” without any warranty
** of any kind.
**
*****************************************************************************
** @attention
**
** <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
** 1. Redistributions of source code must retain the above copyright notice,
** this list of conditions and the following disclaimer.
** 2. Redistributions in binary form must reproduce the above copyright notice,
** this list of conditions and the following disclaimer in the documentation
** and/or other materials provided with the distribution.
** 3. Neither the name of STMicroelectronics nor the names of its contributors
** may be used to endorse or promote products derived from this software
** without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
*****************************************************************************
*/
/* Entry Point */
ENTRY(Reset_Handler)
/* Highest address of the user mode stack */
_estack = ORIGIN(DTCMRAM) + LENGTH(DTCMRAM); /* end of RAM */
/* Generate a link error if heap and stack don't fit into RAM */
_Min_Heap_Size = 0x200; /* required amount of heap */
_Min_Stack_Size = 0x400; /* required amount of stack */
/* Specify the memory areas */
MEMORY
{
DTCMRAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
RAM (xrw) : ORIGIN = 0x24000000, LENGTH = 1024K
ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K
FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 2048K
}
/* Define output sections */
SECTIONS
{
/* The startup code goes first into FLASH */
.isr_vector :
{
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
} >FLASH
/* The program code and other data goes into FLASH */
.text :
{
. = ALIGN(4);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.glue_7) /* glue arm to thumb code */
*(.glue_7t) /* glue thumb to arm code */
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
_etext = .; /* define a global symbols at end of code */
} >FLASH
/* Constant data goes into FLASH */
.rodata :
{
. = ALIGN(4);
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
. = ALIGN(4);
} >FLASH
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
.ARM : {
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} >FLASH
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >FLASH
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
} >FLASH
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
} >FLASH
/* used by the startup to initialize data */
_sidata = LOADADDR(.data);
/* Initialized data sections goes into RAM, load LMA copy after code */
.data :
{
. = ALIGN(4);
_sdata = .; /* create a global symbol at data start */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
. = ALIGN(4);
_edata = .; /* define a global symbol at data end */
} >DTCMRAM AT> FLASH
/* Uninitialized data section */
. = ALIGN(4);
.bss :
{
/* This is used by the startup in order to initialize the .bss secion */
_sbss = .; /* define a global symbol at bss start */
__bss_start__ = _sbss;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .; /* define a global symbol at bss end */
__bss_end__ = _ebss;
} >DTCMRAM
/* User_heap_stack section, used to check that there is enough RAM left */
._user_heap_stack :
{
. = ALIGN(8);
PROVIDE ( end = . );
PROVIDE ( _end = . );
. = . + _Min_Heap_Size;
. = . + _Min_Stack_Size;
. = ALIGN(8);
} >DTCMRAM
/* Remove information from the standard libraries */
/DISCARD/ :
{
libc.a ( * )
libm.a ( * )
libgcc.a ( * )
}
}