merge CAN fixup from master-test
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SHA256:mXpyZkK7RDiJ7qeHCKJX108woM0cl5TrCvNBJASu6lM
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4
AMS_Master_Code/.vscode/launch.json
vendored
4
AMS_Master_Code/.vscode/launch.json
vendored
@ -90,8 +90,8 @@
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"args": [],
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"args": [],
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"stopAtEntry": false,
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"stopAtEntry": false,
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"externalConsole": true,
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"externalConsole": true,
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"cwd": "${workspaceFolder}",
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"cwd": "c:/Users/lenex/Desktop/ams-master/AMS_Master_Code/Core/Lib/ADBMS6830B_Driver/Core/Src",
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"program": "${workspaceFolder}/build/debug/AMS_Master_Nucleo.elf",
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"program": "c:/Users/lenex/Desktop/ams-master/AMS_Master_Code/Core/Lib/ADBMS6830B_Driver/Core/Src/build/Debug/outDebug",
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"MIMode": "gdb",
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"MIMode": "gdb",
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"miDebuggerPath": "gdb",
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"miDebuggerPath": "gdb",
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"setupCommands": [
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"setupCommands": [
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@ -4,7 +4,7 @@
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#define N_BMS 1
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#define N_BMS 1
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#define N_CELLS 16
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#define N_CELLS 16
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#define ADBMS_MAX_CHIP_TEMP 110 // max temperature of ADBMS6830B (not battery) in C
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#define ADBMS_MAX_CHIP_TEMP 1100 // max temperature of ADBMS6830B (not battery) in C
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#define ADBMS_SPI_TIMEOUT 50 // Timeout in ms
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#define ADBMS_SPI_TIMEOUT 50 // Timeout in ms
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#define DEFAULT_UV 3000 // mV
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#define DEFAULT_UV 3000 // mV
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#define DEFAULT_OV 4200 // mV
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#define DEFAULT_OV 4200 // mV
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@ -203,7 +203,7 @@ int main(void)
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// for testing. in the final code can log streaming will be enabled by can message
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// for testing. in the final code can log streaming will be enabled by can message
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isotp_log_enable_streaming(LOG_LEVEL_INFO);
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isotp_log_enable_streaming(LOG_LEVEL_INFO);
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shunt_init();
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//shunt_init();
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ts_sm_init();
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ts_sm_init();
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soc_init();
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soc_init();
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imd_init(&htim15);
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imd_init(&htim15);
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@ -242,7 +242,7 @@ int main(void)
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print_battery_info();
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print_battery_info();
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print_master_status();
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print_master_status();
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}
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}
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shunt_check();
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//shunt_check();
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ts_sm_update();
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ts_sm_update();
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soc_update();
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soc_update();
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imd_update();
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imd_update();
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@ -331,17 +331,16 @@ void PeriphCommonClock_Config(void)
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/** Initializes the peripherals clock
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/** Initializes the peripherals clock
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*/
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*/
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PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADC|RCC_PERIPHCLK_FDCAN;
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PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADC;
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PeriphClkInitStruct.PLL2.PLL2M = 1;
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PeriphClkInitStruct.PLL3.PLL3M = 1;
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PeriphClkInitStruct.PLL2.PLL2N = 8;
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PeriphClkInitStruct.PLL3.PLL3N = 8;
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PeriphClkInitStruct.PLL2.PLL2P = 3;
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PeriphClkInitStruct.PLL3.PLL3P = 2;
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PeriphClkInitStruct.PLL2.PLL2Q = 3;
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PeriphClkInitStruct.PLL3.PLL3Q = 2;
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PeriphClkInitStruct.PLL2.PLL2R = 2;
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PeriphClkInitStruct.PLL3.PLL3R = 3;
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PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_3;
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PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3VCIRANGE_3;
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PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE;
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PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3VCOWIDE;
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PeriphClkInitStruct.PLL2.PLL2FRACN = 0;
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PeriphClkInitStruct.PLL3.PLL3FRACN = 0;
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PeriphClkInitStruct.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL2;
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PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLL3;
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PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLL2;
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if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
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if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
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{
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{
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Error_Handler();
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Error_Handler();
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@ -370,7 +369,7 @@ static void MX_ADC1_Init(void)
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/** Common config
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/** Common config
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*/
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*/
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hadc1.Instance = ADC1;
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hadc1.Instance = ADC1;
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hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1;
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hadc1.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV2;
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hadc1.Init.Resolution = ADC_RESOLUTION_16B;
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hadc1.Init.Resolution = ADC_RESOLUTION_16B;
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hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
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hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE;
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hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
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hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
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@ -437,7 +436,7 @@ static void MX_ADC2_Init(void)
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/** Common config
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/** Common config
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*/
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*/
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hadc2.Instance = ADC2;
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hadc2.Instance = ADC2;
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hadc2.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1;
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hadc2.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV2;
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hadc2.Init.Resolution = ADC_RESOLUTION_16B;
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hadc2.Init.Resolution = ADC_RESOLUTION_16B;
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hadc2.Init.ScanConvMode = ADC_SCAN_DISABLE;
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hadc2.Init.ScanConvMode = ADC_SCAN_DISABLE;
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hadc2.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
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hadc2.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
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@ -498,7 +497,7 @@ static void MX_FDCAN1_Init(void)
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hfdcan1.Init.ProtocolException = DISABLE;
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hfdcan1.Init.ProtocolException = DISABLE;
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hfdcan1.Init.NominalPrescaler = 2;
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hfdcan1.Init.NominalPrescaler = 2;
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hfdcan1.Init.NominalSyncJumpWidth = 1;
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hfdcan1.Init.NominalSyncJumpWidth = 1;
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hfdcan1.Init.NominalTimeSeg1 = 31;
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hfdcan1.Init.NominalTimeSeg1 = 23;
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hfdcan1.Init.NominalTimeSeg2 = 8;
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hfdcan1.Init.NominalTimeSeg2 = 8;
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hfdcan1.Init.DataPrescaler = 1;
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hfdcan1.Init.DataPrescaler = 1;
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hfdcan1.Init.DataSyncJumpWidth = 1;
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hfdcan1.Init.DataSyncJumpWidth = 1;
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@ -202,11 +202,30 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
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void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef* hfdcan)
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void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef* hfdcan)
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{
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{
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GPIO_InitTypeDef GPIO_InitStruct = {0};
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GPIO_InitTypeDef GPIO_InitStruct = {0};
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RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
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if(hfdcan->Instance==FDCAN1)
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if(hfdcan->Instance==FDCAN1)
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{
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{
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/* USER CODE BEGIN FDCAN1_MspInit 0 */
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/* USER CODE BEGIN FDCAN1_MspInit 0 */
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/* USER CODE END FDCAN1_MspInit 0 */
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/* USER CODE END FDCAN1_MspInit 0 */
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/** Initializes the peripherals clock
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*/
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PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_FDCAN;
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PeriphClkInitStruct.PLL2.PLL2M = 1;
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PeriphClkInitStruct.PLL2.PLL2N = 8;
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PeriphClkInitStruct.PLL2.PLL2P = 2;
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PeriphClkInitStruct.PLL2.PLL2Q = 4;
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PeriphClkInitStruct.PLL2.PLL2R = 2;
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PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_3;
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PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE;
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PeriphClkInitStruct.PLL2.PLL2FRACN = 0.0;
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PeriphClkInitStruct.FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL2;
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if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
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{
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Error_Handler();
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}
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/* Peripheral clock enable */
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/* Peripheral clock enable */
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__HAL_RCC_FDCAN_CLK_ENABLE();
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__HAL_RCC_FDCAN_CLK_ENABLE();
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@ -1,5 +1,5 @@
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##########################################################################################################################
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##########################################################################################################################
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# File automatically-generated by tool: [projectgenerator] version: [4.5.0-RC5] date: [Wed Mar 26 19:38:08 CET 2025]
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# File automatically-generated by tool: [projectgenerator] version: [4.6.0-B36] date: [Sat Apr 26 19:50:03 CEST 2025]
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##########################################################################################################################
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##########################################################################################################################
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# ------------------------------------------------
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# ------------------------------------------------
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@ -150,7 +150,7 @@ CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)"
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# LDFLAGS
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# LDFLAGS
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#######################################
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#######################################
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# link script
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# link script
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LDSCRIPT = stm32h7a3ritx_flash.ld
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LDSCRIPT = STM32H7A3XX_FLASH.ld
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# libraries
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# libraries
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LIBS = -lc -lm -lnosys
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LIBS = -lc -lm -lnosys
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@ -1,6 +1,7 @@
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#MicroXplorer Configuration settings - do not modify
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#MicroXplorer Configuration settings - do not modify
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ADC1.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_10
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ADC1.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_10
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ADC1.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,OffsetNumber-0\#ChannelRegularConversion,OffsetSignedSaturation-0\#ChannelRegularConversion,NbrOfConversionFlag,master
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ADC1.ClockPrescaler=ADC_CLOCK_ASYNC_DIV2
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ADC1.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,OffsetNumber-0\#ChannelRegularConversion,OffsetSignedSaturation-0\#ChannelRegularConversion,NbrOfConversionFlag,master,ClockPrescaler
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ADC1.NbrOfConversionFlag=1
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ADC1.NbrOfConversionFlag=1
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ADC1.OffsetNumber-0\#ChannelRegularConversion=ADC_OFFSET_NONE
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ADC1.OffsetNumber-0\#ChannelRegularConversion=ADC_OFFSET_NONE
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ADC1.OffsetSignedSaturation-0\#ChannelRegularConversion=DISABLE
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ADC1.OffsetSignedSaturation-0\#ChannelRegularConversion=DISABLE
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@ -8,7 +9,8 @@ ADC1.Rank-0\#ChannelRegularConversion=1
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ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_1CYCLE_5
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ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_1CYCLE_5
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ADC1.master=1
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ADC1.master=1
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ADC2.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_10
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ADC2.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_10
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ADC2.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,OffsetNumber-0\#ChannelRegularConversion,OffsetSignedSaturation-0\#ChannelRegularConversion,NbrOfConversionFlag,SingleDiff-0\#ChannelRegularConversion
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ADC2.ClockPrescaler=ADC_CLOCK_ASYNC_DIV2
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ADC2.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,OffsetNumber-0\#ChannelRegularConversion,OffsetSignedSaturation-0\#ChannelRegularConversion,NbrOfConversionFlag,SingleDiff-0\#ChannelRegularConversion,ClockPrescaler
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ADC2.NbrOfConversionFlag=1
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ADC2.NbrOfConversionFlag=1
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ADC2.OffsetNumber-0\#ChannelRegularConversion=ADC_OFFSET_NONE
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ADC2.OffsetNumber-0\#ChannelRegularConversion=ADC_OFFSET_NONE
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ADC2.OffsetSignedSaturation-0\#ChannelRegularConversion=DISABLE
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ADC2.OffsetSignedSaturation-0\#ChannelRegularConversion=DISABLE
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@ -18,12 +20,12 @@ ADC2.SingleDiff-0\#ChannelRegularConversion=ADC_DIFFERENTIAL_ENDED
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CAD.formats=[]
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CAD.formats=[]
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CAD.pinconfig=Dual
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CAD.pinconfig=Dual
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CAD.provider=
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CAD.provider=
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FDCAN1.CalculateBaudRateNominal=533333
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FDCAN1.CalculateBaudRateNominal=500000
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FDCAN1.CalculateTimeBitNominal=1875
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FDCAN1.CalculateTimeBitNominal=2000
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FDCAN1.CalculateTimeQuantumNominal=46.875
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FDCAN1.CalculateTimeQuantumNominal=62.5
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FDCAN1.IPParameters=CalculateTimeQuantumNominal,CalculateTimeBitNominal,CalculateBaudRateNominal,StdFiltersNbr,NominalPrescaler,NominalTimeSeg1,NominalTimeSeg2,RxFifo0ElmtsNbr,TxFifoQueueElmtsNbr
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FDCAN1.IPParameters=CalculateTimeQuantumNominal,CalculateTimeBitNominal,CalculateBaudRateNominal,StdFiltersNbr,NominalPrescaler,NominalTimeSeg1,NominalTimeSeg2,RxFifo0ElmtsNbr,TxFifoQueueElmtsNbr
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FDCAN1.NominalPrescaler=2
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FDCAN1.NominalPrescaler=2
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FDCAN1.NominalTimeSeg1=31
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FDCAN1.NominalTimeSeg1=23
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FDCAN1.NominalTimeSeg2=8
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FDCAN1.NominalTimeSeg2=8
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FDCAN1.RxFifo0ElmtsNbr=16
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FDCAN1.RxFifo0ElmtsNbr=16
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FDCAN1.StdFiltersNbr=32
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FDCAN1.StdFiltersNbr=32
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@ -265,6 +267,7 @@ PH1-OSC_OUT.Signal=RCC_OSC_OUT
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PinOutPanel.RotationAngle=0
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PinOutPanel.RotationAngle=0
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ProjectManager.AskForMigrate=true
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ProjectManager.AskForMigrate=true
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ProjectManager.BackupPrevious=false
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ProjectManager.BackupPrevious=false
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ProjectManager.CompilerLinker=GCC
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ProjectManager.CompilerOptimize=6
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ProjectManager.CompilerOptimize=6
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ProjectManager.ComputerToolchain=false
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ProjectManager.ComputerToolchain=false
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ProjectManager.CoupleFile=false
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ProjectManager.CoupleFile=false
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@ -294,6 +297,7 @@ ProjectManager.UAScriptAfterPath=
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ProjectManager.UAScriptBeforePath=
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ProjectManager.UAScriptBeforePath=
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ProjectManager.UnderRoot=false
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ProjectManager.UnderRoot=false
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ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_FDCAN1_Init-FDCAN1-false-HAL-true,4-MX_TIM15_Init-TIM15-false-HAL-true,5-MX_SPI1_Init-SPI1-false-HAL-true,6-MX_SPI2_Init-SPI2-false-HAL-true,7-MX_ADC1_Init-ADC1-false-HAL-true,8-MX_ADC2_Init-ADC2-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true
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ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_FDCAN1_Init-FDCAN1-false-HAL-true,4-MX_TIM15_Init-TIM15-false-HAL-true,5-MX_SPI1_Init-SPI1-false-HAL-true,6-MX_SPI2_Init-SPI2-false-HAL-true,7-MX_ADC1_Init-ADC1-false-HAL-true,8-MX_ADC2_Init-ADC2-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true
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RCC.ADCCLockSelection=RCC_ADCCLKSOURCE_PLL3
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RCC.ADCFreq_Value=42666666.666666664
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RCC.ADCFreq_Value=42666666.666666664
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RCC.AHB12Freq_Value=64000000
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RCC.AHB12Freq_Value=64000000
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RCC.AHB4Freq_Value=64000000
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RCC.AHB4Freq_Value=64000000
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@ -315,21 +319,23 @@ RCC.DFSDMACLkFreq_Value=64000000
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RCC.DFSDMFreq_Value=64000000
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RCC.DFSDMFreq_Value=64000000
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RCC.DIVM1=1
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RCC.DIVM1=1
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RCC.DIVM2=1
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RCC.DIVM2=1
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RCC.DIVM3=1
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RCC.DIVN1=8
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RCC.DIVN1=8
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RCC.DIVN2=8
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RCC.DIVN2=8
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RCC.DIVN3=8
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RCC.DIVP1Freq_Value=64000000
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RCC.DIVP1Freq_Value=64000000
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RCC.DIVP2=3
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RCC.DIVP2Freq_Value=64000000
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RCC.DIVP2Freq_Value=42666666.666666664
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RCC.DIVP3Freq_Value=64000000
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RCC.DIVP3Freq_Value=32250000
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RCC.DIVQ1Freq_Value=64000000
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RCC.DIVQ1Freq_Value=64000000
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RCC.DIVQ2=3
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RCC.DIVQ2=4
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RCC.DIVQ2Freq_Value=42666666.666666664
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RCC.DIVQ2Freq_Value=32000000
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RCC.DIVQ3Freq_Value=32250000
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RCC.DIVQ3Freq_Value=64000000
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RCC.DIVR1Freq_Value=64000000
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RCC.DIVR1Freq_Value=64000000
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RCC.DIVR2Freq_Value=64000000
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RCC.DIVR2Freq_Value=64000000
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RCC.DIVR3Freq_Value=32250000
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RCC.DIVR3=3
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RCC.DIVR3Freq_Value=42666666.666666664
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RCC.FDCANCLockSelection=RCC_FDCANCLKSOURCE_PLL2
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RCC.FDCANCLockSelection=RCC_FDCANCLKSOURCE_PLL2
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RCC.FDCANFreq_Value=42666666.666666664
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RCC.FDCANFreq_Value=32000000
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RCC.FMCFreq_Value=64000000
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RCC.FMCFreq_Value=64000000
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RCC.FamilyName=M
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RCC.FamilyName=M
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RCC.HCLK3ClockFreq_Value=64000000
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RCC.HCLK3ClockFreq_Value=64000000
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@ -338,15 +344,16 @@ RCC.HSE_VALUE=16000000
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RCC.I2C123CLockSelection=RCC_I2C123CLKSOURCE_CSI
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RCC.I2C123CLockSelection=RCC_I2C123CLKSOURCE_CSI
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RCC.I2C123Freq_Value=4000000
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RCC.I2C123Freq_Value=4000000
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RCC.I2C4Freq_Value=64000000
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RCC.I2C4Freq_Value=64000000
|
||||||
RCC.IPParameters=ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CDCPREFreq_Value,CECFreq_Value,CKPERFreq_Value,CortexFreq_Value,CpuClockFreq_Value,DAC1Freq_Value,DAC2Freq_Value,DFSDM2ACLkFreq_Value,DFSDM2Freq_Value,DFSDMACLkFreq_Value,DFSDMFreq_Value,DIVM1,DIVM2,DIVN1,DIVN2,DIVP1Freq_Value,DIVP2,DIVP2Freq_Value,DIVP3Freq_Value,DIVQ1Freq_Value,DIVQ2,DIVQ2Freq_Value,DIVQ3Freq_Value,DIVR1Freq_Value,DIVR2Freq_Value,DIVR3Freq_Value,FDCANCLockSelection,FDCANFreq_Value,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,HSE_VALUE,I2C123CLockSelection,I2C123Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM345Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,PLL2FRACN,PLLFRACN,PLLSourceVirtual,QSPIFreq_Value,RNGFreq_Value,RTCFreq_Value,SAI1Freq_Value,SAI2AFreq_Value,SAI2BFreq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI123Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16Freq_Value,USART234578Freq_Value,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value
|
RCC.IPParameters=ADCCLockSelection,ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CDCPREFreq_Value,CECFreq_Value,CKPERFreq_Value,CortexFreq_Value,CpuClockFreq_Value,DAC1Freq_Value,DAC2Freq_Value,DFSDM2ACLkFreq_Value,DFSDM2Freq_Value,DFSDMACLkFreq_Value,DFSDMFreq_Value,DIVM1,DIVM2,DIVM3,DIVN1,DIVN2,DIVN3,DIVP1Freq_Value,DIVP2Freq_Value,DIVP3Freq_Value,DIVQ1Freq_Value,DIVQ2,DIVQ2Freq_Value,DIVQ3Freq_Value,DIVR1Freq_Value,DIVR2Freq_Value,DIVR3,DIVR3Freq_Value,FDCANCLockSelection,FDCANFreq_Value,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,HSE_VALUE,I2C123CLockSelection,I2C123Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM345Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,PLL2FRACN,PLL3FRACN,PLLFRACN,PLLSourceVirtual,QSPIFreq_Value,RNGFreq_Value,RTCFreq_Value,SAI1Freq_Value,SAI2AFreq_Value,SAI2BFreq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI123Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16Freq_Value,USART234578Freq_Value,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value
|
||||||
RCC.LPTIM1Freq_Value=64000000
|
RCC.LPTIM1Freq_Value=64000000
|
||||||
RCC.LPTIM2Freq_Value=64000000
|
RCC.LPTIM2Freq_Value=64000000
|
||||||
RCC.LPTIM345Freq_Value=64000000
|
RCC.LPTIM345Freq_Value=64000000
|
||||||
RCC.LPUART1Freq_Value=64000000
|
RCC.LPUART1Freq_Value=64000000
|
||||||
RCC.LTDCFreq_Value=32250000
|
RCC.LTDCFreq_Value=42666666.666666664
|
||||||
RCC.MCO1PinFreq_Value=64000000
|
RCC.MCO1PinFreq_Value=64000000
|
||||||
RCC.MCO2PinFreq_Value=64000000
|
RCC.MCO2PinFreq_Value=64000000
|
||||||
RCC.PLL2FRACN=0
|
RCC.PLL2FRACN=0
|
||||||
|
RCC.PLL3FRACN=0
|
||||||
RCC.PLLFRACN=0
|
RCC.PLLFRACN=0
|
||||||
RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
|
RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
|
||||||
RCC.QSPIFreq_Value=64000000
|
RCC.QSPIFreq_Value=64000000
|
||||||
@ -371,10 +378,10 @@ RCC.USART234578Freq_Value=64000000
|
|||||||
RCC.USBFreq_Value=64000000
|
RCC.USBFreq_Value=64000000
|
||||||
RCC.VCO1OutputFreq_Value=128000000
|
RCC.VCO1OutputFreq_Value=128000000
|
||||||
RCC.VCO2OutputFreq_Value=128000000
|
RCC.VCO2OutputFreq_Value=128000000
|
||||||
RCC.VCO3OutputFreq_Value=64500000
|
RCC.VCO3OutputFreq_Value=128000000
|
||||||
RCC.VCOInput1Freq_Value=16000000
|
RCC.VCOInput1Freq_Value=16000000
|
||||||
RCC.VCOInput2Freq_Value=16000000
|
RCC.VCOInput2Freq_Value=16000000
|
||||||
RCC.VCOInput3Freq_Value=500000
|
RCC.VCOInput3Freq_Value=16000000
|
||||||
SH.ADCx_INP10.0=ADC1_INP10,IN10-Single-Ended
|
SH.ADCx_INP10.0=ADC1_INP10,IN10-Single-Ended
|
||||||
SH.ADCx_INP10.1=ADC2_INP10,IN10-Differential
|
SH.ADCx_INP10.1=ADC2_INP10,IN10-Differential
|
||||||
SH.ADCx_INP10.ConfNb=2
|
SH.ADCx_INP10.ConfNb=2
|
||||||
|
|||||||
209
AMS_Master_Code/STM32H7A3XX_FLASH.ld
Normal file
209
AMS_Master_Code/STM32H7A3XX_FLASH.ld
Normal file
@ -0,0 +1,209 @@
|
|||||||
|
/*
|
||||||
|
******************************************************************************
|
||||||
|
**
|
||||||
|
|
||||||
|
** File : LinkerScript.ld
|
||||||
|
**
|
||||||
|
** Author : STM32CubeMX
|
||||||
|
**
|
||||||
|
** Abstract : Linker script for STM32H7A3RITx series
|
||||||
|
** 2048Kbytes FLASH and 1216Kbytes RAM
|
||||||
|
**
|
||||||
|
** Set heap size, stack size and stack location according
|
||||||
|
** to application requirements.
|
||||||
|
**
|
||||||
|
** Set memory bank area and size if external memory is used.
|
||||||
|
**
|
||||||
|
** Target : STMicroelectronics STM32
|
||||||
|
**
|
||||||
|
** Distribution: The file is distributed “as is,” without any warranty
|
||||||
|
** of any kind.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
** @attention
|
||||||
|
**
|
||||||
|
** <h2><center>© COPYRIGHT(c) 2025 STMicroelectronics</center></h2>
|
||||||
|
**
|
||||||
|
** Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
** are permitted provided that the following conditions are met:
|
||||||
|
** 1. Redistributions of source code must retain the above copyright notice,
|
||||||
|
** this list of conditions and the following disclaimer.
|
||||||
|
** 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
** this list of conditions and the following disclaimer in the documentation
|
||||||
|
** and/or other materials provided with the distribution.
|
||||||
|
** 3. Neither the name of STMicroelectronics nor the names of its contributors
|
||||||
|
** may be used to endorse or promote products derived from this software
|
||||||
|
** without specific prior written permission.
|
||||||
|
**
|
||||||
|
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||||
|
** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||||
|
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||||
|
** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||||
|
** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
**
|
||||||
|
*****************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Entry Point */
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
|
||||||
|
/* Highest address of the user mode stack */
|
||||||
|
_estack = ORIGIN(DTCMRAM) + LENGTH(DTCMRAM); /* end of RAM */
|
||||||
|
/* Generate a link error if heap and stack don't fit into RAM */
|
||||||
|
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||||
|
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||||
|
|
||||||
|
/* Specify the memory areas */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
DTCMRAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
|
||||||
|
RAM (xrw) : ORIGIN = 0x24000000, LENGTH = 1024K
|
||||||
|
ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K
|
||||||
|
FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 2048K
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Define output sections */
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
/* The startup code goes first into FLASH */
|
||||||
|
.isr_vector :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(.isr_vector)) /* Startup code */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* The program code and other data goes into FLASH */
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text) /* .text sections (code) */
|
||||||
|
*(.text*) /* .text* sections (code) */
|
||||||
|
*(.glue_7) /* glue arm to thumb code */
|
||||||
|
*(.glue_7t) /* glue thumb to arm code */
|
||||||
|
*(.eh_frame)
|
||||||
|
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etext = .; /* define a global symbols at end of code */
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* Constant data goes into FLASH */
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||||
|
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* used by the startup to initialize data */
|
||||||
|
_sidata = LOADADDR(.data);
|
||||||
|
|
||||||
|
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
_sdata = .; /* create a global symbol at data start */
|
||||||
|
*(.data) /* .data sections */
|
||||||
|
*(.data*) /* .data* sections */
|
||||||
|
*(.RamFunc) /* .RamFunc sections */
|
||||||
|
*(.RamFunc*) /* .RamFunc* sections */
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_edata = .; /* define a global symbol at data end */
|
||||||
|
} >DTCMRAM AT> FLASH
|
||||||
|
|
||||||
|
|
||||||
|
/* Uninitialized data section */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
/* This is used by the startup in order to initialize the .bss secion */
|
||||||
|
_sbss = .; /* define a global symbol at bss start */
|
||||||
|
__bss_start__ = _sbss;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
_ebss = .; /* define a global symbol at bss end */
|
||||||
|
__bss_end__ = _ebss;
|
||||||
|
} >DTCMRAM
|
||||||
|
|
||||||
|
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||||
|
._user_heap_stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
PROVIDE ( end = . );
|
||||||
|
PROVIDE ( _end = . );
|
||||||
|
. = . + _Min_Heap_Size;
|
||||||
|
. = . + _Min_Stack_Size;
|
||||||
|
. = ALIGN(8);
|
||||||
|
} >DTCMRAM
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* Remove information from the standard libraries */
|
||||||
|
/DISCARD/ :
|
||||||
|
{
|
||||||
|
libc.a ( * )
|
||||||
|
libm.a ( * )
|
||||||
|
libgcc.a ( * )
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
745
AMS_Master_Code/startup_stm32h7a3xx.s
Normal file
745
AMS_Master_Code/startup_stm32h7a3xx.s
Normal file
@ -0,0 +1,745 @@
|
|||||||
|
/**
|
||||||
|
******************************************************************************
|
||||||
|
* @file startup_stm32h7a3xx.s
|
||||||
|
* @author MCD Application Team
|
||||||
|
* @brief STM32H7B3xx Devices vector table for GCC based toolchain.
|
||||||
|
* This module performs:
|
||||||
|
* - Set the initial SP
|
||||||
|
* - Set the initial PC == Reset_Handler,
|
||||||
|
* - Set the vector table entries with the exceptions ISR address
|
||||||
|
* - Branches to main in the C library (which eventually
|
||||||
|
* calls main()).
|
||||||
|
* After Reset the Cortex-M processor is in Thread mode,
|
||||||
|
* priority is Privileged, and the Stack is set to Main.
|
||||||
|
******************************************************************************
|
||||||
|
* @attention
|
||||||
|
*
|
||||||
|
* Copyright (c) 2019 STMicroelectronics.
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* This software is licensed under terms that can be found in the LICENSE file
|
||||||
|
* in the root directory of this software component.
|
||||||
|
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||||
|
*
|
||||||
|
******************************************************************************
|
||||||
|
*/
|
||||||
|
|
||||||
|
.syntax unified
|
||||||
|
.cpu cortex-m7
|
||||||
|
.fpu softvfp
|
||||||
|
.thumb
|
||||||
|
|
||||||
|
.global g_pfnVectors
|
||||||
|
.global Default_Handler
|
||||||
|
|
||||||
|
/* start address for the initialization values of the .data section.
|
||||||
|
defined in linker script */
|
||||||
|
.word _sidata
|
||||||
|
/* start address for the .data section. defined in linker script */
|
||||||
|
.word _sdata
|
||||||
|
/* end address for the .data section. defined in linker script */
|
||||||
|
.word _edata
|
||||||
|
/* start address for the .bss section. defined in linker script */
|
||||||
|
.word _sbss
|
||||||
|
/* end address for the .bss section. defined in linker script */
|
||||||
|
.word _ebss
|
||||||
|
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor first
|
||||||
|
* starts execution following a reset event. Only the absolutely
|
||||||
|
* necessary set is performed, after which the application
|
||||||
|
* supplied main() routine is called.
|
||||||
|
* @param None
|
||||||
|
* @retval : None
|
||||||
|
*/
|
||||||
|
|
||||||
|
.section .text.Reset_Handler
|
||||||
|
.weak Reset_Handler
|
||||||
|
.type Reset_Handler, %function
|
||||||
|
Reset_Handler:
|
||||||
|
ldr sp, =_estack /* set stack pointer */
|
||||||
|
|
||||||
|
/* Call the ExitRun0Mode function to configure the power supply */
|
||||||
|
bl ExitRun0Mode
|
||||||
|
/* Call the clock system initialization function.*/
|
||||||
|
bl SystemInit
|
||||||
|
|
||||||
|
/* Copy the data segment initializers from flash to SRAM */
|
||||||
|
ldr r0, =_sdata
|
||||||
|
ldr r1, =_edata
|
||||||
|
ldr r2, =_sidata
|
||||||
|
movs r3, #0
|
||||||
|
b LoopCopyDataInit
|
||||||
|
|
||||||
|
CopyDataInit:
|
||||||
|
ldr r4, [r2, r3]
|
||||||
|
str r4, [r0, r3]
|
||||||
|
adds r3, r3, #4
|
||||||
|
|
||||||
|
LoopCopyDataInit:
|
||||||
|
adds r4, r0, r3
|
||||||
|
cmp r4, r1
|
||||||
|
bcc CopyDataInit
|
||||||
|
/* Zero fill the bss segment. */
|
||||||
|
ldr r2, =_sbss
|
||||||
|
ldr r4, =_ebss
|
||||||
|
movs r3, #0
|
||||||
|
b LoopFillZerobss
|
||||||
|
|
||||||
|
FillZerobss:
|
||||||
|
str r3, [r2]
|
||||||
|
adds r2, r2, #4
|
||||||
|
|
||||||
|
LoopFillZerobss:
|
||||||
|
cmp r2, r4
|
||||||
|
bcc FillZerobss
|
||||||
|
|
||||||
|
/* Call static constructors */
|
||||||
|
bl __libc_init_array
|
||||||
|
/* Call the application's entry point.*/
|
||||||
|
bl main
|
||||||
|
bx lr
|
||||||
|
.size Reset_Handler, .-Reset_Handler
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This is the code that gets called when the processor receives an
|
||||||
|
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||||
|
* the system state for examination by a debugger.
|
||||||
|
* @param None
|
||||||
|
* @retval None
|
||||||
|
*/
|
||||||
|
.section .text.Default_Handler,"ax",%progbits
|
||||||
|
Default_Handler:
|
||||||
|
Infinite_Loop:
|
||||||
|
b Infinite_Loop
|
||||||
|
.size Default_Handler, .-Default_Handler
|
||||||
|
/******************************************************************************
|
||||||
|
*
|
||||||
|
* The minimal vector table for a Cortex M. Note that the proper constructs
|
||||||
|
* must be placed on this to ensure that it ends up at physical address
|
||||||
|
* 0x0000.0000.
|
||||||
|
*
|
||||||
|
*******************************************************************************/
|
||||||
|
.section .isr_vector,"a",%progbits
|
||||||
|
.type g_pfnVectors, %object
|
||||||
|
|
||||||
|
|
||||||
|
g_pfnVectors:
|
||||||
|
.word _estack
|
||||||
|
.word Reset_Handler
|
||||||
|
|
||||||
|
.word NMI_Handler
|
||||||
|
.word HardFault_Handler
|
||||||
|
.word MemManage_Handler
|
||||||
|
.word BusFault_Handler
|
||||||
|
.word UsageFault_Handler
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word 0
|
||||||
|
.word SVC_Handler
|
||||||
|
.word DebugMon_Handler
|
||||||
|
.word 0
|
||||||
|
.word PendSV_Handler
|
||||||
|
.word SysTick_Handler
|
||||||
|
|
||||||
|
/* External Interrupts */
|
||||||
|
.word WWDG_IRQHandler /* Window WatchDog */
|
||||||
|
.word PVD_PVM_IRQHandler /* PVD/PVM through EXTI Line detection */
|
||||||
|
.word RTC_TAMP_STAMP_CSS_LSE_IRQHandler /* Tamper and TimeStamps through the EXTI line */
|
||||||
|
.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
|
||||||
|
.word FLASH_IRQHandler /* FLASH */
|
||||||
|
.word RCC_IRQHandler /* RCC */
|
||||||
|
.word EXTI0_IRQHandler /* EXTI Line0 */
|
||||||
|
.word EXTI1_IRQHandler /* EXTI Line1 */
|
||||||
|
.word EXTI2_IRQHandler /* EXTI Line2 */
|
||||||
|
.word EXTI3_IRQHandler /* EXTI Line3 */
|
||||||
|
.word EXTI4_IRQHandler /* EXTI Line4 */
|
||||||
|
.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
|
||||||
|
.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
|
||||||
|
.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
|
||||||
|
.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
|
||||||
|
.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
|
||||||
|
.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
|
||||||
|
.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
|
||||||
|
.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
|
||||||
|
.word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
|
||||||
|
.word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
|
||||||
|
.word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
|
||||||
|
.word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
|
||||||
|
.word EXTI9_5_IRQHandler /* External Line[9:5]s */
|
||||||
|
.word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
|
||||||
|
.word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
|
||||||
|
.word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
|
||||||
|
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
|
||||||
|
.word TIM2_IRQHandler /* TIM2 */
|
||||||
|
.word TIM3_IRQHandler /* TIM3 */
|
||||||
|
.word TIM4_IRQHandler /* TIM4 */
|
||||||
|
.word I2C1_EV_IRQHandler /* I2C1 Event */
|
||||||
|
.word I2C1_ER_IRQHandler /* I2C1 Error */
|
||||||
|
.word I2C2_EV_IRQHandler /* I2C2 Event */
|
||||||
|
.word I2C2_ER_IRQHandler /* I2C2 Error */
|
||||||
|
.word SPI1_IRQHandler /* SPI1 */
|
||||||
|
.word SPI2_IRQHandler /* SPI2 */
|
||||||
|
.word USART1_IRQHandler /* USART1 */
|
||||||
|
.word USART2_IRQHandler /* USART2 */
|
||||||
|
.word USART3_IRQHandler /* USART3 */
|
||||||
|
.word EXTI15_10_IRQHandler /* External Line[15:10]s */
|
||||||
|
.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
|
||||||
|
.word DFSDM2_IRQHandler /* DFSDM2 Interrupt */
|
||||||
|
.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
|
||||||
|
.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
|
||||||
|
.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
|
||||||
|
.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
|
||||||
|
.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
|
||||||
|
.word FMC_IRQHandler /* FMC */
|
||||||
|
.word SDMMC1_IRQHandler /* SDMMC1 */
|
||||||
|
.word TIM5_IRQHandler /* TIM5 */
|
||||||
|
.word SPI3_IRQHandler /* SPI3 */
|
||||||
|
.word UART4_IRQHandler /* UART4 */
|
||||||
|
.word UART5_IRQHandler /* UART5 */
|
||||||
|
.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
|
||||||
|
.word TIM7_IRQHandler /* TIM7 */
|
||||||
|
.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
|
||||||
|
.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
|
||||||
|
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
|
||||||
|
.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
|
||||||
|
.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/
|
||||||
|
.word DFSDM1_FLT4_IRQHandler /* DFSDM Filter4 Interrupt */
|
||||||
|
.word DFSDM1_FLT5_IRQHandler /* DFSDM Filter5 Interrupt */
|
||||||
|
.word DFSDM1_FLT6_IRQHandler /* DFSDM Filter6 Interrupt */
|
||||||
|
.word DFSDM1_FLT7_IRQHandler /* DFSDM Filter7 Interrupt */
|
||||||
|
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
|
||||||
|
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
|
||||||
|
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
|
||||||
|
.word USART6_IRQHandler /* USART6 */
|
||||||
|
.word I2C3_EV_IRQHandler /* I2C3 event */
|
||||||
|
.word I2C3_ER_IRQHandler /* I2C3 error */
|
||||||
|
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
|
||||||
|
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
|
||||||
|
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
|
||||||
|
.word OTG_HS_IRQHandler /* USB OTG HS */
|
||||||
|
.word DCMI_PSSI_IRQHandler /* DCMI, PSSI */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word RNG_IRQHandler /* RNG */
|
||||||
|
.word FPU_IRQHandler /* FPU */
|
||||||
|
.word UART7_IRQHandler /* UART7 */
|
||||||
|
.word UART8_IRQHandler /* UART8 */
|
||||||
|
.word SPI4_IRQHandler /* SPI4 */
|
||||||
|
.word SPI5_IRQHandler /* SPI5 */
|
||||||
|
.word SPI6_IRQHandler /* SPI6 */
|
||||||
|
.word SAI1_IRQHandler /* SAI1 */
|
||||||
|
.word LTDC_IRQHandler /* LTDC */
|
||||||
|
.word LTDC_ER_IRQHandler /* LTDC error */
|
||||||
|
.word DMA2D_IRQHandler /* DMA2D */
|
||||||
|
.word SAI2_IRQHandler /* SAI2 */
|
||||||
|
.word OCTOSPI1_IRQHandler /* OCTOSPI1 */
|
||||||
|
.word LPTIM1_IRQHandler /* LPTIM1 */
|
||||||
|
.word CEC_IRQHandler /* HDMI_CEC */
|
||||||
|
.word I2C4_EV_IRQHandler /* I2C4 Event */
|
||||||
|
.word I2C4_ER_IRQHandler /* I2C4 Error */
|
||||||
|
.word SPDIF_RX_IRQHandler /* SPDIF_RX */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
|
||||||
|
.word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
|
||||||
|
.word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
|
||||||
|
.word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
|
||||||
|
.word TIM15_IRQHandler /* TIM15 global Interrupt */
|
||||||
|
.word TIM16_IRQHandler /* TIM16 global Interrupt */
|
||||||
|
.word TIM17_IRQHandler /* TIM17 global Interrupt */
|
||||||
|
.word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
|
||||||
|
.word MDIOS_IRQHandler /* MDIOS global Interrupt */
|
||||||
|
.word JPEG_IRQHandler /* JPEG global Interrupt */
|
||||||
|
.word MDMA_IRQHandler /* MDMA global Interrupt */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
|
||||||
|
.word HSEM1_IRQHandler /* HSEM1 global Interrupt */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word DAC2_IRQHandler /* DAC2 global Interrupt */
|
||||||
|
.word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
|
||||||
|
.word BDMA2_Channel0_IRQHandler /* BDMA2 Channel 0 global Interrupt */
|
||||||
|
.word BDMA2_Channel1_IRQHandler /* BDMA2 Channel 1 global Interrupt */
|
||||||
|
.word BDMA2_Channel2_IRQHandler /* BDMA2 Channel 2 global Interrupt */
|
||||||
|
.word BDMA2_Channel3_IRQHandler /* BDMA2 Channel 3 global Interrupt */
|
||||||
|
.word BDMA2_Channel4_IRQHandler /* BDMA2 Channel 4 global Interrupt */
|
||||||
|
.word BDMA2_Channel5_IRQHandler /* BDMA2 Channel 5 global Interrupt */
|
||||||
|
.word BDMA2_Channel6_IRQHandler /* BDMA2 Channel 6 global Interrupt */
|
||||||
|
.word BDMA2_Channel7_IRQHandler /* BDMA2 Channel 7 global Interrupt */
|
||||||
|
.word COMP_IRQHandler /* COMP global Interrupt */
|
||||||
|
.word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
|
||||||
|
.word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
|
||||||
|
.word UART9_IRQHandler /* UART9 global interrupt */
|
||||||
|
.word USART10_IRQHandler /* USART10 global interrupt */
|
||||||
|
.word LPUART1_IRQHandler /* LP UART1 interrupt */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word CRS_IRQHandler /* Clock Recovery Global Interrupt */
|
||||||
|
.word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word DTS_IRQHandler /* DTS */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
|
||||||
|
.word OCTOSPI2_IRQHandler /* OCTOSPI2 */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word GFXMMU_IRQHandler /* GFXMMU */
|
||||||
|
.word BDMA1_IRQHandler /* BDMA1 */
|
||||||
|
|
||||||
|
.size g_pfnVectors, .-g_pfnVectors
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
*
|
||||||
|
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||||
|
* As they are weak aliases, any function with the same name will override
|
||||||
|
* this definition.
|
||||||
|
*
|
||||||
|
*******************************************************************************/
|
||||||
|
.weak NMI_Handler
|
||||||
|
.thumb_set NMI_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak HardFault_Handler
|
||||||
|
.thumb_set HardFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak MemManage_Handler
|
||||||
|
.thumb_set MemManage_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak BusFault_Handler
|
||||||
|
.thumb_set BusFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak UsageFault_Handler
|
||||||
|
.thumb_set UsageFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SVC_Handler
|
||||||
|
.thumb_set SVC_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak DebugMon_Handler
|
||||||
|
.thumb_set DebugMon_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak PendSV_Handler
|
||||||
|
.thumb_set PendSV_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SysTick_Handler
|
||||||
|
.thumb_set SysTick_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak WWDG_IRQHandler
|
||||||
|
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak PVD_PVM_IRQHandler
|
||||||
|
.thumb_set PVD_PVM_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_TAMP_STAMP_CSS_LSE_IRQHandler
|
||||||
|
.thumb_set RTC_TAMP_STAMP_CSS_LSE_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_WKUP_IRQHandler
|
||||||
|
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FLASH_IRQHandler
|
||||||
|
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RCC_IRQHandler
|
||||||
|
.thumb_set RCC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI0_IRQHandler
|
||||||
|
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI1_IRQHandler
|
||||||
|
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI2_IRQHandler
|
||||||
|
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI3_IRQHandler
|
||||||
|
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI4_IRQHandler
|
||||||
|
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream0_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream1_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream2_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream3_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream4_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream5_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream6_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ADC_IRQHandler
|
||||||
|
.thumb_set ADC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FDCAN1_IT0_IRQHandler
|
||||||
|
.thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FDCAN2_IT0_IRQHandler
|
||||||
|
.thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FDCAN1_IT1_IRQHandler
|
||||||
|
.thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FDCAN2_IT1_IRQHandler
|
||||||
|
.thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI9_5_IRQHandler
|
||||||
|
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_BRK_IRQHandler
|
||||||
|
.thumb_set TIM1_BRK_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_UP_IRQHandler
|
||||||
|
.thumb_set TIM1_UP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_TRG_COM_IRQHandler
|
||||||
|
.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_CC_IRQHandler
|
||||||
|
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM2_IRQHandler
|
||||||
|
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM3_IRQHandler
|
||||||
|
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM4_IRQHandler
|
||||||
|
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_EV_IRQHandler
|
||||||
|
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_ER_IRQHandler
|
||||||
|
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_EV_IRQHandler
|
||||||
|
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_ER_IRQHandler
|
||||||
|
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI1_IRQHandler
|
||||||
|
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI2_IRQHandler
|
||||||
|
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART1_IRQHandler
|
||||||
|
.thumb_set USART1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART2_IRQHandler
|
||||||
|
.thumb_set USART2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART3_IRQHandler
|
||||||
|
.thumb_set USART3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI15_10_IRQHandler
|
||||||
|
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_Alarm_IRQHandler
|
||||||
|
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DFSDM2_IRQHandler
|
||||||
|
.thumb_set DFSDM2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM8_BRK_TIM12_IRQHandler
|
||||||
|
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM8_UP_TIM13_IRQHandler
|
||||||
|
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM8_TRG_COM_TIM14_IRQHandler
|
||||||
|
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM8_CC_IRQHandler
|
||||||
|
.thumb_set TIM8_CC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Stream7_IRQHandler
|
||||||
|
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FMC_IRQHandler
|
||||||
|
.thumb_set FMC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SDMMC1_IRQHandler
|
||||||
|
.thumb_set SDMMC1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM5_IRQHandler
|
||||||
|
.thumb_set TIM5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI3_IRQHandler
|
||||||
|
.thumb_set SPI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART4_IRQHandler
|
||||||
|
.thumb_set UART4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART5_IRQHandler
|
||||||
|
.thumb_set UART5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM6_DAC_IRQHandler
|
||||||
|
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM7_IRQHandler
|
||||||
|
.thumb_set TIM7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream0_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream1_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream2_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream3_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream4_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FDCAN_CAL_IRQHandler
|
||||||
|
.thumb_set FDCAN_CAL_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DFSDM1_FLT4_IRQHandler
|
||||||
|
.thumb_set DFSDM1_FLT4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DFSDM1_FLT5_IRQHandler
|
||||||
|
.thumb_set DFSDM1_FLT5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DFSDM1_FLT6_IRQHandler
|
||||||
|
.thumb_set DFSDM1_FLT6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DFSDM1_FLT7_IRQHandler
|
||||||
|
.thumb_set DFSDM1_FLT7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream5_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream6_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2_Stream7_IRQHandler
|
||||||
|
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART6_IRQHandler
|
||||||
|
.thumb_set USART6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C3_EV_IRQHandler
|
||||||
|
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C3_ER_IRQHandler
|
||||||
|
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_HS_EP1_OUT_IRQHandler
|
||||||
|
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_HS_EP1_IN_IRQHandler
|
||||||
|
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_HS_WKUP_IRQHandler
|
||||||
|
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OTG_HS_IRQHandler
|
||||||
|
.thumb_set OTG_HS_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DCMI_PSSI_IRQHandler
|
||||||
|
.thumb_set DCMI_PSSI_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RNG_IRQHandler
|
||||||
|
.thumb_set RNG_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FPU_IRQHandler
|
||||||
|
.thumb_set FPU_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART7_IRQHandler
|
||||||
|
.thumb_set UART7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART8_IRQHandler
|
||||||
|
.thumb_set UART8_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI4_IRQHandler
|
||||||
|
.thumb_set SPI4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI5_IRQHandler
|
||||||
|
.thumb_set SPI5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI6_IRQHandler
|
||||||
|
.thumb_set SPI6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SAI1_IRQHandler
|
||||||
|
.thumb_set SAI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LTDC_IRQHandler
|
||||||
|
.thumb_set LTDC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LTDC_ER_IRQHandler
|
||||||
|
.thumb_set LTDC_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA2D_IRQHandler
|
||||||
|
.thumb_set DMA2D_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SAI2_IRQHandler
|
||||||
|
.thumb_set SAI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OCTOSPI1_IRQHandler
|
||||||
|
.thumb_set OCTOSPI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LPTIM1_IRQHandler
|
||||||
|
.thumb_set LPTIM1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CEC_IRQHandler
|
||||||
|
.thumb_set CEC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C4_EV_IRQHandler
|
||||||
|
.thumb_set I2C4_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C4_ER_IRQHandler
|
||||||
|
.thumb_set I2C4_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPDIF_RX_IRQHandler
|
||||||
|
.thumb_set SPDIF_RX_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMAMUX1_OVR_IRQHandler
|
||||||
|
.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DFSDM1_FLT0_IRQHandler
|
||||||
|
.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DFSDM1_FLT1_IRQHandler
|
||||||
|
.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DFSDM1_FLT2_IRQHandler
|
||||||
|
.thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DFSDM1_FLT3_IRQHandler
|
||||||
|
.thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SWPMI1_IRQHandler
|
||||||
|
.thumb_set SWPMI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM15_IRQHandler
|
||||||
|
.thumb_set TIM15_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM16_IRQHandler
|
||||||
|
.thumb_set TIM16_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM17_IRQHandler
|
||||||
|
.thumb_set TIM17_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak MDIOS_WKUP_IRQHandler
|
||||||
|
.thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak MDIOS_IRQHandler
|
||||||
|
.thumb_set MDIOS_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak JPEG_IRQHandler
|
||||||
|
.thumb_set JPEG_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak MDMA_IRQHandler
|
||||||
|
.thumb_set MDMA_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SDMMC2_IRQHandler
|
||||||
|
.thumb_set SDMMC2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak HSEM1_IRQHandler
|
||||||
|
.thumb_set HSEM1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DAC2_IRQHandler
|
||||||
|
.thumb_set DAC2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMAMUX2_OVR_IRQHandler
|
||||||
|
.thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA2_Channel0_IRQHandler
|
||||||
|
.thumb_set BDMA2_Channel0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA2_Channel1_IRQHandler
|
||||||
|
.thumb_set BDMA2_Channel1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA2_Channel2_IRQHandler
|
||||||
|
.thumb_set BDMA2_Channel2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA2_Channel3_IRQHandler
|
||||||
|
.thumb_set BDMA2_Channel3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA2_Channel4_IRQHandler
|
||||||
|
.thumb_set BDMA2_Channel4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA2_Channel5_IRQHandler
|
||||||
|
.thumb_set BDMA2_Channel5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA2_Channel6_IRQHandler
|
||||||
|
.thumb_set BDMA2_Channel6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA2_Channel7_IRQHandler
|
||||||
|
.thumb_set BDMA2_Channel7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak COMP_IRQHandler
|
||||||
|
.thumb_set COMP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LPTIM2_IRQHandler
|
||||||
|
.thumb_set LPTIM2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LPTIM3_IRQHandler
|
||||||
|
.thumb_set LPTIM3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LPTIM4_IRQHandler
|
||||||
|
.thumb_set LPTIM4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LPTIM5_IRQHandler
|
||||||
|
.thumb_set LPTIM5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART9_IRQHandler
|
||||||
|
.thumb_set UART9_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART10_IRQHandler
|
||||||
|
.thumb_set USART10_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LPUART1_IRQHandler
|
||||||
|
.thumb_set LPUART1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CRS_IRQHandler
|
||||||
|
.thumb_set CRS_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ECC_IRQHandler
|
||||||
|
.thumb_set ECC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DTS_IRQHandler
|
||||||
|
.thumb_set DTS_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak WAKEUP_PIN_IRQHandler
|
||||||
|
.thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak OCTOSPI2_IRQHandler
|
||||||
|
.thumb_set OCTOSPI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak GFXMMU_IRQHandler
|
||||||
|
.thumb_set GFXMMU_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak BDMA1_IRQHandler
|
||||||
|
.thumb_set BDMA1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
|
||||||
Loading…
x
Reference in New Issue
Block a user