ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 1


   1              		.cpu cortex-m7
   2              		.arch armv7e-m
   3              		.fpu fpv5-d16
   4              		.eabi_attribute 28, 1
   5              		.eabi_attribute 20, 1
   6              		.eabi_attribute 21, 1
   7              		.eabi_attribute 23, 3
   8              		.eabi_attribute 24, 1
   9              		.eabi_attribute 25, 1
  10              		.eabi_attribute 26, 1
  11              		.eabi_attribute 30, 1
  12              		.eabi_attribute 34, 1
  13              		.eabi_attribute 18, 4
  14              		.file	"stm32h7xx_hal_pwr_ex.c"
  15              		.text
  16              	.Ltext0:
  17              		.cfi_sections	.debug_frame
  18              		.file 1 "Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c"
  19              		.section	.text.HAL_PWREx_ConfigSupply,"ax",%progbits
  20              		.align	1
  21              		.global	HAL_PWREx_ConfigSupply
  22              		.syntax unified
  23              		.thumb
  24              		.thumb_func
  26              	HAL_PWREx_ConfigSupply:
  27              	.LVL0:
  28              	.LFB335:
   1:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
   2:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   ******************************************************************************
   3:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @file    stm32h7xx_hal_pwr_ex.c
   4:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @author  MCD Application Team
   5:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief   Extended PWR HAL module driver.
   6:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *          This file provides firmware functions to manage the following
   7:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *          functionalities of PWR extension peripheral:
   8:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *           + Peripheral Extended features functions
   9:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   ******************************************************************************
  10:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @attention
  11:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *
  12:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * Copyright (c) 2017 STMicroelectronics.
  13:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * All rights reserved.
  14:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *
  15:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * This software is licensed under terms that can be found in the LICENSE file
  16:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * in the root directory of this software component.
  17:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
  18:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *
  19:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   ******************************************************************************
  20:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   @verbatim
  21:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   ==============================================================================
  22:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****                         ##### How to use this driver #####
  23:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   ==============================================================================
  24:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   [..]
  25:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****    (#) Call HAL_PWREx_ConfigSupply() function to configure the regulator supply
  26:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        with the following different setups according to hardware (support SMPS):
  27:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        (+) PWR_DIRECT_SMPS_SUPPLY
  28:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        (+) PWR_SMPS_1V8_SUPPLIES_LDO
  29:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        (+) PWR_SMPS_2V5_SUPPLIES_LDO
  30:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        (+) PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 2


  31:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        (+) PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO
  32:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        (+) PWR_SMPS_1V8_SUPPLIES_EXT
  33:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        (+) PWR_SMPS_2V5_SUPPLIES_EXT
  34:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        (+) PWR_LDO_SUPPLY
  35:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        (+) PWR_EXTERNAL_SOURCE_SUPPLY
  36:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
  37:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****    (#) Call HAL_PWREx_GetSupplyConfig() function to get the current supply setup.
  38:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
  39:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****    (#) Call HAL_PWREx_ControlVoltageScaling() function to configure the main
  40:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        internal regulator output voltage. The voltage scaling could be one of
  41:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        the following scales :
  42:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        (+) PWR_REGULATOR_VOLTAGE_SCALE0
  43:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        (+) PWR_REGULATOR_VOLTAGE_SCALE1
  44:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        (+) PWR_REGULATOR_VOLTAGE_SCALE2
  45:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        (+) PWR_REGULATOR_VOLTAGE_SCALE3
  46:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
  47:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****    (#) Call HAL_PWREx_GetVoltageRange() function to get the current output
  48:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        voltage applied to the main regulator.
  49:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
  50:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****    (#) Call HAL_PWREx_ControlStopModeVoltageScaling() function to configure the
  51:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        main internal regulator output voltage in STOP mode. The voltage scaling
  52:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        in STOP mode could be one of the following scales :
  53:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        (+) PWR_REGULATOR_SVOS_SCALE3
  54:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        (+) PWR_REGULATOR_SVOS_SCALE4
  55:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        (+) PWR_REGULATOR_SVOS_SCALE5
  56:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
  57:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****    (#) Call HAL_PWREx_GetStopModeVoltageRange() function to get the current
  58:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        output voltage applied to the main regulator in STOP mode.
  59:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
  60:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****    (#) Call HAL_PWREx_EnterSTOP2Mode() function to enter the system in STOP mode
  61:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        with core domain in D2STOP mode. This API is used only for STM32H7Axxx
  62:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        and STM32H7Bxxx devices.
  63:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        Please ensure to clear all CPU pending events by calling
  64:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx
  65:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        in DEEP-SLEEP mode with __WFE() entry.
  66:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
  67:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****    (#) Call HAL_PWREx_EnterSTOPMode() function to enter the selected domain in
  68:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        DSTOP mode. Call this API with all available power domains to enter the
  69:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        system in STOP mode.
  70:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        Please ensure to clear all CPU pending events by calling
  71:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        HAL_PWREx_ClearPendingEvent() function when trying to enter the Cortex-Mx
  72:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        in DEEP-SLEEP mode with __WFE() entry.
  73:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
  74:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****    (#) Call HAL_PWREx_ClearPendingEvent() function always before entring the
  75:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        Cortex-Mx in any low power mode (SLEEP/DEEP-SLEEP) using WFE entry.
  76:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
  77:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****    (#) Call HAL_PWREx_EnterSTANDBYMode() function to enter the selected domain
  78:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        in DSTANDBY mode. Call this API with all available power domains to enter
  79:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        the system in STANDBY mode.
  80:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
  81:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****    (#) Call HAL_PWREx_ConfigD3Domain() function to setup the D3/SRD domain state
  82:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        (RUN/STOP) when the system enter to low power mode.
  83:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
  84:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****    (#) Call HAL_PWREx_ClearDomainFlags() function to clear the CPU flags for the
  85:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        selected power domain. This API is used only for dual core devices.
  86:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
  87:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****    (#) Call HAL_PWREx_HoldCore() and HAL_PWREx_ReleaseCore() functions to hold
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 3


  88:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        and release the selected CPU and and their domain peripherals when
  89:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        exiting STOP mode. These APIs are used only for dual core devices.
  90:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
  91:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****    (#) Call HAL_PWREx_EnableFlashPowerDown() and
  92:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        HAL_PWREx_DisableFlashPowerDown() functions to enable and disable the
  93:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        Flash Power Down in STOP mode.
  94:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
  95:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****    (#) Call HAL_PWREx_EnableMemoryShutOff() and
  96:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        HAL_PWREx_DisableMemoryShutOff() functions to enable and disable the
  97:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        memory block shut-off in DStop or DStop2. These APIs are used only for
  98:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        STM32H7Axxx and STM32H7Bxxx lines.
  99:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****    (#) Call HAL_PWREx_EnableWakeUpPin() and HAL_PWREx_DisableWakeUpPin()
 101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        functions to enable and disable the Wake-up pin functionality for
 102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        the selected pin.
 103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****    (#) Call HAL_PWREx_GetWakeupFlag() and HAL_PWREx_ClearWakeupFlag()
 105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        functions to manage wake-up flag for the selected pin.
 106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****    (#) Call HAL_PWREx_WAKEUP_PIN_IRQHandler() function to handle all wake-up
 108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        pins interrupts.
 109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****    (#) Call HAL_PWREx_EnableBkUpReg() and HAL_PWREx_DisableBkUpReg() functions
 111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        to enable and disable the backup domain regulator.
 112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****    (#) Call HAL_PWREx_EnableUSBReg(), HAL_PWREx_DisableUSBReg(),
 114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        HAL_PWREx_EnableUSBVoltageDetector() and
 115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        HAL_PWREx_DisableUSBVoltageDetector() functions to manage USB power
 116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        regulation functionalities.
 117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****    (#) Call HAL_PWREx_EnableBatteryCharging() and
 119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        HAL_PWREx_DisableBatteryCharging() functions to enable and disable the
 120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        battery charging feature with the selected resistor.
 121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****    (#) Call HAL_PWREx_EnableAnalogBooster() and
 123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        HAL_PWREx_DisableAnalogBooster() functions to enable and disable the
 124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        AVD boost feature when the VDD supply voltage is below 2V7.
 125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****    (#) Call HAL_PWREx_EnableMonitoring() and HAL_PWREx_DisableMonitoring()
 127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        functions to enable and disable the VBAT and Temperature monitoring.
 128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        When VBAT and Temperature monitoring feature is enables, use
 129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        HAL_PWREx_GetTemperatureLevel() and HAL_PWREx_GetVBATLevel() to get
 130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        respectively the Temperature level and VBAT level.
 131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****    (#) Call HAL_PWREx_GetMMCVoltage() and HAL_PWREx_DisableMonitoring()
 133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        function to get VDDMMC voltage level. This API is used only for
 134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        STM32H7Axxx and STM32H7Bxxx lines
 135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****    (#) Call HAL_PWREx_ConfigAVD() after setting parameter to be configured
 137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        (event mode and voltage threshold) in order to set up the Analog Voltage
 138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        Detector then use HAL_PWREx_EnableAVD() and  HAL_PWREx_DisableAVD()
 139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        functions to start and stop the AVD detection.
 140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        (+) AVD level could be one of the following values :
 141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****              (++) 1V7
 142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****              (++) 2V1
 143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****              (++) 2V5
 144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****              (++) 2V8
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 4


 145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****    (#) Call HAL_PWREx_PVD_AVD_IRQHandler() function to handle the PWR PVD and
 147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        AVD interrupt request.
 148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   @endverbatim
 150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
 151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Includes ------------------------------------------------------------------*/
 153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #include "stm32h7xx_hal.h"
 154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** @addtogroup STM32H7xx_HAL_Driver
 156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @{
 157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
 158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** @defgroup PWREx PWREx
 160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief PWR Extended HAL module driver
 161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @{
 162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
 163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #ifdef HAL_PWR_MODULE_ENABLED
 165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Private typedef -----------------------------------------------------------*/
 167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Private define ------------------------------------------------------------*/
 168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** @addtogroup PWREx_Private_Constants
 170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @{
 171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
 172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** @defgroup PWREx_AVD_Mode_Mask PWR Extended AVD Mode Mask
 174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @{
 175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
 176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #define AVD_MODE_IT              (0x00010000U)
 177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #define AVD_MODE_EVT             (0x00020000U)
 178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #define AVD_RISING_EDGE          (0x00000001U)
 179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #define AVD_FALLING_EDGE         (0x00000002U)
 180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #define AVD_RISING_FALLING_EDGE  (0x00000003U)
 181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
 182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @}
 183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
 184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** @defgroup PWREx_REG_SET_TIMEOUT PWR Extended Flag Setting Time Out Value
 186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @{
 187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
 188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #define PWR_FLAG_SETTING_DELAY   (1000U)
 189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
 190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @}
 191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
 192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** @defgroup PWREx_WakeUp_Pins_Offsets PWREx Wake-Up Pins masks and offsets
 194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @{
 195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
 196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Wake-Up Pins EXTI register mask */
 197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (EXTI_IMR2_IM57)
 198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #define PWR_EXTI_WAKEUP_PINS_MASK  (EXTI_IMR2_IM55 | EXTI_IMR2_IM56 |\
 199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****                                     EXTI_IMR2_IM57 | EXTI_IMR2_IM58 |\
 200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****                                     EXTI_IMR2_IM59 | EXTI_IMR2_IM60)
 201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #else
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 5


 202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #define PWR_EXTI_WAKEUP_PINS_MASK  (EXTI_IMR2_IM55 | EXTI_IMR2_IM56 |\
 203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****                                     EXTI_IMR2_IM58 | EXTI_IMR2_IM60)
 204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (EXTI_IMR2_IM57) */
 205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Wake-Up Pins PWR Pin Pull shift offsets */
 207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #define PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET (2U)
 208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
 209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @}
 210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
 211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
 213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @}
 214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
 215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Private macro -------------------------------------------------------------*/
 217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Private variables ---------------------------------------------------------*/
 218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Private function prototypes -----------------------------------------------*/
 219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Private functions ---------------------------------------------------------*/
 220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Exported types ------------------------------------------------------------*/
 221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /* Exported functions --------------------------------------------------------*/
 222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** @defgroup PWREx_Exported_Functions PWREx Exported Functions
 224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @{
 225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
 226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** @defgroup PWREx_Exported_Functions_Group1 Power Supply Control Functions
 228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief    Power supply control functions
 229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *
 230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** @verbatim
 231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****  ===============================================================================
 232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****                   ##### Power supply control functions #####
 233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****  ===============================================================================
 234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     [..]
 235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****    (#) When the system is powered on, the POR monitors VDD supply. Once VDD is
 236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        above the POR threshold level, the voltage regulator is enabled in the
 237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        default supply configuration:
 238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       (+) The Voltage converter output level is set at 1V0 in accordance with
 239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           the VOS3 level configured in PWR (D3/SRD) domain control register
 240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           (PWR_D3CR/PWR_SRDCR).
 241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       (+) The system is kept in reset mode as long as VCORE is not ok.
 242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       (+) Once VCORE is ok, the system is taken out of reset and the HSI
 243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           oscillator is enabled.
 244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       (+) Once the oscillator is stable, the system is initialized: Flash memory
 245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           and option bytes are loaded and the CPU starts in Run* mode.
 246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       (+) The software shall then initialize the system including supply
 247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           configuration programming using the HAL_PWREx_ConfigSupply().
 248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       (+) Once the supply configuration has been configured, the
 249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           HAL_PWREx_ConfigSupply() function checks the ACTVOSRDY bit in PWR
 250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           control status register 1 (PWR_CSR1) to guarantee a valid voltage
 251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           levels:
 252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        (++) As long as ACTVOSRDY indicates that voltage levels are invalid, the
 253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****             system is in limited Run* mode, write accesses to the RAMs are not
 254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****             permitted and VOS shall not be changed.
 255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        (++) Once ACTVOSRDY indicates that voltage levels are valid, the system
 256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****             is in normal Run mode, write accesses to RAMs are allowed and VOS
 257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****             can be changed.
 258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
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 259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** @endverbatim
 260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @{
 261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
 262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
 264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief Configure the system Power Supply.
 265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @param  SupplySource : Specifies the Power Supply source to set after a
 266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                        system startup.
 267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         This parameter can be one of the following values :
 268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_DIRECT_SMPS_SUPPLY : The SMPS supplies the Vcore Power
 269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                                          Domains. The LDO is Bypassed.
 270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_SMPS_1V8_SUPPLIES_LDO : The SMPS 1.8V output supplies
 271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                                             the LDO. The Vcore Power Domains
 272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                                             are supplied from the LDO.
 273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_SMPS_2V5_SUPPLIES_LDO : The SMPS 2.5V output supplies
 274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                                             the LDO. The Vcore Power Domains
 275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                                             are supplied from the LDO.
 276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO : The SMPS 1.8V output
 277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                                                     supplies external
 278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                                                     circuits and the LDO.
 279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                                                     The Vcore Power Domains
 280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                                                     are supplied from the
 281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                                                     LDO.
 282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO : The SMPS 2.5V output
 283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                                                     supplies external
 284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                                                     circuits and the LDO.
 285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                                                     The Vcore Power Domains
 286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                                                     are supplied from the
 287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                                                     LDO.
 288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_SMPS_1V8_SUPPLIES_EXT : The SMPS 1.8V output supplies
 289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                                             external circuits. The LDO is
 290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                                             Bypassed. The Vcore Power
 291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                                             Domains are supplied from
 292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                                             external source.
 293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_SMPS_2V5_SUPPLIES_EXT : The SMPS 2.5V output supplies
 294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                                             external circuits. The LDO is
 295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                                             Bypassed. The Vcore Power
 296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                                             Domains are supplied from
 297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                                             external source.
 298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_LDO_SUPPLY : The LDO regulator supplies the Vcore Power
 299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                                  Domains. The SMPS regulator is Bypassed.
 300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_EXTERNAL_SOURCE_SUPPLY : The SMPS and the LDO are
 301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                                              Bypassed. The Vcore Power
 302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                                              Domains are supplied from
 303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                                              external source.
 304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @note   The PWR_LDO_SUPPLY and PWR_EXTERNAL_SOURCE_SUPPLY are used by all
 305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         H7 lines.
 306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         The PWR_DIRECT_SMPS_SUPPLY, PWR_SMPS_1V8_SUPPLIES_LDO,
 307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         PWR_SMPS_2V5_SUPPLIES_LDO, PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO,
 308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO, PWR_SMPS_1V8_SUPPLIES_EXT and
 309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         PWR_SMPS_2V5_SUPPLIES_EXT are used only for lines that supports SMPS
 310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         regulator.
 311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @retval HAL status.
 312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
 313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_ConfigSupply (uint32_t SupplySource)
 314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
  29              		.loc 1 314 1 view -0
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 7


  30              		.cfi_startproc
  31              		@ args = 0, pretend = 0, frame = 0
  32              		@ frame_needed = 0, uses_anonymous_args = 0
 315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   uint32_t tickstart;
  33              		.loc 1 315 3 view .LVU1
 316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Check the parameters */
 318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   assert_param (IS_PWR_SUPPLY (SupplySource));
  34              		.loc 1 318 3 view .LVU2
 319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Check if supply source was configured */
 321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (PWR_FLAG_SCUEN)
 322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   if (__HAL_PWR_GET_FLAG (PWR_FLAG_SCUEN) == 0U)
  35              		.loc 1 322 3 view .LVU3
  36              		.loc 1 322 7 is_stmt 0 view .LVU4
  37 0000 134B     		ldr	r3, .L12
  38 0002 DB68     		ldr	r3, [r3, #12]
  39              		.loc 1 322 6 view .LVU5
  40 0004 13F0040F 		tst	r3, #4
  41 0008 07D1     		bne	.L2
 323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #else
 324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   if ((PWR->CR3 & (PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)) != (PWR_CR3_SMPSEN | PWR_CR3_L
 325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (PWR_FLAG_SCUEN) */
 326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
 327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* Check supply configuration */
 328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     if ((PWR->CR3 & PWR_SUPPLY_CONFIG_MASK) != SupplySource)
  42              		.loc 1 328 5 is_stmt 1 view .LVU6
  43              		.loc 1 328 13 is_stmt 0 view .LVU7
  44 000a 114B     		ldr	r3, .L12
  45 000c DB68     		ldr	r3, [r3, #12]
  46              		.loc 1 328 19 view .LVU8
  47 000e 03F00703 		and	r3, r3, #7
  48              		.loc 1 328 8 view .LVU9
  49 0012 8342     		cmp	r3, r0
  50 0014 1AD0     		beq	.L6
 329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     {
 330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       /* Supply configuration update locked, can't apply a new supply config */
 331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       return HAL_ERROR;
  51              		.loc 1 331 14 view .LVU10
  52 0016 0120     		movs	r0, #1
  53              	.LVL1:
  54              		.loc 1 331 14 view .LVU11
  55 0018 7047     		bx	lr
  56              	.LVL2:
  57              	.L2:
 314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   uint32_t tickstart;
  58              		.loc 1 314 1 view .LVU12
  59 001a 10B5     		push	{r4, lr}
  60              		.cfi_def_cfa_offset 8
  61              		.cfi_offset 4, -8
  62              		.cfi_offset 14, -4
 332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     }
 333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     else
 334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     {
 335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       /* Supply configuration update locked, but new supply configuration
 336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****          matches with old supply configuration : nothing to do
 337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       */
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 8


 338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       return HAL_OK;
 339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     }
 340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
 341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Set the power supply configuration */
 343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   MODIFY_REG (PWR->CR3, PWR_SUPPLY_CONFIG_MASK, SupplySource);
  63              		.loc 1 343 3 is_stmt 1 view .LVU13
  64 001c 0C4A     		ldr	r2, .L12
  65 001e D368     		ldr	r3, [r2, #12]
  66 0020 23F00703 		bic	r3, r3, #7
  67 0024 0343     		orrs	r3, r3, r0
  68 0026 D360     		str	r3, [r2, #12]
 344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Get tick */
 346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   tickstart = HAL_GetTick ();
  69              		.loc 1 346 3 view .LVU14
  70              		.loc 1 346 15 is_stmt 0 view .LVU15
  71 0028 FFF7FEFF 		bl	HAL_GetTick
  72              	.LVL3:
  73              		.loc 1 346 15 view .LVU16
  74 002c 0446     		mov	r4, r0
  75              	.LVL4:
 347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Wait till voltage level flag is set */
 349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U)
  76              		.loc 1 349 3 is_stmt 1 view .LVU17
  77              	.L4:
  78              		.loc 1 349 50 view .LVU18
  79              		.loc 1 349 10 is_stmt 0 view .LVU19
  80 002e 084B     		ldr	r3, .L12
  81 0030 5B68     		ldr	r3, [r3, #4]
  82              		.loc 1 349 50 view .LVU20
  83 0032 13F4005F 		tst	r3, #8192
  84 0036 07D1     		bne	.L11
 350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
 351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY)
  85              		.loc 1 351 5 is_stmt 1 view .LVU21
  86              		.loc 1 351 10 is_stmt 0 view .LVU22
  87 0038 FFF7FEFF 		bl	HAL_GetTick
  88              	.LVL5:
  89              		.loc 1 351 25 discriminator 1 view .LVU23
  90 003c 001B     		subs	r0, r0, r4
  91              		.loc 1 351 8 discriminator 1 view .LVU24
  92 003e B0F57A7F 		cmp	r0, #1000
  93 0042 F4D9     		bls	.L4
 352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     {
 353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       return HAL_ERROR;
  94              		.loc 1 353 14 view .LVU25
  95 0044 0120     		movs	r0, #1
  96 0046 00E0     		b	.L3
  97              	.L11:
 354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     }
 355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
 356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (SMPS)
 358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* When the SMPS supplies external circuits verify that SDEXTRDY flag is set */
 359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   if ((SupplySource == PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) ||
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 9


 360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       (SupplySource == PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) ||
 361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       (SupplySource == PWR_SMPS_1V8_SUPPLIES_EXT)         ||
 362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       (SupplySource == PWR_SMPS_2V5_SUPPLIES_EXT))
 363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
 364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* Get the current tick number */
 365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     tickstart = HAL_GetTick ();
 366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* Wait till SMPS external supply ready flag is set */
 368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     while (__HAL_PWR_GET_FLAG (PWR_FLAG_SMPSEXTRDY) == 0U)
 369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     {
 370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY)
 371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       {
 372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         return HAL_ERROR;
 373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       }
 374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     }
 375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
 376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (SMPS) */
 377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   return HAL_OK;
  98              		.loc 1 378 10 view .LVU26
  99 0048 0020     		movs	r0, #0
 100              	.L3:
 379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
 101              		.loc 1 379 1 view .LVU27
 102 004a 10BD     		pop	{r4, pc}
 103              	.LVL6:
 104              	.L6:
 105              		.cfi_def_cfa_offset 0
 106              		.cfi_restore 4
 107              		.cfi_restore 14
 338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     }
 108              		.loc 1 338 14 view .LVU28
 109 004c 0020     		movs	r0, #0
 110              	.LVL7:
 111              		.loc 1 379 1 view .LVU29
 112 004e 7047     		bx	lr
 113              	.L13:
 114              		.align	2
 115              	.L12:
 116 0050 00480258 		.word	1476544512
 117              		.cfi_endproc
 118              	.LFE335:
 120              		.section	.text.HAL_PWREx_GetSupplyConfig,"ax",%progbits
 121              		.align	1
 122              		.global	HAL_PWREx_GetSupplyConfig
 123              		.syntax unified
 124              		.thumb
 125              		.thumb_func
 127              	HAL_PWREx_GetSupplyConfig:
 128              	.LFB336:
 380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
 382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief Get the power supply configuration.
 383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @retval The supply configuration.
 384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
 385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** uint32_t HAL_PWREx_GetSupplyConfig (void)
 386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 10


 129              		.loc 1 386 1 is_stmt 1 view -0
 130              		.cfi_startproc
 131              		@ args = 0, pretend = 0, frame = 0
 132              		@ frame_needed = 0, uses_anonymous_args = 0
 133              		@ link register save eliminated.
 387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   return (PWR->CR3 & PWR_SUPPLY_CONFIG_MASK);
 134              		.loc 1 387 3 view .LVU31
 135              		.loc 1 387 14 is_stmt 0 view .LVU32
 136 0000 024B     		ldr	r3, .L15
 137 0002 D868     		ldr	r0, [r3, #12]
 388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
 138              		.loc 1 388 1 view .LVU33
 139 0004 00F00700 		and	r0, r0, #7
 140 0008 7047     		bx	lr
 141              	.L16:
 142 000a 00BF     		.align	2
 143              	.L15:
 144 000c 00480258 		.word	1476544512
 145              		.cfi_endproc
 146              	.LFE336:
 148              		.section	.text.HAL_PWREx_ControlVoltageScaling,"ax",%progbits
 149              		.align	1
 150              		.global	HAL_PWREx_ControlVoltageScaling
 151              		.syntax unified
 152              		.thumb
 153              		.thumb_func
 155              	HAL_PWREx_ControlVoltageScaling:
 156              	.LVL8:
 157              	.LFB337:
 389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
 391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief Configure the main internal regulator output voltage.
 392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @param  VoltageScaling : Specifies the regulator output voltage to achieve
 393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                          a tradeoff between performance and power
 394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                          consumption.
 395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *          This parameter can be one of the following values :
 396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_REGULATOR_VOLTAGE_SCALE0 : Regulator voltage output
 397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                                                Scale 0 mode.
 398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output
 399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                                                range 1 mode.
 400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output
 401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                                                range 2 mode.
 402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_REGULATOR_VOLTAGE_SCALE3 : Regulator voltage output
 403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                                                range 3 mode.
 404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @note   For STM32H74x and STM32H75x lines, configuring Voltage Scale 0 is
 405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         only possible when Vcore is supplied from LDO (Low DropOut). The
 406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         SYSCFG Clock must be enabled through __HAL_RCC_SYSCFG_CLK_ENABLE()
 407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         macro before configuring Voltage Scale 0.
 408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         To enter low power mode , and if current regulator voltage is
 409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         Voltage Scale 0 then first switch to Voltage Scale 1 before entering
 410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         low power mode.
 411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @retval HAL Status
 412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
 413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling (uint32_t VoltageScaling)
 414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
 158              		.loc 1 414 1 is_stmt 1 view -0
 159              		.cfi_startproc
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 11


 160              		@ args = 0, pretend = 0, frame = 0
 161              		@ frame_needed = 0, uses_anonymous_args = 0
 415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   uint32_t tickstart;
 162              		.loc 1 415 3 view .LVU35
 416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Check the parameters */
 418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   assert_param (IS_PWR_REGULATOR_VOLTAGE (VoltageScaling));
 163              		.loc 1 418 3 view .LVU36
 419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Get the voltage scaling  */
 421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   if ((PWR->CSR1 & PWR_CSR1_ACTVOS) == VoltageScaling)
 164              		.loc 1 421 3 view .LVU37
 165              		.loc 1 421 11 is_stmt 0 view .LVU38
 166 0000 104B     		ldr	r3, .L28
 167 0002 5B68     		ldr	r3, [r3, #4]
 168              		.loc 1 421 18 view .LVU39
 169 0004 03F44043 		and	r3, r3, #49152
 170              		.loc 1 421 6 view .LVU40
 171 0008 8342     		cmp	r3, r0
 172 000a 18D0     		beq	.L21
 414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   uint32_t tickstart;
 173              		.loc 1 414 1 view .LVU41
 174 000c 10B5     		push	{r4, lr}
 175              		.cfi_def_cfa_offset 8
 176              		.cfi_offset 4, -8
 177              		.cfi_offset 14, -4
 422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
 423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* Old and new voltage scaling configuration match : nothing to do */
 424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     return HAL_OK;
 425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
 426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (PWR_SRDCR_VOS)
 428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Set the voltage range */
 429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   MODIFY_REG (PWR->SRDCR, PWR_SRDCR_VOS, VoltageScaling);
 178              		.loc 1 429 3 is_stmt 1 view .LVU42
 179 000e 0D4A     		ldr	r2, .L28
 180 0010 9369     		ldr	r3, [r2, #24]
 181 0012 23F44043 		bic	r3, r3, #49152
 182 0016 0343     		orrs	r3, r3, r0
 183 0018 9361     		str	r3, [r2, #24]
 430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #else
 431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined(SYSCFG_PWRCR_ODEN) /* STM32H74xxx and STM32H75xxx lines */
 432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE0)
 433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
 434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     if ((PWR->CR3 & PWR_CR3_LDOEN) == PWR_CR3_LDOEN)
 435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     {
 436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       /* Set the voltage range */
 437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       MODIFY_REG (PWR->D3CR, PWR_D3CR_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
 438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       /* Get tick */
 440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       tickstart = HAL_GetTick ();
 441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       /* Wait till voltage level flag is set */
 443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U)
 444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       {
 445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY)
 446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         {
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 12


 447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           return HAL_ERROR;
 448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         }
 449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       }
 450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       /* Enable the PWR overdrive */
 452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       SET_BIT (SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);
 453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     }
 454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     else
 455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     {
 456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       /* The voltage scale 0 is only possible when LDO regulator is enabled */
 457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       return HAL_ERROR;
 458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     }
 459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
 460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   else
 461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
 462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     if ((PWR->CSR1 & PWR_CSR1_ACTVOS) == PWR_REGULATOR_VOLTAGE_SCALE1)
 463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     {
 464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       if ((SYSCFG->PWRCR & SYSCFG_PWRCR_ODEN) != 0U)
 465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       {
 466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         /* Disable the PWR overdrive */
 467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         CLEAR_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);
 468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         /* Get tick */
 470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         tickstart = HAL_GetTick ();
 471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         /* Wait till voltage level flag is set */
 473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U)
 474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         {
 475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           if ((HAL_GetTick () - tickstart) > PWR_FLAG_SETTING_DELAY)
 476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           {
 477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****             return HAL_ERROR;
 478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           }
 479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         }
 480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       }
 481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     }
 482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* Set the voltage range */
 484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     MODIFY_REG (PWR->D3CR, PWR_D3CR_VOS, VoltageScaling);
 485:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
 486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #else  /* STM32H72xxx and STM32H73xxx lines */
 487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Set the voltage range */
 488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, VoltageScaling);
 489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (SYSCFG_PWRCR_ODEN) */
 490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (PWR_SRDCR_VOS) */
 491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Get tick */
 493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   tickstart = HAL_GetTick ();
 184              		.loc 1 493 3 view .LVU43
 185              		.loc 1 493 15 is_stmt 0 view .LVU44
 186 001a FFF7FEFF 		bl	HAL_GetTick
 187              	.LVL9:
 188              		.loc 1 493 15 view .LVU45
 189 001e 0446     		mov	r4, r0
 190              	.LVL10:
 494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Wait till voltage level flag is set */
 496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   while (__HAL_PWR_GET_FLAG (PWR_FLAG_ACTVOSRDY) == 0U)
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 13


 191              		.loc 1 496 3 is_stmt 1 view .LVU46
 192              	.L19:
 193              		.loc 1 496 50 view .LVU47
 194              		.loc 1 496 10 is_stmt 0 view .LVU48
 195 0020 084B     		ldr	r3, .L28
 196 0022 5B68     		ldr	r3, [r3, #4]
 197              		.loc 1 496 50 view .LVU49
 198 0024 13F4005F 		tst	r3, #8192
 199 0028 07D1     		bne	.L27
 497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
 498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     if ((HAL_GetTick() - tickstart) > PWR_FLAG_SETTING_DELAY)
 200              		.loc 1 498 5 is_stmt 1 view .LVU50
 201              		.loc 1 498 10 is_stmt 0 view .LVU51
 202 002a FFF7FEFF 		bl	HAL_GetTick
 203              	.LVL11:
 204              		.loc 1 498 24 discriminator 1 view .LVU52
 205 002e 001B     		subs	r0, r0, r4
 206              		.loc 1 498 8 discriminator 1 view .LVU53
 207 0030 B0F57A7F 		cmp	r0, #1000
 208 0034 F4D9     		bls	.L19
 499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     {
 500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       return HAL_ERROR;
 209              		.loc 1 500 14 view .LVU54
 210 0036 0120     		movs	r0, #1
 211 0038 00E0     		b	.L18
 212              	.L27:
 501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     }
 502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
 503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   return HAL_OK;
 213              		.loc 1 504 10 view .LVU55
 214 003a 0020     		movs	r0, #0
 215              	.L18:
 505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
 216              		.loc 1 505 1 view .LVU56
 217 003c 10BD     		pop	{r4, pc}
 218              	.LVL12:
 219              	.L21:
 220              		.cfi_def_cfa_offset 0
 221              		.cfi_restore 4
 222              		.cfi_restore 14
 424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
 223              		.loc 1 424 12 view .LVU57
 224 003e 0020     		movs	r0, #0
 225              	.LVL13:
 226              		.loc 1 505 1 view .LVU58
 227 0040 7047     		bx	lr
 228              	.L29:
 229 0042 00BF     		.align	2
 230              	.L28:
 231 0044 00480258 		.word	1476544512
 232              		.cfi_endproc
 233              	.LFE337:
 235              		.section	.text.HAL_PWREx_GetVoltageRange,"ax",%progbits
 236              		.align	1
 237              		.global	HAL_PWREx_GetVoltageRange
 238              		.syntax unified
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 14


 239              		.thumb
 240              		.thumb_func
 242              	HAL_PWREx_GetVoltageRange:
 243              	.LFB338:
 506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
 508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief Get the main internal regulator output voltage. Reflecting the last
 509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *        VOS value applied to the PMU.
 510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @retval The current applied VOS selection.
 511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
 512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** uint32_t HAL_PWREx_GetVoltageRange (void)
 513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
 244              		.loc 1 513 1 is_stmt 1 view -0
 245              		.cfi_startproc
 246              		@ args = 0, pretend = 0, frame = 0
 247              		@ frame_needed = 0, uses_anonymous_args = 0
 248              		@ link register save eliminated.
 514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Get the active voltage scaling */
 515:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   return (PWR->CSR1 & PWR_CSR1_ACTVOS);
 249              		.loc 1 515 3 view .LVU60
 250              		.loc 1 515 14 is_stmt 0 view .LVU61
 251 0000 024B     		ldr	r3, .L31
 252 0002 5868     		ldr	r0, [r3, #4]
 516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
 253              		.loc 1 516 1 view .LVU62
 254 0004 00F44040 		and	r0, r0, #49152
 255 0008 7047     		bx	lr
 256              	.L32:
 257 000a 00BF     		.align	2
 258              	.L31:
 259 000c 00480258 		.word	1476544512
 260              		.cfi_endproc
 261              	.LFE338:
 263              		.section	.text.HAL_PWREx_ControlStopModeVoltageScaling,"ax",%progbits
 264              		.align	1
 265              		.global	HAL_PWREx_ControlStopModeVoltageScaling
 266              		.syntax unified
 267              		.thumb
 268              		.thumb_func
 270              	HAL_PWREx_ControlStopModeVoltageScaling:
 271              	.LVL14:
 272              	.LFB339:
 517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
 519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief Configure the main internal regulator output voltage in STOP mode.
 520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @param  VoltageScaling : Specifies the regulator output voltage when the
 521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         system enters Stop mode to achieve a tradeoff between performance
 522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         and power consumption.
 523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *          This parameter can be one of the following values:
 524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_REGULATOR_SVOS_SCALE3 : Regulator voltage output range
 525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                                             3 mode.
 526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_REGULATOR_SVOS_SCALE4 : Regulator voltage output range
 527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                                             4 mode.
 528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_REGULATOR_SVOS_SCALE5 : Regulator voltage output range
 529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                                             5 mode.
 530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @note   The Stop mode voltage scaling for SVOS4 and SVOS5 sets the voltage
 531:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         regulator in Low-power (LP) mode to further reduce power consumption.
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 15


 532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         When preselecting SVOS3, the use of the voltage regulator low-power
 533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         mode (LP) can be selected by LPDS register bit.
 534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @note   The selected SVOS4 and SVOS5 levels add an additional startup delay
 535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         when exiting from system Stop mode.
 536:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @retval HAL Status.
 537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
 538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling (uint32_t VoltageScaling)
 539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
 273              		.loc 1 539 1 is_stmt 1 view -0
 274              		.cfi_startproc
 275              		@ args = 0, pretend = 0, frame = 0
 276              		@ frame_needed = 0, uses_anonymous_args = 0
 277              		@ link register save eliminated.
 540:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Check the parameters */
 541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   assert_param (IS_PWR_STOP_MODE_REGULATOR_VOLTAGE (VoltageScaling));
 278              		.loc 1 541 3 view .LVU64
 542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Return the stop mode voltage range */
 544:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   MODIFY_REG (PWR->CR1, PWR_CR1_SVOS, VoltageScaling);
 279              		.loc 1 544 3 view .LVU65
 280 0000 034A     		ldr	r2, .L34
 281 0002 1368     		ldr	r3, [r2]
 282 0004 23F44043 		bic	r3, r3, #49152
 283 0008 0343     		orrs	r3, r3, r0
 284 000a 1360     		str	r3, [r2]
 545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   return HAL_OK;
 285              		.loc 1 546 3 view .LVU66
 547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
 286              		.loc 1 547 1 is_stmt 0 view .LVU67
 287 000c 0020     		movs	r0, #0
 288              	.LVL15:
 289              		.loc 1 547 1 view .LVU68
 290 000e 7047     		bx	lr
 291              	.L35:
 292              		.align	2
 293              	.L34:
 294 0010 00480258 		.word	1476544512
 295              		.cfi_endproc
 296              	.LFE339:
 298              		.section	.text.HAL_PWREx_GetStopModeVoltageRange,"ax",%progbits
 299              		.align	1
 300              		.global	HAL_PWREx_GetStopModeVoltageRange
 301              		.syntax unified
 302              		.thumb
 303              		.thumb_func
 305              	HAL_PWREx_GetStopModeVoltageRange:
 306              	.LFB340:
 548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
 550:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief Get the main internal regulator output voltage in STOP mode.
 551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @retval The actual applied VOS selection.
 552:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
 553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** uint32_t HAL_PWREx_GetStopModeVoltageRange (void)
 554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
 307              		.loc 1 554 1 is_stmt 1 view -0
 308              		.cfi_startproc
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 16


 309              		@ args = 0, pretend = 0, frame = 0
 310              		@ frame_needed = 0, uses_anonymous_args = 0
 311              		@ link register save eliminated.
 555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Return the stop voltage scaling */
 556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   return (PWR->CR1 & PWR_CR1_SVOS);
 312              		.loc 1 556 3 view .LVU70
 313              		.loc 1 556 14 is_stmt 0 view .LVU71
 314 0000 024B     		ldr	r3, .L37
 315 0002 1868     		ldr	r0, [r3]
 557:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
 316              		.loc 1 557 1 view .LVU72
 317 0004 00F44040 		and	r0, r0, #49152
 318 0008 7047     		bx	lr
 319              	.L38:
 320 000a 00BF     		.align	2
 321              	.L37:
 322 000c 00480258 		.word	1476544512
 323              		.cfi_endproc
 324              	.LFE340:
 326              		.section	.text.HAL_PWREx_EnterSTOP2Mode,"ax",%progbits
 327              		.align	1
 328              		.global	HAL_PWREx_EnterSTOP2Mode
 329              		.syntax unified
 330              		.thumb
 331              		.thumb_func
 333              	HAL_PWREx_EnterSTOP2Mode:
 334              	.LVL16:
 335              	.LFB341:
 558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
 559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @}
 560:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
 561:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** @defgroup PWREx_Exported_Functions_Group2 Low Power Control Functions
 563:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief    Low power control functions
 564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *
 565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** @verbatim
 566:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****  ===============================================================================
 567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****                      ##### Low power control functions #####
 568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****  ===============================================================================
 569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     *** Domains Low Power modes configuration ***
 571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     =============================================
 572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     [..]
 573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       This section provides the extended low power mode control APIs.
 574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       The system presents 3 principles domains (D1, D2 and D3) that can be
 575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       operated in low-power modes (DSTOP or DSTANDBY mode):
 576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       (+) DSTOP mode to enters a domain to STOP mode:
 578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        (++) D1 domain and/or D2 domain enters DSTOP mode only when the CPU
 579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****             subsystem is in CSTOP mode and has allocated peripheral in the
 580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****             domain.
 581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****             In DSTOP mode the domain bus matrix clock is stopped.
 582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        (++) The system enters STOP mode using one of the following scenarios:
 583:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         (+++) D1 domain enters DSTANDBY mode (powered off) and D2, D3 domains
 584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****               enter DSTOP mode.
 585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         (+++) D2 domain enters DSTANDBY mode (powered off) and D1, D3 domains
 586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****               enter DSTOP mode.
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 17


 587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         (+++) D3 domain enters DSTANDBY mode (powered off) and D1, D2 domains
 588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****               enter DSTOP mode.
 589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         (+++) D1 and D2 domains enter DSTANDBY mode (powered off) and D3 domain
 590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****               enters DSTOP mode.
 591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         (+++) D1 and D3 domains enter DSTANDBY mode (powered off) and D2 domain
 592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****               enters DSTOP mode.
 593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         (+++) D2 and D3 domains enter DSTANDBY mode (powered off) and D1 domain
 594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****               enters DSTOP mode.
 595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         (+++) D1, D2 and D3 domains enter DSTOP mode.
 596:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        (++) When the system enters STOP mode, the clocks are stopped and the
 597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****             regulator is running in main or low power mode.
 598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        (++) D3 domain can be kept in Run mode regardless of the CPU status when
 599:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****             enter STOP mode by using HAL_PWREx_ConfigD3Domain(D3State) function.
 600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       (+) DSTANDBY mode to enters a domain to STANDBY mode:
 602:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        (++) The DSTANDBY mode is entered when the PDDS_Dn bit in PWR CPU control
 603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****             register (PWR_CPUCR) for the Dn domain selects Standby mode.
 604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        (++) The system enters STANDBY mode only when D1, D2 and D3 domains enter
 605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****             DSTANDBY mode. Consequently the VCORE supply regulator is powered
 606:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****             off.
 607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****    *** DSTOP mode ***
 609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****    ==================
 610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     [..]
 611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       In DStop mode the domain bus matrix clock is stopped.
 612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       The Flash memory can enter low-power Stop mode when it is enabled through
 613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       FLPS in PWR_CR1 register. This allows a trade-off between domain DStop
 614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       restart time and low power consumption.
 615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     [..]
 616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       In DStop mode domain peripherals using the LSI or LSE clock and
 617:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       peripherals having a kernel clock request are still able to operate.
 618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     [..]
 619:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       Before entering DSTOP mode it is recommended to call SCB_CleanDCache
 620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       function in order to clean the D-Cache and guarantee the data integrity
 621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       for the SRAM memories.
 622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       (+) Entry:
 624:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****          The DSTOP mode is entered using the HAL_PWREx_EnterSTOPMode(Regulator,
 625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****          STOPEntry, Domain) function with:
 626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****          (++) Regulator:
 627:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           (+++) PWR_MAINREGULATOR_ON     : Main regulator ON.
 628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           (+++) PWR_LOWPOWERREGULATOR_ON : Low Power regulator ON.
 629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****          (++) STOPEntry:
 630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           (+++) PWR_STOPENTRY_WFI : enter STOP mode with WFI instruction
 631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           (+++) PWR_STOPENTRY_WFE : enter STOP mode with WFE instruction
 632:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****          (++) Domain:
 633:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           (+++) PWR_D1_DOMAIN : Enters D1/CD domain to DSTOP mode.
 634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           (+++) PWR_D2_DOMAIN : Enters D2 domain to DSTOP mode.
 635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           (+++) PWR_D3_DOMAIN : Enters D3/SRD domain to DSTOP mode.
 636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       (+) Exit:
 638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
 639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****    *** DSTANDBY mode ***
 641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****    =====================
 642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     [..]
 643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       In DStandby mode:
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 18


 644:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         (+) The domain bus matrix clock is stopped.
 645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         (+) The domain is powered down and the domain RAM and register contents
 646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****             are lost.
 647:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     [..]
 648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       Before entering DSTANDBY mode it is recommended to call SCB_CleanDCache
 649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       function in order to clean the D-Cache and guarantee the data integrity
 650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       for the SRAM memories.
 651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       (+) Entry:
 653:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****          The DSTANDBY mode is entered using the HAL_PWREx_EnterSTANDBYMode
 654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****          (Domain) function with:
 655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        (++) Domain:
 656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         (+++) PWR_D1_DOMAIN : Enters D1/CD domain to DSTANDBY mode.
 657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         (+++) PWR_D2_DOMAIN : Enters D2 domain to DSTANDBY mode.
 658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         (+++) PWR_D3_DOMAIN : Enters D3/SRD domain to DSTANDBY mode.
 659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       (+) Exit:
 661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC
 662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         wakeup, tamper event, time stamp event, external reset in NRST pin,
 663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         IWDG reset.
 664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****    *** Keep D3/SRD in RUN mode ***
 666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****    ===============================
 667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     [..]
 668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       D3/SRD domain can be kept in Run mode regardless of the CPU status when
 669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       entering STOP mode by using HAL_PWREx_ConfigD3Domain(D3State) function
 670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       with :
 671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        (+) D3State:
 672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         (++) PWR_D3_DOMAIN_STOP : D3/SDR domain follows the CPU sub-system
 673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****                                   mode.
 674:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         (++) PWR_D3_DOMAIN_RUN : D3/SRD domain remains in Run mode regardless
 675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****                                  of CPU subsystem mode.
 676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     *** FLASH Power Down configuration ****
 678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     =======================================
 679:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     [..]
 680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       By setting the FLPS bit in the PWR_CR1 register using the
 681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters
 682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       power down mode when the device enters STOP mode. When the Flash memory is
 683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       in power down mode, an additional startup delay is incurred when waking up
 684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       from STOP mode.
 685:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     *** Wakeup Pins configuration ****
 687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     ===================================
 688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     [..]
 689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       Wakeup pins allow the system to exit from Standby mode. The configuration
 690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       of wakeup pins is done with the HAL_PWREx_EnableWakeUpPin(sPinParams)
 691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       function with:
 692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        (+) sPinParams: structure to enable and configure a wakeup pin:
 693:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         (++) WakeUpPin: Wakeup pin to be enabled.
 694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         (++) PinPolarity: Wakeup pin polarity (rising or falling edge).
 695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         (++) PinPull: Wakeup pin pull (no pull, pull-up or pull-down).
 696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     [..]
 697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       The wakeup pins are internally connected to the EXTI lines [55-60] to
 698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       generate an interrupt if enabled. The EXTI lines configuration is done by
 699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       the HAL_EXTI_Dx_EventInputConfig() functions defined in the stm32h7xxhal.c
 700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       file.
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 19


 701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     [..]
 702:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       When a wakeup pin event is received the HAL_PWREx_WAKEUP_PIN_IRQHandler is
 703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       called and the appropriate flag is set in the PWR_WKUPFR register. Then in
 704:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       the HAL_PWREx_WAKEUP_PIN_IRQHandler function the wakeup pin flag will be
 705:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       cleared and the appropriate user callback will be called. The user can add
 706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       his own code by customization of function pointer HAL_PWREx_WKUPx_Callback.
 707:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** @endverbatim
 709:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @{
 710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
 711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 712:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (PWR_CPUCR_RETDS_CD)
 713:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
 714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief Enter the system to STOP mode with main domain in DSTOP2.
 715:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @note   In STOP mode, the domain bus matrix clock is stalled.
 716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @note   In STOP mode, memories and registers are maintained and peripherals
 717:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         in CPU domain are no longer operational.
 718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @note   All clocks in the VCORE domain are stopped, the PLL, the HSI and the
 719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         HSE oscillators are disabled. Only Peripherals that have wakeup
 720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         capability can switch on the HSI to receive a frame, and switch off
 721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         the HSI after receiving the frame if it is not a wakeup frame. In
 722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         this case the HSI clock is propagated only to the peripheral
 723:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         requesting it.
 724:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @note   When exiting STOP mode by issuing an interrupt or a wakeup event,
 725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         the HSI RC oscillator is selected as system clock if STOPWUCK bit in
 726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         RCC_CFGR register is set.
 727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @param  Regulator : Specifies the regulator state in STOP mode.
 728:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *          This parameter can be one of the following values:
 729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_MAINREGULATOR_ON     : STOP mode with regulator ON.
 730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_LOWPOWERREGULATOR_ON : STOP mode with low power
 731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                                            regulator ON.
 732:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @param  STOPEntry : Specifies if STOP mode in entered with WFI or WFE
 733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                     intrinsic instruction.
 734:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *          This parameter can be one of the following values:
 735:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction.
 736:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction.
 737:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @retval None.
 738:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
 739:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_EnterSTOP2Mode (uint32_t Regulator, uint8_t STOPEntry)
 740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
 336              		.loc 1 740 1 is_stmt 1 view -0
 337              		.cfi_startproc
 338              		@ args = 0, pretend = 0, frame = 0
 339              		@ frame_needed = 0, uses_anonymous_args = 0
 340              		@ link register save eliminated.
 741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Check the parameters */
 742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   assert_param (IS_PWR_REGULATOR (Regulator));
 341              		.loc 1 742 3 view .LVU74
 743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   assert_param (IS_PWR_STOP_ENTRY (STOPEntry));
 342              		.loc 1 743 3 view .LVU75
 744:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 745:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Select the regulator state in Stop mode */
 746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   MODIFY_REG (PWR->CR1, PWR_CR1_LPDS, Regulator);
 343              		.loc 1 746 3 view .LVU76
 344 0000 104B     		ldr	r3, .L43
 345 0002 1A68     		ldr	r2, [r3]
 346 0004 22F00102 		bic	r2, r2, #1
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 20


 347 0008 0243     		orrs	r2, r2, r0
 348 000a 1A60     		str	r2, [r3]
 747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 748:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Go to DStop2 mode (deep retention) when CPU domain enters Deepsleep */
 749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   SET_BIT (PWR->CPUCR, PWR_CPUCR_RETDS_CD);
 349              		.loc 1 749 3 view .LVU77
 350 000c 1A69     		ldr	r2, [r3, #16]
 351 000e 42F00102 		orr	r2, r2, #1
 352 0012 1A61     		str	r2, [r3, #16]
 750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 751:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Keep DSTOP mode when SmartRun domain enters Deepsleep */
 752:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_SRD);
 353              		.loc 1 752 3 view .LVU78
 354 0014 1A69     		ldr	r2, [r3, #16]
 355 0016 22F00402 		bic	r2, r2, #4
 356 001a 1A61     		str	r2, [r3, #16]
 753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 754:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Set SLEEPDEEP bit of Cortex System Control Register */
 755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
 357              		.loc 1 755 3 view .LVU79
 358 001c 0A4A     		ldr	r2, .L43+4
 359 001e 1369     		ldr	r3, [r2, #16]
 360 0020 43F00403 		orr	r3, r3, #4
 361 0024 1361     		str	r3, [r2, #16]
 756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 757:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Ensure that all instructions are done before entering STOP mode */
 758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   __ISB ();
 362              		.loc 1 758 3 view .LVU80
 363              	.LBB26:
 364              	.LBI26:
 365              		.file 2 "Drivers/CMSIS/Include/cmsis_gcc.h"
   1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//**
   2:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @file     cmsis_gcc.h
   3:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @brief    CMSIS compiler GCC header file
   4:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @version  V5.2.0
   5:Drivers/CMSIS/Include/cmsis_gcc.h ****  * @date     08. May 2019
   6:Drivers/CMSIS/Include/cmsis_gcc.h ****  ******************************************************************************/
   7:Drivers/CMSIS/Include/cmsis_gcc.h **** /*
   8:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
   9:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
  10:Drivers/CMSIS/Include/cmsis_gcc.h ****  * SPDX-License-Identifier: Apache-2.0
  11:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
  12:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Licensed under the Apache License, Version 2.0 (the License); you may
  13:Drivers/CMSIS/Include/cmsis_gcc.h ****  * not use this file except in compliance with the License.
  14:Drivers/CMSIS/Include/cmsis_gcc.h ****  * You may obtain a copy of the License at
  15:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
  16:Drivers/CMSIS/Include/cmsis_gcc.h ****  * www.apache.org/licenses/LICENSE-2.0
  17:Drivers/CMSIS/Include/cmsis_gcc.h ****  *
  18:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Unless required by applicable law or agreed to in writing, software
  19:Drivers/CMSIS/Include/cmsis_gcc.h ****  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  20:Drivers/CMSIS/Include/cmsis_gcc.h ****  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  21:Drivers/CMSIS/Include/cmsis_gcc.h ****  * See the License for the specific language governing permissions and
  22:Drivers/CMSIS/Include/cmsis_gcc.h ****  * limitations under the License.
  23:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
  24:Drivers/CMSIS/Include/cmsis_gcc.h **** 
  25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H
  26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 21


  27:Drivers/CMSIS/Include/cmsis_gcc.h **** 
  28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */
  29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
  30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion"
  31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion"
  32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter"
  33:Drivers/CMSIS/Include/cmsis_gcc.h **** 
  34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */
  35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin
  36:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __has_builtin(x) (0)
  37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  38:Drivers/CMSIS/Include/cmsis_gcc.h **** 
  39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */
  40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __ASM
  41:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __ASM                                  __asm
  42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __INLINE
  44:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __INLINE                               inline
  45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __STATIC_INLINE
  47:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __STATIC_INLINE                        static inline
  48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __STATIC_FORCEINLINE                 
  50:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
  51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif                                           
  52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __NO_RETURN
  53:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __NO_RETURN                            __attribute__((__noreturn__))
  54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __USED
  56:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __USED                                 __attribute__((used))
  57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __WEAK
  59:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __WEAK                                 __attribute__((weak))
  60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED
  62:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED                               __attribute__((packed, aligned(1)))
  63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED_STRUCT
  65:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
  66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __PACKED_UNION
  68:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
  69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32        /* deprecated */
  71:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
  72:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  73:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  74:Drivers/CMSIS/Include/cmsis_gcc.h ****   struct __attribute__((packed)) T_UINT32 { uint32_t v; };
  75:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
  76:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
  77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_WRITE
  79:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
  80:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  81:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  82:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
  83:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 22


  84:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))-
  85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT16_READ
  87:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
  88:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  89:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  90:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
  91:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
  92:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(add
  93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_WRITE
  95:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
  96:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
  97:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
  98:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
  99:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
 100:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))-
 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __UNALIGNED_UINT32_READ
 103:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic push
 104:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wpacked"
 105:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic ignored "-Wattributes"
 106:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
 107:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
 108:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(add
 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __ALIGNED
 111:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __ALIGNED(x)                           __attribute__((aligned(x)))
 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __RESTRICT
 114:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __RESTRICT                             __restrict
 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 116:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __COMPILER_BARRIER
 117:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __COMPILER_BARRIER()                   __ASM volatile("":::"memory")
 118:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 119:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 120:Drivers/CMSIS/Include/cmsis_gcc.h **** /* #########################  Startup and Lowlevel Init  ######################## */
 121:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 122:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PROGRAM_START
 123:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 125:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Initializes data and bss sections
 126:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details This default implementations initialized all data and additional bss
 127:Drivers/CMSIS/Include/cmsis_gcc.h ****            sections relying on .copy.table and .zero.table specified properly
 128:Drivers/CMSIS/Include/cmsis_gcc.h ****            in the used linker script.
 129:Drivers/CMSIS/Include/cmsis_gcc.h ****   
 130:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
 132:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 133:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern void _start(void) __NO_RETURN;
 134:Drivers/CMSIS/Include/cmsis_gcc.h ****   
 135:Drivers/CMSIS/Include/cmsis_gcc.h ****   typedef struct {
 136:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t const* src;
 137:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t* dest;
 138:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t  wlen;
 139:Drivers/CMSIS/Include/cmsis_gcc.h ****   } __copy_table_t;
 140:Drivers/CMSIS/Include/cmsis_gcc.h ****   
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 23


 141:Drivers/CMSIS/Include/cmsis_gcc.h ****   typedef struct {
 142:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t* dest;
 143:Drivers/CMSIS/Include/cmsis_gcc.h ****     uint32_t  wlen;
 144:Drivers/CMSIS/Include/cmsis_gcc.h ****   } __zero_table_t;
 145:Drivers/CMSIS/Include/cmsis_gcc.h ****   
 146:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __copy_table_t __copy_table_start__;
 147:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __copy_table_t __copy_table_end__;
 148:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __zero_table_t __zero_table_start__;
 149:Drivers/CMSIS/Include/cmsis_gcc.h ****   extern const __zero_table_t __zero_table_end__;
 150:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 151:Drivers/CMSIS/Include/cmsis_gcc.h ****   for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable
 152:Drivers/CMSIS/Include/cmsis_gcc.h ****     for(uint32_t i=0u; i<pTable->wlen; ++i) {
 153:Drivers/CMSIS/Include/cmsis_gcc.h ****       pTable->dest[i] = pTable->src[i];
 154:Drivers/CMSIS/Include/cmsis_gcc.h ****     }
 155:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
 156:Drivers/CMSIS/Include/cmsis_gcc.h ****  
 157:Drivers/CMSIS/Include/cmsis_gcc.h ****   for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable
 158:Drivers/CMSIS/Include/cmsis_gcc.h ****     for(uint32_t i=0u; i<pTable->wlen; ++i) {
 159:Drivers/CMSIS/Include/cmsis_gcc.h ****       pTable->dest[i] = 0u;
 160:Drivers/CMSIS/Include/cmsis_gcc.h ****     }
 161:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
 162:Drivers/CMSIS/Include/cmsis_gcc.h ****  
 163:Drivers/CMSIS/Include/cmsis_gcc.h ****   _start();
 164:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 165:Drivers/CMSIS/Include/cmsis_gcc.h ****   
 166:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PROGRAM_START           __cmsis_start
 167:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 168:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 169:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INITIAL_SP
 170:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INITIAL_SP              __StackTop
 171:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 172:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STACK_LIMIT
 174:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STACK_LIMIT             __StackLimit
 175:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 176:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 177:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE
 178:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE            __Vectors
 179:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 180:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 181:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE_ATTRIBUTE
 182:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE_ATTRIBUTE  __attribute((used, section(".vectors")))
 183:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 184:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 185:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ###########################  Core Function Access  ########################### */
 186:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup  CMSIS_Core_FunctionInterface
 187:Drivers/CMSIS/Include/cmsis_gcc.h ****     \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
 188:Drivers/CMSIS/Include/cmsis_gcc.h ****   @{
 189:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 190:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 191:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 192:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Enable IRQ Interrupts
 193:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
 194:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
 195:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 196:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void)
 197:Drivers/CMSIS/Include/cmsis_gcc.h **** {
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 24


 198:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsie i" : : : "memory");
 199:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 200:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 201:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 202:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 203:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Disable IRQ Interrupts
 204:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Disables IRQ interrupts by setting the I-bit in the CPSR.
 205:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
 206:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 207:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void)
 208:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 209:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsid i" : : : "memory");
 210:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 211:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 212:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 213:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 214:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Control Register
 215:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the Control Register.
 216:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Control Register value
 217:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 218:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
 219:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 220:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 221:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 222:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, control" : "=r" (result) );
 223:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
 224:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 225:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 226:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 227:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
 228:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 229:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Control Register (non-secure)
 230:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the non-secure Control Register when in secure mode.
 231:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               non-secure Control Register value
 232:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 233:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
 234:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 235:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 236:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 237:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
 238:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
 239:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 240:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 241:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 242:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 243:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 244:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Control Register
 245:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Writes the given value to the Control Register.
 246:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    control  Control Register value to set
 247:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 248:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
 249:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 250:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
 251:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 252:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 253:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 254:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 25


 255:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 256:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Control Register (non-secure)
 257:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Writes the given value to the non-secure Control Register when in secure state.
 258:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    control  Control Register value to set
 259:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 260:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
 261:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 262:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
 263:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 264:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 265:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 266:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 267:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 268:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get IPSR Register
 269:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the IPSR Register.
 270:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               IPSR Register value
 271:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 272:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_IPSR(void)
 273:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 274:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 275:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 276:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
 277:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
 278:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 279:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 280:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 281:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 282:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get APSR Register
 283:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the APSR Register.
 284:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               APSR Register value
 285:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 286:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_APSR(void)
 287:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 288:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 289:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 290:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, apsr" : "=r" (result) );
 291:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
 292:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 293:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 294:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 295:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 296:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get xPSR Register
 297:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the xPSR Register.
 298:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               xPSR Register value
 299:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 300:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
 301:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 302:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 303:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 304:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
 305:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
 306:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 307:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 308:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 309:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 310:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer
 311:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Process Stack Pointer (PSP).
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 26


 312:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSP Register value
 313:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 314:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSP(void)
 315:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 316:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 317:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 318:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psp"  : "=r" (result) );
 319:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
 320:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 321:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 322:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 323:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
 324:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 325:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer (non-secure)
 326:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure s
 327:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSP Register value
 328:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 329:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
 330:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 331:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 332:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 333:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
 334:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
 335:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 336:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 337:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 338:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 339:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 340:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer
 341:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Process Stack Pointer (PSP).
 342:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfProcStack  Process Stack Pointer value to set
 343:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 344:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
 345:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 346:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
 347:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 348:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 349:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 350:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
 351:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 352:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer (non-secure)
 353:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure sta
 354:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfProcStack  Process Stack Pointer value to set
 355:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 356:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
 357:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 358:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
 359:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 360:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 361:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 362:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 363:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 364:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer
 365:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Main Stack Pointer (MSP).
 366:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSP Register value
 367:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 368:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSP(void)
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 27


 369:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 370:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 371:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 372:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msp" : "=r" (result) );
 373:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
 374:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 375:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 376:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 377:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
 378:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 379:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer (non-secure)
 380:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure stat
 381:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSP Register value
 382:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 383:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
 384:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 385:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 386:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 387:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
 388:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
 389:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 390:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 391:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 392:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 393:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 394:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer
 395:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Main Stack Pointer (MSP).
 396:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfMainStack  Main Stack Pointer value to set
 397:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 398:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
 399:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 400:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
 401:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 402:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 403:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 404:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
 405:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 406:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer (non-secure)
 407:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
 408:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfMainStack  Main Stack Pointer value to set
 409:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 410:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
 411:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 412:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
 413:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 414:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 415:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 416:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 417:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
 418:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 419:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Stack Pointer (non-secure)
 420:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
 421:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               SP Register value
 422:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 423:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
 424:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 425:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 28


 426:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 427:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
 428:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
 429:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 430:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 431:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 432:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 433:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Stack Pointer (non-secure)
 434:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
 435:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfStack  Stack Pointer value to set
 436:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 437:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
 438:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 439:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
 440:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 441:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 442:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 443:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 444:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 445:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Priority Mask
 446:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current state of the priority mask bit from the Priority Mask Register.
 447:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Priority Mask value
 448:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 449:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
 450:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 451:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 452:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 453:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
 454:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
 455:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 456:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 457:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 458:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
 459:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 460:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Priority Mask (non-secure)
 461:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg
 462:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Priority Mask value
 463:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 464:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
 465:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 466:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 467:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 468:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
 469:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
 470:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 471:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 472:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 473:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 474:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 475:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Priority Mask
 476:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Priority Mask Register.
 477:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    priMask  Priority Mask
 478:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 479:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
 480:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 481:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
 482:Drivers/CMSIS/Include/cmsis_gcc.h **** }
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 29


 483:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 484:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 485:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
 486:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 487:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Priority Mask (non-secure)
 488:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
 489:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    priMask  Priority Mask
 490:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 491:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
 492:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 493:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
 494:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 495:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 496:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 497:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 498:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
 499:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
 500:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
 501:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 502:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Enable FIQ
 503:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
 504:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
 505:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 506:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_fault_irq(void)
 507:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 508:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsie f" : : : "memory");
 509:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 510:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 511:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 512:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 513:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Disable FIQ
 514:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Disables FIQ interrupts by setting the F-bit in the CPSR.
 515:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
 516:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 517:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void)
 518:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 519:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsid f" : : : "memory");
 520:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 521:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 522:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 523:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 524:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Base Priority
 525:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Base Priority register.
 526:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Base Priority register value
 527:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 528:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
 529:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 530:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 531:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 532:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, basepri" : "=r" (result) );
 533:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
 534:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 535:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 536:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 537:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
 538:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 539:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Base Priority (non-secure)
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 30


 540:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Base Priority register when in secure state.
 541:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Base Priority register value
 542:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 543:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
 544:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 545:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 546:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 547:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
 548:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
 549:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 550:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 551:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 552:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 553:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 554:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority
 555:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Base Priority register.
 556:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
 557:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 558:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
 559:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 560:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
 561:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 562:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 563:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 564:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
 565:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 566:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority (non-secure)
 567:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Base Priority register when in secure state.
 568:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
 569:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 570:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
 571:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 572:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
 573:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 574:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 575:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 576:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 577:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 578:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority with condition
 579:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable
 580:Drivers/CMSIS/Include/cmsis_gcc.h ****            or the new value increases the BASEPRI priority level.
 581:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    basePri  Base Priority value to set
 582:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 583:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
 584:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 585:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
 586:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 587:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 588:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 589:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 590:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Fault Mask
 591:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Fault Mask register.
 592:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Fault Mask register value
 593:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 594:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
 595:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 596:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 31


 597:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 598:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
 599:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
 600:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 601:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 602:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 603:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
 604:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 605:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Fault Mask (non-secure)
 606:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Fault Mask register when in secure state.
 607:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Fault Mask register value
 608:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 609:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
 610:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 611:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 612:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 613:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
 614:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
 615:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 616:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 617:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 618:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 619:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 620:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Fault Mask
 621:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Fault Mask register.
 622:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    faultMask  Fault Mask value to set
 623:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 624:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
 625:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 626:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
 627:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 628:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 629:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 630:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
 631:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 632:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Fault Mask (non-secure)
 633:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Fault Mask register when in secure state.
 634:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    faultMask  Fault Mask value to set
 635:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 636:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
 637:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 638:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
 639:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 640:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 641:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 642:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
 643:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
 644:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
 645:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 646:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 647:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
 648:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
 649:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 650:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 651:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer Limit
 652:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
 653:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always in non-secure
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 32


 654:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
 655:Drivers/CMSIS/Include/cmsis_gcc.h ****   
 656:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
 657:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSPLIM Register value
 658:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 659:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
 660:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 661:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
 662:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
 663:Drivers/CMSIS/Include/cmsis_gcc.h ****     // without main extensions, the non-secure PSPLIM is RAZ/WI
 664:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
 665:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 666:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 667:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
 668:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
 669:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 670:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 671:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 672:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
 673:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 674:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Process Stack Pointer Limit (non-secure)
 675:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
 676:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always.
 677:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 678:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in
 679:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               PSPLIM Register value
 680:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 681:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
 682:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 683:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
 684:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
 685:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
 686:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 687:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 688:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
 689:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
 690:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 691:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 692:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 693:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 694:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 695:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 696:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer Limit
 697:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
 698:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored in non-secure
 699:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
 700:Drivers/CMSIS/Include/cmsis_gcc.h ****   
 701:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
 702:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
 703:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 704:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
 705:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 706:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
 707:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
 708:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
 709:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)ProcStackPtrLimit;
 710:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 33


 711:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
 712:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 713:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 714:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 715:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 716:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
 717:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 718:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Process Stack Pointer (non-secure)
 719:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
 720:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored.
 721:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 722:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in s
 723:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
 724:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 725:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
 726:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 727:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
 728:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure PSPLIM is RAZ/WI
 729:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)ProcStackPtrLimit;
 730:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 731:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
 732:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 733:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 734:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 735:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 736:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 737:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 738:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer Limit
 739:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
 740:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always in non-secure
 741:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
 742:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 743:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
 744:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSPLIM Register value
 745:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 746:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
 747:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 748:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
 749:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
 750:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
 751:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
 752:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 753:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 754:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msplim" : "=r" (result) );
 755:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
 756:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 757:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 758:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 759:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 760:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
 761:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 762:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Main Stack Pointer Limit (non-secure)
 763:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
 764:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence zero is returned always.
 765:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 766:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in sec
 767:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSPLIM Register value
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 34


 768:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 769:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
 770:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 771:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
 772:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
 773:Drivers/CMSIS/Include/cmsis_gcc.h ****   return 0U;
 774:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 775:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 776:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
 777:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
 778:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 779:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 780:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 781:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 782:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 783:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 784:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer Limit
 785:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
 786:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored in non-secure
 787:Drivers/CMSIS/Include/cmsis_gcc.h ****   mode.
 788:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 789:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
 790:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
 791:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
 793:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
 795:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
 796:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
 797:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)MainStackPtrLimit;
 798:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 799:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
 800:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 801:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 802:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 803:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 804:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
 805:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 806:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer Limit (non-secure)
 807:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
 808:Drivers/CMSIS/Include/cmsis_gcc.h ****   Stack Pointer Limit register hence the write is silently ignored.
 809:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 810:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secu
 811:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
 812:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 813:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
 814:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 815:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
 816:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI
 817:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)MainStackPtrLimit;
 818:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 819:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
 820:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 821:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 822:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 823:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 824:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 35


 825:Drivers/CMSIS/Include/cmsis_gcc.h ****            (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
 826:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 827:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 828:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 829:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get FPSCR
 830:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Floating Point Status/Control register.
 831:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Floating Point Status/Control register value
 832:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 833:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
 834:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 835:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
 836:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
 837:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_get_fpscr) 
 838:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed
 839:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
 840:Drivers/CMSIS/Include/cmsis_gcc.h ****   /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
 841:Drivers/CMSIS/Include/cmsis_gcc.h ****   return __builtin_arm_get_fpscr();
 842:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 843:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 844:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 845:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
 846:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
 847:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 848:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 849:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(0U);
 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 851:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 852:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 853:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 854:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 855:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set FPSCR
 856:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Floating Point Status/Control register.
 857:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    fpscr  Floating Point Status/Control value to set
 858:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 859:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
 860:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 861:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
 862:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
 863:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr)
 864:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed
 865:Drivers/CMSIS/Include/cmsis_gcc.h **** // || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
 866:Drivers/CMSIS/Include/cmsis_gcc.h ****   /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
 867:Drivers/CMSIS/Include/cmsis_gcc.h ****   __builtin_arm_set_fpscr(fpscr);
 868:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 869:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
 870:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 871:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 872:Drivers/CMSIS/Include/cmsis_gcc.h ****   (void)fpscr;
 873:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 874:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 875:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 876:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 877:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@} end of CMSIS_Core_RegAccFunctions */
 878:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 879:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 880:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ##########################  Core Instruction Access  ######################### */
 881:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 36


 882:Drivers/CMSIS/Include/cmsis_gcc.h ****   Access to dedicated instructions
 883:Drivers/CMSIS/Include/cmsis_gcc.h ****   @{
 884:Drivers/CMSIS/Include/cmsis_gcc.h **** */
 885:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 886:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2.
 887:Drivers/CMSIS/Include/cmsis_gcc.h ****  * For thumb1, use low register (r0-r7), specified by constraint "l"
 888:Drivers/CMSIS/Include/cmsis_gcc.h ****  * Otherwise, use general registers, specified by constraint "r" */
 889:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__)
 890:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
 891:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r)
 892:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r)
 893:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 894:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
 895:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r)
 896:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r)
 897:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 898:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 899:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 900:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   No Operation
 901:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details No Operation does nothing. This instruction can be used for code alignment purposes.
 902:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 903:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP()                             __ASM volatile ("nop")
 904:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 905:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 906:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Wait For Interrupt
 907:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o
 908:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 909:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI()                             __ASM volatile ("wfi")
 910:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 911:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 912:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 913:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Wait For Event
 914:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Wait For Event is a hint instruction that permits the processor to enter
 915:Drivers/CMSIS/Include/cmsis_gcc.h ****            a low-power state until one of a number of events occurs.
 916:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 917:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE()                             __ASM volatile ("wfe")
 918:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 919:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 920:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 921:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Send Event
 922:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
 923:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 924:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV()                             __ASM volatile ("sev")
 925:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 926:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 927:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 928:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Instruction Synchronization Barrier
 929:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Instruction Synchronization Barrier flushes the pipeline in the processor,
 930:Drivers/CMSIS/Include/cmsis_gcc.h ****            so that all instructions following the ISB are fetched from cache or memory,
 931:Drivers/CMSIS/Include/cmsis_gcc.h ****            after the instruction has been completed.
 932:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 933:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void)
 366              		.loc 2 933 27 view .LVU81
 367              	.LBB27:
 934:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 935:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("isb 0xF":::"memory");
 368              		.loc 2 935 3 view .LVU82
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 37


 369              		.syntax unified
 370              	@ 935 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
 371 0026 BFF36F8F 		isb 0xF
 372              	@ 0 "" 2
 373              		.thumb
 374              		.syntax unified
 375              	.LBE27:
 376              	.LBE26:
 759:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   __DSB ();
 377              		.loc 1 759 3 view .LVU83
 378              	.LBB28:
 379              	.LBI28:
 936:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 937:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 938:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 939:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 940:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Data Synchronization Barrier
 941:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Acts as a special kind of Data Memory Barrier.
 942:Drivers/CMSIS/Include/cmsis_gcc.h ****            It completes when all explicit memory accesses before this instruction complete.
 943:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 944:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void)
 380              		.loc 2 944 27 view .LVU84
 381              	.LBB29:
 945:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 946:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("dsb 0xF":::"memory");
 382              		.loc 2 946 3 view .LVU85
 383              		.syntax unified
 384              	@ 946 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
 385 002a BFF34F8F 		dsb 0xF
 386              	@ 0 "" 2
 387              		.thumb
 388              		.syntax unified
 389              	.LBE29:
 390              	.LBE28:
 760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Select Stop mode entry */
 762:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   if (STOPEntry == PWR_STOPENTRY_WFI)
 391              		.loc 1 762 3 view .LVU86
 392              		.loc 1 762 6 is_stmt 0 view .LVU87
 393 002e 0129     		cmp	r1, #1
 394 0030 06D0     		beq	.L42
 763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
 764:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* Request Wait For Interrupt */
 765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     __WFI ();
 766:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
 767:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   else
 768:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
 769:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* Request Wait For Event */
 770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     __WFE ();
 395              		.loc 1 770 5 is_stmt 1 view .LVU88
 396              		.syntax unified
 397              	@ 770 "Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c" 1
 398 0032 20BF     		wfe
 399              	@ 0 "" 2
 400              		.thumb
 401              		.syntax unified
 402              	.L41:
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 38


 771:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
 772:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 773:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */
 774:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
 403              		.loc 1 774 3 view .LVU89
 404 0034 044A     		ldr	r2, .L43+4
 405 0036 1369     		ldr	r3, [r2, #16]
 406 0038 23F00403 		bic	r3, r3, #4
 407 003c 1361     		str	r3, [r2, #16]
 775:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
 408              		.loc 1 775 1 is_stmt 0 view .LVU90
 409 003e 7047     		bx	lr
 410              	.L42:
 765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
 411              		.loc 1 765 5 is_stmt 1 view .LVU91
 412              		.syntax unified
 413              	@ 765 "Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c" 1
 414 0040 30BF     		wfi
 415              	@ 0 "" 2
 416              		.thumb
 417              		.syntax unified
 418 0042 F7E7     		b	.L41
 419              	.L44:
 420              		.align	2
 421              	.L43:
 422 0044 00480258 		.word	1476544512
 423 0048 00ED00E0 		.word	-536810240
 424              		.cfi_endproc
 425              	.LFE341:
 427              		.section	.text.HAL_PWREx_EnterSTOPMode,"ax",%progbits
 428              		.align	1
 429              		.global	HAL_PWREx_EnterSTOPMode
 430              		.syntax unified
 431              		.thumb
 432              		.thumb_func
 434              	HAL_PWREx_EnterSTOPMode:
 435              	.LVL17:
 436              	.LFB342:
 776:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (PWR_CPUCR_RETDS_CD) */
 777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 778:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
 779:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief Enter a Domain to DSTOP mode.
 780:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @note   This API gives flexibility to manage independently each domain STOP
 781:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         mode. For dual core lines, this API should be executed with the
 782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         corresponding Cortex-Mx to enter domain to DSTOP mode. When it is
 783:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         executed by all available Cortex-Mx, the system enter to STOP mode.
 784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         For single core lines, calling this API with domain parameter set to
 785:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         PWR_D1_DOMAIN (D1/CD), the whole system will enter in STOP mode
 786:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         independently of PWR_CPUCR_PDDS_Dx bits values if RUN_D3 bit in the
 787:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         CPUCR_RUN_D3 is cleared.
 788:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @note   In DStop mode the domain bus matrix clock is stopped.
 789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @note   The system D3/SRD domain enter Stop mode only when the CPU subsystem
 790:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         is in CStop mode, the EXTI wakeup sources are inactive and at least
 791:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         one PDDS_Dn bit in PWR CPU control register (PWR_CPUCR) for
 792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         any domain request Stop.
 793:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @note   Before entering DSTOP mode it is recommended to call SCB_CleanDCache
 794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         function in order to clean the D-Cache and guarantee the data
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 39


 795:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         integrity for the SRAM memories.
 796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @note   In System Stop mode, the domain peripherals that use the LSI or LSE
 797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         clock, and the peripherals that have a kernel clock request to
 798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         select HSI or CSI as source, are still able to operate.
 799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @param  Regulator : Specifies the regulator state in STOP mode.
 800:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *          This parameter can be one of the following values:
 801:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_MAINREGULATOR_ON     : STOP mode with regulator ON.
 802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_LOWPOWERREGULATOR_ON : STOP mode with low power
 803:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                                            regulator ON.
 804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @param  STOPEntry : Specifies if STOP mode in entered with WFI or WFE
 805:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                     intrinsic instruction.
 806:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *          This parameter can be one of the following values:
 807:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction.
 808:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction.
 809:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @param  Domain : Specifies the Domain to enter in DSTOP mode.
 810:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *          This parameter can be one of the following values:
 811:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_D1_DOMAIN : Enter D1/CD Domain to DSTOP mode.
 812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_D2_DOMAIN : Enter D2 Domain to DSTOP mode.
 813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_D3_DOMAIN : Enter D3/SRD Domain to DSTOP mode.
 814:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @retval None.
 815:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
 816:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain)
 817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
 437              		.loc 1 817 1 view -0
 438              		.cfi_startproc
 439              		@ args = 0, pretend = 0, frame = 0
 440              		@ frame_needed = 0, uses_anonymous_args = 0
 441              		@ link register save eliminated.
 442              		.loc 1 817 1 is_stmt 0 view .LVU93
 443 0000 10B4     		push	{r4}
 444              		.cfi_def_cfa_offset 4
 445              		.cfi_offset 4, -4
 818:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Check the parameters */
 819:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   assert_param (IS_PWR_REGULATOR (Regulator));
 446              		.loc 1 819 3 is_stmt 1 view .LVU94
 820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   assert_param (IS_PWR_STOP_ENTRY (STOPEntry));
 447              		.loc 1 820 3 view .LVU95
 821:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   assert_param (IS_PWR_DOMAIN (Domain));
 448              		.loc 1 821 3 view .LVU96
 822:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 823:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Select the regulator state in Stop mode */
 824:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   MODIFY_REG (PWR->CR1, PWR_CR1_LPDS, Regulator);
 449              		.loc 1 824 3 view .LVU97
 450 0002 134C     		ldr	r4, .L52
 451 0004 2368     		ldr	r3, [r4]
 452 0006 23F00103 		bic	r3, r3, #1
 453 000a 0343     		orrs	r3, r3, r0
 454 000c 2360     		str	r3, [r4]
 825:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 826:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Select the domain Power Down DeepSleep */
 827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   if (Domain == PWR_D1_DOMAIN)
 455              		.loc 1 827 3 view .LVU98
 456              		.loc 1 827 6 is_stmt 0 view .LVU99
 457 000e CAB9     		cbnz	r2, .L46
 828:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
 829:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (DUAL_CORE)
 830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* Check current core */
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 40


 831:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     if (HAL_GetCurrentCPUID () != CM7_CPUID)
 832:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     {
 833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       /*
 834:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****          When the domain selected and the cortex-mx don't match, entering stop
 835:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****          mode will not be performed
 836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       */
 837:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       return;
 838:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     }
 839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (DUAL_CORE) */
 840:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 841:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* Keep DSTOP mode when D1/CD domain enters Deepsleep */
 842:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D1);
 458              		.loc 1 842 5 is_stmt 1 view .LVU100
 459 0010 2369     		ldr	r3, [r4, #16]
 460 0012 23F00103 		bic	r3, r3, #1
 461 0016 2361     		str	r3, [r4, #16]
 843:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 844:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* Set SLEEPDEEP bit of Cortex System Control Register */
 845:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
 462              		.loc 1 845 5 view .LVU101
 463 0018 0E4A     		ldr	r2, .L52+4
 464              	.LVL18:
 465              		.loc 1 845 5 is_stmt 0 view .LVU102
 466 001a 1369     		ldr	r3, [r2, #16]
 467 001c 43F00403 		orr	r3, r3, #4
 468 0020 1361     		str	r3, [r2, #16]
 846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 847:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* Ensure that all instructions are done before entering STOP mode */
 848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     __DSB ();
 469              		.loc 1 848 5 is_stmt 1 view .LVU103
 470              	.LBB30:
 471              	.LBI30:
 944:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 472              		.loc 2 944 27 view .LVU104
 473              	.LBB31:
 474              		.loc 2 946 3 view .LVU105
 475              		.syntax unified
 476              	@ 946 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
 477 0022 BFF34F8F 		dsb 0xF
 478              	@ 0 "" 2
 479              		.thumb
 480              		.syntax unified
 481              	.LBE31:
 482              	.LBE30:
 849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     __ISB ();
 483              		.loc 1 849 5 view .LVU106
 484              	.LBB32:
 485              	.LBI32:
 933:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 486              		.loc 2 933 27 view .LVU107
 487              	.LBB33:
 935:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 488              		.loc 2 935 3 view .LVU108
 489              		.syntax unified
 490              	@ 935 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
 491 0026 BFF36F8F 		isb 0xF
 492              	@ 0 "" 2
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 41


 493              		.thumb
 494              		.syntax unified
 495              	.LBE33:
 496              	.LBE32:
 850:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* Select Stop mode entry */
 852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     if (STOPEntry == PWR_STOPENTRY_WFI)
 497              		.loc 1 852 5 view .LVU109
 498              		.loc 1 852 8 is_stmt 0 view .LVU110
 499 002a 0129     		cmp	r1, #1
 500 002c 08D0     		beq	.L51
 853:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     {
 854:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       /* Request Wait For Interrupt */
 855:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       __WFI ();
 856:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     }
 857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     else
 858:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     {
 859:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       /* Request Wait For Event */
 860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       __WFE ();
 501              		.loc 1 860 7 is_stmt 1 view .LVU111
 502              		.syntax unified
 503              	@ 860 "Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c" 1
 504 002e 20BF     		wfe
 505              	@ 0 "" 2
 506              		.thumb
 507              		.syntax unified
 508              	.L48:
 861:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     }
 862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */
 864:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
 509              		.loc 1 864 5 view .LVU112
 510 0030 084A     		ldr	r2, .L52+4
 511 0032 1369     		ldr	r3, [r2, #16]
 512 0034 23F00403 		bic	r3, r3, #4
 513 0038 1361     		str	r3, [r2, #16]
 514              	.L45:
 865:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
 866:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (PWR_CPUCR_PDDS_D2)
 867:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   else if (Domain == PWR_D2_DOMAIN)
 868:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
 869:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (DUAL_CORE)
 870:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* Check current core */
 871:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     if (HAL_GetCurrentCPUID () != CM4_CPUID)
 872:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     {
 873:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       /*
 874:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****          When the domain selected and the cortex-mx don't match, entering stop
 875:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****          mode will not be performed
 876:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       */
 877:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       return;
 878:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     }
 879:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 880:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* Keep DSTOP mode when D2 domain enters Deepsleep */
 881:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     CLEAR_BIT (PWR->CPU2CR, PWR_CPU2CR_PDDS_D2);
 882:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 883:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* Set SLEEPDEEP bit of Cortex System Control Register */
 884:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 42


 885:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* Ensure that all instructions are done before entering STOP mode */
 887:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     __DSB ();
 888:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     __ISB ();
 889:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 890:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* Select Stop mode entry */
 891:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     if (STOPEntry == PWR_STOPENTRY_WFI)
 892:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     {
 893:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       /* Request Wait For Interrupt */
 894:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       __WFI ();
 895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     }
 896:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     else
 897:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     {
 898:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       /* Request Wait For Event */
 899:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       __WFE ();
 900:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     }
 901:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* Clear SLEEPDEEP bit of Cortex-Mx in the System Control Register */
 903:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
 904:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #else
 905:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* Keep DSTOP mode when D2 domain enters Deepsleep */
 906:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D2);
 907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif  /* defined (DUAL_CORE) */
 908:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
 909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (PWR_CPUCR_PDDS_D2) */
 910:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   else
 911:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
 912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (DUAL_CORE)
 913:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* Check current core */
 914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     if (HAL_GetCurrentCPUID () == CM7_CPUID)
 915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     {
 916:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       /* Keep DSTOP mode when D3 domain enters Deepsleep */
 917:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D3);
 918:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     }
 919:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     else
 920:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     {
 921:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       /* Keep DSTOP mode when D3 domain enters Deepsleep */
 922:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       CLEAR_BIT (PWR->CPU2CR, PWR_CPU2CR_PDDS_D3);
 923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     }
 924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #else
 925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* Keep DSTOP mode when D3/SRD domain enters Deepsleep */
 926:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D3);
 927:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif  /* defined (DUAL_CORE) */
 928:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
 929:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
 515              		.loc 1 929 1 is_stmt 0 view .LVU113
 516 003a 5DF8044B 		ldr	r4, [sp], #4
 517              		.cfi_remember_state
 518              		.cfi_restore 4
 519              		.cfi_def_cfa_offset 0
 520 003e 7047     		bx	lr
 521              	.L51:
 522              		.cfi_restore_state
 855:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     }
 523              		.loc 1 855 7 is_stmt 1 view .LVU114
 524              		.syntax unified
 525              	@ 855 "Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c" 1
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 43


 526 0040 30BF     		wfi
 527              	@ 0 "" 2
 528              		.thumb
 529              		.syntax unified
 530 0042 F5E7     		b	.L48
 531              	.LVL19:
 532              	.L46:
 926:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif  /* defined (DUAL_CORE) */
 533              		.loc 1 926 5 view .LVU115
 534 0044 024A     		ldr	r2, .L52
 535              	.LVL20:
 926:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif  /* defined (DUAL_CORE) */
 536              		.loc 1 926 5 is_stmt 0 view .LVU116
 537 0046 1369     		ldr	r3, [r2, #16]
 538 0048 23F00403 		bic	r3, r3, #4
 539 004c 1361     		str	r3, [r2, #16]
 540              		.loc 1 929 1 view .LVU117
 541 004e F4E7     		b	.L45
 542              	.L53:
 543              		.align	2
 544              	.L52:
 545 0050 00480258 		.word	1476544512
 546 0054 00ED00E0 		.word	-536810240
 547              		.cfi_endproc
 548              	.LFE342:
 550              		.section	.text.HAL_PWREx_ClearPendingEvent,"ax",%progbits
 551              		.align	1
 552              		.global	HAL_PWREx_ClearPendingEvent
 553              		.syntax unified
 554              		.thumb
 555              		.thumb_func
 557              	HAL_PWREx_ClearPendingEvent:
 558              	.LFB343:
 930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 931:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
 932:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief Clear pending event.
 933:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @note   This API clears the pending event in order to enter a given CPU
 934:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         to CSLEEP or CSTOP. It should be called just before APIs performing
 935:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         enter low power mode using Wait For Event request.
 936:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @note   Cortex-M7 must be in CRUN mode when calling this API by Cortex-M4.
 937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @retval None.
 938:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
 939:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_ClearPendingEvent (void)
 940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
 559              		.loc 1 940 1 is_stmt 1 view -0
 560              		.cfi_startproc
 561              		@ args = 0, pretend = 0, frame = 0
 562              		@ frame_needed = 0, uses_anonymous_args = 0
 563              		@ link register save eliminated.
 941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (DUAL_CORE)
 942:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Check the current Core */
 943:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   if (HAL_GetCurrentCPUID () == CM7_CPUID)
 944:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
 945:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     __WFE ();
 946:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
 947:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   else
 948:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 44


 949:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     __SEV ();
 950:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     __WFE ();
 951:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
 952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #else
 953:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   __WFE ();
 564              		.loc 1 953 3 view .LVU119
 565              		.syntax unified
 566              	@ 953 "Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c" 1
 567 0000 20BF     		wfe
 568              	@ 0 "" 2
 954:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (DUAL_CORE) */
 955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
 569              		.loc 1 955 1 is_stmt 0 view .LVU120
 570              		.thumb
 571              		.syntax unified
 572 0002 7047     		bx	lr
 573              		.cfi_endproc
 574              	.LFE343:
 576              		.section	.text.HAL_PWREx_EnterSTANDBYMode,"ax",%progbits
 577              		.align	1
 578              		.global	HAL_PWREx_EnterSTANDBYMode
 579              		.syntax unified
 580              		.thumb
 581              		.thumb_func
 583              	HAL_PWREx_EnterSTANDBYMode:
 584              	.LVL21:
 585              	.LFB344:
 956:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 957:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
 958:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief Enter a Domain to DSTANDBY mode.
 959:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @note   This API gives flexibility to manage independently each domain
 960:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         STANDBY mode. For dual core lines, this API should be executed with
 961:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         the corresponding Cortex-Mx to enter domain to DSTANDBY mode. When
 962:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         it is executed by all available Cortex-Mx, the system enter STANDBY
 963:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         mode.
 964:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         For single core lines, calling this API with D1/SRD the selected
 965:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         domain will enter the whole system in STOP if PWR_CPUCR_PDDS_D3 = 0
 966:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         and enter the whole system in STANDBY if PWR_CPUCR_PDDS_D3 = 1.
 967:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @note   The DStandby mode is entered when all PDDS_Dn bits in PWR_CPUCR for
 968:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         the Dn domain select Standby mode. When the system enters Standby
 969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         mode, the voltage regulator is disabled.
 970:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @note   When D2 or D3 domain is in DStandby mode and the CPU sets the
 971:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         domain PDDS_Dn bit to select Stop mode, the domain remains in
 972:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         DStandby mode. The domain will only exit DStandby when the CPU
 973:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         allocates a peripheral in the domain.
 974:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @note   The system D3/SRD domain enters Standby mode only when the D1 and D2
 975:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         domain are in DStandby.
 976:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @note   Before entering DSTANDBY mode it is recommended to call
 977:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         SCB_CleanDCache function in order to clean the D-Cache and guarantee
 978:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         the data integrity for the SRAM memories.
 979:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @param  Domain : Specifies the Domain to enter to STANDBY mode.
 980:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *          This parameter can be one of the following values:
 981:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_D1_DOMAIN: Enter D1/CD Domain to DSTANDBY mode.
 982:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_D2_DOMAIN: Enter D2 Domain to DSTANDBY mode.
 983:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_D3_DOMAIN: Enter D3/SRD Domain to DSTANDBY mode.
 984:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @retval None
 985:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 45


 986:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_EnterSTANDBYMode (uint32_t Domain)
 987:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
 586              		.loc 1 987 1 is_stmt 1 view -0
 587              		.cfi_startproc
 588              		@ args = 0, pretend = 0, frame = 0
 589              		@ frame_needed = 0, uses_anonymous_args = 0
 590              		@ link register save eliminated.
 988:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Check the parameters */
 989:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   assert_param (IS_PWR_DOMAIN (Domain));
 591              		.loc 1 989 3 view .LVU122
 990:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 991:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Select the domain Power Down DeepSleep */
 992:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   if (Domain == PWR_D1_DOMAIN)
 592              		.loc 1 992 3 view .LVU123
 593              		.loc 1 992 6 is_stmt 0 view .LVU124
 594 0000 58B9     		cbnz	r0, .L56
 993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
 994:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (DUAL_CORE)
 995:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* Check current core */
 996:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     if (HAL_GetCurrentCPUID () != CM7_CPUID)
 997:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     {
 998:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       /*
 999:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****          When the domain selected and the cortex-mx don't match, entering
1000:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****          standby mode will not be performed
1001:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       */
1002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       return;
1003:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     }
1004:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (DUAL_CORE) */
1005:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1006:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* Allow DSTANDBY mode when D1/CD domain enters Deepsleep */
1007:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     SET_BIT (PWR-> CPUCR, PWR_CPUCR_PDDS_D1);
 595              		.loc 1 1007 5 is_stmt 1 view .LVU125
 596 0002 094A     		ldr	r2, .L58
 597 0004 1369     		ldr	r3, [r2, #16]
 598 0006 43F00103 		orr	r3, r3, #1
 599 000a 1361     		str	r3, [r2, #16]
1008:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1009:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (DUAL_CORE)
1010:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* Allow DSTANDBY mode when D1/CD domain enters Deepsleep */
1011:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     SET_BIT (PWR-> CPU2CR, PWR_CPU2CR_PDDS_D1);
1012:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /*DUAL_CORE*/
1013:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1014:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* Set SLEEPDEEP bit of Cortex System Control Register */
1015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
 600              		.loc 1 1015 5 view .LVU126
 601 000c 074A     		ldr	r2, .L58+4
 602 000e 1369     		ldr	r3, [r2, #16]
 603 0010 43F00403 		orr	r3, r3, #4
 604 0014 1361     		str	r3, [r2, #16]
1016:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1017:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* This option is used to ensure that store operations are completed */
1018:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (__CC_ARM)
1019:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     __force_stores ();
1020:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (__CC_ARM) */
1021:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1022:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* Request Wait For Interrupt */
1023:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     __WFI ();
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 46


 605              		.loc 1 1023 5 view .LVU127
 606              		.syntax unified
 607              	@ 1023 "Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c" 1
 608 0016 30BF     		wfi
 609              	@ 0 "" 2
 610              		.thumb
 611              		.syntax unified
 612 0018 7047     		bx	lr
 613              	.L56:
1024:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
1025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (PWR_CPUCR_PDDS_D2)
1026:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   else if (Domain == PWR_D2_DOMAIN)
1027:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
1028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* Allow DSTANDBY mode when D2 domain enters Deepsleep */
1029:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     SET_BIT (PWR-> CPUCR, PWR_CPUCR_PDDS_D2);
1030:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1031:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (DUAL_CORE)
1032:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* Check current core */
1033:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     if (HAL_GetCurrentCPUID () != CM4_CPUID)
1034:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     {
1035:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       /*
1036:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****          When the domain selected and the cortex-mx don't match, entering
1037:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****          standby mode will not be performed
1038:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       */
1039:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       return;
1040:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     }
1041:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1042:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* Allow DSTANDBY mode when D2 domain enters Deepsleep */
1043:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     SET_BIT (PWR-> CPU2CR, PWR_CPU2CR_PDDS_D2);
1044:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* Set SLEEPDEEP bit of Cortex System Control Register */
1046:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     SET_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
1047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1048:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* This option is used to ensure that store operations are completed */
1049:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (__CC_ARM)
1050:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     __force_stores ();
1051:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (__CC_ARM) */
1052:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* Request Wait For Interrupt */
1054:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     __WFI ();
1055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (DUAL_CORE) */
1056:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
1057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (PWR_CPUCR_PDDS_D2) */
1058:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   else
1059:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
1060:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* Allow DSTANDBY mode when D3/SRD domain enters Deepsleep */
1061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     SET_BIT (PWR->CPUCR, PWR_CPUCR_PDDS_D3);
 614              		.loc 1 1061 5 view .LVU128
 615 001a 034A     		ldr	r2, .L58
 616 001c 1369     		ldr	r3, [r2, #16]
 617 001e 43F00403 		orr	r3, r3, #4
 618 0022 1361     		str	r3, [r2, #16]
1062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1063:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (DUAL_CORE)
1064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* Allow DSTANDBY mode when D3/SRD domain enters Deepsleep */
1065:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     SET_BIT (PWR->CPU2CR, PWR_CPU2CR_PDDS_D3);
1066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (DUAL_CORE) */
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 47


1067:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
1068:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
 619              		.loc 1 1068 1 is_stmt 0 view .LVU129
 620 0024 7047     		bx	lr
 621              	.L59:
 622 0026 00BF     		.align	2
 623              	.L58:
 624 0028 00480258 		.word	1476544512
 625 002c 00ED00E0 		.word	-536810240
 626              		.cfi_endproc
 627              	.LFE344:
 629              		.section	.text.HAL_PWREx_ConfigD3Domain,"ax",%progbits
 630              		.align	1
 631              		.global	HAL_PWREx_ConfigD3Domain
 632              		.syntax unified
 633              		.thumb
 634              		.thumb_func
 636              	HAL_PWREx_ConfigD3Domain:
 637              	.LVL22:
 638              	.LFB345:
1069:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
1071:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief Configure the D3/SRD Domain state when the System in low power mode.
1072:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @param  D3State : Specifies the D3/SRD state.
1073:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *          This parameter can be one of the following values :
1074:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_D3_DOMAIN_STOP : D3/SRD domain will follow the most deep
1075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                                      CPU sub-system low power mode.
1076:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_D3_DOMAIN_RUN : D3/SRD domain will stay in RUN mode
1077:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                                     regardless of the CPU sub-system low
1078:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                                     power mode.
1079:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @retval None
1080:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
1081:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_ConfigD3Domain (uint32_t D3State)
1082:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
 639              		.loc 1 1082 1 is_stmt 1 view -0
 640              		.cfi_startproc
 641              		@ args = 0, pretend = 0, frame = 0
 642              		@ frame_needed = 0, uses_anonymous_args = 0
 643              		@ link register save eliminated.
1083:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Check the parameter */
1084:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   assert_param (IS_D3_STATE (D3State));
 644              		.loc 1 1084 3 view .LVU131
1085:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1086:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Keep D3/SRD in run mode */
1087:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   MODIFY_REG (PWR->CPUCR, PWR_CPUCR_RUN_D3, D3State);
 645              		.loc 1 1087 3 view .LVU132
 646 0000 034A     		ldr	r2, .L61
 647 0002 1369     		ldr	r3, [r2, #16]
 648 0004 23F40063 		bic	r3, r3, #2048
 649 0008 0343     		orrs	r3, r3, r0
 650 000a 1361     		str	r3, [r2, #16]
1088:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
 651              		.loc 1 1088 1 is_stmt 0 view .LVU133
 652 000c 7047     		bx	lr
 653              	.L62:
 654 000e 00BF     		.align	2
 655              	.L61:
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 48


 656 0010 00480258 		.word	1476544512
 657              		.cfi_endproc
 658              	.LFE345:
 660              		.section	.text.HAL_PWREx_EnableFlashPowerDown,"ax",%progbits
 661              		.align	1
 662              		.global	HAL_PWREx_EnableFlashPowerDown
 663              		.syntax unified
 664              		.thumb
 665              		.thumb_func
 667              	HAL_PWREx_EnableFlashPowerDown:
 668              	.LFB346:
1089:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1090:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (DUAL_CORE)
1091:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
1092:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief Clear HOLD2F, HOLD1F, STOPF, SBF, SBF_D1, and SBF_D2 flags for a
1093:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *        given domain.
1094:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @param  DomainFlags : Specifies the Domain flags to be cleared.
1095:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *          This parameter can be one of the following values:
1096:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_D1_DOMAIN_FLAGS : Clear D1 Domain flags.
1097:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_D2_DOMAIN_FLAGS : Clear D2 Domain flags.
1098:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_ALL_DOMAIN_FLAGS : Clear D1 and D2 Domain flags.
1099:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @retval None.
1100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
1101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_ClearDomainFlags (uint32_t DomainFlags)
1102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
1103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Check the parameter */
1104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   assert_param (IS_PWR_DOMAIN_FLAG (DomainFlags));
1105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* D1 CPU flags */
1107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   if (DomainFlags == PWR_D1_DOMAIN_FLAGS)
1108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
1109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* Clear D1 domain flags (HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2) */
1110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     SET_BIT (PWR->CPUCR, PWR_CPUCR_CSSF);
1111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
1112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* D2 CPU flags */
1113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   else if (DomainFlags == PWR_D2_DOMAIN_FLAGS)
1114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
1115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* Clear D2 domain flags (HOLD1F, STOPF, SBF, SBF_D1, and SBF_D2) */
1116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     SET_BIT (PWR->CPU2CR, PWR_CPU2CR_CSSF);
1117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
1118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   else
1119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
1120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* Clear D1 domain flags (HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2) */
1121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     SET_BIT (PWR->CPUCR, PWR_CPUCR_CSSF);
1122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* Clear D2 domain flags (HOLD1F, STOPF, SBF, SBF_D1, and SBF_D2) */
1123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     SET_BIT (PWR->CPU2CR, PWR_CPU2CR_CSSF);
1124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
1125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
1126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
1128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief Hold the CPU and their domain peripherals when exiting STOP mode.
1129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @param  CPU : Specifies the core to be held.
1130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         This parameter can be one of the following values:
1131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *             @arg PWR_CORE_CPU1: Hold CPU1 and set CPU2 as master.
1132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *             @arg PWR_CORE_CPU2: Hold CPU2 and set CPU1 as master.
1133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @retval HAL status
1134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 49


1135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_HoldCore (uint32_t CPU)
1136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
1137:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   HAL_StatusTypeDef status = HAL_OK;
1138:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1139:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Check the parameters */
1140:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   assert_param (IS_PWR_CORE (CPU));
1141:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1142:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Check CPU index */
1143:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   if (CPU == PWR_CORE_CPU2)
1144:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
1145:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* If CPU1 is not held */
1146:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     if ((PWR->CPU2CR & PWR_CPU2CR_HOLD1) != PWR_CPU2CR_HOLD1)
1147:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     {
1148:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       /* Set HOLD2 bit */
1149:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       SET_BIT (PWR->CPUCR, PWR_CPUCR_HOLD2);
1150:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     }
1151:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     else
1152:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     {
1153:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       status = HAL_ERROR;
1154:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     }
1155:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
1156:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   else
1157:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
1158:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* If CPU2 is not held */
1159:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     if ((PWR->CPUCR & PWR_CPUCR_HOLD2) != PWR_CPUCR_HOLD2)
1160:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     {
1161:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       /* Set HOLD1 bit */
1162:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       SET_BIT (PWR->CPU2CR, PWR_CPU2CR_HOLD1);
1163:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     }
1164:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     else
1165:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     {
1166:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       status = HAL_ERROR;
1167:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     }
1168:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
1169:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1170:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   return status;
1171:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
1172:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1173:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
1174:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief Release the CPU and their domain peripherals after a wake-up from
1175:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *        STOP mode.
1176:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @param  CPU: Specifies the core to be released.
1177:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         This parameter can be one of the following values:
1178:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *             @arg  PWR_CORE_CPU1: Release the CPU1 and their domain
1179:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                   peripherals from holding.
1180:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *             @arg  PWR_CORE_CPU2: Release the CPU2 and their domain
1181:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                   peripherals from holding.
1182:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @retval None
1183:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
1184:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_ReleaseCore (uint32_t CPU)
1185:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
1186:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Check the parameters */
1187:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   assert_param (IS_PWR_CORE (CPU));
1188:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1189:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Check CPU index */
1190:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   if (CPU == PWR_CORE_CPU2)
1191:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 50


1192:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* Reset HOLD2 bit */
1193:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     CLEAR_BIT (PWR->CPUCR, PWR_CPUCR_HOLD2);
1194:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
1195:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   else
1196:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
1197:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* Reset HOLD1 bit */
1198:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     CLEAR_BIT (PWR->CPU2CR, PWR_CPU2CR_HOLD1);
1199:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
1200:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
1201:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (DUAL_CORE) */
1202:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1203:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1204:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
1205:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief Enable the Flash Power Down in Stop mode.
1206:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @note   When Flash Power Down is enabled  the Flash memory enters low-power
1207:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         mode when D1/SRD domain is in DStop mode. This feature allows to
1208:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         obtain the best trade-off between low-power consumption and restart
1209:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         time when exiting from DStop mode.
1210:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @retval None.
1211:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
1212:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_EnableFlashPowerDown (void)
1213:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
 669              		.loc 1 1213 1 is_stmt 1 view -0
 670              		.cfi_startproc
 671              		@ args = 0, pretend = 0, frame = 0
 672              		@ frame_needed = 0, uses_anonymous_args = 0
 673              		@ link register save eliminated.
1214:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Enable the Flash Power Down */
1215:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   SET_BIT (PWR->CR1, PWR_CR1_FLPS);
 674              		.loc 1 1215 3 view .LVU135
 675 0000 024A     		ldr	r2, .L64
 676 0002 1368     		ldr	r3, [r2]
 677 0004 43F40073 		orr	r3, r3, #512
 678 0008 1360     		str	r3, [r2]
1216:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
 679              		.loc 1 1216 1 is_stmt 0 view .LVU136
 680 000a 7047     		bx	lr
 681              	.L65:
 682              		.align	2
 683              	.L64:
 684 000c 00480258 		.word	1476544512
 685              		.cfi_endproc
 686              	.LFE346:
 688              		.section	.text.HAL_PWREx_DisableFlashPowerDown,"ax",%progbits
 689              		.align	1
 690              		.global	HAL_PWREx_DisableFlashPowerDown
 691              		.syntax unified
 692              		.thumb
 693              		.thumb_func
 695              	HAL_PWREx_DisableFlashPowerDown:
 696              	.LFB347:
1217:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1218:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
1219:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief Disable the Flash Power Down in Stop mode.
1220:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @note   When Flash Power Down is disabled  the Flash memory is kept on
1221:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         normal mode when D1/SRD domain is in DStop mode. This feature allows
1222:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         to obtain the best trade-off between low-power consumption and
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 51


1223:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         restart time when exiting from DStop mode.
1224:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @retval None.
1225:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
1226:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_DisableFlashPowerDown (void)
1227:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
 697              		.loc 1 1227 1 is_stmt 1 view -0
 698              		.cfi_startproc
 699              		@ args = 0, pretend = 0, frame = 0
 700              		@ frame_needed = 0, uses_anonymous_args = 0
 701              		@ link register save eliminated.
1228:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Disable the Flash Power Down */
1229:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   CLEAR_BIT (PWR->CR1, PWR_CR1_FLPS);
 702              		.loc 1 1229 3 view .LVU138
 703 0000 024A     		ldr	r2, .L67
 704 0002 1368     		ldr	r3, [r2]
 705 0004 23F40073 		bic	r3, r3, #512
 706 0008 1360     		str	r3, [r2]
1230:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
 707              		.loc 1 1230 1 is_stmt 0 view .LVU139
 708 000a 7047     		bx	lr
 709              	.L68:
 710              		.align	2
 711              	.L67:
 712 000c 00480258 		.word	1476544512
 713              		.cfi_endproc
 714              	.LFE347:
 716              		.section	.text.HAL_PWREx_EnableMemoryShutOff,"ax",%progbits
 717              		.align	1
 718              		.global	HAL_PWREx_EnableMemoryShutOff
 719              		.syntax unified
 720              		.thumb
 721              		.thumb_func
 723              	HAL_PWREx_EnableMemoryShutOff:
 724              	.LVL23:
 725              	.LFB348:
1231:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1232:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (PWR_CR1_SRDRAMSO)
1233:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
1234:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief Enable memory block shut-off in DStop or DStop2 modes
1235:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @note   In DStop or DStop2 mode, the content of the memory blocks is
1236:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         maintained. Further power optimization can be obtained by switching
1237:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         off some memory blocks. This optimization implies loss of the memory
1238:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         content. The user can select which memory is discarded during STOP
1239:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         mode by means of xxSO bits.
1240:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @param  MemoryBlock : Specifies the memory block to shut-off during DStop or
1241:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                       DStop2 mode.
1242:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *          This parameter can be one of the following values:
1243:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_SRD_AHB_MEMORY_BLOCK : SmartRun domain AHB memory.
1244:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_USB_FDCAN_MEMORY_BLOCK : High-speed interfaces USB and
1245:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                                              FDCAN memories.
1246:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_GFXMMU_JPEG_MEMORY_BLOCK : GFXMMU and JPEG memories.
1247:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_TCM_ECM_MEMORY_BLOCK : Instruction TCM and ETM memories.
1248:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_RAM1_AHB_MEMORY_BLOCK : AHB RAM1 memory.
1249:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_RAM2_AHB_MEMORY_BLOCK : AHB RAM2 memory.
1250:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_RAM1_AXI_MEMORY_BLOCK : AXI RAM1 memory.
1251:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_RAM2_AXI_MEMORY_BLOCK : AXI RAM2 memory.
1252:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_RAM3_AXI_MEMORY_BLOCK : AXI RAM3 memory.
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 52


1253:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @retval None.
1254:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
1255:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_EnableMemoryShutOff (uint32_t MemoryBlock)
1256:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
 726              		.loc 1 1256 1 is_stmt 1 view -0
 727              		.cfi_startproc
 728              		@ args = 0, pretend = 0, frame = 0
 729              		@ frame_needed = 0, uses_anonymous_args = 0
 730              		@ link register save eliminated.
1257:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Check the parameter */
1258:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   assert_param (IS_PWR_MEMORY_BLOCK (MemoryBlock));
 731              		.loc 1 1258 3 view .LVU141
1259:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1260:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Enable memory block shut-off */
1261:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   SET_BIT (PWR->CR1, MemoryBlock);
 732              		.loc 1 1261 3 view .LVU142
 733 0000 024A     		ldr	r2, .L70
 734 0002 1368     		ldr	r3, [r2]
 735 0004 0343     		orrs	r3, r3, r0
 736 0006 1360     		str	r3, [r2]
1262:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
 737              		.loc 1 1262 1 is_stmt 0 view .LVU143
 738 0008 7047     		bx	lr
 739              	.L71:
 740 000a 00BF     		.align	2
 741              	.L70:
 742 000c 00480258 		.word	1476544512
 743              		.cfi_endproc
 744              	.LFE348:
 746              		.section	.text.HAL_PWREx_DisableMemoryShutOff,"ax",%progbits
 747              		.align	1
 748              		.global	HAL_PWREx_DisableMemoryShutOff
 749              		.syntax unified
 750              		.thumb
 751              		.thumb_func
 753              	HAL_PWREx_DisableMemoryShutOff:
 754              	.LVL24:
 755              	.LFB349:
1263:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1264:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
1265:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief Disable memory block shut-off in DStop or DStop2 modes
1266:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @param  MemoryBlock : Specifies the memory block to keep content during
1267:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                       DStop or DStop2 mode.
1268:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *          This parameter can be one of the following values:
1269:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_SRD_AHB_MEMORY_BLOCK : SmartRun domain AHB memory.
1270:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_USB_FDCAN_MEMORY_BLOCK : High-speed interfaces USB and
1271:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                                              FDCAN memories.
1272:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_GFXMMU_JPEG_MEMORY_BLOCK : GFXMMU and JPEG memories.
1273:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_TCM_ECM_MEMORY_BLOCK : Instruction TCM and ETM memories.
1274:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_RAM1_AHB_MEMORY_BLOCK : AHB RAM1 memory.
1275:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_RAM2_AHB_MEMORY_BLOCK : AHB RAM2 memory.
1276:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_RAM1_AXI_MEMORY_BLOCK : AXI RAM1 memory.
1277:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_RAM2_AXI_MEMORY_BLOCK : AXI RAM2 memory.
1278:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_RAM3_AXI_MEMORY_BLOCK : AXI RAM3 memory.
1279:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @retval None.
1280:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
1281:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_DisableMemoryShutOff (uint32_t MemoryBlock)
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 53


1282:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
 756              		.loc 1 1282 1 is_stmt 1 view -0
 757              		.cfi_startproc
 758              		@ args = 0, pretend = 0, frame = 0
 759              		@ frame_needed = 0, uses_anonymous_args = 0
 760              		@ link register save eliminated.
1283:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Check the parameter */
1284:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   assert_param (IS_PWR_MEMORY_BLOCK (MemoryBlock));
 761              		.loc 1 1284 3 view .LVU145
1285:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1286:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Disable memory block shut-off */
1287:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   CLEAR_BIT (PWR->CR1, MemoryBlock);
 762              		.loc 1 1287 3 view .LVU146
 763 0000 024A     		ldr	r2, .L73
 764 0002 1368     		ldr	r3, [r2]
 765 0004 23EA0003 		bic	r3, r3, r0
 766 0008 1360     		str	r3, [r2]
1288:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
 767              		.loc 1 1288 1 is_stmt 0 view .LVU147
 768 000a 7047     		bx	lr
 769              	.L74:
 770              		.align	2
 771              	.L73:
 772 000c 00480258 		.word	1476544512
 773              		.cfi_endproc
 774              	.LFE349:
 776              		.section	.text.HAL_PWREx_EnableWakeUpPin,"ax",%progbits
 777              		.align	1
 778              		.global	HAL_PWREx_EnableWakeUpPin
 779              		.syntax unified
 780              		.thumb
 781              		.thumb_func
 783              	HAL_PWREx_EnableWakeUpPin:
 784              	.LVL25:
 785              	.LFB350:
1289:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (PWR_CR1_SRDRAMSO) */
1290:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1291:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
1292:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief Enable the Wake-up PINx functionality.
1293:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @param  sPinParams : Pointer to a PWREx_WakeupPinTypeDef structure that
1294:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                      contains the configuration information for the wake-up
1295:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                      Pin.
1296:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @note   For dual core devices, please ensure to configure the EXTI lines for
1297:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         the different Cortex-Mx. All combination are allowed: wake up only
1298:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         Cortex-M7, wake up only Cortex-M4 and wake up Cortex-M7 and
1299:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         Cortex-M4.
1300:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @retval None.
1301:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
1302:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_EnableWakeUpPin (PWREx_WakeupPinTypeDef *sPinParams)
1303:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
 786              		.loc 1 1303 1 is_stmt 1 view -0
 787              		.cfi_startproc
 788              		@ args = 0, pretend = 0, frame = 0
 789              		@ frame_needed = 0, uses_anonymous_args = 0
 790              		@ link register save eliminated.
 791              		.loc 1 1303 1 is_stmt 0 view .LVU149
 792 0000 10B4     		push	{r4}
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 54


 793              		.cfi_def_cfa_offset 4
 794              		.cfi_offset 4, -4
1304:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   uint32_t pinConfig;
 795              		.loc 1 1304 3 is_stmt 1 view .LVU150
1305:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   uint32_t regMask;
 796              		.loc 1 1305 3 view .LVU151
1306:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   const uint32_t pullMask = PWR_WKUPEPR_WKUPPUPD1;
 797              		.loc 1 1306 3 view .LVU152
 798              	.LVL26:
1307:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1308:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Check the parameters */
1309:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   assert_param (IS_PWR_WAKEUP_PIN (sPinParams->WakeUpPin));
 799              		.loc 1 1309 3 view .LVU153
1310:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   assert_param (IS_PWR_WAKEUP_PIN_POLARITY (sPinParams->PinPolarity));
 800              		.loc 1 1310 3 view .LVU154
1311:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   assert_param (IS_PWR_WAKEUP_PIN_PULL (sPinParams->PinPull));
 801              		.loc 1 1311 3 view .LVU155
1312:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   pinConfig = sPinParams->WakeUpPin | \
 802              		.loc 1 1313 3 view .LVU156
 803              		.loc 1 1313 25 is_stmt 0 view .LVU157
 804 0002 0368     		ldr	r3, [r0]
1314:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****               (sPinParams->PinPolarity << ((POSITION_VAL(sPinParams->WakeUpPin) + PWR_WKUPEPR_WKUPP
 805              		.loc 1 1314 26 view .LVU158
 806 0004 4168     		ldr	r1, [r0, #4]
 807              	.LVL27:
 808              	.LBB34:
 809              	.LBI34:
 947:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 948:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 949:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 950:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 951:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Data Memory Barrier
 952:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Ensures the apparent order of the explicit memory operations before
 953:Drivers/CMSIS/Include/cmsis_gcc.h ****            and after the instruction, without ensuring their completion.
 954:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 955:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void)
 956:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 957:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("dmb 0xF":::"memory");
 958:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 959:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 960:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 961:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 962:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Reverse byte order (32 bit)
 963:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x785
 964:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  Value to reverse
 965:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Reversed value
 966:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 967:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
 968:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 969:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
 970:Drivers/CMSIS/Include/cmsis_gcc.h ****   return __builtin_bswap32(value);
 971:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 972:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 973:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 974:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
 975:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 55


 976:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 977:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 978:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 979:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 980:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 981:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Reverse byte order (16 bit)
 982:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 
 983:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  Value to reverse
 984:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Reversed value
 985:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 986:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
 987:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 988:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 989:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 990:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
 991:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
 992:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 993:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 994:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 995:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 996:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Reverse byte order (16 bit)
 997:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For exam
 998:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  Value to reverse
 999:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Reversed value
1000:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
1001:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
1002:Drivers/CMSIS/Include/cmsis_gcc.h **** {
1003:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
1004:Drivers/CMSIS/Include/cmsis_gcc.h ****   return (int16_t)__builtin_bswap16(value);
1005:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
1006:Drivers/CMSIS/Include/cmsis_gcc.h ****   int16_t result;
1007:Drivers/CMSIS/Include/cmsis_gcc.h **** 
1008:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
1009:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
1010:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
1011:Drivers/CMSIS/Include/cmsis_gcc.h **** }
1012:Drivers/CMSIS/Include/cmsis_gcc.h **** 
1013:Drivers/CMSIS/Include/cmsis_gcc.h **** 
1014:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
1015:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Rotate Right in unsigned value (32 bit)
1016:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v
1017:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    op1  Value to rotate
1018:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    op2  Number of Bits to rotate
1019:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Rotated value
1020:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
1021:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
1022:Drivers/CMSIS/Include/cmsis_gcc.h **** {
1023:Drivers/CMSIS/Include/cmsis_gcc.h ****   op2 %= 32U;
1024:Drivers/CMSIS/Include/cmsis_gcc.h ****   if (op2 == 0U)
1025:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
1026:Drivers/CMSIS/Include/cmsis_gcc.h ****     return op1;
1027:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
1028:Drivers/CMSIS/Include/cmsis_gcc.h ****   return (op1 >> op2) | (op1 << (32U - op2));
1029:Drivers/CMSIS/Include/cmsis_gcc.h **** }
1030:Drivers/CMSIS/Include/cmsis_gcc.h **** 
1031:Drivers/CMSIS/Include/cmsis_gcc.h **** 
1032:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 56


1033:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Breakpoint
1034:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Causes the processor to enter Debug state.
1035:Drivers/CMSIS/Include/cmsis_gcc.h ****            Debug tools can use this to investigate system state when the instruction at a particula
1036:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  is ignored by the processor.
1037:Drivers/CMSIS/Include/cmsis_gcc.h ****                  If required, a debugger can use it to store additional information about the break
1038:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
1039:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __BKPT(value)                       __ASM volatile ("bkpt "#value)
1040:Drivers/CMSIS/Include/cmsis_gcc.h **** 
1041:Drivers/CMSIS/Include/cmsis_gcc.h **** 
1042:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
1043:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Reverse bit order of value
1044:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Reverses the bit order of the given value.
1045:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    value  Value to reverse
1046:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Reversed value
1047:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
1048:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
 810              		.loc 2 1048 31 is_stmt 1 view .LVU159
 811              	.LBB35:
1049:Drivers/CMSIS/Include/cmsis_gcc.h **** {
1050:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 812              		.loc 2 1050 3 view .LVU160
1051:Drivers/CMSIS/Include/cmsis_gcc.h **** 
1052:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
1053:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
1054:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
1055:Drivers/CMSIS/Include/cmsis_gcc.h ****    __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
 813              		.loc 2 1055 4 view .LVU161
 814              		.syntax unified
 815              	@ 1055 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
 816 0006 93FAA3F2 		rbit r2, r3
 817              	@ 0 "" 2
 818              	.LVL28:
1056:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
1057:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
1058:Drivers/CMSIS/Include/cmsis_gcc.h **** 
1059:Drivers/CMSIS/Include/cmsis_gcc.h ****   result = value;                      /* r will be reversed bits of v; first get LSB of v */
1060:Drivers/CMSIS/Include/cmsis_gcc.h ****   for (value >>= 1U; value != 0U; value >>= 1U)
1061:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
1062:Drivers/CMSIS/Include/cmsis_gcc.h ****     result <<= 1U;
1063:Drivers/CMSIS/Include/cmsis_gcc.h ****     result |= value & 1U;
1064:Drivers/CMSIS/Include/cmsis_gcc.h ****     s--;
1065:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
1066:Drivers/CMSIS/Include/cmsis_gcc.h ****   result <<= s;                        /* shift when v's highest bits are zero */
1067:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
1068:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
 819              		.loc 2 1068 3 view .LVU162
 820              		.loc 2 1068 3 is_stmt 0 view .LVU163
 821              		.thumb
 822              		.syntax unified
 823              	.LBE35:
 824              	.LBE34:
 825              	.LBB36:
 826              	.LBI36:
1069:Drivers/CMSIS/Include/cmsis_gcc.h **** }
1070:Drivers/CMSIS/Include/cmsis_gcc.h **** 
1071:Drivers/CMSIS/Include/cmsis_gcc.h **** 
1072:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 57


1073:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Count leading zeros
1074:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Counts the number of leading zeros of a data value.
1075:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]  value  Value to count the leading zeros
1076:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return             number of leading zeros in value
1077:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
1078:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
 827              		.loc 2 1078 30 is_stmt 1 view .LVU164
 828              	.LBB37:
1079:Drivers/CMSIS/Include/cmsis_gcc.h **** {
1080:Drivers/CMSIS/Include/cmsis_gcc.h ****   /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
1081:Drivers/CMSIS/Include/cmsis_gcc.h ****      __builtin_clz(0) is undefined behaviour, so handle this case specially.
1082:Drivers/CMSIS/Include/cmsis_gcc.h ****      This guarantees ARM-compatible results if happening to compile on a non-ARM
1083:Drivers/CMSIS/Include/cmsis_gcc.h ****      target, and ensures the compiler doesn't decide to activate any
1084:Drivers/CMSIS/Include/cmsis_gcc.h ****      optimisations using the logic "value was passed to __builtin_clz, so it
1085:Drivers/CMSIS/Include/cmsis_gcc.h ****      is non-zero".
1086:Drivers/CMSIS/Include/cmsis_gcc.h ****      ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
1087:Drivers/CMSIS/Include/cmsis_gcc.h ****      single CLZ instruction.
1088:Drivers/CMSIS/Include/cmsis_gcc.h ****    */
1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   if (value == 0U)
 829              		.loc 2 1089 3 view .LVU165
 830              		.loc 2 1089 6 is_stmt 0 view .LVU166
 831 000a 002A     		cmp	r2, #0
 832 000c 42D0     		beq	.L80
1090:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
1091:Drivers/CMSIS/Include/cmsis_gcc.h ****     return 32U;
1092:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
1093:Drivers/CMSIS/Include/cmsis_gcc.h ****   return __builtin_clz(value);
 833              		.loc 2 1093 3 is_stmt 1 view .LVU167
 834              		.loc 2 1093 10 is_stmt 0 discriminator 1 view .LVU168
 835 000e B2FA82F2 		clz	r2, r2
 836              	.LVL29:
 837              	.L76:
 838              		.loc 2 1093 10 discriminator 1 view .LVU169
 839              	.LBE37:
 840              	.LBE36:
 841              		.loc 1 1314 81 discriminator 2 view .LVU170
 842 0012 0832     		adds	r2, r2, #8
 843              		.loc 1 1314 107 discriminator 2 view .LVU171
 844 0014 02F01F02 		and	r2, r2, #31
 845              		.loc 1 1314 40 discriminator 2 view .LVU172
 846 0018 01FA02F2 		lsl	r2, r1, r2
1313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****               (sPinParams->PinPolarity << ((POSITION_VAL(sPinParams->WakeUpPin) + PWR_WKUPEPR_WKUPP
 847              		.loc 1 1313 37 view .LVU173
 848 001c 43EA0201 		orr	r1, r3, r2
1315:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****               (sPinParams->PinPull << (((POSITION_VAL(sPinParams->WakeUpPin) * PWR_WAKEUP_PINS_PULL
 849              		.loc 1 1315 26 view .LVU174
 850 0020 8468     		ldr	r4, [r0, #8]
 851              	.LVL30:
 852              	.LBB39:
 853              	.LBI39:
1048:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 854              		.loc 2 1048 31 is_stmt 1 view .LVU175
 855              	.LBB40:
1050:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 856              		.loc 2 1050 3 view .LVU176
1055:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 857              		.loc 2 1055 4 view .LVU177
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 58


 858              		.syntax unified
 859              	@ 1055 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
 860 0022 93FAA3F2 		rbit r2, r3
 861              	@ 0 "" 2
 862              	.LVL31:
1068:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 863              		.loc 2 1068 3 view .LVU178
1068:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 864              		.loc 2 1068 3 is_stmt 0 view .LVU179
 865              		.thumb
 866              		.syntax unified
 867              	.LBE40:
 868              	.LBE39:
 869              	.LBB41:
 870              	.LBI41:
1078:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 871              		.loc 2 1078 30 is_stmt 1 view .LVU180
 872              	.LBB42:
1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
 873              		.loc 2 1089 3 view .LVU181
1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
 874              		.loc 2 1089 6 is_stmt 0 view .LVU182
 875 0026 BAB3     		cbz	r2, .L81
 876              		.loc 2 1093 3 is_stmt 1 view .LVU183
 877              		.loc 2 1093 10 is_stmt 0 discriminator 1 view .LVU184
 878 0028 B2FA82F2 		clz	r2, r2
 879              	.LVL32:
 880              	.L77:
 881              		.loc 2 1093 10 discriminator 1 view .LVU185
 882              	.LBE42:
 883              	.LBE41:
 884              		.loc 1 1315 115 discriminator 2 view .LVU186
 885 002c 0832     		adds	r2, r2, #8
 886 002e 5200     		lsls	r2, r2, #1
 887              		.loc 1 1315 144 discriminator 2 view .LVU187
 888 0030 02F01E02 		and	r2, r2, #30
 889              		.loc 1 1315 36 discriminator 2 view .LVU188
 890 0034 04FA02F2 		lsl	r2, r4, r2
1313:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****               (sPinParams->PinPolarity << ((POSITION_VAL(sPinParams->WakeUpPin) + PWR_WKUPEPR_WKUPP
 891              		.loc 1 1313 13 view .LVU189
 892 0038 0A43     		orrs	r2, r2, r1
 893              	.LVL33:
1316:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   regMask   = sPinParams->WakeUpPin | \
 894              		.loc 1 1317 3 is_stmt 1 view .LVU190
 895              	.LBB44:
 896              	.LBI44:
1048:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 897              		.loc 2 1048 31 view .LVU191
 898              	.LBB45:
1050:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 899              		.loc 2 1050 3 view .LVU192
1055:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 900              		.loc 2 1055 4 view .LVU193
 901              		.syntax unified
 902              	@ 1055 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
 903 003a 93FAA3F1 		rbit r1, r3
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 59


 904              	@ 0 "" 2
 905              	.LVL34:
1068:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 906              		.loc 2 1068 3 view .LVU194
1068:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 907              		.loc 2 1068 3 is_stmt 0 view .LVU195
 908              		.thumb
 909              		.syntax unified
 910              	.LBE45:
 911              	.LBE44:
 912              	.LBB46:
 913              	.LBI46:
1078:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 914              		.loc 2 1078 30 is_stmt 1 view .LVU196
 915              	.LBB47:
1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
 916              		.loc 2 1089 3 view .LVU197
1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
 917              		.loc 2 1089 6 is_stmt 0 view .LVU198
 918 003e 69B3     		cbz	r1, .L82
 919              		.loc 2 1093 3 is_stmt 1 view .LVU199
 920              		.loc 2 1093 10 is_stmt 0 discriminator 1 view .LVU200
 921 0040 B1FA81F1 		clz	r1, r1
 922              	.LVL35:
 923              	.L78:
 924              		.loc 2 1093 10 discriminator 1 view .LVU201
 925              	.LBE47:
 926              	.LBE46:
1318:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****               (PWR_WKUPEPR_WKUPP1 << (POSITION_VAL(sPinParams->WakeUpPin) & 0x1FU)) | \
 927              		.loc 1 1318 75 discriminator 2 view .LVU202
 928 0044 01F01F0C 		and	ip, r1, #31
 929              		.loc 1 1318 35 discriminator 2 view .LVU203
 930 0048 4FF48071 		mov	r1, #256
 931 004c 01FA0CF1 		lsl	r1, r1, ip
1317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****               (PWR_WKUPEPR_WKUPP1 << (POSITION_VAL(sPinParams->WakeUpPin) & 0x1FU)) | \
 932              		.loc 1 1317 37 view .LVU204
 933 0050 1943     		orrs	r1, r1, r3
 934              	.LVL36:
 935              	.LBB49:
 936              	.LBI49:
1048:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 937              		.loc 2 1048 31 is_stmt 1 view .LVU205
 938              	.LBB50:
1050:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 939              		.loc 2 1050 3 view .LVU206
1055:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 940              		.loc 2 1055 4 view .LVU207
 941              		.syntax unified
 942              	@ 1055 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
 943 0052 93FAA3F3 		rbit r3, r3
 944              	@ 0 "" 2
 945              	.LVL37:
1068:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 946              		.loc 2 1068 3 view .LVU208
1068:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 947              		.loc 2 1068 3 is_stmt 0 view .LVU209
 948              		.thumb
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 60


 949              		.syntax unified
 950              	.LBE50:
 951              	.LBE49:
 952              	.LBB51:
 953              	.LBI51:
1078:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 954              		.loc 2 1078 30 is_stmt 1 view .LVU210
 955              	.LBB52:
1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
 956              		.loc 2 1089 3 view .LVU211
1089:Drivers/CMSIS/Include/cmsis_gcc.h ****   {
 957              		.loc 2 1089 6 is_stmt 0 view .LVU212
 958 0056 1BB3     		cbz	r3, .L83
 959              		.loc 2 1093 3 is_stmt 1 view .LVU213
 960              		.loc 2 1093 10 is_stmt 0 discriminator 1 view .LVU214
 961 0058 B3FA83F3 		clz	r3, r3
 962              	.LVL38:
 963              	.L79:
 964              		.loc 2 1093 10 discriminator 1 view .LVU215
 965              	.LBE52:
 966              	.LBE51:
1319:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****               (pullMask << ((POSITION_VAL(sPinParams->WakeUpPin) * PWR_WAKEUP_PINS_PULL_SHIFT_OFFSE
 967              		.loc 1 1319 66 discriminator 2 view .LVU216
 968 005c 5B00     		lsls	r3, r3, #1
 969              		.loc 1 1319 103 discriminator 2 view .LVU217
 970 005e 03F01E03 		and	r3, r3, #30
 971              		.loc 1 1319 25 discriminator 2 view .LVU218
 972 0062 4FF4403C 		mov	ip, #196608
 973 0066 0CFA03F3 		lsl	r3, ip, r3
1317:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****               (PWR_WKUPEPR_WKUPP1 << (POSITION_VAL(sPinParams->WakeUpPin) & 0x1FU)) | \
 974              		.loc 1 1317 13 view .LVU219
 975 006a 0B43     		orrs	r3, r3, r1
 976              	.LVL39:
1320:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1321:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Enable and Specify the Wake-Up pin polarity and the pull configuration
1322:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****      for the event detection (rising or falling edge) */
1323:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   MODIFY_REG (PWR->WKUPEPR, regMask, pinConfig);
 977              		.loc 1 1323 3 is_stmt 1 view .LVU220
 978 006c 0D4C     		ldr	r4, .L85
 979 006e A16A     		ldr	r1, [r4, #40]
 980 0070 21EA0303 		bic	r3, r1, r3
 981              	.LVL40:
 982              		.loc 1 1323 3 is_stmt 0 view .LVU221
 983 0074 1343     		orrs	r3, r3, r2
 984 0076 A362     		str	r3, [r4, #40]
1324:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #ifndef DUAL_CORE
1325:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Configure the Wakeup Pin EXTI Line */
1326:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   MODIFY_REG (EXTI->IMR2, PWR_EXTI_WAKEUP_PINS_MASK, (sPinParams->WakeUpPin << EXTI_IMR2_IM55_Pos))
 985              		.loc 1 1326 3 is_stmt 1 view .LVU222
 986 0078 4FF0B042 		mov	r2, #1476395008
 987              	.LVL41:
 988              		.loc 1 1326 3 is_stmt 0 view .LVU223
 989 007c D2F89030 		ldr	r3, [r2, #144]
 990 0080 23F0FC53 		bic	r3, r3, #528482304
 991 0084 0168     		ldr	r1, [r0]
 992 0086 43EAC153 		orr	r3, r3, r1, lsl #23
 993 008a C2F89030 		str	r3, [r2, #144]
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 61


1327:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* !DUAL_CORE */
1328:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
 994              		.loc 1 1328 1 view .LVU224
 995 008e 5DF8044B 		ldr	r4, [sp], #4
 996              		.cfi_remember_state
 997              		.cfi_restore 4
 998              		.cfi_def_cfa_offset 0
 999 0092 7047     		bx	lr
 1000              	.LVL42:
 1001              	.L80:
 1002              		.cfi_restore_state
 1003              	.LBB54:
 1004              	.LBB38:
1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
 1005              		.loc 2 1091 12 view .LVU225
 1006 0094 2022     		movs	r2, #32
 1007              	.LVL43:
1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
 1008              		.loc 2 1091 12 view .LVU226
 1009 0096 BCE7     		b	.L76
 1010              	.LVL44:
 1011              	.L81:
1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
 1012              		.loc 2 1091 12 view .LVU227
 1013              	.LBE38:
 1014              	.LBE54:
 1015              	.LBB55:
 1016              	.LBB43:
 1017 0098 2022     		movs	r2, #32
 1018              	.LVL45:
1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
 1019              		.loc 2 1091 12 view .LVU228
 1020 009a C7E7     		b	.L77
 1021              	.LVL46:
 1022              	.L82:
1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
 1023              		.loc 2 1091 12 view .LVU229
 1024              	.LBE43:
 1025              	.LBE55:
 1026              	.LBB56:
 1027              	.LBB48:
 1028 009c 2021     		movs	r1, #32
 1029              	.LVL47:
1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
 1030              		.loc 2 1091 12 view .LVU230
 1031 009e D1E7     		b	.L78
 1032              	.LVL48:
 1033              	.L83:
1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
 1034              		.loc 2 1091 12 view .LVU231
 1035              	.LBE48:
 1036              	.LBE56:
 1037              	.LBB57:
 1038              	.LBB53:
 1039 00a0 2023     		movs	r3, #32
 1040              	.LVL49:
1091:Drivers/CMSIS/Include/cmsis_gcc.h ****   }
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 62


 1041              		.loc 2 1091 12 view .LVU232
 1042 00a2 DBE7     		b	.L79
 1043              	.L86:
 1044              		.align	2
 1045              	.L85:
 1046 00a4 00480258 		.word	1476544512
 1047              	.LBE53:
 1048              	.LBE57:
 1049              		.cfi_endproc
 1050              	.LFE350:
 1052              		.section	.text.HAL_PWREx_DisableWakeUpPin,"ax",%progbits
 1053              		.align	1
 1054              		.global	HAL_PWREx_DisableWakeUpPin
 1055              		.syntax unified
 1056              		.thumb
 1057              		.thumb_func
 1059              	HAL_PWREx_DisableWakeUpPin:
 1060              	.LVL50:
 1061              	.LFB351:
1329:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1330:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
1331:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief Disable the Wake-up PINx functionality.
1332:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @param  WakeUpPin : Specifies the Wake-Up pin to be disabled.
1333:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *          This parameter can be one of the following values:
1334:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *           @arg PWR_WAKEUP_PIN1 : Disable PA0  wake-up PIN.
1335:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *           @arg PWR_WAKEUP_PIN2 : Disable PA2  wake-up PIN.
1336:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *           @arg PWR_WAKEUP_PIN3 : Disable PI8  wake-up PIN.
1337:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *           @arg PWR_WAKEUP_PIN4 : Disable PC13 wake-up PIN.
1338:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *           @arg PWR_WAKEUP_PIN5 : Disable PI11 wake-up PIN.
1339:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *           @arg PWR_WAKEUP_PIN6 : Disable PC1  wake-up PIN.
1340:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @note   The PWR_WAKEUP_PIN3 and PWR_WAKEUP_PIN5 are available only for
1341:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         devices that support GPIOI port.
1342:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @retval None
1343:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
1344:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_DisableWakeUpPin (uint32_t WakeUpPin)
1345:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
 1062              		.loc 1 1345 1 is_stmt 1 view -0
 1063              		.cfi_startproc
 1064              		@ args = 0, pretend = 0, frame = 0
 1065              		@ frame_needed = 0, uses_anonymous_args = 0
 1066              		@ link register save eliminated.
1346:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Check the parameter */
1347:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   assert_param (IS_PWR_WAKEUP_PIN (WakeUpPin));
 1067              		.loc 1 1347 3 view .LVU234
1348:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1349:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Disable the WakeUpPin */
1350:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   CLEAR_BIT (PWR->WKUPEPR, WakeUpPin);
 1068              		.loc 1 1350 3 view .LVU235
 1069 0000 024A     		ldr	r2, .L88
 1070 0002 936A     		ldr	r3, [r2, #40]
 1071 0004 23EA0003 		bic	r3, r3, r0
 1072 0008 9362     		str	r3, [r2, #40]
1351:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
 1073              		.loc 1 1351 1 is_stmt 0 view .LVU236
 1074 000a 7047     		bx	lr
 1075              	.L89:
 1076              		.align	2
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 63


 1077              	.L88:
 1078 000c 00480258 		.word	1476544512
 1079              		.cfi_endproc
 1080              	.LFE351:
 1082              		.section	.text.HAL_PWREx_GetWakeupFlag,"ax",%progbits
 1083              		.align	1
 1084              		.global	HAL_PWREx_GetWakeupFlag
 1085              		.syntax unified
 1086              		.thumb
 1087              		.thumb_func
 1089              	HAL_PWREx_GetWakeupFlag:
 1090              	.LVL51:
 1091              	.LFB352:
1352:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1353:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
1354:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief Get the Wake-Up Pin pending flags.
1355:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @param  WakeUpFlag : Specifies the Wake-Up PIN flag to be checked.
1356:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *          This parameter can be one of the following values:
1357:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_WAKEUP_FLAG1    : Get wakeup event received from PA0.
1358:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_WAKEUP_FLAG2    : Get wakeup event received from PA2.
1359:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_WAKEUP_FLAG3    : Get wakeup event received from PI8.
1360:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_WAKEUP_FLAG4    : Get wakeup event received from PC13.
1361:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_WAKEUP_FLAG5    : Get wakeup event received from PI11.
1362:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_WAKEUP_FLAG6    : Get wakeup event received from PC1.
1363:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_WAKEUP_FLAG_ALL : Get Wakeup event received from all
1364:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                                      wake up pins.
1365:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @note   The PWR_WAKEUP_FLAG3 and PWR_WAKEUP_FLAG5 are available only for
1366:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         devices that support GPIOI port.
1367:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @retval The Wake-Up pin flag.
1368:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
1369:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** uint32_t HAL_PWREx_GetWakeupFlag (uint32_t WakeUpFlag)
1370:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
 1092              		.loc 1 1370 1 is_stmt 1 view -0
 1093              		.cfi_startproc
 1094              		@ args = 0, pretend = 0, frame = 0
 1095              		@ frame_needed = 0, uses_anonymous_args = 0
 1096              		@ link register save eliminated.
1371:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Check the parameters */
1372:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   assert_param (IS_PWR_WAKEUP_FLAG (WakeUpFlag));
 1097              		.loc 1 1372 3 view .LVU238
1373:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1374:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Return the wake up pin flag */
1375:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   return (PWR->WKUPFR & WakeUpFlag);
 1098              		.loc 1 1375 3 view .LVU239
 1099              		.loc 1 1375 14 is_stmt 0 view .LVU240
 1100 0000 014B     		ldr	r3, .L91
 1101 0002 5B6A     		ldr	r3, [r3, #36]
1376:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
 1102              		.loc 1 1376 1 view .LVU241
 1103 0004 1840     		ands	r0, r0, r3
 1104              	.LVL52:
 1105              		.loc 1 1376 1 view .LVU242
 1106 0006 7047     		bx	lr
 1107              	.L92:
 1108              		.align	2
 1109              	.L91:
 1110 0008 00480258 		.word	1476544512
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 64


 1111              		.cfi_endproc
 1112              	.LFE352:
 1114              		.section	.text.HAL_PWREx_ClearWakeupFlag,"ax",%progbits
 1115              		.align	1
 1116              		.global	HAL_PWREx_ClearWakeupFlag
 1117              		.syntax unified
 1118              		.thumb
 1119              		.thumb_func
 1121              	HAL_PWREx_ClearWakeupFlag:
 1122              	.LVL53:
 1123              	.LFB353:
1377:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1378:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
1379:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief Clear the Wake-Up pin pending flag.
1380:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @param  WakeUpFlag: Specifies the Wake-Up PIN flag to clear.
1381:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *          This parameter can be one of the following values:
1382:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_WAKEUP_FLAG1 : Clear the wakeup event received from PA0.
1383:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_WAKEUP_FLAG2 : Clear the wakeup event received from PA2.
1384:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_WAKEUP_FLAG3 : Clear the wakeup event received from PI8.
1385:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_WAKEUP_FLAG4 : Clear the wakeup event received from PC13.
1386:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_WAKEUP_FLAG5 : Clear the wakeup event received from PI11.
1387:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_WAKEUP_FLAG6 : Clear the wakeup event received from PC1.
1388:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_WAKEUP_FLAG_ALL : Clear the wakeup events received from
1389:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                                      all wake up pins.
1390:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @note   The PWR_WAKEUP_FLAG3 and PWR_WAKEUP_FLAG5 are available only for
1391:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         devices that support GPIOI port.
1392:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @retval HAL status.
1393:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
1394:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag (uint32_t WakeUpFlag)
1395:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
 1124              		.loc 1 1395 1 is_stmt 1 view -0
 1125              		.cfi_startproc
 1126              		@ args = 0, pretend = 0, frame = 0
 1127              		@ frame_needed = 0, uses_anonymous_args = 0
 1128              		@ link register save eliminated.
1396:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Check the parameter */
1397:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   assert_param (IS_PWR_WAKEUP_FLAG (WakeUpFlag));
 1129              		.loc 1 1397 3 view .LVU244
1398:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1399:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Clear the wake up event received from wake up pin x */
1400:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   SET_BIT (PWR->WKUPCR, WakeUpFlag);
 1130              		.loc 1 1400 3 view .LVU245
 1131 0000 054B     		ldr	r3, .L96
 1132 0002 1A6A     		ldr	r2, [r3, #32]
 1133 0004 0243     		orrs	r2, r2, r0
 1134 0006 1A62     		str	r2, [r3, #32]
1401:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1402:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Check if the wake up event is well cleared */
1403:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   if ((PWR->WKUPFR & WakeUpFlag) != 0U)
 1135              		.loc 1 1403 3 view .LVU246
 1136              		.loc 1 1403 11 is_stmt 0 view .LVU247
 1137 0008 5B6A     		ldr	r3, [r3, #36]
 1138              		.loc 1 1403 6 view .LVU248
 1139 000a 0342     		tst	r3, r0
 1140 000c 01D1     		bne	.L95
1404:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
1405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     return HAL_ERROR;
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 65


1406:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
1407:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1408:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   return HAL_OK;
 1141              		.loc 1 1408 10 view .LVU249
 1142 000e 0020     		movs	r0, #0
 1143              	.LVL54:
 1144              		.loc 1 1408 10 view .LVU250
 1145 0010 7047     		bx	lr
 1146              	.LVL55:
 1147              	.L95:
1405:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
 1148              		.loc 1 1405 12 view .LVU251
 1149 0012 0120     		movs	r0, #1
 1150              	.LVL56:
1409:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
 1151              		.loc 1 1409 1 view .LVU252
 1152 0014 7047     		bx	lr
 1153              	.L97:
 1154 0016 00BF     		.align	2
 1155              	.L96:
 1156 0018 00480258 		.word	1476544512
 1157              		.cfi_endproc
 1158              	.LFE353:
 1160              		.section	.text.HAL_PWREx_WKUP1_Callback,"ax",%progbits
 1161              		.align	1
 1162              		.weak	HAL_PWREx_WKUP1_Callback
 1163              		.syntax unified
 1164              		.thumb
 1165              		.thumb_func
 1167              	HAL_PWREx_WKUP1_Callback:
 1168              	.LFB355:
1410:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1411:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
1412:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief This function handles the PWR WAKEUP PIN interrupt request.
1413:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @note   This API should be called under the WAKEUP_PIN_IRQHandler().
1414:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @retval None.
1415:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
1416:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_WAKEUP_PIN_IRQHandler (void)
1417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
1418:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Wakeup pin EXTI line interrupt detected */
1419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   if (READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF1) != 0U)
1420:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
1421:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* Clear PWR WKUPF1 flag */
1422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP1);
1423:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1424:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* PWR WKUP1 interrupt user callback */
1425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     HAL_PWREx_WKUP1_Callback ();
1426:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
1427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF2) != 0U)
1428:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
1429:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* Clear PWR WKUPF2 flag */
1430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP2);
1431:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1432:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* PWR WKUP2 interrupt user callback */
1433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     HAL_PWREx_WKUP2_Callback ();
1434:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
1435:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (PWR_WKUPFR_WKUPF3)
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 66


1436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF3) != 0U)
1437:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
1438:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* Clear PWR WKUPF3 flag */
1439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP3);
1440:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1441:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* PWR WKUP3 interrupt user callback */
1442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     HAL_PWREx_WKUP3_Callback ();
1443:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
1444:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (PWR_WKUPFR_WKUPF3) */
1445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF4) != 0U)
1446:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
1447:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* Clear PWR WKUPF4 flag */
1448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP4);
1449:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1450:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* PWR WKUP4 interrupt user callback */
1451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     HAL_PWREx_WKUP4_Callback ();
1452:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
1453:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (PWR_WKUPFR_WKUPF5)
1454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   else if (READ_BIT (PWR->WKUPFR, PWR_WKUPFR_WKUPF5) != 0U)
1455:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
1456:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* Clear PWR WKUPF5 flag */
1457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP5);
1458:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1459:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* PWR WKUP5 interrupt user callback */
1460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     HAL_PWREx_WKUP5_Callback ();
1461:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
1462:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (PWR_WKUPFR_WKUPF5) */
1463:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   else
1464:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
1465:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* Clear PWR WKUPF6 flag */
1466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     __HAL_PWR_CLEAR_WAKEUPFLAG (PWR_FLAG_WKUP6);
1467:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1468:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     /* PWR WKUP6 interrupt user callback */
1469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     HAL_PWREx_WKUP6_Callback ();
1470:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
1471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
1472:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1473:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
1474:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief PWR WKUP1 interrupt callback.
1475:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @retval None.
1476:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
1477:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __weak void HAL_PWREx_WKUP1_Callback (void)
1478:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
 1169              		.loc 1 1478 1 is_stmt 1 view -0
 1170              		.cfi_startproc
 1171              		@ args = 0, pretend = 0, frame = 0
 1172              		@ frame_needed = 0, uses_anonymous_args = 0
 1173              		@ link register save eliminated.
1479:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* NOTE : This function should not be modified, when the callback is needed,
1480:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****             the HAL_PWREx_WKUP1Callback can be implemented in the user file
1481:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
1482:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
 1174              		.loc 1 1482 1 view .LVU254
 1175 0000 7047     		bx	lr
 1176              		.cfi_endproc
 1177              	.LFE355:
 1179              		.section	.text.HAL_PWREx_WKUP2_Callback,"ax",%progbits
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 67


 1180              		.align	1
 1181              		.weak	HAL_PWREx_WKUP2_Callback
 1182              		.syntax unified
 1183              		.thumb
 1184              		.thumb_func
 1186              	HAL_PWREx_WKUP2_Callback:
 1187              	.LFB356:
1483:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1484:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
1485:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief PWR WKUP2 interrupt callback.
1486:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @retval None.
1487:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
1488:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __weak void HAL_PWREx_WKUP2_Callback (void)
1489:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
 1188              		.loc 1 1489 1 view -0
 1189              		.cfi_startproc
 1190              		@ args = 0, pretend = 0, frame = 0
 1191              		@ frame_needed = 0, uses_anonymous_args = 0
 1192              		@ link register save eliminated.
1490:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* NOTE : This function should not be modified, when the callback is needed,
1491:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****             the HAL_PWREx_WKUP2Callback can be implemented in the user file
1492:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
1493:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
 1193              		.loc 1 1493 1 view .LVU256
 1194 0000 7047     		bx	lr
 1195              		.cfi_endproc
 1196              	.LFE356:
 1198              		.section	.text.HAL_PWREx_WKUP3_Callback,"ax",%progbits
 1199              		.align	1
 1200              		.weak	HAL_PWREx_WKUP3_Callback
 1201              		.syntax unified
 1202              		.thumb
 1203              		.thumb_func
 1205              	HAL_PWREx_WKUP3_Callback:
 1206              	.LFB357:
1494:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1495:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (PWR_WKUPFR_WKUPF3)
1496:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
1497:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief PWR WKUP3 interrupt callback.
1498:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @retval None.
1499:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
1500:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __weak void HAL_PWREx_WKUP3_Callback (void)
1501:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
 1207              		.loc 1 1501 1 view -0
 1208              		.cfi_startproc
 1209              		@ args = 0, pretend = 0, frame = 0
 1210              		@ frame_needed = 0, uses_anonymous_args = 0
 1211              		@ link register save eliminated.
1502:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* NOTE : This function should not be modified, when the callback is needed,
1503:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****             the HAL_PWREx_WKUP3Callback can be implemented in the user file
1504:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
1505:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
 1212              		.loc 1 1505 1 view .LVU258
 1213 0000 7047     		bx	lr
 1214              		.cfi_endproc
 1215              	.LFE357:
 1217              		.section	.text.HAL_PWREx_WKUP4_Callback,"ax",%progbits
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 68


 1218              		.align	1
 1219              		.weak	HAL_PWREx_WKUP4_Callback
 1220              		.syntax unified
 1221              		.thumb
 1222              		.thumb_func
 1224              	HAL_PWREx_WKUP4_Callback:
 1225              	.LFB358:
1506:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (PWR_WKUPFR_WKUPF3) */
1507:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1508:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
1509:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief PWR WKUP4 interrupt callback.
1510:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @retval None.
1511:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
1512:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __weak void HAL_PWREx_WKUP4_Callback (void)
1513:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
 1226              		.loc 1 1513 1 view -0
 1227              		.cfi_startproc
 1228              		@ args = 0, pretend = 0, frame = 0
 1229              		@ frame_needed = 0, uses_anonymous_args = 0
 1230              		@ link register save eliminated.
1514:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* NOTE : This function should not be modified, when the callback is needed,
1515:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****             the HAL_PWREx_WKUP4Callback can be implemented in the user file
1516:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
1517:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
 1231              		.loc 1 1517 1 view .LVU260
 1232 0000 7047     		bx	lr
 1233              		.cfi_endproc
 1234              	.LFE358:
 1236              		.section	.text.HAL_PWREx_WKUP5_Callback,"ax",%progbits
 1237              		.align	1
 1238              		.weak	HAL_PWREx_WKUP5_Callback
 1239              		.syntax unified
 1240              		.thumb
 1241              		.thumb_func
 1243              	HAL_PWREx_WKUP5_Callback:
 1244              	.LFB359:
1518:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1519:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (PWR_WKUPFR_WKUPF5)
1520:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
1521:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief PWR WKUP5 interrupt callback.
1522:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @retval None.
1523:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
1524:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __weak void HAL_PWREx_WKUP5_Callback (void)
1525:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
 1245              		.loc 1 1525 1 view -0
 1246              		.cfi_startproc
 1247              		@ args = 0, pretend = 0, frame = 0
 1248              		@ frame_needed = 0, uses_anonymous_args = 0
 1249              		@ link register save eliminated.
1526:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* NOTE : This function should not be modified, when the callback is needed,
1527:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****             the HAL_PWREx_WKUP5Callback can be implemented in the user file
1528:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
1529:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
 1250              		.loc 1 1529 1 view .LVU262
 1251 0000 7047     		bx	lr
 1252              		.cfi_endproc
 1253              	.LFE359:
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 69


 1255              		.section	.text.HAL_PWREx_WKUP6_Callback,"ax",%progbits
 1256              		.align	1
 1257              		.weak	HAL_PWREx_WKUP6_Callback
 1258              		.syntax unified
 1259              		.thumb
 1260              		.thumb_func
 1262              	HAL_PWREx_WKUP6_Callback:
 1263              	.LFB360:
1530:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (PWR_WKUPFR_WKUPF5) */
1531:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1532:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
1533:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief PWR WKUP6 interrupt callback.
1534:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @retval None.
1535:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
1536:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __weak void HAL_PWREx_WKUP6_Callback (void)
1537:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
 1264              		.loc 1 1537 1 view -0
 1265              		.cfi_startproc
 1266              		@ args = 0, pretend = 0, frame = 0
 1267              		@ frame_needed = 0, uses_anonymous_args = 0
 1268              		@ link register save eliminated.
1538:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* NOTE : This function should not be modified, when the callback is needed,
1539:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****             the HAL_PWREx_WKUP6Callback can be implemented in the user file
1540:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
1541:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
 1269              		.loc 1 1541 1 view .LVU264
 1270 0000 7047     		bx	lr
 1271              		.cfi_endproc
 1272              	.LFE360:
 1274              		.section	.text.HAL_PWREx_WAKEUP_PIN_IRQHandler,"ax",%progbits
 1275              		.align	1
 1276              		.global	HAL_PWREx_WAKEUP_PIN_IRQHandler
 1277              		.syntax unified
 1278              		.thumb
 1279              		.thumb_func
 1281              	HAL_PWREx_WAKEUP_PIN_IRQHandler:
 1282              	.LFB354:
1417:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Wakeup pin EXTI line interrupt detected */
 1283              		.loc 1 1417 1 view -0
 1284              		.cfi_startproc
 1285              		@ args = 0, pretend = 0, frame = 0
 1286              		@ frame_needed = 0, uses_anonymous_args = 0
 1287 0000 08B5     		push	{r3, lr}
 1288              		.cfi_def_cfa_offset 8
 1289              		.cfi_offset 3, -8
 1290              		.cfi_offset 14, -4
1419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
 1291              		.loc 1 1419 3 view .LVU266
1419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
 1292              		.loc 1 1419 7 is_stmt 0 view .LVU267
 1293 0002 244B     		ldr	r3, .L116
 1294 0004 5B6A     		ldr	r3, [r3, #36]
1419:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
 1295              		.loc 1 1419 6 view .LVU268
 1296 0006 13F0010F 		tst	r3, #1
 1297 000a 1BD1     		bne	.L112
1427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 70


 1298              		.loc 1 1427 8 is_stmt 1 view .LVU269
1427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
 1299              		.loc 1 1427 12 is_stmt 0 view .LVU270
 1300 000c 214B     		ldr	r3, .L116
 1301 000e 5B6A     		ldr	r3, [r3, #36]
1427:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
 1302              		.loc 1 1427 11 view .LVU271
 1303 0010 13F0020F 		tst	r3, #2
 1304 0014 1ED1     		bne	.L113
1436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
 1305              		.loc 1 1436 8 is_stmt 1 view .LVU272
1436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
 1306              		.loc 1 1436 12 is_stmt 0 view .LVU273
 1307 0016 1F4B     		ldr	r3, .L116
 1308 0018 5B6A     		ldr	r3, [r3, #36]
1436:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
 1309              		.loc 1 1436 11 view .LVU274
 1310 001a 13F0040F 		tst	r3, #4
 1311 001e 21D1     		bne	.L114
1445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
 1312              		.loc 1 1445 8 is_stmt 1 view .LVU275
1445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
 1313              		.loc 1 1445 12 is_stmt 0 view .LVU276
 1314 0020 1C4B     		ldr	r3, .L116
 1315 0022 5B6A     		ldr	r3, [r3, #36]
1445:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
 1316              		.loc 1 1445 11 view .LVU277
 1317 0024 13F0080F 		tst	r3, #8
 1318 0028 24D1     		bne	.L115
1454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
 1319              		.loc 1 1454 8 is_stmt 1 view .LVU278
1454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
 1320              		.loc 1 1454 12 is_stmt 0 view .LVU279
 1321 002a 1A4B     		ldr	r3, .L116
 1322 002c 5B6A     		ldr	r3, [r3, #36]
1454:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
 1323              		.loc 1 1454 11 view .LVU280
 1324 002e 13F0100F 		tst	r3, #16
 1325 0032 27D0     		beq	.L110
1457:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 1326              		.loc 1 1457 5 is_stmt 1 view .LVU281
 1327 0034 174A     		ldr	r2, .L116
 1328 0036 136A     		ldr	r3, [r2, #32]
 1329 0038 43F01003 		orr	r3, r3, #16
 1330 003c 1362     		str	r3, [r2, #32]
1460:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
 1331              		.loc 1 1460 5 view .LVU282
 1332 003e FFF7FEFF 		bl	HAL_PWREx_WKUP5_Callback
 1333              	.LVL57:
 1334 0042 06E0     		b	.L104
 1335              	.L112:
1422:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 1336              		.loc 1 1422 5 view .LVU283
 1337 0044 134A     		ldr	r2, .L116
 1338 0046 136A     		ldr	r3, [r2, #32]
 1339 0048 43F00103 		orr	r3, r3, #1
 1340 004c 1362     		str	r3, [r2, #32]
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 71


1425:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
 1341              		.loc 1 1425 5 view .LVU284
 1342 004e FFF7FEFF 		bl	HAL_PWREx_WKUP1_Callback
 1343              	.LVL58:
 1344              	.L104:
1471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 1345              		.loc 1 1471 1 is_stmt 0 view .LVU285
 1346 0052 08BD     		pop	{r3, pc}
 1347              	.L113:
1430:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 1348              		.loc 1 1430 5 is_stmt 1 view .LVU286
 1349 0054 0F4A     		ldr	r2, .L116
 1350 0056 136A     		ldr	r3, [r2, #32]
 1351 0058 43F00203 		orr	r3, r3, #2
 1352 005c 1362     		str	r3, [r2, #32]
1433:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
 1353              		.loc 1 1433 5 view .LVU287
 1354 005e FFF7FEFF 		bl	HAL_PWREx_WKUP2_Callback
 1355              	.LVL59:
 1356 0062 F6E7     		b	.L104
 1357              	.L114:
1439:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 1358              		.loc 1 1439 5 view .LVU288
 1359 0064 0B4A     		ldr	r2, .L116
 1360 0066 136A     		ldr	r3, [r2, #32]
 1361 0068 43F00403 		orr	r3, r3, #4
 1362 006c 1362     		str	r3, [r2, #32]
1442:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
 1363              		.loc 1 1442 5 view .LVU289
 1364 006e FFF7FEFF 		bl	HAL_PWREx_WKUP3_Callback
 1365              	.LVL60:
 1366 0072 EEE7     		b	.L104
 1367              	.L115:
1448:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 1368              		.loc 1 1448 5 view .LVU290
 1369 0074 074A     		ldr	r2, .L116
 1370 0076 136A     		ldr	r3, [r2, #32]
 1371 0078 43F00803 		orr	r3, r3, #8
 1372 007c 1362     		str	r3, [r2, #32]
1451:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
 1373              		.loc 1 1451 5 view .LVU291
 1374 007e FFF7FEFF 		bl	HAL_PWREx_WKUP4_Callback
 1375              	.LVL61:
 1376 0082 E6E7     		b	.L104
 1377              	.L110:
1466:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 1378              		.loc 1 1466 5 view .LVU292
 1379 0084 034A     		ldr	r2, .L116
 1380 0086 136A     		ldr	r3, [r2, #32]
 1381 0088 43F02003 		orr	r3, r3, #32
 1382 008c 1362     		str	r3, [r2, #32]
1469:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
 1383              		.loc 1 1469 5 view .LVU293
 1384 008e FFF7FEFF 		bl	HAL_PWREx_WKUP6_Callback
 1385              	.LVL62:
1471:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 1386              		.loc 1 1471 1 is_stmt 0 view .LVU294
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 72


 1387 0092 DEE7     		b	.L104
 1388              	.L117:
 1389              		.align	2
 1390              	.L116:
 1391 0094 00480258 		.word	1476544512
 1392              		.cfi_endproc
 1393              	.LFE354:
 1395              		.section	.text.HAL_PWREx_EnableBkUpReg,"ax",%progbits
 1396              		.align	1
 1397              		.global	HAL_PWREx_EnableBkUpReg
 1398              		.syntax unified
 1399              		.thumb
 1400              		.thumb_func
 1402              	HAL_PWREx_EnableBkUpReg:
 1403              	.LFB361:
1542:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
1543:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @}
1544:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
1545:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1546:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** @defgroup PWREx_Exported_Functions_Group3 Peripherals control functions
1547:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief    Peripherals control functions
1548:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *
1549:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** @verbatim
1550:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****  ===============================================================================
1551:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****                  ##### Peripherals control functions #####
1552:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****  ===============================================================================
1553:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1554:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     *** Main and Backup Regulators configuration ***
1555:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     ================================================
1556:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     [..]
1557:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       (+) The backup domain includes 4 Kbytes of backup SRAM accessible only
1558:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           from the CPU, and addressed in 32-bit, 16-bit or 8-bit mode. Its
1559:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           content is retained even in Standby or VBAT mode when the low power
1560:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           backup regulator is enabled. It can be considered as an internal
1561:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           EEPROM when VBAT is always present. You can use the
1562:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           HAL_PWREx_EnableBkUpReg() function to enable the low power backup
1563:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           regulator.
1564:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       (+) When the backup domain is supplied by VDD (analog switch connected to
1565:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           VDD) the backup SRAM is powered from VDD which replaces the VBAT power
1566:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           supply to save battery life.
1567:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       (+) The backup SRAM is not mass erased by a tamper event. It is read
1568:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           protected to prevent confidential data, such as cryptographic private
1569:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           key, from being accessed. The backup SRAM can be erased only through
1570:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           the Flash interface when a protection level change from level 1 to
1571:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           level 0 is requested.
1572:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       -@- Refer to the description of Read protection (RDP) in the Flash
1573:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           programming manual.
1574:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       (+) The main internal regulator can be configured to have a tradeoff
1575:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           between performance and power consumption when the device does not
1576:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           operate at the maximum frequency. This is done through
1577:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           HAL_PWREx_ControlVoltageScaling(VOS) function which configure the VOS
1578:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           bit in PWR_D3CR register.
1579:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       (+) The main internal regulator can be configured to operate in Low Power
1580:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           mode when the system enters STOP mode to further reduce power
1581:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           consumption.
1582:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           This is done through HAL_PWREx_ControlStopModeVoltageScaling(SVOS)
1583:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           function which configure the SVOS bit in PWR_CR1 register.
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 73


1584:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           The selected SVOS4 and SVOS5 levels add an additional startup delay
1585:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           when exiting from system Stop mode.
1586:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     -@- Refer to the product datasheets for more details.
1587:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1588:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     *** USB Regulator configuration ***
1589:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     ===================================
1590:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     [..]
1591:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       (+) The USB transceivers are supplied from a dedicated VDD33USB supply
1592:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           that can be provided either by the integrated USB regulator, or by an
1593:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           external USB supply.
1594:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       (+) The USB regulator is enabled by HAL_PWREx_EnableUSBReg() function, the
1595:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           VDD33USB is then provided from the USB regulator.
1596:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       (+) When the USB regulator is enabled, the VDD33USB supply level detector
1597:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           shall be enabled through  HAL_PWREx_EnableUSBVoltageDetector()
1598:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           function.
1599:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       (+) The USB regulator is disabled through HAL_PWREx_DisableUSBReg()
1600:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           function and VDD33USB can be provided from an external supply. In this
1601:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           case VDD33USB and VDD50USB shall be connected together.
1602:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1603:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     *** VBAT battery charging ***
1604:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     =============================
1605:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     [..]
1606:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       (+) When VDD is present, the external battery connected to VBAT can be
1607:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           charged through an internal resistance. VBAT charging can be performed
1608:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           either through a 5 KOhm resistor or through a 1.5 KOhm resistor.
1609:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       (+) VBAT charging is enabled by HAL_PWREx_EnableBatteryCharging
1610:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           (ResistorValue) function with:
1611:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****        (++) ResistorValue:
1612:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         (+++) PWR_BATTERY_CHARGING_RESISTOR_5: 5 KOhm resistor.
1613:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         (+++) PWR_BATTERY_CHARGING_RESISTOR_1_5: 1.5 KOhm resistor.
1614:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       (+) VBAT charging is disabled by HAL_PWREx_DisableBatteryCharging()
1615:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           function.
1616:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1617:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** @endverbatim
1618:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @{
1619:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
1620:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1621:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
1622:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief Enable the Backup Regulator.
1623:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @retval HAL status.
1624:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
1625:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg (void)
1626:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
 1404              		.loc 1 1626 1 is_stmt 1 view -0
 1405              		.cfi_startproc
 1406              		@ args = 0, pretend = 0, frame = 0
 1407              		@ frame_needed = 0, uses_anonymous_args = 0
 1408 0000 10B5     		push	{r4, lr}
 1409              		.cfi_def_cfa_offset 8
 1410              		.cfi_offset 4, -8
 1411              		.cfi_offset 14, -4
1627:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   uint32_t tickstart;
 1412              		.loc 1 1627 3 view .LVU296
1628:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1629:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Enable the Backup regulator */
1630:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   SET_BIT (PWR->CR2, PWR_CR2_BREN);
 1413              		.loc 1 1630 3 view .LVU297
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 74


 1414 0002 0B4A     		ldr	r2, .L125
 1415 0004 9368     		ldr	r3, [r2, #8]
 1416 0006 43F00103 		orr	r3, r3, #1
 1417 000a 9360     		str	r3, [r2, #8]
1631:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1632:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Get tick */
1633:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   tickstart = HAL_GetTick ();
 1418              		.loc 1 1633 3 view .LVU298
 1419              		.loc 1 1633 15 is_stmt 0 view .LVU299
 1420 000c FFF7FEFF 		bl	HAL_GetTick
 1421              	.LVL63:
 1422 0010 0446     		mov	r4, r0
 1423              	.LVL64:
1634:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1635:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Wait till Backup regulator ready flag is set */
1636:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   while (__HAL_PWR_GET_FLAG (PWR_FLAG_BRR) == 0U)
 1424              		.loc 1 1636 3 is_stmt 1 view .LVU300
 1425              	.L119:
 1426              		.loc 1 1636 44 view .LVU301
 1427              		.loc 1 1636 10 is_stmt 0 view .LVU302
 1428 0012 074B     		ldr	r3, .L125
 1429 0014 9B68     		ldr	r3, [r3, #8]
 1430              		.loc 1 1636 44 view .LVU303
 1431 0016 13F4803F 		tst	r3, #65536
 1432 001a 07D1     		bne	.L124
1637:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
1638:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY)
 1433              		.loc 1 1638 5 is_stmt 1 view .LVU304
 1434              		.loc 1 1638 10 is_stmt 0 view .LVU305
 1435 001c FFF7FEFF 		bl	HAL_GetTick
 1436              	.LVL65:
 1437              		.loc 1 1638 24 discriminator 1 view .LVU306
 1438 0020 001B     		subs	r0, r0, r4
 1439              		.loc 1 1638 8 discriminator 1 view .LVU307
 1440 0022 B0F57A7F 		cmp	r0, #1000
 1441 0026 F4D9     		bls	.L119
1639:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     {
1640:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       return HAL_ERROR;
 1442              		.loc 1 1640 14 view .LVU308
 1443 0028 0120     		movs	r0, #1
 1444 002a 00E0     		b	.L120
 1445              	.L124:
1641:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     }
1642:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
1643:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1644:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   return HAL_OK;
 1446              		.loc 1 1644 10 view .LVU309
 1447 002c 0020     		movs	r0, #0
 1448              	.L120:
1645:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
 1449              		.loc 1 1645 1 view .LVU310
 1450 002e 10BD     		pop	{r4, pc}
 1451              	.LVL66:
 1452              	.L126:
 1453              		.loc 1 1645 1 view .LVU311
 1454              		.align	2
 1455              	.L125:
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 75


 1456 0030 00480258 		.word	1476544512
 1457              		.cfi_endproc
 1458              	.LFE361:
 1460              		.section	.text.HAL_PWREx_DisableBkUpReg,"ax",%progbits
 1461              		.align	1
 1462              		.global	HAL_PWREx_DisableBkUpReg
 1463              		.syntax unified
 1464              		.thumb
 1465              		.thumb_func
 1467              	HAL_PWREx_DisableBkUpReg:
 1468              	.LFB362:
1646:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1647:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
1648:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief Disable the Backup Regulator.
1649:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @retval HAL status.
1650:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
1651:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg (void)
1652:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
 1469              		.loc 1 1652 1 is_stmt 1 view -0
 1470              		.cfi_startproc
 1471              		@ args = 0, pretend = 0, frame = 0
 1472              		@ frame_needed = 0, uses_anonymous_args = 0
 1473 0000 10B5     		push	{r4, lr}
 1474              		.cfi_def_cfa_offset 8
 1475              		.cfi_offset 4, -8
 1476              		.cfi_offset 14, -4
1653:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   uint32_t tickstart;
 1477              		.loc 1 1653 3 view .LVU313
1654:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1655:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Disable the Backup regulator */
1656:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   CLEAR_BIT (PWR->CR2, PWR_CR2_BREN);
 1478              		.loc 1 1656 3 view .LVU314
 1479 0002 0B4A     		ldr	r2, .L134
 1480 0004 9368     		ldr	r3, [r2, #8]
 1481 0006 23F00103 		bic	r3, r3, #1
 1482 000a 9360     		str	r3, [r2, #8]
1657:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1658:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Get tick */
1659:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   tickstart = HAL_GetTick ();
 1483              		.loc 1 1659 3 view .LVU315
 1484              		.loc 1 1659 15 is_stmt 0 view .LVU316
 1485 000c FFF7FEFF 		bl	HAL_GetTick
 1486              	.LVL67:
 1487 0010 0446     		mov	r4, r0
 1488              	.LVL68:
1660:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1661:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Wait till Backup regulator ready flag is reset */
1662:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   while (__HAL_PWR_GET_FLAG (PWR_FLAG_BRR) != 0U)
 1489              		.loc 1 1662 3 is_stmt 1 view .LVU317
 1490              	.L128:
 1491              		.loc 1 1662 44 view .LVU318
 1492              		.loc 1 1662 10 is_stmt 0 view .LVU319
 1493 0012 074B     		ldr	r3, .L134
 1494 0014 9B68     		ldr	r3, [r3, #8]
 1495              		.loc 1 1662 44 view .LVU320
 1496 0016 13F4803F 		tst	r3, #65536
 1497 001a 07D0     		beq	.L133
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 76


1663:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
1664:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY)
 1498              		.loc 1 1664 5 is_stmt 1 view .LVU321
 1499              		.loc 1 1664 10 is_stmt 0 view .LVU322
 1500 001c FFF7FEFF 		bl	HAL_GetTick
 1501              	.LVL69:
 1502              		.loc 1 1664 24 discriminator 1 view .LVU323
 1503 0020 001B     		subs	r0, r0, r4
 1504              		.loc 1 1664 8 discriminator 1 view .LVU324
 1505 0022 B0F57A7F 		cmp	r0, #1000
 1506 0026 F4D9     		bls	.L128
1665:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     {
1666:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       return HAL_ERROR;
 1507              		.loc 1 1666 14 view .LVU325
 1508 0028 0120     		movs	r0, #1
 1509 002a 00E0     		b	.L129
 1510              	.L133:
1667:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     }
1668:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
1669:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1670:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   return HAL_OK;
 1511              		.loc 1 1670 10 view .LVU326
 1512 002c 0020     		movs	r0, #0
 1513              	.L129:
1671:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
 1514              		.loc 1 1671 1 view .LVU327
 1515 002e 10BD     		pop	{r4, pc}
 1516              	.LVL70:
 1517              	.L135:
 1518              		.loc 1 1671 1 view .LVU328
 1519              		.align	2
 1520              	.L134:
 1521 0030 00480258 		.word	1476544512
 1522              		.cfi_endproc
 1523              	.LFE362:
 1525              		.section	.text.HAL_PWREx_EnableUSBReg,"ax",%progbits
 1526              		.align	1
 1527              		.global	HAL_PWREx_EnableUSBReg
 1528              		.syntax unified
 1529              		.thumb
 1530              		.thumb_func
 1532              	HAL_PWREx_EnableUSBReg:
 1533              	.LFB363:
1672:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1673:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
1674:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief Enable the USB Regulator.
1675:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @retval HAL status.
1676:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
1677:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_EnableUSBReg (void)
1678:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
 1534              		.loc 1 1678 1 is_stmt 1 view -0
 1535              		.cfi_startproc
 1536              		@ args = 0, pretend = 0, frame = 0
 1537              		@ frame_needed = 0, uses_anonymous_args = 0
 1538 0000 10B5     		push	{r4, lr}
 1539              		.cfi_def_cfa_offset 8
 1540              		.cfi_offset 4, -8
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 77


 1541              		.cfi_offset 14, -4
1679:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   uint32_t tickstart;
 1542              		.loc 1 1679 3 view .LVU330
1680:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1681:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Enable the USB regulator */
1682:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   SET_BIT (PWR->CR3, PWR_CR3_USBREGEN);
 1543              		.loc 1 1682 3 view .LVU331
 1544 0002 0B4A     		ldr	r2, .L143
 1545 0004 D368     		ldr	r3, [r2, #12]
 1546 0006 43F00073 		orr	r3, r3, #33554432
 1547 000a D360     		str	r3, [r2, #12]
1683:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1684:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Get tick */
1685:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   tickstart = HAL_GetTick ();
 1548              		.loc 1 1685 3 view .LVU332
 1549              		.loc 1 1685 15 is_stmt 0 view .LVU333
 1550 000c FFF7FEFF 		bl	HAL_GetTick
 1551              	.LVL71:
 1552 0010 0446     		mov	r4, r0
 1553              	.LVL72:
1686:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1687:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Wait till the USB regulator ready flag is set */
1688:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   while (__HAL_PWR_GET_FLAG (PWR_FLAG_USB33RDY) == 0U)
 1554              		.loc 1 1688 3 is_stmt 1 view .LVU334
 1555              	.L137:
 1556              		.loc 1 1688 49 view .LVU335
 1557              		.loc 1 1688 10 is_stmt 0 view .LVU336
 1558 0012 074B     		ldr	r3, .L143
 1559 0014 DB68     		ldr	r3, [r3, #12]
 1560              		.loc 1 1688 49 view .LVU337
 1561 0016 13F0806F 		tst	r3, #67108864
 1562 001a 07D1     		bne	.L142
1689:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
1690:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY)
 1563              		.loc 1 1690 5 is_stmt 1 view .LVU338
 1564              		.loc 1 1690 10 is_stmt 0 view .LVU339
 1565 001c FFF7FEFF 		bl	HAL_GetTick
 1566              	.LVL73:
 1567              		.loc 1 1690 24 discriminator 1 view .LVU340
 1568 0020 001B     		subs	r0, r0, r4
 1569              		.loc 1 1690 8 discriminator 1 view .LVU341
 1570 0022 B0F57A7F 		cmp	r0, #1000
 1571 0026 F4D9     		bls	.L137
1691:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     {
1692:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       return HAL_ERROR;
 1572              		.loc 1 1692 14 view .LVU342
 1573 0028 0120     		movs	r0, #1
 1574 002a 00E0     		b	.L138
 1575              	.L142:
1693:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     }
1694:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
1695:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1696:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   return HAL_OK;
 1576              		.loc 1 1696 10 view .LVU343
 1577 002c 0020     		movs	r0, #0
 1578              	.L138:
1697:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 78


 1579              		.loc 1 1697 1 view .LVU344
 1580 002e 10BD     		pop	{r4, pc}
 1581              	.LVL74:
 1582              	.L144:
 1583              		.loc 1 1697 1 view .LVU345
 1584              		.align	2
 1585              	.L143:
 1586 0030 00480258 		.word	1476544512
 1587              		.cfi_endproc
 1588              	.LFE363:
 1590              		.section	.text.HAL_PWREx_DisableUSBReg,"ax",%progbits
 1591              		.align	1
 1592              		.global	HAL_PWREx_DisableUSBReg
 1593              		.syntax unified
 1594              		.thumb
 1595              		.thumb_func
 1597              	HAL_PWREx_DisableUSBReg:
 1598              	.LFB364:
1698:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1699:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
1700:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief Disable the USB Regulator.
1701:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @retval HAL status.
1702:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
1703:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** HAL_StatusTypeDef HAL_PWREx_DisableUSBReg (void)
1704:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
 1599              		.loc 1 1704 1 is_stmt 1 view -0
 1600              		.cfi_startproc
 1601              		@ args = 0, pretend = 0, frame = 0
 1602              		@ frame_needed = 0, uses_anonymous_args = 0
 1603 0000 10B5     		push	{r4, lr}
 1604              		.cfi_def_cfa_offset 8
 1605              		.cfi_offset 4, -8
 1606              		.cfi_offset 14, -4
1705:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   uint32_t tickstart;
 1607              		.loc 1 1705 3 view .LVU347
1706:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1707:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Disable the USB regulator */
1708:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   CLEAR_BIT (PWR->CR3, PWR_CR3_USBREGEN);
 1608              		.loc 1 1708 3 view .LVU348
 1609 0002 0B4A     		ldr	r2, .L152
 1610 0004 D368     		ldr	r3, [r2, #12]
 1611 0006 23F00073 		bic	r3, r3, #33554432
 1612 000a D360     		str	r3, [r2, #12]
1709:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1710:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Get tick */
1711:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   tickstart = HAL_GetTick ();
 1613              		.loc 1 1711 3 view .LVU349
 1614              		.loc 1 1711 15 is_stmt 0 view .LVU350
 1615 000c FFF7FEFF 		bl	HAL_GetTick
 1616              	.LVL75:
 1617 0010 0446     		mov	r4, r0
 1618              	.LVL76:
1712:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1713:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Wait till the USB regulator ready flag is reset */
1714:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   while(__HAL_PWR_GET_FLAG (PWR_FLAG_USB33RDY) != 0U)
 1619              		.loc 1 1714 3 is_stmt 1 view .LVU351
 1620              	.L146:
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 79


 1621              		.loc 1 1714 48 view .LVU352
 1622              		.loc 1 1714 9 is_stmt 0 view .LVU353
 1623 0012 074B     		ldr	r3, .L152
 1624 0014 DB68     		ldr	r3, [r3, #12]
 1625              		.loc 1 1714 48 view .LVU354
 1626 0016 13F0806F 		tst	r3, #67108864
 1627 001a 07D0     		beq	.L151
1715:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
1716:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     if ((HAL_GetTick() - tickstart ) > PWR_FLAG_SETTING_DELAY)
 1628              		.loc 1 1716 5 is_stmt 1 view .LVU355
 1629              		.loc 1 1716 10 is_stmt 0 view .LVU356
 1630 001c FFF7FEFF 		bl	HAL_GetTick
 1631              	.LVL77:
 1632              		.loc 1 1716 24 discriminator 1 view .LVU357
 1633 0020 001B     		subs	r0, r0, r4
 1634              		.loc 1 1716 8 discriminator 1 view .LVU358
 1635 0022 B0F57A7F 		cmp	r0, #1000
 1636 0026 F4D9     		bls	.L146
1717:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     {
1718:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       return HAL_ERROR;
 1637              		.loc 1 1718 14 view .LVU359
 1638 0028 0120     		movs	r0, #1
 1639 002a 00E0     		b	.L147
 1640              	.L151:
1719:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     }
1720:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
1721:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1722:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   return HAL_OK;
 1641              		.loc 1 1722 10 view .LVU360
 1642 002c 0020     		movs	r0, #0
 1643              	.L147:
1723:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
 1644              		.loc 1 1723 1 view .LVU361
 1645 002e 10BD     		pop	{r4, pc}
 1646              	.LVL78:
 1647              	.L153:
 1648              		.loc 1 1723 1 view .LVU362
 1649              		.align	2
 1650              	.L152:
 1651 0030 00480258 		.word	1476544512
 1652              		.cfi_endproc
 1653              	.LFE364:
 1655              		.section	.text.HAL_PWREx_EnableUSBVoltageDetector,"ax",%progbits
 1656              		.align	1
 1657              		.global	HAL_PWREx_EnableUSBVoltageDetector
 1658              		.syntax unified
 1659              		.thumb
 1660              		.thumb_func
 1662              	HAL_PWREx_EnableUSBVoltageDetector:
 1663              	.LFB365:
1724:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1725:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
1726:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief Enable the USB voltage level detector.
1727:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @retval None.
1728:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
1729:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_EnableUSBVoltageDetector (void)
1730:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 80


 1664              		.loc 1 1730 1 is_stmt 1 view -0
 1665              		.cfi_startproc
 1666              		@ args = 0, pretend = 0, frame = 0
 1667              		@ frame_needed = 0, uses_anonymous_args = 0
 1668              		@ link register save eliminated.
1731:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Enable the USB voltage detector */
1732:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   SET_BIT (PWR->CR3, PWR_CR3_USB33DEN);
 1669              		.loc 1 1732 3 view .LVU364
 1670 0000 024A     		ldr	r2, .L155
 1671 0002 D368     		ldr	r3, [r2, #12]
 1672 0004 43F08073 		orr	r3, r3, #16777216
 1673 0008 D360     		str	r3, [r2, #12]
1733:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
 1674              		.loc 1 1733 1 is_stmt 0 view .LVU365
 1675 000a 7047     		bx	lr
 1676              	.L156:
 1677              		.align	2
 1678              	.L155:
 1679 000c 00480258 		.word	1476544512
 1680              		.cfi_endproc
 1681              	.LFE365:
 1683              		.section	.text.HAL_PWREx_DisableUSBVoltageDetector,"ax",%progbits
 1684              		.align	1
 1685              		.global	HAL_PWREx_DisableUSBVoltageDetector
 1686              		.syntax unified
 1687              		.thumb
 1688              		.thumb_func
 1690              	HAL_PWREx_DisableUSBVoltageDetector:
 1691              	.LFB366:
1734:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1735:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
1736:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief Disable the USB voltage level detector.
1737:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @retval None.
1738:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
1739:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_DisableUSBVoltageDetector (void)
1740:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
 1692              		.loc 1 1740 1 is_stmt 1 view -0
 1693              		.cfi_startproc
 1694              		@ args = 0, pretend = 0, frame = 0
 1695              		@ frame_needed = 0, uses_anonymous_args = 0
 1696              		@ link register save eliminated.
1741:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Disable the USB voltage detector */
1742:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   CLEAR_BIT (PWR->CR3, PWR_CR3_USB33DEN);
 1697              		.loc 1 1742 3 view .LVU367
 1698 0000 024A     		ldr	r2, .L158
 1699 0002 D368     		ldr	r3, [r2, #12]
 1700 0004 23F08073 		bic	r3, r3, #16777216
 1701 0008 D360     		str	r3, [r2, #12]
1743:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
 1702              		.loc 1 1743 1 is_stmt 0 view .LVU368
 1703 000a 7047     		bx	lr
 1704              	.L159:
 1705              		.align	2
 1706              	.L158:
 1707 000c 00480258 		.word	1476544512
 1708              		.cfi_endproc
 1709              	.LFE366:
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 81


 1711              		.section	.text.HAL_PWREx_EnableBatteryCharging,"ax",%progbits
 1712              		.align	1
 1713              		.global	HAL_PWREx_EnableBatteryCharging
 1714              		.syntax unified
 1715              		.thumb
 1716              		.thumb_func
 1718              	HAL_PWREx_EnableBatteryCharging:
 1719              	.LVL79:
 1720              	.LFB367:
1744:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1745:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
1746:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief Enable the Battery charging.
1747:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @note   When VDD is present, charge the external battery through an internal
1748:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         resistor.
1749:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @param  ResistorValue : Specifies the charging resistor.
1750:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *          This parameter can be one of the following values :
1751:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_BATTERY_CHARGING_RESISTOR_5 : 5 KOhm resistor.
1752:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *            @arg PWR_BATTERY_CHARGING_RESISTOR_1_5 : 1.5 KOhm resistor.
1753:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @retval None.
1754:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
1755:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_EnableBatteryCharging (uint32_t ResistorValue)
1756:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
 1721              		.loc 1 1756 1 is_stmt 1 view -0
 1722              		.cfi_startproc
 1723              		@ args = 0, pretend = 0, frame = 0
 1724              		@ frame_needed = 0, uses_anonymous_args = 0
 1725              		@ link register save eliminated.
1757:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Check the parameter */
1758:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   assert_param (IS_PWR_BATTERY_RESISTOR_SELECT (ResistorValue));
 1726              		.loc 1 1758 3 view .LVU370
1759:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1760:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Specify the charging resistor */
1761:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   MODIFY_REG (PWR->CR3, PWR_CR3_VBRS, ResistorValue);
 1727              		.loc 1 1761 3 view .LVU371
 1728 0000 054A     		ldr	r2, .L161
 1729 0002 D368     		ldr	r3, [r2, #12]
 1730 0004 23F40073 		bic	r3, r3, #512
 1731 0008 0343     		orrs	r3, r3, r0
 1732 000a D360     		str	r3, [r2, #12]
1762:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1763:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Enable the Battery charging */
1764:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   SET_BIT (PWR->CR3, PWR_CR3_VBE);
 1733              		.loc 1 1764 3 view .LVU372
 1734 000c D368     		ldr	r3, [r2, #12]
 1735 000e 43F48073 		orr	r3, r3, #256
 1736 0012 D360     		str	r3, [r2, #12]
1765:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
 1737              		.loc 1 1765 1 is_stmt 0 view .LVU373
 1738 0014 7047     		bx	lr
 1739              	.L162:
 1740 0016 00BF     		.align	2
 1741              	.L161:
 1742 0018 00480258 		.word	1476544512
 1743              		.cfi_endproc
 1744              	.LFE367:
 1746              		.section	.text.HAL_PWREx_DisableBatteryCharging,"ax",%progbits
 1747              		.align	1
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 82


 1748              		.global	HAL_PWREx_DisableBatteryCharging
 1749              		.syntax unified
 1750              		.thumb
 1751              		.thumb_func
 1753              	HAL_PWREx_DisableBatteryCharging:
 1754              	.LFB368:
1766:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1767:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
1768:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief Disable the Battery charging.
1769:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @retval None.
1770:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
1771:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_DisableBatteryCharging (void)
1772:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
 1755              		.loc 1 1772 1 is_stmt 1 view -0
 1756              		.cfi_startproc
 1757              		@ args = 0, pretend = 0, frame = 0
 1758              		@ frame_needed = 0, uses_anonymous_args = 0
 1759              		@ link register save eliminated.
1773:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Disable the Battery charging */
1774:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   CLEAR_BIT (PWR->CR3, PWR_CR3_VBE);
 1760              		.loc 1 1774 3 view .LVU375
 1761 0000 024A     		ldr	r2, .L164
 1762 0002 D368     		ldr	r3, [r2, #12]
 1763 0004 23F48073 		bic	r3, r3, #256
 1764 0008 D360     		str	r3, [r2, #12]
1775:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
 1765              		.loc 1 1775 1 is_stmt 0 view .LVU376
 1766 000a 7047     		bx	lr
 1767              	.L165:
 1768              		.align	2
 1769              	.L164:
 1770 000c 00480258 		.word	1476544512
 1771              		.cfi_endproc
 1772              	.LFE368:
 1774              		.section	.text.HAL_PWREx_EnableAnalogBooster,"ax",%progbits
 1775              		.align	1
 1776              		.global	HAL_PWREx_EnableAnalogBooster
 1777              		.syntax unified
 1778              		.thumb
 1779              		.thumb_func
 1781              	HAL_PWREx_EnableAnalogBooster:
 1782              	.LFB369:
1776:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1777:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (PWR_CR1_BOOSTE)
1778:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
1779:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief Enable the booster to guarantee the analog switch AC performance when
1780:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *        the VDD supply voltage is below 2V7.
1781:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @note   The VDD supply voltage can be monitored through the PVD and the PLS
1782:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         field bits.
1783:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @retval None.
1784:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
1785:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_EnableAnalogBooster (void)
1786:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
 1783              		.loc 1 1786 1 is_stmt 1 view -0
 1784              		.cfi_startproc
 1785              		@ args = 0, pretend = 0, frame = 0
 1786              		@ frame_needed = 0, uses_anonymous_args = 0
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 83


 1787              		@ link register save eliminated.
1787:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Enable the Analog voltage */
1788:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   SET_BIT (PWR->CR1, PWR_CR1_AVD_READY);
 1788              		.loc 1 1788 3 view .LVU378
 1789 0000 044B     		ldr	r3, .L167
 1790 0002 1A68     		ldr	r2, [r3]
 1791 0004 42F40052 		orr	r2, r2, #8192
 1792 0008 1A60     		str	r2, [r3]
1789:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1790:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Enable VDDA booster */
1791:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   SET_BIT (PWR->CR1, PWR_CR1_BOOSTE);
 1793              		.loc 1 1791 3 view .LVU379
 1794 000a 1A68     		ldr	r2, [r3]
 1795 000c 42F48052 		orr	r2, r2, #4096
 1796 0010 1A60     		str	r2, [r3]
1792:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
 1797              		.loc 1 1792 1 is_stmt 0 view .LVU380
 1798 0012 7047     		bx	lr
 1799              	.L168:
 1800              		.align	2
 1801              	.L167:
 1802 0014 00480258 		.word	1476544512
 1803              		.cfi_endproc
 1804              	.LFE369:
 1806              		.section	.text.HAL_PWREx_DisableAnalogBooster,"ax",%progbits
 1807              		.align	1
 1808              		.global	HAL_PWREx_DisableAnalogBooster
 1809              		.syntax unified
 1810              		.thumb
 1811              		.thumb_func
 1813              	HAL_PWREx_DisableAnalogBooster:
 1814              	.LFB370:
1793:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1794:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
1795:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief Disable the analog booster.
1796:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @retval None.
1797:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
1798:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_DisableAnalogBooster (void)
1799:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
 1815              		.loc 1 1799 1 is_stmt 1 view -0
 1816              		.cfi_startproc
 1817              		@ args = 0, pretend = 0, frame = 0
 1818              		@ frame_needed = 0, uses_anonymous_args = 0
 1819              		@ link register save eliminated.
1800:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Disable VDDA booster */
1801:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   CLEAR_BIT (PWR->CR1, PWR_CR1_BOOSTE);
 1820              		.loc 1 1801 3 view .LVU382
 1821 0000 044B     		ldr	r3, .L170
 1822 0002 1A68     		ldr	r2, [r3]
 1823 0004 22F48052 		bic	r2, r2, #4096
 1824 0008 1A60     		str	r2, [r3]
1802:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1803:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Disable the Analog voltage */
1804:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   CLEAR_BIT (PWR->CR1, PWR_CR1_AVD_READY);
 1825              		.loc 1 1804 3 view .LVU383
 1826 000a 1A68     		ldr	r2, [r3]
 1827 000c 22F40052 		bic	r2, r2, #8192
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 84


 1828 0010 1A60     		str	r2, [r3]
1805:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
 1829              		.loc 1 1805 1 is_stmt 0 view .LVU384
 1830 0012 7047     		bx	lr
 1831              	.L171:
 1832              		.align	2
 1833              	.L170:
 1834 0014 00480258 		.word	1476544512
 1835              		.cfi_endproc
 1836              	.LFE370:
 1838              		.section	.text.HAL_PWREx_EnableMonitoring,"ax",%progbits
 1839              		.align	1
 1840              		.global	HAL_PWREx_EnableMonitoring
 1841              		.syntax unified
 1842              		.thumb
 1843              		.thumb_func
 1845              	HAL_PWREx_EnableMonitoring:
 1846              	.LFB371:
1806:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (PWR_CR1_BOOSTE) */
1807:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
1808:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @}
1809:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
1810:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1811:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /** @defgroup PWREx_Exported_Functions_Group4 Power Monitoring functions
1812:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief    Power Monitoring functions
1813:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *
1814:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** @verbatim
1815:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****  ===============================================================================
1816:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****                  ##### Power Monitoring functions #####
1817:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****  ===============================================================================
1818:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1819:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     *** VBAT and Temperature supervision ***
1820:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     ========================================
1821:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     [..]
1822:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       (+) The VBAT battery voltage supply can be monitored by comparing it with
1823:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           two threshold levels: VBAThigh and VBATlow. VBATH flag and VBATL flags
1824:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           in the PWR control register 2 (PWR_CR2), indicate if VBAT is higher or
1825:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           lower than the threshold.
1826:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       (+) The temperature can be monitored by comparing it with two threshold
1827:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           levels, TEMPhigh and TEMPlow. TEMPH and TEMPL flags, in the PWR
1828:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           control register 2 (PWR_CR2), indicate whether the device temperature
1829:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           is higher or lower than the threshold.
1830:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       (+) The VBAT and the temperature monitoring is enabled by
1831:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           HAL_PWREx_EnableMonitoring() function and disabled by
1832:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           HAL_PWREx_DisableMonitoring() function.
1833:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       (+) The HAL_PWREx_GetVBATLevel() function returns the VBAT level which can
1834:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           be : PWR_VBAT_BELOW_LOW_THRESHOLD or PWR_VBAT_ABOVE_HIGH_THRESHOLD or
1835:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD.
1836:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       (+) The HAL_PWREx_GetTemperatureLevel() function returns the Temperature
1837:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           level which can be :
1838:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           PWR_TEMP_BELOW_LOW_THRESHOLD or PWR_TEMP_ABOVE_HIGH_THRESHOLD or
1839:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD.
1840:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1841:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     *** AVD configuration ***
1842:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     =========================
1843:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     [..]
1844:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       (+) The AVD is used to monitor the VDDA power supply by comparing it to a
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 85


1845:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           threshold selected by the AVD Level (ALS[3:0] bits in the PWR_CR1
1846:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           register).
1847:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       (+) A AVDO flag is available to indicate if VDDA is higher or lower
1848:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           than the AVD threshold. This event is internally connected to the EXTI
1849:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           line 16 to generate an interrupt if enabled.
1850:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           It is configurable through __HAL_PWR_AVD_EXTI_ENABLE_IT() macro.
1851:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       (+) The AVD is stopped in System Standby mode.
1852:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1853:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** @endverbatim
1854:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @{
1855:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
1856:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1857:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
1858:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief Enable the VBAT and temperature monitoring.
1859:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @retval HAL status.
1860:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
1861:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_EnableMonitoring (void)
1862:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
 1847              		.loc 1 1862 1 is_stmt 1 view -0
 1848              		.cfi_startproc
 1849              		@ args = 0, pretend = 0, frame = 0
 1850              		@ frame_needed = 0, uses_anonymous_args = 0
 1851              		@ link register save eliminated.
1863:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Enable the VBAT and Temperature monitoring */
1864:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   SET_BIT (PWR->CR2, PWR_CR2_MONEN);
 1852              		.loc 1 1864 3 view .LVU386
 1853 0000 024A     		ldr	r2, .L173
 1854 0002 9368     		ldr	r3, [r2, #8]
 1855 0004 43F01003 		orr	r3, r3, #16
 1856 0008 9360     		str	r3, [r2, #8]
1865:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
 1857              		.loc 1 1865 1 is_stmt 0 view .LVU387
 1858 000a 7047     		bx	lr
 1859              	.L174:
 1860              		.align	2
 1861              	.L173:
 1862 000c 00480258 		.word	1476544512
 1863              		.cfi_endproc
 1864              	.LFE371:
 1866              		.section	.text.HAL_PWREx_DisableMonitoring,"ax",%progbits
 1867              		.align	1
 1868              		.global	HAL_PWREx_DisableMonitoring
 1869              		.syntax unified
 1870              		.thumb
 1871              		.thumb_func
 1873              	HAL_PWREx_DisableMonitoring:
 1874              	.LFB372:
1866:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1867:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
1868:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief Disable the VBAT and temperature monitoring.
1869:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @retval HAL status.
1870:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
1871:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_DisableMonitoring (void)
1872:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
 1875              		.loc 1 1872 1 is_stmt 1 view -0
 1876              		.cfi_startproc
 1877              		@ args = 0, pretend = 0, frame = 0
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 86


 1878              		@ frame_needed = 0, uses_anonymous_args = 0
 1879              		@ link register save eliminated.
1873:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Disable the VBAT and Temperature monitoring */
1874:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   CLEAR_BIT (PWR->CR2, PWR_CR2_MONEN);
 1880              		.loc 1 1874 3 view .LVU389
 1881 0000 024A     		ldr	r2, .L176
 1882 0002 9368     		ldr	r3, [r2, #8]
 1883 0004 23F01003 		bic	r3, r3, #16
 1884 0008 9360     		str	r3, [r2, #8]
1875:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
 1885              		.loc 1 1875 1 is_stmt 0 view .LVU390
 1886 000a 7047     		bx	lr
 1887              	.L177:
 1888              		.align	2
 1889              	.L176:
 1890 000c 00480258 		.word	1476544512
 1891              		.cfi_endproc
 1892              	.LFE372:
 1894              		.section	.text.HAL_PWREx_GetTemperatureLevel,"ax",%progbits
 1895              		.align	1
 1896              		.global	HAL_PWREx_GetTemperatureLevel
 1897              		.syntax unified
 1898              		.thumb
 1899              		.thumb_func
 1901              	HAL_PWREx_GetTemperatureLevel:
 1902              	.LFB373:
1876:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1877:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
1878:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief Indicate whether the junction temperature is between, above or below
1879:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *        the thresholds.
1880:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @retval Temperature level.
1881:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
1882:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** uint32_t HAL_PWREx_GetTemperatureLevel (void)
1883:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
 1903              		.loc 1 1883 1 is_stmt 1 view -0
 1904              		.cfi_startproc
 1905              		@ args = 0, pretend = 0, frame = 0
 1906              		@ frame_needed = 0, uses_anonymous_args = 0
 1907              		@ link register save eliminated.
1884:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   uint32_t tempLevel, regValue;
 1908              		.loc 1 1884 3 view .LVU392
1885:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1886:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Read the temperature flags */
1887:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   regValue = READ_BIT (PWR->CR2, (PWR_CR2_TEMPH | PWR_CR2_TEMPL));
 1909              		.loc 1 1887 3 view .LVU393
 1910              		.loc 1 1887 14 is_stmt 0 view .LVU394
 1911 0000 054B     		ldr	r3, .L181
 1912 0002 9868     		ldr	r0, [r3, #8]
 1913              		.loc 1 1887 12 view .LVU395
 1914 0004 00F44000 		and	r0, r0, #12582912
 1915              	.LVL80:
1888:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1889:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Check if the temperature is below the threshold */
1890:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   if (regValue == PWR_CR2_TEMPL)
 1916              		.loc 1 1890 3 is_stmt 1 view .LVU396
 1917              		.loc 1 1890 6 is_stmt 0 view .LVU397
 1918 0008 B0F5800F 		cmp	r0, #4194304
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 87


 1919 000c 03D0     		beq	.L178
1891:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
1892:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     tempLevel = PWR_TEMP_BELOW_LOW_THRESHOLD;
1893:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
1894:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Check if the temperature is above the threshold */
1895:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   else if (regValue == PWR_CR2_TEMPH)
 1920              		.loc 1 1895 8 is_stmt 1 view .LVU398
 1921              		.loc 1 1895 11 is_stmt 0 view .LVU399
 1922 000e B0F5000F 		cmp	r0, #8388608
 1923 0012 00D0     		beq	.L178
1896:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
1897:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     tempLevel = PWR_TEMP_ABOVE_HIGH_THRESHOLD;
1898:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
1899:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* The temperature is between the thresholds */
1900:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   else
1901:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
1902:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     tempLevel = PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD;
 1924              		.loc 1 1902 15 view .LVU400
 1925 0014 0020     		movs	r0, #0
 1926              	.LVL81:
1903:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
1904:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1905:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   return tempLevel;
 1927              		.loc 1 1905 3 is_stmt 1 view .LVU401
 1928              	.L178:
1906:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
 1929              		.loc 1 1906 1 is_stmt 0 view .LVU402
 1930 0016 7047     		bx	lr
 1931              	.L182:
 1932              		.align	2
 1933              	.L181:
 1934 0018 00480258 		.word	1476544512
 1935              		.cfi_endproc
 1936              	.LFE373:
 1938              		.section	.text.HAL_PWREx_GetVBATLevel,"ax",%progbits
 1939              		.align	1
 1940              		.global	HAL_PWREx_GetVBATLevel
 1941              		.syntax unified
 1942              		.thumb
 1943              		.thumb_func
 1945              	HAL_PWREx_GetVBATLevel:
 1946              	.LFB374:
1907:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1908:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
1909:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief Indicate whether the Battery voltage level is between, above or below
1910:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *        the thresholds.
1911:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @retval VBAT level.
1912:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
1913:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** uint32_t HAL_PWREx_GetVBATLevel (void)
1914:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
 1947              		.loc 1 1914 1 is_stmt 1 view -0
 1948              		.cfi_startproc
 1949              		@ args = 0, pretend = 0, frame = 0
 1950              		@ frame_needed = 0, uses_anonymous_args = 0
 1951              		@ link register save eliminated.
1915:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   uint32_t VBATLevel, regValue;
 1952              		.loc 1 1915 3 view .LVU404
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 88


1916:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1917:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Read the VBAT flags */
1918:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   regValue = READ_BIT (PWR->CR2, (PWR_CR2_VBATH | PWR_CR2_VBATL));
 1953              		.loc 1 1918 3 view .LVU405
 1954              		.loc 1 1918 14 is_stmt 0 view .LVU406
 1955 0000 054B     		ldr	r3, .L186
 1956 0002 9868     		ldr	r0, [r3, #8]
 1957              		.loc 1 1918 12 view .LVU407
 1958 0004 00F44010 		and	r0, r0, #3145728
 1959              	.LVL82:
1919:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1920:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Check if the VBAT is below the threshold */
1921:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   if (regValue == PWR_CR2_VBATL)
 1960              		.loc 1 1921 3 is_stmt 1 view .LVU408
 1961              		.loc 1 1921 6 is_stmt 0 view .LVU409
 1962 0008 B0F5801F 		cmp	r0, #1048576
 1963 000c 03D0     		beq	.L183
1922:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
1923:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     VBATLevel = PWR_VBAT_BELOW_LOW_THRESHOLD;
1924:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
1925:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Check if the VBAT is above the threshold */
1926:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   else if (regValue == PWR_CR2_VBATH)
 1964              		.loc 1 1926 8 is_stmt 1 view .LVU410
 1965              		.loc 1 1926 11 is_stmt 0 view .LVU411
 1966 000e B0F5001F 		cmp	r0, #2097152
 1967 0012 00D0     		beq	.L183
1927:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
1928:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     VBATLevel = PWR_VBAT_ABOVE_HIGH_THRESHOLD;
1929:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
1930:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* The VBAT is between the thresholds */
1931:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   else
1932:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
1933:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     VBATLevel = PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD;
 1968              		.loc 1 1933 15 view .LVU412
 1969 0014 0020     		movs	r0, #0
 1970              	.LVL83:
1934:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
1935:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1936:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   return VBATLevel;
 1971              		.loc 1 1936 3 is_stmt 1 view .LVU413
 1972              	.L183:
1937:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
 1973              		.loc 1 1937 1 is_stmt 0 view .LVU414
 1974 0016 7047     		bx	lr
 1975              	.L187:
 1976              		.align	2
 1977              	.L186:
 1978 0018 00480258 		.word	1476544512
 1979              		.cfi_endproc
 1980              	.LFE374:
 1982              		.section	.text.HAL_PWREx_GetMMCVoltage,"ax",%progbits
 1983              		.align	1
 1984              		.global	HAL_PWREx_GetMMCVoltage
 1985              		.syntax unified
 1986              		.thumb
 1987              		.thumb_func
 1989              	HAL_PWREx_GetMMCVoltage:
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 89


 1990              	.LFB375:
1938:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1939:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (PWR_CSR1_MMCVDO)
1940:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
1941:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief Get the VDDMMC voltage level.
1942:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @retval The VDDMMC voltage level.
1943:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
1944:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** PWREx_MMC_VoltageLevel HAL_PWREx_GetMMCVoltage (void)
1945:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
 1991              		.loc 1 1945 1 is_stmt 1 view -0
 1992              		.cfi_startproc
 1993              		@ args = 0, pretend = 0, frame = 0
 1994              		@ frame_needed = 0, uses_anonymous_args = 0
 1995              		@ link register save eliminated.
1946:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   PWREx_MMC_VoltageLevel mmc_voltage;
 1996              		.loc 1 1946 3 view .LVU416
1947:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1948:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Check voltage detector output on VDDMMC value */
1949:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   if ((PWR->CSR1 & PWR_CSR1_MMCVDO_Msk) == 0U)
 1997              		.loc 1 1949 3 view .LVU417
 1998              		.loc 1 1949 11 is_stmt 0 view .LVU418
 1999 0000 044B     		ldr	r3, .L191
 2000 0002 5B68     		ldr	r3, [r3, #4]
 2001              		.loc 1 1949 6 view .LVU419
 2002 0004 13F4003F 		tst	r3, #131072
 2003 0008 01D1     		bne	.L190
1950:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
1951:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     mmc_voltage = PWR_MMC_VOLTAGE_BELOW_1V2;
 2004              		.loc 1 1951 17 view .LVU420
 2005 000a 0020     		movs	r0, #0
 2006 000c 7047     		bx	lr
 2007              	.L190:
1952:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
1953:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   else
1954:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
1955:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     mmc_voltage = PWR_MMC_VOLTAGE_EQUAL_ABOVE_1V2;
 2008              		.loc 1 1955 17 view .LVU421
 2009 000e 0120     		movs	r0, #1
 2010              	.LVL84:
1956:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
1957:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1958:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   return mmc_voltage;
 2011              		.loc 1 1958 3 is_stmt 1 view .LVU422
1959:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
 2012              		.loc 1 1959 1 is_stmt 0 view .LVU423
 2013 0010 7047     		bx	lr
 2014              	.L192:
 2015 0012 00BF     		.align	2
 2016              	.L191:
 2017 0014 00480258 		.word	1476544512
 2018              		.cfi_endproc
 2019              	.LFE375:
 2021              		.section	.text.HAL_PWREx_ConfigAVD,"ax",%progbits
 2022              		.align	1
 2023              		.global	HAL_PWREx_ConfigAVD
 2024              		.syntax unified
 2025              		.thumb
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 90


 2026              		.thumb_func
 2028              	HAL_PWREx_ConfigAVD:
 2029              	.LVL85:
 2030              	.LFB376:
1960:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (PWR_CSR1_MMCVDO) */
1961:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1962:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
1963:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief  Configure the event mode and the voltage threshold detected by the
1964:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         Analog Voltage Detector (AVD).
1965:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @param  sConfigAVD : Pointer to an PWREx_AVDTypeDef structure that contains
1966:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *                      the configuration information for the AVD.
1967:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @note   Refer to the electrical characteristics of your device datasheet for
1968:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         more details about the voltage threshold corresponding to each
1969:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         detection level.
1970:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @note   For dual core devices, please ensure to configure the EXTI lines for
1971:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         the different Cortex-Mx through PWR_Exported_Macro provided by this
1972:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         driver. All combination are allowed: wake up only Cortex-M7, wake up
1973:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   *         only Cortex-M4 and wake up Cortex-M7 and Cortex-M4.
1974:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @retval None.
1975:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
1976:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_ConfigAVD (PWREx_AVDTypeDef *sConfigAVD)
1977:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
 2031              		.loc 1 1977 1 is_stmt 1 view -0
 2032              		.cfi_startproc
 2033              		@ args = 0, pretend = 0, frame = 0
 2034              		@ frame_needed = 0, uses_anonymous_args = 0
 2035              		@ link register save eliminated.
1978:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Check the parameters */
1979:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   assert_param (IS_PWR_AVD_LEVEL (sConfigAVD->AVDLevel));
 2036              		.loc 1 1979 3 view .LVU425
1980:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   assert_param (IS_PWR_AVD_MODE (sConfigAVD->Mode));
 2037              		.loc 1 1980 3 view .LVU426
1981:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1982:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Set the ALS[18:17] bits according to AVDLevel value */
1983:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   MODIFY_REG (PWR->CR1, PWR_CR1_ALS, sConfigAVD->AVDLevel);
 2038              		.loc 1 1983 3 view .LVU427
 2039 0000 244A     		ldr	r2, .L198
 2040 0002 1368     		ldr	r3, [r2]
 2041 0004 23F4C023 		bic	r3, r3, #393216
 2042 0008 0168     		ldr	r1, [r0]
 2043 000a 0B43     		orrs	r3, r3, r1
 2044 000c 1360     		str	r3, [r2]
1984:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1985:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Clear any previous config */
1986:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if !defined (DUAL_CORE)
1987:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   __HAL_PWR_AVD_EXTI_DISABLE_EVENT ();
 2045              		.loc 1 1987 3 view .LVU428
 2046 000e 4FF0B043 		mov	r3, #1476395008
 2047 0012 D3F88420 		ldr	r2, [r3, #132]
 2048 0016 22F48032 		bic	r2, r2, #65536
 2049 001a C3F88420 		str	r2, [r3, #132]
1988:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   __HAL_PWR_AVD_EXTI_DISABLE_IT ();
 2050              		.loc 1 1988 3 view .LVU429
 2051 001e D3F88020 		ldr	r2, [r3, #128]
 2052 0022 22F48032 		bic	r2, r2, #65536
 2053 0026 C3F88020 		str	r2, [r3, #128]
1989:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* !defined (DUAL_CORE) */
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 91


1990:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1991:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE ();
 2054              		.loc 1 1991 3 view .LVU430
 2055 002a 1A68     		ldr	r2, [r3]
 2056 002c 22F48032 		bic	r2, r2, #65536
 2057 0030 1A60     		str	r2, [r3]
1992:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE ();
 2058              		.loc 1 1992 3 view .LVU431
 2059 0032 5A68     		ldr	r2, [r3, #4]
 2060 0034 22F48032 		bic	r2, r2, #65536
 2061 0038 5A60     		str	r2, [r3, #4]
1993:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
1994:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if !defined (DUAL_CORE)
1995:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Configure the interrupt mode */
1996:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   if ((sConfigAVD->Mode & AVD_MODE_IT) == AVD_MODE_IT)
 2062              		.loc 1 1996 3 view .LVU432
 2063              		.loc 1 1996 18 is_stmt 0 view .LVU433
 2064 003a 4368     		ldr	r3, [r0, #4]
 2065              		.loc 1 1996 6 view .LVU434
 2066 003c 13F4803F 		tst	r3, #65536
 2067 0040 07D0     		beq	.L194
1997:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
1998:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     __HAL_PWR_AVD_EXTI_ENABLE_IT ();
 2068              		.loc 1 1998 5 is_stmt 1 view .LVU435
 2069 0042 4FF0B042 		mov	r2, #1476395008
 2070 0046 D2F88030 		ldr	r3, [r2, #128]
 2071 004a 43F48033 		orr	r3, r3, #65536
 2072 004e C2F88030 		str	r3, [r2, #128]
 2073              	.L194:
1999:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
2000:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
2001:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Configure the event mode */
2002:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   if ((sConfigAVD->Mode & AVD_MODE_EVT) == AVD_MODE_EVT)
 2074              		.loc 1 2002 3 view .LVU436
 2075              		.loc 1 2002 18 is_stmt 0 view .LVU437
 2076 0052 4368     		ldr	r3, [r0, #4]
 2077              		.loc 1 2002 6 view .LVU438
 2078 0054 13F4003F 		tst	r3, #131072
 2079 0058 07D0     		beq	.L195
2003:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
2004:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     __HAL_PWR_AVD_EXTI_ENABLE_EVENT ();
 2080              		.loc 1 2004 5 is_stmt 1 view .LVU439
 2081 005a 4FF0B042 		mov	r2, #1476395008
 2082 005e D2F88430 		ldr	r3, [r2, #132]
 2083 0062 43F48033 		orr	r3, r3, #65536
 2084 0066 C2F88430 		str	r3, [r2, #132]
 2085              	.L195:
2005:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
2006:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* !defined (DUAL_CORE) */
2007:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
2008:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Rising edge configuration */
2009:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   if ((sConfigAVD->Mode & AVD_RISING_EDGE) == AVD_RISING_EDGE)
 2086              		.loc 1 2009 3 view .LVU440
 2087              		.loc 1 2009 18 is_stmt 0 view .LVU441
 2088 006a 4368     		ldr	r3, [r0, #4]
 2089              		.loc 1 2009 6 view .LVU442
 2090 006c 13F0010F 		tst	r3, #1
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 92


 2091 0070 05D0     		beq	.L196
2010:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
2011:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE ();
 2092              		.loc 1 2011 5 is_stmt 1 view .LVU443
 2093 0072 4FF0B042 		mov	r2, #1476395008
 2094 0076 1368     		ldr	r3, [r2]
 2095 0078 43F48033 		orr	r3, r3, #65536
 2096 007c 1360     		str	r3, [r2]
 2097              	.L196:
2012:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
2013:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
2014:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Falling edge configuration */
2015:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   if ((sConfigAVD->Mode & AVD_FALLING_EDGE) == AVD_FALLING_EDGE)
 2098              		.loc 1 2015 3 view .LVU444
 2099              		.loc 1 2015 18 is_stmt 0 view .LVU445
 2100 007e 4368     		ldr	r3, [r0, #4]
 2101              		.loc 1 2015 6 view .LVU446
 2102 0080 13F0020F 		tst	r3, #2
 2103 0084 05D0     		beq	.L193
2016:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
2017:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE ();
 2104              		.loc 1 2017 5 is_stmt 1 view .LVU447
 2105 0086 4FF0B042 		mov	r2, #1476395008
 2106 008a 5368     		ldr	r3, [r2, #4]
 2107 008c 43F48033 		orr	r3, r3, #65536
 2108 0090 5360     		str	r3, [r2, #4]
 2109              	.L193:
2018:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
2019:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
 2110              		.loc 1 2019 1 is_stmt 0 view .LVU448
 2111 0092 7047     		bx	lr
 2112              	.L199:
 2113              		.align	2
 2114              	.L198:
 2115 0094 00480258 		.word	1476544512
 2116              		.cfi_endproc
 2117              	.LFE376:
 2119              		.section	.text.HAL_PWREx_EnableAVD,"ax",%progbits
 2120              		.align	1
 2121              		.global	HAL_PWREx_EnableAVD
 2122              		.syntax unified
 2123              		.thumb
 2124              		.thumb_func
 2126              	HAL_PWREx_EnableAVD:
 2127              	.LFB377:
2020:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
2021:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
2022:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief Enable the Analog Voltage Detector (AVD).
2023:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @retval None.
2024:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
2025:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_EnableAVD (void)
2026:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
 2128              		.loc 1 2026 1 is_stmt 1 view -0
 2129              		.cfi_startproc
 2130              		@ args = 0, pretend = 0, frame = 0
 2131              		@ frame_needed = 0, uses_anonymous_args = 0
 2132              		@ link register save eliminated.
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 93


2027:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Enable the Analog Voltage Detector */
2028:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   SET_BIT (PWR->CR1, PWR_CR1_AVDEN);
 2133              		.loc 1 2028 3 view .LVU450
 2134 0000 024A     		ldr	r2, .L201
 2135 0002 1368     		ldr	r3, [r2]
 2136 0004 43F48033 		orr	r3, r3, #65536
 2137 0008 1360     		str	r3, [r2]
2029:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
 2138              		.loc 1 2029 1 is_stmt 0 view .LVU451
 2139 000a 7047     		bx	lr
 2140              	.L202:
 2141              		.align	2
 2142              	.L201:
 2143 000c 00480258 		.word	1476544512
 2144              		.cfi_endproc
 2145              	.LFE377:
 2147              		.section	.text.HAL_PWREx_DisableAVD,"ax",%progbits
 2148              		.align	1
 2149              		.global	HAL_PWREx_DisableAVD
 2150              		.syntax unified
 2151              		.thumb
 2152              		.thumb_func
 2154              	HAL_PWREx_DisableAVD:
 2155              	.LFB378:
2030:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
2031:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
2032:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief Disable the Analog Voltage Detector(AVD).
2033:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @retval None.
2034:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
2035:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_DisableAVD (void)
2036:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
 2156              		.loc 1 2036 1 is_stmt 1 view -0
 2157              		.cfi_startproc
 2158              		@ args = 0, pretend = 0, frame = 0
 2159              		@ frame_needed = 0, uses_anonymous_args = 0
 2160              		@ link register save eliminated.
2037:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Disable the Analog Voltage Detector */
2038:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   CLEAR_BIT (PWR->CR1, PWR_CR1_AVDEN);
 2161              		.loc 1 2038 3 view .LVU453
 2162 0000 024A     		ldr	r2, .L204
 2163 0002 1368     		ldr	r3, [r2]
 2164 0004 23F48033 		bic	r3, r3, #65536
 2165 0008 1360     		str	r3, [r2]
2039:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
 2166              		.loc 1 2039 1 is_stmt 0 view .LVU454
 2167 000a 7047     		bx	lr
 2168              	.L205:
 2169              		.align	2
 2170              	.L204:
 2171 000c 00480258 		.word	1476544512
 2172              		.cfi_endproc
 2173              	.LFE378:
 2175              		.section	.text.HAL_PWREx_AVDCallback,"ax",%progbits
 2176              		.align	1
 2177              		.weak	HAL_PWREx_AVDCallback
 2178              		.syntax unified
 2179              		.thumb
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 94


 2180              		.thumb_func
 2182              	HAL_PWREx_AVDCallback:
 2183              	.LFB380:
2040:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
2041:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
2042:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief  This function handles the PWR PVD/AVD interrupt request.
2043:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @note   This API should be called under the PVD_AVD_IRQHandler().
2044:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @retval None
2045:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
2046:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** void HAL_PWREx_PVD_AVD_IRQHandler (void)
2047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
2048:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Check if the Programmable Voltage Detector is enabled (PVD) */
2049:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   if (READ_BIT (PWR->CR1, PWR_CR1_PVDEN) != 0U)
2050:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
2051:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (DUAL_CORE)
2052:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     if (HAL_GetCurrentCPUID () == CM7_CPUID)
2053:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (DUAL_CORE) */
2054:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     {
2055:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       /* Check PWR D1/CD EXTI flag */
2056:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       if (__HAL_PWR_PVD_EXTI_GET_FLAG () != 0U)
2057:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       {
2058:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         /* PWR PVD interrupt user callback */
2059:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         HAL_PWR_PVDCallback ();
2060:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
2061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         if(__HAL_PWR_GET_FLAG (PWR_FLAG_AVDO) == 0U)
2062:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         {
2063:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           /* Clear PWR EXTI D1/CD pending bit */
2064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           __HAL_PWR_PVD_EXTI_CLEAR_FLAG ();
2065:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         }
2066:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       }
2067:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     }
2068:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (DUAL_CORE)
2069:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     else
2070:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     {
2071:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       /* Check PWR EXTI D2 flag */
2072:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       if (__HAL_PWR_PVD_EXTID2_GET_FLAG () != 0U)
2073:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       {
2074:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         /* PWR PVD interrupt user callback */
2075:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         HAL_PWR_PVDCallback ();
2076:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
2077:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         if(__HAL_PWR_GET_FLAG (PWR_FLAG_AVDO) == 0U)
2078:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         {
2079:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           /* Clear PWR EXTI D2 pending bit */
2080:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           __HAL_PWR_PVD_EXTID2_CLEAR_FLAG ();
2081:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         }
2082:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       }
2083:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     }
2084:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (DUAL_CORE) */
2085:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
2086:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
2087:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Check if the Analog Voltage Detector is enabled (AVD) */
2088:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   if (READ_BIT (PWR->CR1, PWR_CR1_AVDEN) != 0U)
2089:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
2090:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (DUAL_CORE)
2091:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     if (HAL_GetCurrentCPUID () == CM7_CPUID)
2092:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (DUAL_CORE) */
2093:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     {
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 95


2094:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       /* Check PWR EXTI D1/CD flag */
2095:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       if (__HAL_PWR_AVD_EXTI_GET_FLAG () != 0U)
2096:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       {
2097:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         /* PWR AVD interrupt user callback */
2098:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         HAL_PWREx_AVDCallback ();
2099:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
2100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         if(__HAL_PWR_GET_FLAG (PWR_FLAG_PVDO) == 0U)
2101:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         {
2102:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           /* Clear PWR EXTI D1/CD pending bit */
2103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           __HAL_PWR_AVD_EXTI_CLEAR_FLAG ();
2104:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         }
2105:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       }
2106:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     }
2107:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #if defined (DUAL_CORE)
2108:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     else
2109:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     {
2110:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       /* Check PWR EXTI D2 flag */
2111:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       if (__HAL_PWR_AVD_EXTID2_GET_FLAG () != 0U)
2112:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       {
2113:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         /* PWR AVD interrupt user callback */
2114:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         HAL_PWREx_AVDCallback ();
2115:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
2116:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         if(__HAL_PWR_GET_FLAG (PWR_FLAG_PVDO) == 0U)
2117:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         {
2118:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           /* Clear PWR EXTI D2 pending bit */
2119:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****           __HAL_PWR_AVD_EXTID2_CLEAR_FLAG ();
2120:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         }
2121:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       }
2122:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****     }
2123:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** #endif /* defined (DUAL_CORE) */
2124:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   }
2125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
2126:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
2127:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** /**
2128:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @brief PWR AVD interrupt callback.
2129:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   * @retval None.
2130:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
2131:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** __weak void HAL_PWREx_AVDCallback (void)
2132:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** {
 2184              		.loc 1 2132 1 is_stmt 1 view -0
 2185              		.cfi_startproc
 2186              		@ args = 0, pretend = 0, frame = 0
 2187              		@ frame_needed = 0, uses_anonymous_args = 0
 2188              		@ link register save eliminated.
2133:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* NOTE : This function should not be modified, when the callback is needed,
2134:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****             the HAL_PWR_AVDCallback can be implemented in the user file
2135:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   */
2136:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** }
 2189              		.loc 1 2136 1 view .LVU456
 2190 0000 7047     		bx	lr
 2191              		.cfi_endproc
 2192              	.LFE380:
 2194              		.section	.text.HAL_PWREx_PVD_AVD_IRQHandler,"ax",%progbits
 2195              		.align	1
 2196              		.global	HAL_PWREx_PVD_AVD_IRQHandler
 2197              		.syntax unified
 2198              		.thumb
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 96


 2199              		.thumb_func
 2201              	HAL_PWREx_PVD_AVD_IRQHandler:
 2202              	.LFB379:
2047:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   /* Check if the Programmable Voltage Detector is enabled (PVD) */
 2203              		.loc 1 2047 1 view -0
 2204              		.cfi_startproc
 2205              		@ args = 0, pretend = 0, frame = 0
 2206              		@ frame_needed = 0, uses_anonymous_args = 0
 2207 0000 08B5     		push	{r3, lr}
 2208              		.cfi_def_cfa_offset 8
 2209              		.cfi_offset 3, -8
 2210              		.cfi_offset 14, -4
2049:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
 2211              		.loc 1 2049 3 view .LVU458
2049:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
 2212              		.loc 1 2049 7 is_stmt 0 view .LVU459
 2213 0002 1C4B     		ldr	r3, .L213
 2214 0004 1B68     		ldr	r3, [r3]
2049:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
 2215              		.loc 1 2049 6 view .LVU460
 2216 0006 13F0100F 		tst	r3, #16
 2217 000a 06D0     		beq	.L208
2056:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       {
 2218              		.loc 1 2056 7 is_stmt 1 view .LVU461
2056:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       {
 2219              		.loc 1 2056 11 is_stmt 0 view .LVU462
 2220 000c 4FF0B043 		mov	r3, #1476395008
 2221 0010 D3F88830 		ldr	r3, [r3, #136]
2056:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       {
 2222              		.loc 1 2056 10 view .LVU463
 2223 0014 13F4803F 		tst	r3, #65536
 2224 0018 0CD1     		bne	.L211
 2225              	.L208:
2088:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
 2226              		.loc 1 2088 3 is_stmt 1 view .LVU464
2088:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
 2227              		.loc 1 2088 7 is_stmt 0 view .LVU465
 2228 001a 164B     		ldr	r3, .L213
 2229 001c 1B68     		ldr	r3, [r3]
2088:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****   {
 2230              		.loc 1 2088 6 view .LVU466
 2231 001e 13F4803F 		tst	r3, #65536
 2232 0022 06D0     		beq	.L207
2095:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       {
 2233              		.loc 1 2095 7 is_stmt 1 view .LVU467
2095:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       {
 2234              		.loc 1 2095 11 is_stmt 0 view .LVU468
 2235 0024 4FF0B043 		mov	r3, #1476395008
 2236 0028 D3F88830 		ldr	r3, [r3, #136]
2095:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****       {
 2237              		.loc 1 2095 10 view .LVU469
 2238 002c 13F4803F 		tst	r3, #65536
 2239 0030 10D1     		bne	.L212
 2240              	.L207:
2125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 2241              		.loc 1 2125 1 view .LVU470
 2242 0032 08BD     		pop	{r3, pc}
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 97


 2243              	.L211:
2059:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 2244              		.loc 1 2059 9 is_stmt 1 view .LVU471
 2245 0034 FFF7FEFF 		bl	HAL_PWR_PVDCallback
 2246              	.LVL86:
2061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         {
 2247              		.loc 1 2061 9 view .LVU472
2061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         {
 2248              		.loc 1 2061 12 is_stmt 0 view .LVU473
 2249 0038 0E4B     		ldr	r3, .L213
 2250 003a 5B68     		ldr	r3, [r3, #4]
2061:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         {
 2251              		.loc 1 2061 11 view .LVU474
 2252 003c 13F4803F 		tst	r3, #65536
 2253 0040 EBD1     		bne	.L208
2064:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         }
 2254              		.loc 1 2064 11 is_stmt 1 view .LVU475
 2255 0042 4FF0B042 		mov	r2, #1476395008
 2256 0046 D2F88830 		ldr	r3, [r2, #136]
 2257 004a 43F48033 		orr	r3, r3, #65536
 2258 004e C2F88830 		str	r3, [r2, #136]
 2259 0052 E2E7     		b	.L208
 2260              	.L212:
2098:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 2261              		.loc 1 2098 9 view .LVU476
 2262 0054 FFF7FEFF 		bl	HAL_PWREx_AVDCallback
 2263              	.LVL87:
2100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         {
 2264              		.loc 1 2100 9 view .LVU477
2100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         {
 2265              		.loc 1 2100 12 is_stmt 0 view .LVU478
 2266 0058 064B     		ldr	r3, .L213
 2267 005a 5B68     		ldr	r3, [r3, #4]
2100:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         {
 2268              		.loc 1 2100 11 view .LVU479
 2269 005c 13F0100F 		tst	r3, #16
 2270 0060 E7D1     		bne	.L207
2103:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c ****         }
 2271              		.loc 1 2103 11 is_stmt 1 view .LVU480
 2272 0062 4FF0B042 		mov	r2, #1476395008
 2273 0066 D2F88830 		ldr	r3, [r2, #136]
 2274 006a 43F48033 		orr	r3, r3, #65536
 2275 006e C2F88830 		str	r3, [r2, #136]
2125:Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c **** 
 2276              		.loc 1 2125 1 is_stmt 0 view .LVU481
 2277 0072 DEE7     		b	.L207
 2278              	.L214:
 2279              		.align	2
 2280              	.L213:
 2281 0074 00480258 		.word	1476544512
 2282              		.cfi_endproc
 2283              	.LFE379:
 2285              		.text
 2286              	.Letext0:
 2287              		.file 3 "C:/Users/lenex/AppData/Roaming/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-to
 2288              		.file 4 "C:/Users/lenex/AppData/Roaming/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-to
 2289              		.file 5 "Drivers/CMSIS/Include/core_cm7.h"
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 98


 2290              		.file 6 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7a3xx.h"
 2291              		.file 7 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h"
 2292              		.file 8 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h"
 2293              		.file 9 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h"
 2294              		.file 10 "Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h"
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 99


DEFINED SYMBOLS
                            *ABS*:00000000 stm32h7xx_hal_pwr_ex.c
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:20     .text.HAL_PWREx_ConfigSupply:00000000 $t
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:26     .text.HAL_PWREx_ConfigSupply:00000000 HAL_PWREx_ConfigSupply
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:116    .text.HAL_PWREx_ConfigSupply:00000050 $d
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:121    .text.HAL_PWREx_GetSupplyConfig:00000000 $t
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:127    .text.HAL_PWREx_GetSupplyConfig:00000000 HAL_PWREx_GetSupplyConfig
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:144    .text.HAL_PWREx_GetSupplyConfig:0000000c $d
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:149    .text.HAL_PWREx_ControlVoltageScaling:00000000 $t
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:155    .text.HAL_PWREx_ControlVoltageScaling:00000000 HAL_PWREx_ControlVoltageScaling
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:231    .text.HAL_PWREx_ControlVoltageScaling:00000044 $d
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:236    .text.HAL_PWREx_GetVoltageRange:00000000 $t
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:242    .text.HAL_PWREx_GetVoltageRange:00000000 HAL_PWREx_GetVoltageRange
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:259    .text.HAL_PWREx_GetVoltageRange:0000000c $d
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:264    .text.HAL_PWREx_ControlStopModeVoltageScaling:00000000 $t
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:270    .text.HAL_PWREx_ControlStopModeVoltageScaling:00000000 HAL_PWREx_ControlStopModeVoltageScaling
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:294    .text.HAL_PWREx_ControlStopModeVoltageScaling:00000010 $d
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:299    .text.HAL_PWREx_GetStopModeVoltageRange:00000000 $t
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:305    .text.HAL_PWREx_GetStopModeVoltageRange:00000000 HAL_PWREx_GetStopModeVoltageRange
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:322    .text.HAL_PWREx_GetStopModeVoltageRange:0000000c $d
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:327    .text.HAL_PWREx_EnterSTOP2Mode:00000000 $t
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:333    .text.HAL_PWREx_EnterSTOP2Mode:00000000 HAL_PWREx_EnterSTOP2Mode
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:422    .text.HAL_PWREx_EnterSTOP2Mode:00000044 $d
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:428    .text.HAL_PWREx_EnterSTOPMode:00000000 $t
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:434    .text.HAL_PWREx_EnterSTOPMode:00000000 HAL_PWREx_EnterSTOPMode
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:545    .text.HAL_PWREx_EnterSTOPMode:00000050 $d
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:551    .text.HAL_PWREx_ClearPendingEvent:00000000 $t
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:557    .text.HAL_PWREx_ClearPendingEvent:00000000 HAL_PWREx_ClearPendingEvent
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:577    .text.HAL_PWREx_EnterSTANDBYMode:00000000 $t
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:583    .text.HAL_PWREx_EnterSTANDBYMode:00000000 HAL_PWREx_EnterSTANDBYMode
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:624    .text.HAL_PWREx_EnterSTANDBYMode:00000028 $d
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:630    .text.HAL_PWREx_ConfigD3Domain:00000000 $t
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:636    .text.HAL_PWREx_ConfigD3Domain:00000000 HAL_PWREx_ConfigD3Domain
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:656    .text.HAL_PWREx_ConfigD3Domain:00000010 $d
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:661    .text.HAL_PWREx_EnableFlashPowerDown:00000000 $t
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:667    .text.HAL_PWREx_EnableFlashPowerDown:00000000 HAL_PWREx_EnableFlashPowerDown
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:684    .text.HAL_PWREx_EnableFlashPowerDown:0000000c $d
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:689    .text.HAL_PWREx_DisableFlashPowerDown:00000000 $t
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:695    .text.HAL_PWREx_DisableFlashPowerDown:00000000 HAL_PWREx_DisableFlashPowerDown
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:712    .text.HAL_PWREx_DisableFlashPowerDown:0000000c $d
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:717    .text.HAL_PWREx_EnableMemoryShutOff:00000000 $t
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:723    .text.HAL_PWREx_EnableMemoryShutOff:00000000 HAL_PWREx_EnableMemoryShutOff
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:742    .text.HAL_PWREx_EnableMemoryShutOff:0000000c $d
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:747    .text.HAL_PWREx_DisableMemoryShutOff:00000000 $t
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:753    .text.HAL_PWREx_DisableMemoryShutOff:00000000 HAL_PWREx_DisableMemoryShutOff
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:772    .text.HAL_PWREx_DisableMemoryShutOff:0000000c $d
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:777    .text.HAL_PWREx_EnableWakeUpPin:00000000 $t
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:783    .text.HAL_PWREx_EnableWakeUpPin:00000000 HAL_PWREx_EnableWakeUpPin
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1046   .text.HAL_PWREx_EnableWakeUpPin:000000a4 $d
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1053   .text.HAL_PWREx_DisableWakeUpPin:00000000 $t
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1059   .text.HAL_PWREx_DisableWakeUpPin:00000000 HAL_PWREx_DisableWakeUpPin
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1078   .text.HAL_PWREx_DisableWakeUpPin:0000000c $d
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1083   .text.HAL_PWREx_GetWakeupFlag:00000000 $t
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1089   .text.HAL_PWREx_GetWakeupFlag:00000000 HAL_PWREx_GetWakeupFlag
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1110   .text.HAL_PWREx_GetWakeupFlag:00000008 $d
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1115   .text.HAL_PWREx_ClearWakeupFlag:00000000 $t
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1121   .text.HAL_PWREx_ClearWakeupFlag:00000000 HAL_PWREx_ClearWakeupFlag
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 100


C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1156   .text.HAL_PWREx_ClearWakeupFlag:00000018 $d
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1161   .text.HAL_PWREx_WKUP1_Callback:00000000 $t
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1167   .text.HAL_PWREx_WKUP1_Callback:00000000 HAL_PWREx_WKUP1_Callback
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1180   .text.HAL_PWREx_WKUP2_Callback:00000000 $t
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1186   .text.HAL_PWREx_WKUP2_Callback:00000000 HAL_PWREx_WKUP2_Callback
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1199   .text.HAL_PWREx_WKUP3_Callback:00000000 $t
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1205   .text.HAL_PWREx_WKUP3_Callback:00000000 HAL_PWREx_WKUP3_Callback
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1218   .text.HAL_PWREx_WKUP4_Callback:00000000 $t
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1224   .text.HAL_PWREx_WKUP4_Callback:00000000 HAL_PWREx_WKUP4_Callback
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1237   .text.HAL_PWREx_WKUP5_Callback:00000000 $t
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1243   .text.HAL_PWREx_WKUP5_Callback:00000000 HAL_PWREx_WKUP5_Callback
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1256   .text.HAL_PWREx_WKUP6_Callback:00000000 $t
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1262   .text.HAL_PWREx_WKUP6_Callback:00000000 HAL_PWREx_WKUP6_Callback
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1275   .text.HAL_PWREx_WAKEUP_PIN_IRQHandler:00000000 $t
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1281   .text.HAL_PWREx_WAKEUP_PIN_IRQHandler:00000000 HAL_PWREx_WAKEUP_PIN_IRQHandler
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1391   .text.HAL_PWREx_WAKEUP_PIN_IRQHandler:00000094 $d
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1396   .text.HAL_PWREx_EnableBkUpReg:00000000 $t
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1402   .text.HAL_PWREx_EnableBkUpReg:00000000 HAL_PWREx_EnableBkUpReg
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1456   .text.HAL_PWREx_EnableBkUpReg:00000030 $d
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1461   .text.HAL_PWREx_DisableBkUpReg:00000000 $t
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1467   .text.HAL_PWREx_DisableBkUpReg:00000000 HAL_PWREx_DisableBkUpReg
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1521   .text.HAL_PWREx_DisableBkUpReg:00000030 $d
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1526   .text.HAL_PWREx_EnableUSBReg:00000000 $t
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1532   .text.HAL_PWREx_EnableUSBReg:00000000 HAL_PWREx_EnableUSBReg
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1586   .text.HAL_PWREx_EnableUSBReg:00000030 $d
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1591   .text.HAL_PWREx_DisableUSBReg:00000000 $t
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1597   .text.HAL_PWREx_DisableUSBReg:00000000 HAL_PWREx_DisableUSBReg
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1651   .text.HAL_PWREx_DisableUSBReg:00000030 $d
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1656   .text.HAL_PWREx_EnableUSBVoltageDetector:00000000 $t
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1662   .text.HAL_PWREx_EnableUSBVoltageDetector:00000000 HAL_PWREx_EnableUSBVoltageDetector
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1679   .text.HAL_PWREx_EnableUSBVoltageDetector:0000000c $d
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1684   .text.HAL_PWREx_DisableUSBVoltageDetector:00000000 $t
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1690   .text.HAL_PWREx_DisableUSBVoltageDetector:00000000 HAL_PWREx_DisableUSBVoltageDetector
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1707   .text.HAL_PWREx_DisableUSBVoltageDetector:0000000c $d
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1712   .text.HAL_PWREx_EnableBatteryCharging:00000000 $t
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1718   .text.HAL_PWREx_EnableBatteryCharging:00000000 HAL_PWREx_EnableBatteryCharging
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1742   .text.HAL_PWREx_EnableBatteryCharging:00000018 $d
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1747   .text.HAL_PWREx_DisableBatteryCharging:00000000 $t
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1753   .text.HAL_PWREx_DisableBatteryCharging:00000000 HAL_PWREx_DisableBatteryCharging
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1770   .text.HAL_PWREx_DisableBatteryCharging:0000000c $d
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1775   .text.HAL_PWREx_EnableAnalogBooster:00000000 $t
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1781   .text.HAL_PWREx_EnableAnalogBooster:00000000 HAL_PWREx_EnableAnalogBooster
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1802   .text.HAL_PWREx_EnableAnalogBooster:00000014 $d
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1807   .text.HAL_PWREx_DisableAnalogBooster:00000000 $t
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1813   .text.HAL_PWREx_DisableAnalogBooster:00000000 HAL_PWREx_DisableAnalogBooster
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1834   .text.HAL_PWREx_DisableAnalogBooster:00000014 $d
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1839   .text.HAL_PWREx_EnableMonitoring:00000000 $t
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1845   .text.HAL_PWREx_EnableMonitoring:00000000 HAL_PWREx_EnableMonitoring
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1862   .text.HAL_PWREx_EnableMonitoring:0000000c $d
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1867   .text.HAL_PWREx_DisableMonitoring:00000000 $t
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1873   .text.HAL_PWREx_DisableMonitoring:00000000 HAL_PWREx_DisableMonitoring
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1890   .text.HAL_PWREx_DisableMonitoring:0000000c $d
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1895   .text.HAL_PWREx_GetTemperatureLevel:00000000 $t
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1901   .text.HAL_PWREx_GetTemperatureLevel:00000000 HAL_PWREx_GetTemperatureLevel
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1934   .text.HAL_PWREx_GetTemperatureLevel:00000018 $d
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1939   .text.HAL_PWREx_GetVBATLevel:00000000 $t
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1945   .text.HAL_PWREx_GetVBATLevel:00000000 HAL_PWREx_GetVBATLevel
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s 			page 101


C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1978   .text.HAL_PWREx_GetVBATLevel:00000018 $d
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1983   .text.HAL_PWREx_GetMMCVoltage:00000000 $t
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:1989   .text.HAL_PWREx_GetMMCVoltage:00000000 HAL_PWREx_GetMMCVoltage
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:2017   .text.HAL_PWREx_GetMMCVoltage:00000014 $d
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:2022   .text.HAL_PWREx_ConfigAVD:00000000 $t
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:2028   .text.HAL_PWREx_ConfigAVD:00000000 HAL_PWREx_ConfigAVD
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:2115   .text.HAL_PWREx_ConfigAVD:00000094 $d
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:2120   .text.HAL_PWREx_EnableAVD:00000000 $t
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:2126   .text.HAL_PWREx_EnableAVD:00000000 HAL_PWREx_EnableAVD
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:2143   .text.HAL_PWREx_EnableAVD:0000000c $d
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:2148   .text.HAL_PWREx_DisableAVD:00000000 $t
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:2154   .text.HAL_PWREx_DisableAVD:00000000 HAL_PWREx_DisableAVD
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:2171   .text.HAL_PWREx_DisableAVD:0000000c $d
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:2176   .text.HAL_PWREx_AVDCallback:00000000 $t
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:2182   .text.HAL_PWREx_AVDCallback:00000000 HAL_PWREx_AVDCallback
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:2195   .text.HAL_PWREx_PVD_AVD_IRQHandler:00000000 $t
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:2201   .text.HAL_PWREx_PVD_AVD_IRQHandler:00000000 HAL_PWREx_PVD_AVD_IRQHandler
C:\Users\lenex\AppData\Local\Temp\ccEPg7Zt.s:2281   .text.HAL_PWREx_PVD_AVD_IRQHandler:00000074 $d

UNDEFINED SYMBOLS
HAL_GetTick
HAL_PWR_PVDCallback
