ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccQzuQch.s 			page 1


   1              		.cpu cortex-m7
   2              		.arch armv7e-m
   3              		.fpu fpv5-d16
   4              		.eabi_attribute 28, 1
   5              		.eabi_attribute 20, 1
   6              		.eabi_attribute 21, 1
   7              		.eabi_attribute 23, 3
   8              		.eabi_attribute 24, 1
   9              		.eabi_attribute 25, 1
  10              		.eabi_attribute 26, 1
  11              		.eabi_attribute 30, 1
  12              		.eabi_attribute 34, 1
  13              		.eabi_attribute 18, 4
  14              		.file	"system_stm32h7xx.c"
  15              		.text
  16              	.Ltext0:
  17              		.cfi_sections	.debug_frame
  18              		.file 1 "Core/Src/system_stm32h7xx.c"
  19              		.section	.text.SystemInit,"ax",%progbits
  20              		.align	1
  21              		.global	SystemInit
  22              		.syntax unified
  23              		.thumb
  24              		.thumb_func
  26              	SystemInit:
  27              	.LFB335:
   1:Core/Src/system_stm32h7xx.c **** /**
   2:Core/Src/system_stm32h7xx.c ****   ******************************************************************************
   3:Core/Src/system_stm32h7xx.c ****   * @file    system_stm32h7xx.c
   4:Core/Src/system_stm32h7xx.c ****   * @author  MCD Application Team
   5:Core/Src/system_stm32h7xx.c ****   * @brief   CMSIS Cortex-Mx Device Peripheral Access Layer System Source File.
   6:Core/Src/system_stm32h7xx.c ****   *
   7:Core/Src/system_stm32h7xx.c ****   *   This file provides two functions and one global variable to be called from
   8:Core/Src/system_stm32h7xx.c ****   *   user application:
   9:Core/Src/system_stm32h7xx.c ****   *      - SystemInit(): This function is called at startup just after reset and
  10:Core/Src/system_stm32h7xx.c ****   *                      before branch to main program. This call is made inside
  11:Core/Src/system_stm32h7xx.c ****   *                      the "startup_stm32h7xx.s" file.
  12:Core/Src/system_stm32h7xx.c ****   *
  13:Core/Src/system_stm32h7xx.c ****   *      - SystemCoreClock variable: Contains the core clock, it can be used
  14:Core/Src/system_stm32h7xx.c ****   *                                  by the user application to setup the SysTick
  15:Core/Src/system_stm32h7xx.c ****   *                                  timer or configure other parameters.
  16:Core/Src/system_stm32h7xx.c ****   *
  17:Core/Src/system_stm32h7xx.c ****   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
  18:Core/Src/system_stm32h7xx.c ****   *                                 be called whenever the core clock is changed
  19:Core/Src/system_stm32h7xx.c ****   *                                 during program execution.
  20:Core/Src/system_stm32h7xx.c ****   *
  21:Core/Src/system_stm32h7xx.c ****   *
  22:Core/Src/system_stm32h7xx.c ****   ******************************************************************************
  23:Core/Src/system_stm32h7xx.c ****   * @attention
  24:Core/Src/system_stm32h7xx.c ****   *
  25:Core/Src/system_stm32h7xx.c ****   * Copyright (c) 2017 STMicroelectronics.
  26:Core/Src/system_stm32h7xx.c ****   * All rights reserved.
  27:Core/Src/system_stm32h7xx.c ****   *
  28:Core/Src/system_stm32h7xx.c ****   * This software is licensed under terms that can be found in the LICENSE file
  29:Core/Src/system_stm32h7xx.c ****   * in the root directory of this software component.
  30:Core/Src/system_stm32h7xx.c ****   * If no LICENSE file comes with this software, it is provided AS-IS.
  31:Core/Src/system_stm32h7xx.c ****   *
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccQzuQch.s 			page 2


  32:Core/Src/system_stm32h7xx.c ****   ******************************************************************************
  33:Core/Src/system_stm32h7xx.c ****   */
  34:Core/Src/system_stm32h7xx.c **** 
  35:Core/Src/system_stm32h7xx.c **** /** @addtogroup CMSIS
  36:Core/Src/system_stm32h7xx.c ****   * @{
  37:Core/Src/system_stm32h7xx.c ****   */
  38:Core/Src/system_stm32h7xx.c **** 
  39:Core/Src/system_stm32h7xx.c **** /** @addtogroup stm32h7xx_system
  40:Core/Src/system_stm32h7xx.c ****   * @{
  41:Core/Src/system_stm32h7xx.c ****   */
  42:Core/Src/system_stm32h7xx.c **** 
  43:Core/Src/system_stm32h7xx.c **** /** @addtogroup STM32H7xx_System_Private_Includes
  44:Core/Src/system_stm32h7xx.c ****   * @{
  45:Core/Src/system_stm32h7xx.c ****   */
  46:Core/Src/system_stm32h7xx.c **** 
  47:Core/Src/system_stm32h7xx.c **** #include "stm32h7xx.h"
  48:Core/Src/system_stm32h7xx.c **** #include <math.h>
  49:Core/Src/system_stm32h7xx.c **** 
  50:Core/Src/system_stm32h7xx.c **** #if !defined  (HSE_VALUE)
  51:Core/Src/system_stm32h7xx.c **** #define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
  52:Core/Src/system_stm32h7xx.c **** #endif /* HSE_VALUE */
  53:Core/Src/system_stm32h7xx.c **** 
  54:Core/Src/system_stm32h7xx.c **** #if !defined  (CSI_VALUE)
  55:Core/Src/system_stm32h7xx.c ****   #define CSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
  56:Core/Src/system_stm32h7xx.c **** #endif /* CSI_VALUE */
  57:Core/Src/system_stm32h7xx.c **** 
  58:Core/Src/system_stm32h7xx.c **** #if !defined  (HSI_VALUE)
  59:Core/Src/system_stm32h7xx.c ****   #define HSI_VALUE    ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
  60:Core/Src/system_stm32h7xx.c **** #endif /* HSI_VALUE */
  61:Core/Src/system_stm32h7xx.c **** 
  62:Core/Src/system_stm32h7xx.c **** 
  63:Core/Src/system_stm32h7xx.c **** /**
  64:Core/Src/system_stm32h7xx.c ****   * @}
  65:Core/Src/system_stm32h7xx.c ****   */
  66:Core/Src/system_stm32h7xx.c **** 
  67:Core/Src/system_stm32h7xx.c **** /** @addtogroup STM32H7xx_System_Private_TypesDefinitions
  68:Core/Src/system_stm32h7xx.c ****   * @{
  69:Core/Src/system_stm32h7xx.c ****   */
  70:Core/Src/system_stm32h7xx.c **** 
  71:Core/Src/system_stm32h7xx.c **** /**
  72:Core/Src/system_stm32h7xx.c ****   * @}
  73:Core/Src/system_stm32h7xx.c ****   */
  74:Core/Src/system_stm32h7xx.c **** 
  75:Core/Src/system_stm32h7xx.c **** /** @addtogroup STM32H7xx_System_Private_Defines
  76:Core/Src/system_stm32h7xx.c ****   * @{
  77:Core/Src/system_stm32h7xx.c ****   */
  78:Core/Src/system_stm32h7xx.c **** 
  79:Core/Src/system_stm32h7xx.c **** /************************* Miscellaneous Configuration ************************/
  80:Core/Src/system_stm32h7xx.c **** /*!< Uncomment the following line if you need to use initialized data in D2 domain SRAM (AHB SRAM) 
  81:Core/Src/system_stm32h7xx.c **** /* #define DATA_IN_D2_SRAM */
  82:Core/Src/system_stm32h7xx.c **** 
  83:Core/Src/system_stm32h7xx.c **** /* Note: Following vector table addresses must be defined in line with linker
  84:Core/Src/system_stm32h7xx.c ****          configuration. */
  85:Core/Src/system_stm32h7xx.c **** /*!< Uncomment the following line if you need to relocate the vector table
  86:Core/Src/system_stm32h7xx.c ****      anywhere in FLASH BANK1 or AXI SRAM, else the vector table is kept at the automatic
  87:Core/Src/system_stm32h7xx.c ****      remap of boot address selected */
  88:Core/Src/system_stm32h7xx.c **** /* #define USER_VECT_TAB_ADDRESS */
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccQzuQch.s 			page 3


  89:Core/Src/system_stm32h7xx.c **** 
  90:Core/Src/system_stm32h7xx.c **** #if defined(USER_VECT_TAB_ADDRESS)
  91:Core/Src/system_stm32h7xx.c **** #if defined(DUAL_CORE) && defined(CORE_CM4)
  92:Core/Src/system_stm32h7xx.c **** /*!< Uncomment the following line if you need to relocate your vector Table
  93:Core/Src/system_stm32h7xx.c ****      in D2 AXI SRAM else user remap will be done in FLASH BANK2. */
  94:Core/Src/system_stm32h7xx.c **** /* #define VECT_TAB_SRAM */
  95:Core/Src/system_stm32h7xx.c **** #if defined(VECT_TAB_SRAM)
  96:Core/Src/system_stm32h7xx.c **** #define VECT_TAB_BASE_ADDRESS   D2_AXISRAM_BASE   /*!< Vector Table base address field.
  97:Core/Src/system_stm32h7xx.c ****                                                        This value must be a multiple of 0x400. */
  98:Core/Src/system_stm32h7xx.c **** #define VECT_TAB_OFFSET         0x00000000U       /*!< Vector Table base offset field.
  99:Core/Src/system_stm32h7xx.c ****                                                        This value must be a multiple of 0x400. */
 100:Core/Src/system_stm32h7xx.c **** #else
 101:Core/Src/system_stm32h7xx.c **** #define VECT_TAB_BASE_ADDRESS   FLASH_BANK2_BASE  /*!< Vector Table base address field.
 102:Core/Src/system_stm32h7xx.c ****                                                        This value must be a multiple of 0x400. */
 103:Core/Src/system_stm32h7xx.c **** #define VECT_TAB_OFFSET         0x00000000U       /*!< Vector Table base offset field.
 104:Core/Src/system_stm32h7xx.c ****                                                        This value must be a multiple of 0x400. */
 105:Core/Src/system_stm32h7xx.c **** #endif /* VECT_TAB_SRAM */
 106:Core/Src/system_stm32h7xx.c **** #else
 107:Core/Src/system_stm32h7xx.c **** /*!< Uncomment the following line if you need to relocate your vector Table
 108:Core/Src/system_stm32h7xx.c ****      in D1 AXI SRAM else user remap will be done in FLASH BANK1. */
 109:Core/Src/system_stm32h7xx.c **** /* #define VECT_TAB_SRAM */
 110:Core/Src/system_stm32h7xx.c **** #if defined(VECT_TAB_SRAM)
 111:Core/Src/system_stm32h7xx.c **** #define VECT_TAB_BASE_ADDRESS   D1_AXISRAM_BASE   /*!< Vector Table base address field.
 112:Core/Src/system_stm32h7xx.c ****                                                        This value must be a multiple of 0x400. */
 113:Core/Src/system_stm32h7xx.c **** #define VECT_TAB_OFFSET         0x00000000U       /*!< Vector Table base offset field.
 114:Core/Src/system_stm32h7xx.c ****                                                        This value must be a multiple of 0x400. */
 115:Core/Src/system_stm32h7xx.c **** #else
 116:Core/Src/system_stm32h7xx.c **** #define VECT_TAB_BASE_ADDRESS   FLASH_BANK1_BASE  /*!< Vector Table base address field.
 117:Core/Src/system_stm32h7xx.c ****                                                        This value must be a multiple of 0x400. */
 118:Core/Src/system_stm32h7xx.c **** #define VECT_TAB_OFFSET         0x00000000U       /*!< Vector Table base offset field.
 119:Core/Src/system_stm32h7xx.c ****                                                        This value must be a multiple of 0x400. */
 120:Core/Src/system_stm32h7xx.c **** #endif /* VECT_TAB_SRAM */
 121:Core/Src/system_stm32h7xx.c **** #endif /* DUAL_CORE && CORE_CM4 */
 122:Core/Src/system_stm32h7xx.c **** #endif /* USER_VECT_TAB_ADDRESS */
 123:Core/Src/system_stm32h7xx.c **** /******************************************************************************/
 124:Core/Src/system_stm32h7xx.c **** 
 125:Core/Src/system_stm32h7xx.c **** /**
 126:Core/Src/system_stm32h7xx.c ****   * @}
 127:Core/Src/system_stm32h7xx.c ****   */
 128:Core/Src/system_stm32h7xx.c **** 
 129:Core/Src/system_stm32h7xx.c **** /** @addtogroup STM32H7xx_System_Private_Macros
 130:Core/Src/system_stm32h7xx.c ****   * @{
 131:Core/Src/system_stm32h7xx.c ****   */
 132:Core/Src/system_stm32h7xx.c **** 
 133:Core/Src/system_stm32h7xx.c **** /**
 134:Core/Src/system_stm32h7xx.c ****   * @}
 135:Core/Src/system_stm32h7xx.c ****   */
 136:Core/Src/system_stm32h7xx.c **** 
 137:Core/Src/system_stm32h7xx.c **** /** @addtogroup STM32H7xx_System_Private_Variables
 138:Core/Src/system_stm32h7xx.c ****   * @{
 139:Core/Src/system_stm32h7xx.c ****   */
 140:Core/Src/system_stm32h7xx.c ****   /* This variable is updated in three ways:
 141:Core/Src/system_stm32h7xx.c ****       1) by calling CMSIS function SystemCoreClockUpdate()
 142:Core/Src/system_stm32h7xx.c ****       2) by calling HAL API function HAL_RCC_GetHCLKFreq()
 143:Core/Src/system_stm32h7xx.c ****       3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
 144:Core/Src/system_stm32h7xx.c ****          Note: If you use this function to configure the system clock; then there
 145:Core/Src/system_stm32h7xx.c ****                is no need to call the 2 first functions listed above, since SystemCoreClock
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccQzuQch.s 			page 4


 146:Core/Src/system_stm32h7xx.c ****                variable is updated automatically.
 147:Core/Src/system_stm32h7xx.c ****   */
 148:Core/Src/system_stm32h7xx.c ****   uint32_t SystemCoreClock = 64000000;
 149:Core/Src/system_stm32h7xx.c ****   uint32_t SystemD2Clock = 64000000;
 150:Core/Src/system_stm32h7xx.c ****   const  uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
 151:Core/Src/system_stm32h7xx.c **** 
 152:Core/Src/system_stm32h7xx.c **** /**
 153:Core/Src/system_stm32h7xx.c ****   * @}
 154:Core/Src/system_stm32h7xx.c ****   */
 155:Core/Src/system_stm32h7xx.c **** 
 156:Core/Src/system_stm32h7xx.c **** /** @addtogroup STM32H7xx_System_Private_FunctionPrototypes
 157:Core/Src/system_stm32h7xx.c ****   * @{
 158:Core/Src/system_stm32h7xx.c ****   */
 159:Core/Src/system_stm32h7xx.c **** 
 160:Core/Src/system_stm32h7xx.c **** /**
 161:Core/Src/system_stm32h7xx.c ****   * @}
 162:Core/Src/system_stm32h7xx.c ****   */
 163:Core/Src/system_stm32h7xx.c **** 
 164:Core/Src/system_stm32h7xx.c **** /** @addtogroup STM32H7xx_System_Private_Functions
 165:Core/Src/system_stm32h7xx.c ****   * @{
 166:Core/Src/system_stm32h7xx.c ****   */
 167:Core/Src/system_stm32h7xx.c **** 
 168:Core/Src/system_stm32h7xx.c **** /**
 169:Core/Src/system_stm32h7xx.c ****   * @brief  Setup the microcontroller system
 170:Core/Src/system_stm32h7xx.c ****   *         Initialize the FPU setting and  vector table location
 171:Core/Src/system_stm32h7xx.c ****   *         configuration.
 172:Core/Src/system_stm32h7xx.c ****   * @param  None
 173:Core/Src/system_stm32h7xx.c ****   * @retval None
 174:Core/Src/system_stm32h7xx.c ****   */
 175:Core/Src/system_stm32h7xx.c **** void SystemInit (void)
 176:Core/Src/system_stm32h7xx.c **** {
  28              		.loc 1 176 1 view -0
  29              		.cfi_startproc
  30              		@ args = 0, pretend = 0, frame = 0
  31              		@ frame_needed = 0, uses_anonymous_args = 0
  32              		@ link register save eliminated.
 177:Core/Src/system_stm32h7xx.c **** #if defined (DATA_IN_D2_SRAM)
 178:Core/Src/system_stm32h7xx.c ****  __IO uint32_t tmpreg;
 179:Core/Src/system_stm32h7xx.c **** #endif /* DATA_IN_D2_SRAM */
 180:Core/Src/system_stm32h7xx.c **** 
 181:Core/Src/system_stm32h7xx.c ****   /* FPU settings ------------------------------------------------------------*/
 182:Core/Src/system_stm32h7xx.c ****   #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
 183:Core/Src/system_stm32h7xx.c ****     SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2)));  /* set CP10 and CP11 Full Access */
  33              		.loc 1 183 5 view .LVU1
  34              		.loc 1 183 8 is_stmt 0 view .LVU2
  35 0000 224A     		ldr	r2, .L4
  36 0002 D2F88830 		ldr	r3, [r2, #136]
  37              		.loc 1 183 16 view .LVU3
  38 0006 43F47003 		orr	r3, r3, #15728640
  39 000a C2F88830 		str	r3, [r2, #136]
 184:Core/Src/system_stm32h7xx.c ****   #endif
 185:Core/Src/system_stm32h7xx.c ****   /* Reset the RCC clock configuration to the default reset state ------------*/
 186:Core/Src/system_stm32h7xx.c **** 
 187:Core/Src/system_stm32h7xx.c ****    /* Increasing the CPU frequency */
 188:Core/Src/system_stm32h7xx.c ****   if(FLASH_LATENCY_DEFAULT  > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
  40              		.loc 1 188 3 is_stmt 1 view .LVU4
  41              		.loc 1 188 32 is_stmt 0 view .LVU5
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccQzuQch.s 			page 5


  42 000e 204B     		ldr	r3, .L4+4
  43 0010 1B68     		ldr	r3, [r3]
  44 0012 03F00F03 		and	r3, r3, #15
  45              		.loc 1 188 5 view .LVU6
  46 0016 022B     		cmp	r3, #2
  47 0018 06D8     		bhi	.L2
 189:Core/Src/system_stm32h7xx.c ****   {
 190:Core/Src/system_stm32h7xx.c ****     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
 191:Core/Src/system_stm32h7xx.c ****     MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
  48              		.loc 1 191 5 is_stmt 1 view .LVU7
  49 001a 1D4A     		ldr	r2, .L4+4
  50 001c 1368     		ldr	r3, [r2]
  51 001e 23F00F03 		bic	r3, r3, #15
  52 0022 43F00303 		orr	r3, r3, #3
  53 0026 1360     		str	r3, [r2]
  54              	.L2:
 192:Core/Src/system_stm32h7xx.c ****   }
 193:Core/Src/system_stm32h7xx.c **** 
 194:Core/Src/system_stm32h7xx.c ****   /* Set HSION bit */
 195:Core/Src/system_stm32h7xx.c ****   RCC->CR |= RCC_CR_HSION;
  55              		.loc 1 195 3 view .LVU8
  56              		.loc 1 195 6 is_stmt 0 view .LVU9
  57 0028 1A4B     		ldr	r3, .L4+8
  58 002a 1A68     		ldr	r2, [r3]
  59              		.loc 1 195 11 view .LVU10
  60 002c 42F00102 		orr	r2, r2, #1
  61 0030 1A60     		str	r2, [r3]
 196:Core/Src/system_stm32h7xx.c **** 
 197:Core/Src/system_stm32h7xx.c ****   /* Reset CFGR register */
 198:Core/Src/system_stm32h7xx.c ****   RCC->CFGR = 0x00000000;
  62              		.loc 1 198 3 is_stmt 1 view .LVU11
  63              		.loc 1 198 13 is_stmt 0 view .LVU12
  64 0032 0022     		movs	r2, #0
  65 0034 1A61     		str	r2, [r3, #16]
 199:Core/Src/system_stm32h7xx.c **** 
 200:Core/Src/system_stm32h7xx.c ****   /* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */
 201:Core/Src/system_stm32h7xx.c ****   RCC->CR &= 0xEAF6ED7FU;
  66              		.loc 1 201 3 is_stmt 1 view .LVU13
  67              		.loc 1 201 6 is_stmt 0 view .LVU14
  68 0036 1968     		ldr	r1, [r3]
  69              		.loc 1 201 11 view .LVU15
  70 0038 174A     		ldr	r2, .L4+12
  71 003a 0A40     		ands	r2, r2, r1
  72 003c 1A60     		str	r2, [r3]
 202:Core/Src/system_stm32h7xx.c **** 
 203:Core/Src/system_stm32h7xx.c ****    /* Decreasing the number of wait states because of lower CPU frequency */
 204:Core/Src/system_stm32h7xx.c ****   if(FLASH_LATENCY_DEFAULT  < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
  73              		.loc 1 204 3 is_stmt 1 view .LVU16
  74              		.loc 1 204 32 is_stmt 0 view .LVU17
  75 003e 144B     		ldr	r3, .L4+4
  76 0040 1B68     		ldr	r3, [r3]
  77              		.loc 1 204 5 view .LVU18
  78 0042 13F00C0F 		tst	r3, #12
  79 0046 06D0     		beq	.L3
 205:Core/Src/system_stm32h7xx.c ****   {
 206:Core/Src/system_stm32h7xx.c ****     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
 207:Core/Src/system_stm32h7xx.c ****     MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccQzuQch.s 			page 6


  80              		.loc 1 207 5 is_stmt 1 view .LVU19
  81 0048 114A     		ldr	r2, .L4+4
  82 004a 1368     		ldr	r3, [r2]
  83 004c 23F00F03 		bic	r3, r3, #15
  84 0050 43F00303 		orr	r3, r3, #3
  85 0054 1360     		str	r3, [r2]
  86              	.L3:
 208:Core/Src/system_stm32h7xx.c ****   }
 209:Core/Src/system_stm32h7xx.c **** 
 210:Core/Src/system_stm32h7xx.c **** #if defined(D3_SRAM_BASE)
 211:Core/Src/system_stm32h7xx.c ****   /* Reset D1CFGR register */
 212:Core/Src/system_stm32h7xx.c ****   RCC->D1CFGR = 0x00000000;
 213:Core/Src/system_stm32h7xx.c **** 
 214:Core/Src/system_stm32h7xx.c ****   /* Reset D2CFGR register */
 215:Core/Src/system_stm32h7xx.c ****   RCC->D2CFGR = 0x00000000;
 216:Core/Src/system_stm32h7xx.c **** 
 217:Core/Src/system_stm32h7xx.c ****   /* Reset D3CFGR register */
 218:Core/Src/system_stm32h7xx.c ****   RCC->D3CFGR = 0x00000000;
 219:Core/Src/system_stm32h7xx.c **** #else
 220:Core/Src/system_stm32h7xx.c ****   /* Reset CDCFGR1 register */
 221:Core/Src/system_stm32h7xx.c ****   RCC->CDCFGR1 = 0x00000000;
  87              		.loc 1 221 3 view .LVU20
  88              		.loc 1 221 16 is_stmt 0 view .LVU21
  89 0056 0F4B     		ldr	r3, .L4+8
  90 0058 0022     		movs	r2, #0
  91 005a 9A61     		str	r2, [r3, #24]
 222:Core/Src/system_stm32h7xx.c **** 
 223:Core/Src/system_stm32h7xx.c ****   /* Reset CDCFGR2 register */
 224:Core/Src/system_stm32h7xx.c ****   RCC->CDCFGR2 = 0x00000000;
  92              		.loc 1 224 3 is_stmt 1 view .LVU22
  93              		.loc 1 224 16 is_stmt 0 view .LVU23
  94 005c DA61     		str	r2, [r3, #28]
 225:Core/Src/system_stm32h7xx.c **** 
 226:Core/Src/system_stm32h7xx.c ****   /* Reset SRDCFGR register */
 227:Core/Src/system_stm32h7xx.c ****   RCC->SRDCFGR = 0x00000000;
  95              		.loc 1 227 3 is_stmt 1 view .LVU24
  96              		.loc 1 227 16 is_stmt 0 view .LVU25
  97 005e 1A62     		str	r2, [r3, #32]
 228:Core/Src/system_stm32h7xx.c **** #endif
 229:Core/Src/system_stm32h7xx.c ****   /* Reset PLLCKSELR register */
 230:Core/Src/system_stm32h7xx.c ****   RCC->PLLCKSELR = 0x02020200;
  98              		.loc 1 230 3 is_stmt 1 view .LVU26
  99              		.loc 1 230 18 is_stmt 0 view .LVU27
 100 0060 0E49     		ldr	r1, .L4+16
 101 0062 9962     		str	r1, [r3, #40]
 231:Core/Src/system_stm32h7xx.c **** 
 232:Core/Src/system_stm32h7xx.c ****   /* Reset PLLCFGR register */
 233:Core/Src/system_stm32h7xx.c ****   RCC->PLLCFGR = 0x01FF0000;
 102              		.loc 1 233 3 is_stmt 1 view .LVU28
 103              		.loc 1 233 16 is_stmt 0 view .LVU29
 104 0064 0E49     		ldr	r1, .L4+20
 105 0066 D962     		str	r1, [r3, #44]
 234:Core/Src/system_stm32h7xx.c ****   /* Reset PLL1DIVR register */
 235:Core/Src/system_stm32h7xx.c ****   RCC->PLL1DIVR = 0x01010280;
 106              		.loc 1 235 3 is_stmt 1 view .LVU30
 107              		.loc 1 235 17 is_stmt 0 view .LVU31
 108 0068 0E49     		ldr	r1, .L4+24
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccQzuQch.s 			page 7


 109 006a 1963     		str	r1, [r3, #48]
 236:Core/Src/system_stm32h7xx.c ****   /* Reset PLL1FRACR register */
 237:Core/Src/system_stm32h7xx.c ****   RCC->PLL1FRACR = 0x00000000;
 110              		.loc 1 237 3 is_stmt 1 view .LVU32
 111              		.loc 1 237 18 is_stmt 0 view .LVU33
 112 006c 5A63     		str	r2, [r3, #52]
 238:Core/Src/system_stm32h7xx.c **** 
 239:Core/Src/system_stm32h7xx.c ****   /* Reset PLL2DIVR register */
 240:Core/Src/system_stm32h7xx.c ****   RCC->PLL2DIVR = 0x01010280;
 113              		.loc 1 240 3 is_stmt 1 view .LVU34
 114              		.loc 1 240 17 is_stmt 0 view .LVU35
 115 006e 9963     		str	r1, [r3, #56]
 241:Core/Src/system_stm32h7xx.c **** 
 242:Core/Src/system_stm32h7xx.c ****   /* Reset PLL2FRACR register */
 243:Core/Src/system_stm32h7xx.c **** 
 244:Core/Src/system_stm32h7xx.c ****   RCC->PLL2FRACR = 0x00000000;
 116              		.loc 1 244 3 is_stmt 1 view .LVU36
 117              		.loc 1 244 18 is_stmt 0 view .LVU37
 118 0070 DA63     		str	r2, [r3, #60]
 245:Core/Src/system_stm32h7xx.c ****   /* Reset PLL3DIVR register */
 246:Core/Src/system_stm32h7xx.c ****   RCC->PLL3DIVR = 0x01010280;
 119              		.loc 1 246 3 is_stmt 1 view .LVU38
 120              		.loc 1 246 17 is_stmt 0 view .LVU39
 121 0072 1964     		str	r1, [r3, #64]
 247:Core/Src/system_stm32h7xx.c **** 
 248:Core/Src/system_stm32h7xx.c ****   /* Reset PLL3FRACR register */
 249:Core/Src/system_stm32h7xx.c ****   RCC->PLL3FRACR = 0x00000000;
 122              		.loc 1 249 3 is_stmt 1 view .LVU40
 123              		.loc 1 249 18 is_stmt 0 view .LVU41
 124 0074 5A64     		str	r2, [r3, #68]
 250:Core/Src/system_stm32h7xx.c **** 
 251:Core/Src/system_stm32h7xx.c ****   /* Reset HSEBYP bit */
 252:Core/Src/system_stm32h7xx.c ****   RCC->CR &= 0xFFFBFFFFU;
 125              		.loc 1 252 3 is_stmt 1 view .LVU42
 126              		.loc 1 252 6 is_stmt 0 view .LVU43
 127 0076 1968     		ldr	r1, [r3]
 128              		.loc 1 252 11 view .LVU44
 129 0078 21F48021 		bic	r1, r1, #262144
 130 007c 1960     		str	r1, [r3]
 253:Core/Src/system_stm32h7xx.c **** 
 254:Core/Src/system_stm32h7xx.c ****   /* Disable all interrupts */
 255:Core/Src/system_stm32h7xx.c ****   RCC->CIER = 0x00000000;
 131              		.loc 1 255 3 is_stmt 1 view .LVU45
 132              		.loc 1 255 13 is_stmt 0 view .LVU46
 133 007e 1A66     		str	r2, [r3, #96]
 256:Core/Src/system_stm32h7xx.c **** 
 257:Core/Src/system_stm32h7xx.c **** #if (STM32H7_DEV_ID == 0x450UL)
 258:Core/Src/system_stm32h7xx.c ****   /* dual core CM7 or single core line */
 259:Core/Src/system_stm32h7xx.c ****   if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
 260:Core/Src/system_stm32h7xx.c ****   {
 261:Core/Src/system_stm32h7xx.c ****     /* if stm32h7 revY*/
 262:Core/Src/system_stm32h7xx.c ****     /* Change  the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
 263:Core/Src/system_stm32h7xx.c ****     *((__IO uint32_t*)0x51008108) = 0x000000001U;
 264:Core/Src/system_stm32h7xx.c ****   }
 265:Core/Src/system_stm32h7xx.c **** #endif /* STM32H7_DEV_ID */
 266:Core/Src/system_stm32h7xx.c **** 
 267:Core/Src/system_stm32h7xx.c **** #if defined(DATA_IN_D2_SRAM)
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccQzuQch.s 			page 8


 268:Core/Src/system_stm32h7xx.c ****   /* in case of initialized data in D2 SRAM (AHB SRAM), enable the D2 SRAM clock (AHB SRAM clock) *
 269:Core/Src/system_stm32h7xx.c **** #if defined(RCC_AHB2ENR_D2SRAM3EN)
 270:Core/Src/system_stm32h7xx.c ****   RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN);
 271:Core/Src/system_stm32h7xx.c **** #elif defined(RCC_AHB2ENR_D2SRAM2EN)
 272:Core/Src/system_stm32h7xx.c ****   RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN);
 273:Core/Src/system_stm32h7xx.c **** #else
 274:Core/Src/system_stm32h7xx.c ****   RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN);
 275:Core/Src/system_stm32h7xx.c **** #endif /* RCC_AHB2ENR_D2SRAM3EN */
 276:Core/Src/system_stm32h7xx.c **** 
 277:Core/Src/system_stm32h7xx.c ****   tmpreg = RCC->AHB2ENR;
 278:Core/Src/system_stm32h7xx.c ****   (void) tmpreg;
 279:Core/Src/system_stm32h7xx.c **** #endif /* DATA_IN_D2_SRAM */
 280:Core/Src/system_stm32h7xx.c **** 
 281:Core/Src/system_stm32h7xx.c **** #if defined(DUAL_CORE) && defined(CORE_CM4)
 282:Core/Src/system_stm32h7xx.c ****   /* Configure the Vector Table location add offset address for cortex-M4 ------------------*/
 283:Core/Src/system_stm32h7xx.c **** #if defined(USER_VECT_TAB_ADDRESS)
 284:Core/Src/system_stm32h7xx.c ****   SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D2 AX
 285:Core/Src/system_stm32h7xx.c **** #endif /* USER_VECT_TAB_ADDRESS */
 286:Core/Src/system_stm32h7xx.c **** 
 287:Core/Src/system_stm32h7xx.c **** #else
 288:Core/Src/system_stm32h7xx.c ****   /*
 289:Core/Src/system_stm32h7xx.c ****    * Disable the FMC bank1 (enabled after reset).
 290:Core/Src/system_stm32h7xx.c ****    * This, prevents CPU speculation access on this bank which blocks the use of FMC during
 291:Core/Src/system_stm32h7xx.c ****    * 24us. During this time the others FMC master (such as LTDC) cannot use it!
 292:Core/Src/system_stm32h7xx.c ****    */
 293:Core/Src/system_stm32h7xx.c ****   FMC_Bank1_R->BTCR[0] = 0x000030D2;
 134              		.loc 1 293 3 is_stmt 1 view .LVU47
 135              		.loc 1 293 24 is_stmt 0 view .LVU48
 136 0080 094B     		ldr	r3, .L4+28
 137 0082 43F2D202 		movw	r2, #12498
 138 0086 1A60     		str	r2, [r3]
 294:Core/Src/system_stm32h7xx.c **** 
 295:Core/Src/system_stm32h7xx.c ****   /* Configure the Vector Table location -------------------------------------*/
 296:Core/Src/system_stm32h7xx.c **** #if defined(USER_VECT_TAB_ADDRESS)
 297:Core/Src/system_stm32h7xx.c ****   SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AX
 298:Core/Src/system_stm32h7xx.c **** #endif /* USER_VECT_TAB_ADDRESS */
 299:Core/Src/system_stm32h7xx.c **** 
 300:Core/Src/system_stm32h7xx.c **** #endif /*DUAL_CORE && CORE_CM4*/
 301:Core/Src/system_stm32h7xx.c **** }
 139              		.loc 1 301 1 view .LVU49
 140 0088 7047     		bx	lr
 141              	.L5:
 142 008a 00BF     		.align	2
 143              	.L4:
 144 008c 00ED00E0 		.word	-536810240
 145 0090 00200052 		.word	1375739904
 146 0094 00440258 		.word	1476543488
 147 0098 7FEDF6EA 		.word	-352916097
 148 009c 00020202 		.word	33686016
 149 00a0 0000FF01 		.word	33488896
 150 00a4 80020101 		.word	16843392
 151 00a8 00400052 		.word	1375748096
 152              		.cfi_endproc
 153              	.LFE335:
 155              		.section	.text.SystemCoreClockUpdate,"ax",%progbits
 156              		.align	1
 157              		.global	SystemCoreClockUpdate
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccQzuQch.s 			page 9


 158              		.syntax unified
 159              		.thumb
 160              		.thumb_func
 162              	SystemCoreClockUpdate:
 163              	.LFB336:
 302:Core/Src/system_stm32h7xx.c **** 
 303:Core/Src/system_stm32h7xx.c **** /**
 304:Core/Src/system_stm32h7xx.c ****    * @brief  Update SystemCoreClock variable according to Clock Register Values.
 305:Core/Src/system_stm32h7xx.c ****   *         The SystemCoreClock variable contains the core clock , it can
 306:Core/Src/system_stm32h7xx.c ****   *         be used by the user application to setup the SysTick timer or configure
 307:Core/Src/system_stm32h7xx.c ****   *         other parameters.
 308:Core/Src/system_stm32h7xx.c ****   *
 309:Core/Src/system_stm32h7xx.c ****   * @note   Each time the core clock changes, this function must be called
 310:Core/Src/system_stm32h7xx.c ****   *         to update SystemCoreClock variable value. Otherwise, any configuration
 311:Core/Src/system_stm32h7xx.c ****   *         based on this variable will be incorrect.
 312:Core/Src/system_stm32h7xx.c ****   *
 313:Core/Src/system_stm32h7xx.c ****   * @note   - The system frequency computed by this function is not the real
 314:Core/Src/system_stm32h7xx.c ****   *           frequency in the chip. It is calculated based on the predefined
 315:Core/Src/system_stm32h7xx.c ****   *           constant and the selected clock source:
 316:Core/Src/system_stm32h7xx.c ****   *
 317:Core/Src/system_stm32h7xx.c ****   *           - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*)
 318:Core/Src/system_stm32h7xx.c ****   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
 319:Core/Src/system_stm32h7xx.c ****   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
 320:Core/Src/system_stm32h7xx.c ****   *           - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*),
 321:Core/Src/system_stm32h7xx.c ****   *             HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
 322:Core/Src/system_stm32h7xx.c ****   *
 323:Core/Src/system_stm32h7xx.c ****   *         (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
 324:Core/Src/system_stm32h7xx.c ****   *             4 MHz) but the real value may vary depending on the variations
 325:Core/Src/system_stm32h7xx.c ****   *             in voltage and temperature.
 326:Core/Src/system_stm32h7xx.c ****   *         (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
 327:Core/Src/system_stm32h7xx.c ****   *             64 MHz) but the real value may vary depending on the variations
 328:Core/Src/system_stm32h7xx.c ****   *             in voltage and temperature.
 329:Core/Src/system_stm32h7xx.c ****   *
 330:Core/Src/system_stm32h7xx.c ****   *         (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value
 331:Core/Src/system_stm32h7xx.c ****   *              25 MHz), user has to ensure that HSE_VALUE is same as the real
 332:Core/Src/system_stm32h7xx.c ****   *              frequency of the crystal used. Otherwise, this function may
 333:Core/Src/system_stm32h7xx.c ****   *              have wrong result.
 334:Core/Src/system_stm32h7xx.c ****   *
 335:Core/Src/system_stm32h7xx.c ****   *         - The result of this function could be not correct when using fractional
 336:Core/Src/system_stm32h7xx.c ****   *           value for HSE crystal.
 337:Core/Src/system_stm32h7xx.c ****   * @param  None
 338:Core/Src/system_stm32h7xx.c ****   * @retval None
 339:Core/Src/system_stm32h7xx.c ****   */
 340:Core/Src/system_stm32h7xx.c **** void SystemCoreClockUpdate (void)
 341:Core/Src/system_stm32h7xx.c **** {
 164              		.loc 1 341 1 is_stmt 1 view -0
 165              		.cfi_startproc
 166              		@ args = 0, pretend = 0, frame = 0
 167              		@ frame_needed = 0, uses_anonymous_args = 0
 168              		@ link register save eliminated.
 169 0000 10B4     		push	{r4}
 170              		.cfi_def_cfa_offset 4
 171              		.cfi_offset 4, -4
 342:Core/Src/system_stm32h7xx.c ****   uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
 172              		.loc 1 342 3 view .LVU51
 343:Core/Src/system_stm32h7xx.c ****   uint32_t common_system_clock;
 173              		.loc 1 343 3 view .LVU52
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccQzuQch.s 			page 10


 344:Core/Src/system_stm32h7xx.c ****   float_t fracn1, pllvco;
 174              		.loc 1 344 3 view .LVU53
 345:Core/Src/system_stm32h7xx.c **** 
 346:Core/Src/system_stm32h7xx.c **** 
 347:Core/Src/system_stm32h7xx.c ****   /* Get SYSCLK source -------------------------------------------------------*/
 348:Core/Src/system_stm32h7xx.c **** 
 349:Core/Src/system_stm32h7xx.c ****   switch (RCC->CFGR & RCC_CFGR_SWS)
 175              		.loc 1 349 3 view .LVU54
 176              		.loc 1 349 14 is_stmt 0 view .LVU55
 177 0002 7B4B     		ldr	r3, .L19
 178 0004 1B69     		ldr	r3, [r3, #16]
 179              		.loc 1 349 21 view .LVU56
 180 0006 03F03803 		and	r3, r3, #56
 181              		.loc 1 349 3 view .LVU57
 182 000a 182B     		cmp	r3, #24
 183 000c 00F2D280 		bhi	.L7
 184 0010 DFE813F0 		tbh	[pc, r3, lsl #1]
 185              	.L9:
 186 0014 1B00     		.2byte	(.L12-.L9)/2
 187 0016 D000     		.2byte	(.L7-.L9)/2
 188 0018 D000     		.2byte	(.L7-.L9)/2
 189 001a D000     		.2byte	(.L7-.L9)/2
 190 001c D000     		.2byte	(.L7-.L9)/2
 191 001e D000     		.2byte	(.L7-.L9)/2
 192 0020 D000     		.2byte	(.L7-.L9)/2
 193 0022 D000     		.2byte	(.L7-.L9)/2
 194 0024 1900     		.2byte	(.L11-.L9)/2
 195 0026 D000     		.2byte	(.L7-.L9)/2
 196 0028 D000     		.2byte	(.L7-.L9)/2
 197 002a D000     		.2byte	(.L7-.L9)/2
 198 002c D000     		.2byte	(.L7-.L9)/2
 199 002e D000     		.2byte	(.L7-.L9)/2
 200 0030 D000     		.2byte	(.L7-.L9)/2
 201 0032 D000     		.2byte	(.L7-.L9)/2
 202 0034 EC00     		.2byte	(.L17-.L9)/2
 203 0036 D000     		.2byte	(.L7-.L9)/2
 204 0038 D000     		.2byte	(.L7-.L9)/2
 205 003a D000     		.2byte	(.L7-.L9)/2
 206 003c D000     		.2byte	(.L7-.L9)/2
 207 003e D000     		.2byte	(.L7-.L9)/2
 208 0040 D000     		.2byte	(.L7-.L9)/2
 209 0042 D000     		.2byte	(.L7-.L9)/2
 210 0044 2200     		.2byte	(.L8-.L9)/2
 211              		.p2align 1
 212              	.L11:
 213 0046 6B4A     		ldr	r2, .L19+4
 214 0048 BAE0     		b	.L10
 215              	.L12:
 350:Core/Src/system_stm32h7xx.c ****   {
 351:Core/Src/system_stm32h7xx.c ****   case RCC_CFGR_SWS_HSI:  /* HSI used as system clock source */
 352:Core/Src/system_stm32h7xx.c ****     common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
 216              		.loc 1 352 5 is_stmt 1 view .LVU58
 217              		.loc 1 352 57 is_stmt 0 view .LVU59
 218 004a 694B     		ldr	r3, .L19
 219 004c 1B68     		ldr	r3, [r3]
 220              		.loc 1 352 78 view .LVU60
 221 004e C3F3C103 		ubfx	r3, r3, #3, #2
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccQzuQch.s 			page 11


 222              		.loc 1 352 25 view .LVU61
 223 0052 694A     		ldr	r2, .L19+8
 224 0054 DA40     		lsrs	r2, r2, r3
 225              	.LVL0:
 353:Core/Src/system_stm32h7xx.c ****     break;
 226              		.loc 1 353 5 is_stmt 1 view .LVU62
 227 0056 B3E0     		b	.L10
 228              	.LVL1:
 229              	.L8:
 354:Core/Src/system_stm32h7xx.c **** 
 355:Core/Src/system_stm32h7xx.c ****   case RCC_CFGR_SWS_CSI:  /* CSI used as system clock  source */
 356:Core/Src/system_stm32h7xx.c ****     common_system_clock = CSI_VALUE;
 357:Core/Src/system_stm32h7xx.c ****     break;
 358:Core/Src/system_stm32h7xx.c **** 
 359:Core/Src/system_stm32h7xx.c ****   case RCC_CFGR_SWS_HSE:  /* HSE used as system clock  source */
 360:Core/Src/system_stm32h7xx.c ****     common_system_clock = HSE_VALUE;
 361:Core/Src/system_stm32h7xx.c ****     break;
 362:Core/Src/system_stm32h7xx.c **** 
 363:Core/Src/system_stm32h7xx.c ****   case RCC_CFGR_SWS_PLL1:  /* PLL1 used as system clock  source */
 364:Core/Src/system_stm32h7xx.c **** 
 365:Core/Src/system_stm32h7xx.c ****     /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
 366:Core/Src/system_stm32h7xx.c ****     SYSCLK = PLL_VCO / PLLR
 367:Core/Src/system_stm32h7xx.c ****     */
 368:Core/Src/system_stm32h7xx.c ****     pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
 230              		.loc 1 368 5 view .LVU63
 231              		.loc 1 368 21 is_stmt 0 view .LVU64
 232 0058 654B     		ldr	r3, .L19
 233 005a 996A     		ldr	r1, [r3, #40]
 234              		.loc 1 368 15 view .LVU65
 235 005c 01F00301 		and	r1, r1, #3
 236              	.LVL2:
 369:Core/Src/system_stm32h7xx.c ****     pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4)  ;
 237              		.loc 1 369 5 is_stmt 1 view .LVU66
 238              		.loc 1 369 17 is_stmt 0 view .LVU67
 239 0060 9C6A     		ldr	r4, [r3, #40]
 240              		.loc 1 369 10 view .LVU68
 241 0062 C4F30512 		ubfx	r2, r4, #4, #6
 242              	.LVL3:
 370:Core/Src/system_stm32h7xx.c ****     pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos);
 243              		.loc 1 370 5 is_stmt 1 view .LVU69
 244              		.loc 1 370 22 is_stmt 0 view .LVU70
 245 0066 D86A     		ldr	r0, [r3, #44]
 246              		.loc 1 370 15 view .LVU71
 247 0068 00F00100 		and	r0, r0, #1
 248              	.LVL4:
 371:Core/Src/system_stm32h7xx.c ****     fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
 249              		.loc 1 371 5 is_stmt 1 view .LVU72
 250              		.loc 1 371 50 is_stmt 0 view .LVU73
 251 006c 5B6B     		ldr	r3, [r3, #52]
 252              		.loc 1 371 85 view .LVU74
 253 006e C3F3CC03 		ubfx	r3, r3, #3, #13
 254              		.loc 1 371 23 view .LVU75
 255 0072 00FB03F3 		mul	r3, r0, r3
 256              		.loc 1 371 12 view .LVU76
 257 0076 07EE903A 		vmov	s15, r3	@ int
 258 007a F8EE677A 		vcvt.f32.u32	s15, s15
 259              	.LVL5:
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccQzuQch.s 			page 12


 372:Core/Src/system_stm32h7xx.c **** 
 373:Core/Src/system_stm32h7xx.c ****     if (pllm != 0U)
 260              		.loc 1 373 5 is_stmt 1 view .LVU77
 261              		.loc 1 373 8 is_stmt 0 view .LVU78
 262 007e 14F47C7F 		tst	r4, #1008
 263 0082 00F09D80 		beq	.L10
 374:Core/Src/system_stm32h7xx.c ****     {
 375:Core/Src/system_stm32h7xx.c ****       switch (pllsource)
 264              		.loc 1 375 7 is_stmt 1 view .LVU79
 265 0086 0129     		cmp	r1, #1
 266 0088 36D0     		beq	.L13
 267 008a 0229     		cmp	r1, #2
 268 008c 51D0     		beq	.L14
 269 008e 0029     		cmp	r1, #0
 270 0090 6CD1     		bne	.L15
 376:Core/Src/system_stm32h7xx.c ****       {
 377:Core/Src/system_stm32h7xx.c ****         case RCC_PLLCKSELR_PLLSRC_HSI:  /* HSI used as PLL clock source */
 378:Core/Src/system_stm32h7xx.c **** 
 379:Core/Src/system_stm32h7xx.c ****         hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
 271              		.loc 1 379 9 view .LVU80
 272              		.loc 1 379 39 is_stmt 0 view .LVU81
 273 0092 5748     		ldr	r0, .L19
 274              	.LVL6:
 275              		.loc 1 379 39 view .LVU82
 276 0094 0168     		ldr	r1, [r0]
 277              	.LVL7:
 278              		.loc 1 379 60 view .LVU83
 279 0096 C1F3C101 		ubfx	r1, r1, #3, #2
 280              		.loc 1 379 18 view .LVU84
 281 009a 574B     		ldr	r3, .L19+8
 282 009c CB40     		lsrs	r3, r3, r1
 283              	.LVL8:
 380:Core/Src/system_stm32h7xx.c ****         pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PL
 284              		.loc 1 380 9 is_stmt 1 view .LVU85
 285              		.loc 1 380 20 is_stmt 0 view .LVU86
 286 009e 07EE103A 		vmov	s14, r3	@ int
 287 00a2 F8EE476A 		vcvt.f32.u32	s13, s14
 288              		.loc 1 380 40 view .LVU87
 289 00a6 07EE102A 		vmov	s14, r2	@ int
 290 00aa B8EE476A 		vcvt.f32.u32	s12, s14
 291              		.loc 1 380 38 view .LVU88
 292 00ae 86EE867A 		vdiv.f32	s14, s13, s12
 293              		.loc 1 380 81 view .LVU89
 294 00b2 036B     		ldr	r3, [r0, #48]
 295              	.LVL9:
 296              		.loc 1 380 67 view .LVU90
 297 00b4 C3F30803 		ubfx	r3, r3, #0, #9
 298              		.loc 1 380 58 view .LVU91
 299 00b8 06EE903A 		vmov	s13, r3	@ int
 300 00bc F8EE666A 		vcvt.f32.u32	s13, s13
 301              		.loc 1 380 120 view .LVU92
 302 00c0 9FED4E6A 		vldr.32	s12, .L19+12
 303 00c4 67EE867A 		vmul.f32	s15, s15, s12
 304              	.LVL10:
 305              		.loc 1 380 111 view .LVU93
 306 00c8 76EEA77A 		vadd.f32	s15, s13, s15
 307              		.loc 1 380 138 view .LVU94
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccQzuQch.s 			page 13


 308 00cc F7EE006A 		vmov.f32	s13, #1.0e+0
 309 00d0 77EEA67A 		vadd.f32	s15, s15, s13
 310              		.loc 1 380 16 view .LVU95
 311 00d4 27EE277A 		vmul.f32	s14, s14, s15
 312              	.LVL11:
 381:Core/Src/system_stm32h7xx.c **** 
 382:Core/Src/system_stm32h7xx.c ****         break;
 313              		.loc 1 382 9 is_stmt 1 view .LVU96
 314              	.L16:
 383:Core/Src/system_stm32h7xx.c **** 
 384:Core/Src/system_stm32h7xx.c ****         case RCC_PLLCKSELR_PLLSRC_CSI:  /* CSI used as PLL clock source */
 385:Core/Src/system_stm32h7xx.c ****           pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_
 386:Core/Src/system_stm32h7xx.c ****         break;
 387:Core/Src/system_stm32h7xx.c **** 
 388:Core/Src/system_stm32h7xx.c ****         case RCC_PLLCKSELR_PLLSRC_HSE:  /* HSE used as PLL clock source */
 389:Core/Src/system_stm32h7xx.c ****           pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_
 390:Core/Src/system_stm32h7xx.c ****         break;
 391:Core/Src/system_stm32h7xx.c **** 
 392:Core/Src/system_stm32h7xx.c ****       default:
 393:Core/Src/system_stm32h7xx.c ****           hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
 394:Core/Src/system_stm32h7xx.c ****           pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_P
 395:Core/Src/system_stm32h7xx.c ****         break;
 396:Core/Src/system_stm32h7xx.c ****       }
 397:Core/Src/system_stm32h7xx.c ****       pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
 315              		.loc 1 397 7 view .LVU97
 316              		.loc 1 397 20 is_stmt 0 view .LVU98
 317 00d8 454B     		ldr	r3, .L19
 318 00da 1B6B     		ldr	r3, [r3, #48]
 319              		.loc 1 397 50 view .LVU99
 320 00dc C3F34623 		ubfx	r3, r3, #9, #7
 321              		.loc 1 397 12 view .LVU100
 322 00e0 0133     		adds	r3, r3, #1
 323              	.LVL12:
 398:Core/Src/system_stm32h7xx.c ****       common_system_clock =  (uint32_t)(float_t)(pllvco/(float_t)pllp);
 324              		.loc 1 398 7 is_stmt 1 view .LVU101
 325              		.loc 1 398 57 is_stmt 0 view .LVU102
 326 00e2 07EE903A 		vmov	s15, r3	@ int
 327 00e6 F8EE677A 		vcvt.f32.u32	s15, s15
 328              		.loc 1 398 40 view .LVU103
 329 00ea C7EE276A 		vdiv.f32	s13, s14, s15
 330              		.loc 1 398 27 view .LVU104
 331 00ee FCEEE67A 		vcvt.u32.f32	s15, s13
 332 00f2 17EE902A 		vmov	r2, s15	@ int
 333              	.LVL13:
 334              		.loc 1 398 27 view .LVU105
 335 00f6 63E0     		b	.L10
 336              	.LVL14:
 337              	.L13:
 385:Core/Src/system_stm32h7xx.c ****         break;
 338              		.loc 1 385 11 is_stmt 1 view .LVU106
 385:Core/Src/system_stm32h7xx.c ****         break;
 339              		.loc 1 385 42 is_stmt 0 view .LVU107
 340 00f8 07EE102A 		vmov	s14, r2	@ int
 341 00fc F8EE476A 		vcvt.f32.u32	s13, s14
 385:Core/Src/system_stm32h7xx.c ****         break;
 342              		.loc 1 385 40 view .LVU108
 343 0100 9FED3F6A 		vldr.32	s12, .L19+16
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccQzuQch.s 			page 14


 344 0104 86EE267A 		vdiv.f32	s14, s12, s13
 385:Core/Src/system_stm32h7xx.c ****         break;
 345              		.loc 1 385 83 view .LVU109
 346 0108 394B     		ldr	r3, .L19
 347 010a 1B6B     		ldr	r3, [r3, #48]
 385:Core/Src/system_stm32h7xx.c ****         break;
 348              		.loc 1 385 69 view .LVU110
 349 010c C3F30803 		ubfx	r3, r3, #0, #9
 385:Core/Src/system_stm32h7xx.c ****         break;
 350              		.loc 1 385 60 view .LVU111
 351 0110 06EE903A 		vmov	s13, r3	@ int
 352 0114 F8EE666A 		vcvt.f32.u32	s13, s13
 385:Core/Src/system_stm32h7xx.c ****         break;
 353              		.loc 1 385 122 view .LVU112
 354 0118 9FED386A 		vldr.32	s12, .L19+12
 355 011c 67EE867A 		vmul.f32	s15, s15, s12
 356              	.LVL15:
 385:Core/Src/system_stm32h7xx.c ****         break;
 357              		.loc 1 385 113 view .LVU113
 358 0120 76EEA77A 		vadd.f32	s15, s13, s15
 385:Core/Src/system_stm32h7xx.c ****         break;
 359              		.loc 1 385 140 view .LVU114
 360 0124 F7EE006A 		vmov.f32	s13, #1.0e+0
 361 0128 77EEA67A 		vadd.f32	s15, s15, s13
 385:Core/Src/system_stm32h7xx.c ****         break;
 362              		.loc 1 385 18 view .LVU115
 363 012c 27EE277A 		vmul.f32	s14, s14, s15
 364              	.LVL16:
 386:Core/Src/system_stm32h7xx.c **** 
 365              		.loc 1 386 9 is_stmt 1 view .LVU116
 366 0130 D2E7     		b	.L16
 367              	.LVL17:
 368              	.L14:
 389:Core/Src/system_stm32h7xx.c ****         break;
 369              		.loc 1 389 11 view .LVU117
 389:Core/Src/system_stm32h7xx.c ****         break;
 370              		.loc 1 389 42 is_stmt 0 view .LVU118
 371 0132 07EE102A 		vmov	s14, r2	@ int
 372 0136 F8EE476A 		vcvt.f32.u32	s13, s14
 389:Core/Src/system_stm32h7xx.c ****         break;
 373              		.loc 1 389 40 view .LVU119
 374 013a 9FED326A 		vldr.32	s12, .L19+20
 375 013e 86EE267A 		vdiv.f32	s14, s12, s13
 389:Core/Src/system_stm32h7xx.c ****         break;
 376              		.loc 1 389 83 view .LVU120
 377 0142 2B4B     		ldr	r3, .L19
 378 0144 1B6B     		ldr	r3, [r3, #48]
 389:Core/Src/system_stm32h7xx.c ****         break;
 379              		.loc 1 389 69 view .LVU121
 380 0146 C3F30803 		ubfx	r3, r3, #0, #9
 389:Core/Src/system_stm32h7xx.c ****         break;
 381              		.loc 1 389 60 view .LVU122
 382 014a 06EE903A 		vmov	s13, r3	@ int
 383 014e F8EE666A 		vcvt.f32.u32	s13, s13
 389:Core/Src/system_stm32h7xx.c ****         break;
 384              		.loc 1 389 122 view .LVU123
 385 0152 9FED2A6A 		vldr.32	s12, .L19+12
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccQzuQch.s 			page 15


 386 0156 67EE867A 		vmul.f32	s15, s15, s12
 387              	.LVL18:
 389:Core/Src/system_stm32h7xx.c ****         break;
 388              		.loc 1 389 113 view .LVU124
 389 015a 76EEA77A 		vadd.f32	s15, s13, s15
 389:Core/Src/system_stm32h7xx.c ****         break;
 390              		.loc 1 389 140 view .LVU125
 391 015e F7EE006A 		vmov.f32	s13, #1.0e+0
 392 0162 77EEA67A 		vadd.f32	s15, s15, s13
 389:Core/Src/system_stm32h7xx.c ****         break;
 393              		.loc 1 389 18 view .LVU126
 394 0166 27EE277A 		vmul.f32	s14, s14, s15
 395              	.LVL19:
 390:Core/Src/system_stm32h7xx.c **** 
 396              		.loc 1 390 9 is_stmt 1 view .LVU127
 397 016a B5E7     		b	.L16
 398              	.LVL20:
 399              	.L15:
 393:Core/Src/system_stm32h7xx.c ****           pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_P
 400              		.loc 1 393 11 view .LVU128
 393:Core/Src/system_stm32h7xx.c ****           pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_P
 401              		.loc 1 393 41 is_stmt 0 view .LVU129
 402 016c 2048     		ldr	r0, .L19
 403              	.LVL21:
 393:Core/Src/system_stm32h7xx.c ****           pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_P
 404              		.loc 1 393 41 view .LVU130
 405 016e 0168     		ldr	r1, [r0]
 406              	.LVL22:
 393:Core/Src/system_stm32h7xx.c ****           pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_P
 407              		.loc 1 393 62 view .LVU131
 408 0170 C1F3C101 		ubfx	r1, r1, #3, #2
 393:Core/Src/system_stm32h7xx.c ****           pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_P
 409              		.loc 1 393 20 view .LVU132
 410 0174 204B     		ldr	r3, .L19+8
 411 0176 CB40     		lsrs	r3, r3, r1
 412              	.LVL23:
 394:Core/Src/system_stm32h7xx.c ****         break;
 413              		.loc 1 394 11 is_stmt 1 view .LVU133
 394:Core/Src/system_stm32h7xx.c ****         break;
 414              		.loc 1 394 21 is_stmt 0 view .LVU134
 415 0178 07EE103A 		vmov	s14, r3	@ int
 416 017c F8EE476A 		vcvt.f32.u32	s13, s14
 394:Core/Src/system_stm32h7xx.c ****         break;
 417              		.loc 1 394 41 view .LVU135
 418 0180 07EE102A 		vmov	s14, r2	@ int
 419 0184 B8EE476A 		vcvt.f32.u32	s12, s14
 394:Core/Src/system_stm32h7xx.c ****         break;
 420              		.loc 1 394 39 view .LVU136
 421 0188 86EE867A 		vdiv.f32	s14, s13, s12
 394:Core/Src/system_stm32h7xx.c ****         break;
 422              		.loc 1 394 82 view .LVU137
 423 018c 036B     		ldr	r3, [r0, #48]
 424              	.LVL24:
 394:Core/Src/system_stm32h7xx.c ****         break;
 425              		.loc 1 394 68 view .LVU138
 426 018e C3F30803 		ubfx	r3, r3, #0, #9
 394:Core/Src/system_stm32h7xx.c ****         break;
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccQzuQch.s 			page 16


 427              		.loc 1 394 59 view .LVU139
 428 0192 06EE903A 		vmov	s13, r3	@ int
 429 0196 F8EE666A 		vcvt.f32.u32	s13, s13
 394:Core/Src/system_stm32h7xx.c ****         break;
 430              		.loc 1 394 121 view .LVU140
 431 019a 9FED186A 		vldr.32	s12, .L19+12
 432 019e 67EE867A 		vmul.f32	s15, s15, s12
 433              	.LVL25:
 394:Core/Src/system_stm32h7xx.c ****         break;
 434              		.loc 1 394 112 view .LVU141
 435 01a2 76EEA77A 		vadd.f32	s15, s13, s15
 394:Core/Src/system_stm32h7xx.c ****         break;
 436              		.loc 1 394 139 view .LVU142
 437 01a6 F7EE006A 		vmov.f32	s13, #1.0e+0
 438 01aa 77EEA67A 		vadd.f32	s15, s15, s13
 394:Core/Src/system_stm32h7xx.c ****         break;
 439              		.loc 1 394 18 view .LVU143
 440 01ae 27EE277A 		vmul.f32	s14, s14, s15
 441              	.LVL26:
 395:Core/Src/system_stm32h7xx.c ****       }
 442              		.loc 1 395 9 is_stmt 1 view .LVU144
 443 01b2 91E7     		b	.L16
 444              	.LVL27:
 445              	.L7:
 399:Core/Src/system_stm32h7xx.c ****     }
 400:Core/Src/system_stm32h7xx.c ****     else
 401:Core/Src/system_stm32h7xx.c ****     {
 402:Core/Src/system_stm32h7xx.c ****       common_system_clock = 0U;
 403:Core/Src/system_stm32h7xx.c ****     }
 404:Core/Src/system_stm32h7xx.c ****     break;
 405:Core/Src/system_stm32h7xx.c **** 
 406:Core/Src/system_stm32h7xx.c ****   default:
 407:Core/Src/system_stm32h7xx.c ****     common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
 446              		.loc 1 407 5 view .LVU145
 447              		.loc 1 407 57 is_stmt 0 view .LVU146
 448 01b4 0E4B     		ldr	r3, .L19
 449 01b6 1B68     		ldr	r3, [r3]
 450              		.loc 1 407 78 view .LVU147
 451 01b8 C3F3C103 		ubfx	r3, r3, #3, #2
 452              		.loc 1 407 25 view .LVU148
 453 01bc 0E4A     		ldr	r2, .L19+8
 454 01be DA40     		lsrs	r2, r2, r3
 455              	.LVL28:
 408:Core/Src/system_stm32h7xx.c ****     break;
 456              		.loc 1 408 5 is_stmt 1 view .LVU149
 457              	.L10:
 409:Core/Src/system_stm32h7xx.c ****   }
 410:Core/Src/system_stm32h7xx.c **** 
 411:Core/Src/system_stm32h7xx.c ****   /* Compute SystemClock frequency --------------------------------------------------*/
 412:Core/Src/system_stm32h7xx.c **** #if defined (RCC_D1CFGR_D1CPRE)
 413:Core/Src/system_stm32h7xx.c ****   tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos];
 414:Core/Src/system_stm32h7xx.c **** 
 415:Core/Src/system_stm32h7xx.c ****   /* common_system_clock frequency : CM7 CPU frequency  */
 416:Core/Src/system_stm32h7xx.c ****   common_system_clock >>= tmp;
 417:Core/Src/system_stm32h7xx.c **** 
 418:Core/Src/system_stm32h7xx.c ****   /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency  */
 419:Core/Src/system_stm32h7xx.c ****   SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccQzuQch.s 			page 17


 420:Core/Src/system_stm32h7xx.c **** 
 421:Core/Src/system_stm32h7xx.c **** #else
 422:Core/Src/system_stm32h7xx.c ****   tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos];
 458              		.loc 1 422 3 view .LVU150
 459              		.loc 1 422 30 is_stmt 0 view .LVU151
 460 01c0 0B48     		ldr	r0, .L19
 461 01c2 8369     		ldr	r3, [r0, #24]
 462              		.loc 1 422 61 view .LVU152
 463 01c4 C3F30323 		ubfx	r3, r3, #8, #4
 464              		.loc 1 422 25 view .LVU153
 465 01c8 0F49     		ldr	r1, .L19+24
 466 01ca CB5C     		ldrb	r3, [r1, r3]	@ zero_extendqisi2
 467              	.LVL29:
 423:Core/Src/system_stm32h7xx.c **** 
 424:Core/Src/system_stm32h7xx.c ****   /* common_system_clock frequency : CM7 CPU frequency  */
 425:Core/Src/system_stm32h7xx.c ****   common_system_clock >>= tmp;
 468              		.loc 1 425 3 is_stmt 1 view .LVU154
 469              		.loc 1 425 23 is_stmt 0 view .LVU155
 470 01cc DA40     		lsrs	r2, r2, r3
 471              	.LVL30:
 426:Core/Src/system_stm32h7xx.c **** 
 427:Core/Src/system_stm32h7xx.c ****   /* SystemD2Clock frequency : AXI and AHBs Clock frequency  */
 428:Core/Src/system_stm32h7xx.c ****   SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RC
 472              		.loc 1 428 3 is_stmt 1 view .LVU156
 473              		.loc 1 428 66 is_stmt 0 view .LVU157
 474 01ce 8369     		ldr	r3, [r0, #24]
 475              	.LVL31:
 476              		.loc 1 428 95 view .LVU158
 477 01d0 03F00F03 		and	r3, r3, #15
 478              		.loc 1 428 61 view .LVU159
 479 01d4 CB5C     		ldrb	r3, [r1, r3]	@ zero_extendqisi2
 480              		.loc 1 428 121 view .LVU160
 481 01d6 03F01F03 		and	r3, r3, #31
 482              		.loc 1 428 40 view .LVU161
 483 01da 22FA03F3 		lsr	r3, r2, r3
 484              		.loc 1 428 17 view .LVU162
 485 01de 0B49     		ldr	r1, .L19+28
 486              		.loc 1 428 17 view .LVU163
 487 01e0 0B60     		str	r3, [r1]
 429:Core/Src/system_stm32h7xx.c **** 
 430:Core/Src/system_stm32h7xx.c **** #endif
 431:Core/Src/system_stm32h7xx.c **** 
 432:Core/Src/system_stm32h7xx.c **** #if defined(DUAL_CORE) && defined(CORE_CM4)
 433:Core/Src/system_stm32h7xx.c ****   SystemCoreClock = SystemD2Clock;
 434:Core/Src/system_stm32h7xx.c **** #else
 435:Core/Src/system_stm32h7xx.c ****   SystemCoreClock = common_system_clock;
 488              		.loc 1 435 3 is_stmt 1 view .LVU164
 489              		.loc 1 435 19 is_stmt 0 view .LVU165
 490 01e2 0B4B     		ldr	r3, .L19+32
 491 01e4 1A60     		str	r2, [r3]
 436:Core/Src/system_stm32h7xx.c **** #endif /* DUAL_CORE && CORE_CM4 */
 437:Core/Src/system_stm32h7xx.c **** }
 492              		.loc 1 437 1 view .LVU166
 493 01e6 5DF8044B 		ldr	r4, [sp], #4
 494              		.cfi_remember_state
 495              		.cfi_restore 4
 496              		.cfi_def_cfa_offset 0
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccQzuQch.s 			page 18


 497 01ea 7047     		bx	lr
 498              	.LVL32:
 499              	.L17:
 500              		.cfi_restore_state
 360:Core/Src/system_stm32h7xx.c ****     break;
 501              		.loc 1 360 25 view .LVU167
 502 01ec 094A     		ldr	r2, .L19+36
 503 01ee E7E7     		b	.L10
 504              	.L20:
 505              		.align	2
 506              	.L19:
 507 01f0 00440258 		.word	1476543488
 508 01f4 00093D00 		.word	4000000
 509 01f8 0090D003 		.word	64000000
 510 01fc 00000039 		.word	956301312
 511 0200 0024744A 		.word	1249125376
 512 0204 0024744B 		.word	1265902592
 513 0208 00000000 		.word	D1CorePrescTable
 514 020c 00000000 		.word	SystemD2Clock
 515 0210 00000000 		.word	SystemCoreClock
 516 0214 0024F400 		.word	16000000
 517              		.cfi_endproc
 518              	.LFE336:
 520              		.global	D1CorePrescTable
 521              		.section	.rodata.D1CorePrescTable,"a"
 522              		.align	2
 525              	D1CorePrescTable:
 526 0000 00000000 		.ascii	"\000\000\000\000\001\002\003\004\001\002\003\004\006"
 526      01020304 
 526      01020304 
 526      06
 527 000d 070809   		.ascii	"\007\010\011"
 528              		.global	SystemD2Clock
 529              		.section	.data.SystemD2Clock,"aw"
 530              		.align	2
 533              	SystemD2Clock:
 534 0000 0090D003 		.word	64000000
 535              		.global	SystemCoreClock
 536              		.section	.data.SystemCoreClock,"aw"
 537              		.align	2
 540              	SystemCoreClock:
 541 0000 0090D003 		.word	64000000
 542              		.text
 543              	.Letext0:
 544              		.file 2 "C:/Users/lenex/AppData/Roaming/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-to
 545              		.file 3 "C:/Users/lenex/AppData/Roaming/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-to
 546              		.file 4 "Drivers/CMSIS/Include/core_cm7.h"
 547              		.file 5 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h"
 548              		.file 6 "Drivers/CMSIS/Device/ST/STM32H7xx/Include/stm32h7a3xx.h"
 549              		.file 7 "C:/Users/lenex/AppData/Roaming/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-to
ARM GAS  C:\Users\lenex\AppData\Local\Temp\ccQzuQch.s 			page 19


DEFINED SYMBOLS
                            *ABS*:00000000 system_stm32h7xx.c
C:\Users\lenex\AppData\Local\Temp\ccQzuQch.s:20     .text.SystemInit:00000000 $t
C:\Users\lenex\AppData\Local\Temp\ccQzuQch.s:26     .text.SystemInit:00000000 SystemInit
C:\Users\lenex\AppData\Local\Temp\ccQzuQch.s:144    .text.SystemInit:0000008c $d
C:\Users\lenex\AppData\Local\Temp\ccQzuQch.s:156    .text.SystemCoreClockUpdate:00000000 $t
C:\Users\lenex\AppData\Local\Temp\ccQzuQch.s:162    .text.SystemCoreClockUpdate:00000000 SystemCoreClockUpdate
C:\Users\lenex\AppData\Local\Temp\ccQzuQch.s:186    .text.SystemCoreClockUpdate:00000014 $d
C:\Users\lenex\AppData\Local\Temp\ccQzuQch.s:211    .text.SystemCoreClockUpdate:00000046 $t
C:\Users\lenex\AppData\Local\Temp\ccQzuQch.s:507    .text.SystemCoreClockUpdate:000001f0 $d
C:\Users\lenex\AppData\Local\Temp\ccQzuQch.s:525    .rodata.D1CorePrescTable:00000000 D1CorePrescTable
C:\Users\lenex\AppData\Local\Temp\ccQzuQch.s:533    .data.SystemD2Clock:00000000 SystemD2Clock
C:\Users\lenex\AppData\Local\Temp\ccQzuQch.s:540    .data.SystemCoreClock:00000000 SystemCoreClock
C:\Users\lenex\AppData\Local\Temp\ccQzuQch.s:522    .rodata.D1CorePrescTable:00000000 $d
C:\Users\lenex\AppData\Local\Temp\ccQzuQch.s:530    .data.SystemD2Clock:00000000 $d
C:\Users\lenex\AppData\Local\Temp\ccQzuQch.s:537    .data.SystemCoreClock:00000000 $d

NO UNDEFINED SYMBOLS
