713 lines
25 KiB
C
713 lines
25 KiB
C
/**
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******************************************************************************
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* @file stm32h7xx_hal_dma_ex.c
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* @author MCD Application Team
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* @brief DMA Extension HAL module driver
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* This file provides firmware functions to manage the following
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* functionalities of the DMA Extension peripheral:
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* + Extended features functions
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*
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@verbatim
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==============================================================================
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##### How to use this driver #####
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==============================================================================
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[..]
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The DMA Extension HAL driver can be used as follows:
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(+) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function
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for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode.
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(+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
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(+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
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Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
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to respectively enable/disable the request generator.
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(+) To handle the DMAMUX Interrupts, the function HAL_DMAEx_MUX_IRQHandler should be called from
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the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler or DMAMUX2_OVR_IRQHandler .
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As only one interrupt line is available for all DMAMUX channels and request generators , HAL_DMA_MUX_IRQHandler should be
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called with, as parameter, the appropriate DMA handle as many as used DMAs in the user project
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(exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator)
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-@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.
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-@- When Multi (Double) Buffer mode is enabled, the transfer is circular by default.
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-@- In Multi (Double) buffer mode, it is possible to update the base address for
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the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled.
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-@- Multi (Double) buffer mode is possible with DMA and BDMA instances.
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@endverbatim
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32h7xx_hal.h"
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/** @addtogroup STM32H7xx_HAL_Driver
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* @{
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*/
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/** @defgroup DMAEx DMAEx
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* @brief DMA Extended HAL module driver
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* @{
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*/
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#ifdef HAL_DMA_MODULE_ENABLED
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/* Private types -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private Constants ---------------------------------------------------------*/
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/* Private macros ------------------------------------------------------------*/
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/* Private functions ---------------------------------------------------------*/
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/** @addtogroup DMAEx_Private_Functions
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* @{
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*/
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static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
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/**
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* @}
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*/
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/* Exported functions ---------------------------------------------------------*/
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/** @addtogroup DMAEx_Exported_Functions
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* @{
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*/
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/** @addtogroup DMAEx_Exported_Functions_Group1
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*
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@verbatim
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===============================================================================
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##### Extended features functions #####
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===============================================================================
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[..] This section provides functions allowing to:
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(+) Configure the source, destination address and data length and
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Start MultiBuffer DMA transfer
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(+) Configure the source, destination address and data length and
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Start MultiBuffer DMA transfer with interrupt
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(+) Change on the fly the memory0 or memory1 address.
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(+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
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(+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
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(+) Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
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to respectively enable/disable the request generator.
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(+) Handle DMAMUX interrupts using HAL_DMAEx_MUX_IRQHandler : should be called from
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the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler or DMAMUX2_OVR_IRQHandler
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@endverbatim
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* @{
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*/
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/**
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* @brief Starts the multi_buffer DMA Transfer.
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* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
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* the configuration information for the specified DMA Stream.
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* @param SrcAddress: The source memory Buffer address
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* @param DstAddress: The destination memory Buffer address
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* @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer
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* @param DataLength: The length of data to be transferred from source to destination
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
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{
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HAL_StatusTypeDef status = HAL_OK;
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__IO uint32_t *ifcRegister_Base; /* DMA Stream Interrupt Clear register */
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/* Check the parameters */
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assert_param(IS_DMA_BUFFER_SIZE(DataLength));
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assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
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/* Memory-to-memory transfer not supported in double buffering mode */
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if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
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{
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hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
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status = HAL_ERROR;
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}
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else
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{
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/* Process Locked */
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__HAL_LOCK(hdma);
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if(HAL_DMA_STATE_READY == hdma->State)
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{
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/* Change DMA peripheral state */
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hdma->State = HAL_DMA_STATE_BUSY;
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/* Initialize the error code */
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hdma->ErrorCode = HAL_DMA_ERROR_NONE;
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if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
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{
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/* Enable the Double buffer mode */
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((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_SxCR_DBM;
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/* Configure DMA Stream destination address */
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((DMA_Stream_TypeDef *)hdma->Instance)->M1AR = SecondMemAddress;
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/* Calculate the interrupt clear flag register (IFCR) base address */
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ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 8U));
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/* Clear all flags */
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*ifcRegister_Base = 0x3FUL << (hdma->StreamIndex & 0x1FU);
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}
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else /* BDMA instance(s) */
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{
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/* Enable the Double buffer mode */
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((BDMA_Channel_TypeDef *)hdma->Instance)->CCR |= (BDMA_CCR_DBM | BDMA_CCR_CIRC);
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/* Configure DMA Stream destination address */
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((BDMA_Channel_TypeDef *)hdma->Instance)->CM1AR = SecondMemAddress;
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/* Calculate the interrupt clear flag register (IFCR) base address */
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ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 4U));
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/* Clear all flags */
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*ifcRegister_Base = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU);
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}
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if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
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{
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/* Configure the source, destination address and the data length */
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DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
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/* Clear the DMAMUX synchro overrun flag */
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hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
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if(hdma->DMAmuxRequestGen != 0U)
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{
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/* Clear the DMAMUX request generator overrun flag */
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hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
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}
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}
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/* Enable the peripheral */
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__HAL_DMA_ENABLE(hdma);
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}
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else
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{
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/* Set the error code to busy */
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hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
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/* Return error status */
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status = HAL_ERROR;
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}
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}
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return status;
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}
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/**
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* @brief Starts the multi_buffer DMA Transfer with interrupt enabled.
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* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
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* the configuration information for the specified DMA Stream.
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* @param SrcAddress: The source memory Buffer address
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* @param DstAddress: The destination memory Buffer address
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* @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer
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* @param DataLength: The length of data to be transferred from source to destination
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
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{
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HAL_StatusTypeDef status = HAL_OK;
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__IO uint32_t *ifcRegister_Base; /* DMA Stream Interrupt Clear register */
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/* Check the parameters */
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assert_param(IS_DMA_BUFFER_SIZE(DataLength));
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assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
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/* Memory-to-memory transfer not supported in double buffering mode */
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if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
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{
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hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
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return HAL_ERROR;
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}
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/* Process locked */
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__HAL_LOCK(hdma);
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if(HAL_DMA_STATE_READY == hdma->State)
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{
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/* Change DMA peripheral state */
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hdma->State = HAL_DMA_STATE_BUSY;
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/* Initialize the error code */
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hdma->ErrorCode = HAL_DMA_ERROR_NONE;
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if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
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{
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/* Enable the Double buffer mode */
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((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_SxCR_DBM;
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/* Configure DMA Stream destination address */
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((DMA_Stream_TypeDef *)hdma->Instance)->M1AR = SecondMemAddress;
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/* Calculate the interrupt clear flag register (IFCR) base address */
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ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 8U));
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/* Clear all flags */
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*ifcRegister_Base = 0x3FUL << (hdma->StreamIndex & 0x1FU);
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}
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else /* BDMA instance(s) */
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{
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/* Enable the Double buffer mode */
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((BDMA_Channel_TypeDef *)hdma->Instance)->CCR |= (BDMA_CCR_DBM | BDMA_CCR_CIRC);
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/* Configure DMA Stream destination address */
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((BDMA_Channel_TypeDef *)hdma->Instance)->CM1AR = SecondMemAddress;
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/* Calculate the interrupt clear flag register (IFCR) base address */
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ifcRegister_Base = (uint32_t *)((uint32_t)(hdma->StreamBaseAddress + 4U));
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/* Clear all flags */
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*ifcRegister_Base = (BDMA_ISR_GIF0) << (hdma->StreamIndex & 0x1FU);
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}
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/* Configure the source, destination address and the data length */
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DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
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if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
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{
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/* Clear the DMAMUX synchro overrun flag */
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hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
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if(hdma->DMAmuxRequestGen != 0U)
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{
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/* Clear the DMAMUX request generator overrun flag */
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hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
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}
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}
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if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
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{
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/* Enable Common interrupts*/
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MODIFY_REG(((DMA_Stream_TypeDef *)hdma->Instance)->CR, (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME | DMA_IT_HT), (DMA_IT_TC | DMA_IT_TE | DMA_IT_DME));
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((DMA_Stream_TypeDef *)hdma->Instance)->FCR |= DMA_IT_FE;
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if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
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{
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/*Enable Half Transfer IT if corresponding Callback is set*/
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((DMA_Stream_TypeDef *)hdma->Instance)->CR |= DMA_IT_HT;
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}
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}
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else /* BDMA instance(s) */
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{
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/* Enable Common interrupts*/
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MODIFY_REG(((BDMA_Channel_TypeDef *)hdma->Instance)->CCR, (BDMA_CCR_TCIE | BDMA_CCR_HTIE | BDMA_CCR_TEIE), (BDMA_CCR_TCIE | BDMA_CCR_TEIE));
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if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
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{
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/*Enable Half Transfer IT if corresponding Callback is set*/
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((BDMA_Channel_TypeDef *)hdma->Instance)->CCR |= BDMA_CCR_HTIE;
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}
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}
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if(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance) != 0U) /* No DMAMUX available for BDMA1 */
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{
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/* Check if DMAMUX Synchronization is enabled*/
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if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
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{
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/* Enable DMAMUX sync overrun IT*/
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hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
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}
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if(hdma->DMAmuxRequestGen != 0U)
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{
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/* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
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/* enable the request gen overrun IT*/
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hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
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}
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}
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/* Enable the peripheral */
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__HAL_DMA_ENABLE(hdma);
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}
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else
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{
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/* Set the error code to busy */
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hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
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/* Return error status */
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status = HAL_ERROR;
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}
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return status;
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}
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/**
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* @brief Change the memory0 or memory1 address on the fly.
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* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
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* the configuration information for the specified DMA Stream.
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* @param Address: The new address
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* @param memory: the memory to be changed, This parameter can be one of
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* the following values:
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* MEMORY0 /
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* MEMORY1
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* @note The MEMORY0 address can be changed only when the current transfer use
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* MEMORY1 and the MEMORY1 address can be changed only when the current
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* transfer use MEMORY0.
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)
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{
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if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
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{
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if(memory == MEMORY0)
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{
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/* change the memory0 address */
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((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = Address;
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}
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else
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{
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/* change the memory1 address */
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((DMA_Stream_TypeDef *)hdma->Instance)->M1AR = Address;
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}
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}
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else /* BDMA instance(s) */
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{
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if(memory == MEMORY0)
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{
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/* change the memory0 address */
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((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = Address;
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}
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else
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{
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/* change the memory1 address */
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((BDMA_Channel_TypeDef *)hdma->Instance)->CM1AR = Address;
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}
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}
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return HAL_OK;
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}
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/**
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* @brief Configure the DMAMUX synchronization parameters for a given DMA stream (instance).
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* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
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* the configuration information for the specified DMA Stream.
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* @param pSyncConfig : pointer to HAL_DMA_MuxSyncConfigTypeDef : contains the DMAMUX synchronization parameters
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig)
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{
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uint32_t syncSignalID = 0;
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uint32_t syncPolarity = 0;
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/* Check the parameters */
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assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance));
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assert_param(IS_DMAMUX_SYNC_STATE(pSyncConfig->SyncEnable));
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assert_param(IS_DMAMUX_SYNC_EVENT(pSyncConfig->EventEnable));
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assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber));
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if(pSyncConfig->SyncEnable == ENABLE)
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{
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assert_param(IS_DMAMUX_SYNC_POLARITY(pSyncConfig->SyncPolarity));
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if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
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{
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assert_param(IS_DMA_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID));
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}
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else
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{
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assert_param(IS_BDMA_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID));
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}
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syncSignalID = pSyncConfig->SyncSignalID;
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syncPolarity = pSyncConfig->SyncPolarity;
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}
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/*Check if the DMA state is ready */
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if(hdma->State == HAL_DMA_STATE_READY)
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{
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/* Process Locked */
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__HAL_LOCK(hdma);
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/* Disable the synchronization and event generation before applying a new config */
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CLEAR_BIT(hdma->DMAmuxChannel->CCR,(DMAMUX_CxCR_SE | DMAMUX_CxCR_EGE));
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/* Set the new synchronization parameters (and keep the request ID filled during the Init)*/
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MODIFY_REG( hdma->DMAmuxChannel->CCR, \
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(~DMAMUX_CxCR_DMAREQ_ID) , \
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(syncSignalID << DMAMUX_CxCR_SYNC_ID_Pos) | \
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((pSyncConfig->RequestNumber - 1U) << DMAMUX_CxCR_NBREQ_Pos) | \
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syncPolarity | ((uint32_t)pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos) | \
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((uint32_t)pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos));
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/* Process Locked */
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__HAL_UNLOCK(hdma);
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return HAL_OK;
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}
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else
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{
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/* Set the error code to busy */
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hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
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/* Return error status */
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return HAL_ERROR;
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}
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}
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/**
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* @brief Configure the DMAMUX request generator block used by the given DMA stream (instance).
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* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
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* the configuration information for the specified DMA Stream.
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* @param pRequestGeneratorConfig : pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef :
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* contains the request generator parameters.
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*
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig)
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{
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HAL_StatusTypeDef status;
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HAL_DMA_StateTypeDef temp_state = hdma->State;
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/* Check the parameters */
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assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance));
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if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
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{
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assert_param(IS_DMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID));
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}
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else
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{
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assert_param(IS_BDMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID));
|
|
}
|
|
|
|
|
|
assert_param(IS_DMAMUX_REQUEST_GEN_POLARITY(pRequestGeneratorConfig->Polarity));
|
|
assert_param(IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(pRequestGeneratorConfig->RequestNumber));
|
|
|
|
/* check if the DMA state is ready
|
|
and DMA is using a DMAMUX request generator block
|
|
*/
|
|
if(hdma->DMAmuxRequestGen == 0U)
|
|
{
|
|
/* Set the error code to busy */
|
|
hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
|
|
|
|
/* error status */
|
|
status = HAL_ERROR;
|
|
}
|
|
else if(((hdma->DMAmuxRequestGen->RGCR & DMAMUX_RGxCR_GE) == 0U) && (temp_state == HAL_DMA_STATE_READY))
|
|
{
|
|
/* RequestGenerator must be disable prior to the configuration i.e GE bit is 0 */
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(hdma);
|
|
|
|
/* Set the request generator new parameters */
|
|
hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \
|
|
((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_GNBREQ_Pos)| \
|
|
pRequestGeneratorConfig->Polarity;
|
|
/* Process Locked */
|
|
__HAL_UNLOCK(hdma);
|
|
|
|
return HAL_OK;
|
|
}
|
|
else
|
|
{
|
|
/* Set the error code to busy */
|
|
hdma->ErrorCode = HAL_DMA_ERROR_BUSY;
|
|
|
|
/* error status */
|
|
status = HAL_ERROR;
|
|
}
|
|
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* @brief Enable the DMAMUX request generator block used by the given DMA stream (instance).
|
|
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Stream.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance));
|
|
|
|
/* check if the DMA state is ready
|
|
and DMA is using a DMAMUX request generator block */
|
|
if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0U))
|
|
{
|
|
/* Enable the request generator*/
|
|
hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_GE;
|
|
|
|
return HAL_OK;
|
|
}
|
|
else
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Disable the DMAMUX request generator block used by the given DMA stream (instance).
|
|
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Stream.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_DMA_DMAMUX_ALL_INSTANCE(hdma->Instance));
|
|
|
|
/* check if the DMA state is ready
|
|
and DMA is using a DMAMUX request generator block */
|
|
if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0U))
|
|
{
|
|
/* Disable the request generator*/
|
|
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_GE;
|
|
|
|
return HAL_OK;
|
|
}
|
|
else
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Handles DMAMUX interrupt request.
|
|
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Stream.
|
|
* @retval None
|
|
*/
|
|
void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma)
|
|
{
|
|
/* Check for DMAMUX Synchronization overrun */
|
|
if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
|
|
{
|
|
/* Disable the synchro overrun interrupt */
|
|
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
|
|
|
|
/* Clear the DMAMUX synchro overrun flag */
|
|
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
|
|
|
|
/* Update error code */
|
|
hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
|
|
|
|
if(hdma->XferErrorCallback != NULL)
|
|
{
|
|
/* Transfer error callback */
|
|
hdma->XferErrorCallback(hdma);
|
|
}
|
|
}
|
|
|
|
if(hdma->DMAmuxRequestGen != 0)
|
|
{
|
|
/* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */
|
|
if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
|
|
{
|
|
/* Disable the request gen overrun interrupt */
|
|
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
|
|
|
|
/* Clear the DMAMUX request generator overrun flag */
|
|
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
|
|
|
|
/* Update error code */
|
|
hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
|
|
|
|
if(hdma->XferErrorCallback != NULL)
|
|
{
|
|
/* Transfer error callback */
|
|
hdma->XferErrorCallback(hdma);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @addtogroup DMAEx_Private_Functions
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Set the DMA Transfer parameter.
|
|
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Stream.
|
|
* @param SrcAddress: The source memory Buffer address
|
|
* @param DstAddress: The destination memory Buffer address
|
|
* @param DataLength: The length of data to be transferred from source to destination
|
|
* @retval HAL status
|
|
*/
|
|
static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
|
|
{
|
|
if(IS_DMA_STREAM_INSTANCE(hdma->Instance) != 0U) /* DMA1 or DMA2 instance */
|
|
{
|
|
/* Configure DMA Stream data length */
|
|
((DMA_Stream_TypeDef *)hdma->Instance)->NDTR = DataLength;
|
|
|
|
/* Peripheral to Memory */
|
|
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
|
|
{
|
|
/* Configure DMA Stream destination address */
|
|
((DMA_Stream_TypeDef *)hdma->Instance)->PAR = DstAddress;
|
|
|
|
/* Configure DMA Stream source address */
|
|
((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = SrcAddress;
|
|
}
|
|
/* Memory to Peripheral */
|
|
else
|
|
{
|
|
/* Configure DMA Stream source address */
|
|
((DMA_Stream_TypeDef *)hdma->Instance)->PAR = SrcAddress;
|
|
|
|
/* Configure DMA Stream destination address */
|
|
((DMA_Stream_TypeDef *)hdma->Instance)->M0AR = DstAddress;
|
|
}
|
|
}
|
|
else /* BDMA instance(s) */
|
|
{
|
|
/* Configure DMA Stream data length */
|
|
((BDMA_Channel_TypeDef *)hdma->Instance)->CNDTR = DataLength;
|
|
|
|
/* Peripheral to Memory */
|
|
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
|
|
{
|
|
/* Configure DMA Stream destination address */
|
|
((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = DstAddress;
|
|
|
|
/* Configure DMA Stream source address */
|
|
((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = SrcAddress;
|
|
}
|
|
/* Memory to Peripheral */
|
|
else
|
|
{
|
|
/* Configure DMA Stream source address */
|
|
((BDMA_Channel_TypeDef *)hdma->Instance)->CPAR = SrcAddress;
|
|
|
|
/* Configure DMA Stream destination address */
|
|
((BDMA_Channel_TypeDef *)hdma->Instance)->CM0AR = DstAddress;
|
|
}
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#endif /* HAL_DMA_MODULE_ENABLED */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|