first conversion attempt
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@ -1,8 +1,8 @@
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/**************************************************************************//**
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* @file core_cm23.h
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* @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File
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* @version V5.0.7
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* @date 22. June 2018
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* @version V5.0.8
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* @date 12. November 2018
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******************************************************************************/
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/*
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* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
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@ -81,7 +81,7 @@
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#endif
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#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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#if defined __ARM_PCS_VFP
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#if defined __ARM_FP
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#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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#endif
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@ -1298,7 +1298,7 @@ typedef struct
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#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
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#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
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#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
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#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */
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#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
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#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
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/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
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@ -1328,7 +1328,9 @@ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
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{
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if ((int32_t)(IRQn) >= 0)
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{
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__COMPILER_BARRIER();
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NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
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__COMPILER_BARRIER();
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}
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}
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@ -1627,6 +1629,7 @@ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
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uint32_t *vectors = (uint32_t *)0x0U;
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#endif
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vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
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__DSB();
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}
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