first conversion attempt
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@ -1,8 +1,8 @@
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/**************************************************************************//**
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* @file core_cm1.h
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* @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File
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* @version V1.0.0
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* @date 23. July 2018
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* @version V1.0.1
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* @date 12. November 2018
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******************************************************************************/
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/*
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* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
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@ -81,7 +81,7 @@
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#endif
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#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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#if defined __ARM_PCS_VFP
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#if defined __ARM_FP
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#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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#endif
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@ -651,7 +651,9 @@ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
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{
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if ((int32_t)(IRQn) >= 0)
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{
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__COMPILER_BARRIER();
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NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
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__COMPILER_BARRIER();
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}
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}
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@ -858,6 +860,7 @@ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
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{
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uint32_t *vectors = (uint32_t *)0x0U;
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vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
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/* ARM Application Note 321 states that the M1 does not require the architectural barrier */
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}
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