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adbmsFunctionTest/build/stm32f3xx_hal_pwr.lst
Johnny Hsu d3e8839f9d first commit
2024-10-12 22:13:04 +02:00

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ARM GAS /tmp/cccsSMWX.s page 1
1 .cpu cortex-m4
2 .arch armv7e-m
3 .fpu fpv4-sp-d16
4 .eabi_attribute 27, 1
5 .eabi_attribute 28, 1
6 .eabi_attribute 20, 1
7 .eabi_attribute 21, 1
8 .eabi_attribute 23, 3
9 .eabi_attribute 24, 1
10 .eabi_attribute 25, 1
11 .eabi_attribute 26, 1
12 .eabi_attribute 30, 1
13 .eabi_attribute 34, 1
14 .eabi_attribute 18, 4
15 .file "stm32f3xx_hal_pwr.c"
16 .text
17 .Ltext0:
18 .cfi_sections .debug_frame
19 .file 1 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c"
20 .section .text.HAL_PWR_DeInit,"ax",%progbits
21 .align 1
22 .global HAL_PWR_DeInit
23 .syntax unified
24 .thumb
25 .thumb_func
27 HAL_PWR_DeInit:
28 .LFB123:
1:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
2:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ******************************************************************************
3:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @file stm32f3xx_hal_pwr.c
4:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @author MCD Application Team
5:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief PWR HAL module driver.
6:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This file provides firmware functions to manage the following
7:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * functionalities of the Power Controller (PWR) peripheral:
8:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * + Initialization/de-initialization functions
9:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * + Peripheral Control functions
10:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *
11:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ******************************************************************************
12:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @attention
13:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *
14:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * Copyright (c) 2016 STMicroelectronics.
15:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * All rights reserved.
16:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *
17:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This software is licensed under terms that can be found in the LICENSE file
18:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * in the root directory of this software component.
19:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * If no LICENSE file comes with this software, it is provided AS-IS.
20:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *
21:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ******************************************************************************
22:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
23:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
24:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Includes ------------------------------------------------------------------*/
25:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** #include "stm32f3xx_hal.h"
26:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
27:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** @addtogroup STM32F3xx_HAL_Driver
28:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @{
29:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
30:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
ARM GAS /tmp/cccsSMWX.s page 2
31:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** @defgroup PWR PWR
32:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief PWR HAL module driver
33:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @{
34:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
35:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
36:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** #ifdef HAL_PWR_MODULE_ENABLED
37:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
38:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Private typedef -----------------------------------------------------------*/
39:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Private define ------------------------------------------------------------*/
40:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Private macro -------------------------------------------------------------*/
41:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Private variables ---------------------------------------------------------*/
42:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Private function prototypes -----------------------------------------------*/
43:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Private functions ---------------------------------------------------------*/
44:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
45:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions PWR Exported Functions
46:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @{
47:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
48:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
49:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
50:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Initialization and de-initialization functions
51:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *
52:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** @verbatim
53:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ===============================================================================
54:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ##### Initialization and de-initialization functions #####
55:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ===============================================================================
56:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..]
57:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** After reset, the backup domain (RTC registers, RTC backup data
58:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** registers and backup SRAM) is protected against possible unwanted
59:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** write accesses.
60:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** To enable access to the RTC Domain and RTC registers, proceed as follows:
61:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Enable the Power Controller (PWR) APB1 interface clock using the
62:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __HAL_RCC_PWR_CLK_ENABLE() macro.
63:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
64:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
65:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** @endverbatim
66:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @{
67:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
68:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
69:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
70:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Deinitializes the PWR peripheral registers to their default reset values.
71:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
72:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
73:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_DeInit(void)
74:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
29 .loc 1 74 1 view -0
30 .cfi_startproc
31 @ args = 0, pretend = 0, frame = 0
32 @ frame_needed = 0, uses_anonymous_args = 0
33 @ link register save eliminated.
75:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __HAL_RCC_PWR_FORCE_RESET();
34 .loc 1 75 3 view .LVU1
35 0000 044B ldr r3, .L2
36 0002 1A69 ldr r2, [r3, #16]
37 0004 42F08052 orr r2, r2, #268435456
38 0008 1A61 str r2, [r3, #16]
76:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __HAL_RCC_PWR_RELEASE_RESET();
39 .loc 1 76 3 view .LVU2
ARM GAS /tmp/cccsSMWX.s page 3
40 000a 1A69 ldr r2, [r3, #16]
41 000c 22F08052 bic r2, r2, #268435456
42 0010 1A61 str r2, [r3, #16]
77:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
43 .loc 1 77 1 is_stmt 0 view .LVU3
44 0012 7047 bx lr
45 .L3:
46 .align 2
47 .L2:
48 0014 00100240 .word 1073876992
49 .cfi_endproc
50 .LFE123:
52 .section .text.HAL_PWR_EnableBkUpAccess,"ax",%progbits
53 .align 1
54 .global HAL_PWR_EnableBkUpAccess
55 .syntax unified
56 .thumb
57 .thumb_func
59 HAL_PWR_EnableBkUpAccess:
60 .LFB124:
78:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
79:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
80:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Enables access to the backup domain (RTC registers, RTC
81:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * backup data registers and backup SRAM).
82:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note If the HSE divided by 32 is used as the RTC clock, the
83:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * Backup Domain Access should be kept enabled.
84:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
85:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
86:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnableBkUpAccess(void)
87:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
61 .loc 1 87 1 is_stmt 1 view -0
62 .cfi_startproc
63 @ args = 0, pretend = 0, frame = 0
64 @ frame_needed = 0, uses_anonymous_args = 0
65 @ link register save eliminated.
88:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SET_BIT(PWR->CR, PWR_CR_DBP);
66 .loc 1 88 3 view .LVU5
67 0000 024A ldr r2, .L5
68 0002 1368 ldr r3, [r2]
69 0004 43F48073 orr r3, r3, #256
70 0008 1360 str r3, [r2]
89:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
71 .loc 1 89 1 is_stmt 0 view .LVU6
72 000a 7047 bx lr
73 .L6:
74 .align 2
75 .L5:
76 000c 00700040 .word 1073770496
77 .cfi_endproc
78 .LFE124:
80 .section .text.HAL_PWR_DisableBkUpAccess,"ax",%progbits
81 .align 1
82 .global HAL_PWR_DisableBkUpAccess
83 .syntax unified
84 .thumb
85 .thumb_func
87 HAL_PWR_DisableBkUpAccess:
ARM GAS /tmp/cccsSMWX.s page 4
88 .LFB125:
90:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
91:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
92:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Disables access to the backup domain (RTC registers, RTC
93:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * backup data registers and backup SRAM).
94:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note If the HSE divided by 32 is used as the RTC clock, the
95:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * Backup Domain Access should be kept enabled.
96:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
97:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
98:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_DisableBkUpAccess(void)
99:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
89 .loc 1 99 1 is_stmt 1 view -0
90 .cfi_startproc
91 @ args = 0, pretend = 0, frame = 0
92 @ frame_needed = 0, uses_anonymous_args = 0
93 @ link register save eliminated.
100:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** CLEAR_BIT(PWR->CR, PWR_CR_DBP);
94 .loc 1 100 3 view .LVU8
95 0000 024A ldr r2, .L8
96 0002 1368 ldr r3, [r2]
97 0004 23F48073 bic r3, r3, #256
98 0008 1360 str r3, [r2]
101:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
99 .loc 1 101 1 is_stmt 0 view .LVU9
100 000a 7047 bx lr
101 .L9:
102 .align 2
103 .L8:
104 000c 00700040 .word 1073770496
105 .cfi_endproc
106 .LFE125:
108 .section .text.HAL_PWR_EnableWakeUpPin,"ax",%progbits
109 .align 1
110 .global HAL_PWR_EnableWakeUpPin
111 .syntax unified
112 .thumb
113 .thumb_func
115 HAL_PWR_EnableWakeUpPin:
116 .LVL0:
117 .LFB126:
102:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
103:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
104:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @}
105:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
106:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
107:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
108:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Low Power modes configuration functions
109:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *
110:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** @verbatim
111:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
112:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ===============================================================================
113:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ##### Peripheral Control functions #####
114:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ===============================================================================
115:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
116:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *** WakeUp pin configuration ***
117:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ================================
118:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..]
ARM GAS /tmp/cccsSMWX.s page 5
119:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) WakeUp pin is used to wakeup the system from Standby mode. This pin is
120:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** forced in input pull down configuration and is active on rising edges.
121:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) There are up to three WakeUp pins:
122:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++)WakeUp Pin 1 on PA.00.
123:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++)WakeUp Pin 2 on PC.13 (STM32F303xC, STM32F303xE only).
124:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++)WakeUp Pin 3 on PE.06.
125:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
126:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *** Main and Backup Regulators configuration ***
127:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ================================================
128:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..]
129:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) When the backup domain is supplied by VDD (analog switch connected to VDD)
130:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** the backup SRAM is powered from VDD which replaces the VBAT power supply to
131:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** save battery life.
132:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
133:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) The backup SRAM is not mass erased by a tamper event. It is read
134:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** protected to prevent confidential data, such as cryptographic private
135:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** key, from being accessed. The backup SRAM can be erased only through
136:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** the Flash interface when a protection level change from level 1 to
137:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** level 0 is requested.
138:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** -@- Refer to the description of Read protection (RDP) in the Flash
139:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** programming manual.
140:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
141:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** Refer to the datasheets for more details.
142:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
143:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *** Low Power modes configuration ***
144:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** =====================================
145:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..]
146:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The devices feature 3 low-power modes:
147:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running.
148:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Stop mode: all clocks are stopped, regulator running, regulator
149:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** in low power mode
150:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Standby mode: 1.2V domain powered off (mode not available on STM32F3x8 devices).
151:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
152:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *** Sleep mode ***
153:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ==================
154:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..]
155:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Entry:
156:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_S
157:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** functions with
158:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
159:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
160:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
161:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Exit:
162:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
163:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** controller (NVIC) can wake up the device from Sleep mode.
164:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
165:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *** Stop mode ***
166:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** =================
167:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..]
168:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** In Stop mode, all clocks in the 1.8V domain are stopped, the PLL, the HSI,
169:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** and the HSE RC oscillators are disabled. Internal SRAM and register contents
170:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** are preserved.
171:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The voltage regulator can be configured either in normal or low-power mode to minimize the co
172:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
173:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Entry:
174:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_STOPEN
175:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** function with:
ARM GAS /tmp/cccsSMWX.s page 6
176:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) Main regulator ON or
177:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) Low Power regulator ON.
178:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction or
179:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction
180:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Exit:
181:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
182:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) Some specific communication peripherals (CEC, USART, I2C) interrupts,
183:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** when programmed in wakeup mode (the peripheral must be
184:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** programmed in wakeup mode and the corresponding interrupt vector
185:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** must be enabled in the NVIC).
186:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
187:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *** Standby mode ***
188:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** ====================
189:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..]
190:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The Standby mode allows to achieve the lowest power consumption. It is based
191:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** on the Cortex-M4 deep sleep mode, with the voltage regulator disabled.
192:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The 1.8V domain is consequently powered off. The PLL, the HSI oscillator and
193:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** the HSE oscillator are also switched off. SRAM and register contents are lost
194:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** except for the RTC registers, RTC backup registers, backup SRAM and Standby
195:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** circuitry.
196:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The voltage regulator is OFF.
197:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
198:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Entry:
199:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
200:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Exit:
201:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
202:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
203:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
204:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** *** Auto-wakeup (AWU) from low-power mode ***
205:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** =============================================
206:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** [..]
207:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
208:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** Wakeup event, a tamper event, a time-stamp event, or a comparator event,
209:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** without depending on an external interrupt (Auto-wakeup mode).
210:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
211:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) RTC auto-wakeup (AWU) from the Stop and Standby modes
212:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
213:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
214:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
215:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
216:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
217:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** is necessary to configure the RTC to detect the tamper or time stamp event using the
218:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** HAL_RTC_SetTimeStamp_IT() or HAL_RTC_SetTamper_IT() functions.
219:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
220:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
221:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** configure the RTC to generate the RTC WakeUp event using the HAL_RTC_SetWakeUpTimer_IT()
222:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
223:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+) Comparator auto-wakeup (AWU) from the Stop mode
224:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
225:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (++) To wake up from the Stop mode with a comparator wakeup event, it is necessary to:
226:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+++) Configure the EXTI Line associated with the comparator (example EXTI Line 22 for c
227:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** to be sensitive to to the selected edges (falling, rising or falling
228:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** and rising) (Interrupt or Event modes) using the EXTI_Init() function.
229:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** (+++) Configure the comparator to generate the event.
230:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** @endverbatim
231:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @{
232:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
ARM GAS /tmp/cccsSMWX.s page 7
233:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
234:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
235:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Enables the WakeUp PINx functionality.
236:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @param WakeUpPinx Specifies the Power Wake-Up pin to enable.
237:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This parameter can be value of :
238:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @ref PWR_WakeUp_Pins
239:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
240:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
241:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
242:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
118 .loc 1 242 1 is_stmt 1 view -0
119 .cfi_startproc
120 @ args = 0, pretend = 0, frame = 0
121 @ frame_needed = 0, uses_anonymous_args = 0
122 @ link register save eliminated.
243:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Check the parameters */
244:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
123 .loc 1 244 3 view .LVU11
245:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Enable the EWUPx pin */
246:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SET_BIT(PWR->CSR, WakeUpPinx);
124 .loc 1 246 3 view .LVU12
125 0000 024A ldr r2, .L11
126 0002 5368 ldr r3, [r2, #4]
127 0004 0343 orrs r3, r3, r0
128 0006 5360 str r3, [r2, #4]
247:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
129 .loc 1 247 1 is_stmt 0 view .LVU13
130 0008 7047 bx lr
131 .L12:
132 000a 00BF .align 2
133 .L11:
134 000c 00700040 .word 1073770496
135 .cfi_endproc
136 .LFE126:
138 .section .text.HAL_PWR_DisableWakeUpPin,"ax",%progbits
139 .align 1
140 .global HAL_PWR_DisableWakeUpPin
141 .syntax unified
142 .thumb
143 .thumb_func
145 HAL_PWR_DisableWakeUpPin:
146 .LVL1:
147 .LFB127:
248:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
249:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
250:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Disables the WakeUp PINx functionality.
251:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @param WakeUpPinx Specifies the Power Wake-Up pin to disable.
252:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This parameter can be values of :
253:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @ref PWR_WakeUp_Pins
254:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
255:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
256:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
257:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
148 .loc 1 257 1 is_stmt 1 view -0
149 .cfi_startproc
150 @ args = 0, pretend = 0, frame = 0
151 @ frame_needed = 0, uses_anonymous_args = 0
ARM GAS /tmp/cccsSMWX.s page 8
152 @ link register save eliminated.
258:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Check the parameters */
259:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
153 .loc 1 259 3 view .LVU15
260:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Disable the EWUPx pin */
261:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** CLEAR_BIT(PWR->CSR, WakeUpPinx);
154 .loc 1 261 3 view .LVU16
155 0000 024A ldr r2, .L14
156 0002 5368 ldr r3, [r2, #4]
157 0004 23EA0003 bic r3, r3, r0
158 0008 5360 str r3, [r2, #4]
262:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
159 .loc 1 262 1 is_stmt 0 view .LVU17
160 000a 7047 bx lr
161 .L15:
162 .align 2
163 .L14:
164 000c 00700040 .word 1073770496
165 .cfi_endproc
166 .LFE127:
168 .section .text.HAL_PWR_EnterSLEEPMode,"ax",%progbits
169 .align 1
170 .global HAL_PWR_EnterSLEEPMode
171 .syntax unified
172 .thumb
173 .thumb_func
175 HAL_PWR_EnterSLEEPMode:
176 .LVL2:
177 .LFB128:
263:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
264:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
265:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Enters Sleep mode.
266:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
267:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @param Regulator Specifies the regulator state in SLEEP mode.
268:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This parameter can be one of the following values:
269:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
270:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
271:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note This parameter has no effect in F3 family and is just maintained to
272:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * offer full portability of other STM32 families software.
273:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @param SLEEPEntry Specifies if SLEEP mode is entered with WFI or WFE instruction.
274:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * When WFI entry is used, tick interrupt have to be disabled if not desired as
275:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * the interrupt wake up source.
276:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This parameter can be one of the following values:
277:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
278:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
279:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
280:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
281:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
282:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
178 .loc 1 282 1 is_stmt 1 view -0
179 .cfi_startproc
180 @ args = 0, pretend = 0, frame = 0
181 @ frame_needed = 0, uses_anonymous_args = 0
182 @ link register save eliminated.
283:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Check the parameters */
284:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
183 .loc 1 284 3 view .LVU19
ARM GAS /tmp/cccsSMWX.s page 9
285:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
286:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Prevent unused argument(s) compilation warning */
287:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** UNUSED(Regulator);
184 .loc 1 287 3 view .LVU20
288:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
289:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Clear SLEEPDEEP bit of Cortex System Control Register */
290:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
185 .loc 1 290 3 view .LVU21
186 .loc 1 290 6 is_stmt 0 view .LVU22
187 0000 064A ldr r2, .L20
188 0002 1369 ldr r3, [r2, #16]
189 .loc 1 290 12 view .LVU23
190 0004 23F00403 bic r3, r3, #4
191 0008 1361 str r3, [r2, #16]
291:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
292:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Select SLEEP mode entry -------------------------------------------------*/
293:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
192 .loc 1 293 3 is_stmt 1 view .LVU24
193 .loc 1 293 5 is_stmt 0 view .LVU25
194 000a 0129 cmp r1, #1
195 000c 03D0 beq .L19
294:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
295:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Request Wait For Interrupt */
296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFI();
297:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
298:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** else
299:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
300:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Request Wait For Event */
301:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __SEV();
196 .loc 1 301 5 is_stmt 1 view .LVU26
197 .syntax unified
198 @ 301 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
199 000e 40BF sev
200 @ 0 "" 2
302:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFE();
201 .loc 1 302 5 view .LVU27
202 @ 302 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
203 0010 20BF wfe
204 @ 0 "" 2
303:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFE();
205 .loc 1 303 5 view .LVU28
206 @ 303 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
207 0012 20BF wfe
208 @ 0 "" 2
304:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
305:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
209 .loc 1 305 1 is_stmt 0 view .LVU29
210 .thumb
211 .syntax unified
212 0014 7047 bx lr
213 .L19:
296:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
214 .loc 1 296 5 is_stmt 1 view .LVU30
215 .syntax unified
216 @ 296 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
217 0016 30BF wfi
218 @ 0 "" 2
ARM GAS /tmp/cccsSMWX.s page 10
219 .thumb
220 .syntax unified
221 0018 7047 bx lr
222 .L21:
223 001a 00BF .align 2
224 .L20:
225 001c 00ED00E0 .word -536810240
226 .cfi_endproc
227 .LFE128:
229 .section .text.HAL_PWR_EnterSTOPMode,"ax",%progbits
230 .align 1
231 .global HAL_PWR_EnterSTOPMode
232 .syntax unified
233 .thumb
234 .thumb_func
236 HAL_PWR_EnterSTOPMode:
237 .LVL3:
238 .LFB129:
306:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
307:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
308:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Enters STOP mode.
309:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note In Stop mode, all I/O pins keep the same state as in Run mode.
310:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note When exiting Stop mode by issuing an interrupt or a wakeup event,
311:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * the HSI RC oscillator is selected as system clock.
312:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note When the voltage regulator operates in low power mode, an additional
313:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * startup delay is incurred when waking up from Stop mode.
314:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * By keeping the internal regulator ON during Stop mode, the consumption
315:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * is higher although the startup time is reduced.
316:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @param Regulator Specifies the regulator state in STOP mode.
317:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This parameter can be one of the following values:
318:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_MAINREGULATOR_ON: STOP mode with regulator ON
319:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_LOWPOWERREGULATOR_ON: STOP mode with low power regulator ON
320:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction.
321:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * This parameter can be one of the following values:
322:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_STOPENTRY_WFI:Enter STOP mode with WFI instruction
323:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @arg PWR_STOPENTRY_WFE: Enter STOP mode with WFE instruction
324:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
325:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
326:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
327:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
239 .loc 1 327 1 view -0
240 .cfi_startproc
241 @ args = 0, pretend = 0, frame = 0
242 @ frame_needed = 0, uses_anonymous_args = 0
243 @ link register save eliminated.
328:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** uint32_t tmpreg = 0U;
244 .loc 1 328 3 view .LVU32
329:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
330:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Check the parameters */
331:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** assert_param(IS_PWR_REGULATOR(Regulator));
245 .loc 1 331 3 view .LVU33
332:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
246 .loc 1 332 3 view .LVU34
333:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
334:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Select the regulator state in STOP mode ---------------------------------*/
335:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** tmpreg = PWR->CR;
247 .loc 1 335 3 view .LVU35
ARM GAS /tmp/cccsSMWX.s page 11
248 .loc 1 335 10 is_stmt 0 view .LVU36
249 0000 0B4A ldr r2, .L26
250 0002 1368 ldr r3, [r2]
251 .LVL4:
336:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
337:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Clear PDDS and LPDS bits */
338:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** tmpreg &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS);
252 .loc 1 338 3 is_stmt 1 view .LVU37
253 .loc 1 338 10 is_stmt 0 view .LVU38
254 0004 23F00303 bic r3, r3, #3
255 .LVL5:
339:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
340:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Set LPDS bit according to Regulator value */
341:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** tmpreg |= Regulator;
256 .loc 1 341 3 is_stmt 1 view .LVU39
257 .loc 1 341 10 is_stmt 0 view .LVU40
258 0008 0343 orrs r3, r3, r0
259 .LVL6:
342:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
343:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Store the new value */
344:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** PWR->CR = tmpreg;
260 .loc 1 344 3 is_stmt 1 view .LVU41
261 .loc 1 344 11 is_stmt 0 view .LVU42
262 000a 1360 str r3, [r2]
345:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
346:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */
347:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
263 .loc 1 347 3 is_stmt 1 view .LVU43
264 .loc 1 347 6 is_stmt 0 view .LVU44
265 000c 094A ldr r2, .L26+4
266 000e 1369 ldr r3, [r2, #16]
267 .LVL7:
268 .loc 1 347 12 view .LVU45
269 0010 43F00403 orr r3, r3, #4
270 0014 1361 str r3, [r2, #16]
271 .LVL8:
348:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
349:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Select STOP mode entry --------------------------------------------------*/
350:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** if(STOPEntry == PWR_STOPENTRY_WFI)
272 .loc 1 350 3 is_stmt 1 view .LVU46
273 .loc 1 350 5 is_stmt 0 view .LVU47
274 0016 0129 cmp r1, #1
275 0018 08D0 beq .L25
351:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
352:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Request Wait For Interrupt */
353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFI();
354:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
355:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** else
356:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
357:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Request Wait For Event */
358:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __SEV();
276 .loc 1 358 5 is_stmt 1 view .LVU48
277 .syntax unified
278 @ 358 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
279 001a 40BF sev
280 @ 0 "" 2
359:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFE();
ARM GAS /tmp/cccsSMWX.s page 12
281 .loc 1 359 5 view .LVU49
282 @ 359 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
283 001c 20BF wfe
284 @ 0 "" 2
360:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFE();
285 .loc 1 360 5 view .LVU50
286 @ 360 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
287 001e 20BF wfe
288 @ 0 "" 2
289 .thumb
290 .syntax unified
291 .L24:
361:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
362:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
363:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Reset SLEEPDEEP bit of Cortex System Control Register */
364:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
292 .loc 1 364 3 view .LVU51
293 .loc 1 364 6 is_stmt 0 view .LVU52
294 0020 044A ldr r2, .L26+4
295 0022 1369 ldr r3, [r2, #16]
296 .loc 1 364 12 view .LVU53
297 0024 23F00403 bic r3, r3, #4
298 0028 1361 str r3, [r2, #16]
365:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
299 .loc 1 365 1 view .LVU54
300 002a 7047 bx lr
301 .L25:
353:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
302 .loc 1 353 5 is_stmt 1 view .LVU55
303 .syntax unified
304 @ 353 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
305 002c 30BF wfi
306 @ 0 "" 2
307 .thumb
308 .syntax unified
309 002e F7E7 b .L24
310 .L27:
311 .align 2
312 .L26:
313 0030 00700040 .word 1073770496
314 0034 00ED00E0 .word -536810240
315 .cfi_endproc
316 .LFE129:
318 .section .text.HAL_PWR_EnterSTANDBYMode,"ax",%progbits
319 .align 1
320 .global HAL_PWR_EnterSTANDBYMode
321 .syntax unified
322 .thumb
323 .thumb_func
325 HAL_PWR_EnterSTANDBYMode:
326 .LFB130:
366:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
367:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
368:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Enters STANDBY mode.
369:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note In Standby mode, all I/O pins are high impedance except for:
370:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * - Reset pad (still available),
371:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * - RTC alternate function pins if configured for tamper, time-stamp, RTC
ARM GAS /tmp/cccsSMWX.s page 13
372:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * Alarm out, or RTC clock calibration out,
373:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * - WKUP pins if enabled.
374:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
375:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
376:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnterSTANDBYMode(void)
377:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
327 .loc 1 377 1 view -0
328 .cfi_startproc
329 @ args = 0, pretend = 0, frame = 0
330 @ frame_needed = 0, uses_anonymous_args = 0
331 @ link register save eliminated.
378:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Select STANDBY mode */
379:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** PWR->CR |= PWR_CR_PDDS;
332 .loc 1 379 3 view .LVU57
333 .loc 1 379 6 is_stmt 0 view .LVU58
334 0000 054A ldr r2, .L29
335 0002 1368 ldr r3, [r2]
336 .loc 1 379 11 view .LVU59
337 0004 43F00203 orr r3, r3, #2
338 0008 1360 str r3, [r2]
380:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
381:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */
382:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
339 .loc 1 382 3 is_stmt 1 view .LVU60
340 .loc 1 382 6 is_stmt 0 view .LVU61
341 000a 044A ldr r2, .L29+4
342 000c 1369 ldr r3, [r2, #16]
343 .loc 1 382 12 view .LVU62
344 000e 43F00403 orr r3, r3, #4
345 0012 1361 str r3, [r2, #16]
383:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
384:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* This option is used to ensure that store operations are completed */
385:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** #if defined ( __CC_ARM)
386:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __force_stores();
387:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** #endif
388:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Request Wait For Interrupt */
389:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** __WFI();
346 .loc 1 389 3 is_stmt 1 view .LVU63
347 .syntax unified
348 @ 389 "Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c" 1
349 0014 30BF wfi
350 @ 0 "" 2
390:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
351 .loc 1 390 1 is_stmt 0 view .LVU64
352 .thumb
353 .syntax unified
354 0016 7047 bx lr
355 .L30:
356 .align 2
357 .L29:
358 0018 00700040 .word 1073770496
359 001c 00ED00E0 .word -536810240
360 .cfi_endproc
361 .LFE130:
363 .section .text.HAL_PWR_EnableSleepOnExit,"ax",%progbits
364 .align 1
365 .global HAL_PWR_EnableSleepOnExit
ARM GAS /tmp/cccsSMWX.s page 14
366 .syntax unified
367 .thumb
368 .thumb_func
370 HAL_PWR_EnableSleepOnExit:
371 .LFB131:
391:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
392:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
393:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
394:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
395:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * re-enters SLEEP mode when an interruption handling is over.
396:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * Setting this bit is useful when the processor is expected to run only on
397:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * interruptions handling.
398:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
399:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
400:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnableSleepOnExit(void)
401:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
372 .loc 1 401 1 is_stmt 1 view -0
373 .cfi_startproc
374 @ args = 0, pretend = 0, frame = 0
375 @ frame_needed = 0, uses_anonymous_args = 0
376 @ link register save eliminated.
402:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Set SLEEPONEXIT bit of Cortex System Control Register */
403:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
377 .loc 1 403 3 view .LVU66
378 0000 024A ldr r2, .L32
379 0002 1369 ldr r3, [r2, #16]
380 0004 43F00203 orr r3, r3, #2
381 0008 1361 str r3, [r2, #16]
404:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
382 .loc 1 404 1 is_stmt 0 view .LVU67
383 000a 7047 bx lr
384 .L33:
385 .align 2
386 .L32:
387 000c 00ED00E0 .word -536810240
388 .cfi_endproc
389 .LFE131:
391 .section .text.HAL_PWR_DisableSleepOnExit,"ax",%progbits
392 .align 1
393 .global HAL_PWR_DisableSleepOnExit
394 .syntax unified
395 .thumb
396 .thumb_func
398 HAL_PWR_DisableSleepOnExit:
399 .LFB132:
405:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
406:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
407:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
408:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
409:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
410:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * re-enters SLEEP mode when an interruption handling is over.
411:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
412:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
413:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_DisableSleepOnExit(void)
414:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
400 .loc 1 414 1 is_stmt 1 view -0
401 .cfi_startproc
ARM GAS /tmp/cccsSMWX.s page 15
402 @ args = 0, pretend = 0, frame = 0
403 @ frame_needed = 0, uses_anonymous_args = 0
404 @ link register save eliminated.
415:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Clear SLEEPONEXIT bit of Cortex System Control Register */
416:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
405 .loc 1 416 3 view .LVU69
406 0000 024A ldr r2, .L35
407 0002 1369 ldr r3, [r2, #16]
408 0004 23F00203 bic r3, r3, #2
409 0008 1361 str r3, [r2, #16]
417:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
410 .loc 1 417 1 is_stmt 0 view .LVU70
411 000a 7047 bx lr
412 .L36:
413 .align 2
414 .L35:
415 000c 00ED00E0 .word -536810240
416 .cfi_endproc
417 .LFE132:
419 .section .text.HAL_PWR_EnableSEVOnPend,"ax",%progbits
420 .align 1
421 .global HAL_PWR_EnableSEVOnPend
422 .syntax unified
423 .thumb
424 .thumb_func
426 HAL_PWR_EnableSEVOnPend:
427 .LFB133:
418:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
419:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
420:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
421:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
422:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Enables CORTEX M4 SEVONPEND bit.
423:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
424:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * WFE to wake up when an interrupt moves from inactive to pended.
425:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
426:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
427:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_EnableSEVOnPend(void)
428:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
428 .loc 1 428 1 is_stmt 1 view -0
429 .cfi_startproc
430 @ args = 0, pretend = 0, frame = 0
431 @ frame_needed = 0, uses_anonymous_args = 0
432 @ link register save eliminated.
429:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Set SEVONPEND bit of Cortex System Control Register */
430:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
433 .loc 1 430 3 view .LVU72
434 0000 024A ldr r2, .L38
435 0002 1369 ldr r3, [r2, #16]
436 0004 43F01003 orr r3, r3, #16
437 0008 1361 str r3, [r2, #16]
431:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
438 .loc 1 431 1 is_stmt 0 view .LVU73
439 000a 7047 bx lr
440 .L39:
441 .align 2
442 .L38:
443 000c 00ED00E0 .word -536810240
ARM GAS /tmp/cccsSMWX.s page 16
444 .cfi_endproc
445 .LFE133:
447 .section .text.HAL_PWR_DisableSEVOnPend,"ax",%progbits
448 .align 1
449 .global HAL_PWR_DisableSEVOnPend
450 .syntax unified
451 .thumb
452 .thumb_func
454 HAL_PWR_DisableSEVOnPend:
455 .LFB134:
432:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
433:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c ****
434:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /**
435:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @brief Disables CORTEX M4 SEVONPEND bit.
436:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
437:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * WFE to wake up when an interrupt moves from inactive to pended.
438:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** * @retval None
439:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** */
440:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** void HAL_PWR_DisableSEVOnPend(void)
441:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** {
456 .loc 1 441 1 is_stmt 1 view -0
457 .cfi_startproc
458 @ args = 0, pretend = 0, frame = 0
459 @ frame_needed = 0, uses_anonymous_args = 0
460 @ link register save eliminated.
442:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** /* Clear SEVONPEND bit of Cortex System Control Register */
443:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
461 .loc 1 443 3 view .LVU75
462 0000 024A ldr r2, .L41
463 0002 1369 ldr r3, [r2, #16]
464 0004 23F01003 bic r3, r3, #16
465 0008 1361 str r3, [r2, #16]
444:Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c **** }
466 .loc 1 444 1 is_stmt 0 view .LVU76
467 000a 7047 bx lr
468 .L42:
469 .align 2
470 .L41:
471 000c 00ED00E0 .word -536810240
472 .cfi_endproc
473 .LFE134:
475 .text
476 .Letext0:
477 .file 2 "/home/chiangni/.config/VSCodium/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/
478 .file 3 "/home/chiangni/.config/VSCodium/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/
479 .file 4 "Drivers/CMSIS/Include/core_cm4.h"
480 .file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302x8.h"
ARM GAS /tmp/cccsSMWX.s page 17
DEFINED SYMBOLS
*ABS*:00000000 stm32f3xx_hal_pwr.c
/tmp/cccsSMWX.s:21 .text.HAL_PWR_DeInit:00000000 $t
/tmp/cccsSMWX.s:27 .text.HAL_PWR_DeInit:00000000 HAL_PWR_DeInit
/tmp/cccsSMWX.s:48 .text.HAL_PWR_DeInit:00000014 $d
/tmp/cccsSMWX.s:53 .text.HAL_PWR_EnableBkUpAccess:00000000 $t
/tmp/cccsSMWX.s:59 .text.HAL_PWR_EnableBkUpAccess:00000000 HAL_PWR_EnableBkUpAccess
/tmp/cccsSMWX.s:76 .text.HAL_PWR_EnableBkUpAccess:0000000c $d
/tmp/cccsSMWX.s:81 .text.HAL_PWR_DisableBkUpAccess:00000000 $t
/tmp/cccsSMWX.s:87 .text.HAL_PWR_DisableBkUpAccess:00000000 HAL_PWR_DisableBkUpAccess
/tmp/cccsSMWX.s:104 .text.HAL_PWR_DisableBkUpAccess:0000000c $d
/tmp/cccsSMWX.s:109 .text.HAL_PWR_EnableWakeUpPin:00000000 $t
/tmp/cccsSMWX.s:115 .text.HAL_PWR_EnableWakeUpPin:00000000 HAL_PWR_EnableWakeUpPin
/tmp/cccsSMWX.s:134 .text.HAL_PWR_EnableWakeUpPin:0000000c $d
/tmp/cccsSMWX.s:139 .text.HAL_PWR_DisableWakeUpPin:00000000 $t
/tmp/cccsSMWX.s:145 .text.HAL_PWR_DisableWakeUpPin:00000000 HAL_PWR_DisableWakeUpPin
/tmp/cccsSMWX.s:164 .text.HAL_PWR_DisableWakeUpPin:0000000c $d
/tmp/cccsSMWX.s:169 .text.HAL_PWR_EnterSLEEPMode:00000000 $t
/tmp/cccsSMWX.s:175 .text.HAL_PWR_EnterSLEEPMode:00000000 HAL_PWR_EnterSLEEPMode
/tmp/cccsSMWX.s:225 .text.HAL_PWR_EnterSLEEPMode:0000001c $d
/tmp/cccsSMWX.s:230 .text.HAL_PWR_EnterSTOPMode:00000000 $t
/tmp/cccsSMWX.s:236 .text.HAL_PWR_EnterSTOPMode:00000000 HAL_PWR_EnterSTOPMode
/tmp/cccsSMWX.s:313 .text.HAL_PWR_EnterSTOPMode:00000030 $d
/tmp/cccsSMWX.s:319 .text.HAL_PWR_EnterSTANDBYMode:00000000 $t
/tmp/cccsSMWX.s:325 .text.HAL_PWR_EnterSTANDBYMode:00000000 HAL_PWR_EnterSTANDBYMode
/tmp/cccsSMWX.s:358 .text.HAL_PWR_EnterSTANDBYMode:00000018 $d
/tmp/cccsSMWX.s:364 .text.HAL_PWR_EnableSleepOnExit:00000000 $t
/tmp/cccsSMWX.s:370 .text.HAL_PWR_EnableSleepOnExit:00000000 HAL_PWR_EnableSleepOnExit
/tmp/cccsSMWX.s:387 .text.HAL_PWR_EnableSleepOnExit:0000000c $d
/tmp/cccsSMWX.s:392 .text.HAL_PWR_DisableSleepOnExit:00000000 $t
/tmp/cccsSMWX.s:398 .text.HAL_PWR_DisableSleepOnExit:00000000 HAL_PWR_DisableSleepOnExit
/tmp/cccsSMWX.s:415 .text.HAL_PWR_DisableSleepOnExit:0000000c $d
/tmp/cccsSMWX.s:420 .text.HAL_PWR_EnableSEVOnPend:00000000 $t
/tmp/cccsSMWX.s:426 .text.HAL_PWR_EnableSEVOnPend:00000000 HAL_PWR_EnableSEVOnPend
/tmp/cccsSMWX.s:443 .text.HAL_PWR_EnableSEVOnPend:0000000c $d
/tmp/cccsSMWX.s:448 .text.HAL_PWR_DisableSEVOnPend:00000000 $t
/tmp/cccsSMWX.s:454 .text.HAL_PWR_DisableSEVOnPend:00000000 HAL_PWR_DisableSEVOnPend
/tmp/cccsSMWX.s:471 .text.HAL_PWR_DisableSEVOnPend:0000000c $d
NO UNDEFINED SYMBOLS
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