1034 lines
50 KiB
Plaintext
1034 lines
50 KiB
Plaintext
ARM GAS /tmp/ccAtRMJ3.s page 1
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1 .cpu cortex-m4
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2 .arch armv7e-m
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3 .fpu fpv4-sp-d16
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4 .eabi_attribute 27, 1
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5 .eabi_attribute 28, 1
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6 .eabi_attribute 20, 1
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7 .eabi_attribute 21, 1
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8 .eabi_attribute 23, 3
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9 .eabi_attribute 24, 1
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10 .eabi_attribute 25, 1
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11 .eabi_attribute 26, 1
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12 .eabi_attribute 30, 1
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13 .eabi_attribute 34, 1
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14 .eabi_attribute 18, 4
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15 .file "main.c"
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16 .text
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17 .Ltext0:
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18 .cfi_sections .debug_frame
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19 .file 1 "Core/Src/main.c"
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20 .section .text.MX_GPIO_Init,"ax",%progbits
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21 .align 1
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22 .syntax unified
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23 .thumb
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24 .thumb_func
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26 MX_GPIO_Init:
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27 .LFB126:
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1:Core/Src/main.c **** /* USER CODE BEGIN Header */
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2:Core/Src/main.c **** /**
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3:Core/Src/main.c **** ******************************************************************************
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4:Core/Src/main.c **** * @file : main.c
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5:Core/Src/main.c **** * @brief : Main program body
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6:Core/Src/main.c **** ******************************************************************************
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7:Core/Src/main.c **** * @attention
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8:Core/Src/main.c **** *
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9:Core/Src/main.c **** * Copyright (c) 2024 STMicroelectronics.
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10:Core/Src/main.c **** * All rights reserved.
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11:Core/Src/main.c **** *
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12:Core/Src/main.c **** * This software is licensed under terms that can be found in the LICENSE file
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13:Core/Src/main.c **** * in the root directory of this software component.
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14:Core/Src/main.c **** * If no LICENSE file comes with this software, it is provided AS-IS.
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15:Core/Src/main.c **** *
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16:Core/Src/main.c **** ******************************************************************************
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17:Core/Src/main.c **** */
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18:Core/Src/main.c **** /* USER CODE END Header */
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19:Core/Src/main.c **** /* Includes ------------------------------------------------------------------*/
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20:Core/Src/main.c **** #include "main.h"
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21:Core/Src/main.c ****
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22:Core/Src/main.c **** /* Private includes ----------------------------------------------------------*/
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23:Core/Src/main.c **** /* USER CODE BEGIN Includes */
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24:Core/Src/main.c **** #include "AMS_HighLevel.h"
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25:Core/Src/main.c **** #include "24LC02.h"
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26:Core/Src/main.c **** /* USER CODE END Includes */
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27:Core/Src/main.c ****
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28:Core/Src/main.c **** /* Private typedef -----------------------------------------------------------*/
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29:Core/Src/main.c **** /* USER CODE BEGIN PTD */
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30:Core/Src/main.c ****
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31:Core/Src/main.c **** /* USER CODE END PTD */
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ARM GAS /tmp/ccAtRMJ3.s page 2
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32:Core/Src/main.c ****
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33:Core/Src/main.c **** /* Private define ------------------------------------------------------------*/
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34:Core/Src/main.c **** /* USER CODE BEGIN PD */
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35:Core/Src/main.c ****
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36:Core/Src/main.c **** /* USER CODE END PD */
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37:Core/Src/main.c ****
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38:Core/Src/main.c **** /* Private macro -------------------------------------------------------------*/
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39:Core/Src/main.c **** /* USER CODE BEGIN PM */
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40:Core/Src/main.c ****
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41:Core/Src/main.c **** /* USER CODE END PM */
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42:Core/Src/main.c ****
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43:Core/Src/main.c **** /* Private variables ---------------------------------------------------------*/
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44:Core/Src/main.c **** SPI_HandleTypeDef hspi2;
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45:Core/Src/main.c ****
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46:Core/Src/main.c **** /* USER CODE BEGIN PV */
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47:Core/Src/main.c ****
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48:Core/Src/main.c **** /* USER CODE END PV */
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49:Core/Src/main.c ****
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50:Core/Src/main.c **** /* Private function prototypes -----------------------------------------------*/
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51:Core/Src/main.c **** void SystemClock_Config(void);
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52:Core/Src/main.c **** static void MX_GPIO_Init(void);
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53:Core/Src/main.c **** static void MX_SPI2_Init(void);
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54:Core/Src/main.c **** /* USER CODE BEGIN PFP */
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55:Core/Src/main.c ****
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56:Core/Src/main.c **** /* USER CODE END PFP */
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57:Core/Src/main.c ****
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58:Core/Src/main.c **** /* Private user code ---------------------------------------------------------*/
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59:Core/Src/main.c **** /* USER CODE BEGIN 0 */
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60:Core/Src/main.c ****
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61:Core/Src/main.c **** /* USER CODE END 0 */
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62:Core/Src/main.c ****
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63:Core/Src/main.c **** /**
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64:Core/Src/main.c **** * @brief The application entry point.
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65:Core/Src/main.c **** * @retval int
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66:Core/Src/main.c **** */
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67:Core/Src/main.c **** int main(void)
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68:Core/Src/main.c **** {
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69:Core/Src/main.c ****
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70:Core/Src/main.c **** /* USER CODE BEGIN 1 */
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71:Core/Src/main.c ****
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72:Core/Src/main.c **** /* USER CODE END 1 */
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73:Core/Src/main.c ****
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74:Core/Src/main.c **** /* MCU Configuration--------------------------------------------------------*/
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75:Core/Src/main.c ****
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76:Core/Src/main.c **** /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
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77:Core/Src/main.c **** HAL_Init();
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78:Core/Src/main.c ****
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79:Core/Src/main.c **** /* USER CODE BEGIN Init */
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80:Core/Src/main.c ****
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81:Core/Src/main.c **** /* USER CODE END Init */
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82:Core/Src/main.c ****
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83:Core/Src/main.c **** /* Configure the system clock */
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84:Core/Src/main.c **** SystemClock_Config();
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85:Core/Src/main.c ****
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86:Core/Src/main.c **** /* USER CODE BEGIN SysInit */
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87:Core/Src/main.c ****
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88:Core/Src/main.c **** /* USER CODE END SysInit */
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ARM GAS /tmp/ccAtRMJ3.s page 3
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89:Core/Src/main.c ****
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90:Core/Src/main.c **** /* Initialize all configured peripherals */
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91:Core/Src/main.c **** MX_GPIO_Init();
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92:Core/Src/main.c **** MX_SPI2_Init();
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93:Core/Src/main.c **** /* USER CODE BEGIN 2 */
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94:Core/Src/main.c **** AMS_Init(&hspi2);
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95:Core/Src/main.c **** eeprom_init();
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96:Core/Src/main.c **** /* USER CODE END 2 */
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97:Core/Src/main.c ****
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98:Core/Src/main.c **** /* Infinite loop */
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99:Core/Src/main.c **** /* USER CODE BEGIN WHILE */
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100:Core/Src/main.c **** while (1)
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101:Core/Src/main.c **** {
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102:Core/Src/main.c **** /* USER CODE END WHILE */
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103:Core/Src/main.c ****
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104:Core/Src/main.c **** /* USER CODE BEGIN 3 */
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105:Core/Src/main.c **** AMS_Idle_Loop();
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106:Core/Src/main.c ****
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107:Core/Src/main.c **** }
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108:Core/Src/main.c **** /* USER CODE END 3 */
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109:Core/Src/main.c **** }
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110:Core/Src/main.c ****
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111:Core/Src/main.c **** /**
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112:Core/Src/main.c **** * @brief System Clock Configuration
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113:Core/Src/main.c **** * @retval None
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114:Core/Src/main.c **** */
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115:Core/Src/main.c **** void SystemClock_Config(void)
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116:Core/Src/main.c **** {
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117:Core/Src/main.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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118:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
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119:Core/Src/main.c ****
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120:Core/Src/main.c **** /** Initializes the RCC Oscillators according to the specified parameters
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121:Core/Src/main.c **** * in the RCC_OscInitTypeDef structure.
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122:Core/Src/main.c **** */
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123:Core/Src/main.c **** RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
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124:Core/Src/main.c **** RCC_OscInitStruct.HSIState = RCC_HSI_ON;
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125:Core/Src/main.c **** RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
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126:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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127:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
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128:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL16;
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129:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
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130:Core/Src/main.c **** {
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131:Core/Src/main.c **** Error_Handler();
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132:Core/Src/main.c **** }
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133:Core/Src/main.c ****
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134:Core/Src/main.c **** /** Initializes the CPU, AHB and APB buses clocks
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135:Core/Src/main.c **** */
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136:Core/Src/main.c **** RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
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137:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
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138:Core/Src/main.c **** RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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139:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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140:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
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141:Core/Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
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142:Core/Src/main.c ****
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143:Core/Src/main.c **** if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
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144:Core/Src/main.c **** {
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145:Core/Src/main.c **** Error_Handler();
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ARM GAS /tmp/ccAtRMJ3.s page 4
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146:Core/Src/main.c **** }
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147:Core/Src/main.c **** }
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148:Core/Src/main.c ****
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149:Core/Src/main.c **** /**
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150:Core/Src/main.c **** * @brief SPI2 Initialization Function
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151:Core/Src/main.c **** * @param None
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152:Core/Src/main.c **** * @retval None
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153:Core/Src/main.c **** */
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154:Core/Src/main.c **** static void MX_SPI2_Init(void)
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155:Core/Src/main.c **** {
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156:Core/Src/main.c ****
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157:Core/Src/main.c **** /* USER CODE BEGIN SPI2_Init 0 */
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158:Core/Src/main.c ****
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159:Core/Src/main.c **** /* USER CODE END SPI2_Init 0 */
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160:Core/Src/main.c ****
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161:Core/Src/main.c **** /* USER CODE BEGIN SPI2_Init 1 */
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162:Core/Src/main.c ****
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163:Core/Src/main.c **** /* USER CODE END SPI2_Init 1 */
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164:Core/Src/main.c **** /* SPI2 parameter configuration*/
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165:Core/Src/main.c **** hspi2.Instance = SPI2;
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166:Core/Src/main.c **** hspi2.Init.Mode = SPI_MODE_MASTER;
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167:Core/Src/main.c **** hspi2.Init.Direction = SPI_DIRECTION_2LINES;
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168:Core/Src/main.c **** hspi2.Init.DataSize = SPI_DATASIZE_8BIT;
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169:Core/Src/main.c **** hspi2.Init.CLKPolarity = SPI_POLARITY_LOW;
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170:Core/Src/main.c **** hspi2.Init.CLKPhase = SPI_PHASE_1EDGE;
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171:Core/Src/main.c **** hspi2.Init.NSS = SPI_NSS_SOFT;
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172:Core/Src/main.c **** hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_16;
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173:Core/Src/main.c **** hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB;
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174:Core/Src/main.c **** hspi2.Init.TIMode = SPI_TIMODE_DISABLE;
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175:Core/Src/main.c **** hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
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176:Core/Src/main.c **** hspi2.Init.CRCPolynomial = 7;
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177:Core/Src/main.c **** hspi2.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE;
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178:Core/Src/main.c **** hspi2.Init.NSSPMode = SPI_NSS_PULSE_ENABLE;
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179:Core/Src/main.c **** if (HAL_SPI_Init(&hspi2) != HAL_OK)
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180:Core/Src/main.c **** {
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181:Core/Src/main.c **** Error_Handler();
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182:Core/Src/main.c **** }
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183:Core/Src/main.c **** /* USER CODE BEGIN SPI2_Init 2 */
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184:Core/Src/main.c ****
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185:Core/Src/main.c **** /* USER CODE END SPI2_Init 2 */
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186:Core/Src/main.c ****
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187:Core/Src/main.c **** }
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188:Core/Src/main.c ****
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189:Core/Src/main.c **** /**
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190:Core/Src/main.c **** * @brief GPIO Initialization Function
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191:Core/Src/main.c **** * @param None
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192:Core/Src/main.c **** * @retval None
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193:Core/Src/main.c **** */
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194:Core/Src/main.c **** static void MX_GPIO_Init(void)
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195:Core/Src/main.c **** {
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28 .loc 1 195 1 view -0
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29 .cfi_startproc
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30 @ args = 0, pretend = 0, frame = 40
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31 @ frame_needed = 0, uses_anonymous_args = 0
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32 0000 30B5 push {r4, r5, lr}
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33 .cfi_def_cfa_offset 12
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34 .cfi_offset 4, -12
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ARM GAS /tmp/ccAtRMJ3.s page 5
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35 .cfi_offset 5, -8
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36 .cfi_offset 14, -4
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37 0002 8BB0 sub sp, sp, #44
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38 .cfi_def_cfa_offset 56
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196:Core/Src/main.c **** GPIO_InitTypeDef GPIO_InitStruct = {0};
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39 .loc 1 196 3 view .LVU1
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40 .loc 1 196 20 is_stmt 0 view .LVU2
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41 0004 0024 movs r4, #0
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42 0006 0594 str r4, [sp, #20]
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43 0008 0694 str r4, [sp, #24]
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44 000a 0794 str r4, [sp, #28]
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45 000c 0894 str r4, [sp, #32]
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46 000e 0994 str r4, [sp, #36]
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197:Core/Src/main.c **** /* USER CODE BEGIN MX_GPIO_Init_1 */
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198:Core/Src/main.c **** /* USER CODE END MX_GPIO_Init_1 */
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199:Core/Src/main.c ****
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200:Core/Src/main.c **** /* GPIO Ports Clock Enable */
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201:Core/Src/main.c **** __HAL_RCC_GPIOC_CLK_ENABLE();
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47 .loc 1 201 3 is_stmt 1 view .LVU3
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48 .LBB4:
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49 .loc 1 201 3 view .LVU4
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50 .loc 1 201 3 view .LVU5
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51 0010 274B ldr r3, .L3
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52 0012 5A69 ldr r2, [r3, #20]
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53 0014 42F40022 orr r2, r2, #524288
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54 0018 5A61 str r2, [r3, #20]
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55 .loc 1 201 3 view .LVU6
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56 001a 5A69 ldr r2, [r3, #20]
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57 001c 02F40022 and r2, r2, #524288
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58 0020 0192 str r2, [sp, #4]
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59 .loc 1 201 3 view .LVU7
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60 0022 019A ldr r2, [sp, #4]
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61 .LBE4:
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62 .loc 1 201 3 view .LVU8
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202:Core/Src/main.c **** __HAL_RCC_GPIOF_CLK_ENABLE();
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63 .loc 1 202 3 view .LVU9
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64 .LBB5:
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65 .loc 1 202 3 view .LVU10
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66 .loc 1 202 3 view .LVU11
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67 0024 5A69 ldr r2, [r3, #20]
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68 0026 42F48002 orr r2, r2, #4194304
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69 002a 5A61 str r2, [r3, #20]
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70 .loc 1 202 3 view .LVU12
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71 002c 5A69 ldr r2, [r3, #20]
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72 002e 02F48002 and r2, r2, #4194304
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73 0032 0292 str r2, [sp, #8]
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74 .loc 1 202 3 view .LVU13
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75 0034 029A ldr r2, [sp, #8]
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76 .LBE5:
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77 .loc 1 202 3 view .LVU14
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203:Core/Src/main.c **** __HAL_RCC_GPIOA_CLK_ENABLE();
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78 .loc 1 203 3 view .LVU15
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79 .LBB6:
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80 .loc 1 203 3 view .LVU16
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81 .loc 1 203 3 view .LVU17
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82 0036 5A69 ldr r2, [r3, #20]
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83 0038 42F40032 orr r2, r2, #131072
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ARM GAS /tmp/ccAtRMJ3.s page 6
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84 003c 5A61 str r2, [r3, #20]
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85 .loc 1 203 3 view .LVU18
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86 003e 5A69 ldr r2, [r3, #20]
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87 0040 02F40032 and r2, r2, #131072
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88 0044 0392 str r2, [sp, #12]
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89 .loc 1 203 3 view .LVU19
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90 0046 039A ldr r2, [sp, #12]
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91 .LBE6:
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92 .loc 1 203 3 view .LVU20
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204:Core/Src/main.c **** __HAL_RCC_GPIOB_CLK_ENABLE();
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93 .loc 1 204 3 view .LVU21
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94 .LBB7:
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95 .loc 1 204 3 view .LVU22
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96 .loc 1 204 3 view .LVU23
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97 0048 5A69 ldr r2, [r3, #20]
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98 004a 42F48022 orr r2, r2, #262144
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99 004e 5A61 str r2, [r3, #20]
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100 .loc 1 204 3 view .LVU24
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101 0050 5B69 ldr r3, [r3, #20]
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102 0052 03F48023 and r3, r3, #262144
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103 0056 0493 str r3, [sp, #16]
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104 .loc 1 204 3 view .LVU25
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105 0058 049B ldr r3, [sp, #16]
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106 .LBE7:
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107 .loc 1 204 3 view .LVU26
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205:Core/Src/main.c ****
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206:Core/Src/main.c **** /*Configure GPIO pin Output Level */
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207:Core/Src/main.c **** HAL_GPIO_WritePin(CSB_GPIO_Port, CSB_Pin, GPIO_PIN_RESET);
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108 .loc 1 207 3 view .LVU27
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109 005a 164D ldr r5, .L3+4
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110 005c 2246 mov r2, r4
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111 005e 4021 movs r1, #64
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112 0060 2846 mov r0, r5
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113 0062 FFF7FEFF bl HAL_GPIO_WritePin
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114 .LVL0:
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208:Core/Src/main.c ****
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209:Core/Src/main.c **** /*Configure GPIO pin : B1_Pin */
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210:Core/Src/main.c **** GPIO_InitStruct.Pin = B1_Pin;
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115 .loc 1 210 3 view .LVU28
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116 .loc 1 210 23 is_stmt 0 view .LVU29
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117 0066 4FF40053 mov r3, #8192
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118 006a 0593 str r3, [sp, #20]
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211:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
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119 .loc 1 211 3 is_stmt 1 view .LVU30
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120 .loc 1 211 24 is_stmt 0 view .LVU31
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121 006c 4FF40413 mov r3, #2162688
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122 0070 0693 str r3, [sp, #24]
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212:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
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123 .loc 1 212 3 is_stmt 1 view .LVU32
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124 .loc 1 212 24 is_stmt 0 view .LVU33
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125 0072 0794 str r4, [sp, #28]
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213:Core/Src/main.c **** HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct);
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126 .loc 1 213 3 is_stmt 1 view .LVU34
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||
127 0074 05A9 add r1, sp, #20
|
||
128 0076 1048 ldr r0, .L3+8
|
||
129 0078 FFF7FEFF bl HAL_GPIO_Init
|
||
130 .LVL1:
|
||
ARM GAS /tmp/ccAtRMJ3.s page 7
|
||
|
||
|
||
214:Core/Src/main.c ****
|
||
215:Core/Src/main.c **** /*Configure GPIO pins : USART_TX_Pin USART_RX_Pin */
|
||
216:Core/Src/main.c **** GPIO_InitStruct.Pin = USART_TX_Pin|USART_RX_Pin;
|
||
131 .loc 1 216 3 view .LVU35
|
||
132 .loc 1 216 23 is_stmt 0 view .LVU36
|
||
133 007c 0C23 movs r3, #12
|
||
134 007e 0593 str r3, [sp, #20]
|
||
217:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||
135 .loc 1 217 3 is_stmt 1 view .LVU37
|
||
136 .loc 1 217 24 is_stmt 0 view .LVU38
|
||
137 0080 0223 movs r3, #2
|
||
138 0082 0693 str r3, [sp, #24]
|
||
218:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||
139 .loc 1 218 3 is_stmt 1 view .LVU39
|
||
140 .loc 1 218 24 is_stmt 0 view .LVU40
|
||
141 0084 0794 str r4, [sp, #28]
|
||
219:Core/Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
||
142 .loc 1 219 3 is_stmt 1 view .LVU41
|
||
143 .loc 1 219 25 is_stmt 0 view .LVU42
|
||
144 0086 0894 str r4, [sp, #32]
|
||
220:Core/Src/main.c **** GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
|
||
145 .loc 1 220 3 is_stmt 1 view .LVU43
|
||
146 .loc 1 220 29 is_stmt 0 view .LVU44
|
||
147 0088 0723 movs r3, #7
|
||
148 008a 0993 str r3, [sp, #36]
|
||
221:Core/Src/main.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||
149 .loc 1 221 3 is_stmt 1 view .LVU45
|
||
150 008c 05A9 add r1, sp, #20
|
||
151 008e 4FF09040 mov r0, #1207959552
|
||
152 0092 FFF7FEFF bl HAL_GPIO_Init
|
||
153 .LVL2:
|
||
222:Core/Src/main.c ****
|
||
223:Core/Src/main.c **** /*Configure GPIO pin : CSB_Pin */
|
||
224:Core/Src/main.c **** GPIO_InitStruct.Pin = CSB_Pin;
|
||
154 .loc 1 224 3 view .LVU46
|
||
155 .loc 1 224 23 is_stmt 0 view .LVU47
|
||
156 0096 4023 movs r3, #64
|
||
157 0098 0593 str r3, [sp, #20]
|
||
225:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
||
158 .loc 1 225 3 is_stmt 1 view .LVU48
|
||
159 .loc 1 225 24 is_stmt 0 view .LVU49
|
||
160 009a 0123 movs r3, #1
|
||
161 009c 0693 str r3, [sp, #24]
|
||
226:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||
162 .loc 1 226 3 is_stmt 1 view .LVU50
|
||
163 .loc 1 226 24 is_stmt 0 view .LVU51
|
||
164 009e 0794 str r4, [sp, #28]
|
||
227:Core/Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_MEDIUM;
|
||
165 .loc 1 227 3 is_stmt 1 view .LVU52
|
||
166 .loc 1 227 25 is_stmt 0 view .LVU53
|
||
167 00a0 0893 str r3, [sp, #32]
|
||
228:Core/Src/main.c **** HAL_GPIO_Init(CSB_GPIO_Port, &GPIO_InitStruct);
|
||
168 .loc 1 228 3 is_stmt 1 view .LVU54
|
||
169 00a2 05A9 add r1, sp, #20
|
||
170 00a4 2846 mov r0, r5
|
||
171 00a6 FFF7FEFF bl HAL_GPIO_Init
|
||
172 .LVL3:
|
||
ARM GAS /tmp/ccAtRMJ3.s page 8
|
||
|
||
|
||
229:Core/Src/main.c ****
|
||
230:Core/Src/main.c **** /* USER CODE BEGIN MX_GPIO_Init_2 */
|
||
231:Core/Src/main.c **** /* USER CODE END MX_GPIO_Init_2 */
|
||
232:Core/Src/main.c **** }
|
||
173 .loc 1 232 1 is_stmt 0 view .LVU55
|
||
174 00aa 0BB0 add sp, sp, #44
|
||
175 .cfi_def_cfa_offset 12
|
||
176 @ sp needed
|
||
177 00ac 30BD pop {r4, r5, pc}
|
||
178 .L4:
|
||
179 00ae 00BF .align 2
|
||
180 .L3:
|
||
181 00b0 00100240 .word 1073876992
|
||
182 00b4 00040048 .word 1207960576
|
||
183 00b8 00080048 .word 1207961600
|
||
184 .cfi_endproc
|
||
185 .LFE126:
|
||
187 .section .text.Error_Handler,"ax",%progbits
|
||
188 .align 1
|
||
189 .global Error_Handler
|
||
190 .syntax unified
|
||
191 .thumb
|
||
192 .thumb_func
|
||
194 Error_Handler:
|
||
195 .LFB127:
|
||
233:Core/Src/main.c ****
|
||
234:Core/Src/main.c **** /* USER CODE BEGIN 4 */
|
||
235:Core/Src/main.c ****
|
||
236:Core/Src/main.c **** /* USER CODE END 4 */
|
||
237:Core/Src/main.c ****
|
||
238:Core/Src/main.c **** /**
|
||
239:Core/Src/main.c **** * @brief This function is executed in case of error occurrence.
|
||
240:Core/Src/main.c **** * @retval None
|
||
241:Core/Src/main.c **** */
|
||
242:Core/Src/main.c **** void Error_Handler(void)
|
||
243:Core/Src/main.c **** {
|
||
196 .loc 1 243 1 is_stmt 1 view -0
|
||
197 .cfi_startproc
|
||
198 @ Volatile: function does not return.
|
||
199 @ args = 0, pretend = 0, frame = 0
|
||
200 @ frame_needed = 0, uses_anonymous_args = 0
|
||
201 @ link register save eliminated.
|
||
244:Core/Src/main.c **** /* USER CODE BEGIN Error_Handler_Debug */
|
||
245:Core/Src/main.c **** /* User can add his own implementation to report the HAL error return state */
|
||
246:Core/Src/main.c **** __disable_irq();
|
||
202 .loc 1 246 3 view .LVU57
|
||
203 .LBB8:
|
||
204 .LBI8:
|
||
205 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h"
|
||
1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//**
|
||
2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h
|
||
3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file
|
||
4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.0.4
|
||
5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 09. April 2018
|
||
6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/
|
||
7:Drivers/CMSIS/Include/cmsis_gcc.h **** /*
|
||
8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||
ARM GAS /tmp/ccAtRMJ3.s page 9
|
||
|
||
|
||
9:Drivers/CMSIS/Include/cmsis_gcc.h **** *
|
||
10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0
|
||
11:Drivers/CMSIS/Include/cmsis_gcc.h **** *
|
||
12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may
|
||
13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License.
|
||
14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at
|
||
15:Drivers/CMSIS/Include/cmsis_gcc.h **** *
|
||
16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0
|
||
17:Drivers/CMSIS/Include/cmsis_gcc.h **** *
|
||
18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software
|
||
19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||
20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||
21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and
|
||
22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License.
|
||
23:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
24:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H
|
||
26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H
|
||
27:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */
|
||
29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
|
||
30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion"
|
||
31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion"
|
||
32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter"
|
||
33:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */
|
||
35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin
|
||
36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0)
|
||
37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
38:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */
|
||
40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM
|
||
41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm
|
||
42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE
|
||
44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline
|
||
45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE
|
||
47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline
|
||
48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE
|
||
50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
|
||
51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN
|
||
53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__))
|
||
54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED
|
||
56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used))
|
||
57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK
|
||
59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak))
|
||
60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED
|
||
62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1)))
|
||
63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT
|
||
65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
|
||
ARM GAS /tmp/ccAtRMJ3.s page 10
|
||
|
||
|
||
66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION
|
||
68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1)))
|
||
69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */
|
||
71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
|
||
72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
|
||
73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
|
||
74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; };
|
||
75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
|
||
76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||
77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE
|
||
79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
|
||
80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
|
||
81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
|
||
82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||
83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
|
||
84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))-
|
||
85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ
|
||
87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
|
||
88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
|
||
89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
|
||
90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||
91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
|
||
92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add
|
||
93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE
|
||
95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
|
||
96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
|
||
97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
|
||
98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||
99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
|
||
100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))-
|
||
101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ
|
||
103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push
|
||
104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked"
|
||
105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes"
|
||
106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||
107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop
|
||
108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add
|
||
109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED
|
||
111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x)))
|
||
112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT
|
||
114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict
|
||
115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
|
||
116:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
117:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
118:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */
|
||
119:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface
|
||
120:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||
121:Drivers/CMSIS/Include/cmsis_gcc.h **** @{
|
||
122:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
ARM GAS /tmp/ccAtRMJ3.s page 11
|
||
|
||
|
||
123:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
124:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts
|
||
126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
|
||
127:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes.
|
||
128:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
129:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void)
|
||
130:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
131:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory");
|
||
132:Drivers/CMSIS/Include/cmsis_gcc.h **** }
|
||
133:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
134:Drivers/CMSIS/Include/cmsis_gcc.h ****
|
||
135:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
|
||
136:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts
|
||
137:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting the I-bit in the CPSR.
|
||
138:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes.
|
||
139:Drivers/CMSIS/Include/cmsis_gcc.h **** */
|
||
140:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void)
|
||
206 .loc 2 140 27 view .LVU58
|
||
207 .LBB9:
|
||
141:Drivers/CMSIS/Include/cmsis_gcc.h **** {
|
||
142:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory");
|
||
208 .loc 2 142 3 view .LVU59
|
||
209 .syntax unified
|
||
210 @ 142 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
|
||
211 0000 72B6 cpsid i
|
||
212 @ 0 "" 2
|
||
213 .thumb
|
||
214 .syntax unified
|
||
215 .L6:
|
||
216 .LBE9:
|
||
217 .LBE8:
|
||
247:Core/Src/main.c **** while (1)
|
||
218 .loc 1 247 3 view .LVU60
|
||
248:Core/Src/main.c **** {
|
||
249:Core/Src/main.c **** }
|
||
219 .loc 1 249 3 view .LVU61
|
||
247:Core/Src/main.c **** while (1)
|
||
220 .loc 1 247 9 view .LVU62
|
||
221 0002 FEE7 b .L6
|
||
222 .cfi_endproc
|
||
223 .LFE127:
|
||
225 .section .text.MX_SPI2_Init,"ax",%progbits
|
||
226 .align 1
|
||
227 .syntax unified
|
||
228 .thumb
|
||
229 .thumb_func
|
||
231 MX_SPI2_Init:
|
||
232 .LFB125:
|
||
155:Core/Src/main.c ****
|
||
233 .loc 1 155 1 view -0
|
||
234 .cfi_startproc
|
||
235 @ args = 0, pretend = 0, frame = 0
|
||
236 @ frame_needed = 0, uses_anonymous_args = 0
|
||
237 0000 08B5 push {r3, lr}
|
||
238 .cfi_def_cfa_offset 8
|
||
239 .cfi_offset 3, -8
|
||
ARM GAS /tmp/ccAtRMJ3.s page 12
|
||
|
||
|
||
240 .cfi_offset 14, -4
|
||
165:Core/Src/main.c **** hspi2.Init.Mode = SPI_MODE_MASTER;
|
||
241 .loc 1 165 3 view .LVU64
|
||
165:Core/Src/main.c **** hspi2.Init.Mode = SPI_MODE_MASTER;
|
||
242 .loc 1 165 18 is_stmt 0 view .LVU65
|
||
243 0002 1048 ldr r0, .L11
|
||
244 0004 104B ldr r3, .L11+4
|
||
245 0006 0360 str r3, [r0]
|
||
166:Core/Src/main.c **** hspi2.Init.Direction = SPI_DIRECTION_2LINES;
|
||
246 .loc 1 166 3 is_stmt 1 view .LVU66
|
||
166:Core/Src/main.c **** hspi2.Init.Direction = SPI_DIRECTION_2LINES;
|
||
247 .loc 1 166 19 is_stmt 0 view .LVU67
|
||
248 0008 4FF48273 mov r3, #260
|
||
249 000c 4360 str r3, [r0, #4]
|
||
167:Core/Src/main.c **** hspi2.Init.DataSize = SPI_DATASIZE_8BIT;
|
||
250 .loc 1 167 3 is_stmt 1 view .LVU68
|
||
167:Core/Src/main.c **** hspi2.Init.DataSize = SPI_DATASIZE_8BIT;
|
||
251 .loc 1 167 24 is_stmt 0 view .LVU69
|
||
252 000e 0023 movs r3, #0
|
||
253 0010 8360 str r3, [r0, #8]
|
||
168:Core/Src/main.c **** hspi2.Init.CLKPolarity = SPI_POLARITY_LOW;
|
||
254 .loc 1 168 3 is_stmt 1 view .LVU70
|
||
168:Core/Src/main.c **** hspi2.Init.CLKPolarity = SPI_POLARITY_LOW;
|
||
255 .loc 1 168 23 is_stmt 0 view .LVU71
|
||
256 0012 4FF4E062 mov r2, #1792
|
||
257 0016 C260 str r2, [r0, #12]
|
||
169:Core/Src/main.c **** hspi2.Init.CLKPhase = SPI_PHASE_1EDGE;
|
||
258 .loc 1 169 3 is_stmt 1 view .LVU72
|
||
169:Core/Src/main.c **** hspi2.Init.CLKPhase = SPI_PHASE_1EDGE;
|
||
259 .loc 1 169 26 is_stmt 0 view .LVU73
|
||
260 0018 0361 str r3, [r0, #16]
|
||
170:Core/Src/main.c **** hspi2.Init.NSS = SPI_NSS_SOFT;
|
||
261 .loc 1 170 3 is_stmt 1 view .LVU74
|
||
170:Core/Src/main.c **** hspi2.Init.NSS = SPI_NSS_SOFT;
|
||
262 .loc 1 170 23 is_stmt 0 view .LVU75
|
||
263 001a 4361 str r3, [r0, #20]
|
||
171:Core/Src/main.c **** hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_16;
|
||
264 .loc 1 171 3 is_stmt 1 view .LVU76
|
||
171:Core/Src/main.c **** hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_16;
|
||
265 .loc 1 171 18 is_stmt 0 view .LVU77
|
||
266 001c 4FF40072 mov r2, #512
|
||
267 0020 8261 str r2, [r0, #24]
|
||
172:Core/Src/main.c **** hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB;
|
||
268 .loc 1 172 3 is_stmt 1 view .LVU78
|
||
172:Core/Src/main.c **** hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB;
|
||
269 .loc 1 172 32 is_stmt 0 view .LVU79
|
||
270 0022 1822 movs r2, #24
|
||
271 0024 C261 str r2, [r0, #28]
|
||
173:Core/Src/main.c **** hspi2.Init.TIMode = SPI_TIMODE_DISABLE;
|
||
272 .loc 1 173 3 is_stmt 1 view .LVU80
|
||
173:Core/Src/main.c **** hspi2.Init.TIMode = SPI_TIMODE_DISABLE;
|
||
273 .loc 1 173 23 is_stmt 0 view .LVU81
|
||
274 0026 0362 str r3, [r0, #32]
|
||
174:Core/Src/main.c **** hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
|
||
275 .loc 1 174 3 is_stmt 1 view .LVU82
|
||
174:Core/Src/main.c **** hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
|
||
276 .loc 1 174 21 is_stmt 0 view .LVU83
|
||
ARM GAS /tmp/ccAtRMJ3.s page 13
|
||
|
||
|
||
277 0028 4362 str r3, [r0, #36]
|
||
175:Core/Src/main.c **** hspi2.Init.CRCPolynomial = 7;
|
||
278 .loc 1 175 3 is_stmt 1 view .LVU84
|
||
175:Core/Src/main.c **** hspi2.Init.CRCPolynomial = 7;
|
||
279 .loc 1 175 29 is_stmt 0 view .LVU85
|
||
280 002a 8362 str r3, [r0, #40]
|
||
176:Core/Src/main.c **** hspi2.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE;
|
||
281 .loc 1 176 3 is_stmt 1 view .LVU86
|
||
176:Core/Src/main.c **** hspi2.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE;
|
||
282 .loc 1 176 28 is_stmt 0 view .LVU87
|
||
283 002c 0722 movs r2, #7
|
||
284 002e C262 str r2, [r0, #44]
|
||
177:Core/Src/main.c **** hspi2.Init.NSSPMode = SPI_NSS_PULSE_ENABLE;
|
||
285 .loc 1 177 3 is_stmt 1 view .LVU88
|
||
177:Core/Src/main.c **** hspi2.Init.NSSPMode = SPI_NSS_PULSE_ENABLE;
|
||
286 .loc 1 177 24 is_stmt 0 view .LVU89
|
||
287 0030 0363 str r3, [r0, #48]
|
||
178:Core/Src/main.c **** if (HAL_SPI_Init(&hspi2) != HAL_OK)
|
||
288 .loc 1 178 3 is_stmt 1 view .LVU90
|
||
178:Core/Src/main.c **** if (HAL_SPI_Init(&hspi2) != HAL_OK)
|
||
289 .loc 1 178 23 is_stmt 0 view .LVU91
|
||
290 0032 0823 movs r3, #8
|
||
291 0034 4363 str r3, [r0, #52]
|
||
179:Core/Src/main.c **** {
|
||
292 .loc 1 179 3 is_stmt 1 view .LVU92
|
||
179:Core/Src/main.c **** {
|
||
293 .loc 1 179 7 is_stmt 0 view .LVU93
|
||
294 0036 FFF7FEFF bl HAL_SPI_Init
|
||
295 .LVL4:
|
||
179:Core/Src/main.c **** {
|
||
296 .loc 1 179 6 discriminator 1 view .LVU94
|
||
297 003a 00B9 cbnz r0, .L10
|
||
187:Core/Src/main.c ****
|
||
298 .loc 1 187 1 view .LVU95
|
||
299 003c 08BD pop {r3, pc}
|
||
300 .L10:
|
||
181:Core/Src/main.c **** }
|
||
301 .loc 1 181 5 is_stmt 1 view .LVU96
|
||
302 003e FFF7FEFF bl Error_Handler
|
||
303 .LVL5:
|
||
304 .L12:
|
||
305 0042 00BF .align 2
|
||
306 .L11:
|
||
307 0044 00000000 .word hspi2
|
||
308 0048 00380040 .word 1073756160
|
||
309 .cfi_endproc
|
||
310 .LFE125:
|
||
312 .section .text.SystemClock_Config,"ax",%progbits
|
||
313 .align 1
|
||
314 .global SystemClock_Config
|
||
315 .syntax unified
|
||
316 .thumb
|
||
317 .thumb_func
|
||
319 SystemClock_Config:
|
||
320 .LFB124:
|
||
116:Core/Src/main.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||
321 .loc 1 116 1 view -0
|
||
ARM GAS /tmp/ccAtRMJ3.s page 14
|
||
|
||
|
||
322 .cfi_startproc
|
||
323 @ args = 0, pretend = 0, frame = 64
|
||
324 @ frame_needed = 0, uses_anonymous_args = 0
|
||
325 0000 00B5 push {lr}
|
||
326 .cfi_def_cfa_offset 4
|
||
327 .cfi_offset 14, -4
|
||
328 0002 91B0 sub sp, sp, #68
|
||
329 .cfi_def_cfa_offset 72
|
||
117:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||
330 .loc 1 117 3 view .LVU98
|
||
117:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||
331 .loc 1 117 22 is_stmt 0 view .LVU99
|
||
332 0004 2822 movs r2, #40
|
||
333 0006 0021 movs r1, #0
|
||
334 0008 06A8 add r0, sp, #24
|
||
335 000a FFF7FEFF bl memset
|
||
336 .LVL6:
|
||
118:Core/Src/main.c ****
|
||
337 .loc 1 118 3 is_stmt 1 view .LVU100
|
||
118:Core/Src/main.c ****
|
||
338 .loc 1 118 22 is_stmt 0 view .LVU101
|
||
339 000e 0023 movs r3, #0
|
||
340 0010 0193 str r3, [sp, #4]
|
||
341 0012 0293 str r3, [sp, #8]
|
||
342 0014 0393 str r3, [sp, #12]
|
||
343 0016 0493 str r3, [sp, #16]
|
||
344 0018 0593 str r3, [sp, #20]
|
||
123:Core/Src/main.c **** RCC_OscInitStruct.HSIState = RCC_HSI_ON;
|
||
345 .loc 1 123 3 is_stmt 1 view .LVU102
|
||
123:Core/Src/main.c **** RCC_OscInitStruct.HSIState = RCC_HSI_ON;
|
||
346 .loc 1 123 36 is_stmt 0 view .LVU103
|
||
347 001a 0223 movs r3, #2
|
||
348 001c 0693 str r3, [sp, #24]
|
||
124:Core/Src/main.c **** RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
|
||
349 .loc 1 124 3 is_stmt 1 view .LVU104
|
||
124:Core/Src/main.c **** RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
|
||
350 .loc 1 124 30 is_stmt 0 view .LVU105
|
||
351 001e 0122 movs r2, #1
|
||
352 0020 0A92 str r2, [sp, #40]
|
||
125:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||
353 .loc 1 125 3 is_stmt 1 view .LVU106
|
||
125:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||
354 .loc 1 125 41 is_stmt 0 view .LVU107
|
||
355 0022 1022 movs r2, #16
|
||
356 0024 0B92 str r2, [sp, #44]
|
||
126:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
|
||
357 .loc 1 126 3 is_stmt 1 view .LVU108
|
||
126:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
|
||
358 .loc 1 126 34 is_stmt 0 view .LVU109
|
||
359 0026 0D93 str r3, [sp, #52]
|
||
127:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL16;
|
||
360 .loc 1 127 3 is_stmt 1 view .LVU110
|
||
128:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
||
361 .loc 1 128 3 view .LVU111
|
||
128:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
||
362 .loc 1 128 32 is_stmt 0 view .LVU112
|
||
363 0028 4FF46013 mov r3, #3670016
|
||
ARM GAS /tmp/ccAtRMJ3.s page 15
|
||
|
||
|
||
364 002c 0F93 str r3, [sp, #60]
|
||
129:Core/Src/main.c **** {
|
||
365 .loc 1 129 3 is_stmt 1 view .LVU113
|
||
129:Core/Src/main.c **** {
|
||
366 .loc 1 129 7 is_stmt 0 view .LVU114
|
||
367 002e 06A8 add r0, sp, #24
|
||
368 0030 FFF7FEFF bl HAL_RCC_OscConfig
|
||
369 .LVL7:
|
||
129:Core/Src/main.c **** {
|
||
370 .loc 1 129 6 discriminator 1 view .LVU115
|
||
371 0034 80B9 cbnz r0, .L17
|
||
136:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
|
||
372 .loc 1 136 3 is_stmt 1 view .LVU116
|
||
136:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
|
||
373 .loc 1 136 31 is_stmt 0 view .LVU117
|
||
374 0036 0F23 movs r3, #15
|
||
375 0038 0193 str r3, [sp, #4]
|
||
138:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
|
||
376 .loc 1 138 3 is_stmt 1 view .LVU118
|
||
138:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
|
||
377 .loc 1 138 34 is_stmt 0 view .LVU119
|
||
378 003a 0221 movs r1, #2
|
||
379 003c 0291 str r1, [sp, #8]
|
||
139:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
|
||
380 .loc 1 139 3 is_stmt 1 view .LVU120
|
||
139:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
|
||
381 .loc 1 139 35 is_stmt 0 view .LVU121
|
||
382 003e 0023 movs r3, #0
|
||
383 0040 0393 str r3, [sp, #12]
|
||
140:Core/Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
|
||
384 .loc 1 140 3 is_stmt 1 view .LVU122
|
||
140:Core/Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
|
||
385 .loc 1 140 36 is_stmt 0 view .LVU123
|
||
386 0042 4FF48062 mov r2, #1024
|
||
387 0046 0492 str r2, [sp, #16]
|
||
141:Core/Src/main.c ****
|
||
388 .loc 1 141 3 is_stmt 1 view .LVU124
|
||
141:Core/Src/main.c ****
|
||
389 .loc 1 141 36 is_stmt 0 view .LVU125
|
||
390 0048 0593 str r3, [sp, #20]
|
||
143:Core/Src/main.c **** {
|
||
391 .loc 1 143 3 is_stmt 1 view .LVU126
|
||
143:Core/Src/main.c **** {
|
||
392 .loc 1 143 7 is_stmt 0 view .LVU127
|
||
393 004a 01A8 add r0, sp, #4
|
||
394 004c FFF7FEFF bl HAL_RCC_ClockConfig
|
||
395 .LVL8:
|
||
143:Core/Src/main.c **** {
|
||
396 .loc 1 143 6 discriminator 1 view .LVU128
|
||
397 0050 20B9 cbnz r0, .L18
|
||
147:Core/Src/main.c ****
|
||
398 .loc 1 147 1 view .LVU129
|
||
399 0052 11B0 add sp, sp, #68
|
||
400 .cfi_remember_state
|
||
401 .cfi_def_cfa_offset 4
|
||
402 @ sp needed
|
||
403 0054 5DF804FB ldr pc, [sp], #4
|
||
ARM GAS /tmp/ccAtRMJ3.s page 16
|
||
|
||
|
||
404 .L17:
|
||
405 .cfi_restore_state
|
||
131:Core/Src/main.c **** }
|
||
406 .loc 1 131 5 is_stmt 1 view .LVU130
|
||
407 0058 FFF7FEFF bl Error_Handler
|
||
408 .LVL9:
|
||
409 .L18:
|
||
145:Core/Src/main.c **** }
|
||
410 .loc 1 145 5 view .LVU131
|
||
411 005c FFF7FEFF bl Error_Handler
|
||
412 .LVL10:
|
||
413 .cfi_endproc
|
||
414 .LFE124:
|
||
416 .section .text.main,"ax",%progbits
|
||
417 .align 1
|
||
418 .global main
|
||
419 .syntax unified
|
||
420 .thumb
|
||
421 .thumb_func
|
||
423 main:
|
||
424 .LFB123:
|
||
68:Core/Src/main.c ****
|
||
425 .loc 1 68 1 view -0
|
||
426 .cfi_startproc
|
||
427 @ Volatile: function does not return.
|
||
428 @ args = 0, pretend = 0, frame = 0
|
||
429 @ frame_needed = 0, uses_anonymous_args = 0
|
||
430 0000 08B5 push {r3, lr}
|
||
431 .cfi_def_cfa_offset 8
|
||
432 .cfi_offset 3, -8
|
||
433 .cfi_offset 14, -4
|
||
77:Core/Src/main.c ****
|
||
434 .loc 1 77 3 view .LVU133
|
||
435 0002 FFF7FEFF bl HAL_Init
|
||
436 .LVL11:
|
||
84:Core/Src/main.c ****
|
||
437 .loc 1 84 3 view .LVU134
|
||
438 0006 FFF7FEFF bl SystemClock_Config
|
||
439 .LVL12:
|
||
91:Core/Src/main.c **** MX_SPI2_Init();
|
||
440 .loc 1 91 3 view .LVU135
|
||
441 000a FFF7FEFF bl MX_GPIO_Init
|
||
442 .LVL13:
|
||
92:Core/Src/main.c **** /* USER CODE BEGIN 2 */
|
||
443 .loc 1 92 3 view .LVU136
|
||
444 000e FFF7FEFF bl MX_SPI2_Init
|
||
445 .LVL14:
|
||
94:Core/Src/main.c **** eeprom_init();
|
||
446 .loc 1 94 3 view .LVU137
|
||
447 0012 0448 ldr r0, .L22
|
||
448 0014 FFF7FEFF bl AMS_Init
|
||
449 .LVL15:
|
||
95:Core/Src/main.c **** /* USER CODE END 2 */
|
||
450 .loc 1 95 3 view .LVU138
|
||
451 0018 FFF7FEFF bl eeprom_init
|
||
452 .LVL16:
|
||
453 .L20:
|
||
ARM GAS /tmp/ccAtRMJ3.s page 17
|
||
|
||
|
||
100:Core/Src/main.c **** {
|
||
454 .loc 1 100 3 view .LVU139
|
||
105:Core/Src/main.c ****
|
||
455 .loc 1 105 5 discriminator 1 view .LVU140
|
||
456 001c FFF7FEFF bl AMS_Idle_Loop
|
||
457 .LVL17:
|
||
100:Core/Src/main.c **** {
|
||
458 .loc 1 100 9 view .LVU141
|
||
459 0020 FCE7 b .L20
|
||
460 .L23:
|
||
461 0022 00BF .align 2
|
||
462 .L22:
|
||
463 0024 00000000 .word hspi2
|
||
464 .cfi_endproc
|
||
465 .LFE123:
|
||
467 .global hspi2
|
||
468 .section .bss.hspi2,"aw",%nobits
|
||
469 .align 2
|
||
472 hspi2:
|
||
473 0000 00000000 .space 100
|
||
473 00000000
|
||
473 00000000
|
||
473 00000000
|
||
473 00000000
|
||
474 .text
|
||
475 .Letext0:
|
||
476 .file 3 "/home/chiangni/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-
|
||
477 .file 4 "/home/chiangni/.config/Code/User/globalStorage/bmd.stm32-for-vscode/@xpack-dev-tools/arm-
|
||
478 .file 5 "Drivers/CMSIS/Device/ST/STM32F3xx/Include/stm32f302x8.h"
|
||
479 .file 6 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_def.h"
|
||
480 .file 7 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_rcc.h"
|
||
481 .file 8 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_gpio.h"
|
||
482 .file 9 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_dma.h"
|
||
483 .file 10 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h"
|
||
484 .file 11 "Core/Inc/AMS_HighLevel.h"
|
||
485 .file 12 "Core/Inc/24LC02.h"
|
||
486 .file 13 "Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal.h"
|
||
487 .file 14 "<built-in>"
|
||
ARM GAS /tmp/ccAtRMJ3.s page 18
|
||
|
||
|
||
DEFINED SYMBOLS
|
||
*ABS*:00000000 main.c
|
||
/tmp/ccAtRMJ3.s:21 .text.MX_GPIO_Init:00000000 $t
|
||
/tmp/ccAtRMJ3.s:26 .text.MX_GPIO_Init:00000000 MX_GPIO_Init
|
||
/tmp/ccAtRMJ3.s:181 .text.MX_GPIO_Init:000000b0 $d
|
||
/tmp/ccAtRMJ3.s:188 .text.Error_Handler:00000000 $t
|
||
/tmp/ccAtRMJ3.s:194 .text.Error_Handler:00000000 Error_Handler
|
||
/tmp/ccAtRMJ3.s:226 .text.MX_SPI2_Init:00000000 $t
|
||
/tmp/ccAtRMJ3.s:231 .text.MX_SPI2_Init:00000000 MX_SPI2_Init
|
||
/tmp/ccAtRMJ3.s:307 .text.MX_SPI2_Init:00000044 $d
|
||
/tmp/ccAtRMJ3.s:472 .bss.hspi2:00000000 hspi2
|
||
/tmp/ccAtRMJ3.s:313 .text.SystemClock_Config:00000000 $t
|
||
/tmp/ccAtRMJ3.s:319 .text.SystemClock_Config:00000000 SystemClock_Config
|
||
/tmp/ccAtRMJ3.s:417 .text.main:00000000 $t
|
||
/tmp/ccAtRMJ3.s:423 .text.main:00000000 main
|
||
/tmp/ccAtRMJ3.s:463 .text.main:00000024 $d
|
||
/tmp/ccAtRMJ3.s:469 .bss.hspi2:00000000 $d
|
||
|
||
UNDEFINED SYMBOLS
|
||
HAL_GPIO_WritePin
|
||
HAL_GPIO_Init
|
||
HAL_SPI_Init
|
||
memset
|
||
HAL_RCC_OscConfig
|
||
HAL_RCC_ClockConfig
|
||
HAL_Init
|
||
AMS_Init
|
||
eeprom_init
|
||
AMS_Idle_Loop
|