2316 lines
74 KiB
C
2316 lines
74 KiB
C
/**
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******************************************************************************
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* @file stm32f3xx_hal_nand.c
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* @author MCD Application Team
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* @brief NAND HAL module driver.
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* This file provides a generic firmware to drive NAND memories mounted
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* as external device.
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*
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2016 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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@verbatim
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==============================================================================
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##### How to use this driver #####
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==============================================================================
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[..]
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This driver is a generic layered driver which contains a set of APIs used to
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control NAND flash memories. It uses the FMC layer functions to interface
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with NAND devices. This driver is used as follows:
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(+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
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with control and timing parameters for both common and attribute spaces.
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(+) Read NAND flash memory maker and device IDs using the function
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HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
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structure declared by the function caller.
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(+) Access NAND flash memory by read/write operations using the functions
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HAL_NAND_Read_Page_8b()/HAL_NAND_Read_SpareArea_8b(),
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HAL_NAND_Write_Page_8b()/HAL_NAND_Write_SpareArea_8b(),
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HAL_NAND_Read_Page_16b()/HAL_NAND_Read_SpareArea_16b(),
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HAL_NAND_Write_Page_16b()/HAL_NAND_Write_SpareArea_16b()
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to read/write page(s)/spare area(s). These functions use specific device
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information (Block, page size..) predefined by the user in the NAND_DeviceConfigTypeDef
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structure. The read/write address information is contained by the Nand_Address_Typedef
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structure passed as parameter.
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(+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().
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(+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
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The erase block address information is contained in the Nand_Address_Typedef
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structure passed as parameter.
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(+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().
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(+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
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HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
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feature or the function HAL_NAND_GetECC() to get the ECC correction code.
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(+) You can monitor the NAND device HAL state by calling the function
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HAL_NAND_GetState()
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[..]
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(@) This driver is a set of generic APIs which handle standard NAND flash operations.
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If a NAND flash device contains different operations and/or implementations,
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it should be implemented separately.
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*** Callback registration ***
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=============================================
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[..]
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The compilation define USE_HAL_NAND_REGISTER_CALLBACKS when set to 1
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allows the user to configure dynamically the driver callbacks.
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Use Functions HAL_NAND_RegisterCallback() to register a user callback,
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it allows to register following callbacks:
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(+) MspInitCallback : NAND MspInit.
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(+) MspDeInitCallback : NAND MspDeInit.
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This function takes as parameters the HAL peripheral handle, the Callback ID
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and a pointer to the user callback function.
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Use function HAL_NAND_UnRegisterCallback() to reset a callback to the default
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weak (overridden) function. It allows to reset following callbacks:
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(+) MspInitCallback : NAND MspInit.
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(+) MspDeInitCallback : NAND MspDeInit.
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This function) takes as parameters the HAL peripheral handle and the Callback ID.
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By default, after the HAL_NAND_Init and if the state is HAL_NAND_STATE_RESET
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all callbacks are reset to the corresponding legacy weak (overridden) functions.
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Exception done for MspInit and MspDeInit callbacks that are respectively
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reset to the legacy weak (overridden) functions in the HAL_NAND_Init
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and HAL_NAND_DeInit only when these callbacks are null (not registered beforehand).
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If not, MspInit or MspDeInit are not null, the HAL_NAND_Init and HAL_NAND_DeInit
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keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
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Callbacks can be registered/unregistered in READY state only.
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Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
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in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
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during the Init/DeInit.
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In that case first register the MspInit/MspDeInit user callbacks
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using HAL_NAND_RegisterCallback before calling HAL_NAND_DeInit
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or HAL_NAND_Init function.
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When The compilation define USE_HAL_NAND_REGISTER_CALLBACKS is set to 0 or
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not defined, the callback registering feature is not available
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and weak (overridden) callbacks are used.
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@endverbatim
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f3xx_hal.h"
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#if defined(FMC_BANK3)
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/** @addtogroup STM32F3xx_HAL_Driver
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* @{
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*/
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#ifdef HAL_NAND_MODULE_ENABLED
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/** @defgroup NAND NAND
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* @brief NAND HAL module driver
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* @{
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*/
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/* Private typedef -----------------------------------------------------------*/
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/* Private Constants ------------------------------------------------------------*/
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/* Exported functions ---------------------------------------------------------*/
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/** @defgroup NAND_Exported_Functions NAND Exported Functions
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* @{
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*/
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/** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
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* @brief Initialization and Configuration functions
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*
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@verbatim
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==============================================================================
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##### NAND Initialization and de-initialization functions #####
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==============================================================================
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[..]
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This section provides functions allowing to initialize/de-initialize
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the NAND memory
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@endverbatim
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* @{
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*/
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/**
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* @brief Perform NAND memory Initialization sequence
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* @param hnand pointer to a NAND_HandleTypeDef structure that contains
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* the configuration information for NAND module.
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* @param ComSpace_Timing pointer to Common space timing structure
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* @param AttSpace_Timing pointer to Attribute space timing structure
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing,
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FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
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{
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/* Check the NAND handle state */
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if (hnand == NULL)
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{
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return HAL_ERROR;
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}
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if (hnand->State == HAL_NAND_STATE_RESET)
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{
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/* Allocate lock resource and initialize it */
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hnand->Lock = HAL_UNLOCKED;
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#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
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if (hnand->MspInitCallback == NULL)
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{
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hnand->MspInitCallback = HAL_NAND_MspInit;
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}
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hnand->ItCallback = HAL_NAND_ITCallback;
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/* Init the low level hardware */
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hnand->MspInitCallback(hnand);
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#else
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/* Initialize the low level hardware (MSP) */
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HAL_NAND_MspInit(hnand);
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#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
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}
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/* Initialize NAND control Interface */
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(void)FMC_NAND_Init(hnand->Instance, &(hnand->Init));
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/* Initialize NAND common space timing Interface */
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(void)FMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
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/* Initialize NAND attribute space timing Interface */
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(void)FMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
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/* Enable the NAND device */
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__FMC_NAND_ENABLE(hnand->Instance, hnand->Init.NandBank);
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/* Update the NAND controller state */
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hnand->State = HAL_NAND_STATE_READY;
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return HAL_OK;
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}
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/**
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* @brief Perform NAND memory De-Initialization sequence
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* @param hnand pointer to a NAND_HandleTypeDef structure that contains
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* the configuration information for NAND module.
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
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{
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#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
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if (hnand->MspDeInitCallback == NULL)
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{
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hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
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}
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/* DeInit the low level hardware */
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hnand->MspDeInitCallback(hnand);
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#else
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/* Initialize the low level hardware (MSP) */
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HAL_NAND_MspDeInit(hnand);
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#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
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/* Configure the NAND registers with their reset values */
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(void)FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
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/* Reset the NAND controller state */
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hnand->State = HAL_NAND_STATE_RESET;
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/* Release Lock */
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__HAL_UNLOCK(hnand);
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return HAL_OK;
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}
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/**
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* @brief NAND MSP Init
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* @param hnand pointer to a NAND_HandleTypeDef structure that contains
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* the configuration information for NAND module.
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* @retval None
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*/
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__weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
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{
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/* Prevent unused argument(s) compilation warning */
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UNUSED(hnand);
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/* NOTE : This function Should not be modified, when the callback is needed,
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the HAL_NAND_MspInit could be implemented in the user file
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*/
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}
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/**
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* @brief NAND MSP DeInit
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* @param hnand pointer to a NAND_HandleTypeDef structure that contains
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* the configuration information for NAND module.
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* @retval None
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*/
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__weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
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{
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/* Prevent unused argument(s) compilation warning */
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UNUSED(hnand);
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/* NOTE : This function Should not be modified, when the callback is needed,
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the HAL_NAND_MspDeInit could be implemented in the user file
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*/
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}
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/**
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* @brief This function handles NAND device interrupt request.
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* @param hnand pointer to a NAND_HandleTypeDef structure that contains
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* the configuration information for NAND module.
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* @retval HAL status
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*/
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void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
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{
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/* Check NAND interrupt Rising edge flag */
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if (__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE))
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{
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/* NAND interrupt callback*/
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#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
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hnand->ItCallback(hnand);
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#else
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HAL_NAND_ITCallback(hnand);
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#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
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/* Clear NAND interrupt Rising edge pending bit */
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__FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE);
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}
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/* Check NAND interrupt Level flag */
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if (__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL))
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{
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/* NAND interrupt callback*/
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#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
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hnand->ItCallback(hnand);
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#else
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HAL_NAND_ITCallback(hnand);
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#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
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/* Clear NAND interrupt Level pending bit */
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__FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL);
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}
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/* Check NAND interrupt Falling edge flag */
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if (__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE))
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{
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/* NAND interrupt callback*/
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#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
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hnand->ItCallback(hnand);
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#else
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HAL_NAND_ITCallback(hnand);
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#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
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/* Clear NAND interrupt Falling edge pending bit */
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__FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE);
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}
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/* Check NAND interrupt FIFO empty flag */
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if (__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT))
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{
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/* NAND interrupt callback*/
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#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
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hnand->ItCallback(hnand);
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#else
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HAL_NAND_ITCallback(hnand);
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#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */
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/* Clear NAND interrupt FIFO empty pending bit */
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__FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT);
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}
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}
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/**
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* @brief NAND interrupt feature callback
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* @param hnand pointer to a NAND_HandleTypeDef structure that contains
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* the configuration information for NAND module.
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* @retval None
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*/
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__weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
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{
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/* Prevent unused argument(s) compilation warning */
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UNUSED(hnand);
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/* NOTE : This function Should not be modified, when the callback is needed,
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the HAL_NAND_ITCallback could be implemented in the user file
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*/
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}
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/**
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* @}
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*/
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/** @defgroup NAND_Exported_Functions_Group2 Input and Output functions
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* @brief Input Output and memory control functions
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*
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@verbatim
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==============================================================================
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##### NAND Input and Output functions #####
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==============================================================================
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[..]
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This section provides functions allowing to use and control the NAND
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memory
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@endverbatim
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* @{
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*/
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/**
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* @brief Read the NAND memory electronic signature
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* @param hnand pointer to a NAND_HandleTypeDef structure that contains
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* the configuration information for NAND module.
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* @param pNAND_ID NAND ID structure
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
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{
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__IO uint32_t data = 0;
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__IO uint32_t data1 = 0;
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uint32_t deviceaddress;
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/* Check the NAND controller state */
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if (hnand->State == HAL_NAND_STATE_BUSY)
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{
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return HAL_BUSY;
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}
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else if (hnand->State == HAL_NAND_STATE_READY)
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{
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/* Process Locked */
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__HAL_LOCK(hnand);
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/* Update the NAND controller state */
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hnand->State = HAL_NAND_STATE_BUSY;
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/* Identify the device address */
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if (hnand->Init.NandBank == FMC_NAND_BANK2)
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{
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deviceaddress = NAND_DEVICE1;
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}
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else
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{
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deviceaddress = NAND_DEVICE2;
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}
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/* Send Read ID command sequence */
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*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_READID;
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__DSB();
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*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
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__DSB();
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/* Read the electronic signature from NAND flash */
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if (hnand->Init.MemoryDataWidth == FMC_NAND_PCC_MEM_BUS_WIDTH_8)
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{
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data = *(__IO uint32_t *)deviceaddress;
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/* Return the data read */
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pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
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pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data);
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pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data);
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pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data);
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}
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else
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{
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data = *(__IO uint32_t *)deviceaddress;
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data1 = *((__IO uint32_t *)deviceaddress + 4);
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/* Return the data read */
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pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
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pNAND_ID->Device_Id = ADDR_3RD_CYCLE(data);
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pNAND_ID->Third_Id = ADDR_1ST_CYCLE(data1);
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pNAND_ID->Fourth_Id = ADDR_3RD_CYCLE(data1);
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}
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/* Update the NAND controller state */
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hnand->State = HAL_NAND_STATE_READY;
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/* Process unlocked */
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__HAL_UNLOCK(hnand);
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}
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else
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{
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return HAL_ERROR;
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}
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return HAL_OK;
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}
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/**
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* @brief NAND memory reset
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* @param hnand pointer to a NAND_HandleTypeDef structure that contains
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* the configuration information for NAND module.
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
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{
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uint32_t deviceaddress;
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/* Check the NAND controller state */
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if (hnand->State == HAL_NAND_STATE_BUSY)
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{
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return HAL_BUSY;
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}
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else if (hnand->State == HAL_NAND_STATE_READY)
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{
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/* Process Locked */
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__HAL_LOCK(hnand);
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/* Update the NAND controller state */
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hnand->State = HAL_NAND_STATE_BUSY;
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/* Identify the device address */
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if (hnand->Init.NandBank == FMC_NAND_BANK2)
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{
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deviceaddress = NAND_DEVICE1;
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}
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else
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{
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deviceaddress = NAND_DEVICE2;
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}
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/* Send NAND reset command */
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*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF;
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/* Update the NAND controller state */
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hnand->State = HAL_NAND_STATE_READY;
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/* Process unlocked */
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__HAL_UNLOCK(hnand);
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}
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else
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{
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return HAL_ERROR;
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}
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return HAL_OK;
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}
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/**
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* @brief Configure the device: Enter the physical parameters of the device
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* @param hnand pointer to a NAND_HandleTypeDef structure that contains
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* the configuration information for NAND module.
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* @param pDeviceConfig pointer to NAND_DeviceConfigTypeDef structure
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* @retval HAL status
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*/
|
|
HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig)
|
|
{
|
|
hnand->Config.PageSize = pDeviceConfig->PageSize;
|
|
hnand->Config.SpareAreaSize = pDeviceConfig->SpareAreaSize;
|
|
hnand->Config.BlockSize = pDeviceConfig->BlockSize;
|
|
hnand->Config.BlockNbr = pDeviceConfig->BlockNbr;
|
|
hnand->Config.PlaneSize = pDeviceConfig->PlaneSize;
|
|
hnand->Config.PlaneNbr = pDeviceConfig->PlaneNbr;
|
|
hnand->Config.ExtraCommandEnable = pDeviceConfig->ExtraCommandEnable;
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Read Page(s) from NAND memory block (8-bits addressing)
|
|
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
|
|
* the configuration information for NAND module.
|
|
* @param pAddress pointer to NAND address structure
|
|
* @param pBuffer pointer to destination read buffer
|
|
* @param NumPageToRead number of pages to read from block
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
|
|
uint8_t *pBuffer, uint32_t NumPageToRead)
|
|
{
|
|
uint32_t index;
|
|
uint32_t tickstart;
|
|
uint32_t deviceaddress;
|
|
uint32_t numpagesread = 0U;
|
|
uint32_t nandaddress;
|
|
uint32_t nbpages = NumPageToRead;
|
|
uint8_t *buff = pBuffer;
|
|
|
|
/* Check the NAND controller state */
|
|
if (hnand->State == HAL_NAND_STATE_BUSY)
|
|
{
|
|
return HAL_BUSY;
|
|
}
|
|
else if (hnand->State == HAL_NAND_STATE_READY)
|
|
{
|
|
/* Process Locked */
|
|
__HAL_LOCK(hnand);
|
|
|
|
/* Update the NAND controller state */
|
|
hnand->State = HAL_NAND_STATE_BUSY;
|
|
|
|
/* Identify the device address */
|
|
if (hnand->Init.NandBank == FMC_NAND_BANK2)
|
|
{
|
|
deviceaddress = NAND_DEVICE1;
|
|
}
|
|
else
|
|
{
|
|
deviceaddress = NAND_DEVICE2;
|
|
}
|
|
|
|
/* NAND raw address calculation */
|
|
nandaddress = ARRAY_ADDRESS(pAddress, hnand);
|
|
|
|
/* Page(s) read loop */
|
|
while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
|
|
{
|
|
/* Send read page command sequence */
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
|
|
__DSB();
|
|
|
|
/* Cards with page size <= 512 bytes */
|
|
if ((hnand->Config.PageSize) <= 512U)
|
|
{
|
|
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
|
|
{
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
|
|
__DSB();
|
|
}
|
|
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
|
|
{
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
|
|
__DSB();
|
|
}
|
|
}
|
|
else /* (hnand->Config.PageSize) > 512 */
|
|
{
|
|
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
|
|
{
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
|
|
__DSB();
|
|
}
|
|
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
|
|
{
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
|
|
__DSB();
|
|
}
|
|
}
|
|
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
|
|
__DSB();
|
|
|
|
|
|
if (hnand->Config.ExtraCommandEnable == ENABLE)
|
|
{
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Read status until NAND is ready */
|
|
while (HAL_NAND_Read_Status(hnand) != NAND_READY)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
|
|
{
|
|
/* Update the NAND controller state */
|
|
hnand->State = HAL_NAND_STATE_ERROR;
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hnand);
|
|
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
|
|
/* Go back to read mode */
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
|
|
__DSB();
|
|
}
|
|
|
|
/* Get Data into Buffer */
|
|
for (index = 0U; index < hnand->Config.PageSize; index++)
|
|
{
|
|
*buff = *(uint8_t *)deviceaddress;
|
|
buff++;
|
|
}
|
|
|
|
/* Increment read pages number */
|
|
numpagesread++;
|
|
|
|
/* Decrement pages to read */
|
|
nbpages--;
|
|
|
|
/* Increment the NAND address */
|
|
nandaddress = (uint32_t)(nandaddress + 1U);
|
|
}
|
|
|
|
/* Update the NAND controller state */
|
|
hnand->State = HAL_NAND_STATE_READY;
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hnand);
|
|
}
|
|
else
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Read Page(s) from NAND memory block (16-bits addressing)
|
|
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
|
|
* the configuration information for NAND module.
|
|
* @param pAddress pointer to NAND address structure
|
|
* @param pBuffer pointer to destination read buffer. pBuffer should be 16bits aligned
|
|
* @param NumPageToRead number of pages to read from block
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
|
|
uint16_t *pBuffer, uint32_t NumPageToRead)
|
|
{
|
|
uint32_t index;
|
|
uint32_t tickstart;
|
|
uint32_t deviceaddress;
|
|
uint32_t numpagesread = 0U;
|
|
uint32_t nandaddress;
|
|
uint32_t nbpages = NumPageToRead;
|
|
uint16_t *buff = pBuffer;
|
|
|
|
/* Check the NAND controller state */
|
|
if (hnand->State == HAL_NAND_STATE_BUSY)
|
|
{
|
|
return HAL_BUSY;
|
|
}
|
|
else if (hnand->State == HAL_NAND_STATE_READY)
|
|
{
|
|
/* Process Locked */
|
|
__HAL_LOCK(hnand);
|
|
|
|
/* Update the NAND controller state */
|
|
hnand->State = HAL_NAND_STATE_BUSY;
|
|
|
|
/* Identify the device address */
|
|
if (hnand->Init.NandBank == FMC_NAND_BANK2)
|
|
{
|
|
deviceaddress = NAND_DEVICE1;
|
|
}
|
|
else
|
|
{
|
|
deviceaddress = NAND_DEVICE2;
|
|
}
|
|
|
|
/* NAND raw address calculation */
|
|
nandaddress = ARRAY_ADDRESS(pAddress, hnand);
|
|
|
|
/* Page(s) read loop */
|
|
while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
|
|
{
|
|
/* Send read page command sequence */
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
|
|
__DSB();
|
|
|
|
/* Cards with page size <= 512 bytes */
|
|
if ((hnand->Config.PageSize) <= 512U)
|
|
{
|
|
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
|
|
{
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
|
|
__DSB();
|
|
}
|
|
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
|
|
{
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
|
|
__DSB();
|
|
}
|
|
}
|
|
else /* (hnand->Config.PageSize) > 512 */
|
|
{
|
|
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
|
|
{
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
|
|
__DSB();
|
|
}
|
|
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
|
|
{
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
|
|
__DSB();
|
|
}
|
|
}
|
|
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
|
|
__DSB();
|
|
|
|
if (hnand->Config.ExtraCommandEnable == ENABLE)
|
|
{
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Read status until NAND is ready */
|
|
while (HAL_NAND_Read_Status(hnand) != NAND_READY)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
|
|
{
|
|
/* Update the NAND controller state */
|
|
hnand->State = HAL_NAND_STATE_ERROR;
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hnand);
|
|
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
|
|
/* Go back to read mode */
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
|
|
__DSB();
|
|
}
|
|
|
|
/* Calculate PageSize */
|
|
if (hnand->Init.MemoryDataWidth == FMC_NAND_PCC_MEM_BUS_WIDTH_8)
|
|
{
|
|
hnand->Config.PageSize = hnand->Config.PageSize / 2U;
|
|
}
|
|
else
|
|
{
|
|
/* Do nothing */
|
|
/* Keep the same PageSize for FMC_NAND_MEM_BUS_WIDTH_16*/
|
|
}
|
|
|
|
/* Get Data into Buffer */
|
|
for (index = 0U; index < hnand->Config.PageSize; index++)
|
|
{
|
|
*buff = *(uint16_t *)deviceaddress;
|
|
buff++;
|
|
}
|
|
|
|
/* Increment read pages number */
|
|
numpagesread++;
|
|
|
|
/* Decrement pages to read */
|
|
nbpages--;
|
|
|
|
/* Increment the NAND address */
|
|
nandaddress = (uint32_t)(nandaddress + 1U);
|
|
}
|
|
|
|
/* Update the NAND controller state */
|
|
hnand->State = HAL_NAND_STATE_READY;
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hnand);
|
|
}
|
|
else
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Write Page(s) to NAND memory block (8-bits addressing)
|
|
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
|
|
* the configuration information for NAND module.
|
|
* @param pAddress pointer to NAND address structure
|
|
* @param pBuffer pointer to source buffer to write
|
|
* @param NumPageToWrite number of pages to write to block
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
|
|
const uint8_t *pBuffer, uint32_t NumPageToWrite)
|
|
{
|
|
uint32_t index;
|
|
uint32_t tickstart;
|
|
uint32_t deviceaddress;
|
|
uint32_t numpageswritten = 0U;
|
|
uint32_t nandaddress;
|
|
uint32_t nbpages = NumPageToWrite;
|
|
const uint8_t *buff = pBuffer;
|
|
|
|
/* Check the NAND controller state */
|
|
if (hnand->State == HAL_NAND_STATE_BUSY)
|
|
{
|
|
return HAL_BUSY;
|
|
}
|
|
else if (hnand->State == HAL_NAND_STATE_READY)
|
|
{
|
|
/* Process Locked */
|
|
__HAL_LOCK(hnand);
|
|
|
|
/* Update the NAND controller state */
|
|
hnand->State = HAL_NAND_STATE_BUSY;
|
|
|
|
/* Identify the device address */
|
|
if (hnand->Init.NandBank == FMC_NAND_BANK2)
|
|
{
|
|
deviceaddress = NAND_DEVICE1;
|
|
}
|
|
else
|
|
{
|
|
deviceaddress = NAND_DEVICE2;
|
|
}
|
|
|
|
/* NAND raw address calculation */
|
|
nandaddress = ARRAY_ADDRESS(pAddress, hnand);
|
|
|
|
/* Page(s) write loop */
|
|
while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
|
|
{
|
|
/* Send write page command sequence */
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
|
|
__DSB();
|
|
|
|
/* Cards with page size <= 512 bytes */
|
|
if ((hnand->Config.PageSize) <= 512U)
|
|
{
|
|
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
|
|
{
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
|
|
__DSB();
|
|
}
|
|
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
|
|
{
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
|
|
__DSB();
|
|
}
|
|
}
|
|
else /* (hnand->Config.PageSize) > 512 */
|
|
{
|
|
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
|
|
{
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
|
|
__DSB();
|
|
}
|
|
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
|
|
{
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
|
|
__DSB();
|
|
}
|
|
}
|
|
|
|
/* Write data to memory */
|
|
for (index = 0U; index < hnand->Config.PageSize; index++)
|
|
{
|
|
*(__IO uint8_t *)deviceaddress = *buff;
|
|
buff++;
|
|
__DSB();
|
|
}
|
|
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
|
|
__DSB();
|
|
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Read status until NAND is ready */
|
|
while (HAL_NAND_Read_Status(hnand) != NAND_READY)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
|
|
{
|
|
/* Update the NAND controller state */
|
|
hnand->State = HAL_NAND_STATE_ERROR;
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hnand);
|
|
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
|
|
/* Increment written pages number */
|
|
numpageswritten++;
|
|
|
|
/* Decrement pages to write */
|
|
nbpages--;
|
|
|
|
/* Increment the NAND address */
|
|
nandaddress = (uint32_t)(nandaddress + 1U);
|
|
}
|
|
|
|
/* Update the NAND controller state */
|
|
hnand->State = HAL_NAND_STATE_READY;
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hnand);
|
|
}
|
|
else
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Write Page(s) to NAND memory block (16-bits addressing)
|
|
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
|
|
* the configuration information for NAND module.
|
|
* @param pAddress pointer to NAND address structure
|
|
* @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned
|
|
* @param NumPageToWrite number of pages to write to block
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
|
|
const uint16_t *pBuffer, uint32_t NumPageToWrite)
|
|
{
|
|
uint32_t index;
|
|
uint32_t tickstart;
|
|
uint32_t deviceaddress;
|
|
uint32_t numpageswritten = 0U;
|
|
uint32_t nandaddress;
|
|
uint32_t nbpages = NumPageToWrite;
|
|
const uint16_t *buff = pBuffer;
|
|
|
|
/* Check the NAND controller state */
|
|
if (hnand->State == HAL_NAND_STATE_BUSY)
|
|
{
|
|
return HAL_BUSY;
|
|
}
|
|
else if (hnand->State == HAL_NAND_STATE_READY)
|
|
{
|
|
/* Process Locked */
|
|
__HAL_LOCK(hnand);
|
|
|
|
/* Update the NAND controller state */
|
|
hnand->State = HAL_NAND_STATE_BUSY;
|
|
|
|
/* Identify the device address */
|
|
if (hnand->Init.NandBank == FMC_NAND_BANK2)
|
|
{
|
|
deviceaddress = NAND_DEVICE1;
|
|
}
|
|
else
|
|
{
|
|
deviceaddress = NAND_DEVICE2;
|
|
}
|
|
|
|
/* NAND raw address calculation */
|
|
nandaddress = ARRAY_ADDRESS(pAddress, hnand);
|
|
|
|
/* Page(s) write loop */
|
|
while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
|
|
{
|
|
/* Send write page command sequence */
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
|
|
__DSB();
|
|
|
|
/* Cards with page size <= 512 bytes */
|
|
if ((hnand->Config.PageSize) <= 512U)
|
|
{
|
|
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
|
|
{
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
|
|
__DSB();
|
|
}
|
|
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
|
|
{
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
|
|
__DSB();
|
|
}
|
|
}
|
|
else /* (hnand->Config.PageSize) > 512 */
|
|
{
|
|
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
|
|
{
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
|
|
__DSB();
|
|
}
|
|
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
|
|
{
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
|
|
__DSB();
|
|
}
|
|
}
|
|
|
|
/* Calculate PageSize */
|
|
if (hnand->Init.MemoryDataWidth == FMC_NAND_PCC_MEM_BUS_WIDTH_8)
|
|
{
|
|
hnand->Config.PageSize = hnand->Config.PageSize / 2U;
|
|
}
|
|
else
|
|
{
|
|
/* Do nothing */
|
|
/* Keep the same PageSize for FMC_NAND_MEM_BUS_WIDTH_16*/
|
|
}
|
|
|
|
/* Write data to memory */
|
|
for (index = 0U; index < hnand->Config.PageSize; index++)
|
|
{
|
|
*(__IO uint16_t *)deviceaddress = *buff;
|
|
buff++;
|
|
__DSB();
|
|
}
|
|
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
|
|
__DSB();
|
|
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Read status until NAND is ready */
|
|
while (HAL_NAND_Read_Status(hnand) != NAND_READY)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
|
|
{
|
|
/* Update the NAND controller state */
|
|
hnand->State = HAL_NAND_STATE_ERROR;
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hnand);
|
|
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
|
|
/* Increment written pages number */
|
|
numpageswritten++;
|
|
|
|
/* Decrement pages to write */
|
|
nbpages--;
|
|
|
|
/* Increment the NAND address */
|
|
nandaddress = (uint32_t)(nandaddress + 1U);
|
|
}
|
|
|
|
/* Update the NAND controller state */
|
|
hnand->State = HAL_NAND_STATE_READY;
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hnand);
|
|
}
|
|
else
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Read Spare area(s) from NAND memory (8-bits addressing)
|
|
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
|
|
* the configuration information for NAND module.
|
|
* @param pAddress pointer to NAND address structure
|
|
* @param pBuffer pointer to source buffer to write
|
|
* @param NumSpareAreaToRead Number of spare area to read
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
|
|
uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
|
|
{
|
|
uint32_t index;
|
|
uint32_t tickstart;
|
|
uint32_t deviceaddress;
|
|
uint32_t numsparearearead = 0U;
|
|
uint32_t nandaddress;
|
|
uint32_t columnaddress;
|
|
uint32_t nbspare = NumSpareAreaToRead;
|
|
uint8_t *buff = pBuffer;
|
|
|
|
/* Check the NAND controller state */
|
|
if (hnand->State == HAL_NAND_STATE_BUSY)
|
|
{
|
|
return HAL_BUSY;
|
|
}
|
|
else if (hnand->State == HAL_NAND_STATE_READY)
|
|
{
|
|
/* Process Locked */
|
|
__HAL_LOCK(hnand);
|
|
|
|
/* Update the NAND controller state */
|
|
hnand->State = HAL_NAND_STATE_BUSY;
|
|
|
|
/* Identify the device address */
|
|
if (hnand->Init.NandBank == FMC_NAND_BANK2)
|
|
{
|
|
deviceaddress = NAND_DEVICE1;
|
|
}
|
|
else
|
|
{
|
|
deviceaddress = NAND_DEVICE2;
|
|
}
|
|
|
|
/* NAND raw address calculation */
|
|
nandaddress = ARRAY_ADDRESS(pAddress, hnand);
|
|
|
|
/* Column in page address */
|
|
columnaddress = COLUMN_ADDRESS(hnand);
|
|
|
|
/* Spare area(s) read loop */
|
|
while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
|
|
{
|
|
/* Cards with page size <= 512 bytes */
|
|
if ((hnand->Config.PageSize) <= 512U)
|
|
{
|
|
/* Send read spare area command sequence */
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
|
|
__DSB();
|
|
|
|
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
|
|
{
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
|
|
__DSB();
|
|
}
|
|
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
|
|
{
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
|
|
__DSB();
|
|
}
|
|
}
|
|
else /* (hnand->Config.PageSize) > 512 */
|
|
{
|
|
/* Send read spare area command sequence */
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
|
|
__DSB();
|
|
|
|
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
|
|
{
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
|
|
__DSB();
|
|
}
|
|
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
|
|
{
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
|
|
__DSB();
|
|
}
|
|
}
|
|
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
|
|
__DSB();
|
|
|
|
if (hnand->Config.ExtraCommandEnable == ENABLE)
|
|
{
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Read status until NAND is ready */
|
|
while (HAL_NAND_Read_Status(hnand) != NAND_READY)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
|
|
{
|
|
/* Update the NAND controller state */
|
|
hnand->State = HAL_NAND_STATE_ERROR;
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hnand);
|
|
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
|
|
/* Go back to read mode */
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
|
|
__DSB();
|
|
}
|
|
|
|
/* Get Data into Buffer */
|
|
for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
|
|
{
|
|
*buff = *(uint8_t *)deviceaddress;
|
|
buff++;
|
|
}
|
|
|
|
/* Increment read spare areas number */
|
|
numsparearearead++;
|
|
|
|
/* Decrement spare areas to read */
|
|
nbspare--;
|
|
|
|
/* Increment the NAND address */
|
|
nandaddress = (uint32_t)(nandaddress + 1U);
|
|
}
|
|
|
|
/* Update the NAND controller state */
|
|
hnand->State = HAL_NAND_STATE_READY;
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hnand);
|
|
}
|
|
else
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Read Spare area(s) from NAND memory (16-bits addressing)
|
|
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
|
|
* the configuration information for NAND module.
|
|
* @param pAddress pointer to NAND address structure
|
|
* @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned.
|
|
* @param NumSpareAreaToRead Number of spare area to read
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
|
|
uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
|
|
{
|
|
uint32_t index;
|
|
uint32_t tickstart;
|
|
uint32_t deviceaddress;
|
|
uint32_t numsparearearead = 0U;
|
|
uint32_t nandaddress;
|
|
uint32_t columnaddress;
|
|
uint32_t nbspare = NumSpareAreaToRead;
|
|
uint16_t *buff = pBuffer;
|
|
|
|
/* Check the NAND controller state */
|
|
if (hnand->State == HAL_NAND_STATE_BUSY)
|
|
{
|
|
return HAL_BUSY;
|
|
}
|
|
else if (hnand->State == HAL_NAND_STATE_READY)
|
|
{
|
|
/* Process Locked */
|
|
__HAL_LOCK(hnand);
|
|
|
|
/* Update the NAND controller state */
|
|
hnand->State = HAL_NAND_STATE_BUSY;
|
|
|
|
/* Identify the device address */
|
|
if (hnand->Init.NandBank == FMC_NAND_BANK2)
|
|
{
|
|
deviceaddress = NAND_DEVICE1;
|
|
}
|
|
else
|
|
{
|
|
deviceaddress = NAND_DEVICE2;
|
|
}
|
|
|
|
/* NAND raw address calculation */
|
|
nandaddress = ARRAY_ADDRESS(pAddress, hnand);
|
|
|
|
/* Column in page address */
|
|
columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand));
|
|
|
|
/* Spare area(s) read loop */
|
|
while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
|
|
{
|
|
/* Cards with page size <= 512 bytes */
|
|
if ((hnand->Config.PageSize) <= 512U)
|
|
{
|
|
/* Send read spare area command sequence */
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
|
|
__DSB();
|
|
|
|
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
|
|
{
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
|
|
__DSB();
|
|
}
|
|
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
|
|
{
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
|
|
__DSB();
|
|
}
|
|
}
|
|
else /* (hnand->Config.PageSize) > 512 */
|
|
{
|
|
/* Send read spare area command sequence */
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
|
|
__DSB();
|
|
|
|
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
|
|
{
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
|
|
__DSB();
|
|
}
|
|
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
|
|
{
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
|
|
__DSB();
|
|
}
|
|
}
|
|
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
|
|
__DSB();
|
|
|
|
if (hnand->Config.ExtraCommandEnable == ENABLE)
|
|
{
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Read status until NAND is ready */
|
|
while (HAL_NAND_Read_Status(hnand) != NAND_READY)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
|
|
{
|
|
/* Update the NAND controller state */
|
|
hnand->State = HAL_NAND_STATE_ERROR;
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hnand);
|
|
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
|
|
/* Go back to read mode */
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
|
|
__DSB();
|
|
}
|
|
|
|
/* Get Data into Buffer */
|
|
for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
|
|
{
|
|
*buff = *(uint16_t *)deviceaddress;
|
|
buff++;
|
|
}
|
|
|
|
/* Increment read spare areas number */
|
|
numsparearearead++;
|
|
|
|
/* Decrement spare areas to read */
|
|
nbspare--;
|
|
|
|
/* Increment the NAND address */
|
|
nandaddress = (uint32_t)(nandaddress + 1U);
|
|
}
|
|
|
|
/* Update the NAND controller state */
|
|
hnand->State = HAL_NAND_STATE_READY;
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hnand);
|
|
}
|
|
else
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Write Spare area(s) to NAND memory (8-bits addressing)
|
|
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
|
|
* the configuration information for NAND module.
|
|
* @param pAddress pointer to NAND address structure
|
|
* @param pBuffer pointer to source buffer to write
|
|
* @param NumSpareAreaTowrite number of spare areas to write to block
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
|
|
const uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
|
|
{
|
|
uint32_t index;
|
|
uint32_t tickstart;
|
|
uint32_t deviceaddress;
|
|
uint32_t numspareareawritten = 0U;
|
|
uint32_t nandaddress;
|
|
uint32_t columnaddress;
|
|
uint32_t nbspare = NumSpareAreaTowrite;
|
|
const uint8_t *buff = pBuffer;
|
|
|
|
/* Check the NAND controller state */
|
|
if (hnand->State == HAL_NAND_STATE_BUSY)
|
|
{
|
|
return HAL_BUSY;
|
|
}
|
|
else if (hnand->State == HAL_NAND_STATE_READY)
|
|
{
|
|
/* Process Locked */
|
|
__HAL_LOCK(hnand);
|
|
|
|
/* Update the NAND controller state */
|
|
hnand->State = HAL_NAND_STATE_BUSY;
|
|
|
|
/* Identify the device address */
|
|
if (hnand->Init.NandBank == FMC_NAND_BANK2)
|
|
{
|
|
deviceaddress = NAND_DEVICE1;
|
|
}
|
|
else
|
|
{
|
|
deviceaddress = NAND_DEVICE2;
|
|
}
|
|
|
|
/* Page address calculation */
|
|
nandaddress = ARRAY_ADDRESS(pAddress, hnand);
|
|
|
|
/* Column in page address */
|
|
columnaddress = COLUMN_ADDRESS(hnand);
|
|
|
|
/* Spare area(s) write loop */
|
|
while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
|
|
{
|
|
/* Cards with page size <= 512 bytes */
|
|
if ((hnand->Config.PageSize) <= 512U)
|
|
{
|
|
/* Send write Spare area command sequence */
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
|
|
__DSB();
|
|
|
|
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
|
|
{
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
|
|
__DSB();
|
|
}
|
|
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
|
|
{
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
|
|
__DSB();
|
|
}
|
|
}
|
|
else /* (hnand->Config.PageSize) > 512 */
|
|
{
|
|
/* Send write Spare area command sequence */
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
|
|
__DSB();
|
|
|
|
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
|
|
{
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
|
|
__DSB();
|
|
}
|
|
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
|
|
{
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
|
|
__DSB();
|
|
}
|
|
}
|
|
|
|
/* Write data to memory */
|
|
for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
|
|
{
|
|
*(__IO uint8_t *)deviceaddress = *buff;
|
|
buff++;
|
|
__DSB();
|
|
}
|
|
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
|
|
__DSB();
|
|
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Read status until NAND is ready */
|
|
while (HAL_NAND_Read_Status(hnand) != NAND_READY)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
|
|
{
|
|
/* Update the NAND controller state */
|
|
hnand->State = HAL_NAND_STATE_ERROR;
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hnand);
|
|
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
|
|
/* Increment written spare areas number */
|
|
numspareareawritten++;
|
|
|
|
/* Decrement spare areas to write */
|
|
nbspare--;
|
|
|
|
/* Increment the NAND address */
|
|
nandaddress = (uint32_t)(nandaddress + 1U);
|
|
}
|
|
|
|
/* Update the NAND controller state */
|
|
hnand->State = HAL_NAND_STATE_READY;
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hnand);
|
|
}
|
|
else
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Write Spare area(s) to NAND memory (16-bits addressing)
|
|
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
|
|
* the configuration information for NAND module.
|
|
* @param pAddress pointer to NAND address structure
|
|
* @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned.
|
|
* @param NumSpareAreaTowrite number of spare areas to write to block
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress,
|
|
const uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
|
|
{
|
|
uint32_t index;
|
|
uint32_t tickstart;
|
|
uint32_t deviceaddress;
|
|
uint32_t numspareareawritten = 0U;
|
|
uint32_t nandaddress;
|
|
uint32_t columnaddress;
|
|
uint32_t nbspare = NumSpareAreaTowrite;
|
|
const uint16_t *buff = pBuffer;
|
|
|
|
/* Check the NAND controller state */
|
|
if (hnand->State == HAL_NAND_STATE_BUSY)
|
|
{
|
|
return HAL_BUSY;
|
|
}
|
|
else if (hnand->State == HAL_NAND_STATE_READY)
|
|
{
|
|
/* Process Locked */
|
|
__HAL_LOCK(hnand);
|
|
|
|
/* Update the NAND controller state */
|
|
hnand->State = HAL_NAND_STATE_BUSY;
|
|
|
|
/* Identify the device address */
|
|
if (hnand->Init.NandBank == FMC_NAND_BANK2)
|
|
{
|
|
deviceaddress = NAND_DEVICE1;
|
|
}
|
|
else
|
|
{
|
|
deviceaddress = NAND_DEVICE2;
|
|
}
|
|
|
|
/* NAND raw address calculation */
|
|
nandaddress = ARRAY_ADDRESS(pAddress, hnand);
|
|
|
|
/* Column in page address */
|
|
columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand));
|
|
|
|
/* Spare area(s) write loop */
|
|
while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
|
|
{
|
|
/* Cards with page size <= 512 bytes */
|
|
if ((hnand->Config.PageSize) <= 512U)
|
|
{
|
|
/* Send write Spare area command sequence */
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
|
|
__DSB();
|
|
|
|
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
|
|
{
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
|
|
__DSB();
|
|
}
|
|
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
|
|
{
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U;
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
|
|
__DSB();
|
|
}
|
|
}
|
|
else /* (hnand->Config.PageSize) > 512 */
|
|
{
|
|
/* Send write Spare area command sequence */
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
|
|
__DSB();
|
|
|
|
if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
|
|
{
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
|
|
__DSB();
|
|
}
|
|
else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
|
|
{
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
|
|
__DSB();
|
|
}
|
|
}
|
|
|
|
/* Write data to memory */
|
|
for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
|
|
{
|
|
*(__IO uint16_t *)deviceaddress = *buff;
|
|
buff++;
|
|
__DSB();
|
|
}
|
|
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
|
|
__DSB();
|
|
|
|
/* Get tick */
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Read status until NAND is ready */
|
|
while (HAL_NAND_Read_Status(hnand) != NAND_READY)
|
|
{
|
|
if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
|
|
{
|
|
/* Update the NAND controller state */
|
|
hnand->State = HAL_NAND_STATE_ERROR;
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hnand);
|
|
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
|
|
/* Increment written spare areas number */
|
|
numspareareawritten++;
|
|
|
|
/* Decrement spare areas to write */
|
|
nbspare--;
|
|
|
|
/* Increment the NAND address */
|
|
nandaddress = (uint32_t)(nandaddress + 1U);
|
|
}
|
|
|
|
/* Update the NAND controller state */
|
|
hnand->State = HAL_NAND_STATE_READY;
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hnand);
|
|
}
|
|
else
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief NAND memory Block erase
|
|
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
|
|
* the configuration information for NAND module.
|
|
* @param pAddress pointer to NAND address structure
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress)
|
|
{
|
|
uint32_t deviceaddress;
|
|
|
|
/* Check the NAND controller state */
|
|
if (hnand->State == HAL_NAND_STATE_BUSY)
|
|
{
|
|
return HAL_BUSY;
|
|
}
|
|
else if (hnand->State == HAL_NAND_STATE_READY)
|
|
{
|
|
/* Process Locked */
|
|
__HAL_LOCK(hnand);
|
|
|
|
/* Update the NAND controller state */
|
|
hnand->State = HAL_NAND_STATE_BUSY;
|
|
|
|
/* Identify the device address */
|
|
if (hnand->Init.NandBank == FMC_NAND_BANK2)
|
|
{
|
|
deviceaddress = NAND_DEVICE1;
|
|
}
|
|
else
|
|
{
|
|
deviceaddress = NAND_DEVICE2;
|
|
}
|
|
|
|
/* Send Erase block command sequence */
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0;
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
|
|
__DSB();
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
|
|
__DSB();
|
|
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1;
|
|
__DSB();
|
|
|
|
/* Update the NAND controller state */
|
|
hnand->State = HAL_NAND_STATE_READY;
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hnand);
|
|
}
|
|
else
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Increment the NAND memory address
|
|
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
|
|
* the configuration information for NAND module.
|
|
* @param pAddress pointer to NAND address structure
|
|
* @retval The new status of the increment address operation. It can be:
|
|
* - NAND_VALID_ADDRESS: When the new address is valid address
|
|
* - NAND_INVALID_ADDRESS: When the new address is invalid address
|
|
*/
|
|
uint32_t HAL_NAND_Address_Inc(const NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
|
|
{
|
|
uint32_t status = NAND_VALID_ADDRESS;
|
|
|
|
/* Increment page address */
|
|
pAddress->Page++;
|
|
|
|
/* Check NAND address is valid */
|
|
if (pAddress->Page == hnand->Config.BlockSize)
|
|
{
|
|
pAddress->Page = 0;
|
|
pAddress->Block++;
|
|
|
|
if (pAddress->Block == hnand->Config.PlaneSize)
|
|
{
|
|
pAddress->Block = 0;
|
|
pAddress->Plane++;
|
|
|
|
if (pAddress->Plane == (hnand->Config.PlaneNbr))
|
|
{
|
|
status = NAND_INVALID_ADDRESS;
|
|
}
|
|
}
|
|
}
|
|
|
|
return (status);
|
|
}
|
|
|
|
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
|
|
/**
|
|
* @brief Register a User NAND Callback
|
|
* To be used to override the weak predefined callback
|
|
* @param hnand : NAND handle
|
|
* @param CallbackId : ID of the callback to be registered
|
|
* This parameter can be one of the following values:
|
|
* @arg @ref HAL_NAND_MSP_INIT_CB_ID NAND MspInit callback ID
|
|
* @arg @ref HAL_NAND_MSP_DEINIT_CB_ID NAND MspDeInit callback ID
|
|
* @arg @ref HAL_NAND_IT_CB_ID NAND IT callback ID
|
|
* @param pCallback : pointer to the Callback function
|
|
* @retval status
|
|
*/
|
|
HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId,
|
|
pNAND_CallbackTypeDef pCallback)
|
|
{
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
|
|
if (pCallback == NULL)
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
if (hnand->State == HAL_NAND_STATE_READY)
|
|
{
|
|
switch (CallbackId)
|
|
{
|
|
case HAL_NAND_MSP_INIT_CB_ID :
|
|
hnand->MspInitCallback = pCallback;
|
|
break;
|
|
case HAL_NAND_MSP_DEINIT_CB_ID :
|
|
hnand->MspDeInitCallback = pCallback;
|
|
break;
|
|
case HAL_NAND_IT_CB_ID :
|
|
hnand->ItCallback = pCallback;
|
|
break;
|
|
default :
|
|
/* update return status */
|
|
status = HAL_ERROR;
|
|
break;
|
|
}
|
|
}
|
|
else if (hnand->State == HAL_NAND_STATE_RESET)
|
|
{
|
|
switch (CallbackId)
|
|
{
|
|
case HAL_NAND_MSP_INIT_CB_ID :
|
|
hnand->MspInitCallback = pCallback;
|
|
break;
|
|
case HAL_NAND_MSP_DEINIT_CB_ID :
|
|
hnand->MspDeInitCallback = pCallback;
|
|
break;
|
|
default :
|
|
/* update return status */
|
|
status = HAL_ERROR;
|
|
break;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* update return status */
|
|
status = HAL_ERROR;
|
|
}
|
|
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* @brief Unregister a User NAND Callback
|
|
* NAND Callback is redirected to the weak predefined callback
|
|
* @param hnand : NAND handle
|
|
* @param CallbackId : ID of the callback to be unregistered
|
|
* This parameter can be one of the following values:
|
|
* @arg @ref HAL_NAND_MSP_INIT_CB_ID NAND MspInit callback ID
|
|
* @arg @ref HAL_NAND_MSP_DEINIT_CB_ID NAND MspDeInit callback ID
|
|
* @arg @ref HAL_NAND_IT_CB_ID NAND IT callback ID
|
|
* @retval status
|
|
*/
|
|
HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId)
|
|
{
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
|
|
if (hnand->State == HAL_NAND_STATE_READY)
|
|
{
|
|
switch (CallbackId)
|
|
{
|
|
case HAL_NAND_MSP_INIT_CB_ID :
|
|
hnand->MspInitCallback = HAL_NAND_MspInit;
|
|
break;
|
|
case HAL_NAND_MSP_DEINIT_CB_ID :
|
|
hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
|
|
break;
|
|
case HAL_NAND_IT_CB_ID :
|
|
hnand->ItCallback = HAL_NAND_ITCallback;
|
|
break;
|
|
default :
|
|
/* update return status */
|
|
status = HAL_ERROR;
|
|
break;
|
|
}
|
|
}
|
|
else if (hnand->State == HAL_NAND_STATE_RESET)
|
|
{
|
|
switch (CallbackId)
|
|
{
|
|
case HAL_NAND_MSP_INIT_CB_ID :
|
|
hnand->MspInitCallback = HAL_NAND_MspInit;
|
|
break;
|
|
case HAL_NAND_MSP_DEINIT_CB_ID :
|
|
hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
|
|
break;
|
|
default :
|
|
/* update return status */
|
|
status = HAL_ERROR;
|
|
break;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* update return status */
|
|
status = HAL_ERROR;
|
|
}
|
|
|
|
return status;
|
|
}
|
|
#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions
|
|
* @brief management functions
|
|
*
|
|
@verbatim
|
|
==============================================================================
|
|
##### NAND Control functions #####
|
|
==============================================================================
|
|
[..]
|
|
This subsection provides a set of functions allowing to control dynamically
|
|
the NAND interface.
|
|
|
|
@endverbatim
|
|
* @{
|
|
*/
|
|
|
|
|
|
/**
|
|
* @brief Enables dynamically NAND ECC feature.
|
|
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
|
|
* the configuration information for NAND module.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
|
|
{
|
|
/* Check the NAND controller state */
|
|
if (hnand->State == HAL_NAND_STATE_BUSY)
|
|
{
|
|
return HAL_BUSY;
|
|
}
|
|
else if (hnand->State == HAL_NAND_STATE_READY)
|
|
{
|
|
/* Update the NAND state */
|
|
hnand->State = HAL_NAND_STATE_BUSY;
|
|
|
|
/* Enable ECC feature */
|
|
(void)FMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
|
|
|
|
/* Update the NAND state */
|
|
hnand->State = HAL_NAND_STATE_READY;
|
|
}
|
|
else
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Disables dynamically FMC_NAND ECC feature.
|
|
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
|
|
* the configuration information for NAND module.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
|
|
{
|
|
/* Check the NAND controller state */
|
|
if (hnand->State == HAL_NAND_STATE_BUSY)
|
|
{
|
|
return HAL_BUSY;
|
|
}
|
|
else if (hnand->State == HAL_NAND_STATE_READY)
|
|
{
|
|
/* Update the NAND state */
|
|
hnand->State = HAL_NAND_STATE_BUSY;
|
|
|
|
/* Disable ECC feature */
|
|
(void)FMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
|
|
|
|
/* Update the NAND state */
|
|
hnand->State = HAL_NAND_STATE_READY;
|
|
}
|
|
else
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Disables dynamically NAND ECC feature.
|
|
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
|
|
* the configuration information for NAND module.
|
|
* @param ECCval pointer to ECC value
|
|
* @param Timeout maximum timeout to wait
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
|
|
{
|
|
HAL_StatusTypeDef status;
|
|
|
|
/* Check the NAND controller state */
|
|
if (hnand->State == HAL_NAND_STATE_BUSY)
|
|
{
|
|
return HAL_BUSY;
|
|
}
|
|
else if (hnand->State == HAL_NAND_STATE_READY)
|
|
{
|
|
/* Update the NAND state */
|
|
hnand->State = HAL_NAND_STATE_BUSY;
|
|
|
|
/* Get NAND ECC value */
|
|
status = FMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
|
|
|
|
/* Update the NAND state */
|
|
hnand->State = HAL_NAND_STATE_READY;
|
|
}
|
|
else
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
|
|
/** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
|
|
* @brief Peripheral State functions
|
|
*
|
|
@verbatim
|
|
==============================================================================
|
|
##### NAND State functions #####
|
|
==============================================================================
|
|
[..]
|
|
This subsection permits to get in run-time the status of the NAND controller
|
|
and the data flow.
|
|
|
|
@endverbatim
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief return the NAND state
|
|
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
|
|
* the configuration information for NAND module.
|
|
* @retval HAL state
|
|
*/
|
|
HAL_NAND_StateTypeDef HAL_NAND_GetState(const NAND_HandleTypeDef *hnand)
|
|
{
|
|
return hnand->State;
|
|
}
|
|
|
|
/**
|
|
* @brief NAND memory read status
|
|
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
|
|
* the configuration information for NAND module.
|
|
* @retval NAND status
|
|
*/
|
|
uint32_t HAL_NAND_Read_Status(const NAND_HandleTypeDef *hnand)
|
|
{
|
|
uint32_t data;
|
|
uint32_t deviceaddress;
|
|
UNUSED(hnand);
|
|
|
|
/* Identify the device address */
|
|
if (hnand->Init.NandBank == FMC_NAND_BANK2)
|
|
{
|
|
deviceaddress = NAND_DEVICE1;
|
|
}
|
|
else
|
|
{
|
|
deviceaddress = NAND_DEVICE2;
|
|
}
|
|
|
|
/* Send Read status operation command */
|
|
*(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS;
|
|
|
|
/* Read status register data */
|
|
data = *(__IO uint8_t *)deviceaddress;
|
|
|
|
/* Return the status */
|
|
if ((data & NAND_ERROR) == NAND_ERROR)
|
|
{
|
|
return NAND_ERROR;
|
|
}
|
|
else if ((data & NAND_READY) == NAND_READY)
|
|
{
|
|
return NAND_READY;
|
|
}
|
|
else
|
|
{
|
|
return NAND_BUSY;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#endif /* HAL_NAND_MODULE_ENABLED */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#endif /* FMC_BANK3 */
|